| blob | b6f3c2d748f00d73d217c66723e4cc4be22cd40c |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
72 #ifndef CHECK_STACK_LIMIT
73 #define CHECK_STACK_LIMIT (-1)
74 #endif
76 /* Return index of given mode in mult and division cost tables. */
77 #define MODE_INDEX(mode) \
78 ((mode) == QImode ? 0 \
79 : (mode) == HImode ? 1 \
80 : (mode) == SImode ? 2 \
81 : (mode) == DImode ? 3 \
82 : 4)
84 /* Processor costs (relative to an add) */
85 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
86 #define COSTS_N_BYTES(N) ((N) * 2)
88 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
97 const
120 in QImode, HImode and SImode.
121 Relative to reg-reg move (2). */
125 in SFmode, DFmode and XFmode */
127 in SFmode, DFmode and XFmode */
130 in SImode and DImode */
132 in SImode and DImode */
135 in SImode, DImode and TImode */
137 in SImode, DImode and TImode */
150 ix86_size_memcpy,
151 ix86_size_memset,
163 };
165 /* Processor costs (relative to an add) */
168 DUMMY_STRINGOP_ALGS};
171 DUMMY_STRINGOP_ALGS};
173 static const
196 in QImode, HImode and SImode.
197 Relative to reg-reg move (2). */
201 in SFmode, DFmode and XFmode */
203 in SFmode, DFmode and XFmode */
206 in SImode and DImode */
208 in SImode and DImode */
211 in SImode, DImode and TImode */
213 in SImode, DImode and TImode */
226 i386_memcpy,
227 i386_memset,
239 };
243 DUMMY_STRINGOP_ALGS};
246 DUMMY_STRINGOP_ALGS};
248 static const
271 in QImode, HImode and SImode.
272 Relative to reg-reg move (2). */
276 in SFmode, DFmode and XFmode */
278 in SFmode, DFmode and XFmode */
281 in SImode and DImode */
283 in SImode and DImode */
286 in SImode, DImode and TImode */
288 in SImode, DImode and TImode */
291 shared for code and data, so 4kB is
292 not really precise. */
303 i486_memcpy,
304 i486_memset,
316 };
320 DUMMY_STRINGOP_ALGS};
323 DUMMY_STRINGOP_ALGS};
325 static const
348 in QImode, HImode and SImode.
349 Relative to reg-reg move (2). */
353 in SFmode, DFmode and XFmode */
355 in SFmode, DFmode and XFmode */
358 in SImode and DImode */
360 in SImode and DImode */
363 in SImode, DImode and TImode */
365 in SImode, DImode and TImode */
378 pentium_memcpy,
379 pentium_memset,
391 };
393 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
394 (we ensure the alignment). For small blocks inline loop is still a
395 noticeable win, for bigger blocks either rep movsl or rep movsb is
396 way to go. Rep movsb has apparently more expensive startup time in CPU,
397 but after 4K the difference is down in the noise. */
402 DUMMY_STRINGOP_ALGS};
407 DUMMY_STRINGOP_ALGS};
408 static const
431 in QImode, HImode and SImode.
432 Relative to reg-reg move (2). */
436 in SFmode, DFmode and XFmode */
438 in SFmode, DFmode and XFmode */
441 in SImode and DImode */
443 in SImode and DImode */
446 in SImode, DImode and TImode */
448 in SImode, DImode and TImode */
461 pentiumpro_memcpy,
462 pentiumpro_memset,
474 };
478 DUMMY_STRINGOP_ALGS};
481 DUMMY_STRINGOP_ALGS};
482 static const
505 in QImode, HImode and SImode.
506 Relative to reg-reg move (2). */
510 in SFmode, DFmode and XFmode */
512 in SFmode, DFmode and XFmode */
516 in SImode and DImode */
518 in SImode and DImode */
521 in SImode, DImode and TImode */
523 in SImode, DImode and TImode */
536 geode_memcpy,
537 geode_memset,
549 };
553 DUMMY_STRINGOP_ALGS};
556 DUMMY_STRINGOP_ALGS};
557 static const
580 in QImode, HImode and SImode.
581 Relative to reg-reg move (2). */
585 in SFmode, DFmode and XFmode */
587 in SFmode, DFmode and XFmode */
590 in SImode and DImode */
592 in SImode and DImode */
595 in SImode, DImode and TImode */
597 in SImode, DImode and TImode */
601 have integrated l2 cache, but
602 optimizing for k6 is not important
603 enough to worry about that. */
613 k6_memcpy,
614 k6_memset,
626 };
628 /* For some reason, Athlon deals better with REP prefix (relative to loops)
629 compared to K8. Alignment becomes important after 8 bytes for memcpy and
630 128 bytes for memset. */
633 DUMMY_STRINGOP_ALGS};
636 DUMMY_STRINGOP_ALGS};
637 static const
660 in QImode, HImode and SImode.
661 Relative to reg-reg move (2). */
665 in SFmode, DFmode and XFmode */
667 in SFmode, DFmode and XFmode */
670 in SImode and DImode */
672 in SImode and DImode */
675 in SImode, DImode and TImode */
677 in SImode, DImode and TImode */
690 athlon_memcpy,
691 athlon_memset,
703 };
705 /* K8 has optimized REP instruction for medium sized blocks, but for very
706 small blocks it is better to use loop. For large blocks, libcall can
707 do nontemporary accesses and beat inline considerably. */
718 static const
741 in QImode, HImode and SImode.
742 Relative to reg-reg move (2). */
746 in SFmode, DFmode and XFmode */
748 in SFmode, DFmode and XFmode */
751 in SImode and DImode */
753 in SImode and DImode */
756 in SImode, DImode and TImode */
758 in SImode, DImode and TImode */
763 /* New AMD processors never drop prefetches; if they cannot be performed
764 immediately, they are queued. We set number of simultaneous prefetches
765 to a large constant to reflect this (it probably is not a good idea not
766 to limit number of prefetches at all, as their execution also takes some
767 time). */
777 k8_memcpy,
778 k8_memset,
790 };
792 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
793 very small blocks it is better to use loop. For large blocks, libcall can
794 do nontemporary accesses and beat inline considerably. */
827 in QImode, HImode and SImode.
828 Relative to reg-reg move (2). */
832 in SFmode, DFmode and XFmode */
834 in SFmode, DFmode and XFmode */
837 in SImode and DImode */
839 in SImode and DImode */
842 in SImode, DImode and TImode */
844 in SImode, DImode and TImode */
846 /* On K8:
847 MOVD reg64, xmmreg Double FSTORE 4
848 MOVD reg32, xmmreg Double FSTORE 4
849 On AMDFAM10:
850 MOVD reg64, xmmreg Double FADD 3
851 1/1 1/1
852 MOVD reg32, xmmreg Double FADD 3
853 1/1 1/1 */
857 /* New AMD processors never drop prefetches; if they cannot be performed
858 immediately, they are queued. We set number of simultaneous prefetches
859 to a large constant to reflect this (it probably is not a good idea not
860 to limit number of prefetches at all, as their execution also takes some
861 time). */
871 amdfam10_memcpy,
872 amdfam10_memset,
884 };
886 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
887 very small blocks it is better to use loop. For large blocks, libcall
888 can do nontemporary accesses and beat inline considerably. */
922 in QImode, HImode and SImode.
923 Relative to reg-reg move (2). */
927 in SFmode, DFmode and XFmode */
929 in SFmode, DFmode and XFmode */
932 in SImode and DImode */
934 in SImode and DImode */
937 in SImode, DImode and TImode */
939 in SImode, DImode and TImode */
941 /* On K8:
942 MOVD reg64, xmmreg Double FSTORE 4
943 MOVD reg32, xmmreg Double FSTORE 4
944 On AMDFAM10:
945 MOVD reg64, xmmreg Double FADD 3
946 1/1 1/1
947 MOVD reg32, xmmreg Double FADD 3
948 1/1 1/1 */
952 /* New AMD processors never drop prefetches; if they cannot be performed
953 immediately, they are queued. We set number of simultaneous prefetches
954 to a large constant to reflect this (it probably is not a good idea not
955 to limit number of prefetches at all, as their execution also takes some
956 time). */
966 bdver1_memcpy,
967 bdver1_memset,
979 };
981 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
982 very small blocks it is better to use loop. For large blocks, libcall
983 can do nontemporary accesses and beat inline considerably. */
1018 in QImode, HImode and SImode.
1019 Relative to reg-reg move (2). */
1023 in SFmode, DFmode and XFmode */
1025 in SFmode, DFmode and XFmode */
1028 in SImode and DImode */
1030 in SImode and DImode */
1033 in SImode, DImode and TImode */
1035 in SImode, DImode and TImode */
1037 /* On K8:
1038 MOVD reg64, xmmreg Double FSTORE 4
1039 MOVD reg32, xmmreg Double FSTORE 4
1040 On AMDFAM10:
1041 MOVD reg64, xmmreg Double FADD 3
1042 1/1 1/1
1043 MOVD reg32, xmmreg Double FADD 3
1044 1/1 1/1 */
1048 /* New AMD processors never drop prefetches; if they cannot be performed
1049 immediately, they are queued. We set number of simultaneous prefetches
1050 to a large constant to reflect this (it probably is not a good idea not
1051 to limit number of prefetches at all, as their execution also takes some
1052 time). */
1062 bdver2_memcpy,
1063 bdver2_memset,
1075 };
1078 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1079 very small blocks it is better to use loop. For large blocks, libcall
1080 can do nontemporary accesses and beat inline considerably. */
1113 in QImode, HImode and SImode.
1114 Relative to reg-reg move (2). */
1118 in SFmode, DFmode and XFmode */
1120 in SFmode, DFmode and XFmode */
1123 in SImode and DImode */
1125 in SImode and DImode */
1128 in SImode, DImode and TImode */
1130 in SImode, DImode and TImode */
1135 /* New AMD processors never drop prefetches; if they cannot be performed
1136 immediately, they are queued. We set number of simultaneous prefetches
1137 to a large constant to reflect this (it probably is not a good idea not
1138 to limit number of prefetches at all, as their execution also takes some
1139 time). */
1149 bdver3_memcpy,
1150 bdver3_memset,
1162 };
1164 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1165 very small blocks it is better to use loop. For large blocks, libcall can
1166 do nontemporary accesses and beat inline considerably. */
1199 in QImode, HImode and SImode.
1200 Relative to reg-reg move (2). */
1204 in SFmode, DFmode and XFmode */
1206 in SFmode, DFmode and XFmode */
1209 in SImode and DImode */
1211 in SImode and DImode */
1214 in SImode, DImode and TImode */
1216 in SImode, DImode and TImode */
1218 /* On K8:
1219 MOVD reg64, xmmreg Double FSTORE 4
1220 MOVD reg32, xmmreg Double FSTORE 4
1221 On AMDFAM10:
1222 MOVD reg64, xmmreg Double FADD 3
1223 1/1 1/1
1224 MOVD reg32, xmmreg Double FADD 3
1225 1/1 1/1 */
1238 btver1_memcpy,
1239 btver1_memset,
1251 };
1285 in QImode, HImode and SImode.
1286 Relative to reg-reg move (2). */
1290 in SFmode, DFmode and XFmode */
1292 in SFmode, DFmode and XFmode */
1295 in SImode and DImode */
1297 in SImode and DImode */
1300 in SImode, DImode and TImode */
1302 in SImode, DImode and TImode */
1304 /* On K8:
1305 MOVD reg64, xmmreg Double FSTORE 4
1306 MOVD reg32, xmmreg Double FSTORE 4
1307 On AMDFAM10:
1308 MOVD reg64, xmmreg Double FADD 3
1309 1/1 1/1
1310 MOVD reg32, xmmreg Double FADD 3
1311 1/1 1/1 */
1323 btver2_memcpy,
1324 btver2_memset,
1336 };
1340 DUMMY_STRINGOP_ALGS};
1344 DUMMY_STRINGOP_ALGS};
1346 static const
1369 in QImode, HImode and SImode.
1370 Relative to reg-reg move (2). */
1374 in SFmode, DFmode and XFmode */
1376 in SFmode, DFmode and XFmode */
1379 in SImode and DImode */
1381 in SImode and DImode */
1384 in SImode, DImode and TImode */
1386 in SImode, DImode and TImode */
1399 pentium4_memcpy,
1400 pentium4_memset,
1412 };
1425 static const
1448 in QImode, HImode and SImode.
1449 Relative to reg-reg move (2). */
1453 in SFmode, DFmode and XFmode */
1455 in SFmode, DFmode and XFmode */
1458 in SImode and DImode */
1460 in SImode and DImode */
1463 in SImode, DImode and TImode */
1465 in SImode, DImode and TImode */
1478 nocona_memcpy,
1479 nocona_memset,
1491 };
1502 static const
1525 in QImode, HImode and SImode.
1526 Relative to reg-reg move (2). */
1530 in SFmode, DFmode and XFmode */
1532 in SFmode, DFmode and XFmode */
1535 in SImode and DImode */
1537 in SImode and DImode */
1540 in SImode, DImode and TImode */
1542 in SImode, DImode and TImode */
1555 atom_memcpy,
1556 atom_memset,
1568 };
1579 static const
1602 in QImode, HImode and SImode.
1603 Relative to reg-reg move (2). */
1607 in SFmode, DFmode and XFmode */
1609 in SFmode, DFmode and XFmode */
1612 in SImode and DImode */
1614 in SImode and DImode */
1617 in SImode, DImode and TImode */
1619 in SImode, DImode and TImode */
1632 slm_memcpy,
1633 slm_memset,
1645 };
1647 /* Generic should produce code tuned for Core-i7 (and newer chips)
1648 and btver1 (and newer chips). */
1651 DUMMY_STRINGOP_ALGS,
1655 DUMMY_STRINGOP_ALGS,
1658 static const
1661 /* On all chips taken into consideration lea is 2 cycles and more. With
1662 this cost however our current implementation of synth_mult results in
1663 use of unnecessary temporary registers causing regression on several
1664 SPECfp benchmarks. */
1685 in QImode, HImode and SImode.
1686 Relative to reg-reg move (2). */
1690 in SFmode, DFmode and XFmode */
1692 in SFmode, DFmode and XFmode */
1695 in SImode and DImode */
1697 in SImode and DImode */
1700 in SImode, DImode and TImode */
1702 in SImode, DImode and TImode */
1708 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1709 value is increased to perhaps more appropriate value of 5. */
1717 generic_memcpy,
1718 generic_memset,
1730 };
1732 /* core_cost should produce code tuned for Core familly of CPUs. */
1745 static const
1748 /* On all chips taken into consideration lea is 2 cycles and more. With
1749 this cost however our current implementation of synth_mult results in
1750 use of unnecessary temporary registers causing regression on several
1751 SPECfp benchmarks. */
1772 in QImode, HImode and SImode.
1773 Relative to reg-reg move (2). */
1777 in SFmode, DFmode and XFmode */
1779 in SFmode, DFmode and XFmode */
1782 in SImode and DImode */
1784 in SImode and DImode */
1787 in SImode, DImode and TImode */
1789 in SImode, DImode and TImode */
1795 /* FIXME perhaps more appropriate value is 5. */
1803 core_memcpy,
1804 core_memset,
1816 };
1819 /* Set by -mtune. */
1822 /* Set by -mtune or -Os. */
1825 /* Processor feature/optimization bitmasks. */
1826 #define m_386 (1<<PROCESSOR_I386)
1827 #define m_486 (1<<PROCESSOR_I486)
1828 #define m_PENT (1<<PROCESSOR_PENTIUM)
1829 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1830 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1831 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1832 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1833 #define m_CORE2 (1<<PROCESSOR_CORE2)
1834 #define m_COREI7 (1<<PROCESSOR_COREI7)
1835 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1836 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1837 #define m_ATOM (1<<PROCESSOR_ATOM)
1838 #define m_SLM (1<<PROCESSOR_SLM)
1840 #define m_GEODE (1<<PROCESSOR_GEODE)
1841 #define m_K6 (1<<PROCESSOR_K6)
1842 #define m_K6_GEODE (m_K6 | m_GEODE)
1843 #define m_K8 (1<<PROCESSOR_K8)
1844 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1845 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1846 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1847 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1848 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1849 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1850 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1851 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1852 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1853 #define m_BTVER (m_BTVER1 | m_BTVER2)
1854 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1856 #define m_GENERIC (1<<PROCESSOR_GENERIC)
1859 #undef DEF_TUNE
1860 #define DEF_TUNE(tune, name, selector) name,
1862 #undef DEF_TUNE
1863 };
1865 /* Feature tests against the various tunings. */
1868 /* Feature tests against the various tunings used to create ix86_tune_features
1869 based on the processor mask. */
1871 #undef DEF_TUNE
1872 #define DEF_TUNE(tune, name, selector) selector,
1874 #undef DEF_TUNE
1875 };
1877 /* Feature tests against the various architecture variations. */
1880 /* Feature tests against the various architecture variations, used to create
1881 ix86_arch_features based on the processor mask. */
1883 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
1886 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1889 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1892 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1895 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1897 };
1899 static const unsigned int x86_accumulate_outgoing_args
1902 static const unsigned int x86_arch_always_fancy_math_387
1905 static const unsigned int x86_avx256_split_unaligned_load
1908 static const unsigned int x86_avx256_split_unaligned_store
1911 /* In case the average insn count for single function invocation is
1912 lower than this constant, emit fast (but longer) prologue and
1913 epilogue code. */
1914 #define FAST_PROLOGUE_INSN_COUNT 20
1916 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1921 /* Array of the smallest class containing reg number REGNO, indexed by
1922 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1925 {
1926 /* ax, dx, cx, bx */
1928 /* si, di, bp, sp */
1930 /* FP registers */
1933 /* arg pointer */
1934 NON_Q_REGS,
1935 /* flags, fpsr, fpcr, frame */
1937 /* SSE registers */
1940 /* MMX registers */
1943 /* REX registers */
1946 /* SSE REX registers */
1949 /* AVX-512 SSE registers */
1954 /* Mask registers. */
1957 };
1959 /* The "default" register map used in 32bit mode. */
1962 {
1973 };
1975 /* The "default" register map used in 64bit mode. */
1978 {
1989 };
1991 /* Define the register numbers to be used in Dwarf debugging information.
1992 The SVR4 reference port C compiler uses the following register numbers
1993 in its Dwarf output code:
1994 0 for %eax (gcc regno = 0)
1995 1 for %ecx (gcc regno = 2)
1996 2 for %edx (gcc regno = 1)
1997 3 for %ebx (gcc regno = 3)
1998 4 for %esp (gcc regno = 7)
1999 5 for %ebp (gcc regno = 6)
2000 6 for %esi (gcc regno = 4)
2001 7 for %edi (gcc regno = 5)
2002 The following three DWARF register numbers are never generated by
2003 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2004 believes these numbers have these meanings.
2005 8 for %eip (no gcc equivalent)
2006 9 for %eflags (gcc regno = 17)
2007 10 for %trapno (no gcc equivalent)
2008 It is not at all clear how we should number the FP stack registers
2009 for the x86 architecture. If the version of SDB on x86/svr4 were
2010 a bit less brain dead with respect to floating-point then we would
2011 have a precedent to follow with respect to DWARF register numbers
2012 for x86 FP registers, but the SDB on x86/svr4 is so completely
2013 broken with respect to FP registers that it is hardly worth thinking
2014 of it as something to strive for compatibility with.
2015 The version of x86/svr4 SDB I have at the moment does (partially)
2016 seem to believe that DWARF register number 11 is associated with
2017 the x86 register %st(0), but that's about all. Higher DWARF
2018 register numbers don't seem to be associated with anything in
2019 particular, and even for DWARF regno 11, SDB only seems to under-
2020 stand that it should say that a variable lives in %st(0) (when
2021 asked via an `=' command) if we said it was in DWARF regno 11,
2022 but SDB still prints garbage when asked for the value of the
2023 variable in question (via a `/' command).
2024 (Also note that the labels SDB prints for various FP stack regs
2025 when doing an `x' command are all wrong.)
2026 Note that these problems generally don't affect the native SVR4
2027 C compiler because it doesn't allow the use of -O with -g and
2028 because when it is *not* optimizing, it allocates a memory
2029 location for each floating-point variable, and the memory
2030 location is what gets described in the DWARF AT_location
2031 attribute for the variable in question.
2032 Regardless of the severe mental illness of the x86/svr4 SDB, we
2033 do something sensible here and we use the following DWARF
2034 register numbers. Note that these are all stack-top-relative
2035 numbers.
2036 11 for %st(0) (gcc regno = 8)
2037 12 for %st(1) (gcc regno = 9)
2038 13 for %st(2) (gcc regno = 10)
2039 14 for %st(3) (gcc regno = 11)
2040 15 for %st(4) (gcc regno = 12)
2041 16 for %st(5) (gcc regno = 13)
2042 17 for %st(6) (gcc regno = 14)
2043 18 for %st(7) (gcc regno = 15)
2044 */
2046 {
2057 };
2059 /* Define parameter passing and return registers. */
2062 {
2064 };
2067 {
2069 };
2072 {
2074 };
2076 /* Additional registers that are clobbered by SYSV calls. */
2079 {
2084 };
2086 /* Define the structure for the machine field in struct function. */
2091 rtx rtl;
2093 };
2095 /* Structure describing stack frame layout.
2096 Stack grows downward:
2098 [arguments]
2099 <- ARG_POINTER
2100 saved pc
2102 saved static chain if ix86_static_chain_on_stack
2104 saved frame pointer if frame_pointer_needed
2105 <- HARD_FRAME_POINTER
2106 [saved regs]
2107 <- regs_save_offset
2108 [padding0]
2110 [saved SSE regs]
2111 <- sse_regs_save_offset
2112 [padding1] |
2113 | <- FRAME_POINTER
2114 [va_arg registers] |
2115 |
2116 [frame] |
2117 |
2118 [padding2] | = to_allocate
2119 <- STACK_POINTER
2120 */
2121 struct ix86_frame
2122 {
2129 /* The offsets relative to ARG_POINTER. */
2130 HOST_WIDE_INT frame_pointer_offset;
2131 HOST_WIDE_INT hard_frame_pointer_offset;
2132 HOST_WIDE_INT stack_pointer_offset;
2133 HOST_WIDE_INT hfp_save_offset;
2134 HOST_WIDE_INT reg_save_offset;
2135 HOST_WIDE_INT sse_reg_save_offset;
2137 /* When save_regs_using_mov is set, emit prologue using
2138 move instead of push instructions. */
2140 };
2142 /* Which cpu are we scheduling for. */
2145 /* Which cpu are we optimizing for. */
2148 /* Which instruction set architecture to use. */
2151 /* True if processor has SSE prefetch instruction. */
2154 /* -mstackrealign option */
2171 /* Preferred alignment for stack boundary in bits. */
2174 /* Alignment for incoming stack boundary in bits specified at
2175 command line. */
2178 /* Default alignment for incoming stack boundary in bits. */
2181 /* Alignment for incoming stack boundary in bits. */
2184 /* Calling abi specific va_list type nodes. */
2188 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2192 /* Fence to use after loop using movnt. */
2193 tree x86_mfence;
2195 /* Register class used for passing given 64bit part of the argument.
2196 These represent classes as documented by the PS ABI, with the exception
2197 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2198 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2200 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2201 whenever possible (upper half does contain padding). */
2202 enum x86_64_reg_class
2203 {
2204 X86_64_NO_CLASS,
2205 X86_64_INTEGER_CLASS,
2206 X86_64_INTEGERSI_CLASS,
2207 X86_64_SSE_CLASS,
2208 X86_64_SSESF_CLASS,
2209 X86_64_SSEDF_CLASS,
2210 X86_64_SSEUP_CLASS,
2211 X86_64_X87_CLASS,
2212 X86_64_X87UP_CLASS,
2213 X86_64_COMPLEX_X87_CLASS,
2214 X86_64_MEMORY_CLASS
2215 };
2217 #define MAX_CLASSES 4
2219 /* Table of constants used by fldpi, fldln2, etc.... */
2223 \f
2228 const_tree);
2240 enum ix86_function_specific_strings
2241 {
2242 IX86_FUNCTION_SPECIFIC_ARCH,
2243 IX86_FUNCTION_SPECIFIC_TUNE,
2244 IX86_FUNCTION_SPECIFIC_MAX
2245 };
2262 \f
2263 #ifndef SUBTARGET32_DEFAULT_CPU
2265 #endif
2267 /* Whether -mtune= or -march= were specified */
2271 /* Vectorization library interface and handlers. */
2277 /* Processor target table, indexed by processor number */
2278 struct ptt
2279 {
2286 };
2289 {
2300 /* Core 2 */
2302 /* Core i7 */
2304 /* Core avx2 */
2315 };
2318 {
2348 "btver2"
2349 };
2350 \f
2351 static bool
2353 {
2355 }
2357 static unsigned int
2359 {
2362 /* vzeroupper instructions are inserted immediately after reload to
2363 account for possible spills from 256bit registers. The pass
2364 reuses mode switching infrastructure by re-running mode insertion
2365 pass, so disable entities that have already been processed. */
2371 /* Call optimize_mode_switching. */
2374 }
2379 {
2391 };
2394 {
2398 {}
2400 /* opt_pass methods: */
2408 rtl_opt_pass *
2410 {
2412 }
2414 /* Return true if a red-zone is in use. */
2418 {
2420 }
2421 \f
2422 /* Return a string that documents the current -m options. The caller is
2423 responsible for freeing the string. */
2429 {
2430 struct ix86_target_opts
2431 {
2434 };
2436 /* This table is ordered so that options like -msse4.2 that imply
2437 preceding options while match those first. */
2439 {
2479 };
2481 /* Flag options. */
2483 {
2511 };
2528 /* Add -march= option. */
2530 {
2533 }
2535 /* Add -mtune= option. */
2537 {
2540 }
2542 /* Add -m32/-m64/-mx32. */
2544 {
2547 else
2549 isa &= ~ (OPTION_MASK_ISA_64BIT
2550 | OPTION_MASK_ABI_64
2552 }
2553 else
2557 /* Pick out the options in isa options. */
2559 {
2561 {
2564 }
2565 }
2568 {
2571 isa);
2572 }
2574 /* Add flag options. */
2576 {
2578 {
2581 }
2582 }
2585 {
2588 }
2590 /* Add -fpmath= option. */
2592 {
2595 {
2610 }
2611 }
2613 /* Any options? */
2619 /* Size the string. */
2623 {
2628 }
2630 /* Build the string. */
2635 {
2642 {
2644 line_len++;
2647 {
2651 }
2652 }
2656 {
2660 }
2661 }
2667 }
2669 /* Return true, if profiling code should be emitted before
2670 prologue. Otherwise it returns false.
2671 Note: For x86 with "hotfix" it is sorried. */
2672 static bool
2674 {
2676 }
2678 /* Function that is callable from the debugger to print the current
2679 options. */
2680 void ATTRIBUTE_UNUSED
2682 {
2688 {
2691 }
2692 else
2696 }
2699 #define DEF_ENUM
2700 #define DEF_ALG(alg, name) #name,
2702 #undef DEF_ENUM
2703 #undef DEF_ALG
2704 };
2706 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2707 The string is of the following form (or comma separated list of it):
2709 strategy_alg:max_size:[align|noalign]
2711 where the full size range for the strategy is either [0, max_size] or
2712 [min_size, max_size], in which min_size is the max_size + 1 of the
2713 preceding range. The last size range must have max_size == -1.
2715 Examples:
2717 1.
2718 -mmemcpy-strategy=libcall:-1:noalign
2720 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2723 2.
2724 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2726 This is to tell the compiler to use the following strategy for memset
2727 1) when the expected size is between [1, 16], use rep_8byte strategy;
2728 2) when the size is between [17, 2048], use vector_loop;
2729 3) when the size is > 2048, use libcall. */
2731 struct stringop_size_range
2732 {
2734 stringop_alg alg;
2736 };
2738 static void
2740 {
2748 else
2753 do
2754 {
2756 stringop_alg alg;
2765 {
2769 }
2772 {
2776 }
2779 {
2781 {
2784 }
2785 }
2788 {
2790 alg_name,
2793 }
2801 else
2802 {
2806 }
2807 n++;
2809 }
2813 {
2818 }
2821 {
2825 }
2827 /* Now override the default algs array. */
2829 {
2835 }
2836 }
2838 \f
2839 /* parse -mtune-ctrl= option. When DUMP is true,
2840 print the features that are explicitly set. */
2842 static void
2844 {
2852 do
2853 {
2860 {
2861 curr_feature_string++;
2863 }
2865 {
2867 {
2873 }
2874 }
2879 }
2882 }
2884 /* Helper function to set ix86_tune_features. IX86_TUNE is the
2885 processor type. */
2887 static void
2889 {
2894 {
2897 else
2899 }
2902 {
2907 }
2910 }
2913 /* Override various settings based on options. If MAIN_ARGS_P, the
2914 options are from the command line, otherwise they are from
2915 attributes. */
2917 static void
2919 {
2927 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2928 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2929 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2930 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2931 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2932 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2933 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2934 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2935 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2936 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2937 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2938 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2939 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2940 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2941 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2942 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2943 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2944 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2945 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2946 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2947 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2948 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2949 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2950 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2951 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2952 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2953 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2954 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2955 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2956 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2957 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2958 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2959 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2960 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2961 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2962 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2963 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2964 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2965 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2966 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2967 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
2968 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
2969 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
2970 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
2972 /* if this reaches 64, need to widen struct pta flags below */
2974 static struct pta
2975 {
2980 }
2982 {
3115 PTA_64BIT
3117 };
3119 /* -mrecip options. */
3120 static struct
3121 {
3124 }
3126 {
3133 };
3137 /* Set up prefix/suffix so the error messages refer to either the command
3138 line argument, or the attribute(target). */
3140 {
3144 }
3145 else
3146 {
3150 }
3152 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3153 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3156 #ifdef TARGET_BI_ARCH
3157 else
3158 {
3159 #if TARGET_BI_ARCH == 1
3160 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3161 is on and OPTION_MASK_ABI_X32 is off. We turn off
3162 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3163 -mx32. */
3166 #else
3167 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3168 on and OPTION_MASK_ABI_64 is off. We turn off
3169 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3170 -m64. */
3173 #endif
3174 }
3175 #endif
3178 {
3179 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3180 OPTION_MASK_ABI_64 for TARGET_X32. */
3183 }
3185 {
3186 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3187 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3190 }
3192 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3193 SUBTARGET_OVERRIDE_OPTIONS;
3194 #endif
3196 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3197 SUBSUBTARGET_OVERRIDE_OPTIONS;
3198 #endif
3200 /* -fPIC is the default for x86_64. */
3204 /* Need to check -mtune=generic first. */
3206 {
3209 /* As special support for cross compilers we read -mtune=native
3210 as -mtune=generic. With native compilers we won't see the
3211 -mtune=native, as it was changed by the driver. */
3213 {
3215 }
3216 /* If this call is for setting the option attribute, allow the
3217 generic that was previously set. */
3220 ;
3228 }
3229 else
3230 {
3234 {
3237 }
3239 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3240 need to use a sensible tune option. */
3244 {
3246 }
3247 }
3250 {
3251 /* rep; movq isn't available in 32-bit code. */
3254 }
3258 else
3262 {
3268 }
3269 else
3275 /* For targets using ms ABI enable ms-extensions, if not
3276 explicit turned off. For non-ms ABI we turn off this
3277 option. */
3282 {
3284 {
3328 {
3331 }
3339 }
3340 }
3341 else
3342 {
3343 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3344 use of rip-relative addressing. This eliminates fixups that
3345 would otherwise be needed if this object is to be placed in a
3346 DLL, and is essentially just as efficient as direct addressing. */
3351 else
3353 }
3355 {
3358 }
3365 {
3368 /* Default cpu tuning to the architecture. */
3505 }
3520 {
3524 {
3526 {
3528 {
3536 }
3537 else
3540 }
3541 }
3542 /* Intel CPUs have always interpreted SSE prefetch instructions as
3543 NOPs; so, we can enable SSE prefetch instructions even when
3544 -mtune (rather than -march) points us to a processor that has them.
3545 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3546 higher processors. */
3551 }
3559 #ifndef USE_IX86_FRAME_POINTER
3560 #define USE_IX86_FRAME_POINTER 0
3561 #endif
3563 #ifndef USE_X86_64_FRAME_POINTER
3564 #define USE_X86_64_FRAME_POINTER 0
3565 #endif
3567 /* Set the default values for switches whose default depends on TARGET_64BIT
3568 in case they weren't overwritten by command line options. */
3570 {
3577 }
3578 else
3579 {
3586 }
3591 else
3594 /* Arrange to set up i386_stack_locals for all functions. */
3597 /* Validate -mregparm= value. */
3599 {
3603 {
3607 }
3608 }
3612 /* Default align_* from the processor table. */
3614 {
3617 }
3619 {
3622 }
3624 {
3626 }
3628 /* Provide default for -mbranch-cost= value. */
3633 {
3636 /* Enable by default the SSE and MMX builtins. Do allow the user to
3637 explicitly disable any of these. In particular, disabling SSE and
3638 MMX for kernel code is extremely useful. */
3640 ix86_isa_flags
3646 }
3647 else
3648 {
3652 ix86_isa_flags
3655 /* i386 ABI does not specify red zone. It still makes sense to use it
3656 when programmer takes care to stack from being destroyed. */
3659 }
3661 /* Keep nonleaf frame pointers. */
3667 /* If we're doing fast math, we don't care about comparison order
3668 wrt NaNs. This lets us use a shorter comparison sequence. */
3672 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3673 since the insns won't need emulation. */
3677 /* Likewise, if the target doesn't have a 387, or we've specified
3678 software floating point, don't use 387 inline intrinsics. */
3682 /* Turn on MMX builtins for -msse. */
3686 /* Enable SSE prefetch. */
3690 /* Enable prefetch{,w} instructions for -m3dnow. */
3694 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3698 /* Enable lzcnt instruction for -mabm. */
3702 /* Validate -mpreferred-stack-boundary= value or default it to
3703 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3706 {
3712 {
3716 else
3719 }
3720 else
3721 ix86_preferred_stack_boundary
3723 }
3725 /* Set the default value for -mstackrealign. */
3731 /* Validate -mincoming-stack-boundary= value or default it to
3732 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3735 {
3740 else
3741 {
3742 ix86_user_incoming_stack_boundary
3744 ix86_incoming_stack_boundary
3746 }
3747 }
3749 /* Accept -msseregparm only if at least SSE support is enabled. */
3755 {
3757 {
3759 {
3762 }
3764 {
3767 }
3768 }
3769 }
3770 else
3773 /* If the i387 is disabled, then do not return values in it. */
3777 /* Use external vectorized library in vectorizing intrinsics. */
3780 {
3791 }
3800 /* ??? Unwind info is not correct around the CFG unless either a frame
3801 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3802 unwind info generation to be aware of the CFG and propagating states
3803 around edges. */
3806 && flag_omit_frame_pointer
3808 {
3814 }
3816 /* If stack probes are required, the space used for large function
3817 arguments on the stack must also be probed, so enable
3818 -maccumulate-outgoing-args so this happens in the prologue. */
3821 {
3826 }
3828 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3829 {
3835 }
3837 /* When scheduling description is not available, disable scheduler pass
3838 so it won't slow down the compilation and make x87 code slower. */
3859 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3861 && HAVE_prefetch
3866 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3867 can be optimized to ap = __builtin_next_arg (0). */
3872 {
3875 {
3877 ix86_gen_tls_local_dynamic_base_64
3879 }
3880 else
3881 {
3883 ix86_gen_tls_local_dynamic_base_64
3885 }
3886 }
3887 else
3891 {
3901 }
3902 else
3903 {
3913 }
3915 #ifdef USE_IX86_CLD
3916 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3919 #endif
3922 {
3927 }
3929 {
3933 }
3935 {
3936 #if defined(PROFILE_BEFORE_PROLOGUE)
3938 #else
3940 #endif
3941 }
3943 /* When not optimize for size, enable vzeroupper optimization for
3944 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3945 AVX unaligned load/store. */
3947 {
3957 /* Enable 128-bit AVX instruction generation
3958 for the auto-vectorizer. */
3962 }
3965 {
3972 {
3975 {
3977 q++;
3978 }
3979 else
3984 else
3985 {
3988 {
3991 }
3994 {
3998 }
3999 }
4004 else
4006 }
4007 }
4014 /* Default long double to 64-bit for Bionic. */
4019 /* Save the initial options in case the user does function specific
4020 options. */
4022 target_option_default_node = target_option_current_node
4025 /* Handle stack protector */
4029 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4031 {
4035 }
4038 {
4042 }
4043 }
4045 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4047 static void
4049 {
4051 static struct register_pass_info insert_vzeroupper_info
4054 };
4059 /* This needs to be done at start up. It's convenient to do it here. */
4061 }
4063 /* Update register usage after having seen the compiler flags. */
4065 static void
4067 {
4071 /* The PIC register, if it exists, is fixed. */
4076 /* For 32-bit targets, squash the REX registers. */
4078 {
4085 }
4087 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4095 {
4096 /* Set/reset conditionally defined registers from
4097 CALL_USED_REGISTERS initializer. */
4101 /* Calculate registers of CLOBBERED_REGS register set
4102 as call used registers from GENERAL_REGS register set. */
4106 }
4108 /* If MMX is disabled, squash the registers. */
4114 /* If SSE is disabled, squash the registers. */
4120 /* If the FPU is disabled, squash the registers. */
4126 /* If AVX512F is disabled, squash the registers. */
4128 {
4134 }
4135 }
4137 \f
4138 /* Save the current options */
4140 static void
4142 {
4153 /* The fields are char but the variables are not; make sure the
4154 values fit in the fields. */
4159 }
4161 /* Restore the current options */
4163 static void
4165 {
4181 /* Recreate the arch feature tests if the arch changed */
4183 {
4188 }
4190 /* Recreate the tune optimization tests */
4193 }
4195 /* Print the current options */
4197 static void
4200 {
4222 {
4225 }
4226 }
4228 \f
4229 /* Inner function to process the attribute((target(...))), take an argument and
4230 set the current options from the argument. If we have a list, recursively go
4231 over the list. */
4233 static bool
4236 {
4240 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4241 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4242 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4243 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4244 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4246 enum ix86_opt_type
4247 {
4248 ix86_opt_unknown,
4249 ix86_opt_yes,
4250 ix86_opt_no,
4251 ix86_opt_str,
4252 ix86_opt_enum,
4253 ix86_opt_isa
4254 };
4256 static const struct
4257 {
4264 /* isa options */
4305 /* enum options */
4308 /* string options */
4312 /* flag options */
4314 OPT_mcld,
4315 MASK_CLD),
4318 OPT_mfancy_math_387,
4319 MASK_NO_FANCY_MATH_387),
4322 OPT_mieee_fp,
4323 MASK_IEEE_FP),
4326 OPT_minline_all_stringops,
4327 MASK_INLINE_ALL_STRINGOPS),
4330 OPT_minline_stringops_dynamically,
4331 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4334 OPT_mno_align_stringops,
4335 MASK_NO_ALIGN_STRINGOPS),
4338 OPT_mrecip,
4339 MASK_RECIP),
4341 };
4343 /* If this is a list, recurse to get the options. */
4345 {
4355 }
4358 {
4361 }
4363 /* Handle multiple arguments separated by commas. */
4367 {
4381 {
4385 }
4386 else
4387 {
4390 }
4392 /* Recognize no-xxx. */
4394 {
4398 }
4399 else
4402 /* Find the option. */
4406 {
4414 {
4419 }
4420 }
4422 /* Process the option. */
4424 {
4427 }
4430 {
4436 }
4439 {
4445 else
4447 }
4450 {
4452 {
4455 }
4456 else
4458 }
4461 {
4469 global_dc);
4470 else
4471 {
4474 }
4475 }
4477 else
4479 }
4482 }
4484 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4486 tree
4488 {
4503 /* Process each of the options on the chain. */
4508 /* If the changed options are different from the default, rerun
4509 ix86_option_override_internal, and then save the options away.
4510 The string options are are attribute options, and will be undone
4511 when we copy the save structure. */
4517 {
4518 /* If we are using the default tune= or arch=, undo the string assigned,
4519 and use the default. */
4530 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4534 {
4537 }
4539 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4542 /* Add any builtin functions with the new isa if any. */
4545 /* Save the current options unless we are validating options for
4546 #pragma. */
4553 /* Free up memory allocated to hold the strings */
4556 }
4559 }
4561 /* Hook to validate attribute((target("string"))). */
4563 static bool
4566 tree args,
4568 {
4572 /* attribute((target("default"))) does nothing, beyond
4573 affecting multi-versioning. */
4584 /* If the function changed the optimization levels as well as setting target
4585 options, start with the optimizations specified. */
4590 /* The target attributes may also change some optimization flags, so update
4591 the optimization options if necessary. */
4600 {
4605 }
4614 }
4616 \f
4617 /* Hook to determine if one function can safely inline another. */
4619 static bool
4621 {
4626 /* If callee has no option attributes, then it is ok to inline. */
4630 /* If caller has no option attributes, but callee does then it is not ok to
4631 inline. */
4635 else
4636 {
4640 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4641 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4642 function. */
4647 /* See if we have the same non-isa options. */
4651 /* See if arch, tune, etc. are the same. */
4664 else
4666 }
4669 }
4671 \f
4672 /* Remember the last target of ix86_set_current_function. */
4675 /* Invalidate ix86_previous_fndecl cache. */
4676 void
4678 {
4680 }
4682 /* Establish appropriate back-end context for processing the function
4683 FNDECL. The argument might be NULL to indicate processing at top
4684 level, outside of any function scope. */
4685 static void
4687 {
4688 /* Only change the context if the function changes. This hook is called
4689 several times in the course of compiling a function, and we don't want to
4690 slow things down too much or call target_reinit when it isn't safe. */
4692 {
4693 tree old_tree = (ix86_previous_fndecl
4697 tree new_tree = (fndecl
4703 ;
4706 {
4710 }
4713 {
4719 }
4720 }
4721 }
4723 \f
4724 /* Return true if this goes in large data/bss. */
4726 static bool
4728 {
4732 /* Functions are never large data. */
4737 {
4743 }
4744 else
4745 {
4748 /* If this is an incomplete type with size 0, then we can't put it
4749 in data because it might be too big when completed. */
4752 }
4755 }
4757 /* Switch to the appropriate section for output of DECL.
4758 DECL is either a `VAR_DECL' node or a constant of some sort.
4759 RELOC indicates whether forming the initial value of DECL requires
4760 link-time relocations. */
4765 {
4768 {
4772 {
4806 /* We don't split these for medium model. Place them into
4807 default sections and hope for best. */
4809 }
4811 {
4812 /* We might get called with string constants, but get_named_section
4813 doesn't like them as they are not DECLs. Also, we need to set
4814 flags in that case. */
4818 }
4819 }
4821 }
4823 /* Select a set of attributes for section NAME based on the properties
4824 of DECL and whether or not RELOC indicates that DECL's initializer
4825 might contain runtime relocations. */
4827 static unsigned int ATTRIBUTE_UNUSED
4829 {
4843 }
4845 /* Build up a unique section name, expressed as a
4846 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4847 RELOC indicates whether the initial value of EXP requires
4848 link-time relocations. */
4850 static void ATTRIBUTE_UNUSED
4852 {
4855 {
4857 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4861 {
4885 /* We don't split these for medium model. Place them into
4886 default sections and hope for best. */
4888 }
4890 {
4897 /* If we're using one_only, then there needs to be a .gnu.linkonce
4898 prefix to the section name. */
4905 }
4906 }
4908 }
4910 #ifdef COMMON_ASM_OP
4911 /* This says how to output assembler code to declare an
4912 uninitialized external linkage data object.
4914 For medium model x86-64 we need to use .largecomm opcode for
4915 large objects. */
4916 void
4920 {
4924 else
4929 }
4930 #endif
4932 /* Utility function for targets to use in implementing
4933 ASM_OUTPUT_ALIGNED_BSS. */
4935 void
4939 {
4943 else
4946 #ifdef ASM_DECLARE_OBJECT_NAME
4949 #else
4950 /* Standard thing is just output label for the object. */
4954 }
4955 \f
4956 /* Decide whether we must probe the stack before any space allocation
4957 on this target. It's essentially TARGET_STACK_PROBE except when
4958 -fstack-check causes the stack to be already probed differently. */
4960 bool
4962 {
4963 /* Do not probe the stack twice if static stack checking is enabled. */
4968 }
4969 \f
4970 /* Decide whether we can make a sibling call to a function. DECL is the
4971 declaration of the function being targeted by the call and EXP is the
4972 CALL_EXPR representing the call. */
4974 static bool
4976 {
4980 /* If we are generating position-independent code, we cannot sibcall
4981 optimize any indirect call, or a direct call to a global function,
4982 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4984 && !TARGET_64BIT
4985 && flag_pic
4989 /* If we need to align the outgoing stack, then sibcalling would
4990 unalign the stack, which may break the called function. */
4996 {
4999 }
5000 else
5001 {
5002 /* We're looking at the CALL_EXPR, we need the type of the function. */
5007 }
5009 /* Check that the return value locations are the same. Like
5010 if we are returning floats on the 80387 register stack, we cannot
5011 make a sibcall from a function that doesn't return a float to a
5012 function that does or, conversely, from a function that does return
5013 a float to a function that doesn't; the necessary stack adjustment
5014 would not be executed. This is also the place we notice
5015 differences in the return value ABI. Note that it is ok for one
5016 of the functions to have void return type as long as the return
5017 value of the other is passed in a register. */
5022 {
5025 }
5027 ;
5032 {
5033 /* The SYSV ABI has more call-clobbered registers;
5034 disallow sibcalls from MS to SYSV. */
5038 }
5039 else
5040 {
5041 /* If this call is indirect, we'll need to be able to use a
5042 call-clobbered register for the address of the target function.
5043 Make sure that all such registers are not used for passing
5044 parameters. Note that DLLIMPORT functions are indirect. */
5047 {
5049 {
5050 /* ??? Need to count the actual number of registers to be used,
5051 not the possible number of registers. Fix later. */
5053 }
5054 }
5055 }
5057 /* Otherwise okay. That also includes certain types of indirect calls. */
5059 }
5061 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5062 and "sseregparm" calling convention attributes;
5063 arguments as in struct attribute_spec.handler. */
5065 static tree
5067 tree args,
5070 {
5075 {
5077 name);
5080 }
5082 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5084 {
5085 tree cst;
5088 {
5090 }
5093 {
5095 }
5099 {
5102 name);
5104 }
5106 {
5110 }
5113 }
5116 {
5117 /* Do not warn when emulating the MS ABI. */
5122 name);
5125 }
5127 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5129 {
5131 {
5133 }
5135 {
5137 }
5139 {
5141 }
5143 {
5145 }
5146 }
5148 /* Can combine stdcall with fastcall (redundant), regparm and
5149 sseregparm. */
5151 {
5153 {
5155 }
5157 {
5159 }
5161 {
5163 }
5164 }
5166 /* Can combine cdecl with regparm and sseregparm. */
5168 {
5170 {
5172 }
5174 {
5176 }
5178 {
5180 }
5181 }
5183 {
5186 name);
5188 {
5190 }
5192 {
5194 }
5196 {
5198 }
5199 }
5201 /* Can combine sseregparm with all attributes. */
5204 }
5206 /* The transactional memory builtins are implicitly regparm or fastcall
5207 depending on the ABI. Override the generic do-nothing attribute that
5208 these builtins were declared with, and replace it with one of the two
5209 attributes that we expect elsewhere. */
5211 static tree
5213 tree args ATTRIBUTE_UNUSED,
5215 {
5216 tree alt;
5218 /* In no case do we want to add the placeholder attribute. */
5221 /* The 64-bit ABI is unchanged for transactional memory. */
5225 /* ??? Is there a better way to validate 32-bit windows? We have
5226 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5229 else
5230 {
5233 }
5237 }
5239 /* This function determines from TYPE the calling-convention. */
5241 unsigned int
5243 {
5246 tree attrs;
5253 {
5263 /* Regparam isn't allowed for thiscall and fastcall. */
5265 {
5270 }
5274 }
5281 || is_stdarg
5287 }
5289 /* Return 0 if the attributes for two types are incompatible, 1 if they
5290 are compatible, and 2 if they are nearly compatible (which causes a
5291 warning to be generated). */
5293 static int
5295 {
5311 }
5312 \f
5313 /* Return the regparm value for a function with the indicated TYPE and DECL.
5314 DECL may be NULL when calling function indirectly
5315 or considering a libcall. */
5317 static int
5319 {
5320 tree attr;
5331 {
5334 {
5337 }
5338 }
5344 /* Use register calling convention for local functions when possible. */
5347 && optimize
5349 {
5350 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5353 {
5356 /* Make sure no regparm register is taken by a
5357 fixed register variable. */
5362 /* We don't want to use regparm(3) for nested functions as
5363 these use a static chain pointer in the third argument. */
5367 /* In 32-bit mode save a register for the split stack. */
5371 /* Each fixed register usage increases register pressure,
5372 so less registers should be used for argument passing.
5373 This functionality can be overriden by an explicit
5374 regparm value. */
5377 globals++;
5379 local_regparm
5384 }
5385 }
5388 }
5390 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5391 DFmode (2) arguments in SSE registers for a function with the
5392 indicated TYPE and DECL. DECL may be NULL when calling function
5393 indirectly or considering a libcall. Otherwise return 0. */
5395 static int
5397 {
5400 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5401 by the sseregparm attribute. */
5404 {
5406 {
5408 {
5412 else
5415 }
5417 }
5420 }
5422 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5423 (and DFmode for SSE2) arguments in SSE registers. */
5426 {
5427 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5431 }
5434 }
5436 /* Return true if EAX is live at the start of the function. Used by
5437 ix86_expand_prologue to determine if we need special help before
5438 calling allocate_stack_worker. */
5440 static bool
5442 {
5443 /* Cheat. Don't bother working forward from ix86_function_regparm
5444 to the function type to whether an actual argument is located in
5445 eax. Instead just look at cfg info, which is still close enough
5446 to correct at this point. This gives false positives for broken
5447 functions that might use uninitialized data that happens to be
5448 allocated in eax, but who cares? */
5450 }
5452 static bool
5454 {
5455 tree attr;
5458 {
5464 /* For 32-bit MS-ABI the default is to keep aggregate
5465 return pointer. */
5468 }
5470 }
5472 /* Value is the number of bytes of arguments automatically
5473 popped when returning from a subroutine call.
5474 FUNDECL is the declaration node of the function (as a tree),
5475 FUNTYPE is the data type of the function (as a tree),
5476 or for a library call it is an identifier node for the subroutine name.
5477 SIZE is the number of bytes of arguments passed on the stack.
5479 On the 80386, the RTD insn may be used to pop them if the number
5480 of args is fixed, but if the number is variable then the caller
5481 must pop them all. RTD can't be used for library calls now
5482 because the library is compiled with the Unix compiler.
5483 Use of RTD is a selectable option, since it is incompatible with
5484 standard Unix calling sequences. If the option is not selected,
5485 the caller must always pop the args.
5487 The attribute stdcall is equivalent to RTD on a per module basis. */
5489 static int
5491 {
5494 /* None of the 64-bit ABIs pop arguments. */
5505 /* Lose any fake structure return argument if it is passed on the stack. */
5508 {
5512 }
5515 }
5517 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5519 static bool
5521 {
5522 /* Check operand constraints in case hard registers were propagated
5523 into insn pattern. This check prevents combine pass from
5524 generating insn patterns with invalid hard register operands.
5525 These invalid insns can eventually confuse reload to error out
5526 with a spill failure. See also PRs 46829 and 46843. */
5528 {
5535 {
5543 /* A unary operator may be accepted by the predicate, but it
5544 is irrelevant for matching constraints. */
5549 {
5557 }
5564 /* Operand has no constraints, anything is OK. */
5568 {
5571 && operands_match_p
5575 {
5578 }
5579 }
5583 }
5584 }
5587 }
5588 \f
5589 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5591 static unsigned HOST_WIDE_INT
5593 {
5597 }
5598 \f
5599 /* Argument support functions. */
5601 /* Return true when register may be used to pass function parameters. */
5602 bool
5604 {
5609 {
5613 else
5619 }
5625 /* TODO: The function should depend on current function ABI but
5626 builtins.c would need updating then. Therefore we use the
5627 default ABI. */
5629 /* RAX is used as hidden argument to va_arg functions. */
5635 else
5642 }
5644 /* Return if we do not know how to pass TYPE solely in registers. */
5646 static bool
5648 {
5652 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5653 The layout_type routine is crafty and tries to trick us into passing
5654 currently unsupported vector types on the stack by using TImode. */
5657 }
5659 /* It returns the size, in bytes, of the area reserved for arguments passed
5660 in registers for the function represented by fndecl dependent to the used
5661 abi format. */
5662 int
5664 {
5668 else
5673 }
5675 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5676 call abi used. */
5677 enum calling_abi
5679 {
5681 {
5684 {
5687 }
5691 }
5693 }
5695 /* We add this as a workaround in order to use libc_has_function
5696 hook in i386.md. */
5697 bool
5699 {
5701 }
5703 static bool
5705 {
5707 {
5711 else
5713 }
5715 }
5717 static enum calling_abi
5719 {
5723 }
5725 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5726 call abi used. */
5727 enum calling_abi
5729 {
5733 }
5735 /* Write the extra assembler code needed to declare a function properly. */
5737 void
5739 tree decl)
5740 {
5744 {
5750 }
5752 #ifdef SUBTARGET_ASM_UNWIND_INIT
5754 #endif
5758 /* Output magic byte marker, if hot-patch attribute is set. */
5760 {
5762 {
5763 /* leaq [%rsp + 0], %rsp */
5766 }
5767 else
5768 {
5769 /* movl.s %edi, %edi
5770 push %ebp
5771 movl.s %esp, %ebp */
5774 }
5775 }
5776 }
5778 /* regclass.c */
5781 /* Implementation of call abi switching target hook. Specific to FNDECL
5782 the specific call register sets are set. See also
5783 ix86_conditional_register_usage for more details. */
5784 void
5786 {
5789 else
5791 }
5793 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5794 expensive re-initialization of init_regs each time we switch function context
5795 since this is needed only during RTL expansion. */
5796 static void
5798 {
5802 }
5804 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5805 for a call to a function whose data type is FNTYPE.
5806 For a library call, FNTYPE is 0. */
5808 void
5812 tree fndecl,
5814 {
5820 {
5823 }
5824 else
5825 {
5828 }
5832 /* Set up the number of registers to use for passing arguments. */
5839 {
5841 ? X86_64_REGPARM_MAX
5843 }
5845 {
5848 {
5850 ? X86_64_SSE_REGPARM_MAX
5852 }
5853 }
5860 /* Because type might mismatch in between caller and callee, we need to
5861 use actual type of function for local calls.
5862 FIXME: cgraph_analyze can be told to actually record if function uses
5863 va_start so for local functions maybe_vaarg can be made aggressive
5864 helping K&R code.
5865 FIXME: once typesytem is fixed, we won't need this code anymore. */
5873 {
5874 /* If there are variable arguments, then we won't pass anything
5875 in registers in 32-bit mode. */
5877 {
5885 }
5887 /* Use ecx and edx registers if function has fastcall attribute,
5888 else look for regparm information. */
5890 {
5893 {
5896 }
5898 {
5901 }
5902 else
5904 }
5906 /* Set up the number of SSE registers used for passing SFmode
5907 and DFmode arguments. Warn for mismatching ABI. */
5909 }
5910 }
5912 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5913 But in the case of vector types, it is some vector mode.
5915 When we have only some of our vector isa extensions enabled, then there
5916 are some modes for which vector_mode_supported_p is false. For these
5917 modes, the generic vector support in gcc will choose some non-vector mode
5918 in order to implement the type. By computing the natural mode, we'll
5919 select the proper ABI location for the operand and not depend on whatever
5920 the middle-end decides to do with these vector types.
5922 The midde-end can't deal with the vector types > 16 bytes. In this
5923 case, we return the original mode and warn ABI change if CUM isn't
5924 NULL. */
5926 static enum machine_mode
5928 {
5932 {
5935 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5937 {
5942 else
5945 /* Get the mode which has this inner mode and number of units. */
5949 {
5951 {
5955 && !warnedavx
5957 {
5961 }
5963 }
5965 {
5969 && !warnedsse
5971 {
5975 }
5977 }
5978 else
5980 }
5983 }
5984 }
5987 }
5989 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5990 this may not agree with the mode that the type system has chosen for the
5991 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5992 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5994 static rtx
5997 {
5998 rtx tmp;
6002 else
6003 {
6007 }
6010 }
6012 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6013 of this code is to classify each 8bytes of incoming argument by the register
6014 class and assign registers accordingly. */
6016 /* Return the union class of CLASS1 and CLASS2.
6017 See the x86-64 PS ABI for details. */
6019 static enum x86_64_reg_class
6021 {
6022 /* Rule #1: If both classes are equal, this is the resulting class. */
6026 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6027 the other class. */
6033 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6037 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6045 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6046 MEMORY is used. */
6055 /* Rule #6: Otherwise class SSE is used. */
6057 }
6059 /* Classify the argument of type TYPE and mode MODE.
6060 CLASSES will be filled by the register class used to pass each word
6061 of the operand. The number of words is returned. In case the parameter
6062 should be passed in memory, 0 is returned. As a special case for zero
6063 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6065 BIT_OFFSET is used internally for handling records and specifies offset
6066 of the offset in bits modulo 256 to avoid overflow cases.
6068 See the x86-64 PS ABI for details.
6069 */
6071 static int
6074 {
6075 HOST_WIDE_INT bytes =
6077 int words
6080 /* Variable sized entities are always passed/returned in memory. */
6089 {
6091 tree field;
6094 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
6101 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6102 signalize memory class, so handle it as special case. */
6104 {
6107 }
6109 /* Classify each field of record and merge classes. */
6111 {
6113 /* And now merge the fields of structure. */
6115 {
6117 {
6123 /* Bitfields are always classified as integer. Handle them
6124 early, since later code would consider them to be
6125 misaligned integers. */
6127 {
6136 }
6137 else
6138 {
6143 /* Flexible array member is ignored. */
6150 {
6154 {
6157 "the ABI of passing struct with"
6158 " a flexible array member has"
6160 }
6162 }
6164 subclasses,
6174 }
6175 }
6176 }
6180 /* Arrays are handled as small records. */
6181 {
6188 /* The partial classes are now full classes. */
6199 }
6202 /* Unions are similar to RECORD_TYPE but offset is always 0.
6203 */
6205 {
6207 {
6215 bit_offset);
6220 }
6221 }
6226 }
6229 {
6230 /* When size > 16 bytes, if the first one isn't
6231 X86_64_SSE_CLASS or any other ones aren't
6232 X86_64_SSEUP_CLASS, everything should be passed in
6233 memory. */
6240 }
6242 /* Final merger cleanup. */
6244 {
6245 /* If one class is MEMORY, everything should be passed in
6246 memory. */
6250 /* The X86_64_SSEUP_CLASS should be always preceded by
6251 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6255 {
6256 /* The first one should never be X86_64_SSEUP_CLASS. */
6259 }
6261 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6262 everything should be passed in memory. */
6265 {
6268 /* The first one should never be X86_64_X87UP_CLASS. */
6271 {
6274 "the ABI of passing union with long double"
6276 }
6278 }
6279 }
6281 }
6283 /* Compute alignment needed. We align all types to natural boundaries with
6284 exception of XFmode that is aligned to 64bits. */
6286 {
6295 /* Misaligned fields are always returned in memory. */
6298 }
6300 /* for V1xx modes, just use the base mode */
6305 /* Classification of atomic types. */
6307 {
6323 {
6327 {
6330 }
6332 {
6335 }
6337 {
6341 }
6343 {
6346 }
6347 else
6349 }
6356 /* OImode shouldn't be used directly. */
6363 else
6381 else
6382 {
6386 {
6389 "the ABI of passing structure with complex float"
6391 }
6394 }
6403 /* This modes is larger than 16 bytes. */
6446 else
6450 }
6451 }
6453 /* Examine the argument and return set number of register required in each
6454 class. Return 0 iff parameter should be passed in memory. */
6455 static int
6458 {
6468 {
6490 }
6492 }
6494 /* Construct container for the argument used by GCC interface. See
6495 FUNCTION_ARG for the detailed description. */
6497 static rtx
6501 {
6502 /* The following variables hold the static issued_error state. */
6516 rtx ret;
6527 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6528 some less clueful developer tries to use floating-point anyway. */
6530 {
6532 {
6534 {
6537 }
6538 }
6540 {
6543 }
6545 }
6547 /* Likewise, error if the ABI requires us to return values in the
6548 x87 registers and the user specified -mno-80387. */
6554 {
6556 {
6559 }
6561 }
6563 /* First construct simple cases. Avoid SCmode, since we want to use
6564 single register to pass this type. */
6567 {
6582 /* Zero sized array, struct or class. */
6586 }
6613 /* Otherwise figure out the entries of the PARALLEL. */
6615 {
6619 {
6624 /* Merge TImodes on aligned occasions here too. */
6626 tmpmode
6630 else
6632 /* We've requested 24 bytes we
6633 don't have mode for. Use DImode. */
6640 intreg++;
6648 sse_regno++;
6656 sse_regno++;
6661 {
6667 {
6669 i++;
6670 }
6671 else
6684 }
6690 sse_regno++;
6694 }
6695 }
6697 /* Empty aligned struct, union or class. */
6705 }
6707 /* Update the data in CUM to advance over an argument of mode MODE
6708 and data type TYPE. (TYPE is null for libcalls where that information
6709 may not be available.) */
6711 static void
6714 HOST_WIDE_INT words)
6715 {
6717 {
6724 /* FALLTHRU */
6735 {
6738 }
6742 /* OImode shouldn't be used directly. */
6751 /* FALLTHRU */
6767 {
6772 {
6775 }
6776 }
6786 {
6791 {
6794 }
6795 }
6797 }
6798 }
6800 static void
6803 {
6806 /* Unnamed 256bit vector mode parameters are passed on stack. */
6812 {
6817 }
6818 else
6819 {
6823 }
6824 }
6826 static void
6828 HOST_WIDE_INT words)
6829 {
6830 /* Otherwise, this should be passed indirect. */
6835 {
6838 }
6839 }
6841 /* Update the data in CUM to advance over an argument of mode MODE and
6842 data type TYPE. (TYPE is null for libcalls where that information
6843 may not be available.) */
6845 static void
6848 {
6854 else
6865 else
6867 }
6869 /* Define where to put the arguments to a function.
6870 Value is zero to push the argument on the stack,
6871 or a hard register in which to store the argument.
6873 MODE is the argument's machine mode.
6874 TYPE is the data type of the argument (as a tree).
6875 This is null for libcalls where that information may
6876 not be available.
6877 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6878 the preceding args and about the function being called.
6879 NAMED is nonzero if this argument is a named parameter
6880 (otherwise it is an extra parameter matching an ellipsis). */
6882 static rtx
6886 {
6889 /* Avoid the AL settings for the Unix64 ABI. */
6894 {
6901 /* FALLTHRU */
6907 {
6910 /* Fastcall allocates the first two DWORD (SImode) or
6911 smaller arguments to ECX and EDX if it isn't an
6912 aggregate type . */
6914 {
6920 /* ECX not EAX is the first allocated register. */
6923 }
6925 }
6934 /* FALLTHRU */
6936 /* In 32bit, we pass TImode in xmm registers. */
6944 {
6946 {
6950 }
6954 }
6958 /* OImode shouldn't be used directly. */
6968 {
6972 }
6982 {
6984 {
6988 }
6992 }
6994 }
6997 }
6999 static rtx
7002 {
7003 /* Handle a hidden AL argument containing number of registers
7004 for varargs x86-64 functions. */
7008 ? X86_64_SSE_REGPARM_MAX
7013 {
7023 /* Unnamed 256bit vector mode parameters are passed on stack. */
7027 }
7033 }
7035 static rtx
7038 HOST_WIDE_INT bytes)
7039 {
7042 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7043 We use value of -2 to specify that current function call is MSABI. */
7047 /* If we've run out of registers, it goes on the stack. */
7053 /* Only floating point modes are passed in anything but integer regs. */
7055 {
7058 else
7059 {
7062 /* Unnamed floating parameters are passed in both the
7063 SSE and integer registers. */
7069 }
7070 }
7071 /* Handle aggregated types passed in register. */
7073 {
7078 }
7081 }
7083 /* Return where to put the arguments to a function.
7084 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7086 MODE is the argument's machine mode. TYPE is the data type of the
7087 argument. It is null for libcalls where that information may not be
7088 available. CUM gives information about the preceding args and about
7089 the function being called. NAMED is nonzero if this argument is a
7090 named parameter (otherwise it is an extra parameter matching an
7091 ellipsis). */
7093 static rtx
7096 {
7100 rtx arg;
7104 else
7108 /* To simplify the code below, represent vector types with a vector mode
7109 even if MMX/SSE are not active. */
7117 else
7121 }
7123 /* A C expression that indicates when an argument must be passed by
7124 reference. If nonzero for an argument, a copy of that argument is
7125 made in memory and a pointer to the argument is passed instead of
7126 the argument itself. The pointer is passed in whatever way is
7127 appropriate for passing a pointer to that type. */
7129 static bool
7132 {
7135 /* See Windows x64 Software Convention. */
7137 {
7140 {
7141 /* Arrays are passed by reference. */
7146 {
7147 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7148 are passed by reference. */
7150 }
7151 }
7153 /* __m128 is passed by reference. */
7159 }
7160 }
7165 }
7167 /* Return true when TYPE should be 128bit aligned for 32bit argument
7168 passing ABI. XXX: This function is obsolete and is only used for
7169 checking psABI compatibility with previous versions of GCC. */
7171 static bool
7173 {
7185 {
7186 /* Walk the aggregates recursively. */
7188 {
7192 {
7193 tree field;
7195 /* Walk all the structure fields. */
7197 {
7201 }
7203 }
7206 /* Just for use if some languages passes arrays by value. */
7213 }
7214 }
7216 }
7218 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7219 XXX: This function is obsolete and is only used for checking psABI
7220 compatibility with previous versions of GCC. */
7222 static unsigned int
7225 {
7226 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7227 natural boundaries. */
7229 {
7230 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7231 make an exception for SSE modes since these require 128bit
7232 alignment.
7234 The handling here differs from field_alignment. ICC aligns MMX
7235 arguments to 4 byte boundaries, while structure fields are aligned
7236 to 8 byte boundaries. */
7238 {
7241 }
7242 else
7243 {
7246 }
7247 }
7251 }
7253 /* Return true when TYPE should be 128bit aligned for 32bit argument
7254 passing ABI. */
7256 static bool
7258 {
7268 {
7269 /* Walk the aggregates recursively. */
7271 {
7275 {
7276 tree field;
7278 /* Walk all the structure fields. */
7280 field;
7282 {
7286 }
7288 }
7291 /* Just for use if some languages passes arrays by value. */
7298 }
7299 }
7300 else
7304 }
7306 /* Gives the alignment boundary, in bits, of an argument with the
7307 specified mode and type. */
7309 static unsigned int
7311 {
7314 {
7315 /* Since the main variant type is used for call, we convert it to
7316 the main variant type. */
7319 }
7320 else
7324 else
7325 {
7330 {
7331 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7333 {
7336 }
7342 }
7345 && !warned
7347 saved_align))
7348 {
7351 "The ABI for passing parameters with %d-byte"
7354 }
7355 }
7358 }
7360 /* Return true if N is a possible register number of function value. */
7362 static bool
7364 {
7366 {
7371 /* TODO: The function should depend on current function ABI but
7372 builtins.c would need updating then. Therefore we use the
7373 default ABI. */
7385 }
7388 }
7390 /* Define how to find the value returned by a function.
7391 VALTYPE is the data type of the value (as a tree).
7392 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7393 otherwise, FUNC is 0. */
7395 static rtx
7398 {
7401 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7402 we normally prevent this case when mmx is not available. However
7403 some ABIs may require the result to be returned like DImode. */
7407 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7408 we prevent this case when sse is not available. However some ABIs
7409 may require the result to be returned like integer TImode. */
7414 /* 32-byte vector modes in %ymm0. */
7418 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7421 else
7422 /* Most things go in %eax. */
7425 /* Override FP return register with %xmm0 for local functions when
7426 SSE math is enabled or for functions with sseregparm attribute. */
7428 {
7433 }
7435 /* OImode shouldn't be used directly. */
7439 }
7441 static rtx
7443 const_tree valtype)
7444 {
7445 rtx ret;
7447 /* Handle libcalls, which don't provide a type node. */
7449 {
7453 {
7472 }
7475 }
7477 {
7478 /* Pointers are always returned in word_mode. */
7480 }
7486 /* For zero sized structures, construct_container returns NULL, but we
7487 need to keep rest of compiler happy by returning meaningful value. */
7492 }
7494 static rtx
7496 const_tree valtype)
7497 {
7501 {
7503 {
7522 }
7523 }
7525 }
7527 static rtx
7530 {
7542 else
7544 }
7546 static rtx
7549 {
7555 }
7557 /* Pointer function arguments and return values are promoted to
7558 word_mode. */
7560 static enum machine_mode
7564 {
7566 {
7569 }
7571 for_return);
7572 }
7574 /* Return true if a structure, union or array with MODE containing FIELD
7575 should be accessed using BLKmode. */
7577 static bool
7579 {
7580 /* Union with XFmode must be in BLKmode. */
7584 }
7586 rtx
7588 {
7590 }
7592 /* Return true iff type is returned in memory. */
7594 static bool ATTRIBUTE_UNUSED
7596 {
7597 HOST_WIDE_INT size;
7608 {
7609 /* User-created vectors small enough to fit in EAX. */
7613 /* MMX/3dNow values are returned in MM0,
7614 except when it doesn't exits or the ABI prescribes otherwise. */
7618 /* SSE values are returned in XMM0, except when it doesn't exist. */
7622 /* AVX values are returned in YMM0, except when it doesn't exist. */
7625 }
7633 /* OImode shouldn't be used directly. */
7637 }
7639 static bool ATTRIBUTE_UNUSED
7641 {
7644 }
7646 static bool ATTRIBUTE_UNUSED
7648 {
7651 /* __m128 is returned in xmm0. */
7658 /* Otherwise, the size must be exactly in [1248]. */
7660 }
7662 static bool
7664 {
7665 #ifdef SUBTARGET_RETURN_IN_MEMORY
7667 #else
7671 {
7674 else
7676 }
7677 else
7679 #endif
7680 }
7682 /* When returning SSE vector types, we have a choice of either
7683 (1) being abi incompatible with a -march switch, or
7684 (2) generating an error.
7685 Given no good solution, I think the safest thing is one warning.
7686 The user won't be able to use -Werror, but....
7688 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7689 called in response to actually generating a caller or callee that
7690 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7691 via aggregate_value_p for general type probing from tree-ssa. */
7693 static rtx
7695 {
7699 {
7700 /* Look at the return type of the function, not the function type. */
7704 {
7707 {
7711 }
7712 }
7715 {
7717 {
7721 }
7722 }
7723 }
7726 }
7728 \f
7729 /* Create the va_list data type. */
7731 /* Returns the calling convention specific va_list date type.
7732 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7734 static tree
7736 {
7739 /* For i386 we use plain pointer to argument area. */
7749 unsigned_type_node);
7752 unsigned_type_node);
7755 ptr_type_node);
7758 ptr_type_node);
7777 /* The correct type is an array type of one element. */
7779 }
7781 /* Setup the builtin va_list data type and for 64-bit the additional
7782 calling convention specific va_list data types. */
7784 static tree
7786 {
7789 /* Initialize abi specific va_list builtin types. */
7791 {
7792 tree t;
7794 {
7799 }
7800 else
7801 {
7806 }
7808 {
7813 }
7814 else
7815 {
7820 }
7821 }
7824 }
7826 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7828 static void
7830 {
7832 alias_set_type set;
7835 /* GPR size of varargs save area. */
7838 else
7841 /* FPR size of varargs save area. We don't need it if we don't pass
7842 anything in SSE registers. */
7845 else
7859 {
7867 }
7870 {
7874 /* Now emit code to save SSE registers. The AX parameter contains number
7875 of SSE parameter registers used to call this function, though all we
7876 actually check here is the zero/non-zero status. */
7881 label));
7883 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7884 we used movdqa (i.e. TImode) instead? Perhaps even better would
7885 be if we could determine the real mode of the data, via a hook
7886 into pass_stdarg. Ignore all that for now. */
7896 {
7905 }
7908 }
7909 }
7911 static void
7913 {
7917 /* Reset to zero, as there might be a sysv vaarg used
7918 before. */
7923 {
7934 }
7935 }
7937 static void
7941 {
7943 CUMULATIVE_ARGS next_cum;
7944 tree fntype;
7946 /* This argument doesn't appear to be used anymore. Which is good,
7947 because the old code here didn't suppress rtl generation. */
7955 /* For varargs, we do not want to skip the dummy va_dcl argument.
7956 For stdargs, we do want to skip the last named argument. */
7964 else
7966 }
7968 /* Checks if TYPE is of kind va_list char *. */
7970 static bool
7972 {
7973 tree canonic;
7975 /* For 32-bit it is always true. */
7981 }
7983 /* Implement va_start. */
7985 static void
7987 {
7991 tree type;
7992 rtx ovf_rtx;
7996 {
7999 /* When we are splitting the stack, we can't refer to the stack
8000 arguments using internal_arg_pointer, because they may be on
8001 the old stack. The split stack prologue will arrange to
8002 leave a pointer to the old stack arguments in a scratch
8003 register, which we here copy to a pseudo-register. The split
8004 stack prologue can't set the pseudo-register directly because
8005 it (the prologue) runs before any registers have been saved. */
8009 {
8023 }
8024 }
8026 /* Only 64bit target needs something special. */
8028 {
8031 else
8032 {
8041 }
8043 }
8052 /* The following should be folded into the MEM_REF offset. */
8062 /* Count number of gp and fp argument registers used. */
8068 {
8074 }
8077 {
8083 }
8085 /* Find the overflow area. */
8089 else
8099 {
8100 /* Find the register save area.
8101 Prologue of the function save it right above stack frame. */
8109 }
8110 }
8112 /* Implement va_arg. */
8114 static tree
8117 {
8124 rtx container;
8126 tree ptrtype;
8130 /* Only 64bit target needs something special. */
8154 {
8161 /* Unnamed 256bit vector mode parameters are passed on stack. */
8163 {
8166 }
8174 }
8176 /* Pull the value out of the saved registers. */
8181 {
8195 /* In case we are passing structure, verify that it is consecutive block
8196 on the register save area. If not we need to do moves. */
8198 {
8199 /* Verify that all registers are strictly consecutive */
8201 {
8205 {
8210 }
8211 }
8212 else
8213 {
8217 {
8222 }
8223 }
8224 }
8226 {
8229 }
8230 else
8231 {
8234 }
8236 /* First ensure that we fit completely in registers. */
8238 {
8245 }
8247 {
8255 }
8257 /* Compute index to start of area used for integer regs. */
8259 {
8260 /* int_addr = gpr + sav; */
8263 }
8265 {
8266 /* sse_addr = fpr + sav; */
8269 }
8271 {
8275 /* addr = &temp; */
8280 {
8284 tree piece_type;
8285 tree addr_type;
8286 tree daddr_type;
8295 {
8300 }
8304 else
8311 {
8314 }
8315 else
8316 {
8319 }
8326 {
8331 }
8332 else
8333 {
8334 tree copy
8339 }
8341 }
8342 }
8345 {
8349 }
8352 {
8356 }
8361 }
8363 /* ... otherwise out of the overflow area. */
8365 /* When we align parameter on stack for caller, if the parameter
8366 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8367 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8368 here with caller. */
8373 /* Care for on-stack alignment if needed. */
8376 else
8377 {
8382 }
8399 }
8400 \f
8401 /* Return true if OPNUM's MEM should be matched
8402 in movabs* patterns. */
8404 bool
8406 {
8418 }
8419 \f
8420 /* Initialize the table of extra 80387 mathematical constants. */
8422 static void
8424 {
8426 {
8432 };
8436 {
8438 /* Ensure each constant is rounded to XFmode precision. */
8441 }
8444 }
8446 /* Return non-zero if the constant is something that
8447 can be loaded with a special instruction. */
8449 int
8451 {
8454 REAL_VALUE_TYPE r;
8466 /* For XFmode constants, try to find a special 80387 instruction when
8467 optimizing for size or on those CPUs that benefit from them. */
8470 {
8479 }
8481 /* Load of the constant -0.0 or -1.0 will be split as
8482 fldz;fchs or fld1;fchs sequence. */
8489 }
8491 /* Return the opcode of the special instruction to be used to load
8492 the constant X. */
8496 {
8498 {
8518 }
8519 }
8521 /* Return the CONST_DOUBLE representing the 80387 constant that is
8522 loaded by the specified special instruction. The argument IDX
8523 matches the return value from standard_80387_constant_p. */
8525 rtx
8527 {
8534 {
8545 }
8548 XFmode);
8549 }
8551 /* Return 1 if X is all 0s and 2 if x is all 1s
8552 in supported SSE/AVX vector mode. */
8554 int
8556 {
8563 {
8578 }
8581 }
8583 /* Return the opcode of the special instruction to be used to load
8584 the constant X. */
8588 {
8590 {
8593 {
8610 }
8619 else
8624 }
8626 }
8628 /* Returns true if OP contains a symbol reference */
8630 bool
8632 {
8641 {
8643 {
8649 }
8653 }
8656 }
8658 /* Return true if it is appropriate to emit `ret' instructions in the
8659 body of a function. Do this only if the epilogue is simple, needing a
8660 couple of insns. Prior to reloading, we can't tell how many registers
8661 must be saved, so return false then. Return false if there is no frame
8662 marker to de-allocate. */
8664 bool
8666 {
8672 /* Don't allow more than 32k pop, since that's all we can do
8673 with one instruction. */
8680 }
8681 \f
8682 /* Value should be nonzero if functions must have frame pointers.
8683 Zero means the frame pointer need not be set up (and parms may
8684 be accessed via the stack pointer) in functions that seem suitable. */
8686 static bool
8688 {
8689 /* If we accessed previous frames, then the generated code expects
8690 to be able to access the saved ebp value in our frame. */
8694 /* Several x86 os'es need a frame pointer for other reasons,
8695 usually pertaining to setjmp. */
8699 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8703 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8704 allocation is 4GB. */
8708 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8709 turns off the frame pointer by default. Turn it back on now if
8710 we've not got a leaf function. */
8720 }
8722 /* Record that the current function accesses previous call frames. */
8724 void
8726 {
8728 }
8729 \f
8730 #ifndef USE_HIDDEN_LINKONCE
8731 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8732 # define USE_HIDDEN_LINKONCE 1
8733 # else
8734 # define USE_HIDDEN_LINKONCE 0
8735 # endif
8736 #endif
8740 /* Fills in the label name that should be used for a pc thunk for
8741 the given register. */
8743 static void
8745 {
8750 else
8752 }
8755 /* This function generates code for -fpic that loads %ebx with
8756 the return address of the caller and then returns. */
8758 static void
8760 {
8765 {
8767 tree decl;
8783 #if TARGET_MACHO
8785 {
8794 }
8795 else
8796 #endif
8798 {
8809 }
8810 else
8811 {
8814 }
8820 /* Make sure unwind info is emitted for the thunk if needed. */
8823 /* Pad stack IP move with 4 instructions (two NOPs count
8824 as one instruction). */
8826 {
8831 }
8842 }
8846 }
8848 /* Emit code for the SET_GOT patterns. */
8852 {
8858 {
8859 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8864 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8865 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8866 an unadorned address. */
8871 }
8876 {
8878 /* We don't need a pic base, we're not producing pic. */
8885 }
8886 else
8887 {
8896 #if TARGET_MACHO
8897 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
8898 This is what will be referenced by the Mach-O PIC subsystem. */
8902 /* When we are restoring the pic base at the site of a nonlocal label,
8903 and we decided to emit the pic base above, we will still output a
8904 local label used for calculating the correction offset (even though
8905 the offset will be 0 in that case). */
8909 #endif
8910 }
8916 }
8918 /* Generate an "push" pattern for input ARG. */
8920 static rtx
8922 {
8935 stack_pointer_rtx)),
8936 arg);
8937 }
8939 /* Generate an "pop" pattern for input ARG. */
8941 static rtx
8943 {
8948 arg,
8951 stack_pointer_rtx)));
8952 }
8954 /* Return >= 0 if there is an unused call-clobbered register available
8955 for the entire function. */
8957 static unsigned int
8959 {
8963 {
8965 /* Can't use the same register for both PIC and DRAP. */
8968 else
8973 }
8976 }
8978 /* Return TRUE if we need to save REGNO. */
8980 static bool
8982 {
8993 {
8996 {
9002 }
9003 }
9012 }
9014 /* Return number of saved general prupose registers. */
9016 static int
9018 {
9024 nregs ++;
9026 }
9028 /* Return number of saved SSE registrers. */
9030 static int
9032 {
9040 nregs ++;
9042 }
9044 /* Given FROM and TO register numbers, say whether this elimination is
9045 allowed. If stack alignment is needed, we can only replace argument
9046 pointer with hard frame pointer, or replace frame pointer with stack
9047 pointer. Otherwise, frame pointer elimination is automatically
9048 handled and all other eliminations are valid. */
9050 static bool
9052 {
9058 else
9060 }
9062 /* Return the offset between two registers, one to be eliminated, and the other
9063 its replacement, at the start of a routine. */
9065 HOST_WIDE_INT
9067 {
9076 else
9077 {
9085 }
9086 }
9088 /* In a dynamically-aligned function, we can't know the offset from
9089 stack pointer to frame pointer, so we must ensure that setjmp
9090 eliminates fp against the hard fp (%ebp) rather than trying to
9091 index from %esp up to the top of the frame across a gap that is
9092 of unknown (at compile-time) size. */
9093 static rtx
9095 {
9097 }
9099 /* When using -fsplit-stack, the allocation routines set a field in
9100 the TCB to the bottom of the stack plus this much space, measured
9101 in bytes. */
9103 #define SPLIT_STACK_AVAILABLE 256
9105 /* Fill structure ix86_frame about frame of currently computed function. */
9107 static void
9109 {
9111 HOST_WIDE_INT offset;
9114 HOST_WIDE_INT to_allocate;
9122 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9123 function prologues and leaf. */
9127 {
9132 }
9138 /* For SEH we have to limit the amount of code movement into the prologue.
9139 At present we do this via a BLOCKAGE, at which point there's very little
9140 scheduling that can be done, which means that there's very little point
9141 in doing anything except PUSHs. */
9145 /* During reload iteration the amount of registers saved can change.
9146 Recompute the value as needed. Do not recompute when amount of registers
9147 didn't change as reload does multiple calls to the function and does not
9148 expect the decision to change within single iteration. */
9151 {
9157 /* The fast prologue uses move instead of push to save registers. This
9158 is significantly longer, but also executes faster as modern hardware
9159 can execute the moves in parallel, but can't do that for push/pop.
9161 Be careful about choosing what prologue to emit: When function takes
9162 many instructions to execute we may use slow version as well as in
9163 case function is known to be outside hot spot (this is known with
9164 feedback only). Weight the size of function by number of registers
9165 to save as it is cheap to use one or two push instructions but very
9166 slow to use many of them. */
9170 || (flag_branch_probabilities
9173 else
9176 }
9178 frame->save_regs_using_mov
9180 /* If static stack checking is enabled and done with probes,
9181 the registers need to be saved before allocating the frame. */
9184 /* Skip return address. */
9187 /* Skip pushed static chain. */
9191 /* Skip saved base pointer. */
9196 /* The traditional frame pointer location is at the top of the frame. */
9199 /* Register save area */
9203 /* On SEH target, registers are pushed just before the frame pointer
9204 location. */
9208 /* Align and set SSE register save area. */
9210 {
9211 /* The only ABI that has saved SSE registers (Win64) also has a
9212 16-byte aligned default stack, and thus we don't need to be
9213 within the re-aligned local stack frame to save them. */
9217 }
9220 /* The re-aligned stack starts here. Values before this point are not
9221 directly comparable with values below this point. In order to make
9222 sure that no value happens to be the same before and after, force
9223 the alignment computation below to add a non-zero value. */
9227 /* Va-arg area */
9231 /* Align start of frame for local function. */
9240 /* Frame pointer points here. */
9245 /* Add outgoing arguments area. Can be skipped if we eliminated
9246 all the function calls as dead code.
9247 Skipping is however impossible when function calls alloca. Alloca
9248 expander assumes that last crtl->outgoing_args_size
9249 of stack frame are unused. */
9253 {
9256 }
9257 else
9260 /* Align stack boundary. Only needed if we're calling another function
9261 or using alloca. */
9266 /* We've reached end of stack frame. */
9269 /* Size prologue needs to allocate. */
9280 {
9286 }
9287 else
9291 /* The SEH frame pointer location is near the bottom of the frame.
9292 This is enforced by the fact that the difference between the
9293 stack pointer and the frame pointer is limited to 240 bytes in
9294 the unwind data structure. */
9296 {
9297 HOST_WIDE_INT diff;
9299 /* If we can leave the frame pointer where it is, do so. Also, returns
9300 the establisher frame for __builtin_frame_address (0). */
9305 {
9306 /* Ideally we'd determine what portion of the local stack frame
9307 (within the constraint of the lowest 240) is most heavily used.
9308 But without that complication, simply bias the frame pointer
9309 by 128 bytes so as to maximize the amount of the local stack
9310 frame that is addressable with 8-bit offsets. */
9312 }
9313 }
9314 }
9316 /* This is semi-inlined memory_address_length, but simplified
9317 since we know that we're always dealing with reg+offset, and
9318 to avoid having to create and discard all that rtl. */
9322 {
9326 {
9327 /* EBP and R13 cannot be encoded without an offset. */
9329 }
9333 /* ESP and R12 must be encoded with a SIB byte. */
9335 len++;
9338 }
9340 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9341 The valid base registers are taken from CFUN->MACHINE->FS. */
9343 static rtx
9345 {
9351 {
9352 /* Choose the base register most likely to allow the most scheduling
9353 opportunities. Generally FP is valid throughout the function,
9354 while DRAP must be reloaded within the epilogue. But choose either
9355 over the SP due to increased encoding size. */
9358 {
9361 }
9363 {
9366 }
9368 {
9371 }
9372 }
9373 else
9374 {
9375 HOST_WIDE_INT toffset;
9378 /* Choose the base register with the smallest address encoding.
9379 With a tie, choose FP > DRAP > SP. */
9381 {
9385 }
9387 {
9391 {
9395 }
9396 }
9398 {
9402 {
9406 }
9407 }
9408 }
9412 }
9414 /* Emit code to save registers in the prologue. */
9416 static void
9418 {
9420 rtx insn;
9424 {
9427 }
9428 }
9430 /* Emit a single register save at CFA - CFA_OFFSET. */
9432 static void
9434 HOST_WIDE_INT cfa_offset)
9435 {
9443 /* For SSE saves, we need to indicate the 128-bit alignment. */
9454 /* When saving registers into a re-aligned local stack frame, avoid
9455 any tricky guessing by dwarf2out. */
9457 {
9461 {
9462 /* A bit of a hack. We force the DRAP register to be saved in
9463 the re-aligned stack frame, which provides us with a copy
9464 of the CFA that will last past the prologue. Install it. */
9470 }
9471 else
9472 {
9473 /* The frame pointer is a stable reference within the
9474 aligned frame. Use it. */
9481 }
9482 }
9484 /* The memory may not be relative to the current CFA register,
9485 which means that we may need to generate a new pattern for
9486 use by the unwind info. */
9488 {
9493 }
9494 }
9496 /* Emit code to save registers using MOV insns.
9497 First register is stored at CFA - CFA_OFFSET. */
9498 static void
9500 {
9505 {
9508 }
9509 }
9511 /* Emit code to save SSE registers using MOV insns.
9512 First register is stored at CFA - CFA_OFFSET. */
9513 static void
9515 {
9520 {
9523 }
9524 }
9528 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9529 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9530 Don't add the note if the previously saved value will be left untouched
9531 within stack red-zone till return, as unwinders can find the same value
9532 in the register and on the stack. */
9534 static void
9536 {
9542 {
9545 }
9546 else
9547 queued_cfa_restores
9549 }
9551 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9553 static void
9555 {
9556 rtx last;
9560 ;
9565 }
9567 /* Expand prologue or epilogue stack adjustment.
9568 The pattern exist to put a dependency on all ebp-based memory accesses.
9569 STYLE should be negative if instructions should be marked as frame related,
9570 zero if %r11 register is live and cannot be freely used and positive
9571 otherwise. */
9573 static void
9576 {
9578 rtx insn;
9585 else
9586 {
9587 rtx tmp;
9588 /* r11 is used by indirect sibcall return as well, set before the
9589 epilogue and used after the epilogue. */
9592 else
9593 {
9597 }
9603 }
9610 {
9611 rtx r;
9621 }
9623 {
9626 {
9630 }
9631 }
9634 {
9639 {
9642 }
9644 {
9647 }
9648 else
9649 {
9650 /* Else there are two possibilities: SP itself, which we set
9651 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9652 taken care of this by hand along the eh_return path. */
9655 }
9659 }
9660 }
9662 /* Find an available register to be used as dynamic realign argument
9663 pointer regsiter. Such a register will be written in prologue and
9664 used in begin of body, so it must not be
9665 1. parameter passing register.
9666 2. GOT pointer.
9667 We reuse static-chain register if it is available. Otherwise, we
9668 use DI for i386 and R13 for x86-64. We chose R13 since it has
9669 shorter encoding.
9671 Return: the regno of chosen register. */
9673 static unsigned int
9675 {
9679 {
9680 /* Use R13 for nested function or function need static chain.
9681 Since function with tail call may use any caller-saved
9682 registers in epilogue, DRAP must not use caller-saved
9683 register in such case. */
9688 }
9689 else
9690 {
9691 /* Use DI for nested function or function need static chain.
9692 Since function with tail call may use any caller-saved
9693 registers in epilogue, DRAP must not use caller-saved
9694 register in such case. */
9698 /* Reuse static chain register if it isn't used for parameter
9699 passing. */
9701 {
9705 }
9707 }
9708 }
9710 /* Return minimum incoming stack alignment. */
9712 static unsigned int
9714 {
9717 /* Prefer the one specified at command line. */
9720 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9721 if -mstackrealign is used, it isn't used for sibcall check and
9722 estimated stack alignment is 128bit. */
9724 && !TARGET_64BIT
9725 && ix86_force_align_arg_pointer
9728 else
9731 /* Incoming stack alignment can be changed on individual functions
9732 via force_align_arg_pointer attribute. We use the smallest
9733 incoming stack boundary. */
9739 /* The incoming stack frame has to be aligned at least at
9740 parm_stack_boundary. */
9744 /* Stack at entrance of main is aligned by runtime. We use the
9745 smallest incoming stack boundary. */
9753 }
9755 /* Update incoming stack boundary and estimated stack alignment. */
9757 static void
9759 {
9760 ix86_incoming_stack_boundary
9763 /* x86_64 vararg needs 16byte stack alignment for register save
9764 area. */
9769 }
9771 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9772 needed or an rtx for DRAP otherwise. */
9774 static rtx
9776 {
9781 {
9782 /* Assign DRAP to vDRAP and returns vDRAP */
9784 rtx drap_vreg;
9785 rtx arg_ptr;
9798 {
9801 }
9803 }
9804 else
9806 }
9808 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9810 static rtx
9812 {
9814 }
9817 rtx reg;
9819 };
9821 /* Return a short-lived scratch register for use on function entry.
9822 In 32-bit mode, it is valid only after the registers are saved
9823 in the prologue. This register must be released by means of
9824 release_scratch_register_on_entry once it is dead. */
9826 static void
9828 {
9834 {
9835 /* We always use R11 in 64-bit mode. */
9837 }
9838 else
9839 {
9841 bool fastcall_p
9843 bool thiscall_p
9847 int drap_regno
9850 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9851 for the static chain register. */
9855 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9856 for the static chain register. */
9861 /* ecx is the static chain register. */
9863 && !static_chain_p
9868 /* esi is the static chain register. */
9874 else
9875 {
9878 }
9879 }
9883 {
9886 }
9887 }
9889 /* Release a scratch register obtained from the preceding function. */
9891 static void
9893 {
9895 {
9899 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9905 }
9906 }
9908 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9910 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9912 static void
9914 {
9915 /* We skip the probe for the first interval + a small dope of 4 words and
9916 probe that many bytes past the specified size to maintain a protection
9917 area at the botton of the stack. */
9921 /* See if we have a constant small number of probes to generate. If so,
9922 that's the easy case. The run-time loop is made up of 11 insns in the
9923 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9924 for n # of intervals. */
9926 {
9930 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9931 values of N from 1 until it exceeds SIZE. If only one probe is
9932 needed, this will not generate any code. Then adjust and probe
9933 to PROBE_INTERVAL + SIZE. */
9935 {
9937 {
9940 }
9941 else
9948 }
9952 else
9960 /* Adjust back to account for the additional first interval. */
9964 }
9966 /* Otherwise, do the same as above, but in a loop. Note that we must be
9967 extra careful with variables wrapping around because we might be at
9968 the very top (or the very bottom) of the address space and we have
9969 to be able to handle this case properly; in particular, we use an
9970 equality test for the loop condition. */
9971 else
9972 {
9973 HOST_WIDE_INT rounded_size;
9979 /* Step 1: round SIZE to the previous multiple of the interval. */
9984 /* Step 2: compute initial and final value of the loop counter. */
9986 /* SP = SP_0 + PROBE_INTERVAL. */
9991 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9995 stack_pointer_rtx)));
9998 /* Step 3: the loop
10000 while (SP != LAST_ADDR)
10001 {
10002 SP = SP + PROBE_INTERVAL
10003 probe at SP
10004 }
10006 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10007 values of N from 1 until it is equal to ROUNDED_SIZE. */
10012 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10013 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10016 {
10021 }
10023 /* Adjust back to account for the additional first interval. */
10029 }
10033 /* Even if the stack pointer isn't the CFA register, we need to correctly
10034 describe the adjustments made to it, in particular differentiate the
10035 frame-related ones from the frame-unrelated ones. */
10037 {
10050 }
10052 /* Make sure nothing is scheduled before we are done. */
10054 }
10056 /* Adjust the stack pointer up to REG while probing it. */
10060 {
10070 /* Jump to END_LAB if SP == LAST_ADDR. */
10078 /* SP = SP + PROBE_INTERVAL. */
10082 /* Probe at SP. */
10093 }
10095 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10096 inclusive. These are offsets from the current stack pointer. */
10098 static void
10100 {
10101 /* See if we have a constant small number of probes to generate. If so,
10102 that's the easy case. The run-time loop is made up of 7 insns in the
10103 generic case while the compile-time loop is made up of n insns for n #
10104 of intervals. */
10106 {
10107 HOST_WIDE_INT i;
10109 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10110 it exceeds SIZE. If only one probe is needed, this will not
10111 generate any code. Then probe at FIRST + SIZE. */
10118 }
10120 /* Otherwise, do the same as above, but in a loop. Note that we must be
10121 extra careful with variables wrapping around because we might be at
10122 the very top (or the very bottom) of the address space and we have
10123 to be able to handle this case properly; in particular, we use an
10124 equality test for the loop condition. */
10125 else
10126 {
10133 /* Step 1: round SIZE to the previous multiple of the interval. */
10138 /* Step 2: compute initial and final value of the loop counter. */
10140 /* TEST_OFFSET = FIRST. */
10143 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10147 /* Step 3: the loop
10149 while (TEST_ADDR != LAST_ADDR)
10150 {
10151 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10152 probe at TEST_ADDR
10153 }
10155 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10156 until it is equal to ROUNDED_SIZE. */
10161 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10162 that SIZE is equal to ROUNDED_SIZE. */
10167 stack_pointer_rtx,
10172 }
10174 /* Make sure nothing is scheduled before we are done. */
10176 }
10178 /* Probe a range of stack addresses from REG to END, inclusive. These are
10179 offsets from the current stack pointer. */
10183 {
10193 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10201 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10205 /* Probe at TEST_ADDR. */
10218 }
10220 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10221 to be generated in correct form. */
10222 static void
10224 {
10225 /* Check if stack realign is really needed after reload, and
10226 stores result in cfun */
10227 unsigned int incoming_stack_boundary
10236 {
10237 /* After stack_realign_needed is finalized, we can't no longer
10238 change it. */
10241 }
10243 /* If the only reason for frame_pointer_needed is that we conservatively
10244 assumed stack realignment might be needed, but in the end nothing that
10245 needed the stack alignment had been spilled, clear frame_pointer_needed
10246 and say we don't need stack realignment. */
10249 && frame_pointer_needed
10251 && flag_omit_frame_pointer
10253 && !ix86_current_function_calls_tls_descriptor
10262 {
10264 basic_block bb;
10271 HARD_FRAME_POINTER_REGNUM);
10273 {
10274 rtx insn;
10278 set_up_by_prologue))
10279 {
10283 }
10284 }
10298 }
10302 }
10304 /* Expand the prologue into a bunch of separate insns. */
10306 void
10308 {
10313 HOST_WIDE_INT allocate;
10319 /* DRAP should not coexist with stack_realign_fp */
10324 /* Initialize CFA state for before the prologue. */
10328 /* Track SP offset to the CFA. We continue tracking this after we've
10329 swapped the CFA register away from SP. In the case of re-alignment
10330 this is fudged; we're interested to offsets within the local frame. */
10337 {
10338 /* We should have already generated an error for any use of
10339 ms_hook on a nested function. */
10342 /* Check if profiling is active and we shall use profiling before
10343 prologue variant. If so sorry. */
10348 /* In ix86_asm_output_function_label we emitted:
10349 8b ff movl.s %edi,%edi
10350 55 push %ebp
10351 8b ec movl.s %esp,%ebp
10353 This matches the hookable function prologue in Win32 API
10354 functions in Microsoft Windows XP Service Pack 2 and newer.
10355 Wine uses this to enable Windows apps to hook the Win32 API
10356 functions provided by Wine.
10358 What that means is that we've already set up the frame pointer. */
10362 {
10365 /* We've decided to use the frame pointer already set up.
10366 Describe this to the unwinder by pretending that both
10367 push and mov insns happen right here.
10369 Putting the unwind info here at the end of the ms_hook
10370 is done so that we can make absolutely certain we get
10371 the required byte sequence at the start of the function,
10372 rather than relying on an assembler that can produce
10373 the exact encoding required.
10375 However it does mean (in the unpatched case) that we have
10376 a 1 insn window where the asynchronous unwind info is
10377 incorrect. However, if we placed the unwind info at
10378 its correct location we would have incorrect unwind info
10379 in the patched case. Which is probably all moot since
10380 I don't expect Wine generates dwarf2 unwind info for the
10381 system libraries that use this feature. */
10387 stack_pointer_rtx);
10395 /* Note that gen_push incremented m->fs.cfa_offset, even
10396 though we didn't emit the push insn here. */
10400 }
10401 else
10402 {
10403 /* The frame pointer is not needed so pop %ebp again.
10404 This leaves us with a pristine state. */
10406 }
10407 }
10409 /* The first insn of a function that accepts its static chain on the
10410 stack is to push the register that would be filled in by a direct
10411 call. This insn will be skipped by the trampoline. */
10413 {
10417 /* We don't want to interpret this push insn as a register save,
10418 only as a stack adjustment. The real copy of the register as
10419 a save will be done later, if needed. */
10424 }
10426 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10427 of DRAP is needed and stack realignment is really needed after reload */
10429 {
10432 /* Only need to push parameter pointer reg if it is caller saved. */
10434 {
10435 /* Push arg pointer reg */
10438 }
10440 /* Grab the argument pointer. */
10447 /* Align the stack. */
10449 stack_pointer_rtx,
10453 /* Replicate the return address on the stack so that return
10454 address can be reached via (argp - 1) slot. This is needed
10455 to implement macro RETURN_ADDR_RTX and intrinsic function
10456 expand_builtin_return_addr etc. */
10462 /* For the purposes of frame and register save area addressing,
10463 we've started over with a new frame. */
10466 }
10472 {
10473 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10474 slower on all targets. Also sdb doesn't like it. */
10478 /* Push registers now, before setting the frame pointer
10479 on SEH target. */
10481 && TARGET_SEH
10483 {
10487 }
10490 {
10498 }
10499 }
10502 {
10503 /* If saving registers via PUSH, do so now. */
10505 {
10509 }
10511 /* When using red zone we may start register saving before allocating
10512 the stack frame saving one cycle of the prologue. However, avoid
10513 doing this if we have to probe the stack; at least on x86_64 the
10514 stack probe can turn into a call that clobbers a red zone location. */
10516 && (! TARGET_STACK_PROBE
10518 {
10521 }
10522 }
10525 {
10529 /* The computation of the size of the re-aligned stack frame means
10530 that we must allocate the size of the register save area before
10531 performing the actual alignment. Otherwise we cannot guarantee
10532 that there's enough storage above the realignment point. */
10539 /* Align the stack. */
10541 stack_pointer_rtx,
10544 /* For the purposes of register save area addressing, the stack
10545 pointer is no longer valid. As for the value of sp_offset,
10546 see ix86_compute_frame_layout, which we need to match in order
10547 to pass verification of stack_pointer_offset at the end. */
10550 }
10555 {
10556 /* We start to count from ARG_POINTER. */
10559 /* If it was realigned, take into account the fake frame. */
10561 {
10568 /* This over-estimates by 1 minimal-stack-alignment-unit but
10569 mitigates that by counting in the new return address slot. */
10570 current_function_dynamic_stack_size
10572 }
10575 }
10577 /* On SEH target with very large frame size, allocate an area to save
10578 SSE registers (as the very large allocation won't be described). */
10582 {
10583 HOST_WIDE_INT sse_size =
10588 /* No need to do stack checking as the area will be immediately
10589 written. */
10596 }
10598 /* The stack has already been decremented by the instruction calling us
10599 so probe if the size is non-negative to preserve the protection area. */
10601 {
10602 /* We expect the registers to be saved when probes are used. */
10606 {
10609 }
10610 else
10611 {
10619 else
10621 }
10622 }
10625 ;
10628 {
10632 }
10633 else
10634 {
10647 /* Note that SEH directives need to continue tracking the stack
10648 pointer even after the frame pointer has been set up. */
10650 {
10654 {
10658 }
10659 }
10662 {
10667 {
10671 }
10672 }
10677 /* Use the fact that AX still contains ALLOCATE. */
10679 ? gen_pro_epilogue_adjust_stack_di_sub
10686 {
10694 }
10698 {
10705 }
10707 {
10712 }
10713 }
10716 /* If we havn't already set up the frame pointer, do so now. */
10718 {
10730 }
10738 /* We don't use pic-register for pe-coff target. */
10740 && !TARGET_PECOFF
10743 {
10750 }
10753 {
10755 {
10757 {
10767 label));
10771 }
10772 else
10774 }
10775 else
10776 {
10780 }
10781 }
10783 /* In the pic_reg_used case, make sure that the got load isn't deleted
10784 when mcount needs it. Blockage to avoid call movement across mcount
10785 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10786 note. */
10791 {
10792 /* vDRAP is setup but after reload it turns out stack realign
10793 isn't necessary, here we will emit prologue to setup DRAP
10794 without stack realign adjustment */
10797 }
10799 /* Prevent instructions from being scheduled into register save push
10800 sequence when access to the redzone area is done through frame pointer.
10801 The offset between the frame pointer and the stack pointer is calculated
10802 relative to the value of the stack pointer at the end of the function
10803 prologue, and moving instructions that access redzone area via frame
10804 pointer inside push sequence violates this assumption. */
10808 /* Emit cld instruction if stringops are used in the function. */
10812 /* SEH requires that the prologue end within 256 bytes of the start of
10813 the function. Prevent instruction schedules that would extend that.
10814 Further, prevent alloca modifications to the stack pointer from being
10815 combined with prologue modifications. */
10818 }
10820 /* Emit code to restore REG using a POP insn. */
10822 static void
10824 {
10833 {
10834 /* Previously we'd represented the CFA as an expression
10835 like *(%ebp - 8). We've just popped that value from
10836 the stack, which means we need to reset the CFA to
10837 the drap register. This will remain until we restore
10838 the stack pointer. */
10842 /* This means that the DRAP register is valid for addressing too. */
10845 }
10848 {
10855 }
10857 /* When the frame pointer is the CFA, and we pop it, we are
10858 swapping back to the stack pointer as the CFA. This happens
10859 for stack frames that don't allocate other data, so we assume
10860 the stack pointer is now pointing at the return address, i.e.
10861 the function entry state, which makes the offset be 1 word. */
10863 {
10866 {
10874 }
10875 }
10876 }
10878 /* Emit code to restore saved registers using POP insns. */
10880 static void
10882 {
10888 }
10890 /* Emit code and notes for the LEAVE instruction. */
10892 static void
10894 {
10906 {
10914 }
10917 }
10919 /* Emit code to restore saved registers using MOV insns.
10920 First register is restored from CFA - CFA_OFFSET. */
10921 static void
10924 {
10930 {
10939 {
10940 /* Previously we'd represented the CFA as an expression
10941 like *(%ebp - 8). We've just popped that value from
10942 the stack, which means we need to reset the CFA to
10943 the drap register. This will remain until we restore
10944 the stack pointer. */
10948 /* This means that the DRAP register is valid for addressing. */
10950 }
10951 else
10955 }
10956 }
10958 /* Emit code to restore saved registers using MOV insns.
10959 First register is restored from CFA - CFA_OFFSET. */
10960 static void
10963 {
10968 {
10970 rtx mem;
10980 }
10981 }
10983 /* Restore function stack, frame, and registers. */
10985 void
10987 {
11003 /* The FP must be valid if the frame pointer is present. */
11008 /* We must have *some* valid pointer to the stack frame. */
11011 /* The DRAP is never valid at this point. */
11014 /* See the comment about red zone and frame
11015 pointer usage in ix86_expand_prologue. */
11022 /* Determine the CFA offset of the end of the red-zone. */
11025 {
11026 /* The red-zone begins below the return address. */
11029 /* When the register save area is in the aligned portion of
11030 the stack, determine the maximum runtime displacement that
11031 matches up with the aligned frame. */
11035 }
11037 /* Special care must be taken for the normal return case of a function
11038 using eh_return: the eax and edx registers are marked as saved, but
11039 not restored along this path. Adjust the save location to match. */
11043 /* EH_RETURN requires the use of moves to function properly. */
11046 /* SEH requires the use of pops to identify the epilogue. */
11049 /* If we're only restoring one register and sp is not valid then
11050 using a move instruction to restore the register since it's
11051 less work than reloading sp and popping the register. */
11064 && TARGET_USE_LEAVE
11068 else
11072 {
11073 /* Ensure that the entire register save area is addressable via
11074 the stack pointer, if we will restore via sp. */
11079 {
11083 style,
11085 }
11086 }
11088 /* If there are any SSE registers to restore, then we have to do it
11089 via moves, since there's obviously no pop for SSE regs. */
11095 {
11096 rtx t;
11101 /* eh_return epilogues need %ecx added to the stack pointer. */
11103 {
11106 /* Stack align doesn't work with eh_return. */
11108 /* Neither does regparm nested functions. */
11112 {
11120 /* Note that we use SA as a temporary CFA, as the return
11121 address is at the proper place relative to it. We
11122 pretend this happens at the FP restore insn because
11123 prior to this insn the FP would be stored at the wrong
11124 offset relative to SA, and after this insn we have no
11125 other reasonable register to use for the CFA. We don't
11126 bother resetting the CFA to the SP for the duration of
11127 the return insn. */
11140 }
11141 else
11142 {
11150 {
11154 UNITS_PER_WORD));
11156 }
11157 }
11160 }
11161 }
11162 else
11163 {
11164 /* SEH requires that the function end with (1) a stack adjustment
11165 if necessary, (2) a sequence of pops, and (3) a return or
11166 jump instruction. Prevent insns from the function body from
11167 being scheduled into this sequence. */
11169 {
11170 /* Prevent a catch region from being adjacent to the standard
11171 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11172 several other flags that would be interesting to test are
11173 not yet set up. */
11176 else
11178 }
11180 /* First step is to deallocate the stack frame so that we can
11181 pop the registers. Also do it on SEH target for very large
11182 frame as the emitted instructions aren't allowed by the ABI in
11183 epilogues. */
11185 || (TARGET_SEH
11188 {
11193 }
11195 {
11199 style,
11201 }
11204 }
11206 /* If we used a stack pointer and haven't already got rid of it,
11207 then do so now. */
11209 {
11210 /* If the stack pointer is valid and pointing at the frame
11211 pointer store address, then we only need a pop. */
11214 /* Leave results in shorter dependency chains on CPUs that are
11215 able to grok it fast. */
11220 else
11221 {
11223 hard_frame_pointer_rtx,
11226 }
11227 }
11230 {
11232 rtx insn;
11258 }
11260 /* At this point the stack pointer must be valid, and we must have
11261 restored all of the registers. We may not have deallocated the
11262 entire stack frame. We've delayed this until now because it may
11263 be possible to merge the local stack deallocation with the
11264 deallocation forced by ix86_static_chain_on_stack. */
11269 {
11273 }
11274 else
11277 /* Sibcall epilogues don't want a return instruction. */
11279 {
11282 }
11285 {
11288 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11289 address, do explicit add, and jump indirectly to the caller. */
11292 {
11294 rtx insn;
11296 /* There is no "pascal" calling convention in any 64bit ABI. */
11312 }
11313 else
11315 }
11316 else
11319 /* Restore the state back to the state from the prologue,
11320 so that it's correct for the next epilogue. */
11322 }
11324 /* Reset from the function's potential modifications. */
11326 static void
11328 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11329 {
11332 #if TARGET_MACHO
11333 /* Mach-O doesn't support labels at the end of objects, so if
11334 it looks like we might want one, insert a NOP. */
11335 {
11341 {
11342 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11343 notes only, instead set their CODE_LABEL_NUMBER to -1,
11344 otherwise there would be code generation differences
11345 in between -g and -g0. */
11349 }
11359 }
11360 #endif
11362 }
11364 /* Return a scratch register to use in the split stack prologue. The
11365 split stack prologue is used for -fsplit-stack. It is the first
11366 instructions in the function, even before the regular prologue.
11367 The scratch register can be any caller-saved register which is not
11368 used for parameters or for the static chain. */
11370 static unsigned int
11372 {
11375 else
11376 {
11389 {
11391 {
11395 }
11397 }
11399 {
11403 }
11405 {
11408 else
11409 {
11411 {
11415 }
11417 }
11418 }
11419 else
11420 {
11421 /* FIXME: We could make this work by pushing a register
11422 around the addition and comparison. */
11425 }
11426 }
11427 }
11429 /* A SYMBOL_REF for the function which allocates new stackspace for
11430 -fsplit-stack. */
11434 /* A SYMBOL_REF for the more stack function when using the large
11435 model. */
11439 /* Handle -fsplit-stack. These are the first instructions in the
11440 function, even before the regular prologue. */
11442 void
11444 {
11446 HOST_WIDE_INT allocate;
11451 rtx fn;
11459 /* This is the label we will branch to if we have enough stack
11460 space. We expect the basic block reordering pass to reverse this
11461 branch if optimizing, so that we branch in the unlikely case. */
11464 /* We need to compare the stack pointer minus the frame size with
11465 the stack boundary in the TCB. The stack boundary always gives
11466 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11467 can compare directly. Otherwise we need to do an addition. */
11470 UNSPEC_STACK_CHECK);
11475 else
11476 {
11478 rtx offset;
11480 /* We need a scratch register to hold the stack pointer minus
11481 the required frame size. Since this is the very start of the
11482 function, the scratch register can be any caller-saved
11483 register which is not used for parameters. */
11490 {
11491 /* We don't use ix86_gen_add3 in this case because it will
11492 want to split to lea, but when not optimizing the insn
11493 will not be split after this point. */
11496 offset)));
11497 }
11498 else
11499 {
11502 stack_pointer_rtx));
11503 }
11505 }
11511 /* Mark the jump as very likely to be taken. */
11519 /* Get more stack space. We pass in the desired stack space and the
11520 size of the arguments to copy to the new stack. In 32-bit mode
11521 we push the parameters; __morestack will return on a new stack
11522 anyhow. In 64-bit mode we pass the parameters in r10 and
11523 r11. */
11528 {
11534 /* If this function uses a static chain, it will be in %r10.
11535 Preserve it across the call to __morestack. */
11537 {
11538 rtx rax;
11543 }
11547 {
11548 HOST_WIDE_INT argval;
11551 /* When using the large model we need to load the address
11552 into a register, and we've run out of registers. So we
11553 switch to a different calling convention, and we call a
11554 different function: __morestack_large. We pass the
11555 argument size in the upper 32 bits of r10 and pass the
11556 frame size in the lower 32 bits. */
11561 split_stack_fn_large =
11565 {
11575 UNSPEC_GOT);
11581 }
11582 else
11589 }
11590 else
11591 {
11595 }
11598 }
11599 else
11600 {
11603 }
11609 /* In order to make call/return prediction work right, we now need
11610 to execute a return instruction. See
11611 libgcc/config/i386/morestack.S for the details on how this works.
11613 For flow purposes gcc must not see this as a return
11614 instruction--we need control flow to continue at the subsequent
11615 label. Therefore, we use an unspec. */
11619 /* If we are in 64-bit mode and this function uses a static chain,
11620 we saved %r10 in %rax before calling _morestack. */
11625 /* If this function calls va_start, we need to store a pointer to
11626 the arguments on the old stack, because they may not have been
11627 all copied to the new stack. At this point the old stack can be
11628 found at the frame pointer value used by __morestack, because
11629 __morestack has set that up before calling back to us. Here we
11630 store that pointer in a scratch register, and in
11631 ix86_expand_prologue we store the scratch register in a stack
11632 slot. */
11634 {
11636 rtx frame_reg;
11643 /* 64-bit:
11644 fp -> old fp value
11645 return address within this function
11646 return address of caller of this function
11647 stack arguments
11648 So we add three words to get to the stack arguments.
11650 32-bit:
11651 fp -> old fp value
11652 return address within this function
11653 first argument to __morestack
11654 second argument to __morestack
11655 return address of caller of this function
11656 stack arguments
11657 So we add five words to get to the stack arguments.
11658 */
11669 }
11674 /* If this function calls va_start, we now have to set the scratch
11675 register for the case where we do not call __morestack. In this
11676 case we need to set it based on the stack pointer. */
11678 {
11685 }
11686 }
11688 /* We may have to tell the dataflow pass that the split stack prologue
11689 is initializing a scratch register. */
11691 static void
11693 {
11695 {
11698 }
11699 }
11700 \f
11701 /* Determine if op is suitable SUBREG RTX for address. */
11703 static bool
11705 {
11716 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11717 failures when the register is one word out of a two word structure. */
11721 /* Allow only SUBREGs of non-eliminable hard registers. */
11723 }
11725 /* Extract the parts of an RTL expression that is a valid memory address
11726 for an instruction. Return 0 if the structure of the address is
11727 grossly off. Return -1 if the address contains ASHIFT, so it is not
11728 strictly valid, but still used for computing length of lea instruction. */
11730 int
11732 {
11737 rtx tmp;
11741 /* Allow zero-extended SImode addresses,
11742 they will be emitted with addr32 prefix. */
11744 {
11747 {
11751 }
11754 {
11761 }
11762 }
11764 /* Allow SImode subregs of DImode addresses,
11765 they will be emitted with addr32 prefix. */
11767 {
11770 {
11774 }
11775 }
11780 {
11783 else
11785 }
11787 {
11792 do
11793 {
11798 }
11805 {
11808 {
11833 /* FALLTHRU */
11837 && TARGET_TLS_DIRECT_SEG_REFS
11840 else
11847 /* FALLTHRU */
11854 else
11869 }
11870 }
11871 }
11873 {
11876 }
11878 {
11879 /* We're called for lea too, which implements ashift on occasion. */
11889 }
11891 {
11895 /* Constant addresses are sign extended to 64bit, we have to
11896 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11902 }
11903 else
11907 {
11909 ;
11912 ;
11913 else
11915 }
11917 /* Address override works only on the (%reg) part of %fs:(%reg). */
11923 /* Extract the integral value of scale. */
11925 {
11929 }
11934 /* Avoid useless 0 displacement. */
11938 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11943 {
11944 rtx tmp;
11947 }
11949 /* Special case: %ebp cannot be encoded as a base without a displacement.
11950 Similarly %r13. */
11952 && base_reg
11961 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11962 Avoid this by transforming to [%esi+0].
11963 Reload calls address legitimization without cfun defined, so we need
11964 to test cfun for being non-NULL. */
11970 /* Special case: encode reg+reg instead of reg*2. */
11974 /* Special case: scaling cannot be encoded without base or displacement. */
11985 }
11986 \f
11987 /* Return cost of the memory address x.
11988 For i386, it is better to use a complex address than let gcc copy
11989 the address into a reg and make a new pseudo. But not if the address
11990 requires to two regs - that would mean more pseudos with longer
11991 lifetimes. */
11992 static int
11994 addr_space_t as ATTRIBUTE_UNUSED,
11996 {
12008 /* Attempt to minimize number of registers in the address. */
12014 cost++;
12021 cost++;
12023 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12024 since it's predecode logic can't detect the length of instructions
12025 and it degenerates to vector decoded. Increase cost of such
12026 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12027 to split such addresses or even refuse such addresses at all.
12029 Following addressing modes are affected:
12030 [base+scale*index]
12031 [scale*index+disp]
12032 [base+index]
12034 The first and last case may be avoidable by explicitly coding the zero in
12035 memory address, but I don't have AMD-K6 machine handy to check this
12036 theory. */
12045 }
12046 \f
12047 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12048 this is used for to form addresses to local data when -fPIC is in
12049 use. */
12051 static bool
12053 {
12056 }
12058 /* Determine if a given RTX is a valid constant. We already know this
12059 satisfies CONSTANT_P. */
12061 static bool
12063 {
12065 {
12070 {
12074 }
12079 /* Only some unspecs are valid as "constants". */
12082 {
12098 }
12100 /* We must have drilled down to a symbol. */
12105 /* FALLTHRU */
12108 /* TLS symbols are never valid. */
12112 /* DLLIMPORT symbols are never valid. */
12117 #if TARGET_MACHO
12118 /* mdynamic-no-pic */
12121 #endif
12137 }
12139 /* Otherwise we handle everything else in the move patterns. */
12141 }
12143 /* Determine if it's legal to put X into the constant pool. This
12144 is not possible for the address of thread-local symbols, which
12145 is checked above. */
12147 static bool
12149 {
12150 /* We can always put integral constants and vectors in memory. */
12152 {
12160 }
12162 }
12164 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12165 otherwise zero. */
12167 static bool
12169 {
12175 }
12178 /* Nonzero if the constant value X is a legitimate general operand
12179 when generating PIC code. It is given that flag_pic is on and
12180 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12182 bool
12184 {
12185 rtx inner;
12188 {
12195 /* Only some unspecs are valid as "constants". */
12198 {
12211 }
12212 /* FALLTHRU */
12220 }
12221 }
12223 /* Determine if a given CONST RTX is a valid memory displacement
12224 in PIC mode. */
12226 bool
12228 {
12231 /* In 64bit mode we can allow direct addresses of symbols and labels
12232 when they are not dynamic symbols. */
12234 {
12238 {
12262 /* FALLTHRU */
12265 /* TLS references should always be enclosed in UNSPEC.
12266 The dllimported symbol needs always to be resolved. */
12272 {
12280 /* Function-symbols need to be resolved only for
12281 large-model.
12282 For the small-model we don't need to resolve anything
12283 here. */
12288 /* Non-external symbols don't need to be resolved for
12289 large, and medium-model. */
12294 }
12303 }
12304 }
12310 {
12311 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12312 of GOT tables. We should not need these anyway. */
12324 }
12328 {
12333 }
12342 {
12346 /* We need to check for both symbols and labels because VxWorks loads
12347 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12348 details. */
12352 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12353 While ABI specify also 32bit relocation but we don't produce it in
12354 small PIC model at all. */
12376 }
12379 }
12381 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12382 replace the input X, or the original X if no replacement is called for.
12383 The output parameter *WIN is 1 if the calling macro should goto WIN,
12384 0 if it should not. */
12386 bool
12391 {
12392 /* Reload can generate:
12394 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12395 (reg:DI 97))
12396 (reg:DI 2 cx))
12398 This RTX is rejected from ix86_legitimate_address_p due to
12399 non-strictness of base register 97. Following this rejection,
12400 reload pushes all three components into separate registers,
12401 creating invalid memory address RTX.
12403 Following code reloads only the invalid part of the
12404 memory address RTX. */
12410 {
12416 {
12421 }
12425 {
12430 }
12434 }
12437 }
12439 /* Recognizes RTL expressions that are valid memory addresses for an
12440 instruction. The MODE argument is the machine mode for the MEM
12441 expression that wants to use this address.
12443 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12444 convert common non-canonical forms to canonical form so that they will
12445 be recognized. */
12447 static bool
12450 {
12453 HOST_WIDE_INT scale;
12456 /* Decomposition failed. */
12464 /* Validate base register. */
12466 {
12467 rtx reg;
12473 else
12474 /* Base is not a register. */
12482 /* Base is not valid. */
12484 }
12486 /* Validate index register. */
12488 {
12489 rtx reg;
12495 else
12496 /* Index is not a register. */
12504 /* Index is not valid. */
12506 }
12508 /* Index and base should have the same mode. */
12513 /* Validate scale factor. */
12515 {
12517 /* Scale without index. */
12521 /* Scale is not a valid multiplier. */
12523 }
12525 /* Validate displacement. */
12527 {
12532 {
12533 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12534 used. While ABI specify also 32bit relocations, we don't produce
12535 them at all and use IP relative instead. */
12542 /* 64bit address unspec. */
12562 /* Invalid address unspec. */
12564 }
12567 && (flag_pic
12568 || (TARGET_MACHO
12569 #if TARGET_MACHO
12570 && MACHOPIC_INDIRECT
12572 #endif
12573 )))
12574 {
12576 is_legitimate_pic:
12578 {
12579 /* foo@dtpoff(%rX) is ok. */
12586 /* Non-constant pic memory reference. */
12588 }
12591 /* Displacement is an invalid pic construct. */
12593 #if TARGET_MACHO
12596 /* displacment must be referenced via non_lazy_pointer */
12598 #endif
12600 /* This code used to verify that a symbolic pic displacement
12601 includes the pic_offset_table_rtx register.
12603 While this is good idea, unfortunately these constructs may
12604 be created by "adds using lea" optimization for incorrect
12605 code like:
12607 int a;
12608 int foo(int i)
12609 {
12610 return *(&a+i);
12611 }
12613 This code is nonsensical, but results in addressing
12614 GOT table with pic_offset_table_rtx base. We can't
12615 just refuse it easily, since it gets matched by
12616 "addsi3" pattern, that later gets split to lea in the
12617 case output register differs from input. While this
12618 can be handled by separate addsi pattern for this case
12619 that never results in lea, this seems to be easier and
12620 correct fix for crash to disable this test. */
12621 }
12628 /* Displacement is not constant. */
12632 /* Displacement is out of range. */
12634 }
12636 /* Everything looks valid. */
12638 }
12640 /* Determine if a given RTX is a valid constant address. */
12642 bool
12644 {
12646 }
12647 \f
12648 /* Return a unique alias set for the GOT. */
12650 static alias_set_type
12652 {
12657 }
12659 /* Return a legitimate reference for ORIG (an address) using the
12660 register REG. If REG is 0, a new pseudo is generated.
12662 There are two types of references that must be handled:
12664 1. Global data references must load the address from the GOT, via
12665 the PIC reg. An insn is emitted to do this load, and the reg is
12666 returned.
12668 2. Static data references, constant pool addresses, and code labels
12669 compute the address as an offset from the GOT, whose base is in
12670 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12671 differentiate them from global data objects. The returned
12672 address is the PIC reg + an unspec constant.
12674 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12675 reg also appears in the address. */
12677 static rtx
12679 {
12683 #if TARGET_MACHO
12685 {
12688 /* Use the generic Mach-O PIC machinery. */
12690 }
12691 #endif
12694 {
12698 }
12704 {
12705 rtx tmpreg;
12706 /* This symbol may be referenced via a displacement from the PIC
12707 base address (@GOTOFF). */
12714 {
12716 UNSPEC_GOTOFF);
12718 }
12719 else
12724 else
12729 {
12733 }
12734 else
12736 }
12738 {
12739 /* This symbol may be referenced via a displacement from the PIC
12740 base address (@GOTOFF). */
12747 {
12749 UNSPEC_GOTOFF);
12751 }
12752 else
12758 {
12761 }
12762 }
12764 /* We can't use @GOTOFF for text labels on VxWorks;
12765 see gotoff_operand. */
12767 {
12772 /* For x64 PE-COFF there is no GOT table. So we use address
12773 directly. */
12775 {
12783 }
12785 {
12793 /* Use directly gen_movsi, otherwise the address is loaded
12794 into register for CSE. We don't want to CSE this addresses,
12795 instead we CSE addresses from the GOT table, so skip this. */
12798 }
12799 else
12800 {
12801 /* This symbol must be referenced via a load from the
12802 Global Offset Table (@GOT). */
12818 }
12819 }
12820 else
12821 {
12824 {
12826 {
12829 }
12830 else
12832 }
12834 {
12837 /* We must match stuff we generate before. Assume the only
12838 unspecs that can get here are ours. Not that we could do
12839 anything with them anyway.... */
12845 }
12847 {
12850 /* Check first to see if this is a constant offset from a @GOTOFF
12851 symbol reference. */
12854 {
12856 {
12860 UNSPEC_GOTOFF);
12866 {
12869 }
12870 }
12871 else
12872 {
12875 {
12879 }
12880 }
12881 }
12882 else
12883 {
12886 new_rtx
12890 {
12893 {
12896 new_rtx
12898 }
12899 else
12901 }
12902 else
12903 {
12906 {
12909 }
12911 }
12912 }
12913 }
12914 }
12916 }
12917 \f
12918 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12920 static rtx
12922 {
12926 {
12931 }
12937 }
12939 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12943 static rtx
12945 {
12947 {
12953 }
12956 {
12958 UNSPEC_PLTOFF);
12961 }
12964 }
12966 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12970 rtx
12972 {
12974 {
12975 ix86_tls_module_base_symbol
12980 }
12983 }
12985 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12986 false if we expect this to be used for a memory address and true if
12987 we expect to load the address into a register. */
12989 static rtx
12991 {
12998 {
13003 {
13006 else
13007 {
13010 }
13011 }
13014 {
13017 else
13027 }
13028 else
13029 {
13033 {
13035 rtx insns;
13038 emit_call_insn
13048 }
13049 else
13051 }
13058 {
13061 else
13062 {
13065 }
13066 }
13069 {
13074 else
13080 }
13081 else
13082 {
13086 {
13091 emit_call_insn
13096 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13097 share the LD_BASE result with other LD model accesses. */
13099 UNSPEC_TLS_LD_BASE);
13103 }
13104 else
13106 }
13114 {
13121 }
13126 {
13128 {
13129 /* The Sun linker took the AMD64 TLS spec literally
13130 and can only handle %rax as destination of the
13131 initial executable code sequence. */
13136 }
13138 /* Generate DImode references to avoid %fs:(%reg32)
13139 problems and linker IE->LE relaxation bug. */
13143 }
13145 {
13150 }
13152 {
13156 }
13157 else
13158 {
13161 }
13171 {
13176 }
13177 else
13178 {
13182 }
13192 {
13196 }
13197 else
13198 {
13202 }
13207 }
13210 }
13212 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13213 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13214 unique refptr-DECL symbol corresponding to symbol DECL. */
13217 htab_t dllimport_map;
13219 static tree
13221 {
13228 tree to;
13229 rtx rtl;
13256 else
13269 {
13271 #ifdef SUB_TARGET_RECORD_STUB
13273 #endif
13274 }
13283 }
13285 /* Expand SYMBOL into its corresponding far-addresse symbol.
13286 WANT_REG is true if we require the result be a register. */
13288 static rtx
13290 {
13291 tree imp_decl;
13292 rtx x;
13301 }
13303 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13304 true if we require the result be a register. */
13306 static rtx
13308 {
13309 tree imp_decl;
13310 rtx x;
13319 }
13321 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13322 is true if we require the result be a register. */
13324 static rtx
13326 {
13331 {
13338 {
13341 }
13342 }
13358 {
13361 }
13363 }
13365 /* Try machine-dependent ways of modifying an illegitimate address
13366 to be legitimate. If we find one, return the new, valid address.
13367 This macro is used in only one place: `memory_address' in explow.c.
13369 OLDX is the address as it was before break_out_memory_refs was called.
13370 In some cases it is useful to look at this to decide what needs to be done.
13372 It is always safe for this macro to do nothing. It exists to recognize
13373 opportunities to optimize the output.
13375 For the 80386, we handle X+REG by loading X into a register R and
13376 using R+REG. R will go in a general reg and indexing will be used.
13377 However, if REG is a broken-out memory address or multiplication,
13378 nothing needs to be done because REG can certainly go in a general reg.
13380 When -fpic is used, special handling is needed for symbolic references.
13381 See comments by legitimize_pic_address in i386.c for details. */
13383 static rtx
13386 {
13397 {
13401 }
13404 {
13408 }
13413 #if TARGET_MACHO
13416 #endif
13418 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13422 {
13427 }
13430 {
13431 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13436 {
13442 }
13447 {
13453 }
13455 /* Put multiply first if it isn't already. */
13457 {
13462 }
13464 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13465 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13466 created by virtual register instantiation, register elimination, and
13467 similar optimizations. */
13469 {
13475 }
13477 /* Canonicalize
13478 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13479 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13484 {
13485 rtx constant;
13489 {
13492 }
13494 {
13497 }
13498 else
13502 {
13509 }
13510 }
13516 {
13519 }
13522 {
13525 }
13533 {
13536 }
13542 {
13546 {
13549 }
13553 }
13556 {
13560 {
13563 }
13567 }
13568 }
13571 }
13572 \f
13573 /* Print an integer constant expression in assembler syntax. Addition
13574 and subtraction are the only arithmetic that may appear in these
13575 expressions. FILE is the stdio stream to write to, X is the rtx, and
13576 CODE is the operand print code from the output string. */
13578 static void
13580 {
13584 {
13593 else
13594 {
13597 /* Mark the decl as referenced so that cgraph will
13598 output the function. */
13602 #if TARGET_MACHO
13606 #endif
13608 }
13616 /* FALLTHRU */
13627 /* This used to output parentheses around the expression,
13628 but that does not work on the 386 (either ATT or BSD assembler). */
13634 {
13635 /* We can use %d if the number is <32 bits and positive. */
13640 else
13642 }
13643 else
13644 /* We can't handle floating point constants;
13645 TARGET_PRINT_OPERAND must handle them. */
13650 /* Some assemblers need integer constants to appear first. */
13652 {
13656 }
13657 else
13658 {
13663 }
13678 {
13682 }
13687 {
13706 /* FIXME: This might be @TPOFF in Sun ld too. */
13715 else
13725 else
13731 #if TARGET_MACHO
13736 #endif
13740 }
13745 }
13746 }
13748 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13749 We need to emit DTP-relative relocations. */
13751 static void ATTRIBUTE_UNUSED
13753 {
13758 {
13766 }
13767 }
13769 /* Return true if X is a representation of the PIC register. This copes
13770 with calls from ix86_find_base_term, where the register might have
13771 been replaced by a cselib value. */
13773 static bool
13775 {
13779 else
13781 }
13783 /* Helper function for ix86_delegitimize_address.
13784 Attempt to delegitimize TLS local-exec accesses. */
13786 static rtx
13788 {
13813 {
13818 }
13824 }
13826 /* In the name of slightly smaller debug output, and to cater to
13827 general assembler lossage, recognize PIC+GOTOFF and turn it back
13828 into a direct symbol reference.
13830 On Darwin, this is necessary to avoid a crash, because Darwin
13831 has a different PIC label for each routine but the DWARF debugging
13832 information is not associated with any particular routine, so it's
13833 necessary to remove references to the PIC label from RTL stored by
13834 the DWARF output code. */
13836 static rtx
13838 {
13840 /* addend is NULL or some rtx if x is something+GOTOFF where
13841 something doesn't include the PIC register. */
13843 /* reg_addend is NULL or a multiple of some register. */
13845 /* const_addend is NULL or a const_int. */
13847 /* This is the result, or NULL. */
13856 {
13863 {
13869 }
13876 {
13879 {
13884 }
13886 }
13891 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
13892 and -mcmodel=medium -fpic. */
13893 }
13900 /* %ebx + GOT/GOTOFF */
13901 ;
13903 {
13904 /* %ebx + %reg * scale + GOT/GOTOFF */
13910 else
13911 {
13914 }
13915 }
13916 else
13922 {
13925 }
13946 {
13947 /* If the rest of original X doesn't involve the PIC register, add
13948 addend and subtract pic_offset_table_rtx. This can happen e.g.
13949 for code like:
13950 leal (%ebx, %ecx, 4), %ecx
13951 ...
13952 movl foo@GOTOFF(%ecx), %edx
13953 in which case we return (%ecx - %ebx) + foo. */
13956 pic_offset_table_rtx),
13957 result);
13958 else
13960 }
13962 {
13966 }
13968 }
13970 /* If X is a machine specific address (i.e. a symbol or label being
13971 referenced as a displacement from the GOT implemented using an
13972 UNSPEC), then return the base term. Otherwise return X. */
13974 rtx
13976 {
13977 rtx term;
13980 {
13994 }
13997 }
13998 \f
13999 static void
14002 {
14006 {
14009 }
14014 {
14017 {
14036 }
14040 {
14059 }
14066 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14067 Those same assemblers have the same but opposite lossage on cmov. */
14072 else
14077 {
14090 }
14098 {
14111 }
14114 /* ??? As above. */
14123 /* ??? As above. */
14128 else
14139 }
14141 }
14143 /* Print the name of register X to FILE based on its machine mode and number.
14144 If CODE is 'w', pretend the mode is HImode.
14145 If CODE is 'b', pretend the mode is QImode.
14146 If CODE is 'k', pretend the mode is SImode.
14147 If CODE is 'q', pretend the mode is DImode.
14148 If CODE is 'x', pretend the mode is V4SFmode.
14149 If CODE is 't', pretend the mode is V8SFmode.
14150 If CODE is 'g', pretend the mode is V16SFmode.
14151 If CODE is 'h', pretend the reg is the 'high' byte register.
14152 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14153 If CODE is 'd', duplicate the operand for AVX instruction.
14154 */
14156 void
14158 {
14167 {
14171 }
14198 else
14201 /* Irritatingly, AMD extended registers use different naming convention
14202 from the normal registers: "r%d[bwd]" */
14204 {
14209 {
14223 /* no suffix */
14228 }
14230 }
14234 {
14237 {
14240 }
14241 /* FALLTHRU */
14247 /* FALLTHRU */
14250 normal:
14265 {
14270 }
14273 {
14278 }
14282 }
14286 {
14289 else
14291 }
14292 }
14294 /* Locate some local-dynamic symbol still in use by this function
14295 so that we can print its name in some tls_local_dynamic_base
14296 pattern. */
14298 static int
14300 {
14305 {
14308 }
14311 }
14315 {
14316 rtx insn;
14327 }
14329 /* Meaning of CODE:
14330 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14331 C -- print opcode suffix for set/cmov insn.
14332 c -- like C, but print reversed condition
14333 F,f -- likewise, but for floating-point.
14334 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14335 otherwise nothing
14336 R -- print the prefix for register names.
14337 z -- print the opcode suffix for the size of the current operand.
14338 Z -- likewise, with special suffixes for x87 instructions.
14339 * -- print a star (in certain assembler syntax)
14340 A -- print an absolute memory reference.
14341 E -- print address with DImode register names if TARGET_64BIT.
14342 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14343 s -- print a shift double count, followed by the assemblers argument
14344 delimiter.
14345 b -- print the QImode name of the register for the indicated operand.
14346 %b0 would print %al if operands[0] is reg 0.
14347 w -- likewise, print the HImode name of the register.
14348 k -- likewise, print the SImode name of the register.
14349 q -- likewise, print the DImode name of the register.
14350 x -- likewise, print the V4SFmode name of the register.
14351 t -- likewise, print the V8SFmode name of the register.
14352 g -- likewise, print the V16SFmode name of the register.
14353 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14354 y -- print "st(0)" instead of "st" as a register.
14355 d -- print duplicated register operand for AVX instruction.
14356 D -- print condition for SSE cmp instruction.
14357 P -- if PIC, print an @PLT suffix.
14358 p -- print raw symbol name.
14359 X -- don't print any sort of PIC '@' suffix for a symbol.
14360 & -- print some in-use local-dynamic symbol name.
14361 H -- print a memory address offset by 8; used for sse high-parts
14362 Y -- print condition for XOP pcom* instruction.
14363 + -- print a branch hint as 'cs' or 'ds' prefix
14364 ; -- print a semicolon (after prefixes due to bug in older gas).
14365 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14366 @ -- print a segment register of thread base pointer load
14367 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14368 */
14370 void
14372 {
14374 {
14376 {
14379 {
14385 /* Intel syntax. For absolute addresses, registers should not
14386 be surrounded by braces. */
14388 {
14393 }
14398 }
14404 /* Wrap address in an UNSPEC to declare special handling. */
14442 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14447 {
14461 output_operand_lossage
14464 }
14467 #endif
14472 {
14473 /* Opcodes don't get size suffixes if using Intel opcodes. */
14478 {
14496 output_operand_lossage
14499 }
14500 }
14503 warning
14505 /* FALLTHRU */
14508 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14513 {
14515 {
14517 #ifdef HAVE_AS_IX86_FILDS
14519 #endif
14527 #ifdef HAVE_AS_IX86_FILDQ
14529 #else
14531 #endif
14536 }
14537 }
14539 {
14540 /* 387 opcodes don't get size suffixes
14541 if the operands are registers. */
14546 {
14562 }
14563 }
14564 else
14565 {
14566 output_operand_lossage
14569 }
14571 output_operand_lossage
14592 {
14595 }
14600 {
14651 }
14655 /* Little bit of braindamage here. The SSE compare instructions
14656 does use completely different names for the comparisons that the
14657 fp conditional moves. */
14659 {
14662 {
14665 }
14671 {
14674 }
14680 {
14683 }
14692 {
14695 }
14701 {
14704 }
14710 {
14713 }
14724 }
14729 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14732 #endif
14737 {
14741 }
14745 file);
14750 {
14754 }
14755 /* It doesn't actually matter what mode we use here, as we're
14756 only going to use this for printing. */
14758 /* Output 'qword ptr' for intel assembler dialect. */
14767 #ifdef HAVE_AS_IX86_HLE
14769 #else
14771 #endif
14773 #ifdef HAVE_AS_IX86_HLE
14775 #else
14777 #endif
14778 /* We do not want to print value of the operand. */
14787 {
14792 else
14795 }
14798 {
14799 rtx x;
14808 {
14813 {
14815 bool cputaken
14818 /* Emit hints only in the case default branch prediction
14819 heuristics would fail. */
14821 {
14822 /* We use 3e (DS) prefix for taken branches and
14823 2e (CS) prefix for not taken branches. */
14826 else
14828 }
14829 }
14830 }
14832 }
14835 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14837 #endif
14844 /* The kernel uses a different segment register for performance
14845 reasons; a system call would not have to trash the userspace
14846 segment register, which would be expensive. */
14849 else
14864 }
14865 }
14871 {
14872 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14875 {
14878 {
14887 else
14894 }
14896 /* Check for explicit size override (codes 'b', 'w', 'k',
14897 'q' and 'x') */
14911 }
14914 /* Avoid (%rip) for call operands. */
14920 else
14922 }
14925 {
14926 REAL_VALUE_TYPE r;
14934 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14938 else
14940 }
14943 {
14944 REAL_VALUE_TYPE r;
14953 }
14955 /* These float cases don't actually occur as immediate operands. */
14957 {
14962 }
14964 else
14965 {
14966 /* We have patterns that allow zero sets of memory, for instance.
14967 In 64-bit mode, we should probably support all 8-byte vectors,
14968 since we can in fact encode that into an immediate. */
14970 {
14973 }
14976 {
14978 {
14981 }
14984 {
14987 else
14989 }
14990 }
14995 else
14997 }
14998 }
15000 static bool
15002 {
15005 }
15006 \f
15007 /* Print a memory operand whose address is ADDR. */
15009 static void
15011 {
15020 {
15027 }
15029 {
15033 }
15034 else
15045 {
15056 }
15058 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15060 {
15072 }
15074 {
15075 /* Displacement only requires special attention. */
15078 {
15082 }
15085 else
15087 }
15088 else
15089 {
15090 /* Print SImode register names to force addr32 prefix. */
15092 {
15093 #ifdef ENABLE_CHECKING
15096 {
15107 }
15108 #endif
15111 }
15113 && TARGET_X32
15114 && disp
15117 {
15118 /* X32 runs in 64-bit mode, where displacement, DISP, in
15119 address DISP(%r64), is encoded as 32-bit immediate sign-
15120 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15121 address is %r64 + 0xffffffffbffffd00. When %r64 <
15122 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15123 which is invalid for x32. The correct address is %r64
15124 - 0x40000300 == 0xf7ffdd64. To properly encode
15125 -0x40000300(%r64) for x32, we zero-extend negative
15126 displacement by forcing addr32 prefix which truncates
15127 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15128 zero-extend all negative displacements, including -1(%rsp).
15129 However, for small negative displacements, sign-extension
15130 won't cause overflow. We only zero-extend negative
15131 displacements if they < -16*1024*1024, which is also used
15132 to check legitimate address displacements for PIC. */
15134 }
15137 {
15139 {
15144 else
15146 }
15152 {
15157 }
15159 }
15160 else
15161 {
15165 {
15166 /* Pull out the offset of a symbol; print any symbol itself. */
15170 {
15174 }
15182 else
15184 }
15188 {
15191 {
15195 }
15196 }
15199 else
15203 {
15208 }
15210 }
15211 }
15212 }
15214 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15216 static bool
15218 {
15219 rtx op;
15226 {
15229 /* FIXME: This might be @TPOFF in Sun ld. */
15240 else
15252 else
15259 #if TARGET_MACHO
15265 #endif
15268 {
15273 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15275 #else
15277 #endif
15280 }
15285 }
15288 }
15289 \f
15290 /* Split one or more double-mode RTL references into pairs of half-mode
15291 references. The RTL can be REG, offsettable MEM, integer constant, or
15292 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15293 split and "num" is its length. lo_half and hi_half are output arrays
15294 that parallel "operands". */
15296 void
15299 {
15304 {
15313 }
15318 {
15321 /* simplify_subreg refuse to split volatile memory addresses,
15322 but we still have to handle it. */
15324 {
15327 }
15328 else
15329 {
15336 }
15337 }
15338 }
15339 \f
15340 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15341 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15342 is the expression of the binary operation. The output may either be
15343 emitted here, or returned to the caller, like all output_* functions.
15345 There is no guarantee that the operands are the same mode, as they
15346 might be within FLOAT or FLOAT_EXTEND expressions. */
15348 #ifndef SYSV386_COMPAT
15349 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15350 wants to fix the assemblers because that causes incompatibility
15351 with gcc. No-one wants to fix gcc because that causes
15352 incompatibility with assemblers... You can use the option of
15353 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15354 #define SYSV386_COMPAT 1
15355 #endif
15359 {
15365 #ifdef ENABLE_CHECKING
15366 /* Even if we do not want to check the inputs, this documents input
15367 constraints. Which helps in understanding the following code. */
15377 else
15379 #endif
15382 {
15387 else
15396 else
15405 else
15414 else
15421 }
15424 {
15426 {
15430 else
15432 }
15433 else
15434 {
15438 else
15440 }
15442 }
15446 {
15450 {
15454 }
15456 /* know operands[0] == operands[1]. */
15459 {
15462 }
15465 {
15467 /* How is it that we are storing to a dead operand[2]?
15468 Well, presumably operands[1] is dead too. We can't
15469 store the result to st(0) as st(0) gets popped on this
15470 instruction. Instead store to operands[2] (which I
15471 think has to be st(1)). st(1) will be popped later.
15472 gcc <= 2.8.1 didn't have this check and generated
15473 assembly code that the Unixware assembler rejected. */
15475 else
15478 }
15482 else
15489 {
15492 }
15495 {
15498 }
15501 {
15502 #if SYSV386_COMPAT
15503 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15504 derived assemblers, confusingly reverse the direction of
15505 the operation for fsub{r} and fdiv{r} when the
15506 destination register is not st(0). The Intel assembler
15507 doesn't have this brain damage. Read !SYSV386_COMPAT to
15508 figure out what the hardware really does. */
15511 else
15513 #else
15515 /* As above for fmul/fadd, we can't store to st(0). */
15517 else
15519 #endif
15521 }
15524 {
15525 #if SYSV386_COMPAT
15528 else
15530 #else
15533 else
15535 #endif
15537 }
15540 {
15543 else
15546 }
15548 {
15549 #if SYSV386_COMPAT
15551 #else
15553 #endif
15554 }
15555 else
15556 {
15557 #if SYSV386_COMPAT
15559 #else
15561 #endif
15562 }
15567 }
15571 }
15573 /* Check if a 256bit AVX register is referenced inside of EXP. */
15575 static int
15577 {
15588 }
15590 /* Return needed mode for entity in optimize_mode_switching pass. */
15592 static int
15594 {
15596 {
15597 rtx link;
15599 /* Needed mode is set to AVX_U128_CLEAN if there are
15600 no 256bit modes used in function arguments. */
15602 link;
15604 {
15606 {
15611 }
15612 }
15615 }
15617 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15618 changes state only when a 256bit register is written to, but we need
15619 to prevent the compiler from moving optimal insertion point above
15620 eventual read from 256bit register. */
15625 }
15627 /* Return mode that i387 must be switched into
15628 prior to the execution of insn. */
15630 static int
15632 {
15635 /* The mode UNINITIALIZED is used to store control word after a
15636 function call or ASM pattern. The mode ANY specify that function
15637 has no requirements on the control word and make no changes in the
15638 bits we are interested in. */
15652 {
15675 }
15678 }
15680 /* Return mode that entity must be switched into
15681 prior to the execution of insn. */
15683 int
15685 {
15687 {
15697 }
15699 }
15701 /* Check if a 256bit AVX register is referenced in stores. */
15703 static void
15705 {
15707 {
15710 }
15711 }
15713 /* Calculate mode of upper 128bit AVX registers after the insn. */
15715 static int
15717 {
15724 /* We know that state is clean after CALL insn if there are no
15725 256bit registers used in the function return register. */
15727 {
15732 }
15734 /* Otherwise, return current mode. Remember that if insn
15735 references AVX 256bit registers, the mode was already changed
15736 to DIRTY from MODE_NEEDED. */
15738 }
15740 /* Return the mode that an insn results in. */
15742 int
15744 {
15746 {
15756 }
15757 }
15759 static int
15761 {
15762 tree arg;
15764 /* Entry mode is set to AVX_U128_DIRTY if there are
15765 256bit modes used in function arguments. */
15768 {
15773 }
15776 }
15778 /* Return a mode that ENTITY is assumed to be
15779 switched to at function entry. */
15781 int
15783 {
15785 {
15795 }
15796 }
15798 static int
15800 {
15803 /* Exit mode is set to AVX_U128_DIRTY if there are
15804 256bit modes used in the function return register. */
15809 }
15811 /* Return a mode that ENTITY is assumed to be
15812 switched to at function exit. */
15814 int
15816 {
15818 {
15828 }
15829 }
15831 /* Output code to initialize control word copies used by trunc?f?i and
15832 rounding patterns. CURRENT_MODE is set to current control word,
15833 while NEW_MODE is set to new control word. */
15835 static void
15837 {
15839 rtx new_mode;
15850 {
15852 {
15854 /* round toward zero (truncate) */
15860 /* round down toward -oo */
15867 /* round up toward +oo */
15874 /* mask precision exception for nearbyint() */
15881 }
15882 }
15883 else
15884 {
15886 {
15888 /* round toward zero (truncate) */
15894 /* round down toward -oo */
15900 /* round up toward +oo */
15906 /* mask precision exception for nearbyint() */
15913 }
15914 }
15920 }
15922 /* Emit vzeroupper. */
15924 void
15926 {
15929 /* Cancel automatic vzeroupper insertion if there are
15930 live call-saved SSE registers at the insertion point. */
15942 }
15944 /* Generate one or more insns to set ENTITY to MODE. */
15946 void
15948 {
15950 {
15965 }
15966 }
15968 /* Output code for INSN to convert a float to a signed int. OPERANDS
15969 are the insn operands. The output may be [HSD]Imode and the input
15970 operand may be [SDX]Fmode. */
15974 {
15979 /* Jump through a hoop or two for DImode, since the hardware has no
15980 non-popping instruction. We used to do this a different way, but
15981 that was somewhat fragile and broke with post-reload splitters. */
15991 else
15992 {
15997 else
16001 }
16004 }
16006 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16007 have the values zero or one, indicates the ffreep insn's operand
16008 from the OPERANDS array. */
16012 {
16014 #ifdef HAVE_AS_IX86_FFREEP
16016 #else
16017 {
16027 }
16028 #endif
16031 }
16034 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16035 should be used. UNORDERED_P is true when fucom should be used. */
16039 {
16045 {
16048 }
16049 else
16050 {
16053 }
16056 {
16060 else
16062 else
16065 else
16067 }
16074 {
16076 {
16079 }
16080 else
16082 }
16085 && stack_top_dies
16088 {
16089 /* If both the top of the 387 stack dies, and the other operand
16090 is also a stack register that dies, then this must be a
16091 `fcompp' float compare */
16094 {
16095 /* There is no double popping fcomi variant. Fortunately,
16096 eflags is immune from the fstp's cc clobbering. */
16099 else
16102 }
16103 else
16104 {
16107 else
16109 }
16110 }
16111 else
16112 {
16113 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16116 {
16124 NULL,
16125 NULL,
16132 NULL,
16133 NULL,
16134 NULL,
16135 NULL
16136 };
16151 }
16152 }
16154 void
16156 {
16159 #ifdef ASM_QUAD
16162 #else
16164 #endif
16167 }
16169 void
16171 {
16174 #ifdef ASM_QUAD
16177 #else
16179 #endif
16180 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16186 #if TARGET_MACHO
16188 {
16192 }
16193 #endif
16194 else
16197 }
16198 \f
16199 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16200 for the target. */
16202 void
16204 {
16205 rtx tmp;
16207 /* We play register width games, which are only valid after reload. */
16210 /* Avoid HImode and its attendant prefix byte. */
16215 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16217 {
16220 }
16223 }
16225 /* X is an unchanging MEM. If it is a constant pool reference, return
16226 the constant pool rtx, else NULL. */
16228 rtx
16230 {
16237 }
16239 void
16241 {
16249 {
16250 rtx tmp;
16254 {
16260 }
16263 }
16267 {
16270 rtx tmp;
16275 else
16279 {
16286 }
16287 }
16291 {
16293 {
16294 #if TARGET_MACHO
16295 /* dynamic-no-pic */
16297 {
16298 rtx temp = ((reload_in_progress
16306 }
16308 {
16312 }
16315 else
16316 {
16324 }
16325 /* dynamic-no-pic */
16326 #endif
16327 }
16328 else
16329 {
16333 {
16339 }
16340 }
16341 }
16342 else
16343 {
16354 /* Force large constants in 64bit compilation into register
16355 to get them CSEed. */
16367 {
16368 /* If we are loading a floating point constant to a register,
16369 force the value to memory now, since we'll get better code
16370 out the back end. */
16374 {
16379 }
16380 }
16381 }
16384 }
16386 void
16388 {
16392 /* Force constants other than zero into memory. We do not know how
16393 the instructions used to build constants modify the upper 64 bits
16394 of the register, once we have that information we may be able
16395 to handle some of them more efficiently. */
16404 /* We need to check memory alignment for SSE mode since attribute
16405 can make operands unaligned. */
16410 {
16413 /* ix86_expand_vector_move_misalign() does not like constants ... */
16419 /* ... nor both arguments in memory. */
16427 }
16429 /* Make operand1 a register if it isn't already. */
16433 {
16436 }
16439 }
16441 /* Split 32-byte AVX unaligned load and store if needed. */
16443 static void
16445 {
16446 rtx m;
16453 {
16474 }
16477 {
16479 {
16486 }
16487 else
16489 }
16491 {
16493 {
16498 }
16499 else
16501 }
16502 else
16504 }
16506 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16507 straight to ix86_expand_vector_move. */
16508 /* Code generation for scalar reg-reg moves of single and double precision data:
16509 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16510 movaps reg, reg
16511 else
16512 movss reg, reg
16513 if (x86_sse_partial_reg_dependency == true)
16514 movapd reg, reg
16515 else
16516 movsd reg, reg
16518 Code generation for scalar loads of double precision data:
16519 if (x86_sse_split_regs == true)
16520 movlpd mem, reg (gas syntax)
16521 else
16522 movsd mem, reg
16524 Code generation for unaligned packed loads of single precision data
16525 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16526 if (x86_sse_unaligned_move_optimal)
16527 movups mem, reg
16529 if (x86_sse_partial_reg_dependency == true)
16530 {
16531 xorps reg, reg
16532 movlps mem, reg
16533 movhps mem+8, reg
16534 }
16535 else
16536 {
16537 movlps mem, reg
16538 movhps mem+8, reg
16539 }
16541 Code generation for unaligned packed loads of double precision data
16542 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16543 if (x86_sse_unaligned_move_optimal)
16544 movupd mem, reg
16546 if (x86_sse_split_regs == true)
16547 {
16548 movlpd mem, reg
16549 movhpd mem+8, reg
16550 }
16551 else
16552 {
16553 movsd mem, reg
16554 movhpd mem+8, reg
16555 }
16556 */
16558 void
16560 {
16568 {
16570 {
16575 /* FALLTHRU */
16583 }
16586 }
16589 {
16590 /* ??? If we have typed data, then it would appear that using
16591 movdqu is the only way to get unaligned data loaded with
16592 integer type. */
16594 {
16597 /* We will eventually emit movups based on insn attributes. */
16599 }
16601 {
16602 rtx zero;
16605 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16606 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16608 {
16609 /* We will eventually emit movups based on insn attributes. */
16612 }
16614 /* When SSE registers are split into halves, we can avoid
16615 writing to the top half twice. */
16617 {
16620 }
16621 else
16622 {
16623 /* ??? Not sure about the best option for the Intel chips.
16624 The following would seem to satisfy; the register is
16625 entirely cleared, breaking the dependency chain. We
16626 then store to the upper half, with a dependency depth
16627 of one. A rumor has it that Intel recommends two movsd
16628 followed by an unpacklpd, but this is unconfirmed. And
16629 given that the dependency depth of the unpacklpd would
16630 still be one, I'm not sure why this would be better. */
16632 }
16638 }
16639 else
16640 {
16642 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16643 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16645 {
16650 }
16654 else
16664 }
16665 }
16667 {
16669 {
16672 /* We will eventually emit movups based on insn attributes. */
16674 }
16676 {
16678 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16679 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16681 /* We will eventually emit movups based on insn attributes. */
16683 else
16684 {
16689 }
16690 }
16691 else
16692 {
16697 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16698 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16700 {
16703 }
16704 else
16705 {
16710 }
16711 }
16712 }
16713 else
16715 }
16717 /* Expand a push in MODE. This is some mode for which we do not support
16718 proper push instructions, at least from the registers that we expect
16719 the value to live in. */
16721 void
16723 {
16724 rtx tmp;
16734 /* When we push an operand onto stack, it has to be aligned at least
16735 at the function argument boundary. However since we don't have
16736 the argument type, we can't determine the actual argument
16737 boundary. */
16739 }
16741 /* Helper function of ix86_fixup_binary_operands to canonicalize
16742 operand order. Returns true if the operands should be swapped. */
16744 static bool
16746 rtx operands[])
16747 {
16752 /* If the operation is not commutative, we can't do anything. */
16756 /* Highest priority is that src1 should match dst. */
16762 /* Next highest priority is that immediate constants come second. */
16768 /* Lowest priority is that memory references should come second. */
16775 }
16778 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16779 destination to use for the operation. If different from the true
16780 destination in operands[0], a copy operation will be required. */
16782 rtx
16784 rtx operands[])
16785 {
16790 /* Canonicalize operand order. */
16792 {
16793 rtx temp;
16795 /* It is invalid to swap operands of different modes. */
16801 }
16803 /* Both source operands cannot be in memory. */
16805 {
16806 /* Optimization: Only read from memory once. */
16808 {
16811 }
16812 else
16814 }
16816 /* If the destination is memory, and we do not have matching source
16817 operands, do things in registers. */
16821 /* Source 1 cannot be a constant. */
16825 /* Source 1 cannot be a non-matching memory. */
16829 /* Improve address combine. */
16838 }
16840 /* Similarly, but assume that the destination has already been
16841 set up properly. */
16843 void
16846 {
16849 }
16851 /* Attempt to expand a binary operator. Make the expansion closer to the
16852 actual machine, then just general_operand, which will allow 3 separate
16853 memory references (one output, two input) in a single insn. */
16855 void
16857 rtx operands[])
16858 {
16865 /* Emit the instruction. */
16869 {
16870 /* Reload doesn't know about the flags register, and doesn't know that
16871 it doesn't want to clobber it. We can only do this with PLUS. */
16874 }
16878 {
16879 /* This is going to be an LEA; avoid splitting it later. */
16881 }
16882 else
16883 {
16886 }
16888 /* Fix up the destination if needed. */
16891 }
16893 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16894 the given OPERANDS. */
16896 void
16898 rtx operands[])
16899 {
16902 {
16905 }
16907 {
16910 }
16911 /* Optimize (__m128i) d | (__m128i) e and similar code
16912 when d and e are float vectors into float vector logical
16913 insn. In C/C++ without using intrinsics there is no other way
16914 to express vector logical operation on float vectors than
16915 to cast them temporarily to integer vectors. */
16917 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16926 {
16927 rtx dst;
16929 {
16936 {
16939 }
16940 else
16941 {
16946 }
16957 }
16958 }
16967 }
16969 /* Return TRUE or FALSE depending on whether the binary operator meets the
16970 appropriate constraints. */
16972 bool
16975 {
16980 /* Both source operands cannot be in memory. */
16984 /* Canonicalize operand order for commutative operators. */
16986 {
16990 }
16992 /* If the destination is memory, we must have a matching source operand. */
16996 /* Source 1 cannot be a constant. */
17000 /* Source 1 cannot be a non-matching memory. */
17002 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17010 }
17012 /* Attempt to expand a unary operator. Make the expansion closer to the
17013 actual machine, then just general_operand, which will allow 2 separate
17014 memory references (one output, one input) in a single insn. */
17016 void
17018 rtx operands[])
17019 {
17026 /* If the destination is memory, and we do not have matching source
17027 operands, do things in registers. */
17030 {
17033 else
17035 }
17037 /* When source operand is memory, destination must match. */
17041 /* Emit the instruction. */
17045 {
17046 /* Reload doesn't know about the flags register, and doesn't know that
17047 it doesn't want to clobber it. */
17050 }
17051 else
17052 {
17055 }
17057 /* Fix up the destination if needed. */
17060 }
17062 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17063 divisor are within the range [0-255]. */
17065 void
17068 {
17077 {
17090 }
17097 /* Use 8bit unsigned divimod if dividend and divisor are within
17098 the range [0-255]. */
17107 pc_rtx);
17112 /* Generate original signed/unsigned divimod. */
17117 /* Branch to the end. */
17121 /* Generate 8bit unsigned divide. */
17123 /* Don't use operands[0] for result of 8bit divide since not all
17124 registers support QImode ZERO_EXTRACT. */
17131 {
17134 }
17135 else
17136 {
17139 }
17141 /* Extract remainder from AH. */
17145 else
17146 {
17147 /* Need a new scratch register since the old one has result
17148 of 8bit divide. */
17152 }
17155 /* Zero extend quotient from AL. */
17161 }
17163 #define LEA_MAX_STALL (3)
17164 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17166 /* Increase given DISTANCE in half-cycles according to
17167 dependencies between PREV and NEXT instructions.
17168 Add 1 half-cycle if there is no dependency and
17169 go to next cycle if there is some dependecy. */
17171 static unsigned int
17173 {
17190 }
17192 /* Function checks if instruction INSN defines register number
17193 REGNO1 or REGNO2. */
17195 static bool
17197 rtx insn)
17198 {
17206 {
17208 }
17211 }
17213 /* Function checks if instruction INSN uses register number
17214 REGNO as a part of address expression. */
17216 static bool
17218 {
17226 }
17228 /* Search backward for non-agu definition of register number REGNO1
17229 or register number REGNO2 in basic block starting from instruction
17230 START up to head of basic block or instruction INSN.
17232 Function puts true value into *FOUND var if definition was found
17233 and false otherwise.
17235 Distance in half-cycles between START and found instruction or head
17236 of BB is added to DISTANCE and returned. */
17238 static int
17242 {
17252 {
17254 {
17257 {
17260 {
17263 }
17264 }
17267 }
17272 }
17275 }
17277 /* Search backward for non-agu definition of register number REGNO1
17278 or register number REGNO2 in INSN's basic block until
17279 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17280 2. Reach neighbour BBs boundary, or
17281 3. Reach agu definition.
17282 Returns the distance between the non-agu definition point and INSN.
17283 If no definition point, returns -1. */
17285 static int
17287 rtx insn)
17288 {
17299 {
17300 edge e;
17301 edge_iterator ei;
17306 {
17309 }
17315 else
17316 {
17321 {
17322 int bb_dist
17328 {
17335 }
17336 }
17339 }
17340 }
17342 /* get_attr_type may modify recog data. We want to make sure
17343 that recog data is valid for instruction INSN, on which
17344 distance_non_agu_define is called. INSN is unchanged here. */
17351 }
17353 /* Return the distance in half-cycles between INSN and the next
17354 insn that uses register number REGNO in memory address added
17355 to DISTANCE. Return -1 if REGNO0 is set.
17357 Put true value into *FOUND if register usage was found and
17358 false otherwise.
17359 Put true value into *REDEFINED if register redefinition was
17360 found and false otherwise. */
17362 static int
17366 {
17375 {
17378 /* If insn and start belong to the same bb, set prev to insn,
17379 so the call to increase_distance will increase the distance
17380 between insns by 1. */
17382 }
17387 {
17389 {
17392 {
17393 /* Return DISTANCE if OP0 is used in memory
17394 address in NEXT. */
17397 }
17400 {
17401 /* Return -1 if OP0 is set in NEXT. */
17404 }
17407 }
17413 }
17416 }
17418 /* Return the distance between INSN and the next insn that uses
17419 register number REGNO0 in memory address. Return -1 if no such
17420 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17422 static int
17424 {
17436 {
17437 edge e;
17438 edge_iterator ei;
17443 {
17446 }
17452 else
17453 {
17459 {
17460 int bb_dist
17465 {
17472 }
17473 }
17476 }
17477 }
17483 }
17485 /* Define this macro to tune LEA priority vs ADD, it take effect when
17486 there is a dilemma of choicing LEA or ADD
17487 Negative value: ADD is more preferred than LEA
17488 Zero: Netrual
17489 Positive value: LEA is more preferred than ADD*/
17490 #define IX86_LEA_PRIORITY 0
17492 /* Return true if usage of lea INSN has performance advantage
17493 over a sequence of instructions. Instructions sequence has
17494 SPLIT_COST cycles higher latency than lea latency. */
17496 static bool
17499 {
17502 /* For Silvermont if using a 2-source or 3-source LEA for
17503 non-destructive destination purposes, or due to wanting
17504 ability to use SCALE, the use of LEA is justified. */
17506 {
17514 }
17520 {
17521 /* If there is no non AGU operand definition, no AGU
17522 operand usage and split cost is 0 then both lea
17523 and non lea variants have same priority. Currently
17524 we prefer lea for 64 bit code and non lea on 32 bit
17525 code. */
17528 else
17530 }
17532 /* With longer definitions distance lea is more preferable.
17533 Here we change it to take into account splitting cost and
17534 lea priority. */
17537 /* If there is no use in memory addess then we just check
17538 that split cost exceeds AGU stall. */
17542 /* If this insn has both backward non-agu dependence and forward
17543 agu dependence, the one with short distance takes effect. */
17545 }
17547 /* Return true if it is legal to clobber flags by INSN and
17548 false otherwise. */
17550 static bool
17552 {
17555 bitmap live;
17558 {
17560 {
17567 }
17573 }
17577 }
17579 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17580 move and add to avoid AGU stalls. */
17582 bool
17584 {
17587 /* Check if we need to optimize. */
17591 /* Check it is correct to split here. */
17599 /* We need to split only adds with non destructive
17600 destination operand. */
17603 else
17605 }
17607 /* Return true if we should emit lea instruction instead of mov
17608 instruction. */
17610 bool
17612 {
17615 /* Check if we need to optimize. */
17619 /* Use lea for reg to reg moves only. */
17627 }
17629 /* Return true if we need to split lea into a sequence of
17630 instructions to avoid AGU stalls. */
17632 bool
17634 {
17640 /* Check we need to optimize. */
17644 /* Check it is correct to split here. */
17651 /* There should be at least two components in the address. */
17656 /* We should not split into add if non legitimate pic
17657 operand is used as displacement. */
17672 /* Compute how many cycles we will add to execution time
17673 if split lea into a sequence of instructions. */
17675 {
17676 /* Have to use mov instruction if non desctructive
17677 destination form is used. */
17681 /* Have to add index to base if both exist. */
17685 /* Have to use shift and adds if scale is 2 or greater. */
17687 {
17692 else
17694 }
17696 /* Have to use add instruction with immediate if
17697 disp is non zero. */
17701 /* Subtract the price of lea. */
17703 }
17707 }
17709 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17710 matches destination. RTX includes clobber of FLAGS_REG. */
17712 static void
17715 {
17722 }
17724 /* Return true if regno1 def is nearest to the insn. */
17726 static bool
17728 {
17735 {
17737 {
17740 }
17746 }
17748 /* None of the regs is defined in the bb. */
17750 }
17752 /* Split lea instructions into a sequence of instructions
17753 which are executed on ALU to avoid AGU stalls.
17754 It is assumed that it is allowed to clobber flags register
17755 at lea position. */
17757 void
17759 {
17775 {
17778 }
17781 {
17784 }
17790 {
17791 /* Case r1 = r1 + ... */
17793 {
17794 /* If we have a case r1 = r1 + C * r1 then we
17795 should use multiplication which is very
17796 expensive. Assume cost model is wrong if we
17797 have such case here. */
17802 }
17803 else
17804 {
17805 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17809 /* Use shift for scaling. */
17818 }
17819 }
17821 {
17824 }
17825 else
17826 {
17828 {
17831 }
17833 {
17836 }
17837 else
17838 {
17843 else
17844 {
17845 rtx tmp1;
17847 /* Find better operand for SET instruction, depending
17848 on which definition is farther from the insn. */
17851 else
17861 }
17864 }
17868 }
17869 }
17871 /* Return true if it is ok to optimize an ADD operation to LEA
17872 operation to avoid flag register consumation. For most processors,
17873 ADD is faster than LEA. For the processors like ATOM, if the
17874 destination register of LEA holds an actual address which will be
17875 used soon, LEA is better and otherwise ADD is better. */
17877 bool
17879 {
17884 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17892 }
17894 /* Return true if destination reg of SET_BODY is shift count of
17895 USE_BODY. */
17897 static bool
17899 {
17900 rtx set_dest;
17901 rtx shift_rtx;
17904 /* Retrieve destination of SET_BODY. */
17906 {
17915 use_body))
17920 }
17922 /* Retrieve shift count of USE_BODY. */
17924 {
17936 }
17944 {
17947 /* Return true if shift count is dest of SET_BODY. */
17949 {
17950 /* Add check since it can be invoked before register
17951 allocation in pre-reload schedule. */
17957 }
17958 }
17961 }
17963 /* Return true if destination reg of SET_INSN is shift count of
17964 USE_INSN. */
17966 bool
17968 {
17971 }
17973 /* Return TRUE or FALSE depending on whether the unary operator meets the
17974 appropriate constraints. */
17976 bool
17980 {
17981 /* If one of operands is memory, source and destination must match. */
17987 }
17989 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17990 are ok, keeping in mind the possible movddup alternative. */
17992 bool
17994 {
18000 }
18002 /* Post-reload splitter for converting an SF or DFmode value in an
18003 SSE register into an unsigned SImode. */
18005 void
18007 {
18018 /* Load up the value into the low element. We must ensure that the other
18019 elements are valid floats -- zero is the easiest such value. */
18021 {
18024 else
18026 }
18027 else
18028 {
18033 else
18035 }
18055 else
18060 }
18062 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18063 Expects the 64-bit DImode to be supplied in a pair of integral
18064 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18065 -mfpmath=sse, !optimize_size only. */
18067 void
18069 {
18073 rtx x;
18079 {
18082 }
18083 else
18084 {
18088 }
18096 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18099 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18100 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18101 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18102 (0x1.0p84 + double(fp_value_hi_xmm)).
18103 Note these exponents differ by 32. */
18107 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18108 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18117 /* Add the upper and lower DFmode values together. */
18120 else
18121 {
18125 }
18128 }
18130 /* Not used, but eases macroization of patterns. */
18131 void
18133 rtx input ATTRIBUTE_UNUSED)
18134 {
18136 }
18138 /* Convert an unsigned SImode value into a DFmode. Only currently used
18139 for SSE, but applicable anywhere. */
18141 void
18143 {
18144 REAL_VALUE_TYPE TWO31r;
18159 }
18161 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18162 32-bit mode; otherwise we have a direct convert instruction. */
18164 void
18166 {
18167 REAL_VALUE_TYPE TWO32r;
18185 }
18187 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18188 For x86_32, -mfpmath=sse, !optimize_size only. */
18189 void
18191 {
18192 REAL_VALUE_TYPE ONE16r;
18211 }
18213 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18214 a vector of unsigned ints VAL to vector of floats TARGET. */
18216 void
18218 {
18220 REAL_VALUE_TYPE TWO16r;
18227 else
18232 OPTAB_DIRECT);
18243 OPTAB_DIRECT);
18245 OPTAB_DIRECT);
18248 }
18250 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18251 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18252 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18253 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18255 rtx
18257 {
18258 REAL_VALUE_TYPE TWO31r;
18273 {
18279 }
18288 OPTAB_DIRECT);
18289 else
18290 {
18296 OPTAB_DIRECT);
18297 }
18300 }
18302 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18303 then replicate the value for all elements of the vector
18304 register. */
18306 rtx
18308 {
18310 rtvec v;
18314 {
18341 }
18342 }
18344 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18345 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18346 for an SSE register. If VECT is true, then replicate the mask for
18347 all elements of the vector register. If INVERT is true, then create
18348 a mask excluding the sign bit. */
18350 rtx
18352 {
18356 rtx v;
18357 rtx mask;
18359 /* Find the sign bit, sign extended to 2*HWI. */
18361 {
18381 else
18389 {
18392 }
18393 else
18394 {
18395 rtvec vec;
18401 {
18404 }
18405 else
18415 }
18420 }
18425 /* Force this value into the low part of a fp vector constant. */
18434 }
18436 /* Generate code for floating point ABS or NEG. */
18438 void
18440 rtx operands[])
18441 {
18452 {
18458 }
18460 /* NEG and ABS performed with SSE use bitwise mask operations.
18461 Create the appropriate mask now. */
18464 else
18474 {
18476 rtvec par;
18481 else
18482 {
18485 }
18487 }
18488 else
18490 }
18492 /* Expand a copysign operation. Special case operand 0 being a constant. */
18494 void
18496 {
18510 else
18514 {
18521 {
18524 else
18525 {
18529 }
18530 }
18540 else
18544 }
18545 else
18546 {
18556 else
18560 }
18561 }
18563 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18564 be a constant, and so has already been expanded into a vector constant. */
18566 void
18568 {
18584 {
18587 }
18588 }
18590 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18591 so we have to do two masks. */
18593 void
18595 {
18610 {
18611 /* Shouldn't happen often (it's useless, obviously), but when it does
18612 we'd generate incorrect code if we continue below. */
18615 }
18618 {
18629 }
18630 else
18631 {
18633 {
18635 }
18637 {
18641 }
18645 {
18648 }
18650 {
18655 }
18657 }
18661 }
18663 /* Return TRUE or FALSE depending on whether the first SET in INSN
18664 has source and destination with matching CC modes, and that the
18665 CC mode is at least as constrained as REQ_MODE. */
18667 bool
18669 {
18670 rtx set;
18681 {
18691 /* FALLTHRU */
18695 /* FALLTHRU */
18699 /* FALLTHRU */
18713 }
18716 }
18718 /* Generate insn patterns to do an integer compare of OPERANDS. */
18720 static rtx
18722 {
18729 /* This is very simple, but making the interface the same as in the
18730 FP case makes the rest of the code easier. */
18734 /* Return the test that should be put into the flags user, i.e.
18735 the bcc, scc, or cmov instruction. */
18737 }
18739 /* Figure out whether to use ordered or unordered fp comparisons.
18740 Return the appropriate mode to use. */
18742 enum machine_mode
18744 {
18745 /* ??? In order to make all comparisons reversible, we do all comparisons
18746 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18747 all forms trapping and nontrapping comparisons, we can make inequality
18748 comparisons trapping again, since it results in better code when using
18749 FCOM based compares. */
18751 }
18753 enum machine_mode
18755 {
18759 {
18762 }
18765 {
18766 /* Only zero flag is needed. */
18770 /* Codes needing carry flag. */
18773 /* Detect overflow checks. They need just the carry flag. */
18777 else
18781 /* Detect overflow checks. They need just the carry flag. */
18785 else
18787 /* Codes possibly doable only with sign flag when
18788 comparing against zero. */
18793 else
18794 /* For other cases Carry flag is not required. */
18796 /* Codes doable only with sign flag when comparing
18797 against zero, but we miss jump instruction for it
18798 so we need to use relational tests against overflow
18799 that thus needs to be zero. */
18804 else
18806 /* strcmp pattern do (use flags) and combine may ask us for proper
18807 mode. */
18812 }
18813 }
18815 /* Return the fixed registers used for condition codes. */
18817 static bool
18819 {
18823 }
18825 /* If two condition code modes are compatible, return a condition code
18826 mode which is compatible with both. Otherwise, return
18827 VOIDmode. */
18829 static enum machine_mode
18831 {
18848 {
18862 {
18876 }
18880 /* These are only compatible with themselves, which we already
18881 checked above. */
18883 }
18884 }
18887 /* Return a comparison we can do and that it is equivalent to
18888 swap_condition (code) apart possibly from orderedness.
18889 But, never change orderedness if TARGET_IEEE_FP, returning
18890 UNKNOWN in that case if necessary. */
18892 static enum rtx_code
18894 {
18896 {
18907 }
18908 }
18910 /* Return cost of comparison CODE using the best strategy for performance.
18911 All following functions do use number of instructions as a cost metrics.
18912 In future this should be tweaked to compute bytes for optimize_size and
18913 take into account performance of various instructions on various CPUs. */
18915 static int
18917 {
18920 /* The cost of code using bit-twiddling on %ah. */
18922 {
18945 }
18948 {
18955 }
18956 }
18958 /* Return strategy to use for floating-point. We assume that fcomi is always
18959 preferrable where available, since that is also true when looking at size
18960 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18962 enum ix86_fpcmp_strategy
18964 {
18965 /* Do fcomi/sahf based test when profitable. */
18974 }
18976 /* Swap, force into registers, or otherwise massage the two operands
18977 to a fp comparison. The operands are updated in place; the new
18978 comparison code is returned. */
18980 static enum rtx_code
18982 {
18988 /* All of the unordered compare instructions only work on registers.
18989 The same is true of the fcomi compare instructions. The XFmode
18990 compare instructions require registers except when comparing
18991 against zero or when converting operand 1 from fixed point to
18992 floating point. */
19001 {
19004 }
19005 else
19006 {
19007 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19008 things around if they appear profitable, otherwise force op0
19009 into a register. */
19015 {
19018 {
19019 rtx tmp;
19022 }
19023 }
19029 {
19034 {
19037 }
19038 else
19040 }
19041 }
19043 /* Try to rearrange the comparison to make it cheaper. */
19047 {
19048 rtx tmp;
19053 }
19058 }
19060 /* Convert comparison codes we use to represent FP comparison to integer
19061 code that will result in proper branch. Return UNKNOWN if no such code
19062 is available. */
19064 enum rtx_code
19066 {
19068 {
19091 }
19092 }
19094 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19096 static rtx
19098 {
19105 /* Do fcomi/sahf based test when profitable. */
19107 {
19112 tmp);
19120 tmp);
19129 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19136 /* In the unordered case, we have to check C2 for NaN's, which
19137 doesn't happen to work out to anything nice combination-wise.
19138 So do some bit twiddling on the value we've got in AH to come
19139 up with an appropriate set of condition codes. */
19143 {
19147 {
19150 }
19151 else
19152 {
19158 }
19163 {
19168 }
19169 else
19170 {
19173 }
19178 {
19181 }
19182 else
19183 {
19187 }
19192 {
19198 }
19199 else
19200 {
19203 }
19208 {
19213 }
19214 else
19215 {
19218 }
19223 {
19228 }
19229 else
19230 {
19233 }
19247 }
19252 }
19254 /* Return the test that should be put into the flags user, i.e.
19255 the bcc, scc, or cmov instruction. */
19258 const0_rtx);
19259 }
19261 static rtx
19263 {
19264 rtx ret;
19270 {
19273 }
19274 else
19278 }
19280 void
19282 {
19284 rtx tmp;
19287 {
19294 simple:
19298 pc_rtx);
19306 /* Expand DImode branch into multiple compare+branch. */
19307 {
19313 {
19316 }
19323 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19324 avoid two branches. This costs one extra insn, so disable when
19325 optimizing for size. */
19330 {
19348 }
19350 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19351 op1 is a constant and the low word is zero, then we can just
19352 examine the high word. Similarly for low word -1 and
19353 less-or-equal-than or greater-than. */
19357 {
19360 {
19363 }
19367 {
19370 }
19374 }
19376 /* Otherwise, we need two or three jumps. */
19385 {
19399 }
19401 /*
19402 * a < b =>
19403 * if (hi(a) < hi(b)) goto true;
19404 * if (hi(a) > hi(b)) goto false;
19405 * if (lo(a) < lo(b)) goto true;
19406 * false:
19407 */
19419 }
19424 }
19425 }
19427 /* Split branch based on floating point condition. */
19428 void
19431 {
19432 rtx condition;
19433 rtx i;
19436 {
19441 }
19444 tmp);
19446 /* Remove pushed operand from stack. */
19456 }
19458 void
19460 {
19461 rtx ret;
19468 }
19470 /* Expand comparison setting or clearing carry flag. Return true when
19471 successful and set pop for the operation. */
19472 static bool
19474 {
19478 /* Do not handle double-mode compares that go through special path. */
19483 {
19488 /* Shortcut: following common codes never translate
19489 into carry flag compares. */
19494 /* These comparisons require zero flag; swap operands so they won't. */
19497 {
19502 }
19504 /* Try to expand the comparison and verify that we end up with
19505 carry flag based comparison. This fails to be true only when
19506 we decide to expand comparison using arithmetic that is not
19507 too common scenario. */
19516 else
19525 }
19531 {
19536 /* Convert a==0 into (unsigned)a<1. */
19545 /* Convert a>b into b<a or a>=b-1. */
19549 {
19551 /* Bail out on overflow. We still can swap operands but that
19552 would force loading of the constant into register. */
19557 }
19558 else
19559 {
19564 }
19567 /* Convert a>=0 into (unsigned)a<0x80000000. */
19585 }
19586 /* Swapping operands may cause constant to appear as first operand. */
19588 {
19592 }
19596 }
19598 bool
19600 {
19624 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19625 HImode insns, we'd be swallowed in word prefix ops. */
19631 {
19635 HOST_WIDE_INT diff;
19638 /* Sign bit compares are better done using shifts than we do by using
19639 sbb. */
19642 {
19643 /* Detect overlap between destination and compare sources. */
19647 {
19648 rtx flags;
19657 {
19659 compare_code
19661 }
19663 /* To simplify rest of code, restrict to the GEU case. */
19665 {
19671 }
19672 else
19673 {
19676 reverse_condition_maybe_unordered
19678 else
19681 }
19690 else
19693 }
19694 else
19695 {
19698 else
19699 {
19704 }
19706 }
19709 {
19710 /*
19711 * cmpl op0,op1
19712 * sbbl dest,dest
19713 * [addl dest, ct]
19714 *
19715 * Size 5 - 8.
19716 */
19721 }
19723 {
19724 /*
19725 * cmpl op0,op1
19726 * sbbl dest,dest
19727 * orl $ct, dest
19728 *
19729 * Size 8.
19730 */
19734 }
19736 {
19737 /*
19738 * cmpl op0,op1
19739 * sbbl dest,dest
19740 * notl dest
19741 * [addl dest, cf]
19742 *
19743 * Size 8 - 11.
19744 */
19750 }
19751 else
19752 {
19753 /*
19754 * cmpl op0,op1
19755 * sbbl dest,dest
19756 * [notl dest]
19757 * andl cf - ct, dest
19758 * [addl dest, ct]
19759 *
19760 * Size 8 - 11.
19761 */
19764 {
19768 }
19778 }
19784 }
19787 {
19790 HOST_WIDE_INT tmp;
19795 {
19798 /* We may be reversing unordered compare to normal compare, that
19799 is not valid in general (we may convert non-trapping condition
19800 to trapping one), however on i386 we currently emit all
19801 comparisons unordered. */
19804 }
19805 else
19806 {
19809 }
19810 }
19815 {
19820 {
19825 }
19826 }
19828 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19832 {
19833 /* If lea code below could be used, only optimize
19834 if it results in a 2 insn sequence. */
19840 {
19841 /*
19842 * notl op1 (if necessary)
19843 * sarl $31, op1
19844 * orl cf, op1
19845 */
19847 {
19851 }
19862 }
19863 }
19871 {
19872 /*
19873 * xorl dest,dest
19874 * cmpl op1,op2
19875 * setcc dest
19876 * lea cf(dest*(ct-cf)),dest
19877 *
19878 * Size 14.
19879 *
19880 * This also catches the degenerate setcc-only case.
19881 */
19883 rtx tmp;
19889 /* On x86_64 the lea instruction operates on Pmode, so we need
19890 to get arithmetics done in proper mode to match. */
19893 else
19894 {
19895 rtx out1;
19898 nops++;
19900 {
19902 nops++;
19903 }
19904 }
19906 {
19908 nops++;
19909 }
19911 {
19914 else
19916 }
19921 }
19923 /*
19924 * General case: Jumpful:
19925 * xorl dest,dest cmpl op1, op2
19926 * cmpl op1, op2 movl ct, dest
19927 * setcc dest jcc 1f
19928 * decl dest movl cf, dest
19929 * andl (cf-ct),dest 1:
19930 * addl ct,dest
19931 *
19932 * Size 20. Size 14.
19933 *
19934 * This is reasonably steep, but branch mispredict costs are
19935 * high on modern cpus, so consider failing only if optimizing
19936 * for space.
19937 */
19942 {
19944 {
19951 {
19954 /* We may be reversing unordered compare to normal compare,
19955 that is not valid in general (we may convert non-trapping
19956 condition to trapping one), however on i386 we currently
19957 emit all comparisons unordered. */
19959 }
19960 else
19961 {
19965 }
19966 }
19969 {
19970 /* notl op1 (if needed)
19971 sarl $31, op1
19972 andl (cf-ct), op1
19973 addl ct, op1
19975 For x < 0 (resp. x <= -1) there will be no notl,
19976 so if possible swap the constants to get rid of the
19977 complement.
19978 True/false will be -1/0 while code below (store flag
19979 followed by decrement) is 0/-1, so the constants need
19980 to be exchanged once more. */
19983 {
19986 }
19987 else
19988 {
19992 }
19995 }
19996 else
19997 {
20001 constm1_rtx,
20003 }
20015 }
20016 }
20019 {
20020 /* Try a few things more with specific constants and a variable. */
20022 optab op;
20028 /* If one of the two operands is an interesting constant, load a
20029 constant with the above and mask it in with a logical operation. */
20032 {
20038 else
20040 }
20042 {
20048 else
20050 }
20051 else
20058 /* Recurse to get the constant loaded. */
20062 /* Mask in the interesting variable. */
20064 OPTAB_WIDEN);
20069 }
20071 /*
20072 * For comparison with above,
20073 *
20074 * movl cf,dest
20075 * movl ct,tmp
20076 * cmpl op1,op2
20077 * cmovcc tmp,dest
20078 *
20079 * Size 15.
20080 */
20102 }
20104 /* Swap, force into registers, or otherwise massage the two operands
20105 to an sse comparison with a mask result. Thus we differ a bit from
20106 ix86_prepare_fp_compare_args which expects to produce a flags result.
20108 The DEST operand exists to help determine whether to commute commutative
20109 operators. The POP0/POP1 operands are updated in place. The new
20110 comparison code is returned, or UNKNOWN if not implementable. */
20112 static enum rtx_code
20115 {
20116 rtx tmp;
20119 {
20122 /* AVX supports all the needed comparisons. */
20125 /* We have no LTGT as an operator. We could implement it with
20126 NE & ORDERED, but this requires an extra temporary. It's
20127 not clear that it's worth it. */
20134 /* These are supported directly. */
20141 /* AVX has 3 operand comparisons, no need to swap anything. */
20144 /* For commutative operators, try to canonicalize the destination
20145 operand to be first in the comparison - this helps reload to
20146 avoid extra moves. */
20149 /* FALLTHRU */
20155 /* These are not supported directly before AVX, and furthermore
20156 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20157 comparison operands to transform into something that is
20158 supported. */
20167 }
20170 }
20172 /* Detect conditional moves that exactly match min/max operational
20173 semantics. Note that this is IEEE safe, as long as we don't
20174 interchange the operands.
20176 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20177 and TRUE if the operation is successful and instructions are emitted. */
20179 static bool
20182 {
20185 rtx tmp;
20188 ;
20190 {
20194 }
20195 else
20202 else
20207 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20208 but MODE may be a vector mode and thus not appropriate. */
20210 {
20212 rtvec v;
20217 }
20218 else
20219 {
20222 }
20226 }
20228 /* Expand an sse vector comparison. Return the register with the result. */
20230 static rtx
20233 {
20236 rtx x;
20249 {
20252 }
20253 else
20257 }
20259 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20260 operations. This is used for both scalar and vector conditional moves. */
20262 static void
20264 {
20270 {
20272 }
20274 {
20278 }
20280 {
20285 }
20287 {
20291 }
20293 {
20301 op_true,
20302 op_false)));
20303 }
20304 else
20305 {
20314 {
20328 {
20334 }
20349 {
20355 }
20359 }
20363 else
20364 {
20370 else
20382 }
20383 }
20384 }
20386 /* Expand a floating-point conditional move. Return true if successful. */
20388 bool
20390 {
20398 {
20401 /* Since we've no cmove for sse registers, don't force bad register
20402 allocation just to gain access to it. Deny movcc when the
20403 comparison mode doesn't match the move mode. */
20422 }
20429 /* The floating point conditional move instructions don't directly
20430 support conditions resulting from a signed integer comparison. */
20434 {
20439 }
20446 }
20448 /* Expand a floating-point vector conditional move; a vcond operation
20449 rather than a movcc operation. */
20451 bool
20453 {
20455 rtx cmp;
20460 {
20461 rtx temp;
20463 {
20480 }
20482 OPTAB_DIRECT);
20485 }
20495 }
20497 /* Expand a signed/unsigned integral vector conditional move. */
20499 bool
20501 {
20511 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20512 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20521 {
20525 {
20531 }
20534 {
20540 }
20541 }
20550 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20554 ;
20555 else
20556 {
20557 /* Canonicalize the comparison to EQ, GT, GTU. */
20559 {
20576 /* FALLTHRU */
20586 }
20588 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20590 {
20592 {
20594 /* SSE4.1 supports EQ. */
20601 /* SSE4.2 supports GT/GTU. */
20608 }
20609 }
20611 /* Unsigned parallel compare is not supported by the hardware.
20612 Play some tricks to turn this into a signed comparison
20613 against 0. */
20615 {
20619 {
20624 {
20629 {
20636 }
20637 /* Subtract (-(INT MAX) - 1) from both operands to make
20638 them signed. */
20649 }
20656 /* Perform a parallel unsigned saturating subtraction. */
20669 }
20670 }
20671 }
20673 /* Allow the comparison to be done in one mode, but the movcc to
20674 happen in another mode. */
20676 {
20679 }
20680 else
20681 {
20687 }
20692 }
20694 /* Expand a variable vector permutation. */
20696 void
20698 {
20709 /* Number of elements in the vector. */
20715 {
20717 {
20718 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20719 an constant shuffle operand. With a tiny bit of effort we can
20720 use VPERMD instead. A re-interpretation stall for V4DFmode is
20721 unfortunate but there's no avoiding it.
20722 Similarly for V16HImode we don't have instructions for variable
20723 shuffling, while for V32QImode we can use after preparing suitable
20724 masks vpshufb; vpshufb; vpermq; vpor. */
20727 {
20731 }
20732 else
20733 {
20737 }
20740 /* Replicate the low bits of the V4DImode mask into V8SImode:
20741 mask = { A B C D }
20742 t1 = { A A B B C C D D }. */
20750 else
20753 /* Multiply the shuffle indicies by two. */
20755 OPTAB_DIRECT);
20757 /* Add one to the odd shuffle indicies:
20758 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20760 {
20763 }
20767 OPTAB_DIRECT);
20769 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20774 }
20777 {
20779 /* The VPERMD and VPERMPS instructions already properly ignore
20780 the high bits of the shuffle elements. No need for us to
20781 perform an AND ourselves. */
20784 else
20785 {
20791 }
20798 else
20799 {
20805 }
20809 /* By combining the two 128-bit input vectors into one 256-bit
20810 input vector, we can use VPERMD and VPERMPS for the full
20811 two-operand shuffle. */
20843 /* From mask create two adjusted masks, which contain the same
20844 bits as mask in the low 7 bits of each vector element.
20845 The first mask will have the most significant bit clear
20846 if it requests element from the same 128-bit lane
20847 and MSB set if it requests element from the other 128-bit lane.
20848 The second mask will have the opposite values of the MSB,
20849 and additionally will have its 128-bit lanes swapped.
20850 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20851 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20852 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20853 stands for other 12 bytes. */
20854 /* The bit whether element is from the same lane or the other
20855 lane is bit 4, so shift it up by 3 to the MSB position. */
20859 /* Clear MSB bits from the mask just in case it had them set. */
20861 /* After this t1 will have MSB set for elements from other lane. */
20863 /* Clear bits other than MSB. */
20865 /* Or in the lower bits from mask into t3. */
20867 /* And invert MSB bits in t1, so MSB is set for elements from the same
20868 lane. */
20870 /* Swap 128-bit lanes in t3. */
20875 /* And or in the lower bits from mask into t1. */
20878 {
20879 /* Each of these shuffles will put 0s in places where
20880 element from the other 128-bit lane is needed, otherwise
20881 will shuffle in the requested value. */
20884 /* For t3 the 128-bit lanes are swapped again. */
20889 /* And oring both together leads to the result. */
20892 }
20895 /* Similarly to the above one_operand_shuffle code,
20896 just for repeated twice for each operand. merge_two:
20897 code will merge the two results together. */
20919 }
20920 }
20923 {
20924 /* The XOP VPPERM insn supports three inputs. By ignoring the
20925 one_operand_shuffle special case, we avoid creating another
20926 set of constant vectors in memory. */
20929 /* mask = mask & {2*w-1, ...} */
20931 }
20932 else
20933 {
20934 /* mask = mask & {w-1, ...} */
20936 }
20944 /* For non-QImode operations, convert the word permutation control
20945 into a byte permutation control. */
20947 {
20952 /* Convert mask to vector of chars. */
20955 /* Replicate each of the input bytes into byte positions:
20956 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20957 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20958 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20965 else
20968 /* Convert it into the byte positions by doing
20969 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20975 }
20977 /* The actual shuffle operations all operate on V16QImode. */
20983 {
20985 }
20987 {
20989 }
20990 else
20991 {
20995 /* Shuffle the two input vectors independently. */
21001 merge_two:
21002 /* Then merge them together. The key is whether any given control
21003 element contained a bit set that indicates the second word. */
21007 {
21008 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21009 more shuffle to convert the V2DI input mask into a V4SI
21010 input mask. At which point the masking that expand_int_vcond
21011 will work as desired. */
21019 }
21036 }
21037 }
21039 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21040 true if we should do zero extension, else sign extension. HIGH_P is
21041 true if we want the N/2 high elements, else the low elements. */
21043 void
21045 {
21047 rtx tmp;
21050 {
21056 {
21060 else
21063 extract
21069 else
21072 extract
21078 else
21081 extract
21087 else
21093 else
21099 else
21104 }
21107 {
21110 }
21112 {
21113 /* Shift higher 8 bytes to lower 8 bytes. */
21118 }
21119 else
21123 }
21124 else
21125 {
21129 {
21133 else
21139 else
21145 else
21150 }
21154 else
21159 }
21160 }
21162 /* Expand conditional increment or decrement using adb/sbb instructions.
21163 The default case using setcc followed by the conditional move can be
21164 done by generic code. */
21165 bool
21167 {
21169 rtx flags;
21171 rtx compare_op;
21189 {
21192 }
21195 {
21199 reverse_condition_maybe_unordered
21201 else
21203 }
21207 /* Construct either adc or sbb insn. */
21209 {
21211 {
21226 }
21227 }
21228 else
21229 {
21231 {
21246 }
21247 }
21251 }
21254 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
21255 but works for floating pointer parameters and nonoffsetable memories.
21256 For pushes, it returns just stack offsets; the values will be saved
21257 in the right order. Maximally three parts are generated. */
21259 static int
21261 {
21266 else
21272 /* Optimize constant pool reference to immediates. This is used by fp
21273 moves, that force all constants to memory to allow combining. */
21275 {
21279 }
21282 {
21283 /* The only non-offsetable memories we handle are pushes. */
21292 }
21295 {
21297 /* Caution: if we looked through a constant pool memory above,
21298 the operand may actually have a different mode now. That's
21299 ok, since we want to pun this all the way back to an integer. */
21303 }
21306 {
21309 else
21310 {
21314 {
21318 }
21320 {
21325 }
21327 {
21328 REAL_VALUE_TYPE r;
21333 {
21340 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21341 long double may not be 80-bit. */
21350 }
21353 }
21354 else
21356 }
21357 }
21358 else
21359 {
21363 {
21366 {
21370 }
21372 {
21376 }
21378 {
21379 REAL_VALUE_TYPE r;
21385 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21388 = gen_int_mode
21391 DImode);
21392 else
21399 = gen_int_mode
21402 DImode);
21403 else
21405 }
21406 else
21408 }
21409 }
21412 }
21414 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21415 Return false when normal moves are needed; true when all required
21416 insns have been emitted. Operands 2-4 contain the input values
21417 int the correct order; operands 5-7 contain the output values. */
21419 void
21421 {
21429 /* The DFmode expanders may ask us to move double.
21430 For 64bit target this is single move. By hiding the fact
21431 here we simplify i386.md splitters. */
21433 {
21434 /* Optimize constant pool reference to immediates. This is used by
21435 fp moves, that force all constants to memory to allow combining. */
21442 {
21445 }
21446 else
21451 }
21453 /* The only non-offsettable memory we handle is push. */
21456 else
21463 /* When emitting push, take care for source operands on the stack. */
21466 {
21469 /* Compensate for the stack decrement by 4. */
21474 /* src_base refers to the stack pointer and is
21475 automatically decreased by emitted push. */
21479 }
21481 /* We need to do copy in the right order in case an address register
21482 of the source overlaps the destination. */
21484 {
21485 rtx tmp;
21488 {
21492 collisions++;
21493 }
21495 /* Collision in the middle part can be handled by reordering. */
21497 {
21500 }
21504 {
21506 {
21509 }
21510 else
21511 {
21514 }
21515 }
21517 /* If there are more collisions, we can't handle it by reordering.
21518 Do an lea to the last part and use only one colliding move. */
21520 {
21521 rtx base;
21527 /* Handle the case when the last part isn't valid for lea.
21528 Happens in 64-bit mode storing the 12-byte XFmode. */
21535 {
21538 }
21539 }
21540 }
21543 {
21545 {
21547 {
21552 }
21554 {
21557 }
21558 }
21559 else
21560 {
21561 /* In 64bit mode we don't have 32bit push available. In case this is
21562 register, it is OK - we will just use larger counterpart. We also
21563 retype memory - these comes from attempt to avoid REX prefix on
21564 moving of second half of TFmode value. */
21566 {
21568 {
21579 }
21583 }
21584 }
21588 }
21590 /* Choose correct order to not overwrite the source before it is copied. */
21600 {
21602 {
21605 }
21606 }
21607 else
21608 {
21610 {
21613 }
21614 }
21616 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21618 {
21627 }
21633 }
21635 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21636 left shift by a constant, either using a single shift or
21637 a sequence of add instructions. */
21639 static void
21641 {
21647 {
21651 }
21652 else
21653 {
21656 }
21657 }
21659 void
21661 {
21670 {
21675 {
21681 }
21682 else
21683 {
21691 }
21693 }
21700 {
21701 /* Assuming we've chosen a QImode capable registers, then 1 << N
21702 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21704 {
21720 }
21722 /* Otherwise, we can get the same results by manually performing
21723 a bit extract operation on bit 5/6, and then performing the two
21724 shifts. The two methods of getting 0/1 into low/high are exactly
21725 the same size. Avoiding the shift in the bit extract case helps
21726 pentium4 a bit; no one else seems to care much either way. */
21727 else
21728 {
21733 HOST_WIDE_INT bits;
21734 rtx x;
21737 {
21743 }
21744 else
21745 {
21751 }
21755 else
21763 }
21768 }
21771 {
21772 /* For -1 << N, we can avoid the shld instruction, because we
21773 know that we're shifting 0...31/63 ones into a -1. */
21777 else
21779 }
21780 else
21781 {
21789 }
21794 {
21800 }
21801 else
21802 {
21807 }
21808 }
21810 void
21812 {
21822 {
21827 {
21833 }
21835 {
21844 }
21845 else
21846 {
21854 }
21855 }
21856 else
21857 {
21869 {
21877 scratch));
21878 }
21879 else
21880 {
21885 }
21886 }
21887 }
21889 void
21891 {
21901 {
21906 {
21913 }
21914 else
21915 {
21923 }
21924 }
21925 else
21926 {
21938 {
21944 scratch));
21945 }
21946 else
21947 {
21952 }
21953 }
21954 }
21956 /* Predict just emitted jump instruction to be taken with probability PROB. */
21957 static void
21959 {
21963 }
21965 /* Helper function for the string operations below. Dest VARIABLE whether
21966 it is aligned to VALUE bytes. If true, jump to the label. */
21967 static rtx
21969 {
21974 else
21980 else
21983 }
21985 /* Adjust COUNTER by the VALUE. */
21986 static void
21988 {
21993 }
21995 /* Zero extend possibly SImode EXP to Pmode register. */
21996 rtx
21998 {
22000 }
22002 /* Divide COUNTREG by SCALE. */
22003 static rtx
22005 {
22006 rtx sc;
22018 }
22020 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22021 DImode for constant loop counts. */
22023 static enum machine_mode
22025 {
22033 }
22035 /* When SRCPTR is non-NULL, output simple loop to move memory
22036 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
22037 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
22038 equivalent loop to set memory by VALUE (supposed to be in MODE).
22040 The size is rounded down to whole number of chunk size moved at once.
22041 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
22044 static void
22049 {
22055 rtx size;
22064 /* Those two should combine. */
22066 {
22070 }
22077 /* This assert could be relaxed - in this case we'll need to compute
22078 smallest power of two, containing in PIECE_SIZE_N and pass it to
22079 offset_address. */
22085 {
22089 /* When unrolling for chips that reorder memory reads and writes,
22090 we can save registers by using single temporary.
22091 Also using 4 temporaries is overkill in 32bit mode. */
22093 {
22095 {
22097 {
22098 destmem =
22100 srcmem =
22102 }
22104 }
22105 }
22106 else
22107 {
22111 {
22114 {
22115 srcmem =
22117 }
22119 }
22121 {
22123 {
22124 destmem =
22126 }
22128 }
22129 }
22130 }
22131 else
22133 {
22135 destmem =
22138 }
22148 {
22154 else
22156 }
22157 else
22165 {
22170 }
22172 }
22174 /* Output "rep; mov" instruction.
22175 Arguments have same meaning as for previous function */
22176 static void
22179 rtx count,
22181 {
22182 rtx destexp;
22183 rtx srcexp;
22184 rtx countreg;
22185 HOST_WIDE_INT rounded_count;
22187 /* If the size is known, it is shorter to use rep movs. */
22198 {
22205 }
22206 else
22207 {
22210 }
22212 {
22219 }
22220 else
22221 {
22226 }
22229 }
22231 /* Output "rep; stos" instruction.
22232 Arguments have same meaning as for previous function */
22233 static void
22236 rtx orig_value)
22237 {
22238 rtx destexp;
22239 rtx countreg;
22240 HOST_WIDE_INT rounded_count;
22247 {
22251 }
22252 else
22255 {
22260 }
22264 }
22266 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
22267 DESTMEM.
22268 SRC is passed by pointer to be updated on return.
22269 Return value is updated DST. */
22270 static rtx
22272 HOST_WIDE_INT size_to_move)
22273 {
22279 /* Find the widest mode in which we could perform moves.
22280 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
22281 it until move of such size is supported. */
22286 {
22290 }
22292 /* Find the corresponding vector mode with the same size as MOVE_MODE.
22293 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
22295 {
22300 {
22304 }
22305 }
22311 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
22315 {
22316 /* We move from memory to memory, so we'll need to do it via
22317 a temporary register. */
22328 piece_size);
22330 piece_size);
22331 }
22333 /* Update DST and SRC rtx. */
22336 }
22338 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
22339 static void
22342 {
22345 {
22350 /* For now MAX_SIZE should be a power of 2. This assert could be
22351 relaxed, but it'll require a bit more complicated epilogue
22352 expanding. */
22355 {
22358 }
22360 }
22362 {
22368 }
22370 /* When there are stringops, we can cheaply increase dest and src pointers.
22371 Otherwise we save code size by maintaining offset (zero is readily
22372 available from preceding rep operation) and using x86 addressing modes.
22373 */
22375 {
22377 {
22384 }
22386 {
22393 }
22395 {
22402 }
22403 }
22404 else
22405 {
22407 rtx tmp;
22410 {
22421 }
22423 {
22436 }
22438 {
22447 }
22448 }
22449 }
22451 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22452 static void
22455 {
22456 count =
22462 }
22464 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22465 static void
22467 {
22468 rtx dest;
22471 {
22476 {
22478 {
22483 }
22484 else
22487 }
22489 {
22491 {
22494 }
22495 else
22496 {
22501 }
22503 }
22505 {
22509 }
22511 {
22515 }
22517 {
22521 }
22523 }
22525 {
22528 }
22530 {
22533 {
22537 }
22538 else
22539 {
22545 }
22548 }
22550 {
22553 {
22556 }
22557 else
22558 {
22562 }
22565 }
22567 {
22573 }
22575 {
22581 }
22583 {
22589 }
22590 }
22592 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22593 DESIRED_ALIGNMENT.
22594 Return value is updated DESTMEM. */
22595 static rtx
22599 {
22602 {
22604 {
22611 }
22612 }
22614 }
22616 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22617 ALIGN_BYTES is how many bytes need to be copied.
22618 The function updates DST and SRC, namely, it sets proper alignment.
22619 DST is returned via return value, SRC is updated via pointer SRCP. */
22620 static rtx
22623 {
22636 {
22638 {
22641 }
22642 }
22647 {
22650 {
22654 }
22659 }
22666 }
22668 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22669 DESIRED_ALIGNMENT. */
22670 static void
22673 {
22675 {
22682 }
22684 {
22691 }
22693 {
22700 }
22702 }
22704 /* Set enough from DST to align DST known to by aligned by ALIGN to
22705 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22706 static rtx
22709 {
22713 {
22718 }
22720 {
22727 }
22729 {
22736 }
22743 }
22745 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22746 static enum stringop_alg
22749 {
22752 /* Algorithms using the rep prefix want at least edi and ecx;
22753 additionally, memset wants eax and memcpy wants esi. Don't
22754 consider such algorithms if the user has appropriated those
22755 registers for their own purposes. */
22757 || (memset
22761 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22762 || (alg != rep_prefix_1_byte \
22763 && alg != rep_prefix_4_byte \
22764 && alg != rep_prefix_8_byte))
22767 /* Even if the string operation call is cold, we still might spend a lot
22768 of time processing large blocks. */
22773 else
22781 else
22785 /* rep; movq or rep; movl is the smallest variant. */
22787 {
22790 else
22792 }
22793 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22794 */
22798 {
22802 {
22803 /* We get here if the algorithms that were not libcall-based
22804 were rep-prefix based and we are unable to use rep prefixes
22805 based on global register usage. Break out of the loop and
22806 use the heuristic below. */
22810 {
22815 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22816 last non-libcall inline algorithm. */
22818 {
22819 /* When the current size is best to be copied by a libcall,
22820 but we are still forced to inline, run the heuristic below
22821 that will pick code for medium sized blocks. */
22825 }
22827 {
22830 }
22831 }
22832 }
22834 }
22835 /* When asked to inline the call anyway, try to pick meaningful choice.
22836 We look for maximal size of block that is faster to copy by hand and
22837 take blocks of at most of that size guessing that average size will
22838 be roughly half of the block.
22840 If this turns out to be bad, we might simply specify the preferred
22841 choice in ix86_costs. */
22844 {
22851 {
22858 }
22859 /* If there aren't any usable algorithms, then recursing on
22860 smaller sizes isn't going to find anything. Just return the
22861 simple byte-at-a-time copy loop. */
22863 {
22864 /* Pick something reasonable. */
22868 }
22877 }
22879 #undef ALG_USABLE_P
22880 }
22882 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22883 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22884 static int
22889 {
22900 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22901 copying whole cacheline at once. */
22914 }
22916 /* Expand string move (memcpy) operation. Use i386 string operations
22917 when profitable. expand_setmem contains similar code. The code
22918 depends upon architecture, block size and alignment, but always has
22919 the same overall structure:
22921 1) Prologue guard: Conditional that jumps up to epilogues for small
22922 blocks that can be handled by epilogue alone. This is faster
22923 but also needed for correctness, since prologue assume the block
22924 is larger than the desired alignment.
22926 Optional dynamic check for size and libcall for large
22927 blocks is emitted here too, with -minline-stringops-dynamically.
22929 2) Prologue: copy first few bytes in order to get destination
22930 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22931 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22932 copied. We emit either a jump tree on power of two sized
22933 blocks, or a byte loop.
22935 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22936 with specified algorithm.
22938 4) Epilogue: code copying tail of the block that is too small to be
22939 handled by main body (or up to size guarded by prologue guard). */
22941 bool
22944 {
22945 rtx destreg;
22946 rtx srcreg;
22948 rtx tmp;
22964 /* i386 can do misaligned access on reasonably increased cost. */
22968 /* ALIGN is the minimum of destination and source alignment, but we care here
22969 just about destination alignment. */
22978 /* Make sure we don't need to care about overflow later on. */
22982 /* Step 0: Decide on preferred algorithm, desired alignment and
22983 size of chunks to be copied by main loop. */
22997 {
23016 /* Find the widest supported mode. */
23022 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23023 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23025 {
23030 }
23042 }
23050 /* Step 1: Prologue guard. */
23052 /* Alignment code needs count to be in register. */
23054 {
23057 {
23058 align_bytes
23062 else
23064 }
23067 }
23070 /* Ensure that alignment prologue won't copy past end of block. */
23072 {
23074 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
23075 Make sure it is power of 2. */
23079 {
23081 {
23082 /* If main algorithm works on QImode, no epilogue is needed.
23083 For small sizes just don't align anything. */
23086 else
23088 }
23089 }
23090 else
23091 {
23098 else
23100 }
23101 }
23103 /* Emit code to decide on runtime whether library call or inline should be
23104 used. */
23106 {
23108 {
23110 {
23114 }
23115 }
23116 else
23117 {
23126 }
23127 }
23129 /* Step 2: Alignment prologue. */
23132 {
23134 {
23135 /* Except for the first move in epilogue, we no longer know
23136 constant offset in aliasing info. It don't seems to worth
23137 the pain to maintain it for the first move, so throw away
23138 the info early. */
23142 desired_align);
23143 }
23144 else
23145 {
23146 /* If we know how many bytes need to be stored before dst is
23147 sufficiently aligned, maintain aliasing info accurately. */
23153 }
23159 {
23160 /* It is possible that we copied enough so the main loop will not
23161 execute. */
23171 else
23173 }
23174 }
23176 {
23181 }
23185 /* Step 3: Main loop. */
23188 {
23199 expected_size);
23205 move_mode);
23207 }
23208 /* Adjust properly the offset of src and dest memory for aliasing. */
23210 {
23215 }
23216 else
23217 {
23220 }
23222 /* Step 4: Epilogue to copy the remaining bytes. */
23223 epilogue:
23225 {
23226 /* When the main loop is done, COUNT_EXP might hold original count,
23227 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23228 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23229 bytes. Compensate if needed. */
23232 {
23233 tmp =
23236 OPTAB_DIRECT);
23239 }
23242 }
23246 epilogue_size_needed);
23250 }
23252 /* Helper function for memcpy. For QImode value 0xXY produce
23253 0xXYXYXYXY of wide specified by MODE. This is essentially
23254 a * 0x10101010, but we can do slightly better than
23255 synth_mult by unwinding the sequence by hand on CPUs with
23256 slow multiply. */
23257 static rtx
23259 {
23261 rtx tmp;
23268 {
23276 }
23285 nops--;
23290 {
23294 OPTAB_DIRECT);
23295 }
23296 else
23297 {
23303 else
23305 else
23306 {
23309 reg =
23311 }
23321 }
23322 }
23324 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23325 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23326 alignment from ALIGN to DESIRED_ALIGN. */
23327 static rtx
23329 {
23330 rtx promoted_val;
23339 else
23343 }
23345 /* Expand string clear operation (bzero). Use i386 string operations when
23346 profitable. See expand_movmem comment for explanation of individual
23347 steps performed. */
23348 bool
23351 {
23352 rtx destreg;
23354 rtx tmp;
23372 /* i386 can do misaligned access on reasonably increased cost. */
23381 /* Make sure we don't need to care about overflow later on. */
23385 /* Step 0: Decide on preferred algorithm, desired alignment and
23386 size of chunks to be copied by main loop. */
23400 {
23426 }
23434 /* Step 1: Prologue guard. */
23436 /* Alignment code needs count to be in register. */
23438 {
23441 {
23442 align_bytes
23446 else
23448 }
23450 {
23455 }
23456 }
23457 /* Do the cheap promotion to allow better CSE across the
23458 main loop and epilogue (ie one load of the big constant in the
23459 front of all code. */
23463 /* Ensure that alignment prologue won't copy past end of block. */
23465 {
23467 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23468 Make sure it is power of 2. */
23471 /* To improve performance of small blocks, we jump around the VAL
23472 promoting mode. This mean that if the promoted VAL is not constant,
23473 we might not use it in the epilogue and have to use byte
23474 loop variant. */
23478 {
23480 {
23481 /* If main algorithm works on QImode, no epilogue is needed.
23482 For small sizes just don't align anything. */
23485 else
23487 }
23488 }
23489 else
23490 {
23497 else
23499 }
23500 }
23502 {
23511 }
23513 /* Step 2: Alignment prologue. */
23515 /* Do the expensive promotion once we branched off the small blocks. */
23522 {
23524 {
23525 /* Except for the first move in epilogue, we no longer know
23526 constant offset in aliasing info. It don't seems to worth
23527 the pain to maintain it for the first move, so throw away
23528 the info early. */
23531 desired_align);
23532 }
23533 else
23534 {
23535 /* If we know how many bytes need to be stored before dst is
23536 sufficiently aligned, maintain aliasing info accurately. */
23542 }
23548 {
23549 /* It is possible that we copied enough so the main loop will not
23550 execute. */
23560 else
23562 }
23563 }
23565 {
23571 }
23575 /* Step 3: Main loop. */
23578 {
23589 expected_size);
23603 }
23604 /* Adjust properly the offset of src and dest memory for aliasing. */
23608 else
23611 /* Step 4: Epilogue to copy the remaining bytes. */
23614 {
23615 /* When the main loop is done, COUNT_EXP might hold original count,
23616 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23617 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23618 bytes. Compensate if needed. */
23621 {
23622 tmp =
23625 OPTAB_DIRECT);
23628 }
23631 }
23632 epilogue:
23634 {
23637 epilogue_size_needed);
23638 else
23640 epilogue_size_needed);
23641 }
23645 }
23647 /* Expand the appropriate insns for doing strlen if not just doing
23648 repnz; scasb
23650 out = result, initialized with the start address
23651 align_rtx = alignment of the address.
23652 scratch = scratch register, initialized with the startaddress when
23653 not aligned, otherwise undefined
23655 This is just the body. It needs the initializations mentioned above and
23656 some address computing at the end. These things are done in i386.md. */
23658 static void
23660 {
23662 rtx tmp;
23667 rtx mem;
23670 rtx cmp;
23676 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23678 /* Is there a known alignment and is it less than 4? */
23680 {
23683 /* Is there a known alignment and is it not 2? */
23685 {
23689 /* Leave just the 3 lower bits. */
23699 }
23700 else
23701 {
23702 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23703 check if is aligned to 4 - byte. */
23710 }
23714 /* Now compare the bytes. */
23716 /* Compare the first n unaligned byte on a byte per byte basis. */
23720 /* Increment the address. */
23723 /* Not needed with an alignment of 2 */
23725 {
23729 end_0_label);
23734 }
23737 end_0_label);
23740 }
23742 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23743 align this loop. It gives only huge programs, but does not help to
23744 speed up. */
23751 /* This formula yields a nonzero result iff one of the bytes is zero.
23752 This saves three branches inside loop and many cycles. */
23760 align_4_label);
23763 {
23769 /* If zero is not in the first two bytes, move two bytes forward. */
23775 reg,
23776 tmpreg)));
23777 /* Emit lea manually to avoid clobbering of flags. */
23785 reg2,
23786 out)));
23787 }
23788 else
23789 {
23791 /* Is zero in the first two bytes? */
23798 pc_rtx);
23802 /* Not in the first two. Move two bytes forward. */
23808 }
23810 /* Avoid branch in fixing the byte. */
23818 }
23820 /* Expand strlen. */
23822 bool
23824 {
23827 /* The generic case of strlen expander is long. Avoid it's
23828 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23831 && !TARGET_INLINE_ALL_STRINGOPS
23841 {
23842 /* Well it seems that some optimizer does not combine a call like
23843 foo(strlen(bar), strlen(bar));
23844 when the move and the subtraction is done here. It does calculate
23845 the length just once when these instructions are done inside of
23846 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23847 often used and I use one fewer register for the lifetime of
23848 output_strlen_unroll() this is better. */
23854 /* strlensi_unroll_1 returns the address of the zero at the end of
23855 the string, like memchr(), so compute the length by subtracting
23856 the start address. */
23858 }
23859 else
23860 {
23861 rtx unspec;
23863 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23876 /* If .md starts supporting :P, this can be done in .md. */
23882 }
23884 }
23886 /* For given symbol (function) construct code to compute address of it's PLT
23887 entry in large x86-64 PIC model. */
23888 static rtx
23890 {
23903 }
23905 rtx
23907 rtx callarg2,
23909 {
23910 unsigned int const cregs_size
23921 {
23922 #if TARGET_MACHO
23925 #endif
23926 }
23927 else
23928 {
23929 /* Static functions and indirect calls don't need the pic register. */
23931 && (!TARGET_64BIT
23937 }
23940 {
23944 }
23947 && !TARGET_PECOFF
23955 {
23958 }
23966 {
23970 }
23974 {
23978 UNSPEC_MS_TO_SYSV_CALL);
23981 {
23987 }
23988 }
23997 }
23999 /* Output the assembly for a call instruction. */
24003 {
24009 {
24012 /* SEH epilogue detection requires the indirect branch case
24013 to include REX.W. */
24016 else
24021 }
24023 /* SEH unwinding can require an extra nop to be emitted in several
24024 circumstances. Determine if we have one of those. */
24026 {
24027 rtx i;
24030 {
24031 /* If we get to another real insn, we don't need the nop. */
24035 /* If we get to the epilogue note, prevent a catch region from
24036 being adjacent to the standard epilogue sequence. If non-
24037 call-exceptions, we'll have done this during epilogue emission. */
24039 && !flag_non_call_exceptions
24041 {
24044 }
24045 }
24047 /* If we didn't find a real insn following the call, prevent the
24048 unwinder from looking into the next function. */
24051 }
24055 else
24064 }
24065 \f
24066 /* Clear stack slot assignments remembered from previous functions.
24067 This is called from INIT_EXPANDERS once before RTL is emitted for each
24068 function. */
24072 {
24080 }
24082 /* Return a MEM corresponding to a stack slot with mode MODE.
24083 Allocate a new slot if necessary.
24085 The RTL for a function can have several slots available: N is
24086 which slot to use. */
24088 rtx
24090 {
24107 }
24109 static void
24111 {
24117 }
24118 \f
24119 /* Calculate the length of the memory address in the instruction encoding.
24120 Includes addr32 prefix, does not include the one-byte modrm, opcode,
24121 or other prefixes. We never generate addr32 prefix for LEA insn. */
24123 int
24125 {
24142 /* If this is not LEA instruction, add the length of addr32 prefix. */
24147 len++;
24161 /* Rule of thumb:
24162 - esp as the base always wants an index,
24163 - ebp as the base always wants a displacement,
24164 - r12 as the base always wants an index,
24165 - r13 as the base always wants a displacement. */
24167 /* Register Indirect. */
24169 {
24170 /* esp (for its index) and ebp (for its displacement) need
24171 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
24172 code. */
24179 len++;
24180 }
24182 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
24183 is not disp32, but disp32(%rip), so for disp32
24184 SIB byte is needed, unless print_operand_address
24185 optimizes it into disp32(%rip) or (%rip) is implied
24186 by UNSPEC. */
24188 {
24191 {
24207 len++;
24208 }
24209 }
24210 else
24211 {
24212 /* Find the length of the displacement constant. */
24214 {
24217 else
24219 }
24220 /* ebp always wants a displacement. Similarly r13. */
24222 len++;
24224 /* An index requires the two-byte modrm form.... */
24226 /* ...like esp (or r12), which always wants an index. */
24230 len++;
24231 }
24234 }
24236 /* Compute default value for "length_immediate" attribute. When SHORTFORM
24237 is set, expect that insn have 8bit immediate alternative. */
24238 int
24240 {
24246 {
24251 {
24254 {
24266 }
24268 {
24271 }
24272 }
24274 {
24284 /* Immediates for DImode instructions are encoded
24285 as 32bit sign extended values. */
24291 }
24292 }
24294 }
24296 /* Compute default value for "length_address" attribute. */
24297 int
24299 {
24303 {
24314 }
24319 {
24322 {
24327 constraints++;
24330 ;
24331 /* Skip ignored operands. */
24334 }
24336 }
24338 }
24340 /* Compute default value for "length_vex" attribute. It includes
24341 2 or 3 byte VEX prefix and 1 opcode byte. */
24343 int
24345 {
24348 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24349 byte VEX prefix. */
24353 /* We can always use 2 byte VEX prefix in 32bit. */
24361 {
24362 /* REX.W bit uses 3 byte VEX prefix. */
24366 }
24367 else
24368 {
24369 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24373 }
24376 }
24377 \f
24378 /* Return the maximum number of instructions a cpu can issue. */
24380 static int
24382 {
24384 {
24410 }
24411 }
24413 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24414 by DEP_INSN and nothing set by DEP_INSN. */
24416 static bool
24418 {
24421 /* Simplify the test for uninteresting insns. */
24429 {
24432 }
24437 {
24440 }
24441 else
24447 /* This test is true if the dependent insn reads the flags but
24448 not any other potentially set register. */
24456 }
24458 /* Return true iff USE_INSN has a memory address with operands set by
24459 SET_INSN. */
24461 bool
24463 {
24468 {
24471 }
24473 }
24475 /* Helper function for exact_store_load_dependency.
24476 Return true if addr is found in insn. */
24477 static bool
24479 {
24486 {
24492 CASE_CONST_ANY:
24501 }
24505 {
24507 {
24517 }
24518 }
24520 }
24522 /* Return true if there exists exact dependency for store & load, i.e.
24523 the same memory address is used in them. */
24524 static bool
24526 {
24540 }
24542 static int
24544 {
24550 /* Anti and output dependencies have zero cost on all CPUs. */
24556 /* If we can't recognize the insns, we can't really do anything. */
24564 {
24566 /* Address Generation Interlock adds a cycle of latency. */
24568 {
24579 }
24583 /* ??? Compares pair with jump/setcc. */
24587 /* Floating point stores require value to be ready one cycle earlier. */
24597 /* INT->FP conversion is expensive. */
24601 /* There is one cycle extra latency between an FP op and a store. */
24609 /* Show ability of reorder buffer to hide latency of load by executing
24610 in parallel with previous instruction in case
24611 previous instruction is not needed to compute the address. */
24614 {
24615 /* Claim moves to take one cycle, as core can issue one load
24616 at time and the next load can start cycle later. */
24621 cost--;
24622 }
24628 /* The esp dependency is resolved before the instruction is really
24629 finished. */
24634 /* INT->FP conversion is expensive. */
24638 /* Show ability of reorder buffer to hide latency of load by executing
24639 in parallel with previous instruction in case
24640 previous instruction is not needed to compute the address. */
24643 {
24644 /* Claim moves to take one cycle, as core can issue one load
24645 at time and the next load can start cycle later. */
24651 else
24653 }
24668 /* Show ability of reorder buffer to hide latency of load by executing
24669 in parallel with previous instruction in case
24670 previous instruction is not needed to compute the address. */
24673 {
24677 /* Because of the difference between the length of integer and
24678 floating unit pipeline preparation stages, the memory operands
24679 for floating point are cheaper.
24681 ??? For Athlon it the difference is most probably 2. */
24684 else
24689 else
24691 }
24698 /* Increase cost of integer loads. */
24701 {
24704 {
24707 else
24708 {
24709 /* Increase cost of ld/st for short int types only
24710 because of store forwarding issue. */
24714 {
24715 /* Increase cost of store/load insn if exact
24716 dependence exists and it is load insn. */
24721 }
24722 }
24723 }
24724 }
24728 }
24731 }
24733 /* How many alternative schedules to try. This should be as wide as the
24734 scheduling freedom in the DFA, but no wider. Making this value too
24735 large results extra work for the scheduler. */
24737 static int
24739 {
24741 {
24754 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24755 as many instructions can be executed on a cycle, i.e.,
24756 issue_rate. I wonder why tuning for many CPUs does not do this. */
24759 /* Don't use lookahead for pre-reload schedule to save compile time. */
24764 }
24765 }
24767 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24768 execution. It is applied if
24769 (1) IMUL instruction is on the top of list;
24770 (2) There exists the only producer of independent IMUL instruction in
24771 ready list.
24772 Return index of IMUL producer if it was found and -1 otherwise. */
24773 static int
24775 {
24777 sd_iterator_def sd_it;
24778 dep_t dep;
24785 /* Check that IMUL instruction is on the top of ready list. */
24794 /* Search for producer of independent IMUL instruction. */
24796 {
24800 /* Skip IMUL instruction. */
24810 {
24811 rtx con;
24822 {
24823 sd_iterator_def sd_it1;
24824 dep_t dep1;
24825 /* Check if there is no other dependee for IMUL. */
24828 {
24829 rtx pro;
24835 }
24838 }
24839 }
24842 }
24844 }
24846 /* Try to find the best candidate on the top of ready list if two insns
24847 have the same priority - candidate is best if its dependees were
24848 scheduled earlier. Applied for Silvermont only.
24849 Return true if top 2 insns must be interchanged. */
24850 static bool
24852 {
24855 rtx set;
24856 sd_iterator_def sd_it;
24857 dep_t dep;
24860 #define INSN_TICK(INSN) (HID (INSN)->tick)
24881 {
24884 /* Determine winner more precise. */
24886 {
24887 rtx pro;
24893 }
24895 {
24896 rtx pro;
24902 }
24905 {
24906 /* Determine winner - load must win. */
24912 }
24914 }
24916 #undef INSN_TICK
24917 }
24919 /* Perform possible reodering of ready list for Atom/Silvermont only.
24920 Return issue rate. */
24921 static int
24924 {
24928 rtx insn;
24931 /* Set up issue rate. */
24934 /* Do reodering for Atom/SLM only. */
24938 /* Nothing to do if ready list contains only 1 instruction. */
24942 /* Do reodering for post-reload scheduler only. */
24947 {
24952 /* Put IMUL producer (ready[index]) at the top of ready list. */
24958 }
24960 {
24964 /* Swap 2 top elements of ready list. */
24968 }
24970 }
24972 static bool
24975 /* Returns true if lhs of insn is HW function argument register and set up
24976 is_spilled to true if it is likely spilled HW register. */
24977 static bool
24979 {
24980 rtx dst;
24984 /* Call instructions are not movable, ignore it. */
24995 {
24996 /* Is it likely spilled HW register? */
25001 }
25003 }
25005 /* Add output dependencies for chain of function adjacent arguments if only
25006 there is a move to likely spilled HW register. Return first argument
25007 if at least one dependence was added or NULL otherwise. */
25008 static rtx
25010 {
25011 rtx insn;
25018 /* Find nearest to call argument passing instruction. */
25020 {
25029 }
25033 {
25040 {
25043 }
25045 {
25046 /* Add output depdendence between two function arguments if chain
25047 of output arguments contains likely spilled HW registers. */
25051 }
25052 else
25054 }
25058 }
25060 /* Add output or anti dependency from insn to first_arg to restrict its code
25061 motion. */
25062 static void
25064 {
25065 rtx set;
25066 rtx tmp;
25073 {
25074 /* Add output dependency to the first function argument. */
25077 }
25078 /* Add anti dependency. */
25080 }
25082 /* Avoid cross block motion of function argument through adding dependency
25083 from the first non-jump instruction in bb. */
25084 static void
25086 {
25090 {
25092 {
25095 {
25098 }
25099 }
25103 }
25104 }
25106 /* Hook for pre-reload schedule - avoid motion of function arguments
25107 passed in likely spilled HW registers. */
25108 static void
25110 {
25111 rtx insn;
25119 {
25122 {
25123 /* Add dependee for first argument to predecessors if only
25124 region contains more than one block. */
25128 /* Skip trivial regions and region head blocks that can have
25129 predecessors outside of region. */
25131 {
25132 edge e;
25133 edge_iterator ei;
25134 /* Assume that region is SCC, i.e. all immediate predecessors
25135 of non-head block are in the same region. */
25137 {
25138 /* Avoid creating of loop-carried dependencies through
25139 using topological odering in region. */
25142 }
25143 }
25147 }
25148 }
25151 }
25153 /* Hook for pre-reload schedule - set priority of moves from likely spilled
25154 HW registers to maximum, to schedule them at soon as possible. These are
25155 moves from function argument registers at the top of the function entry
25156 and moves from function return value registers after call. */
25157 static int
25159 {
25160 rtx set;
25170 {
25177 }
25180 }
25182 /* Model decoder of Core 2/i7.
25183 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
25184 track the instruction fetch block boundaries and make sure that long
25185 (9+ bytes) instructions are assigned to D0. */
25187 /* Maximum length of an insn that can be handled by
25188 a secondary decoder unit. '8' for Core 2/i7. */
25191 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
25192 '16' for Core 2/i7. */
25195 /* Maximum number of instructions decoder can handle per cycle.
25196 '6' for Core 2/i7. */
25200 ix86_first_cycle_multipass_data_t;
25202 const_ix86_first_cycle_multipass_data_t;
25204 /* A variable to store target state across calls to max_issue within
25205 one cycle. */
25209 /* Initialize DATA. */
25210 static void
25212 {
25213 ix86_first_cycle_multipass_data_t data
25220 }
25222 /* Advancing the cycle; reset ifetch block counts. */
25223 static void
25225 {
25232 }
25236 /* Filter out insns from ready_try that the core will not be able to issue
25237 on current cycle due to decoder. */
25238 static void
25239 core2i7_first_cycle_multipass_filter_ready_try
25242 {
25244 {
25245 rtx insn;
25255 (!first_cycle_insn_p
25257 /* ... or it would not fit into the ifetch block ... */
25259 /* ... or the decoder is full already ... */
25261 /* ... mask the insn out. */
25262 {
25267 }
25268 }
25269 }
25271 /* Prepare for a new round of multipass lookahead scheduling. */
25272 static void
25275 {
25276 ix86_first_cycle_multipass_data_t data
25278 const_ix86_first_cycle_multipass_data_t prev_data
25281 /* Restore the state from the end of the previous round. */
25285 /* Filter instructions that cannot be issued on current cycle due to
25286 decoder restrictions. */
25288 first_cycle_insn_p);
25289 }
25291 /* INSN is being issued in current solution. Account for its impact on
25292 the decoder model. */
25293 static void
25296 {
25297 ix86_first_cycle_multipass_data_t data
25299 const_ix86_first_cycle_multipass_data_t prev_data
25309 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
25311 {
25314 }
25316 {
25320 }
25323 /* Filter out insns from ready_try that the core will not be able to issue
25324 on current cycle due to decoder. */
25327 }
25329 /* Revert the effect on ready_try. */
25330 static void
25334 {
25335 const_ix86_first_cycle_multipass_data_t data
25338 sbitmap_iterator sbi;
25342 {
25344 }
25345 }
25347 /* Save the result of multipass lookahead scheduling for the next round. */
25348 static void
25350 {
25351 const_ix86_first_cycle_multipass_data_t data
25353 ix86_first_cycle_multipass_data_t next_data
25357 {
25360 }
25361 }
25363 /* Deallocate target data. */
25364 static void
25366 {
25367 ix86_first_cycle_multipass_data_t data
25371 {
25375 }
25376 }
25378 /* Prepare for scheduling pass. */
25379 static void
25383 {
25384 /* Install scheduling hooks for current CPU. Some of these hooks are used
25385 in time-critical parts of the scheduler, so we only set them up when
25386 they are actually used. */
25388 {
25392 /* Do not perform multipass scheduling for pre-reload schedule
25393 to save compile time. */
25395 {
25411 /* Set decoder parameters. */
25416 }
25417 /* ... Fall through ... */
25427 }
25428 }
25430 \f
25431 /* Compute the alignment given to a constant that is being placed in memory.
25432 EXP is the constant and ALIGN is the alignment that the object would
25433 ordinarily have.
25434 The value of this function is used instead of that alignment to align
25435 the object. */
25437 int
25439 {
25442 {
25447 }
25453 }
25455 /* Compute the alignment for a static variable.
25456 TYPE is the data type, and ALIGN is the alignment that
25457 the object would ordinarily have. The value of this function is used
25458 instead of that alignment to align the object. */
25460 int
25462 {
25474 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25475 to 16byte boundary. */
25477 {
25484 }
25490 {
25495 }
25497 {
25504 }
25509 {
25514 }
25517 {
25522 }
25525 }
25527 /* Compute the alignment for a local variable or a stack slot. EXP is
25528 the data type or decl itself, MODE is the widest mode available and
25529 ALIGN is the alignment that the object would ordinarily have. The
25530 value of this macro is used instead of that alignment to align the
25531 object. */
25533 unsigned int
25536 {
25540 {
25543 }
25544 else
25545 {
25548 }
25550 /* Don't do dynamic stack realignment for long long objects with
25551 -mpreferred-stack-boundary=2. */
25560 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25561 register in MODE. We will return the largest alignment of XF
25562 and DF. */
25564 {
25568 }
25570 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25571 to 16byte boundary. Exact wording is:
25573 An array uses the same alignment as its elements, except that a local or
25574 global array variable of length at least 16 bytes or
25575 a C99 variable-length array variable always has alignment of at least 16 bytes.
25577 This was added to allow use of aligned SSE instructions at arrays. This
25578 rule is meant for static storage (where compiler can not do the analysis
25579 by itself). We follow it for automatic variables only when convenient.
25580 We fully control everything in the function compiled and functions from
25581 other unit can not rely on the alignment.
25583 Exclude va_list type. It is the common case of local array where
25584 we can not benefit from the alignment.
25586 TODO: Probably one should optimize for size only when var is not escaping. */
25589 {
25599 }
25601 {
25606 }
25608 {
25614 }
25619 {
25624 }
25627 {
25633 }
25635 }
25637 /* Compute the minimum required alignment for dynamic stack realignment
25638 purposes for a local variable, parameter or a stack slot. EXP is
25639 the data type or decl itself, MODE is its mode and ALIGN is the
25640 alignment that the object would ordinarily have. */
25642 unsigned int
25645 {
25649 {
25652 }
25653 else
25654 {
25657 }
25662 /* Don't do dynamic stack realignment for long long objects with
25663 -mpreferred-stack-boundary=2. */
25670 }
25671 \f
25672 /* Find a location for the static chain incoming to a nested function.
25673 This is a register, unless all free registers are used by arguments. */
25675 static rtx
25677 {
25684 {
25685 /* We always use R10 in 64-bit mode. */
25687 }
25688 else
25689 {
25690 tree fntype;
25693 /* By default in 32-bit mode we use ECX to pass the static chain. */
25699 {
25700 /* Fastcall functions use ecx/edx for arguments, which leaves
25701 us with EAX for the static chain.
25702 Thiscall functions use ecx for arguments, which also
25703 leaves us with EAX for the static chain. */
25705 }
25707 {
25708 /* Thiscall functions use ecx for arguments, which leaves
25709 us with EAX and EDX for the static chain.
25710 We are using for abi-compatibility EAX. */
25712 }
25714 {
25715 /* For regparm 3, we have no free call-clobbered registers in
25716 which to store the static chain. In order to implement this,
25717 we have the trampoline push the static chain to the stack.
25718 However, we can't push a value below the return address when
25719 we call the nested function directly, so we have to use an
25720 alternate entry point. For this we use ESI, and have the
25721 alternate entry point push ESI, so that things appear the
25722 same once we're executing the nested function. */
25724 {
25730 }
25732 }
25733 }
25736 }
25738 /* Emit RTL insns to initialize the variable parts of a trampoline.
25739 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25740 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25741 to be passed to the target function. */
25743 static void
25745 {
25753 {
25756 /* Load the function address to r11. Try to load address using
25757 the shorter movl instead of movabs. We may want to support
25758 movq for kernel mode, but kernel does not use trampolines at
25759 the moment. FNADDR is a 32bit address and may not be in
25760 DImode when ptr_mode == SImode. Always use movl in this
25761 case. */
25764 {
25773 }
25774 else
25775 {
25782 }
25784 /* Load static chain using movabs to r10. Use the shorter movl
25785 instead of movabs when ptr_mode == SImode. */
25787 {
25790 }
25791 else
25792 {
25795 }
25804 /* Jump to r11; the last (unused) byte is a nop, only there to
25805 pad the write out to a single 32-bit store. */
25809 }
25810 else
25811 {
25814 /* Depending on the static chain location, either load a register
25815 with a constant, or push the constant to the stack. All of the
25816 instructions are the same size. */
25819 {
25821 {
25828 }
25829 }
25830 else
25845 /* Compute offset from the end of the jmp to the target function.
25846 In the case in which the trampoline stores the static chain on
25847 the stack, we need to skip the first insn which pushes the
25848 (call-saved) register static chain; this push is 1 byte. */
25855 }
25859 #ifdef HAVE_ENABLE_EXECUTE_STACK
25860 #ifdef CHECK_EXECUTE_STACK_ENABLED
25862 #endif
25865 #endif
25866 }
25867 \f
25868 /* The following file contains several enumerations and data structures
25869 built from the definitions in i386-builtin-types.def. */
25873 /* Table for the ix86 builtin non-function types. */
25876 /* Retrieve an element from the above table, building some of
25877 the types lazily. */
25879 static tree
25881 {
25893 {
25901 }
25902 else
25903 {
25909 else
25917 }
25921 }
25923 /* Table for the ix86 builtin function types. */
25926 /* Retrieve an element from the above table, building some of
25927 the types lazily. */
25929 static tree
25931 {
25932 tree type;
25941 {
25949 {
25952 }
25955 }
25956 else
25957 {
25963 }
25967 }
25970 /* Codes for all the SSE/MMX builtins. */
25971 enum ix86_builtins
25972 {
25973 IX86_BUILTIN_ADDPS,
25974 IX86_BUILTIN_ADDSS,
25975 IX86_BUILTIN_DIVPS,
25976 IX86_BUILTIN_DIVSS,
25977 IX86_BUILTIN_MULPS,
25978 IX86_BUILTIN_MULSS,
25979 IX86_BUILTIN_SUBPS,
25980 IX86_BUILTIN_SUBSS,
25982 IX86_BUILTIN_CMPEQPS,
25983 IX86_BUILTIN_CMPLTPS,
25984 IX86_BUILTIN_CMPLEPS,
25985 IX86_BUILTIN_CMPGTPS,
25986 IX86_BUILTIN_CMPGEPS,
25987 IX86_BUILTIN_CMPNEQPS,
25988 IX86_BUILTIN_CMPNLTPS,
25989 IX86_BUILTIN_CMPNLEPS,
25990 IX86_BUILTIN_CMPNGTPS,
25991 IX86_BUILTIN_CMPNGEPS,
25992 IX86_BUILTIN_CMPORDPS,
25993 IX86_BUILTIN_CMPUNORDPS,
25994 IX86_BUILTIN_CMPEQSS,
25995 IX86_BUILTIN_CMPLTSS,
25996 IX86_BUILTIN_CMPLESS,
25997 IX86_BUILTIN_CMPNEQSS,
25998 IX86_BUILTIN_CMPNLTSS,
25999 IX86_BUILTIN_CMPNLESS,
26000 IX86_BUILTIN_CMPORDSS,
26001 IX86_BUILTIN_CMPUNORDSS,
26003 IX86_BUILTIN_COMIEQSS,
26004 IX86_BUILTIN_COMILTSS,
26005 IX86_BUILTIN_COMILESS,
26006 IX86_BUILTIN_COMIGTSS,
26007 IX86_BUILTIN_COMIGESS,
26008 IX86_BUILTIN_COMINEQSS,
26009 IX86_BUILTIN_UCOMIEQSS,
26010 IX86_BUILTIN_UCOMILTSS,
26011 IX86_BUILTIN_UCOMILESS,
26012 IX86_BUILTIN_UCOMIGTSS,
26013 IX86_BUILTIN_UCOMIGESS,
26014 IX86_BUILTIN_UCOMINEQSS,
26016 IX86_BUILTIN_CVTPI2PS,
26017 IX86_BUILTIN_CVTPS2PI,
26018 IX86_BUILTIN_CVTSI2SS,
26019 IX86_BUILTIN_CVTSI642SS,
26020 IX86_BUILTIN_CVTSS2SI,
26021 IX86_BUILTIN_CVTSS2SI64,
26022 IX86_BUILTIN_CVTTPS2PI,
26023 IX86_BUILTIN_CVTTSS2SI,
26024 IX86_BUILTIN_CVTTSS2SI64,
26026 IX86_BUILTIN_MAXPS,
26027 IX86_BUILTIN_MAXSS,
26028 IX86_BUILTIN_MINPS,
26029 IX86_BUILTIN_MINSS,
26031 IX86_BUILTIN_LOADUPS,
26032 IX86_BUILTIN_STOREUPS,
26033 IX86_BUILTIN_MOVSS,
26035 IX86_BUILTIN_MOVHLPS,
26036 IX86_BUILTIN_MOVLHPS,
26037 IX86_BUILTIN_LOADHPS,
26038 IX86_BUILTIN_LOADLPS,
26039 IX86_BUILTIN_STOREHPS,
26040 IX86_BUILTIN_STORELPS,
26042 IX86_BUILTIN_MASKMOVQ,
26043 IX86_BUILTIN_MOVMSKPS,
26044 IX86_BUILTIN_PMOVMSKB,
26046 IX86_BUILTIN_MOVNTPS,
26047 IX86_BUILTIN_MOVNTQ,
26049 IX86_BUILTIN_LOADDQU,
26050 IX86_BUILTIN_STOREDQU,
26052 IX86_BUILTIN_PACKSSWB,
26053 IX86_BUILTIN_PACKSSDW,
26054 IX86_BUILTIN_PACKUSWB,
26056 IX86_BUILTIN_PADDB,
26057 IX86_BUILTIN_PADDW,
26058 IX86_BUILTIN_PADDD,
26059 IX86_BUILTIN_PADDQ,
26060 IX86_BUILTIN_PADDSB,
26061 IX86_BUILTIN_PADDSW,
26062 IX86_BUILTIN_PADDUSB,
26063 IX86_BUILTIN_PADDUSW,
26064 IX86_BUILTIN_PSUBB,
26065 IX86_BUILTIN_PSUBW,
26066 IX86_BUILTIN_PSUBD,
26067 IX86_BUILTIN_PSUBQ,
26068 IX86_BUILTIN_PSUBSB,
26069 IX86_BUILTIN_PSUBSW,
26070 IX86_BUILTIN_PSUBUSB,
26071 IX86_BUILTIN_PSUBUSW,
26073 IX86_BUILTIN_PAND,
26074 IX86_BUILTIN_PANDN,
26075 IX86_BUILTIN_POR,
26076 IX86_BUILTIN_PXOR,
26078 IX86_BUILTIN_PAVGB,
26079 IX86_BUILTIN_PAVGW,
26081 IX86_BUILTIN_PCMPEQB,
26082 IX86_BUILTIN_PCMPEQW,
26083 IX86_BUILTIN_PCMPEQD,
26084 IX86_BUILTIN_PCMPGTB,
26085 IX86_BUILTIN_PCMPGTW,
26086 IX86_BUILTIN_PCMPGTD,
26088 IX86_BUILTIN_PMADDWD,
26090 IX86_BUILTIN_PMAXSW,
26091 IX86_BUILTIN_PMAXUB,
26092 IX86_BUILTIN_PMINSW,
26093 IX86_BUILTIN_PMINUB,
26095 IX86_BUILTIN_PMULHUW,
26096 IX86_BUILTIN_PMULHW,
26097 IX86_BUILTIN_PMULLW,
26099 IX86_BUILTIN_PSADBW,
26100 IX86_BUILTIN_PSHUFW,
26102 IX86_BUILTIN_PSLLW,
26103 IX86_BUILTIN_PSLLD,
26104 IX86_BUILTIN_PSLLQ,
26105 IX86_BUILTIN_PSRAW,
26106 IX86_BUILTIN_PSRAD,
26107 IX86_BUILTIN_PSRLW,
26108 IX86_BUILTIN_PSRLD,
26109 IX86_BUILTIN_PSRLQ,
26110 IX86_BUILTIN_PSLLWI,
26111 IX86_BUILTIN_PSLLDI,
26112 IX86_BUILTIN_PSLLQI,
26113 IX86_BUILTIN_PSRAWI,
26114 IX86_BUILTIN_PSRADI,
26115 IX86_BUILTIN_PSRLWI,
26116 IX86_BUILTIN_PSRLDI,
26117 IX86_BUILTIN_PSRLQI,
26119 IX86_BUILTIN_PUNPCKHBW,
26120 IX86_BUILTIN_PUNPCKHWD,
26121 IX86_BUILTIN_PUNPCKHDQ,
26122 IX86_BUILTIN_PUNPCKLBW,
26123 IX86_BUILTIN_PUNPCKLWD,
26124 IX86_BUILTIN_PUNPCKLDQ,
26126 IX86_BUILTIN_SHUFPS,
26128 IX86_BUILTIN_RCPPS,
26129 IX86_BUILTIN_RCPSS,
26130 IX86_BUILTIN_RSQRTPS,
26131 IX86_BUILTIN_RSQRTPS_NR,
26132 IX86_BUILTIN_RSQRTSS,
26133 IX86_BUILTIN_RSQRTF,
26134 IX86_BUILTIN_SQRTPS,
26135 IX86_BUILTIN_SQRTPS_NR,
26136 IX86_BUILTIN_SQRTSS,
26138 IX86_BUILTIN_UNPCKHPS,
26139 IX86_BUILTIN_UNPCKLPS,
26141 IX86_BUILTIN_ANDPS,
26142 IX86_BUILTIN_ANDNPS,
26143 IX86_BUILTIN_ORPS,
26144 IX86_BUILTIN_XORPS,
26146 IX86_BUILTIN_EMMS,
26147 IX86_BUILTIN_LDMXCSR,
26148 IX86_BUILTIN_STMXCSR,
26149 IX86_BUILTIN_SFENCE,
26151 IX86_BUILTIN_FXSAVE,
26152 IX86_BUILTIN_FXRSTOR,
26153 IX86_BUILTIN_FXSAVE64,
26154 IX86_BUILTIN_FXRSTOR64,
26156 IX86_BUILTIN_XSAVE,
26157 IX86_BUILTIN_XRSTOR,
26158 IX86_BUILTIN_XSAVE64,
26159 IX86_BUILTIN_XRSTOR64,
26161 IX86_BUILTIN_XSAVEOPT,
26162 IX86_BUILTIN_XSAVEOPT64,
26164 /* 3DNow! Original */
26165 IX86_BUILTIN_FEMMS,
26166 IX86_BUILTIN_PAVGUSB,
26167 IX86_BUILTIN_PF2ID,
26168 IX86_BUILTIN_PFACC,
26169 IX86_BUILTIN_PFADD,
26170 IX86_BUILTIN_PFCMPEQ,
26171 IX86_BUILTIN_PFCMPGE,
26172 IX86_BUILTIN_PFCMPGT,
26173 IX86_BUILTIN_PFMAX,
26174 IX86_BUILTIN_PFMIN,
26175 IX86_BUILTIN_PFMUL,
26176 IX86_BUILTIN_PFRCP,
26177 IX86_BUILTIN_PFRCPIT1,
26178 IX86_BUILTIN_PFRCPIT2,
26179 IX86_BUILTIN_PFRSQIT1,
26180 IX86_BUILTIN_PFRSQRT,
26181 IX86_BUILTIN_PFSUB,
26182 IX86_BUILTIN_PFSUBR,
26183 IX86_BUILTIN_PI2FD,
26184 IX86_BUILTIN_PMULHRW,
26186 /* 3DNow! Athlon Extensions */
26187 IX86_BUILTIN_PF2IW,
26188 IX86_BUILTIN_PFNACC,
26189 IX86_BUILTIN_PFPNACC,
26190 IX86_BUILTIN_PI2FW,
26191 IX86_BUILTIN_PSWAPDSI,
26192 IX86_BUILTIN_PSWAPDSF,
26194 /* SSE2 */
26195 IX86_BUILTIN_ADDPD,
26196 IX86_BUILTIN_ADDSD,
26197 IX86_BUILTIN_DIVPD,
26198 IX86_BUILTIN_DIVSD,
26199 IX86_BUILTIN_MULPD,
26200 IX86_BUILTIN_MULSD,
26201 IX86_BUILTIN_SUBPD,
26202 IX86_BUILTIN_SUBSD,
26204 IX86_BUILTIN_CMPEQPD,
26205 IX86_BUILTIN_CMPLTPD,
26206 IX86_BUILTIN_CMPLEPD,
26207 IX86_BUILTIN_CMPGTPD,
26208 IX86_BUILTIN_CMPGEPD,
26209 IX86_BUILTIN_CMPNEQPD,
26210 IX86_BUILTIN_CMPNLTPD,
26211 IX86_BUILTIN_CMPNLEPD,
26212 IX86_BUILTIN_CMPNGTPD,
26213 IX86_BUILTIN_CMPNGEPD,
26214 IX86_BUILTIN_CMPORDPD,
26215 IX86_BUILTIN_CMPUNORDPD,
26216 IX86_BUILTIN_CMPEQSD,
26217 IX86_BUILTIN_CMPLTSD,
26218 IX86_BUILTIN_CMPLESD,
26219 IX86_BUILTIN_CMPNEQSD,
26220 IX86_BUILTIN_CMPNLTSD,
26221 IX86_BUILTIN_CMPNLESD,
26222 IX86_BUILTIN_CMPORDSD,
26223 IX86_BUILTIN_CMPUNORDSD,
26225 IX86_BUILTIN_COMIEQSD,
26226 IX86_BUILTIN_COMILTSD,
26227 IX86_BUILTIN_COMILESD,
26228 IX86_BUILTIN_COMIGTSD,
26229 IX86_BUILTIN_COMIGESD,
26230 IX86_BUILTIN_COMINEQSD,
26231 IX86_BUILTIN_UCOMIEQSD,
26232 IX86_BUILTIN_UCOMILTSD,
26233 IX86_BUILTIN_UCOMILESD,
26234 IX86_BUILTIN_UCOMIGTSD,
26235 IX86_BUILTIN_UCOMIGESD,
26236 IX86_BUILTIN_UCOMINEQSD,
26238 IX86_BUILTIN_MAXPD,
26239 IX86_BUILTIN_MAXSD,
26240 IX86_BUILTIN_MINPD,
26241 IX86_BUILTIN_MINSD,
26243 IX86_BUILTIN_ANDPD,
26244 IX86_BUILTIN_ANDNPD,
26245 IX86_BUILTIN_ORPD,
26246 IX86_BUILTIN_XORPD,
26248 IX86_BUILTIN_SQRTPD,
26249 IX86_BUILTIN_SQRTSD,
26251 IX86_BUILTIN_UNPCKHPD,
26252 IX86_BUILTIN_UNPCKLPD,
26254 IX86_BUILTIN_SHUFPD,
26256 IX86_BUILTIN_LOADUPD,
26257 IX86_BUILTIN_STOREUPD,
26258 IX86_BUILTIN_MOVSD,
26260 IX86_BUILTIN_LOADHPD,
26261 IX86_BUILTIN_LOADLPD,
26263 IX86_BUILTIN_CVTDQ2PD,
26264 IX86_BUILTIN_CVTDQ2PS,
26266 IX86_BUILTIN_CVTPD2DQ,
26267 IX86_BUILTIN_CVTPD2PI,
26268 IX86_BUILTIN_CVTPD2PS,
26269 IX86_BUILTIN_CVTTPD2DQ,
26270 IX86_BUILTIN_CVTTPD2PI,
26272 IX86_BUILTIN_CVTPI2PD,
26273 IX86_BUILTIN_CVTSI2SD,
26274 IX86_BUILTIN_CVTSI642SD,
26276 IX86_BUILTIN_CVTSD2SI,
26277 IX86_BUILTIN_CVTSD2SI64,
26278 IX86_BUILTIN_CVTSD2SS,
26279 IX86_BUILTIN_CVTSS2SD,
26280 IX86_BUILTIN_CVTTSD2SI,
26281 IX86_BUILTIN_CVTTSD2SI64,
26283 IX86_BUILTIN_CVTPS2DQ,
26284 IX86_BUILTIN_CVTPS2PD,
26285 IX86_BUILTIN_CVTTPS2DQ,
26287 IX86_BUILTIN_MOVNTI,
26288 IX86_BUILTIN_MOVNTI64,
26289 IX86_BUILTIN_MOVNTPD,
26290 IX86_BUILTIN_MOVNTDQ,
26292 IX86_BUILTIN_MOVQ128,
26294 /* SSE2 MMX */
26295 IX86_BUILTIN_MASKMOVDQU,
26296 IX86_BUILTIN_MOVMSKPD,
26297 IX86_BUILTIN_PMOVMSKB128,
26299 IX86_BUILTIN_PACKSSWB128,
26300 IX86_BUILTIN_PACKSSDW128,
26301 IX86_BUILTIN_PACKUSWB128,
26303 IX86_BUILTIN_PADDB128,
26304 IX86_BUILTIN_PADDW128,
26305 IX86_BUILTIN_PADDD128,
26306 IX86_BUILTIN_PADDQ128,
26307 IX86_BUILTIN_PADDSB128,
26308 IX86_BUILTIN_PADDSW128,
26309 IX86_BUILTIN_PADDUSB128,
26310 IX86_BUILTIN_PADDUSW128,
26311 IX86_BUILTIN_PSUBB128,
26312 IX86_BUILTIN_PSUBW128,
26313 IX86_BUILTIN_PSUBD128,
26314 IX86_BUILTIN_PSUBQ128,
26315 IX86_BUILTIN_PSUBSB128,
26316 IX86_BUILTIN_PSUBSW128,
26317 IX86_BUILTIN_PSUBUSB128,
26318 IX86_BUILTIN_PSUBUSW128,
26320 IX86_BUILTIN_PAND128,
26321 IX86_BUILTIN_PANDN128,
26322 IX86_BUILTIN_POR128,
26323 IX86_BUILTIN_PXOR128,
26325 IX86_BUILTIN_PAVGB128,
26326 IX86_BUILTIN_PAVGW128,
26328 IX86_BUILTIN_PCMPEQB128,
26329 IX86_BUILTIN_PCMPEQW128,
26330 IX86_BUILTIN_PCMPEQD128,
26331 IX86_BUILTIN_PCMPGTB128,
26332 IX86_BUILTIN_PCMPGTW128,
26333 IX86_BUILTIN_PCMPGTD128,
26335 IX86_BUILTIN_PMADDWD128,
26337 IX86_BUILTIN_PMAXSW128,
26338 IX86_BUILTIN_PMAXUB128,
26339 IX86_BUILTIN_PMINSW128,
26340 IX86_BUILTIN_PMINUB128,
26342 IX86_BUILTIN_PMULUDQ,
26343 IX86_BUILTIN_PMULUDQ128,
26344 IX86_BUILTIN_PMULHUW128,
26345 IX86_BUILTIN_PMULHW128,
26346 IX86_BUILTIN_PMULLW128,
26348 IX86_BUILTIN_PSADBW128,
26349 IX86_BUILTIN_PSHUFHW,
26350 IX86_BUILTIN_PSHUFLW,
26351 IX86_BUILTIN_PSHUFD,
26353 IX86_BUILTIN_PSLLDQI128,
26354 IX86_BUILTIN_PSLLWI128,
26355 IX86_BUILTIN_PSLLDI128,
26356 IX86_BUILTIN_PSLLQI128,
26357 IX86_BUILTIN_PSRAWI128,
26358 IX86_BUILTIN_PSRADI128,
26359 IX86_BUILTIN_PSRLDQI128,
26360 IX86_BUILTIN_PSRLWI128,
26361 IX86_BUILTIN_PSRLDI128,
26362 IX86_BUILTIN_PSRLQI128,
26364 IX86_BUILTIN_PSLLDQ128,
26365 IX86_BUILTIN_PSLLW128,
26366 IX86_BUILTIN_PSLLD128,
26367 IX86_BUILTIN_PSLLQ128,
26368 IX86_BUILTIN_PSRAW128,
26369 IX86_BUILTIN_PSRAD128,
26370 IX86_BUILTIN_PSRLW128,
26371 IX86_BUILTIN_PSRLD128,
26372 IX86_BUILTIN_PSRLQ128,
26374 IX86_BUILTIN_PUNPCKHBW128,
26375 IX86_BUILTIN_PUNPCKHWD128,
26376 IX86_BUILTIN_PUNPCKHDQ128,
26377 IX86_BUILTIN_PUNPCKHQDQ128,
26378 IX86_BUILTIN_PUNPCKLBW128,
26379 IX86_BUILTIN_PUNPCKLWD128,
26380 IX86_BUILTIN_PUNPCKLDQ128,
26381 IX86_BUILTIN_PUNPCKLQDQ128,
26383 IX86_BUILTIN_CLFLUSH,
26384 IX86_BUILTIN_MFENCE,
26385 IX86_BUILTIN_LFENCE,
26386 IX86_BUILTIN_PAUSE,
26388 IX86_BUILTIN_BSRSI,
26389 IX86_BUILTIN_BSRDI,
26390 IX86_BUILTIN_RDPMC,
26391 IX86_BUILTIN_RDTSC,
26392 IX86_BUILTIN_RDTSCP,
26393 IX86_BUILTIN_ROLQI,
26394 IX86_BUILTIN_ROLHI,
26395 IX86_BUILTIN_RORQI,
26396 IX86_BUILTIN_RORHI,
26398 /* SSE3. */
26399 IX86_BUILTIN_ADDSUBPS,
26400 IX86_BUILTIN_HADDPS,
26401 IX86_BUILTIN_HSUBPS,
26402 IX86_BUILTIN_MOVSHDUP,
26403 IX86_BUILTIN_MOVSLDUP,
26404 IX86_BUILTIN_ADDSUBPD,
26405 IX86_BUILTIN_HADDPD,
26406 IX86_BUILTIN_HSUBPD,
26407 IX86_BUILTIN_LDDQU,
26409 IX86_BUILTIN_MONITOR,
26410 IX86_BUILTIN_MWAIT,
26412 /* SSSE3. */
26413 IX86_BUILTIN_PHADDW,
26414 IX86_BUILTIN_PHADDD,
26415 IX86_BUILTIN_PHADDSW,
26416 IX86_BUILTIN_PHSUBW,
26417 IX86_BUILTIN_PHSUBD,
26418 IX86_BUILTIN_PHSUBSW,
26419 IX86_BUILTIN_PMADDUBSW,
26420 IX86_BUILTIN_PMULHRSW,
26421 IX86_BUILTIN_PSHUFB,
26422 IX86_BUILTIN_PSIGNB,
26423 IX86_BUILTIN_PSIGNW,
26424 IX86_BUILTIN_PSIGND,
26425 IX86_BUILTIN_PALIGNR,
26426 IX86_BUILTIN_PABSB,
26427 IX86_BUILTIN_PABSW,
26428 IX86_BUILTIN_PABSD,
26430 IX86_BUILTIN_PHADDW128,
26431 IX86_BUILTIN_PHADDD128,
26432 IX86_BUILTIN_PHADDSW128,
26433 IX86_BUILTIN_PHSUBW128,
26434 IX86_BUILTIN_PHSUBD128,
26435 IX86_BUILTIN_PHSUBSW128,
26436 IX86_BUILTIN_PMADDUBSW128,
26437 IX86_BUILTIN_PMULHRSW128,
26438 IX86_BUILTIN_PSHUFB128,
26439 IX86_BUILTIN_PSIGNB128,
26440 IX86_BUILTIN_PSIGNW128,
26441 IX86_BUILTIN_PSIGND128,
26442 IX86_BUILTIN_PALIGNR128,
26443 IX86_BUILTIN_PABSB128,
26444 IX86_BUILTIN_PABSW128,
26445 IX86_BUILTIN_PABSD128,
26447 /* AMDFAM10 - SSE4A New Instructions. */
26448 IX86_BUILTIN_MOVNTSD,
26449 IX86_BUILTIN_MOVNTSS,
26450 IX86_BUILTIN_EXTRQI,
26451 IX86_BUILTIN_EXTRQ,
26452 IX86_BUILTIN_INSERTQI,
26453 IX86_BUILTIN_INSERTQ,
26455 /* SSE4.1. */
26456 IX86_BUILTIN_BLENDPD,
26457 IX86_BUILTIN_BLENDPS,
26458 IX86_BUILTIN_BLENDVPD,
26459 IX86_BUILTIN_BLENDVPS,
26460 IX86_BUILTIN_PBLENDVB128,
26461 IX86_BUILTIN_PBLENDW128,
26463 IX86_BUILTIN_DPPD,
26464 IX86_BUILTIN_DPPS,
26466 IX86_BUILTIN_INSERTPS128,
26468 IX86_BUILTIN_MOVNTDQA,
26469 IX86_BUILTIN_MPSADBW128,
26470 IX86_BUILTIN_PACKUSDW128,
26471 IX86_BUILTIN_PCMPEQQ,
26472 IX86_BUILTIN_PHMINPOSUW128,
26474 IX86_BUILTIN_PMAXSB128,
26475 IX86_BUILTIN_PMAXSD128,
26476 IX86_BUILTIN_PMAXUD128,
26477 IX86_BUILTIN_PMAXUW128,
26479 IX86_BUILTIN_PMINSB128,
26480 IX86_BUILTIN_PMINSD128,
26481 IX86_BUILTIN_PMINUD128,
26482 IX86_BUILTIN_PMINUW128,
26484 IX86_BUILTIN_PMOVSXBW128,
26485 IX86_BUILTIN_PMOVSXBD128,
26486 IX86_BUILTIN_PMOVSXBQ128,
26487 IX86_BUILTIN_PMOVSXWD128,
26488 IX86_BUILTIN_PMOVSXWQ128,
26489 IX86_BUILTIN_PMOVSXDQ128,
26491 IX86_BUILTIN_PMOVZXBW128,
26492 IX86_BUILTIN_PMOVZXBD128,
26493 IX86_BUILTIN_PMOVZXBQ128,
26494 IX86_BUILTIN_PMOVZXWD128,
26495 IX86_BUILTIN_PMOVZXWQ128,
26496 IX86_BUILTIN_PMOVZXDQ128,
26498 IX86_BUILTIN_PMULDQ128,
26499 IX86_BUILTIN_PMULLD128,
26501 IX86_BUILTIN_ROUNDSD,
26502 IX86_BUILTIN_ROUNDSS,
26504 IX86_BUILTIN_ROUNDPD,
26505 IX86_BUILTIN_ROUNDPS,
26507 IX86_BUILTIN_FLOORPD,
26508 IX86_BUILTIN_CEILPD,
26509 IX86_BUILTIN_TRUNCPD,
26510 IX86_BUILTIN_RINTPD,
26511 IX86_BUILTIN_ROUNDPD_AZ,
26513 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26514 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26515 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26517 IX86_BUILTIN_FLOORPS,
26518 IX86_BUILTIN_CEILPS,
26519 IX86_BUILTIN_TRUNCPS,
26520 IX86_BUILTIN_RINTPS,
26521 IX86_BUILTIN_ROUNDPS_AZ,
26523 IX86_BUILTIN_FLOORPS_SFIX,
26524 IX86_BUILTIN_CEILPS_SFIX,
26525 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26527 IX86_BUILTIN_PTESTZ,
26528 IX86_BUILTIN_PTESTC,
26529 IX86_BUILTIN_PTESTNZC,
26531 IX86_BUILTIN_VEC_INIT_V2SI,
26532 IX86_BUILTIN_VEC_INIT_V4HI,
26533 IX86_BUILTIN_VEC_INIT_V8QI,
26534 IX86_BUILTIN_VEC_EXT_V2DF,
26535 IX86_BUILTIN_VEC_EXT_V2DI,
26536 IX86_BUILTIN_VEC_EXT_V4SF,
26537 IX86_BUILTIN_VEC_EXT_V4SI,
26538 IX86_BUILTIN_VEC_EXT_V8HI,
26539 IX86_BUILTIN_VEC_EXT_V2SI,
26540 IX86_BUILTIN_VEC_EXT_V4HI,
26541 IX86_BUILTIN_VEC_EXT_V16QI,
26542 IX86_BUILTIN_VEC_SET_V2DI,
26543 IX86_BUILTIN_VEC_SET_V4SF,
26544 IX86_BUILTIN_VEC_SET_V4SI,
26545 IX86_BUILTIN_VEC_SET_V8HI,
26546 IX86_BUILTIN_VEC_SET_V4HI,
26547 IX86_BUILTIN_VEC_SET_V16QI,
26549 IX86_BUILTIN_VEC_PACK_SFIX,
26550 IX86_BUILTIN_VEC_PACK_SFIX256,
26552 /* SSE4.2. */
26553 IX86_BUILTIN_CRC32QI,
26554 IX86_BUILTIN_CRC32HI,
26555 IX86_BUILTIN_CRC32SI,
26556 IX86_BUILTIN_CRC32DI,
26558 IX86_BUILTIN_PCMPESTRI128,
26559 IX86_BUILTIN_PCMPESTRM128,
26560 IX86_BUILTIN_PCMPESTRA128,
26561 IX86_BUILTIN_PCMPESTRC128,
26562 IX86_BUILTIN_PCMPESTRO128,
26563 IX86_BUILTIN_PCMPESTRS128,
26564 IX86_BUILTIN_PCMPESTRZ128,
26565 IX86_BUILTIN_PCMPISTRI128,
26566 IX86_BUILTIN_PCMPISTRM128,
26567 IX86_BUILTIN_PCMPISTRA128,
26568 IX86_BUILTIN_PCMPISTRC128,
26569 IX86_BUILTIN_PCMPISTRO128,
26570 IX86_BUILTIN_PCMPISTRS128,
26571 IX86_BUILTIN_PCMPISTRZ128,
26573 IX86_BUILTIN_PCMPGTQ,
26575 /* AES instructions */
26576 IX86_BUILTIN_AESENC128,
26577 IX86_BUILTIN_AESENCLAST128,
26578 IX86_BUILTIN_AESDEC128,
26579 IX86_BUILTIN_AESDECLAST128,
26580 IX86_BUILTIN_AESIMC128,
26581 IX86_BUILTIN_AESKEYGENASSIST128,
26583 /* PCLMUL instruction */
26584 IX86_BUILTIN_PCLMULQDQ128,
26586 /* AVX */
26587 IX86_BUILTIN_ADDPD256,
26588 IX86_BUILTIN_ADDPS256,
26589 IX86_BUILTIN_ADDSUBPD256,
26590 IX86_BUILTIN_ADDSUBPS256,
26591 IX86_BUILTIN_ANDPD256,
26592 IX86_BUILTIN_ANDPS256,
26593 IX86_BUILTIN_ANDNPD256,
26594 IX86_BUILTIN_ANDNPS256,
26595 IX86_BUILTIN_BLENDPD256,
26596 IX86_BUILTIN_BLENDPS256,
26597 IX86_BUILTIN_BLENDVPD256,
26598 IX86_BUILTIN_BLENDVPS256,
26599 IX86_BUILTIN_DIVPD256,
26600 IX86_BUILTIN_DIVPS256,
26601 IX86_BUILTIN_DPPS256,
26602 IX86_BUILTIN_HADDPD256,
26603 IX86_BUILTIN_HADDPS256,
26604 IX86_BUILTIN_HSUBPD256,
26605 IX86_BUILTIN_HSUBPS256,
26606 IX86_BUILTIN_MAXPD256,
26607 IX86_BUILTIN_MAXPS256,
26608 IX86_BUILTIN_MINPD256,
26609 IX86_BUILTIN_MINPS256,
26610 IX86_BUILTIN_MULPD256,
26611 IX86_BUILTIN_MULPS256,
26612 IX86_BUILTIN_ORPD256,
26613 IX86_BUILTIN_ORPS256,
26614 IX86_BUILTIN_SHUFPD256,
26615 IX86_BUILTIN_SHUFPS256,
26616 IX86_BUILTIN_SUBPD256,
26617 IX86_BUILTIN_SUBPS256,
26618 IX86_BUILTIN_XORPD256,
26619 IX86_BUILTIN_XORPS256,
26620 IX86_BUILTIN_CMPSD,
26621 IX86_BUILTIN_CMPSS,
26622 IX86_BUILTIN_CMPPD,
26623 IX86_BUILTIN_CMPPS,
26624 IX86_BUILTIN_CMPPD256,
26625 IX86_BUILTIN_CMPPS256,
26626 IX86_BUILTIN_CVTDQ2PD256,
26627 IX86_BUILTIN_CVTDQ2PS256,
26628 IX86_BUILTIN_CVTPD2PS256,
26629 IX86_BUILTIN_CVTPS2DQ256,
26630 IX86_BUILTIN_CVTPS2PD256,
26631 IX86_BUILTIN_CVTTPD2DQ256,
26632 IX86_BUILTIN_CVTPD2DQ256,
26633 IX86_BUILTIN_CVTTPS2DQ256,
26634 IX86_BUILTIN_EXTRACTF128PD256,
26635 IX86_BUILTIN_EXTRACTF128PS256,
26636 IX86_BUILTIN_EXTRACTF128SI256,
26637 IX86_BUILTIN_VZEROALL,
26638 IX86_BUILTIN_VZEROUPPER,
26639 IX86_BUILTIN_VPERMILVARPD,
26640 IX86_BUILTIN_VPERMILVARPS,
26641 IX86_BUILTIN_VPERMILVARPD256,
26642 IX86_BUILTIN_VPERMILVARPS256,
26643 IX86_BUILTIN_VPERMILPD,
26644 IX86_BUILTIN_VPERMILPS,
26645 IX86_BUILTIN_VPERMILPD256,
26646 IX86_BUILTIN_VPERMILPS256,
26647 IX86_BUILTIN_VPERMIL2PD,
26648 IX86_BUILTIN_VPERMIL2PS,
26649 IX86_BUILTIN_VPERMIL2PD256,
26650 IX86_BUILTIN_VPERMIL2PS256,
26651 IX86_BUILTIN_VPERM2F128PD256,
26652 IX86_BUILTIN_VPERM2F128PS256,
26653 IX86_BUILTIN_VPERM2F128SI256,
26654 IX86_BUILTIN_VBROADCASTSS,
26655 IX86_BUILTIN_VBROADCASTSD256,
26656 IX86_BUILTIN_VBROADCASTSS256,
26657 IX86_BUILTIN_VBROADCASTPD256,
26658 IX86_BUILTIN_VBROADCASTPS256,
26659 IX86_BUILTIN_VINSERTF128PD256,
26660 IX86_BUILTIN_VINSERTF128PS256,
26661 IX86_BUILTIN_VINSERTF128SI256,
26662 IX86_BUILTIN_LOADUPD256,
26663 IX86_BUILTIN_LOADUPS256,
26664 IX86_BUILTIN_STOREUPD256,
26665 IX86_BUILTIN_STOREUPS256,
26666 IX86_BUILTIN_LDDQU256,
26667 IX86_BUILTIN_MOVNTDQ256,
26668 IX86_BUILTIN_MOVNTPD256,
26669 IX86_BUILTIN_MOVNTPS256,
26670 IX86_BUILTIN_LOADDQU256,
26671 IX86_BUILTIN_STOREDQU256,
26672 IX86_BUILTIN_MASKLOADPD,
26673 IX86_BUILTIN_MASKLOADPS,
26674 IX86_BUILTIN_MASKSTOREPD,
26675 IX86_BUILTIN_MASKSTOREPS,
26676 IX86_BUILTIN_MASKLOADPD256,
26677 IX86_BUILTIN_MASKLOADPS256,
26678 IX86_BUILTIN_MASKSTOREPD256,
26679 IX86_BUILTIN_MASKSTOREPS256,
26680 IX86_BUILTIN_MOVSHDUP256,
26681 IX86_BUILTIN_MOVSLDUP256,
26682 IX86_BUILTIN_MOVDDUP256,
26684 IX86_BUILTIN_SQRTPD256,
26685 IX86_BUILTIN_SQRTPS256,
26686 IX86_BUILTIN_SQRTPS_NR256,
26687 IX86_BUILTIN_RSQRTPS256,
26688 IX86_BUILTIN_RSQRTPS_NR256,
26690 IX86_BUILTIN_RCPPS256,
26692 IX86_BUILTIN_ROUNDPD256,
26693 IX86_BUILTIN_ROUNDPS256,
26695 IX86_BUILTIN_FLOORPD256,
26696 IX86_BUILTIN_CEILPD256,
26697 IX86_BUILTIN_TRUNCPD256,
26698 IX86_BUILTIN_RINTPD256,
26699 IX86_BUILTIN_ROUNDPD_AZ256,
26701 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26702 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26703 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26705 IX86_BUILTIN_FLOORPS256,
26706 IX86_BUILTIN_CEILPS256,
26707 IX86_BUILTIN_TRUNCPS256,
26708 IX86_BUILTIN_RINTPS256,
26709 IX86_BUILTIN_ROUNDPS_AZ256,
26711 IX86_BUILTIN_FLOORPS_SFIX256,
26712 IX86_BUILTIN_CEILPS_SFIX256,
26713 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26715 IX86_BUILTIN_UNPCKHPD256,
26716 IX86_BUILTIN_UNPCKLPD256,
26717 IX86_BUILTIN_UNPCKHPS256,
26718 IX86_BUILTIN_UNPCKLPS256,
26720 IX86_BUILTIN_SI256_SI,
26721 IX86_BUILTIN_PS256_PS,
26722 IX86_BUILTIN_PD256_PD,
26723 IX86_BUILTIN_SI_SI256,
26724 IX86_BUILTIN_PS_PS256,
26725 IX86_BUILTIN_PD_PD256,
26727 IX86_BUILTIN_VTESTZPD,
26728 IX86_BUILTIN_VTESTCPD,
26729 IX86_BUILTIN_VTESTNZCPD,
26730 IX86_BUILTIN_VTESTZPS,
26731 IX86_BUILTIN_VTESTCPS,
26732 IX86_BUILTIN_VTESTNZCPS,
26733 IX86_BUILTIN_VTESTZPD256,
26734 IX86_BUILTIN_VTESTCPD256,
26735 IX86_BUILTIN_VTESTNZCPD256,
26736 IX86_BUILTIN_VTESTZPS256,
26737 IX86_BUILTIN_VTESTCPS256,
26738 IX86_BUILTIN_VTESTNZCPS256,
26739 IX86_BUILTIN_PTESTZ256,
26740 IX86_BUILTIN_PTESTC256,
26741 IX86_BUILTIN_PTESTNZC256,
26743 IX86_BUILTIN_MOVMSKPD256,
26744 IX86_BUILTIN_MOVMSKPS256,
26746 /* AVX2 */
26747 IX86_BUILTIN_MPSADBW256,
26748 IX86_BUILTIN_PABSB256,
26749 IX86_BUILTIN_PABSW256,
26750 IX86_BUILTIN_PABSD256,
26751 IX86_BUILTIN_PACKSSDW256,
26752 IX86_BUILTIN_PACKSSWB256,
26753 IX86_BUILTIN_PACKUSDW256,
26754 IX86_BUILTIN_PACKUSWB256,
26755 IX86_BUILTIN_PADDB256,
26756 IX86_BUILTIN_PADDW256,
26757 IX86_BUILTIN_PADDD256,
26758 IX86_BUILTIN_PADDQ256,
26759 IX86_BUILTIN_PADDSB256,
26760 IX86_BUILTIN_PADDSW256,
26761 IX86_BUILTIN_PADDUSB256,
26762 IX86_BUILTIN_PADDUSW256,
26763 IX86_BUILTIN_PALIGNR256,
26764 IX86_BUILTIN_AND256I,
26765 IX86_BUILTIN_ANDNOT256I,
26766 IX86_BUILTIN_PAVGB256,
26767 IX86_BUILTIN_PAVGW256,
26768 IX86_BUILTIN_PBLENDVB256,
26769 IX86_BUILTIN_PBLENDVW256,
26770 IX86_BUILTIN_PCMPEQB256,
26771 IX86_BUILTIN_PCMPEQW256,
26772 IX86_BUILTIN_PCMPEQD256,
26773 IX86_BUILTIN_PCMPEQQ256,
26774 IX86_BUILTIN_PCMPGTB256,
26775 IX86_BUILTIN_PCMPGTW256,
26776 IX86_BUILTIN_PCMPGTD256,
26777 IX86_BUILTIN_PCMPGTQ256,
26778 IX86_BUILTIN_PHADDW256,
26779 IX86_BUILTIN_PHADDD256,
26780 IX86_BUILTIN_PHADDSW256,
26781 IX86_BUILTIN_PHSUBW256,
26782 IX86_BUILTIN_PHSUBD256,
26783 IX86_BUILTIN_PHSUBSW256,
26784 IX86_BUILTIN_PMADDUBSW256,
26785 IX86_BUILTIN_PMADDWD256,
26786 IX86_BUILTIN_PMAXSB256,
26787 IX86_BUILTIN_PMAXSW256,
26788 IX86_BUILTIN_PMAXSD256,
26789 IX86_BUILTIN_PMAXUB256,
26790 IX86_BUILTIN_PMAXUW256,
26791 IX86_BUILTIN_PMAXUD256,
26792 IX86_BUILTIN_PMINSB256,
26793 IX86_BUILTIN_PMINSW256,
26794 IX86_BUILTIN_PMINSD256,
26795 IX86_BUILTIN_PMINUB256,
26796 IX86_BUILTIN_PMINUW256,
26797 IX86_BUILTIN_PMINUD256,
26798 IX86_BUILTIN_PMOVMSKB256,
26799 IX86_BUILTIN_PMOVSXBW256,
26800 IX86_BUILTIN_PMOVSXBD256,
26801 IX86_BUILTIN_PMOVSXBQ256,
26802 IX86_BUILTIN_PMOVSXWD256,
26803 IX86_BUILTIN_PMOVSXWQ256,
26804 IX86_BUILTIN_PMOVSXDQ256,
26805 IX86_BUILTIN_PMOVZXBW256,
26806 IX86_BUILTIN_PMOVZXBD256,
26807 IX86_BUILTIN_PMOVZXBQ256,
26808 IX86_BUILTIN_PMOVZXWD256,
26809 IX86_BUILTIN_PMOVZXWQ256,
26810 IX86_BUILTIN_PMOVZXDQ256,
26811 IX86_BUILTIN_PMULDQ256,
26812 IX86_BUILTIN_PMULHRSW256,
26813 IX86_BUILTIN_PMULHUW256,
26814 IX86_BUILTIN_PMULHW256,
26815 IX86_BUILTIN_PMULLW256,
26816 IX86_BUILTIN_PMULLD256,
26817 IX86_BUILTIN_PMULUDQ256,
26818 IX86_BUILTIN_POR256,
26819 IX86_BUILTIN_PSADBW256,
26820 IX86_BUILTIN_PSHUFB256,
26821 IX86_BUILTIN_PSHUFD256,
26822 IX86_BUILTIN_PSHUFHW256,
26823 IX86_BUILTIN_PSHUFLW256,
26824 IX86_BUILTIN_PSIGNB256,
26825 IX86_BUILTIN_PSIGNW256,
26826 IX86_BUILTIN_PSIGND256,
26827 IX86_BUILTIN_PSLLDQI256,
26828 IX86_BUILTIN_PSLLWI256,
26829 IX86_BUILTIN_PSLLW256,
26830 IX86_BUILTIN_PSLLDI256,
26831 IX86_BUILTIN_PSLLD256,
26832 IX86_BUILTIN_PSLLQI256,
26833 IX86_BUILTIN_PSLLQ256,
26834 IX86_BUILTIN_PSRAWI256,
26835 IX86_BUILTIN_PSRAW256,
26836 IX86_BUILTIN_PSRADI256,
26837 IX86_BUILTIN_PSRAD256,
26838 IX86_BUILTIN_PSRLDQI256,
26839 IX86_BUILTIN_PSRLWI256,
26840 IX86_BUILTIN_PSRLW256,
26841 IX86_BUILTIN_PSRLDI256,
26842 IX86_BUILTIN_PSRLD256,
26843 IX86_BUILTIN_PSRLQI256,
26844 IX86_BUILTIN_PSRLQ256,
26845 IX86_BUILTIN_PSUBB256,
26846 IX86_BUILTIN_PSUBW256,
26847 IX86_BUILTIN_PSUBD256,
26848 IX86_BUILTIN_PSUBQ256,
26849 IX86_BUILTIN_PSUBSB256,
26850 IX86_BUILTIN_PSUBSW256,
26851 IX86_BUILTIN_PSUBUSB256,
26852 IX86_BUILTIN_PSUBUSW256,
26853 IX86_BUILTIN_PUNPCKHBW256,
26854 IX86_BUILTIN_PUNPCKHWD256,
26855 IX86_BUILTIN_PUNPCKHDQ256,
26856 IX86_BUILTIN_PUNPCKHQDQ256,
26857 IX86_BUILTIN_PUNPCKLBW256,
26858 IX86_BUILTIN_PUNPCKLWD256,
26859 IX86_BUILTIN_PUNPCKLDQ256,
26860 IX86_BUILTIN_PUNPCKLQDQ256,
26861 IX86_BUILTIN_PXOR256,
26862 IX86_BUILTIN_MOVNTDQA256,
26863 IX86_BUILTIN_VBROADCASTSS_PS,
26864 IX86_BUILTIN_VBROADCASTSS_PS256,
26865 IX86_BUILTIN_VBROADCASTSD_PD256,
26866 IX86_BUILTIN_VBROADCASTSI256,
26867 IX86_BUILTIN_PBLENDD256,
26868 IX86_BUILTIN_PBLENDD128,
26869 IX86_BUILTIN_PBROADCASTB256,
26870 IX86_BUILTIN_PBROADCASTW256,
26871 IX86_BUILTIN_PBROADCASTD256,
26872 IX86_BUILTIN_PBROADCASTQ256,
26873 IX86_BUILTIN_PBROADCASTB128,
26874 IX86_BUILTIN_PBROADCASTW128,
26875 IX86_BUILTIN_PBROADCASTD128,
26876 IX86_BUILTIN_PBROADCASTQ128,
26877 IX86_BUILTIN_VPERMVARSI256,
26878 IX86_BUILTIN_VPERMDF256,
26879 IX86_BUILTIN_VPERMVARSF256,
26880 IX86_BUILTIN_VPERMDI256,
26881 IX86_BUILTIN_VPERMTI256,
26882 IX86_BUILTIN_VEXTRACT128I256,
26883 IX86_BUILTIN_VINSERT128I256,
26884 IX86_BUILTIN_MASKLOADD,
26885 IX86_BUILTIN_MASKLOADQ,
26886 IX86_BUILTIN_MASKLOADD256,
26887 IX86_BUILTIN_MASKLOADQ256,
26888 IX86_BUILTIN_MASKSTORED,
26889 IX86_BUILTIN_MASKSTOREQ,
26890 IX86_BUILTIN_MASKSTORED256,
26891 IX86_BUILTIN_MASKSTOREQ256,
26892 IX86_BUILTIN_PSLLVV4DI,
26893 IX86_BUILTIN_PSLLVV2DI,
26894 IX86_BUILTIN_PSLLVV8SI,
26895 IX86_BUILTIN_PSLLVV4SI,
26896 IX86_BUILTIN_PSRAVV8SI,
26897 IX86_BUILTIN_PSRAVV4SI,
26898 IX86_BUILTIN_PSRLVV4DI,
26899 IX86_BUILTIN_PSRLVV2DI,
26900 IX86_BUILTIN_PSRLVV8SI,
26901 IX86_BUILTIN_PSRLVV4SI,
26903 IX86_BUILTIN_GATHERSIV2DF,
26904 IX86_BUILTIN_GATHERSIV4DF,
26905 IX86_BUILTIN_GATHERDIV2DF,
26906 IX86_BUILTIN_GATHERDIV4DF,
26907 IX86_BUILTIN_GATHERSIV4SF,
26908 IX86_BUILTIN_GATHERSIV8SF,
26909 IX86_BUILTIN_GATHERDIV4SF,
26910 IX86_BUILTIN_GATHERDIV8SF,
26911 IX86_BUILTIN_GATHERSIV2DI,
26912 IX86_BUILTIN_GATHERSIV4DI,
26913 IX86_BUILTIN_GATHERDIV2DI,
26914 IX86_BUILTIN_GATHERDIV4DI,
26915 IX86_BUILTIN_GATHERSIV4SI,
26916 IX86_BUILTIN_GATHERSIV8SI,
26917 IX86_BUILTIN_GATHERDIV4SI,
26918 IX86_BUILTIN_GATHERDIV8SI,
26920 /* Alternate 4 element gather for the vectorizer where
26921 all operands are 32-byte wide. */
26922 IX86_BUILTIN_GATHERALTSIV4DF,
26923 IX86_BUILTIN_GATHERALTDIV8SF,
26924 IX86_BUILTIN_GATHERALTSIV4DI,
26925 IX86_BUILTIN_GATHERALTDIV8SI,
26927 /* TFmode support builtins. */
26928 IX86_BUILTIN_INFQ,
26929 IX86_BUILTIN_HUGE_VALQ,
26930 IX86_BUILTIN_FABSQ,
26931 IX86_BUILTIN_COPYSIGNQ,
26933 /* Vectorizer support builtins. */
26934 IX86_BUILTIN_CPYSGNPS,
26935 IX86_BUILTIN_CPYSGNPD,
26936 IX86_BUILTIN_CPYSGNPS256,
26937 IX86_BUILTIN_CPYSGNPD256,
26939 /* FMA4 instructions. */
26940 IX86_BUILTIN_VFMADDSS,
26941 IX86_BUILTIN_VFMADDSD,
26942 IX86_BUILTIN_VFMADDPS,
26943 IX86_BUILTIN_VFMADDPD,
26944 IX86_BUILTIN_VFMADDPS256,
26945 IX86_BUILTIN_VFMADDPD256,
26946 IX86_BUILTIN_VFMADDSUBPS,
26947 IX86_BUILTIN_VFMADDSUBPD,
26948 IX86_BUILTIN_VFMADDSUBPS256,
26949 IX86_BUILTIN_VFMADDSUBPD256,
26951 /* FMA3 instructions. */
26952 IX86_BUILTIN_VFMADDSS3,
26953 IX86_BUILTIN_VFMADDSD3,
26955 /* XOP instructions. */
26956 IX86_BUILTIN_VPCMOV,
26957 IX86_BUILTIN_VPCMOV_V2DI,
26958 IX86_BUILTIN_VPCMOV_V4SI,
26959 IX86_BUILTIN_VPCMOV_V8HI,
26960 IX86_BUILTIN_VPCMOV_V16QI,
26961 IX86_BUILTIN_VPCMOV_V4SF,
26962 IX86_BUILTIN_VPCMOV_V2DF,
26963 IX86_BUILTIN_VPCMOV256,
26964 IX86_BUILTIN_VPCMOV_V4DI256,
26965 IX86_BUILTIN_VPCMOV_V8SI256,
26966 IX86_BUILTIN_VPCMOV_V16HI256,
26967 IX86_BUILTIN_VPCMOV_V32QI256,
26968 IX86_BUILTIN_VPCMOV_V8SF256,
26969 IX86_BUILTIN_VPCMOV_V4DF256,
26971 IX86_BUILTIN_VPPERM,
26973 IX86_BUILTIN_VPMACSSWW,
26974 IX86_BUILTIN_VPMACSWW,
26975 IX86_BUILTIN_VPMACSSWD,
26976 IX86_BUILTIN_VPMACSWD,
26977 IX86_BUILTIN_VPMACSSDD,
26978 IX86_BUILTIN_VPMACSDD,
26979 IX86_BUILTIN_VPMACSSDQL,
26980 IX86_BUILTIN_VPMACSSDQH,
26981 IX86_BUILTIN_VPMACSDQL,
26982 IX86_BUILTIN_VPMACSDQH,
26983 IX86_BUILTIN_VPMADCSSWD,
26984 IX86_BUILTIN_VPMADCSWD,
26986 IX86_BUILTIN_VPHADDBW,
26987 IX86_BUILTIN_VPHADDBD,
26988 IX86_BUILTIN_VPHADDBQ,
26989 IX86_BUILTIN_VPHADDWD,
26990 IX86_BUILTIN_VPHADDWQ,
26991 IX86_BUILTIN_VPHADDDQ,
26992 IX86_BUILTIN_VPHADDUBW,
26993 IX86_BUILTIN_VPHADDUBD,
26994 IX86_BUILTIN_VPHADDUBQ,
26995 IX86_BUILTIN_VPHADDUWD,
26996 IX86_BUILTIN_VPHADDUWQ,
26997 IX86_BUILTIN_VPHADDUDQ,
26998 IX86_BUILTIN_VPHSUBBW,
26999 IX86_BUILTIN_VPHSUBWD,
27000 IX86_BUILTIN_VPHSUBDQ,
27002 IX86_BUILTIN_VPROTB,
27003 IX86_BUILTIN_VPROTW,
27004 IX86_BUILTIN_VPROTD,
27005 IX86_BUILTIN_VPROTQ,
27006 IX86_BUILTIN_VPROTB_IMM,
27007 IX86_BUILTIN_VPROTW_IMM,
27008 IX86_BUILTIN_VPROTD_IMM,
27009 IX86_BUILTIN_VPROTQ_IMM,
27011 IX86_BUILTIN_VPSHLB,
27012 IX86_BUILTIN_VPSHLW,
27013 IX86_BUILTIN_VPSHLD,
27014 IX86_BUILTIN_VPSHLQ,
27015 IX86_BUILTIN_VPSHAB,
27016 IX86_BUILTIN_VPSHAW,
27017 IX86_BUILTIN_VPSHAD,
27018 IX86_BUILTIN_VPSHAQ,
27020 IX86_BUILTIN_VFRCZSS,
27021 IX86_BUILTIN_VFRCZSD,
27022 IX86_BUILTIN_VFRCZPS,
27023 IX86_BUILTIN_VFRCZPD,
27024 IX86_BUILTIN_VFRCZPS256,
27025 IX86_BUILTIN_VFRCZPD256,
27027 IX86_BUILTIN_VPCOMEQUB,
27028 IX86_BUILTIN_VPCOMNEUB,
27029 IX86_BUILTIN_VPCOMLTUB,
27030 IX86_BUILTIN_VPCOMLEUB,
27031 IX86_BUILTIN_VPCOMGTUB,
27032 IX86_BUILTIN_VPCOMGEUB,
27033 IX86_BUILTIN_VPCOMFALSEUB,
27034 IX86_BUILTIN_VPCOMTRUEUB,
27036 IX86_BUILTIN_VPCOMEQUW,
27037 IX86_BUILTIN_VPCOMNEUW,
27038 IX86_BUILTIN_VPCOMLTUW,
27039 IX86_BUILTIN_VPCOMLEUW,
27040 IX86_BUILTIN_VPCOMGTUW,
27041 IX86_BUILTIN_VPCOMGEUW,
27042 IX86_BUILTIN_VPCOMFALSEUW,
27043 IX86_BUILTIN_VPCOMTRUEUW,
27045 IX86_BUILTIN_VPCOMEQUD,
27046 IX86_BUILTIN_VPCOMNEUD,
27047 IX86_BUILTIN_VPCOMLTUD,
27048 IX86_BUILTIN_VPCOMLEUD,
27049 IX86_BUILTIN_VPCOMGTUD,
27050 IX86_BUILTIN_VPCOMGEUD,
27051 IX86_BUILTIN_VPCOMFALSEUD,
27052 IX86_BUILTIN_VPCOMTRUEUD,
27054 IX86_BUILTIN_VPCOMEQUQ,
27055 IX86_BUILTIN_VPCOMNEUQ,
27056 IX86_BUILTIN_VPCOMLTUQ,
27057 IX86_BUILTIN_VPCOMLEUQ,
27058 IX86_BUILTIN_VPCOMGTUQ,
27059 IX86_BUILTIN_VPCOMGEUQ,
27060 IX86_BUILTIN_VPCOMFALSEUQ,
27061 IX86_BUILTIN_VPCOMTRUEUQ,
27063 IX86_BUILTIN_VPCOMEQB,
27064 IX86_BUILTIN_VPCOMNEB,
27065 IX86_BUILTIN_VPCOMLTB,
27066 IX86_BUILTIN_VPCOMLEB,
27067 IX86_BUILTIN_VPCOMGTB,
27068 IX86_BUILTIN_VPCOMGEB,
27069 IX86_BUILTIN_VPCOMFALSEB,
27070 IX86_BUILTIN_VPCOMTRUEB,
27072 IX86_BUILTIN_VPCOMEQW,
27073 IX86_BUILTIN_VPCOMNEW,
27074 IX86_BUILTIN_VPCOMLTW,
27075 IX86_BUILTIN_VPCOMLEW,
27076 IX86_BUILTIN_VPCOMGTW,
27077 IX86_BUILTIN_VPCOMGEW,
27078 IX86_BUILTIN_VPCOMFALSEW,
27079 IX86_BUILTIN_VPCOMTRUEW,
27081 IX86_BUILTIN_VPCOMEQD,
27082 IX86_BUILTIN_VPCOMNED,
27083 IX86_BUILTIN_VPCOMLTD,
27084 IX86_BUILTIN_VPCOMLED,
27085 IX86_BUILTIN_VPCOMGTD,
27086 IX86_BUILTIN_VPCOMGED,
27087 IX86_BUILTIN_VPCOMFALSED,
27088 IX86_BUILTIN_VPCOMTRUED,
27090 IX86_BUILTIN_VPCOMEQQ,
27091 IX86_BUILTIN_VPCOMNEQ,
27092 IX86_BUILTIN_VPCOMLTQ,
27093 IX86_BUILTIN_VPCOMLEQ,
27094 IX86_BUILTIN_VPCOMGTQ,
27095 IX86_BUILTIN_VPCOMGEQ,
27096 IX86_BUILTIN_VPCOMFALSEQ,
27097 IX86_BUILTIN_VPCOMTRUEQ,
27099 /* LWP instructions. */
27100 IX86_BUILTIN_LLWPCB,
27101 IX86_BUILTIN_SLWPCB,
27102 IX86_BUILTIN_LWPVAL32,
27103 IX86_BUILTIN_LWPVAL64,
27104 IX86_BUILTIN_LWPINS32,
27105 IX86_BUILTIN_LWPINS64,
27107 IX86_BUILTIN_CLZS,
27109 /* RTM */
27110 IX86_BUILTIN_XBEGIN,
27111 IX86_BUILTIN_XEND,
27112 IX86_BUILTIN_XABORT,
27113 IX86_BUILTIN_XTEST,
27115 /* BMI instructions. */
27116 IX86_BUILTIN_BEXTR32,
27117 IX86_BUILTIN_BEXTR64,
27118 IX86_BUILTIN_CTZS,
27120 /* TBM instructions. */
27121 IX86_BUILTIN_BEXTRI32,
27122 IX86_BUILTIN_BEXTRI64,
27124 /* BMI2 instructions. */
27125 IX86_BUILTIN_BZHI32,
27126 IX86_BUILTIN_BZHI64,
27127 IX86_BUILTIN_PDEP32,
27128 IX86_BUILTIN_PDEP64,
27129 IX86_BUILTIN_PEXT32,
27130 IX86_BUILTIN_PEXT64,
27132 /* ADX instructions. */
27133 IX86_BUILTIN_ADDCARRYX32,
27134 IX86_BUILTIN_ADDCARRYX64,
27136 /* FSGSBASE instructions. */
27137 IX86_BUILTIN_RDFSBASE32,
27138 IX86_BUILTIN_RDFSBASE64,
27139 IX86_BUILTIN_RDGSBASE32,
27140 IX86_BUILTIN_RDGSBASE64,
27141 IX86_BUILTIN_WRFSBASE32,
27142 IX86_BUILTIN_WRFSBASE64,
27143 IX86_BUILTIN_WRGSBASE32,
27144 IX86_BUILTIN_WRGSBASE64,
27146 /* RDRND instructions. */
27147 IX86_BUILTIN_RDRAND16_STEP,
27148 IX86_BUILTIN_RDRAND32_STEP,
27149 IX86_BUILTIN_RDRAND64_STEP,
27151 /* RDSEED instructions. */
27152 IX86_BUILTIN_RDSEED16_STEP,
27153 IX86_BUILTIN_RDSEED32_STEP,
27154 IX86_BUILTIN_RDSEED64_STEP,
27156 /* F16C instructions. */
27157 IX86_BUILTIN_CVTPH2PS,
27158 IX86_BUILTIN_CVTPH2PS256,
27159 IX86_BUILTIN_CVTPS2PH,
27160 IX86_BUILTIN_CVTPS2PH256,
27162 /* CFString built-in for darwin */
27163 IX86_BUILTIN_CFSTRING,
27165 /* Builtins to get CPU type and supported features. */
27166 IX86_BUILTIN_CPU_INIT,
27167 IX86_BUILTIN_CPU_IS,
27168 IX86_BUILTIN_CPU_SUPPORTS,
27170 IX86_BUILTIN_MAX
27171 };
27173 /* Table for the ix86 builtin decls. */
27176 /* Table of all of the builtin functions that are possible with different ISA's
27177 but are waiting to be built until a function is declared to use that
27178 ISA. */
27185 };
27190 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
27191 of which isa_flags to use in the ix86_builtins_isa array. Stores the
27192 function decl in the ix86_builtins array. Returns the function decl or
27193 NULL_TREE, if the builtin was not added.
27195 If the front end has a special hook for builtin functions, delay adding
27196 builtin functions that aren't in the current ISA until the ISA is changed
27197 with function specific optimization. Doing so, can save about 300K for the
27198 default compiler. When the builtin is expanded, check at that time whether
27199 it is valid.
27201 If the front end doesn't have a special hook, record all builtins, even if
27202 it isn't an instruction set in the current ISA in case the user uses
27203 function specific options for a different ISA, so that we don't get scope
27204 errors if a builtin is added in the middle of a function scope. */
27210 {
27214 {
27223 {
27229 }
27230 else
27231 {
27237 }
27238 }
27241 }
27243 /* Like def_builtin, but also marks the function decl "const". */
27248 {
27252 else
27256 }
27258 /* Add any new builtin functions for a given ISA that may not have been
27259 declared. This saves a bit of space compared to adding all of the
27260 declarations to the tree, even if we didn't use them. */
27262 static void
27264 {
27268 {
27271 {
27274 /* Don't define the builtin again. */
27280 NULL_TREE);
27285 }
27286 }
27287 }
27289 /* Bits for builtin_description.flag. */
27291 /* Set when we don't support the comparison natively, and should
27292 swap_comparison in order to support it. */
27293 #define BUILTIN_DESC_SWAP_OPERANDS 1
27295 struct builtin_description
27296 {
27303 };
27306 {
27307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
27308 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
27309 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
27310 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
27311 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
27312 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
27313 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
27314 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
27315 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
27316 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
27317 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
27318 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
27319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
27321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
27322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
27323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
27324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
27325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
27327 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
27328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
27329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
27330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
27331 };
27334 {
27335 /* SSE4.2 */
27336 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
27337 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
27338 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
27339 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
27340 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
27341 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
27342 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
27343 };
27346 {
27347 /* SSE4.2 */
27348 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
27349 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
27350 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
27351 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
27352 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
27353 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
27354 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
27355 };
27357 /* Special builtins with variable number of arguments. */
27359 {
27360 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
27361 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
27362 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
27364 /* MMX */
27365 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
27367 /* 3DNow! */
27368 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
27370 /* FXSR, XSAVE and XSAVEOPT */
27371 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
27372 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
27373 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27374 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27375 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27377 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
27378 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
27379 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27380 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27381 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
27383 /* SSE */
27384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27385 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27386 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
27388 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
27389 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
27390 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
27391 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
27393 /* SSE or 3DNow!A */
27394 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27395 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
27397 /* SSE2 */
27398 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
27402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
27404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
27405 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
27406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
27407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
27409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
27410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
27412 /* SSE3 */
27413 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
27415 /* SSE4.1 */
27416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
27418 /* SSE4A */
27419 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27420 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27422 /* AVX */
27423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
27424 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
27426 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
27427 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
27428 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
27429 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
27430 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
27432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
27433 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
27434 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
27435 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
27436 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
27437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
27438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
27440 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
27441 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
27442 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
27444 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
27445 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
27446 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
27447 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
27448 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
27449 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
27450 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
27451 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
27453 /* AVX2 */
27454 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
27455 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
27456 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
27457 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
27458 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
27459 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
27460 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
27461 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
27462 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
27464 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
27465 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
27466 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
27467 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
27468 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
27469 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
27471 /* FSGSBASE */
27472 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27473 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
27474 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27475 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
27476 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
27477 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
27478 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
27479 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
27481 /* RTM */
27482 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27483 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
27484 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
27485 };
27487 /* Builtins with variable number of arguments. */
27489 {
27490 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
27491 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
27492 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
27493 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27494 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27495 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27496 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27498 /* MMX */
27499 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27500 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27501 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27502 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27503 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27504 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27506 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27507 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27508 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27509 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27510 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27511 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27512 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27513 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27515 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27516 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27518 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27519 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27520 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27521 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27523 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27524 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27525 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27526 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27527 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27528 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27530 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27531 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27532 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27533 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27534 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27535 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27537 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27538 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27539 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27541 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27543 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27544 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27545 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27546 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27547 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27548 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27550 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27551 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27552 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27553 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27554 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27555 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27557 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27558 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27559 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27560 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27562 /* 3DNow! */
27563 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27564 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27565 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27566 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27568 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27569 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27570 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27571 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27572 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27573 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27574 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27575 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27576 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27577 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27578 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27579 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27580 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27581 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27582 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27584 /* 3DNow!A */
27585 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27586 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27587 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27588 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27589 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27590 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27592 /* SSE */
27593 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27594 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27595 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27596 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27597 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27598 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27599 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27600 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27601 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27602 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27603 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27604 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27606 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27608 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27609 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27610 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27611 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27612 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27613 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27614 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27615 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27617 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27618 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27619 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27620 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27621 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27622 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27623 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27624 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27625 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27626 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27627 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27628 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27629 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27630 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27631 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27632 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27633 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27634 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27635 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27636 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27638 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27639 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27640 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27641 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27643 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27644 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27645 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27646 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27648 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27650 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27651 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27652 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27653 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27654 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27656 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27657 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27658 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27660 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27662 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27663 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27664 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27666 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27667 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27669 /* SSE MMX or 3Dnow!A */
27670 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27671 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27672 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27674 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27675 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27676 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27677 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27679 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27680 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27682 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27684 /* SSE2 */
27685 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27687 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27688 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27689 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27690 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27691 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27693 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27694 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27695 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27696 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27697 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27699 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27701 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27702 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27703 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27704 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27706 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27707 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27708 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27710 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27711 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27712 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27713 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27714 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27715 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27716 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27717 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27719 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27720 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27721 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27722 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27723 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27724 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27725 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27726 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27727 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27728 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27729 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27730 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27731 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27732 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27733 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27734 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27735 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27736 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27737 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27738 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27740 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27741 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27742 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27743 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27745 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27746 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27747 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27748 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27750 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27752 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27753 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27754 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27756 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27758 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27759 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27760 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27761 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27762 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27763 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27764 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27765 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27767 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27768 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27769 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27770 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27771 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27772 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27773 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27774 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27776 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27777 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27779 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27781 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27782 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27784 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27787 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27788 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27789 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27790 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27791 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27792 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27794 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27795 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27796 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27797 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27799 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27800 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27801 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27802 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27803 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27804 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27805 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27806 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27812 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27813 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27815 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27816 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27818 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27820 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27821 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27822 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27823 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27826 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27827 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27828 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27829 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27830 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27831 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27833 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27834 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27835 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27836 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27837 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27838 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27839 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27841 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27842 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27843 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27844 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27852 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27854 /* SSE2 MMX */
27855 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27856 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27858 /* SSE3 */
27859 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27860 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27862 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27863 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27864 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27865 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27866 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27867 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27869 /* SSSE3 */
27870 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27871 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27872 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27873 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27874 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27875 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27877 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27878 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27879 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27880 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27881 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27882 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27883 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27884 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27885 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27886 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27887 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27888 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27889 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27890 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27891 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27892 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27893 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27894 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27895 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27896 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27897 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27898 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27899 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27900 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27902 /* SSSE3. */
27903 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27904 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27906 /* SSE4.1 */
27907 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27908 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27909 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27910 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27911 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27912 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27913 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27914 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27915 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27916 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27918 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27919 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27920 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27921 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27922 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27923 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27924 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27925 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27926 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27927 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27928 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27929 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27930 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27932 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27933 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27934 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27935 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27936 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27937 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27938 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27939 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27940 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27941 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27942 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27943 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27945 /* SSE4.1 */
27946 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27947 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27948 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27949 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27951 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27952 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27953 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27954 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27956 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27957 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27959 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27960 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27962 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27963 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27964 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27965 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27967 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27968 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27970 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27971 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27973 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27974 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27975 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27977 /* SSE4.2 */
27978 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27979 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27980 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27981 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27982 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27984 /* SSE4A */
27985 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27986 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27987 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27988 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27990 /* AES */
27991 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27992 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27994 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27995 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27996 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27997 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27999 /* PCLMUL */
28000 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
28002 /* AVX */
28003 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28004 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28006 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28007 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28008 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28009 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28011 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28012 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28013 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28015 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28017 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28018 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28019 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28020 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28021 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28022 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28023 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28024 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28025 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28026 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28027 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28028 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28030 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
28031 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
28032 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
28033 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
28035 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28036 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28037 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
28038 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
28039 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28040 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28042 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28043 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28044 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
28045 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
28046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28047 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28048 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
28049 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
28050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
28051 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
28052 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
28053 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
28054 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
28056 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
28057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
28058 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
28060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
28061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
28062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
28063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
28064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
28066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
28067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
28068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
28070 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28072 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28074 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28076 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28078 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28080 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28082 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28083 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
28085 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
28086 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
28087 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
28088 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
28090 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
28091 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
28093 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
28094 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
28096 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
28097 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
28098 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
28099 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
28101 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
28102 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
28104 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
28105 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
28107 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28108 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28109 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28110 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28112 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
28113 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
28114 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
28115 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
28116 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
28117 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
28119 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28120 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28121 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
28122 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28123 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28124 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
28125 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28126 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28127 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
28128 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28129 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28130 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
28131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
28135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
28136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
28138 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
28139 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
28141 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
28143 /* AVX2 */
28144 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
28145 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
28146 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
28147 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
28148 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
28149 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
28150 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
28151 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
28152 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28153 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28154 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28155 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28156 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28157 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28158 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28159 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28160 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
28161 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28162 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28163 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28164 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28165 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
28166 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
28167 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28168 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28169 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28170 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28171 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28172 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28173 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28174 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28175 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28176 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28177 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28178 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28179 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28180 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28181 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
28182 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
28183 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28184 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28185 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28186 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28187 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28188 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28189 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28190 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28191 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28192 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28193 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28194 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28195 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
28196 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
28197 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
28198 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
28199 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
28200 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
28201 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
28202 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
28203 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
28204 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
28205 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
28206 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
28207 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
28208 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
28209 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28210 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28211 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28212 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28213 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28214 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
28215 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28216 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
28217 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28218 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
28219 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
28220 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
28221 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28222 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28223 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28224 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
28225 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28226 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28227 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28228 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28229 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
28230 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
28231 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28232 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28233 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28234 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28235 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
28236 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
28237 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
28238 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
28239 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
28240 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
28241 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
28242 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28243 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28244 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28245 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28246 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28247 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28248 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28249 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28250 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28251 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28252 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28253 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28254 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
28255 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
28256 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28257 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28258 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28259 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
28260 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
28261 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
28262 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
28263 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
28264 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
28265 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
28266 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
28267 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
28268 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
28269 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
28270 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
28271 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
28272 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
28273 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28274 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
28275 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
28276 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
28277 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
28278 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
28279 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
28280 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28281 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28282 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28283 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28284 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28285 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28286 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
28287 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
28288 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
28289 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
28291 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
28293 /* BMI */
28294 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28295 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28296 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
28298 /* TBM */
28299 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28300 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28302 /* F16C */
28303 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
28304 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
28305 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
28306 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
28308 /* BMI2 */
28309 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28310 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28311 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28312 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28313 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
28314 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
28315 };
28317 /* FMA4 and XOP. */
28318 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
28319 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
28320 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
28321 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
28322 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
28323 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
28324 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
28325 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
28326 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
28327 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
28328 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
28329 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
28330 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
28331 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
28332 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
28333 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
28334 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
28335 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
28336 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
28337 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
28338 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
28339 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
28340 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
28341 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
28342 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
28343 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
28344 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
28345 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
28346 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
28347 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
28348 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
28349 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
28350 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
28351 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
28352 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
28353 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
28354 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
28355 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
28356 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
28357 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
28358 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
28359 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
28360 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
28361 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
28362 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
28363 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
28364 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
28365 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
28366 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
28367 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
28368 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
28369 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
28372 {
28413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
28414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
28415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
28416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
28417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
28418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
28419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
28421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
28422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
28423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
28424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
28425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
28426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
28427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
28429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
28431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
28432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
28433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
28436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
28437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
28446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
28447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
28448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
28449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
28450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
28451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
28452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
28454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
28455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
28456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
28458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
28459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
28461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
28462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
28463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
28464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
28465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
28466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
28468 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
28470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
28471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
28473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
28476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
28477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
28479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
28485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
28486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
28487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
28488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
28489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
28490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
28492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
28493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
28496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
28497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
28498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
28500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
28501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
28504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
28505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
28506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
28508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28571 };
28572 \f
28573 /* TM vector builtins. */
28575 /* Reuse the existing x86-specific `struct builtin_description' cause
28576 we're lazy. Add casts to make them fit. */
28578 {
28579 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28580 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28581 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28582 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28583 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28584 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28585 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28587 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28588 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28589 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28590 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28591 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28592 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28593 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28595 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28596 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28597 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28598 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28599 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28600 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28601 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28603 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28604 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28605 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28606 };
28608 /* TM callbacks. */
28610 /* Return the builtin decl needed to load a vector of TYPE. */
28612 static tree
28614 {
28616 {
28618 {
28625 }
28626 }
28628 }
28630 /* Return the builtin decl needed to store a vector of TYPE. */
28632 static tree
28634 {
28636 {
28638 {
28645 }
28646 }
28648 }
28649 \f
28650 /* Initialize the transactional memory vector load/store builtins. */
28652 static void
28654 {
28658 tree decl;
28665 /* If there are no builtins defined, we must be compiling in a
28666 language without trans-mem support. */
28670 /* Use whatever attributes a normal TM load has. */
28674 /* Use whatever attributes a normal TM store has. */
28678 /* Use whatever attributes a normal TM log has. */
28686 {
28690 {
28698 {
28701 }
28703 {
28706 }
28707 else
28708 {
28711 }
28713 /* The builtin without the prefix for
28714 calling it directly. */
28716 attrs);
28717 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28718 set the TYPE_ATTRIBUTES. */
28722 }
28723 }
28724 }
28726 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28727 in the current target ISA to allow the user to compile particular modules
28728 with different target specific options that differ from the command line
28729 options. */
28730 static void
28732 {
28737 /* Add all special builtins with variable number of operands. */
28741 {
28747 }
28749 /* Add all builtins with variable number of operands. */
28753 {
28759 }
28761 /* pcmpestr[im] insns. */
28765 {
28768 else
28771 }
28773 /* pcmpistr[im] insns. */
28777 {
28780 else
28783 }
28785 /* comi/ucomi insns. */
28787 {
28790 else
28793 }
28795 /* SSE */
28801 /* SSE or 3DNow!A */
28804 IX86_BUILTIN_MASKMOVQ);
28806 /* SSE2 */
28815 /* SSE3. */
28821 /* AES */
28835 /* PCLMUL */
28839 /* RDRND */
28846 IX86_BUILTIN_RDRAND64_STEP);
28848 /* AVX2 */
28850 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28851 IX86_BUILTIN_GATHERSIV2DF);
28854 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28855 IX86_BUILTIN_GATHERSIV4DF);
28858 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28859 IX86_BUILTIN_GATHERDIV2DF);
28862 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28863 IX86_BUILTIN_GATHERDIV4DF);
28866 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28867 IX86_BUILTIN_GATHERSIV4SF);
28870 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28871 IX86_BUILTIN_GATHERSIV8SF);
28874 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28875 IX86_BUILTIN_GATHERDIV4SF);
28878 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28879 IX86_BUILTIN_GATHERDIV8SF);
28882 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28883 IX86_BUILTIN_GATHERSIV2DI);
28886 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28887 IX86_BUILTIN_GATHERSIV4DI);
28890 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28891 IX86_BUILTIN_GATHERDIV2DI);
28894 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28895 IX86_BUILTIN_GATHERDIV4DI);
28898 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28899 IX86_BUILTIN_GATHERSIV4SI);
28902 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28903 IX86_BUILTIN_GATHERSIV8SI);
28906 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28907 IX86_BUILTIN_GATHERDIV4SI);
28910 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28911 IX86_BUILTIN_GATHERDIV8SI);
28914 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28915 IX86_BUILTIN_GATHERALTSIV4DF);
28918 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28919 IX86_BUILTIN_GATHERALTDIV8SF);
28922 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28923 IX86_BUILTIN_GATHERALTSIV4DI);
28926 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28927 IX86_BUILTIN_GATHERALTDIV8SI);
28929 /* RTM. */
28933 /* MMX access to the vec_init patterns. */
28938 V4HI_FTYPE_HI_HI_HI_HI,
28939 IX86_BUILTIN_VEC_INIT_V4HI);
28942 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28943 IX86_BUILTIN_VEC_INIT_V8QI);
28945 /* Access to the vec_extract patterns. */
28967 /* Access to the vec_set patterns. */
28988 /* RDSEED */
28997 /* ADCX */
29002 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
29003 IX86_BUILTIN_ADDCARRYX64);
29005 /* Add FMA4 multi-arg argument instructions */
29007 {
29013 }
29014 }
29016 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
29017 to return a pointer to VERSION_DECL if the outcome of the expression
29018 formed by PREDICATE_CHAIN is true. This function will be called during
29019 version dispatch to decide which function version to execute. It returns
29020 the basic block at the end, to which more conditions can be added. */
29022 static basic_block
29025 {
29026 gimple return_stmt;
29028 gimple convert_stmt;
29029 gimple call_cond_stmt;
29030 gimple if_else_stmt;
29036 gimple_seq gseq;
29053 {
29061 }
29064 {
29079 else
29080 {
29081 gimple assign_stmt;
29082 /* Use MIN_EXPR to check if any integer is zero?.
29083 and_expr_var = min_expr <cond_var, and_expr_var> */
29091 }
29092 }
29095 integer_zero_node,
29125 }
29127 /* This parses the attribute arguments to target in DECL and determines
29128 the right builtin to use to match the platform specification.
29129 It returns the priority value for this version decl. If PREDICATE_LIST
29130 is not NULL, it stores the list of cpu features that need to be checked
29131 before dispatching this function. */
29133 static unsigned int
29135 {
29136 tree attrs;
29138 tree target_node;
29145 /* Priority of i386 features, greater value is higher priority. This is
29146 used to decide the order in which function dispatch must happen. For
29147 instance, a version specialized for SSE4.2 should be checked for dispatch
29148 before a version for SSE3, as SSE4.2 implies SSE3. */
29149 enum feature_priority
29150 {
29152 P_MMX,
29153 P_SSE,
29154 P_SSE2,
29155 P_SSE3,
29156 P_SSSE3,
29157 P_PROC_SSSE3,
29158 P_SSE4_a,
29159 P_PROC_SSE4_a,
29160 P_SSE4_1,
29161 P_SSE4_2,
29162 P_PROC_SSE4_2,
29163 P_POPCNT,
29164 P_AVX,
29165 P_AVX2,
29166 P_FMA,
29167 P_PROC_FMA
29168 };
29172 /* These are the target attribute strings for which a dispatcher is
29173 available, from fold_builtin_cpu. */
29175 static struct _feature_list
29176 {
29179 }
29181 {
29192 };
29195 static unsigned int NUM_FEATURES
29211 /* Return priority zero for default function. */
29215 /* Handle arch= if specified. For priority, set it to be 1 more than
29216 the best instruction set the processor can handle. For instance, if
29217 there is a version for atom and a version for ssse3 (the highest ISA
29218 priority for atom), the atom version must be checked for dispatch
29219 before the ssse3 version. */
29221 {
29230 {
29232 {
29257 }
29258 }
29263 {
29267 }
29270 {
29272 /* For a C string literal the length includes the trailing NULL. */
29275 predicate_chain);
29276 }
29277 }
29279 /* Process feature name. */
29286 {
29287 /* Do not process "arch=" */
29289 {
29292 }
29294 {
29296 {
29298 {
29303 predicate_chain);
29304 }
29305 /* Find the maximum priority feature. */
29310 }
29311 }
29313 {
29317 }
29319 }
29323 {
29326 attrs_str);
29328 }
29330 {
29333 }
29336 }
29338 /* This compares the priority of target features in function DECL1
29339 and DECL2. It returns positive value if DECL1 is higher priority,
29340 negative value if DECL2 is higher priority and 0 if they are the
29341 same. */
29343 static int
29345 {
29350 }
29352 /* V1 and V2 point to function versions with different priorities
29353 based on the target ISA. This function compares their priorities. */
29355 static int
29357 {
29359 {
29360 tree version_decl;
29361 tree predicate_chain;
29368 }
29370 /* This function generates the dispatch function for
29371 multi-versioned functions. DISPATCH_DECL is the function which will
29372 contain the dispatch logic. FNDECLS are the function choices for
29373 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
29374 in DISPATCH_DECL in which the dispatch code is generated. */
29376 static int
29380 {
29381 tree default_decl;
29382 gimple ifunc_cpu_init_stmt;
29383 gimple_seq gseq;
29385 tree ele;
29391 struct _function_version_info
29392 {
29393 tree version_decl;
29394 tree predicate_chain;
29402 /*fndecls_p is actually a vector. */
29405 /* At least one more version other than the default. */
29412 /* The first version in the vector is the default decl. */
29418 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
29419 constructors, so explicity call __builtin_cpu_init here. */
29430 {
29434 /* Get attribute string, parse it and find the right predicate decl.
29435 The predicate function could be a lengthy combination of many
29436 features, like arch-type and various isa-variants. */
29447 actual_versions++;
29448 }
29450 /* Sort the versions according to descending order of dispatch priority. The
29451 priority is based on the ISA. This is not a perfect solution. There
29452 could still be ambiguity. If more than one function version is suitable
29453 to execute, which one should be dispatched? In future, allow the user
29454 to specify a dispatch priority next to the version. */
29464 /* dispatch default version at the end. */
29470 }
29472 /* Comparator function to be used in qsort routine to sort attribute
29473 specification strings to "target". */
29475 static int
29477 {
29481 }
29483 /* ARGLIST is the argument to target attribute. This function tokenizes
29484 the comma separated arguments, sorts them and returns a string which
29485 is a unique identifier for the comma separated arguments. It also
29486 replaces non-identifier characters "=,-" with "_". */
29490 {
29491 tree arg;
29500 {
29505 argnum++;
29508 argnum++;
29509 }
29514 {
29520 }
29522 /* Replace "=,-" with "_". */
29535 {
29537 i++;
29539 }
29546 {
29551 }
29556 }
29558 /* This function changes the assembler name for functions that are
29559 versions. If DECL is a function version and has a "target"
29560 attribute, it appends the attribute string to its assembler name. */
29562 static tree
29564 {
29565 tree version_attr;
29573 "Function versions cannot be marked as gnu_inline,"
29582 /* target attribute string cannot be NULL. */
29586 version_string
29597 /* Allow assembler name to be modified if already set. */
29605 }
29607 /* This function returns true if FN1 and FN2 are versions of the same function,
29608 that is, the target strings of the function decls are different. This assumes
29609 that FN1 and FN2 have the same signature. */
29611 static bool
29613 {
29625 /* At least one function decl should have the target attribute specified. */
29629 /* Diagnose missing target attribute if one of the decls is already
29630 multi-versioned. */
29632 {
29634 {
29636 {
29641 }
29644 fn2);
29647 /* Prevent diagnosing of the same error multiple times. */
29652 }
29654 }
29659 /* The sorted target strings must be different for fn1 and fn2
29660 to be versions. */
29663 else
29670 }
29672 static tree
29674 {
29675 /* For function version, add the target suffix to the assembler name. */
29679 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29681 #endif
29684 }
29686 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29687 is true, append the full path name of the source file. */
29691 {
29699 /* Get a unique name that can be used globally without any chances
29700 of collision at link time. */
29710 /* Use '.' to concatenate names as it is demangler friendly. */
29713 suffix);
29714 else
29718 }
29720 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
29722 /* Make a dispatcher declaration for the multi-versioned function DECL.
29723 Calls to DECL function will be replaced with calls to the dispatcher
29724 by the front-end. Return the decl created. */
29726 static tree
29728 {
29729 tree func_decl;
29749 /* Mark this func as external, the resolver will flip it again if
29750 it gets generated. */
29752 /* This will be of type IFUNCs have to be externally visible. */
29756 }
29758 #endif
29760 /* Returns true if decl is multi-versioned and DECL is the default function,
29761 that is it is not tagged with target specific optimization. */
29763 static bool
29765 {
29774 }
29776 /* Make a dispatcher declaration for the multi-versioned function DECL.
29777 Calls to DECL function will be replaced with calls to the dispatcher
29778 by the front-end. Returns the decl of the dispatcher function. */
29780 static tree
29782 {
29804 /* Find the default version and make it the first node. */
29806 /* Go to the beginning of the chain. */
29811 {
29816 }
29818 /* If there is no default node, just return NULL. */
29822 /* Make default info the first node. */
29824 {
29831 }
29835 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
29837 {
29842 /* Right now, the dispatching is done via ifunc. */
29848 dispatcher_version_info
29853 /* Set the dispatcher for all the versions. */
29856 {
29859 }
29860 }
29861 else
29862 #endif
29863 {
29865 "multiversioning needs ifunc which is not supported "
29867 }
29870 }
29872 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29873 it to CHAIN. */
29875 static tree
29877 {
29878 tree attr_name;
29879 tree attr_arg_name;
29880 tree attr_args;
29881 tree attr;
29888 }
29890 /* Make the resolver function decl to dispatch the versions of
29891 a multi-versioned function, DEFAULT_DECL. Create an
29892 empty basic block in the resolver and store the pointer in
29893 EMPTY_BB. Return the decl of the resolver function. */
29895 static tree
29899 {
29904 /* IFUNC's have to be globally visible. So, if the default_decl is
29905 not, then the name of the IFUNC should be made unique. */
29909 /* Append the filename to the resolver function if the versions are
29910 not externally visible. This is because the resolver function has
29911 to be externally visible for the loader to find it. So, appending
29912 the filename will prevent conflicts with a resolver function from
29913 another module which is based on the same version name. */
29916 /* The resolver function should return a (void *). */
29927 /* IFUNC resolvers have to be externally visible. */
29931 /* Resolver is not external, body is generated. */
29941 {
29942 /* In this case, each translation unit with a call to this
29943 versioned function will put out a resolver. Ensure it
29944 is comdat to keep just one copy. */
29947 }
29948 /* Build result decl and add to function_decl. */
29964 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29968 /* Create the alias for dispatch to resolver here. */
29969 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29973 }
29975 /* Generate the dispatching code body to dispatch multi-versioned function
29976 DECL. The target hook is called to process the "target" attributes and
29977 provide the code to dispatch the right function at run-time. NODE points
29978 to the dispatcher decl whose body will be created. */
29980 static tree
29982 {
29983 tree resolver_decl;
29984 basic_block empty_bb;
29986 tree default_ver_decl;
30002 /* The first version in the chain corresponds to the default version. */
30005 /* node is going to be an alias, so remove the finalized bit. */
30019 {
30021 /* Check for virtual functions here again, as by this time it should
30022 have been determined if this function needs a vtable index or
30023 not. This happens for methods in derived classes that override
30024 virtual methods in base classes but are not explicitly marked as
30025 virtual. */
30030 }
30037 }
30038 /* This builds the processor_model struct type defined in
30039 libgcc/config/i386/cpuinfo.c */
30041 static tree
30043 {
30050 /* The first 3 fields are unsigned int. */
30052 {
30058 }
30060 /* The last field is an array of unsigned integers of size one. */
30071 }
30073 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
30075 static tree
30077 {
30078 tree new_decl;
30081 VAR_DECL,
30083 type);
30096 }
30098 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
30099 into an integer defined in libgcc/config/i386/cpuinfo.c */
30101 static tree
30103 {
30109 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
30110 enum processor_features
30111 {
30113 F_MMX,
30114 F_POPCNT,
30115 F_SSE,
30116 F_SSE2,
30117 F_SSE3,
30118 F_SSSE3,
30119 F_SSE4_1,
30120 F_SSE4_2,
30121 F_AVX,
30122 F_AVX2,
30123 F_MAX
30124 };
30126 /* These are the values for vendor types and cpu types and subtypes
30127 in cpuinfo.c. Cpu types and subtypes should be subtracted by
30128 the corresponding start value. */
30129 enum processor_model
30130 {
30132 M_AMD,
30133 M_CPU_TYPE_START,
30134 M_INTEL_ATOM,
30135 M_INTEL_CORE2,
30136 M_INTEL_COREI7,
30137 M_AMDFAM10H,
30138 M_AMDFAM15H,
30139 M_INTEL_SLM,
30140 M_CPU_SUBTYPE_START,
30141 M_INTEL_COREI7_NEHALEM,
30142 M_INTEL_COREI7_WESTMERE,
30143 M_INTEL_COREI7_SANDYBRIDGE,
30144 M_AMDFAM10H_BARCELONA,
30145 M_AMDFAM10H_SHANGHAI,
30146 M_AMDFAM10H_ISTANBUL,
30147 M_AMDFAM15H_BDVER1,
30148 M_AMDFAM15H_BDVER2,
30149 M_AMDFAM15H_BDVER3
30150 };
30152 static struct _arch_names_table
30153 {
30156 }
30158 {
30176 };
30178 static struct _isa_names_table
30179 {
30182 }
30184 {
30196 };
30210 {
30211 /* *args must be a expr that can contain other EXPRS leading to a
30212 STRING_CST. */
30214 {
30217 }
30219 }
30224 {
30225 tree ref;
30226 tree field;
30227 tree final;
30230 unsigned int NUM_ARCH_NAMES
30239 {
30243 }
30248 /* CPU types are stored in the next field. */
30251 {
30254 }
30256 /* CPU subtypes are stored in the next field. */
30258 {
30261 }
30263 /* Get the appropriate field in __cpu_model. */
30267 /* Check the value. */
30271 }
30273 {
30274 tree ref;
30275 tree array_elt;
30276 tree field;
30277 tree final;
30280 unsigned int NUM_ISA_NAMES
30289 {
30293 }
30296 /* Get the last field, which is __cpu_features. */
30300 /* Get the appropriate field: __cpu_model.__cpu_features */
30304 /* Access the 0th element of __cpu_features array. */
30309 /* Return __cpu_model.__cpu_features[0] & field_val */
30313 }
30315 }
30317 static tree
30320 {
30322 {
30327 {
30330 }
30331 }
30333 #ifdef SUBTARGET_FOLD_BUILTIN
30335 #endif
30338 }
30340 /* Make builtins to detect cpu type and features supported. NAME is
30341 the builtin name, CODE is the builtin code, and FTYPE is the function
30342 type of the builtin. */
30344 static void
30347 {
30348 tree decl;
30349 tree type;
30357 }
30359 /* Make builtins to get CPU type and features supported. The created
30360 builtins are :
30362 __builtin_cpu_init (), to detect cpu type and features,
30363 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
30364 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
30365 */
30367 static void
30369 {
30376 }
30378 /* Internal method for ix86_init_builtins. */
30380 static void
30382 {
30394 sysv_va_ref =
30397 fnvoid_va_end_ms =
30399 fnvoid_va_start_ms =
30401 fnvoid_va_end_sysv =
30403 fnvoid_va_start_sysv =
30405 NULL_TREE);
30406 fnvoid_va_copy_ms =
30408 NULL_TREE);
30409 fnvoid_va_copy_sysv =
30425 }
30427 static void
30429 {
30432 /* The __float80 type. */
30435 {
30436 /* The __float80 type. */
30441 }
30444 /* The __float128 type. */
30450 /* This macro is built by i386-builtin-types.awk. */
30451 DEFINE_BUILTIN_PRIMITIVE_TYPES;
30452 }
30454 static void
30456 {
30457 tree t;
30461 /* Builtins to get CPU type and features. */
30464 /* TFmode support builtins. */
30470 /* We will expand them to normal call if SSE isn't available since
30471 they are used by libgcc. */
30490 #ifdef SUBTARGET_INIT_BUILTINS
30491 SUBTARGET_INIT_BUILTINS;
30492 #endif
30493 }
30495 /* Return the ix86 builtin for CODE. */
30497 static tree
30499 {
30504 }
30506 /* Errors in the source file can cause expand_expr to return const0_rtx
30507 where we expect a vector. To avoid crashing, use one of the vector
30508 clear instructions. */
30509 static rtx
30511 {
30515 }
30517 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
30519 static rtx
30521 {
30522 rtx pat;
30542 {
30546 }
30560 }
30562 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30564 static rtx
30568 {
30569 rtx pat;
30577 rtx op;
30584 {
30664 }
30674 {
30681 {
30683 {
30686 {
30704 xop_rotl:
30706 {
30709 gcc_checking_assert
30711 }
30712 else
30713 {
30714 gcc_checking_assert
30725 }
30729 }
30730 }
30731 }
30732 else
30733 {
30734 non_constant:
30738 /* If we aren't optimizing, only allow one memory operand to be
30739 generated. */
30741 num_memory++;
30749 }
30753 }
30756 {
30767 else
30768 {
30774 }
30787 }
30794 }
30796 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30797 insns with vec_merge. */
30799 static rtx
30801 rtx target)
30802 {
30803 rtx pat;
30830 }
30832 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30834 static rtx
30837 {
30838 rtx pat;
30843 rtx op2;
30854 /* Swap operands if we have a comparison that isn't available in
30855 hardware. */
30857 {
30862 }
30882 }
30884 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30886 static rtx
30888 rtx target)
30889 {
30890 rtx pat;
30904 /* Swap operands if we have a comparison that isn't available in
30905 hardware. */
30907 {
30911 }
30932 const0_rtx)));
30935 }
30937 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30939 static rtx
30941 rtx target)
30942 {
30943 rtx pat;
30968 }
30970 static rtx
30973 {
30974 rtx pat;
30979 rtx op2;
31006 }
31008 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
31010 static rtx
31012 rtx target)
31013 {
31014 rtx pat;
31047 const0_rtx)));
31050 }
31052 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
31054 static rtx
31057 {
31058 rtx pat;
31096 {
31099 }
31102 {
31111 }
31113 {
31122 }
31123 else
31124 {
31131 }
31139 {
31144 emit_insn
31148 FLAGS_REG),
31149 const0_rtx)));
31151 }
31152 else
31154 }
31157 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
31159 static rtx
31162 {
31163 rtx pat;
31191 {
31194 }
31197 {
31206 }
31208 {
31217 }
31218 else
31219 {
31226 }
31234 {
31239 emit_insn
31243 FLAGS_REG),
31244 const0_rtx)));
31246 }
31247 else
31249 }
31251 /* Subroutine of ix86_expand_builtin to take care of insns with
31252 variable number of operands. */
31254 static rtx
31257 {
31262 struct
31263 {
31264 rtx op;
31276 {
31555 }
31560 {
31563 }
31566 {
31573 }
31574 else
31575 {
31578 }
31581 {
31588 {
31589 /* SIMD shift insns take either an 8-bit immediate or
31590 register as count. But builtin functions take int as
31591 count. If count doesn't match, we put it in register. */
31593 {
31597 }
31598 }
31600 {
31603 {
31657 {
31660 {
31663 }
31669 }
31671 }
31672 }
31673 else
31674 {
31678 /* If we aren't optimizing, only allow one memory operand to
31679 be generated. */
31681 num_memory++;
31684 {
31687 }
31688 else
31689 {
31692 }
31693 }
31697 }
31700 {
31717 }
31724 }
31726 /* Subroutine of ix86_expand_builtin to take care of special insns
31727 with variable number of operands. */
31729 static rtx
31732 {
31733 tree arg;
31736 struct
31737 {
31738 rtx op;
31748 {
31796 /* Reserve memory operand for target. */
31827 /* Reserve memory operand for target. */
31841 }
31846 {
31851 {
31854 }
31855 else
31858 }
31859 else
31860 {
31867 }
31870 {
31879 {
31881 {
31887 else
31890 }
31891 }
31892 else
31893 {
31895 {
31896 /* This must be the memory operand. */
31901 }
31902 else
31903 {
31904 /* This must be register. */
31911 }
31912 }
31916 }
31919 {
31934 }
31940 }
31942 /* Return the integer constant in ARG. Constrain it to be in the range
31943 of the subparts of VEC_TYPE; issue an error if not. */
31945 static int
31947 {
31952 {
31955 }
31958 }
31960 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31961 ix86_expand_vector_init. We DO have language-level syntax for this, in
31962 the form of (type){ init-list }. Except that since we can't place emms
31963 instructions from inside the compiler, we can't allow the use of MMX
31964 registers unless the user explicitly asks for it. So we do *not* define
31965 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31966 we have builtins invoked by mmintrin.h that gives us license to emit
31967 these sorts of instructions. */
31969 static rtx
31971 {
31981 {
31984 }
31991 }
31993 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31994 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31995 had a language-level syntax for referencing vector elements. */
31997 static rtx
31999 {
32003 rtx op0;
32023 }
32025 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
32026 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
32027 a language-level syntax for referencing vector elements. */
32029 static rtx
32031 {
32055 /* OP0 is the source of these builtin functions and shouldn't be
32056 modified. Create a copy, use it and return it as target. */
32062 }
32064 /* Expand an expression EXP that calls a built-in function,
32065 with result going to TARGET if that's convenient
32066 (and in mode MODE if that's convenient).
32067 SUBTARGET may be used as the target for computing one of EXP's operands.
32068 IGNORE is nonzero if the value is to be ignored. */
32070 static rtx
32073 {
32083 /* For CPU builtins that can be folded, fold first and expand the fold. */
32085 {
32087 {
32088 /* Make it call __cpu_indicator_init in libgcc. */
32094 }
32097 {
32102 }
32103 }
32105 /* Determine whether the builtin function is available under the current ISA.
32106 Originally the builtin was not created if it wasn't applicable to the
32107 current ISA based on the command line switches. With function specific
32108 options, we need to check in the context of the function making the call
32109 whether it is supported. */
32112 {
32118 else
32119 {
32123 }
32125 }
32128 {
32132 ? CODE_FOR_mmx_maskmovq
32134 /* Note the arg order is different from the operand order. */
32235 {
32236 REAL_VALUE_TYPE inf;
32237 rtx tmp;
32249 }
32259 {
32265 insn = (TARGET_64BIT
32269 }
32271 {
32272 insn = (TARGET_64BIT
32276 }
32277 else
32278 {
32281 insn = (TARGET_64BIT
32289 {
32292 }
32294 }
32297 {
32298 /* mode is VOIDmode if __builtin_rd* has been called
32299 without lhs. */
32303 }
32306 {
32311 }
32321 {
32336 }
32342 {
32345 }
32365 {
32368 }
32374 {
32378 {
32399 }
32404 }
32405 else
32406 {
32408 {
32420 }
32422 }
32452 ? CODE_FOR_tbm_bextri_si
32455 {
32458 }
32459 else
32460 {
32469 }
32485 rdrand_step:
32492 {
32495 }
32501 /* Emit SImode conditional move. */
32503 {
32506 }
32509 else
32516 const0_rtx);
32535 rdseed_step:
32542 {
32545 }
32551 const0_rtx);
32569 addcarryx:
32577 /* Generate CF from input operand. */
32582 /* Gen ADCX instruction to compute X+Y+CF. */
32597 /* Store the result. */
32600 {
32603 }
32606 /* Return current CF value. */
32675 gather_gen:
32686 /* Note the arg order is different from the operand order. */
32695 else
32700 {
32706 }
32709 {
32714 else
32724 }
32726 /* Force memory operand only with base register here. But we
32727 don't want to do it on memory operand for other builtin
32728 functions. */
32740 {
32743 }
32745 /* Optimize. If mask is known to have all high bits set,
32746 replace op0 with pc_rtx to signal that the instruction
32747 overwrites the whole destination and doesn't use its
32748 previous contents. */
32750 {
32752 {
32755 {
32759 negative++;
32762 negative++;
32763 }
32766 }
32768 {
32769 /* Recognize also when mask is like:
32770 __v2df src = _mm_setzero_pd ();
32771 __v2df mask = _mm_cmpeq_pd (src, src);
32772 or
32773 __v8sf src = _mm256_setzero_ps ();
32774 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32775 as that is a cheaper way to load all ones into
32776 a register than having to load a constant from
32777 memory. */
32780 {
32785 {
32792 /* FALLTHRU */
32802 }
32803 }
32804 }
32805 }
32814 {
32821 else
32823 }
32824 else
32835 {
32838 }
32844 }
32857 {
32861 /* Emit a normal call if SSE isn't available. */
32865 }
32890 }
32892 /* Returns a function decl for a vectorized version of the builtin function
32893 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32894 if it is not available. */
32896 static tree
32898 tree type_in)
32899 {
32915 {
32918 {
32923 }
32928 {
32933 }
32939 /* The round insn does not trap on denormals. */
32944 {
32949 }
32955 /* The round insn does not trap on denormals. */
32960 {
32965 }
32971 /* The round insn does not trap on denormals. */
32976 {
32981 }
32987 /* The round insn does not trap on denormals. */
32992 {
32997 }
33004 {
33009 }
33016 {
33021 }
33027 /* The round insn does not trap on denormals. */
33032 {
33037 }
33043 /* The round insn does not trap on denormals. */
33048 {
33053 }
33058 {
33063 }
33068 {
33073 }
33077 /* The round insn does not trap on denormals. */
33082 {
33087 }
33091 /* The round insn does not trap on denormals. */
33096 {
33101 }
33105 /* The round insn does not trap on denormals. */
33110 {
33115 }
33119 /* The round insn does not trap on denormals. */
33124 {
33129 }
33133 /* The round insn does not trap on denormals. */
33138 {
33143 }
33147 /* The round insn does not trap on denormals. */
33152 {
33157 }
33161 /* The round insn does not trap on denormals. */
33166 {
33171 }
33175 /* The round insn does not trap on denormals. */
33180 {
33185 }
33189 /* The round insn does not trap on denormals. */
33194 {
33199 }
33203 /* The round insn does not trap on denormals. */
33208 {
33213 }
33218 {
33223 }
33228 {
33233 }
33238 }
33240 /* Dispatch to a handler for a vectorization library. */
33243 type_in);
33246 }
33248 /* Handler for an SVML-style interface to
33249 a library with vectorized intrinsics. */
33251 static tree
33253 {
33261 /* The SVML is suitable for unsafe math only. */
33274 {
33321 }
33330 {
33333 }
33334 else
33337 /* Convert to uppercase. */
33342 args;
33344 arity++;
33348 else
33351 /* Build a function declaration for the vectorized function. */
33360 }
33362 /* Handler for an ACML-style interface to
33363 a library with vectorized intrinsics. */
33365 static tree
33367 {
33375 /* The ACML is 64bits only and suitable for unsafe math only as
33376 it does not correctly support parts of IEEE with the required
33377 precision such as denormals. */
33391 {
33421 }
33428 args;
33430 arity++;
33434 else
33437 /* Build a function declaration for the vectorized function. */
33446 }
33448 /* Returns a decl of a function that implements gather load with
33449 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
33450 Return NULL_TREE if it is not available. */
33452 static tree
33455 {
33471 /* v*gather* insn sign extends index to pointer mode. */
33483 {
33510 }
33513 }
33515 /* Returns a code for a target-specific builtin that implements
33516 reciprocal of the function, or NULL_TREE if not available. */
33518 static tree
33521 {
33528 /* Machine dependent builtins. */
33530 {
33531 /* Vectorized version of sqrt to rsqrt conversion. */
33540 }
33541 else
33542 /* Normal builtins. */
33544 {
33545 /* Sqrt to rsqrt conversion. */
33551 }
33552 }
33553 \f
33554 /* Helper for avx_vpermilps256_operand et al. This is also used by
33555 the expansion functions to turn the parallel back into a mask.
33556 The return value is 0 for no match and the imm8+1 for a match. */
33558 int
33560 {
33568 /* Validate that all of the elements are constants, and not totally
33569 out of range. Copy the data into an integral array to make the
33570 subsequent checks easier. */
33572 {
33582 }
33585 {
33587 /* In the 256-bit DFmode case, we can only move elements within
33588 a 128-bit lane. */
33590 {
33594 }
33596 {
33600 }
33604 /* In the 256-bit SFmode case, we have full freedom of movement
33605 within the low 128-bit lane, but the high 128-bit lane must
33606 mirror the exact same pattern. */
33611 /* FALLTHRU */
33615 /* In the 128-bit case, we've full freedom in the placement of
33616 the elements from the source operand. */
33623 }
33625 /* Make sure success has a non-zero value by adding one. */
33627 }
33629 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33630 the expansion functions to turn the parallel back into a mask.
33631 The return value is 0 for no match and the imm8+1 for a match. */
33633 int
33635 {
33643 /* Validate that all of the elements are constants, and not totally
33644 out of range. Copy the data into an integral array to make the
33645 subsequent checks easier. */
33647 {
33657 }
33659 /* Validate that the halves of the permute are halves. */
33667 /* Reconstruct the mask. */
33669 {
33675 }
33677 /* Make sure success has a non-zero value by adding one. */
33679 }
33680 \f
33681 /* Store OPERAND to the memory after reload is completed. This means
33682 that we can't easily use assign_stack_local. */
33683 rtx
33685 {
33686 rtx result;
33690 {
33693 stack_pointer_rtx,
33696 }
33698 {
33700 {
33704 /* FALLTHRU */
33710 stack_pointer_rtx)),
33711 operand));
33715 }
33717 }
33718 else
33719 {
33721 {
33723 {
33730 stack_pointer_rtx)),
33736 stack_pointer_rtx)),
33738 }
33741 /* Store HImodes as SImodes. */
33743 /* FALLTHRU */
33749 stack_pointer_rtx)),
33750 operand));
33754 }
33756 }
33758 }
33760 /* Free operand from the memory. */
33761 void
33763 {
33765 {
33770 else
33772 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33773 to pop or add instruction if registers are available. */
33777 }
33778 }
33780 /* Return a register priority for hard reg REGNO. */
33781 static int
33783 {
33784 /* ebp and r13 as the base always wants a displacement, r12 as the
33785 base always wants an index. So discourage their usage in an
33786 address. */
33791 /* New x86-64 int registers result in bigger code size. Discourage
33792 them. */
33795 /* New x86-64 SSE registers result in bigger code size. Discourage
33796 them. */
33799 /* Usage of AX register results in smaller code. Prefer it. */
33803 }
33805 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33807 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33808 QImode must go into class Q_REGS.
33809 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33810 movdf to do mem-to-mem moves through integer regs. */
33812 static reg_class_t
33814 {
33817 /* We're only allowed to return a subclass of CLASS. Many of the
33818 following checks fail for NO_REGS, so eliminate that early. */
33822 /* All classes can load zeros. */
33826 /* Force constants into memory if we are loading a (nonzero) constant into
33827 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
33828 instructions to load from a constant. */
33835 /* Prefer SSE regs only, if we can use them for math. */
33839 /* Floating-point constants need more complex checks. */
33841 {
33842 /* General regs can load everything. */
33846 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33847 zero above. We only want to wind up preferring 80387 registers if
33848 we plan on doing computation with them. */
33851 {
33852 /* Limit class to non-sse. */
33861 }
33864 }
33866 /* Generally when we see PLUS here, it's the function invariant
33867 (plus soft-fp const_int). Which can only be computed into general
33868 regs. */
33872 /* QImode constants are easy to load, but non-constant QImode data
33873 must go into Q_REGS. */
33875 {
33881 }
33884 }
33886 /* Discourage putting floating-point values in SSE registers unless
33887 SSE math is being used, and likewise for the 387 registers. */
33888 static reg_class_t
33890 {
33893 /* Restrict the output reload class to the register bank that we are doing
33894 math on. If we would like not to return a subset of CLASS, reject this
33895 alternative: if reload cannot do this, it will still use its choice. */
33901 {
33906 else
33908 }
33911 }
33913 static reg_class_t
33916 {
33917 /* Double-word spills from general registers to non-offsettable memory
33918 references (zero-extended addresses) require special handling. */
33924 {
33926 ? CODE_FOR_reload_noff_load
33928 /* Add the cost of moving address to a temporary. */
33932 }
33934 /* QImode spills from non-QI registers require
33935 intermediate register on 32bit targets. */
33941 {
33946 else
33952 /* Return Q_REGS if the operand is in memory. */
33955 }
33957 /* This condition handles corner case where an expression involving
33958 pointers gets vectorized. We're trying to use the address of a
33959 stack slot as a vector initializer.
33961 (set (reg:V2DI 74 [ vect_cst_.2 ])
33962 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33964 Eventually frame gets turned into sp+offset like this:
33966 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33967 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33968 (const_int 392 [0x188]))))
33970 That later gets turned into:
33972 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33973 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33974 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33976 We'll have the following reload recorded:
33978 Reload 0: reload_in (DI) =
33979 (plus:DI (reg/f:DI 7 sp)
33980 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33981 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33982 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33983 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33984 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33985 reload_reg_rtx: (reg:V2DI 22 xmm1)
33987 Which isn't going to work since SSE instructions can't handle scalar
33988 additions. Returning GENERAL_REGS forces the addition into integer
33989 register and reload can handle subsequent reloads without problems. */
33997 }
33999 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
34001 static bool
34003 {
34005 {
34020 }
34023 }
34025 /* If we are copying between general and FP registers, we need a memory
34026 location. The same is true for SSE and MMX registers.
34028 To optimize register_move_cost performance, allow inline variant.
34030 The macro can't work reliably when one of the CLASSES is class containing
34031 registers from multiple units (SSE, MMX, integer). We avoid this by never
34032 combining those units in single alternative in the machine description.
34033 Ensure that this constraint holds to avoid unexpected surprises.
34035 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
34036 enforce these sanity checks. */
34041 {
34050 {
34053 }
34058 /* ??? This is a lie. We do have moves between mmx/general, and for
34059 mmx/sse2. But by saying we need secondary memory we discourage the
34060 register allocator from using the mmx registers unless needed. */
34065 {
34066 /* SSE1 doesn't have any direct moves from other classes. */
34070 /* If the target says that inter-unit moves are more expensive
34071 than moving through memory, then don't generate them. */
34076 /* Between SSE and general, we have moves no larger than word size. */
34079 }
34082 }
34084 bool
34087 {
34089 }
34091 /* Implement the TARGET_CLASS_MAX_NREGS hook.
34093 On the 80386, this is the size of MODE in words,
34094 except in the FP regs, where a single reg is always enough. */
34096 static unsigned char
34098 {
34100 {
34105 else
34107 }
34108 else
34109 {
34112 else
34114 }
34115 }
34117 /* Return true if the registers in CLASS cannot represent the change from
34118 modes FROM to TO. */
34120 bool
34123 {
34127 /* x87 registers can't do subreg at all, as all values are reformatted
34128 to extended precision. */
34133 {
34134 /* Vector registers do not support QI or HImode loads. If we don't
34135 disallow a change to these modes, reload will assume it's ok to
34136 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
34137 the vec_dupv4hi pattern. */
34141 /* Vector registers do not support subreg with nonzero offsets, which
34142 are otherwise valid for integer registers. Since we can't see
34143 whether we have a nonzero offset from here, prohibit all
34144 nonparadoxical subregs changing size. */
34147 }
34150 }
34152 /* Return the cost of moving data of mode M between a
34153 register and memory. A value of 2 is the default; this cost is
34154 relative to those in `REGISTER_MOVE_COST'.
34156 This function is used extensively by register_move_cost that is used to
34157 build tables at startup. Make it inline in this case.
34158 When IN is 2, return maximum of in and out move cost.
34160 If moving between registers and memory is more expensive than
34161 between two registers, you should define this macro to express the
34162 relative cost.
34164 Model also increased moving costs of QImode registers in non
34165 Q_REGS classes.
34166 */
34170 {
34173 {
34176 {
34188 }
34192 }
34194 {
34197 {
34209 }
34213 }
34215 {
34218 {
34227 }
34231 }
34233 {
34236 {
34242 else
34247 }
34248 else
34249 {
34254 else
34256 }
34263 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
34270 else
34274 }
34275 }
34277 static int
34280 {
34282 }
34285 /* Return the cost of moving data from a register in class CLASS1 to
34286 one in class CLASS2.
34288 It is not required that the cost always equal 2 when FROM is the same as TO;
34289 on some machines it is expensive to move between registers if they are not
34290 general registers. */
34292 static int
34294 reg_class_t class2_i)
34295 {
34299 /* In case we require secondary memory, compute cost of the store followed
34300 by load. In order to avoid bad register allocation choices, we need
34301 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
34304 {
34310 /* In case of copying from general_purpose_register we may emit multiple
34311 stores followed by single load causing memory size mismatch stall.
34312 Count this as arbitrarily high cost of 20. */
34317 /* In the case of FP/MMX moves, the registers actually overlap, and we
34318 have to switch modes in order to treat them differently. */
34324 }
34326 /* Moves between SSE/MMX and integer unit are expensive. */
34330 /* ??? By keeping returned value relatively high, we limit the number
34331 of moves between integer and MMX/SSE registers for all targets.
34332 Additionally, high value prevents problem with x86_modes_tieable_p(),
34333 where integer modes in MMX/SSE registers are not tieable
34334 because of missing QImode and HImode moves to, from or between
34335 MMX/SSE registers. */
34345 }
34347 /* Return TRUE if hard register REGNO can hold a value of machine-mode
34348 MODE. */
34350 bool
34352 {
34353 /* Flags and only flags can only hold CCmode values. */
34365 {
34366 /* We implement the move patterns for all vector modes into and
34367 out of SSE registers, even when no operation instructions
34368 are available. */
34370 /* For AVX-512 we allow, regardless of regno:
34371 - XI mode
34372 - any of 512-bit wide vector mode
34373 - any scalar mode. */
34380 /* xmm16-xmm31 are only available for AVX-512. */
34384 /* OImode move is available only when AVX is enabled. */
34391 }
34393 {
34394 /* We implement the move patterns for 3DNOW modes even in MMX mode,
34395 so if the register is available at all, then we can move data of
34396 the given mode into or out of it. */
34399 }
34402 {
34403 /* Take care for QImode values - they can be in non-QI regs,
34404 but then they do cause partial register stalls. */
34409 /* LRA checks if the hard register is OK for the given mode.
34410 QImode values can live in non-QI regs, so we allow all
34411 registers here. */
34415 }
34416 /* We handle both integer and floats in the general purpose registers. */
34423 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
34424 on to use that value in smaller contexts, this can easily force a
34425 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
34426 supporting DImode, allow it. */
34431 }
34433 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
34434 tieable integer mode. */
34436 static bool
34438 {
34440 {
34453 }
34454 }
34456 /* Return true if MODE1 is accessible in a register that can hold MODE2
34457 without copying. That is, all register classes that can hold MODE2
34458 can also hold MODE1. */
34460 bool
34462 {
34470 /* MODE2 being XFmode implies fp stack or general regs, which means we
34471 can tie any smaller floating point modes to it. Note that we do not
34472 tie this with TFmode. */
34476 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
34477 that we can tie it with SFmode. */
34481 /* If MODE2 is only appropriate for an SSE register, then tie with
34482 any other mode acceptable to SSE registers. */
34492 /* If MODE2 is appropriate for an MMX register, then tie
34493 with any other mode acceptable to MMX registers. */
34500 }
34502 /* Return the cost of moving between two registers of mode MODE. */
34504 static int
34506 {
34510 {
34542 }
34544 /* Return the cost of moving between two registers of mode MODE,
34545 assuming that the move will be in pieces of at most UNITS bytes. */
34547 }
34549 /* Compute a (partial) cost for rtx X. Return true if the complete
34550 cost has been computed, and false if subexpressions should be
34551 scanned. In either case, *TOTAL contains the cost result. */
34553 static bool
34556 {
34563 {
34567 {
34570 }
34582 && (!TARGET_64BIT
34587 else
34593 {
34596 }
34598 {
34608 }
34610 {
34613 {
34622 }
34623 }
34624 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34625 it'll probably end up. Add a penalty for size. */
34632 /* The zero extensions is often completely free on x86_64, so make
34633 it as cheap as possible. */
34639 else
34651 {
34654 {
34657 }
34660 {
34663 }
34664 }
34665 /* FALLTHRU */
34672 {
34673 /* ??? Should be SSE vector operation cost. */
34674 /* At least for published AMD latencies, this really is the same
34675 as the latency for a simple fpu operation like fabs. */
34676 /* V*QImode is emulated with 1-11 insns. */
34678 {
34681 {
34682 /* For XOP we use vpshab, which requires a broadcast of the
34683 value to the variable shift insn. For constants this
34684 means a V16Q const in mem; even when we can perform the
34685 shift with one insn set the cost to prefer paddb. */
34687 {
34692 }
34694 }
34698 }
34699 else
34701 }
34703 {
34705 {
34708 else
34710 }
34711 else
34712 {
34715 else
34717 }
34718 }
34719 else
34720 {
34725 {
34726 /* Return the cost after shift-and truncation. */
34729 }
34730 else
34732 }
34736 {
34737 rtx sub;
34742 /* ??? SSE scalar/vector cost should be used here. */
34743 /* ??? Bald assumption that fma has the same cost as fmul. */
34747 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34758 }
34762 {
34763 /* ??? SSE scalar cost should be used here. */
34766 }
34768 {
34771 }
34773 {
34774 /* ??? SSE vector cost should be used here. */
34777 }
34779 {
34780 /* V*QImode is emulated with 7-13 insns. */
34782 {
34789 }
34790 /* V*DImode is emulated with 5-8 insns. */
34792 {
34795 else
34797 }
34798 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34799 insns, including two PMULUDQ. */
34802 else
34805 }
34806 else
34807 {
34812 {
34815 nbits++;
34816 }
34817 else
34818 /* This is arbitrary. */
34821 /* Compute costs correctly for widening multiplication. */
34825 {
34832 {
34836 else
34838 }
34842 }
34850 }
34857 /* ??? SSE cost should be used here. */
34862 /* ??? SSE vector cost should be used here. */
34864 else
34871 {
34876 {
34879 {
34887 }
34888 }
34891 {
34894 {
34900 }
34901 }
34903 {
34911 }
34912 }
34913 /* FALLTHRU */
34917 {
34918 /* ??? SSE cost should be used here. */
34921 }
34923 {
34926 }
34928 {
34929 /* ??? SSE vector cost should be used here. */
34932 }
34933 /* FALLTHRU */
34940 {
34947 }
34948 /* FALLTHRU */
34952 {
34953 /* ??? SSE cost should be used here. */
34956 }
34958 {
34961 }
34963 {
34964 /* ??? SSE vector cost should be used here. */
34967 }
34968 /* FALLTHRU */
34972 {
34973 /* ??? Should be SSE vector operation cost. */
34974 /* At least for published AMD latencies, this really is the same
34975 as the latency for a simple fpu operation like fabs. */
34977 }
34980 else
34989 {
34990 /* This kind of construct is implemented using test[bwl].
34991 Treat it as if we had an AND. */
34996 }
35006 /* ??? SSE cost should be used here. */
35011 /* ??? SSE vector cost should be used here. */
35017 /* ??? SSE cost should be used here. */
35022 /* ??? SSE vector cost should be used here. */
35035 /* ??? Assume all of these vector manipulation patterns are
35036 recognizable. In which case they all pretty much have the
35037 same cost. */
35043 }
35044 }
35046 #if TARGET_MACHO
35050 /* Given a symbol name and its associated stub, write out the
35051 definition of the stub. */
35053 void
35055 {
35060 /* For 64-bit we shouldn't get here. */
35063 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
35080 else
35087 {
35089 }
35091 {
35092 /* PIC stub. */
35093 /* 25-byte PIC stub using "CALL get_pc_thunk". */
35099 }
35100 else
35103 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
35104 it needs no stub-binding-helper. */
35111 {
35114 }
35115 else
35120 /* N.B. Keep the correspondence of these
35121 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
35122 old-pic/new-pic/non-pic stubs; altering this will break
35123 compatibility with existing dylibs. */
35125 {
35126 /* 25-byte PIC stub using "CALL get_pc_thunk". */
35128 }
35129 else
35130 /* 16-byte -mdynamic-no-pic stub. */
35136 }
35139 /* Order the registers for register allocator. */
35141 void
35143 {
35147 /* First allocate the local general purpose registers. */
35152 /* Global general purpose registers. */
35157 /* x87 registers come first in case we are doing FP math
35158 using them. */
35163 /* SSE registers. */
35169 /* Extended REX SSE registers. */
35173 /* Mask register. */
35177 /* x87 registers. */
35185 /* Initialize the rest of array as we do not allocate some registers
35186 at all. */
35189 }
35191 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
35192 in struct attribute_spec handler. */
35193 static tree
35195 tree args,
35198 {
35203 {
35205 name);
35208 }
35210 {
35212 name);
35215 }
35217 {
35218 tree cst;
35222 {
35225 name);
35227 }
35230 {
35233 name);
35235 }
35238 }
35241 }
35243 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
35244 struct attribute_spec.handler. */
35245 static tree
35247 tree args ATTRIBUTE_UNUSED,
35249 {
35254 {
35256 name);
35259 }
35261 /* Can combine regparm with all attributes but fastcall. */
35263 {
35265 {
35267 }
35270 }
35272 {
35274 {
35276 }
35279 }
35282 }
35284 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
35285 struct attribute_spec.handler. */
35286 static tree
35288 tree args ATTRIBUTE_UNUSED,
35290 {
35293 {
35296 }
35297 else
35301 {
35303 name);
35305 }
35311 {
35313 name);
35315 }
35318 }
35320 static tree
35322 tree args ATTRIBUTE_UNUSED,
35324 {
35326 {
35328 name);
35330 }
35332 }
35334 static bool
35336 {
35340 }
35342 /* Returns an expression indicating where the this parameter is
35343 located on entry to the FUNCTION. */
35345 static rtx
35347 {
35353 {
35358 else
35361 }
35366 {
35373 {
35378 }
35379 else
35380 {
35383 {
35389 }
35390 }
35392 }
35396 }
35398 /* Determine whether x86_output_mi_thunk can succeed. */
35400 static bool
35402 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
35404 {
35405 /* 64-bit can handle anything. */
35409 /* For 32-bit, everything's fine if we have one free register. */
35413 /* Need a free register for vcall_offset. */
35417 /* Need a free register for GOT references. */
35421 /* Otherwise ok. */
35423 }
35425 /* Output the assembler code for a thunk function. THUNK_DECL is the
35426 declaration for the thunk function itself, FUNCTION is the decl for
35427 the target function. DELTA is an immediate constant offset to be
35428 added to THIS. If VCALL_OFFSET is nonzero, the word at
35429 *(*this + vcall_offset) should be added to THIS. */
35431 static void
35435 {
35442 else
35443 {
35449 else
35451 }
35455 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
35456 pull it in now and let DELTA benefit. */
35460 {
35461 /* Put the this parameter into %eax. */
35464 }
35465 else
35468 /* Adjust the this parameter by a fixed constant. */
35470 {
35475 {
35477 {
35481 }
35482 }
35485 }
35487 /* Adjust the this parameter by a value stored in the vtable. */
35489 {
35499 /* Adjust the this parameter. */
35503 {
35507 }
35514 vcall_mem));
35515 else
35517 }
35519 /* If necessary, drop THIS back to its stack slot. */
35525 {
35528 ;
35529 else
35530 {
35534 }
35535 }
35536 else
35537 {
35539 ;
35540 #if TARGET_MACHO
35542 {
35545 }
35547 else
35548 {
35555 }
35556 }
35558 /* Our sibling call patterns do not allow memories, because we have no
35559 predicate that can distinguish between frame and non-frame memory.
35560 For our purposes here, we can get away with (ab)using a jump pattern,
35561 because we're going to do no optimization. */
35564 else
35565 {
35571 {
35577 }
35583 }
35586 /* Emit just enough of rest_of_compilation to get the insns emitted.
35587 Note that use_thunk calls assemble_start_function et al. */
35593 }
35595 static void
35597 {
35599 #if TARGET_MACHO
35601 #endif
35608 }
35610 int
35612 {
35624 }
35626 /* Output assembler code to FILE to increment profiler label # LABELNO
35627 for profiling a function entry. */
35628 void
35630 {
35635 {
35636 #ifndef NO_PROFILE_COUNTERS
35638 #endif
35642 else
35644 }
35646 {
35647 #ifndef NO_PROFILE_COUNTERS
35650 #endif
35652 }
35653 else
35654 {
35655 #ifndef NO_PROFILE_COUNTERS
35658 #endif
35660 }
35661 }
35663 /* We don't have exact information about the insn sizes, but we may assume
35664 quite safely that we are informed about all 1 byte insns and memory
35665 address sizes. This is enough to eliminate unnecessary padding in
35666 99% of cases. */
35668 static int
35670 {
35676 /* Discard alignments we've emit and jump instructions. */
35681 /* Important case - calls are always 5 bytes.
35682 It is common to have many calls in the row. */
35691 /* For normal instructions we rely on get_attr_length being exact,
35692 with a few exceptions. */
35694 {
35698 {
35708 /* Otherwise trust get_attr_length. */
35710 }
35715 }
35718 else
35720 }
35722 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35724 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35725 window. */
35727 static void
35729 {
35734 /* Look for all minimal intervals of instructions containing 4 jumps.
35735 The intervals are bounded by START and INSN. NBYTES is the total
35736 size of instructions in the interval including INSN and not including
35737 START. When the NBYTES is smaller than 16 bytes, it is possible
35738 that the end of START and INSN ends up in the same 16byte page.
35740 The smallest offset in the page INSN can start is the case where START
35741 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35742 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35743 */
35745 {
35749 {
35755 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35756 already in the current 16 byte page, because otherwise
35757 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35758 bytes to reach 16 byte boundary. */
35766 {
35768 {
35772 else
35775 }
35776 }
35778 }
35786 njumps++;
35787 else
35791 {
35795 else
35798 }
35805 {
35812 }
35813 }
35814 }
35815 #endif
35817 /* AMD Athlon works faster
35818 when RET is not destination of conditional jump or directly preceded
35819 by other jump instruction. We avoid the penalty by inserting NOP just
35820 before the RET instructions in such cases. */
35821 static void
35823 {
35824 edge e;
35825 edge_iterator ei;
35828 {
35831 rtx prev;
35841 {
35842 edge e;
35843 edge_iterator ei;
35848 {
35851 }
35852 }
35854 {
35860 /* Empty functions get branch mispredict even when
35861 the jump destination is not visible to us. */
35864 }
35866 {
35869 }
35870 }
35871 }
35873 /* Count the minimum number of instructions in BB. Return 4 if the
35874 number of instructions >= 4. */
35876 static int
35878 {
35879 rtx insn;
35882 /* Count number of instructions in this block. Return 4 if the number
35883 of instructions >= 4. */
35885 {
35886 /* Only happen in exit blocks. */
35894 {
35895 insn_count++;
35898 }
35899 }
35902 }
35905 /* Count the minimum number of instructions in code path in BB.
35906 Return 4 if the number of instructions >= 4. */
35908 static int
35910 {
35911 edge e;
35912 edge_iterator ei;
35915 /* Only bother counting instructions along paths with no
35916 more than 2 basic blocks between entry and exit. Given
35917 that BB has an edge to exit, determine if a predecessor
35918 of BB has an edge from entry. If so, compute the number
35919 of instructions in the predecessor block. If there
35920 happen to be multiple such blocks, compute the minimum. */
35923 {
35924 edge prev_e;
35925 edge_iterator prev_ei;
35928 {
35931 }
35933 {
35935 {
35940 }
35941 }
35942 }
35948 }
35950 /* Pad short function to 4 instructions. */
35952 static void
35954 {
35955 edge e;
35956 edge_iterator ei;
35959 {
35962 {
35965 /* Pad short function. */
35967 {
35970 /* Find epilogue. */
35979 /* Two NOPs count as one instruction. */
35982 }
35983 }
35984 }
35985 }
35987 /* Fix up a Windows system unwinder issue. If an EH region falls through into
35988 the epilogue, the Windows system unwinder will apply epilogue logic and
35989 produce incorrect offsets. This can be avoided by adding a nop between
35990 the last insn that can throw and the first insn of the epilogue. */
35992 static void
35994 {
35995 edge e;
35996 edge_iterator ei;
35999 {
36002 /* Find the beginning of the epilogue. */
36009 /* We only care about preceding insns that can throw. */
36014 /* Do not separate calls from their debug information. */
36020 else
36024 }
36025 }
36027 /* Implement machine specific optimizations. We implement padding of returns
36028 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
36029 static void
36031 {
36032 /* We are freeing block_for_insn in the toplev to keep compatibility
36033 with old MDEP_REORGS that are not CFG based. Recompute it now. */
36040 {
36045 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
36048 #endif
36049 }
36050 }
36052 /* Return nonzero when QImode register that must be represented via REX prefix
36053 is used. */
36054 bool
36056 {
36064 }
36066 /* Return nonzero when P points to register encoded via REX prefix.
36067 Called via for_each_rtx. */
36068 static int
36070 {
36076 }
36078 /* Return true when INSN mentions register that must be encoded using REX
36079 prefix. */
36080 bool
36082 {
36085 }
36087 /* If profitable, negate (without causing overflow) integer constant
36088 of mode MODE at location LOC. Return true in this case. */
36089 bool
36091 {
36092 HOST_WIDE_INT val;
36098 {
36100 /* DImode x86_64 constants must fit in 32 bits. */
36113 }
36115 /* Avoid overflows. */
36121 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
36122 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
36125 {
36128 }
36131 }
36133 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
36134 optabs would emit if we didn't have TFmode patterns. */
36136 void
36138 {
36172 }
36173 \f
36174 /* AVX512F does support 64-byte integer vector operations,
36175 thus the longest vector we are faced with is V64QImode. */
36176 #define MAX_VECT_LEN 64
36178 struct expand_vec_perm_d
36179 {
36186 };
36192 /* Get a vector mode of the same size as the original but with elements
36193 twice as wide. This is only guaranteed to apply to integral vectors. */
36197 {
36198 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
36203 }
36205 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36206 with all elements equal to VAR. Return true if successful. */
36208 static bool
36211 {
36215 {
36220 /* FALLTHRU */
36230 {
36233 /* First attempt to recognize VAL as-is. */
36237 {
36238 rtx seq;
36239 /* If that fails, force VAL into a register. */
36250 }
36251 }
36258 {
36259 rtx x;
36266 }
36276 {
36280 permute:
36288 /* Extend to SImode using a paradoxical SUBREG. */
36292 /* Insert the SImode value as low element of a V4SImode vector. */
36300 }
36308 widen:
36309 /* Replicate the value once into the next wider mode and recurse. */
36310 {
36312 rtx x;
36328 }
36332 {
36341 }
36346 }
36347 }
36349 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36350 whose ONE_VAR element is VAR, and other elements are zero. Return true
36351 if successful. */
36353 static bool
36356 {
36358 rtx new_target;
36363 {
36365 /* For SSE4.1, we normally use vector set. But if the second
36366 element is zero and inter-unit moves are OK, we use movq
36367 instead. */
36369 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
36391 /* Use ix86_expand_vector_set in 64bit mode only. */
36396 }
36399 {
36404 }
36407 {
36412 /* FALLTHRU */
36427 else
36434 {
36435 /* We need to shuffle the value to the correct position, so
36436 create a new pseudo to store the intermediate result. */
36438 /* With SSE2, we can use the integer shuffle insns. */
36440 {
36442 const1_rtx,
36449 }
36451 /* Otherwise convert the intermediate result to V4SFmode and
36452 use the SSE1 shuffle instructions. */
36454 {
36457 }
36458 else
36462 const1_rtx,
36471 }
36486 widen:
36490 /* Zero extend the variable element to SImode and recurse. */
36503 }
36504 }
36506 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36507 consisting of the values in VALS. It is known that all elements
36508 except ONE_VAR are constants. Return true if successful. */
36510 static bool
36513 {
36523 {
36528 /* For the two element vectors, it's just as easy to use
36529 the general case. */
36533 /* Use ix86_expand_vector_set in 64bit mode only. */
36555 widen:
36556 /* There's no way to set one QImode entry easily. Combine
36557 the variable value with its adjacent constant value, and
36558 promote to an HImode set. */
36561 {
36566 }
36567 else
36568 {
36571 }
36585 }
36590 }
36592 /* A subroutine of ix86_expand_vector_init_general. Use vector
36593 concatenate to handle the most general case: all values variable,
36594 and none identical. */
36596 static void
36599 {
36602 rtvec v;
36606 {
36609 {
36642 }
36655 {
36670 }
36675 {
36686 }
36689 half:
36690 /* FIXME: We process inputs backward to help RA. PR 36222. */
36694 {
36699 }
36703 {
36706 {
36710 }
36713 }
36714 else
36720 }
36721 }
36723 /* A subroutine of ix86_expand_vector_init_general. Use vector
36724 interleave to handle the most general case: all values variable,
36725 and none identical. */
36727 static void
36730 {
36739 {
36760 }
36763 {
36764 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36768 /* Insert the SImode value as low element of V4SImode vector. */
36772 op0),
36774 const1_rtx);
36777 /* Cast the V4SImode vector back to a vector in orignal mode. */
36781 /* Load even elements into the second position. */
36785 const1_rtx));
36787 /* Cast vector to FIRST_IMODE vector. */
36790 }
36792 /* Interleave low FIRST_IMODE vectors. */
36794 {
36798 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36801 }
36803 /* Interleave low SECOND_IMODE vectors. */
36805 {
36808 {
36813 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36814 vector. */
36817 }
36820 /* FALLTHRU */
36827 /* Cast the SECOND_IMODE vector back to a vector on original
36828 mode. */
36835 }
36836 }
36838 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36839 all values variable, and none identical. */
36841 static void
36844 {
36850 {
36855 /* FALLTHRU */
36879 half:
36896 /* FALLTHRU */
36902 /* Don't use ix86_expand_vector_init_interleave if we can't
36903 move from GPR to SSE register directly. */
36919 }
36921 {
36933 {
36937 {
36943 else
36944 {
36949 }
36950 }
36953 }
36958 {
36964 }
36966 {
36972 }
36973 else
36975 }
36976 }
36978 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36979 instructions unless MMX_OK is true. */
36981 void
36983 {
36990 rtx x;
36993 {
37003 }
37005 /* Constants are best loaded from the constant pool. */
37007 {
37010 }
37012 /* If all values are identical, broadcast the value. */
37018 /* Values where only one field is non-constant are best loaded from
37019 the pool and overwritten via move later. */
37021 {
37025 one_var))
37030 }
37033 }
37035 void
37037 {
37042 rtx tmp;
37044 = {
37051 };
37053 = {
37060 };
37064 {
37068 {
37073 else
37077 }
37089 else
37095 {
37098 /* For the two element vectors, we implement a VEC_CONCAT with
37099 the extraction of the other element. */
37106 else
37111 }
37120 {
37126 /* tmp = target = A B C D */
37128 /* target = A A B B */
37130 /* target = X A B B */
37132 /* target = A X C D */
37139 /* tmp = target = A B C D */
37141 /* tmp = X B C D */
37143 /* target = A B X D */
37150 /* tmp = target = A B C D */
37152 /* tmp = X B C D */
37154 /* target = A B X D */
37162 }
37170 /* Element 0 handled by vec_merge below. */
37172 {
37175 }
37178 {
37179 /* With SSE2, use integer shuffles to swap element 0 and ELT,
37180 store into element 0, then shuffle them back. */
37197 }
37198 else
37199 {
37200 /* For SSE1, we have to reuse the V4SF code. */
37203 }
37256 half:
37257 /* Compute offset. */
37263 /* Extract the half. */
37267 /* Put val in tmp at elt. */
37270 /* Put it back. */
37276 }
37279 {
37283 }
37284 else
37285 {
37294 }
37295 }
37297 void
37299 {
37303 rtx tmp;
37306 {
37311 /* FALLTHRU */
37324 {
37344 }
37356 {
37358 {
37378 }
37382 }
37383 else
37384 {
37385 /* For SSE1, we have to reuse the V4SF code. */
37389 }
37405 {
37409 else
37413 }
37418 {
37422 else
37426 }
37431 {
37435 else
37439 }
37444 {
37448 else
37452 }
37457 {
37461 else
37465 }
37470 {
37474 else
37478 }
37482 /* ??? Could extract the appropriate HImode element and shift. */
37485 }
37488 {
37492 /* Let the rtl optimizers know about the zero extension performed. */
37494 {
37497 }
37500 }
37501 else
37502 {
37509 }
37510 }
37512 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
37513 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
37514 The upper bits of DEST are undefined, though they shouldn't cause
37515 exceptions (some bits from src or all zeros are ok). */
37517 static void
37519 {
37520 rtx tem;
37522 {
37526 else
37544 else
37551 else
37562 const1_rtx);
37563 else
37570 }
37572 }
37574 /* Expand a vector reduction. FN is the binary pattern to reduce;
37575 DEST is the destination; IN is the input vector. */
37577 void
37579 {
37584 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
37588 {
37591 }
37596 {
37601 else
37605 }
37606 }
37607 \f
37608 /* Target hook for scalar_mode_supported_p. */
37609 static bool
37611 {
37616 else
37618 }
37620 /* Implements target hook vector_mode_supported_p. */
37621 static bool
37623 {
37635 }
37637 /* Target hook for c_mode_for_suffix. */
37638 static enum machine_mode
37640 {
37647 }
37649 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37651 We do this in the new i386 backend to maintain source compatibility
37652 with the old cc0-based compiler. */
37654 static tree
37656 tree inputs ATTRIBUTE_UNUSED,
37657 tree clobbers)
37658 {
37660 clobbers);
37662 clobbers);
37664 }
37666 /* Implements target vector targetm.asm.encode_section_info. */
37668 static void ATTRIBUTE_UNUSED
37670 {
37677 }
37679 /* Worker function for REVERSE_CONDITION. */
37681 enum rtx_code
37683 {
37687 }
37689 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37690 to OPERANDS[0]. */
37694 {
37696 {
37699 {
37703 }
37707 }
37709 {
37713 else
37714 {
37715 /* There is no non-popping store to memory for XFmode.
37716 So if we need one, follow the store with a load. */
37719 else
37721 }
37722 }
37723 else
37725 }
37727 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37728 FP status register is set. */
37730 void
37732 {
37734 rtx temp;
37739 {
37744 }
37745 else
37746 {
37751 }
37755 pc_rtx);
37760 }
37762 /* Output code to perform a log1p XFmode calculation. */
37765 {
37771 rtx test;
37777 XFmode));
37791 }
37793 /* Emit code for round calculation. */
37795 {
37802 rtx insn;
37807 {
37819 }
37822 {
37843 }
37851 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37853 /* scratch = fxam(op1) */
37856 UNSPEC_FXAM)));
37857 /* e1 = fabs(op1) */
37860 /* e2 = e1 + 0.5 */
37865 /* res = floor(e2) */
37867 {
37872 }
37873 else
37877 {
37880 {
37887 UNSPEC_TRUNC_NOOP)));
37888 }
37904 }
37906 /* flags = signbit(a) */
37909 /* if (flags) then res = -res */
37913 pc_rtx);
37924 }
37926 /* Output code to perform a Newton-Rhapson approximation of a single precision
37927 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37930 {
37938 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37942 /* x0 = rcp(b) estimate */
37945 UNSPEC_RCP)));
37946 /* e0 = x0 * b */
37950 /* e0 = x0 * e0 */
37954 /* e1 = x0 + x0 */
37958 /* x1 = e1 - e0 */
37962 /* res = a * x1 */
37965 }
37967 /* Output code to perform a Newton-Rhapson approximation of a
37968 single precision floating point [reciprocal] square root. */
37972 {
37974 REAL_VALUE_TYPE r;
37989 {
37992 }
37994 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37995 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37999 /* x0 = rsqrt(a) estimate */
38002 UNSPEC_RSQRT)));
38004 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
38006 {
38018 }
38020 /* e0 = x0 * a */
38023 /* e1 = e0 * x0 */
38027 /* e2 = e1 - 3. */
38034 /* e3 = -.5 * x0 */
38037 else
38038 /* e3 = -.5 * e0 */
38041 /* ret = e2 * e3 */
38044 }
38046 #ifdef TARGET_SOLARIS
38047 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
38049 static void
38051 tree decl)
38052 {
38053 /* With Binutils 2.15, the "@unwind" marker must be specified on
38054 every occurrence of the ".eh_frame" section, not just the first
38055 one. */
38058 {
38062 }
38064 #ifndef USE_GAS
38066 {
38069 }
38070 #endif
38073 }
38076 /* Return the mangling of TYPE if it is an extended fundamental type. */
38080 {
38088 {
38090 /* __float128 is "g". */
38093 /* "long double" or __float80 is "e". */
38097 }
38098 }
38100 /* For 32-bit code we can save PIC register setup by using
38101 __stack_chk_fail_local hidden function instead of calling
38102 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
38103 register, so it is better to call __stack_chk_fail directly. */
38105 static tree ATTRIBUTE_UNUSED
38107 {
38108 return TARGET_64BIT
38111 }
38113 /* Select a format to encode pointers in exception handling data. CODE
38114 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
38115 true if the symbol may be affected by dynamic relocations.
38117 ??? All x86 object file formats are capable of representing this.
38118 After all, the relocation needed is the same as for the call insn.
38119 Whether or not a particular assembler allows us to enter such, I
38120 guess we'll have to see. */
38121 int
38123 {
38125 {
38132 }
38137 }
38138 \f
38139 /* Expand copysign from SIGN to the positive value ABS_VALUE
38140 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
38141 the sign-bit. */
38142 static void
38144 {
38148 {
38155 else
38160 {
38161 /* We need to generate a scalar mode mask in this case. */
38166 }
38167 }
38168 else
38174 }
38176 /* Expand fabs (OP0) and return a new rtx that holds the result. The
38177 mask for masking out the sign-bit is stored in *SMASK, if that is
38178 non-null. */
38179 static rtx
38181 {
38190 else
38194 {
38195 /* We need to generate a scalar mode mask in this case. */
38200 }
38208 }
38210 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
38211 swapping the operands if SWAP_OPERANDS is true. The expanded
38212 code is a forward jump to a newly created label in case the
38213 comparison is true. The generated label rtx is returned. */
38214 static rtx
38217 {
38221 {
38225 }
38238 }
38240 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
38241 using comparison code CODE. Operands are swapped for the comparison if
38242 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
38243 static rtx
38246 {
38252 {
38256 }
38263 }
38265 /* Generate and return a rtx of mode MODE for 2**n where n is the number
38266 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
38267 static rtx
38269 {
38270 REAL_VALUE_TYPE TWO52r;
38271 rtx TWO52;
38278 }
38280 /* Expand SSE sequence for computing lround from OP1 storing
38281 into OP0. */
38282 void
38284 {
38285 /* C code for the stuff we're doing below:
38286 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
38287 return (long)tmp;
38288 */
38292 rtx adj;
38294 /* load nextafter (0.5, 0.0) */
38299 /* adj = copysign (0.5, op1) */
38303 /* adj = op1 + adj */
38306 /* op0 = (imode)adj */
38308 }
38310 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
38311 into OPERAND0. */
38312 void
38314 {
38315 /* C code for the stuff we're doing below (for do_floor):
38316 xi = (long)op1;
38317 xi -= (double)xi > op1 ? 1 : 0;
38318 return xi;
38319 */
38324 /* reg = (long)op1 */
38328 /* freg = (double)reg */
38332 /* ireg = (freg > op1) ? ireg - 1 : ireg */
38343 }
38345 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
38346 result in OPERAND0. */
38347 void
38349 {
38350 /* C code for the stuff we're doing below:
38351 xa = fabs (operand1);
38352 if (!isless (xa, 2**52))
38353 return operand1;
38354 xa = xa + 2**52 - 2**52;
38355 return copysign (xa, operand1);
38356 */
38363 /* xa = abs (operand1) */
38366 /* if (!isless (xa, TWO52)) goto label; */
38379 }
38381 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
38382 into OPERAND0. */
38383 void
38385 {
38386 /* C code for the stuff we expand below.
38387 double xa = fabs (x), x2;
38388 if (!isless (xa, TWO52))
38389 return x;
38390 xa = xa + TWO52 - TWO52;
38391 x2 = copysign (xa, x);
38392 Compensate. Floor:
38393 if (x2 > x)
38394 x2 -= 1;
38395 Compensate. Ceil:
38396 if (x2 < x)
38397 x2 -= -1;
38398 return x2;
38399 */
38405 /* Temporary for holding the result, initialized to the input
38406 operand to ease control flow. */
38410 /* xa = abs (operand1) */
38413 /* if (!isless (xa, TWO52)) goto label; */
38416 /* xa = xa + TWO52 - TWO52; */
38420 /* xa = copysign (xa, operand1) */
38423 /* generate 1.0 or -1.0 */
38428 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
38432 /* We always need to subtract here to preserve signed zero. */
38441 }
38443 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
38444 into OPERAND0. */
38445 void
38447 {
38448 /* C code for the stuff we expand below.
38449 double xa = fabs (x), x2;
38450 if (!isless (xa, TWO52))
38451 return x;
38452 x2 = (double)(long)x;
38453 Compensate. Floor:
38454 if (x2 > x)
38455 x2 -= 1;
38456 Compensate. Ceil:
38457 if (x2 < x)
38458 x2 += 1;
38459 if (HONOR_SIGNED_ZEROS (mode))
38460 return copysign (x2, x);
38461 return x2;
38462 */
38468 /* Temporary for holding the result, initialized to the input
38469 operand to ease control flow. */
38473 /* xa = abs (operand1) */
38476 /* if (!isless (xa, TWO52)) goto label; */
38479 /* xa = (double)(long)x */
38484 /* generate 1.0 */
38487 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
38502 }
38504 /* Expand SSE sequence for computing round from OPERAND1 storing
38505 into OPERAND0. Sequence that works without relying on DImode truncation
38506 via cvttsd2siq that is only available on 64bit targets. */
38507 void
38509 {
38510 /* C code for the stuff we expand below.
38511 double xa = fabs (x), xa2, x2;
38512 if (!isless (xa, TWO52))
38513 return x;
38514 Using the absolute value and copying back sign makes
38515 -0.0 -> -0.0 correct.
38516 xa2 = xa + TWO52 - TWO52;
38517 Compensate.
38518 dxa = xa2 - xa;
38519 if (dxa <= -0.5)
38520 xa2 += 1;
38521 else if (dxa > 0.5)
38522 xa2 -= 1;
38523 x2 = copysign (xa2, x);
38524 return x2;
38525 */
38531 /* Temporary for holding the result, initialized to the input
38532 operand to ease control flow. */
38536 /* xa = abs (operand1) */
38539 /* if (!isless (xa, TWO52)) goto label; */
38542 /* xa2 = xa + TWO52 - TWO52; */
38546 /* dxa = xa2 - xa; */
38549 /* generate 0.5, 1.0 and -0.5 */
38555 /* Compensate. */
38557 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
38562 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
38568 /* res = copysign (xa2, operand1) */
38575 }
38577 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38578 into OPERAND0. */
38579 void
38581 {
38582 /* C code for SSE variant we expand below.
38583 double xa = fabs (x), x2;
38584 if (!isless (xa, TWO52))
38585 return x;
38586 x2 = (double)(long)x;
38587 if (HONOR_SIGNED_ZEROS (mode))
38588 return copysign (x2, x);
38589 return x2;
38590 */
38596 /* Temporary for holding the result, initialized to the input
38597 operand to ease control flow. */
38601 /* xa = abs (operand1) */
38604 /* if (!isless (xa, TWO52)) goto label; */
38607 /* x = (double)(long)x */
38619 }
38621 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38622 into OPERAND0. */
38623 void
38625 {
38629 /* C code for SSE variant we expand below.
38630 double xa = fabs (x), x2;
38631 if (!isless (xa, TWO52))
38632 return x;
38633 xa2 = xa + TWO52 - TWO52;
38634 Compensate:
38635 if (xa2 > xa)
38636 xa2 -= 1.0;
38637 x2 = copysign (xa2, x);
38638 return x2;
38639 */
38643 /* Temporary for holding the result, initialized to the input
38644 operand to ease control flow. */
38648 /* xa = abs (operand1) */
38651 /* if (!isless (xa, TWO52)) goto label; */
38654 /* res = xa + TWO52 - TWO52; */
38659 /* generate 1.0 */
38662 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38670 /* res = copysign (res, operand1) */
38677 }
38679 /* Expand SSE sequence for computing round from OPERAND1 storing
38680 into OPERAND0. */
38681 void
38683 {
38684 /* C code for the stuff we're doing below:
38685 double xa = fabs (x);
38686 if (!isless (xa, TWO52))
38687 return x;
38688 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38689 return copysign (xa, x);
38690 */
38696 /* Temporary for holding the result, initialized to the input
38697 operand to ease control flow. */
38705 /* load nextafter (0.5, 0.0) */
38710 /* xa = xa + 0.5 */
38714 /* xa = (double)(int64_t)xa */
38719 /* res = copysign (xa, operand1) */
38726 }
38728 /* Expand SSE sequence for computing round
38729 from OP1 storing into OP0 using sse4 round insn. */
38730 void
38732 {
38741 {
38752 }
38754 /* round (a) = trunc (a + copysign (0.5, a)) */
38756 /* load nextafter (0.5, 0.0) */
38762 /* e1 = copysign (0.5, op1) */
38766 /* e2 = op1 + e1 */
38769 /* res = trunc (e2) */
38774 }
38775 \f
38777 /* Table of valid machine attributes. */
38779 {
38780 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38781 affects_type_identity } */
38782 /* Stdcall attribute says callee is responsible for popping arguments
38783 if they are not variable. */
38786 /* Fastcall attribute says callee is responsible for popping arguments
38787 if they are not variable. */
38790 /* Thiscall attribute says callee is responsible for popping arguments
38791 if they are not variable. */
38794 /* Cdecl attribute says the callee is a normal C declaration */
38797 /* Regparm attribute specifies how many integer arguments are to be
38798 passed in registers. */
38801 /* Sseregparm attribute says we are using x86_64 calling conventions
38802 for FP arguments. */
38805 /* The transactional memory builtins are implicitly regparm or fastcall
38806 depending on the ABI. Override the generic do-nothing attribute that
38807 these builtins were declared with. */
38810 /* force_align_arg_pointer says this function realigns the stack at entry. */
38813 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38818 #endif
38823 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38824 SUBTARGET_ATTRIBUTE_TABLE,
38825 #endif
38826 /* ms_abi and sysv_abi calling convention function attributes. */
38833 /* End element. */
38835 };
38837 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38838 static int
38840 tree vectype,
38842 {
38846 {
38891 }
38892 }
38894 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38895 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38896 insn every time. */
38900 /* Initialize vselect_insn. */
38902 static void
38904 {
38906 rtx x;
38917 }
38919 /* Construct (set target (vec_select op0 (parallel perm))) and
38920 return true if that's a valid instruction in the active ISA. */
38922 static bool
38925 {
38951 }
38953 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38955 static bool
38959 {
38961 rtx x;
38976 }
38978 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38979 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38981 static bool
38983 {
38992 ;
38994 ;
38996 ;
38997 else
39000 /* This is a blend, not a permute. Elements must stay in their
39001 respective lanes. */
39003 {
39007 }
39012 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
39013 decision should be extracted elsewhere, so that we only try that
39014 sequence once all budget==3 options have been tried. */
39021 {
39045 /* See if bytes move in pairs so we can use pblendw with
39046 an immediate argument, rather than pblendvb with a vector
39047 argument. */
39050 {
39051 use_pblendvb:
39055 finish_pblendvb:
39061 else
39064 }
39069 /* FALLTHRU */
39071 do_subreg:
39078 /* See if bytes move in pairs. If not, vpblendvb must be used. */
39082 /* See if bytes move in quadruplets. If yes, vpblendd
39083 with immediate can be used. */
39088 {
39089 /* See if bytes move the same in both lanes. If yes,
39090 vpblendw with immediate can be used. */
39095 /* Use vpblendw. */
39100 }
39102 /* Use vpblendd. */
39109 /* See if words move in pairs. If yes, vpblendd can be used. */
39114 {
39115 /* See if words move the same in both lanes. If not,
39116 vpblendvb must be used. */
39119 {
39120 /* Use vpblendvb. */
39130 }
39132 /* Use vpblendw. */
39136 }
39138 /* Use vpblendd. */
39145 /* Use vpblendd. */
39153 }
39155 /* This matches five different patterns with the different modes. */
39161 }
39163 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39164 in terms of the variable form of vpermilps.
39166 Note that we will have already failed the immediate input vpermilps,
39167 which requires that the high and low part shuffle be identical; the
39168 variable form doesn't require that. */
39170 static bool
39172 {
39179 /* We can only permute within the 128-bit lane. */
39181 {
39185 }
39191 {
39194 /* Within each 128-bit lane, the elements of op0 are numbered
39195 from 0 and the elements of op1 are numbered from 4. */
39202 }
39209 }
39211 /* Return true if permutation D can be performed as VMODE permutation
39212 instead. */
39214 static bool
39216 {
39231 else
39237 }
39239 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39240 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
39242 static bool
39244 {
39253 {
39255 {
39258 {
39262 /* Use vperm2i128 insn. The pattern uses
39263 V4DImode instead of V2TImode. */
39272 }
39274 }
39275 }
39276 else
39277 {
39279 {
39282 }
39284 {
39288 /* V4DImode should be already handled through
39289 expand_vselect by vpermq instruction. */
39296 {
39297 /* First see if vpermq can be used for
39298 V8SImode/V16HImode/V32QImode. */
39300 {
39308 }
39310 /* Next see if vpermd can be used. */
39313 }
39314 /* Or if vpermps can be used. */
39319 {
39320 /* vpshufb only works intra lanes, it is not
39321 possible to shuffle bytes in between the lanes. */
39325 }
39326 }
39327 else
39329 }
39337 else
39338 {
39344 else
39348 {
39352 }
39353 }
39362 {
39369 else
39371 }
39372 else
39373 {
39376 }
39379 }
39381 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
39382 in a single instruction. */
39384 static bool
39386 {
39390 /* Check plain VEC_SELECT first, because AVX has instructions that could
39391 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
39392 input where SEL+CONCAT may not. */
39394 {
39400 {
39406 }
39409 {
39413 }
39415 {
39416 /* Use vpbroadcast{b,w,d}. */
39419 {
39438 /* For other modes prefer other shuffles this function creates. */
39440 }
39442 {
39446 }
39447 }
39452 /* There are plenty of patterns in sse.md that are written for
39453 SEL+CONCAT and are not replicated for a single op. Perhaps
39454 that should be changed, to avoid the nastiness here. */
39456 /* Recognize interleave style patterns, which means incrementing
39457 every other permutation operand. */
39459 {
39462 }
39467 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
39469 {
39471 {
39476 }
39481 }
39482 }
39484 /* Finally, try the fully general two operand permute. */
39489 /* Recognize interleave style patterns with reversed operands. */
39491 {
39493 {
39497 else
39500 }
39505 }
39507 /* Try the SSE4.1 blend variable merge instructions. */
39511 /* Try one of the AVX vpermil variable permutations. */
39515 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
39516 vpshufb, vpermd, vpermps or vpermq variable permutation. */
39521 }
39523 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39524 in terms of a pair of pshuflw + pshufhw instructions. */
39526 static bool
39528 {
39536 /* The two permutations only operate in 64-bit lanes. */
39547 /* Emit the pshuflw. */
39554 /* Emit the pshufhw. */
39562 }
39564 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39565 the permutation using the SSSE3 palignr instruction. This succeeds
39566 when all of the elements in PERM fit within one vector and we merely
39567 need to shift them down so that a single vector permutation has a
39568 chance to succeed. */
39570 static bool
39572 {
39576 rtx shift;
39578 /* Even with AVX, palignr only operates on 128-bit vectors. */
39584 {
39590 }
39594 /* Given that we have SSSE3, we know we'll be able to implement the
39595 single operand permutation after the palignr with pshufb. */
39609 {
39614 }
39616 /* Test for the degenerate case where the alignment by itself
39617 produces the desired permutation. */
39625 }
39629 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39630 a two vector permutation into a single vector permutation by using
39631 an interleave operation to merge the vectors. */
39633 static bool
39635 {
39640 rtx seq;
39644 {
39647 }
39649 {
39652 /* For 32-byte modes allow even d->one_operand_p.
39653 The lack of cross-lane shuffling in some instructions
39654 might prevent a single insn shuffle. */
39657 /* If expand_vec_perm_interleave3 can expand this into
39658 a 3 insn sequence, give up and let it be expanded as
39659 3 insn sequence. While that is one insn longer,
39660 it doesn't need a memory operand and in the common
39661 case that both interleave low and high permutations
39662 with the same operands are adjacent needs 4 insns
39663 for both after CSE. */
39666 }
39667 else
39670 /* Examine from whence the elements come. */
39679 {
39682 /* Split the two input vectors into 4 halves. */
39688 /* If the elements from the low halves use interleave low, and similarly
39689 for interleave high. If the elements are from mis-matched halves, we
39690 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39692 {
39693 /* punpckl* */
39695 {
39700 }
39703 }
39705 {
39706 /* punpckh* */
39708 {
39713 }
39716 }
39718 {
39719 /* shufps */
39721 {
39726 }
39728 {
39729 /* shufpd */
39734 }
39735 }
39737 {
39738 /* shufps */
39740 {
39745 }
39747 {
39748 /* shufpd */
39753 }
39754 }
39755 else
39757 }
39758 else
39759 {
39764 /* Split the two input vectors into 8 quarters. */
39770 {
39773 }
39776 {
39780 }
39782 {
39785 }
39788 {
39790 {
39791 /* Attempt to increase the likelihood that dfinal
39792 shuffle will be intra-lane. */
39796 }
39798 /* vperm2f128 or vperm2i128. */
39800 {
39805 }
39810 {
39814 {
39817 }
39818 }
39819 }
39824 {
39825 /* vpunpckl* */
39827 {
39836 }
39837 }
39840 {
39841 /* vpunpckh* */
39843 {
39852 }
39853 }
39854 else
39856 }
39858 /* Use the remapping array set up above to move the elements from their
39859 swizzled locations into their final destinations. */
39862 {
39865 /* If same_halves is true, both halves of the remapped vector are the
39866 same. Avoid cross-lane accesses if possible. */
39868 {
39871 }
39872 else
39874 }
39880 /* Test if the final remap can be done with a single insn. For V4SFmode or
39881 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39894 {
39898 }
39905 }
39907 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39908 a single vector cross-lane permutation into vpermq followed
39909 by any of the single insn permutations. */
39911 static bool
39913 {
39927 {
39930 }
39933 {
39938 }
39951 {
39958 }
39965 {
39970 ;
39973 else
39975 }
39984 }
39986 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39987 a vector permutation using two instructions, vperm2f128 resp.
39988 vperm2i128 followed by any single in-lane permutation. */
39990 static bool
39992 {
40006 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
40007 immediate. For perm < 16 the second permutation uses
40008 d->op0 as first operand, for perm >= 16 it uses d->op1
40009 as first operand. The second operand is the result of
40010 vperm2[fi]128. */
40012 {
40013 /* Ignore permutations which do not move anything cross-lane. */
40015 {
40016 /* The second shuffle for e.g. V4DFmode has
40017 0123 and ABCD operands.
40018 Ignore AB23, as 23 is already in the second lane
40019 of the first operand. */
40021 /* And 01CD, as 01 is in the first lane of the first
40022 operand. */
40024 /* And 4567, as then the vperm2[fi]128 doesn't change
40025 anything on the original 4567 second operand. */
40027 }
40028 else
40029 {
40030 /* The second shuffle for e.g. V4DFmode has
40031 4567 and ABCD operands.
40032 Ignore AB67, as 67 is already in the second lane
40033 of the first operand. */
40035 /* And 45CD, as 45 is in the first lane of the first
40036 operand. */
40038 /* And 0123, as then the vperm2[fi]128 doesn't change
40039 anything on the original 0123 first operand. */
40041 }
40044 {
40050 else
40052 }
40055 {
40059 }
40060 else
40064 {
40068 /* Found a usable second shuffle. dfirst will be
40069 vperm2f128 on d->op0 and d->op1. */
40080 /* And dsecond is some single insn shuffle, taking
40081 d->op0 and result of vperm2f128 (if perm < 16) or
40082 d->op1 and result of vperm2f128 (otherwise). */
40091 }
40093 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
40096 }
40099 }
40101 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
40102 a two vector permutation using 2 intra-lane interleave insns
40103 and cross-lane shuffle for 32-byte vectors. */
40105 static bool
40107 {
40114 ;
40116 ;
40117 else
40132 {
40136 else
40142 else
40148 else
40154 else
40160 else
40166 else
40171 }
40175 }
40177 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
40178 a single vector permutation using a single intra-lane vector
40179 permutation, vperm2f128 swapping the lanes and vblend* insn blending
40180 the non-swapped and swapped vectors together. */
40182 static bool
40184 {
40187 rtx seq;
40192 || TARGET_AVX2
40201 {
40208 }
40243 }
40245 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
40246 permutation using two vperm2f128, followed by a vshufpd insn blending
40247 the two vectors together. */
40249 static bool
40251 {
40294 }
40296 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
40297 permutation with two pshufb insns and an ior. We should have already
40298 failed all two instruction sequences. */
40300 static bool
40302 {
40313 /* Generate two permutation masks. If the required element is within
40314 the given vector it is shuffled into the proper lane. If the required
40315 element is in the other vector, force a zero into the lane by setting
40316 bit 7 in the permutation mask. */
40319 {
40326 {
40329 }
40330 }
40350 }
40352 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
40353 with two vpshufb insns, vpermq and vpor. We should have already failed
40354 all two or three instruction sequences. */
40356 static bool
40358 {
40373 /* Generate two permutation masks. If the required element is within
40374 the same lane, it is shuffled in. If the required element from the
40375 other lane, force a zero by setting bit 7 in the permutation mask.
40376 In the other mask the mask has non-negative elements if element
40377 is requested from the other lane, but also moved to the other lane,
40378 so that the result of vpshufb can have the two V2TImode halves
40379 swapped. */
40382 {
40387 {
40390 }
40391 }
40400 /* Swap the 128-byte lanes of h into hp. */
40404 const1_rtx));
40417 }
40419 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
40420 and extract-odd permutations of two V32QImode and V16QImode operand
40421 with two vpshufb insns, vpor and vpermq. We should have already
40422 failed all two or three instruction sequences. */
40424 static bool
40426 {
40445 /* Generate two permutation masks. In the first permutation mask
40446 the first quarter will contain indexes for the first half
40447 of the op0, the second quarter will contain bit 7 set, third quarter
40448 will contain indexes for the second half of the op0 and the
40449 last quarter bit 7 set. In the second permutation mask
40450 the first quarter will contain bit 7 set, the second quarter
40451 indexes for the first half of the op1, the third quarter bit 7 set
40452 and last quarter indexes for the second half of the op1.
40453 I.e. the first mask e.g. for V32QImode extract even will be:
40454 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
40455 (all values masked with 0xf except for -128) and second mask
40456 for extract even will be
40457 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
40460 {
40466 {
40469 }
40470 }
40489 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
40496 }
40498 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
40499 and extract-odd permutations. */
40501 static bool
40503 {
40507 {
40512 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40516 /* Now an unpck[lh]pd will produce the result required. */
40519 else
40525 {
40532 /* Shuffle within the 128-bit lanes to produce:
40533 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
40537 /* Shuffle the lanes around to produce:
40538 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
40542 /* Shuffle within the 128-bit lanes to produce:
40543 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
40546 /* Shuffle within the 128-bit lanes to produce:
40547 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
40550 /* Shuffle the lanes around to produce:
40551 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
40554 }
40561 /* These are always directly implementable by expand_vec_perm_1. */
40567 else
40568 {
40569 /* We need 2*log2(N)-1 operations to achieve odd/even
40570 with interleave. */
40579 else
40582 }
40588 else
40589 {
40601 else
40604 }
40613 {
40620 }
40625 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40629 /* Now an vpunpck[lh]qdq will produce the result required. */
40632 else
40639 {
40646 }
40651 /* Shuffle the lanes around into
40652 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40662 /* Swap the 2nd and 3rd position in each lane into
40663 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40669 /* Now an vpunpck[lh]qdq will produce
40670 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40675 else
40684 }
40687 }
40689 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40690 extract-even and extract-odd permutations. */
40692 static bool
40694 {
40706 }
40708 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40709 permutations. We assume that expand_vec_perm_1 has already failed. */
40711 static bool
40713 {
40721 {
40724 /* These are special-cased in sse.md so that we can optionally
40725 use the vbroadcast instruction. They expand to two insns
40726 if the input happens to be in a register. */
40733 /* These are always implementable using standard shuffle patterns. */
40738 /* These can be implemented via interleave. We save one insn by
40739 stopping once we have promoted to V4SImode and then use pshufd. */
40740 do
40741 {
40742 rtx dest;
40748 {
40752 }
40759 }
40772 /* For AVX2 broadcasts of the first element vpbroadcast* or
40773 vpermq should be used by expand_vec_perm_1. */
40779 }
40780 }
40782 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40783 broadcast permutations. */
40785 static bool
40787 {
40799 }
40801 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40802 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40803 all the shorter instruction sequences. */
40805 static bool
40807 {
40823 /* Generate 4 permutation masks. If the required element is within
40824 the same lane, it is shuffled in. If the required element from the
40825 other lane, force a zero by setting bit 7 in the permutation mask.
40826 In the other mask the mask has non-negative elements if element
40827 is requested from the other lane, but also moved to the other lane,
40828 so that the result of vpshufb can have the two V2TImode halves
40829 swapped. */
40832 {
40837 }
40843 {
40851 }
40854 {
40856 {
40859 }
40866 }
40868 /* Swap the 128-byte lanes of h[X]. */
40870 {
40876 const1_rtx));
40878 }
40881 {
40883 {
40886 }
40892 }
40895 {
40897 {
40901 }
40904 }
40910 }
40912 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40913 With all of the interface bits taken care of, perform the expansion
40914 in D and return true on success. */
40916 static bool
40918 {
40919 /* Try a single instruction expansion. */
40923 /* Try sequences of two instructions. */
40943 /* Try sequences of three instructions. */
40957 /* Try sequences of four instructions. */
40965 /* ??? Look for narrow permutations whose element orderings would
40966 allow the promotion to a wider mode. */
40968 /* ??? Look for sequences of interleave or a wider permute that place
40969 the data into the correct lanes for a half-vector shuffle like
40970 pshuf[lh]w or vpermilps. */
40972 /* ??? Look for sequences of interleave that produce the desired results.
40973 The combinatorics of punpck[lh] get pretty ugly... */
40978 /* Even longer sequences. */
40983 }
40985 /* If a permutation only uses one operand, make it clear. Returns true
40986 if the permutation references both operands. */
40988 static bool
40990 {
40998 {
41004 {
41007 }
41008 /* The elements of PERM do not suggest that only the first operand
41009 is used, but both operands are identical. Allow easier matching
41010 of the permutation by folding the permutation into the single
41011 input vector. */
41012 /* FALLTHRU */
41023 }
41026 }
41028 bool
41030 {
41035 rtx sel;
41052 {
41057 }
41064 /* If the selector says both arguments are needed, but the operands are the
41065 same, the above tried to expand with one_operand_p and flattened selector.
41066 If that didn't work, retry without one_operand_p; we succeeded with that
41067 during testing. */
41069 {
41073 }
41076 }
41078 /* Implement targetm.vectorize.vec_perm_const_ok. */
41080 static bool
41083 {
41092 /* Given sufficient ISA support we can just return true here
41093 for selected vector modes. */
41095 {
41096 /* All implementable with a single vpperm insn. */
41099 /* All implementable with 2 pshufb + 1 ior. */
41102 /* All implementable with shufpd or unpck[lh]pd. */
41105 }
41107 /* Extract the values from the vector CST into the permutation
41108 array in D. */
41111 {
41115 }
41117 /* For all elements from second vector, fold the elements to first. */
41122 /* Check whether the mask can be applied to the vector type. */
41125 /* Implementable with shufps or pshufd. */
41129 /* Otherwise we have to go through the motions and see if we can
41130 figure out how to generate the requested permutation. */
41141 }
41143 void
41145 {
41160 /* We'll either be able to implement the permutation directly... */
41164 /* ... or we use the special-case patterns. */
41166 }
41168 static void
41170 {
41185 {
41188 }
41190 /* Note that for AVX this isn't one instruction. */
41193 }
41196 /* Expand a vector operation CODE for a V*QImode in terms of the
41197 same operation on V*HImode. */
41199 void
41201 {
41213 {
41226 }
41230 {
41232 /* Unpack data such that we've got a source byte in each low byte of
41233 each word. We don't care what goes into the high byte of each word.
41234 Rather than trying to get zero in there, most convenient is to let
41235 it be a copy of the low byte. */
41240 /* FALLTHRU */
41252 /* FALLTHRU */
41262 }
41264 /* Perform the operation. */
41271 /* Merge the data back into the right place. */
41281 {
41282 /* For SSE2, we used an full interleave, so the desired
41283 results are in the even elements. */
41286 }
41287 else
41288 {
41289 /* For AVX, the interleave used above was not cross-lane. So the
41290 extraction is evens but with the second and third quarter swapped.
41291 Happily, that is even one insn shorter than even extraction. */
41294 }
41301 }
41303 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
41304 if op is CONST_VECTOR with all odd elements equal to their
41305 preceding element. */
41307 static bool
41309 {
41319 }
41321 void
41324 {
41327 rtx x;
41335 /* We only play even/odd games with vectors of SImode. */
41338 /* If we're looking for the odd results, shift those members down to
41339 the even slots. For some cpus this is faster than a PSHUFD. */
41341 {
41342 /* For XOP use vpmacsdqh, but only for smult, as it is only
41343 signed. */
41345 {
41349 }
41360 }
41363 {
41366 else
41368 }
41373 else
41374 {
41377 /* The easiest way to implement this without PMULDQ is to go through
41378 the motions as if we are performing a full 64-bit multiply. With
41379 the exception that we need to do less shuffling of the elements. */
41381 /* Compute the sign-extension, aka highparts, of the two operands. */
41387 /* Multiply LO(A) * HI(B), and vice-versa. */
41393 /* Multiply LO(A) * LO(B). */
41397 /* Combine and shift the highparts into place. */
41402 /* Combine high and low parts. */
41405 }
41407 }
41409 void
41412 {
41418 {
41423 {
41424 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
41425 shuffle the elements once so that all elements are in the right
41426 place for immediate use: { A C B D }. */
41431 }
41432 else
41433 {
41434 /* Put the elements into place for the multiply. */
41438 }
41443 /* Shuffle the elements between the lanes. After this we
41444 have { A B E F | C D G H } for each operand. */
41454 /* Shuffle the elements within the lanes. After this we
41455 have { A A B B | C C D D } or { E E F F | G G H H }. */
41491 }
41492 }
41494 void
41496 {
41506 /* Move the results in element 2 down to element 1; we don't care
41507 what goes in elements 2 and 3. Then we can merge the parts
41508 back together with an interleave.
41510 Note that two other sequences were tried:
41511 (1) Use interleaves at the start instead of psrldq, which allows
41512 us to use a single shufps to merge things back at the end.
41513 (2) Use shufps here to combine the two vectors, then pshufd to
41514 put the elements in the correct order.
41515 In both cases the cost of the reformatting stall was too high
41516 and the overall sequence slower. */
41525 }
41527 void
41529 {
41534 {
41535 /* op1: A,B,C,D, op2: E,F,G,H */
41544 /* t1: B,A,D,C */
41551 /* t2: (B*E),(A*F),(D*G),(C*H) */
41554 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
41557 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
41560 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
41562 }
41563 else
41564 {
41569 {
41572 }
41574 {
41577 }
41578 else
41582 /* Multiply low parts. */
41586 /* Shift input vectors right 32 bits so we can multiply high parts. */
41591 /* Multiply high parts by low parts. */
41597 /* Combine and shift the highparts back. */
41601 /* Combine high and low parts. */
41603 }
41607 }
41609 /* Expand an insert into a vector register through pinsr insn.
41610 Return true if successful. */
41612 bool
41614 {
41622 {
41625 }
41631 {
41636 {
41643 {
41675 }
41684 }
41688 }
41689 }
41690 \f
41691 /* This function returns the calling abi specific va_list type node.
41692 It returns the FNDECL specific va_list type. */
41694 static tree
41696 {
41703 else
41705 }
41707 /* Returns the canonical va_list type specified by TYPE. If there
41708 is no valid TYPE provided, it return NULL_TREE. */
41710 static tree
41712 {
41715 /* Resolve references and pointers to va_list type. */
41724 {
41729 {
41730 /* If va_list is an array type, the argument may have decayed
41731 to a pointer type, e.g. by being passed to another function.
41732 In that case, unwrap both types so that we can compare the
41733 underlying records. */
41736 {
41739 }
41740 }
41747 {
41748 /* If va_list is an array type, the argument may have decayed
41749 to a pointer type, e.g. by being passed to another function.
41750 In that case, unwrap both types so that we can compare the
41751 underlying records. */
41754 {
41757 }
41758 }
41765 {
41766 /* If va_list is an array type, the argument may have decayed
41767 to a pointer type, e.g. by being passed to another function.
41768 In that case, unwrap both types so that we can compare the
41769 underlying records. */
41772 {
41775 }
41776 }
41780 }
41782 }
41784 /* Iterate through the target-specific builtin types for va_list.
41785 IDX denotes the iterator, *PTREE is set to the result type of
41786 the va_list builtin, and *PNAME to its internal type.
41787 Returns zero if there is no element for this index, otherwise
41788 IDX should be increased upon the next call.
41789 Note, do not iterate a base builtin's name like __builtin_va_list.
41790 Used from c_common_nodes_and_builtins. */
41792 static int
41794 {
41796 {
41798 {
41811 }
41812 }
41815 }
41817 #undef TARGET_SCHED_DISPATCH
41818 #define TARGET_SCHED_DISPATCH has_dispatch
41819 #undef TARGET_SCHED_DISPATCH_DO
41820 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41821 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41822 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41823 #undef TARGET_SCHED_REORDER
41824 #define TARGET_SCHED_REORDER ix86_sched_reorder
41825 #undef TARGET_SCHED_ADJUST_PRIORITY
41826 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41827 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41828 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
41829 ix86_dependencies_evaluation_hook
41831 /* The size of the dispatch window is the total number of bytes of
41832 object code allowed in a window. */
41833 #define DISPATCH_WINDOW_SIZE 16
41835 /* Number of dispatch windows considered for scheduling. */
41836 #define MAX_DISPATCH_WINDOWS 3
41838 /* Maximum number of instructions in a window. */
41839 #define MAX_INSN 4
41841 /* Maximum number of immediate operands in a window. */
41842 #define MAX_IMM 4
41844 /* Maximum number of immediate bits allowed in a window. */
41845 #define MAX_IMM_SIZE 128
41847 /* Maximum number of 32 bit immediates allowed in a window. */
41848 #define MAX_IMM_32 4
41850 /* Maximum number of 64 bit immediates allowed in a window. */
41851 #define MAX_IMM_64 2
41853 /* Maximum total of loads or prefetches allowed in a window. */
41854 #define MAX_LOAD 2
41856 /* Maximum total of stores allowed in a window. */
41857 #define MAX_STORE 1
41859 #undef BIG
41860 #define BIG 100
41863 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41866 disp_load,
41867 disp_store,
41868 disp_load_store,
41869 disp_prefetch,
41870 disp_imm,
41871 disp_imm_32,
41872 disp_imm_64,
41873 disp_branch,
41874 disp_cmp,
41875 disp_jcc,
41876 disp_last
41877 };
41879 /* Number of allowable groups in a dispatch window. It is an array
41880 indexed by dispatch_group enum. 100 is used as a big number,
41881 because the number of these kind of operations does not have any
41882 effect in dispatch window, but we need them for other reasons in
41883 the table. */
41886 };
41892 };
41894 /* Instruction path. */
41900 last_path
41901 };
41903 /* sched_insn_info defines a window to the instructions scheduled in
41904 the basic block. It contains a pointer to the insn_info table and
41905 the instruction scheduled.
41907 Windows are allocated for each basic block and are linked
41908 together. */
41910 rtx insn;
41917 /* Linked list of dispatch windows. This is a two way list of
41918 dispatch windows of a basic block. It contains information about
41919 the number of uops in the window and the total number of
41920 instructions and of bytes in the object code for this dispatch
41921 window. */
41939 /* Immediate valuse used in an insn. */
41941 {
41950 /* Get dispatch group of insn. */
41952 static enum dispatch_group
41954 {
41970 }
41972 /* Return true if insn is a compare instruction. */
41974 static bool
41976 {
41984 }
41986 /* Return true if a dispatch violation encountered. */
41988 static bool
41990 {
41994 }
41996 /* Return true if insn is a branch instruction. */
41998 static bool
42000 {
42002 }
42004 /* Return true if insn is a prefetch instruction. */
42006 static bool
42008 {
42010 }
42012 /* This function initializes a dispatch window and the list container holding a
42013 pointer to the window. */
42015 static void
42017 {
42023 else
42041 {
42047 }
42049 }
42051 /* This function allocates and initializes a dispatch window and the
42052 list container holding a pointer to the window. */
42056 {
42061 }
42063 /* This routine initializes the dispatch scheduling information. It
42064 initiates building dispatch scheduler tables and constructs the
42065 first dispatch window. */
42067 static void
42069 {
42070 /* Allocate a dispatch list and a window. */
42075 }
42077 /* This function returns true if a branch is detected. End of a basic block
42078 does not have to be a branch, but here we assume only branches end a
42079 window. */
42081 static bool
42083 {
42085 }
42087 /* This function is called when the end of a window processing is reached. */
42089 static void
42091 {
42094 {
42099 }
42101 }
42103 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
42104 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
42105 for 48 bytes of instructions. Note that these windows are not dispatch
42106 windows that their sizes are DISPATCH_WINDOW_SIZE. */
42110 {
42112 {
42117 }
42123 }
42125 /* Increment the number of immediate operands of an instruction. */
42127 static int
42129 {
42134 {
42141 else
42152 {
42155 }
42160 }
42163 }
42165 /* Compute number of immediate operands of an instruction. */
42167 static void
42169 {
42172 }
42174 /* Return total size of immediate operands of an instruction along with number
42175 of corresponding immediate-operands. It initializes its parameters to zero
42176 befor calling FIND_CONSTANT.
42177 INSN is the input instruction. IMM is the total of immediates.
42178 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
42179 bit immediates. */
42181 static int
42183 {
42191 }
42193 /* This function indicates if an operand of an instruction is an
42194 immediate. */
42196 static bool
42198 {
42207 }
42209 /* Return single or double path for instructions. */
42211 static enum insn_path
42213 {
42223 }
42225 /* Return insn dispatch group. */
42227 static enum dispatch_group
42229 {
42247 }
42249 /* Count number of GROUP restricted instructions in a dispatch
42250 window WINDOW_LIST. */
42252 static int
42254 {
42265 {
42284 }
42297 }
42299 /* This function returns true if insn satisfies dispatch rules on the
42300 last window scheduled. */
42302 static bool
42304 {
42312 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
42313 instructions should be given the lowest priority in the
42314 scheduling process in Haifa scheduler to make sure they will be
42315 scheduled in the same dispatch window as the reference to them. */
42319 /* Check nonrestricted. */
42323 /* Get last dispatch window. */
42328 {
42333 /* Window 1 is full. Go for next window. */
42335 }
42342 /* See if it fits in the first window. */
42344 {
42345 /* The first widow should have only single and double path
42346 uops. */
42352 }
42354 }
42356 /* Add an instruction INSN with NUM_UOPS micro-operations to the
42357 dispatch window WINDOW_LIST. */
42359 static void
42361 {
42379 /* Initialize window with new instruction. */
42400 {
42403 }
42404 }
42406 /* Adds a scheduled instruction, INSN, to the current dispatch window.
42407 If the total bytes of instructions or the number of instructions in
42408 the window exceed allowable, it allocates a new window. */
42410 static void
42412 {
42435 /* Get the last dispatch window. */
42443 else
42446 /* If current window is full, get a new window.
42447 Window number zero is full, if MAX_INSN uops are scheduled in it.
42448 Window number one is full, if window zero's bytes plus window
42449 one's bytes is 32, or if the bytes of the new instruction added
42450 to the total makes it greater than 48, or it has already MAX_INSN
42451 instructions in it. */
42460 {
42463 }
42466 {
42470 {
42473 }
42474 }
42476 {
42481 {
42484 }
42487 }
42488 else
42492 {
42493 /* End of basic block is reached do end-basic-block process. */
42496 }
42497 }
42499 /* Print the dispatch window, WINDOW_NUM, to FILE. */
42501 DEBUG_FUNCTION static void
42503 {
42509 else
42523 {
42526 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
42532 }
42533 }
42535 /* Print to stdout a dispatch window. */
42537 DEBUG_FUNCTION void
42539 {
42541 }
42543 /* Print INSN dispatch information to FILE. */
42545 DEBUG_FUNCTION static void
42547 {
42570 }
42572 /* Print to STDERR the status of the ready list with respect to
42573 dispatch windows. */
42575 DEBUG_FUNCTION void
42577 {
42585 }
42587 /* This routine is the driver of the dispatch scheduler. */
42589 static void
42591 {
42596 }
42598 /* Return TRUE if Dispatch Scheduling is supported. */
42600 static bool
42602 {
42606 {
42622 }
42625 }
42627 /* Implementation of reassociation_width target hook used by
42628 reassoc phase to identify parallelism level in reassociated
42629 tree. Statements tree_code is passed in OPC. Arguments type
42630 is passed in MODE.
42632 Currently parallel reassociation is enabled for Atom
42633 processors only and we set reassociation width to be 2
42634 because Atom may issue up to 2 instructions per cycle.
42636 Return value should be fixed if parallel reassociation is
42637 enabled for other processors. */
42639 static int
42642 {
42651 }
42653 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42654 place emms and femms instructions. */
42656 static enum machine_mode
42658 {
42663 {
42676 else
42686 /* FALLTHRU */
42690 }
42691 }
42693 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42694 vectors. */
42696 static unsigned int
42698 {
42700 }
42702 \f
42704 /* Return class of registers which could be used for pseudo of MODE
42705 and of class RCLASS for spilling instead of memory. Return NO_REGS
42706 if it is not possible or non-profitable. */
42707 static reg_class_t
42709 {
42715 }
42717 /* Implement targetm.vectorize.init_cost. */
42721 {
42725 }
42727 /* Implement targetm.vectorize.add_stmt_cost. */
42729 static unsigned
42733 {
42738 {
42742 /* Statements in an inner loop relative to the loop being
42743 vectorized are weighted more heavily. The value here is
42744 arbitrary and could potentially be improved with analysis. */
42750 }
42753 }
42755 /* Implement targetm.vectorize.finish_cost. */
42757 static void
42760 {
42765 }
42767 /* Implement targetm.vectorize.destroy_cost_data. */
42769 static void
42771 {
42773 }
42775 /* Validate target specific memory model bits in VAL. */
42777 static unsigned HOST_WIDE_INT
42779 {
42786 {
42790 }
42793 {
42797 }
42799 {
42803 }
42805 }
42807 /* Initialize the GCC target structure. */
42808 #undef TARGET_RETURN_IN_MEMORY
42809 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42811 #undef TARGET_LEGITIMIZE_ADDRESS
42812 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42814 #undef TARGET_ATTRIBUTE_TABLE
42815 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42816 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
42817 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
42818 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42819 # undef TARGET_MERGE_DECL_ATTRIBUTES
42820 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42821 #endif
42823 #undef TARGET_COMP_TYPE_ATTRIBUTES
42824 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42826 #undef TARGET_INIT_BUILTINS
42827 #define TARGET_INIT_BUILTINS ix86_init_builtins
42828 #undef TARGET_BUILTIN_DECL
42829 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42830 #undef TARGET_EXPAND_BUILTIN
42831 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42833 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42834 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42835 ix86_builtin_vectorized_function
42837 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42838 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42840 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42841 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42843 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42844 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42846 #undef TARGET_BUILTIN_RECIPROCAL
42847 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42849 #undef TARGET_ASM_FUNCTION_EPILOGUE
42850 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42852 #undef TARGET_ENCODE_SECTION_INFO
42853 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42854 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42855 #else
42856 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42857 #endif
42859 #undef TARGET_ASM_OPEN_PAREN
42861 #undef TARGET_ASM_CLOSE_PAREN
42864 #undef TARGET_ASM_BYTE_OP
42865 #define TARGET_ASM_BYTE_OP ASM_BYTE
42867 #undef TARGET_ASM_ALIGNED_HI_OP
42868 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42869 #undef TARGET_ASM_ALIGNED_SI_OP
42870 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42871 #ifdef ASM_QUAD
42872 #undef TARGET_ASM_ALIGNED_DI_OP
42873 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42874 #endif
42876 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42877 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42879 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42880 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42882 #undef TARGET_ASM_UNALIGNED_HI_OP
42883 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42884 #undef TARGET_ASM_UNALIGNED_SI_OP
42885 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42886 #undef TARGET_ASM_UNALIGNED_DI_OP
42887 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42889 #undef TARGET_PRINT_OPERAND
42890 #define TARGET_PRINT_OPERAND ix86_print_operand
42891 #undef TARGET_PRINT_OPERAND_ADDRESS
42892 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42893 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42894 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42895 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42896 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42898 #undef TARGET_SCHED_INIT_GLOBAL
42899 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42900 #undef TARGET_SCHED_ADJUST_COST
42901 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42902 #undef TARGET_SCHED_ISSUE_RATE
42903 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42904 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42905 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42906 ia32_multipass_dfa_lookahead
42908 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42909 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42911 #undef TARGET_MEMMODEL_CHECK
42912 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42914 #ifdef HAVE_AS_TLS
42915 #undef TARGET_HAVE_TLS
42916 #define TARGET_HAVE_TLS true
42917 #endif
42918 #undef TARGET_CANNOT_FORCE_CONST_MEM
42919 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42920 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42921 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42923 #undef TARGET_DELEGITIMIZE_ADDRESS
42924 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42926 #undef TARGET_MS_BITFIELD_LAYOUT_P
42927 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42929 #if TARGET_MACHO
42930 #undef TARGET_BINDS_LOCAL_P
42931 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42932 #endif
42933 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42934 #undef TARGET_BINDS_LOCAL_P
42935 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42936 #endif
42938 #undef TARGET_ASM_OUTPUT_MI_THUNK
42939 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42940 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42941 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42943 #undef TARGET_ASM_FILE_START
42944 #define TARGET_ASM_FILE_START x86_file_start
42946 #undef TARGET_OPTION_OVERRIDE
42947 #define TARGET_OPTION_OVERRIDE ix86_option_override
42949 #undef TARGET_REGISTER_MOVE_COST
42950 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42951 #undef TARGET_MEMORY_MOVE_COST
42952 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42953 #undef TARGET_RTX_COSTS
42954 #define TARGET_RTX_COSTS ix86_rtx_costs
42955 #undef TARGET_ADDRESS_COST
42956 #define TARGET_ADDRESS_COST ix86_address_cost
42958 #undef TARGET_FIXED_CONDITION_CODE_REGS
42959 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42960 #undef TARGET_CC_MODES_COMPATIBLE
42961 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42963 #undef TARGET_MACHINE_DEPENDENT_REORG
42964 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42966 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42967 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42969 #undef TARGET_BUILD_BUILTIN_VA_LIST
42970 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42972 #undef TARGET_FOLD_BUILTIN
42973 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42975 #undef TARGET_COMPARE_VERSION_PRIORITY
42976 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42978 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42979 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42980 ix86_generate_version_dispatcher_body
42982 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42983 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42984 ix86_get_function_versions_dispatcher
42986 #undef TARGET_ENUM_VA_LIST_P
42987 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42989 #undef TARGET_FN_ABI_VA_LIST
42990 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42992 #undef TARGET_CANONICAL_VA_LIST_TYPE
42993 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42995 #undef TARGET_EXPAND_BUILTIN_VA_START
42996 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42998 #undef TARGET_MD_ASM_CLOBBERS
42999 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
43001 #undef TARGET_PROMOTE_PROTOTYPES
43002 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
43003 #undef TARGET_STRUCT_VALUE_RTX
43004 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
43005 #undef TARGET_SETUP_INCOMING_VARARGS
43006 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
43007 #undef TARGET_MUST_PASS_IN_STACK
43008 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
43009 #undef TARGET_FUNCTION_ARG_ADVANCE
43010 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
43011 #undef TARGET_FUNCTION_ARG
43012 #define TARGET_FUNCTION_ARG ix86_function_arg
43013 #undef TARGET_FUNCTION_ARG_BOUNDARY
43014 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
43015 #undef TARGET_PASS_BY_REFERENCE
43016 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
43017 #undef TARGET_INTERNAL_ARG_POINTER
43018 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
43019 #undef TARGET_UPDATE_STACK_BOUNDARY
43020 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
43021 #undef TARGET_GET_DRAP_RTX
43022 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
43023 #undef TARGET_STRICT_ARGUMENT_NAMING
43024 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
43025 #undef TARGET_STATIC_CHAIN
43026 #define TARGET_STATIC_CHAIN ix86_static_chain
43027 #undef TARGET_TRAMPOLINE_INIT
43028 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
43029 #undef TARGET_RETURN_POPS_ARGS
43030 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
43032 #undef TARGET_LEGITIMATE_COMBINED_INSN
43033 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
43035 #undef TARGET_ASAN_SHADOW_OFFSET
43036 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
43038 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
43039 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
43041 #undef TARGET_SCALAR_MODE_SUPPORTED_P
43042 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
43044 #undef TARGET_VECTOR_MODE_SUPPORTED_P
43045 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
43047 #undef TARGET_C_MODE_FOR_SUFFIX
43048 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
43050 #ifdef HAVE_AS_TLS
43051 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
43052 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
43053 #endif
43055 #ifdef SUBTARGET_INSERT_ATTRIBUTES
43056 #undef TARGET_INSERT_ATTRIBUTES
43057 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
43058 #endif
43060 #undef TARGET_MANGLE_TYPE
43061 #define TARGET_MANGLE_TYPE ix86_mangle_type
43063 #if !TARGET_MACHO
43064 #undef TARGET_STACK_PROTECT_FAIL
43065 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
43066 #endif
43068 #undef TARGET_FUNCTION_VALUE
43069 #define TARGET_FUNCTION_VALUE ix86_function_value
43071 #undef TARGET_FUNCTION_VALUE_REGNO_P
43072 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
43074 #undef TARGET_PROMOTE_FUNCTION_MODE
43075 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
43077 #undef TARGET_MEMBER_TYPE_FORCES_BLK
43078 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
43080 #undef TARGET_INSTANTIATE_DECLS
43081 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
43083 #undef TARGET_SECONDARY_RELOAD
43084 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
43086 #undef TARGET_CLASS_MAX_NREGS
43087 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
43089 #undef TARGET_PREFERRED_RELOAD_CLASS
43090 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
43091 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
43092 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
43093 #undef TARGET_CLASS_LIKELY_SPILLED_P
43094 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
43096 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
43097 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
43098 ix86_builtin_vectorization_cost
43099 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
43100 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
43101 ix86_vectorize_vec_perm_const_ok
43102 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
43103 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
43104 ix86_preferred_simd_mode
43105 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
43106 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
43107 ix86_autovectorize_vector_sizes
43108 #undef TARGET_VECTORIZE_INIT_COST
43109 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
43110 #undef TARGET_VECTORIZE_ADD_STMT_COST
43111 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
43112 #undef TARGET_VECTORIZE_FINISH_COST
43113 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
43114 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
43115 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
43117 #undef TARGET_SET_CURRENT_FUNCTION
43118 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
43120 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
43121 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
43123 #undef TARGET_OPTION_SAVE
43124 #define TARGET_OPTION_SAVE ix86_function_specific_save
43126 #undef TARGET_OPTION_RESTORE
43127 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
43129 #undef TARGET_OPTION_PRINT
43130 #define TARGET_OPTION_PRINT ix86_function_specific_print
43132 #undef TARGET_OPTION_FUNCTION_VERSIONS
43133 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
43135 #undef TARGET_CAN_INLINE_P
43136 #define TARGET_CAN_INLINE_P ix86_can_inline_p
43138 #undef TARGET_EXPAND_TO_RTL_HOOK
43139 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
43141 #undef TARGET_LEGITIMATE_ADDRESS_P
43142 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
43144 #undef TARGET_LRA_P
43145 #define TARGET_LRA_P hook_bool_void_true
43147 #undef TARGET_REGISTER_PRIORITY
43148 #define TARGET_REGISTER_PRIORITY ix86_register_priority
43150 #undef TARGET_REGISTER_USAGE_LEVELING_P
43151 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
43153 #undef TARGET_LEGITIMATE_CONSTANT_P
43154 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
43156 #undef TARGET_FRAME_POINTER_REQUIRED
43157 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
43159 #undef TARGET_CAN_ELIMINATE
43160 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
43162 #undef TARGET_EXTRA_LIVE_ON_ENTRY
43163 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
43165 #undef TARGET_ASM_CODE_END
43166 #define TARGET_ASM_CODE_END ix86_code_end
43168 #undef TARGET_CONDITIONAL_REGISTER_USAGE
43169 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
43171 #if TARGET_MACHO
43172 #undef TARGET_INIT_LIBFUNCS
43173 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
43174 #endif
43176 #undef TARGET_SPILL_CLASS
43177 #define TARGET_SPILL_CLASS ix86_spill_class
43180 \f