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[official-gcc.git] / gcc / combine.c
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1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
58 linking
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
71 combine anyway. */
73 #include "config.h"
74 #include "system.h"
75 #include "coretypes.h"
76 #include "tm.h"
77 #include "rtl.h"
78 #include "tm_p.h"
79 #include "flags.h"
80 #include "regs.h"
81 #include "hard-reg-set.h"
82 #include "basic-block.h"
83 #include "insn-config.h"
84 #include "function.h"
85 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
86 #include "expr.h"
87 #include "insn-attr.h"
88 #include "recog.h"
89 #include "real.h"
90 #include "toplev.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras;
108 /* Number of instructions combined in this function. */
110 static int combine_successes;
112 /* Totals over entire compilation. */
114 static int total_attempts, total_merges, total_extras, total_successes;
117 /* Vector mapping INSN_UIDs to cuids.
118 The cuids are like uids but increase monotonically always.
119 Combine always uses cuids so that it can compare them.
120 But actually renumbering the uids, which we used to do,
121 proves to be a bad idea because it makes it hard to compare
122 the dumps produced by earlier passes with those from later passes. */
124 static int *uid_cuid;
125 static int max_uid_cuid;
127 /* Get the cuid of an insn. */
129 #define INSN_CUID(INSN) \
130 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
132 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
133 BITS_PER_WORD would invoke undefined behavior. Work around it. */
135 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
136 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
138 #define nonzero_bits(X, M) \
139 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
141 #define num_sign_bit_copies(X, M) \
142 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
144 /* Maximum register number, which is the size of the tables below. */
146 static unsigned int combine_max_regno;
148 /* Record last point of death of (hard or pseudo) register n. */
150 static rtx *reg_last_death;
152 /* Record last point of modification of (hard or pseudo) register n. */
154 static rtx *reg_last_set;
156 /* Record the cuid of the last insn that invalidated memory
157 (anything that writes memory, and subroutine calls, but not pushes). */
159 static int mem_last_set;
161 /* Record the cuid of the last CALL_INSN
162 so we can tell whether a potential combination crosses any calls. */
164 static int last_call_cuid;
166 /* When `subst' is called, this is the insn that is being modified
167 (by combining in a previous insn). The PATTERN of this insn
168 is still the old pattern partially modified and it should not be
169 looked at, but this may be used to examine the successors of the insn
170 to judge whether a simplification is valid. */
172 static rtx subst_insn;
174 /* This is the lowest CUID that `subst' is currently dealing with.
175 get_last_value will not return a value if the register was set at or
176 after this CUID. If not for this mechanism, we could get confused if
177 I2 or I1 in try_combine were an insn that used the old value of a register
178 to obtain a new value. In that case, we might erroneously get the
179 new value of the register when we wanted the old one. */
181 static int subst_low_cuid;
183 /* This contains any hard registers that are used in newpat; reg_dead_at_p
184 must consider all these registers to be always live. */
186 static HARD_REG_SET newpat_used_regs;
188 /* This is an insn to which a LOG_LINKS entry has been added. If this
189 insn is the earlier than I2 or I3, combine should rescan starting at
190 that location. */
192 static rtx added_links_insn;
194 /* Basic block in which we are performing combines. */
195 static basic_block this_basic_block;
197 /* A bitmap indicating which blocks had registers go dead at entry.
198 After combine, we'll need to re-do global life analysis with
199 those blocks as starting points. */
200 static sbitmap refresh_blocks;
202 /* The next group of arrays allows the recording of the last value assigned
203 to (hard or pseudo) register n. We use this information to see if an
204 operation being processed is redundant given a prior operation performed
205 on the register. For example, an `and' with a constant is redundant if
206 all the zero bits are already known to be turned off.
208 We use an approach similar to that used by cse, but change it in the
209 following ways:
211 (1) We do not want to reinitialize at each label.
212 (2) It is useful, but not critical, to know the actual value assigned
213 to a register. Often just its form is helpful.
215 Therefore, we maintain the following arrays:
217 reg_last_set_value the last value assigned
218 reg_last_set_label records the value of label_tick when the
219 register was assigned
220 reg_last_set_table_tick records the value of label_tick when a
221 value using the register is assigned
222 reg_last_set_invalid set to nonzero when it is not valid
223 to use the value of this register in some
224 register's value
226 To understand the usage of these tables, it is important to understand
227 the distinction between the value in reg_last_set_value being valid
228 and the register being validly contained in some other expression in the
229 table.
231 Entry I in reg_last_set_value is valid if it is nonzero, and either
232 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
234 Register I may validly appear in any expression returned for the value
235 of another register if reg_n_sets[i] is 1. It may also appear in the
236 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
237 reg_last_set_invalid[j] is zero.
239 If an expression is found in the table containing a register which may
240 not validly appear in an expression, the register is replaced by
241 something that won't match, (clobber (const_int 0)).
243 reg_last_set_invalid[i] is set nonzero when register I is being assigned
244 to and reg_last_set_table_tick[i] == label_tick. */
246 /* Record last value assigned to (hard or pseudo) register n. */
248 static rtx *reg_last_set_value;
250 /* Record the value of label_tick when the value for register n is placed in
251 reg_last_set_value[n]. */
253 static int *reg_last_set_label;
255 /* Record the value of label_tick when an expression involving register n
256 is placed in reg_last_set_value. */
258 static int *reg_last_set_table_tick;
260 /* Set nonzero if references to register n in expressions should not be
261 used. */
263 static char *reg_last_set_invalid;
265 /* Incremented for each label. */
267 static int label_tick;
269 /* Some registers that are set more than once and used in more than one
270 basic block are nevertheless always set in similar ways. For example,
271 a QImode register may be loaded from memory in two places on a machine
272 where byte loads zero extend.
274 We record in the following array what we know about the nonzero
275 bits of a register, specifically which bits are known to be zero.
277 If an entry is zero, it means that we don't know anything special. */
279 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
281 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
282 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
284 static enum machine_mode nonzero_bits_mode;
286 /* Nonzero if we know that a register has some leading bits that are always
287 equal to the sign bit. */
289 static unsigned char *reg_sign_bit_copies;
291 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
292 It is zero while computing them and after combine has completed. This
293 former test prevents propagating values based on previously set values,
294 which can be incorrect if a variable is modified in a loop. */
296 static int nonzero_sign_valid;
298 /* These arrays are maintained in parallel with reg_last_set_value
299 and are used to store the mode in which the register was last set,
300 the bits that were known to be zero when it was last set, and the
301 number of sign bits copies it was known to have when it was last set. */
303 static enum machine_mode *reg_last_set_mode;
304 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
305 static char *reg_last_set_sign_bit_copies;
307 /* Record one modification to rtl structure
308 to be undone by storing old_contents into *where.
309 is_int is 1 if the contents are an int. */
311 struct undo
313 struct undo *next;
314 int is_int;
315 union {rtx r; int i;} old_contents;
316 union {rtx *r; int *i;} where;
319 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
320 num_undo says how many are currently recorded.
322 other_insn is nonzero if we have modified some other insn in the process
323 of working on subst_insn. It must be verified too. */
325 struct undobuf
327 struct undo *undos;
328 struct undo *frees;
329 rtx other_insn;
332 static struct undobuf undobuf;
334 /* Number of times the pseudo being substituted for
335 was found and replaced. */
337 static int n_occurrences;
339 static void do_SUBST (rtx *, rtx);
340 static void do_SUBST_INT (int *, int);
341 static void init_reg_last_arrays (void);
342 static void setup_incoming_promotions (void);
343 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
344 static int cant_combine_insn_p (rtx);
345 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
346 static int sets_function_arg_p (rtx);
347 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
348 static int contains_muldiv (rtx);
349 static rtx try_combine (rtx, rtx, rtx, int *);
350 static void undo_all (void);
351 static void undo_commit (void);
352 static rtx *find_split_point (rtx *, rtx);
353 static rtx subst (rtx, rtx, rtx, int, int);
354 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
355 static rtx simplify_if_then_else (rtx);
356 static rtx simplify_set (rtx);
357 static rtx simplify_logical (rtx, int);
358 static rtx expand_compound_operation (rtx);
359 static rtx expand_field_assignment (rtx);
360 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
361 rtx, unsigned HOST_WIDE_INT, int, int, int);
362 static rtx extract_left_shift (rtx, int);
363 static rtx make_compound_operation (rtx, enum rtx_code);
364 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
365 unsigned HOST_WIDE_INT *);
366 static rtx force_to_mode (rtx, enum machine_mode,
367 unsigned HOST_WIDE_INT, rtx, int);
368 static rtx if_then_else_cond (rtx, rtx *, rtx *);
369 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
370 static int rtx_equal_for_field_assignment_p (rtx, rtx);
371 static rtx make_field_assignment (rtx);
372 static rtx apply_distributive_law (rtx);
373 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
374 unsigned HOST_WIDE_INT);
375 static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
376 rtx, enum machine_mode,
377 unsigned HOST_WIDE_INT);
378 static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
379 enum machine_mode,
380 unsigned HOST_WIDE_INT);
381 static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
382 enum machine_mode,
383 unsigned int);
384 static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
385 enum machine_mode, unsigned int);
386 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
387 HOST_WIDE_INT, enum machine_mode, int *);
388 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
389 int);
390 static int recog_for_combine (rtx *, rtx, rtx *);
391 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
392 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
393 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
394 static void update_table_tick (rtx);
395 static void record_value_for_reg (rtx, rtx, rtx);
396 static void check_promoted_subreg (rtx, rtx);
397 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
398 static void record_dead_and_set_regs (rtx);
399 static int get_last_value_validate (rtx *, rtx, int, int);
400 static rtx get_last_value (rtx);
401 static int use_crosses_set_p (rtx, int);
402 static void reg_dead_at_p_1 (rtx, rtx, void *);
403 static int reg_dead_at_p (rtx, rtx);
404 static void move_deaths (rtx, rtx, int, rtx, rtx *);
405 static int reg_bitfield_target_p (rtx, rtx);
406 static void distribute_notes (rtx, rtx, rtx, rtx);
407 static void distribute_links (rtx);
408 static void mark_used_regs_combine (rtx);
409 static int insn_cuid (rtx);
410 static void record_promoted_value (rtx, rtx);
411 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
412 static enum rtx_code combine_reversed_comparison_code (rtx);
414 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
415 insn. The substitution can be undone by undo_all. If INTO is already
416 set to NEWVAL, do not record this change. Because computing NEWVAL might
417 also call SUBST, we have to compute it before we put anything into
418 the undo table. */
420 static void
421 do_SUBST (rtx *into, rtx newval)
423 struct undo *buf;
424 rtx oldval = *into;
426 if (oldval == newval)
427 return;
429 /* We'd like to catch as many invalid transformations here as
430 possible. Unfortunately, there are way too many mode changes
431 that are perfectly valid, so we'd waste too much effort for
432 little gain doing the checks here. Focus on catching invalid
433 transformations involving integer constants. */
434 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
435 && GET_CODE (newval) == CONST_INT)
437 /* Sanity check that we're replacing oldval with a CONST_INT
438 that is a valid sign-extension for the original mode. */
439 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
440 GET_MODE (oldval)))
441 abort ();
443 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
444 CONST_INT is not valid, because after the replacement, the
445 original mode would be gone. Unfortunately, we can't tell
446 when do_SUBST is called to replace the operand thereof, so we
447 perform this test on oldval instead, checking whether an
448 invalid replacement took place before we got here. */
449 if ((GET_CODE (oldval) == SUBREG
450 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
451 || (GET_CODE (oldval) == ZERO_EXTEND
452 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
453 abort ();
456 if (undobuf.frees)
457 buf = undobuf.frees, undobuf.frees = buf->next;
458 else
459 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->is_int = 0;
462 buf->where.r = into;
463 buf->old_contents.r = oldval;
464 *into = newval;
466 buf->next = undobuf.undos, undobuf.undos = buf;
469 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
471 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
472 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 not safe. */
475 static void
476 do_SUBST_INT (int *into, int newval)
478 struct undo *buf;
479 int oldval = *into;
481 if (oldval == newval)
482 return;
484 if (undobuf.frees)
485 buf = undobuf.frees, undobuf.frees = buf->next;
486 else
487 buf = (struct undo *) xmalloc (sizeof (struct undo));
489 buf->is_int = 1;
490 buf->where.i = into;
491 buf->old_contents.i = oldval;
492 *into = newval;
494 buf->next = undobuf.undos, undobuf.undos = buf;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return nonzero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (rtx f, unsigned int nregs)
507 rtx insn, next;
508 #ifdef HAVE_cc0
509 rtx prev;
510 #endif
511 int i;
512 rtx links, nextlinks;
514 int new_direct_jump_p = 0;
516 combine_attempts = 0;
517 combine_merges = 0;
518 combine_extras = 0;
519 combine_successes = 0;
521 combine_max_regno = nregs;
523 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
524 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
525 reg_sign_bit_copies
526 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
528 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
529 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
532 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
534 reg_last_set_mode
535 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
536 reg_last_set_nonzero_bits
537 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
538 reg_last_set_sign_bit_copies
539 = (char *) xmalloc (nregs * sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
548 if (INSN_UID (insn) > i)
549 i = INSN_UID (insn);
551 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
552 max_uid_cuid = i;
554 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid = 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
572 label_tick = 1;
574 setup_incoming_promotions ();
576 refresh_blocks = sbitmap_alloc (last_basic_block);
577 sbitmap_zero (refresh_blocks);
579 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
581 uid_cuid[INSN_UID (insn)] = ++i;
582 subst_low_cuid = i;
583 subst_insn = insn;
585 if (INSN_P (insn))
587 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
588 NULL);
589 record_dead_and_set_regs (insn);
591 #ifdef AUTO_INC_DEC
592 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
593 if (REG_NOTE_KIND (links) == REG_INC)
594 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
595 NULL);
596 #endif
599 if (GET_CODE (insn) == CODE_LABEL)
600 label_tick++;
603 nonzero_sign_valid = 1;
605 /* Now scan all the insns in forward order. */
607 label_tick = 1;
608 last_call_cuid = 0;
609 mem_last_set = 0;
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 FOR_EACH_BB (this_basic_block)
615 for (insn = this_basic_block->head;
616 insn != NEXT_INSN (this_basic_block->end);
617 insn = next ? next : NEXT_INSN (insn))
619 next = 0;
621 if (GET_CODE (insn) == CODE_LABEL)
622 label_tick++;
624 else if (INSN_P (insn))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn, PATTERN (insn));
630 /* Try this insn with each insn it links back to. */
632 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
633 if ((next = try_combine (insn, XEXP (links, 0),
634 NULL_RTX, &new_direct_jump_p)) != 0)
635 goto retry;
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 rtx link = XEXP (links, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in pursuing this chain any further. */
645 if (GET_CODE (link) == NOTE)
646 continue;
648 for (nextlinks = LOG_LINKS (link);
649 nextlinks;
650 nextlinks = XEXP (nextlinks, 1))
651 if ((next = try_combine (insn, link,
652 XEXP (nextlinks, 0),
653 &new_direct_jump_p)) != 0)
654 goto retry;
657 #ifdef HAVE_cc0
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn) == JUMP_INSN
666 && (prev = prev_nonnote_insn (insn)) != 0
667 && GET_CODE (prev) == INSN
668 && sets_cc0_p (PATTERN (prev)))
670 if ((next = try_combine (insn, prev,
671 NULL_RTX, &new_direct_jump_p)) != 0)
672 goto retry;
674 for (nextlinks = LOG_LINKS (prev); nextlinks;
675 nextlinks = XEXP (nextlinks, 1))
676 if ((next = try_combine (insn, prev,
677 XEXP (nextlinks, 0),
678 &new_direct_jump_p)) != 0)
679 goto retry;
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn) == INSN
684 && (prev = prev_nonnote_insn (insn)) != 0
685 && GET_CODE (prev) == INSN
686 && sets_cc0_p (PATTERN (prev))
687 && GET_CODE (PATTERN (insn)) == SET
688 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
690 if ((next = try_combine (insn, prev,
691 NULL_RTX, &new_direct_jump_p)) != 0)
692 goto retry;
694 for (nextlinks = LOG_LINKS (prev); nextlinks;
695 nextlinks = XEXP (nextlinks, 1))
696 if ((next = try_combine (insn, prev,
697 XEXP (nextlinks, 0),
698 &new_direct_jump_p)) != 0)
699 goto retry;
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
706 if (GET_CODE (XEXP (links, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
708 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
709 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
710 && GET_CODE (prev) == INSN
711 && sets_cc0_p (PATTERN (prev))
712 && (next = try_combine (insn, XEXP (links, 0),
713 prev, &new_direct_jump_p)) != 0)
714 goto retry;
715 #endif
717 /* Try combining an insn with two different insns whose results it
718 uses. */
719 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
720 for (nextlinks = XEXP (links, 1); nextlinks;
721 nextlinks = XEXP (nextlinks, 1))
722 if ((next = try_combine (insn, XEXP (links, 0),
723 XEXP (nextlinks, 0),
724 &new_direct_jump_p)) != 0)
725 goto retry;
727 if (GET_CODE (insn) != NOTE)
728 record_dead_and_set_regs (insn);
730 retry:
735 clear_bb_flags ();
737 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
738 BASIC_BLOCK (i)->flags |= BB_DIRTY);
739 new_direct_jump_p |= purge_all_dead_edges (0);
740 delete_noop_moves (f);
742 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
743 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
744 | PROP_KILL_DEAD_CODE);
746 /* Clean up. */
747 sbitmap_free (refresh_blocks);
748 free (reg_nonzero_bits);
749 free (reg_sign_bit_copies);
750 free (reg_last_death);
751 free (reg_last_set);
752 free (reg_last_set_value);
753 free (reg_last_set_table_tick);
754 free (reg_last_set_label);
755 free (reg_last_set_invalid);
756 free (reg_last_set_mode);
757 free (reg_last_set_nonzero_bits);
758 free (reg_last_set_sign_bit_copies);
759 free (uid_cuid);
762 struct undo *undo, *next;
763 for (undo = undobuf.frees; undo; undo = next)
765 next = undo->next;
766 free (undo);
768 undobuf.frees = 0;
771 total_attempts += combine_attempts;
772 total_merges += combine_merges;
773 total_extras += combine_extras;
774 total_successes += combine_successes;
776 nonzero_sign_valid = 0;
778 /* Make recognizer allow volatile MEMs again. */
779 init_recog ();
781 return new_direct_jump_p;
784 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
786 static void
787 init_reg_last_arrays (void)
789 unsigned int nregs = combine_max_regno;
791 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
792 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
793 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
794 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
795 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
796 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
797 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
798 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
799 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
802 /* Set up any promoted values for incoming argument registers. */
804 static void
805 setup_incoming_promotions (void)
807 #ifdef PROMOTE_FUNCTION_ARGS
808 unsigned int regno;
809 rtx reg;
810 enum machine_mode mode;
811 int unsignedp;
812 rtx first = get_insns ();
814 #ifndef OUTGOING_REGNO
815 #define OUTGOING_REGNO(N) N
816 #endif
817 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
818 /* Check whether this register can hold an incoming pointer
819 argument. FUNCTION_ARG_REGNO_P tests outgoing register
820 numbers, so translate if necessary due to register windows. */
821 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
822 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
824 record_value_for_reg
825 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
826 : SIGN_EXTEND),
827 GET_MODE (reg),
828 gen_rtx_CLOBBER (mode, const0_rtx)));
830 #endif
833 /* Called via note_stores. If X is a pseudo that is narrower than
834 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
836 If we are setting only a portion of X and we can't figure out what
837 portion, assume all bits will be used since we don't know what will
838 be happening.
840 Similarly, set how many bits of X are known to be copies of the sign bit
841 at all locations in the function. This is the smallest number implied
842 by any set of X. */
844 static void
845 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
846 void *data ATTRIBUTE_UNUSED)
848 unsigned int num;
850 if (GET_CODE (x) == REG
851 && REGNO (x) >= FIRST_PSEUDO_REGISTER
852 /* If this register is undefined at the start of the file, we can't
853 say what its contents were. */
854 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
855 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
857 if (set == 0 || GET_CODE (set) == CLOBBER)
859 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
860 reg_sign_bit_copies[REGNO (x)] = 1;
861 return;
864 /* If this is a complex assignment, see if we can convert it into a
865 simple assignment. */
866 set = expand_field_assignment (set);
868 /* If this is a simple assignment, or we have a paradoxical SUBREG,
869 set what we know about X. */
871 if (SET_DEST (set) == x
872 || (GET_CODE (SET_DEST (set)) == SUBREG
873 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
874 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
875 && SUBREG_REG (SET_DEST (set)) == x))
877 rtx src = SET_SRC (set);
879 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
880 /* If X is narrower than a word and SRC is a non-negative
881 constant that would appear negative in the mode of X,
882 sign-extend it for use in reg_nonzero_bits because some
883 machines (maybe most) will actually do the sign-extension
884 and this is the conservative approach.
886 ??? For 2.5, try to tighten up the MD files in this regard
887 instead of this kludge. */
889 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
890 && GET_CODE (src) == CONST_INT
891 && INTVAL (src) > 0
892 && 0 != (INTVAL (src)
893 & ((HOST_WIDE_INT) 1
894 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
895 src = GEN_INT (INTVAL (src)
896 | ((HOST_WIDE_INT) (-1)
897 << GET_MODE_BITSIZE (GET_MODE (x))));
898 #endif
900 /* Don't call nonzero_bits if it cannot change anything. */
901 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
902 reg_nonzero_bits[REGNO (x)]
903 |= nonzero_bits (src, nonzero_bits_mode);
904 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
905 if (reg_sign_bit_copies[REGNO (x)] == 0
906 || reg_sign_bit_copies[REGNO (x)] > num)
907 reg_sign_bit_copies[REGNO (x)] = num;
909 else
911 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
912 reg_sign_bit_copies[REGNO (x)] = 1;
917 /* See if INSN can be combined into I3. PRED and SUCC are optionally
918 insns that were previously combined into I3 or that will be combined
919 into the merger of INSN and I3.
921 Return 0 if the combination is not allowed for any reason.
923 If the combination is allowed, *PDEST will be set to the single
924 destination of INSN and *PSRC to the single source, and this function
925 will return 1. */
927 static int
928 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
929 rtx *pdest, rtx *psrc)
931 int i;
932 rtx set = 0, src, dest;
933 rtx p;
934 #ifdef AUTO_INC_DEC
935 rtx link;
936 #endif
937 int all_adjacent = (succ ? (next_active_insn (insn) == succ
938 && next_active_insn (succ) == i3)
939 : next_active_insn (insn) == i3);
941 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
942 or a PARALLEL consisting of such a SET and CLOBBERs.
944 If INSN has CLOBBER parallel parts, ignore them for our processing.
945 By definition, these happen during the execution of the insn. When it
946 is merged with another insn, all bets are off. If they are, in fact,
947 needed and aren't also supplied in I3, they may be added by
948 recog_for_combine. Otherwise, it won't match.
950 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
951 note.
953 Get the source and destination of INSN. If more than one, can't
954 combine. */
956 if (GET_CODE (PATTERN (insn)) == SET)
957 set = PATTERN (insn);
958 else if (GET_CODE (PATTERN (insn)) == PARALLEL
959 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
961 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
963 rtx elt = XVECEXP (PATTERN (insn), 0, i);
965 switch (GET_CODE (elt))
967 /* This is important to combine floating point insns
968 for the SH4 port. */
969 case USE:
970 /* Combining an isolated USE doesn't make sense.
971 We depend here on combinable_i3pat to reject them. */
972 /* The code below this loop only verifies that the inputs of
973 the SET in INSN do not change. We call reg_set_between_p
974 to verify that the REG in the USE does not change between
975 I3 and INSN.
976 If the USE in INSN was for a pseudo register, the matching
977 insn pattern will likely match any register; combining this
978 with any other USE would only be safe if we knew that the
979 used registers have identical values, or if there was
980 something to tell them apart, e.g. different modes. For
981 now, we forgo such complicated tests and simply disallow
982 combining of USES of pseudo registers with any other USE. */
983 if (GET_CODE (XEXP (elt, 0)) == REG
984 && GET_CODE (PATTERN (i3)) == PARALLEL)
986 rtx i3pat = PATTERN (i3);
987 int i = XVECLEN (i3pat, 0) - 1;
988 unsigned int regno = REGNO (XEXP (elt, 0));
992 rtx i3elt = XVECEXP (i3pat, 0, i);
994 if (GET_CODE (i3elt) == USE
995 && GET_CODE (XEXP (i3elt, 0)) == REG
996 && (REGNO (XEXP (i3elt, 0)) == regno
997 ? reg_set_between_p (XEXP (elt, 0),
998 PREV_INSN (insn), i3)
999 : regno >= FIRST_PSEUDO_REGISTER))
1000 return 0;
1002 while (--i >= 0);
1004 break;
1006 /* We can ignore CLOBBERs. */
1007 case CLOBBER:
1008 break;
1010 case SET:
1011 /* Ignore SETs whose result isn't used but not those that
1012 have side-effects. */
1013 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1014 && ! side_effects_p (elt))
1015 break;
1017 /* If we have already found a SET, this is a second one and
1018 so we cannot combine with this insn. */
1019 if (set)
1020 return 0;
1022 set = elt;
1023 break;
1025 default:
1026 /* Anything else means we can't combine. */
1027 return 0;
1031 if (set == 0
1032 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1033 so don't do anything with it. */
1034 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1035 return 0;
1037 else
1038 return 0;
1040 if (set == 0)
1041 return 0;
1043 set = expand_field_assignment (set);
1044 src = SET_SRC (set), dest = SET_DEST (set);
1046 /* Don't eliminate a store in the stack pointer. */
1047 if (dest == stack_pointer_rtx
1048 /* Don't combine with an insn that sets a register to itself if it has
1049 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1050 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1051 /* Can't merge an ASM_OPERANDS. */
1052 || GET_CODE (src) == ASM_OPERANDS
1053 /* Can't merge a function call. */
1054 || GET_CODE (src) == CALL
1055 /* Don't eliminate a function call argument. */
1056 || (GET_CODE (i3) == CALL_INSN
1057 && (find_reg_fusage (i3, USE, dest)
1058 || (GET_CODE (dest) == REG
1059 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1060 && global_regs[REGNO (dest)])))
1061 /* Don't substitute into an incremented register. */
1062 || FIND_REG_INC_NOTE (i3, dest)
1063 || (succ && FIND_REG_INC_NOTE (succ, dest))
1064 #if 0
1065 /* Don't combine the end of a libcall into anything. */
1066 /* ??? This gives worse code, and appears to be unnecessary, since no
1067 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1068 use REG_RETVAL notes for noconflict blocks, but other code here
1069 makes sure that those insns don't disappear. */
1070 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1071 #endif
1072 /* Make sure that DEST is not used after SUCC but before I3. */
1073 || (succ && ! all_adjacent
1074 && reg_used_between_p (dest, succ, i3))
1075 /* Make sure that the value that is to be substituted for the register
1076 does not use any registers whose values alter in between. However,
1077 If the insns are adjacent, a use can't cross a set even though we
1078 think it might (this can happen for a sequence of insns each setting
1079 the same destination; reg_last_set of that register might point to
1080 a NOTE). If INSN has a REG_EQUIV note, the register is always
1081 equivalent to the memory so the substitution is valid even if there
1082 are intervening stores. Also, don't move a volatile asm or
1083 UNSPEC_VOLATILE across any other insns. */
1084 || (! all_adjacent
1085 && (((GET_CODE (src) != MEM
1086 || ! find_reg_note (insn, REG_EQUIV, src))
1087 && use_crosses_set_p (src, INSN_CUID (insn)))
1088 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1089 || GET_CODE (src) == UNSPEC_VOLATILE))
1090 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1091 better register allocation by not doing the combine. */
1092 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1093 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1094 /* Don't combine across a CALL_INSN, because that would possibly
1095 change whether the life span of some REGs crosses calls or not,
1096 and it is a pain to update that information.
1097 Exception: if source is a constant, moving it later can't hurt.
1098 Accept that special case, because it helps -fforce-addr a lot. */
1099 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1100 return 0;
1102 /* DEST must either be a REG or CC0. */
1103 if (GET_CODE (dest) == REG)
1105 /* If register alignment is being enforced for multi-word items in all
1106 cases except for parameters, it is possible to have a register copy
1107 insn referencing a hard register that is not allowed to contain the
1108 mode being copied and which would not be valid as an operand of most
1109 insns. Eliminate this problem by not combining with such an insn.
1111 Also, on some machines we don't want to extend the life of a hard
1112 register. */
1114 if (GET_CODE (src) == REG
1115 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1116 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1117 /* Don't extend the life of a hard register unless it is
1118 user variable (if we have few registers) or it can't
1119 fit into the desired register (meaning something special
1120 is going on).
1121 Also avoid substituting a return register into I3, because
1122 reload can't handle a conflict with constraints of other
1123 inputs. */
1124 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1125 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1126 return 0;
1128 else if (GET_CODE (dest) != CC0)
1129 return 0;
1131 /* Don't substitute for a register intended as a clobberable operand.
1132 Similarly, don't substitute an expression containing a register that
1133 will be clobbered in I3. */
1134 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1135 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1136 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1137 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1138 src)
1139 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1140 return 0;
1142 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1143 or not), reject, unless nothing volatile comes between it and I3 */
1145 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1147 /* Make sure succ doesn't contain a volatile reference. */
1148 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1149 return 0;
1151 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1152 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1153 return 0;
1156 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1157 to be an explicit register variable, and was chosen for a reason. */
1159 if (GET_CODE (src) == ASM_OPERANDS
1160 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1161 return 0;
1163 /* If there are any volatile insns between INSN and I3, reject, because
1164 they might affect machine state. */
1166 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1167 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1168 return 0;
1170 /* If INSN or I2 contains an autoincrement or autodecrement,
1171 make sure that register is not used between there and I3,
1172 and not already used in I3 either.
1173 Also insist that I3 not be a jump; if it were one
1174 and the incremented register were spilled, we would lose. */
1176 #ifdef AUTO_INC_DEC
1177 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1178 if (REG_NOTE_KIND (link) == REG_INC
1179 && (GET_CODE (i3) == JUMP_INSN
1180 || reg_used_between_p (XEXP (link, 0), insn, i3)
1181 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1182 return 0;
1183 #endif
1185 #ifdef HAVE_cc0
1186 /* Don't combine an insn that follows a CC0-setting insn.
1187 An insn that uses CC0 must not be separated from the one that sets it.
1188 We do, however, allow I2 to follow a CC0-setting insn if that insn
1189 is passed as I1; in that case it will be deleted also.
1190 We also allow combining in this case if all the insns are adjacent
1191 because that would leave the two CC0 insns adjacent as well.
1192 It would be more logical to test whether CC0 occurs inside I1 or I2,
1193 but that would be much slower, and this ought to be equivalent. */
1195 p = prev_nonnote_insn (insn);
1196 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1197 && ! all_adjacent)
1198 return 0;
1199 #endif
1201 /* If we get here, we have passed all the tests and the combination is
1202 to be allowed. */
1204 *pdest = dest;
1205 *psrc = src;
1207 return 1;
1210 /* Check if PAT is an insn - or a part of it - used to set up an
1211 argument for a function in a hard register. */
1213 static int
1214 sets_function_arg_p (rtx pat)
1216 int i;
1217 rtx inner_dest;
1219 switch (GET_CODE (pat))
1221 case INSN:
1222 return sets_function_arg_p (PATTERN (pat));
1224 case PARALLEL:
1225 for (i = XVECLEN (pat, 0); --i >= 0;)
1226 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1227 return 1;
1229 break;
1231 case SET:
1232 inner_dest = SET_DEST (pat);
1233 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1234 || GET_CODE (inner_dest) == SUBREG
1235 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1236 inner_dest = XEXP (inner_dest, 0);
1238 return (GET_CODE (inner_dest) == REG
1239 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1240 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1242 default:
1243 break;
1246 return 0;
1249 /* LOC is the location within I3 that contains its pattern or the component
1250 of a PARALLEL of the pattern. We validate that it is valid for combining.
1252 One problem is if I3 modifies its output, as opposed to replacing it
1253 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1254 so would produce an insn that is not equivalent to the original insns.
1256 Consider:
1258 (set (reg:DI 101) (reg:DI 100))
1259 (set (subreg:SI (reg:DI 101) 0) <foo>)
1261 This is NOT equivalent to:
1263 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1264 (set (reg:DI 101) (reg:DI 100))])
1266 Not only does this modify 100 (in which case it might still be valid
1267 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1269 We can also run into a problem if I2 sets a register that I1
1270 uses and I1 gets directly substituted into I3 (not via I2). In that
1271 case, we would be getting the wrong value of I2DEST into I3, so we
1272 must reject the combination. This case occurs when I2 and I1 both
1273 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1274 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1275 of a SET must prevent combination from occurring.
1277 Before doing the above check, we first try to expand a field assignment
1278 into a set of logical operations.
1280 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1281 we place a register that is both set and used within I3. If more than one
1282 such register is detected, we fail.
1284 Return 1 if the combination is valid, zero otherwise. */
1286 static int
1287 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1288 int i1_not_in_src, rtx *pi3dest_killed)
1290 rtx x = *loc;
1292 if (GET_CODE (x) == SET)
1294 rtx set = x ;
1295 rtx dest = SET_DEST (set);
1296 rtx src = SET_SRC (set);
1297 rtx inner_dest = dest;
1299 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1300 || GET_CODE (inner_dest) == SUBREG
1301 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1302 inner_dest = XEXP (inner_dest, 0);
1304 /* Check for the case where I3 modifies its output, as
1305 discussed above. */
1306 if ((inner_dest != dest
1307 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1308 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1310 /* This is the same test done in can_combine_p except we can't test
1311 all_adjacent; we don't have to, since this instruction will stay
1312 in place, thus we are not considering increasing the lifetime of
1313 INNER_DEST.
1315 Also, if this insn sets a function argument, combining it with
1316 something that might need a spill could clobber a previous
1317 function argument; the all_adjacent test in can_combine_p also
1318 checks this; here, we do a more specific test for this case. */
1320 || (GET_CODE (inner_dest) == REG
1321 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1322 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1323 GET_MODE (inner_dest))))
1324 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1325 return 0;
1327 /* If DEST is used in I3, it is being killed in this insn,
1328 so record that for later.
1329 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1330 STACK_POINTER_REGNUM, since these are always considered to be
1331 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1332 if (pi3dest_killed && GET_CODE (dest) == REG
1333 && reg_referenced_p (dest, PATTERN (i3))
1334 && REGNO (dest) != FRAME_POINTER_REGNUM
1335 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1336 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1337 #endif
1338 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1339 && (REGNO (dest) != ARG_POINTER_REGNUM
1340 || ! fixed_regs [REGNO (dest)])
1341 #endif
1342 && REGNO (dest) != STACK_POINTER_REGNUM)
1344 if (*pi3dest_killed)
1345 return 0;
1347 *pi3dest_killed = dest;
1351 else if (GET_CODE (x) == PARALLEL)
1353 int i;
1355 for (i = 0; i < XVECLEN (x, 0); i++)
1356 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1357 i1_not_in_src, pi3dest_killed))
1358 return 0;
1361 return 1;
1364 /* Return 1 if X is an arithmetic expression that contains a multiplication
1365 and division. We don't count multiplications by powers of two here. */
1367 static int
1368 contains_muldiv (rtx x)
1370 switch (GET_CODE (x))
1372 case MOD: case DIV: case UMOD: case UDIV:
1373 return 1;
1375 case MULT:
1376 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1377 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1378 default:
1379 switch (GET_RTX_CLASS (GET_CODE (x)))
1381 case 'c': case '<': case '2':
1382 return contains_muldiv (XEXP (x, 0))
1383 || contains_muldiv (XEXP (x, 1));
1385 case '1':
1386 return contains_muldiv (XEXP (x, 0));
1388 default:
1389 return 0;
1394 /* Determine whether INSN can be used in a combination. Return nonzero if
1395 not. This is used in try_combine to detect early some cases where we
1396 can't perform combinations. */
1398 static int
1399 cant_combine_insn_p (rtx insn)
1401 rtx set;
1402 rtx src, dest;
1404 /* If this isn't really an insn, we can't do anything.
1405 This can occur when flow deletes an insn that it has merged into an
1406 auto-increment address. */
1407 if (! INSN_P (insn))
1408 return 1;
1410 /* Never combine loads and stores involving hard regs that are likely
1411 to be spilled. The register allocator can usually handle such
1412 reg-reg moves by tying. If we allow the combiner to make
1413 substitutions of likely-spilled regs, we may abort in reload.
1414 As an exception, we allow combinations involving fixed regs; these are
1415 not available to the register allocator so there's no risk involved. */
1417 set = single_set (insn);
1418 if (! set)
1419 return 0;
1420 src = SET_SRC (set);
1421 dest = SET_DEST (set);
1422 if (GET_CODE (src) == SUBREG)
1423 src = SUBREG_REG (src);
1424 if (GET_CODE (dest) == SUBREG)
1425 dest = SUBREG_REG (dest);
1426 if (REG_P (src) && REG_P (dest)
1427 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1428 && ! fixed_regs[REGNO (src)]
1429 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1430 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1431 && ! fixed_regs[REGNO (dest)]
1432 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1433 return 1;
1435 return 0;
1438 /* Try to combine the insns I1 and I2 into I3.
1439 Here I1 and I2 appear earlier than I3.
1440 I1 can be zero; then we combine just I2 into I3.
1442 If we are combining three insns and the resulting insn is not recognized,
1443 try splitting it into two insns. If that happens, I2 and I3 are retained
1444 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1445 are pseudo-deleted.
1447 Return 0 if the combination does not work. Then nothing is changed.
1448 If we did the combination, return the insn at which combine should
1449 resume scanning.
1451 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1452 new direct jump instruction. */
1454 static rtx
1455 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1457 /* New patterns for I3 and I2, respectively. */
1458 rtx newpat, newi2pat = 0;
1459 int substed_i2 = 0, substed_i1 = 0;
1460 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1461 int added_sets_1, added_sets_2;
1462 /* Total number of SETs to put into I3. */
1463 int total_sets;
1464 /* Nonzero is I2's body now appears in I3. */
1465 int i2_is_used;
1466 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1467 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1468 /* Contains I3 if the destination of I3 is used in its source, which means
1469 that the old life of I3 is being killed. If that usage is placed into
1470 I2 and not in I3, a REG_DEAD note must be made. */
1471 rtx i3dest_killed = 0;
1472 /* SET_DEST and SET_SRC of I2 and I1. */
1473 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1474 /* PATTERN (I2), or a copy of it in certain cases. */
1475 rtx i2pat;
1476 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1477 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1478 int i1_feeds_i3 = 0;
1479 /* Notes that must be added to REG_NOTES in I3 and I2. */
1480 rtx new_i3_notes, new_i2_notes;
1481 /* Notes that we substituted I3 into I2 instead of the normal case. */
1482 int i3_subst_into_i2 = 0;
1483 /* Notes that I1, I2 or I3 is a MULT operation. */
1484 int have_mult = 0;
1486 int maxreg;
1487 rtx temp;
1488 rtx link;
1489 int i;
1491 /* Exit early if one of the insns involved can't be used for
1492 combinations. */
1493 if (cant_combine_insn_p (i3)
1494 || cant_combine_insn_p (i2)
1495 || (i1 && cant_combine_insn_p (i1))
1496 /* We also can't do anything if I3 has a
1497 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1498 libcall. */
1499 #if 0
1500 /* ??? This gives worse code, and appears to be unnecessary, since no
1501 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1502 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1503 #endif
1505 return 0;
1507 combine_attempts++;
1508 undobuf.other_insn = 0;
1510 /* Reset the hard register usage information. */
1511 CLEAR_HARD_REG_SET (newpat_used_regs);
1513 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1514 code below, set I1 to be the earlier of the two insns. */
1515 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1516 temp = i1, i1 = i2, i2 = temp;
1518 added_links_insn = 0;
1520 /* First check for one important special-case that the code below will
1521 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1522 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1523 we may be able to replace that destination with the destination of I3.
1524 This occurs in the common code where we compute both a quotient and
1525 remainder into a structure, in which case we want to do the computation
1526 directly into the structure to avoid register-register copies.
1528 Note that this case handles both multiple sets in I2 and also
1529 cases where I2 has a number of CLOBBER or PARALLELs.
1531 We make very conservative checks below and only try to handle the
1532 most common cases of this. For example, we only handle the case
1533 where I2 and I3 are adjacent to avoid making difficult register
1534 usage tests. */
1536 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1537 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1538 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1539 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1540 && GET_CODE (PATTERN (i2)) == PARALLEL
1541 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1542 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1543 below would need to check what is inside (and reg_overlap_mentioned_p
1544 doesn't support those codes anyway). Don't allow those destinations;
1545 the resulting insn isn't likely to be recognized anyway. */
1546 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1547 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1548 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1549 SET_DEST (PATTERN (i3)))
1550 && next_real_insn (i2) == i3)
1552 rtx p2 = PATTERN (i2);
1554 /* Make sure that the destination of I3,
1555 which we are going to substitute into one output of I2,
1556 is not used within another output of I2. We must avoid making this:
1557 (parallel [(set (mem (reg 69)) ...)
1558 (set (reg 69) ...)])
1559 which is not well-defined as to order of actions.
1560 (Besides, reload can't handle output reloads for this.)
1562 The problem can also happen if the dest of I3 is a memory ref,
1563 if another dest in I2 is an indirect memory ref. */
1564 for (i = 0; i < XVECLEN (p2, 0); i++)
1565 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1566 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1567 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1568 SET_DEST (XVECEXP (p2, 0, i))))
1569 break;
1571 if (i == XVECLEN (p2, 0))
1572 for (i = 0; i < XVECLEN (p2, 0); i++)
1573 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1574 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1575 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1577 combine_merges++;
1579 subst_insn = i3;
1580 subst_low_cuid = INSN_CUID (i2);
1582 added_sets_2 = added_sets_1 = 0;
1583 i2dest = SET_SRC (PATTERN (i3));
1585 /* Replace the dest in I2 with our dest and make the resulting
1586 insn the new pattern for I3. Then skip to where we
1587 validate the pattern. Everything was set up above. */
1588 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1589 SET_DEST (PATTERN (i3)));
1591 newpat = p2;
1592 i3_subst_into_i2 = 1;
1593 goto validate_replacement;
1597 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1598 one of those words to another constant, merge them by making a new
1599 constant. */
1600 if (i1 == 0
1601 && (temp = single_set (i2)) != 0
1602 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1603 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1604 && GET_CODE (SET_DEST (temp)) == REG
1605 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1606 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1607 && GET_CODE (PATTERN (i3)) == SET
1608 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1609 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1610 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1611 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1612 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1614 HOST_WIDE_INT lo, hi;
1616 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1617 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1618 else
1620 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1621 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1624 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1626 /* We don't handle the case of the target word being wider
1627 than a host wide int. */
1628 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1629 abort ();
1631 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1632 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1633 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1635 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1636 hi = INTVAL (SET_SRC (PATTERN (i3)));
1637 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1639 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1640 >> (HOST_BITS_PER_WIDE_INT - 1));
1642 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1643 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1644 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1645 (INTVAL (SET_SRC (PATTERN (i3)))));
1646 if (hi == sign)
1647 hi = lo < 0 ? -1 : 0;
1649 else
1650 /* We don't handle the case of the higher word not fitting
1651 entirely in either hi or lo. */
1652 abort ();
1654 combine_merges++;
1655 subst_insn = i3;
1656 subst_low_cuid = INSN_CUID (i2);
1657 added_sets_2 = added_sets_1 = 0;
1658 i2dest = SET_DEST (temp);
1660 SUBST (SET_SRC (temp),
1661 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1663 newpat = PATTERN (i2);
1664 goto validate_replacement;
1667 #ifndef HAVE_cc0
1668 /* If we have no I1 and I2 looks like:
1669 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1670 (set Y OP)])
1671 make up a dummy I1 that is
1672 (set Y OP)
1673 and change I2 to be
1674 (set (reg:CC X) (compare:CC Y (const_int 0)))
1676 (We can ignore any trailing CLOBBERs.)
1678 This undoes a previous combination and allows us to match a branch-and-
1679 decrement insn. */
1681 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1682 && XVECLEN (PATTERN (i2), 0) >= 2
1683 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1684 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1685 == MODE_CC)
1686 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1687 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1688 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1689 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1690 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1691 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1693 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1694 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1695 break;
1697 if (i == 1)
1699 /* We make I1 with the same INSN_UID as I2. This gives it
1700 the same INSN_CUID for value tracking. Our fake I1 will
1701 never appear in the insn stream so giving it the same INSN_UID
1702 as I2 will not cause a problem. */
1704 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1705 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1706 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1707 NULL_RTX);
1709 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1710 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1711 SET_DEST (PATTERN (i1)));
1714 #endif
1716 /* Verify that I2 and I1 are valid for combining. */
1717 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1718 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1720 undo_all ();
1721 return 0;
1724 /* Record whether I2DEST is used in I2SRC and similarly for the other
1725 cases. Knowing this will help in register status updating below. */
1726 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1727 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1728 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1730 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1731 in I2SRC. */
1732 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1734 /* Ensure that I3's pattern can be the destination of combines. */
1735 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1736 i1 && i2dest_in_i1src && i1_feeds_i3,
1737 &i3dest_killed))
1739 undo_all ();
1740 return 0;
1743 /* See if any of the insns is a MULT operation. Unless one is, we will
1744 reject a combination that is, since it must be slower. Be conservative
1745 here. */
1746 if (GET_CODE (i2src) == MULT
1747 || (i1 != 0 && GET_CODE (i1src) == MULT)
1748 || (GET_CODE (PATTERN (i3)) == SET
1749 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1750 have_mult = 1;
1752 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1753 We used to do this EXCEPT in one case: I3 has a post-inc in an
1754 output operand. However, that exception can give rise to insns like
1755 mov r3,(r3)+
1756 which is a famous insn on the PDP-11 where the value of r3 used as the
1757 source was model-dependent. Avoid this sort of thing. */
1759 #if 0
1760 if (!(GET_CODE (PATTERN (i3)) == SET
1761 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1762 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1763 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1764 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1765 /* It's not the exception. */
1766 #endif
1767 #ifdef AUTO_INC_DEC
1768 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1769 if (REG_NOTE_KIND (link) == REG_INC
1770 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1771 || (i1 != 0
1772 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1774 undo_all ();
1775 return 0;
1777 #endif
1779 /* See if the SETs in I1 or I2 need to be kept around in the merged
1780 instruction: whenever the value set there is still needed past I3.
1781 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1783 For the SET in I1, we have two cases: If I1 and I2 independently
1784 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1785 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1786 in I1 needs to be kept around unless I1DEST dies or is set in either
1787 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1788 I1DEST. If so, we know I1 feeds into I2. */
1790 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1792 added_sets_1
1793 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1794 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1796 /* If the set in I2 needs to be kept around, we must make a copy of
1797 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1798 PATTERN (I2), we are only substituting for the original I1DEST, not into
1799 an already-substituted copy. This also prevents making self-referential
1800 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1801 I2DEST. */
1803 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1804 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1805 : PATTERN (i2));
1807 if (added_sets_2)
1808 i2pat = copy_rtx (i2pat);
1810 combine_merges++;
1812 /* Substitute in the latest insn for the regs set by the earlier ones. */
1814 maxreg = max_reg_num ();
1816 subst_insn = i3;
1818 /* It is possible that the source of I2 or I1 may be performing an
1819 unneeded operation, such as a ZERO_EXTEND of something that is known
1820 to have the high part zero. Handle that case by letting subst look at
1821 the innermost one of them.
1823 Another way to do this would be to have a function that tries to
1824 simplify a single insn instead of merging two or more insns. We don't
1825 do this because of the potential of infinite loops and because
1826 of the potential extra memory required. However, doing it the way
1827 we are is a bit of a kludge and doesn't catch all cases.
1829 But only do this if -fexpensive-optimizations since it slows things down
1830 and doesn't usually win. */
1832 if (flag_expensive_optimizations)
1834 /* Pass pc_rtx so no substitutions are done, just simplifications.
1835 The cases that we are interested in here do not involve the few
1836 cases were is_replaced is checked. */
1837 if (i1)
1839 subst_low_cuid = INSN_CUID (i1);
1840 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1842 else
1844 subst_low_cuid = INSN_CUID (i2);
1845 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1849 #ifndef HAVE_cc0
1850 /* Many machines that don't use CC0 have insns that can both perform an
1851 arithmetic operation and set the condition code. These operations will
1852 be represented as a PARALLEL with the first element of the vector
1853 being a COMPARE of an arithmetic operation with the constant zero.
1854 The second element of the vector will set some pseudo to the result
1855 of the same arithmetic operation. If we simplify the COMPARE, we won't
1856 match such a pattern and so will generate an extra insn. Here we test
1857 for this case, where both the comparison and the operation result are
1858 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1859 I2SRC. Later we will make the PARALLEL that contains I2. */
1861 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1862 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1863 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1864 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1866 #ifdef EXTRA_CC_MODES
1867 rtx *cc_use;
1868 enum machine_mode compare_mode;
1869 #endif
1871 newpat = PATTERN (i3);
1872 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1874 i2_is_used = 1;
1876 #ifdef EXTRA_CC_MODES
1877 /* See if a COMPARE with the operand we substituted in should be done
1878 with the mode that is currently being used. If not, do the same
1879 processing we do in `subst' for a SET; namely, if the destination
1880 is used only once, try to replace it with a register of the proper
1881 mode and also replace the COMPARE. */
1882 if (undobuf.other_insn == 0
1883 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1884 &undobuf.other_insn))
1885 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1886 i2src, const0_rtx))
1887 != GET_MODE (SET_DEST (newpat))))
1889 unsigned int regno = REGNO (SET_DEST (newpat));
1890 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1892 if (regno < FIRST_PSEUDO_REGISTER
1893 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1894 && ! REG_USERVAR_P (SET_DEST (newpat))))
1896 if (regno >= FIRST_PSEUDO_REGISTER)
1897 SUBST (regno_reg_rtx[regno], new_dest);
1899 SUBST (SET_DEST (newpat), new_dest);
1900 SUBST (XEXP (*cc_use, 0), new_dest);
1901 SUBST (SET_SRC (newpat),
1902 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1904 else
1905 undobuf.other_insn = 0;
1907 #endif
1909 else
1910 #endif
1912 n_occurrences = 0; /* `subst' counts here */
1914 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1915 need to make a unique copy of I2SRC each time we substitute it
1916 to avoid self-referential rtl. */
1918 subst_low_cuid = INSN_CUID (i2);
1919 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1920 ! i1_feeds_i3 && i1dest_in_i1src);
1921 substed_i2 = 1;
1923 /* Record whether i2's body now appears within i3's body. */
1924 i2_is_used = n_occurrences;
1927 /* If we already got a failure, don't try to do more. Otherwise,
1928 try to substitute in I1 if we have it. */
1930 if (i1 && GET_CODE (newpat) != CLOBBER)
1932 /* Before we can do this substitution, we must redo the test done
1933 above (see detailed comments there) that ensures that I1DEST
1934 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1936 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1937 0, (rtx*) 0))
1939 undo_all ();
1940 return 0;
1943 n_occurrences = 0;
1944 subst_low_cuid = INSN_CUID (i1);
1945 newpat = subst (newpat, i1dest, i1src, 0, 0);
1946 substed_i1 = 1;
1949 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1950 to count all the ways that I2SRC and I1SRC can be used. */
1951 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1952 && i2_is_used + added_sets_2 > 1)
1953 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1954 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1955 > 1))
1956 /* Fail if we tried to make a new register (we used to abort, but there's
1957 really no reason to). */
1958 || max_reg_num () != maxreg
1959 /* Fail if we couldn't do something and have a CLOBBER. */
1960 || GET_CODE (newpat) == CLOBBER
1961 /* Fail if this new pattern is a MULT and we didn't have one before
1962 at the outer level. */
1963 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1964 && ! have_mult))
1966 undo_all ();
1967 return 0;
1970 /* If the actions of the earlier insns must be kept
1971 in addition to substituting them into the latest one,
1972 we must make a new PARALLEL for the latest insn
1973 to hold additional the SETs. */
1975 if (added_sets_1 || added_sets_2)
1977 combine_extras++;
1979 if (GET_CODE (newpat) == PARALLEL)
1981 rtvec old = XVEC (newpat, 0);
1982 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1983 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1984 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
1985 sizeof (old->elem[0]) * old->num_elem);
1987 else
1989 rtx old = newpat;
1990 total_sets = 1 + added_sets_1 + added_sets_2;
1991 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1992 XVECEXP (newpat, 0, 0) = old;
1995 if (added_sets_1)
1996 XVECEXP (newpat, 0, --total_sets)
1997 = (GET_CODE (PATTERN (i1)) == PARALLEL
1998 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2000 if (added_sets_2)
2002 /* If there is no I1, use I2's body as is. We used to also not do
2003 the subst call below if I2 was substituted into I3,
2004 but that could lose a simplification. */
2005 if (i1 == 0)
2006 XVECEXP (newpat, 0, --total_sets) = i2pat;
2007 else
2008 /* See comment where i2pat is assigned. */
2009 XVECEXP (newpat, 0, --total_sets)
2010 = subst (i2pat, i1dest, i1src, 0, 0);
2014 /* We come here when we are replacing a destination in I2 with the
2015 destination of I3. */
2016 validate_replacement:
2018 /* Note which hard regs this insn has as inputs. */
2019 mark_used_regs_combine (newpat);
2021 /* Is the result of combination a valid instruction? */
2022 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2024 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2025 the second SET's destination is a register that is unused. In that case,
2026 we just need the first SET. This can occur when simplifying a divmod
2027 insn. We *must* test for this case here because the code below that
2028 splits two independent SETs doesn't handle this case correctly when it
2029 updates the register status. Also check the case where the first
2030 SET's destination is unused. That would not cause incorrect code, but
2031 does cause an unneeded insn to remain. */
2033 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2034 && XVECLEN (newpat, 0) == 2
2035 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2036 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2037 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2038 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2039 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2040 && asm_noperands (newpat) < 0)
2042 newpat = XVECEXP (newpat, 0, 0);
2043 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2046 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2047 && XVECLEN (newpat, 0) == 2
2048 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2049 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2050 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2051 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2052 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2053 && asm_noperands (newpat) < 0)
2055 newpat = XVECEXP (newpat, 0, 1);
2056 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2059 /* If we were combining three insns and the result is a simple SET
2060 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2061 insns. There are two ways to do this. It can be split using a
2062 machine-specific method (like when you have an addition of a large
2063 constant) or by combine in the function find_split_point. */
2065 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2066 && asm_noperands (newpat) < 0)
2068 rtx m_split, *split;
2069 rtx ni2dest = i2dest;
2071 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2072 use I2DEST as a scratch register will help. In the latter case,
2073 convert I2DEST to the mode of the source of NEWPAT if we can. */
2075 m_split = split_insns (newpat, i3);
2077 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2078 inputs of NEWPAT. */
2080 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2081 possible to try that as a scratch reg. This would require adding
2082 more code to make it work though. */
2084 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2086 /* If I2DEST is a hard register or the only use of a pseudo,
2087 we can change its mode. */
2088 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2089 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2090 && GET_CODE (i2dest) == REG
2091 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2092 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2093 && ! REG_USERVAR_P (i2dest))))
2094 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2095 REGNO (i2dest));
2097 m_split = split_insns (gen_rtx_PARALLEL
2098 (VOIDmode,
2099 gen_rtvec (2, newpat,
2100 gen_rtx_CLOBBER (VOIDmode,
2101 ni2dest))),
2102 i3);
2103 /* If the split with the mode-changed register didn't work, try
2104 the original register. */
2105 if (! m_split && ni2dest != i2dest)
2107 ni2dest = i2dest;
2108 m_split = split_insns (gen_rtx_PARALLEL
2109 (VOIDmode,
2110 gen_rtvec (2, newpat,
2111 gen_rtx_CLOBBER (VOIDmode,
2112 i2dest))),
2113 i3);
2117 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2119 m_split = PATTERN (m_split);
2120 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2121 if (insn_code_number >= 0)
2122 newpat = m_split;
2124 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2125 && (next_real_insn (i2) == i3
2126 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2128 rtx i2set, i3set;
2129 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2130 newi2pat = PATTERN (m_split);
2132 i3set = single_set (NEXT_INSN (m_split));
2133 i2set = single_set (m_split);
2135 /* In case we changed the mode of I2DEST, replace it in the
2136 pseudo-register table here. We can't do it above in case this
2137 code doesn't get executed and we do a split the other way. */
2139 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2140 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2142 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2144 /* If I2 or I3 has multiple SETs, we won't know how to track
2145 register status, so don't use these insns. If I2's destination
2146 is used between I2 and I3, we also can't use these insns. */
2148 if (i2_code_number >= 0 && i2set && i3set
2149 && (next_real_insn (i2) == i3
2150 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2151 insn_code_number = recog_for_combine (&newi3pat, i3,
2152 &new_i3_notes);
2153 if (insn_code_number >= 0)
2154 newpat = newi3pat;
2156 /* It is possible that both insns now set the destination of I3.
2157 If so, we must show an extra use of it. */
2159 if (insn_code_number >= 0)
2161 rtx new_i3_dest = SET_DEST (i3set);
2162 rtx new_i2_dest = SET_DEST (i2set);
2164 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2165 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2166 || GET_CODE (new_i3_dest) == SUBREG)
2167 new_i3_dest = XEXP (new_i3_dest, 0);
2169 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2170 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2171 || GET_CODE (new_i2_dest) == SUBREG)
2172 new_i2_dest = XEXP (new_i2_dest, 0);
2174 if (GET_CODE (new_i3_dest) == REG
2175 && GET_CODE (new_i2_dest) == REG
2176 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2177 REG_N_SETS (REGNO (new_i2_dest))++;
2181 /* If we can split it and use I2DEST, go ahead and see if that
2182 helps things be recognized. Verify that none of the registers
2183 are set between I2 and I3. */
2184 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2185 #ifdef HAVE_cc0
2186 && GET_CODE (i2dest) == REG
2187 #endif
2188 /* We need I2DEST in the proper mode. If it is a hard register
2189 or the only use of a pseudo, we can change its mode. */
2190 && (GET_MODE (*split) == GET_MODE (i2dest)
2191 || GET_MODE (*split) == VOIDmode
2192 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2193 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2194 && ! REG_USERVAR_P (i2dest)))
2195 && (next_real_insn (i2) == i3
2196 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2197 /* We can't overwrite I2DEST if its value is still used by
2198 NEWPAT. */
2199 && ! reg_referenced_p (i2dest, newpat))
2201 rtx newdest = i2dest;
2202 enum rtx_code split_code = GET_CODE (*split);
2203 enum machine_mode split_mode = GET_MODE (*split);
2205 /* Get NEWDEST as a register in the proper mode. We have already
2206 validated that we can do this. */
2207 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2209 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2211 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2212 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2215 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2216 an ASHIFT. This can occur if it was inside a PLUS and hence
2217 appeared to be a memory address. This is a kludge. */
2218 if (split_code == MULT
2219 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2220 && INTVAL (XEXP (*split, 1)) > 0
2221 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2223 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2224 XEXP (*split, 0), GEN_INT (i)));
2225 /* Update split_code because we may not have a multiply
2226 anymore. */
2227 split_code = GET_CODE (*split);
2230 #ifdef INSN_SCHEDULING
2231 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2232 be written as a ZERO_EXTEND. */
2233 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2235 #ifdef LOAD_EXTEND_OP
2236 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2237 what it really is. */
2238 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2239 == SIGN_EXTEND)
2240 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2241 SUBREG_REG (*split)));
2242 else
2243 #endif
2244 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2245 SUBREG_REG (*split)));
2247 #endif
2249 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2250 SUBST (*split, newdest);
2251 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2253 /* If the split point was a MULT and we didn't have one before,
2254 don't use one now. */
2255 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2256 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2260 /* Check for a case where we loaded from memory in a narrow mode and
2261 then sign extended it, but we need both registers. In that case,
2262 we have a PARALLEL with both loads from the same memory location.
2263 We can split this into a load from memory followed by a register-register
2264 copy. This saves at least one insn, more if register allocation can
2265 eliminate the copy.
2267 We cannot do this if the destination of the first assignment is a
2268 condition code register or cc0. We eliminate this case by making sure
2269 the SET_DEST and SET_SRC have the same mode.
2271 We cannot do this if the destination of the second assignment is
2272 a register that we have already assumed is zero-extended. Similarly
2273 for a SUBREG of such a register. */
2275 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2276 && GET_CODE (newpat) == PARALLEL
2277 && XVECLEN (newpat, 0) == 2
2278 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2279 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2280 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2281 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2282 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2283 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2284 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2285 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2286 INSN_CUID (i2))
2287 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2288 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2289 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2290 (GET_CODE (temp) == REG
2291 && reg_nonzero_bits[REGNO (temp)] != 0
2292 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2293 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2294 && (reg_nonzero_bits[REGNO (temp)]
2295 != GET_MODE_MASK (word_mode))))
2296 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2297 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2298 (GET_CODE (temp) == REG
2299 && reg_nonzero_bits[REGNO (temp)] != 0
2300 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2301 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2302 && (reg_nonzero_bits[REGNO (temp)]
2303 != GET_MODE_MASK (word_mode)))))
2304 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2305 SET_SRC (XVECEXP (newpat, 0, 1)))
2306 && ! find_reg_note (i3, REG_UNUSED,
2307 SET_DEST (XVECEXP (newpat, 0, 0))))
2309 rtx ni2dest;
2311 newi2pat = XVECEXP (newpat, 0, 0);
2312 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2313 newpat = XVECEXP (newpat, 0, 1);
2314 SUBST (SET_SRC (newpat),
2315 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2316 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2318 if (i2_code_number >= 0)
2319 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2321 if (insn_code_number >= 0)
2323 rtx insn;
2324 rtx link;
2326 /* If we will be able to accept this, we have made a change to the
2327 destination of I3. This can invalidate a LOG_LINKS pointing
2328 to I3. No other part of combine.c makes such a transformation.
2330 The new I3 will have a destination that was previously the
2331 destination of I1 or I2 and which was used in i2 or I3. Call
2332 distribute_links to make a LOG_LINK from the next use of
2333 that destination. */
2335 PATTERN (i3) = newpat;
2336 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2338 /* I3 now uses what used to be its destination and which is
2339 now I2's destination. That means we need a LOG_LINK from
2340 I3 to I2. But we used to have one, so we still will.
2342 However, some later insn might be using I2's dest and have
2343 a LOG_LINK pointing at I3. We must remove this link.
2344 The simplest way to remove the link is to point it at I1,
2345 which we know will be a NOTE. */
2347 for (insn = NEXT_INSN (i3);
2348 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2349 || insn != this_basic_block->next_bb->head);
2350 insn = NEXT_INSN (insn))
2352 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2354 for (link = LOG_LINKS (insn); link;
2355 link = XEXP (link, 1))
2356 if (XEXP (link, 0) == i3)
2357 XEXP (link, 0) = i1;
2359 break;
2365 /* Similarly, check for a case where we have a PARALLEL of two independent
2366 SETs but we started with three insns. In this case, we can do the sets
2367 as two separate insns. This case occurs when some SET allows two
2368 other insns to combine, but the destination of that SET is still live. */
2370 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2371 && GET_CODE (newpat) == PARALLEL
2372 && XVECLEN (newpat, 0) == 2
2373 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2374 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2375 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2376 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2377 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2378 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2379 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2380 INSN_CUID (i2))
2381 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2382 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2383 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2384 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2385 XVECEXP (newpat, 0, 0))
2386 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2387 XVECEXP (newpat, 0, 1))
2388 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2389 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2391 /* Normally, it doesn't matter which of the two is done first,
2392 but it does if one references cc0. In that case, it has to
2393 be first. */
2394 #ifdef HAVE_cc0
2395 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2397 newi2pat = XVECEXP (newpat, 0, 0);
2398 newpat = XVECEXP (newpat, 0, 1);
2400 else
2401 #endif
2403 newi2pat = XVECEXP (newpat, 0, 1);
2404 newpat = XVECEXP (newpat, 0, 0);
2407 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2409 if (i2_code_number >= 0)
2410 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2413 /* If it still isn't recognized, fail and change things back the way they
2414 were. */
2415 if ((insn_code_number < 0
2416 /* Is the result a reasonable ASM_OPERANDS? */
2417 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2419 undo_all ();
2420 return 0;
2423 /* If we had to change another insn, make sure it is valid also. */
2424 if (undobuf.other_insn)
2426 rtx other_pat = PATTERN (undobuf.other_insn);
2427 rtx new_other_notes;
2428 rtx note, next;
2430 CLEAR_HARD_REG_SET (newpat_used_regs);
2432 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2433 &new_other_notes);
2435 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2437 undo_all ();
2438 return 0;
2441 PATTERN (undobuf.other_insn) = other_pat;
2443 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2444 are still valid. Then add any non-duplicate notes added by
2445 recog_for_combine. */
2446 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2448 next = XEXP (note, 1);
2450 if (REG_NOTE_KIND (note) == REG_UNUSED
2451 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2453 if (GET_CODE (XEXP (note, 0)) == REG)
2454 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2456 remove_note (undobuf.other_insn, note);
2460 for (note = new_other_notes; note; note = XEXP (note, 1))
2461 if (GET_CODE (XEXP (note, 0)) == REG)
2462 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2464 distribute_notes (new_other_notes, undobuf.other_insn,
2465 undobuf.other_insn, NULL_RTX);
2467 #ifdef HAVE_cc0
2468 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2469 they are adjacent to each other or not. */
2471 rtx p = prev_nonnote_insn (i3);
2472 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2473 && sets_cc0_p (newi2pat))
2475 undo_all ();
2476 return 0;
2479 #endif
2481 /* We now know that we can do this combination. Merge the insns and
2482 update the status of registers and LOG_LINKS. */
2485 rtx i3notes, i2notes, i1notes = 0;
2486 rtx i3links, i2links, i1links = 0;
2487 rtx midnotes = 0;
2488 unsigned int regno;
2490 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2491 clear them. */
2492 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2493 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2494 if (i1)
2495 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2497 /* Ensure that we do not have something that should not be shared but
2498 occurs multiple times in the new insns. Check this by first
2499 resetting all the `used' flags and then copying anything is shared. */
2501 reset_used_flags (i3notes);
2502 reset_used_flags (i2notes);
2503 reset_used_flags (i1notes);
2504 reset_used_flags (newpat);
2505 reset_used_flags (newi2pat);
2506 if (undobuf.other_insn)
2507 reset_used_flags (PATTERN (undobuf.other_insn));
2509 i3notes = copy_rtx_if_shared (i3notes);
2510 i2notes = copy_rtx_if_shared (i2notes);
2511 i1notes = copy_rtx_if_shared (i1notes);
2512 newpat = copy_rtx_if_shared (newpat);
2513 newi2pat = copy_rtx_if_shared (newi2pat);
2514 if (undobuf.other_insn)
2515 reset_used_flags (PATTERN (undobuf.other_insn));
2517 INSN_CODE (i3) = insn_code_number;
2518 PATTERN (i3) = newpat;
2520 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2522 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2524 reset_used_flags (call_usage);
2525 call_usage = copy_rtx (call_usage);
2527 if (substed_i2)
2528 replace_rtx (call_usage, i2dest, i2src);
2530 if (substed_i1)
2531 replace_rtx (call_usage, i1dest, i1src);
2533 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2536 if (undobuf.other_insn)
2537 INSN_CODE (undobuf.other_insn) = other_code_number;
2539 /* We had one special case above where I2 had more than one set and
2540 we replaced a destination of one of those sets with the destination
2541 of I3. In that case, we have to update LOG_LINKS of insns later
2542 in this basic block. Note that this (expensive) case is rare.
2544 Also, in this case, we must pretend that all REG_NOTEs for I2
2545 actually came from I3, so that REG_UNUSED notes from I2 will be
2546 properly handled. */
2548 if (i3_subst_into_i2)
2550 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2551 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2552 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2553 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2554 && ! find_reg_note (i2, REG_UNUSED,
2555 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2556 for (temp = NEXT_INSN (i2);
2557 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2558 || this_basic_block->head != temp);
2559 temp = NEXT_INSN (temp))
2560 if (temp != i3 && INSN_P (temp))
2561 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2562 if (XEXP (link, 0) == i2)
2563 XEXP (link, 0) = i3;
2565 if (i3notes)
2567 rtx link = i3notes;
2568 while (XEXP (link, 1))
2569 link = XEXP (link, 1);
2570 XEXP (link, 1) = i2notes;
2572 else
2573 i3notes = i2notes;
2574 i2notes = 0;
2577 LOG_LINKS (i3) = 0;
2578 REG_NOTES (i3) = 0;
2579 LOG_LINKS (i2) = 0;
2580 REG_NOTES (i2) = 0;
2582 if (newi2pat)
2584 INSN_CODE (i2) = i2_code_number;
2585 PATTERN (i2) = newi2pat;
2587 else
2589 PUT_CODE (i2, NOTE);
2590 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2591 NOTE_SOURCE_FILE (i2) = 0;
2594 if (i1)
2596 LOG_LINKS (i1) = 0;
2597 REG_NOTES (i1) = 0;
2598 PUT_CODE (i1, NOTE);
2599 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2600 NOTE_SOURCE_FILE (i1) = 0;
2603 /* Get death notes for everything that is now used in either I3 or
2604 I2 and used to die in a previous insn. If we built two new
2605 patterns, move from I1 to I2 then I2 to I3 so that we get the
2606 proper movement on registers that I2 modifies. */
2608 if (newi2pat)
2610 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2611 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2613 else
2614 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2615 i3, &midnotes);
2617 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2618 if (i3notes)
2619 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2620 if (i2notes)
2621 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2622 if (i1notes)
2623 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2624 if (midnotes)
2625 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2627 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2628 know these are REG_UNUSED and want them to go to the desired insn,
2629 so we always pass it as i3. We have not counted the notes in
2630 reg_n_deaths yet, so we need to do so now. */
2632 if (newi2pat && new_i2_notes)
2634 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2635 if (GET_CODE (XEXP (temp, 0)) == REG)
2636 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2638 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2641 if (new_i3_notes)
2643 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2644 if (GET_CODE (XEXP (temp, 0)) == REG)
2645 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2647 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2650 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2651 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2652 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2653 in that case, it might delete I2. Similarly for I2 and I1.
2654 Show an additional death due to the REG_DEAD note we make here. If
2655 we discard it in distribute_notes, we will decrement it again. */
2657 if (i3dest_killed)
2659 if (GET_CODE (i3dest_killed) == REG)
2660 REG_N_DEATHS (REGNO (i3dest_killed))++;
2662 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2663 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2664 NULL_RTX),
2665 NULL_RTX, i2, NULL_RTX);
2666 else
2667 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2668 NULL_RTX),
2669 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2672 if (i2dest_in_i2src)
2674 if (GET_CODE (i2dest) == REG)
2675 REG_N_DEATHS (REGNO (i2dest))++;
2677 if (newi2pat && reg_set_p (i2dest, newi2pat))
2678 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2679 NULL_RTX, i2, NULL_RTX);
2680 else
2681 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2682 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2685 if (i1dest_in_i1src)
2687 if (GET_CODE (i1dest) == REG)
2688 REG_N_DEATHS (REGNO (i1dest))++;
2690 if (newi2pat && reg_set_p (i1dest, newi2pat))
2691 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2692 NULL_RTX, i2, NULL_RTX);
2693 else
2694 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2695 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2698 distribute_links (i3links);
2699 distribute_links (i2links);
2700 distribute_links (i1links);
2702 if (GET_CODE (i2dest) == REG)
2704 rtx link;
2705 rtx i2_insn = 0, i2_val = 0, set;
2707 /* The insn that used to set this register doesn't exist, and
2708 this life of the register may not exist either. See if one of
2709 I3's links points to an insn that sets I2DEST. If it does,
2710 that is now the last known value for I2DEST. If we don't update
2711 this and I2 set the register to a value that depended on its old
2712 contents, we will get confused. If this insn is used, thing
2713 will be set correctly in combine_instructions. */
2715 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2716 if ((set = single_set (XEXP (link, 0))) != 0
2717 && rtx_equal_p (i2dest, SET_DEST (set)))
2718 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2720 record_value_for_reg (i2dest, i2_insn, i2_val);
2722 /* If the reg formerly set in I2 died only once and that was in I3,
2723 zero its use count so it won't make `reload' do any work. */
2724 if (! added_sets_2
2725 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2726 && ! i2dest_in_i2src)
2728 regno = REGNO (i2dest);
2729 REG_N_SETS (regno)--;
2733 if (i1 && GET_CODE (i1dest) == REG)
2735 rtx link;
2736 rtx i1_insn = 0, i1_val = 0, set;
2738 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2739 if ((set = single_set (XEXP (link, 0))) != 0
2740 && rtx_equal_p (i1dest, SET_DEST (set)))
2741 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2743 record_value_for_reg (i1dest, i1_insn, i1_val);
2745 regno = REGNO (i1dest);
2746 if (! added_sets_1 && ! i1dest_in_i1src)
2747 REG_N_SETS (regno)--;
2750 /* Update reg_nonzero_bits et al for any changes that may have been made
2751 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2752 important. Because newi2pat can affect nonzero_bits of newpat */
2753 if (newi2pat)
2754 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2755 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2757 /* Set new_direct_jump_p if a new return or simple jump instruction
2758 has been created.
2760 If I3 is now an unconditional jump, ensure that it has a
2761 BARRIER following it since it may have initially been a
2762 conditional jump. It may also be the last nonnote insn. */
2764 if (returnjump_p (i3) || any_uncondjump_p (i3))
2766 *new_direct_jump_p = 1;
2768 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2769 || GET_CODE (temp) != BARRIER)
2770 emit_barrier_after (i3);
2773 if (undobuf.other_insn != NULL_RTX
2774 && (returnjump_p (undobuf.other_insn)
2775 || any_uncondjump_p (undobuf.other_insn)))
2777 *new_direct_jump_p = 1;
2779 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2780 || GET_CODE (temp) != BARRIER)
2781 emit_barrier_after (undobuf.other_insn);
2784 /* An NOOP jump does not need barrier, but it does need cleaning up
2785 of CFG. */
2786 if (GET_CODE (newpat) == SET
2787 && SET_SRC (newpat) == pc_rtx
2788 && SET_DEST (newpat) == pc_rtx)
2789 *new_direct_jump_p = 1;
2792 combine_successes++;
2793 undo_commit ();
2795 if (added_links_insn
2796 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2797 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2798 return added_links_insn;
2799 else
2800 return newi2pat ? i2 : i3;
2803 /* Undo all the modifications recorded in undobuf. */
2805 static void
2806 undo_all (void)
2808 struct undo *undo, *next;
2810 for (undo = undobuf.undos; undo; undo = next)
2812 next = undo->next;
2813 if (undo->is_int)
2814 *undo->where.i = undo->old_contents.i;
2815 else
2816 *undo->where.r = undo->old_contents.r;
2818 undo->next = undobuf.frees;
2819 undobuf.frees = undo;
2822 undobuf.undos = 0;
2825 /* We've committed to accepting the changes we made. Move all
2826 of the undos to the free list. */
2828 static void
2829 undo_commit (void)
2831 struct undo *undo, *next;
2833 for (undo = undobuf.undos; undo; undo = next)
2835 next = undo->next;
2836 undo->next = undobuf.frees;
2837 undobuf.frees = undo;
2839 undobuf.undos = 0;
2843 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2844 where we have an arithmetic expression and return that point. LOC will
2845 be inside INSN.
2847 try_combine will call this function to see if an insn can be split into
2848 two insns. */
2850 static rtx *
2851 find_split_point (rtx *loc, rtx insn)
2853 rtx x = *loc;
2854 enum rtx_code code = GET_CODE (x);
2855 rtx *split;
2856 unsigned HOST_WIDE_INT len = 0;
2857 HOST_WIDE_INT pos = 0;
2858 int unsignedp = 0;
2859 rtx inner = NULL_RTX;
2861 /* First special-case some codes. */
2862 switch (code)
2864 case SUBREG:
2865 #ifdef INSN_SCHEDULING
2866 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2867 point. */
2868 if (GET_CODE (SUBREG_REG (x)) == MEM)
2869 return loc;
2870 #endif
2871 return find_split_point (&SUBREG_REG (x), insn);
2873 case MEM:
2874 #ifdef HAVE_lo_sum
2875 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2876 using LO_SUM and HIGH. */
2877 if (GET_CODE (XEXP (x, 0)) == CONST
2878 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2880 SUBST (XEXP (x, 0),
2881 gen_rtx_LO_SUM (Pmode,
2882 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2883 XEXP (x, 0)));
2884 return &XEXP (XEXP (x, 0), 0);
2886 #endif
2888 /* If we have a PLUS whose second operand is a constant and the
2889 address is not valid, perhaps will can split it up using
2890 the machine-specific way to split large constants. We use
2891 the first pseudo-reg (one of the virtual regs) as a placeholder;
2892 it will not remain in the result. */
2893 if (GET_CODE (XEXP (x, 0)) == PLUS
2894 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2895 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2897 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2898 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2899 subst_insn);
2901 /* This should have produced two insns, each of which sets our
2902 placeholder. If the source of the second is a valid address,
2903 we can make put both sources together and make a split point
2904 in the middle. */
2906 if (seq
2907 && NEXT_INSN (seq) != NULL_RTX
2908 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2909 && GET_CODE (seq) == INSN
2910 && GET_CODE (PATTERN (seq)) == SET
2911 && SET_DEST (PATTERN (seq)) == reg
2912 && ! reg_mentioned_p (reg,
2913 SET_SRC (PATTERN (seq)))
2914 && GET_CODE (NEXT_INSN (seq)) == INSN
2915 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2916 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2917 && memory_address_p (GET_MODE (x),
2918 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2920 rtx src1 = SET_SRC (PATTERN (seq));
2921 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2923 /* Replace the placeholder in SRC2 with SRC1. If we can
2924 find where in SRC2 it was placed, that can become our
2925 split point and we can replace this address with SRC2.
2926 Just try two obvious places. */
2928 src2 = replace_rtx (src2, reg, src1);
2929 split = 0;
2930 if (XEXP (src2, 0) == src1)
2931 split = &XEXP (src2, 0);
2932 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2933 && XEXP (XEXP (src2, 0), 0) == src1)
2934 split = &XEXP (XEXP (src2, 0), 0);
2936 if (split)
2938 SUBST (XEXP (x, 0), src2);
2939 return split;
2943 /* If that didn't work, perhaps the first operand is complex and
2944 needs to be computed separately, so make a split point there.
2945 This will occur on machines that just support REG + CONST
2946 and have a constant moved through some previous computation. */
2948 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2949 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2950 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2951 == 'o')))
2952 return &XEXP (XEXP (x, 0), 0);
2954 break;
2956 case SET:
2957 #ifdef HAVE_cc0
2958 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2959 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2960 we need to put the operand into a register. So split at that
2961 point. */
2963 if (SET_DEST (x) == cc0_rtx
2964 && GET_CODE (SET_SRC (x)) != COMPARE
2965 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2966 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2967 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2968 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2969 return &SET_SRC (x);
2970 #endif
2972 /* See if we can split SET_SRC as it stands. */
2973 split = find_split_point (&SET_SRC (x), insn);
2974 if (split && split != &SET_SRC (x))
2975 return split;
2977 /* See if we can split SET_DEST as it stands. */
2978 split = find_split_point (&SET_DEST (x), insn);
2979 if (split && split != &SET_DEST (x))
2980 return split;
2982 /* See if this is a bitfield assignment with everything constant. If
2983 so, this is an IOR of an AND, so split it into that. */
2984 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2985 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2986 <= HOST_BITS_PER_WIDE_INT)
2987 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2988 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2989 && GET_CODE (SET_SRC (x)) == CONST_INT
2990 && ((INTVAL (XEXP (SET_DEST (x), 1))
2991 + INTVAL (XEXP (SET_DEST (x), 2)))
2992 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2993 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2995 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2996 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2997 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2998 rtx dest = XEXP (SET_DEST (x), 0);
2999 enum machine_mode mode = GET_MODE (dest);
3000 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3002 if (BITS_BIG_ENDIAN)
3003 pos = GET_MODE_BITSIZE (mode) - len - pos;
3005 if (src == mask)
3006 SUBST (SET_SRC (x),
3007 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3008 else
3009 SUBST (SET_SRC (x),
3010 gen_binary (IOR, mode,
3011 gen_binary (AND, mode, dest,
3012 gen_int_mode (~(mask << pos),
3013 mode)),
3014 GEN_INT (src << pos)));
3016 SUBST (SET_DEST (x), dest);
3018 split = find_split_point (&SET_SRC (x), insn);
3019 if (split && split != &SET_SRC (x))
3020 return split;
3023 /* Otherwise, see if this is an operation that we can split into two.
3024 If so, try to split that. */
3025 code = GET_CODE (SET_SRC (x));
3027 switch (code)
3029 case AND:
3030 /* If we are AND'ing with a large constant that is only a single
3031 bit and the result is only being used in a context where we
3032 need to know if it is zero or nonzero, replace it with a bit
3033 extraction. This will avoid the large constant, which might
3034 have taken more than one insn to make. If the constant were
3035 not a valid argument to the AND but took only one insn to make,
3036 this is no worse, but if it took more than one insn, it will
3037 be better. */
3039 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3040 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3041 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3042 && GET_CODE (SET_DEST (x)) == REG
3043 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3044 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3045 && XEXP (*split, 0) == SET_DEST (x)
3046 && XEXP (*split, 1) == const0_rtx)
3048 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3049 XEXP (SET_SRC (x), 0),
3050 pos, NULL_RTX, 1, 1, 0, 0);
3051 if (extraction != 0)
3053 SUBST (SET_SRC (x), extraction);
3054 return find_split_point (loc, insn);
3057 break;
3059 case NE:
3060 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3061 is known to be on, this can be converted into a NEG of a shift. */
3062 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3063 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3064 && 1 <= (pos = exact_log2
3065 (nonzero_bits (XEXP (SET_SRC (x), 0),
3066 GET_MODE (XEXP (SET_SRC (x), 0))))))
3068 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3070 SUBST (SET_SRC (x),
3071 gen_rtx_NEG (mode,
3072 gen_rtx_LSHIFTRT (mode,
3073 XEXP (SET_SRC (x), 0),
3074 GEN_INT (pos))));
3076 split = find_split_point (&SET_SRC (x), insn);
3077 if (split && split != &SET_SRC (x))
3078 return split;
3080 break;
3082 case SIGN_EXTEND:
3083 inner = XEXP (SET_SRC (x), 0);
3085 /* We can't optimize if either mode is a partial integer
3086 mode as we don't know how many bits are significant
3087 in those modes. */
3088 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3089 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3090 break;
3092 pos = 0;
3093 len = GET_MODE_BITSIZE (GET_MODE (inner));
3094 unsignedp = 0;
3095 break;
3097 case SIGN_EXTRACT:
3098 case ZERO_EXTRACT:
3099 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3100 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3102 inner = XEXP (SET_SRC (x), 0);
3103 len = INTVAL (XEXP (SET_SRC (x), 1));
3104 pos = INTVAL (XEXP (SET_SRC (x), 2));
3106 if (BITS_BIG_ENDIAN)
3107 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3108 unsignedp = (code == ZERO_EXTRACT);
3110 break;
3112 default:
3113 break;
3116 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3118 enum machine_mode mode = GET_MODE (SET_SRC (x));
3120 /* For unsigned, we have a choice of a shift followed by an
3121 AND or two shifts. Use two shifts for field sizes where the
3122 constant might be too large. We assume here that we can
3123 always at least get 8-bit constants in an AND insn, which is
3124 true for every current RISC. */
3126 if (unsignedp && len <= 8)
3128 SUBST (SET_SRC (x),
3129 gen_rtx_AND (mode,
3130 gen_rtx_LSHIFTRT
3131 (mode, gen_lowpart_for_combine (mode, inner),
3132 GEN_INT (pos)),
3133 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3135 split = find_split_point (&SET_SRC (x), insn);
3136 if (split && split != &SET_SRC (x))
3137 return split;
3139 else
3141 SUBST (SET_SRC (x),
3142 gen_rtx_fmt_ee
3143 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3144 gen_rtx_ASHIFT (mode,
3145 gen_lowpart_for_combine (mode, inner),
3146 GEN_INT (GET_MODE_BITSIZE (mode)
3147 - len - pos)),
3148 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3150 split = find_split_point (&SET_SRC (x), insn);
3151 if (split && split != &SET_SRC (x))
3152 return split;
3156 /* See if this is a simple operation with a constant as the second
3157 operand. It might be that this constant is out of range and hence
3158 could be used as a split point. */
3159 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3160 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3161 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3162 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3163 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3164 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3165 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3166 == 'o'))))
3167 return &XEXP (SET_SRC (x), 1);
3169 /* Finally, see if this is a simple operation with its first operand
3170 not in a register. The operation might require this operand in a
3171 register, so return it as a split point. We can always do this
3172 because if the first operand were another operation, we would have
3173 already found it as a split point. */
3174 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3175 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3176 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3177 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3178 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3179 return &XEXP (SET_SRC (x), 0);
3181 return 0;
3183 case AND:
3184 case IOR:
3185 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3186 it is better to write this as (not (ior A B)) so we can split it.
3187 Similarly for IOR. */
3188 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3190 SUBST (*loc,
3191 gen_rtx_NOT (GET_MODE (x),
3192 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3193 GET_MODE (x),
3194 XEXP (XEXP (x, 0), 0),
3195 XEXP (XEXP (x, 1), 0))));
3196 return find_split_point (loc, insn);
3199 /* Many RISC machines have a large set of logical insns. If the
3200 second operand is a NOT, put it first so we will try to split the
3201 other operand first. */
3202 if (GET_CODE (XEXP (x, 1)) == NOT)
3204 rtx tem = XEXP (x, 0);
3205 SUBST (XEXP (x, 0), XEXP (x, 1));
3206 SUBST (XEXP (x, 1), tem);
3208 break;
3210 default:
3211 break;
3214 /* Otherwise, select our actions depending on our rtx class. */
3215 switch (GET_RTX_CLASS (code))
3217 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3218 case '3':
3219 split = find_split_point (&XEXP (x, 2), insn);
3220 if (split)
3221 return split;
3222 /* ... fall through ... */
3223 case '2':
3224 case 'c':
3225 case '<':
3226 split = find_split_point (&XEXP (x, 1), insn);
3227 if (split)
3228 return split;
3229 /* ... fall through ... */
3230 case '1':
3231 /* Some machines have (and (shift ...) ...) insns. If X is not
3232 an AND, but XEXP (X, 0) is, use it as our split point. */
3233 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3234 return &XEXP (x, 0);
3236 split = find_split_point (&XEXP (x, 0), insn);
3237 if (split)
3238 return split;
3239 return loc;
3242 /* Otherwise, we don't have a split point. */
3243 return 0;
3246 /* Throughout X, replace FROM with TO, and return the result.
3247 The result is TO if X is FROM;
3248 otherwise the result is X, but its contents may have been modified.
3249 If they were modified, a record was made in undobuf so that
3250 undo_all will (among other things) return X to its original state.
3252 If the number of changes necessary is too much to record to undo,
3253 the excess changes are not made, so the result is invalid.
3254 The changes already made can still be undone.
3255 undobuf.num_undo is incremented for such changes, so by testing that
3256 the caller can tell whether the result is valid.
3258 `n_occurrences' is incremented each time FROM is replaced.
3260 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3262 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3263 by copying if `n_occurrences' is nonzero. */
3265 static rtx
3266 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3268 enum rtx_code code = GET_CODE (x);
3269 enum machine_mode op0_mode = VOIDmode;
3270 const char *fmt;
3271 int len, i;
3272 rtx new;
3274 /* Two expressions are equal if they are identical copies of a shared
3275 RTX or if they are both registers with the same register number
3276 and mode. */
3278 #define COMBINE_RTX_EQUAL_P(X,Y) \
3279 ((X) == (Y) \
3280 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3281 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3283 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3285 n_occurrences++;
3286 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3289 /* If X and FROM are the same register but different modes, they will
3290 not have been seen as equal above. However, flow.c will make a
3291 LOG_LINKS entry for that case. If we do nothing, we will try to
3292 rerecognize our original insn and, when it succeeds, we will
3293 delete the feeding insn, which is incorrect.
3295 So force this insn not to match in this (rare) case. */
3296 if (! in_dest && code == REG && GET_CODE (from) == REG
3297 && REGNO (x) == REGNO (from))
3298 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3300 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3301 of which may contain things that can be combined. */
3302 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3303 return x;
3305 /* It is possible to have a subexpression appear twice in the insn.
3306 Suppose that FROM is a register that appears within TO.
3307 Then, after that subexpression has been scanned once by `subst',
3308 the second time it is scanned, TO may be found. If we were
3309 to scan TO here, we would find FROM within it and create a
3310 self-referent rtl structure which is completely wrong. */
3311 if (COMBINE_RTX_EQUAL_P (x, to))
3312 return to;
3314 /* Parallel asm_operands need special attention because all of the
3315 inputs are shared across the arms. Furthermore, unsharing the
3316 rtl results in recognition failures. Failure to handle this case
3317 specially can result in circular rtl.
3319 Solve this by doing a normal pass across the first entry of the
3320 parallel, and only processing the SET_DESTs of the subsequent
3321 entries. Ug. */
3323 if (code == PARALLEL
3324 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3325 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3327 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3329 /* If this substitution failed, this whole thing fails. */
3330 if (GET_CODE (new) == CLOBBER
3331 && XEXP (new, 0) == const0_rtx)
3332 return new;
3334 SUBST (XVECEXP (x, 0, 0), new);
3336 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3338 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3340 if (GET_CODE (dest) != REG
3341 && GET_CODE (dest) != CC0
3342 && GET_CODE (dest) != PC)
3344 new = subst (dest, from, to, 0, unique_copy);
3346 /* If this substitution failed, this whole thing fails. */
3347 if (GET_CODE (new) == CLOBBER
3348 && XEXP (new, 0) == const0_rtx)
3349 return new;
3351 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3355 else
3357 len = GET_RTX_LENGTH (code);
3358 fmt = GET_RTX_FORMAT (code);
3360 /* We don't need to process a SET_DEST that is a register, CC0,
3361 or PC, so set up to skip this common case. All other cases
3362 where we want to suppress replacing something inside a
3363 SET_SRC are handled via the IN_DEST operand. */
3364 if (code == SET
3365 && (GET_CODE (SET_DEST (x)) == REG
3366 || GET_CODE (SET_DEST (x)) == CC0
3367 || GET_CODE (SET_DEST (x)) == PC))
3368 fmt = "ie";
3370 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3371 constant. */
3372 if (fmt[0] == 'e')
3373 op0_mode = GET_MODE (XEXP (x, 0));
3375 for (i = 0; i < len; i++)
3377 if (fmt[i] == 'E')
3379 int j;
3380 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3382 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3384 new = (unique_copy && n_occurrences
3385 ? copy_rtx (to) : to);
3386 n_occurrences++;
3388 else
3390 new = subst (XVECEXP (x, i, j), from, to, 0,
3391 unique_copy);
3393 /* If this substitution failed, this whole thing
3394 fails. */
3395 if (GET_CODE (new) == CLOBBER
3396 && XEXP (new, 0) == const0_rtx)
3397 return new;
3400 SUBST (XVECEXP (x, i, j), new);
3403 else if (fmt[i] == 'e')
3405 /* If this is a register being set, ignore it. */
3406 new = XEXP (x, i);
3407 if (in_dest
3408 && (code == SUBREG || code == STRICT_LOW_PART
3409 || code == ZERO_EXTRACT)
3410 && i == 0
3411 && GET_CODE (new) == REG)
3414 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3416 /* In general, don't install a subreg involving two
3417 modes not tieable. It can worsen register
3418 allocation, and can even make invalid reload
3419 insns, since the reg inside may need to be copied
3420 from in the outside mode, and that may be invalid
3421 if it is an fp reg copied in integer mode.
3423 We allow two exceptions to this: It is valid if
3424 it is inside another SUBREG and the mode of that
3425 SUBREG and the mode of the inside of TO is
3426 tieable and it is valid if X is a SET that copies
3427 FROM to CC0. */
3429 if (GET_CODE (to) == SUBREG
3430 && ! MODES_TIEABLE_P (GET_MODE (to),
3431 GET_MODE (SUBREG_REG (to)))
3432 && ! (code == SUBREG
3433 && MODES_TIEABLE_P (GET_MODE (x),
3434 GET_MODE (SUBREG_REG (to))))
3435 #ifdef HAVE_cc0
3436 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3437 #endif
3439 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3441 #ifdef CANNOT_CHANGE_MODE_CLASS
3442 if (code == SUBREG
3443 && GET_CODE (to) == REG
3444 && REGNO (to) < FIRST_PSEUDO_REGISTER
3445 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3446 GET_MODE (to),
3447 GET_MODE (x)))
3448 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3449 #endif
3451 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3452 n_occurrences++;
3454 else
3455 /* If we are in a SET_DEST, suppress most cases unless we
3456 have gone inside a MEM, in which case we want to
3457 simplify the address. We assume here that things that
3458 are actually part of the destination have their inner
3459 parts in the first expression. This is true for SUBREG,
3460 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3461 things aside from REG and MEM that should appear in a
3462 SET_DEST. */
3463 new = subst (XEXP (x, i), from, to,
3464 (((in_dest
3465 && (code == SUBREG || code == STRICT_LOW_PART
3466 || code == ZERO_EXTRACT))
3467 || code == SET)
3468 && i == 0), unique_copy);
3470 /* If we found that we will have to reject this combination,
3471 indicate that by returning the CLOBBER ourselves, rather than
3472 an expression containing it. This will speed things up as
3473 well as prevent accidents where two CLOBBERs are considered
3474 to be equal, thus producing an incorrect simplification. */
3476 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3477 return new;
3479 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3481 enum machine_mode mode = GET_MODE (x);
3483 x = simplify_subreg (GET_MODE (x), new,
3484 GET_MODE (SUBREG_REG (x)),
3485 SUBREG_BYTE (x));
3486 if (! x)
3487 x = gen_rtx_CLOBBER (mode, const0_rtx);
3489 else if (GET_CODE (new) == CONST_INT
3490 && GET_CODE (x) == ZERO_EXTEND)
3492 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3493 new, GET_MODE (XEXP (x, 0)));
3494 if (! x)
3495 abort ();
3497 else
3498 SUBST (XEXP (x, i), new);
3503 /* Try to simplify X. If the simplification changed the code, it is likely
3504 that further simplification will help, so loop, but limit the number
3505 of repetitions that will be performed. */
3507 for (i = 0; i < 4; i++)
3509 /* If X is sufficiently simple, don't bother trying to do anything
3510 with it. */
3511 if (code != CONST_INT && code != REG && code != CLOBBER)
3512 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3514 if (GET_CODE (x) == code)
3515 break;
3517 code = GET_CODE (x);
3519 /* We no longer know the original mode of operand 0 since we
3520 have changed the form of X) */
3521 op0_mode = VOIDmode;
3524 return x;
3527 /* Simplify X, a piece of RTL. We just operate on the expression at the
3528 outer level; call `subst' to simplify recursively. Return the new
3529 expression.
3531 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3532 will be the iteration even if an expression with a code different from
3533 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3535 static rtx
3536 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int last,
3537 int in_dest)
3539 enum rtx_code code = GET_CODE (x);
3540 enum machine_mode mode = GET_MODE (x);
3541 rtx temp;
3542 rtx reversed;
3543 int i;
3545 /* If this is a commutative operation, put a constant last and a complex
3546 expression first. We don't need to do this for comparisons here. */
3547 if (GET_RTX_CLASS (code) == 'c'
3548 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3550 temp = XEXP (x, 0);
3551 SUBST (XEXP (x, 0), XEXP (x, 1));
3552 SUBST (XEXP (x, 1), temp);
3555 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3556 sign extension of a PLUS with a constant, reverse the order of the sign
3557 extension and the addition. Note that this not the same as the original
3558 code, but overflow is undefined for signed values. Also note that the
3559 PLUS will have been partially moved "inside" the sign-extension, so that
3560 the first operand of X will really look like:
3561 (ashiftrt (plus (ashift A C4) C5) C4).
3562 We convert this to
3563 (plus (ashiftrt (ashift A C4) C2) C4)
3564 and replace the first operand of X with that expression. Later parts
3565 of this function may simplify the expression further.
3567 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3568 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3569 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3571 We do this to simplify address expressions. */
3573 if ((code == PLUS || code == MINUS || code == MULT)
3574 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3575 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3576 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3577 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3578 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3579 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3580 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3581 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3582 XEXP (XEXP (XEXP (x, 0), 0), 1),
3583 XEXP (XEXP (x, 0), 1))) != 0)
3585 rtx new
3586 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3587 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3588 INTVAL (XEXP (XEXP (x, 0), 1)));
3590 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3591 INTVAL (XEXP (XEXP (x, 0), 1)));
3593 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3596 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3597 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3598 things. Check for cases where both arms are testing the same
3599 condition.
3601 Don't do anything if all operands are very simple. */
3603 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3604 || GET_RTX_CLASS (code) == '<')
3605 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3606 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3607 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3608 == 'o')))
3609 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3610 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3611 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3612 == 'o')))))
3613 || (GET_RTX_CLASS (code) == '1'
3614 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3615 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3616 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3617 == 'o'))))))
3619 rtx cond, true_rtx, false_rtx;
3621 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3622 if (cond != 0
3623 /* If everything is a comparison, what we have is highly unlikely
3624 to be simpler, so don't use it. */
3625 && ! (GET_RTX_CLASS (code) == '<'
3626 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3627 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3629 rtx cop1 = const0_rtx;
3630 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3632 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3633 return x;
3635 /* Simplify the alternative arms; this may collapse the true and
3636 false arms to store-flag values. */
3637 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3638 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3640 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3641 is unlikely to be simpler. */
3642 if (general_operand (true_rtx, VOIDmode)
3643 && general_operand (false_rtx, VOIDmode))
3645 enum rtx_code reversed;
3647 /* Restarting if we generate a store-flag expression will cause
3648 us to loop. Just drop through in this case. */
3650 /* If the result values are STORE_FLAG_VALUE and zero, we can
3651 just make the comparison operation. */
3652 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3653 x = gen_binary (cond_code, mode, cond, cop1);
3654 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3655 && ((reversed = reversed_comparison_code_parts
3656 (cond_code, cond, cop1, NULL))
3657 != UNKNOWN))
3658 x = gen_binary (reversed, mode, cond, cop1);
3660 /* Likewise, we can make the negate of a comparison operation
3661 if the result values are - STORE_FLAG_VALUE and zero. */
3662 else if (GET_CODE (true_rtx) == CONST_INT
3663 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3664 && false_rtx == const0_rtx)
3665 x = simplify_gen_unary (NEG, mode,
3666 gen_binary (cond_code, mode, cond,
3667 cop1),
3668 mode);
3669 else if (GET_CODE (false_rtx) == CONST_INT
3670 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3671 && true_rtx == const0_rtx
3672 && ((reversed = reversed_comparison_code_parts
3673 (cond_code, cond, cop1, NULL))
3674 != UNKNOWN))
3675 x = simplify_gen_unary (NEG, mode,
3676 gen_binary (reversed, mode,
3677 cond, cop1),
3678 mode);
3679 else
3680 return gen_rtx_IF_THEN_ELSE (mode,
3681 gen_binary (cond_code, VOIDmode,
3682 cond, cop1),
3683 true_rtx, false_rtx);
3685 code = GET_CODE (x);
3686 op0_mode = VOIDmode;
3691 /* Try to fold this expression in case we have constants that weren't
3692 present before. */
3693 temp = 0;
3694 switch (GET_RTX_CLASS (code))
3696 case '1':
3697 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3698 break;
3699 case '<':
3701 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3702 if (cmp_mode == VOIDmode)
3704 cmp_mode = GET_MODE (XEXP (x, 1));
3705 if (cmp_mode == VOIDmode)
3706 cmp_mode = op0_mode;
3708 temp = simplify_relational_operation (code, cmp_mode,
3709 XEXP (x, 0), XEXP (x, 1));
3711 #ifdef FLOAT_STORE_FLAG_VALUE
3712 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3714 if (temp == const0_rtx)
3715 temp = CONST0_RTX (mode);
3716 else
3717 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3718 mode);
3720 #endif
3721 break;
3722 case 'c':
3723 case '2':
3724 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3725 break;
3726 case 'b':
3727 case '3':
3728 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3729 XEXP (x, 1), XEXP (x, 2));
3730 break;
3733 if (temp)
3735 x = temp;
3736 code = GET_CODE (temp);
3737 op0_mode = VOIDmode;
3738 mode = GET_MODE (temp);
3741 /* First see if we can apply the inverse distributive law. */
3742 if (code == PLUS || code == MINUS
3743 || code == AND || code == IOR || code == XOR)
3745 x = apply_distributive_law (x);
3746 code = GET_CODE (x);
3747 op0_mode = VOIDmode;
3750 /* If CODE is an associative operation not otherwise handled, see if we
3751 can associate some operands. This can win if they are constants or
3752 if they are logically related (i.e. (a & b) & a). */
3753 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3754 || code == AND || code == IOR || code == XOR
3755 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3756 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3757 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3759 if (GET_CODE (XEXP (x, 0)) == code)
3761 rtx other = XEXP (XEXP (x, 0), 0);
3762 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3763 rtx inner_op1 = XEXP (x, 1);
3764 rtx inner;
3766 /* Make sure we pass the constant operand if any as the second
3767 one if this is a commutative operation. */
3768 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3770 rtx tem = inner_op0;
3771 inner_op0 = inner_op1;
3772 inner_op1 = tem;
3774 inner = simplify_binary_operation (code == MINUS ? PLUS
3775 : code == DIV ? MULT
3776 : code,
3777 mode, inner_op0, inner_op1);
3779 /* For commutative operations, try the other pair if that one
3780 didn't simplify. */
3781 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3783 other = XEXP (XEXP (x, 0), 1);
3784 inner = simplify_binary_operation (code, mode,
3785 XEXP (XEXP (x, 0), 0),
3786 XEXP (x, 1));
3789 if (inner)
3790 return gen_binary (code, mode, other, inner);
3794 /* A little bit of algebraic simplification here. */
3795 switch (code)
3797 case MEM:
3798 /* Ensure that our address has any ASHIFTs converted to MULT in case
3799 address-recognizing predicates are called later. */
3800 temp = make_compound_operation (XEXP (x, 0), MEM);
3801 SUBST (XEXP (x, 0), temp);
3802 break;
3804 case SUBREG:
3805 if (op0_mode == VOIDmode)
3806 op0_mode = GET_MODE (SUBREG_REG (x));
3808 /* simplify_subreg can't use gen_lowpart_for_combine. */
3809 if (CONSTANT_P (SUBREG_REG (x))
3810 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3811 /* Don't call gen_lowpart_for_combine if the inner mode
3812 is VOIDmode and we cannot simplify it, as SUBREG without
3813 inner mode is invalid. */
3814 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3815 || gen_lowpart_common (mode, SUBREG_REG (x))))
3816 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3818 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3819 break;
3821 rtx temp;
3822 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3823 SUBREG_BYTE (x));
3824 if (temp)
3825 return temp;
3828 /* Don't change the mode of the MEM if that would change the meaning
3829 of the address. */
3830 if (GET_CODE (SUBREG_REG (x)) == MEM
3831 && (MEM_VOLATILE_P (SUBREG_REG (x))
3832 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3833 return gen_rtx_CLOBBER (mode, const0_rtx);
3835 /* Note that we cannot do any narrowing for non-constants since
3836 we might have been counting on using the fact that some bits were
3837 zero. We now do this in the SET. */
3839 break;
3841 case NOT:
3842 /* (not (plus X -1)) can become (neg X). */
3843 if (GET_CODE (XEXP (x, 0)) == PLUS
3844 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3845 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3847 /* Similarly, (not (neg X)) is (plus X -1). */
3848 if (GET_CODE (XEXP (x, 0)) == NEG)
3849 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3851 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3852 if (GET_CODE (XEXP (x, 0)) == XOR
3853 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3854 && (temp = simplify_unary_operation (NOT, mode,
3855 XEXP (XEXP (x, 0), 1),
3856 mode)) != 0)
3857 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3859 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3860 other than 1, but that is not valid. We could do a similar
3861 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3862 but this doesn't seem common enough to bother with. */
3863 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3864 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3865 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3866 const1_rtx, mode),
3867 XEXP (XEXP (x, 0), 1));
3869 if (GET_CODE (XEXP (x, 0)) == SUBREG
3870 && subreg_lowpart_p (XEXP (x, 0))
3871 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3872 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3873 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3874 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3876 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3878 x = gen_rtx_ROTATE (inner_mode,
3879 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3880 inner_mode),
3881 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3882 return gen_lowpart_for_combine (mode, x);
3885 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3886 reversing the comparison code if valid. */
3887 if (STORE_FLAG_VALUE == -1
3888 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3889 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3890 XEXP (XEXP (x, 0), 1))))
3891 return reversed;
3893 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3894 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3895 perform the above simplification. */
3897 if (STORE_FLAG_VALUE == -1
3898 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3899 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3900 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3901 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3903 /* Apply De Morgan's laws to reduce number of patterns for machines
3904 with negating logical insns (and-not, nand, etc.). If result has
3905 only one NOT, put it first, since that is how the patterns are
3906 coded. */
3908 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3910 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3911 enum machine_mode op_mode;
3913 op_mode = GET_MODE (in1);
3914 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3916 op_mode = GET_MODE (in2);
3917 if (op_mode == VOIDmode)
3918 op_mode = mode;
3919 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3921 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3923 rtx tem = in2;
3924 in2 = in1; in1 = tem;
3927 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3928 mode, in1, in2);
3930 break;
3932 case NEG:
3933 /* (neg (plus X 1)) can become (not X). */
3934 if (GET_CODE (XEXP (x, 0)) == PLUS
3935 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3936 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3938 /* Similarly, (neg (not X)) is (plus X 1). */
3939 if (GET_CODE (XEXP (x, 0)) == NOT)
3940 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3942 /* (neg (minus X Y)) can become (minus Y X). This transformation
3943 isn't safe for modes with signed zeros, since if X and Y are
3944 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3945 mode is towards +infinity (or -infinity) then the two expressions
3946 will be rounded differently. */
3947 if (GET_CODE (XEXP (x, 0)) == MINUS
3948 && !HONOR_SIGNED_ZEROS (mode)
3949 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
3950 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3951 XEXP (XEXP (x, 0), 0));
3953 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
3954 if (GET_CODE (XEXP (x, 0)) == PLUS
3955 && !HONOR_SIGNED_ZEROS (mode)
3956 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
3958 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
3959 temp = combine_simplify_rtx (temp, mode, last, in_dest);
3960 return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
3963 /* (neg (mult A B)) becomes (mult (neg A) B).
3964 This works even for floating-point values. */
3965 if (GET_CODE (XEXP (x, 0)) == MULT)
3967 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
3968 return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
3971 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3972 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3973 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3974 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3976 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3977 if we can then eliminate the NEG (e.g.,
3978 if the operand is a constant). */
3980 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3982 temp = simplify_unary_operation (NEG, mode,
3983 XEXP (XEXP (x, 0), 0), mode);
3984 if (temp)
3985 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
3988 temp = expand_compound_operation (XEXP (x, 0));
3990 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3991 replaced by (lshiftrt X C). This will convert
3992 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3994 if (GET_CODE (temp) == ASHIFTRT
3995 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3996 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3997 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3998 INTVAL (XEXP (temp, 1)));
4000 /* If X has only a single bit that might be nonzero, say, bit I, convert
4001 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4002 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4003 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4004 or a SUBREG of one since we'd be making the expression more
4005 complex if it was just a register. */
4007 if (GET_CODE (temp) != REG
4008 && ! (GET_CODE (temp) == SUBREG
4009 && GET_CODE (SUBREG_REG (temp)) == REG)
4010 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4012 rtx temp1 = simplify_shift_const
4013 (NULL_RTX, ASHIFTRT, mode,
4014 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4015 GET_MODE_BITSIZE (mode) - 1 - i),
4016 GET_MODE_BITSIZE (mode) - 1 - i);
4018 /* If all we did was surround TEMP with the two shifts, we
4019 haven't improved anything, so don't use it. Otherwise,
4020 we are better off with TEMP1. */
4021 if (GET_CODE (temp1) != ASHIFTRT
4022 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4023 || XEXP (XEXP (temp1, 0), 0) != temp)
4024 return temp1;
4026 break;
4028 case TRUNCATE:
4029 /* We can't handle truncation to a partial integer mode here
4030 because we don't know the real bitsize of the partial
4031 integer mode. */
4032 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4033 break;
4035 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4036 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4037 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4038 SUBST (XEXP (x, 0),
4039 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4040 GET_MODE_MASK (mode), NULL_RTX, 0));
4042 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4043 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4044 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4045 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4046 return XEXP (XEXP (x, 0), 0);
4048 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4049 (OP:SI foo:SI) if OP is NEG or ABS. */
4050 if ((GET_CODE (XEXP (x, 0)) == ABS
4051 || GET_CODE (XEXP (x, 0)) == NEG)
4052 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4053 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4054 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4055 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4056 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4058 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4059 (truncate:SI x). */
4060 if (GET_CODE (XEXP (x, 0)) == SUBREG
4061 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4062 && subreg_lowpart_p (XEXP (x, 0)))
4063 return SUBREG_REG (XEXP (x, 0));
4065 /* If we know that the value is already truncated, we can
4066 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4067 is nonzero for the corresponding modes. But don't do this
4068 for an (LSHIFTRT (MULT ...)) since this will cause problems
4069 with the umulXi3_highpart patterns. */
4070 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4071 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4072 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4073 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4074 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4075 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4076 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4078 /* A truncate of a comparison can be replaced with a subreg if
4079 STORE_FLAG_VALUE permits. This is like the previous test,
4080 but it works even if the comparison is done in a mode larger
4081 than HOST_BITS_PER_WIDE_INT. */
4082 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4083 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4084 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4085 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4087 /* Similarly, a truncate of a register whose value is a
4088 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4089 permits. */
4090 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4091 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4092 && (temp = get_last_value (XEXP (x, 0)))
4093 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4094 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4096 break;
4098 case FLOAT_TRUNCATE:
4099 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4100 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4101 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4102 return XEXP (XEXP (x, 0), 0);
4104 /* (float_truncate:SF (float_truncate:DF foo:XF))
4105 = (float_truncate:SF foo:XF).
4106 This may elliminate double rounding, so it is unsafe.
4108 (float_truncate:SF (float_extend:XF foo:DF))
4109 = (float_truncate:SF foo:DF).
4111 (float_truncate:DF (float_extend:XF foo:SF))
4112 = (float_extend:SF foo:DF). */
4113 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4114 && flag_unsafe_math_optimizations)
4115 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4116 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4117 0)))
4118 > GET_MODE_SIZE (mode)
4119 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4120 mode,
4121 XEXP (XEXP (x, 0), 0), mode);
4123 /* (float_truncate (float x)) is (float x) */
4124 if (GET_CODE (XEXP (x, 0)) == FLOAT
4125 && (flag_unsafe_math_optimizations
4126 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4127 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4128 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4129 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4130 return simplify_gen_unary (FLOAT, mode,
4131 XEXP (XEXP (x, 0), 0),
4132 GET_MODE (XEXP (XEXP (x, 0), 0)));
4134 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4135 (OP:SF foo:SF) if OP is NEG or ABS. */
4136 if ((GET_CODE (XEXP (x, 0)) == ABS
4137 || GET_CODE (XEXP (x, 0)) == NEG)
4138 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4139 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4140 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4141 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4143 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4144 is (float_truncate:SF x). */
4145 if (GET_CODE (XEXP (x, 0)) == SUBREG
4146 && subreg_lowpart_p (XEXP (x, 0))
4147 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4148 return SUBREG_REG (XEXP (x, 0));
4149 break;
4150 case FLOAT_EXTEND:
4151 /* (float_extend (float_extend x)) is (float_extend x)
4153 (float_extend (float x)) is (float x) assuming that double
4154 rounding can't happen.
4156 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4157 || (GET_CODE (XEXP (x, 0)) == FLOAT
4158 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4159 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4160 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4161 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4162 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4163 XEXP (XEXP (x, 0), 0),
4164 GET_MODE (XEXP (XEXP (x, 0), 0)));
4166 break;
4167 #ifdef HAVE_cc0
4168 case COMPARE:
4169 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4170 using cc0, in which case we want to leave it as a COMPARE
4171 so we can distinguish it from a register-register-copy. */
4172 if (XEXP (x, 1) == const0_rtx)
4173 return XEXP (x, 0);
4175 /* x - 0 is the same as x unless x's mode has signed zeros and
4176 allows rounding towards -infinity. Under those conditions,
4177 0 - 0 is -0. */
4178 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4179 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4180 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4181 return XEXP (x, 0);
4182 break;
4183 #endif
4185 case CONST:
4186 /* (const (const X)) can become (const X). Do it this way rather than
4187 returning the inner CONST since CONST can be shared with a
4188 REG_EQUAL note. */
4189 if (GET_CODE (XEXP (x, 0)) == CONST)
4190 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4191 break;
4193 #ifdef HAVE_lo_sum
4194 case LO_SUM:
4195 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4196 can add in an offset. find_split_point will split this address up
4197 again if it doesn't match. */
4198 if (GET_CODE (XEXP (x, 0)) == HIGH
4199 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4200 return XEXP (x, 1);
4201 break;
4202 #endif
4204 case PLUS:
4205 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4207 if (GET_CODE (XEXP (x, 0)) == MULT
4208 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4210 rtx in1, in2;
4212 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4213 in2 = XEXP (XEXP (x, 0), 1);
4214 return gen_binary (MINUS, mode, XEXP (x, 1),
4215 gen_binary (MULT, mode, in1, in2));
4218 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4219 outermost. That's because that's the way indexed addresses are
4220 supposed to appear. This code used to check many more cases, but
4221 they are now checked elsewhere. */
4222 if (GET_CODE (XEXP (x, 0)) == PLUS
4223 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4224 return gen_binary (PLUS, mode,
4225 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4226 XEXP (x, 1)),
4227 XEXP (XEXP (x, 0), 1));
4229 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4230 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4231 bit-field and can be replaced by either a sign_extend or a
4232 sign_extract. The `and' may be a zero_extend and the two
4233 <c>, -<c> constants may be reversed. */
4234 if (GET_CODE (XEXP (x, 0)) == XOR
4235 && GET_CODE (XEXP (x, 1)) == CONST_INT
4236 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4237 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4238 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4239 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4240 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4241 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4242 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4243 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4244 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4245 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4246 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4247 == (unsigned int) i + 1))))
4248 return simplify_shift_const
4249 (NULL_RTX, ASHIFTRT, mode,
4250 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4251 XEXP (XEXP (XEXP (x, 0), 0), 0),
4252 GET_MODE_BITSIZE (mode) - (i + 1)),
4253 GET_MODE_BITSIZE (mode) - (i + 1));
4255 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4256 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4257 is 1. This produces better code than the alternative immediately
4258 below. */
4259 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4260 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4261 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4262 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4263 XEXP (XEXP (x, 0), 0),
4264 XEXP (XEXP (x, 0), 1))))
4265 return
4266 simplify_gen_unary (NEG, mode, reversed, mode);
4268 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4269 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4270 the bitsize of the mode - 1. This allows simplification of
4271 "a = (b & 8) == 0;" */
4272 if (XEXP (x, 1) == constm1_rtx
4273 && GET_CODE (XEXP (x, 0)) != REG
4274 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4275 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4276 && nonzero_bits (XEXP (x, 0), mode) == 1)
4277 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4278 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4279 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4280 GET_MODE_BITSIZE (mode) - 1),
4281 GET_MODE_BITSIZE (mode) - 1);
4283 /* If we are adding two things that have no bits in common, convert
4284 the addition into an IOR. This will often be further simplified,
4285 for example in cases like ((a & 1) + (a & 2)), which can
4286 become a & 3. */
4288 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4289 && (nonzero_bits (XEXP (x, 0), mode)
4290 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4292 /* Try to simplify the expression further. */
4293 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4294 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4296 /* If we could, great. If not, do not go ahead with the IOR
4297 replacement, since PLUS appears in many special purpose
4298 address arithmetic instructions. */
4299 if (GET_CODE (temp) != CLOBBER && temp != tor)
4300 return temp;
4302 break;
4304 case MINUS:
4305 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4306 by reversing the comparison code if valid. */
4307 if (STORE_FLAG_VALUE == 1
4308 && XEXP (x, 0) == const1_rtx
4309 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4310 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4311 XEXP (XEXP (x, 1), 0),
4312 XEXP (XEXP (x, 1), 1))))
4313 return reversed;
4315 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4316 (and <foo> (const_int pow2-1)) */
4317 if (GET_CODE (XEXP (x, 1)) == AND
4318 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4319 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4320 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4321 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4322 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4324 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4326 if (GET_CODE (XEXP (x, 1)) == MULT
4327 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4329 rtx in1, in2;
4331 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4332 in2 = XEXP (XEXP (x, 1), 1);
4333 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4334 XEXP (x, 0));
4337 /* Canonicalize (minus (neg A) (mult B C)) to
4338 (minus (mult (neg B) C) A). */
4339 if (GET_CODE (XEXP (x, 1)) == MULT
4340 && GET_CODE (XEXP (x, 0)) == NEG)
4342 rtx in1, in2;
4344 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4345 in2 = XEXP (XEXP (x, 1), 1);
4346 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4347 XEXP (XEXP (x, 0), 0));
4350 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4351 integers. */
4352 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4353 return gen_binary (MINUS, mode,
4354 gen_binary (MINUS, mode, XEXP (x, 0),
4355 XEXP (XEXP (x, 1), 0)),
4356 XEXP (XEXP (x, 1), 1));
4357 break;
4359 case MULT:
4360 /* If we have (mult (plus A B) C), apply the distributive law and then
4361 the inverse distributive law to see if things simplify. This
4362 occurs mostly in addresses, often when unrolling loops. */
4364 if (GET_CODE (XEXP (x, 0)) == PLUS)
4366 x = apply_distributive_law
4367 (gen_binary (PLUS, mode,
4368 gen_binary (MULT, mode,
4369 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4370 gen_binary (MULT, mode,
4371 XEXP (XEXP (x, 0), 1),
4372 copy_rtx (XEXP (x, 1)))));
4374 if (GET_CODE (x) != MULT)
4375 return x;
4377 /* Try simplify a*(b/c) as (a*b)/c. */
4378 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4379 && GET_CODE (XEXP (x, 0)) == DIV)
4381 rtx tem = simplify_binary_operation (MULT, mode,
4382 XEXP (XEXP (x, 0), 0),
4383 XEXP (x, 1));
4384 if (tem)
4385 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4387 break;
4389 case UDIV:
4390 /* If this is a divide by a power of two, treat it as a shift if
4391 its first operand is a shift. */
4392 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4393 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4394 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4395 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4396 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4397 || GET_CODE (XEXP (x, 0)) == ROTATE
4398 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4399 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4400 break;
4402 case EQ: case NE:
4403 case GT: case GTU: case GE: case GEU:
4404 case LT: case LTU: case LE: case LEU:
4405 case UNEQ: case LTGT:
4406 case UNGT: case UNGE:
4407 case UNLT: case UNLE:
4408 case UNORDERED: case ORDERED:
4409 /* If the first operand is a condition code, we can't do anything
4410 with it. */
4411 if (GET_CODE (XEXP (x, 0)) == COMPARE
4412 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4413 && ! CC0_P (XEXP (x, 0))))
4415 rtx op0 = XEXP (x, 0);
4416 rtx op1 = XEXP (x, 1);
4417 enum rtx_code new_code;
4419 if (GET_CODE (op0) == COMPARE)
4420 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4422 /* Simplify our comparison, if possible. */
4423 new_code = simplify_comparison (code, &op0, &op1);
4425 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4426 if only the low-order bit is possibly nonzero in X (such as when
4427 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4428 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4429 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4430 (plus X 1).
4432 Remove any ZERO_EXTRACT we made when thinking this was a
4433 comparison. It may now be simpler to use, e.g., an AND. If a
4434 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4435 the call to make_compound_operation in the SET case. */
4437 if (STORE_FLAG_VALUE == 1
4438 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4439 && op1 == const0_rtx
4440 && mode == GET_MODE (op0)
4441 && nonzero_bits (op0, mode) == 1)
4442 return gen_lowpart_for_combine (mode,
4443 expand_compound_operation (op0));
4445 else if (STORE_FLAG_VALUE == 1
4446 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4447 && op1 == const0_rtx
4448 && mode == GET_MODE (op0)
4449 && (num_sign_bit_copies (op0, mode)
4450 == GET_MODE_BITSIZE (mode)))
4452 op0 = expand_compound_operation (op0);
4453 return simplify_gen_unary (NEG, mode,
4454 gen_lowpart_for_combine (mode, op0),
4455 mode);
4458 else if (STORE_FLAG_VALUE == 1
4459 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4460 && op1 == const0_rtx
4461 && mode == GET_MODE (op0)
4462 && nonzero_bits (op0, mode) == 1)
4464 op0 = expand_compound_operation (op0);
4465 return gen_binary (XOR, mode,
4466 gen_lowpart_for_combine (mode, op0),
4467 const1_rtx);
4470 else if (STORE_FLAG_VALUE == 1
4471 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4472 && op1 == const0_rtx
4473 && mode == GET_MODE (op0)
4474 && (num_sign_bit_copies (op0, mode)
4475 == GET_MODE_BITSIZE (mode)))
4477 op0 = expand_compound_operation (op0);
4478 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4481 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4482 those above. */
4483 if (STORE_FLAG_VALUE == -1
4484 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4485 && op1 == const0_rtx
4486 && (num_sign_bit_copies (op0, mode)
4487 == GET_MODE_BITSIZE (mode)))
4488 return gen_lowpart_for_combine (mode,
4489 expand_compound_operation (op0));
4491 else if (STORE_FLAG_VALUE == -1
4492 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4493 && op1 == const0_rtx
4494 && mode == GET_MODE (op0)
4495 && nonzero_bits (op0, mode) == 1)
4497 op0 = expand_compound_operation (op0);
4498 return simplify_gen_unary (NEG, mode,
4499 gen_lowpart_for_combine (mode, op0),
4500 mode);
4503 else if (STORE_FLAG_VALUE == -1
4504 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4505 && op1 == const0_rtx
4506 && mode == GET_MODE (op0)
4507 && (num_sign_bit_copies (op0, mode)
4508 == GET_MODE_BITSIZE (mode)))
4510 op0 = expand_compound_operation (op0);
4511 return simplify_gen_unary (NOT, mode,
4512 gen_lowpart_for_combine (mode, op0),
4513 mode);
4516 /* If X is 0/1, (eq X 0) is X-1. */
4517 else if (STORE_FLAG_VALUE == -1
4518 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4519 && op1 == const0_rtx
4520 && mode == GET_MODE (op0)
4521 && nonzero_bits (op0, mode) == 1)
4523 op0 = expand_compound_operation (op0);
4524 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4527 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4528 one bit that might be nonzero, we can convert (ne x 0) to
4529 (ashift x c) where C puts the bit in the sign bit. Remove any
4530 AND with STORE_FLAG_VALUE when we are done, since we are only
4531 going to test the sign bit. */
4532 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4533 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4534 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4535 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4536 && op1 == const0_rtx
4537 && mode == GET_MODE (op0)
4538 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4540 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4541 expand_compound_operation (op0),
4542 GET_MODE_BITSIZE (mode) - 1 - i);
4543 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4544 return XEXP (x, 0);
4545 else
4546 return x;
4549 /* If the code changed, return a whole new comparison. */
4550 if (new_code != code)
4551 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4553 /* Otherwise, keep this operation, but maybe change its operands.
4554 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4555 SUBST (XEXP (x, 0), op0);
4556 SUBST (XEXP (x, 1), op1);
4558 break;
4560 case IF_THEN_ELSE:
4561 return simplify_if_then_else (x);
4563 case ZERO_EXTRACT:
4564 case SIGN_EXTRACT:
4565 case ZERO_EXTEND:
4566 case SIGN_EXTEND:
4567 /* If we are processing SET_DEST, we are done. */
4568 if (in_dest)
4569 return x;
4571 return expand_compound_operation (x);
4573 case SET:
4574 return simplify_set (x);
4576 case AND:
4577 case IOR:
4578 case XOR:
4579 return simplify_logical (x, last);
4581 case ABS:
4582 /* (abs (neg <foo>)) -> (abs <foo>) */
4583 if (GET_CODE (XEXP (x, 0)) == NEG)
4584 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4586 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4587 do nothing. */
4588 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4589 break;
4591 /* If operand is something known to be positive, ignore the ABS. */
4592 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4593 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4594 <= HOST_BITS_PER_WIDE_INT)
4595 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4596 & ((HOST_WIDE_INT) 1
4597 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4598 == 0)))
4599 return XEXP (x, 0);
4601 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4602 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4603 return gen_rtx_NEG (mode, XEXP (x, 0));
4605 break;
4607 case FFS:
4608 /* (ffs (*_extend <X>)) = (ffs <X>) */
4609 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4610 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4611 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4612 break;
4614 case POPCOUNT:
4615 case PARITY:
4616 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4617 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4618 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4619 break;
4621 case FLOAT:
4622 /* (float (sign_extend <X>)) = (float <X>). */
4623 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4624 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4625 break;
4627 case ASHIFT:
4628 case LSHIFTRT:
4629 case ASHIFTRT:
4630 case ROTATE:
4631 case ROTATERT:
4632 /* If this is a shift by a constant amount, simplify it. */
4633 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4634 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4635 INTVAL (XEXP (x, 1)));
4637 #ifdef SHIFT_COUNT_TRUNCATED
4638 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4639 SUBST (XEXP (x, 1),
4640 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4641 ((HOST_WIDE_INT) 1
4642 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4643 - 1,
4644 NULL_RTX, 0));
4645 #endif
4647 break;
4649 case VEC_SELECT:
4651 rtx op0 = XEXP (x, 0);
4652 rtx op1 = XEXP (x, 1);
4653 int len;
4655 if (GET_CODE (op1) != PARALLEL)
4656 abort ();
4657 len = XVECLEN (op1, 0);
4658 if (len == 1
4659 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4660 && GET_CODE (op0) == VEC_CONCAT)
4662 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4664 /* Try to find the element in the VEC_CONCAT. */
4665 for (;;)
4667 if (GET_MODE (op0) == GET_MODE (x))
4668 return op0;
4669 if (GET_CODE (op0) == VEC_CONCAT)
4671 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4672 if (op0_size < offset)
4673 op0 = XEXP (op0, 0);
4674 else
4676 offset -= op0_size;
4677 op0 = XEXP (op0, 1);
4680 else
4681 break;
4686 break;
4688 default:
4689 break;
4692 return x;
4695 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4697 static rtx
4698 simplify_if_then_else (rtx x)
4700 enum machine_mode mode = GET_MODE (x);
4701 rtx cond = XEXP (x, 0);
4702 rtx true_rtx = XEXP (x, 1);
4703 rtx false_rtx = XEXP (x, 2);
4704 enum rtx_code true_code = GET_CODE (cond);
4705 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4706 rtx temp;
4707 int i;
4708 enum rtx_code false_code;
4709 rtx reversed;
4711 /* Simplify storing of the truth value. */
4712 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4713 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4715 /* Also when the truth value has to be reversed. */
4716 if (comparison_p
4717 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4718 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4719 XEXP (cond, 1))))
4720 return reversed;
4722 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4723 in it is being compared against certain values. Get the true and false
4724 comparisons and see if that says anything about the value of each arm. */
4726 if (comparison_p
4727 && ((false_code = combine_reversed_comparison_code (cond))
4728 != UNKNOWN)
4729 && GET_CODE (XEXP (cond, 0)) == REG)
4731 HOST_WIDE_INT nzb;
4732 rtx from = XEXP (cond, 0);
4733 rtx true_val = XEXP (cond, 1);
4734 rtx false_val = true_val;
4735 int swapped = 0;
4737 /* If FALSE_CODE is EQ, swap the codes and arms. */
4739 if (false_code == EQ)
4741 swapped = 1, true_code = EQ, false_code = NE;
4742 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4745 /* If we are comparing against zero and the expression being tested has
4746 only a single bit that might be nonzero, that is its value when it is
4747 not equal to zero. Similarly if it is known to be -1 or 0. */
4749 if (true_code == EQ && true_val == const0_rtx
4750 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4751 false_code = EQ, false_val = GEN_INT (nzb);
4752 else if (true_code == EQ && true_val == const0_rtx
4753 && (num_sign_bit_copies (from, GET_MODE (from))
4754 == GET_MODE_BITSIZE (GET_MODE (from))))
4755 false_code = EQ, false_val = constm1_rtx;
4757 /* Now simplify an arm if we know the value of the register in the
4758 branch and it is used in the arm. Be careful due to the potential
4759 of locally-shared RTL. */
4761 if (reg_mentioned_p (from, true_rtx))
4762 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4763 from, true_val),
4764 pc_rtx, pc_rtx, 0, 0);
4765 if (reg_mentioned_p (from, false_rtx))
4766 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4767 from, false_val),
4768 pc_rtx, pc_rtx, 0, 0);
4770 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4771 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4773 true_rtx = XEXP (x, 1);
4774 false_rtx = XEXP (x, 2);
4775 true_code = GET_CODE (cond);
4778 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4779 reversed, do so to avoid needing two sets of patterns for
4780 subtract-and-branch insns. Similarly if we have a constant in the true
4781 arm, the false arm is the same as the first operand of the comparison, or
4782 the false arm is more complicated than the true arm. */
4784 if (comparison_p
4785 && combine_reversed_comparison_code (cond) != UNKNOWN
4786 && (true_rtx == pc_rtx
4787 || (CONSTANT_P (true_rtx)
4788 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4789 || true_rtx == const0_rtx
4790 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4791 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4792 || (GET_CODE (true_rtx) == SUBREG
4793 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4794 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4795 || reg_mentioned_p (true_rtx, false_rtx)
4796 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4798 true_code = reversed_comparison_code (cond, NULL);
4799 SUBST (XEXP (x, 0),
4800 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4801 XEXP (cond, 1)));
4803 SUBST (XEXP (x, 1), false_rtx);
4804 SUBST (XEXP (x, 2), true_rtx);
4806 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4807 cond = XEXP (x, 0);
4809 /* It is possible that the conditional has been simplified out. */
4810 true_code = GET_CODE (cond);
4811 comparison_p = GET_RTX_CLASS (true_code) == '<';
4814 /* If the two arms are identical, we don't need the comparison. */
4816 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4817 return true_rtx;
4819 /* Convert a == b ? b : a to "a". */
4820 if (true_code == EQ && ! side_effects_p (cond)
4821 && !HONOR_NANS (mode)
4822 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4823 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4824 return false_rtx;
4825 else if (true_code == NE && ! side_effects_p (cond)
4826 && !HONOR_NANS (mode)
4827 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4828 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4829 return true_rtx;
4831 /* Look for cases where we have (abs x) or (neg (abs X)). */
4833 if (GET_MODE_CLASS (mode) == MODE_INT
4834 && GET_CODE (false_rtx) == NEG
4835 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4836 && comparison_p
4837 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4838 && ! side_effects_p (true_rtx))
4839 switch (true_code)
4841 case GT:
4842 case GE:
4843 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4844 case LT:
4845 case LE:
4846 return
4847 simplify_gen_unary (NEG, mode,
4848 simplify_gen_unary (ABS, mode, true_rtx, mode),
4849 mode);
4850 default:
4851 break;
4854 /* Look for MIN or MAX. */
4856 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4857 && comparison_p
4858 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4859 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4860 && ! side_effects_p (cond))
4861 switch (true_code)
4863 case GE:
4864 case GT:
4865 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4866 case LE:
4867 case LT:
4868 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4869 case GEU:
4870 case GTU:
4871 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4872 case LEU:
4873 case LTU:
4874 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4875 default:
4876 break;
4879 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4880 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4881 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4882 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4883 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4884 neither 1 or -1, but it isn't worth checking for. */
4886 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4887 && comparison_p
4888 && GET_MODE_CLASS (mode) == MODE_INT
4889 && ! side_effects_p (x))
4891 rtx t = make_compound_operation (true_rtx, SET);
4892 rtx f = make_compound_operation (false_rtx, SET);
4893 rtx cond_op0 = XEXP (cond, 0);
4894 rtx cond_op1 = XEXP (cond, 1);
4895 enum rtx_code op = NIL, extend_op = NIL;
4896 enum machine_mode m = mode;
4897 rtx z = 0, c1 = NULL_RTX;
4899 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4900 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4901 || GET_CODE (t) == ASHIFT
4902 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4903 && rtx_equal_p (XEXP (t, 0), f))
4904 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4906 /* If an identity-zero op is commutative, check whether there
4907 would be a match if we swapped the operands. */
4908 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4909 || GET_CODE (t) == XOR)
4910 && rtx_equal_p (XEXP (t, 1), f))
4911 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4912 else if (GET_CODE (t) == SIGN_EXTEND
4913 && (GET_CODE (XEXP (t, 0)) == PLUS
4914 || GET_CODE (XEXP (t, 0)) == MINUS
4915 || GET_CODE (XEXP (t, 0)) == IOR
4916 || GET_CODE (XEXP (t, 0)) == XOR
4917 || GET_CODE (XEXP (t, 0)) == ASHIFT
4918 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4919 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4920 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4921 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4922 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4923 && (num_sign_bit_copies (f, GET_MODE (f))
4924 > (unsigned int)
4925 (GET_MODE_BITSIZE (mode)
4926 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4928 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4929 extend_op = SIGN_EXTEND;
4930 m = GET_MODE (XEXP (t, 0));
4932 else if (GET_CODE (t) == SIGN_EXTEND
4933 && (GET_CODE (XEXP (t, 0)) == PLUS
4934 || GET_CODE (XEXP (t, 0)) == IOR
4935 || GET_CODE (XEXP (t, 0)) == XOR)
4936 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4937 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4938 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4939 && (num_sign_bit_copies (f, GET_MODE (f))
4940 > (unsigned int)
4941 (GET_MODE_BITSIZE (mode)
4942 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4944 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4945 extend_op = SIGN_EXTEND;
4946 m = GET_MODE (XEXP (t, 0));
4948 else if (GET_CODE (t) == ZERO_EXTEND
4949 && (GET_CODE (XEXP (t, 0)) == PLUS
4950 || GET_CODE (XEXP (t, 0)) == MINUS
4951 || GET_CODE (XEXP (t, 0)) == IOR
4952 || GET_CODE (XEXP (t, 0)) == XOR
4953 || GET_CODE (XEXP (t, 0)) == ASHIFT
4954 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4955 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4956 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4957 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4958 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4959 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4960 && ((nonzero_bits (f, GET_MODE (f))
4961 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4962 == 0))
4964 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4965 extend_op = ZERO_EXTEND;
4966 m = GET_MODE (XEXP (t, 0));
4968 else if (GET_CODE (t) == ZERO_EXTEND
4969 && (GET_CODE (XEXP (t, 0)) == PLUS
4970 || GET_CODE (XEXP (t, 0)) == IOR
4971 || GET_CODE (XEXP (t, 0)) == XOR)
4972 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4973 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4974 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4975 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4976 && ((nonzero_bits (f, GET_MODE (f))
4977 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4978 == 0))
4980 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4981 extend_op = ZERO_EXTEND;
4982 m = GET_MODE (XEXP (t, 0));
4985 if (z)
4987 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4988 pc_rtx, pc_rtx, 0, 0);
4989 temp = gen_binary (MULT, m, temp,
4990 gen_binary (MULT, m, c1, const_true_rtx));
4991 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4992 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4994 if (extend_op != NIL)
4995 temp = simplify_gen_unary (extend_op, mode, temp, m);
4997 return temp;
5001 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5002 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5003 negation of a single bit, we can convert this operation to a shift. We
5004 can actually do this more generally, but it doesn't seem worth it. */
5006 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5007 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5008 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5009 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5010 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5011 == GET_MODE_BITSIZE (mode))
5012 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5013 return
5014 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5015 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
5017 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5018 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5019 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5020 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5021 == nonzero_bits (XEXP (cond, 0), mode)
5022 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5023 return XEXP (cond, 0);
5025 return x;
5028 /* Simplify X, a SET expression. Return the new expression. */
5030 static rtx
5031 simplify_set (rtx x)
5033 rtx src = SET_SRC (x);
5034 rtx dest = SET_DEST (x);
5035 enum machine_mode mode
5036 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5037 rtx other_insn;
5038 rtx *cc_use;
5040 /* (set (pc) (return)) gets written as (return). */
5041 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5042 return src;
5044 /* Now that we know for sure which bits of SRC we are using, see if we can
5045 simplify the expression for the object knowing that we only need the
5046 low-order bits. */
5048 if (GET_MODE_CLASS (mode) == MODE_INT
5049 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5051 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5052 SUBST (SET_SRC (x), src);
5055 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5056 the comparison result and try to simplify it unless we already have used
5057 undobuf.other_insn. */
5058 if ((GET_MODE_CLASS (mode) == MODE_CC
5059 || GET_CODE (src) == COMPARE
5060 || CC0_P (dest))
5061 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5062 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5063 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5064 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5066 enum rtx_code old_code = GET_CODE (*cc_use);
5067 enum rtx_code new_code;
5068 rtx op0, op1, tmp;
5069 int other_changed = 0;
5070 enum machine_mode compare_mode = GET_MODE (dest);
5071 enum machine_mode tmp_mode;
5073 if (GET_CODE (src) == COMPARE)
5074 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5075 else
5076 op0 = src, op1 = const0_rtx;
5078 /* Check whether the comparison is known at compile time. */
5079 if (GET_MODE (op0) != VOIDmode)
5080 tmp_mode = GET_MODE (op0);
5081 else if (GET_MODE (op1) != VOIDmode)
5082 tmp_mode = GET_MODE (op1);
5083 else
5084 tmp_mode = compare_mode;
5085 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5086 if (tmp != NULL_RTX)
5088 rtx pat = PATTERN (other_insn);
5089 undobuf.other_insn = other_insn;
5090 SUBST (*cc_use, tmp);
5092 /* Attempt to simplify CC user. */
5093 if (GET_CODE (pat) == SET)
5095 rtx new = simplify_rtx (SET_SRC (pat));
5096 if (new != NULL_RTX)
5097 SUBST (SET_SRC (pat), new);
5100 /* Convert X into a no-op move. */
5101 SUBST (SET_DEST (x), pc_rtx);
5102 SUBST (SET_SRC (x), pc_rtx);
5103 return x;
5106 /* Simplify our comparison, if possible. */
5107 new_code = simplify_comparison (old_code, &op0, &op1);
5109 #ifdef EXTRA_CC_MODES
5110 /* If this machine has CC modes other than CCmode, check to see if we
5111 need to use a different CC mode here. */
5112 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5113 #endif /* EXTRA_CC_MODES */
5115 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5116 /* If the mode changed, we have to change SET_DEST, the mode in the
5117 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5118 a hard register, just build new versions with the proper mode. If it
5119 is a pseudo, we lose unless it is only time we set the pseudo, in
5120 which case we can safely change its mode. */
5121 if (compare_mode != GET_MODE (dest))
5123 unsigned int regno = REGNO (dest);
5124 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5126 if (regno < FIRST_PSEUDO_REGISTER
5127 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5129 if (regno >= FIRST_PSEUDO_REGISTER)
5130 SUBST (regno_reg_rtx[regno], new_dest);
5132 SUBST (SET_DEST (x), new_dest);
5133 SUBST (XEXP (*cc_use, 0), new_dest);
5134 other_changed = 1;
5136 dest = new_dest;
5139 #endif
5141 /* If the code changed, we have to build a new comparison in
5142 undobuf.other_insn. */
5143 if (new_code != old_code)
5145 unsigned HOST_WIDE_INT mask;
5147 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5148 dest, const0_rtx));
5150 /* If the only change we made was to change an EQ into an NE or
5151 vice versa, OP0 has only one bit that might be nonzero, and OP1
5152 is zero, check if changing the user of the condition code will
5153 produce a valid insn. If it won't, we can keep the original code
5154 in that insn by surrounding our operation with an XOR. */
5156 if (((old_code == NE && new_code == EQ)
5157 || (old_code == EQ && new_code == NE))
5158 && ! other_changed && op1 == const0_rtx
5159 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5160 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5162 rtx pat = PATTERN (other_insn), note = 0;
5164 if ((recog_for_combine (&pat, other_insn, &note) < 0
5165 && ! check_asm_operands (pat)))
5167 PUT_CODE (*cc_use, old_code);
5168 other_insn = 0;
5170 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5174 other_changed = 1;
5177 if (other_changed)
5178 undobuf.other_insn = other_insn;
5180 #ifdef HAVE_cc0
5181 /* If we are now comparing against zero, change our source if
5182 needed. If we do not use cc0, we always have a COMPARE. */
5183 if (op1 == const0_rtx && dest == cc0_rtx)
5185 SUBST (SET_SRC (x), op0);
5186 src = op0;
5188 else
5189 #endif
5191 /* Otherwise, if we didn't previously have a COMPARE in the
5192 correct mode, we need one. */
5193 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5195 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5196 src = SET_SRC (x);
5198 else
5200 /* Otherwise, update the COMPARE if needed. */
5201 SUBST (XEXP (src, 0), op0);
5202 SUBST (XEXP (src, 1), op1);
5205 else
5207 /* Get SET_SRC in a form where we have placed back any
5208 compound expressions. Then do the checks below. */
5209 src = make_compound_operation (src, SET);
5210 SUBST (SET_SRC (x), src);
5213 #ifdef WORD_REGISTER_OPERATIONS
5214 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5215 and X being a REG or (subreg (reg)), we may be able to convert this to
5216 (set (subreg:m2 x) (op)).
5218 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5219 transformation is safe as long as M1 and M2 have the same number
5220 of words.
5222 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5223 we cannot apply this transformation because it would create a
5224 paradoxical subreg in SET_DEST. */
5226 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5227 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5228 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5229 / UNITS_PER_WORD)
5230 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5231 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5232 #ifdef CANNOT_CHANGE_MODE_CLASS
5233 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5234 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5235 GET_MODE (SUBREG_REG (src)),
5236 GET_MODE (src)))
5237 #endif
5238 && (GET_CODE (dest) == REG
5239 || (GET_CODE (dest) == SUBREG
5240 && GET_CODE (SUBREG_REG (dest)) == REG)))
5242 SUBST (SET_DEST (x),
5243 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5244 dest));
5245 SUBST (SET_SRC (x), SUBREG_REG (src));
5247 src = SET_SRC (x), dest = SET_DEST (x);
5249 #endif
5251 #ifdef HAVE_cc0
5252 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5253 in SRC. */
5254 if (dest == cc0_rtx
5255 && GET_CODE (src) == SUBREG
5256 && subreg_lowpart_p (src)
5257 && (GET_MODE_BITSIZE (GET_MODE (src))
5258 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5260 rtx inner = SUBREG_REG (src);
5261 enum machine_mode inner_mode = GET_MODE (inner);
5263 /* Here we make sure that we don't have a sign bit on. */
5264 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5265 && (nonzero_bits (inner, inner_mode)
5266 < ((unsigned HOST_WIDE_INT) 1
5267 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5269 SUBST (SET_SRC (x), inner);
5270 src = SET_SRC (x);
5273 #endif
5275 #ifdef LOAD_EXTEND_OP
5276 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5277 would require a paradoxical subreg. Replace the subreg with a
5278 zero_extend to avoid the reload that would otherwise be required. */
5280 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5281 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5282 && SUBREG_BYTE (src) == 0
5283 && (GET_MODE_SIZE (GET_MODE (src))
5284 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5285 && GET_CODE (SUBREG_REG (src)) == MEM)
5287 SUBST (SET_SRC (x),
5288 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5289 GET_MODE (src), SUBREG_REG (src)));
5291 src = SET_SRC (x);
5293 #endif
5295 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5296 are comparing an item known to be 0 or -1 against 0, use a logical
5297 operation instead. Check for one of the arms being an IOR of the other
5298 arm with some value. We compute three terms to be IOR'ed together. In
5299 practice, at most two will be nonzero. Then we do the IOR's. */
5301 if (GET_CODE (dest) != PC
5302 && GET_CODE (src) == IF_THEN_ELSE
5303 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5304 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5305 && XEXP (XEXP (src, 0), 1) == const0_rtx
5306 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5307 #ifdef HAVE_conditional_move
5308 && ! can_conditionally_move_p (GET_MODE (src))
5309 #endif
5310 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5311 GET_MODE (XEXP (XEXP (src, 0), 0)))
5312 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5313 && ! side_effects_p (src))
5315 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5316 ? XEXP (src, 1) : XEXP (src, 2));
5317 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5318 ? XEXP (src, 2) : XEXP (src, 1));
5319 rtx term1 = const0_rtx, term2, term3;
5321 if (GET_CODE (true_rtx) == IOR
5322 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5323 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5324 else if (GET_CODE (true_rtx) == IOR
5325 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5326 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5327 else if (GET_CODE (false_rtx) == IOR
5328 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5329 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5330 else if (GET_CODE (false_rtx) == IOR
5331 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5332 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5334 term2 = gen_binary (AND, GET_MODE (src),
5335 XEXP (XEXP (src, 0), 0), true_rtx);
5336 term3 = gen_binary (AND, GET_MODE (src),
5337 simplify_gen_unary (NOT, GET_MODE (src),
5338 XEXP (XEXP (src, 0), 0),
5339 GET_MODE (src)),
5340 false_rtx);
5342 SUBST (SET_SRC (x),
5343 gen_binary (IOR, GET_MODE (src),
5344 gen_binary (IOR, GET_MODE (src), term1, term2),
5345 term3));
5347 src = SET_SRC (x);
5350 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5351 whole thing fail. */
5352 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5353 return src;
5354 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5355 return dest;
5356 else
5357 /* Convert this into a field assignment operation, if possible. */
5358 return make_field_assignment (x);
5361 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5362 result. LAST is nonzero if this is the last retry. */
5364 static rtx
5365 simplify_logical (rtx x, int last)
5367 enum machine_mode mode = GET_MODE (x);
5368 rtx op0 = XEXP (x, 0);
5369 rtx op1 = XEXP (x, 1);
5370 rtx reversed;
5372 switch (GET_CODE (x))
5374 case AND:
5375 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5376 insn (and may simplify more). */
5377 if (GET_CODE (op0) == XOR
5378 && rtx_equal_p (XEXP (op0, 0), op1)
5379 && ! side_effects_p (op1))
5380 x = gen_binary (AND, mode,
5381 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5382 op1);
5384 if (GET_CODE (op0) == XOR
5385 && rtx_equal_p (XEXP (op0, 1), op1)
5386 && ! side_effects_p (op1))
5387 x = gen_binary (AND, mode,
5388 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5389 op1);
5391 /* Similarly for (~(A ^ B)) & A. */
5392 if (GET_CODE (op0) == NOT
5393 && GET_CODE (XEXP (op0, 0)) == XOR
5394 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5395 && ! side_effects_p (op1))
5396 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5398 if (GET_CODE (op0) == NOT
5399 && GET_CODE (XEXP (op0, 0)) == XOR
5400 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5401 && ! side_effects_p (op1))
5402 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5404 /* We can call simplify_and_const_int only if we don't lose
5405 any (sign) bits when converting INTVAL (op1) to
5406 "unsigned HOST_WIDE_INT". */
5407 if (GET_CODE (op1) == CONST_INT
5408 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5409 || INTVAL (op1) > 0))
5411 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5413 /* If we have (ior (and (X C1) C2)) and the next restart would be
5414 the last, simplify this by making C1 as small as possible
5415 and then exit. */
5416 if (last
5417 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5418 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5419 && GET_CODE (op1) == CONST_INT)
5420 return gen_binary (IOR, mode,
5421 gen_binary (AND, mode, XEXP (op0, 0),
5422 GEN_INT (INTVAL (XEXP (op0, 1))
5423 & ~INTVAL (op1))), op1);
5425 if (GET_CODE (x) != AND)
5426 return x;
5428 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5429 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5430 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5433 /* Convert (A | B) & A to A. */
5434 if (GET_CODE (op0) == IOR
5435 && (rtx_equal_p (XEXP (op0, 0), op1)
5436 || rtx_equal_p (XEXP (op0, 1), op1))
5437 && ! side_effects_p (XEXP (op0, 0))
5438 && ! side_effects_p (XEXP (op0, 1)))
5439 return op1;
5441 /* In the following group of tests (and those in case IOR below),
5442 we start with some combination of logical operations and apply
5443 the distributive law followed by the inverse distributive law.
5444 Most of the time, this results in no change. However, if some of
5445 the operands are the same or inverses of each other, simplifications
5446 will result.
5448 For example, (and (ior A B) (not B)) can occur as the result of
5449 expanding a bit field assignment. When we apply the distributive
5450 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5451 which then simplifies to (and (A (not B))).
5453 If we have (and (ior A B) C), apply the distributive law and then
5454 the inverse distributive law to see if things simplify. */
5456 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5458 x = apply_distributive_law
5459 (gen_binary (GET_CODE (op0), mode,
5460 gen_binary (AND, mode, XEXP (op0, 0), op1),
5461 gen_binary (AND, mode, XEXP (op0, 1),
5462 copy_rtx (op1))));
5463 if (GET_CODE (x) != AND)
5464 return x;
5467 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5468 return apply_distributive_law
5469 (gen_binary (GET_CODE (op1), mode,
5470 gen_binary (AND, mode, XEXP (op1, 0), op0),
5471 gen_binary (AND, mode, XEXP (op1, 1),
5472 copy_rtx (op0))));
5474 /* Similarly, taking advantage of the fact that
5475 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5477 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5478 return apply_distributive_law
5479 (gen_binary (XOR, mode,
5480 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5481 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5482 XEXP (op1, 1))));
5484 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5485 return apply_distributive_law
5486 (gen_binary (XOR, mode,
5487 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5488 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5489 break;
5491 case IOR:
5492 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5493 if (GET_CODE (op1) == CONST_INT
5494 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5495 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5496 return op1;
5498 /* Convert (A & B) | A to A. */
5499 if (GET_CODE (op0) == AND
5500 && (rtx_equal_p (XEXP (op0, 0), op1)
5501 || rtx_equal_p (XEXP (op0, 1), op1))
5502 && ! side_effects_p (XEXP (op0, 0))
5503 && ! side_effects_p (XEXP (op0, 1)))
5504 return op1;
5506 /* If we have (ior (and A B) C), apply the distributive law and then
5507 the inverse distributive law to see if things simplify. */
5509 if (GET_CODE (op0) == AND)
5511 x = apply_distributive_law
5512 (gen_binary (AND, mode,
5513 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5514 gen_binary (IOR, mode, XEXP (op0, 1),
5515 copy_rtx (op1))));
5517 if (GET_CODE (x) != IOR)
5518 return x;
5521 if (GET_CODE (op1) == AND)
5523 x = apply_distributive_law
5524 (gen_binary (AND, mode,
5525 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5526 gen_binary (IOR, mode, XEXP (op1, 1),
5527 copy_rtx (op0))));
5529 if (GET_CODE (x) != IOR)
5530 return x;
5533 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5534 mode size to (rotate A CX). */
5536 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5537 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5538 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5539 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5540 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5541 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5542 == GET_MODE_BITSIZE (mode)))
5543 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5544 (GET_CODE (op0) == ASHIFT
5545 ? XEXP (op0, 1) : XEXP (op1, 1)));
5547 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5548 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5549 does not affect any of the bits in OP1, it can really be done
5550 as a PLUS and we can associate. We do this by seeing if OP1
5551 can be safely shifted left C bits. */
5552 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5553 && GET_CODE (XEXP (op0, 0)) == PLUS
5554 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5555 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5556 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5558 int count = INTVAL (XEXP (op0, 1));
5559 HOST_WIDE_INT mask = INTVAL (op1) << count;
5561 if (mask >> count == INTVAL (op1)
5562 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5564 SUBST (XEXP (XEXP (op0, 0), 1),
5565 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5566 return op0;
5569 break;
5571 case XOR:
5572 /* If we are XORing two things that have no bits in common,
5573 convert them into an IOR. This helps to detect rotation encoded
5574 using those methods and possibly other simplifications. */
5576 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5577 && (nonzero_bits (op0, mode)
5578 & nonzero_bits (op1, mode)) == 0)
5579 return (gen_binary (IOR, mode, op0, op1));
5581 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5582 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5583 (NOT y). */
5585 int num_negated = 0;
5587 if (GET_CODE (op0) == NOT)
5588 num_negated++, op0 = XEXP (op0, 0);
5589 if (GET_CODE (op1) == NOT)
5590 num_negated++, op1 = XEXP (op1, 0);
5592 if (num_negated == 2)
5594 SUBST (XEXP (x, 0), op0);
5595 SUBST (XEXP (x, 1), op1);
5597 else if (num_negated == 1)
5598 return
5599 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5600 mode);
5603 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5604 correspond to a machine insn or result in further simplifications
5605 if B is a constant. */
5607 if (GET_CODE (op0) == AND
5608 && rtx_equal_p (XEXP (op0, 1), op1)
5609 && ! side_effects_p (op1))
5610 return gen_binary (AND, mode,
5611 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5612 op1);
5614 else if (GET_CODE (op0) == AND
5615 && rtx_equal_p (XEXP (op0, 0), op1)
5616 && ! side_effects_p (op1))
5617 return gen_binary (AND, mode,
5618 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5619 op1);
5621 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5622 comparison if STORE_FLAG_VALUE is 1. */
5623 if (STORE_FLAG_VALUE == 1
5624 && op1 == const1_rtx
5625 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5626 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5627 XEXP (op0, 1))))
5628 return reversed;
5630 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5631 is (lt foo (const_int 0)), so we can perform the above
5632 simplification if STORE_FLAG_VALUE is 1. */
5634 if (STORE_FLAG_VALUE == 1
5635 && op1 == const1_rtx
5636 && GET_CODE (op0) == LSHIFTRT
5637 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5638 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5639 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5641 /* (xor (comparison foo bar) (const_int sign-bit))
5642 when STORE_FLAG_VALUE is the sign bit. */
5643 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5644 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5645 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5646 && op1 == const_true_rtx
5647 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5648 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5649 XEXP (op0, 1))))
5650 return reversed;
5652 break;
5654 default:
5655 abort ();
5658 return x;
5661 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5662 operations" because they can be replaced with two more basic operations.
5663 ZERO_EXTEND is also considered "compound" because it can be replaced with
5664 an AND operation, which is simpler, though only one operation.
5666 The function expand_compound_operation is called with an rtx expression
5667 and will convert it to the appropriate shifts and AND operations,
5668 simplifying at each stage.
5670 The function make_compound_operation is called to convert an expression
5671 consisting of shifts and ANDs into the equivalent compound expression.
5672 It is the inverse of this function, loosely speaking. */
5674 static rtx
5675 expand_compound_operation (rtx x)
5677 unsigned HOST_WIDE_INT pos = 0, len;
5678 int unsignedp = 0;
5679 unsigned int modewidth;
5680 rtx tem;
5682 switch (GET_CODE (x))
5684 case ZERO_EXTEND:
5685 unsignedp = 1;
5686 case SIGN_EXTEND:
5687 /* We can't necessarily use a const_int for a multiword mode;
5688 it depends on implicitly extending the value.
5689 Since we don't know the right way to extend it,
5690 we can't tell whether the implicit way is right.
5692 Even for a mode that is no wider than a const_int,
5693 we can't win, because we need to sign extend one of its bits through
5694 the rest of it, and we don't know which bit. */
5695 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5696 return x;
5698 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5699 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5700 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5701 reloaded. If not for that, MEM's would very rarely be safe.
5703 Reject MODEs bigger than a word, because we might not be able
5704 to reference a two-register group starting with an arbitrary register
5705 (and currently gen_lowpart might crash for a SUBREG). */
5707 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5708 return x;
5710 /* Reject MODEs that aren't scalar integers because turning vector
5711 or complex modes into shifts causes problems. */
5713 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5714 return x;
5716 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5717 /* If the inner object has VOIDmode (the only way this can happen
5718 is if it is an ASM_OPERANDS), we can't do anything since we don't
5719 know how much masking to do. */
5720 if (len == 0)
5721 return x;
5723 break;
5725 case ZERO_EXTRACT:
5726 unsignedp = 1;
5727 case SIGN_EXTRACT:
5728 /* If the operand is a CLOBBER, just return it. */
5729 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5730 return XEXP (x, 0);
5732 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5733 || GET_CODE (XEXP (x, 2)) != CONST_INT
5734 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5735 return x;
5737 /* Reject MODEs that aren't scalar integers because turning vector
5738 or complex modes into shifts causes problems. */
5740 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5741 return x;
5743 len = INTVAL (XEXP (x, 1));
5744 pos = INTVAL (XEXP (x, 2));
5746 /* If this goes outside the object being extracted, replace the object
5747 with a (use (mem ...)) construct that only combine understands
5748 and is used only for this purpose. */
5749 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5750 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5752 if (BITS_BIG_ENDIAN)
5753 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5755 break;
5757 default:
5758 return x;
5760 /* Convert sign extension to zero extension, if we know that the high
5761 bit is not set, as this is easier to optimize. It will be converted
5762 back to cheaper alternative in make_extraction. */
5763 if (GET_CODE (x) == SIGN_EXTEND
5764 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5765 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5766 & ~(((unsigned HOST_WIDE_INT)
5767 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5768 >> 1))
5769 == 0)))
5771 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5772 rtx temp2 = expand_compound_operation (temp);
5774 /* Make sure this is a profitable operation. */
5775 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5776 return temp2;
5777 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5778 return temp;
5779 else
5780 return x;
5783 /* We can optimize some special cases of ZERO_EXTEND. */
5784 if (GET_CODE (x) == ZERO_EXTEND)
5786 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5787 know that the last value didn't have any inappropriate bits
5788 set. */
5789 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5790 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5791 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5792 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5793 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5794 return XEXP (XEXP (x, 0), 0);
5796 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5797 if (GET_CODE (XEXP (x, 0)) == SUBREG
5798 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5799 && subreg_lowpart_p (XEXP (x, 0))
5800 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5801 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5802 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5803 return SUBREG_REG (XEXP (x, 0));
5805 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5806 is a comparison and STORE_FLAG_VALUE permits. This is like
5807 the first case, but it works even when GET_MODE (x) is larger
5808 than HOST_WIDE_INT. */
5809 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5810 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5811 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5812 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5813 <= HOST_BITS_PER_WIDE_INT)
5814 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5815 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5816 return XEXP (XEXP (x, 0), 0);
5818 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5819 if (GET_CODE (XEXP (x, 0)) == SUBREG
5820 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5821 && subreg_lowpart_p (XEXP (x, 0))
5822 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5823 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5824 <= HOST_BITS_PER_WIDE_INT)
5825 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5826 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5827 return SUBREG_REG (XEXP (x, 0));
5831 /* If we reach here, we want to return a pair of shifts. The inner
5832 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5833 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5834 logical depending on the value of UNSIGNEDP.
5836 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5837 converted into an AND of a shift.
5839 We must check for the case where the left shift would have a negative
5840 count. This can happen in a case like (x >> 31) & 255 on machines
5841 that can't shift by a constant. On those machines, we would first
5842 combine the shift with the AND to produce a variable-position
5843 extraction. Then the constant of 31 would be substituted in to produce
5844 a such a position. */
5846 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5847 if (modewidth + len >= pos)
5848 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5849 GET_MODE (x),
5850 simplify_shift_const (NULL_RTX, ASHIFT,
5851 GET_MODE (x),
5852 XEXP (x, 0),
5853 modewidth - pos - len),
5854 modewidth - len);
5856 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5857 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5858 simplify_shift_const (NULL_RTX, LSHIFTRT,
5859 GET_MODE (x),
5860 XEXP (x, 0), pos),
5861 ((HOST_WIDE_INT) 1 << len) - 1);
5862 else
5863 /* Any other cases we can't handle. */
5864 return x;
5866 /* If we couldn't do this for some reason, return the original
5867 expression. */
5868 if (GET_CODE (tem) == CLOBBER)
5869 return x;
5871 return tem;
5874 /* X is a SET which contains an assignment of one object into
5875 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5876 or certain SUBREGS). If possible, convert it into a series of
5877 logical operations.
5879 We half-heartedly support variable positions, but do not at all
5880 support variable lengths. */
5882 static rtx
5883 expand_field_assignment (rtx x)
5885 rtx inner;
5886 rtx pos; /* Always counts from low bit. */
5887 int len;
5888 rtx mask;
5889 enum machine_mode compute_mode;
5891 /* Loop until we find something we can't simplify. */
5892 while (1)
5894 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5895 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5897 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5898 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5899 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5901 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5902 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5904 inner = XEXP (SET_DEST (x), 0);
5905 len = INTVAL (XEXP (SET_DEST (x), 1));
5906 pos = XEXP (SET_DEST (x), 2);
5908 /* If the position is constant and spans the width of INNER,
5909 surround INNER with a USE to indicate this. */
5910 if (GET_CODE (pos) == CONST_INT
5911 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5912 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5914 if (BITS_BIG_ENDIAN)
5916 if (GET_CODE (pos) == CONST_INT)
5917 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5918 - INTVAL (pos));
5919 else if (GET_CODE (pos) == MINUS
5920 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5921 && (INTVAL (XEXP (pos, 1))
5922 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5923 /* If position is ADJUST - X, new position is X. */
5924 pos = XEXP (pos, 0);
5925 else
5926 pos = gen_binary (MINUS, GET_MODE (pos),
5927 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5928 - len),
5929 pos);
5933 /* A SUBREG between two modes that occupy the same numbers of words
5934 can be done by moving the SUBREG to the source. */
5935 else if (GET_CODE (SET_DEST (x)) == SUBREG
5936 /* We need SUBREGs to compute nonzero_bits properly. */
5937 && nonzero_sign_valid
5938 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5939 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5940 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5941 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5943 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5944 gen_lowpart_for_combine
5945 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5946 SET_SRC (x)));
5947 continue;
5949 else
5950 break;
5952 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5953 inner = SUBREG_REG (inner);
5955 compute_mode = GET_MODE (inner);
5957 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5958 if (! SCALAR_INT_MODE_P (compute_mode))
5960 enum machine_mode imode;
5962 /* Don't do anything for vector or complex integral types. */
5963 if (! FLOAT_MODE_P (compute_mode))
5964 break;
5966 /* Try to find an integral mode to pun with. */
5967 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5968 if (imode == BLKmode)
5969 break;
5971 compute_mode = imode;
5972 inner = gen_lowpart_for_combine (imode, inner);
5975 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5976 if (len < HOST_BITS_PER_WIDE_INT)
5977 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5978 else
5979 break;
5981 /* Now compute the equivalent expression. Make a copy of INNER
5982 for the SET_DEST in case it is a MEM into which we will substitute;
5983 we don't want shared RTL in that case. */
5984 x = gen_rtx_SET
5985 (VOIDmode, copy_rtx (inner),
5986 gen_binary (IOR, compute_mode,
5987 gen_binary (AND, compute_mode,
5988 simplify_gen_unary (NOT, compute_mode,
5989 gen_binary (ASHIFT,
5990 compute_mode,
5991 mask, pos),
5992 compute_mode),
5993 inner),
5994 gen_binary (ASHIFT, compute_mode,
5995 gen_binary (AND, compute_mode,
5996 gen_lowpart_for_combine
5997 (compute_mode, SET_SRC (x)),
5998 mask),
5999 pos)));
6002 return x;
6005 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6006 it is an RTX that represents a variable starting position; otherwise,
6007 POS is the (constant) starting bit position (counted from the LSB).
6009 INNER may be a USE. This will occur when we started with a bitfield
6010 that went outside the boundary of the object in memory, which is
6011 allowed on most machines. To isolate this case, we produce a USE
6012 whose mode is wide enough and surround the MEM with it. The only
6013 code that understands the USE is this routine. If it is not removed,
6014 it will cause the resulting insn not to match.
6016 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6017 signed reference.
6019 IN_DEST is nonzero if this is a reference in the destination of a
6020 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6021 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6022 be used.
6024 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6025 ZERO_EXTRACT should be built even for bits starting at bit 0.
6027 MODE is the desired mode of the result (if IN_DEST == 0).
6029 The result is an RTX for the extraction or NULL_RTX if the target
6030 can't handle it. */
6032 static rtx
6033 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6034 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6035 int in_dest, int in_compare)
6037 /* This mode describes the size of the storage area
6038 to fetch the overall value from. Within that, we
6039 ignore the POS lowest bits, etc. */
6040 enum machine_mode is_mode = GET_MODE (inner);
6041 enum machine_mode inner_mode;
6042 enum machine_mode wanted_inner_mode = byte_mode;
6043 enum machine_mode wanted_inner_reg_mode = word_mode;
6044 enum machine_mode pos_mode = word_mode;
6045 enum machine_mode extraction_mode = word_mode;
6046 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6047 int spans_byte = 0;
6048 rtx new = 0;
6049 rtx orig_pos_rtx = pos_rtx;
6050 HOST_WIDE_INT orig_pos;
6052 /* Get some information about INNER and get the innermost object. */
6053 if (GET_CODE (inner) == USE)
6054 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6055 /* We don't need to adjust the position because we set up the USE
6056 to pretend that it was a full-word object. */
6057 spans_byte = 1, inner = XEXP (inner, 0);
6058 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6060 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6061 consider just the QI as the memory to extract from.
6062 The subreg adds or removes high bits; its mode is
6063 irrelevant to the meaning of this extraction,
6064 since POS and LEN count from the lsb. */
6065 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6066 is_mode = GET_MODE (SUBREG_REG (inner));
6067 inner = SUBREG_REG (inner);
6069 else if (GET_CODE (inner) == ASHIFT
6070 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6071 && pos_rtx == 0 && pos == 0
6072 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6074 /* We're extracting the least significant bits of an rtx
6075 (ashift X (const_int C)), where LEN > C. Extract the
6076 least significant (LEN - C) bits of X, giving an rtx
6077 whose mode is MODE, then shift it left C times. */
6078 new = make_extraction (mode, XEXP (inner, 0),
6079 0, 0, len - INTVAL (XEXP (inner, 1)),
6080 unsignedp, in_dest, in_compare);
6081 if (new != 0)
6082 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6085 inner_mode = GET_MODE (inner);
6087 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6088 pos = INTVAL (pos_rtx), pos_rtx = 0;
6090 /* See if this can be done without an extraction. We never can if the
6091 width of the field is not the same as that of some integer mode. For
6092 registers, we can only avoid the extraction if the position is at the
6093 low-order bit and this is either not in the destination or we have the
6094 appropriate STRICT_LOW_PART operation available.
6096 For MEM, we can avoid an extract if the field starts on an appropriate
6097 boundary and we can change the mode of the memory reference. However,
6098 we cannot directly access the MEM if we have a USE and the underlying
6099 MEM is not TMODE. This combination means that MEM was being used in a
6100 context where bits outside its mode were being referenced; that is only
6101 valid in bit-field insns. */
6103 if (tmode != BLKmode
6104 && ! (spans_byte && inner_mode != tmode)
6105 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6106 && GET_CODE (inner) != MEM
6107 && (! in_dest
6108 || (GET_CODE (inner) == REG
6109 && have_insn_for (STRICT_LOW_PART, tmode))))
6110 || (GET_CODE (inner) == MEM && pos_rtx == 0
6111 && (pos
6112 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6113 : BITS_PER_UNIT)) == 0
6114 /* We can't do this if we are widening INNER_MODE (it
6115 may not be aligned, for one thing). */
6116 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6117 && (inner_mode == tmode
6118 || (! mode_dependent_address_p (XEXP (inner, 0))
6119 && ! MEM_VOLATILE_P (inner))))))
6121 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6122 field. If the original and current mode are the same, we need not
6123 adjust the offset. Otherwise, we do if bytes big endian.
6125 If INNER is not a MEM, get a piece consisting of just the field
6126 of interest (in this case POS % BITS_PER_WORD must be 0). */
6128 if (GET_CODE (inner) == MEM)
6130 HOST_WIDE_INT offset;
6132 /* POS counts from lsb, but make OFFSET count in memory order. */
6133 if (BYTES_BIG_ENDIAN)
6134 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6135 else
6136 offset = pos / BITS_PER_UNIT;
6138 new = adjust_address_nv (inner, tmode, offset);
6140 else if (GET_CODE (inner) == REG)
6142 if (tmode != inner_mode)
6144 if (in_dest)
6146 /* We can't call gen_lowpart_for_combine here since we always want
6147 a SUBREG and it would sometimes return a new hard register. */
6148 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6150 if (WORDS_BIG_ENDIAN
6151 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6152 final_word = ((GET_MODE_SIZE (inner_mode)
6153 - GET_MODE_SIZE (tmode))
6154 / UNITS_PER_WORD) - final_word;
6156 final_word *= UNITS_PER_WORD;
6157 if (BYTES_BIG_ENDIAN &&
6158 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6159 final_word += (GET_MODE_SIZE (inner_mode)
6160 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6162 /* Avoid creating invalid subregs, for example when
6163 simplifying (x>>32)&255. */
6164 if (final_word >= GET_MODE_SIZE (inner_mode))
6165 return NULL_RTX;
6167 new = gen_rtx_SUBREG (tmode, inner, final_word);
6169 else
6170 new = gen_lowpart_for_combine (tmode, inner);
6172 else
6173 new = inner;
6175 else
6176 new = force_to_mode (inner, tmode,
6177 len >= HOST_BITS_PER_WIDE_INT
6178 ? ~(unsigned HOST_WIDE_INT) 0
6179 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6180 NULL_RTX, 0);
6182 /* If this extraction is going into the destination of a SET,
6183 make a STRICT_LOW_PART unless we made a MEM. */
6185 if (in_dest)
6186 return (GET_CODE (new) == MEM ? new
6187 : (GET_CODE (new) != SUBREG
6188 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6189 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6191 if (mode == tmode)
6192 return new;
6194 if (GET_CODE (new) == CONST_INT)
6195 return gen_int_mode (INTVAL (new), mode);
6197 /* If we know that no extraneous bits are set, and that the high
6198 bit is not set, convert the extraction to the cheaper of
6199 sign and zero extension, that are equivalent in these cases. */
6200 if (flag_expensive_optimizations
6201 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6202 && ((nonzero_bits (new, tmode)
6203 & ~(((unsigned HOST_WIDE_INT)
6204 GET_MODE_MASK (tmode))
6205 >> 1))
6206 == 0)))
6208 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6209 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6211 /* Prefer ZERO_EXTENSION, since it gives more information to
6212 backends. */
6213 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6214 return temp;
6215 return temp1;
6218 /* Otherwise, sign- or zero-extend unless we already are in the
6219 proper mode. */
6221 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6222 mode, new));
6225 /* Unless this is a COMPARE or we have a funny memory reference,
6226 don't do anything with zero-extending field extracts starting at
6227 the low-order bit since they are simple AND operations. */
6228 if (pos_rtx == 0 && pos == 0 && ! in_dest
6229 && ! in_compare && ! spans_byte && unsignedp)
6230 return 0;
6232 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6233 we would be spanning bytes or if the position is not a constant and the
6234 length is not 1. In all other cases, we would only be going outside
6235 our object in cases when an original shift would have been
6236 undefined. */
6237 if (! spans_byte && GET_CODE (inner) == MEM
6238 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6239 || (pos_rtx != 0 && len != 1)))
6240 return 0;
6242 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6243 and the mode for the result. */
6244 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6246 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6247 pos_mode = mode_for_extraction (EP_insv, 2);
6248 extraction_mode = mode_for_extraction (EP_insv, 3);
6251 if (! in_dest && unsignedp
6252 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6254 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6255 pos_mode = mode_for_extraction (EP_extzv, 3);
6256 extraction_mode = mode_for_extraction (EP_extzv, 0);
6259 if (! in_dest && ! unsignedp
6260 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6262 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6263 pos_mode = mode_for_extraction (EP_extv, 3);
6264 extraction_mode = mode_for_extraction (EP_extv, 0);
6267 /* Never narrow an object, since that might not be safe. */
6269 if (mode != VOIDmode
6270 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6271 extraction_mode = mode;
6273 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6274 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6275 pos_mode = GET_MODE (pos_rtx);
6277 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6278 if we have to change the mode of memory and cannot, the desired mode is
6279 EXTRACTION_MODE. */
6280 if (GET_CODE (inner) != MEM)
6281 wanted_inner_mode = wanted_inner_reg_mode;
6282 else if (inner_mode != wanted_inner_mode
6283 && (mode_dependent_address_p (XEXP (inner, 0))
6284 || MEM_VOLATILE_P (inner)))
6285 wanted_inner_mode = extraction_mode;
6287 orig_pos = pos;
6289 if (BITS_BIG_ENDIAN)
6291 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6292 BITS_BIG_ENDIAN style. If position is constant, compute new
6293 position. Otherwise, build subtraction.
6294 Note that POS is relative to the mode of the original argument.
6295 If it's a MEM we need to recompute POS relative to that.
6296 However, if we're extracting from (or inserting into) a register,
6297 we want to recompute POS relative to wanted_inner_mode. */
6298 int width = (GET_CODE (inner) == MEM
6299 ? GET_MODE_BITSIZE (is_mode)
6300 : GET_MODE_BITSIZE (wanted_inner_mode));
6302 if (pos_rtx == 0)
6303 pos = width - len - pos;
6304 else
6305 pos_rtx
6306 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6307 /* POS may be less than 0 now, but we check for that below.
6308 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6311 /* If INNER has a wider mode, make it smaller. If this is a constant
6312 extract, try to adjust the byte to point to the byte containing
6313 the value. */
6314 if (wanted_inner_mode != VOIDmode
6315 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6316 && ((GET_CODE (inner) == MEM
6317 && (inner_mode == wanted_inner_mode
6318 || (! mode_dependent_address_p (XEXP (inner, 0))
6319 && ! MEM_VOLATILE_P (inner))))))
6321 int offset = 0;
6323 /* The computations below will be correct if the machine is big
6324 endian in both bits and bytes or little endian in bits and bytes.
6325 If it is mixed, we must adjust. */
6327 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6328 adjust OFFSET to compensate. */
6329 if (BYTES_BIG_ENDIAN
6330 && ! spans_byte
6331 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6332 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6334 /* If this is a constant position, we can move to the desired byte. */
6335 if (pos_rtx == 0)
6337 offset += pos / BITS_PER_UNIT;
6338 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6341 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6342 && ! spans_byte
6343 && is_mode != wanted_inner_mode)
6344 offset = (GET_MODE_SIZE (is_mode)
6345 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6347 if (offset != 0 || inner_mode != wanted_inner_mode)
6348 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6351 /* If INNER is not memory, we can always get it into the proper mode. If we
6352 are changing its mode, POS must be a constant and smaller than the size
6353 of the new mode. */
6354 else if (GET_CODE (inner) != MEM)
6356 if (GET_MODE (inner) != wanted_inner_mode
6357 && (pos_rtx != 0
6358 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6359 return 0;
6361 inner = force_to_mode (inner, wanted_inner_mode,
6362 pos_rtx
6363 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6364 ? ~(unsigned HOST_WIDE_INT) 0
6365 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6366 << orig_pos),
6367 NULL_RTX, 0);
6370 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6371 have to zero extend. Otherwise, we can just use a SUBREG. */
6372 if (pos_rtx != 0
6373 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6375 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6377 /* If we know that no extraneous bits are set, and that the high
6378 bit is not set, convert extraction to cheaper one - either
6379 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6380 cases. */
6381 if (flag_expensive_optimizations
6382 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6383 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6384 & ~(((unsigned HOST_WIDE_INT)
6385 GET_MODE_MASK (GET_MODE (pos_rtx)))
6386 >> 1))
6387 == 0)))
6389 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6391 /* Prefer ZERO_EXTENSION, since it gives more information to
6392 backends. */
6393 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6394 temp = temp1;
6396 pos_rtx = temp;
6398 else if (pos_rtx != 0
6399 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6400 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6402 /* Make POS_RTX unless we already have it and it is correct. If we don't
6403 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6404 be a CONST_INT. */
6405 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6406 pos_rtx = orig_pos_rtx;
6408 else if (pos_rtx == 0)
6409 pos_rtx = GEN_INT (pos);
6411 /* Make the required operation. See if we can use existing rtx. */
6412 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6413 extraction_mode, inner, GEN_INT (len), pos_rtx);
6414 if (! in_dest)
6415 new = gen_lowpart_for_combine (mode, new);
6417 return new;
6420 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6421 with any other operations in X. Return X without that shift if so. */
6423 static rtx
6424 extract_left_shift (rtx x, int count)
6426 enum rtx_code code = GET_CODE (x);
6427 enum machine_mode mode = GET_MODE (x);
6428 rtx tem;
6430 switch (code)
6432 case ASHIFT:
6433 /* This is the shift itself. If it is wide enough, we will return
6434 either the value being shifted if the shift count is equal to
6435 COUNT or a shift for the difference. */
6436 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6437 && INTVAL (XEXP (x, 1)) >= count)
6438 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6439 INTVAL (XEXP (x, 1)) - count);
6440 break;
6442 case NEG: case NOT:
6443 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6444 return simplify_gen_unary (code, mode, tem, mode);
6446 break;
6448 case PLUS: case IOR: case XOR: case AND:
6449 /* If we can safely shift this constant and we find the inner shift,
6450 make a new operation. */
6451 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6452 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6453 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6454 return gen_binary (code, mode, tem,
6455 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6457 break;
6459 default:
6460 break;
6463 return 0;
6466 /* Look at the expression rooted at X. Look for expressions
6467 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6468 Form these expressions.
6470 Return the new rtx, usually just X.
6472 Also, for machines like the VAX that don't have logical shift insns,
6473 try to convert logical to arithmetic shift operations in cases where
6474 they are equivalent. This undoes the canonicalizations to logical
6475 shifts done elsewhere.
6477 We try, as much as possible, to re-use rtl expressions to save memory.
6479 IN_CODE says what kind of expression we are processing. Normally, it is
6480 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6481 being kludges), it is MEM. When processing the arguments of a comparison
6482 or a COMPARE against zero, it is COMPARE. */
6484 static rtx
6485 make_compound_operation (rtx x, enum rtx_code in_code)
6487 enum rtx_code code = GET_CODE (x);
6488 enum machine_mode mode = GET_MODE (x);
6489 int mode_width = GET_MODE_BITSIZE (mode);
6490 rtx rhs, lhs;
6491 enum rtx_code next_code;
6492 int i;
6493 rtx new = 0;
6494 rtx tem;
6495 const char *fmt;
6497 /* Select the code to be used in recursive calls. Once we are inside an
6498 address, we stay there. If we have a comparison, set to COMPARE,
6499 but once inside, go back to our default of SET. */
6501 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6502 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6503 && XEXP (x, 1) == const0_rtx) ? COMPARE
6504 : in_code == COMPARE ? SET : in_code);
6506 /* Process depending on the code of this operation. If NEW is set
6507 nonzero, it will be returned. */
6509 switch (code)
6511 case ASHIFT:
6512 /* Convert shifts by constants into multiplications if inside
6513 an address. */
6514 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6515 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6516 && INTVAL (XEXP (x, 1)) >= 0)
6518 new = make_compound_operation (XEXP (x, 0), next_code);
6519 new = gen_rtx_MULT (mode, new,
6520 GEN_INT ((HOST_WIDE_INT) 1
6521 << INTVAL (XEXP (x, 1))));
6523 break;
6525 case AND:
6526 /* If the second operand is not a constant, we can't do anything
6527 with it. */
6528 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6529 break;
6531 /* If the constant is a power of two minus one and the first operand
6532 is a logical right shift, make an extraction. */
6533 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6534 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6536 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6537 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6538 0, in_code == COMPARE);
6541 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6542 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6543 && subreg_lowpart_p (XEXP (x, 0))
6544 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6545 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6547 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6548 next_code);
6549 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6550 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6551 0, in_code == COMPARE);
6553 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6554 else if ((GET_CODE (XEXP (x, 0)) == XOR
6555 || GET_CODE (XEXP (x, 0)) == IOR)
6556 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6557 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6558 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6560 /* Apply the distributive law, and then try to make extractions. */
6561 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6562 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6563 XEXP (x, 1)),
6564 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6565 XEXP (x, 1)));
6566 new = make_compound_operation (new, in_code);
6569 /* If we are have (and (rotate X C) M) and C is larger than the number
6570 of bits in M, this is an extraction. */
6572 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6573 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6574 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6575 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6577 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6578 new = make_extraction (mode, new,
6579 (GET_MODE_BITSIZE (mode)
6580 - INTVAL (XEXP (XEXP (x, 0), 1))),
6581 NULL_RTX, i, 1, 0, in_code == COMPARE);
6584 /* On machines without logical shifts, if the operand of the AND is
6585 a logical shift and our mask turns off all the propagated sign
6586 bits, we can replace the logical shift with an arithmetic shift. */
6587 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6588 && !have_insn_for (LSHIFTRT, mode)
6589 && have_insn_for (ASHIFTRT, mode)
6590 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6591 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6592 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6593 && mode_width <= HOST_BITS_PER_WIDE_INT)
6595 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6597 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6598 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6599 SUBST (XEXP (x, 0),
6600 gen_rtx_ASHIFTRT (mode,
6601 make_compound_operation
6602 (XEXP (XEXP (x, 0), 0), next_code),
6603 XEXP (XEXP (x, 0), 1)));
6606 /* If the constant is one less than a power of two, this might be
6607 representable by an extraction even if no shift is present.
6608 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6609 we are in a COMPARE. */
6610 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6611 new = make_extraction (mode,
6612 make_compound_operation (XEXP (x, 0),
6613 next_code),
6614 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6616 /* If we are in a comparison and this is an AND with a power of two,
6617 convert this into the appropriate bit extract. */
6618 else if (in_code == COMPARE
6619 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6620 new = make_extraction (mode,
6621 make_compound_operation (XEXP (x, 0),
6622 next_code),
6623 i, NULL_RTX, 1, 1, 0, 1);
6625 break;
6627 case LSHIFTRT:
6628 /* If the sign bit is known to be zero, replace this with an
6629 arithmetic shift. */
6630 if (have_insn_for (ASHIFTRT, mode)
6631 && ! have_insn_for (LSHIFTRT, mode)
6632 && mode_width <= HOST_BITS_PER_WIDE_INT
6633 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6635 new = gen_rtx_ASHIFTRT (mode,
6636 make_compound_operation (XEXP (x, 0),
6637 next_code),
6638 XEXP (x, 1));
6639 break;
6642 /* ... fall through ... */
6644 case ASHIFTRT:
6645 lhs = XEXP (x, 0);
6646 rhs = XEXP (x, 1);
6648 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6649 this is a SIGN_EXTRACT. */
6650 if (GET_CODE (rhs) == CONST_INT
6651 && GET_CODE (lhs) == ASHIFT
6652 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6653 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6655 new = make_compound_operation (XEXP (lhs, 0), next_code);
6656 new = make_extraction (mode, new,
6657 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6658 NULL_RTX, mode_width - INTVAL (rhs),
6659 code == LSHIFTRT, 0, in_code == COMPARE);
6660 break;
6663 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6664 If so, try to merge the shifts into a SIGN_EXTEND. We could
6665 also do this for some cases of SIGN_EXTRACT, but it doesn't
6666 seem worth the effort; the case checked for occurs on Alpha. */
6668 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6669 && ! (GET_CODE (lhs) == SUBREG
6670 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6671 && GET_CODE (rhs) == CONST_INT
6672 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6673 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6674 new = make_extraction (mode, make_compound_operation (new, next_code),
6675 0, NULL_RTX, mode_width - INTVAL (rhs),
6676 code == LSHIFTRT, 0, in_code == COMPARE);
6678 break;
6680 case SUBREG:
6681 /* Call ourselves recursively on the inner expression. If we are
6682 narrowing the object and it has a different RTL code from
6683 what it originally did, do this SUBREG as a force_to_mode. */
6685 tem = make_compound_operation (SUBREG_REG (x), in_code);
6686 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6687 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6688 && subreg_lowpart_p (x))
6690 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6691 NULL_RTX, 0);
6693 /* If we have something other than a SUBREG, we might have
6694 done an expansion, so rerun ourselves. */
6695 if (GET_CODE (newer) != SUBREG)
6696 newer = make_compound_operation (newer, in_code);
6698 return newer;
6701 /* If this is a paradoxical subreg, and the new code is a sign or
6702 zero extension, omit the subreg and widen the extension. If it
6703 is a regular subreg, we can still get rid of the subreg by not
6704 widening so much, or in fact removing the extension entirely. */
6705 if ((GET_CODE (tem) == SIGN_EXTEND
6706 || GET_CODE (tem) == ZERO_EXTEND)
6707 && subreg_lowpart_p (x))
6709 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6710 || (GET_MODE_SIZE (mode) >
6711 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6713 if (! SCALAR_INT_MODE_P (mode))
6714 break;
6715 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6717 else
6718 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6719 return tem;
6721 break;
6723 default:
6724 break;
6727 if (new)
6729 x = gen_lowpart_for_combine (mode, new);
6730 code = GET_CODE (x);
6733 /* Now recursively process each operand of this operation. */
6734 fmt = GET_RTX_FORMAT (code);
6735 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6736 if (fmt[i] == 'e')
6738 new = make_compound_operation (XEXP (x, i), next_code);
6739 SUBST (XEXP (x, i), new);
6742 return x;
6745 /* Given M see if it is a value that would select a field of bits
6746 within an item, but not the entire word. Return -1 if not.
6747 Otherwise, return the starting position of the field, where 0 is the
6748 low-order bit.
6750 *PLEN is set to the length of the field. */
6752 static int
6753 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6755 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6756 int pos = exact_log2 (m & -m);
6757 int len;
6759 if (pos < 0)
6760 return -1;
6762 /* Now shift off the low-order zero bits and see if we have a power of
6763 two minus 1. */
6764 len = exact_log2 ((m >> pos) + 1);
6766 if (len <= 0)
6767 return -1;
6769 *plen = len;
6770 return pos;
6773 /* See if X can be simplified knowing that we will only refer to it in
6774 MODE and will only refer to those bits that are nonzero in MASK.
6775 If other bits are being computed or if masking operations are done
6776 that select a superset of the bits in MASK, they can sometimes be
6777 ignored.
6779 Return a possibly simplified expression, but always convert X to
6780 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6782 Also, if REG is nonzero and X is a register equal in value to REG,
6783 replace X with REG.
6785 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6786 are all off in X. This is used when X will be complemented, by either
6787 NOT, NEG, or XOR. */
6789 static rtx
6790 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6791 rtx reg, int just_select)
6793 enum rtx_code code = GET_CODE (x);
6794 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6795 enum machine_mode op_mode;
6796 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6797 rtx op0, op1, temp;
6799 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6800 code below will do the wrong thing since the mode of such an
6801 expression is VOIDmode.
6803 Also do nothing if X is a CLOBBER; this can happen if X was
6804 the return value from a call to gen_lowpart_for_combine. */
6805 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6806 return x;
6808 /* We want to perform the operation is its present mode unless we know
6809 that the operation is valid in MODE, in which case we do the operation
6810 in MODE. */
6811 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6812 && have_insn_for (code, mode))
6813 ? mode : GET_MODE (x));
6815 /* It is not valid to do a right-shift in a narrower mode
6816 than the one it came in with. */
6817 if ((code == LSHIFTRT || code == ASHIFTRT)
6818 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6819 op_mode = GET_MODE (x);
6821 /* Truncate MASK to fit OP_MODE. */
6822 if (op_mode)
6823 mask &= GET_MODE_MASK (op_mode);
6825 /* When we have an arithmetic operation, or a shift whose count we
6826 do not know, we need to assume that all bit the up to the highest-order
6827 bit in MASK will be needed. This is how we form such a mask. */
6828 if (op_mode)
6829 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6830 ? GET_MODE_MASK (op_mode)
6831 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6832 - 1));
6833 else
6834 fuller_mask = ~(HOST_WIDE_INT) 0;
6836 /* Determine what bits of X are guaranteed to be (non)zero. */
6837 nonzero = nonzero_bits (x, mode);
6839 /* If none of the bits in X are needed, return a zero. */
6840 if (! just_select && (nonzero & mask) == 0)
6841 x = const0_rtx;
6843 /* If X is a CONST_INT, return a new one. Do this here since the
6844 test below will fail. */
6845 if (GET_CODE (x) == CONST_INT)
6847 if (SCALAR_INT_MODE_P (mode))
6848 return gen_int_mode (INTVAL (x) & mask, mode);
6849 else
6851 x = GEN_INT (INTVAL (x) & mask);
6852 return gen_lowpart_common (mode, x);
6856 /* If X is narrower than MODE and we want all the bits in X's mode, just
6857 get X in the proper mode. */
6858 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6859 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6860 return gen_lowpart_for_combine (mode, x);
6862 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6863 MASK are already known to be zero in X, we need not do anything. */
6864 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6865 return x;
6867 switch (code)
6869 case CLOBBER:
6870 /* If X is a (clobber (const_int)), return it since we know we are
6871 generating something that won't match. */
6872 return x;
6874 case USE:
6875 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6876 spanned the boundary of the MEM. If we are now masking so it is
6877 within that boundary, we don't need the USE any more. */
6878 if (! BITS_BIG_ENDIAN
6879 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6880 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6881 break;
6883 case SIGN_EXTEND:
6884 case ZERO_EXTEND:
6885 case ZERO_EXTRACT:
6886 case SIGN_EXTRACT:
6887 x = expand_compound_operation (x);
6888 if (GET_CODE (x) != code)
6889 return force_to_mode (x, mode, mask, reg, next_select);
6890 break;
6892 case REG:
6893 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6894 || rtx_equal_p (reg, get_last_value (x))))
6895 x = reg;
6896 break;
6898 case SUBREG:
6899 if (subreg_lowpart_p (x)
6900 /* We can ignore the effect of this SUBREG if it narrows the mode or
6901 if the constant masks to zero all the bits the mode doesn't
6902 have. */
6903 && ((GET_MODE_SIZE (GET_MODE (x))
6904 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6905 || (0 == (mask
6906 & GET_MODE_MASK (GET_MODE (x))
6907 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6908 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6909 break;
6911 case AND:
6912 /* If this is an AND with a constant, convert it into an AND
6913 whose constant is the AND of that constant with MASK. If it
6914 remains an AND of MASK, delete it since it is redundant. */
6916 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6918 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6919 mask & INTVAL (XEXP (x, 1)));
6921 /* If X is still an AND, see if it is an AND with a mask that
6922 is just some low-order bits. If so, and it is MASK, we don't
6923 need it. */
6925 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6926 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6927 == mask))
6928 x = XEXP (x, 0);
6930 /* If it remains an AND, try making another AND with the bits
6931 in the mode mask that aren't in MASK turned on. If the
6932 constant in the AND is wide enough, this might make a
6933 cheaper constant. */
6935 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6936 && GET_MODE_MASK (GET_MODE (x)) != mask
6937 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6939 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6940 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6941 int width = GET_MODE_BITSIZE (GET_MODE (x));
6942 rtx y;
6944 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6945 number, sign extend it. */
6946 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6947 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6948 cval |= (HOST_WIDE_INT) -1 << width;
6950 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6951 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6952 x = y;
6955 break;
6958 goto binop;
6960 case PLUS:
6961 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6962 low-order bits (as in an alignment operation) and FOO is already
6963 aligned to that boundary, mask C1 to that boundary as well.
6964 This may eliminate that PLUS and, later, the AND. */
6967 unsigned int width = GET_MODE_BITSIZE (mode);
6968 unsigned HOST_WIDE_INT smask = mask;
6970 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6971 number, sign extend it. */
6973 if (width < HOST_BITS_PER_WIDE_INT
6974 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6975 smask |= (HOST_WIDE_INT) -1 << width;
6977 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6978 && exact_log2 (- smask) >= 0
6979 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6980 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6981 return force_to_mode (plus_constant (XEXP (x, 0),
6982 (INTVAL (XEXP (x, 1)) & smask)),
6983 mode, smask, reg, next_select);
6986 /* ... fall through ... */
6988 case MULT:
6989 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6990 most significant bit in MASK since carries from those bits will
6991 affect the bits we are interested in. */
6992 mask = fuller_mask;
6993 goto binop;
6995 case MINUS:
6996 /* If X is (minus C Y) where C's least set bit is larger than any bit
6997 in the mask, then we may replace with (neg Y). */
6998 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6999 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7000 & -INTVAL (XEXP (x, 0))))
7001 > mask))
7003 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7004 GET_MODE (x));
7005 return force_to_mode (x, mode, mask, reg, next_select);
7008 /* Similarly, if C contains every bit in the fuller_mask, then we may
7009 replace with (not Y). */
7010 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7011 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7012 == INTVAL (XEXP (x, 0))))
7014 x = simplify_gen_unary (NOT, GET_MODE (x),
7015 XEXP (x, 1), GET_MODE (x));
7016 return force_to_mode (x, mode, mask, reg, next_select);
7019 mask = fuller_mask;
7020 goto binop;
7022 case IOR:
7023 case XOR:
7024 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7025 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7026 operation which may be a bitfield extraction. Ensure that the
7027 constant we form is not wider than the mode of X. */
7029 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7030 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7031 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7032 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7033 && GET_CODE (XEXP (x, 1)) == CONST_INT
7034 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7035 + floor_log2 (INTVAL (XEXP (x, 1))))
7036 < GET_MODE_BITSIZE (GET_MODE (x)))
7037 && (INTVAL (XEXP (x, 1))
7038 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7040 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7041 << INTVAL (XEXP (XEXP (x, 0), 1)));
7042 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7043 XEXP (XEXP (x, 0), 0), temp);
7044 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7045 XEXP (XEXP (x, 0), 1));
7046 return force_to_mode (x, mode, mask, reg, next_select);
7049 binop:
7050 /* For most binary operations, just propagate into the operation and
7051 change the mode if we have an operation of that mode. */
7053 op0 = gen_lowpart_for_combine (op_mode,
7054 force_to_mode (XEXP (x, 0), mode, mask,
7055 reg, next_select));
7056 op1 = gen_lowpart_for_combine (op_mode,
7057 force_to_mode (XEXP (x, 1), mode, mask,
7058 reg, next_select));
7060 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7061 x = gen_binary (code, op_mode, op0, op1);
7062 break;
7064 case ASHIFT:
7065 /* For left shifts, do the same, but just for the first operand.
7066 However, we cannot do anything with shifts where we cannot
7067 guarantee that the counts are smaller than the size of the mode
7068 because such a count will have a different meaning in a
7069 wider mode. */
7071 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7072 && INTVAL (XEXP (x, 1)) >= 0
7073 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7074 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7075 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7076 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7077 break;
7079 /* If the shift count is a constant and we can do arithmetic in
7080 the mode of the shift, refine which bits we need. Otherwise, use the
7081 conservative form of the mask. */
7082 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7083 && INTVAL (XEXP (x, 1)) >= 0
7084 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7085 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7086 mask >>= INTVAL (XEXP (x, 1));
7087 else
7088 mask = fuller_mask;
7090 op0 = gen_lowpart_for_combine (op_mode,
7091 force_to_mode (XEXP (x, 0), op_mode,
7092 mask, reg, next_select));
7094 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7095 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7096 break;
7098 case LSHIFTRT:
7099 /* Here we can only do something if the shift count is a constant,
7100 this shift constant is valid for the host, and we can do arithmetic
7101 in OP_MODE. */
7103 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7104 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7105 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7107 rtx inner = XEXP (x, 0);
7108 unsigned HOST_WIDE_INT inner_mask;
7110 /* Select the mask of the bits we need for the shift operand. */
7111 inner_mask = mask << INTVAL (XEXP (x, 1));
7113 /* We can only change the mode of the shift if we can do arithmetic
7114 in the mode of the shift and INNER_MASK is no wider than the
7115 width of OP_MODE. */
7116 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7117 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7118 op_mode = GET_MODE (x);
7120 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7122 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7123 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7126 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7127 shift and AND produces only copies of the sign bit (C2 is one less
7128 than a power of two), we can do this with just a shift. */
7130 if (GET_CODE (x) == LSHIFTRT
7131 && GET_CODE (XEXP (x, 1)) == CONST_INT
7132 /* The shift puts one of the sign bit copies in the least significant
7133 bit. */
7134 && ((INTVAL (XEXP (x, 1))
7135 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7136 >= GET_MODE_BITSIZE (GET_MODE (x)))
7137 && exact_log2 (mask + 1) >= 0
7138 /* Number of bits left after the shift must be more than the mask
7139 needs. */
7140 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7141 <= GET_MODE_BITSIZE (GET_MODE (x)))
7142 /* Must be more sign bit copies than the mask needs. */
7143 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7144 >= exact_log2 (mask + 1)))
7145 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7146 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7147 - exact_log2 (mask + 1)));
7149 goto shiftrt;
7151 case ASHIFTRT:
7152 /* If we are just looking for the sign bit, we don't need this shift at
7153 all, even if it has a variable count. */
7154 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7155 && (mask == ((unsigned HOST_WIDE_INT) 1
7156 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7157 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7159 /* If this is a shift by a constant, get a mask that contains those bits
7160 that are not copies of the sign bit. We then have two cases: If
7161 MASK only includes those bits, this can be a logical shift, which may
7162 allow simplifications. If MASK is a single-bit field not within
7163 those bits, we are requesting a copy of the sign bit and hence can
7164 shift the sign bit to the appropriate location. */
7166 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7167 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7169 int i = -1;
7171 /* If the considered data is wider than HOST_WIDE_INT, we can't
7172 represent a mask for all its bits in a single scalar.
7173 But we only care about the lower bits, so calculate these. */
7175 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7177 nonzero = ~(HOST_WIDE_INT) 0;
7179 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7180 is the number of bits a full-width mask would have set.
7181 We need only shift if these are fewer than nonzero can
7182 hold. If not, we must keep all bits set in nonzero. */
7184 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7185 < HOST_BITS_PER_WIDE_INT)
7186 nonzero >>= INTVAL (XEXP (x, 1))
7187 + HOST_BITS_PER_WIDE_INT
7188 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7190 else
7192 nonzero = GET_MODE_MASK (GET_MODE (x));
7193 nonzero >>= INTVAL (XEXP (x, 1));
7196 if ((mask & ~nonzero) == 0
7197 || (i = exact_log2 (mask)) >= 0)
7199 x = simplify_shift_const
7200 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7201 i < 0 ? INTVAL (XEXP (x, 1))
7202 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7204 if (GET_CODE (x) != ASHIFTRT)
7205 return force_to_mode (x, mode, mask, reg, next_select);
7209 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7210 even if the shift count isn't a constant. */
7211 if (mask == 1)
7212 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7214 shiftrt:
7216 /* If this is a zero- or sign-extension operation that just affects bits
7217 we don't care about, remove it. Be sure the call above returned
7218 something that is still a shift. */
7220 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7221 && GET_CODE (XEXP (x, 1)) == CONST_INT
7222 && INTVAL (XEXP (x, 1)) >= 0
7223 && (INTVAL (XEXP (x, 1))
7224 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7225 && GET_CODE (XEXP (x, 0)) == ASHIFT
7226 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7227 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7228 reg, next_select);
7230 break;
7232 case ROTATE:
7233 case ROTATERT:
7234 /* If the shift count is constant and we can do computations
7235 in the mode of X, compute where the bits we care about are.
7236 Otherwise, we can't do anything. Don't change the mode of
7237 the shift or propagate MODE into the shift, though. */
7238 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7239 && INTVAL (XEXP (x, 1)) >= 0)
7241 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7242 GET_MODE (x), GEN_INT (mask),
7243 XEXP (x, 1));
7244 if (temp && GET_CODE (temp) == CONST_INT)
7245 SUBST (XEXP (x, 0),
7246 force_to_mode (XEXP (x, 0), GET_MODE (x),
7247 INTVAL (temp), reg, next_select));
7249 break;
7251 case NEG:
7252 /* If we just want the low-order bit, the NEG isn't needed since it
7253 won't change the low-order bit. */
7254 if (mask == 1)
7255 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7257 /* We need any bits less significant than the most significant bit in
7258 MASK since carries from those bits will affect the bits we are
7259 interested in. */
7260 mask = fuller_mask;
7261 goto unop;
7263 case NOT:
7264 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7265 same as the XOR case above. Ensure that the constant we form is not
7266 wider than the mode of X. */
7268 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7269 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7270 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7271 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7272 < GET_MODE_BITSIZE (GET_MODE (x)))
7273 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7275 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7276 GET_MODE (x));
7277 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7278 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7280 return force_to_mode (x, mode, mask, reg, next_select);
7283 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7284 use the full mask inside the NOT. */
7285 mask = fuller_mask;
7287 unop:
7288 op0 = gen_lowpart_for_combine (op_mode,
7289 force_to_mode (XEXP (x, 0), mode, mask,
7290 reg, next_select));
7291 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7292 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7293 break;
7295 case NE:
7296 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7297 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7298 which is equal to STORE_FLAG_VALUE. */
7299 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7300 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7301 && (nonzero_bits (XEXP (x, 0), mode)
7302 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7303 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7305 break;
7307 case IF_THEN_ELSE:
7308 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7309 written in a narrower mode. We play it safe and do not do so. */
7311 SUBST (XEXP (x, 1),
7312 gen_lowpart_for_combine (GET_MODE (x),
7313 force_to_mode (XEXP (x, 1), mode,
7314 mask, reg, next_select)));
7315 SUBST (XEXP (x, 2),
7316 gen_lowpart_for_combine (GET_MODE (x),
7317 force_to_mode (XEXP (x, 2), mode,
7318 mask, reg, next_select)));
7319 break;
7321 default:
7322 break;
7325 /* Ensure we return a value of the proper mode. */
7326 return gen_lowpart_for_combine (mode, x);
7329 /* Return nonzero if X is an expression that has one of two values depending on
7330 whether some other value is zero or nonzero. In that case, we return the
7331 value that is being tested, *PTRUE is set to the value if the rtx being
7332 returned has a nonzero value, and *PFALSE is set to the other alternative.
7334 If we return zero, we set *PTRUE and *PFALSE to X. */
7336 static rtx
7337 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7339 enum machine_mode mode = GET_MODE (x);
7340 enum rtx_code code = GET_CODE (x);
7341 rtx cond0, cond1, true0, true1, false0, false1;
7342 unsigned HOST_WIDE_INT nz;
7344 /* If we are comparing a value against zero, we are done. */
7345 if ((code == NE || code == EQ)
7346 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7348 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7349 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7350 return XEXP (x, 0);
7353 /* If this is a unary operation whose operand has one of two values, apply
7354 our opcode to compute those values. */
7355 else if (GET_RTX_CLASS (code) == '1'
7356 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7358 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7359 *pfalse = simplify_gen_unary (code, mode, false0,
7360 GET_MODE (XEXP (x, 0)));
7361 return cond0;
7364 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7365 make can't possibly match and would suppress other optimizations. */
7366 else if (code == COMPARE)
7369 /* If this is a binary operation, see if either side has only one of two
7370 values. If either one does or if both do and they are conditional on
7371 the same value, compute the new true and false values. */
7372 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7373 || GET_RTX_CLASS (code) == '<')
7375 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7376 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7378 if ((cond0 != 0 || cond1 != 0)
7379 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7381 /* If if_then_else_cond returned zero, then true/false are the
7382 same rtl. We must copy one of them to prevent invalid rtl
7383 sharing. */
7384 if (cond0 == 0)
7385 true0 = copy_rtx (true0);
7386 else if (cond1 == 0)
7387 true1 = copy_rtx (true1);
7389 *ptrue = gen_binary (code, mode, true0, true1);
7390 *pfalse = gen_binary (code, mode, false0, false1);
7391 return cond0 ? cond0 : cond1;
7394 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7395 operands is zero when the other is nonzero, and vice-versa,
7396 and STORE_FLAG_VALUE is 1 or -1. */
7398 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7399 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7400 || code == UMAX)
7401 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7403 rtx op0 = XEXP (XEXP (x, 0), 1);
7404 rtx op1 = XEXP (XEXP (x, 1), 1);
7406 cond0 = XEXP (XEXP (x, 0), 0);
7407 cond1 = XEXP (XEXP (x, 1), 0);
7409 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7410 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7411 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7412 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7413 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7414 || ((swap_condition (GET_CODE (cond0))
7415 == combine_reversed_comparison_code (cond1))
7416 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7417 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7418 && ! side_effects_p (x))
7420 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7421 *pfalse = gen_binary (MULT, mode,
7422 (code == MINUS
7423 ? simplify_gen_unary (NEG, mode, op1,
7424 mode)
7425 : op1),
7426 const_true_rtx);
7427 return cond0;
7431 /* Similarly for MULT, AND and UMIN, except that for these the result
7432 is always zero. */
7433 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7434 && (code == MULT || code == AND || code == UMIN)
7435 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7437 cond0 = XEXP (XEXP (x, 0), 0);
7438 cond1 = XEXP (XEXP (x, 1), 0);
7440 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7441 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7442 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7443 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7444 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7445 || ((swap_condition (GET_CODE (cond0))
7446 == combine_reversed_comparison_code (cond1))
7447 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7448 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7449 && ! side_effects_p (x))
7451 *ptrue = *pfalse = const0_rtx;
7452 return cond0;
7457 else if (code == IF_THEN_ELSE)
7459 /* If we have IF_THEN_ELSE already, extract the condition and
7460 canonicalize it if it is NE or EQ. */
7461 cond0 = XEXP (x, 0);
7462 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7463 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7464 return XEXP (cond0, 0);
7465 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7467 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7468 return XEXP (cond0, 0);
7470 else
7471 return cond0;
7474 /* If X is a SUBREG, we can narrow both the true and false values
7475 if the inner expression, if there is a condition. */
7476 else if (code == SUBREG
7477 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7478 &true0, &false0)))
7480 *ptrue = simplify_gen_subreg (mode, true0,
7481 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7482 *pfalse = simplify_gen_subreg (mode, false0,
7483 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7485 return cond0;
7488 /* If X is a constant, this isn't special and will cause confusions
7489 if we treat it as such. Likewise if it is equivalent to a constant. */
7490 else if (CONSTANT_P (x)
7491 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7494 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7495 will be least confusing to the rest of the compiler. */
7496 else if (mode == BImode)
7498 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7499 return x;
7502 /* If X is known to be either 0 or -1, those are the true and
7503 false values when testing X. */
7504 else if (x == constm1_rtx || x == const0_rtx
7505 || (mode != VOIDmode
7506 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7508 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7509 return x;
7512 /* Likewise for 0 or a single bit. */
7513 else if (mode != VOIDmode
7514 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7515 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7517 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7518 return x;
7521 /* Otherwise fail; show no condition with true and false values the same. */
7522 *ptrue = *pfalse = x;
7523 return 0;
7526 /* Return the value of expression X given the fact that condition COND
7527 is known to be true when applied to REG as its first operand and VAL
7528 as its second. X is known to not be shared and so can be modified in
7529 place.
7531 We only handle the simplest cases, and specifically those cases that
7532 arise with IF_THEN_ELSE expressions. */
7534 static rtx
7535 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7537 enum rtx_code code = GET_CODE (x);
7538 rtx temp;
7539 const char *fmt;
7540 int i, j;
7542 if (side_effects_p (x))
7543 return x;
7545 /* If either operand of the condition is a floating point value,
7546 then we have to avoid collapsing an EQ comparison. */
7547 if (cond == EQ
7548 && rtx_equal_p (x, reg)
7549 && ! FLOAT_MODE_P (GET_MODE (x))
7550 && ! FLOAT_MODE_P (GET_MODE (val)))
7551 return val;
7553 if (cond == UNEQ && rtx_equal_p (x, reg))
7554 return val;
7556 /* If X is (abs REG) and we know something about REG's relationship
7557 with zero, we may be able to simplify this. */
7559 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7560 switch (cond)
7562 case GE: case GT: case EQ:
7563 return XEXP (x, 0);
7564 case LT: case LE:
7565 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7566 XEXP (x, 0),
7567 GET_MODE (XEXP (x, 0)));
7568 default:
7569 break;
7572 /* The only other cases we handle are MIN, MAX, and comparisons if the
7573 operands are the same as REG and VAL. */
7575 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7577 if (rtx_equal_p (XEXP (x, 0), val))
7578 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7580 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7582 if (GET_RTX_CLASS (code) == '<')
7584 if (comparison_dominates_p (cond, code))
7585 return const_true_rtx;
7587 code = combine_reversed_comparison_code (x);
7588 if (code != UNKNOWN
7589 && comparison_dominates_p (cond, code))
7590 return const0_rtx;
7591 else
7592 return x;
7594 else if (code == SMAX || code == SMIN
7595 || code == UMIN || code == UMAX)
7597 int unsignedp = (code == UMIN || code == UMAX);
7599 /* Do not reverse the condition when it is NE or EQ.
7600 This is because we cannot conclude anything about
7601 the value of 'SMAX (x, y)' when x is not equal to y,
7602 but we can when x equals y. */
7603 if ((code == SMAX || code == UMAX)
7604 && ! (cond == EQ || cond == NE))
7605 cond = reverse_condition (cond);
7607 switch (cond)
7609 case GE: case GT:
7610 return unsignedp ? x : XEXP (x, 1);
7611 case LE: case LT:
7612 return unsignedp ? x : XEXP (x, 0);
7613 case GEU: case GTU:
7614 return unsignedp ? XEXP (x, 1) : x;
7615 case LEU: case LTU:
7616 return unsignedp ? XEXP (x, 0) : x;
7617 default:
7618 break;
7623 else if (code == SUBREG)
7625 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7626 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7628 if (SUBREG_REG (x) != r)
7630 /* We must simplify subreg here, before we lose track of the
7631 original inner_mode. */
7632 new = simplify_subreg (GET_MODE (x), r,
7633 inner_mode, SUBREG_BYTE (x));
7634 if (new)
7635 return new;
7636 else
7637 SUBST (SUBREG_REG (x), r);
7640 return x;
7642 /* We don't have to handle SIGN_EXTEND here, because even in the
7643 case of replacing something with a modeless CONST_INT, a
7644 CONST_INT is already (supposed to be) a valid sign extension for
7645 its narrower mode, which implies it's already properly
7646 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7647 story is different. */
7648 else if (code == ZERO_EXTEND)
7650 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7651 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7653 if (XEXP (x, 0) != r)
7655 /* We must simplify the zero_extend here, before we lose
7656 track of the original inner_mode. */
7657 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7658 r, inner_mode);
7659 if (new)
7660 return new;
7661 else
7662 SUBST (XEXP (x, 0), r);
7665 return x;
7668 fmt = GET_RTX_FORMAT (code);
7669 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7671 if (fmt[i] == 'e')
7672 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7673 else if (fmt[i] == 'E')
7674 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7675 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7676 cond, reg, val));
7679 return x;
7682 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7683 assignment as a field assignment. */
7685 static int
7686 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7688 if (x == y || rtx_equal_p (x, y))
7689 return 1;
7691 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7692 return 0;
7694 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7695 Note that all SUBREGs of MEM are paradoxical; otherwise they
7696 would have been rewritten. */
7697 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7698 && GET_CODE (SUBREG_REG (y)) == MEM
7699 && rtx_equal_p (SUBREG_REG (y),
7700 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7701 return 1;
7703 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7704 && GET_CODE (SUBREG_REG (x)) == MEM
7705 && rtx_equal_p (SUBREG_REG (x),
7706 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7707 return 1;
7709 /* We used to see if get_last_value of X and Y were the same but that's
7710 not correct. In one direction, we'll cause the assignment to have
7711 the wrong destination and in the case, we'll import a register into this
7712 insn that might have already have been dead. So fail if none of the
7713 above cases are true. */
7714 return 0;
7717 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7718 Return that assignment if so.
7720 We only handle the most common cases. */
7722 static rtx
7723 make_field_assignment (rtx x)
7725 rtx dest = SET_DEST (x);
7726 rtx src = SET_SRC (x);
7727 rtx assign;
7728 rtx rhs, lhs;
7729 HOST_WIDE_INT c1;
7730 HOST_WIDE_INT pos;
7731 unsigned HOST_WIDE_INT len;
7732 rtx other;
7733 enum machine_mode mode;
7735 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7736 a clear of a one-bit field. We will have changed it to
7737 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7738 for a SUBREG. */
7740 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7741 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7742 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7743 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7745 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7746 1, 1, 1, 0);
7747 if (assign != 0)
7748 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7749 return x;
7752 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7753 && subreg_lowpart_p (XEXP (src, 0))
7754 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7755 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7756 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7757 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7758 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7760 assign = make_extraction (VOIDmode, dest, 0,
7761 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7762 1, 1, 1, 0);
7763 if (assign != 0)
7764 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7765 return x;
7768 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7769 one-bit field. */
7770 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7771 && XEXP (XEXP (src, 0), 0) == const1_rtx
7772 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7774 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7775 1, 1, 1, 0);
7776 if (assign != 0)
7777 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7778 return x;
7781 /* The other case we handle is assignments into a constant-position
7782 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7783 a mask that has all one bits except for a group of zero bits and
7784 OTHER is known to have zeros where C1 has ones, this is such an
7785 assignment. Compute the position and length from C1. Shift OTHER
7786 to the appropriate position, force it to the required mode, and
7787 make the extraction. Check for the AND in both operands. */
7789 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7790 return x;
7792 rhs = expand_compound_operation (XEXP (src, 0));
7793 lhs = expand_compound_operation (XEXP (src, 1));
7795 if (GET_CODE (rhs) == AND
7796 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7797 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7798 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7799 else if (GET_CODE (lhs) == AND
7800 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7801 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7802 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7803 else
7804 return x;
7806 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7807 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7808 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7809 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7810 return x;
7812 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7813 if (assign == 0)
7814 return x;
7816 /* The mode to use for the source is the mode of the assignment, or of
7817 what is inside a possible STRICT_LOW_PART. */
7818 mode = (GET_CODE (assign) == STRICT_LOW_PART
7819 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7821 /* Shift OTHER right POS places and make it the source, restricting it
7822 to the proper length and mode. */
7824 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7825 GET_MODE (src), other, pos),
7826 mode,
7827 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7828 ? ~(unsigned HOST_WIDE_INT) 0
7829 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7830 dest, 0);
7832 /* If SRC is masked by an AND that does not make a difference in
7833 the value being stored, strip it. */
7834 if (GET_CODE (assign) == ZERO_EXTRACT
7835 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7836 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7837 && GET_CODE (src) == AND
7838 && GET_CODE (XEXP (src, 1)) == CONST_INT
7839 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7840 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7841 src = XEXP (src, 0);
7843 return gen_rtx_SET (VOIDmode, assign, src);
7846 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7847 if so. */
7849 static rtx
7850 apply_distributive_law (rtx x)
7852 enum rtx_code code = GET_CODE (x);
7853 rtx lhs, rhs, other;
7854 rtx tem;
7855 enum rtx_code inner_code;
7857 /* Distributivity is not true for floating point.
7858 It can change the value. So don't do it.
7859 -- rms and moshier@world.std.com. */
7860 if (FLOAT_MODE_P (GET_MODE (x)))
7861 return x;
7863 /* The outer operation can only be one of the following: */
7864 if (code != IOR && code != AND && code != XOR
7865 && code != PLUS && code != MINUS)
7866 return x;
7868 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7870 /* If either operand is a primitive we can't do anything, so get out
7871 fast. */
7872 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7873 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7874 return x;
7876 lhs = expand_compound_operation (lhs);
7877 rhs = expand_compound_operation (rhs);
7878 inner_code = GET_CODE (lhs);
7879 if (inner_code != GET_CODE (rhs))
7880 return x;
7882 /* See if the inner and outer operations distribute. */
7883 switch (inner_code)
7885 case LSHIFTRT:
7886 case ASHIFTRT:
7887 case AND:
7888 case IOR:
7889 /* These all distribute except over PLUS. */
7890 if (code == PLUS || code == MINUS)
7891 return x;
7892 break;
7894 case MULT:
7895 if (code != PLUS && code != MINUS)
7896 return x;
7897 break;
7899 case ASHIFT:
7900 /* This is also a multiply, so it distributes over everything. */
7901 break;
7903 case SUBREG:
7904 /* Non-paradoxical SUBREGs distributes over all operations, provided
7905 the inner modes and byte offsets are the same, this is an extraction
7906 of a low-order part, we don't convert an fp operation to int or
7907 vice versa, and we would not be converting a single-word
7908 operation into a multi-word operation. The latter test is not
7909 required, but it prevents generating unneeded multi-word operations.
7910 Some of the previous tests are redundant given the latter test, but
7911 are retained because they are required for correctness.
7913 We produce the result slightly differently in this case. */
7915 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7916 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7917 || ! subreg_lowpart_p (lhs)
7918 || (GET_MODE_CLASS (GET_MODE (lhs))
7919 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7920 || (GET_MODE_SIZE (GET_MODE (lhs))
7921 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7922 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7923 return x;
7925 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7926 SUBREG_REG (lhs), SUBREG_REG (rhs));
7927 return gen_lowpart_for_combine (GET_MODE (x), tem);
7929 default:
7930 return x;
7933 /* Set LHS and RHS to the inner operands (A and B in the example
7934 above) and set OTHER to the common operand (C in the example).
7935 These is only one way to do this unless the inner operation is
7936 commutative. */
7937 if (GET_RTX_CLASS (inner_code) == 'c'
7938 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7939 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7940 else if (GET_RTX_CLASS (inner_code) == 'c'
7941 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7942 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7943 else if (GET_RTX_CLASS (inner_code) == 'c'
7944 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7945 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7946 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7947 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7948 else
7949 return x;
7951 /* Form the new inner operation, seeing if it simplifies first. */
7952 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7954 /* There is one exception to the general way of distributing:
7955 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7956 if (code == XOR && inner_code == IOR)
7958 inner_code = AND;
7959 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7962 /* We may be able to continuing distributing the result, so call
7963 ourselves recursively on the inner operation before forming the
7964 outer operation, which we return. */
7965 return gen_binary (inner_code, GET_MODE (x),
7966 apply_distributive_law (tem), other);
7969 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7970 in MODE.
7972 Return an equivalent form, if different from X. Otherwise, return X. If
7973 X is zero, we are to always construct the equivalent form. */
7975 static rtx
7976 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7977 unsigned HOST_WIDE_INT constop)
7979 unsigned HOST_WIDE_INT nonzero;
7980 int i;
7982 /* Simplify VAROP knowing that we will be only looking at some of the
7983 bits in it.
7985 Note by passing in CONSTOP, we guarantee that the bits not set in
7986 CONSTOP are not significant and will never be examined. We must
7987 ensure that is the case by explicitly masking out those bits
7988 before returning. */
7989 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7991 /* If VAROP is a CLOBBER, we will fail so return it. */
7992 if (GET_CODE (varop) == CLOBBER)
7993 return varop;
7995 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7996 to VAROP and return the new constant. */
7997 if (GET_CODE (varop) == CONST_INT)
7998 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8000 /* See what bits may be nonzero in VAROP. Unlike the general case of
8001 a call to nonzero_bits, here we don't care about bits outside
8002 MODE. */
8004 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8006 /* Turn off all bits in the constant that are known to already be zero.
8007 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8008 which is tested below. */
8010 constop &= nonzero;
8012 /* If we don't have any bits left, return zero. */
8013 if (constop == 0)
8014 return const0_rtx;
8016 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8017 a power of two, we can replace this with an ASHIFT. */
8018 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8019 && (i = exact_log2 (constop)) >= 0)
8020 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8022 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8023 or XOR, then try to apply the distributive law. This may eliminate
8024 operations if either branch can be simplified because of the AND.
8025 It may also make some cases more complex, but those cases probably
8026 won't match a pattern either with or without this. */
8028 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8029 return
8030 gen_lowpart_for_combine
8031 (mode,
8032 apply_distributive_law
8033 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8034 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8035 XEXP (varop, 0), constop),
8036 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8037 XEXP (varop, 1), constop))));
8039 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8040 the AND and see if one of the operands simplifies to zero. If so, we
8041 may eliminate it. */
8043 if (GET_CODE (varop) == PLUS
8044 && exact_log2 (constop + 1) >= 0)
8046 rtx o0, o1;
8048 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8049 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8050 if (o0 == const0_rtx)
8051 return o1;
8052 if (o1 == const0_rtx)
8053 return o0;
8056 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8057 if we already had one (just check for the simplest cases). */
8058 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8059 && GET_MODE (XEXP (x, 0)) == mode
8060 && SUBREG_REG (XEXP (x, 0)) == varop)
8061 varop = XEXP (x, 0);
8062 else
8063 varop = gen_lowpart_for_combine (mode, varop);
8065 /* If we can't make the SUBREG, try to return what we were given. */
8066 if (GET_CODE (varop) == CLOBBER)
8067 return x ? x : varop;
8069 /* If we are only masking insignificant bits, return VAROP. */
8070 if (constop == nonzero)
8071 x = varop;
8072 else
8074 /* Otherwise, return an AND. */
8075 constop = trunc_int_for_mode (constop, mode);
8076 /* See how much, if any, of X we can use. */
8077 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8078 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8080 else
8082 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8083 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8084 SUBST (XEXP (x, 1), GEN_INT (constop));
8086 SUBST (XEXP (x, 0), varop);
8090 return x;
8093 #define nonzero_bits_with_known(X, MODE) \
8094 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8096 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8097 It avoids exponential behavior in nonzero_bits1 when X has
8098 identical subexpressions on the first or the second level. */
8100 static unsigned HOST_WIDE_INT
8101 cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
8102 enum machine_mode known_mode,
8103 unsigned HOST_WIDE_INT known_ret)
8105 if (x == known_x && mode == known_mode)
8106 return known_ret;
8108 /* Try to find identical subexpressions. If found call
8109 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8110 precomputed value for the subexpression as KNOWN_RET. */
8112 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8113 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8115 rtx x0 = XEXP (x, 0);
8116 rtx x1 = XEXP (x, 1);
8118 /* Check the first level. */
8119 if (x0 == x1)
8120 return nonzero_bits1 (x, mode, x0, mode,
8121 nonzero_bits_with_known (x0, mode));
8123 /* Check the second level. */
8124 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8125 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8126 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8127 return nonzero_bits1 (x, mode, x1, mode,
8128 nonzero_bits_with_known (x1, mode));
8130 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8131 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8132 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8133 return nonzero_bits1 (x, mode, x0, mode,
8134 nonzero_bits_with_known (x0, mode));
8137 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8140 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8141 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8142 is less useful. We can't allow both, because that results in exponential
8143 run time recursion. There is a nullstone testcase that triggered
8144 this. This macro avoids accidental uses of num_sign_bit_copies. */
8145 #define cached_num_sign_bit_copies()
8147 /* Given an expression, X, compute which bits in X can be nonzero.
8148 We don't care about bits outside of those defined in MODE.
8150 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8151 a shift, AND, or zero_extract, we can do better. */
8153 static unsigned HOST_WIDE_INT
8154 nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
8155 enum machine_mode known_mode,
8156 unsigned HOST_WIDE_INT known_ret)
8158 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8159 unsigned HOST_WIDE_INT inner_nz;
8160 enum rtx_code code;
8161 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8162 rtx tem;
8164 /* For floating-point values, assume all bits are needed. */
8165 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8166 return nonzero;
8168 /* If X is wider than MODE, use its mode instead. */
8169 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8171 mode = GET_MODE (x);
8172 nonzero = GET_MODE_MASK (mode);
8173 mode_width = GET_MODE_BITSIZE (mode);
8176 if (mode_width > HOST_BITS_PER_WIDE_INT)
8177 /* Our only callers in this case look for single bit values. So
8178 just return the mode mask. Those tests will then be false. */
8179 return nonzero;
8181 #ifndef WORD_REGISTER_OPERATIONS
8182 /* If MODE is wider than X, but both are a single word for both the host
8183 and target machines, we can compute this from which bits of the
8184 object might be nonzero in its own mode, taking into account the fact
8185 that on many CISC machines, accessing an object in a wider mode
8186 causes the high-order bits to become undefined. So they are
8187 not known to be zero. */
8189 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8190 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8191 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8192 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8194 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8195 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8196 return nonzero;
8198 #endif
8200 code = GET_CODE (x);
8201 switch (code)
8203 case REG:
8204 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8205 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8206 all the bits above ptr_mode are known to be zero. */
8207 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8208 && REG_POINTER (x))
8209 nonzero &= GET_MODE_MASK (ptr_mode);
8210 #endif
8212 /* Include declared information about alignment of pointers. */
8213 /* ??? We don't properly preserve REG_POINTER changes across
8214 pointer-to-integer casts, so we can't trust it except for
8215 things that we know must be pointers. See execute/960116-1.c. */
8216 if ((x == stack_pointer_rtx
8217 || x == frame_pointer_rtx
8218 || x == arg_pointer_rtx)
8219 && REGNO_POINTER_ALIGN (REGNO (x)))
8221 unsigned HOST_WIDE_INT alignment
8222 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8224 #ifdef PUSH_ROUNDING
8225 /* If PUSH_ROUNDING is defined, it is possible for the
8226 stack to be momentarily aligned only to that amount,
8227 so we pick the least alignment. */
8228 if (x == stack_pointer_rtx && PUSH_ARGS)
8229 alignment = MIN (PUSH_ROUNDING (1), alignment);
8230 #endif
8232 nonzero &= ~(alignment - 1);
8235 /* If X is a register whose nonzero bits value is current, use it.
8236 Otherwise, if X is a register whose value we can find, use that
8237 value. Otherwise, use the previously-computed global nonzero bits
8238 for this register. */
8240 if (reg_last_set_value[REGNO (x)] != 0
8241 && (reg_last_set_mode[REGNO (x)] == mode
8242 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8243 && GET_MODE_CLASS (mode) == MODE_INT))
8244 && (reg_last_set_label[REGNO (x)] == label_tick
8245 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8246 && REG_N_SETS (REGNO (x)) == 1
8247 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8248 REGNO (x))))
8249 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8250 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8252 tem = get_last_value (x);
8254 if (tem)
8256 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8257 /* If X is narrower than MODE and TEM is a non-negative
8258 constant that would appear negative in the mode of X,
8259 sign-extend it for use in reg_nonzero_bits because some
8260 machines (maybe most) will actually do the sign-extension
8261 and this is the conservative approach.
8263 ??? For 2.5, try to tighten up the MD files in this regard
8264 instead of this kludge. */
8266 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8267 && GET_CODE (tem) == CONST_INT
8268 && INTVAL (tem) > 0
8269 && 0 != (INTVAL (tem)
8270 & ((HOST_WIDE_INT) 1
8271 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8272 tem = GEN_INT (INTVAL (tem)
8273 | ((HOST_WIDE_INT) (-1)
8274 << GET_MODE_BITSIZE (GET_MODE (x))));
8275 #endif
8276 return nonzero_bits_with_known (tem, mode) & nonzero;
8278 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8280 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8282 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8283 /* We don't know anything about the upper bits. */
8284 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8285 return nonzero & mask;
8287 else
8288 return nonzero;
8290 case CONST_INT:
8291 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8292 /* If X is negative in MODE, sign-extend the value. */
8293 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8294 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8295 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8296 #endif
8298 return INTVAL (x);
8300 case MEM:
8301 #ifdef LOAD_EXTEND_OP
8302 /* In many, if not most, RISC machines, reading a byte from memory
8303 zeros the rest of the register. Noticing that fact saves a lot
8304 of extra zero-extends. */
8305 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8306 nonzero &= GET_MODE_MASK (GET_MODE (x));
8307 #endif
8308 break;
8310 case EQ: case NE:
8311 case UNEQ: case LTGT:
8312 case GT: case GTU: case UNGT:
8313 case LT: case LTU: case UNLT:
8314 case GE: case GEU: case UNGE:
8315 case LE: case LEU: case UNLE:
8316 case UNORDERED: case ORDERED:
8318 /* If this produces an integer result, we know which bits are set.
8319 Code here used to clear bits outside the mode of X, but that is
8320 now done above. */
8322 if (GET_MODE_CLASS (mode) == MODE_INT
8323 && mode_width <= HOST_BITS_PER_WIDE_INT)
8324 nonzero = STORE_FLAG_VALUE;
8325 break;
8327 case NEG:
8328 #if 0
8329 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8330 and num_sign_bit_copies. */
8331 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8332 == GET_MODE_BITSIZE (GET_MODE (x)))
8333 nonzero = 1;
8334 #endif
8336 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8337 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8338 break;
8340 case ABS:
8341 #if 0
8342 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8343 and num_sign_bit_copies. */
8344 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8345 == GET_MODE_BITSIZE (GET_MODE (x)))
8346 nonzero = 1;
8347 #endif
8348 break;
8350 case TRUNCATE:
8351 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8352 & GET_MODE_MASK (mode));
8353 break;
8355 case ZERO_EXTEND:
8356 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8357 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8358 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8359 break;
8361 case SIGN_EXTEND:
8362 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8363 Otherwise, show all the bits in the outer mode but not the inner
8364 may be nonzero. */
8365 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8366 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8368 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8369 if (inner_nz
8370 & (((HOST_WIDE_INT) 1
8371 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8372 inner_nz |= (GET_MODE_MASK (mode)
8373 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8376 nonzero &= inner_nz;
8377 break;
8379 case AND:
8380 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8381 & nonzero_bits_with_known (XEXP (x, 1), mode));
8382 break;
8384 case XOR: case IOR:
8385 case UMIN: case UMAX: case SMIN: case SMAX:
8387 unsigned HOST_WIDE_INT nonzero0 =
8388 nonzero_bits_with_known (XEXP (x, 0), mode);
8390 /* Don't call nonzero_bits for the second time if it cannot change
8391 anything. */
8392 if ((nonzero & nonzero0) != nonzero)
8393 nonzero &= (nonzero0
8394 | nonzero_bits_with_known (XEXP (x, 1), mode));
8396 break;
8398 case PLUS: case MINUS:
8399 case MULT:
8400 case DIV: case UDIV:
8401 case MOD: case UMOD:
8402 /* We can apply the rules of arithmetic to compute the number of
8403 high- and low-order zero bits of these operations. We start by
8404 computing the width (position of the highest-order nonzero bit)
8405 and the number of low-order zero bits for each value. */
8407 unsigned HOST_WIDE_INT nz0 =
8408 nonzero_bits_with_known (XEXP (x, 0), mode);
8409 unsigned HOST_WIDE_INT nz1 =
8410 nonzero_bits_with_known (XEXP (x, 1), mode);
8411 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8412 int width0 = floor_log2 (nz0) + 1;
8413 int width1 = floor_log2 (nz1) + 1;
8414 int low0 = floor_log2 (nz0 & -nz0);
8415 int low1 = floor_log2 (nz1 & -nz1);
8416 HOST_WIDE_INT op0_maybe_minusp
8417 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8418 HOST_WIDE_INT op1_maybe_minusp
8419 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8420 unsigned int result_width = mode_width;
8421 int result_low = 0;
8423 switch (code)
8425 case PLUS:
8426 result_width = MAX (width0, width1) + 1;
8427 result_low = MIN (low0, low1);
8428 break;
8429 case MINUS:
8430 result_low = MIN (low0, low1);
8431 break;
8432 case MULT:
8433 result_width = width0 + width1;
8434 result_low = low0 + low1;
8435 break;
8436 case DIV:
8437 if (width1 == 0)
8438 break;
8439 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8440 result_width = width0;
8441 break;
8442 case UDIV:
8443 if (width1 == 0)
8444 break;
8445 result_width = width0;
8446 break;
8447 case MOD:
8448 if (width1 == 0)
8449 break;
8450 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8451 result_width = MIN (width0, width1);
8452 result_low = MIN (low0, low1);
8453 break;
8454 case UMOD:
8455 if (width1 == 0)
8456 break;
8457 result_width = MIN (width0, width1);
8458 result_low = MIN (low0, low1);
8459 break;
8460 default:
8461 abort ();
8464 if (result_width < mode_width)
8465 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8467 if (result_low > 0)
8468 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8470 #ifdef POINTERS_EXTEND_UNSIGNED
8471 /* If pointers extend unsigned and this is an addition or subtraction
8472 to a pointer in Pmode, all the bits above ptr_mode are known to be
8473 zero. */
8474 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8475 && (code == PLUS || code == MINUS)
8476 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8477 nonzero &= GET_MODE_MASK (ptr_mode);
8478 #endif
8480 break;
8482 case ZERO_EXTRACT:
8483 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8484 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8485 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8486 break;
8488 case SUBREG:
8489 /* If this is a SUBREG formed for a promoted variable that has
8490 been zero-extended, we know that at least the high-order bits
8491 are zero, though others might be too. */
8493 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8494 nonzero = (GET_MODE_MASK (GET_MODE (x))
8495 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8497 /* If the inner mode is a single word for both the host and target
8498 machines, we can compute this from which bits of the inner
8499 object might be nonzero. */
8500 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8501 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8502 <= HOST_BITS_PER_WIDE_INT))
8504 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8506 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8507 /* If this is a typical RISC machine, we only have to worry
8508 about the way loads are extended. */
8509 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8510 ? (((nonzero
8511 & (((unsigned HOST_WIDE_INT) 1
8512 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8513 != 0))
8514 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8515 || GET_CODE (SUBREG_REG (x)) != MEM)
8516 #endif
8518 /* On many CISC machines, accessing an object in a wider mode
8519 causes the high-order bits to become undefined. So they are
8520 not known to be zero. */
8521 if (GET_MODE_SIZE (GET_MODE (x))
8522 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8523 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8524 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8527 break;
8529 case ASHIFTRT:
8530 case LSHIFTRT:
8531 case ASHIFT:
8532 case ROTATE:
8533 /* The nonzero bits are in two classes: any bits within MODE
8534 that aren't in GET_MODE (x) are always significant. The rest of the
8535 nonzero bits are those that are significant in the operand of
8536 the shift when shifted the appropriate number of bits. This
8537 shows that high-order bits are cleared by the right shift and
8538 low-order bits by left shifts. */
8539 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8540 && INTVAL (XEXP (x, 1)) >= 0
8541 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8543 enum machine_mode inner_mode = GET_MODE (x);
8544 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8545 int count = INTVAL (XEXP (x, 1));
8546 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8547 unsigned HOST_WIDE_INT op_nonzero =
8548 nonzero_bits_with_known (XEXP (x, 0), mode);
8549 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8550 unsigned HOST_WIDE_INT outer = 0;
8552 if (mode_width > width)
8553 outer = (op_nonzero & nonzero & ~mode_mask);
8555 if (code == LSHIFTRT)
8556 inner >>= count;
8557 else if (code == ASHIFTRT)
8559 inner >>= count;
8561 /* If the sign bit may have been nonzero before the shift, we
8562 need to mark all the places it could have been copied to
8563 by the shift as possibly nonzero. */
8564 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8565 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8567 else if (code == ASHIFT)
8568 inner <<= count;
8569 else
8570 inner = ((inner << (count % width)
8571 | (inner >> (width - (count % width)))) & mode_mask);
8573 nonzero &= (outer | inner);
8575 break;
8577 case FFS:
8578 case POPCOUNT:
8579 /* This is at most the number of bits in the mode. */
8580 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8581 break;
8583 case CLZ:
8584 /* If CLZ has a known value at zero, then the nonzero bits are
8585 that value, plus the number of bits in the mode minus one. */
8586 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8587 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8588 else
8589 nonzero = -1;
8590 break;
8592 case CTZ:
8593 /* If CTZ has a known value at zero, then the nonzero bits are
8594 that value, plus the number of bits in the mode minus one. */
8595 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8596 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8597 else
8598 nonzero = -1;
8599 break;
8601 case PARITY:
8602 nonzero = 1;
8603 break;
8605 case IF_THEN_ELSE:
8606 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8607 | nonzero_bits_with_known (XEXP (x, 2), mode));
8608 break;
8610 default:
8611 break;
8614 return nonzero;
8617 /* See the macro definition above. */
8618 #undef cached_num_sign_bit_copies
8620 #define num_sign_bit_copies_with_known(X, M) \
8621 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8623 /* The function cached_num_sign_bit_copies is a wrapper around
8624 num_sign_bit_copies1. It avoids exponential behavior in
8625 num_sign_bit_copies1 when X has identical subexpressions on the
8626 first or the second level. */
8628 static unsigned int
8629 cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
8630 enum machine_mode known_mode,
8631 unsigned int known_ret)
8633 if (x == known_x && mode == known_mode)
8634 return known_ret;
8636 /* Try to find identical subexpressions. If found call
8637 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8638 the precomputed value for the subexpression as KNOWN_RET. */
8640 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8641 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8643 rtx x0 = XEXP (x, 0);
8644 rtx x1 = XEXP (x, 1);
8646 /* Check the first level. */
8647 if (x0 == x1)
8648 return
8649 num_sign_bit_copies1 (x, mode, x0, mode,
8650 num_sign_bit_copies_with_known (x0, mode));
8652 /* Check the second level. */
8653 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8654 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8655 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8656 return
8657 num_sign_bit_copies1 (x, mode, x1, mode,
8658 num_sign_bit_copies_with_known (x1, mode));
8660 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8661 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8662 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8663 return
8664 num_sign_bit_copies1 (x, mode, x0, mode,
8665 num_sign_bit_copies_with_known (x0, mode));
8668 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8671 /* Return the number of bits at the high-order end of X that are known to
8672 be equal to the sign bit. X will be used in mode MODE; if MODE is
8673 VOIDmode, X will be used in its own mode. The returned value will always
8674 be between 1 and the number of bits in MODE. */
8676 static unsigned int
8677 num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
8678 enum machine_mode known_mode,
8679 unsigned int known_ret)
8681 enum rtx_code code = GET_CODE (x);
8682 unsigned int bitwidth;
8683 int num0, num1, result;
8684 unsigned HOST_WIDE_INT nonzero;
8685 rtx tem;
8687 /* If we weren't given a mode, use the mode of X. If the mode is still
8688 VOIDmode, we don't know anything. Likewise if one of the modes is
8689 floating-point. */
8691 if (mode == VOIDmode)
8692 mode = GET_MODE (x);
8694 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8695 return 1;
8697 bitwidth = GET_MODE_BITSIZE (mode);
8699 /* For a smaller object, just ignore the high bits. */
8700 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8702 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8703 return MAX (1,
8704 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8707 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8709 #ifndef WORD_REGISTER_OPERATIONS
8710 /* If this machine does not do all register operations on the entire
8711 register and MODE is wider than the mode of X, we can say nothing
8712 at all about the high-order bits. */
8713 return 1;
8714 #else
8715 /* Likewise on machines that do, if the mode of the object is smaller
8716 than a word and loads of that size don't sign extend, we can say
8717 nothing about the high order bits. */
8718 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8719 #ifdef LOAD_EXTEND_OP
8720 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8721 #endif
8723 return 1;
8724 #endif
8727 switch (code)
8729 case REG:
8731 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8732 /* If pointers extend signed and this is a pointer in Pmode, say that
8733 all the bits above ptr_mode are known to be sign bit copies. */
8734 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8735 && REG_POINTER (x))
8736 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8737 #endif
8739 if (reg_last_set_value[REGNO (x)] != 0
8740 && reg_last_set_mode[REGNO (x)] == mode
8741 && (reg_last_set_label[REGNO (x)] == label_tick
8742 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8743 && REG_N_SETS (REGNO (x)) == 1
8744 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8745 REGNO (x))))
8746 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8747 return reg_last_set_sign_bit_copies[REGNO (x)];
8749 tem = get_last_value (x);
8750 if (tem != 0)
8751 return num_sign_bit_copies_with_known (tem, mode);
8753 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8754 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8755 return reg_sign_bit_copies[REGNO (x)];
8756 break;
8758 case MEM:
8759 #ifdef LOAD_EXTEND_OP
8760 /* Some RISC machines sign-extend all loads of smaller than a word. */
8761 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8762 return MAX (1, ((int) bitwidth
8763 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8764 #endif
8765 break;
8767 case CONST_INT:
8768 /* If the constant is negative, take its 1's complement and remask.
8769 Then see how many zero bits we have. */
8770 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8771 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8772 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8773 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8775 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8777 case SUBREG:
8778 /* If this is a SUBREG for a promoted object that is sign-extended
8779 and we are looking at it in a wider mode, we know that at least the
8780 high-order bits are known to be sign bit copies. */
8782 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8784 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8785 return MAX ((int) bitwidth
8786 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8787 num0);
8790 /* For a smaller object, just ignore the high bits. */
8791 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8793 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8794 return MAX (1, (num0
8795 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8796 - bitwidth)));
8799 #ifdef WORD_REGISTER_OPERATIONS
8800 #ifdef LOAD_EXTEND_OP
8801 /* For paradoxical SUBREGs on machines where all register operations
8802 affect the entire register, just look inside. Note that we are
8803 passing MODE to the recursive call, so the number of sign bit copies
8804 will remain relative to that mode, not the inner mode. */
8806 /* This works only if loads sign extend. Otherwise, if we get a
8807 reload for the inner part, it may be loaded from the stack, and
8808 then we lose all sign bit copies that existed before the store
8809 to the stack. */
8811 if ((GET_MODE_SIZE (GET_MODE (x))
8812 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8813 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8814 && GET_CODE (SUBREG_REG (x)) == MEM)
8815 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8816 #endif
8817 #endif
8818 break;
8820 case SIGN_EXTRACT:
8821 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8822 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8823 break;
8825 case SIGN_EXTEND:
8826 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8827 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8829 case TRUNCATE:
8830 /* For a smaller object, just ignore the high bits. */
8831 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8832 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8833 - bitwidth)));
8835 case NOT:
8836 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8838 case ROTATE: case ROTATERT:
8839 /* If we are rotating left by a number of bits less than the number
8840 of sign bit copies, we can just subtract that amount from the
8841 number. */
8842 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8843 && INTVAL (XEXP (x, 1)) >= 0
8844 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8846 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8847 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8848 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8850 break;
8852 case NEG:
8853 /* In general, this subtracts one sign bit copy. But if the value
8854 is known to be positive, the number of sign bit copies is the
8855 same as that of the input. Finally, if the input has just one bit
8856 that might be nonzero, all the bits are copies of the sign bit. */
8857 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8858 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8859 return num0 > 1 ? num0 - 1 : 1;
8861 nonzero = nonzero_bits (XEXP (x, 0), mode);
8862 if (nonzero == 1)
8863 return bitwidth;
8865 if (num0 > 1
8866 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8867 num0--;
8869 return num0;
8871 case IOR: case AND: case XOR:
8872 case SMIN: case SMAX: case UMIN: case UMAX:
8873 /* Logical operations will preserve the number of sign-bit copies.
8874 MIN and MAX operations always return one of the operands. */
8875 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8876 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8877 return MIN (num0, num1);
8879 case PLUS: case MINUS:
8880 /* For addition and subtraction, we can have a 1-bit carry. However,
8881 if we are subtracting 1 from a positive number, there will not
8882 be such a carry. Furthermore, if the positive number is known to
8883 be 0 or 1, we know the result is either -1 or 0. */
8885 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8886 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8888 nonzero = nonzero_bits (XEXP (x, 0), mode);
8889 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8890 return (nonzero == 1 || nonzero == 0 ? bitwidth
8891 : bitwidth - floor_log2 (nonzero) - 1);
8894 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8895 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8896 result = MAX (1, MIN (num0, num1) - 1);
8898 #ifdef POINTERS_EXTEND_UNSIGNED
8899 /* If pointers extend signed and this is an addition or subtraction
8900 to a pointer in Pmode, all the bits above ptr_mode are known to be
8901 sign bit copies. */
8902 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8903 && (code == PLUS || code == MINUS)
8904 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8905 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8906 - GET_MODE_BITSIZE (ptr_mode) + 1),
8907 result);
8908 #endif
8909 return result;
8911 case MULT:
8912 /* The number of bits of the product is the sum of the number of
8913 bits of both terms. However, unless one of the terms if known
8914 to be positive, we must allow for an additional bit since negating
8915 a negative number can remove one sign bit copy. */
8917 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8918 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8920 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8921 if (result > 0
8922 && (bitwidth > HOST_BITS_PER_WIDE_INT
8923 || (((nonzero_bits (XEXP (x, 0), mode)
8924 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8925 && ((nonzero_bits (XEXP (x, 1), mode)
8926 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8927 result--;
8929 return MAX (1, result);
8931 case UDIV:
8932 /* The result must be <= the first operand. If the first operand
8933 has the high bit set, we know nothing about the number of sign
8934 bit copies. */
8935 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8936 return 1;
8937 else if ((nonzero_bits (XEXP (x, 0), mode)
8938 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8939 return 1;
8940 else
8941 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8943 case UMOD:
8944 /* The result must be <= the second operand. */
8945 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8947 case DIV:
8948 /* Similar to unsigned division, except that we have to worry about
8949 the case where the divisor is negative, in which case we have
8950 to add 1. */
8951 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8952 if (result > 1
8953 && (bitwidth > HOST_BITS_PER_WIDE_INT
8954 || (nonzero_bits (XEXP (x, 1), mode)
8955 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8956 result--;
8958 return result;
8960 case MOD:
8961 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8962 if (result > 1
8963 && (bitwidth > HOST_BITS_PER_WIDE_INT
8964 || (nonzero_bits (XEXP (x, 1), mode)
8965 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8966 result--;
8968 return result;
8970 case ASHIFTRT:
8971 /* Shifts by a constant add to the number of bits equal to the
8972 sign bit. */
8973 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8974 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8975 && INTVAL (XEXP (x, 1)) > 0)
8976 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8978 return num0;
8980 case ASHIFT:
8981 /* Left shifts destroy copies. */
8982 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8983 || INTVAL (XEXP (x, 1)) < 0
8984 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8985 return 1;
8987 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8988 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8990 case IF_THEN_ELSE:
8991 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8992 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
8993 return MIN (num0, num1);
8995 case EQ: case NE: case GE: case GT: case LE: case LT:
8996 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8997 case GEU: case GTU: case LEU: case LTU:
8998 case UNORDERED: case ORDERED:
8999 /* If the constant is negative, take its 1's complement and remask.
9000 Then see how many zero bits we have. */
9001 nonzero = STORE_FLAG_VALUE;
9002 if (bitwidth <= HOST_BITS_PER_WIDE_INT
9003 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9004 nonzero = (~nonzero) & GET_MODE_MASK (mode);
9006 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
9007 break;
9009 default:
9010 break;
9013 /* If we haven't been able to figure it out by one of the above rules,
9014 see if some of the high-order bits are known to be zero. If so,
9015 count those bits and return one less than that amount. If we can't
9016 safely compute the mask for this mode, always return BITWIDTH. */
9018 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9019 return 1;
9021 nonzero = nonzero_bits (x, mode);
9022 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
9023 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
9026 /* Return the number of "extended" bits there are in X, when interpreted
9027 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9028 unsigned quantities, this is the number of high-order zero bits.
9029 For signed quantities, this is the number of copies of the sign bit
9030 minus 1. In both case, this function returns the number of "spare"
9031 bits. For example, if two quantities for which this function returns
9032 at least 1 are added, the addition is known not to overflow.
9034 This function will always return 0 unless called during combine, which
9035 implies that it must be called from a define_split. */
9037 unsigned int
9038 extended_count (rtx x, enum machine_mode mode, int unsignedp)
9040 if (nonzero_sign_valid == 0)
9041 return 0;
9043 return (unsignedp
9044 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9045 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9046 - floor_log2 (nonzero_bits (x, mode)))
9047 : 0)
9048 : num_sign_bit_copies (x, mode) - 1);
9051 /* This function is called from `simplify_shift_const' to merge two
9052 outer operations. Specifically, we have already found that we need
9053 to perform operation *POP0 with constant *PCONST0 at the outermost
9054 position. We would now like to also perform OP1 with constant CONST1
9055 (with *POP0 being done last).
9057 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9058 the resulting operation. *PCOMP_P is set to 1 if we would need to
9059 complement the innermost operand, otherwise it is unchanged.
9061 MODE is the mode in which the operation will be done. No bits outside
9062 the width of this mode matter. It is assumed that the width of this mode
9063 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9065 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9066 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9067 result is simply *PCONST0.
9069 If the resulting operation cannot be expressed as one operation, we
9070 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9072 static int
9073 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9075 enum rtx_code op0 = *pop0;
9076 HOST_WIDE_INT const0 = *pconst0;
9078 const0 &= GET_MODE_MASK (mode);
9079 const1 &= GET_MODE_MASK (mode);
9081 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9082 if (op0 == AND)
9083 const1 &= const0;
9085 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9086 if OP0 is SET. */
9088 if (op1 == NIL || op0 == SET)
9089 return 1;
9091 else if (op0 == NIL)
9092 op0 = op1, const0 = const1;
9094 else if (op0 == op1)
9096 switch (op0)
9098 case AND:
9099 const0 &= const1;
9100 break;
9101 case IOR:
9102 const0 |= const1;
9103 break;
9104 case XOR:
9105 const0 ^= const1;
9106 break;
9107 case PLUS:
9108 const0 += const1;
9109 break;
9110 case NEG:
9111 op0 = NIL;
9112 break;
9113 default:
9114 break;
9118 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9119 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9120 return 0;
9122 /* If the two constants aren't the same, we can't do anything. The
9123 remaining six cases can all be done. */
9124 else if (const0 != const1)
9125 return 0;
9127 else
9128 switch (op0)
9130 case IOR:
9131 if (op1 == AND)
9132 /* (a & b) | b == b */
9133 op0 = SET;
9134 else /* op1 == XOR */
9135 /* (a ^ b) | b == a | b */
9137 break;
9139 case XOR:
9140 if (op1 == AND)
9141 /* (a & b) ^ b == (~a) & b */
9142 op0 = AND, *pcomp_p = 1;
9143 else /* op1 == IOR */
9144 /* (a | b) ^ b == a & ~b */
9145 op0 = AND, const0 = ~const0;
9146 break;
9148 case AND:
9149 if (op1 == IOR)
9150 /* (a | b) & b == b */
9151 op0 = SET;
9152 else /* op1 == XOR */
9153 /* (a ^ b) & b) == (~a) & b */
9154 *pcomp_p = 1;
9155 break;
9156 default:
9157 break;
9160 /* Check for NO-OP cases. */
9161 const0 &= GET_MODE_MASK (mode);
9162 if (const0 == 0
9163 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9164 op0 = NIL;
9165 else if (const0 == 0 && op0 == AND)
9166 op0 = SET;
9167 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9168 && op0 == AND)
9169 op0 = NIL;
9171 /* ??? Slightly redundant with the above mask, but not entirely.
9172 Moving this above means we'd have to sign-extend the mode mask
9173 for the final test. */
9174 const0 = trunc_int_for_mode (const0, mode);
9176 *pop0 = op0;
9177 *pconst0 = const0;
9179 return 1;
9182 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9183 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9184 that we started with.
9186 The shift is normally computed in the widest mode we find in VAROP, as
9187 long as it isn't a different number of words than RESULT_MODE. Exceptions
9188 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9190 static rtx
9191 simplify_shift_const (rtx x, enum rtx_code code,
9192 enum machine_mode result_mode, rtx varop,
9193 int orig_count)
9195 enum rtx_code orig_code = code;
9196 unsigned int count;
9197 int signed_count;
9198 enum machine_mode mode = result_mode;
9199 enum machine_mode shift_mode, tmode;
9200 unsigned int mode_words
9201 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9202 /* We form (outer_op (code varop count) (outer_const)). */
9203 enum rtx_code outer_op = NIL;
9204 HOST_WIDE_INT outer_const = 0;
9205 rtx const_rtx;
9206 int complement_p = 0;
9207 rtx new;
9209 /* Make sure and truncate the "natural" shift on the way in. We don't
9210 want to do this inside the loop as it makes it more difficult to
9211 combine shifts. */
9212 #ifdef SHIFT_COUNT_TRUNCATED
9213 if (SHIFT_COUNT_TRUNCATED)
9214 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9215 #endif
9217 /* If we were given an invalid count, don't do anything except exactly
9218 what was requested. */
9220 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9222 if (x)
9223 return x;
9225 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9228 count = orig_count;
9230 /* Unless one of the branches of the `if' in this loop does a `continue',
9231 we will `break' the loop after the `if'. */
9233 while (count != 0)
9235 /* If we have an operand of (clobber (const_int 0)), just return that
9236 value. */
9237 if (GET_CODE (varop) == CLOBBER)
9238 return varop;
9240 /* If we discovered we had to complement VAROP, leave. Making a NOT
9241 here would cause an infinite loop. */
9242 if (complement_p)
9243 break;
9245 /* Convert ROTATERT to ROTATE. */
9246 if (code == ROTATERT)
9248 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9249 code = ROTATE;
9250 if (VECTOR_MODE_P (result_mode))
9251 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9252 else
9253 count = bitsize - count;
9256 /* We need to determine what mode we will do the shift in. If the
9257 shift is a right shift or a ROTATE, we must always do it in the mode
9258 it was originally done in. Otherwise, we can do it in MODE, the
9259 widest mode encountered. */
9260 shift_mode
9261 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9262 ? result_mode : mode);
9264 /* Handle cases where the count is greater than the size of the mode
9265 minus 1. For ASHIFT, use the size minus one as the count (this can
9266 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9267 take the count modulo the size. For other shifts, the result is
9268 zero.
9270 Since these shifts are being produced by the compiler by combining
9271 multiple operations, each of which are defined, we know what the
9272 result is supposed to be. */
9274 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9276 if (code == ASHIFTRT)
9277 count = GET_MODE_BITSIZE (shift_mode) - 1;
9278 else if (code == ROTATE || code == ROTATERT)
9279 count %= GET_MODE_BITSIZE (shift_mode);
9280 else
9282 /* We can't simply return zero because there may be an
9283 outer op. */
9284 varop = const0_rtx;
9285 count = 0;
9286 break;
9290 /* An arithmetic right shift of a quantity known to be -1 or 0
9291 is a no-op. */
9292 if (code == ASHIFTRT
9293 && (num_sign_bit_copies (varop, shift_mode)
9294 == GET_MODE_BITSIZE (shift_mode)))
9296 count = 0;
9297 break;
9300 /* If we are doing an arithmetic right shift and discarding all but
9301 the sign bit copies, this is equivalent to doing a shift by the
9302 bitsize minus one. Convert it into that shift because it will often
9303 allow other simplifications. */
9305 if (code == ASHIFTRT
9306 && (count + num_sign_bit_copies (varop, shift_mode)
9307 >= GET_MODE_BITSIZE (shift_mode)))
9308 count = GET_MODE_BITSIZE (shift_mode) - 1;
9310 /* We simplify the tests below and elsewhere by converting
9311 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9312 `make_compound_operation' will convert it to an ASHIFTRT for
9313 those machines (such as VAX) that don't have an LSHIFTRT. */
9314 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9315 && code == ASHIFTRT
9316 && ((nonzero_bits (varop, shift_mode)
9317 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9318 == 0))
9319 code = LSHIFTRT;
9321 if (code == LSHIFTRT
9322 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9323 && !(nonzero_bits (varop, shift_mode) >> count))
9324 varop = const0_rtx;
9325 if (code == ASHIFT
9326 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9327 && !((nonzero_bits (varop, shift_mode) << count)
9328 & GET_MODE_MASK (shift_mode)))
9329 varop = const0_rtx;
9331 switch (GET_CODE (varop))
9333 case SIGN_EXTEND:
9334 case ZERO_EXTEND:
9335 case SIGN_EXTRACT:
9336 case ZERO_EXTRACT:
9337 new = expand_compound_operation (varop);
9338 if (new != varop)
9340 varop = new;
9341 continue;
9343 break;
9345 case MEM:
9346 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9347 minus the width of a smaller mode, we can do this with a
9348 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9349 if ((code == ASHIFTRT || code == LSHIFTRT)
9350 && ! mode_dependent_address_p (XEXP (varop, 0))
9351 && ! MEM_VOLATILE_P (varop)
9352 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9353 MODE_INT, 1)) != BLKmode)
9355 new = adjust_address_nv (varop, tmode,
9356 BYTES_BIG_ENDIAN ? 0
9357 : count / BITS_PER_UNIT);
9359 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9360 : ZERO_EXTEND, mode, new);
9361 count = 0;
9362 continue;
9364 break;
9366 case USE:
9367 /* Similar to the case above, except that we can only do this if
9368 the resulting mode is the same as that of the underlying
9369 MEM and adjust the address depending on the *bits* endianness
9370 because of the way that bit-field extract insns are defined. */
9371 if ((code == ASHIFTRT || code == LSHIFTRT)
9372 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9373 MODE_INT, 1)) != BLKmode
9374 && tmode == GET_MODE (XEXP (varop, 0)))
9376 if (BITS_BIG_ENDIAN)
9377 new = XEXP (varop, 0);
9378 else
9380 new = copy_rtx (XEXP (varop, 0));
9381 SUBST (XEXP (new, 0),
9382 plus_constant (XEXP (new, 0),
9383 count / BITS_PER_UNIT));
9386 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9387 : ZERO_EXTEND, mode, new);
9388 count = 0;
9389 continue;
9391 break;
9393 case SUBREG:
9394 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9395 the same number of words as what we've seen so far. Then store
9396 the widest mode in MODE. */
9397 if (subreg_lowpart_p (varop)
9398 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9399 > GET_MODE_SIZE (GET_MODE (varop)))
9400 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9401 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9402 == mode_words)
9404 varop = SUBREG_REG (varop);
9405 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9406 mode = GET_MODE (varop);
9407 continue;
9409 break;
9411 case MULT:
9412 /* Some machines use MULT instead of ASHIFT because MULT
9413 is cheaper. But it is still better on those machines to
9414 merge two shifts into one. */
9415 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9416 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9418 varop
9419 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9420 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9421 continue;
9423 break;
9425 case UDIV:
9426 /* Similar, for when divides are cheaper. */
9427 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9428 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9430 varop
9431 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9432 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9433 continue;
9435 break;
9437 case ASHIFTRT:
9438 /* If we are extracting just the sign bit of an arithmetic
9439 right shift, that shift is not needed. However, the sign
9440 bit of a wider mode may be different from what would be
9441 interpreted as the sign bit in a narrower mode, so, if
9442 the result is narrower, don't discard the shift. */
9443 if (code == LSHIFTRT
9444 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9445 && (GET_MODE_BITSIZE (result_mode)
9446 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9448 varop = XEXP (varop, 0);
9449 continue;
9452 /* ... fall through ... */
9454 case LSHIFTRT:
9455 case ASHIFT:
9456 case ROTATE:
9457 /* Here we have two nested shifts. The result is usually the
9458 AND of a new shift with a mask. We compute the result below. */
9459 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9460 && INTVAL (XEXP (varop, 1)) >= 0
9461 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9462 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9463 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9465 enum rtx_code first_code = GET_CODE (varop);
9466 unsigned int first_count = INTVAL (XEXP (varop, 1));
9467 unsigned HOST_WIDE_INT mask;
9468 rtx mask_rtx;
9470 /* We have one common special case. We can't do any merging if
9471 the inner code is an ASHIFTRT of a smaller mode. However, if
9472 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9473 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9474 we can convert it to
9475 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9476 This simplifies certain SIGN_EXTEND operations. */
9477 if (code == ASHIFT && first_code == ASHIFTRT
9478 && count == (unsigned int)
9479 (GET_MODE_BITSIZE (result_mode)
9480 - GET_MODE_BITSIZE (GET_MODE (varop))))
9482 /* C3 has the low-order C1 bits zero. */
9484 mask = (GET_MODE_MASK (mode)
9485 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9487 varop = simplify_and_const_int (NULL_RTX, result_mode,
9488 XEXP (varop, 0), mask);
9489 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9490 varop, count);
9491 count = first_count;
9492 code = ASHIFTRT;
9493 continue;
9496 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9497 than C1 high-order bits equal to the sign bit, we can convert
9498 this to either an ASHIFT or an ASHIFTRT depending on the
9499 two counts.
9501 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9503 if (code == ASHIFTRT && first_code == ASHIFT
9504 && GET_MODE (varop) == shift_mode
9505 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9506 > first_count))
9508 varop = XEXP (varop, 0);
9510 signed_count = count - first_count;
9511 if (signed_count < 0)
9512 count = -signed_count, code = ASHIFT;
9513 else
9514 count = signed_count;
9516 continue;
9519 /* There are some cases we can't do. If CODE is ASHIFTRT,
9520 we can only do this if FIRST_CODE is also ASHIFTRT.
9522 We can't do the case when CODE is ROTATE and FIRST_CODE is
9523 ASHIFTRT.
9525 If the mode of this shift is not the mode of the outer shift,
9526 we can't do this if either shift is a right shift or ROTATE.
9528 Finally, we can't do any of these if the mode is too wide
9529 unless the codes are the same.
9531 Handle the case where the shift codes are the same
9532 first. */
9534 if (code == first_code)
9536 if (GET_MODE (varop) != result_mode
9537 && (code == ASHIFTRT || code == LSHIFTRT
9538 || code == ROTATE))
9539 break;
9541 count += first_count;
9542 varop = XEXP (varop, 0);
9543 continue;
9546 if (code == ASHIFTRT
9547 || (code == ROTATE && first_code == ASHIFTRT)
9548 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9549 || (GET_MODE (varop) != result_mode
9550 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9551 || first_code == ROTATE
9552 || code == ROTATE)))
9553 break;
9555 /* To compute the mask to apply after the shift, shift the
9556 nonzero bits of the inner shift the same way the
9557 outer shift will. */
9559 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9561 mask_rtx
9562 = simplify_binary_operation (code, result_mode, mask_rtx,
9563 GEN_INT (count));
9565 /* Give up if we can't compute an outer operation to use. */
9566 if (mask_rtx == 0
9567 || GET_CODE (mask_rtx) != CONST_INT
9568 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9569 INTVAL (mask_rtx),
9570 result_mode, &complement_p))
9571 break;
9573 /* If the shifts are in the same direction, we add the
9574 counts. Otherwise, we subtract them. */
9575 signed_count = count;
9576 if ((code == ASHIFTRT || code == LSHIFTRT)
9577 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9578 signed_count += first_count;
9579 else
9580 signed_count -= first_count;
9582 /* If COUNT is positive, the new shift is usually CODE,
9583 except for the two exceptions below, in which case it is
9584 FIRST_CODE. If the count is negative, FIRST_CODE should
9585 always be used */
9586 if (signed_count > 0
9587 && ((first_code == ROTATE && code == ASHIFT)
9588 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9589 code = first_code, count = signed_count;
9590 else if (signed_count < 0)
9591 code = first_code, count = -signed_count;
9592 else
9593 count = signed_count;
9595 varop = XEXP (varop, 0);
9596 continue;
9599 /* If we have (A << B << C) for any shift, we can convert this to
9600 (A << C << B). This wins if A is a constant. Only try this if
9601 B is not a constant. */
9603 else if (GET_CODE (varop) == code
9604 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9605 && 0 != (new
9606 = simplify_binary_operation (code, mode,
9607 XEXP (varop, 0),
9608 GEN_INT (count))))
9610 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9611 count = 0;
9612 continue;
9614 break;
9616 case NOT:
9617 /* Make this fit the case below. */
9618 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9619 GEN_INT (GET_MODE_MASK (mode)));
9620 continue;
9622 case IOR:
9623 case AND:
9624 case XOR:
9625 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9626 with C the size of VAROP - 1 and the shift is logical if
9627 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9628 we have an (le X 0) operation. If we have an arithmetic shift
9629 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9630 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9632 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9633 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9634 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9635 && (code == LSHIFTRT || code == ASHIFTRT)
9636 && count == (unsigned int)
9637 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9638 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9640 count = 0;
9641 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9642 const0_rtx);
9644 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9645 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9647 continue;
9650 /* If we have (shift (logical)), move the logical to the outside
9651 to allow it to possibly combine with another logical and the
9652 shift to combine with another shift. This also canonicalizes to
9653 what a ZERO_EXTRACT looks like. Also, some machines have
9654 (and (shift)) insns. */
9656 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9657 && (new = simplify_binary_operation (code, result_mode,
9658 XEXP (varop, 1),
9659 GEN_INT (count))) != 0
9660 && GET_CODE (new) == CONST_INT
9661 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9662 INTVAL (new), result_mode, &complement_p))
9664 varop = XEXP (varop, 0);
9665 continue;
9668 /* If we can't do that, try to simplify the shift in each arm of the
9669 logical expression, make a new logical expression, and apply
9670 the inverse distributive law. */
9672 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9673 XEXP (varop, 0), count);
9674 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9675 XEXP (varop, 1), count);
9677 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9678 varop = apply_distributive_law (varop);
9680 count = 0;
9682 break;
9684 case EQ:
9685 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9686 says that the sign bit can be tested, FOO has mode MODE, C is
9687 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9688 that may be nonzero. */
9689 if (code == LSHIFTRT
9690 && XEXP (varop, 1) == const0_rtx
9691 && GET_MODE (XEXP (varop, 0)) == result_mode
9692 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9693 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9694 && ((STORE_FLAG_VALUE
9695 & ((HOST_WIDE_INT) 1
9696 < (GET_MODE_BITSIZE (result_mode) - 1))))
9697 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9698 && merge_outer_ops (&outer_op, &outer_const, XOR,
9699 (HOST_WIDE_INT) 1, result_mode,
9700 &complement_p))
9702 varop = XEXP (varop, 0);
9703 count = 0;
9704 continue;
9706 break;
9708 case NEG:
9709 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9710 than the number of bits in the mode is equivalent to A. */
9711 if (code == LSHIFTRT
9712 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9713 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9715 varop = XEXP (varop, 0);
9716 count = 0;
9717 continue;
9720 /* NEG commutes with ASHIFT since it is multiplication. Move the
9721 NEG outside to allow shifts to combine. */
9722 if (code == ASHIFT
9723 && merge_outer_ops (&outer_op, &outer_const, NEG,
9724 (HOST_WIDE_INT) 0, result_mode,
9725 &complement_p))
9727 varop = XEXP (varop, 0);
9728 continue;
9730 break;
9732 case PLUS:
9733 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9734 is one less than the number of bits in the mode is
9735 equivalent to (xor A 1). */
9736 if (code == LSHIFTRT
9737 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9738 && XEXP (varop, 1) == constm1_rtx
9739 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9740 && merge_outer_ops (&outer_op, &outer_const, XOR,
9741 (HOST_WIDE_INT) 1, result_mode,
9742 &complement_p))
9744 count = 0;
9745 varop = XEXP (varop, 0);
9746 continue;
9749 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9750 that might be nonzero in BAR are those being shifted out and those
9751 bits are known zero in FOO, we can replace the PLUS with FOO.
9752 Similarly in the other operand order. This code occurs when
9753 we are computing the size of a variable-size array. */
9755 if ((code == ASHIFTRT || code == LSHIFTRT)
9756 && count < HOST_BITS_PER_WIDE_INT
9757 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9758 && (nonzero_bits (XEXP (varop, 1), result_mode)
9759 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9761 varop = XEXP (varop, 0);
9762 continue;
9764 else if ((code == ASHIFTRT || code == LSHIFTRT)
9765 && count < HOST_BITS_PER_WIDE_INT
9766 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9767 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9768 >> count)
9769 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9770 & nonzero_bits (XEXP (varop, 1),
9771 result_mode)))
9773 varop = XEXP (varop, 1);
9774 continue;
9777 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9778 if (code == ASHIFT
9779 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9780 && (new = simplify_binary_operation (ASHIFT, result_mode,
9781 XEXP (varop, 1),
9782 GEN_INT (count))) != 0
9783 && GET_CODE (new) == CONST_INT
9784 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9785 INTVAL (new), result_mode, &complement_p))
9787 varop = XEXP (varop, 0);
9788 continue;
9790 break;
9792 case MINUS:
9793 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9794 with C the size of VAROP - 1 and the shift is logical if
9795 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9796 we have a (gt X 0) operation. If the shift is arithmetic with
9797 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9798 we have a (neg (gt X 0)) operation. */
9800 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9801 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9802 && count == (unsigned int)
9803 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9804 && (code == LSHIFTRT || code == ASHIFTRT)
9805 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9806 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9807 == count
9808 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9810 count = 0;
9811 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9812 const0_rtx);
9814 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9815 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9817 continue;
9819 break;
9821 case TRUNCATE:
9822 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9823 if the truncate does not affect the value. */
9824 if (code == LSHIFTRT
9825 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9826 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9827 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9828 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9829 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9831 rtx varop_inner = XEXP (varop, 0);
9833 varop_inner
9834 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9835 XEXP (varop_inner, 0),
9836 GEN_INT
9837 (count + INTVAL (XEXP (varop_inner, 1))));
9838 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9839 count = 0;
9840 continue;
9842 break;
9844 default:
9845 break;
9848 break;
9851 /* We need to determine what mode to do the shift in. If the shift is
9852 a right shift or ROTATE, we must always do it in the mode it was
9853 originally done in. Otherwise, we can do it in MODE, the widest mode
9854 encountered. The code we care about is that of the shift that will
9855 actually be done, not the shift that was originally requested. */
9856 shift_mode
9857 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9858 ? result_mode : mode);
9860 /* We have now finished analyzing the shift. The result should be
9861 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9862 OUTER_OP is non-NIL, it is an operation that needs to be applied
9863 to the result of the shift. OUTER_CONST is the relevant constant,
9864 but we must turn off all bits turned off in the shift.
9866 If we were passed a value for X, see if we can use any pieces of
9867 it. If not, make new rtx. */
9869 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9870 && GET_CODE (XEXP (x, 1)) == CONST_INT
9871 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9872 const_rtx = XEXP (x, 1);
9873 else
9874 const_rtx = GEN_INT (count);
9876 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9877 && GET_MODE (XEXP (x, 0)) == shift_mode
9878 && SUBREG_REG (XEXP (x, 0)) == varop)
9879 varop = XEXP (x, 0);
9880 else if (GET_MODE (varop) != shift_mode)
9881 varop = gen_lowpart_for_combine (shift_mode, varop);
9883 /* If we can't make the SUBREG, try to return what we were given. */
9884 if (GET_CODE (varop) == CLOBBER)
9885 return x ? x : varop;
9887 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9888 if (new != 0)
9889 x = new;
9890 else
9891 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9893 /* If we have an outer operation and we just made a shift, it is
9894 possible that we could have simplified the shift were it not
9895 for the outer operation. So try to do the simplification
9896 recursively. */
9898 if (outer_op != NIL && GET_CODE (x) == code
9899 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9900 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9901 INTVAL (XEXP (x, 1)));
9903 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9904 turn off all the bits that the shift would have turned off. */
9905 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9906 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9907 GET_MODE_MASK (result_mode) >> orig_count);
9909 /* Do the remainder of the processing in RESULT_MODE. */
9910 x = gen_lowpart_for_combine (result_mode, x);
9912 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9913 operation. */
9914 if (complement_p)
9915 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9917 if (outer_op != NIL)
9919 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9920 outer_const = trunc_int_for_mode (outer_const, result_mode);
9922 if (outer_op == AND)
9923 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9924 else if (outer_op == SET)
9925 /* This means that we have determined that the result is
9926 equivalent to a constant. This should be rare. */
9927 x = GEN_INT (outer_const);
9928 else if (GET_RTX_CLASS (outer_op) == '1')
9929 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9930 else
9931 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9934 return x;
9937 /* Like recog, but we receive the address of a pointer to a new pattern.
9938 We try to match the rtx that the pointer points to.
9939 If that fails, we may try to modify or replace the pattern,
9940 storing the replacement into the same pointer object.
9942 Modifications include deletion or addition of CLOBBERs.
9944 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9945 the CLOBBERs are placed.
9947 The value is the final insn code from the pattern ultimately matched,
9948 or -1. */
9950 static int
9951 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9953 rtx pat = *pnewpat;
9954 int insn_code_number;
9955 int num_clobbers_to_add = 0;
9956 int i;
9957 rtx notes = 0;
9958 rtx dummy_insn;
9960 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9961 we use to indicate that something didn't match. If we find such a
9962 thing, force rejection. */
9963 if (GET_CODE (pat) == PARALLEL)
9964 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9965 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9966 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9967 return -1;
9969 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9970 instruction for pattern recognition. */
9971 dummy_insn = shallow_copy_rtx (insn);
9972 PATTERN (dummy_insn) = pat;
9973 REG_NOTES (dummy_insn) = 0;
9975 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9977 /* If it isn't, there is the possibility that we previously had an insn
9978 that clobbered some register as a side effect, but the combined
9979 insn doesn't need to do that. So try once more without the clobbers
9980 unless this represents an ASM insn. */
9982 if (insn_code_number < 0 && ! check_asm_operands (pat)
9983 && GET_CODE (pat) == PARALLEL)
9985 int pos;
9987 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9988 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9990 if (i != pos)
9991 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9992 pos++;
9995 SUBST_INT (XVECLEN (pat, 0), pos);
9997 if (pos == 1)
9998 pat = XVECEXP (pat, 0, 0);
10000 PATTERN (dummy_insn) = pat;
10001 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10004 /* Recognize all noop sets, these will be killed by followup pass. */
10005 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10006 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10008 /* If we had any clobbers to add, make a new pattern than contains
10009 them. Then check to make sure that all of them are dead. */
10010 if (num_clobbers_to_add)
10012 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10013 rtvec_alloc (GET_CODE (pat) == PARALLEL
10014 ? (XVECLEN (pat, 0)
10015 + num_clobbers_to_add)
10016 : num_clobbers_to_add + 1));
10018 if (GET_CODE (pat) == PARALLEL)
10019 for (i = 0; i < XVECLEN (pat, 0); i++)
10020 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10021 else
10022 XVECEXP (newpat, 0, 0) = pat;
10024 add_clobbers (newpat, insn_code_number);
10026 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10027 i < XVECLEN (newpat, 0); i++)
10029 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
10030 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10031 return -1;
10032 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
10033 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10035 pat = newpat;
10038 *pnewpat = pat;
10039 *pnotes = notes;
10041 return insn_code_number;
10044 /* Like gen_lowpart but for use by combine. In combine it is not possible
10045 to create any new pseudoregs. However, it is safe to create
10046 invalid memory addresses, because combine will try to recognize
10047 them and all they will do is make the combine attempt fail.
10049 If for some reason this cannot do its job, an rtx
10050 (clobber (const_int 0)) is returned.
10051 An insn containing that will not be recognized. */
10053 #undef gen_lowpart
10055 static rtx
10056 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
10058 rtx result;
10060 if (GET_MODE (x) == mode)
10061 return x;
10063 /* Return identity if this is a CONST or symbolic
10064 reference. */
10065 if (mode == Pmode
10066 && (GET_CODE (x) == CONST
10067 || GET_CODE (x) == SYMBOL_REF
10068 || GET_CODE (x) == LABEL_REF))
10069 return x;
10071 /* We can only support MODE being wider than a word if X is a
10072 constant integer or has a mode the same size. */
10074 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
10075 && ! ((GET_MODE (x) == VOIDmode
10076 && (GET_CODE (x) == CONST_INT
10077 || GET_CODE (x) == CONST_DOUBLE))
10078 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10079 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10081 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10082 won't know what to do. So we will strip off the SUBREG here and
10083 process normally. */
10084 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10086 x = SUBREG_REG (x);
10087 if (GET_MODE (x) == mode)
10088 return x;
10091 result = gen_lowpart_common (mode, x);
10092 #ifdef CANNOT_CHANGE_MODE_CLASS
10093 if (result != 0
10094 && GET_CODE (result) == SUBREG
10095 && GET_CODE (SUBREG_REG (result)) == REG
10096 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10097 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10098 * MAX_MACHINE_MODE
10099 + GET_MODE (result));
10100 #endif
10102 if (result)
10103 return result;
10105 if (GET_CODE (x) == MEM)
10107 int offset = 0;
10109 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10110 address. */
10111 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10112 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10114 /* If we want to refer to something bigger than the original memref,
10115 generate a perverse subreg instead. That will force a reload
10116 of the original memref X. */
10117 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10118 return gen_rtx_SUBREG (mode, x, 0);
10120 if (WORDS_BIG_ENDIAN)
10121 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10122 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10124 if (BYTES_BIG_ENDIAN)
10126 /* Adjust the address so that the address-after-the-data is
10127 unchanged. */
10128 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10129 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10132 return adjust_address_nv (x, mode, offset);
10135 /* If X is a comparison operator, rewrite it in a new mode. This
10136 probably won't match, but may allow further simplifications. */
10137 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10138 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10140 /* If we couldn't simplify X any other way, just enclose it in a
10141 SUBREG. Normally, this SUBREG won't match, but some patterns may
10142 include an explicit SUBREG or we may simplify it further in combine. */
10143 else
10145 int offset = 0;
10146 rtx res;
10147 enum machine_mode sub_mode = GET_MODE (x);
10149 offset = subreg_lowpart_offset (mode, sub_mode);
10150 if (sub_mode == VOIDmode)
10152 sub_mode = int_mode_for_mode (mode);
10153 x = gen_lowpart_common (sub_mode, x);
10154 if (x == 0)
10155 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
10157 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10158 if (res)
10159 return res;
10160 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10164 /* These routines make binary and unary operations by first seeing if they
10165 fold; if not, a new expression is allocated. */
10167 static rtx
10168 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
10170 rtx result;
10171 rtx tem;
10173 if (GET_RTX_CLASS (code) == 'c'
10174 && swap_commutative_operands_p (op0, op1))
10175 tem = op0, op0 = op1, op1 = tem;
10177 if (GET_RTX_CLASS (code) == '<')
10179 enum machine_mode op_mode = GET_MODE (op0);
10181 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10182 just (REL_OP X Y). */
10183 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10185 op1 = XEXP (op0, 1);
10186 op0 = XEXP (op0, 0);
10187 op_mode = GET_MODE (op0);
10190 if (op_mode == VOIDmode)
10191 op_mode = GET_MODE (op1);
10192 result = simplify_relational_operation (code, op_mode, op0, op1);
10194 else
10195 result = simplify_binary_operation (code, mode, op0, op1);
10197 if (result)
10198 return result;
10200 /* Put complex operands first and constants second. */
10201 if (GET_RTX_CLASS (code) == 'c'
10202 && swap_commutative_operands_p (op0, op1))
10203 return gen_rtx_fmt_ee (code, mode, op1, op0);
10205 /* If we are turning off bits already known off in OP0, we need not do
10206 an AND. */
10207 else if (code == AND && GET_CODE (op1) == CONST_INT
10208 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10209 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10210 return op0;
10212 return gen_rtx_fmt_ee (code, mode, op0, op1);
10215 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10216 comparison code that will be tested.
10218 The result is a possibly different comparison code to use. *POP0 and
10219 *POP1 may be updated.
10221 It is possible that we might detect that a comparison is either always
10222 true or always false. However, we do not perform general constant
10223 folding in combine, so this knowledge isn't useful. Such tautologies
10224 should have been detected earlier. Hence we ignore all such cases. */
10226 static enum rtx_code
10227 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10229 rtx op0 = *pop0;
10230 rtx op1 = *pop1;
10231 rtx tem, tem1;
10232 int i;
10233 enum machine_mode mode, tmode;
10235 /* Try a few ways of applying the same transformation to both operands. */
10236 while (1)
10238 #ifndef WORD_REGISTER_OPERATIONS
10239 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10240 so check specially. */
10241 if (code != GTU && code != GEU && code != LTU && code != LEU
10242 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10243 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10244 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10245 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10246 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10247 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10248 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10249 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10250 && XEXP (op0, 1) == XEXP (op1, 1)
10251 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10252 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10253 && (INTVAL (XEXP (op0, 1))
10254 == (GET_MODE_BITSIZE (GET_MODE (op0))
10255 - (GET_MODE_BITSIZE
10256 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10258 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10259 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10261 #endif
10263 /* If both operands are the same constant shift, see if we can ignore the
10264 shift. We can if the shift is a rotate or if the bits shifted out of
10265 this shift are known to be zero for both inputs and if the type of
10266 comparison is compatible with the shift. */
10267 if (GET_CODE (op0) == GET_CODE (op1)
10268 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10269 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10270 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10271 && (code != GT && code != LT && code != GE && code != LE))
10272 || (GET_CODE (op0) == ASHIFTRT
10273 && (code != GTU && code != LTU
10274 && code != GEU && code != LEU)))
10275 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10276 && INTVAL (XEXP (op0, 1)) >= 0
10277 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10278 && XEXP (op0, 1) == XEXP (op1, 1))
10280 enum machine_mode mode = GET_MODE (op0);
10281 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10282 int shift_count = INTVAL (XEXP (op0, 1));
10284 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10285 mask &= (mask >> shift_count) << shift_count;
10286 else if (GET_CODE (op0) == ASHIFT)
10287 mask = (mask & (mask << shift_count)) >> shift_count;
10289 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10290 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10291 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10292 else
10293 break;
10296 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10297 SUBREGs are of the same mode, and, in both cases, the AND would
10298 be redundant if the comparison was done in the narrower mode,
10299 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10300 and the operand's possibly nonzero bits are 0xffffff01; in that case
10301 if we only care about QImode, we don't need the AND). This case
10302 occurs if the output mode of an scc insn is not SImode and
10303 STORE_FLAG_VALUE == 1 (e.g., the 386).
10305 Similarly, check for a case where the AND's are ZERO_EXTEND
10306 operations from some narrower mode even though a SUBREG is not
10307 present. */
10309 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10310 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10311 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10313 rtx inner_op0 = XEXP (op0, 0);
10314 rtx inner_op1 = XEXP (op1, 0);
10315 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10316 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10317 int changed = 0;
10319 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10320 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10321 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10322 && (GET_MODE (SUBREG_REG (inner_op0))
10323 == GET_MODE (SUBREG_REG (inner_op1)))
10324 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10325 <= HOST_BITS_PER_WIDE_INT)
10326 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10327 GET_MODE (SUBREG_REG (inner_op0)))))
10328 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10329 GET_MODE (SUBREG_REG (inner_op1))))))
10331 op0 = SUBREG_REG (inner_op0);
10332 op1 = SUBREG_REG (inner_op1);
10334 /* The resulting comparison is always unsigned since we masked
10335 off the original sign bit. */
10336 code = unsigned_condition (code);
10338 changed = 1;
10341 else if (c0 == c1)
10342 for (tmode = GET_CLASS_NARROWEST_MODE
10343 (GET_MODE_CLASS (GET_MODE (op0)));
10344 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10345 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10347 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10348 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10349 code = unsigned_condition (code);
10350 changed = 1;
10351 break;
10354 if (! changed)
10355 break;
10358 /* If both operands are NOT, we can strip off the outer operation
10359 and adjust the comparison code for swapped operands; similarly for
10360 NEG, except that this must be an equality comparison. */
10361 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10362 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10363 && (code == EQ || code == NE)))
10364 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10366 else
10367 break;
10370 /* If the first operand is a constant, swap the operands and adjust the
10371 comparison code appropriately, but don't do this if the second operand
10372 is already a constant integer. */
10373 if (swap_commutative_operands_p (op0, op1))
10375 tem = op0, op0 = op1, op1 = tem;
10376 code = swap_condition (code);
10379 /* We now enter a loop during which we will try to simplify the comparison.
10380 For the most part, we only are concerned with comparisons with zero,
10381 but some things may really be comparisons with zero but not start
10382 out looking that way. */
10384 while (GET_CODE (op1) == CONST_INT)
10386 enum machine_mode mode = GET_MODE (op0);
10387 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10388 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10389 int equality_comparison_p;
10390 int sign_bit_comparison_p;
10391 int unsigned_comparison_p;
10392 HOST_WIDE_INT const_op;
10394 /* We only want to handle integral modes. This catches VOIDmode,
10395 CCmode, and the floating-point modes. An exception is that we
10396 can handle VOIDmode if OP0 is a COMPARE or a comparison
10397 operation. */
10399 if (GET_MODE_CLASS (mode) != MODE_INT
10400 && ! (mode == VOIDmode
10401 && (GET_CODE (op0) == COMPARE
10402 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10403 break;
10405 /* Get the constant we are comparing against and turn off all bits
10406 not on in our mode. */
10407 const_op = INTVAL (op1);
10408 if (mode != VOIDmode)
10409 const_op = trunc_int_for_mode (const_op, mode);
10410 op1 = GEN_INT (const_op);
10412 /* If we are comparing against a constant power of two and the value
10413 being compared can only have that single bit nonzero (e.g., it was
10414 `and'ed with that bit), we can replace this with a comparison
10415 with zero. */
10416 if (const_op
10417 && (code == EQ || code == NE || code == GE || code == GEU
10418 || code == LT || code == LTU)
10419 && mode_width <= HOST_BITS_PER_WIDE_INT
10420 && exact_log2 (const_op) >= 0
10421 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10423 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10424 op1 = const0_rtx, const_op = 0;
10427 /* Similarly, if we are comparing a value known to be either -1 or
10428 0 with -1, change it to the opposite comparison against zero. */
10430 if (const_op == -1
10431 && (code == EQ || code == NE || code == GT || code == LE
10432 || code == GEU || code == LTU)
10433 && num_sign_bit_copies (op0, mode) == mode_width)
10435 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10436 op1 = const0_rtx, const_op = 0;
10439 /* Do some canonicalizations based on the comparison code. We prefer
10440 comparisons against zero and then prefer equality comparisons.
10441 If we can reduce the size of a constant, we will do that too. */
10443 switch (code)
10445 case LT:
10446 /* < C is equivalent to <= (C - 1) */
10447 if (const_op > 0)
10449 const_op -= 1;
10450 op1 = GEN_INT (const_op);
10451 code = LE;
10452 /* ... fall through to LE case below. */
10454 else
10455 break;
10457 case LE:
10458 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10459 if (const_op < 0)
10461 const_op += 1;
10462 op1 = GEN_INT (const_op);
10463 code = LT;
10466 /* If we are doing a <= 0 comparison on a value known to have
10467 a zero sign bit, we can replace this with == 0. */
10468 else if (const_op == 0
10469 && mode_width <= HOST_BITS_PER_WIDE_INT
10470 && (nonzero_bits (op0, mode)
10471 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10472 code = EQ;
10473 break;
10475 case GE:
10476 /* >= C is equivalent to > (C - 1). */
10477 if (const_op > 0)
10479 const_op -= 1;
10480 op1 = GEN_INT (const_op);
10481 code = GT;
10482 /* ... fall through to GT below. */
10484 else
10485 break;
10487 case GT:
10488 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10489 if (const_op < 0)
10491 const_op += 1;
10492 op1 = GEN_INT (const_op);
10493 code = GE;
10496 /* If we are doing a > 0 comparison on a value known to have
10497 a zero sign bit, we can replace this with != 0. */
10498 else if (const_op == 0
10499 && mode_width <= HOST_BITS_PER_WIDE_INT
10500 && (nonzero_bits (op0, mode)
10501 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10502 code = NE;
10503 break;
10505 case LTU:
10506 /* < C is equivalent to <= (C - 1). */
10507 if (const_op > 0)
10509 const_op -= 1;
10510 op1 = GEN_INT (const_op);
10511 code = LEU;
10512 /* ... fall through ... */
10515 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10516 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10517 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10519 const_op = 0, op1 = const0_rtx;
10520 code = GE;
10521 break;
10523 else
10524 break;
10526 case LEU:
10527 /* unsigned <= 0 is equivalent to == 0 */
10528 if (const_op == 0)
10529 code = EQ;
10531 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10532 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10533 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10535 const_op = 0, op1 = const0_rtx;
10536 code = GE;
10538 break;
10540 case GEU:
10541 /* >= C is equivalent to < (C - 1). */
10542 if (const_op > 1)
10544 const_op -= 1;
10545 op1 = GEN_INT (const_op);
10546 code = GTU;
10547 /* ... fall through ... */
10550 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10551 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10552 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10554 const_op = 0, op1 = const0_rtx;
10555 code = LT;
10556 break;
10558 else
10559 break;
10561 case GTU:
10562 /* unsigned > 0 is equivalent to != 0 */
10563 if (const_op == 0)
10564 code = NE;
10566 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10567 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10568 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10570 const_op = 0, op1 = const0_rtx;
10571 code = LT;
10573 break;
10575 default:
10576 break;
10579 /* Compute some predicates to simplify code below. */
10581 equality_comparison_p = (code == EQ || code == NE);
10582 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10583 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10584 || code == GEU);
10586 /* If this is a sign bit comparison and we can do arithmetic in
10587 MODE, say that we will only be needing the sign bit of OP0. */
10588 if (sign_bit_comparison_p
10589 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10590 op0 = force_to_mode (op0, mode,
10591 ((HOST_WIDE_INT) 1
10592 << (GET_MODE_BITSIZE (mode) - 1)),
10593 NULL_RTX, 0);
10595 /* Now try cases based on the opcode of OP0. If none of the cases
10596 does a "continue", we exit this loop immediately after the
10597 switch. */
10599 switch (GET_CODE (op0))
10601 case ZERO_EXTRACT:
10602 /* If we are extracting a single bit from a variable position in
10603 a constant that has only a single bit set and are comparing it
10604 with zero, we can convert this into an equality comparison
10605 between the position and the location of the single bit. */
10607 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10608 && XEXP (op0, 1) == const1_rtx
10609 && equality_comparison_p && const_op == 0
10610 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10612 if (BITS_BIG_ENDIAN)
10614 enum machine_mode new_mode
10615 = mode_for_extraction (EP_extzv, 1);
10616 if (new_mode == MAX_MACHINE_MODE)
10617 i = BITS_PER_WORD - 1 - i;
10618 else
10620 mode = new_mode;
10621 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10625 op0 = XEXP (op0, 2);
10626 op1 = GEN_INT (i);
10627 const_op = i;
10629 /* Result is nonzero iff shift count is equal to I. */
10630 code = reverse_condition (code);
10631 continue;
10634 /* ... fall through ... */
10636 case SIGN_EXTRACT:
10637 tem = expand_compound_operation (op0);
10638 if (tem != op0)
10640 op0 = tem;
10641 continue;
10643 break;
10645 case NOT:
10646 /* If testing for equality, we can take the NOT of the constant. */
10647 if (equality_comparison_p
10648 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10650 op0 = XEXP (op0, 0);
10651 op1 = tem;
10652 continue;
10655 /* If just looking at the sign bit, reverse the sense of the
10656 comparison. */
10657 if (sign_bit_comparison_p)
10659 op0 = XEXP (op0, 0);
10660 code = (code == GE ? LT : GE);
10661 continue;
10663 break;
10665 case NEG:
10666 /* If testing for equality, we can take the NEG of the constant. */
10667 if (equality_comparison_p
10668 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10670 op0 = XEXP (op0, 0);
10671 op1 = tem;
10672 continue;
10675 /* The remaining cases only apply to comparisons with zero. */
10676 if (const_op != 0)
10677 break;
10679 /* When X is ABS or is known positive,
10680 (neg X) is < 0 if and only if X != 0. */
10682 if (sign_bit_comparison_p
10683 && (GET_CODE (XEXP (op0, 0)) == ABS
10684 || (mode_width <= HOST_BITS_PER_WIDE_INT
10685 && (nonzero_bits (XEXP (op0, 0), mode)
10686 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10688 op0 = XEXP (op0, 0);
10689 code = (code == LT ? NE : EQ);
10690 continue;
10693 /* If we have NEG of something whose two high-order bits are the
10694 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10695 if (num_sign_bit_copies (op0, mode) >= 2)
10697 op0 = XEXP (op0, 0);
10698 code = swap_condition (code);
10699 continue;
10701 break;
10703 case ROTATE:
10704 /* If we are testing equality and our count is a constant, we
10705 can perform the inverse operation on our RHS. */
10706 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10707 && (tem = simplify_binary_operation (ROTATERT, mode,
10708 op1, XEXP (op0, 1))) != 0)
10710 op0 = XEXP (op0, 0);
10711 op1 = tem;
10712 continue;
10715 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10716 a particular bit. Convert it to an AND of a constant of that
10717 bit. This will be converted into a ZERO_EXTRACT. */
10718 if (const_op == 0 && sign_bit_comparison_p
10719 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10720 && mode_width <= HOST_BITS_PER_WIDE_INT)
10722 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10723 ((HOST_WIDE_INT) 1
10724 << (mode_width - 1
10725 - INTVAL (XEXP (op0, 1)))));
10726 code = (code == LT ? NE : EQ);
10727 continue;
10730 /* Fall through. */
10732 case ABS:
10733 /* ABS is ignorable inside an equality comparison with zero. */
10734 if (const_op == 0 && equality_comparison_p)
10736 op0 = XEXP (op0, 0);
10737 continue;
10739 break;
10741 case SIGN_EXTEND:
10742 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10743 to (compare FOO CONST) if CONST fits in FOO's mode and we
10744 are either testing inequality or have an unsigned comparison
10745 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10746 if (! unsigned_comparison_p
10747 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10748 <= HOST_BITS_PER_WIDE_INT)
10749 && ((unsigned HOST_WIDE_INT) const_op
10750 < (((unsigned HOST_WIDE_INT) 1
10751 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10753 op0 = XEXP (op0, 0);
10754 continue;
10756 break;
10758 case SUBREG:
10759 /* Check for the case where we are comparing A - C1 with C2,
10760 both constants are smaller than 1/2 the maximum positive
10761 value in MODE, and the comparison is equality or unsigned.
10762 In that case, if A is either zero-extended to MODE or has
10763 sufficient sign bits so that the high-order bit in MODE
10764 is a copy of the sign in the inner mode, we can prove that it is
10765 safe to do the operation in the wider mode. This simplifies
10766 many range checks. */
10768 if (mode_width <= HOST_BITS_PER_WIDE_INT
10769 && subreg_lowpart_p (op0)
10770 && GET_CODE (SUBREG_REG (op0)) == PLUS
10771 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10772 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10773 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10774 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10775 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10776 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10777 GET_MODE (SUBREG_REG (op0)))
10778 & ~GET_MODE_MASK (mode))
10779 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10780 GET_MODE (SUBREG_REG (op0)))
10781 > (unsigned int)
10782 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10783 - GET_MODE_BITSIZE (mode)))))
10785 op0 = SUBREG_REG (op0);
10786 continue;
10789 /* If the inner mode is narrower and we are extracting the low part,
10790 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10791 if (subreg_lowpart_p (op0)
10792 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10793 /* Fall through */ ;
10794 else
10795 break;
10797 /* ... fall through ... */
10799 case ZERO_EXTEND:
10800 if ((unsigned_comparison_p || equality_comparison_p)
10801 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10802 <= HOST_BITS_PER_WIDE_INT)
10803 && ((unsigned HOST_WIDE_INT) const_op
10804 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10806 op0 = XEXP (op0, 0);
10807 continue;
10809 break;
10811 case PLUS:
10812 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10813 this for equality comparisons due to pathological cases involving
10814 overflows. */
10815 if (equality_comparison_p
10816 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10817 op1, XEXP (op0, 1))))
10819 op0 = XEXP (op0, 0);
10820 op1 = tem;
10821 continue;
10824 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10825 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10826 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10828 op0 = XEXP (XEXP (op0, 0), 0);
10829 code = (code == LT ? EQ : NE);
10830 continue;
10832 break;
10834 case MINUS:
10835 /* We used to optimize signed comparisons against zero, but that
10836 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10837 arrive here as equality comparisons, or (GEU, LTU) are
10838 optimized away. No need to special-case them. */
10840 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10841 (eq B (minus A C)), whichever simplifies. We can only do
10842 this for equality comparisons due to pathological cases involving
10843 overflows. */
10844 if (equality_comparison_p
10845 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10846 XEXP (op0, 1), op1)))
10848 op0 = XEXP (op0, 0);
10849 op1 = tem;
10850 continue;
10853 if (equality_comparison_p
10854 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10855 XEXP (op0, 0), op1)))
10857 op0 = XEXP (op0, 1);
10858 op1 = tem;
10859 continue;
10862 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10863 of bits in X minus 1, is one iff X > 0. */
10864 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10865 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10866 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10867 == mode_width - 1
10868 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10870 op0 = XEXP (op0, 1);
10871 code = (code == GE ? LE : GT);
10872 continue;
10874 break;
10876 case XOR:
10877 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10878 if C is zero or B is a constant. */
10879 if (equality_comparison_p
10880 && 0 != (tem = simplify_binary_operation (XOR, mode,
10881 XEXP (op0, 1), op1)))
10883 op0 = XEXP (op0, 0);
10884 op1 = tem;
10885 continue;
10887 break;
10889 case EQ: case NE:
10890 case UNEQ: case LTGT:
10891 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10892 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10893 case UNORDERED: case ORDERED:
10894 /* We can't do anything if OP0 is a condition code value, rather
10895 than an actual data value. */
10896 if (const_op != 0
10897 || CC0_P (XEXP (op0, 0))
10898 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10899 break;
10901 /* Get the two operands being compared. */
10902 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10903 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10904 else
10905 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10907 /* Check for the cases where we simply want the result of the
10908 earlier test or the opposite of that result. */
10909 if (code == NE || code == EQ
10910 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10911 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10912 && (STORE_FLAG_VALUE
10913 & (((HOST_WIDE_INT) 1
10914 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10915 && (code == LT || code == GE)))
10917 enum rtx_code new_code;
10918 if (code == LT || code == NE)
10919 new_code = GET_CODE (op0);
10920 else
10921 new_code = combine_reversed_comparison_code (op0);
10923 if (new_code != UNKNOWN)
10925 code = new_code;
10926 op0 = tem;
10927 op1 = tem1;
10928 continue;
10931 break;
10933 case IOR:
10934 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10935 iff X <= 0. */
10936 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10937 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10938 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10940 op0 = XEXP (op0, 1);
10941 code = (code == GE ? GT : LE);
10942 continue;
10944 break;
10946 case AND:
10947 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10948 will be converted to a ZERO_EXTRACT later. */
10949 if (const_op == 0 && equality_comparison_p
10950 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10951 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10953 op0 = simplify_and_const_int
10954 (op0, mode, gen_rtx_LSHIFTRT (mode,
10955 XEXP (op0, 1),
10956 XEXP (XEXP (op0, 0), 1)),
10957 (HOST_WIDE_INT) 1);
10958 continue;
10961 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10962 zero and X is a comparison and C1 and C2 describe only bits set
10963 in STORE_FLAG_VALUE, we can compare with X. */
10964 if (const_op == 0 && equality_comparison_p
10965 && mode_width <= HOST_BITS_PER_WIDE_INT
10966 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10967 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10968 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10969 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10970 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10972 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10973 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10974 if ((~STORE_FLAG_VALUE & mask) == 0
10975 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10976 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10977 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10979 op0 = XEXP (XEXP (op0, 0), 0);
10980 continue;
10984 /* If we are doing an equality comparison of an AND of a bit equal
10985 to the sign bit, replace this with a LT or GE comparison of
10986 the underlying value. */
10987 if (equality_comparison_p
10988 && const_op == 0
10989 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10990 && mode_width <= HOST_BITS_PER_WIDE_INT
10991 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10992 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10994 op0 = XEXP (op0, 0);
10995 code = (code == EQ ? GE : LT);
10996 continue;
10999 /* If this AND operation is really a ZERO_EXTEND from a narrower
11000 mode, the constant fits within that mode, and this is either an
11001 equality or unsigned comparison, try to do this comparison in
11002 the narrower mode. */
11003 if ((equality_comparison_p || unsigned_comparison_p)
11004 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11005 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11006 & GET_MODE_MASK (mode))
11007 + 1)) >= 0
11008 && const_op >> i == 0
11009 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
11011 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
11012 continue;
11015 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11016 fits in both M1 and M2 and the SUBREG is either paradoxical
11017 or represents the low part, permute the SUBREG and the AND
11018 and try again. */
11019 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11021 unsigned HOST_WIDE_INT c1;
11022 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11023 /* Require an integral mode, to avoid creating something like
11024 (AND:SF ...). */
11025 if (SCALAR_INT_MODE_P (tmode)
11026 /* It is unsafe to commute the AND into the SUBREG if the
11027 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11028 not defined. As originally written the upper bits
11029 have a defined value due to the AND operation.
11030 However, if we commute the AND inside the SUBREG then
11031 they no longer have defined values and the meaning of
11032 the code has been changed. */
11033 && (0
11034 #ifdef WORD_REGISTER_OPERATIONS
11035 || (mode_width > GET_MODE_BITSIZE (tmode)
11036 && mode_width <= BITS_PER_WORD)
11037 #endif
11038 || (mode_width <= GET_MODE_BITSIZE (tmode)
11039 && subreg_lowpart_p (XEXP (op0, 0))))
11040 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11041 && mode_width <= HOST_BITS_PER_WIDE_INT
11042 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11043 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11044 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11045 && c1 != mask
11046 && c1 != GET_MODE_MASK (tmode))
11048 op0 = gen_binary (AND, tmode,
11049 SUBREG_REG (XEXP (op0, 0)),
11050 gen_int_mode (c1, tmode));
11051 op0 = gen_lowpart_for_combine (mode, op0);
11052 continue;
11056 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11057 (eq (and (lshiftrt X) 1) 0). */
11058 if (const_op == 0 && equality_comparison_p
11059 && XEXP (op0, 1) == const1_rtx
11060 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11061 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
11063 op0 = simplify_and_const_int
11064 (op0, mode,
11065 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
11066 XEXP (XEXP (op0, 0), 1)),
11067 (HOST_WIDE_INT) 1);
11068 code = (code == NE ? EQ : NE);
11069 continue;
11071 break;
11073 case ASHIFT:
11074 /* If we have (compare (ashift FOO N) (const_int C)) and
11075 the high order N bits of FOO (N+1 if an inequality comparison)
11076 are known to be zero, we can do this by comparing FOO with C
11077 shifted right N bits so long as the low-order N bits of C are
11078 zero. */
11079 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11080 && INTVAL (XEXP (op0, 1)) >= 0
11081 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11082 < HOST_BITS_PER_WIDE_INT)
11083 && ((const_op
11084 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11085 && mode_width <= HOST_BITS_PER_WIDE_INT
11086 && (nonzero_bits (XEXP (op0, 0), mode)
11087 & ~(mask >> (INTVAL (XEXP (op0, 1))
11088 + ! equality_comparison_p))) == 0)
11090 /* We must perform a logical shift, not an arithmetic one,
11091 as we want the top N bits of C to be zero. */
11092 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11094 temp >>= INTVAL (XEXP (op0, 1));
11095 op1 = gen_int_mode (temp, mode);
11096 op0 = XEXP (op0, 0);
11097 continue;
11100 /* If we are doing a sign bit comparison, it means we are testing
11101 a particular bit. Convert it to the appropriate AND. */
11102 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11103 && mode_width <= HOST_BITS_PER_WIDE_INT)
11105 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11106 ((HOST_WIDE_INT) 1
11107 << (mode_width - 1
11108 - INTVAL (XEXP (op0, 1)))));
11109 code = (code == LT ? NE : EQ);
11110 continue;
11113 /* If this an equality comparison with zero and we are shifting
11114 the low bit to the sign bit, we can convert this to an AND of the
11115 low-order bit. */
11116 if (const_op == 0 && equality_comparison_p
11117 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11118 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11119 == mode_width - 1)
11121 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11122 (HOST_WIDE_INT) 1);
11123 continue;
11125 break;
11127 case ASHIFTRT:
11128 /* If this is an equality comparison with zero, we can do this
11129 as a logical shift, which might be much simpler. */
11130 if (equality_comparison_p && const_op == 0
11131 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11133 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11134 XEXP (op0, 0),
11135 INTVAL (XEXP (op0, 1)));
11136 continue;
11139 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11140 do the comparison in a narrower mode. */
11141 if (! unsigned_comparison_p
11142 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11143 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11144 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11145 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11146 MODE_INT, 1)) != BLKmode
11147 && (((unsigned HOST_WIDE_INT) const_op
11148 + (GET_MODE_MASK (tmode) >> 1) + 1)
11149 <= GET_MODE_MASK (tmode)))
11151 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11152 continue;
11155 /* Likewise if OP0 is a PLUS of a sign extension with a
11156 constant, which is usually represented with the PLUS
11157 between the shifts. */
11158 if (! unsigned_comparison_p
11159 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11160 && GET_CODE (XEXP (op0, 0)) == PLUS
11161 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11162 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11163 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11164 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11165 MODE_INT, 1)) != BLKmode
11166 && (((unsigned HOST_WIDE_INT) const_op
11167 + (GET_MODE_MASK (tmode) >> 1) + 1)
11168 <= GET_MODE_MASK (tmode)))
11170 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11171 rtx add_const = XEXP (XEXP (op0, 0), 1);
11172 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11173 XEXP (op0, 1));
11175 op0 = gen_binary (PLUS, tmode,
11176 gen_lowpart_for_combine (tmode, inner),
11177 new_const);
11178 continue;
11181 /* ... fall through ... */
11182 case LSHIFTRT:
11183 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11184 the low order N bits of FOO are known to be zero, we can do this
11185 by comparing FOO with C shifted left N bits so long as no
11186 overflow occurs. */
11187 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11188 && INTVAL (XEXP (op0, 1)) >= 0
11189 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11190 && mode_width <= HOST_BITS_PER_WIDE_INT
11191 && (nonzero_bits (XEXP (op0, 0), mode)
11192 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11193 && (((unsigned HOST_WIDE_INT) const_op
11194 + (GET_CODE (op0) != LSHIFTRT
11195 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11196 + 1)
11197 : 0))
11198 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11200 /* If the shift was logical, then we must make the condition
11201 unsigned. */
11202 if (GET_CODE (op0) == LSHIFTRT)
11203 code = unsigned_condition (code);
11205 const_op <<= INTVAL (XEXP (op0, 1));
11206 op1 = GEN_INT (const_op);
11207 op0 = XEXP (op0, 0);
11208 continue;
11211 /* If we are using this shift to extract just the sign bit, we
11212 can replace this with an LT or GE comparison. */
11213 if (const_op == 0
11214 && (equality_comparison_p || sign_bit_comparison_p)
11215 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11216 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11217 == mode_width - 1)
11219 op0 = XEXP (op0, 0);
11220 code = (code == NE || code == GT ? LT : GE);
11221 continue;
11223 break;
11225 default:
11226 break;
11229 break;
11232 /* Now make any compound operations involved in this comparison. Then,
11233 check for an outmost SUBREG on OP0 that is not doing anything or is
11234 paradoxical. The latter transformation must only be performed when
11235 it is known that the "extra" bits will be the same in op0 and op1 or
11236 that they don't matter. There are three cases to consider:
11238 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11239 care bits and we can assume they have any convenient value. So
11240 making the transformation is safe.
11242 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11243 In this case the upper bits of op0 are undefined. We should not make
11244 the simplification in that case as we do not know the contents of
11245 those bits.
11247 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11248 NIL. In that case we know those bits are zeros or ones. We must
11249 also be sure that they are the same as the upper bits of op1.
11251 We can never remove a SUBREG for a non-equality comparison because
11252 the sign bit is in a different place in the underlying object. */
11254 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11255 op1 = make_compound_operation (op1, SET);
11257 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11258 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11259 implemented. */
11260 && GET_CODE (SUBREG_REG (op0)) == REG
11261 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11262 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11263 && (code == NE || code == EQ))
11265 if (GET_MODE_SIZE (GET_MODE (op0))
11266 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11268 op0 = SUBREG_REG (op0);
11269 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11271 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11272 <= HOST_BITS_PER_WIDE_INT)
11273 && (nonzero_bits (SUBREG_REG (op0),
11274 GET_MODE (SUBREG_REG (op0)))
11275 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11277 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11279 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11280 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11281 op0 = SUBREG_REG (op0), op1 = tem;
11285 /* We now do the opposite procedure: Some machines don't have compare
11286 insns in all modes. If OP0's mode is an integer mode smaller than a
11287 word and we can't do a compare in that mode, see if there is a larger
11288 mode for which we can do the compare. There are a number of cases in
11289 which we can use the wider mode. */
11291 mode = GET_MODE (op0);
11292 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11293 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11294 && ! have_insn_for (COMPARE, mode))
11295 for (tmode = GET_MODE_WIDER_MODE (mode);
11296 (tmode != VOIDmode
11297 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11298 tmode = GET_MODE_WIDER_MODE (tmode))
11299 if (have_insn_for (COMPARE, tmode))
11301 int zero_extended;
11303 /* If the only nonzero bits in OP0 and OP1 are those in the
11304 narrower mode and this is an equality or unsigned comparison,
11305 we can use the wider mode. Similarly for sign-extended
11306 values, in which case it is true for all comparisons. */
11307 zero_extended = ((code == EQ || code == NE
11308 || code == GEU || code == GTU
11309 || code == LEU || code == LTU)
11310 && (nonzero_bits (op0, tmode)
11311 & ~GET_MODE_MASK (mode)) == 0
11312 && ((GET_CODE (op1) == CONST_INT
11313 || (nonzero_bits (op1, tmode)
11314 & ~GET_MODE_MASK (mode)) == 0)));
11316 if (zero_extended
11317 || ((num_sign_bit_copies (op0, tmode)
11318 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11319 - GET_MODE_BITSIZE (mode)))
11320 && (num_sign_bit_copies (op1, tmode)
11321 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11322 - GET_MODE_BITSIZE (mode)))))
11324 /* If OP0 is an AND and we don't have an AND in MODE either,
11325 make a new AND in the proper mode. */
11326 if (GET_CODE (op0) == AND
11327 && !have_insn_for (AND, mode))
11328 op0 = gen_binary (AND, tmode,
11329 gen_lowpart_for_combine (tmode,
11330 XEXP (op0, 0)),
11331 gen_lowpart_for_combine (tmode,
11332 XEXP (op0, 1)));
11334 op0 = gen_lowpart_for_combine (tmode, op0);
11335 if (zero_extended && GET_CODE (op1) == CONST_INT)
11336 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11337 op1 = gen_lowpart_for_combine (tmode, op1);
11338 break;
11341 /* If this is a test for negative, we can make an explicit
11342 test of the sign bit. */
11344 if (op1 == const0_rtx && (code == LT || code == GE)
11345 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11347 op0 = gen_binary (AND, tmode,
11348 gen_lowpart_for_combine (tmode, op0),
11349 GEN_INT ((HOST_WIDE_INT) 1
11350 << (GET_MODE_BITSIZE (mode) - 1)));
11351 code = (code == LT) ? NE : EQ;
11352 break;
11356 #ifdef CANONICALIZE_COMPARISON
11357 /* If this machine only supports a subset of valid comparisons, see if we
11358 can convert an unsupported one into a supported one. */
11359 CANONICALIZE_COMPARISON (code, op0, op1);
11360 #endif
11362 *pop0 = op0;
11363 *pop1 = op1;
11365 return code;
11368 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11369 searching backward. */
11370 static enum rtx_code
11371 combine_reversed_comparison_code (rtx exp)
11373 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11374 rtx x;
11376 if (code1 != UNKNOWN
11377 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11378 return code1;
11379 /* Otherwise try and find where the condition codes were last set and
11380 use that. */
11381 x = get_last_value (XEXP (exp, 0));
11382 if (!x || GET_CODE (x) != COMPARE)
11383 return UNKNOWN;
11384 return reversed_comparison_code_parts (GET_CODE (exp),
11385 XEXP (x, 0), XEXP (x, 1), NULL);
11388 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11389 Return NULL_RTX in case we fail to do the reversal. */
11390 static rtx
11391 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
11393 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11394 if (reversed_code == UNKNOWN)
11395 return NULL_RTX;
11396 else
11397 return gen_binary (reversed_code, mode, op0, op1);
11400 /* Utility function for following routine. Called when X is part of a value
11401 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11402 for each register mentioned. Similar to mention_regs in cse.c */
11404 static void
11405 update_table_tick (rtx x)
11407 enum rtx_code code = GET_CODE (x);
11408 const char *fmt = GET_RTX_FORMAT (code);
11409 int i;
11411 if (code == REG)
11413 unsigned int regno = REGNO (x);
11414 unsigned int endregno
11415 = regno + (regno < FIRST_PSEUDO_REGISTER
11416 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11417 unsigned int r;
11419 for (r = regno; r < endregno; r++)
11420 reg_last_set_table_tick[r] = label_tick;
11422 return;
11425 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11426 /* Note that we can't have an "E" in values stored; see
11427 get_last_value_validate. */
11428 if (fmt[i] == 'e')
11430 /* Check for identical subexpressions. If x contains
11431 identical subexpression we only have to traverse one of
11432 them. */
11433 if (i == 0
11434 && (GET_RTX_CLASS (code) == '2'
11435 || GET_RTX_CLASS (code) == 'c'))
11437 /* Note that at this point x1 has already been
11438 processed. */
11439 rtx x0 = XEXP (x, 0);
11440 rtx x1 = XEXP (x, 1);
11442 /* If x0 and x1 are identical then there is no need to
11443 process x0. */
11444 if (x0 == x1)
11445 break;
11447 /* If x0 is identical to a subexpression of x1 then while
11448 processing x1, x0 has already been processed. Thus we
11449 are done with x. */
11450 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11451 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11452 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11453 break;
11455 /* If x1 is identical to a subexpression of x0 then we
11456 still have to process the rest of x0. */
11457 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11458 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11459 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11461 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11462 break;
11466 update_table_tick (XEXP (x, i));
11470 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11471 are saying that the register is clobbered and we no longer know its
11472 value. If INSN is zero, don't update reg_last_set; this is only permitted
11473 with VALUE also zero and is used to invalidate the register. */
11475 static void
11476 record_value_for_reg (rtx reg, rtx insn, rtx value)
11478 unsigned int regno = REGNO (reg);
11479 unsigned int endregno
11480 = regno + (regno < FIRST_PSEUDO_REGISTER
11481 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11482 unsigned int i;
11484 /* If VALUE contains REG and we have a previous value for REG, substitute
11485 the previous value. */
11486 if (value && insn && reg_overlap_mentioned_p (reg, value))
11488 rtx tem;
11490 /* Set things up so get_last_value is allowed to see anything set up to
11491 our insn. */
11492 subst_low_cuid = INSN_CUID (insn);
11493 tem = get_last_value (reg);
11495 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11496 it isn't going to be useful and will take a lot of time to process,
11497 so just use the CLOBBER. */
11499 if (tem)
11501 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11502 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11503 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11504 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11505 tem = XEXP (tem, 0);
11507 value = replace_rtx (copy_rtx (value), reg, tem);
11511 /* For each register modified, show we don't know its value, that
11512 we don't know about its bitwise content, that its value has been
11513 updated, and that we don't know the location of the death of the
11514 register. */
11515 for (i = regno; i < endregno; i++)
11517 if (insn)
11518 reg_last_set[i] = insn;
11520 reg_last_set_value[i] = 0;
11521 reg_last_set_mode[i] = 0;
11522 reg_last_set_nonzero_bits[i] = 0;
11523 reg_last_set_sign_bit_copies[i] = 0;
11524 reg_last_death[i] = 0;
11527 /* Mark registers that are being referenced in this value. */
11528 if (value)
11529 update_table_tick (value);
11531 /* Now update the status of each register being set.
11532 If someone is using this register in this block, set this register
11533 to invalid since we will get confused between the two lives in this
11534 basic block. This makes using this register always invalid. In cse, we
11535 scan the table to invalidate all entries using this register, but this
11536 is too much work for us. */
11538 for (i = regno; i < endregno; i++)
11540 reg_last_set_label[i] = label_tick;
11541 if (value && reg_last_set_table_tick[i] == label_tick)
11542 reg_last_set_invalid[i] = 1;
11543 else
11544 reg_last_set_invalid[i] = 0;
11547 /* The value being assigned might refer to X (like in "x++;"). In that
11548 case, we must replace it with (clobber (const_int 0)) to prevent
11549 infinite loops. */
11550 if (value && ! get_last_value_validate (&value, insn,
11551 reg_last_set_label[regno], 0))
11553 value = copy_rtx (value);
11554 if (! get_last_value_validate (&value, insn,
11555 reg_last_set_label[regno], 1))
11556 value = 0;
11559 /* For the main register being modified, update the value, the mode, the
11560 nonzero bits, and the number of sign bit copies. */
11562 reg_last_set_value[regno] = value;
11564 if (value)
11566 enum machine_mode mode = GET_MODE (reg);
11567 subst_low_cuid = INSN_CUID (insn);
11568 reg_last_set_mode[regno] = mode;
11569 if (GET_MODE_CLASS (mode) == MODE_INT
11570 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11571 mode = nonzero_bits_mode;
11572 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11573 reg_last_set_sign_bit_copies[regno]
11574 = num_sign_bit_copies (value, GET_MODE (reg));
11578 /* Called via note_stores from record_dead_and_set_regs to handle one
11579 SET or CLOBBER in an insn. DATA is the instruction in which the
11580 set is occurring. */
11582 static void
11583 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11585 rtx record_dead_insn = (rtx) data;
11587 if (GET_CODE (dest) == SUBREG)
11588 dest = SUBREG_REG (dest);
11590 if (GET_CODE (dest) == REG)
11592 /* If we are setting the whole register, we know its value. Otherwise
11593 show that we don't know the value. We can handle SUBREG in
11594 some cases. */
11595 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11596 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11597 else if (GET_CODE (setter) == SET
11598 && GET_CODE (SET_DEST (setter)) == SUBREG
11599 && SUBREG_REG (SET_DEST (setter)) == dest
11600 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11601 && subreg_lowpart_p (SET_DEST (setter)))
11602 record_value_for_reg (dest, record_dead_insn,
11603 gen_lowpart_for_combine (GET_MODE (dest),
11604 SET_SRC (setter)));
11605 else
11606 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11608 else if (GET_CODE (dest) == MEM
11609 /* Ignore pushes, they clobber nothing. */
11610 && ! push_operand (dest, GET_MODE (dest)))
11611 mem_last_set = INSN_CUID (record_dead_insn);
11614 /* Update the records of when each REG was most recently set or killed
11615 for the things done by INSN. This is the last thing done in processing
11616 INSN in the combiner loop.
11618 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11619 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11620 and also the similar information mem_last_set (which insn most recently
11621 modified memory) and last_call_cuid (which insn was the most recent
11622 subroutine call). */
11624 static void
11625 record_dead_and_set_regs (rtx insn)
11627 rtx link;
11628 unsigned int i;
11630 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11632 if (REG_NOTE_KIND (link) == REG_DEAD
11633 && GET_CODE (XEXP (link, 0)) == REG)
11635 unsigned int regno = REGNO (XEXP (link, 0));
11636 unsigned int endregno
11637 = regno + (regno < FIRST_PSEUDO_REGISTER
11638 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11639 : 1);
11641 for (i = regno; i < endregno; i++)
11642 reg_last_death[i] = insn;
11644 else if (REG_NOTE_KIND (link) == REG_INC)
11645 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11648 if (GET_CODE (insn) == CALL_INSN)
11650 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11651 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11653 reg_last_set_value[i] = 0;
11654 reg_last_set_mode[i] = 0;
11655 reg_last_set_nonzero_bits[i] = 0;
11656 reg_last_set_sign_bit_copies[i] = 0;
11657 reg_last_death[i] = 0;
11660 last_call_cuid = mem_last_set = INSN_CUID (insn);
11662 /* Don't bother recording what this insn does. It might set the
11663 return value register, but we can't combine into a call
11664 pattern anyway, so there's no point trying (and it may cause
11665 a crash, if e.g. we wind up asking for last_set_value of a
11666 SUBREG of the return value register). */
11667 return;
11670 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11673 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11674 register present in the SUBREG, so for each such SUBREG go back and
11675 adjust nonzero and sign bit information of the registers that are
11676 known to have some zero/sign bits set.
11678 This is needed because when combine blows the SUBREGs away, the
11679 information on zero/sign bits is lost and further combines can be
11680 missed because of that. */
11682 static void
11683 record_promoted_value (rtx insn, rtx subreg)
11685 rtx links, set;
11686 unsigned int regno = REGNO (SUBREG_REG (subreg));
11687 enum machine_mode mode = GET_MODE (subreg);
11689 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11690 return;
11692 for (links = LOG_LINKS (insn); links;)
11694 insn = XEXP (links, 0);
11695 set = single_set (insn);
11697 if (! set || GET_CODE (SET_DEST (set)) != REG
11698 || REGNO (SET_DEST (set)) != regno
11699 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11701 links = XEXP (links, 1);
11702 continue;
11705 if (reg_last_set[regno] == insn)
11707 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11708 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11711 if (GET_CODE (SET_SRC (set)) == REG)
11713 regno = REGNO (SET_SRC (set));
11714 links = LOG_LINKS (insn);
11716 else
11717 break;
11721 /* Scan X for promoted SUBREGs. For each one found,
11722 note what it implies to the registers used in it. */
11724 static void
11725 check_promoted_subreg (rtx insn, rtx x)
11727 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11728 && GET_CODE (SUBREG_REG (x)) == REG)
11729 record_promoted_value (insn, x);
11730 else
11732 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11733 int i, j;
11735 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11736 switch (format[i])
11738 case 'e':
11739 check_promoted_subreg (insn, XEXP (x, i));
11740 break;
11741 case 'V':
11742 case 'E':
11743 if (XVEC (x, i) != 0)
11744 for (j = 0; j < XVECLEN (x, i); j++)
11745 check_promoted_subreg (insn, XVECEXP (x, i, j));
11746 break;
11751 /* Utility routine for the following function. Verify that all the registers
11752 mentioned in *LOC are valid when *LOC was part of a value set when
11753 label_tick == TICK. Return 0 if some are not.
11755 If REPLACE is nonzero, replace the invalid reference with
11756 (clobber (const_int 0)) and return 1. This replacement is useful because
11757 we often can get useful information about the form of a value (e.g., if
11758 it was produced by a shift that always produces -1 or 0) even though
11759 we don't know exactly what registers it was produced from. */
11761 static int
11762 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11764 rtx x = *loc;
11765 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11766 int len = GET_RTX_LENGTH (GET_CODE (x));
11767 int i;
11769 if (GET_CODE (x) == REG)
11771 unsigned int regno = REGNO (x);
11772 unsigned int endregno
11773 = regno + (regno < FIRST_PSEUDO_REGISTER
11774 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11775 unsigned int j;
11777 for (j = regno; j < endregno; j++)
11778 if (reg_last_set_invalid[j]
11779 /* If this is a pseudo-register that was only set once and not
11780 live at the beginning of the function, it is always valid. */
11781 || (! (regno >= FIRST_PSEUDO_REGISTER
11782 && REG_N_SETS (regno) == 1
11783 && (! REGNO_REG_SET_P
11784 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11785 && reg_last_set_label[j] > tick))
11787 if (replace)
11788 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11789 return replace;
11792 return 1;
11794 /* If this is a memory reference, make sure that there were
11795 no stores after it that might have clobbered the value. We don't
11796 have alias info, so we assume any store invalidates it. */
11797 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11798 && INSN_CUID (insn) <= mem_last_set)
11800 if (replace)
11801 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11802 return replace;
11805 for (i = 0; i < len; i++)
11807 if (fmt[i] == 'e')
11809 /* Check for identical subexpressions. If x contains
11810 identical subexpression we only have to traverse one of
11811 them. */
11812 if (i == 1
11813 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11814 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11816 /* Note that at this point x0 has already been checked
11817 and found valid. */
11818 rtx x0 = XEXP (x, 0);
11819 rtx x1 = XEXP (x, 1);
11821 /* If x0 and x1 are identical then x is also valid. */
11822 if (x0 == x1)
11823 return 1;
11825 /* If x1 is identical to a subexpression of x0 then
11826 while checking x0, x1 has already been checked. Thus
11827 it is valid and so as x. */
11828 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11829 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11830 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11831 return 1;
11833 /* If x0 is identical to a subexpression of x1 then x is
11834 valid iff the rest of x1 is valid. */
11835 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11836 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11837 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11838 return
11839 get_last_value_validate (&XEXP (x1,
11840 x0 == XEXP (x1, 0) ? 1 : 0),
11841 insn, tick, replace);
11844 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11845 replace) == 0)
11846 return 0;
11848 /* Don't bother with these. They shouldn't occur anyway. */
11849 else if (fmt[i] == 'E')
11850 return 0;
11853 /* If we haven't found a reason for it to be invalid, it is valid. */
11854 return 1;
11857 /* Get the last value assigned to X, if known. Some registers
11858 in the value may be replaced with (clobber (const_int 0)) if their value
11859 is known longer known reliably. */
11861 static rtx
11862 get_last_value (rtx x)
11864 unsigned int regno;
11865 rtx value;
11867 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11868 then convert it to the desired mode. If this is a paradoxical SUBREG,
11869 we cannot predict what values the "extra" bits might have. */
11870 if (GET_CODE (x) == SUBREG
11871 && subreg_lowpart_p (x)
11872 && (GET_MODE_SIZE (GET_MODE (x))
11873 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11874 && (value = get_last_value (SUBREG_REG (x))) != 0)
11875 return gen_lowpart_for_combine (GET_MODE (x), value);
11877 if (GET_CODE (x) != REG)
11878 return 0;
11880 regno = REGNO (x);
11881 value = reg_last_set_value[regno];
11883 /* If we don't have a value, or if it isn't for this basic block and
11884 it's either a hard register, set more than once, or it's a live
11885 at the beginning of the function, return 0.
11887 Because if it's not live at the beginning of the function then the reg
11888 is always set before being used (is never used without being set).
11889 And, if it's set only once, and it's always set before use, then all
11890 uses must have the same last value, even if it's not from this basic
11891 block. */
11893 if (value == 0
11894 || (reg_last_set_label[regno] != label_tick
11895 && (regno < FIRST_PSEUDO_REGISTER
11896 || REG_N_SETS (regno) != 1
11897 || (REGNO_REG_SET_P
11898 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11899 return 0;
11901 /* If the value was set in a later insn than the ones we are processing,
11902 we can't use it even if the register was only set once. */
11903 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11904 return 0;
11906 /* If the value has all its registers valid, return it. */
11907 if (get_last_value_validate (&value, reg_last_set[regno],
11908 reg_last_set_label[regno], 0))
11909 return value;
11911 /* Otherwise, make a copy and replace any invalid register with
11912 (clobber (const_int 0)). If that fails for some reason, return 0. */
11914 value = copy_rtx (value);
11915 if (get_last_value_validate (&value, reg_last_set[regno],
11916 reg_last_set_label[regno], 1))
11917 return value;
11919 return 0;
11922 /* Return nonzero if expression X refers to a REG or to memory
11923 that is set in an instruction more recent than FROM_CUID. */
11925 static int
11926 use_crosses_set_p (rtx x, int from_cuid)
11928 const char *fmt;
11929 int i;
11930 enum rtx_code code = GET_CODE (x);
11932 if (code == REG)
11934 unsigned int regno = REGNO (x);
11935 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11936 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11938 #ifdef PUSH_ROUNDING
11939 /* Don't allow uses of the stack pointer to be moved,
11940 because we don't know whether the move crosses a push insn. */
11941 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11942 return 1;
11943 #endif
11944 for (; regno < endreg; regno++)
11945 if (reg_last_set[regno]
11946 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11947 return 1;
11948 return 0;
11951 if (code == MEM && mem_last_set > from_cuid)
11952 return 1;
11954 fmt = GET_RTX_FORMAT (code);
11956 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11958 if (fmt[i] == 'E')
11960 int j;
11961 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11962 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11963 return 1;
11965 else if (fmt[i] == 'e'
11966 && use_crosses_set_p (XEXP (x, i), from_cuid))
11967 return 1;
11969 return 0;
11972 /* Define three variables used for communication between the following
11973 routines. */
11975 static unsigned int reg_dead_regno, reg_dead_endregno;
11976 static int reg_dead_flag;
11978 /* Function called via note_stores from reg_dead_at_p.
11980 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11981 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11983 static void
11984 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11986 unsigned int regno, endregno;
11988 if (GET_CODE (dest) != REG)
11989 return;
11991 regno = REGNO (dest);
11992 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11993 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11995 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11996 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11999 /* Return nonzero if REG is known to be dead at INSN.
12001 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12002 referencing REG, it is dead. If we hit a SET referencing REG, it is
12003 live. Otherwise, see if it is live or dead at the start of the basic
12004 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12005 must be assumed to be always live. */
12007 static int
12008 reg_dead_at_p (rtx reg, rtx insn)
12010 basic_block block;
12011 unsigned int i;
12013 /* Set variables for reg_dead_at_p_1. */
12014 reg_dead_regno = REGNO (reg);
12015 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
12016 ? HARD_REGNO_NREGS (reg_dead_regno,
12017 GET_MODE (reg))
12018 : 1);
12020 reg_dead_flag = 0;
12022 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12023 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12025 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12026 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
12027 return 0;
12030 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12031 beginning of function. */
12032 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
12033 insn = prev_nonnote_insn (insn))
12035 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12036 if (reg_dead_flag)
12037 return reg_dead_flag == 1 ? 1 : 0;
12039 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12040 return 1;
12043 /* Get the basic block that we were in. */
12044 if (insn == 0)
12045 block = ENTRY_BLOCK_PTR->next_bb;
12046 else
12048 FOR_EACH_BB (block)
12049 if (insn == block->head)
12050 break;
12052 if (block == EXIT_BLOCK_PTR)
12053 return 0;
12056 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12057 if (REGNO_REG_SET_P (block->global_live_at_start, i))
12058 return 0;
12060 return 1;
12063 /* Note hard registers in X that are used. This code is similar to
12064 that in flow.c, but much simpler since we don't care about pseudos. */
12066 static void
12067 mark_used_regs_combine (rtx x)
12069 RTX_CODE code = GET_CODE (x);
12070 unsigned int regno;
12071 int i;
12073 switch (code)
12075 case LABEL_REF:
12076 case SYMBOL_REF:
12077 case CONST_INT:
12078 case CONST:
12079 case CONST_DOUBLE:
12080 case CONST_VECTOR:
12081 case PC:
12082 case ADDR_VEC:
12083 case ADDR_DIFF_VEC:
12084 case ASM_INPUT:
12085 #ifdef HAVE_cc0
12086 /* CC0 must die in the insn after it is set, so we don't need to take
12087 special note of it here. */
12088 case CC0:
12089 #endif
12090 return;
12092 case CLOBBER:
12093 /* If we are clobbering a MEM, mark any hard registers inside the
12094 address as used. */
12095 if (GET_CODE (XEXP (x, 0)) == MEM)
12096 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12097 return;
12099 case REG:
12100 regno = REGNO (x);
12101 /* A hard reg in a wide mode may really be multiple registers.
12102 If so, mark all of them just like the first. */
12103 if (regno < FIRST_PSEUDO_REGISTER)
12105 unsigned int endregno, r;
12107 /* None of this applies to the stack, frame or arg pointers. */
12108 if (regno == STACK_POINTER_REGNUM
12109 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12110 || regno == HARD_FRAME_POINTER_REGNUM
12111 #endif
12112 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12113 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12114 #endif
12115 || regno == FRAME_POINTER_REGNUM)
12116 return;
12118 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12119 for (r = regno; r < endregno; r++)
12120 SET_HARD_REG_BIT (newpat_used_regs, r);
12122 return;
12124 case SET:
12126 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12127 the address. */
12128 rtx testreg = SET_DEST (x);
12130 while (GET_CODE (testreg) == SUBREG
12131 || GET_CODE (testreg) == ZERO_EXTRACT
12132 || GET_CODE (testreg) == SIGN_EXTRACT
12133 || GET_CODE (testreg) == STRICT_LOW_PART)
12134 testreg = XEXP (testreg, 0);
12136 if (GET_CODE (testreg) == MEM)
12137 mark_used_regs_combine (XEXP (testreg, 0));
12139 mark_used_regs_combine (SET_SRC (x));
12141 return;
12143 default:
12144 break;
12147 /* Recursively scan the operands of this expression. */
12150 const char *fmt = GET_RTX_FORMAT (code);
12152 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12154 if (fmt[i] == 'e')
12155 mark_used_regs_combine (XEXP (x, i));
12156 else if (fmt[i] == 'E')
12158 int j;
12160 for (j = 0; j < XVECLEN (x, i); j++)
12161 mark_used_regs_combine (XVECEXP (x, i, j));
12167 /* Remove register number REGNO from the dead registers list of INSN.
12169 Return the note used to record the death, if there was one. */
12172 remove_death (unsigned int regno, rtx insn)
12174 rtx note = find_regno_note (insn, REG_DEAD, regno);
12176 if (note)
12178 REG_N_DEATHS (regno)--;
12179 remove_note (insn, note);
12182 return note;
12185 /* For each register (hardware or pseudo) used within expression X, if its
12186 death is in an instruction with cuid between FROM_CUID (inclusive) and
12187 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12188 list headed by PNOTES.
12190 That said, don't move registers killed by maybe_kill_insn.
12192 This is done when X is being merged by combination into TO_INSN. These
12193 notes will then be distributed as needed. */
12195 static void
12196 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
12197 rtx *pnotes)
12199 const char *fmt;
12200 int len, i;
12201 enum rtx_code code = GET_CODE (x);
12203 if (code == REG)
12205 unsigned int regno = REGNO (x);
12206 rtx where_dead = reg_last_death[regno];
12207 rtx before_dead, after_dead;
12209 /* Don't move the register if it gets killed in between from and to. */
12210 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12211 && ! reg_referenced_p (x, maybe_kill_insn))
12212 return;
12214 /* WHERE_DEAD could be a USE insn made by combine, so first we
12215 make sure that we have insns with valid INSN_CUID values. */
12216 before_dead = where_dead;
12217 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12218 before_dead = PREV_INSN (before_dead);
12220 after_dead = where_dead;
12221 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12222 after_dead = NEXT_INSN (after_dead);
12224 if (before_dead && after_dead
12225 && INSN_CUID (before_dead) >= from_cuid
12226 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12227 || (where_dead != after_dead
12228 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12230 rtx note = remove_death (regno, where_dead);
12232 /* It is possible for the call above to return 0. This can occur
12233 when reg_last_death points to I2 or I1 that we combined with.
12234 In that case make a new note.
12236 We must also check for the case where X is a hard register
12237 and NOTE is a death note for a range of hard registers
12238 including X. In that case, we must put REG_DEAD notes for
12239 the remaining registers in place of NOTE. */
12241 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12242 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12243 > GET_MODE_SIZE (GET_MODE (x))))
12245 unsigned int deadregno = REGNO (XEXP (note, 0));
12246 unsigned int deadend
12247 = (deadregno + HARD_REGNO_NREGS (deadregno,
12248 GET_MODE (XEXP (note, 0))));
12249 unsigned int ourend
12250 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12251 unsigned int i;
12253 for (i = deadregno; i < deadend; i++)
12254 if (i < regno || i >= ourend)
12255 REG_NOTES (where_dead)
12256 = gen_rtx_EXPR_LIST (REG_DEAD,
12257 regno_reg_rtx[i],
12258 REG_NOTES (where_dead));
12261 /* If we didn't find any note, or if we found a REG_DEAD note that
12262 covers only part of the given reg, and we have a multi-reg hard
12263 register, then to be safe we must check for REG_DEAD notes
12264 for each register other than the first. They could have
12265 their own REG_DEAD notes lying around. */
12266 else if ((note == 0
12267 || (note != 0
12268 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12269 < GET_MODE_SIZE (GET_MODE (x)))))
12270 && regno < FIRST_PSEUDO_REGISTER
12271 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12273 unsigned int ourend
12274 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12275 unsigned int i, offset;
12276 rtx oldnotes = 0;
12278 if (note)
12279 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12280 else
12281 offset = 1;
12283 for (i = regno + offset; i < ourend; i++)
12284 move_deaths (regno_reg_rtx[i],
12285 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12288 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12290 XEXP (note, 1) = *pnotes;
12291 *pnotes = note;
12293 else
12294 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12296 REG_N_DEATHS (regno)++;
12299 return;
12302 else if (GET_CODE (x) == SET)
12304 rtx dest = SET_DEST (x);
12306 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12308 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12309 that accesses one word of a multi-word item, some
12310 piece of everything register in the expression is used by
12311 this insn, so remove any old death. */
12312 /* ??? So why do we test for equality of the sizes? */
12314 if (GET_CODE (dest) == ZERO_EXTRACT
12315 || GET_CODE (dest) == STRICT_LOW_PART
12316 || (GET_CODE (dest) == SUBREG
12317 && (((GET_MODE_SIZE (GET_MODE (dest))
12318 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12319 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12320 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12322 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12323 return;
12326 /* If this is some other SUBREG, we know it replaces the entire
12327 value, so use that as the destination. */
12328 if (GET_CODE (dest) == SUBREG)
12329 dest = SUBREG_REG (dest);
12331 /* If this is a MEM, adjust deaths of anything used in the address.
12332 For a REG (the only other possibility), the entire value is
12333 being replaced so the old value is not used in this insn. */
12335 if (GET_CODE (dest) == MEM)
12336 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12337 to_insn, pnotes);
12338 return;
12341 else if (GET_CODE (x) == CLOBBER)
12342 return;
12344 len = GET_RTX_LENGTH (code);
12345 fmt = GET_RTX_FORMAT (code);
12347 for (i = 0; i < len; i++)
12349 if (fmt[i] == 'E')
12351 int j;
12352 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12353 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12354 to_insn, pnotes);
12356 else if (fmt[i] == 'e')
12357 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12361 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12362 pattern of an insn. X must be a REG. */
12364 static int
12365 reg_bitfield_target_p (rtx x, rtx body)
12367 int i;
12369 if (GET_CODE (body) == SET)
12371 rtx dest = SET_DEST (body);
12372 rtx target;
12373 unsigned int regno, tregno, endregno, endtregno;
12375 if (GET_CODE (dest) == ZERO_EXTRACT)
12376 target = XEXP (dest, 0);
12377 else if (GET_CODE (dest) == STRICT_LOW_PART)
12378 target = SUBREG_REG (XEXP (dest, 0));
12379 else
12380 return 0;
12382 if (GET_CODE (target) == SUBREG)
12383 target = SUBREG_REG (target);
12385 if (GET_CODE (target) != REG)
12386 return 0;
12388 tregno = REGNO (target), regno = REGNO (x);
12389 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12390 return target == x;
12392 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12393 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12395 return endregno > tregno && regno < endtregno;
12398 else if (GET_CODE (body) == PARALLEL)
12399 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12400 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12401 return 1;
12403 return 0;
12406 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12407 as appropriate. I3 and I2 are the insns resulting from the combination
12408 insns including FROM (I2 may be zero).
12410 Each note in the list is either ignored or placed on some insns, depending
12411 on the type of note. */
12413 static void
12414 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
12416 rtx note, next_note;
12417 rtx tem;
12419 for (note = notes; note; note = next_note)
12421 rtx place = 0, place2 = 0;
12423 /* If this NOTE references a pseudo register, ensure it references
12424 the latest copy of that register. */
12425 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12426 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12427 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12429 next_note = XEXP (note, 1);
12430 switch (REG_NOTE_KIND (note))
12432 case REG_BR_PROB:
12433 case REG_BR_PRED:
12434 /* Doesn't matter much where we put this, as long as it's somewhere.
12435 It is preferable to keep these notes on branches, which is most
12436 likely to be i3. */
12437 place = i3;
12438 break;
12440 case REG_VTABLE_REF:
12441 /* ??? Should remain with *a particular* memory load. Given the
12442 nature of vtable data, the last insn seems relatively safe. */
12443 place = i3;
12444 break;
12446 case REG_NON_LOCAL_GOTO:
12447 if (GET_CODE (i3) == JUMP_INSN)
12448 place = i3;
12449 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12450 place = i2;
12451 else
12452 abort ();
12453 break;
12455 case REG_EH_REGION:
12456 /* These notes must remain with the call or trapping instruction. */
12457 if (GET_CODE (i3) == CALL_INSN)
12458 place = i3;
12459 else if (i2 && GET_CODE (i2) == CALL_INSN)
12460 place = i2;
12461 else if (flag_non_call_exceptions)
12463 if (may_trap_p (i3))
12464 place = i3;
12465 else if (i2 && may_trap_p (i2))
12466 place = i2;
12467 /* ??? Otherwise assume we've combined things such that we
12468 can now prove that the instructions can't trap. Drop the
12469 note in this case. */
12471 else
12472 abort ();
12473 break;
12475 case REG_NORETURN:
12476 case REG_SETJMP:
12477 /* These notes must remain with the call. It should not be
12478 possible for both I2 and I3 to be a call. */
12479 if (GET_CODE (i3) == CALL_INSN)
12480 place = i3;
12481 else if (i2 && GET_CODE (i2) == CALL_INSN)
12482 place = i2;
12483 else
12484 abort ();
12485 break;
12487 case REG_UNUSED:
12488 /* Any clobbers for i3 may still exist, and so we must process
12489 REG_UNUSED notes from that insn.
12491 Any clobbers from i2 or i1 can only exist if they were added by
12492 recog_for_combine. In that case, recog_for_combine created the
12493 necessary REG_UNUSED notes. Trying to keep any original
12494 REG_UNUSED notes from these insns can cause incorrect output
12495 if it is for the same register as the original i3 dest.
12496 In that case, we will notice that the register is set in i3,
12497 and then add a REG_UNUSED note for the destination of i3, which
12498 is wrong. However, it is possible to have REG_UNUSED notes from
12499 i2 or i1 for register which were both used and clobbered, so
12500 we keep notes from i2 or i1 if they will turn into REG_DEAD
12501 notes. */
12503 /* If this register is set or clobbered in I3, put the note there
12504 unless there is one already. */
12505 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12507 if (from_insn != i3)
12508 break;
12510 if (! (GET_CODE (XEXP (note, 0)) == REG
12511 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12512 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12513 place = i3;
12515 /* Otherwise, if this register is used by I3, then this register
12516 now dies here, so we must put a REG_DEAD note here unless there
12517 is one already. */
12518 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12519 && ! (GET_CODE (XEXP (note, 0)) == REG
12520 ? find_regno_note (i3, REG_DEAD,
12521 REGNO (XEXP (note, 0)))
12522 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12524 PUT_REG_NOTE_KIND (note, REG_DEAD);
12525 place = i3;
12527 break;
12529 case REG_EQUAL:
12530 case REG_EQUIV:
12531 case REG_NOALIAS:
12532 /* These notes say something about results of an insn. We can
12533 only support them if they used to be on I3 in which case they
12534 remain on I3. Otherwise they are ignored.
12536 If the note refers to an expression that is not a constant, we
12537 must also ignore the note since we cannot tell whether the
12538 equivalence is still true. It might be possible to do
12539 slightly better than this (we only have a problem if I2DEST
12540 or I1DEST is present in the expression), but it doesn't
12541 seem worth the trouble. */
12543 if (from_insn == i3
12544 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12545 place = i3;
12546 break;
12548 case REG_INC:
12549 case REG_NO_CONFLICT:
12550 /* These notes say something about how a register is used. They must
12551 be present on any use of the register in I2 or I3. */
12552 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12553 place = i3;
12555 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12557 if (place)
12558 place2 = i2;
12559 else
12560 place = i2;
12562 break;
12564 case REG_LABEL:
12565 /* This can show up in several ways -- either directly in the
12566 pattern, or hidden off in the constant pool with (or without?)
12567 a REG_EQUAL note. */
12568 /* ??? Ignore the without-reg_equal-note problem for now. */
12569 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12570 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12571 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12572 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12573 place = i3;
12575 if (i2
12576 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12577 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12578 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12579 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12581 if (place)
12582 place2 = i2;
12583 else
12584 place = i2;
12587 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12588 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12589 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12591 if (JUMP_LABEL (place) != XEXP (note, 0))
12592 abort ();
12593 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12594 LABEL_NUSES (JUMP_LABEL (place))--;
12595 place = 0;
12597 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12599 if (JUMP_LABEL (place2) != XEXP (note, 0))
12600 abort ();
12601 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12602 LABEL_NUSES (JUMP_LABEL (place2))--;
12603 place2 = 0;
12605 break;
12607 case REG_NONNEG:
12608 case REG_WAS_0:
12609 /* These notes say something about the value of a register prior
12610 to the execution of an insn. It is too much trouble to see
12611 if the note is still correct in all situations. It is better
12612 to simply delete it. */
12613 break;
12615 case REG_RETVAL:
12616 /* If the insn previously containing this note still exists,
12617 put it back where it was. Otherwise move it to the previous
12618 insn. Adjust the corresponding REG_LIBCALL note. */
12619 if (GET_CODE (from_insn) != NOTE)
12620 place = from_insn;
12621 else
12623 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12624 place = prev_real_insn (from_insn);
12625 if (tem && place)
12626 XEXP (tem, 0) = place;
12627 /* If we're deleting the last remaining instruction of a
12628 libcall sequence, don't add the notes. */
12629 else if (XEXP (note, 0) == from_insn)
12630 tem = place = 0;
12632 break;
12634 case REG_LIBCALL:
12635 /* This is handled similarly to REG_RETVAL. */
12636 if (GET_CODE (from_insn) != NOTE)
12637 place = from_insn;
12638 else
12640 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12641 place = next_real_insn (from_insn);
12642 if (tem && place)
12643 XEXP (tem, 0) = place;
12644 /* If we're deleting the last remaining instruction of a
12645 libcall sequence, don't add the notes. */
12646 else if (XEXP (note, 0) == from_insn)
12647 tem = place = 0;
12649 break;
12651 case REG_DEAD:
12652 /* If the register is used as an input in I3, it dies there.
12653 Similarly for I2, if it is nonzero and adjacent to I3.
12655 If the register is not used as an input in either I3 or I2
12656 and it is not one of the registers we were supposed to eliminate,
12657 there are two possibilities. We might have a non-adjacent I2
12658 or we might have somehow eliminated an additional register
12659 from a computation. For example, we might have had A & B where
12660 we discover that B will always be zero. In this case we will
12661 eliminate the reference to A.
12663 In both cases, we must search to see if we can find a previous
12664 use of A and put the death note there. */
12666 if (from_insn
12667 && GET_CODE (from_insn) == CALL_INSN
12668 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12669 place = from_insn;
12670 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12671 place = i3;
12672 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12673 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12674 place = i2;
12676 if (place == 0)
12678 basic_block bb = this_basic_block;
12680 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12682 if (! INSN_P (tem))
12684 if (tem == bb->head)
12685 break;
12686 continue;
12689 /* If the register is being set at TEM, see if that is all
12690 TEM is doing. If so, delete TEM. Otherwise, make this
12691 into a REG_UNUSED note instead. */
12692 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12694 rtx set = single_set (tem);
12695 rtx inner_dest = 0;
12696 #ifdef HAVE_cc0
12697 rtx cc0_setter = NULL_RTX;
12698 #endif
12700 if (set != 0)
12701 for (inner_dest = SET_DEST (set);
12702 (GET_CODE (inner_dest) == STRICT_LOW_PART
12703 || GET_CODE (inner_dest) == SUBREG
12704 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12705 inner_dest = XEXP (inner_dest, 0))
12708 /* Verify that it was the set, and not a clobber that
12709 modified the register.
12711 CC0 targets must be careful to maintain setter/user
12712 pairs. If we cannot delete the setter due to side
12713 effects, mark the user with an UNUSED note instead
12714 of deleting it. */
12716 if (set != 0 && ! side_effects_p (SET_SRC (set))
12717 && rtx_equal_p (XEXP (note, 0), inner_dest)
12718 #ifdef HAVE_cc0
12719 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12720 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12721 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12722 #endif
12725 /* Move the notes and links of TEM elsewhere.
12726 This might delete other dead insns recursively.
12727 First set the pattern to something that won't use
12728 any register. */
12730 PATTERN (tem) = pc_rtx;
12732 distribute_notes (REG_NOTES (tem), tem, tem,
12733 NULL_RTX);
12734 distribute_links (LOG_LINKS (tem));
12736 PUT_CODE (tem, NOTE);
12737 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12738 NOTE_SOURCE_FILE (tem) = 0;
12740 #ifdef HAVE_cc0
12741 /* Delete the setter too. */
12742 if (cc0_setter)
12744 PATTERN (cc0_setter) = pc_rtx;
12746 distribute_notes (REG_NOTES (cc0_setter),
12747 cc0_setter, cc0_setter,
12748 NULL_RTX);
12749 distribute_links (LOG_LINKS (cc0_setter));
12751 PUT_CODE (cc0_setter, NOTE);
12752 NOTE_LINE_NUMBER (cc0_setter)
12753 = NOTE_INSN_DELETED;
12754 NOTE_SOURCE_FILE (cc0_setter) = 0;
12756 #endif
12758 /* If the register is both set and used here, put the
12759 REG_DEAD note here, but place a REG_UNUSED note
12760 here too unless there already is one. */
12761 else if (reg_referenced_p (XEXP (note, 0),
12762 PATTERN (tem)))
12764 place = tem;
12766 if (! find_regno_note (tem, REG_UNUSED,
12767 REGNO (XEXP (note, 0))))
12768 REG_NOTES (tem)
12769 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12770 REG_NOTES (tem));
12772 else
12774 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12776 /* If there isn't already a REG_UNUSED note, put one
12777 here. */
12778 if (! find_regno_note (tem, REG_UNUSED,
12779 REGNO (XEXP (note, 0))))
12780 place = tem;
12781 break;
12784 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12785 || (GET_CODE (tem) == CALL_INSN
12786 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12788 place = tem;
12790 /* If we are doing a 3->2 combination, and we have a
12791 register which formerly died in i3 and was not used
12792 by i2, which now no longer dies in i3 and is used in
12793 i2 but does not die in i2, and place is between i2
12794 and i3, then we may need to move a link from place to
12795 i2. */
12796 if (i2 && INSN_UID (place) <= max_uid_cuid
12797 && INSN_CUID (place) > INSN_CUID (i2)
12798 && from_insn
12799 && INSN_CUID (from_insn) > INSN_CUID (i2)
12800 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12802 rtx links = LOG_LINKS (place);
12803 LOG_LINKS (place) = 0;
12804 distribute_links (links);
12806 break;
12809 if (tem == bb->head)
12810 break;
12813 /* We haven't found an insn for the death note and it
12814 is still a REG_DEAD note, but we have hit the beginning
12815 of the block. If the existing life info says the reg
12816 was dead, there's nothing left to do. Otherwise, we'll
12817 need to do a global life update after combine. */
12818 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12819 && REGNO_REG_SET_P (bb->global_live_at_start,
12820 REGNO (XEXP (note, 0))))
12821 SET_BIT (refresh_blocks, this_basic_block->index);
12824 /* If the register is set or already dead at PLACE, we needn't do
12825 anything with this note if it is still a REG_DEAD note.
12826 We can here if it is set at all, not if is it totally replace,
12827 which is what `dead_or_set_p' checks, so also check for it being
12828 set partially. */
12830 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12832 unsigned int regno = REGNO (XEXP (note, 0));
12834 /* Similarly, if the instruction on which we want to place
12835 the note is a noop, we'll need do a global live update
12836 after we remove them in delete_noop_moves. */
12837 if (noop_move_p (place))
12838 SET_BIT (refresh_blocks, this_basic_block->index);
12840 if (dead_or_set_p (place, XEXP (note, 0))
12841 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12843 /* Unless the register previously died in PLACE, clear
12844 reg_last_death. [I no longer understand why this is
12845 being done.] */
12846 if (reg_last_death[regno] != place)
12847 reg_last_death[regno] = 0;
12848 place = 0;
12850 else
12851 reg_last_death[regno] = place;
12853 /* If this is a death note for a hard reg that is occupying
12854 multiple registers, ensure that we are still using all
12855 parts of the object. If we find a piece of the object
12856 that is unused, we must arrange for an appropriate REG_DEAD
12857 note to be added for it. However, we can't just emit a USE
12858 and tag the note to it, since the register might actually
12859 be dead; so we recourse, and the recursive call then finds
12860 the previous insn that used this register. */
12862 if (place && regno < FIRST_PSEUDO_REGISTER
12863 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12865 unsigned int endregno
12866 = regno + HARD_REGNO_NREGS (regno,
12867 GET_MODE (XEXP (note, 0)));
12868 int all_used = 1;
12869 unsigned int i;
12871 for (i = regno; i < endregno; i++)
12872 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12873 && ! find_regno_fusage (place, USE, i))
12874 || dead_or_set_regno_p (place, i))
12875 all_used = 0;
12877 if (! all_used)
12879 /* Put only REG_DEAD notes for pieces that are
12880 not already dead or set. */
12882 for (i = regno; i < endregno;
12883 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12885 rtx piece = regno_reg_rtx[i];
12886 basic_block bb = this_basic_block;
12888 if (! dead_or_set_p (place, piece)
12889 && ! reg_bitfield_target_p (piece,
12890 PATTERN (place)))
12892 rtx new_note
12893 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12895 distribute_notes (new_note, place, place,
12896 NULL_RTX);
12898 else if (! refers_to_regno_p (i, i + 1,
12899 PATTERN (place), 0)
12900 && ! find_regno_fusage (place, USE, i))
12901 for (tem = PREV_INSN (place); ;
12902 tem = PREV_INSN (tem))
12904 if (! INSN_P (tem))
12906 if (tem == bb->head)
12908 SET_BIT (refresh_blocks,
12909 this_basic_block->index);
12910 break;
12912 continue;
12914 if (dead_or_set_p (tem, piece)
12915 || reg_bitfield_target_p (piece,
12916 PATTERN (tem)))
12918 REG_NOTES (tem)
12919 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12920 REG_NOTES (tem));
12921 break;
12927 place = 0;
12931 break;
12933 default:
12934 /* Any other notes should not be present at this point in the
12935 compilation. */
12936 abort ();
12939 if (place)
12941 XEXP (note, 1) = REG_NOTES (place);
12942 REG_NOTES (place) = note;
12944 else if ((REG_NOTE_KIND (note) == REG_DEAD
12945 || REG_NOTE_KIND (note) == REG_UNUSED)
12946 && GET_CODE (XEXP (note, 0)) == REG)
12947 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12949 if (place2)
12951 if ((REG_NOTE_KIND (note) == REG_DEAD
12952 || REG_NOTE_KIND (note) == REG_UNUSED)
12953 && GET_CODE (XEXP (note, 0)) == REG)
12954 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12956 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12957 REG_NOTE_KIND (note),
12958 XEXP (note, 0),
12959 REG_NOTES (place2));
12964 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12965 I3, I2, and I1 to new locations. This is also called in one case to
12966 add a link pointing at I3 when I3's destination is changed. */
12968 static void
12969 distribute_links (rtx links)
12971 rtx link, next_link;
12973 for (link = links; link; link = next_link)
12975 rtx place = 0;
12976 rtx insn;
12977 rtx set, reg;
12979 next_link = XEXP (link, 1);
12981 /* If the insn that this link points to is a NOTE or isn't a single
12982 set, ignore it. In the latter case, it isn't clear what we
12983 can do other than ignore the link, since we can't tell which
12984 register it was for. Such links wouldn't be used by combine
12985 anyway.
12987 It is not possible for the destination of the target of the link to
12988 have been changed by combine. The only potential of this is if we
12989 replace I3, I2, and I1 by I3 and I2. But in that case the
12990 destination of I2 also remains unchanged. */
12992 if (GET_CODE (XEXP (link, 0)) == NOTE
12993 || (set = single_set (XEXP (link, 0))) == 0)
12994 continue;
12996 reg = SET_DEST (set);
12997 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12998 || GET_CODE (reg) == SIGN_EXTRACT
12999 || GET_CODE (reg) == STRICT_LOW_PART)
13000 reg = XEXP (reg, 0);
13002 /* A LOG_LINK is defined as being placed on the first insn that uses
13003 a register and points to the insn that sets the register. Start
13004 searching at the next insn after the target of the link and stop
13005 when we reach a set of the register or the end of the basic block.
13007 Note that this correctly handles the link that used to point from
13008 I3 to I2. Also note that not much searching is typically done here
13009 since most links don't point very far away. */
13011 for (insn = NEXT_INSN (XEXP (link, 0));
13012 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13013 || this_basic_block->next_bb->head != insn));
13014 insn = NEXT_INSN (insn))
13015 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13017 if (reg_referenced_p (reg, PATTERN (insn)))
13018 place = insn;
13019 break;
13021 else if (GET_CODE (insn) == CALL_INSN
13022 && find_reg_fusage (insn, USE, reg))
13024 place = insn;
13025 break;
13028 /* If we found a place to put the link, place it there unless there
13029 is already a link to the same insn as LINK at that point. */
13031 if (place)
13033 rtx link2;
13035 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13036 if (XEXP (link2, 0) == XEXP (link, 0))
13037 break;
13039 if (link2 == 0)
13041 XEXP (link, 1) = LOG_LINKS (place);
13042 LOG_LINKS (place) = link;
13044 /* Set added_links_insn to the earliest insn we added a
13045 link to. */
13046 if (added_links_insn == 0
13047 || INSN_CUID (added_links_insn) > INSN_CUID (place))
13048 added_links_insn = place;
13054 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13056 static int
13057 insn_cuid (rtx insn)
13059 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13060 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13061 insn = NEXT_INSN (insn);
13063 if (INSN_UID (insn) > max_uid_cuid)
13064 abort ();
13066 return INSN_CUID (insn);
13069 void
13070 dump_combine_stats (FILE *file)
13072 fnotice
13073 (file,
13074 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13075 combine_attempts, combine_merges, combine_extras, combine_successes);
13078 void
13079 dump_combine_total_stats (FILE *file)
13081 fnotice
13082 (file,
13083 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13084 total_attempts, total_merges, total_extras, total_successes);