1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
27 #include "rtl-error.h"
30 #include "insn-config.h"
37 #include "addresses.h"
38 #include "basic-block.h"
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 struct target_reload default_target_reload
;
85 struct target_reload
*this_target_reload
= &default_target_reload
;
88 #define spill_indirect_levels \
89 (this_target_reload->x_spill_indirect_levels)
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx
*reg_last_reload_reg
;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static regset_head reg_has_output_reload
;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload
;
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static unsigned int *reg_max_ref_width
;
106 /* Vector to remember old contents of reg_renumber before spilling. */
107 static short *reg_old_renumber
;
109 /* During reload_as_needed, element N contains the last pseudo regno reloaded
110 into hard register N. If that pseudo reg occupied more than one register,
111 reg_reloaded_contents points to that pseudo for each spill register in
112 use; all of these must remain set for an inheritance to occur. */
113 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
115 /* During reload_as_needed, element N contains the insn for which
116 hard register N was last used. Its contents are significant only
117 when reg_reloaded_valid is set for this register. */
118 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
120 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
121 static HARD_REG_SET reg_reloaded_valid
;
122 /* Indicate if the register was dead at the end of the reload.
123 This is only valid if reg_reloaded_contents is set and valid. */
124 static HARD_REG_SET reg_reloaded_dead
;
126 /* Indicate whether the register's current value is one that is not
127 safe to retain across a call, even for registers that are normally
128 call-saved. This is only meaningful for members of reg_reloaded_valid. */
129 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
131 /* Number of spill-regs so far; number of valid elements of spill_regs. */
134 /* In parallel with spill_regs, contains REG rtx's for those regs.
135 Holds the last rtx used for any given reg, or 0 if it has never
136 been used for spilling yet. This rtx is reused, provided it has
138 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
140 /* In parallel with spill_regs, contains nonzero for a spill reg
141 that was stored after the last time it was used.
142 The precise value is the insn generated to do the store. */
143 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
145 /* This is the register that was stored with spill_reg_store. This is a
146 copy of reload_out / reload_out_reg when the value was stored; if
147 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
148 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
150 /* This table is the inverse mapping of spill_regs:
151 indexed by hard reg number,
152 it contains the position of that reg in spill_regs,
153 or -1 for something that is not in spill_regs.
155 ?!? This is no longer accurate. */
156 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
158 /* This reg set indicates registers that can't be used as spill registers for
159 the currently processed insn. These are the hard registers which are live
160 during the insn, but not allocated to pseudos, as well as fixed
162 static HARD_REG_SET bad_spill_regs
;
164 /* These are the hard registers that can't be used as spill register for any
165 insn. This includes registers used for user variables and registers that
166 we can't eliminate. A register that appears in this set also can't be used
167 to retry register allocation. */
168 static HARD_REG_SET bad_spill_regs_global
;
170 /* Describes order of use of registers for reloading
171 of spilled pseudo-registers. `n_spills' is the number of
172 elements that are actually valid; new ones are added at the end.
174 Both spill_regs and spill_reg_order are used on two occasions:
175 once during find_reload_regs, where they keep track of the spill registers
176 for a single insn, but also during reload_as_needed where they show all
177 the registers ever used by reload. For the latter case, the information
178 is calculated during finish_spills. */
179 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
181 /* This vector of reg sets indicates, for each pseudo, which hard registers
182 may not be used for retrying global allocation because the register was
183 formerly spilled from one of them. If we allowed reallocating a pseudo to
184 a register that it was already allocated to, reload might not
186 static HARD_REG_SET
*pseudo_previous_regs
;
188 /* This vector of reg sets indicates, for each pseudo, which hard
189 registers may not be used for retrying global allocation because they
190 are used as spill registers during one of the insns in which the
192 static HARD_REG_SET
*pseudo_forbidden_regs
;
194 /* All hard regs that have been used as spill registers for any insn are
195 marked in this set. */
196 static HARD_REG_SET used_spill_regs
;
198 /* Index of last register assigned as a spill register. We allocate in
199 a round-robin fashion. */
200 static int last_spill_reg
;
202 /* Record the stack slot for each spilled hard register. */
203 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
205 /* Width allocated so far for that stack slot. */
206 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
208 /* Record which pseudos needed to be spilled. */
209 static regset_head spilled_pseudos
;
211 /* Record which pseudos changed their allocation in finish_spills. */
212 static regset_head changed_allocation_pseudos
;
214 /* Used for communication between order_regs_for_reload and count_pseudo.
215 Used to avoid counting one pseudo twice. */
216 static regset_head pseudos_counted
;
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid
;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
224 int caller_save_needed
;
226 /* Set to 1 while reload_as_needed is operating.
227 Required by some machines to handle any generated moves differently. */
228 int reload_in_progress
= 0;
230 /* This obstack is used for allocation of rtl during register elimination.
231 The allocated storage can be freed once find_reloads has processed the
233 static struct obstack reload_obstack
;
235 /* Points to the beginning of the reload_obstack. All insn_chain structures
236 are allocated first. */
237 static char *reload_startobj
;
239 /* The point after all insn_chain structures. Used to quickly deallocate
240 memory allocated in copy_reloads during calculate_needs_all_insns. */
241 static char *reload_firstobj
;
243 /* This points before all local rtl generated by register elimination.
244 Used to quickly free all memory after processing one insn. */
245 static char *reload_insn_firstobj
;
247 /* List of insn_chain instructions, one for every insn that reload needs to
249 struct insn_chain
*reload_insn_chain
;
251 /* TRUE if we potentially left dead insns in the insn stream and want to
252 run DCE immediately after reload, FALSE otherwise. */
253 static bool need_dce
;
255 /* List of all insns needing reloads. */
256 static struct insn_chain
*insns_need_reload
;
258 /* This structure is used to record information about register eliminations.
259 Each array entry describes one possible way of eliminating a register
260 in favor of another. If there is more than one way of eliminating a
261 particular register, the most preferred should be specified first. */
265 int from
; /* Register number to be eliminated. */
266 int to
; /* Register number used as replacement. */
267 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
268 int can_eliminate
; /* Nonzero if this elimination can be done. */
269 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
270 target hook in previous scan over insns
272 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
273 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
274 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
275 rtx from_rtx
; /* REG rtx for the register to be eliminated.
276 We cannot simply compare the number since
277 we might then spuriously replace a hard
278 register corresponding to a pseudo
279 assigned to the reg to be eliminated. */
280 rtx to_rtx
; /* REG rtx for the replacement. */
283 static struct elim_table
*reg_eliminate
= 0;
285 /* This is an intermediate structure to initialize the table. It has
286 exactly the members provided by ELIMINABLE_REGS. */
287 static const struct elim_table_1
291 } reg_eliminate_1
[] =
293 /* If a set of eliminable registers was specified, define the table from it.
294 Otherwise, default to the normal case of the frame pointer being
295 replaced by the stack pointer. */
297 #ifdef ELIMINABLE_REGS
300 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
303 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
305 /* Record the number of pending eliminations that have an offset not equal
306 to their initial offset. If nonzero, we use a new copy of each
307 replacement result in any insns encountered. */
308 int num_not_at_initial_offset
;
310 /* Count the number of registers that we may be able to eliminate. */
311 static int num_eliminable
;
312 /* And the number of registers that are equivalent to a constant that
313 can be eliminated to frame_pointer / arg_pointer + constant. */
314 static int num_eliminable_invariants
;
316 /* For each label, we record the offset of each elimination. If we reach
317 a label by more than one path and an offset differs, we cannot do the
318 elimination. This information is indexed by the difference of the
319 number of the label and the first label number. We can't offset the
320 pointer itself as this can cause problems on machines with segmented
321 memory. The first table is an array of flags that records whether we
322 have yet encountered a label and the second table is an array of arrays,
323 one entry in the latter array for each elimination. */
325 static int first_label_num
;
326 static char *offsets_known_at
;
327 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
329 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
331 /* Stack of addresses where an rtx has been changed. We can undo the
332 changes by popping items off the stack and restoring the original
333 value at each location.
335 We use this simplistic undo capability rather than copy_rtx as copy_rtx
336 will not make a deep copy of a normally sharable rtx, such as
337 (const (plus (symbol_ref) (const_int))). If such an expression appears
338 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
339 rtx expression would be changed. See PR 42431. */
342 static vec
<rtx_p
> substitute_stack
;
344 /* Number of labels in the current function. */
346 static int num_labels
;
348 static void replace_pseudos_in (rtx
*, enum machine_mode
, rtx
);
349 static void maybe_fix_stack_asms (void);
350 static void copy_reloads (struct insn_chain
*);
351 static void calculate_needs_all_insns (int);
352 static int find_reg (struct insn_chain
*, int);
353 static void find_reload_regs (struct insn_chain
*);
354 static void select_reload_regs (void);
355 static void delete_caller_save_insns (void);
357 static void spill_failure (rtx
, enum reg_class
);
358 static void count_spilled_pseudo (int, int, int);
359 static void delete_dead_insn (rtx
);
360 static void alter_reg (int, int, bool);
361 static void set_label_offsets (rtx
, rtx
, int);
362 static void check_eliminable_occurrences (rtx
);
363 static void elimination_effects (rtx
, enum machine_mode
);
364 static rtx
eliminate_regs_1 (rtx
, enum machine_mode
, rtx
, bool, bool);
365 static int eliminate_regs_in_insn (rtx
, int);
366 static void update_eliminable_offsets (void);
367 static void mark_not_eliminable (rtx
, const_rtx
, void *);
368 static void set_initial_elim_offsets (void);
369 static bool verify_initial_elim_offsets (void);
370 static void set_initial_label_offsets (void);
371 static void set_offsets_for_label (rtx
);
372 static void init_eliminable_invariants (rtx
, bool);
373 static void init_elim_table (void);
374 static void free_reg_equiv (void);
375 static void update_eliminables (HARD_REG_SET
*);
376 static void elimination_costs_in_insn (rtx
);
377 static void spill_hard_reg (unsigned int, int);
378 static int finish_spills (int);
379 static void scan_paradoxical_subregs (rtx
);
380 static void count_pseudo (int);
381 static void order_regs_for_reload (struct insn_chain
*);
382 static void reload_as_needed (int);
383 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
384 static void forget_marked_reloads (regset
);
385 static int reload_reg_class_lower (const void *, const void *);
386 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
388 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
390 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
391 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
393 static int free_for_value_p (int, enum machine_mode
, int, enum reload_type
,
395 static int allocate_reload_reg (struct insn_chain
*, int, int);
396 static int conflicts_with_override (rtx
);
397 static void failed_reload (rtx
, int);
398 static int set_reload_reg (int, int);
399 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
400 static void choose_reload_regs (struct insn_chain
*);
401 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
403 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
405 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
406 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
407 static void emit_reload_insns (struct insn_chain
*);
408 static void delete_output_reload (rtx
, int, int, rtx
);
409 static void delete_address_reloads (rtx
, rtx
);
410 static void delete_address_reloads_1 (rtx
, rtx
, rtx
);
411 static void inc_for_reload (rtx
, rtx
, rtx
, int);
413 static void add_auto_inc_notes (rtx
, rtx
);
415 static void substitute (rtx
*, const_rtx
, rtx
);
416 static bool gen_reload_chain_without_interm_reg_p (int, int);
417 static int reloads_conflict (int, int);
418 static rtx
gen_reload (rtx
, rtx
, int, enum reload_type
);
419 static rtx
emit_insn_if_valid_for_reload (rtx
);
421 /* Initialize the reload pass. This is called at the beginning of compilation
422 and may be called again if the target is reinitialized. */
429 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
430 Set spill_indirect_levels to the number of levels such addressing is
431 permitted, zero if it is not permitted at all. */
434 = gen_rtx_MEM (Pmode
,
437 LAST_VIRTUAL_REGISTER
+ 1),
438 gen_int_mode (4, Pmode
)));
439 spill_indirect_levels
= 0;
441 while (memory_address_p (QImode
, tem
))
443 spill_indirect_levels
++;
444 tem
= gen_rtx_MEM (Pmode
, tem
);
447 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
449 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
450 indirect_symref_ok
= memory_address_p (QImode
, tem
);
452 /* See if reg+reg is a valid (and offsettable) address. */
454 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
456 tem
= gen_rtx_PLUS (Pmode
,
457 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
458 gen_rtx_REG (Pmode
, i
));
460 /* This way, we make sure that reg+reg is an offsettable address. */
461 tem
= plus_constant (Pmode
, tem
, 4);
463 if (memory_address_p (QImode
, tem
))
465 double_reg_address_ok
= 1;
470 /* Initialize obstack for our rtl allocation. */
471 if (reload_startobj
== NULL
)
473 gcc_obstack_init (&reload_obstack
);
474 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
477 INIT_REG_SET (&spilled_pseudos
);
478 INIT_REG_SET (&changed_allocation_pseudos
);
479 INIT_REG_SET (&pseudos_counted
);
482 /* List of insn chains that are currently unused. */
483 static struct insn_chain
*unused_insn_chains
= 0;
485 /* Allocate an empty insn_chain structure. */
487 new_insn_chain (void)
489 struct insn_chain
*c
;
491 if (unused_insn_chains
== 0)
493 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
494 INIT_REG_SET (&c
->live_throughout
);
495 INIT_REG_SET (&c
->dead_or_set
);
499 c
= unused_insn_chains
;
500 unused_insn_chains
= c
->next
;
502 c
->is_caller_save_insn
= 0;
503 c
->need_operand_change
= 0;
509 /* Small utility function to set all regs in hard reg set TO which are
510 allocated to pseudos in regset FROM. */
513 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
516 reg_set_iterator rsi
;
518 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
520 int r
= reg_renumber
[regno
];
524 /* reload_combine uses the information from DF_LIVE_IN,
525 which might still contain registers that have not
526 actually been allocated since they have an
528 gcc_assert (ira_conflicts_p
|| reload_completed
);
531 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
535 /* Replace all pseudos found in LOC with their corresponding
539 replace_pseudos_in (rtx
*loc
, enum machine_mode mem_mode
, rtx usage
)
552 unsigned int regno
= REGNO (x
);
554 if (regno
< FIRST_PSEUDO_REGISTER
)
557 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
561 replace_pseudos_in (loc
, mem_mode
, usage
);
565 if (reg_equiv_constant (regno
))
566 *loc
= reg_equiv_constant (regno
);
567 else if (reg_equiv_invariant (regno
))
568 *loc
= reg_equiv_invariant (regno
);
569 else if (reg_equiv_mem (regno
))
570 *loc
= reg_equiv_mem (regno
);
571 else if (reg_equiv_address (regno
))
572 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
575 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
576 || REGNO (regno_reg_rtx
[regno
]) != regno
);
577 *loc
= regno_reg_rtx
[regno
];
582 else if (code
== MEM
)
584 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
588 /* Process each of our operands recursively. */
589 fmt
= GET_RTX_FORMAT (code
);
590 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
592 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
593 else if (*fmt
== 'E')
594 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
595 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
598 /* Determine if the current function has an exception receiver block
599 that reaches the exit block via non-exceptional edges */
602 has_nonexceptional_receiver (void)
606 basic_block
*tos
, *worklist
, bb
;
608 /* If we're not optimizing, then just err on the safe side. */
612 /* First determine which blocks can reach exit via normal paths. */
613 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
616 bb
->flags
&= ~BB_REACHABLE
;
618 /* Place the exit block on our worklist. */
619 EXIT_BLOCK_PTR
->flags
|= BB_REACHABLE
;
620 *tos
++ = EXIT_BLOCK_PTR
;
622 /* Iterate: find everything reachable from what we've already seen. */
623 while (tos
!= worklist
)
627 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
628 if (!(e
->flags
& EDGE_ABNORMAL
))
630 basic_block src
= e
->src
;
632 if (!(src
->flags
& BB_REACHABLE
))
634 src
->flags
|= BB_REACHABLE
;
641 /* Now see if there's a reachable block with an exceptional incoming
644 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
647 /* No exceptional block reached exit unexceptionally. */
651 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
652 zero elements) to MAX_REG_NUM elements.
654 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
656 grow_reg_equivs (void)
658 int old_size
= vec_safe_length (reg_equivs
);
659 int max_regno
= max_reg_num ();
663 memset (&ze
, 0, sizeof (reg_equivs_t
));
664 vec_safe_reserve (reg_equivs
, max_regno
);
665 for (i
= old_size
; i
< max_regno
; i
++)
666 reg_equivs
->quick_insert (i
, ze
);
670 /* Global variables used by reload and its subroutines. */
672 /* The current basic block while in calculate_elim_costs_all_insns. */
673 static basic_block elim_bb
;
675 /* Set during calculate_needs if an insn needs register elimination. */
676 static int something_needs_elimination
;
677 /* Set during calculate_needs if an insn needs an operand changed. */
678 static int something_needs_operands_changed
;
679 /* Set by alter_regs if we spilled a register to the stack. */
680 static bool something_was_spilled
;
682 /* Nonzero means we couldn't get enough spill regs. */
685 /* Temporary array of pseudo-register number. */
686 static int *temp_pseudo_reg_arr
;
688 /* Main entry point for the reload pass.
690 FIRST is the first insn of the function being compiled.
692 GLOBAL nonzero means we were called from global_alloc
693 and should attempt to reallocate any pseudoregs that we
694 displace from hard regs we will use for reloads.
695 If GLOBAL is zero, we do not have enough information to do that,
696 so any pseudo reg that is spilled must go to the stack.
698 Return value is TRUE if reload likely left dead insns in the
699 stream and a DCE pass should be run to elimiante them. Else the
700 return value is FALSE. */
703 reload (rtx first
, int global
)
707 struct elim_table
*ep
;
711 /* Make sure even insns with volatile mem refs are recognizable. */
716 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
718 /* Make sure that the last insn in the chain
719 is not something that needs reloading. */
720 emit_note (NOTE_INSN_DELETED
);
722 /* Enable find_equiv_reg to distinguish insns made by reload. */
723 reload_first_uid
= get_max_uid ();
725 #ifdef SECONDARY_MEMORY_NEEDED
726 /* Initialize the secondary memory table. */
727 clear_secondary_mem ();
730 /* We don't have a stack slot for any spill reg yet. */
731 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
732 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
734 /* Initialize the save area information for caller-save, in case some
738 /* Compute which hard registers are now in use
739 as homes for pseudo registers.
740 This is done here rather than (eg) in global_alloc
741 because this point is reached even if not optimizing. */
742 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
745 /* A function that has a nonlocal label that can reach the exit
746 block via non-exceptional paths must save all call-saved
748 if (cfun
->has_nonlocal_label
749 && has_nonexceptional_receiver ())
750 crtl
->saves_all_registers
= 1;
752 if (crtl
->saves_all_registers
)
753 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
754 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
755 df_set_regs_ever_live (i
, true);
757 /* Find all the pseudo registers that didn't get hard regs
758 but do have known equivalent constants or memory slots.
759 These include parameters (known equivalent to parameter slots)
760 and cse'd or loop-moved constant memory addresses.
762 Record constant equivalents in reg_equiv_constant
763 so they will be substituted by find_reloads.
764 Record memory equivalents in reg_mem_equiv so they can
765 be substituted eventually by altering the REG-rtx's. */
768 reg_old_renumber
= XCNEWVEC (short, max_regno
);
769 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
770 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
771 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
773 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
775 init_eliminable_invariants (first
, true);
778 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
779 stack slots to the pseudos that lack hard regs or equivalents.
780 Do not touch virtual registers. */
782 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
783 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
784 temp_pseudo_reg_arr
[n
++] = i
;
787 /* Ask IRA to order pseudo-registers for better stack slot
789 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
791 for (i
= 0; i
< n
; i
++)
792 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
794 /* If we have some registers we think can be eliminated, scan all insns to
795 see if there is an insn that sets one of these registers to something
796 other than itself plus a constant. If so, the register cannot be
797 eliminated. Doing this scan here eliminates an extra pass through the
798 main reload loop in the most common case where register elimination
800 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
802 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
804 maybe_fix_stack_asms ();
806 insns_need_reload
= 0;
807 something_needs_elimination
= 0;
809 /* Initialize to -1, which means take the first spill register. */
812 /* Spill any hard regs that we know we can't eliminate. */
813 CLEAR_HARD_REG_SET (used_spill_regs
);
814 /* There can be multiple ways to eliminate a register;
815 they should be listed adjacently.
816 Elimination for any register fails only if all possible ways fail. */
817 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
820 int can_eliminate
= 0;
823 can_eliminate
|= ep
->can_eliminate
;
826 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
828 spill_hard_reg (from
, 1);
831 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
832 if (frame_pointer_needed
)
833 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
835 finish_spills (global
);
837 /* From now on, we may need to generate moves differently. We may also
838 allow modifications of insns which cause them to not be recognized.
839 Any such modifications will be cleaned up during reload itself. */
840 reload_in_progress
= 1;
842 /* This loop scans the entire function each go-round
843 and repeats until one repetition spills no additional hard regs. */
846 int something_changed
;
848 HOST_WIDE_INT starting_frame_size
;
850 starting_frame_size
= get_frame_size ();
851 something_was_spilled
= false;
853 set_initial_elim_offsets ();
854 set_initial_label_offsets ();
856 /* For each pseudo register that has an equivalent location defined,
857 try to eliminate any eliminable registers (such as the frame pointer)
858 assuming initial offsets for the replacement register, which
861 If the resulting location is directly addressable, substitute
862 the MEM we just got directly for the old REG.
864 If it is not addressable but is a constant or the sum of a hard reg
865 and constant, it is probably not addressable because the constant is
866 out of range, in that case record the address; we will generate
867 hairy code to compute the address in a register each time it is
868 needed. Similarly if it is a hard register, but one that is not
869 valid as an address register.
871 If the location is not addressable, but does not have one of the
872 above forms, assign a stack slot. We have to do this to avoid the
873 potential of producing lots of reloads if, e.g., a location involves
874 a pseudo that didn't get a hard register and has an equivalent memory
875 location that also involves a pseudo that didn't get a hard register.
877 Perhaps at some point we will improve reload_when_needed handling
878 so this problem goes away. But that's very hairy. */
880 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
881 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
883 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
886 if (strict_memory_address_addr_space_p
887 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
889 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
890 else if (CONSTANT_P (XEXP (x
, 0))
891 || (REG_P (XEXP (x
, 0))
892 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
893 || (GET_CODE (XEXP (x
, 0)) == PLUS
894 && REG_P (XEXP (XEXP (x
, 0), 0))
895 && (REGNO (XEXP (XEXP (x
, 0), 0))
896 < FIRST_PSEUDO_REGISTER
)
897 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
898 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
901 /* Make a new stack slot. Then indicate that something
902 changed so we go back and recompute offsets for
903 eliminable registers because the allocation of memory
904 below might change some offset. reg_equiv_{mem,address}
905 will be set up for this pseudo on the next pass around
907 reg_equiv_memory_loc (i
) = 0;
908 reg_equiv_init (i
) = 0;
909 alter_reg (i
, -1, true);
913 if (caller_save_needed
)
916 /* If we allocated another stack slot, redo elimination bookkeeping. */
917 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
919 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
921 /* If we have a stack frame, we must align it now. The
922 stack size may be a part of the offset computation for
923 register elimination. So if this changes the stack size,
924 then repeat the elimination bookkeeping. We don't
925 realign when there is no stack, as that will cause a
926 stack frame when none is needed should
927 STARTING_FRAME_OFFSET not be already aligned to
929 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
930 if (starting_frame_size
!= get_frame_size ())
934 if (caller_save_needed
)
936 save_call_clobbered_regs ();
937 /* That might have allocated new insn_chain structures. */
938 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
941 calculate_needs_all_insns (global
);
943 if (! ira_conflicts_p
)
944 /* Don't do it for IRA. We need this info because we don't
945 change live_throughout and dead_or_set for chains when IRA
947 CLEAR_REG_SET (&spilled_pseudos
);
951 something_changed
= 0;
953 /* If we allocated any new memory locations, make another pass
954 since it might have changed elimination offsets. */
955 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
956 something_changed
= 1;
958 /* Even if the frame size remained the same, we might still have
959 changed elimination offsets, e.g. if find_reloads called
960 force_const_mem requiring the back end to allocate a constant
961 pool base register that needs to be saved on the stack. */
962 else if (!verify_initial_elim_offsets ())
963 something_changed
= 1;
966 HARD_REG_SET to_spill
;
967 CLEAR_HARD_REG_SET (to_spill
);
968 update_eliminables (&to_spill
);
969 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
971 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
972 if (TEST_HARD_REG_BIT (to_spill
, i
))
974 spill_hard_reg (i
, 1);
977 /* Regardless of the state of spills, if we previously had
978 a register that we thought we could eliminate, but now can
979 not eliminate, we must run another pass.
981 Consider pseudos which have an entry in reg_equiv_* which
982 reference an eliminable register. We must make another pass
983 to update reg_equiv_* so that we do not substitute in the
984 old value from when we thought the elimination could be
986 something_changed
= 1;
990 select_reload_regs ();
994 if (insns_need_reload
!= 0 || did_spill
)
995 something_changed
|= finish_spills (global
);
997 if (! something_changed
)
1000 if (caller_save_needed
)
1001 delete_caller_save_insns ();
1003 obstack_free (&reload_obstack
, reload_firstobj
);
1006 /* If global-alloc was run, notify it of any register eliminations we have
1009 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1010 if (ep
->can_eliminate
)
1011 mark_elimination (ep
->from
, ep
->to
);
1013 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1014 If that insn didn't set the register (i.e., it copied the register to
1015 memory), just delete that insn instead of the equivalencing insn plus
1016 anything now dead. If we call delete_dead_insn on that insn, we may
1017 delete the insn that actually sets the register if the register dies
1018 there and that is incorrect. */
1020 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1022 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
1025 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
1027 rtx equiv_insn
= XEXP (list
, 0);
1029 /* If we already deleted the insn or if it may trap, we can't
1030 delete it. The latter case shouldn't happen, but can
1031 if an insn has a variable address, gets a REG_EH_REGION
1032 note added to it, and then gets converted into a load
1033 from a constant address. */
1034 if (NOTE_P (equiv_insn
)
1035 || can_throw_internal (equiv_insn
))
1037 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1038 delete_dead_insn (equiv_insn
);
1040 SET_INSN_DELETED (equiv_insn
);
1045 /* Use the reload registers where necessary
1046 by generating move instructions to move the must-be-register
1047 values into or out of the reload registers. */
1049 if (insns_need_reload
!= 0 || something_needs_elimination
1050 || something_needs_operands_changed
)
1052 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1054 reload_as_needed (global
);
1056 gcc_assert (old_frame_size
== get_frame_size ());
1058 gcc_assert (verify_initial_elim_offsets ());
1061 /* If we were able to eliminate the frame pointer, show that it is no
1062 longer live at the start of any basic block. If it ls live by
1063 virtue of being in a pseudo, that pseudo will be marked live
1064 and hence the frame pointer will be known to be live via that
1067 if (! frame_pointer_needed
)
1069 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1071 /* Come here (with failure set nonzero) if we can't get enough spill
1075 CLEAR_REG_SET (&changed_allocation_pseudos
);
1076 CLEAR_REG_SET (&spilled_pseudos
);
1077 reload_in_progress
= 0;
1079 /* Now eliminate all pseudo regs by modifying them into
1080 their equivalent memory references.
1081 The REG-rtx's for the pseudos are modified in place,
1082 so all insns that used to refer to them now refer to memory.
1084 For a reg that has a reg_equiv_address, all those insns
1085 were changed by reloading so that no insns refer to it any longer;
1086 but the DECL_RTL of a variable decl may refer to it,
1087 and if so this causes the debugging info to mention the variable. */
1089 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1093 if (reg_equiv_mem (i
))
1094 addr
= XEXP (reg_equiv_mem (i
), 0);
1096 if (reg_equiv_address (i
))
1097 addr
= reg_equiv_address (i
);
1101 if (reg_renumber
[i
] < 0)
1103 rtx reg
= regno_reg_rtx
[i
];
1105 REG_USERVAR_P (reg
) = 0;
1106 PUT_CODE (reg
, MEM
);
1107 XEXP (reg
, 0) = addr
;
1108 if (reg_equiv_memory_loc (i
))
1109 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1111 MEM_ATTRS (reg
) = 0;
1112 MEM_NOTRAP_P (reg
) = 1;
1114 else if (reg_equiv_mem (i
))
1115 XEXP (reg_equiv_mem (i
), 0) = addr
;
1118 /* We don't want complex addressing modes in debug insns
1119 if simpler ones will do, so delegitimize equivalences
1121 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1123 rtx reg
= regno_reg_rtx
[i
];
1127 if (reg_equiv_constant (i
))
1128 equiv
= reg_equiv_constant (i
);
1129 else if (reg_equiv_invariant (i
))
1130 equiv
= reg_equiv_invariant (i
);
1131 else if (reg
&& MEM_P (reg
))
1132 equiv
= targetm
.delegitimize_address (reg
);
1133 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1139 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1141 insn
= DF_REF_INSN (use
);
1143 /* Make sure the next ref is for a different instruction,
1144 so that we're not affected by the rescan. */
1145 next
= DF_REF_NEXT_REG (use
);
1146 while (next
&& DF_REF_INSN (next
) == insn
)
1147 next
= DF_REF_NEXT_REG (next
);
1149 if (DEBUG_INSN_P (insn
))
1153 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1154 df_insn_rescan_debug_internal (insn
);
1157 INSN_VAR_LOCATION_LOC (insn
)
1158 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1165 /* We must set reload_completed now since the cleanup_subreg_operands call
1166 below will re-recognize each insn and reload may have generated insns
1167 which are only valid during and after reload. */
1168 reload_completed
= 1;
1170 /* Make a pass over all the insns and delete all USEs which we inserted
1171 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1172 notes. Delete all CLOBBER insns, except those that refer to the return
1173 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1174 from misarranging variable-array code, and simplify (subreg (reg))
1175 operands. Strip and regenerate REG_INC notes that may have been moved
1178 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1184 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1185 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1187 if ((GET_CODE (PATTERN (insn
)) == USE
1188 /* We mark with QImode USEs introduced by reload itself. */
1189 && (GET_MODE (insn
) == QImode
1190 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1191 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1192 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1193 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1194 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1195 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1196 != stack_pointer_rtx
))
1197 && (!REG_P (XEXP (PATTERN (insn
), 0))
1198 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1204 /* Some CLOBBERs may survive until here and still reference unassigned
1205 pseudos with const equivalent, which may in turn cause ICE in later
1206 passes if the reference remains in place. */
1207 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1208 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1209 VOIDmode
, PATTERN (insn
));
1211 /* Discard obvious no-ops, even without -O. This optimization
1212 is fast and doesn't interfere with debugging. */
1213 if (NONJUMP_INSN_P (insn
)
1214 && GET_CODE (PATTERN (insn
)) == SET
1215 && REG_P (SET_SRC (PATTERN (insn
)))
1216 && REG_P (SET_DEST (PATTERN (insn
)))
1217 && (REGNO (SET_SRC (PATTERN (insn
)))
1218 == REGNO (SET_DEST (PATTERN (insn
)))))
1224 pnote
= ®_NOTES (insn
);
1227 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1228 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1229 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1230 *pnote
= XEXP (*pnote
, 1);
1232 pnote
= &XEXP (*pnote
, 1);
1236 add_auto_inc_notes (insn
, PATTERN (insn
));
1239 /* Simplify (subreg (reg)) if it appears as an operand. */
1240 cleanup_subreg_operands (insn
);
1242 /* Clean up invalid ASMs so that they don't confuse later passes.
1244 if (asm_noperands (PATTERN (insn
)) >= 0)
1246 extract_insn (insn
);
1247 if (!constrain_operands (1))
1249 error_for_asm (insn
,
1250 "%<asm%> operand has impossible constraints");
1257 /* If we are doing generic stack checking, give a warning if this
1258 function's frame size is larger than we expect. */
1259 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1261 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1262 static int verbose_warned
= 0;
1264 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1265 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1266 size
+= UNITS_PER_WORD
;
1268 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1270 warning (0, "frame size too large for reliable stack checking");
1271 if (! verbose_warned
)
1273 warning (0, "try reducing the number of local variables");
1279 free (temp_pseudo_reg_arr
);
1281 /* Indicate that we no longer have known memory locations or constants. */
1284 free (reg_max_ref_width
);
1285 free (reg_old_renumber
);
1286 free (pseudo_previous_regs
);
1287 free (pseudo_forbidden_regs
);
1289 CLEAR_HARD_REG_SET (used_spill_regs
);
1290 for (i
= 0; i
< n_spills
; i
++)
1291 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1293 /* Free all the insn_chain structures at once. */
1294 obstack_free (&reload_obstack
, reload_startobj
);
1295 unused_insn_chains
= 0;
1297 inserted
= fixup_abnormal_edges ();
1299 /* We've possibly turned single trapping insn into multiple ones. */
1300 if (cfun
->can_throw_non_call_exceptions
)
1303 blocks
= sbitmap_alloc (last_basic_block
);
1304 bitmap_ones (blocks
);
1305 find_many_sub_basic_blocks (blocks
);
1306 sbitmap_free (blocks
);
1310 commit_edge_insertions ();
1312 /* Replacing pseudos with their memory equivalents might have
1313 created shared rtx. Subsequent passes would get confused
1314 by this, so unshare everything here. */
1315 unshare_all_rtl_again (first
);
1317 #ifdef STACK_BOUNDARY
1318 /* init_emit has set the alignment of the hard frame pointer
1319 to STACK_BOUNDARY. It is very likely no longer valid if
1320 the hard frame pointer was used for register allocation. */
1321 if (!frame_pointer_needed
)
1322 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1325 substitute_stack
.release ();
1327 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1329 reload_completed
= !failure
;
1334 /* Yet another special case. Unfortunately, reg-stack forces people to
1335 write incorrect clobbers in asm statements. These clobbers must not
1336 cause the register to appear in bad_spill_regs, otherwise we'll call
1337 fatal_insn later. We clear the corresponding regnos in the live
1338 register sets to avoid this.
1339 The whole thing is rather sick, I'm afraid. */
1342 maybe_fix_stack_asms (void)
1345 const char *constraints
[MAX_RECOG_OPERANDS
];
1346 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1347 struct insn_chain
*chain
;
1349 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1352 HARD_REG_SET clobbered
, allowed
;
1355 if (! INSN_P (chain
->insn
)
1356 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1358 pat
= PATTERN (chain
->insn
);
1359 if (GET_CODE (pat
) != PARALLEL
)
1362 CLEAR_HARD_REG_SET (clobbered
);
1363 CLEAR_HARD_REG_SET (allowed
);
1365 /* First, make a mask of all stack regs that are clobbered. */
1366 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1368 rtx t
= XVECEXP (pat
, 0, i
);
1369 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1370 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1373 /* Get the operand values and constraints out of the insn. */
1374 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1375 constraints
, operand_mode
, NULL
);
1377 /* For every operand, see what registers are allowed. */
1378 for (i
= 0; i
< noperands
; i
++)
1380 const char *p
= constraints
[i
];
1381 /* For every alternative, we compute the class of registers allowed
1382 for reloading in CLS, and merge its contents into the reg set
1384 int cls
= (int) NO_REGS
;
1390 if (c
== '\0' || c
== ',' || c
== '#')
1392 /* End of one alternative - mark the regs in the current
1393 class, and reset the class. */
1394 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1400 } while (c
!= '\0' && c
!= ',');
1408 case '=': case '+': case '*': case '%': case '?': case '!':
1409 case '0': case '1': case '2': case '3': case '4': case '<':
1410 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1411 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1412 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1413 case TARGET_MEM_CONSTRAINT
:
1417 cls
= (int) reg_class_subunion
[cls
]
1418 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1424 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1428 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1429 cls
= (int) reg_class_subunion
[cls
]
1430 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1433 cls
= (int) reg_class_subunion
[cls
]
1434 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1436 p
+= CONSTRAINT_LEN (c
, p
);
1439 /* Those of the registers which are clobbered, but allowed by the
1440 constraints, must be usable as reload registers. So clear them
1441 out of the life information. */
1442 AND_HARD_REG_SET (allowed
, clobbered
);
1443 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1444 if (TEST_HARD_REG_BIT (allowed
, i
))
1446 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1447 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1454 /* Copy the global variables n_reloads and rld into the corresponding elts
1457 copy_reloads (struct insn_chain
*chain
)
1459 chain
->n_reloads
= n_reloads
;
1460 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1461 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1462 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1465 /* Walk the chain of insns, and determine for each whether it needs reloads
1466 and/or eliminations. Build the corresponding insns_need_reload list, and
1467 set something_needs_elimination as appropriate. */
1469 calculate_needs_all_insns (int global
)
1471 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1472 struct insn_chain
*chain
, *next
= 0;
1474 something_needs_elimination
= 0;
1476 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1477 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1479 rtx insn
= chain
->insn
;
1483 /* Clear out the shortcuts. */
1484 chain
->n_reloads
= 0;
1485 chain
->need_elim
= 0;
1486 chain
->need_reload
= 0;
1487 chain
->need_operand_change
= 0;
1489 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1490 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1491 what effects this has on the known offsets at labels. */
1493 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1494 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1495 set_label_offsets (insn
, insn
, 0);
1499 rtx old_body
= PATTERN (insn
);
1500 int old_code
= INSN_CODE (insn
);
1501 rtx old_notes
= REG_NOTES (insn
);
1502 int did_elimination
= 0;
1503 int operands_changed
= 0;
1504 rtx set
= single_set (insn
);
1506 /* Skip insns that only set an equivalence. */
1507 if (set
&& REG_P (SET_DEST (set
))
1508 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1509 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1510 || (reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1511 && reg_equiv_init (REGNO (SET_DEST (set
))))
1514 /* If needed, eliminate any eliminable registers. */
1515 if (num_eliminable
|| num_eliminable_invariants
)
1516 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1518 /* Analyze the instruction. */
1519 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1520 global
, spill_reg_order
);
1522 /* If a no-op set needs more than one reload, this is likely
1523 to be something that needs input address reloads. We
1524 can't get rid of this cleanly later, and it is of no use
1525 anyway, so discard it now.
1526 We only do this when expensive_optimizations is enabled,
1527 since this complements reload inheritance / output
1528 reload deletion, and it can make debugging harder. */
1529 if (flag_expensive_optimizations
&& n_reloads
> 1)
1531 rtx set
= single_set (insn
);
1534 ((SET_SRC (set
) == SET_DEST (set
)
1535 && REG_P (SET_SRC (set
))
1536 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1537 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1538 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1539 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1540 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1541 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1542 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1543 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1545 if (ira_conflicts_p
)
1546 /* Inform IRA about the insn deletion. */
1547 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1548 REGNO (SET_SRC (set
)));
1550 /* Delete it from the reload chain. */
1552 chain
->prev
->next
= next
;
1554 reload_insn_chain
= next
;
1556 next
->prev
= chain
->prev
;
1557 chain
->next
= unused_insn_chains
;
1558 unused_insn_chains
= chain
;
1563 update_eliminable_offsets ();
1565 /* Remember for later shortcuts which insns had any reloads or
1566 register eliminations. */
1567 chain
->need_elim
= did_elimination
;
1568 chain
->need_reload
= n_reloads
> 0;
1569 chain
->need_operand_change
= operands_changed
;
1571 /* Discard any register replacements done. */
1572 if (did_elimination
)
1574 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1575 PATTERN (insn
) = old_body
;
1576 INSN_CODE (insn
) = old_code
;
1577 REG_NOTES (insn
) = old_notes
;
1578 something_needs_elimination
= 1;
1581 something_needs_operands_changed
|= operands_changed
;
1585 copy_reloads (chain
);
1586 *pprev_reload
= chain
;
1587 pprev_reload
= &chain
->next_need_reload
;
1594 /* This function is called from the register allocator to set up estimates
1595 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1596 an invariant. The structure is similar to calculate_needs_all_insns. */
1599 calculate_elim_costs_all_insns (void)
1601 int *reg_equiv_init_cost
;
1605 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1607 init_eliminable_invariants (get_insns (), false);
1609 set_initial_elim_offsets ();
1610 set_initial_label_offsets ();
1617 FOR_BB_INSNS (bb
, insn
)
1619 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1620 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1621 what effects this has on the known offsets at labels. */
1623 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1624 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1625 set_label_offsets (insn
, insn
, 0);
1629 rtx set
= single_set (insn
);
1631 /* Skip insns that only set an equivalence. */
1632 if (set
&& REG_P (SET_DEST (set
))
1633 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1634 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1635 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1637 unsigned regno
= REGNO (SET_DEST (set
));
1638 rtx init
= reg_equiv_init (regno
);
1641 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1643 int cost
= set_src_cost (t
, optimize_bb_for_speed_p (bb
));
1644 int freq
= REG_FREQ_FROM_BB (bb
);
1646 reg_equiv_init_cost
[regno
] = cost
* freq
;
1650 /* If needed, eliminate any eliminable registers. */
1651 if (num_eliminable
|| num_eliminable_invariants
)
1652 elimination_costs_in_insn (insn
);
1655 update_eliminable_offsets ();
1659 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1661 if (reg_equiv_invariant (i
))
1663 if (reg_equiv_init (i
))
1665 int cost
= reg_equiv_init_cost
[i
];
1668 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1670 ira_adjust_equiv_reg_cost (i
, cost
);
1676 "Reg %d had equivalence, but can't be eliminated\n",
1678 ira_adjust_equiv_reg_cost (i
, 0);
1683 free (reg_equiv_init_cost
);
1684 free (offsets_known_at
);
1687 offsets_known_at
= NULL
;
1690 /* Comparison function for qsort to decide which of two reloads
1691 should be handled first. *P1 and *P2 are the reload numbers. */
1694 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1696 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1699 /* Consider required reloads before optional ones. */
1700 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1704 /* Count all solitary classes before non-solitary ones. */
1705 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1706 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1710 /* Aside from solitaires, consider all multi-reg groups first. */
1711 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1715 /* Consider reloads in order of increasing reg-class number. */
1716 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1720 /* If reloads are equally urgent, sort by reload number,
1721 so that the results of qsort leave nothing to chance. */
1725 /* The cost of spilling each hard reg. */
1726 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1728 /* When spilling multiple hard registers, we use SPILL_COST for the first
1729 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1730 only the first hard reg for a multi-reg pseudo. */
1731 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1733 /* Map of hard regno to pseudo regno currently occupying the hard
1735 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1737 /* Update the spill cost arrays, considering that pseudo REG is live. */
1740 count_pseudo (int reg
)
1742 int freq
= REG_FREQ (reg
);
1743 int r
= reg_renumber
[reg
];
1746 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1747 if (ira_conflicts_p
&& r
< 0)
1750 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1751 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1754 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1756 gcc_assert (r
>= 0);
1758 spill_add_cost
[r
] += freq
;
1759 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1762 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1763 spill_cost
[r
+ nregs
] += freq
;
1767 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1768 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1771 order_regs_for_reload (struct insn_chain
*chain
)
1774 HARD_REG_SET used_by_pseudos
;
1775 HARD_REG_SET used_by_pseudos2
;
1776 reg_set_iterator rsi
;
1778 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1780 memset (spill_cost
, 0, sizeof spill_cost
);
1781 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1782 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1783 hard_regno_to_pseudo_regno
[i
] = -1;
1785 /* Count number of uses of each hard reg by pseudo regs allocated to it
1786 and then order them by decreasing use. First exclude hard registers
1787 that are live in or across this insn. */
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1790 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1791 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1792 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1794 /* Now find out which pseudos are allocated to it, and update
1796 CLEAR_REG_SET (&pseudos_counted
);
1798 EXECUTE_IF_SET_IN_REG_SET
1799 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1803 EXECUTE_IF_SET_IN_REG_SET
1804 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1808 CLEAR_REG_SET (&pseudos_counted
);
1811 /* Vector of reload-numbers showing the order in which the reloads should
1813 static short reload_order
[MAX_RELOADS
];
1815 /* This is used to keep track of the spill regs used in one insn. */
1816 static HARD_REG_SET used_spill_regs_local
;
1818 /* We decided to spill hard register SPILLED, which has a size of
1819 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1820 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1821 update SPILL_COST/SPILL_ADD_COST. */
1824 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1826 int freq
= REG_FREQ (reg
);
1827 int r
= reg_renumber
[reg
];
1830 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1831 if (ira_conflicts_p
&& r
< 0)
1834 gcc_assert (r
>= 0);
1836 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1838 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1839 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1842 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1844 spill_add_cost
[r
] -= freq
;
1847 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1848 spill_cost
[r
+ nregs
] -= freq
;
1852 /* Find reload register to use for reload number ORDER. */
1855 find_reg (struct insn_chain
*chain
, int order
)
1857 int rnum
= reload_order
[order
];
1858 struct reload
*rl
= rld
+ rnum
;
1859 int best_cost
= INT_MAX
;
1861 unsigned int i
, j
, n
;
1863 HARD_REG_SET not_usable
;
1864 HARD_REG_SET used_by_other_reload
;
1865 reg_set_iterator rsi
;
1866 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1867 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1869 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1870 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1871 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1873 CLEAR_HARD_REG_SET (used_by_other_reload
);
1874 for (k
= 0; k
< order
; k
++)
1876 int other
= reload_order
[k
];
1878 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1879 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1880 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1883 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1885 #ifdef REG_ALLOC_ORDER
1886 unsigned int regno
= reg_alloc_order
[i
];
1888 unsigned int regno
= i
;
1891 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1892 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1893 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1895 int this_cost
= spill_cost
[regno
];
1897 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1899 for (j
= 1; j
< this_nregs
; j
++)
1901 this_cost
+= spill_add_cost
[regno
+ j
];
1902 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1903 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1909 if (ira_conflicts_p
)
1911 /* Ask IRA to find a better pseudo-register for
1913 for (n
= j
= 0; j
< this_nregs
; j
++)
1915 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1919 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1920 regno_pseudo_regs
[n
++] = r
;
1922 regno_pseudo_regs
[n
++] = -1;
1924 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1925 best_regno_pseudo_regs
,
1932 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1933 if (regno_pseudo_regs
[j
] < 0)
1940 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1942 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1944 if (this_cost
< best_cost
1945 /* Among registers with equal cost, prefer caller-saved ones, or
1946 use REG_ALLOC_ORDER if it is defined. */
1947 || (this_cost
== best_cost
1948 #ifdef REG_ALLOC_ORDER
1949 && (inv_reg_alloc_order
[regno
]
1950 < inv_reg_alloc_order
[best_reg
])
1952 && call_used_regs
[regno
]
1953 && ! call_used_regs
[best_reg
]
1958 best_cost
= this_cost
;
1966 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1968 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1969 rl
->regno
= best_reg
;
1971 EXECUTE_IF_SET_IN_REG_SET
1972 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1974 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1977 EXECUTE_IF_SET_IN_REG_SET
1978 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1980 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1983 for (i
= 0; i
< rl
->nregs
; i
++)
1985 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1986 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1987 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1988 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1993 /* Find more reload regs to satisfy the remaining need of an insn, which
1995 Do it by ascending class number, since otherwise a reg
1996 might be spilled for a big class and might fail to count
1997 for a smaller class even though it belongs to that class. */
2000 find_reload_regs (struct insn_chain
*chain
)
2004 /* In order to be certain of getting the registers we need,
2005 we must sort the reloads into order of increasing register class.
2006 Then our grabbing of reload registers will parallel the process
2007 that provided the reload registers. */
2008 for (i
= 0; i
< chain
->n_reloads
; i
++)
2010 /* Show whether this reload already has a hard reg. */
2011 if (chain
->rld
[i
].reg_rtx
)
2013 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
2014 chain
->rld
[i
].regno
= regno
;
2016 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2019 chain
->rld
[i
].regno
= -1;
2020 reload_order
[i
] = i
;
2023 n_reloads
= chain
->n_reloads
;
2024 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2026 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2029 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2031 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2033 /* Compute the order of preference for hard registers to spill. */
2035 order_regs_for_reload (chain
);
2037 for (i
= 0; i
< n_reloads
; i
++)
2039 int r
= reload_order
[i
];
2041 /* Ignore reloads that got marked inoperative. */
2042 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2043 && ! rld
[r
].optional
2044 && rld
[r
].regno
== -1)
2045 if (! find_reg (chain
, i
))
2048 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2049 spill_failure (chain
->insn
, rld
[r
].rclass
);
2055 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2056 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2058 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2062 select_reload_regs (void)
2064 struct insn_chain
*chain
;
2066 /* Try to satisfy the needs for each insn. */
2067 for (chain
= insns_need_reload
; chain
!= 0;
2068 chain
= chain
->next_need_reload
)
2069 find_reload_regs (chain
);
2072 /* Delete all insns that were inserted by emit_caller_save_insns during
2075 delete_caller_save_insns (void)
2077 struct insn_chain
*c
= reload_insn_chain
;
2081 while (c
!= 0 && c
->is_caller_save_insn
)
2083 struct insn_chain
*next
= c
->next
;
2086 if (c
== reload_insn_chain
)
2087 reload_insn_chain
= next
;
2091 next
->prev
= c
->prev
;
2093 c
->prev
->next
= next
;
2094 c
->next
= unused_insn_chains
;
2095 unused_insn_chains
= c
;
2103 /* Handle the failure to find a register to spill.
2104 INSN should be one of the insns which needed this particular spill reg. */
2107 spill_failure (rtx insn
, enum reg_class rclass
)
2109 if (asm_noperands (PATTERN (insn
)) >= 0)
2110 error_for_asm (insn
, "can%'t find a register in class %qs while "
2111 "reloading %<asm%>",
2112 reg_class_names
[rclass
]);
2115 error ("unable to find a register to spill in class %qs",
2116 reg_class_names
[rclass
]);
2120 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2121 debug_reload_to_stream (dump_file
);
2123 fatal_insn ("this is the insn:", insn
);
2127 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2128 data that is dead in INSN. */
2131 delete_dead_insn (rtx insn
)
2133 rtx prev
= prev_active_insn (insn
);
2136 /* If the previous insn sets a register that dies in our insn make
2137 a note that we want to run DCE immediately after reload.
2139 We used to delete the previous insn & recurse, but that's wrong for
2140 block local equivalences. Instead of trying to figure out the exact
2141 circumstances where we can delete the potentially dead insns, just
2142 let DCE do the job. */
2143 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2144 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2145 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2146 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2147 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2150 SET_INSN_DELETED (insn
);
2153 /* Modify the home of pseudo-reg I.
2154 The new home is present in reg_renumber[I].
2156 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2157 or it may be -1, meaning there is none or it is not relevant.
2158 This is used so that all pseudos spilled from a given hard reg
2159 can share one stack slot. */
2162 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2164 /* When outputting an inline function, this can happen
2165 for a reg that isn't actually used. */
2166 if (regno_reg_rtx
[i
] == 0)
2169 /* If the reg got changed to a MEM at rtl-generation time,
2171 if (!REG_P (regno_reg_rtx
[i
]))
2174 /* Modify the reg-rtx to contain the new hard reg
2175 number or else to contain its pseudo reg number. */
2176 SET_REGNO (regno_reg_rtx
[i
],
2177 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2179 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2180 allocate a stack slot for it. */
2182 if (reg_renumber
[i
] < 0
2183 && REG_N_REFS (i
) > 0
2184 && reg_equiv_constant (i
) == 0
2185 && (reg_equiv_invariant (i
) == 0
2186 || reg_equiv_init (i
) == 0)
2187 && reg_equiv_memory_loc (i
) == 0)
2190 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2191 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2192 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2193 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2194 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2197 something_was_spilled
= true;
2199 if (ira_conflicts_p
)
2201 /* Mark the spill for IRA. */
2202 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2204 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2210 /* Each pseudo reg has an inherent size which comes from its own mode,
2211 and a total size which provides room for paradoxical subregs
2212 which refer to the pseudo reg in wider modes.
2214 We can use a slot already allocated if it provides both
2215 enough inherent space and enough total space.
2216 Otherwise, we allocate a new slot, making sure that it has no less
2217 inherent space, and no less total space, then the previous slot. */
2218 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2222 /* No known place to spill from => no slot to reuse. */
2223 x
= assign_stack_local (mode
, total_size
,
2224 min_align
> inherent_align
2225 || total_size
> inherent_size
? -1 : 0);
2229 /* Cancel the big-endian correction done in assign_stack_local.
2230 Get the address of the beginning of the slot. This is so we
2231 can do a big-endian correction unconditionally below. */
2232 if (BYTES_BIG_ENDIAN
)
2234 adjust
= inherent_size
- total_size
;
2237 = adjust_address_nv (x
, mode_for_size (total_size
2243 if (! dont_share_p
&& ira_conflicts_p
)
2244 /* Inform IRA about allocation a new stack slot. */
2245 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2248 /* Reuse a stack slot if possible. */
2249 else if (spill_stack_slot
[from_reg
] != 0
2250 && spill_stack_slot_width
[from_reg
] >= total_size
2251 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2253 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2254 x
= spill_stack_slot
[from_reg
];
2256 /* Allocate a bigger slot. */
2259 /* Compute maximum size needed, both for inherent size
2260 and for total size. */
2263 if (spill_stack_slot
[from_reg
])
2265 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2267 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2268 if (spill_stack_slot_width
[from_reg
] > total_size
)
2269 total_size
= spill_stack_slot_width
[from_reg
];
2270 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2271 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2274 /* Make a slot with that size. */
2275 x
= assign_stack_local (mode
, total_size
,
2276 min_align
> inherent_align
2277 || total_size
> inherent_size
? -1 : 0);
2280 /* Cancel the big-endian correction done in assign_stack_local.
2281 Get the address of the beginning of the slot. This is so we
2282 can do a big-endian correction unconditionally below. */
2283 if (BYTES_BIG_ENDIAN
)
2285 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2288 = adjust_address_nv (x
, mode_for_size (total_size
2294 spill_stack_slot
[from_reg
] = stack_slot
;
2295 spill_stack_slot_width
[from_reg
] = total_size
;
2298 /* On a big endian machine, the "address" of the slot
2299 is the address of the low part that fits its inherent mode. */
2300 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2301 adjust
+= (total_size
- inherent_size
);
2303 /* If we have any adjustment to make, or if the stack slot is the
2304 wrong mode, make a new stack slot. */
2305 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2307 /* Set all of the memory attributes as appropriate for a spill. */
2308 set_mem_attrs_for_spill (x
);
2310 /* Save the stack slot for later. */
2311 reg_equiv_memory_loc (i
) = x
;
2315 /* Mark the slots in regs_ever_live for the hard regs used by
2316 pseudo-reg number REGNO, accessed in MODE. */
2319 mark_home_live_1 (int regno
, enum machine_mode mode
)
2323 i
= reg_renumber
[regno
];
2326 lim
= end_hard_regno (mode
, i
);
2328 df_set_regs_ever_live (i
++, true);
2331 /* Mark the slots in regs_ever_live for the hard regs
2332 used by pseudo-reg number REGNO. */
2335 mark_home_live (int regno
)
2337 if (reg_renumber
[regno
] >= 0)
2338 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2341 /* This function handles the tracking of elimination offsets around branches.
2343 X is a piece of RTL being scanned.
2345 INSN is the insn that it came from, if any.
2347 INITIAL_P is nonzero if we are to set the offset to be the initial
2348 offset and zero if we are setting the offset of the label to be the
2352 set_label_offsets (rtx x
, rtx insn
, int initial_p
)
2354 enum rtx_code code
= GET_CODE (x
);
2357 struct elim_table
*p
;
2362 if (LABEL_REF_NONLOCAL_P (x
))
2367 /* ... fall through ... */
2370 /* If we know nothing about this label, set the desired offsets. Note
2371 that this sets the offset at a label to be the offset before a label
2372 if we don't know anything about the label. This is not correct for
2373 the label after a BARRIER, but is the best guess we can make. If
2374 we guessed wrong, we will suppress an elimination that might have
2375 been possible had we been able to guess correctly. */
2377 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2379 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2380 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2381 = (initial_p
? reg_eliminate
[i
].initial_offset
2382 : reg_eliminate
[i
].offset
);
2383 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2386 /* Otherwise, if this is the definition of a label and it is
2387 preceded by a BARRIER, set our offsets to the known offset of
2391 && (tem
= prev_nonnote_insn (insn
)) != 0
2393 set_offsets_for_label (insn
);
2395 /* If neither of the above cases is true, compare each offset
2396 with those previously recorded and suppress any eliminations
2397 where the offsets disagree. */
2399 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2400 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2401 != (initial_p
? reg_eliminate
[i
].initial_offset
2402 : reg_eliminate
[i
].offset
))
2403 reg_eliminate
[i
].can_eliminate
= 0;
2407 case JUMP_TABLE_DATA
:
2408 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2412 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2414 /* ... fall through ... */
2418 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2419 to indirectly and hence must have all eliminations at their
2421 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2422 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2423 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2429 /* Each of the labels in the parallel or address vector must be
2430 at their initial offsets. We want the first field for PARALLEL
2431 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2433 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2434 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2439 /* We only care about setting PC. If the source is not RETURN,
2440 IF_THEN_ELSE, or a label, disable any eliminations not at
2441 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2442 isn't one of those possibilities. For branches to a label,
2443 call ourselves recursively.
2445 Note that this can disable elimination unnecessarily when we have
2446 a non-local goto since it will look like a non-constant jump to
2447 someplace in the current function. This isn't a significant
2448 problem since such jumps will normally be when all elimination
2449 pairs are back to their initial offsets. */
2451 if (SET_DEST (x
) != pc_rtx
)
2454 switch (GET_CODE (SET_SRC (x
)))
2461 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2465 tem
= XEXP (SET_SRC (x
), 1);
2466 if (GET_CODE (tem
) == LABEL_REF
)
2467 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2468 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2471 tem
= XEXP (SET_SRC (x
), 2);
2472 if (GET_CODE (tem
) == LABEL_REF
)
2473 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2474 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2482 /* If we reach here, all eliminations must be at their initial
2483 offset because we are doing a jump to a variable address. */
2484 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2485 if (p
->offset
!= p
->initial_offset
)
2486 p
->can_eliminate
= 0;
2494 /* Called through for_each_rtx, this function examines every reg that occurs
2495 in PX and adjusts the costs for its elimination which are gathered by IRA.
2496 DATA is the insn in which PX occurs. We do not recurse into MEM
2500 note_reg_elim_costly (rtx
*px
, void *data
)
2502 rtx insn
= (rtx
)data
;
2509 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2510 && reg_equiv_init (REGNO (x
))
2511 && reg_equiv_invariant (REGNO (x
)))
2513 rtx t
= reg_equiv_invariant (REGNO (x
));
2514 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2515 int cost
= set_src_cost (new_rtx
, optimize_bb_for_speed_p (elim_bb
));
2516 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2519 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2524 /* Scan X and replace any eliminable registers (such as fp) with a
2525 replacement (such as sp), plus an offset.
2527 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2528 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2529 MEM, we are allowed to replace a sum of a register and the constant zero
2530 with the register, which we cannot do outside a MEM. In addition, we need
2531 to record the fact that a register is referenced outside a MEM.
2533 If INSN is an insn, it is the insn containing X. If we replace a REG
2534 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2535 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2536 the REG is being modified.
2538 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2539 That's used when we eliminate in expressions stored in notes.
2540 This means, do not set ref_outside_mem even if the reference
2543 If FOR_COSTS is true, we are being called before reload in order to
2544 estimate the costs of keeping registers with an equivalence unallocated.
2546 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2547 replacements done assuming all offsets are at their initial values. If
2548 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2549 encounter, return the actual location so that find_reloads will do
2550 the proper thing. */
2553 eliminate_regs_1 (rtx x
, enum machine_mode mem_mode
, rtx insn
,
2554 bool may_use_invariant
, bool for_costs
)
2556 enum rtx_code code
= GET_CODE (x
);
2557 struct elim_table
*ep
;
2564 if (! current_function_decl
)
2584 /* First handle the case where we encounter a bare register that
2585 is eliminable. Replace it with a PLUS. */
2586 if (regno
< FIRST_PSEUDO_REGISTER
)
2588 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2590 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2591 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2594 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2596 && reg_equiv_invariant (regno
))
2598 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2599 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2600 mem_mode
, insn
, true, for_costs
);
2601 /* There exists at least one use of REGNO that cannot be
2602 eliminated. Prevent the defining insn from being deleted. */
2603 reg_equiv_init (regno
) = NULL_RTX
;
2605 alter_reg (regno
, -1, true);
2609 /* You might think handling MINUS in a manner similar to PLUS is a
2610 good idea. It is not. It has been tried multiple times and every
2611 time the change has had to have been reverted.
2613 Other parts of reload know a PLUS is special (gen_reload for example)
2614 and require special code to handle code a reloaded PLUS operand.
2616 Also consider backends where the flags register is clobbered by a
2617 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2618 lea instruction comes to mind). If we try to reload a MINUS, we
2619 may kill the flags register that was holding a useful value.
2621 So, please before trying to handle MINUS, consider reload as a
2622 whole instead of this little section as well as the backend issues. */
2624 /* If this is the sum of an eliminable register and a constant, rework
2626 if (REG_P (XEXP (x
, 0))
2627 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2628 && CONSTANT_P (XEXP (x
, 1)))
2630 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2632 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2634 /* The only time we want to replace a PLUS with a REG (this
2635 occurs when the constant operand of the PLUS is the negative
2636 of the offset) is when we are inside a MEM. We won't want
2637 to do so at other times because that would change the
2638 structure of the insn in a way that reload can't handle.
2639 We special-case the commonest situation in
2640 eliminate_regs_in_insn, so just replace a PLUS with a
2641 PLUS here, unless inside a MEM. */
2642 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2643 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2646 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2647 plus_constant (Pmode
, XEXP (x
, 1),
2648 ep
->previous_offset
));
2651 /* If the register is not eliminable, we are done since the other
2652 operand is a constant. */
2656 /* If this is part of an address, we want to bring any constant to the
2657 outermost PLUS. We will do this by doing register replacement in
2658 our operands and seeing if a constant shows up in one of them.
2660 Note that there is no risk of modifying the structure of the insn,
2661 since we only get called for its operands, thus we are either
2662 modifying the address inside a MEM, or something like an address
2663 operand of a load-address insn. */
2666 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2668 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2671 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2673 /* If one side is a PLUS and the other side is a pseudo that
2674 didn't get a hard register but has a reg_equiv_constant,
2675 we must replace the constant here since it may no longer
2676 be in the position of any operand. */
2677 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2678 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2679 && reg_renumber
[REGNO (new1
)] < 0
2681 && reg_equiv_constant (REGNO (new1
)) != 0)
2682 new1
= reg_equiv_constant (REGNO (new1
));
2683 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2684 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2685 && reg_renumber
[REGNO (new0
)] < 0
2686 && reg_equiv_constant (REGNO (new0
)) != 0)
2687 new0
= reg_equiv_constant (REGNO (new0
));
2689 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2691 /* As above, if we are not inside a MEM we do not want to
2692 turn a PLUS into something else. We might try to do so here
2693 for an addition of 0 if we aren't optimizing. */
2694 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2695 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2703 /* If this is the product of an eliminable register and a
2704 constant, apply the distribute law and move the constant out
2705 so that we have (plus (mult ..) ..). This is needed in order
2706 to keep load-address insns valid. This case is pathological.
2707 We ignore the possibility of overflow here. */
2708 if (REG_P (XEXP (x
, 0))
2709 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2710 && CONST_INT_P (XEXP (x
, 1)))
2711 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2713 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2716 /* Refs inside notes or in DEBUG_INSNs don't count for
2718 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2719 || GET_CODE (insn
) == INSN_LIST
2720 || DEBUG_INSN_P (insn
))))
2721 ep
->ref_outside_mem
= 1;
2724 plus_constant (Pmode
,
2725 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2726 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2729 /* ... fall through ... */
2733 /* See comments before PLUS about handling MINUS. */
2735 case DIV
: case UDIV
:
2736 case MOD
: case UMOD
:
2737 case AND
: case IOR
: case XOR
:
2738 case ROTATERT
: case ROTATE
:
2739 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2741 case GE
: case GT
: case GEU
: case GTU
:
2742 case LE
: case LT
: case LEU
: case LTU
:
2744 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2746 rtx new1
= XEXP (x
, 1)
2747 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2750 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2751 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2756 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2759 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2761 if (new_rtx
!= XEXP (x
, 0))
2763 /* If this is a REG_DEAD note, it is not valid anymore.
2764 Using the eliminated version could result in creating a
2765 REG_DEAD note for the stack or frame pointer. */
2766 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2768 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2772 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2776 /* ... fall through ... */
2780 /* Now do eliminations in the rest of the chain. If this was
2781 an EXPR_LIST, this might result in allocating more memory than is
2782 strictly needed, but it simplifies the code. */
2785 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2787 if (new_rtx
!= XEXP (x
, 1))
2789 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2797 /* We do not support elimination of a register that is modified.
2798 elimination_effects has already make sure that this does not
2804 /* We do not support elimination of a register that is modified.
2805 elimination_effects has already make sure that this does not
2806 happen. The only remaining case we need to consider here is
2807 that the increment value may be an eliminable register. */
2808 if (GET_CODE (XEXP (x
, 1)) == PLUS
2809 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2811 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2812 insn
, true, for_costs
);
2814 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2815 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2816 gen_rtx_PLUS (GET_MODE (x
),
2817 XEXP (x
, 0), new_rtx
));
2821 case STRICT_LOW_PART
:
2823 case SIGN_EXTEND
: case ZERO_EXTEND
:
2824 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2825 case FLOAT
: case FIX
:
2826 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2835 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2837 if (new_rtx
!= XEXP (x
, 0))
2838 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2842 /* Similar to above processing, but preserve SUBREG_BYTE.
2843 Convert (subreg (mem)) to (mem) if not paradoxical.
2844 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2845 pseudo didn't get a hard reg, we must replace this with the
2846 eliminated version of the memory location because push_reload
2847 may do the replacement in certain circumstances. */
2848 if (REG_P (SUBREG_REG (x
))
2849 && !paradoxical_subreg_p (x
)
2851 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2853 new_rtx
= SUBREG_REG (x
);
2856 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2858 if (new_rtx
!= SUBREG_REG (x
))
2860 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2861 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2864 && ((x_size
< new_size
2865 #ifdef WORD_REGISTER_OPERATIONS
2866 /* On these machines, combine can create rtl of the form
2867 (set (subreg:m1 (reg:m2 R) 0) ...)
2868 where m1 < m2, and expects something interesting to
2869 happen to the entire word. Moreover, it will use the
2870 (reg:m2 R) later, expecting all bits to be preserved.
2871 So if the number of words is the same, preserve the
2872 subreg so that push_reload can see it. */
2873 && ! ((x_size
- 1) / UNITS_PER_WORD
2874 == (new_size
-1 ) / UNITS_PER_WORD
)
2877 || x_size
== new_size
)
2879 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2881 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2887 /* Our only special processing is to pass the mode of the MEM to our
2888 recursive call and copy the flags. While we are here, handle this
2889 case more efficiently. */
2891 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2894 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2895 && !memory_address_p (GET_MODE (x
), new_rtx
))
2896 for_each_rtx (&XEXP (x
, 0), note_reg_elim_costly
, insn
);
2898 return replace_equiv_address_nv (x
, new_rtx
);
2901 /* Handle insn_list USE that a call to a pure function may generate. */
2902 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2904 if (new_rtx
!= XEXP (x
, 0))
2905 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2910 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2920 /* Process each of our operands recursively. If any have changed, make a
2922 fmt
= GET_RTX_FORMAT (code
);
2923 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2927 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2929 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2931 x
= shallow_copy_rtx (x
);
2934 XEXP (x
, i
) = new_rtx
;
2936 else if (*fmt
== 'E')
2939 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2941 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2943 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2945 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2949 x
= shallow_copy_rtx (x
);
2952 XVEC (x
, i
) = new_v
;
2955 XVECEXP (x
, i
, j
) = new_rtx
;
2964 eliminate_regs (rtx x
, enum machine_mode mem_mode
, rtx insn
)
2966 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2969 /* Scan rtx X for modifications of elimination target registers. Update
2970 the table of eliminables to reflect the changed state. MEM_MODE is
2971 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2974 elimination_effects (rtx x
, enum machine_mode mem_mode
)
2976 enum rtx_code code
= GET_CODE (x
);
2977 struct elim_table
*ep
;
2999 /* First handle the case where we encounter a bare register that
3000 is eliminable. Replace it with a PLUS. */
3001 if (regno
< FIRST_PSEUDO_REGISTER
)
3003 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3005 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
3008 ep
->ref_outside_mem
= 1;
3013 else if (reg_renumber
[regno
] < 0
3015 && reg_equiv_constant (regno
)
3016 && ! function_invariant_p (reg_equiv_constant (regno
)))
3017 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3026 /* If we modify the source of an elimination rule, disable it. */
3027 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3028 if (ep
->from_rtx
== XEXP (x
, 0))
3029 ep
->can_eliminate
= 0;
3031 /* If we modify the target of an elimination rule by adding a constant,
3032 update its offset. If we modify the target in any other way, we'll
3033 have to disable the rule as well. */
3034 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3035 if (ep
->to_rtx
== XEXP (x
, 0))
3037 int size
= GET_MODE_SIZE (mem_mode
);
3039 /* If more bytes than MEM_MODE are pushed, account for them. */
3040 #ifdef PUSH_ROUNDING
3041 if (ep
->to_rtx
== stack_pointer_rtx
)
3042 size
= PUSH_ROUNDING (size
);
3044 if (code
== PRE_DEC
|| code
== POST_DEC
)
3046 else if (code
== PRE_INC
|| code
== POST_INC
)
3048 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3050 if (GET_CODE (XEXP (x
, 1)) == PLUS
3051 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3052 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3053 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3055 ep
->can_eliminate
= 0;
3059 /* These two aren't unary operators. */
3060 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3063 /* Fall through to generic unary operation case. */
3064 case STRICT_LOW_PART
:
3066 case SIGN_EXTEND
: case ZERO_EXTEND
:
3067 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3068 case FLOAT
: case FIX
:
3069 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3078 elimination_effects (XEXP (x
, 0), mem_mode
);
3082 if (REG_P (SUBREG_REG (x
))
3083 && (GET_MODE_SIZE (GET_MODE (x
))
3084 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3086 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3089 elimination_effects (SUBREG_REG (x
), mem_mode
);
3093 /* If using a register that is the source of an eliminate we still
3094 think can be performed, note it cannot be performed since we don't
3095 know how this register is used. */
3096 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3097 if (ep
->from_rtx
== XEXP (x
, 0))
3098 ep
->can_eliminate
= 0;
3100 elimination_effects (XEXP (x
, 0), mem_mode
);
3104 /* If clobbering a register that is the replacement register for an
3105 elimination we still think can be performed, note that it cannot
3106 be performed. Otherwise, we need not be concerned about it. */
3107 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3108 if (ep
->to_rtx
== XEXP (x
, 0))
3109 ep
->can_eliminate
= 0;
3111 elimination_effects (XEXP (x
, 0), mem_mode
);
3115 /* Check for setting a register that we know about. */
3116 if (REG_P (SET_DEST (x
)))
3118 /* See if this is setting the replacement register for an
3121 If DEST is the hard frame pointer, we do nothing because we
3122 assume that all assignments to the frame pointer are for
3123 non-local gotos and are being done at a time when they are valid
3124 and do not disturb anything else. Some machines want to
3125 eliminate a fake argument pointer (or even a fake frame pointer)
3126 with either the real frame or the stack pointer. Assignments to
3127 the hard frame pointer must not prevent this elimination. */
3129 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3131 if (ep
->to_rtx
== SET_DEST (x
)
3132 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3134 /* If it is being incremented, adjust the offset. Otherwise,
3135 this elimination can't be done. */
3136 rtx src
= SET_SRC (x
);
3138 if (GET_CODE (src
) == PLUS
3139 && XEXP (src
, 0) == SET_DEST (x
)
3140 && CONST_INT_P (XEXP (src
, 1)))
3141 ep
->offset
-= INTVAL (XEXP (src
, 1));
3143 ep
->can_eliminate
= 0;
3147 elimination_effects (SET_DEST (x
), VOIDmode
);
3148 elimination_effects (SET_SRC (x
), VOIDmode
);
3152 /* Our only special processing is to pass the mode of the MEM to our
3154 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3161 fmt
= GET_RTX_FORMAT (code
);
3162 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3165 elimination_effects (XEXP (x
, i
), mem_mode
);
3166 else if (*fmt
== 'E')
3167 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3168 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3172 /* Descend through rtx X and verify that no references to eliminable registers
3173 remain. If any do remain, mark the involved register as not
3177 check_eliminable_occurrences (rtx x
)
3186 code
= GET_CODE (x
);
3188 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3190 struct elim_table
*ep
;
3192 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3193 if (ep
->from_rtx
== x
)
3194 ep
->can_eliminate
= 0;
3198 fmt
= GET_RTX_FORMAT (code
);
3199 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3202 check_eliminable_occurrences (XEXP (x
, i
));
3203 else if (*fmt
== 'E')
3206 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3207 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3212 /* Scan INSN and eliminate all eliminable registers in it.
3214 If REPLACE is nonzero, do the replacement destructively. Also
3215 delete the insn as dead it if it is setting an eliminable register.
3217 If REPLACE is zero, do all our allocations in reload_obstack.
3219 If no eliminations were done and this insn doesn't require any elimination
3220 processing (these are not identical conditions: it might be updating sp,
3221 but not referencing fp; this needs to be seen during reload_as_needed so
3222 that the offset between fp and sp can be taken into consideration), zero
3223 is returned. Otherwise, 1 is returned. */
3226 eliminate_regs_in_insn (rtx insn
, int replace
)
3228 int icode
= recog_memoized (insn
);
3229 rtx old_body
= PATTERN (insn
);
3230 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3231 rtx old_set
= single_set (insn
);
3235 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3236 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3237 struct elim_table
*ep
;
3238 rtx plus_src
, plus_cst_src
;
3240 if (! insn_is_asm
&& icode
< 0)
3242 gcc_assert (DEBUG_INSN_P (insn
)
3243 || GET_CODE (PATTERN (insn
)) == USE
3244 || GET_CODE (PATTERN (insn
)) == CLOBBER
3245 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3246 if (DEBUG_INSN_P (insn
))
3247 INSN_VAR_LOCATION_LOC (insn
)
3248 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3252 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3253 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3255 /* Check for setting an eliminable register. */
3256 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3257 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3259 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3260 /* If this is setting the frame pointer register to the
3261 hardware frame pointer register and this is an elimination
3262 that will be done (tested above), this insn is really
3263 adjusting the frame pointer downward to compensate for
3264 the adjustment done before a nonlocal goto. */
3265 if (ep
->from
== FRAME_POINTER_REGNUM
3266 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3268 rtx base
= SET_SRC (old_set
);
3269 rtx base_insn
= insn
;
3270 HOST_WIDE_INT offset
= 0;
3272 while (base
!= ep
->to_rtx
)
3274 rtx prev_insn
, prev_set
;
3276 if (GET_CODE (base
) == PLUS
3277 && CONST_INT_P (XEXP (base
, 1)))
3279 offset
+= INTVAL (XEXP (base
, 1));
3280 base
= XEXP (base
, 0);
3282 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3283 && (prev_set
= single_set (prev_insn
)) != 0
3284 && rtx_equal_p (SET_DEST (prev_set
), base
))
3286 base
= SET_SRC (prev_set
);
3287 base_insn
= prev_insn
;
3293 if (base
== ep
->to_rtx
)
3295 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3296 offset
- ep
->offset
);
3298 new_body
= old_body
;
3301 new_body
= copy_insn (old_body
);
3302 if (REG_NOTES (insn
))
3303 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3305 PATTERN (insn
) = new_body
;
3306 old_set
= single_set (insn
);
3308 /* First see if this insn remains valid when we
3309 make the change. If not, keep the INSN_CODE
3310 the same and let reload fit it up. */
3311 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3312 validate_change (insn
, &SET_DEST (old_set
),
3314 if (! apply_change_group ())
3316 SET_SRC (old_set
) = src
;
3317 SET_DEST (old_set
) = ep
->to_rtx
;
3326 /* In this case this insn isn't serving a useful purpose. We
3327 will delete it in reload_as_needed once we know that this
3328 elimination is, in fact, being done.
3330 If REPLACE isn't set, we can't delete this insn, but needn't
3331 process it since it won't be used unless something changes. */
3334 delete_dead_insn (insn
);
3342 /* We allow one special case which happens to work on all machines we
3343 currently support: a single set with the source or a REG_EQUAL
3344 note being a PLUS of an eliminable register and a constant. */
3345 plus_src
= plus_cst_src
= 0;
3346 if (old_set
&& REG_P (SET_DEST (old_set
)))
3348 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3349 plus_src
= SET_SRC (old_set
);
3350 /* First see if the source is of the form (plus (...) CST). */
3352 && CONST_INT_P (XEXP (plus_src
, 1)))
3353 plus_cst_src
= plus_src
;
3354 else if (REG_P (SET_SRC (old_set
))
3357 /* Otherwise, see if we have a REG_EQUAL note of the form
3358 (plus (...) CST). */
3360 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3362 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3363 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3364 && GET_CODE (XEXP (links
, 0)) == PLUS
3365 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3367 plus_cst_src
= XEXP (links
, 0);
3373 /* Check that the first operand of the PLUS is a hard reg or
3374 the lowpart subreg of one. */
3377 rtx reg
= XEXP (plus_cst_src
, 0);
3378 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3379 reg
= SUBREG_REG (reg
);
3381 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3387 rtx reg
= XEXP (plus_cst_src
, 0);
3388 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3390 if (GET_CODE (reg
) == SUBREG
)
3391 reg
= SUBREG_REG (reg
);
3393 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3394 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3396 rtx to_rtx
= ep
->to_rtx
;
3397 offset
+= ep
->offset
;
3398 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3400 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3401 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3403 /* If we have a nonzero offset, and the source is already
3404 a simple REG, the following transformation would
3405 increase the cost of the insn by replacing a simple REG
3406 with (plus (reg sp) CST). So try only when we already
3407 had a PLUS before. */
3408 if (offset
== 0 || plus_src
)
3410 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3413 new_body
= old_body
;
3416 new_body
= copy_insn (old_body
);
3417 if (REG_NOTES (insn
))
3418 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3420 PATTERN (insn
) = new_body
;
3421 old_set
= single_set (insn
);
3423 /* First see if this insn remains valid when we make the
3424 change. If not, try to replace the whole pattern with
3425 a simple set (this may help if the original insn was a
3426 PARALLEL that was only recognized as single_set due to
3427 REG_UNUSED notes). If this isn't valid either, keep
3428 the INSN_CODE the same and let reload fix it up. */
3429 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3431 rtx new_pat
= gen_rtx_SET (VOIDmode
,
3432 SET_DEST (old_set
), new_src
);
3434 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3435 SET_SRC (old_set
) = new_src
;
3442 /* This can't have an effect on elimination offsets, so skip right
3448 /* Determine the effects of this insn on elimination offsets. */
3449 elimination_effects (old_body
, VOIDmode
);
3451 /* Eliminate all eliminable registers occurring in operands that
3452 can be handled by reload. */
3453 extract_insn (insn
);
3454 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3456 orig_operand
[i
] = recog_data
.operand
[i
];
3457 substed_operand
[i
] = recog_data
.operand
[i
];
3459 /* For an asm statement, every operand is eliminable. */
3460 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3462 bool is_set_src
, in_plus
;
3464 /* Check for setting a register that we know about. */
3465 if (recog_data
.operand_type
[i
] != OP_IN
3466 && REG_P (orig_operand
[i
]))
3468 /* If we are assigning to a register that can be eliminated, it
3469 must be as part of a PARALLEL, since the code above handles
3470 single SETs. We must indicate that we can no longer
3471 eliminate this reg. */
3472 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3474 if (ep
->from_rtx
== orig_operand
[i
])
3475 ep
->can_eliminate
= 0;
3478 /* Companion to the above plus substitution, we can allow
3479 invariants as the source of a plain move. */
3482 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3486 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3487 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3491 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3492 replace
? insn
: NULL_RTX
,
3493 is_set_src
|| in_plus
, false);
3494 if (substed_operand
[i
] != orig_operand
[i
])
3496 /* Terminate the search in check_eliminable_occurrences at
3498 *recog_data
.operand_loc
[i
] = 0;
3500 /* If an output operand changed from a REG to a MEM and INSN is an
3501 insn, write a CLOBBER insn. */
3502 if (recog_data
.operand_type
[i
] != OP_IN
3503 && REG_P (orig_operand
[i
])
3504 && MEM_P (substed_operand
[i
])
3506 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3510 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3511 *recog_data
.dup_loc
[i
]
3512 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3514 /* If any eliminable remain, they aren't eliminable anymore. */
3515 check_eliminable_occurrences (old_body
);
3517 /* Substitute the operands; the new values are in the substed_operand
3519 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3520 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3521 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3522 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3524 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3525 re-recognize the insn. We do this in case we had a simple addition
3526 but now can do this as a load-address. This saves an insn in this
3528 If re-recognition fails, the old insn code number will still be used,
3529 and some register operands may have changed into PLUS expressions.
3530 These will be handled by find_reloads by loading them into a register
3535 /* If we aren't replacing things permanently and we changed something,
3536 make another copy to ensure that all the RTL is new. Otherwise
3537 things can go wrong if find_reload swaps commutative operands
3538 and one is inside RTL that has been copied while the other is not. */
3539 new_body
= old_body
;
3542 new_body
= copy_insn (old_body
);
3543 if (REG_NOTES (insn
))
3544 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3546 PATTERN (insn
) = new_body
;
3548 /* If we had a move insn but now we don't, rerecognize it. This will
3549 cause spurious re-recognition if the old move had a PARALLEL since
3550 the new one still will, but we can't call single_set without
3551 having put NEW_BODY into the insn and the re-recognition won't
3552 hurt in this rare case. */
3553 /* ??? Why this huge if statement - why don't we just rerecognize the
3557 && ((REG_P (SET_SRC (old_set
))
3558 && (GET_CODE (new_body
) != SET
3559 || !REG_P (SET_SRC (new_body
))))
3560 /* If this was a load from or store to memory, compare
3561 the MEM in recog_data.operand to the one in the insn.
3562 If they are not equal, then rerecognize the insn. */
3564 && ((MEM_P (SET_SRC (old_set
))
3565 && SET_SRC (old_set
) != recog_data
.operand
[1])
3566 || (MEM_P (SET_DEST (old_set
))
3567 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3568 /* If this was an add insn before, rerecognize. */
3569 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3571 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3573 INSN_CODE (insn
) = new_icode
;
3577 /* Restore the old body. If there were any changes to it, we made a copy
3578 of it while the changes were still in place, so we'll correctly return
3579 a modified insn below. */
3582 /* Restore the old body. */
3583 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3584 /* Restoring a top-level match_parallel would clobber the new_body
3585 we installed in the insn. */
3586 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3587 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3588 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3589 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3592 /* Update all elimination pairs to reflect the status after the current
3593 insn. The changes we make were determined by the earlier call to
3594 elimination_effects.
3596 We also detect cases where register elimination cannot be done,
3597 namely, if a register would be both changed and referenced outside a MEM
3598 in the resulting insn since such an insn is often undefined and, even if
3599 not, we cannot know what meaning will be given to it. Note that it is
3600 valid to have a register used in an address in an insn that changes it
3601 (presumably with a pre- or post-increment or decrement).
3603 If anything changes, return nonzero. */
3605 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3607 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3608 ep
->can_eliminate
= 0;
3610 ep
->ref_outside_mem
= 0;
3612 if (ep
->previous_offset
!= ep
->offset
)
3617 /* If we changed something, perform elimination in REG_NOTES. This is
3618 needed even when REPLACE is zero because a REG_DEAD note might refer
3619 to a register that we eliminate and could cause a different number
3620 of spill registers to be needed in the final reload pass than in
3622 if (val
&& REG_NOTES (insn
) != 0)
3624 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3630 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3631 register allocator. INSN is the instruction we need to examine, we perform
3632 eliminations in its operands and record cases where eliminating a reg with
3633 an invariant equivalence would add extra cost. */
3636 elimination_costs_in_insn (rtx insn
)
3638 int icode
= recog_memoized (insn
);
3639 rtx old_body
= PATTERN (insn
);
3640 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3641 rtx old_set
= single_set (insn
);
3643 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3644 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3645 struct elim_table
*ep
;
3646 rtx plus_src
, plus_cst_src
;
3649 if (! insn_is_asm
&& icode
< 0)
3651 gcc_assert (DEBUG_INSN_P (insn
)
3652 || GET_CODE (PATTERN (insn
)) == USE
3653 || GET_CODE (PATTERN (insn
)) == CLOBBER
3654 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3658 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3659 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3661 /* Check for setting an eliminable register. */
3662 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3663 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3667 /* We allow one special case which happens to work on all machines we
3668 currently support: a single set with the source or a REG_EQUAL
3669 note being a PLUS of an eliminable register and a constant. */
3670 plus_src
= plus_cst_src
= 0;
3672 if (old_set
&& REG_P (SET_DEST (old_set
)))
3675 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3676 plus_src
= SET_SRC (old_set
);
3677 /* First see if the source is of the form (plus (...) CST). */
3679 && CONST_INT_P (XEXP (plus_src
, 1)))
3680 plus_cst_src
= plus_src
;
3681 else if (REG_P (SET_SRC (old_set
))
3684 /* Otherwise, see if we have a REG_EQUAL note of the form
3685 (plus (...) CST). */
3687 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3689 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3690 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3691 && GET_CODE (XEXP (links
, 0)) == PLUS
3692 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3694 plus_cst_src
= XEXP (links
, 0);
3701 /* Determine the effects of this insn on elimination offsets. */
3702 elimination_effects (old_body
, VOIDmode
);
3704 /* Eliminate all eliminable registers occurring in operands that
3705 can be handled by reload. */
3706 extract_insn (insn
);
3707 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3708 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3710 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3712 orig_operand
[i
] = recog_data
.operand
[i
];
3714 /* For an asm statement, every operand is eliminable. */
3715 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3717 bool is_set_src
, in_plus
;
3719 /* Check for setting a register that we know about. */
3720 if (recog_data
.operand_type
[i
] != OP_IN
3721 && REG_P (orig_operand
[i
]))
3723 /* If we are assigning to a register that can be eliminated, it
3724 must be as part of a PARALLEL, since the code above handles
3725 single SETs. We must indicate that we can no longer
3726 eliminate this reg. */
3727 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3729 if (ep
->from_rtx
== orig_operand
[i
])
3730 ep
->can_eliminate
= 0;
3733 /* Companion to the above plus substitution, we can allow
3734 invariants as the source of a plain move. */
3736 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3738 if (is_set_src
&& !sets_reg_p
)
3739 note_reg_elim_costly (&SET_SRC (old_set
), insn
);
3741 if (plus_src
&& sets_reg_p
3742 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3743 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3746 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3748 is_set_src
|| in_plus
, true);
3749 /* Terminate the search in check_eliminable_occurrences at
3751 *recog_data
.operand_loc
[i
] = 0;
3755 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3756 *recog_data
.dup_loc
[i
]
3757 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3759 /* If any eliminable remain, they aren't eliminable anymore. */
3760 check_eliminable_occurrences (old_body
);
3762 /* Restore the old body. */
3763 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3764 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3765 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3766 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3768 /* Update all elimination pairs to reflect the status after the current
3769 insn. The changes we make were determined by the earlier call to
3770 elimination_effects. */
3772 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3774 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3775 ep
->can_eliminate
= 0;
3777 ep
->ref_outside_mem
= 0;
3783 /* Loop through all elimination pairs.
3784 Recalculate the number not at initial offset.
3786 Compute the maximum offset (minimum offset if the stack does not
3787 grow downward) for each elimination pair. */
3790 update_eliminable_offsets (void)
3792 struct elim_table
*ep
;
3794 num_not_at_initial_offset
= 0;
3795 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3797 ep
->previous_offset
= ep
->offset
;
3798 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3799 num_not_at_initial_offset
++;
3803 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3804 replacement we currently believe is valid, mark it as not eliminable if X
3805 modifies DEST in any way other than by adding a constant integer to it.
3807 If DEST is the frame pointer, we do nothing because we assume that
3808 all assignments to the hard frame pointer are nonlocal gotos and are being
3809 done at a time when they are valid and do not disturb anything else.
3810 Some machines want to eliminate a fake argument pointer with either the
3811 frame or stack pointer. Assignments to the hard frame pointer must not
3812 prevent this elimination.
3814 Called via note_stores from reload before starting its passes to scan
3815 the insns of the function. */
3818 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3822 /* A SUBREG of a hard register here is just changing its mode. We should
3823 not see a SUBREG of an eliminable hard register, but check just in
3825 if (GET_CODE (dest
) == SUBREG
)
3826 dest
= SUBREG_REG (dest
);
3828 if (dest
== hard_frame_pointer_rtx
)
3831 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3832 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3833 && (GET_CODE (x
) != SET
3834 || GET_CODE (SET_SRC (x
)) != PLUS
3835 || XEXP (SET_SRC (x
), 0) != dest
3836 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3838 reg_eliminate
[i
].can_eliminate_previous
3839 = reg_eliminate
[i
].can_eliminate
= 0;
3844 /* Verify that the initial elimination offsets did not change since the
3845 last call to set_initial_elim_offsets. This is used to catch cases
3846 where something illegal happened during reload_as_needed that could
3847 cause incorrect code to be generated if we did not check for it. */
3850 verify_initial_elim_offsets (void)
3854 if (!num_eliminable
)
3857 #ifdef ELIMINABLE_REGS
3859 struct elim_table
*ep
;
3861 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3863 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3864 if (t
!= ep
->initial_offset
)
3869 INITIAL_FRAME_POINTER_OFFSET (t
);
3870 if (t
!= reg_eliminate
[0].initial_offset
)
3877 /* Reset all offsets on eliminable registers to their initial values. */
3880 set_initial_elim_offsets (void)
3882 struct elim_table
*ep
= reg_eliminate
;
3884 #ifdef ELIMINABLE_REGS
3885 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3887 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3888 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3891 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3892 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3895 num_not_at_initial_offset
= 0;
3898 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3901 set_initial_eh_label_offset (rtx label
)
3903 set_label_offsets (label
, NULL_RTX
, 1);
3906 /* Initialize the known label offsets.
3907 Set a known offset for each forced label to be at the initial offset
3908 of each elimination. We do this because we assume that all
3909 computed jumps occur from a location where each elimination is
3910 at its initial offset.
3911 For all other labels, show that we don't know the offsets. */
3914 set_initial_label_offsets (void)
3917 memset (offsets_known_at
, 0, num_labels
);
3919 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3921 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3923 for (x
= nonlocal_goto_handler_labels
; x
; x
= XEXP (x
, 1))
3925 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3927 for_each_eh_label (set_initial_eh_label_offset
);
3930 /* Set all elimination offsets to the known values for the code label given
3934 set_offsets_for_label (rtx insn
)
3937 int label_nr
= CODE_LABEL_NUMBER (insn
);
3938 struct elim_table
*ep
;
3940 num_not_at_initial_offset
= 0;
3941 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3943 ep
->offset
= ep
->previous_offset
3944 = offsets_at
[label_nr
- first_label_num
][i
];
3945 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3946 num_not_at_initial_offset
++;
3950 /* See if anything that happened changes which eliminations are valid.
3951 For example, on the SPARC, whether or not the frame pointer can
3952 be eliminated can depend on what registers have been used. We need
3953 not check some conditions again (such as flag_omit_frame_pointer)
3954 since they can't have changed. */
3957 update_eliminables (HARD_REG_SET
*pset
)
3959 int previous_frame_pointer_needed
= frame_pointer_needed
;
3960 struct elim_table
*ep
;
3962 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3963 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3964 && targetm
.frame_pointer_required ())
3965 #ifdef ELIMINABLE_REGS
3966 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3969 ep
->can_eliminate
= 0;
3971 /* Look for the case where we have discovered that we can't replace
3972 register A with register B and that means that we will now be
3973 trying to replace register A with register C. This means we can
3974 no longer replace register C with register B and we need to disable
3975 such an elimination, if it exists. This occurs often with A == ap,
3976 B == sp, and C == fp. */
3978 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3980 struct elim_table
*op
;
3983 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3985 /* Find the current elimination for ep->from, if there is a
3987 for (op
= reg_eliminate
;
3988 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3989 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3995 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3997 for (op
= reg_eliminate
;
3998 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3999 if (op
->from
== new_to
&& op
->to
== ep
->to
)
4000 op
->can_eliminate
= 0;
4004 /* See if any registers that we thought we could eliminate the previous
4005 time are no longer eliminable. If so, something has changed and we
4006 must spill the register. Also, recompute the number of eliminable
4007 registers and see if the frame pointer is needed; it is if there is
4008 no elimination of the frame pointer that we can perform. */
4010 frame_pointer_needed
= 1;
4011 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4013 if (ep
->can_eliminate
4014 && ep
->from
== FRAME_POINTER_REGNUM
4015 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
4016 && (! SUPPORTS_STACK_ALIGNMENT
4017 || ! crtl
->stack_realign_needed
))
4018 frame_pointer_needed
= 0;
4020 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4022 ep
->can_eliminate_previous
= 0;
4023 SET_HARD_REG_BIT (*pset
, ep
->from
);
4028 /* If we didn't need a frame pointer last time, but we do now, spill
4029 the hard frame pointer. */
4030 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4031 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4034 /* Return true if X is used as the target register of an elimination. */
4037 elimination_target_reg_p (rtx x
)
4039 struct elim_table
*ep
;
4041 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4042 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4048 /* Initialize the table of registers to eliminate.
4049 Pre-condition: global flag frame_pointer_needed has been set before
4050 calling this function. */
4053 init_elim_table (void)
4055 struct elim_table
*ep
;
4056 #ifdef ELIMINABLE_REGS
4057 const struct elim_table_1
*ep1
;
4061 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4065 #ifdef ELIMINABLE_REGS
4066 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4067 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4069 ep
->from
= ep1
->from
;
4071 ep
->can_eliminate
= ep
->can_eliminate_previous
4072 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4073 && ! (ep
->to
== STACK_POINTER_REGNUM
4074 && frame_pointer_needed
4075 && (! SUPPORTS_STACK_ALIGNMENT
4076 || ! stack_realign_fp
)));
4079 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4080 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4081 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4082 = ! frame_pointer_needed
;
4085 /* Count the number of eliminable registers and build the FROM and TO
4086 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4087 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4088 We depend on this. */
4089 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4091 num_eliminable
+= ep
->can_eliminate
;
4092 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4093 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4097 /* Find all the pseudo registers that didn't get hard regs
4098 but do have known equivalent constants or memory slots.
4099 These include parameters (known equivalent to parameter slots)
4100 and cse'd or loop-moved constant memory addresses.
4102 Record constant equivalents in reg_equiv_constant
4103 so they will be substituted by find_reloads.
4104 Record memory equivalents in reg_mem_equiv so they can
4105 be substituted eventually by altering the REG-rtx's. */
4108 init_eliminable_invariants (rtx first
, bool do_subregs
)
4115 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4117 reg_max_ref_width
= NULL
;
4119 num_eliminable_invariants
= 0;
4121 first_label_num
= get_first_label_num ();
4122 num_labels
= max_label_num () - first_label_num
;
4124 /* Allocate the tables used to store offset information at labels. */
4125 offsets_known_at
= XNEWVEC (char, num_labels
);
4126 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4128 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4129 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4130 find largest such for each pseudo. FIRST is the head of the insn
4133 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4135 rtx set
= single_set (insn
);
4137 /* We may introduce USEs that we want to remove at the end, so
4138 we'll mark them with QImode. Make sure there are no
4139 previously-marked insns left by say regmove. */
4140 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4141 && GET_MODE (insn
) != VOIDmode
)
4142 PUT_MODE (insn
, VOIDmode
);
4144 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4145 scan_paradoxical_subregs (PATTERN (insn
));
4147 if (set
!= 0 && REG_P (SET_DEST (set
)))
4149 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4155 i
= REGNO (SET_DEST (set
));
4158 if (i
<= LAST_VIRTUAL_REGISTER
)
4161 /* If flag_pic and we have constant, verify it's legitimate. */
4163 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4165 /* It can happen that a REG_EQUIV note contains a MEM
4166 that is not a legitimate memory operand. As later
4167 stages of reload assume that all addresses found
4168 in the reg_equiv_* arrays were originally legitimate,
4169 we ignore such REG_EQUIV notes. */
4170 if (memory_operand (x
, VOIDmode
))
4172 /* Always unshare the equivalence, so we can
4173 substitute into this insn without touching the
4175 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4177 else if (function_invariant_p (x
))
4179 enum machine_mode mode
;
4181 mode
= GET_MODE (SET_DEST (set
));
4182 if (GET_CODE (x
) == PLUS
)
4184 /* This is PLUS of frame pointer and a constant,
4185 and might be shared. Unshare it. */
4186 reg_equiv_invariant (i
) = copy_rtx (x
);
4187 num_eliminable_invariants
++;
4189 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4191 reg_equiv_invariant (i
) = x
;
4192 num_eliminable_invariants
++;
4194 else if (targetm
.legitimate_constant_p (mode
, x
))
4195 reg_equiv_constant (i
) = x
;
4198 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4199 if (! reg_equiv_memory_loc (i
))
4200 reg_equiv_init (i
) = NULL_RTX
;
4205 reg_equiv_init (i
) = NULL_RTX
;
4210 reg_equiv_init (i
) = NULL_RTX
;
4215 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4216 if (reg_equiv_init (i
))
4218 fprintf (dump_file
, "init_insns for %u: ", i
);
4219 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4220 fprintf (dump_file
, "\n");
4224 /* Indicate that we no longer have known memory locations or constants.
4225 Free all data involved in tracking these. */
4228 free_reg_equiv (void)
4232 free (offsets_known_at
);
4235 offsets_known_at
= 0;
4237 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4238 if (reg_equiv_alt_mem_list (i
))
4239 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4240 vec_free (reg_equivs
);
4243 /* Kick all pseudos out of hard register REGNO.
4245 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4246 because we found we can't eliminate some register. In the case, no pseudos
4247 are allowed to be in the register, even if they are only in a block that
4248 doesn't require spill registers, unlike the case when we are spilling this
4249 hard reg to produce another spill register.
4251 Return nonzero if any pseudos needed to be kicked out. */
4254 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4260 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4261 df_set_regs_ever_live (regno
, true);
4264 /* Spill every pseudo reg that was allocated to this reg
4265 or to something that overlaps this reg. */
4267 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4268 if (reg_renumber
[i
] >= 0
4269 && (unsigned int) reg_renumber
[i
] <= regno
4270 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4271 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4274 /* After find_reload_regs has been run for all insn that need reloads,
4275 and/or spill_hard_regs was called, this function is used to actually
4276 spill pseudo registers and try to reallocate them. It also sets up the
4277 spill_regs array for use by choose_reload_regs. */
4280 finish_spills (int global
)
4282 struct insn_chain
*chain
;
4283 int something_changed
= 0;
4285 reg_set_iterator rsi
;
4287 /* Build the spill_regs array for the function. */
4288 /* If there are some registers still to eliminate and one of the spill regs
4289 wasn't ever used before, additional stack space may have to be
4290 allocated to store this register. Thus, we may have changed the offset
4291 between the stack and frame pointers, so mark that something has changed.
4293 One might think that we need only set VAL to 1 if this is a call-used
4294 register. However, the set of registers that must be saved by the
4295 prologue is not identical to the call-used set. For example, the
4296 register used by the call insn for the return PC is a call-used register,
4297 but must be saved by the prologue. */
4300 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4301 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4303 spill_reg_order
[i
] = n_spills
;
4304 spill_regs
[n_spills
++] = i
;
4305 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4306 something_changed
= 1;
4307 df_set_regs_ever_live (i
, true);
4310 spill_reg_order
[i
] = -1;
4312 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4313 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4315 /* Record the current hard register the pseudo is allocated to
4316 in pseudo_previous_regs so we avoid reallocating it to the
4317 same hard reg in a later pass. */
4318 gcc_assert (reg_renumber
[i
] >= 0);
4320 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4321 /* Mark it as no longer having a hard register home. */
4322 reg_renumber
[i
] = -1;
4323 if (ira_conflicts_p
)
4324 /* Inform IRA about the change. */
4325 ira_mark_allocation_change (i
);
4326 /* We will need to scan everything again. */
4327 something_changed
= 1;
4330 /* Retry global register allocation if possible. */
4331 if (global
&& ira_conflicts_p
)
4335 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4336 /* For every insn that needs reloads, set the registers used as spill
4337 regs in pseudo_forbidden_regs for every pseudo live across the
4339 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4341 EXECUTE_IF_SET_IN_REG_SET
4342 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4344 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4345 chain
->used_spill_regs
);
4347 EXECUTE_IF_SET_IN_REG_SET
4348 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4350 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4351 chain
->used_spill_regs
);
4355 /* Retry allocating the pseudos spilled in IRA and the
4356 reload. For each reg, merge the various reg sets that
4357 indicate which hard regs can't be used, and call
4358 ira_reassign_pseudos. */
4359 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4360 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4362 if (reg_renumber
[i
] < 0)
4363 temp_pseudo_reg_arr
[n
++] = i
;
4365 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4367 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4368 bad_spill_regs_global
,
4369 pseudo_forbidden_regs
, pseudo_previous_regs
,
4371 something_changed
= 1;
4373 /* Fix up the register information in the insn chain.
4374 This involves deleting those of the spilled pseudos which did not get
4375 a new hard register home from the live_{before,after} sets. */
4376 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4378 HARD_REG_SET used_by_pseudos
;
4379 HARD_REG_SET used_by_pseudos2
;
4381 if (! ira_conflicts_p
)
4383 /* Don't do it for IRA because IRA and the reload still can
4384 assign hard registers to the spilled pseudos on next
4385 reload iterations. */
4386 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4387 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4389 /* Mark any unallocated hard regs as available for spills. That
4390 makes inheritance work somewhat better. */
4391 if (chain
->need_reload
)
4393 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4394 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4395 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4397 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4398 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4399 /* Value of chain->used_spill_regs from previous iteration
4400 may be not included in the value calculated here because
4401 of possible removing caller-saves insns (see function
4402 delete_caller_save_insns. */
4403 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4404 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4408 CLEAR_REG_SET (&changed_allocation_pseudos
);
4409 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4410 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4412 int regno
= reg_renumber
[i
];
4413 if (reg_old_renumber
[i
] == regno
)
4416 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4418 alter_reg (i
, reg_old_renumber
[i
], false);
4419 reg_old_renumber
[i
] = regno
;
4423 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4425 fprintf (dump_file
, " Register %d now in %d.\n\n",
4426 i
, reg_renumber
[i
]);
4430 return something_changed
;
4433 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4436 scan_paradoxical_subregs (rtx x
)
4440 enum rtx_code code
= GET_CODE (x
);
4456 if (REG_P (SUBREG_REG (x
))
4457 && (GET_MODE_SIZE (GET_MODE (x
))
4458 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4460 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4461 = GET_MODE_SIZE (GET_MODE (x
));
4462 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4470 fmt
= GET_RTX_FORMAT (code
);
4471 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4474 scan_paradoxical_subregs (XEXP (x
, i
));
4475 else if (fmt
[i
] == 'E')
4478 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4479 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4484 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4485 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4486 and apply the corresponding narrowing subreg to *OTHER_PTR.
4487 Return true if the operands were changed, false otherwise. */
4490 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4492 rtx op
, inner
, other
, tem
;
4495 if (!paradoxical_subreg_p (op
))
4497 inner
= SUBREG_REG (op
);
4500 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4504 /* If the lowpart operation turned a hard register into a subreg,
4505 rather than simplifying it to another hard register, then the
4506 mode change cannot be properly represented. For example, OTHER
4507 might be valid in its current mode, but not in the new one. */
4508 if (GET_CODE (tem
) == SUBREG
4510 && HARD_REGISTER_P (other
))
4518 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4519 examine all of the reload insns between PREV and NEXT exclusive, and
4520 annotate all that may trap. */
4523 fixup_eh_region_note (rtx insn
, rtx prev
, rtx next
)
4525 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4528 if (!insn_could_throw_p (insn
))
4529 remove_note (insn
, note
);
4530 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4533 /* Reload pseudo-registers into hard regs around each insn as needed.
4534 Additional register load insns are output before the insn that needs it
4535 and perhaps store insns after insns that modify the reloaded pseudo reg.
4537 reg_last_reload_reg and reg_reloaded_contents keep track of
4538 which registers are already available in reload registers.
4539 We update these for the reloads that we perform,
4540 as the insns are scanned. */
4543 reload_as_needed (int live_known
)
4545 struct insn_chain
*chain
;
4546 #if defined (AUTO_INC_DEC)
4551 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4552 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4553 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4554 INIT_REG_SET (®_has_output_reload
);
4555 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4556 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4558 set_initial_elim_offsets ();
4560 /* Generate a marker insn that we will move around. */
4561 marker
= emit_note (NOTE_INSN_DELETED
);
4562 unlink_insn_chain (marker
, marker
);
4564 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4567 rtx insn
= chain
->insn
;
4568 rtx old_next
= NEXT_INSN (insn
);
4570 rtx old_prev
= PREV_INSN (insn
);
4573 /* If we pass a label, copy the offsets from the label information
4574 into the current offsets of each elimination. */
4576 set_offsets_for_label (insn
);
4578 else if (INSN_P (insn
))
4580 regset_head regs_to_forget
;
4581 INIT_REG_SET (®s_to_forget
);
4582 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4584 /* If this is a USE and CLOBBER of a MEM, ensure that any
4585 references to eliminable registers have been removed. */
4587 if ((GET_CODE (PATTERN (insn
)) == USE
4588 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4589 && MEM_P (XEXP (PATTERN (insn
), 0)))
4590 XEXP (XEXP (PATTERN (insn
), 0), 0)
4591 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4592 GET_MODE (XEXP (PATTERN (insn
), 0)),
4595 /* If we need to do register elimination processing, do so.
4596 This might delete the insn, in which case we are done. */
4597 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4599 eliminate_regs_in_insn (insn
, 1);
4602 update_eliminable_offsets ();
4603 CLEAR_REG_SET (®s_to_forget
);
4608 /* If need_elim is nonzero but need_reload is zero, one might think
4609 that we could simply set n_reloads to 0. However, find_reloads
4610 could have done some manipulation of the insn (such as swapping
4611 commutative operands), and these manipulations are lost during
4612 the first pass for every insn that needs register elimination.
4613 So the actions of find_reloads must be redone here. */
4615 if (! chain
->need_elim
&& ! chain
->need_reload
4616 && ! chain
->need_operand_change
)
4618 /* First find the pseudo regs that must be reloaded for this insn.
4619 This info is returned in the tables reload_... (see reload.h).
4620 Also modify the body of INSN by substituting RELOAD
4621 rtx's for those pseudo regs. */
4624 CLEAR_REG_SET (®_has_output_reload
);
4625 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4627 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4633 rtx next
= NEXT_INSN (insn
);
4636 /* ??? PREV can get deleted by reload inheritance.
4637 Work around this by emitting a marker note. */
4638 prev
= PREV_INSN (insn
);
4639 reorder_insns_nobb (marker
, marker
, prev
);
4641 /* Now compute which reload regs to reload them into. Perhaps
4642 reusing reload regs from previous insns, or else output
4643 load insns to reload them. Maybe output store insns too.
4644 Record the choices of reload reg in reload_reg_rtx. */
4645 choose_reload_regs (chain
);
4647 /* Generate the insns to reload operands into or out of
4648 their reload regs. */
4649 emit_reload_insns (chain
);
4651 /* Substitute the chosen reload regs from reload_reg_rtx
4652 into the insn's body (or perhaps into the bodies of other
4653 load and store insn that we just made for reloading
4654 and that we moved the structure into). */
4655 subst_reloads (insn
);
4657 prev
= PREV_INSN (marker
);
4658 unlink_insn_chain (marker
, marker
);
4660 /* Adjust the exception region notes for loads and stores. */
4661 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4662 fixup_eh_region_note (insn
, prev
, next
);
4664 /* Adjust the location of REG_ARGS_SIZE. */
4665 p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4668 remove_note (insn
, p
);
4669 fixup_args_size_notes (prev
, PREV_INSN (next
),
4670 INTVAL (XEXP (p
, 0)));
4673 /* If this was an ASM, make sure that all the reload insns
4674 we have generated are valid. If not, give an error
4676 if (asm_noperands (PATTERN (insn
)) >= 0)
4677 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4678 if (p
!= insn
&& INSN_P (p
)
4679 && GET_CODE (PATTERN (p
)) != USE
4680 && (recog_memoized (p
) < 0
4681 || (extract_insn (p
), ! constrain_operands (1))))
4683 error_for_asm (insn
,
4684 "%<asm%> operand requires "
4685 "impossible reload");
4690 if (num_eliminable
&& chain
->need_elim
)
4691 update_eliminable_offsets ();
4693 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4694 is no longer validly lying around to save a future reload.
4695 Note that this does not detect pseudos that were reloaded
4696 for this insn in order to be stored in
4697 (obeying register constraints). That is correct; such reload
4698 registers ARE still valid. */
4699 forget_marked_reloads (®s_to_forget
);
4700 CLEAR_REG_SET (®s_to_forget
);
4702 /* There may have been CLOBBER insns placed after INSN. So scan
4703 between INSN and NEXT and use them to forget old reloads. */
4704 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4705 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4706 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4709 /* Likewise for regs altered by auto-increment in this insn.
4710 REG_INC notes have been changed by reloading:
4711 find_reloads_address_1 records substitutions for them,
4712 which have been performed by subst_reloads above. */
4713 for (i
= n_reloads
- 1; i
>= 0; i
--)
4715 rtx in_reg
= rld
[i
].in_reg
;
4718 enum rtx_code code
= GET_CODE (in_reg
);
4719 /* PRE_INC / PRE_DEC will have the reload register ending up
4720 with the same value as the stack slot, but that doesn't
4721 hold true for POST_INC / POST_DEC. Either we have to
4722 convert the memory access to a true POST_INC / POST_DEC,
4723 or we can't use the reload register for inheritance. */
4724 if ((code
== POST_INC
|| code
== POST_DEC
)
4725 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4726 REGNO (rld
[i
].reg_rtx
))
4727 /* Make sure it is the inc/dec pseudo, and not
4728 some other (e.g. output operand) pseudo. */
4729 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4730 == REGNO (XEXP (in_reg
, 0))))
4733 rtx reload_reg
= rld
[i
].reg_rtx
;
4734 enum machine_mode mode
= GET_MODE (reload_reg
);
4738 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4740 /* We really want to ignore REG_INC notes here, so
4741 use PATTERN (p) as argument to reg_set_p . */
4742 if (reg_set_p (reload_reg
, PATTERN (p
)))
4744 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4750 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4752 validate_replace_rtx_group (reload_reg
,
4754 n
= verify_changes (0);
4756 /* We must also verify that the constraints
4757 are met after the replacement. Make sure
4758 extract_insn is only called for an insn
4759 where the replacements were found to be
4764 n
= constrain_operands (1);
4767 /* If the constraints were not met, then
4768 undo the replacement, else confirm it. */
4772 confirm_change_group ();
4778 add_reg_note (p
, REG_INC
, reload_reg
);
4779 /* Mark this as having an output reload so that the
4780 REG_INC processing code below won't invalidate
4781 the reload for inheritance. */
4782 SET_HARD_REG_BIT (reg_is_output_reload
,
4783 REGNO (reload_reg
));
4784 SET_REGNO_REG_SET (®_has_output_reload
,
4785 REGNO (XEXP (in_reg
, 0)));
4788 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4791 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4792 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4793 REGNO (rld
[i
].reg_rtx
))
4794 /* Make sure it is the inc/dec pseudo, and not
4795 some other (e.g. output operand) pseudo. */
4796 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4797 == REGNO (XEXP (in_reg
, 0))))
4799 SET_HARD_REG_BIT (reg_is_output_reload
,
4800 REGNO (rld
[i
].reg_rtx
));
4801 SET_REGNO_REG_SET (®_has_output_reload
,
4802 REGNO (XEXP (in_reg
, 0)));
4804 else if (code
== PRE_INC
|| code
== PRE_DEC
4805 || code
== POST_INC
|| code
== POST_DEC
)
4807 int in_regno
= REGNO (XEXP (in_reg
, 0));
4809 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4812 bool forget_p
= true;
4814 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4815 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4818 for (x
= old_prev
? NEXT_INSN (old_prev
) : insn
;
4821 if (x
== reg_reloaded_insn
[in_hard_regno
])
4827 /* If for some reasons, we didn't set up
4828 reg_last_reload_reg in this insn,
4829 invalidate inheritance from previous
4830 insns for the incremented/decremented
4831 register. Such registers will be not in
4832 reg_has_output_reload. Invalidate it
4833 also if the corresponding element in
4834 reg_reloaded_insn is also
4837 forget_old_reloads_1 (XEXP (in_reg
, 0),
4843 /* If a pseudo that got a hard register is auto-incremented,
4844 we must purge records of copying it into pseudos without
4846 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4847 if (REG_NOTE_KIND (x
) == REG_INC
)
4849 /* See if this pseudo reg was reloaded in this insn.
4850 If so, its last-reload info is still valid
4851 because it is based on this insn's reload. */
4852 for (i
= 0; i
< n_reloads
; i
++)
4853 if (rld
[i
].out
== XEXP (x
, 0))
4857 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4861 /* A reload reg's contents are unknown after a label. */
4863 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4865 /* Don't assume a reload reg is still good after a call insn
4866 if it is a call-used reg, or if it contains a value that will
4867 be partially clobbered by the call. */
4868 else if (CALL_P (insn
))
4870 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4871 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4873 /* If this is a call to a setjmp-type function, we must not
4874 reuse any reload reg contents across the call; that will
4875 just be clobbered by other uses of the register in later
4876 code, before the longjmp. */
4877 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4878 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4883 free (reg_last_reload_reg
);
4884 CLEAR_REG_SET (®_has_output_reload
);
4887 /* Discard all record of any value reloaded from X,
4888 or reloaded in X from someplace else;
4889 unless X is an output reload reg of the current insn.
4891 X may be a hard reg (the reload reg)
4892 or it may be a pseudo reg that was reloaded from.
4894 When DATA is non-NULL just mark the registers in regset
4895 to be forgotten later. */
4898 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4903 regset regs
= (regset
) data
;
4905 /* note_stores does give us subregs of hard regs,
4906 subreg_regno_offset requires a hard reg. */
4907 while (GET_CODE (x
) == SUBREG
)
4909 /* We ignore the subreg offset when calculating the regno,
4910 because we are using the entire underlying hard register
4920 if (regno
>= FIRST_PSEUDO_REGISTER
)
4926 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4927 /* Storing into a spilled-reg invalidates its contents.
4928 This can happen if a block-local pseudo is allocated to that reg
4929 and it wasn't spilled because this block's total need is 0.
4930 Then some insn might have an optional reload and use this reg. */
4932 for (i
= 0; i
< nr
; i
++)
4933 /* But don't do this if the reg actually serves as an output
4934 reload reg in the current instruction. */
4936 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4938 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4939 spill_reg_store
[regno
+ i
] = 0;
4945 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4948 /* Since value of X has changed,
4949 forget any value previously copied from it. */
4952 /* But don't forget a copy if this is the output reload
4953 that establishes the copy's validity. */
4955 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4956 reg_last_reload_reg
[regno
+ nr
] = 0;
4960 /* Forget the reloads marked in regset by previous function. */
4962 forget_marked_reloads (regset regs
)
4965 reg_set_iterator rsi
;
4966 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4968 if (reg
< FIRST_PSEUDO_REGISTER
4969 /* But don't do this if the reg actually serves as an output
4970 reload reg in the current instruction. */
4972 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4974 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4975 spill_reg_store
[reg
] = 0;
4978 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4979 reg_last_reload_reg
[reg
] = 0;
4983 /* The following HARD_REG_SETs indicate when each hard register is
4984 used for a reload of various parts of the current insn. */
4986 /* If reg is unavailable for all reloads. */
4987 static HARD_REG_SET reload_reg_unavailable
;
4988 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4989 static HARD_REG_SET reload_reg_used
;
4990 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4991 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4992 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4993 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4994 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4995 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4996 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4997 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4998 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4999 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5000 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5001 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5002 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5003 static HARD_REG_SET reload_reg_used_in_op_addr
;
5004 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5005 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5006 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5007 static HARD_REG_SET reload_reg_used_in_insn
;
5008 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5009 static HARD_REG_SET reload_reg_used_in_other_addr
;
5011 /* If reg is in use as a reload reg for any sort of reload. */
5012 static HARD_REG_SET reload_reg_used_at_all
;
5014 /* If reg is use as an inherited reload. We just mark the first register
5016 static HARD_REG_SET reload_reg_used_for_inherit
;
5018 /* Records which hard regs are used in any way, either as explicit use or
5019 by being allocated to a pseudo during any point of the current insn. */
5020 static HARD_REG_SET reg_used_in_insn
;
5022 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5023 TYPE. MODE is used to indicate how many consecutive regs are
5027 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5028 enum machine_mode mode
)
5033 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5036 case RELOAD_FOR_INPUT_ADDRESS
:
5037 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5040 case RELOAD_FOR_INPADDR_ADDRESS
:
5041 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5044 case RELOAD_FOR_OUTPUT_ADDRESS
:
5045 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5048 case RELOAD_FOR_OUTADDR_ADDRESS
:
5049 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5052 case RELOAD_FOR_OPERAND_ADDRESS
:
5053 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5056 case RELOAD_FOR_OPADDR_ADDR
:
5057 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5060 case RELOAD_FOR_OTHER_ADDRESS
:
5061 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5064 case RELOAD_FOR_INPUT
:
5065 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5068 case RELOAD_FOR_OUTPUT
:
5069 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5072 case RELOAD_FOR_INSN
:
5073 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5077 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5080 /* Similarly, but show REGNO is no longer in use for a reload. */
5083 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5084 enum reload_type type
, enum machine_mode mode
)
5086 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5087 unsigned int start_regno
, end_regno
, r
;
5089 /* A complication is that for some reload types, inheritance might
5090 allow multiple reloads of the same types to share a reload register.
5091 We set check_opnum if we have to check only reloads with the same
5092 operand number, and check_any if we have to check all reloads. */
5093 int check_opnum
= 0;
5095 HARD_REG_SET
*used_in_set
;
5100 used_in_set
= &reload_reg_used
;
5103 case RELOAD_FOR_INPUT_ADDRESS
:
5104 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5107 case RELOAD_FOR_INPADDR_ADDRESS
:
5109 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5112 case RELOAD_FOR_OUTPUT_ADDRESS
:
5113 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5116 case RELOAD_FOR_OUTADDR_ADDRESS
:
5118 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5121 case RELOAD_FOR_OPERAND_ADDRESS
:
5122 used_in_set
= &reload_reg_used_in_op_addr
;
5125 case RELOAD_FOR_OPADDR_ADDR
:
5127 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5130 case RELOAD_FOR_OTHER_ADDRESS
:
5131 used_in_set
= &reload_reg_used_in_other_addr
;
5135 case RELOAD_FOR_INPUT
:
5136 used_in_set
= &reload_reg_used_in_input
[opnum
];
5139 case RELOAD_FOR_OUTPUT
:
5140 used_in_set
= &reload_reg_used_in_output
[opnum
];
5143 case RELOAD_FOR_INSN
:
5144 used_in_set
= &reload_reg_used_in_insn
;
5149 /* We resolve conflicts with remaining reloads of the same type by
5150 excluding the intervals of reload registers by them from the
5151 interval of freed reload registers. Since we only keep track of
5152 one set of interval bounds, we might have to exclude somewhat
5153 more than what would be necessary if we used a HARD_REG_SET here.
5154 But this should only happen very infrequently, so there should
5155 be no reason to worry about it. */
5157 start_regno
= regno
;
5158 end_regno
= regno
+ nregs
;
5159 if (check_opnum
|| check_any
)
5161 for (i
= n_reloads
- 1; i
>= 0; i
--)
5163 if (rld
[i
].when_needed
== type
5164 && (check_any
|| rld
[i
].opnum
== opnum
)
5167 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5168 unsigned int conflict_end
5169 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5171 /* If there is an overlap with the first to-be-freed register,
5172 adjust the interval start. */
5173 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5174 start_regno
= conflict_end
;
5175 /* Otherwise, if there is a conflict with one of the other
5176 to-be-freed registers, adjust the interval end. */
5177 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5178 end_regno
= conflict_start
;
5183 for (r
= start_regno
; r
< end_regno
; r
++)
5184 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5187 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5188 specified by OPNUM and TYPE. */
5191 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5195 /* In use for a RELOAD_OTHER means it's not available for anything. */
5196 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5197 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5203 /* In use for anything means we can't use it for RELOAD_OTHER. */
5204 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5205 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5206 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5207 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5210 for (i
= 0; i
< reload_n_operands
; i
++)
5211 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5212 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5213 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5214 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5215 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5216 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5221 case RELOAD_FOR_INPUT
:
5222 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5223 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5226 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5229 /* If it is used for some other input, can't use it. */
5230 for (i
= 0; i
< reload_n_operands
; i
++)
5231 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5234 /* If it is used in a later operand's address, can't use it. */
5235 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5236 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5237 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5242 case RELOAD_FOR_INPUT_ADDRESS
:
5243 /* Can't use a register if it is used for an input address for this
5244 operand or used as an input in an earlier one. */
5245 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5246 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5249 for (i
= 0; i
< opnum
; i
++)
5250 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5255 case RELOAD_FOR_INPADDR_ADDRESS
:
5256 /* Can't use a register if it is used for an input address
5257 for this operand or used as an input in an earlier
5259 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5262 for (i
= 0; i
< opnum
; i
++)
5263 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5268 case RELOAD_FOR_OUTPUT_ADDRESS
:
5269 /* Can't use a register if it is used for an output address for this
5270 operand or used as an output in this or a later operand. Note
5271 that multiple output operands are emitted in reverse order, so
5272 the conflicting ones are those with lower indices. */
5273 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5276 for (i
= 0; i
<= opnum
; i
++)
5277 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5282 case RELOAD_FOR_OUTADDR_ADDRESS
:
5283 /* Can't use a register if it is used for an output address
5284 for this operand or used as an output in this or a
5285 later operand. Note that multiple output operands are
5286 emitted in reverse order, so the conflicting ones are
5287 those with lower indices. */
5288 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5291 for (i
= 0; i
<= opnum
; i
++)
5292 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5297 case RELOAD_FOR_OPERAND_ADDRESS
:
5298 for (i
= 0; i
< reload_n_operands
; i
++)
5299 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5302 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5303 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5305 case RELOAD_FOR_OPADDR_ADDR
:
5306 for (i
= 0; i
< reload_n_operands
; i
++)
5307 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5310 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5312 case RELOAD_FOR_OUTPUT
:
5313 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5314 outputs, or an operand address for this or an earlier output.
5315 Note that multiple output operands are emitted in reverse order,
5316 so the conflicting ones are those with higher indices. */
5317 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5320 for (i
= 0; i
< reload_n_operands
; i
++)
5321 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5324 for (i
= opnum
; i
< reload_n_operands
; i
++)
5325 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5326 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5331 case RELOAD_FOR_INSN
:
5332 for (i
= 0; i
< reload_n_operands
; i
++)
5333 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5334 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5337 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5338 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5340 case RELOAD_FOR_OTHER_ADDRESS
:
5341 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5348 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5349 the number RELOADNUM, is still available in REGNO at the end of the insn.
5351 We can assume that the reload reg was already tested for availability
5352 at the time it is needed, and we should not check this again,
5353 in case the reg has already been marked in use. */
5356 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5358 int opnum
= rld
[reloadnum
].opnum
;
5359 enum reload_type type
= rld
[reloadnum
].when_needed
;
5362 /* See if there is a reload with the same type for this operand, using
5363 the same register. This case is not handled by the code below. */
5364 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5369 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5371 reg
= rld
[i
].reg_rtx
;
5372 if (reg
== NULL_RTX
)
5374 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5375 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5382 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5383 its value must reach the end. */
5386 /* If this use is for part of the insn,
5387 its value reaches if no subsequent part uses the same register.
5388 Just like the above function, don't try to do this with lots
5391 case RELOAD_FOR_OTHER_ADDRESS
:
5392 /* Here we check for everything else, since these don't conflict
5393 with anything else and everything comes later. */
5395 for (i
= 0; i
< reload_n_operands
; i
++)
5396 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5397 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5398 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5399 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5400 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5401 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5404 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5405 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5406 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5407 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5409 case RELOAD_FOR_INPUT_ADDRESS
:
5410 case RELOAD_FOR_INPADDR_ADDRESS
:
5411 /* Similar, except that we check only for this and subsequent inputs
5412 and the address of only subsequent inputs and we do not need
5413 to check for RELOAD_OTHER objects since they are known not to
5416 for (i
= opnum
; i
< reload_n_operands
; i
++)
5417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5420 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5421 could be killed if the register is also used by reload with type
5422 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5423 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5424 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5427 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5428 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5429 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5432 for (i
= 0; i
< reload_n_operands
; i
++)
5433 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5434 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5435 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5438 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5441 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5442 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5443 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5445 case RELOAD_FOR_INPUT
:
5446 /* Similar to input address, except we start at the next operand for
5447 both input and input address and we do not check for
5448 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5451 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5452 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5453 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5454 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5457 /* ... fall through ... */
5459 case RELOAD_FOR_OPERAND_ADDRESS
:
5460 /* Check outputs and their addresses. */
5462 for (i
= 0; i
< reload_n_operands
; i
++)
5463 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5464 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5465 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5468 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5470 case RELOAD_FOR_OPADDR_ADDR
:
5471 for (i
= 0; i
< reload_n_operands
; i
++)
5472 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5473 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5474 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5477 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5478 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5479 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5481 case RELOAD_FOR_INSN
:
5482 /* These conflict with other outputs with RELOAD_OTHER. So
5483 we need only check for output addresses. */
5485 opnum
= reload_n_operands
;
5487 /* ... fall through ... */
5489 case RELOAD_FOR_OUTPUT
:
5490 case RELOAD_FOR_OUTPUT_ADDRESS
:
5491 case RELOAD_FOR_OUTADDR_ADDRESS
:
5492 /* We already know these can't conflict with a later output. So the
5493 only thing to check are later output addresses.
5494 Note that multiple output operands are emitted in reverse order,
5495 so the conflicting ones are those with lower indices. */
5496 for (i
= 0; i
< opnum
; i
++)
5497 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5498 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5501 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5502 could be killed if the register is also used by reload with type
5503 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5504 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5505 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5515 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5516 every register in REG. */
5519 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5523 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5524 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5530 /* Returns whether R1 and R2 are uniquely chained: the value of one
5531 is used by the other, and that value is not used by any other
5532 reload for this insn. This is used to partially undo the decision
5533 made in find_reloads when in the case of multiple
5534 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5535 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5536 reloads. This code tries to avoid the conflict created by that
5537 change. It might be cleaner to explicitly keep track of which
5538 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5539 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5540 this after the fact. */
5542 reloads_unique_chain_p (int r1
, int r2
)
5546 /* We only check input reloads. */
5547 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5550 /* Avoid anything with output reloads. */
5551 if (rld
[r1
].out
|| rld
[r2
].out
)
5554 /* "chained" means one reload is a component of the other reload,
5555 not the same as the other reload. */
5556 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5557 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5558 || rld
[r1
].optional
|| rld
[r2
].optional
5559 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5560 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5563 for (i
= 0; i
< n_reloads
; i
++)
5564 /* Look for input reloads that aren't our two */
5565 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5567 /* If our reload is mentioned at all, it isn't a simple chain. */
5568 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5574 /* The recursive function change all occurrences of WHAT in *WHERE
5577 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5586 if (*where
== what
|| rtx_equal_p (*where
, what
))
5588 /* Record the location of the changed rtx. */
5589 substitute_stack
.safe_push (where
);
5594 code
= GET_CODE (*where
);
5595 fmt
= GET_RTX_FORMAT (code
);
5596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5602 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5603 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5605 else if (fmt
[i
] == 'e')
5606 substitute (&XEXP (*where
, i
), what
, repl
);
5610 /* The function returns TRUE if chain of reload R1 and R2 (in any
5611 order) can be evaluated without usage of intermediate register for
5612 the reload containing another reload. It is important to see
5613 gen_reload to understand what the function is trying to do. As an
5614 example, let us have reload chain
5617 r1: <something> + const
5619 and reload R2 got reload reg HR. The function returns true if
5620 there is a correct insn HR = HR + <something>. Otherwise,
5621 gen_reload will use intermediate register (and this is the reload
5622 reg for R1) to reload <something>.
5624 We need this function to find a conflict for chain reloads. In our
5625 example, if HR = HR + <something> is incorrect insn, then we cannot
5626 use HR as a reload register for R2. If we do use it then we get a
5635 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5637 /* Assume other cases in gen_reload are not possible for
5638 chain reloads or do need an intermediate hard registers. */
5642 rtx last
= get_last_insn ();
5644 /* Make r2 a component of r1. */
5645 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5651 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5652 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5653 gcc_assert (regno
>= 0);
5654 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5656 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5658 /* If IN is a paradoxical SUBREG, remove it and try to put the
5659 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5660 strip_paradoxical_subreg (&in
, &out
);
5662 if (GET_CODE (in
) == PLUS
5663 && (REG_P (XEXP (in
, 0))
5664 || GET_CODE (XEXP (in
, 0)) == SUBREG
5665 || MEM_P (XEXP (in
, 0)))
5666 && (REG_P (XEXP (in
, 1))
5667 || GET_CODE (XEXP (in
, 1)) == SUBREG
5668 || CONSTANT_P (XEXP (in
, 1))
5669 || MEM_P (XEXP (in
, 1))))
5671 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
5672 code
= recog_memoized (insn
);
5677 extract_insn (insn
);
5678 /* We want constrain operands to treat this insn strictly in
5679 its validity determination, i.e., the way it would after
5680 reload has completed. */
5681 result
= constrain_operands (1);
5684 delete_insns_since (last
);
5687 /* Restore the original value at each changed address within R1. */
5688 while (!substitute_stack
.is_empty ())
5690 rtx
*where
= substitute_stack
.pop ();
5691 *where
= rld
[r2
].in
;
5697 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5700 This function uses the same algorithm as reload_reg_free_p above. */
5703 reloads_conflict (int r1
, int r2
)
5705 enum reload_type r1_type
= rld
[r1
].when_needed
;
5706 enum reload_type r2_type
= rld
[r2
].when_needed
;
5707 int r1_opnum
= rld
[r1
].opnum
;
5708 int r2_opnum
= rld
[r2
].opnum
;
5710 /* RELOAD_OTHER conflicts with everything. */
5711 if (r2_type
== RELOAD_OTHER
)
5714 /* Otherwise, check conflicts differently for each type. */
5718 case RELOAD_FOR_INPUT
:
5719 return (r2_type
== RELOAD_FOR_INSN
5720 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5721 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5722 || r2_type
== RELOAD_FOR_INPUT
5723 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5724 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5725 && r2_opnum
> r1_opnum
));
5727 case RELOAD_FOR_INPUT_ADDRESS
:
5728 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5729 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5731 case RELOAD_FOR_INPADDR_ADDRESS
:
5732 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5733 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5735 case RELOAD_FOR_OUTPUT_ADDRESS
:
5736 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5737 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5739 case RELOAD_FOR_OUTADDR_ADDRESS
:
5740 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5741 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5743 case RELOAD_FOR_OPERAND_ADDRESS
:
5744 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5745 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5746 && (!reloads_unique_chain_p (r1
, r2
)
5747 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5749 case RELOAD_FOR_OPADDR_ADDR
:
5750 return (r2_type
== RELOAD_FOR_INPUT
5751 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5753 case RELOAD_FOR_OUTPUT
:
5754 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5755 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5756 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5757 && r2_opnum
>= r1_opnum
));
5759 case RELOAD_FOR_INSN
:
5760 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5761 || r2_type
== RELOAD_FOR_INSN
5762 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5764 case RELOAD_FOR_OTHER_ADDRESS
:
5765 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5775 /* Indexed by reload number, 1 if incoming value
5776 inherited from previous insns. */
5777 static char reload_inherited
[MAX_RELOADS
];
5779 /* For an inherited reload, this is the insn the reload was inherited from,
5780 if we know it. Otherwise, this is 0. */
5781 static rtx reload_inheritance_insn
[MAX_RELOADS
];
5783 /* If nonzero, this is a place to get the value of the reload,
5784 rather than using reload_in. */
5785 static rtx reload_override_in
[MAX_RELOADS
];
5787 /* For each reload, the hard register number of the register used,
5788 or -1 if we did not need a register for this reload. */
5789 static int reload_spill_index
[MAX_RELOADS
];
5791 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5792 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5794 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5795 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5797 /* Subroutine of free_for_value_p, used to check a single register.
5798 START_REGNO is the starting regno of the full reload register
5799 (possibly comprising multiple hard registers) that we are considering. */
5802 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5803 enum reload_type type
, rtx value
, rtx out
,
5804 int reloadnum
, int ignore_address_reloads
)
5807 /* Set if we see an input reload that must not share its reload register
5808 with any new earlyclobber, but might otherwise share the reload
5809 register with an output or input-output reload. */
5810 int check_earlyclobber
= 0;
5814 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5817 if (out
== const0_rtx
)
5823 /* We use some pseudo 'time' value to check if the lifetimes of the
5824 new register use would overlap with the one of a previous reload
5825 that is not read-only or uses a different value.
5826 The 'time' used doesn't have to be linear in any shape or form, just
5828 Some reload types use different 'buckets' for each operand.
5829 So there are MAX_RECOG_OPERANDS different time values for each
5831 We compute TIME1 as the time when the register for the prospective
5832 new reload ceases to be live, and TIME2 for each existing
5833 reload as the time when that the reload register of that reload
5835 Where there is little to be gained by exact lifetime calculations,
5836 we just make conservative assumptions, i.e. a longer lifetime;
5837 this is done in the 'default:' cases. */
5840 case RELOAD_FOR_OTHER_ADDRESS
:
5841 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5842 time1
= copy
? 0 : 1;
5845 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5847 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5848 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5849 respectively, to the time values for these, we get distinct time
5850 values. To get distinct time values for each operand, we have to
5851 multiply opnum by at least three. We round that up to four because
5852 multiply by four is often cheaper. */
5853 case RELOAD_FOR_INPADDR_ADDRESS
:
5854 time1
= opnum
* 4 + 2;
5856 case RELOAD_FOR_INPUT_ADDRESS
:
5857 time1
= opnum
* 4 + 3;
5859 case RELOAD_FOR_INPUT
:
5860 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5861 executes (inclusive). */
5862 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5864 case RELOAD_FOR_OPADDR_ADDR
:
5866 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5867 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5869 case RELOAD_FOR_OPERAND_ADDRESS
:
5870 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5872 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5874 case RELOAD_FOR_OUTADDR_ADDRESS
:
5875 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5877 case RELOAD_FOR_OUTPUT_ADDRESS
:
5878 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5881 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5884 for (i
= 0; i
< n_reloads
; i
++)
5886 rtx reg
= rld
[i
].reg_rtx
;
5887 if (reg
&& REG_P (reg
)
5888 && ((unsigned) regno
- true_regnum (reg
)
5889 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5892 rtx other_input
= rld
[i
].in
;
5894 /* If the other reload loads the same input value, that
5895 will not cause a conflict only if it's loading it into
5896 the same register. */
5897 if (true_regnum (reg
) != start_regno
)
5898 other_input
= NULL_RTX
;
5899 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5900 || rld
[i
].out
|| out
)
5903 switch (rld
[i
].when_needed
)
5905 case RELOAD_FOR_OTHER_ADDRESS
:
5908 case RELOAD_FOR_INPADDR_ADDRESS
:
5909 /* find_reloads makes sure that a
5910 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5911 by at most one - the first -
5912 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5913 address reload is inherited, the address address reload
5914 goes away, so we can ignore this conflict. */
5915 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5916 && ignore_address_reloads
5917 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5918 Then the address address is still needed to store
5919 back the new address. */
5920 && ! rld
[reloadnum
].out
)
5922 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5923 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5925 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5926 && ignore_address_reloads
5927 /* Unless we are reloading an auto_inc expression. */
5928 && ! rld
[reloadnum
].out
)
5930 time2
= rld
[i
].opnum
* 4 + 2;
5932 case RELOAD_FOR_INPUT_ADDRESS
:
5933 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5934 && ignore_address_reloads
5935 && ! rld
[reloadnum
].out
)
5937 time2
= rld
[i
].opnum
* 4 + 3;
5939 case RELOAD_FOR_INPUT
:
5940 time2
= rld
[i
].opnum
* 4 + 4;
5941 check_earlyclobber
= 1;
5943 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5944 == MAX_RECOG_OPERAND * 4 */
5945 case RELOAD_FOR_OPADDR_ADDR
:
5946 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5947 && ignore_address_reloads
5948 && ! rld
[reloadnum
].out
)
5950 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5952 case RELOAD_FOR_OPERAND_ADDRESS
:
5953 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5954 check_earlyclobber
= 1;
5956 case RELOAD_FOR_INSN
:
5957 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5959 case RELOAD_FOR_OUTPUT
:
5960 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5961 instruction is executed. */
5962 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5964 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5965 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5967 case RELOAD_FOR_OUTADDR_ADDRESS
:
5968 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5969 && ignore_address_reloads
5970 && ! rld
[reloadnum
].out
)
5972 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5974 case RELOAD_FOR_OUTPUT_ADDRESS
:
5975 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5978 /* If there is no conflict in the input part, handle this
5979 like an output reload. */
5980 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5982 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5983 /* Earlyclobbered outputs must conflict with inputs. */
5984 if (earlyclobber_operand_p (rld
[i
].out
))
5985 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5990 /* RELOAD_OTHER might be live beyond instruction execution,
5991 but this is not obvious when we set time2 = 1. So check
5992 here if there might be a problem with the new reload
5993 clobbering the register used by the RELOAD_OTHER. */
6001 && (! rld
[i
].in
|| rld
[i
].out
6002 || ! rtx_equal_p (other_input
, value
)))
6003 || (out
&& rld
[reloadnum
].out_reg
6004 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6010 /* Earlyclobbered outputs must conflict with inputs. */
6011 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6017 /* Return 1 if the value in reload reg REGNO, as used by a reload
6018 needed for the part of the insn specified by OPNUM and TYPE,
6019 may be used to load VALUE into it.
6021 MODE is the mode in which the register is used, this is needed to
6022 determine how many hard regs to test.
6024 Other read-only reloads with the same value do not conflict
6025 unless OUT is nonzero and these other reloads have to live while
6026 output reloads live.
6027 If OUT is CONST0_RTX, this is a special case: it means that the
6028 test should not be for using register REGNO as reload register, but
6029 for copying from register REGNO into the reload register.
6031 RELOADNUM is the number of the reload we want to load this value for;
6032 a reload does not conflict with itself.
6034 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6035 reloads that load an address for the very reload we are considering.
6037 The caller has to make sure that there is no conflict with the return
6041 free_for_value_p (int regno
, enum machine_mode mode
, int opnum
,
6042 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6043 int ignore_address_reloads
)
6045 int nregs
= hard_regno_nregs
[regno
][mode
];
6047 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6048 value
, out
, reloadnum
,
6049 ignore_address_reloads
))
6054 /* Return nonzero if the rtx X is invariant over the current function. */
6055 /* ??? Actually, the places where we use this expect exactly what is
6056 tested here, and not everything that is function invariant. In
6057 particular, the frame pointer and arg pointer are special cased;
6058 pic_offset_table_rtx is not, and we must not spill these things to
6062 function_invariant_p (const_rtx x
)
6066 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6068 if (GET_CODE (x
) == PLUS
6069 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6070 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6075 /* Determine whether the reload reg X overlaps any rtx'es used for
6076 overriding inheritance. Return nonzero if so. */
6079 conflicts_with_override (rtx x
)
6082 for (i
= 0; i
< n_reloads
; i
++)
6083 if (reload_override_in
[i
]
6084 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6089 /* Give an error message saying we failed to find a reload for INSN,
6090 and clear out reload R. */
6092 failed_reload (rtx insn
, int r
)
6094 if (asm_noperands (PATTERN (insn
)) < 0)
6095 /* It's the compiler's fault. */
6096 fatal_insn ("could not find a spill register", insn
);
6098 /* It's the user's fault; the operand's mode and constraint
6099 don't match. Disable this reload so we don't crash in final. */
6100 error_for_asm (insn
,
6101 "%<asm%> operand constraint incompatible with operand size");
6105 rld
[r
].optional
= 1;
6106 rld
[r
].secondary_p
= 1;
6109 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6110 for reload R. If it's valid, get an rtx for it. Return nonzero if
6113 set_reload_reg (int i
, int r
)
6115 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6117 int regno ATTRIBUTE_UNUSED
;
6118 rtx reg
= spill_reg_rtx
[i
];
6120 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6121 spill_reg_rtx
[i
] = reg
6122 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6124 regno
= true_regnum (reg
);
6126 /* Detect when the reload reg can't hold the reload mode.
6127 This used to be one `if', but Sequent compiler can't handle that. */
6128 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6130 enum machine_mode test_mode
= VOIDmode
;
6132 test_mode
= GET_MODE (rld
[r
].in
);
6133 /* If rld[r].in has VOIDmode, it means we will load it
6134 in whatever mode the reload reg has: to wit, rld[r].mode.
6135 We have already tested that for validity. */
6136 /* Aside from that, we need to test that the expressions
6137 to reload from or into have modes which are valid for this
6138 reload register. Otherwise the reload insns would be invalid. */
6139 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6140 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6141 if (! (rld
[r
].out
!= 0
6142 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6144 /* The reg is OK. */
6147 /* Mark as in use for this insn the reload regs we use
6149 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6150 rld
[r
].when_needed
, rld
[r
].mode
);
6152 rld
[r
].reg_rtx
= reg
;
6153 reload_spill_index
[r
] = spill_regs
[i
];
6160 /* Find a spill register to use as a reload register for reload R.
6161 LAST_RELOAD is nonzero if this is the last reload for the insn being
6164 Set rld[R].reg_rtx to the register allocated.
6166 We return 1 if successful, or 0 if we couldn't find a spill reg and
6167 we didn't change anything. */
6170 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6175 /* If we put this reload ahead, thinking it is a group,
6176 then insist on finding a group. Otherwise we can grab a
6177 reg that some other reload needs.
6178 (That can happen when we have a 68000 DATA_OR_FP_REG
6179 which is a group of data regs or one fp reg.)
6180 We need not be so restrictive if there are no more reloads
6183 ??? Really it would be nicer to have smarter handling
6184 for that kind of reg class, where a problem like this is normal.
6185 Perhaps those classes should be avoided for reloading
6186 by use of more alternatives. */
6188 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6190 /* If we want a single register and haven't yet found one,
6191 take any reg in the right class and not in use.
6192 If we want a consecutive group, here is where we look for it.
6194 We use three passes so we can first look for reload regs to
6195 reuse, which are already in use for other reloads in this insn,
6196 and only then use additional registers which are not "bad", then
6197 finally any register.
6199 I think that maximizing reuse is needed to make sure we don't
6200 run out of reload regs. Suppose we have three reloads, and
6201 reloads A and B can share regs. These need two regs.
6202 Suppose A and B are given different regs.
6203 That leaves none for C. */
6204 for (pass
= 0; pass
< 3; pass
++)
6206 /* I is the index in spill_regs.
6207 We advance it round-robin between insns to use all spill regs
6208 equally, so that inherited reloads have a chance
6209 of leapfrogging each other. */
6213 for (count
= 0; count
< n_spills
; count
++)
6215 int rclass
= (int) rld
[r
].rclass
;
6221 regnum
= spill_regs
[i
];
6223 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6226 /* We check reload_reg_used to make sure we
6227 don't clobber the return register. */
6228 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6229 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6230 rld
[r
].when_needed
, rld
[r
].in
,
6232 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6233 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6234 /* Look first for regs to share, then for unshared. But
6235 don't share regs used for inherited reloads; they are
6236 the ones we want to preserve. */
6238 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6240 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6243 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6245 /* During the second pass we want to avoid reload registers
6246 which are "bad" for this reload. */
6248 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6251 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6252 (on 68000) got us two FP regs. If NR is 1,
6253 we would reject both of them. */
6256 /* If we need only one reg, we have already won. */
6259 /* But reject a single reg if we demand a group. */
6264 /* Otherwise check that as many consecutive regs as we need
6265 are available here. */
6268 int regno
= regnum
+ nr
- 1;
6269 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6270 && spill_reg_order
[regno
] >= 0
6271 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6272 rld
[r
].when_needed
)))
6281 /* If we found something on the current pass, omit later passes. */
6282 if (count
< n_spills
)
6286 /* We should have found a spill register by now. */
6287 if (count
>= n_spills
)
6290 /* I is the index in SPILL_REG_RTX of the reload register we are to
6291 allocate. Get an rtx for it and find its register number. */
6293 return set_reload_reg (i
, r
);
6296 /* Initialize all the tables needed to allocate reload registers.
6297 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6298 is the array we use to restore the reg_rtx field for every reload. */
6301 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6305 for (i
= 0; i
< n_reloads
; i
++)
6306 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6308 memset (reload_inherited
, 0, MAX_RELOADS
);
6309 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6310 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6312 CLEAR_HARD_REG_SET (reload_reg_used
);
6313 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6314 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6315 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6316 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6317 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6319 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6322 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6323 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6324 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6325 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6326 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6327 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6330 for (i
= 0; i
< reload_n_operands
; i
++)
6332 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6333 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6334 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6335 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6336 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6337 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6340 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6342 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6344 for (i
= 0; i
< n_reloads
; i
++)
6345 /* If we have already decided to use a certain register,
6346 don't use it in another way. */
6348 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6349 rld
[i
].when_needed
, rld
[i
].mode
);
6352 #ifdef SECONDARY_MEMORY_NEEDED
6353 /* If X is not a subreg, return it unmodified. If it is a subreg,
6354 look up whether we made a replacement for the SUBREG_REG. Return
6355 either the replacement or the SUBREG_REG. */
6358 replaced_subreg (rtx x
)
6360 if (GET_CODE (x
) == SUBREG
)
6361 return find_replacement (&SUBREG_REG (x
));
6366 /* Assign hard reg targets for the pseudo-registers we must reload
6367 into hard regs for this insn.
6368 Also output the instructions to copy them in and out of the hard regs.
6370 For machines with register classes, we are responsible for
6371 finding a reload reg in the proper class. */
6374 choose_reload_regs (struct insn_chain
*chain
)
6376 rtx insn
= chain
->insn
;
6378 unsigned int max_group_size
= 1;
6379 enum reg_class group_class
= NO_REGS
;
6380 int pass
, win
, inheritance
;
6382 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6384 /* In order to be certain of getting the registers we need,
6385 we must sort the reloads into order of increasing register class.
6386 Then our grabbing of reload registers will parallel the process
6387 that provided the reload registers.
6389 Also note whether any of the reloads wants a consecutive group of regs.
6390 If so, record the maximum size of the group desired and what
6391 register class contains all the groups needed by this insn. */
6393 for (j
= 0; j
< n_reloads
; j
++)
6395 reload_order
[j
] = j
;
6396 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6398 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6399 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6400 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6403 reload_spill_index
[j
] = -1;
6405 if (rld
[j
].nregs
> 1)
6407 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6409 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6412 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6416 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6418 /* If -O, try first with inheritance, then turning it off.
6419 If not -O, don't do inheritance.
6420 Using inheritance when not optimizing leads to paradoxes
6421 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6422 because one side of the comparison might be inherited. */
6424 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6426 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6428 /* Process the reloads in order of preference just found.
6429 Beyond this point, subregs can be found in reload_reg_rtx.
6431 This used to look for an existing reloaded home for all of the
6432 reloads, and only then perform any new reloads. But that could lose
6433 if the reloads were done out of reg-class order because a later
6434 reload with a looser constraint might have an old home in a register
6435 needed by an earlier reload with a tighter constraint.
6437 To solve this, we make two passes over the reloads, in the order
6438 described above. In the first pass we try to inherit a reload
6439 from a previous insn. If there is a later reload that needs a
6440 class that is a proper subset of the class being processed, we must
6441 also allocate a spill register during the first pass.
6443 Then make a second pass over the reloads to allocate any reloads
6444 that haven't been given registers yet. */
6446 for (j
= 0; j
< n_reloads
; j
++)
6448 int r
= reload_order
[j
];
6449 rtx search_equiv
= NULL_RTX
;
6451 /* Ignore reloads that got marked inoperative. */
6452 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6453 && ! rld
[r
].secondary_p
)
6456 /* If find_reloads chose to use reload_in or reload_out as a reload
6457 register, we don't need to chose one. Otherwise, try even if it
6458 found one since we might save an insn if we find the value lying
6460 Try also when reload_in is a pseudo without a hard reg. */
6461 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6462 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6463 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6464 && !MEM_P (rld
[r
].in
)
6465 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6468 #if 0 /* No longer needed for correct operation.
6469 It might give better code, or might not; worth an experiment? */
6470 /* If this is an optional reload, we can't inherit from earlier insns
6471 until we are sure that any non-optional reloads have been allocated.
6472 The following code takes advantage of the fact that optional reloads
6473 are at the end of reload_order. */
6474 if (rld
[r
].optional
!= 0)
6475 for (i
= 0; i
< j
; i
++)
6476 if ((rld
[reload_order
[i
]].out
!= 0
6477 || rld
[reload_order
[i
]].in
!= 0
6478 || rld
[reload_order
[i
]].secondary_p
)
6479 && ! rld
[reload_order
[i
]].optional
6480 && rld
[reload_order
[i
]].reg_rtx
== 0)
6481 allocate_reload_reg (chain
, reload_order
[i
], 0);
6484 /* First see if this pseudo is already available as reloaded
6485 for a previous insn. We cannot try to inherit for reloads
6486 that are smaller than the maximum number of registers needed
6487 for groups unless the register we would allocate cannot be used
6490 We could check here to see if this is a secondary reload for
6491 an object that is already in a register of the desired class.
6492 This would avoid the need for the secondary reload register.
6493 But this is complex because we can't easily determine what
6494 objects might want to be loaded via this reload. So let a
6495 register be allocated here. In `emit_reload_insns' we suppress
6496 one of the loads in the case described above. */
6502 enum machine_mode mode
= VOIDmode
;
6506 else if (REG_P (rld
[r
].in
))
6508 regno
= REGNO (rld
[r
].in
);
6509 mode
= GET_MODE (rld
[r
].in
);
6511 else if (REG_P (rld
[r
].in_reg
))
6513 regno
= REGNO (rld
[r
].in_reg
);
6514 mode
= GET_MODE (rld
[r
].in_reg
);
6516 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6517 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6519 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6520 if (regno
< FIRST_PSEUDO_REGISTER
)
6521 regno
= subreg_regno (rld
[r
].in_reg
);
6523 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
6524 mode
= GET_MODE (rld
[r
].in_reg
);
6527 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6528 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6530 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6531 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6532 rld
[r
].out
= rld
[r
].in
;
6536 /* This won't work, since REGNO can be a pseudo reg number.
6537 Also, it takes much more hair to keep track of all the things
6538 that can invalidate an inherited reload of part of a pseudoreg. */
6539 else if (GET_CODE (rld
[r
].in
) == SUBREG
6540 && REG_P (SUBREG_REG (rld
[r
].in
)))
6541 regno
= subreg_regno (rld
[r
].in
);
6545 && reg_last_reload_reg
[regno
] != 0
6546 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6547 >= GET_MODE_SIZE (mode
) + byte
)
6548 #ifdef CANNOT_CHANGE_MODE_CLASS
6549 /* Verify that the register it's in can be used in
6551 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6552 GET_MODE (reg_last_reload_reg
[regno
]),
6557 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6558 rtx last_reg
= reg_last_reload_reg
[regno
];
6560 i
= REGNO (last_reg
);
6561 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6562 last_class
= REGNO_REG_CLASS (i
);
6564 if (reg_reloaded_contents
[i
] == regno
6565 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6566 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6567 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6568 /* Even if we can't use this register as a reload
6569 register, we might use it for reload_override_in,
6570 if copying it to the desired class is cheap
6572 || ((register_move_cost (mode
, last_class
, rclass
)
6573 < memory_move_cost (mode
, rclass
, true))
6574 && (secondary_reload_class (1, rclass
, mode
,
6577 #ifdef SECONDARY_MEMORY_NEEDED
6578 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6583 && (rld
[r
].nregs
== max_group_size
6584 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6586 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6587 rld
[r
].when_needed
, rld
[r
].in
,
6590 /* If a group is needed, verify that all the subsequent
6591 registers still have their values intact. */
6592 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6595 for (k
= 1; k
< nr
; k
++)
6596 if (reg_reloaded_contents
[i
+ k
] != regno
6597 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6605 last_reg
= (GET_MODE (last_reg
) == mode
6606 ? last_reg
: gen_rtx_REG (mode
, i
));
6609 for (k
= 0; k
< nr
; k
++)
6610 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6613 /* We found a register that contains the
6614 value we need. If this register is the
6615 same as an `earlyclobber' operand of the
6616 current insn, just mark it as a place to
6617 reload from since we can't use it as the
6618 reload register itself. */
6620 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6621 if (reg_overlap_mentioned_for_reload_p
6622 (reg_last_reload_reg
[regno
],
6623 reload_earlyclobbers
[i1
]))
6626 if (i1
!= n_earlyclobbers
6627 || ! (free_for_value_p (i
, rld
[r
].mode
,
6629 rld
[r
].when_needed
, rld
[r
].in
,
6631 /* Don't use it if we'd clobber a pseudo reg. */
6632 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6634 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6635 /* Don't clobber the frame pointer. */
6636 || (i
== HARD_FRAME_POINTER_REGNUM
6637 && frame_pointer_needed
6639 /* Don't really use the inherited spill reg
6640 if we need it wider than we've got it. */
6641 || (GET_MODE_SIZE (rld
[r
].mode
)
6642 > GET_MODE_SIZE (mode
))
6645 /* If find_reloads chose reload_out as reload
6646 register, stay with it - that leaves the
6647 inherited register for subsequent reloads. */
6648 || (rld
[r
].out
&& rld
[r
].reg_rtx
6649 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6651 if (! rld
[r
].optional
)
6653 reload_override_in
[r
] = last_reg
;
6654 reload_inheritance_insn
[r
]
6655 = reg_reloaded_insn
[i
];
6661 /* We can use this as a reload reg. */
6662 /* Mark the register as in use for this part of
6664 mark_reload_reg_in_use (i
,
6668 rld
[r
].reg_rtx
= last_reg
;
6669 reload_inherited
[r
] = 1;
6670 reload_inheritance_insn
[r
]
6671 = reg_reloaded_insn
[i
];
6672 reload_spill_index
[r
] = i
;
6673 for (k
= 0; k
< nr
; k
++)
6674 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6682 /* Here's another way to see if the value is already lying around. */
6685 && ! reload_inherited
[r
]
6687 && (CONSTANT_P (rld
[r
].in
)
6688 || GET_CODE (rld
[r
].in
) == PLUS
6689 || REG_P (rld
[r
].in
)
6690 || MEM_P (rld
[r
].in
))
6691 && (rld
[r
].nregs
== max_group_size
6692 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6693 search_equiv
= rld
[r
].in
;
6698 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6699 -1, NULL
, 0, rld
[r
].mode
);
6705 regno
= REGNO (equiv
);
6708 /* This must be a SUBREG of a hard register.
6709 Make a new REG since this might be used in an
6710 address and not all machines support SUBREGs
6712 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6713 regno
= subreg_regno (equiv
);
6714 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6715 /* If we choose EQUIV as the reload register, but the
6716 loop below decides to cancel the inheritance, we'll
6717 end up reloading EQUIV in rld[r].mode, not the mode
6718 it had originally. That isn't safe when EQUIV isn't
6719 available as a spill register since its value might
6720 still be live at this point. */
6721 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6722 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6727 /* If we found a spill reg, reject it unless it is free
6728 and of the desired class. */
6732 int bad_for_class
= 0;
6733 int max_regno
= regno
+ rld
[r
].nregs
;
6735 for (i
= regno
; i
< max_regno
; i
++)
6737 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6739 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6744 && ! free_for_value_p (regno
, rld
[r
].mode
,
6745 rld
[r
].opnum
, rld
[r
].when_needed
,
6746 rld
[r
].in
, rld
[r
].out
, r
, 1))
6751 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6754 /* We found a register that contains the value we need.
6755 If this register is the same as an `earlyclobber' operand
6756 of the current insn, just mark it as a place to reload from
6757 since we can't use it as the reload register itself. */
6760 for (i
= 0; i
< n_earlyclobbers
; i
++)
6761 if (reg_overlap_mentioned_for_reload_p (equiv
,
6762 reload_earlyclobbers
[i
]))
6764 if (! rld
[r
].optional
)
6765 reload_override_in
[r
] = equiv
;
6770 /* If the equiv register we have found is explicitly clobbered
6771 in the current insn, it depends on the reload type if we
6772 can use it, use it for reload_override_in, or not at all.
6773 In particular, we then can't use EQUIV for a
6774 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6778 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6779 switch (rld
[r
].when_needed
)
6781 case RELOAD_FOR_OTHER_ADDRESS
:
6782 case RELOAD_FOR_INPADDR_ADDRESS
:
6783 case RELOAD_FOR_INPUT_ADDRESS
:
6784 case RELOAD_FOR_OPADDR_ADDR
:
6787 case RELOAD_FOR_INPUT
:
6788 case RELOAD_FOR_OPERAND_ADDRESS
:
6789 if (! rld
[r
].optional
)
6790 reload_override_in
[r
] = equiv
;
6796 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6797 switch (rld
[r
].when_needed
)
6799 case RELOAD_FOR_OTHER_ADDRESS
:
6800 case RELOAD_FOR_INPADDR_ADDRESS
:
6801 case RELOAD_FOR_INPUT_ADDRESS
:
6802 case RELOAD_FOR_OPADDR_ADDR
:
6803 case RELOAD_FOR_OPERAND_ADDRESS
:
6804 case RELOAD_FOR_INPUT
:
6807 if (! rld
[r
].optional
)
6808 reload_override_in
[r
] = equiv
;
6816 /* If we found an equivalent reg, say no code need be generated
6817 to load it, and use it as our reload reg. */
6819 && (regno
!= HARD_FRAME_POINTER_REGNUM
6820 || !frame_pointer_needed
))
6822 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6824 rld
[r
].reg_rtx
= equiv
;
6825 reload_spill_index
[r
] = regno
;
6826 reload_inherited
[r
] = 1;
6828 /* If reg_reloaded_valid is not set for this register,
6829 there might be a stale spill_reg_store lying around.
6830 We must clear it, since otherwise emit_reload_insns
6831 might delete the store. */
6832 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6833 spill_reg_store
[regno
] = NULL_RTX
;
6834 /* If any of the hard registers in EQUIV are spill
6835 registers, mark them as in use for this insn. */
6836 for (k
= 0; k
< nr
; k
++)
6838 i
= spill_reg_order
[regno
+ k
];
6841 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6844 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6851 /* If we found a register to use already, or if this is an optional
6852 reload, we are done. */
6853 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6857 /* No longer needed for correct operation. Might or might
6858 not give better code on the average. Want to experiment? */
6860 /* See if there is a later reload that has a class different from our
6861 class that intersects our class or that requires less register
6862 than our reload. If so, we must allocate a register to this
6863 reload now, since that reload might inherit a previous reload
6864 and take the only available register in our class. Don't do this
6865 for optional reloads since they will force all previous reloads
6866 to be allocated. Also don't do this for reloads that have been
6869 for (i
= j
+ 1; i
< n_reloads
; i
++)
6871 int s
= reload_order
[i
];
6873 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6874 && ! rld
[s
].secondary_p
)
6878 if ((rld
[s
].rclass
!= rld
[r
].rclass
6879 && reg_classes_intersect_p (rld
[r
].rclass
,
6881 || rld
[s
].nregs
< rld
[r
].nregs
)
6888 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6892 /* Now allocate reload registers for anything non-optional that
6893 didn't get one yet. */
6894 for (j
= 0; j
< n_reloads
; j
++)
6896 int r
= reload_order
[j
];
6898 /* Ignore reloads that got marked inoperative. */
6899 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6902 /* Skip reloads that already have a register allocated or are
6904 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6907 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6911 /* If that loop got all the way, we have won. */
6918 /* Loop around and try without any inheritance. */
6923 /* First undo everything done by the failed attempt
6924 to allocate with inheritance. */
6925 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6927 /* Some sanity tests to verify that the reloads found in the first
6928 pass are identical to the ones we have now. */
6929 gcc_assert (chain
->n_reloads
== n_reloads
);
6931 for (i
= 0; i
< n_reloads
; i
++)
6933 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6935 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6936 for (j
= 0; j
< n_spills
; j
++)
6937 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6938 if (! set_reload_reg (j
, i
))
6939 failed_reload (chain
->insn
, i
);
6943 /* If we thought we could inherit a reload, because it seemed that
6944 nothing else wanted the same reload register earlier in the insn,
6945 verify that assumption, now that all reloads have been assigned.
6946 Likewise for reloads where reload_override_in has been set. */
6948 /* If doing expensive optimizations, do one preliminary pass that doesn't
6949 cancel any inheritance, but removes reloads that have been needed only
6950 for reloads that we know can be inherited. */
6951 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6953 for (j
= 0; j
< n_reloads
; j
++)
6955 int r
= reload_order
[j
];
6957 #ifdef SECONDARY_MEMORY_NEEDED
6960 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6961 check_reg
= rld
[r
].reg_rtx
;
6962 else if (reload_override_in
[r
]
6963 && (REG_P (reload_override_in
[r
])
6964 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6965 check_reg
= reload_override_in
[r
];
6968 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6969 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6970 (reload_inherited
[r
]
6971 ? rld
[r
].out
: const0_rtx
),
6976 reload_inherited
[r
] = 0;
6977 reload_override_in
[r
] = 0;
6979 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6980 reload_override_in, then we do not need its related
6981 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6982 likewise for other reload types.
6983 We handle this by removing a reload when its only replacement
6984 is mentioned in reload_in of the reload we are going to inherit.
6985 A special case are auto_inc expressions; even if the input is
6986 inherited, we still need the address for the output. We can
6987 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6988 If we succeeded removing some reload and we are doing a preliminary
6989 pass just to remove such reloads, make another pass, since the
6990 removal of one reload might allow us to inherit another one. */
6992 && rld
[r
].out
!= rld
[r
].in
6993 && remove_address_replacements (rld
[r
].in
))
6998 #ifdef SECONDARY_MEMORY_NEEDED
6999 /* If we needed a memory location for the reload, we also have to
7000 remove its related reloads. */
7002 && rld
[r
].out
!= rld
[r
].in
7003 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7004 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7005 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7006 rld
[r
].rclass
, rld
[r
].inmode
)
7007 && remove_address_replacements
7008 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7009 rld
[r
].when_needed
)))
7018 /* Now that reload_override_in is known valid,
7019 actually override reload_in. */
7020 for (j
= 0; j
< n_reloads
; j
++)
7021 if (reload_override_in
[j
])
7022 rld
[j
].in
= reload_override_in
[j
];
7024 /* If this reload won't be done because it has been canceled or is
7025 optional and not inherited, clear reload_reg_rtx so other
7026 routines (such as subst_reloads) don't get confused. */
7027 for (j
= 0; j
< n_reloads
; j
++)
7028 if (rld
[j
].reg_rtx
!= 0
7029 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7030 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7031 && ! rld
[j
].secondary_p
)))
7033 int regno
= true_regnum (rld
[j
].reg_rtx
);
7035 if (spill_reg_order
[regno
] >= 0)
7036 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7037 rld
[j
].when_needed
, rld
[j
].mode
);
7039 reload_spill_index
[j
] = -1;
7042 /* Record which pseudos and which spill regs have output reloads. */
7043 for (j
= 0; j
< n_reloads
; j
++)
7045 int r
= reload_order
[j
];
7047 i
= reload_spill_index
[r
];
7049 /* I is nonneg if this reload uses a register.
7050 If rld[r].reg_rtx is 0, this is an optional reload
7051 that we opted to ignore. */
7052 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7053 && rld
[r
].reg_rtx
!= 0)
7055 int nregno
= REGNO (rld
[r
].out_reg
);
7058 if (nregno
< FIRST_PSEUDO_REGISTER
)
7059 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7062 SET_REGNO_REG_SET (®_has_output_reload
,
7066 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7068 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7069 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7070 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7075 /* Deallocate the reload register for reload R. This is called from
7076 remove_address_replacements. */
7079 deallocate_reload_reg (int r
)
7083 if (! rld
[r
].reg_rtx
)
7085 regno
= true_regnum (rld
[r
].reg_rtx
);
7087 if (spill_reg_order
[regno
] >= 0)
7088 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7090 reload_spill_index
[r
] = -1;
7093 /* These arrays are filled by emit_reload_insns and its subroutines. */
7094 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
7095 static rtx other_input_address_reload_insns
= 0;
7096 static rtx other_input_reload_insns
= 0;
7097 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7098 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7099 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
7100 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7101 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7102 static rtx operand_reload_insns
= 0;
7103 static rtx other_operand_reload_insns
= 0;
7104 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7106 /* Values to be put in spill_reg_store are put here first. Instructions
7107 must only be placed here if the associated reload register reaches
7108 the end of the instruction's reload sequence. */
7109 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7110 static HARD_REG_SET reg_reloaded_died
;
7112 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7113 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7114 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7115 adjusted register, and return true. Otherwise, return false. */
7117 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7118 enum reg_class new_class
,
7119 enum machine_mode new_mode
)
7124 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7126 unsigned regno
= REGNO (reg
);
7128 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7130 if (GET_MODE (reg
) != new_mode
)
7132 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7134 if (hard_regno_nregs
[regno
][new_mode
]
7135 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7137 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7145 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7146 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7147 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7148 adjusted register, and return true. Otherwise, return false. */
7150 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7151 enum insn_code icode
)
7154 enum reg_class new_class
= scratch_reload_class (icode
);
7155 enum machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7157 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7158 new_class
, new_mode
);
7161 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7162 has the number J. OLD contains the value to be used as input. */
7165 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7168 rtx insn
= chain
->insn
;
7170 rtx oldequiv_reg
= 0;
7173 enum machine_mode mode
;
7176 /* delete_output_reload is only invoked properly if old contains
7177 the original pseudo register. Since this is replaced with a
7178 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7179 find the pseudo in RELOAD_IN_REG. */
7180 if (reload_override_in
[j
]
7181 && REG_P (rl
->in_reg
))
7188 else if (REG_P (oldequiv
))
7189 oldequiv_reg
= oldequiv
;
7190 else if (GET_CODE (oldequiv
) == SUBREG
)
7191 oldequiv_reg
= SUBREG_REG (oldequiv
);
7193 reloadreg
= reload_reg_rtx_for_input
[j
];
7194 mode
= GET_MODE (reloadreg
);
7196 /* If we are reloading from a register that was recently stored in
7197 with an output-reload, see if we can prove there was
7198 actually no need to store the old value in it. */
7200 if (optimize
&& REG_P (oldequiv
)
7201 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7202 && spill_reg_store
[REGNO (oldequiv
)]
7204 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7205 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7207 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7209 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7212 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7213 oldequiv
= SUBREG_REG (oldequiv
);
7214 if (GET_MODE (oldequiv
) != VOIDmode
7215 && mode
!= GET_MODE (oldequiv
))
7216 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7218 /* Switch to the right place to emit the reload insns. */
7219 switch (rl
->when_needed
)
7222 where
= &other_input_reload_insns
;
7224 case RELOAD_FOR_INPUT
:
7225 where
= &input_reload_insns
[rl
->opnum
];
7227 case RELOAD_FOR_INPUT_ADDRESS
:
7228 where
= &input_address_reload_insns
[rl
->opnum
];
7230 case RELOAD_FOR_INPADDR_ADDRESS
:
7231 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7233 case RELOAD_FOR_OUTPUT_ADDRESS
:
7234 where
= &output_address_reload_insns
[rl
->opnum
];
7236 case RELOAD_FOR_OUTADDR_ADDRESS
:
7237 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7239 case RELOAD_FOR_OPERAND_ADDRESS
:
7240 where
= &operand_reload_insns
;
7242 case RELOAD_FOR_OPADDR_ADDR
:
7243 where
= &other_operand_reload_insns
;
7245 case RELOAD_FOR_OTHER_ADDRESS
:
7246 where
= &other_input_address_reload_insns
;
7252 push_to_sequence (*where
);
7254 /* Auto-increment addresses must be reloaded in a special way. */
7255 if (rl
->out
&& ! rl
->out_reg
)
7257 /* We are not going to bother supporting the case where a
7258 incremented register can't be copied directly from
7259 OLDEQUIV since this seems highly unlikely. */
7260 gcc_assert (rl
->secondary_in_reload
< 0);
7262 if (reload_inherited
[j
])
7263 oldequiv
= reloadreg
;
7265 old
= XEXP (rl
->in_reg
, 0);
7267 /* Prevent normal processing of this reload. */
7269 /* Output a special code sequence for this case. */
7270 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7273 /* If we are reloading a pseudo-register that was set by the previous
7274 insn, see if we can get rid of that pseudo-register entirely
7275 by redirecting the previous insn into our reload register. */
7277 else if (optimize
&& REG_P (old
)
7278 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7279 && dead_or_set_p (insn
, old
)
7280 /* This is unsafe if some other reload
7281 uses the same reg first. */
7282 && ! conflicts_with_override (reloadreg
)
7283 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7284 rl
->when_needed
, old
, rl
->out
, j
, 0))
7286 rtx temp
= PREV_INSN (insn
);
7287 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7288 temp
= PREV_INSN (temp
);
7290 && NONJUMP_INSN_P (temp
)
7291 && GET_CODE (PATTERN (temp
)) == SET
7292 && SET_DEST (PATTERN (temp
)) == old
7293 /* Make sure we can access insn_operand_constraint. */
7294 && asm_noperands (PATTERN (temp
)) < 0
7295 /* This is unsafe if operand occurs more than once in current
7296 insn. Perhaps some occurrences aren't reloaded. */
7297 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7299 rtx old
= SET_DEST (PATTERN (temp
));
7300 /* Store into the reload register instead of the pseudo. */
7301 SET_DEST (PATTERN (temp
)) = reloadreg
;
7303 /* Verify that resulting insn is valid. */
7304 extract_insn (temp
);
7305 if (constrain_operands (1))
7307 /* If the previous insn is an output reload, the source is
7308 a reload register, and its spill_reg_store entry will
7309 contain the previous destination. This is now
7311 if (REG_P (SET_SRC (PATTERN (temp
)))
7312 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7314 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7315 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7318 /* If these are the only uses of the pseudo reg,
7319 pretend for GDB it lives in the reload reg we used. */
7320 if (REG_N_DEATHS (REGNO (old
)) == 1
7321 && REG_N_SETS (REGNO (old
)) == 1)
7323 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7324 if (ira_conflicts_p
)
7325 /* Inform IRA about the change. */
7326 ira_mark_allocation_change (REGNO (old
));
7327 alter_reg (REGNO (old
), -1, false);
7331 /* Adjust any debug insns between temp and insn. */
7332 while ((temp
= NEXT_INSN (temp
)) != insn
)
7333 if (DEBUG_INSN_P (temp
))
7334 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7336 gcc_assert (NOTE_P (temp
));
7340 SET_DEST (PATTERN (temp
)) = old
;
7345 /* We can't do that, so output an insn to load RELOADREG. */
7347 /* If we have a secondary reload, pick up the secondary register
7348 and icode, if any. If OLDEQUIV and OLD are different or
7349 if this is an in-out reload, recompute whether or not we
7350 still need a secondary register and what the icode should
7351 be. If we still need a secondary register and the class or
7352 icode is different, go back to reloading from OLD if using
7353 OLDEQUIV means that we got the wrong type of register. We
7354 cannot have different class or icode due to an in-out reload
7355 because we don't make such reloads when both the input and
7356 output need secondary reload registers. */
7358 if (! special
&& rl
->secondary_in_reload
>= 0)
7360 rtx second_reload_reg
= 0;
7361 rtx third_reload_reg
= 0;
7362 int secondary_reload
= rl
->secondary_in_reload
;
7363 rtx real_oldequiv
= oldequiv
;
7366 enum insn_code icode
;
7367 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7369 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7370 and similarly for OLD.
7371 See comments in get_secondary_reload in reload.c. */
7372 /* If it is a pseudo that cannot be replaced with its
7373 equivalent MEM, we must fall back to reload_in, which
7374 will have all the necessary substitutions registered.
7375 Likewise for a pseudo that can't be replaced with its
7376 equivalent constant.
7378 Take extra care for subregs of such pseudos. Note that
7379 we cannot use reg_equiv_mem in this case because it is
7380 not in the right mode. */
7383 if (GET_CODE (tmp
) == SUBREG
)
7384 tmp
= SUBREG_REG (tmp
);
7386 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7387 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7388 || reg_equiv_constant (REGNO (tmp
)) != 0))
7390 if (! reg_equiv_mem (REGNO (tmp
))
7391 || num_not_at_initial_offset
7392 || GET_CODE (oldequiv
) == SUBREG
)
7393 real_oldequiv
= rl
->in
;
7395 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7399 if (GET_CODE (tmp
) == SUBREG
)
7400 tmp
= SUBREG_REG (tmp
);
7402 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7403 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7404 || reg_equiv_constant (REGNO (tmp
)) != 0))
7406 if (! reg_equiv_mem (REGNO (tmp
))
7407 || num_not_at_initial_offset
7408 || GET_CODE (old
) == SUBREG
)
7411 real_old
= reg_equiv_mem (REGNO (tmp
));
7414 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7415 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7417 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7419 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7420 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7421 /* We'd have to add more code for quartary reloads. */
7422 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7424 icode
= rl
->secondary_in_icode
;
7426 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7427 || (rl
->in
!= 0 && rl
->out
!= 0))
7429 secondary_reload_info sri
, sri2
;
7430 enum reg_class new_class
, new_t_class
;
7432 sri
.icode
= CODE_FOR_nothing
;
7433 sri
.prev_sri
= NULL
;
7435 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7439 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7440 second_reload_reg
= 0;
7441 else if (new_class
== NO_REGS
)
7443 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7445 (enum insn_code
) sri
.icode
))
7447 icode
= (enum insn_code
) sri
.icode
;
7448 third_reload_reg
= 0;
7453 real_oldequiv
= real_old
;
7456 else if (sri
.icode
!= CODE_FOR_nothing
)
7457 /* We currently lack a way to express this in reloads. */
7461 sri2
.icode
= CODE_FOR_nothing
;
7462 sri2
.prev_sri
= &sri
;
7464 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7467 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7469 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7473 third_reload_reg
= 0;
7474 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7479 real_oldequiv
= real_old
;
7482 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7484 rtx intermediate
= second_reload_reg
;
7486 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7488 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7492 second_reload_reg
= intermediate
;
7493 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7498 real_oldequiv
= real_old
;
7501 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7503 rtx intermediate
= second_reload_reg
;
7505 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7507 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7510 second_reload_reg
= intermediate
;
7511 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7516 real_oldequiv
= real_old
;
7521 /* This could be handled more intelligently too. */
7523 real_oldequiv
= real_old
;
7528 /* If we still need a secondary reload register, check
7529 to see if it is being used as a scratch or intermediate
7530 register and generate code appropriately. If we need
7531 a scratch register, use REAL_OLDEQUIV since the form of
7532 the insn may depend on the actual address if it is
7535 if (second_reload_reg
)
7537 if (icode
!= CODE_FOR_nothing
)
7539 /* We'd have to add extra code to handle this case. */
7540 gcc_assert (!third_reload_reg
);
7542 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7543 second_reload_reg
));
7548 /* See if we need a scratch register to load the
7549 intermediate register (a tertiary reload). */
7550 if (tertiary_icode
!= CODE_FOR_nothing
)
7552 emit_insn ((GEN_FCN (tertiary_icode
)
7553 (second_reload_reg
, real_oldequiv
,
7554 third_reload_reg
)));
7556 else if (third_reload_reg
)
7558 gen_reload (third_reload_reg
, real_oldequiv
,
7561 gen_reload (second_reload_reg
, third_reload_reg
,
7566 gen_reload (second_reload_reg
, real_oldequiv
,
7570 oldequiv
= second_reload_reg
;
7575 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7577 rtx real_oldequiv
= oldequiv
;
7579 if ((REG_P (oldequiv
)
7580 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7581 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7582 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7583 || (GET_CODE (oldequiv
) == SUBREG
7584 && REG_P (SUBREG_REG (oldequiv
))
7585 && (REGNO (SUBREG_REG (oldequiv
))
7586 >= FIRST_PSEUDO_REGISTER
)
7587 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7588 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7589 || (CONSTANT_P (oldequiv
)
7590 && (targetm
.preferred_reload_class (oldequiv
,
7591 REGNO_REG_CLASS (REGNO (reloadreg
)))
7593 real_oldequiv
= rl
->in
;
7594 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7598 if (cfun
->can_throw_non_call_exceptions
)
7599 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7601 /* End this sequence. */
7602 *where
= get_insns ();
7605 /* Update reload_override_in so that delete_address_reloads_1
7606 can see the actual register usage. */
7608 reload_override_in
[j
] = oldequiv
;
7611 /* Generate insns to for the output reload RL, which is for the insn described
7612 by CHAIN and has the number J. */
7614 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7618 rtx insn
= chain
->insn
;
7621 enum machine_mode mode
;
7625 if (rl
->when_needed
== RELOAD_OTHER
)
7628 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7630 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7631 mode
= GET_MODE (rl_reg_rtx
);
7633 reloadreg
= rl_reg_rtx
;
7635 /* If we need two reload regs, set RELOADREG to the intermediate
7636 one, since it will be stored into OLD. We might need a secondary
7637 register only for an input reload, so check again here. */
7639 if (rl
->secondary_out_reload
>= 0)
7642 int secondary_reload
= rl
->secondary_out_reload
;
7643 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7645 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7646 && reg_equiv_mem (REGNO (old
)) != 0)
7647 real_old
= reg_equiv_mem (REGNO (old
));
7649 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7651 rtx second_reloadreg
= reloadreg
;
7652 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7654 /* See if RELOADREG is to be used as a scratch register
7655 or as an intermediate register. */
7656 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7658 /* We'd have to add extra code to handle this case. */
7659 gcc_assert (tertiary_reload
< 0);
7661 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7662 (real_old
, second_reloadreg
, reloadreg
)));
7667 /* See if we need both a scratch and intermediate reload
7670 enum insn_code tertiary_icode
7671 = rld
[secondary_reload
].secondary_out_icode
;
7673 /* We'd have to add more code for quartary reloads. */
7674 gcc_assert (tertiary_reload
< 0
7675 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7677 if (GET_MODE (reloadreg
) != mode
)
7678 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7680 if (tertiary_icode
!= CODE_FOR_nothing
)
7682 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7684 /* Copy primary reload reg to secondary reload reg.
7685 (Note that these have been swapped above, then
7686 secondary reload reg to OLD using our insn.) */
7688 /* If REAL_OLD is a paradoxical SUBREG, remove it
7689 and try to put the opposite SUBREG on
7691 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7693 gen_reload (reloadreg
, second_reloadreg
,
7694 rl
->opnum
, rl
->when_needed
);
7695 emit_insn ((GEN_FCN (tertiary_icode
)
7696 (real_old
, reloadreg
, third_reloadreg
)));
7702 /* Copy between the reload regs here and then to
7705 gen_reload (reloadreg
, second_reloadreg
,
7706 rl
->opnum
, rl
->when_needed
);
7707 if (tertiary_reload
>= 0)
7709 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7711 gen_reload (third_reloadreg
, reloadreg
,
7712 rl
->opnum
, rl
->when_needed
);
7713 reloadreg
= third_reloadreg
;
7720 /* Output the last reload insn. */
7725 /* Don't output the last reload if OLD is not the dest of
7726 INSN and is in the src and is clobbered by INSN. */
7727 if (! flag_expensive_optimizations
7729 || !(set
= single_set (insn
))
7730 || rtx_equal_p (old
, SET_DEST (set
))
7731 || !reg_mentioned_p (old
, SET_SRC (set
))
7732 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7733 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7734 gen_reload (old
, reloadreg
, rl
->opnum
,
7738 /* Look at all insns we emitted, just to be safe. */
7739 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7742 rtx pat
= PATTERN (p
);
7744 /* If this output reload doesn't come from a spill reg,
7745 clear any memory of reloaded copies of the pseudo reg.
7746 If this output reload comes from a spill reg,
7747 reg_has_output_reload will make this do nothing. */
7748 note_stores (pat
, forget_old_reloads_1
, NULL
);
7750 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7752 rtx set
= single_set (insn
);
7753 if (reload_spill_index
[j
] < 0
7755 && SET_SRC (set
) == rl_reg_rtx
)
7757 int src
= REGNO (SET_SRC (set
));
7759 reload_spill_index
[j
] = src
;
7760 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7761 if (find_regno_note (insn
, REG_DEAD
, src
))
7762 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7764 if (HARD_REGISTER_P (rl_reg_rtx
))
7766 int s
= rl
->secondary_out_reload
;
7767 set
= single_set (p
);
7768 /* If this reload copies only to the secondary reload
7769 register, the secondary reload does the actual
7771 if (s
>= 0 && set
== NULL_RTX
)
7772 /* We can't tell what function the secondary reload
7773 has and where the actual store to the pseudo is
7774 made; leave new_spill_reg_store alone. */
7777 && SET_SRC (set
) == rl_reg_rtx
7778 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7780 /* Usually the next instruction will be the
7781 secondary reload insn; if we can confirm
7782 that it is, setting new_spill_reg_store to
7783 that insn will allow an extra optimization. */
7784 rtx s_reg
= rld
[s
].reg_rtx
;
7785 rtx next
= NEXT_INSN (p
);
7786 rld
[s
].out
= rl
->out
;
7787 rld
[s
].out_reg
= rl
->out_reg
;
7788 set
= single_set (next
);
7789 if (set
&& SET_SRC (set
) == s_reg
7790 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7792 SET_HARD_REG_BIT (reg_is_output_reload
,
7794 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7797 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7798 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7803 if (rl
->when_needed
== RELOAD_OTHER
)
7805 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7806 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7809 output_reload_insns
[rl
->opnum
] = get_insns ();
7811 if (cfun
->can_throw_non_call_exceptions
)
7812 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7817 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7818 and has the number J. */
7820 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7822 rtx insn
= chain
->insn
;
7823 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7824 ? rl
->in_reg
: rl
->in
);
7825 rtx reg_rtx
= rl
->reg_rtx
;
7829 enum machine_mode mode
;
7831 /* Determine the mode to reload in.
7832 This is very tricky because we have three to choose from.
7833 There is the mode the insn operand wants (rl->inmode).
7834 There is the mode of the reload register RELOADREG.
7835 There is the intrinsic mode of the operand, which we could find
7836 by stripping some SUBREGs.
7837 It turns out that RELOADREG's mode is irrelevant:
7838 we can change that arbitrarily.
7840 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7841 then the reload reg may not support QImode moves, so use SImode.
7842 If foo is in memory due to spilling a pseudo reg, this is safe,
7843 because the QImode value is in the least significant part of a
7844 slot big enough for a SImode. If foo is some other sort of
7845 memory reference, then it is impossible to reload this case,
7846 so previous passes had better make sure this never happens.
7848 Then consider a one-word union which has SImode and one of its
7849 members is a float, being fetched as (SUBREG:SF union:SI).
7850 We must fetch that as SFmode because we could be loading into
7851 a float-only register. In this case OLD's mode is correct.
7853 Consider an immediate integer: it has VOIDmode. Here we need
7854 to get a mode from something else.
7856 In some cases, there is a fourth mode, the operand's
7857 containing mode. If the insn specifies a containing mode for
7858 this operand, it overrides all others.
7860 I am not sure whether the algorithm here is always right,
7861 but it does the right things in those cases. */
7863 mode
= GET_MODE (old
);
7864 if (mode
== VOIDmode
)
7867 /* We cannot use gen_lowpart_common since it can do the wrong thing
7868 when REG_RTX has a multi-word mode. Note that REG_RTX must
7869 always be a REG here. */
7870 if (GET_MODE (reg_rtx
) != mode
)
7871 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7873 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7876 /* AUTO_INC reloads need to be handled even if inherited. We got an
7877 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7878 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7879 && ! rtx_equal_p (reg_rtx
, old
)
7881 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7883 /* When inheriting a wider reload, we have a MEM in rl->in,
7884 e.g. inheriting a SImode output reload for
7885 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7886 if (optimize
&& reload_inherited
[j
] && rl
->in
7888 && MEM_P (rl
->in_reg
)
7889 && reload_spill_index
[j
] >= 0
7890 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7891 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7893 /* If we are reloading a register that was recently stored in with an
7894 output-reload, see if we can prove there was
7895 actually no need to store the old value in it. */
7898 && (reload_inherited
[j
] || reload_override_in
[j
])
7901 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7903 /* There doesn't seem to be any reason to restrict this to pseudos
7904 and doing so loses in the case where we are copying from a
7905 register of the wrong class. */
7906 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7908 /* The insn might have already some references to stackslots
7909 replaced by MEMs, while reload_out_reg still names the
7911 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7912 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7913 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7916 /* Do output reloading for reload RL, which is for the insn described by
7917 CHAIN and has the number J.
7918 ??? At some point we need to support handling output reloads of
7919 JUMP_INSNs or insns that set cc0. */
7921 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7924 rtx insn
= chain
->insn
;
7925 /* If this is an output reload that stores something that is
7926 not loaded in this same reload, see if we can eliminate a previous
7928 rtx pseudo
= rl
->out_reg
;
7929 rtx reg_rtx
= rl
->reg_rtx
;
7931 if (rl
->out
&& reg_rtx
)
7933 enum machine_mode mode
;
7935 /* Determine the mode to reload in.
7936 See comments above (for input reloading). */
7937 mode
= GET_MODE (rl
->out
);
7938 if (mode
== VOIDmode
)
7940 /* VOIDmode should never happen for an output. */
7941 if (asm_noperands (PATTERN (insn
)) < 0)
7942 /* It's the compiler's fault. */
7943 fatal_insn ("VOIDmode on an output", insn
);
7944 error_for_asm (insn
, "output operand is constant in %<asm%>");
7945 /* Prevent crash--use something we know is valid. */
7947 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7949 if (GET_MODE (reg_rtx
) != mode
)
7950 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7952 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7957 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7958 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7959 && reg_last_reload_reg
[REGNO (pseudo
)])
7961 int pseudo_no
= REGNO (pseudo
);
7962 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7964 /* We don't need to test full validity of last_regno for
7965 inherit here; we only want to know if the store actually
7966 matches the pseudo. */
7967 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7968 && reg_reloaded_contents
[last_regno
] == pseudo_no
7969 && spill_reg_store
[last_regno
]
7970 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7971 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7977 || rtx_equal_p (old
, reg_rtx
))
7980 /* An output operand that dies right away does need a reload,
7981 but need not be copied from it. Show the new location in the
7983 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7984 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7986 XEXP (note
, 0) = reg_rtx
;
7989 /* Likewise for a SUBREG of an operand that dies. */
7990 else if (GET_CODE (old
) == SUBREG
7991 && REG_P (SUBREG_REG (old
))
7992 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7995 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7998 else if (GET_CODE (old
) == SCRATCH
)
7999 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8000 but we don't want to make an output reload. */
8003 /* If is a JUMP_INSN, we can't support output reloads yet. */
8004 gcc_assert (NONJUMP_INSN_P (insn
));
8006 emit_output_reload_insns (chain
, rld
+ j
, j
);
8009 /* A reload copies values of MODE from register SRC to register DEST.
8010 Return true if it can be treated for inheritance purposes like a
8011 group of reloads, each one reloading a single hard register. The
8012 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8013 occupy the same number of hard registers. */
8016 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8017 int src ATTRIBUTE_UNUSED
,
8018 enum machine_mode mode ATTRIBUTE_UNUSED
)
8020 #ifdef CANNOT_CHANGE_MODE_CLASS
8021 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8022 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8028 /* Output insns to reload values in and out of the chosen reload regs. */
8031 emit_reload_insns (struct insn_chain
*chain
)
8033 rtx insn
= chain
->insn
;
8037 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8039 for (j
= 0; j
< reload_n_operands
; j
++)
8040 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8041 = inpaddr_address_reload_insns
[j
]
8042 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8043 = outaddr_address_reload_insns
[j
]
8044 = other_output_reload_insns
[j
] = 0;
8045 other_input_address_reload_insns
= 0;
8046 other_input_reload_insns
= 0;
8047 operand_reload_insns
= 0;
8048 other_operand_reload_insns
= 0;
8050 /* Dump reloads into the dump file. */
8053 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8054 debug_reload_to_stream (dump_file
);
8057 for (j
= 0; j
< n_reloads
; j
++)
8058 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8062 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8063 new_spill_reg_store
[i
] = 0;
8066 /* Now output the instructions to copy the data into and out of the
8067 reload registers. Do these in the order that the reloads were reported,
8068 since reloads of base and index registers precede reloads of operands
8069 and the operands may need the base and index registers reloaded. */
8071 for (j
= 0; j
< n_reloads
; j
++)
8073 do_input_reload (chain
, rld
+ j
, j
);
8074 do_output_reload (chain
, rld
+ j
, j
);
8077 /* Now write all the insns we made for reloads in the order expected by
8078 the allocation functions. Prior to the insn being reloaded, we write
8079 the following reloads:
8081 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8083 RELOAD_OTHER reloads.
8085 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8086 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8087 RELOAD_FOR_INPUT reload for the operand.
8089 RELOAD_FOR_OPADDR_ADDRS reloads.
8091 RELOAD_FOR_OPERAND_ADDRESS reloads.
8093 After the insn being reloaded, we write the following:
8095 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8096 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8097 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8098 reloads for the operand. The RELOAD_OTHER output reloads are
8099 output in descending order by reload number. */
8101 emit_insn_before (other_input_address_reload_insns
, insn
);
8102 emit_insn_before (other_input_reload_insns
, insn
);
8104 for (j
= 0; j
< reload_n_operands
; j
++)
8106 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8107 emit_insn_before (input_address_reload_insns
[j
], insn
);
8108 emit_insn_before (input_reload_insns
[j
], insn
);
8111 emit_insn_before (other_operand_reload_insns
, insn
);
8112 emit_insn_before (operand_reload_insns
, insn
);
8114 for (j
= 0; j
< reload_n_operands
; j
++)
8116 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8117 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8118 x
= emit_insn_after (output_reload_insns
[j
], x
);
8119 emit_insn_after (other_output_reload_insns
[j
], x
);
8122 /* For all the spill regs newly reloaded in this instruction,
8123 record what they were reloaded from, so subsequent instructions
8124 can inherit the reloads.
8126 Update spill_reg_store for the reloads of this insn.
8127 Copy the elements that were updated in the loop above. */
8129 for (j
= 0; j
< n_reloads
; j
++)
8131 int r
= reload_order
[j
];
8132 int i
= reload_spill_index
[r
];
8134 /* If this is a non-inherited input reload from a pseudo, we must
8135 clear any memory of a previous store to the same pseudo. Only do
8136 something if there will not be an output reload for the pseudo
8138 if (rld
[r
].in_reg
!= 0
8139 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8141 rtx reg
= rld
[r
].in_reg
;
8143 if (GET_CODE (reg
) == SUBREG
)
8144 reg
= SUBREG_REG (reg
);
8147 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8148 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8150 int nregno
= REGNO (reg
);
8152 if (reg_last_reload_reg
[nregno
])
8154 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8156 if (reg_reloaded_contents
[last_regno
] == nregno
)
8157 spill_reg_store
[last_regno
] = 0;
8162 /* I is nonneg if this reload used a register.
8163 If rld[r].reg_rtx is 0, this is an optional reload
8164 that we opted to ignore. */
8166 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8168 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8171 /* For a multi register reload, we need to check if all or part
8172 of the value lives to the end. */
8173 for (k
= 0; k
< nr
; k
++)
8174 if (reload_reg_reaches_end_p (i
+ k
, r
))
8175 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8177 /* Maybe the spill reg contains a copy of reload_out. */
8179 && (REG_P (rld
[r
].out
)
8181 ? REG_P (rld
[r
].out_reg
)
8182 /* The reload value is an auto-modification of
8183 some kind. For PRE_INC, POST_INC, PRE_DEC
8184 and POST_DEC, we record an equivalence
8185 between the reload register and the operand
8186 on the optimistic assumption that we can make
8187 the equivalence hold. reload_as_needed must
8188 then either make it hold or invalidate the
8191 PRE_MODIFY and POST_MODIFY addresses are reloaded
8192 somewhat differently, and allowing them here leads
8194 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8195 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8199 reg
= reload_reg_rtx_for_output
[r
];
8200 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8202 enum machine_mode mode
= GET_MODE (reg
);
8203 int regno
= REGNO (reg
);
8204 int nregs
= hard_regno_nregs
[regno
][mode
];
8205 rtx out
= (REG_P (rld
[r
].out
)
8209 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8210 int out_regno
= REGNO (out
);
8211 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8212 : hard_regno_nregs
[out_regno
][mode
]);
8215 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8216 spill_reg_stored_to
[regno
] = out
;
8217 reg_last_reload_reg
[out_regno
] = reg
;
8219 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8220 && nregs
== out_nregs
8221 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8223 /* If OUT_REGNO is a hard register, it may occupy more than
8224 one register. If it does, say what is in the
8225 rest of the registers assuming that both registers
8226 agree on how many words the object takes. If not,
8227 invalidate the subsequent registers. */
8229 if (HARD_REGISTER_NUM_P (out_regno
))
8230 for (k
= 1; k
< out_nregs
; k
++)
8231 reg_last_reload_reg
[out_regno
+ k
]
8232 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8234 /* Now do the inverse operation. */
8235 for (k
= 0; k
< nregs
; k
++)
8237 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8238 reg_reloaded_contents
[regno
+ k
]
8239 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8242 reg_reloaded_insn
[regno
+ k
] = insn
;
8243 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8244 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8245 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8248 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8253 /* Maybe the spill reg contains a copy of reload_in. Only do
8254 something if there will not be an output reload for
8255 the register being reloaded. */
8256 else if (rld
[r
].out_reg
== 0
8258 && ((REG_P (rld
[r
].in
)
8259 && !HARD_REGISTER_P (rld
[r
].in
)
8260 && !REGNO_REG_SET_P (®_has_output_reload
,
8262 || (REG_P (rld
[r
].in_reg
)
8263 && !REGNO_REG_SET_P (®_has_output_reload
,
8264 REGNO (rld
[r
].in_reg
))))
8265 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8269 reg
= reload_reg_rtx_for_input
[r
];
8270 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8272 enum machine_mode mode
;
8280 mode
= GET_MODE (reg
);
8281 regno
= REGNO (reg
);
8282 nregs
= hard_regno_nregs
[regno
][mode
];
8283 if (REG_P (rld
[r
].in
)
8284 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8286 else if (REG_P (rld
[r
].in_reg
))
8289 in
= XEXP (rld
[r
].in_reg
, 0);
8290 in_regno
= REGNO (in
);
8292 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8293 : hard_regno_nregs
[in_regno
][mode
]);
8295 reg_last_reload_reg
[in_regno
] = reg
;
8297 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8298 && nregs
== in_nregs
8299 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8301 if (HARD_REGISTER_NUM_P (in_regno
))
8302 for (k
= 1; k
< in_nregs
; k
++)
8303 reg_last_reload_reg
[in_regno
+ k
]
8304 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8306 /* Unless we inherited this reload, show we haven't
8307 recently done a store.
8308 Previous stores of inherited auto_inc expressions
8309 also have to be discarded. */
8310 if (! reload_inherited
[r
]
8311 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8312 spill_reg_store
[regno
] = 0;
8314 for (k
= 0; k
< nregs
; k
++)
8316 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8317 reg_reloaded_contents
[regno
+ k
]
8318 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8321 reg_reloaded_insn
[regno
+ k
] = insn
;
8322 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8323 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8324 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8327 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8334 /* The following if-statement was #if 0'd in 1.34 (or before...).
8335 It's reenabled in 1.35 because supposedly nothing else
8336 deals with this problem. */
8338 /* If a register gets output-reloaded from a non-spill register,
8339 that invalidates any previous reloaded copy of it.
8340 But forget_old_reloads_1 won't get to see it, because
8341 it thinks only about the original insn. So invalidate it here.
8342 Also do the same thing for RELOAD_OTHER constraints where the
8343 output is discarded. */
8345 && ((rld
[r
].out
!= 0
8346 && (REG_P (rld
[r
].out
)
8347 || (MEM_P (rld
[r
].out
)
8348 && REG_P (rld
[r
].out_reg
))))
8349 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8350 && REG_P (rld
[r
].out_reg
))))
8352 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8353 ? rld
[r
].out
: rld
[r
].out_reg
);
8354 int out_regno
= REGNO (out
);
8355 enum machine_mode mode
= GET_MODE (out
);
8357 /* REG_RTX is now set or clobbered by the main instruction.
8358 As the comment above explains, forget_old_reloads_1 only
8359 sees the original instruction, and there is no guarantee
8360 that the original instruction also clobbered REG_RTX.
8361 For example, if find_reloads sees that the input side of
8362 a matched operand pair dies in this instruction, it may
8363 use the input register as the reload register.
8365 Calling forget_old_reloads_1 is a waste of effort if
8366 REG_RTX is also the output register.
8368 If we know that REG_RTX holds the value of a pseudo
8369 register, the code after the call will record that fact. */
8370 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8371 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8373 if (!HARD_REGISTER_NUM_P (out_regno
))
8375 rtx src_reg
, store_insn
= NULL_RTX
;
8377 reg_last_reload_reg
[out_regno
] = 0;
8379 /* If we can find a hard register that is stored, record
8380 the storing insn so that we may delete this insn with
8381 delete_output_reload. */
8382 src_reg
= reload_reg_rtx_for_output
[r
];
8386 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8387 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8393 /* If this is an optional reload, try to find the
8394 source reg from an input reload. */
8395 rtx set
= single_set (insn
);
8396 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8400 src_reg
= SET_SRC (set
);
8402 for (k
= 0; k
< n_reloads
; k
++)
8404 if (rld
[k
].in
== src_reg
)
8406 src_reg
= reload_reg_rtx_for_input
[k
];
8412 if (src_reg
&& REG_P (src_reg
)
8413 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8415 int src_regno
, src_nregs
, k
;
8418 gcc_assert (GET_MODE (src_reg
) == mode
);
8419 src_regno
= REGNO (src_reg
);
8420 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8421 /* The place where to find a death note varies with
8422 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8423 necessarily checked exactly in the code that moves
8424 notes, so just check both locations. */
8425 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8426 if (! note
&& store_insn
)
8427 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8428 for (k
= 0; k
< src_nregs
; k
++)
8430 spill_reg_store
[src_regno
+ k
] = store_insn
;
8431 spill_reg_stored_to
[src_regno
+ k
] = out
;
8432 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8433 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8434 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8435 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8436 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8438 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8441 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8443 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8445 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8447 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8449 reg_last_reload_reg
[out_regno
] = src_reg
;
8450 /* We have to set reg_has_output_reload here, or else
8451 forget_old_reloads_1 will clear reg_last_reload_reg
8453 SET_REGNO_REG_SET (®_has_output_reload
,
8459 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8461 for (k
= 0; k
< out_nregs
; k
++)
8462 reg_last_reload_reg
[out_regno
+ k
] = 0;
8466 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8469 /* Go through the motions to emit INSN and test if it is strictly valid.
8470 Return the emitted insn if valid, else return NULL. */
8473 emit_insn_if_valid_for_reload (rtx insn
)
8475 rtx last
= get_last_insn ();
8478 insn
= emit_insn (insn
);
8479 code
= recog_memoized (insn
);
8483 extract_insn (insn
);
8484 /* We want constrain operands to treat this insn strictly in its
8485 validity determination, i.e., the way it would after reload has
8487 if (constrain_operands (1))
8491 delete_insns_since (last
);
8495 /* Emit code to perform a reload from IN (which may be a reload register) to
8496 OUT (which may also be a reload register). IN or OUT is from operand
8497 OPNUM with reload type TYPE.
8499 Returns first insn emitted. */
8502 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8504 rtx last
= get_last_insn ();
8506 #ifdef SECONDARY_MEMORY_NEEDED
8510 /* If IN is a paradoxical SUBREG, remove it and try to put the
8511 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8512 if (!strip_paradoxical_subreg (&in
, &out
))
8513 strip_paradoxical_subreg (&out
, &in
);
8515 /* How to do this reload can get quite tricky. Normally, we are being
8516 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8517 register that didn't get a hard register. In that case we can just
8518 call emit_move_insn.
8520 We can also be asked to reload a PLUS that adds a register or a MEM to
8521 another register, constant or MEM. This can occur during frame pointer
8522 elimination and while reloading addresses. This case is handled by
8523 trying to emit a single insn to perform the add. If it is not valid,
8524 we use a two insn sequence.
8526 Or we can be asked to reload an unary operand that was a fragment of
8527 an addressing mode, into a register. If it isn't recognized as-is,
8528 we try making the unop operand and the reload-register the same:
8529 (set reg:X (unop:X expr:Y))
8530 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8532 Finally, we could be called to handle an 'o' constraint by putting
8533 an address into a register. In that case, we first try to do this
8534 with a named pattern of "reload_load_address". If no such pattern
8535 exists, we just emit a SET insn and hope for the best (it will normally
8536 be valid on machines that use 'o').
8538 This entire process is made complex because reload will never
8539 process the insns we generate here and so we must ensure that
8540 they will fit their constraints and also by the fact that parts of
8541 IN might be being reloaded separately and replaced with spill registers.
8542 Because of this, we are, in some sense, just guessing the right approach
8543 here. The one listed above seems to work.
8545 ??? At some point, this whole thing needs to be rethought. */
8547 if (GET_CODE (in
) == PLUS
8548 && (REG_P (XEXP (in
, 0))
8549 || GET_CODE (XEXP (in
, 0)) == SUBREG
8550 || MEM_P (XEXP (in
, 0)))
8551 && (REG_P (XEXP (in
, 1))
8552 || GET_CODE (XEXP (in
, 1)) == SUBREG
8553 || CONSTANT_P (XEXP (in
, 1))
8554 || MEM_P (XEXP (in
, 1))))
8556 /* We need to compute the sum of a register or a MEM and another
8557 register, constant, or MEM, and put it into the reload
8558 register. The best possible way of doing this is if the machine
8559 has a three-operand ADD insn that accepts the required operands.
8561 The simplest approach is to try to generate such an insn and see if it
8562 is recognized and matches its constraints. If so, it can be used.
8564 It might be better not to actually emit the insn unless it is valid,
8565 but we need to pass the insn as an operand to `recog' and
8566 `extract_insn' and it is simpler to emit and then delete the insn if
8567 not valid than to dummy things up. */
8569 rtx op0
, op1
, tem
, insn
;
8570 enum insn_code code
;
8572 op0
= find_replacement (&XEXP (in
, 0));
8573 op1
= find_replacement (&XEXP (in
, 1));
8575 /* Since constraint checking is strict, commutativity won't be
8576 checked, so we need to do that here to avoid spurious failure
8577 if the add instruction is two-address and the second operand
8578 of the add is the same as the reload reg, which is frequently
8579 the case. If the insn would be A = B + A, rearrange it so
8580 it will be A = A + B as constrain_operands expects. */
8582 if (REG_P (XEXP (in
, 1))
8583 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8584 tem
= op0
, op0
= op1
, op1
= tem
;
8586 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8587 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8589 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8593 /* If that failed, we must use a conservative two-insn sequence.
8595 Use a move to copy one operand into the reload register. Prefer
8596 to reload a constant, MEM or pseudo since the move patterns can
8597 handle an arbitrary operand. If OP1 is not a constant, MEM or
8598 pseudo and OP1 is not a valid operand for an add instruction, then
8601 After reloading one of the operands into the reload register, add
8602 the reload register to the output register.
8604 If there is another way to do this for a specific machine, a
8605 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8608 code
= optab_handler (add_optab
, GET_MODE (out
));
8610 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8612 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8613 || (code
!= CODE_FOR_nothing
8614 && !insn_operand_matches (code
, 2, op1
)))
8615 tem
= op0
, op0
= op1
, op1
= tem
;
8617 gen_reload (out
, op0
, opnum
, type
);
8619 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8620 This fixes a problem on the 32K where the stack pointer cannot
8621 be used as an operand of an add insn. */
8623 if (rtx_equal_p (op0
, op1
))
8626 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8629 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8630 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8634 /* If that failed, copy the address register to the reload register.
8635 Then add the constant to the reload register. */
8637 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8638 gen_reload (out
, op1
, opnum
, type
);
8639 insn
= emit_insn (gen_add2_insn (out
, op0
));
8640 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8643 #ifdef SECONDARY_MEMORY_NEEDED
8644 /* If we need a memory location to do the move, do it that way. */
8645 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8646 (REG_P (tem1
) && REG_P (tem2
)))
8647 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8648 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8649 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8650 REGNO_REG_CLASS (REGNO (tem2
)),
8653 /* Get the memory to use and rewrite both registers to its mode. */
8654 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8656 if (GET_MODE (loc
) != GET_MODE (out
))
8657 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8659 if (GET_MODE (loc
) != GET_MODE (in
))
8660 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8662 gen_reload (loc
, in
, opnum
, type
);
8663 gen_reload (out
, loc
, opnum
, type
);
8666 else if (REG_P (out
) && UNARY_P (in
))
8673 op1
= find_replacement (&XEXP (in
, 0));
8674 if (op1
!= XEXP (in
, 0))
8675 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8677 /* First, try a plain SET. */
8678 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode
, out
, in
));
8682 /* If that failed, move the inner operand to the reload
8683 register, and try the same unop with the inner expression
8684 replaced with the reload register. */
8686 if (GET_MODE (op1
) != GET_MODE (out
))
8687 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8691 gen_reload (out_moded
, op1
, opnum
, type
);
8694 = gen_rtx_SET (VOIDmode
, out
,
8695 gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8697 insn
= emit_insn_if_valid_for_reload (insn
);
8700 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8704 fatal_insn ("failure trying to reload:", set
);
8706 /* If IN is a simple operand, use gen_move_insn. */
8707 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8709 tem
= emit_insn (gen_move_insn (out
, in
));
8710 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8711 mark_jump_label (in
, tem
, 0);
8714 #ifdef HAVE_reload_load_address
8715 else if (HAVE_reload_load_address
)
8716 emit_insn (gen_reload_load_address (out
, in
));
8719 /* Otherwise, just write (set OUT IN) and hope for the best. */
8721 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8723 /* Return the first insn emitted.
8724 We can not just return get_last_insn, because there may have
8725 been multiple instructions emitted. Also note that gen_move_insn may
8726 emit more than one insn itself, so we can not assume that there is one
8727 insn emitted per emit_insn_before call. */
8729 return last
? NEXT_INSN (last
) : get_insns ();
8732 /* Delete a previously made output-reload whose result we now believe
8733 is not needed. First we double-check.
8735 INSN is the insn now being processed.
8736 LAST_RELOAD_REG is the hard register number for which we want to delete
8737 the last output reload.
8738 J is the reload-number that originally used REG. The caller has made
8739 certain that reload J doesn't use REG any longer for input.
8740 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8743 delete_output_reload (rtx insn
, int j
, int last_reload_reg
, rtx new_reload_reg
)
8745 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8746 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8749 int n_inherited
= 0;
8755 /* It is possible that this reload has been only used to set another reload
8756 we eliminated earlier and thus deleted this instruction too. */
8757 if (INSN_DELETED_P (output_reload_insn
))
8760 /* Get the raw pseudo-register referred to. */
8762 while (GET_CODE (reg
) == SUBREG
)
8763 reg
= SUBREG_REG (reg
);
8764 substed
= reg_equiv_memory_loc (REGNO (reg
));
8766 /* This is unsafe if the operand occurs more often in the current
8767 insn than it is inherited. */
8768 for (k
= n_reloads
- 1; k
>= 0; k
--)
8770 rtx reg2
= rld
[k
].in
;
8773 if (MEM_P (reg2
) || reload_override_in
[k
])
8774 reg2
= rld
[k
].in_reg
;
8776 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8777 reg2
= XEXP (rld
[k
].in_reg
, 0);
8779 while (GET_CODE (reg2
) == SUBREG
)
8780 reg2
= SUBREG_REG (reg2
);
8781 if (rtx_equal_p (reg2
, reg
))
8783 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8789 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8790 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8791 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8794 n_occurrences
+= count_occurrences (PATTERN (insn
),
8795 eliminate_regs (substed
, VOIDmode
,
8797 for (i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8799 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8800 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8802 if (n_occurrences
> n_inherited
)
8805 regno
= REGNO (reg
);
8806 if (regno
>= FIRST_PSEUDO_REGISTER
)
8809 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8811 /* If the pseudo-reg we are reloading is no longer referenced
8812 anywhere between the store into it and here,
8813 and we're within the same basic block, then the value can only
8814 pass through the reload reg and end up here.
8815 Otherwise, give up--return. */
8816 for (i1
= NEXT_INSN (output_reload_insn
);
8817 i1
!= insn
; i1
= NEXT_INSN (i1
))
8819 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8821 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8822 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8824 /* If this is USE in front of INSN, we only have to check that
8825 there are no more references than accounted for by inheritance. */
8826 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8828 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8829 i1
= NEXT_INSN (i1
);
8831 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8837 /* We will be deleting the insn. Remove the spill reg information. */
8838 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8840 spill_reg_store
[last_reload_reg
+ k
] = 0;
8841 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8844 /* The caller has already checked that REG dies or is set in INSN.
8845 It has also checked that we are optimizing, and thus some
8846 inaccuracies in the debugging information are acceptable.
8847 So we could just delete output_reload_insn. But in some cases
8848 we can improve the debugging information without sacrificing
8849 optimization - maybe even improving the code: See if the pseudo
8850 reg has been completely replaced with reload regs. If so, delete
8851 the store insn and forget we had a stack slot for the pseudo. */
8852 if (rld
[j
].out
!= rld
[j
].in
8853 && REG_N_DEATHS (REGNO (reg
)) == 1
8854 && REG_N_SETS (REGNO (reg
)) == 1
8855 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8856 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8860 /* We know that it was used only between here and the beginning of
8861 the current basic block. (We also know that the last use before
8862 INSN was the output reload we are thinking of deleting, but never
8863 mind that.) Search that range; see if any ref remains. */
8864 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8866 rtx set
= single_set (i2
);
8868 /* Uses which just store in the pseudo don't count,
8869 since if they are the only uses, they are dead. */
8870 if (set
!= 0 && SET_DEST (set
) == reg
)
8872 if (LABEL_P (i2
) || JUMP_P (i2
))
8874 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8875 && reg_mentioned_p (reg
, PATTERN (i2
)))
8877 /* Some other ref remains; just delete the output reload we
8879 delete_address_reloads (output_reload_insn
, insn
);
8880 delete_insn (output_reload_insn
);
8885 /* Delete the now-dead stores into this pseudo. Note that this
8886 loop also takes care of deleting output_reload_insn. */
8887 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8889 rtx set
= single_set (i2
);
8891 if (set
!= 0 && SET_DEST (set
) == reg
)
8893 delete_address_reloads (i2
, insn
);
8896 if (LABEL_P (i2
) || JUMP_P (i2
))
8900 /* For the debugging info, say the pseudo lives in this reload reg. */
8901 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8902 if (ira_conflicts_p
)
8903 /* Inform IRA about the change. */
8904 ira_mark_allocation_change (REGNO (reg
));
8905 alter_reg (REGNO (reg
), -1, false);
8909 delete_address_reloads (output_reload_insn
, insn
);
8910 delete_insn (output_reload_insn
);
8914 /* We are going to delete DEAD_INSN. Recursively delete loads of
8915 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8916 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8918 delete_address_reloads (rtx dead_insn
, rtx current_insn
)
8920 rtx set
= single_set (dead_insn
);
8921 rtx set2
, dst
, prev
, next
;
8924 rtx dst
= SET_DEST (set
);
8926 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8928 /* If we deleted the store from a reloaded post_{in,de}c expression,
8929 we can delete the matching adds. */
8930 prev
= PREV_INSN (dead_insn
);
8931 next
= NEXT_INSN (dead_insn
);
8932 if (! prev
|| ! next
)
8934 set
= single_set (next
);
8935 set2
= single_set (prev
);
8937 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8938 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8939 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8941 dst
= SET_DEST (set
);
8942 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8943 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8944 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8945 || (INTVAL (XEXP (SET_SRC (set
), 1))
8946 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8948 delete_related_insns (prev
);
8949 delete_related_insns (next
);
8952 /* Subfunction of delete_address_reloads: process registers found in X. */
8954 delete_address_reloads_1 (rtx dead_insn
, rtx x
, rtx current_insn
)
8956 rtx prev
, set
, dst
, i2
;
8958 enum rtx_code code
= GET_CODE (x
);
8962 const char *fmt
= GET_RTX_FORMAT (code
);
8963 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8966 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8967 else if (fmt
[i
] == 'E')
8969 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8970 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8977 if (spill_reg_order
[REGNO (x
)] < 0)
8980 /* Scan backwards for the insn that sets x. This might be a way back due
8982 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8984 code
= GET_CODE (prev
);
8985 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8989 if (reg_set_p (x
, PATTERN (prev
)))
8991 if (reg_referenced_p (x
, PATTERN (prev
)))
8994 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8996 /* Check that PREV only sets the reload register. */
8997 set
= single_set (prev
);
9000 dst
= SET_DEST (set
);
9002 || ! rtx_equal_p (dst
, x
))
9004 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9006 /* Check if DST was used in a later insn -
9007 it might have been inherited. */
9008 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9014 if (reg_referenced_p (dst
, PATTERN (i2
)))
9016 /* If there is a reference to the register in the current insn,
9017 it might be loaded in a non-inherited reload. If no other
9018 reload uses it, that means the register is set before
9020 if (i2
== current_insn
)
9022 for (j
= n_reloads
- 1; j
>= 0; j
--)
9023 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9024 || reload_override_in
[j
] == dst
)
9026 for (j
= n_reloads
- 1; j
>= 0; j
--)
9027 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9036 /* If DST is still live at CURRENT_INSN, check if it is used for
9037 any reload. Note that even if CURRENT_INSN sets DST, we still
9038 have to check the reloads. */
9039 if (i2
== current_insn
)
9041 for (j
= n_reloads
- 1; j
>= 0; j
--)
9042 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9043 || reload_override_in
[j
] == dst
)
9045 /* ??? We can't finish the loop here, because dst might be
9046 allocated to a pseudo in this block if no reload in this
9047 block needs any of the classes containing DST - see
9048 spill_hard_reg. There is no easy way to tell this, so we
9049 have to scan till the end of the basic block. */
9051 if (reg_set_p (dst
, PATTERN (i2
)))
9055 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9056 reg_reloaded_contents
[REGNO (dst
)] = -1;
9060 /* Output reload-insns to reload VALUE into RELOADREG.
9061 VALUE is an autoincrement or autodecrement RTX whose operand
9062 is a register or memory location;
9063 so reloading involves incrementing that location.
9064 IN is either identical to VALUE, or some cheaper place to reload from.
9066 INC_AMOUNT is the number to increment or decrement by (always positive).
9067 This cannot be deduced from VALUE. */
9070 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9072 /* REG or MEM to be copied and incremented. */
9073 rtx incloc
= find_replacement (&XEXP (value
, 0));
9074 /* Nonzero if increment after copying. */
9075 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9076 || GET_CODE (value
) == POST_MODIFY
);
9081 rtx real_in
= in
== value
? incloc
: in
;
9083 /* No hard register is equivalent to this register after
9084 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9085 we could inc/dec that register as well (maybe even using it for
9086 the source), but I'm not sure it's worth worrying about. */
9088 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9090 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9092 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9093 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9097 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9098 inc_amount
= -inc_amount
;
9100 inc
= GEN_INT (inc_amount
);
9103 /* If this is post-increment, first copy the location to the reload reg. */
9104 if (post
&& real_in
!= reloadreg
)
9105 emit_insn (gen_move_insn (reloadreg
, real_in
));
9109 /* See if we can directly increment INCLOC. Use a method similar to
9110 that in gen_reload. */
9112 last
= get_last_insn ();
9113 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
9114 gen_rtx_PLUS (GET_MODE (incloc
),
9117 code
= recog_memoized (add_insn
);
9120 extract_insn (add_insn
);
9121 if (constrain_operands (1))
9123 /* If this is a pre-increment and we have incremented the value
9124 where it lives, copy the incremented value to RELOADREG to
9125 be used as an address. */
9128 emit_insn (gen_move_insn (reloadreg
, incloc
));
9132 delete_insns_since (last
);
9135 /* If couldn't do the increment directly, must increment in RELOADREG.
9136 The way we do this depends on whether this is pre- or post-increment.
9137 For pre-increment, copy INCLOC to the reload register, increment it
9138 there, then save back. */
9142 if (in
!= reloadreg
)
9143 emit_insn (gen_move_insn (reloadreg
, real_in
));
9144 emit_insn (gen_add2_insn (reloadreg
, inc
));
9145 emit_insn (gen_move_insn (incloc
, reloadreg
));
9150 Because this might be a jump insn or a compare, and because RELOADREG
9151 may not be available after the insn in an input reload, we must do
9152 the incrementation before the insn being reloaded for.
9154 We have already copied IN to RELOADREG. Increment the copy in
9155 RELOADREG, save that back, then decrement RELOADREG so it has
9156 the original value. */
9158 emit_insn (gen_add2_insn (reloadreg
, inc
));
9159 emit_insn (gen_move_insn (incloc
, reloadreg
));
9160 if (CONST_INT_P (inc
))
9161 emit_insn (gen_add2_insn (reloadreg
,
9162 gen_int_mode (-INTVAL (inc
),
9163 GET_MODE (reloadreg
))));
9165 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9171 add_auto_inc_notes (rtx insn
, rtx x
)
9173 enum rtx_code code
= GET_CODE (x
);
9177 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9179 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9183 /* Scan all the operand sub-expressions. */
9184 fmt
= GET_RTX_FORMAT (code
);
9185 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9188 add_auto_inc_notes (insn
, XEXP (x
, i
));
9189 else if (fmt
[i
] == 'E')
9190 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9191 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));