1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
86 #include "double-int.h"
93 #include "stor-layout.h"
97 #include "hard-reg-set.h"
100 #include "dominance.h"
103 #include "cfgcleanup.h"
104 #include "basic-block.h"
105 #include "insn-config.h"
106 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 #include "statistics.h"
110 #include "fixed-value.h"
115 #include "emit-rtl.h"
119 #include "insn-attr.h"
121 #include "diagnostic-core.h"
123 #include "insn-codes.h"
125 #include "rtlhooks-def.h"
127 #include "tree-pass.h"
129 #include "valtrack.h"
130 #include "hash-map.h"
132 #include "plugin-api.h"
136 #include "rtl-iter.h"
138 /* Number of attempts to combine instructions in this function. */
140 static int combine_attempts
;
142 /* Number of attempts that got as far as substitution in this function. */
144 static int combine_merges
;
146 /* Number of instructions combined with added SETs in this function. */
148 static int combine_extras
;
150 /* Number of instructions combined in this function. */
152 static int combine_successes
;
154 /* Totals over entire compilation. */
156 static int total_attempts
, total_merges
, total_extras
, total_successes
;
158 /* combine_instructions may try to replace the right hand side of the
159 second instruction with the value of an associated REG_EQUAL note
160 before throwing it at try_combine. That is problematic when there
161 is a REG_DEAD note for a register used in the old right hand side
162 and can cause distribute_notes to do wrong things. This is the
163 second instruction if it has been so modified, null otherwise. */
165 static rtx_insn
*i2mod
;
167 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
169 static rtx i2mod_old_rhs
;
171 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
173 static rtx i2mod_new_rhs
;
175 typedef struct reg_stat_struct
{
176 /* Record last point of death of (hard or pseudo) register n. */
177 rtx_insn
*last_death
;
179 /* Record last point of modification of (hard or pseudo) register n. */
182 /* The next group of fields allows the recording of the last value assigned
183 to (hard or pseudo) register n. We use this information to see if an
184 operation being processed is redundant given a prior operation performed
185 on the register. For example, an `and' with a constant is redundant if
186 all the zero bits are already known to be turned off.
188 We use an approach similar to that used by cse, but change it in the
191 (1) We do not want to reinitialize at each label.
192 (2) It is useful, but not critical, to know the actual value assigned
193 to a register. Often just its form is helpful.
195 Therefore, we maintain the following fields:
197 last_set_value the last value assigned
198 last_set_label records the value of label_tick when the
199 register was assigned
200 last_set_table_tick records the value of label_tick when a
201 value using the register is assigned
202 last_set_invalid set to nonzero when it is not valid
203 to use the value of this register in some
206 To understand the usage of these tables, it is important to understand
207 the distinction between the value in last_set_value being valid and
208 the register being validly contained in some other expression in the
211 (The next two parameters are out of date).
213 reg_stat[i].last_set_value is valid if it is nonzero, and either
214 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
216 Register I may validly appear in any expression returned for the value
217 of another register if reg_n_sets[i] is 1. It may also appear in the
218 value for register J if reg_stat[j].last_set_invalid is zero, or
219 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
221 If an expression is found in the table containing a register which may
222 not validly appear in an expression, the register is replaced by
223 something that won't match, (clobber (const_int 0)). */
225 /* Record last value assigned to (hard or pseudo) register n. */
229 /* Record the value of label_tick when an expression involving register n
230 is placed in last_set_value. */
232 int last_set_table_tick
;
234 /* Record the value of label_tick when the value for register n is placed in
239 /* These fields are maintained in parallel with last_set_value and are
240 used to store the mode in which the register was last set, the bits
241 that were known to be zero when it was last set, and the number of
242 sign bits copies it was known to have when it was last set. */
244 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
245 char last_set_sign_bit_copies
;
246 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
248 /* Set nonzero if references to register n in expressions should not be
249 used. last_set_invalid is set nonzero when this register is being
250 assigned to and last_set_table_tick == label_tick. */
252 char last_set_invalid
;
254 /* Some registers that are set more than once and used in more than one
255 basic block are nevertheless always set in similar ways. For example,
256 a QImode register may be loaded from memory in two places on a machine
257 where byte loads zero extend.
259 We record in the following fields if a register has some leading bits
260 that are always equal to the sign bit, and what we know about the
261 nonzero bits of a register, specifically which bits are known to be
264 If an entry is zero, it means that we don't know anything special. */
266 unsigned char sign_bit_copies
;
268 unsigned HOST_WIDE_INT nonzero_bits
;
270 /* Record the value of the label_tick when the last truncation
271 happened. The field truncated_to_mode is only valid if
272 truncation_label == label_tick. */
274 int truncation_label
;
276 /* Record the last truncation seen for this register. If truncation
277 is not a nop to this mode we might be able to save an explicit
278 truncation if we know that value already contains a truncated
281 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
285 static vec
<reg_stat_type
> reg_stat
;
287 /* One plus the highest pseudo for which we track REG_N_SETS.
288 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
289 but during combine_split_insns new pseudos can be created. As we don't have
290 updated DF information in that case, it is hard to initialize the array
291 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
292 so instead of growing the arrays, just assume all newly created pseudos
293 during combine might be set multiple times. */
295 static unsigned int reg_n_sets_max
;
297 /* Record the luid of the last insn that invalidated memory
298 (anything that writes memory, and subroutine calls, but not pushes). */
300 static int mem_last_set
;
302 /* Record the luid of the last CALL_INSN
303 so we can tell whether a potential combination crosses any calls. */
305 static int last_call_luid
;
307 /* When `subst' is called, this is the insn that is being modified
308 (by combining in a previous insn). The PATTERN of this insn
309 is still the old pattern partially modified and it should not be
310 looked at, but this may be used to examine the successors of the insn
311 to judge whether a simplification is valid. */
313 static rtx_insn
*subst_insn
;
315 /* This is the lowest LUID that `subst' is currently dealing with.
316 get_last_value will not return a value if the register was set at or
317 after this LUID. If not for this mechanism, we could get confused if
318 I2 or I1 in try_combine were an insn that used the old value of a register
319 to obtain a new value. In that case, we might erroneously get the
320 new value of the register when we wanted the old one. */
322 static int subst_low_luid
;
324 /* This contains any hard registers that are used in newpat; reg_dead_at_p
325 must consider all these registers to be always live. */
327 static HARD_REG_SET newpat_used_regs
;
329 /* This is an insn to which a LOG_LINKS entry has been added. If this
330 insn is the earlier than I2 or I3, combine should rescan starting at
333 static rtx_insn
*added_links_insn
;
335 /* Basic block in which we are performing combines. */
336 static basic_block this_basic_block
;
337 static bool optimize_this_for_speed_p
;
340 /* Length of the currently allocated uid_insn_cost array. */
342 static int max_uid_known
;
344 /* The following array records the insn_rtx_cost for every insn
345 in the instruction stream. */
347 static int *uid_insn_cost
;
349 /* The following array records the LOG_LINKS for every insn in the
350 instruction stream as struct insn_link pointers. */
355 struct insn_link
*next
;
358 static struct insn_link
**uid_log_links
;
360 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
361 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
363 #define FOR_EACH_LOG_LINK(L, INSN) \
364 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
366 /* Links for LOG_LINKS are allocated from this obstack. */
368 static struct obstack insn_link_obstack
;
370 /* Allocate a link. */
372 static inline struct insn_link
*
373 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
376 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
377 sizeof (struct insn_link
));
384 /* Incremented for each basic block. */
386 static int label_tick
;
388 /* Reset to label_tick for each extended basic block in scanning order. */
390 static int label_tick_ebb_start
;
392 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
393 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
395 static machine_mode nonzero_bits_mode
;
397 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
398 be safely used. It is zero while computing them and after combine has
399 completed. This former test prevents propagating values based on
400 previously set values, which can be incorrect if a variable is modified
403 static int nonzero_sign_valid
;
406 /* Record one modification to rtl structure
407 to be undone by storing old_contents into *where. */
409 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
415 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
416 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
419 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
420 num_undo says how many are currently recorded.
422 other_insn is nonzero if we have modified some other insn in the process
423 of working on subst_insn. It must be verified too. */
429 rtx_insn
*other_insn
;
432 static struct undobuf undobuf
;
434 /* Number of times the pseudo being substituted for
435 was found and replaced. */
437 static int n_occurrences
;
439 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
441 unsigned HOST_WIDE_INT
,
442 unsigned HOST_WIDE_INT
*);
443 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
445 unsigned int, unsigned int *);
446 static void do_SUBST (rtx
*, rtx
);
447 static void do_SUBST_INT (int *, int);
448 static void init_reg_last (void);
449 static void setup_incoming_promotions (rtx_insn
*);
450 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
451 static int cant_combine_insn_p (rtx_insn
*);
452 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
453 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
454 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
455 static int contains_muldiv (rtx
);
456 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
458 static void undo_all (void);
459 static void undo_commit (void);
460 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
461 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
462 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
463 static rtx
simplify_if_then_else (rtx
);
464 static rtx
simplify_set (rtx
);
465 static rtx
simplify_logical (rtx
);
466 static rtx
expand_compound_operation (rtx
);
467 static const_rtx
expand_field_assignment (const_rtx
);
468 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
469 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
470 static rtx
extract_left_shift (rtx
, int);
471 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
472 unsigned HOST_WIDE_INT
*);
473 static rtx
canon_reg_for_combine (rtx
, rtx
);
474 static rtx
force_to_mode (rtx
, machine_mode
,
475 unsigned HOST_WIDE_INT
, int);
476 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
477 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
478 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
479 static rtx
make_field_assignment (rtx
);
480 static rtx
apply_distributive_law (rtx
);
481 static rtx
distribute_and_simplify_rtx (rtx
, int);
482 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
483 unsigned HOST_WIDE_INT
);
484 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
485 unsigned HOST_WIDE_INT
);
486 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
487 HOST_WIDE_INT
, machine_mode
, int *);
488 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
489 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
491 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
492 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
493 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
495 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
496 static void update_table_tick (rtx
);
497 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
498 static void check_promoted_subreg (rtx_insn
*, rtx
);
499 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
500 static void record_dead_and_set_regs (rtx_insn
*);
501 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
502 static rtx
get_last_value (const_rtx
);
503 static int use_crosses_set_p (const_rtx
, int);
504 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
505 static int reg_dead_at_p (rtx
, rtx_insn
*);
506 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
507 static int reg_bitfield_target_p (rtx
, rtx
);
508 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
509 static void distribute_links (struct insn_link
*);
510 static void mark_used_regs_combine (rtx
);
511 static void record_promoted_value (rtx_insn
*, rtx
);
512 static bool unmentioned_reg_p (rtx
, rtx
);
513 static void record_truncated_values (rtx
*, void *);
514 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
515 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
518 /* It is not safe to use ordinary gen_lowpart in combine.
519 See comments in gen_lowpart_for_combine. */
520 #undef RTL_HOOKS_GEN_LOWPART
521 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
523 /* Our implementation of gen_lowpart never emits a new pseudo. */
524 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
525 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
527 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
528 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
530 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
531 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
533 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
534 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
536 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
539 /* Convenience wrapper for the canonicalize_comparison target hook.
540 Target hooks cannot use enum rtx_code. */
542 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
543 bool op0_preserve_value
)
545 int code_int
= (int)*code
;
546 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
547 *code
= (enum rtx_code
)code_int
;
550 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
551 PATTERN can not be split. Otherwise, it returns an insn sequence.
552 This is a wrapper around split_insns which ensures that the
553 reg_stat vector is made larger if the splitter creates a new
557 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
562 ret
= safe_as_a
<rtx_insn
*> (split_insns (pattern
, insn
));
563 nregs
= max_reg_num ();
564 if (nregs
> reg_stat
.length ())
565 reg_stat
.safe_grow_cleared (nregs
);
569 /* This is used by find_single_use to locate an rtx in LOC that
570 contains exactly one use of DEST, which is typically either a REG
571 or CC0. It returns a pointer to the innermost rtx expression
572 containing DEST. Appearances of DEST that are being used to
573 totally replace it are not counted. */
576 find_single_use_1 (rtx dest
, rtx
*loc
)
579 enum rtx_code code
= GET_CODE (x
);
595 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
596 of a REG that occupies all of the REG, the insn uses DEST if
597 it is mentioned in the destination or the source. Otherwise, we
598 need just check the source. */
599 if (GET_CODE (SET_DEST (x
)) != CC0
600 && GET_CODE (SET_DEST (x
)) != PC
601 && !REG_P (SET_DEST (x
))
602 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
603 && REG_P (SUBREG_REG (SET_DEST (x
)))
604 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
605 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
606 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
607 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
610 return find_single_use_1 (dest
, &SET_SRC (x
));
614 return find_single_use_1 (dest
, &XEXP (x
, 0));
620 /* If it wasn't one of the common cases above, check each expression and
621 vector of this code. Look for a unique usage of DEST. */
623 fmt
= GET_RTX_FORMAT (code
);
624 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
628 if (dest
== XEXP (x
, i
)
629 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
630 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
633 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
636 result
= this_result
;
637 else if (this_result
)
638 /* Duplicate usage. */
641 else if (fmt
[i
] == 'E')
645 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
647 if (XVECEXP (x
, i
, j
) == dest
649 && REG_P (XVECEXP (x
, i
, j
))
650 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
653 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
656 result
= this_result
;
657 else if (this_result
)
667 /* See if DEST, produced in INSN, is used only a single time in the
668 sequel. If so, return a pointer to the innermost rtx expression in which
671 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
673 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
674 care about REG_DEAD notes or LOG_LINKS.
676 Otherwise, we find the single use by finding an insn that has a
677 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
678 only referenced once in that insn, we know that it must be the first
679 and last insn referencing DEST. */
682 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
687 struct insn_link
*link
;
691 next
= NEXT_INSN (insn
);
693 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
696 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 bb
= BLOCK_FOR_INSN (insn
);
706 for (next
= NEXT_INSN (insn
);
707 next
&& BLOCK_FOR_INSN (next
) == bb
;
708 next
= NEXT_INSN (next
))
709 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
711 FOR_EACH_LOG_LINK (link
, next
)
712 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
717 result
= find_single_use_1 (dest
, &PATTERN (next
));
727 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
728 insn. The substitution can be undone by undo_all. If INTO is already
729 set to NEWVAL, do not record this change. Because computing NEWVAL might
730 also call SUBST, we have to compute it before we put anything into
734 do_SUBST (rtx
*into
, rtx newval
)
739 if (oldval
== newval
)
742 /* We'd like to catch as many invalid transformations here as
743 possible. Unfortunately, there are way too many mode changes
744 that are perfectly valid, so we'd waste too much effort for
745 little gain doing the checks here. Focus on catching invalid
746 transformations involving integer constants. */
747 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
748 && CONST_INT_P (newval
))
750 /* Sanity check that we're replacing oldval with a CONST_INT
751 that is a valid sign-extension for the original mode. */
752 gcc_assert (INTVAL (newval
)
753 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
755 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
756 CONST_INT is not valid, because after the replacement, the
757 original mode would be gone. Unfortunately, we can't tell
758 when do_SUBST is called to replace the operand thereof, so we
759 perform this test on oldval instead, checking whether an
760 invalid replacement took place before we got here. */
761 gcc_assert (!(GET_CODE (oldval
) == SUBREG
762 && CONST_INT_P (SUBREG_REG (oldval
))));
763 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
764 && CONST_INT_P (XEXP (oldval
, 0))));
768 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
770 buf
= XNEW (struct undo
);
772 buf
->kind
= UNDO_RTX
;
774 buf
->old_contents
.r
= oldval
;
777 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
780 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
782 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
783 for the value of a HOST_WIDE_INT value (including CONST_INT) is
787 do_SUBST_INT (int *into
, int newval
)
792 if (oldval
== newval
)
796 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
798 buf
= XNEW (struct undo
);
800 buf
->kind
= UNDO_INT
;
802 buf
->old_contents
.i
= oldval
;
805 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
808 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
810 /* Similar to SUBST, but just substitute the mode. This is used when
811 changing the mode of a pseudo-register, so that any other
812 references to the entry in the regno_reg_rtx array will change as
816 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
819 machine_mode oldval
= GET_MODE (*into
);
821 if (oldval
== newval
)
825 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
827 buf
= XNEW (struct undo
);
829 buf
->kind
= UNDO_MODE
;
831 buf
->old_contents
.m
= oldval
;
832 adjust_reg_mode (*into
, newval
);
834 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
837 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
840 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
843 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
846 struct insn_link
* oldval
= *into
;
848 if (oldval
== newval
)
852 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
854 buf
= XNEW (struct undo
);
856 buf
->kind
= UNDO_LINKS
;
858 buf
->old_contents
.l
= oldval
;
861 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
864 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
867 /* Subroutine of try_combine. Determine whether the replacement patterns
868 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
869 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
870 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
871 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
872 of all the instructions can be estimated and the replacements are more
873 expensive than the original sequence. */
876 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
877 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
879 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
880 int new_i2_cost
, new_i3_cost
;
881 int old_cost
, new_cost
;
883 /* Lookup the original insn_rtx_costs. */
884 i2_cost
= INSN_COST (i2
);
885 i3_cost
= INSN_COST (i3
);
889 i1_cost
= INSN_COST (i1
);
892 i0_cost
= INSN_COST (i0
);
893 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
894 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
898 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
899 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
905 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
906 i1_cost
= i0_cost
= 0;
909 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
911 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
915 /* Calculate the replacement insn_rtx_costs. */
916 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
919 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
920 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
921 ? new_i2_cost
+ new_i3_cost
: 0;
925 new_cost
= new_i3_cost
;
929 if (undobuf
.other_insn
)
931 int old_other_cost
, new_other_cost
;
933 old_other_cost
= INSN_COST (undobuf
.other_insn
);
934 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
935 if (old_other_cost
> 0 && new_other_cost
> 0)
937 old_cost
+= old_other_cost
;
938 new_cost
+= new_other_cost
;
944 /* Disallow this combination if both new_cost and old_cost are greater than
945 zero, and new_cost is greater than old cost. */
946 int reject
= old_cost
> 0 && new_cost
> old_cost
;
950 fprintf (dump_file
, "%s combination of insns ",
951 reject
? "rejecting" : "allowing");
953 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
954 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
955 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
956 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
958 fprintf (dump_file
, "original costs ");
960 fprintf (dump_file
, "%d + ", i0_cost
);
961 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
962 fprintf (dump_file
, "%d + ", i1_cost
);
963 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
966 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
967 new_i2_cost
, new_i3_cost
, new_cost
);
969 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
975 /* Update the uid_insn_cost array with the replacement costs. */
976 INSN_COST (i2
) = new_i2_cost
;
977 INSN_COST (i3
) = new_i3_cost
;
989 /* Delete any insns that copy a register to itself. */
992 delete_noop_moves (void)
994 rtx_insn
*insn
, *next
;
997 FOR_EACH_BB_FN (bb
, cfun
)
999 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
1001 next
= NEXT_INSN (insn
);
1002 if (INSN_P (insn
) && noop_move_p (insn
))
1005 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
1007 delete_insn_and_edges (insn
);
1014 /* Return false if we do not want to (or cannot) combine DEF. */
1016 can_combine_def_p (df_ref def
)
1018 /* Do not consider if it is pre/post modification in MEM. */
1019 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1022 unsigned int regno
= DF_REF_REGNO (def
);
1024 /* Do not combine frame pointer adjustments. */
1025 if ((regno
== FRAME_POINTER_REGNUM
1026 && (!reload_completed
|| frame_pointer_needed
))
1027 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1028 || (regno
== HARD_FRAME_POINTER_REGNUM
1029 && (!reload_completed
|| frame_pointer_needed
))
1031 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1032 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1038 /* Return false if we do not want to (or cannot) combine USE. */
1040 can_combine_use_p (df_ref use
)
1042 /* Do not consider the usage of the stack pointer by function call. */
1043 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1049 /* Fill in log links field for all insns. */
1052 create_log_links (void)
1055 rtx_insn
**next_use
;
1059 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1061 /* Pass through each block from the end, recording the uses of each
1062 register and establishing log links when def is encountered.
1063 Note that we do not clear next_use array in order to save time,
1064 so we have to test whether the use is in the same basic block as def.
1066 There are a few cases below when we do not consider the definition or
1067 usage -- these are taken from original flow.c did. Don't ask me why it is
1068 done this way; I don't know and if it works, I don't want to know. */
1070 FOR_EACH_BB_FN (bb
, cfun
)
1072 FOR_BB_INSNS_REVERSE (bb
, insn
)
1074 if (!NONDEBUG_INSN_P (insn
))
1077 /* Log links are created only once. */
1078 gcc_assert (!LOG_LINKS (insn
));
1080 FOR_EACH_INSN_DEF (def
, insn
)
1082 unsigned int regno
= DF_REF_REGNO (def
);
1085 if (!next_use
[regno
])
1088 if (!can_combine_def_p (def
))
1091 use_insn
= next_use
[regno
];
1092 next_use
[regno
] = NULL
;
1094 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1099 We don't build a LOG_LINK for hard registers contained
1100 in ASM_OPERANDs. If these registers get replaced,
1101 we might wind up changing the semantics of the insn,
1102 even if reload can make what appear to be valid
1103 assignments later. */
1104 if (regno
< FIRST_PSEUDO_REGISTER
1105 && asm_noperands (PATTERN (use_insn
)) >= 0)
1108 /* Don't add duplicate links between instructions. */
1109 struct insn_link
*links
;
1110 FOR_EACH_LOG_LINK (links
, use_insn
)
1111 if (insn
== links
->insn
&& regno
== links
->regno
)
1115 LOG_LINKS (use_insn
)
1116 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1119 FOR_EACH_INSN_USE (use
, insn
)
1120 if (can_combine_use_p (use
))
1121 next_use
[DF_REF_REGNO (use
)] = insn
;
1128 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1129 true if we found a LOG_LINK that proves that A feeds B. This only works
1130 if there are no instructions between A and B which could have a link
1131 depending on A, since in that case we would not record a link for B.
1132 We also check the implicit dependency created by a cc0 setter/user
1136 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1138 struct insn_link
*links
;
1139 FOR_EACH_LOG_LINK (links
, b
)
1140 if (links
->insn
== a
)
1142 if (HAVE_cc0
&& sets_cc0_p (a
))
1147 /* Main entry point for combiner. F is the first insn of the function.
1148 NREGS is the first unused pseudo-reg number.
1150 Return nonzero if the combiner has turned an indirect jump
1151 instruction into a direct jump. */
1153 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1155 rtx_insn
*insn
, *next
;
1159 struct insn_link
*links
, *nextlinks
;
1161 basic_block last_bb
;
1163 int new_direct_jump_p
= 0;
1165 for (first
= f
; first
&& !INSN_P (first
); )
1166 first
= NEXT_INSN (first
);
1170 combine_attempts
= 0;
1173 combine_successes
= 0;
1175 rtl_hooks
= combine_rtl_hooks
;
1177 reg_stat
.safe_grow_cleared (nregs
);
1179 init_recog_no_volatile ();
1181 /* Allocate array for insn info. */
1182 max_uid_known
= get_max_uid ();
1183 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1184 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1185 gcc_obstack_init (&insn_link_obstack
);
1187 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1189 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1190 problems when, for example, we have j <<= 1 in a loop. */
1192 nonzero_sign_valid
= 0;
1193 label_tick
= label_tick_ebb_start
= 1;
1195 /* Scan all SETs and see if we can deduce anything about what
1196 bits are known to be zero for some registers and how many copies
1197 of the sign bit are known to exist for those registers.
1199 Also set any known values so that we can use it while searching
1200 for what bits are known to be set. */
1202 setup_incoming_promotions (first
);
1203 /* Allow the entry block and the first block to fall into the same EBB.
1204 Conceptually the incoming promotions are assigned to the entry block. */
1205 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1207 create_log_links ();
1208 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1210 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1215 if (!single_pred_p (this_basic_block
)
1216 || single_pred (this_basic_block
) != last_bb
)
1217 label_tick_ebb_start
= label_tick
;
1218 last_bb
= this_basic_block
;
1220 FOR_BB_INSNS (this_basic_block
, insn
)
1221 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1227 subst_low_luid
= DF_INSN_LUID (insn
);
1230 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1232 record_dead_and_set_regs (insn
);
1235 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1236 if (REG_NOTE_KIND (links
) == REG_INC
)
1237 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1241 /* Record the current insn_rtx_cost of this instruction. */
1242 if (NONJUMP_INSN_P (insn
))
1243 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1244 optimize_this_for_speed_p
);
1246 fprintf (dump_file
, "insn_cost %d: %d\n",
1247 INSN_UID (insn
), INSN_COST (insn
));
1251 nonzero_sign_valid
= 1;
1253 /* Now scan all the insns in forward order. */
1254 label_tick
= label_tick_ebb_start
= 1;
1256 setup_incoming_promotions (first
);
1257 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1258 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1260 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1262 rtx_insn
*last_combined_insn
= NULL
;
1263 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1268 if (!single_pred_p (this_basic_block
)
1269 || single_pred (this_basic_block
) != last_bb
)
1270 label_tick_ebb_start
= label_tick
;
1271 last_bb
= this_basic_block
;
1273 rtl_profile_for_bb (this_basic_block
);
1274 for (insn
= BB_HEAD (this_basic_block
);
1275 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1276 insn
= next
? next
: NEXT_INSN (insn
))
1279 if (!NONDEBUG_INSN_P (insn
))
1282 while (last_combined_insn
1283 && last_combined_insn
->deleted ())
1284 last_combined_insn
= PREV_INSN (last_combined_insn
);
1285 if (last_combined_insn
== NULL_RTX
1286 || BARRIER_P (last_combined_insn
)
1287 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1288 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1289 last_combined_insn
= insn
;
1291 /* See if we know about function return values before this
1292 insn based upon SUBREG flags. */
1293 check_promoted_subreg (insn
, PATTERN (insn
));
1295 /* See if we can find hardregs and subreg of pseudos in
1296 narrower modes. This could help turning TRUNCATEs
1298 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1300 /* Try this insn with each insn it links back to. */
1302 FOR_EACH_LOG_LINK (links
, insn
)
1303 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1304 NULL
, &new_direct_jump_p
,
1305 last_combined_insn
)) != 0)
1307 statistics_counter_event (cfun
, "two-insn combine", 1);
1311 /* Try each sequence of three linked insns ending with this one. */
1313 if (max_combine
>= 3)
1314 FOR_EACH_LOG_LINK (links
, insn
)
1316 rtx_insn
*link
= links
->insn
;
1318 /* If the linked insn has been replaced by a note, then there
1319 is no point in pursuing this chain any further. */
1323 FOR_EACH_LOG_LINK (nextlinks
, link
)
1324 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1325 NULL
, &new_direct_jump_p
,
1326 last_combined_insn
)) != 0)
1328 statistics_counter_event (cfun
, "three-insn combine", 1);
1334 /* Try to combine a jump insn that uses CC0
1335 with a preceding insn that sets CC0, and maybe with its
1336 logical predecessor as well.
1337 This is how we make decrement-and-branch insns.
1338 We need this special code because data flow connections
1339 via CC0 do not get entered in LOG_LINKS. */
1342 && (prev
= prev_nonnote_insn (insn
)) != 0
1343 && NONJUMP_INSN_P (prev
)
1344 && sets_cc0_p (PATTERN (prev
)))
1346 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1348 last_combined_insn
)) != 0)
1351 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1352 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1353 NULL
, &new_direct_jump_p
,
1354 last_combined_insn
)) != 0)
1358 /* Do the same for an insn that explicitly references CC0. */
1359 if (NONJUMP_INSN_P (insn
)
1360 && (prev
= prev_nonnote_insn (insn
)) != 0
1361 && NONJUMP_INSN_P (prev
)
1362 && sets_cc0_p (PATTERN (prev
))
1363 && GET_CODE (PATTERN (insn
)) == SET
1364 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1366 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1368 last_combined_insn
)) != 0)
1371 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1372 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1373 NULL
, &new_direct_jump_p
,
1374 last_combined_insn
)) != 0)
1378 /* Finally, see if any of the insns that this insn links to
1379 explicitly references CC0. If so, try this insn, that insn,
1380 and its predecessor if it sets CC0. */
1381 FOR_EACH_LOG_LINK (links
, insn
)
1382 if (NONJUMP_INSN_P (links
->insn
)
1383 && GET_CODE (PATTERN (links
->insn
)) == SET
1384 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1385 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1386 && NONJUMP_INSN_P (prev
)
1387 && sets_cc0_p (PATTERN (prev
))
1388 && (next
= try_combine (insn
, links
->insn
,
1389 prev
, NULL
, &new_direct_jump_p
,
1390 last_combined_insn
)) != 0)
1394 /* Try combining an insn with two different insns whose results it
1396 if (max_combine
>= 3)
1397 FOR_EACH_LOG_LINK (links
, insn
)
1398 for (nextlinks
= links
->next
; nextlinks
;
1399 nextlinks
= nextlinks
->next
)
1400 if ((next
= try_combine (insn
, links
->insn
,
1401 nextlinks
->insn
, NULL
,
1403 last_combined_insn
)) != 0)
1406 statistics_counter_event (cfun
, "three-insn combine", 1);
1410 /* Try four-instruction combinations. */
1411 if (max_combine
>= 4)
1412 FOR_EACH_LOG_LINK (links
, insn
)
1414 struct insn_link
*next1
;
1415 rtx_insn
*link
= links
->insn
;
1417 /* If the linked insn has been replaced by a note, then there
1418 is no point in pursuing this chain any further. */
1422 FOR_EACH_LOG_LINK (next1
, link
)
1424 rtx_insn
*link1
= next1
->insn
;
1427 /* I0 -> I1 -> I2 -> I3. */
1428 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1429 if ((next
= try_combine (insn
, link
, link1
,
1432 last_combined_insn
)) != 0)
1434 statistics_counter_event (cfun
, "four-insn combine", 1);
1437 /* I0, I1 -> I2, I2 -> I3. */
1438 for (nextlinks
= next1
->next
; nextlinks
;
1439 nextlinks
= nextlinks
->next
)
1440 if ((next
= try_combine (insn
, link
, link1
,
1443 last_combined_insn
)) != 0)
1445 statistics_counter_event (cfun
, "four-insn combine", 1);
1450 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1452 rtx_insn
*link1
= next1
->insn
;
1455 /* I0 -> I2; I1, I2 -> I3. */
1456 FOR_EACH_LOG_LINK (nextlinks
, link
)
1457 if ((next
= try_combine (insn
, link
, link1
,
1460 last_combined_insn
)) != 0)
1462 statistics_counter_event (cfun
, "four-insn combine", 1);
1465 /* I0 -> I1; I1, I2 -> I3. */
1466 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1467 if ((next
= try_combine (insn
, link
, link1
,
1470 last_combined_insn
)) != 0)
1472 statistics_counter_event (cfun
, "four-insn combine", 1);
1478 /* Try this insn with each REG_EQUAL note it links back to. */
1479 FOR_EACH_LOG_LINK (links
, insn
)
1482 rtx_insn
*temp
= links
->insn
;
1483 if ((set
= single_set (temp
)) != 0
1484 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1485 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1486 /* Avoid using a register that may already been marked
1487 dead by an earlier instruction. */
1488 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1489 && (GET_MODE (note
) == VOIDmode
1490 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1491 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1493 /* Temporarily replace the set's source with the
1494 contents of the REG_EQUAL note. The insn will
1495 be deleted or recognized by try_combine. */
1496 rtx orig
= SET_SRC (set
);
1497 SET_SRC (set
) = note
;
1499 i2mod_old_rhs
= copy_rtx (orig
);
1500 i2mod_new_rhs
= copy_rtx (note
);
1501 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1503 last_combined_insn
);
1507 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1510 SET_SRC (set
) = orig
;
1515 record_dead_and_set_regs (insn
);
1522 default_rtl_profile ();
1524 new_direct_jump_p
|= purge_all_dead_edges ();
1525 delete_noop_moves ();
1528 obstack_free (&insn_link_obstack
, NULL
);
1529 free (uid_log_links
);
1530 free (uid_insn_cost
);
1531 reg_stat
.release ();
1534 struct undo
*undo
, *next
;
1535 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1543 total_attempts
+= combine_attempts
;
1544 total_merges
+= combine_merges
;
1545 total_extras
+= combine_extras
;
1546 total_successes
+= combine_successes
;
1548 nonzero_sign_valid
= 0;
1549 rtl_hooks
= general_rtl_hooks
;
1551 /* Make recognizer allow volatile MEMs again. */
1554 return new_direct_jump_p
;
1557 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1560 init_reg_last (void)
1565 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1566 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1569 /* Set up any promoted values for incoming argument registers. */
1572 setup_incoming_promotions (rtx_insn
*first
)
1575 bool strictly_local
= false;
1577 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1578 arg
= DECL_CHAIN (arg
))
1580 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1582 machine_mode mode1
, mode2
, mode3
, mode4
;
1584 /* Only continue if the incoming argument is in a register. */
1588 /* Determine, if possible, whether all call sites of the current
1589 function lie within the current compilation unit. (This does
1590 take into account the exporting of a function via taking its
1591 address, and so forth.) */
1592 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1594 /* The mode and signedness of the argument before any promotions happen
1595 (equal to the mode of the pseudo holding it at that stage). */
1596 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1597 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1599 /* The mode and signedness of the argument after any source language and
1600 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1601 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1602 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1604 /* The mode and signedness of the argument as it is actually passed,
1605 see assign_parm_setup_reg in function.c. */
1606 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1607 TREE_TYPE (cfun
->decl
), 0);
1609 /* The mode of the register in which the argument is being passed. */
1610 mode4
= GET_MODE (reg
);
1612 /* Eliminate sign extensions in the callee when:
1613 (a) A mode promotion has occurred; */
1616 /* (b) The mode of the register is the same as the mode of
1617 the argument as it is passed; */
1620 /* (c) There's no language level extension; */
1623 /* (c.1) All callers are from the current compilation unit. If that's
1624 the case we don't have to rely on an ABI, we only have to know
1625 what we're generating right now, and we know that we will do the
1626 mode1 to mode2 promotion with the given sign. */
1627 else if (!strictly_local
)
1629 /* (c.2) The combination of the two promotions is useful. This is
1630 true when the signs match, or if the first promotion is unsigned.
1631 In the later case, (sign_extend (zero_extend x)) is the same as
1632 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1638 /* Record that the value was promoted from mode1 to mode3,
1639 so that any sign extension at the head of the current
1640 function may be eliminated. */
1641 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1642 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1643 record_value_for_reg (reg
, first
, x
);
1647 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1648 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1649 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1650 because some machines (maybe most) will actually do the sign-extension and
1651 this is the conservative approach.
1653 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1657 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1659 if (GET_MODE_PRECISION (mode
) < prec
1660 && CONST_INT_P (src
)
1662 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1663 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1669 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1673 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1676 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1677 unsigned HOST_WIDE_INT bits
= 0;
1678 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1679 unsigned int num
= 0;
1682 reg_equal
= XEXP (reg_equal_note
, 0);
1684 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1685 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1687 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1690 /* Don't call nonzero_bits if it cannot change anything. */
1691 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1693 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1694 if (reg_equal
&& bits
)
1695 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1696 rsp
->nonzero_bits
|= bits
;
1699 /* Don't call num_sign_bit_copies if it cannot change anything. */
1700 if (rsp
->sign_bit_copies
!= 1)
1702 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1703 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1705 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1706 if (num
== 0 || numeq
> num
)
1709 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1710 rsp
->sign_bit_copies
= num
;
1714 /* Called via note_stores. If X is a pseudo that is narrower than
1715 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1717 If we are setting only a portion of X and we can't figure out what
1718 portion, assume all bits will be used since we don't know what will
1721 Similarly, set how many bits of X are known to be copies of the sign bit
1722 at all locations in the function. This is the smallest number implied
1726 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1728 rtx_insn
*insn
= (rtx_insn
*) data
;
1731 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1732 /* If this register is undefined at the start of the file, we can't
1733 say what its contents were. */
1734 && ! REGNO_REG_SET_P
1735 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1736 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1738 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1740 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1742 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1743 rsp
->sign_bit_copies
= 1;
1747 /* If this register is being initialized using itself, and the
1748 register is uninitialized in this basic block, and there are
1749 no LOG_LINKS which set the register, then part of the
1750 register is uninitialized. In that case we can't assume
1751 anything about the number of nonzero bits.
1753 ??? We could do better if we checked this in
1754 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1755 could avoid making assumptions about the insn which initially
1756 sets the register, while still using the information in other
1757 insns. We would have to be careful to check every insn
1758 involved in the combination. */
1761 && reg_referenced_p (x
, PATTERN (insn
))
1762 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1765 struct insn_link
*link
;
1767 FOR_EACH_LOG_LINK (link
, insn
)
1768 if (dead_or_set_p (link
->insn
, x
))
1772 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1773 rsp
->sign_bit_copies
= 1;
1778 /* If this is a complex assignment, see if we can convert it into a
1779 simple assignment. */
1780 set
= expand_field_assignment (set
);
1782 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1783 set what we know about X. */
1785 if (SET_DEST (set
) == x
1786 || (paradoxical_subreg_p (SET_DEST (set
))
1787 && SUBREG_REG (SET_DEST (set
)) == x
))
1788 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1791 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1792 rsp
->sign_bit_copies
= 1;
1797 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1798 optionally insns that were previously combined into I3 or that will be
1799 combined into the merger of INSN and I3. The order is PRED, PRED2,
1800 INSN, SUCC, SUCC2, I3.
1802 Return 0 if the combination is not allowed for any reason.
1804 If the combination is allowed, *PDEST will be set to the single
1805 destination of INSN and *PSRC to the single source, and this function
1809 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1810 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1811 rtx
*pdest
, rtx
*psrc
)
1820 bool all_adjacent
= true;
1821 int (*is_volatile_p
) (const_rtx
);
1827 if (next_active_insn (succ2
) != i3
)
1828 all_adjacent
= false;
1829 if (next_active_insn (succ
) != succ2
)
1830 all_adjacent
= false;
1832 else if (next_active_insn (succ
) != i3
)
1833 all_adjacent
= false;
1834 if (next_active_insn (insn
) != succ
)
1835 all_adjacent
= false;
1837 else if (next_active_insn (insn
) != i3
)
1838 all_adjacent
= false;
1840 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1841 or a PARALLEL consisting of such a SET and CLOBBERs.
1843 If INSN has CLOBBER parallel parts, ignore them for our processing.
1844 By definition, these happen during the execution of the insn. When it
1845 is merged with another insn, all bets are off. If they are, in fact,
1846 needed and aren't also supplied in I3, they may be added by
1847 recog_for_combine. Otherwise, it won't match.
1849 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1852 Get the source and destination of INSN. If more than one, can't
1855 if (GET_CODE (PATTERN (insn
)) == SET
)
1856 set
= PATTERN (insn
);
1857 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1858 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1860 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1862 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1864 switch (GET_CODE (elt
))
1866 /* This is important to combine floating point insns
1867 for the SH4 port. */
1869 /* Combining an isolated USE doesn't make sense.
1870 We depend here on combinable_i3pat to reject them. */
1871 /* The code below this loop only verifies that the inputs of
1872 the SET in INSN do not change. We call reg_set_between_p
1873 to verify that the REG in the USE does not change between
1875 If the USE in INSN was for a pseudo register, the matching
1876 insn pattern will likely match any register; combining this
1877 with any other USE would only be safe if we knew that the
1878 used registers have identical values, or if there was
1879 something to tell them apart, e.g. different modes. For
1880 now, we forgo such complicated tests and simply disallow
1881 combining of USES of pseudo registers with any other USE. */
1882 if (REG_P (XEXP (elt
, 0))
1883 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1885 rtx i3pat
= PATTERN (i3
);
1886 int i
= XVECLEN (i3pat
, 0) - 1;
1887 unsigned int regno
= REGNO (XEXP (elt
, 0));
1891 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1893 if (GET_CODE (i3elt
) == USE
1894 && REG_P (XEXP (i3elt
, 0))
1895 && (REGNO (XEXP (i3elt
, 0)) == regno
1896 ? reg_set_between_p (XEXP (elt
, 0),
1897 PREV_INSN (insn
), i3
)
1898 : regno
>= FIRST_PSEUDO_REGISTER
))
1905 /* We can ignore CLOBBERs. */
1910 /* Ignore SETs whose result isn't used but not those that
1911 have side-effects. */
1912 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1913 && insn_nothrow_p (insn
)
1914 && !side_effects_p (elt
))
1917 /* If we have already found a SET, this is a second one and
1918 so we cannot combine with this insn. */
1926 /* Anything else means we can't combine. */
1932 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1933 so don't do anything with it. */
1934 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1943 /* The simplification in expand_field_assignment may call back to
1944 get_last_value, so set safe guard here. */
1945 subst_low_luid
= DF_INSN_LUID (insn
);
1947 set
= expand_field_assignment (set
);
1948 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1950 /* Do not eliminate user-specified register if it is in an
1951 asm input because we may break the register asm usage defined
1952 in GCC manual if allow to do so.
1953 Be aware that this may cover more cases than we expect but this
1954 should be harmless. */
1955 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1956 && extract_asm_operands (PATTERN (i3
)))
1959 /* Don't eliminate a store in the stack pointer. */
1960 if (dest
== stack_pointer_rtx
1961 /* Don't combine with an insn that sets a register to itself if it has
1962 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1963 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1964 /* Can't merge an ASM_OPERANDS. */
1965 || GET_CODE (src
) == ASM_OPERANDS
1966 /* Can't merge a function call. */
1967 || GET_CODE (src
) == CALL
1968 /* Don't eliminate a function call argument. */
1970 && (find_reg_fusage (i3
, USE
, dest
)
1972 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1973 && global_regs
[REGNO (dest
)])))
1974 /* Don't substitute into an incremented register. */
1975 || FIND_REG_INC_NOTE (i3
, dest
)
1976 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1977 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1978 /* Don't substitute into a non-local goto, this confuses CFG. */
1979 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1980 /* Make sure that DEST is not used after SUCC but before I3. */
1983 && (reg_used_between_p (dest
, succ2
, i3
)
1984 || reg_used_between_p (dest
, succ
, succ2
)))
1985 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1986 /* Make sure that the value that is to be substituted for the register
1987 does not use any registers whose values alter in between. However,
1988 If the insns are adjacent, a use can't cross a set even though we
1989 think it might (this can happen for a sequence of insns each setting
1990 the same destination; last_set of that register might point to
1991 a NOTE). If INSN has a REG_EQUIV note, the register is always
1992 equivalent to the memory so the substitution is valid even if there
1993 are intervening stores. Also, don't move a volatile asm or
1994 UNSPEC_VOLATILE across any other insns. */
1997 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1998 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1999 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
2000 || GET_CODE (src
) == UNSPEC_VOLATILE
))
2001 /* Don't combine across a CALL_INSN, because that would possibly
2002 change whether the life span of some REGs crosses calls or not,
2003 and it is a pain to update that information.
2004 Exception: if source is a constant, moving it later can't hurt.
2005 Accept that as a special case. */
2006 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
2009 /* DEST must either be a REG or CC0. */
2012 /* If register alignment is being enforced for multi-word items in all
2013 cases except for parameters, it is possible to have a register copy
2014 insn referencing a hard register that is not allowed to contain the
2015 mode being copied and which would not be valid as an operand of most
2016 insns. Eliminate this problem by not combining with such an insn.
2018 Also, on some machines we don't want to extend the life of a hard
2022 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2023 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2024 /* Don't extend the life of a hard register unless it is
2025 user variable (if we have few registers) or it can't
2026 fit into the desired register (meaning something special
2028 Also avoid substituting a return register into I3, because
2029 reload can't handle a conflict with constraints of other
2031 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2032 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2035 else if (GET_CODE (dest
) != CC0
)
2039 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2040 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2041 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2043 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2045 /* If the clobber represents an earlyclobber operand, we must not
2046 substitute an expression containing the clobbered register.
2047 As we do not analyze the constraint strings here, we have to
2048 make the conservative assumption. However, if the register is
2049 a fixed hard reg, the clobber cannot represent any operand;
2050 we leave it up to the machine description to either accept or
2051 reject use-and-clobber patterns. */
2053 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2054 || !fixed_regs
[REGNO (reg
)])
2055 if (reg_overlap_mentioned_p (reg
, src
))
2059 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2060 or not), reject, unless nothing volatile comes between it and I3 */
2062 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2064 /* Make sure neither succ nor succ2 contains a volatile reference. */
2065 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2067 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2069 /* We'll check insns between INSN and I3 below. */
2072 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2073 to be an explicit register variable, and was chosen for a reason. */
2075 if (GET_CODE (src
) == ASM_OPERANDS
2076 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2079 /* If INSN contains volatile references (specifically volatile MEMs),
2080 we cannot combine across any other volatile references.
2081 Even if INSN doesn't contain volatile references, any intervening
2082 volatile insn might affect machine state. */
2084 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2088 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2089 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2092 /* If INSN contains an autoincrement or autodecrement, make sure that
2093 register is not used between there and I3, and not already used in
2094 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2095 Also insist that I3 not be a jump; if it were one
2096 and the incremented register were spilled, we would lose. */
2099 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2100 if (REG_NOTE_KIND (link
) == REG_INC
2102 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2103 || (pred
!= NULL_RTX
2104 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2105 || (pred2
!= NULL_RTX
2106 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2107 || (succ
!= NULL_RTX
2108 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2109 || (succ2
!= NULL_RTX
2110 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2111 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2115 /* Don't combine an insn that follows a CC0-setting insn.
2116 An insn that uses CC0 must not be separated from the one that sets it.
2117 We do, however, allow I2 to follow a CC0-setting insn if that insn
2118 is passed as I1; in that case it will be deleted also.
2119 We also allow combining in this case if all the insns are adjacent
2120 because that would leave the two CC0 insns adjacent as well.
2121 It would be more logical to test whether CC0 occurs inside I1 or I2,
2122 but that would be much slower, and this ought to be equivalent. */
2126 p
= prev_nonnote_insn (insn
);
2127 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2132 /* If we get here, we have passed all the tests and the combination is
2141 /* LOC is the location within I3 that contains its pattern or the component
2142 of a PARALLEL of the pattern. We validate that it is valid for combining.
2144 One problem is if I3 modifies its output, as opposed to replacing it
2145 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2146 doing so would produce an insn that is not equivalent to the original insns.
2150 (set (reg:DI 101) (reg:DI 100))
2151 (set (subreg:SI (reg:DI 101) 0) <foo>)
2153 This is NOT equivalent to:
2155 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2156 (set (reg:DI 101) (reg:DI 100))])
2158 Not only does this modify 100 (in which case it might still be valid
2159 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2161 We can also run into a problem if I2 sets a register that I1
2162 uses and I1 gets directly substituted into I3 (not via I2). In that
2163 case, we would be getting the wrong value of I2DEST into I3, so we
2164 must reject the combination. This case occurs when I2 and I1 both
2165 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2166 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2167 of a SET must prevent combination from occurring. The same situation
2168 can occur for I0, in which case I0_NOT_IN_SRC is set.
2170 Before doing the above check, we first try to expand a field assignment
2171 into a set of logical operations.
2173 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2174 we place a register that is both set and used within I3. If more than one
2175 such register is detected, we fail.
2177 Return 1 if the combination is valid, zero otherwise. */
2180 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2181 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2185 if (GET_CODE (x
) == SET
)
2188 rtx dest
= SET_DEST (set
);
2189 rtx src
= SET_SRC (set
);
2190 rtx inner_dest
= dest
;
2193 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2194 || GET_CODE (inner_dest
) == SUBREG
2195 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2196 inner_dest
= XEXP (inner_dest
, 0);
2198 /* Check for the case where I3 modifies its output, as discussed
2199 above. We don't want to prevent pseudos from being combined
2200 into the address of a MEM, so only prevent the combination if
2201 i1 or i2 set the same MEM. */
2202 if ((inner_dest
!= dest
&&
2203 (!MEM_P (inner_dest
)
2204 || rtx_equal_p (i2dest
, inner_dest
)
2205 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2206 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2207 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2208 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2209 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2211 /* This is the same test done in can_combine_p except we can't test
2212 all_adjacent; we don't have to, since this instruction will stay
2213 in place, thus we are not considering increasing the lifetime of
2216 Also, if this insn sets a function argument, combining it with
2217 something that might need a spill could clobber a previous
2218 function argument; the all_adjacent test in can_combine_p also
2219 checks this; here, we do a more specific test for this case. */
2221 || (REG_P (inner_dest
)
2222 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2223 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2224 GET_MODE (inner_dest
))))
2225 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2226 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2229 /* If DEST is used in I3, it is being killed in this insn, so
2230 record that for later. We have to consider paradoxical
2231 subregs here, since they kill the whole register, but we
2232 ignore partial subregs, STRICT_LOW_PART, etc.
2233 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2234 STACK_POINTER_REGNUM, since these are always considered to be
2235 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2237 if (GET_CODE (subdest
) == SUBREG
2238 && (GET_MODE_SIZE (GET_MODE (subdest
))
2239 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2240 subdest
= SUBREG_REG (subdest
);
2243 && reg_referenced_p (subdest
, PATTERN (i3
))
2244 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2245 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2246 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2248 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2249 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2250 || ! fixed_regs
[REGNO (subdest
)]))
2251 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2253 if (*pi3dest_killed
)
2256 *pi3dest_killed
= subdest
;
2260 else if (GET_CODE (x
) == PARALLEL
)
2264 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2265 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2266 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2273 /* Return 1 if X is an arithmetic expression that contains a multiplication
2274 and division. We don't count multiplications by powers of two here. */
2277 contains_muldiv (rtx x
)
2279 switch (GET_CODE (x
))
2281 case MOD
: case DIV
: case UMOD
: case UDIV
:
2285 return ! (CONST_INT_P (XEXP (x
, 1))
2286 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2289 return contains_muldiv (XEXP (x
, 0))
2290 || contains_muldiv (XEXP (x
, 1));
2293 return contains_muldiv (XEXP (x
, 0));
2299 /* Determine whether INSN can be used in a combination. Return nonzero if
2300 not. This is used in try_combine to detect early some cases where we
2301 can't perform combinations. */
2304 cant_combine_insn_p (rtx_insn
*insn
)
2309 /* If this isn't really an insn, we can't do anything.
2310 This can occur when flow deletes an insn that it has merged into an
2311 auto-increment address. */
2312 if (! INSN_P (insn
))
2315 /* Never combine loads and stores involving hard regs that are likely
2316 to be spilled. The register allocator can usually handle such
2317 reg-reg moves by tying. If we allow the combiner to make
2318 substitutions of likely-spilled regs, reload might die.
2319 As an exception, we allow combinations involving fixed regs; these are
2320 not available to the register allocator so there's no risk involved. */
2322 set
= single_set (insn
);
2325 src
= SET_SRC (set
);
2326 dest
= SET_DEST (set
);
2327 if (GET_CODE (src
) == SUBREG
)
2328 src
= SUBREG_REG (src
);
2329 if (GET_CODE (dest
) == SUBREG
)
2330 dest
= SUBREG_REG (dest
);
2331 if (REG_P (src
) && REG_P (dest
)
2332 && ((HARD_REGISTER_P (src
)
2333 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2334 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2335 || (HARD_REGISTER_P (dest
)
2336 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2337 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2343 struct likely_spilled_retval_info
2345 unsigned regno
, nregs
;
2349 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2350 hard registers that are known to be written to / clobbered in full. */
2352 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2354 struct likely_spilled_retval_info
*const info
=
2355 (struct likely_spilled_retval_info
*) data
;
2356 unsigned regno
, nregs
;
2359 if (!REG_P (XEXP (set
, 0)))
2362 if (regno
>= info
->regno
+ info
->nregs
)
2364 nregs
= REG_NREGS (x
);
2365 if (regno
+ nregs
<= info
->regno
)
2367 new_mask
= (2U << (nregs
- 1)) - 1;
2368 if (regno
< info
->regno
)
2369 new_mask
>>= info
->regno
- regno
;
2371 new_mask
<<= regno
- info
->regno
;
2372 info
->mask
&= ~new_mask
;
2375 /* Return nonzero iff part of the return value is live during INSN, and
2376 it is likely spilled. This can happen when more than one insn is needed
2377 to copy the return value, e.g. when we consider to combine into the
2378 second copy insn for a complex value. */
2381 likely_spilled_retval_p (rtx_insn
*insn
)
2383 rtx_insn
*use
= BB_END (this_basic_block
);
2386 unsigned regno
, nregs
;
2387 /* We assume here that no machine mode needs more than
2388 32 hard registers when the value overlaps with a register
2389 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2391 struct likely_spilled_retval_info info
;
2393 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2395 reg
= XEXP (PATTERN (use
), 0);
2396 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2398 regno
= REGNO (reg
);
2399 nregs
= REG_NREGS (reg
);
2402 mask
= (2U << (nregs
- 1)) - 1;
2404 /* Disregard parts of the return value that are set later. */
2408 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2410 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2413 /* Check if any of the (probably) live return value registers is
2418 if ((mask
& 1 << nregs
)
2419 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2425 /* Adjust INSN after we made a change to its destination.
2427 Changing the destination can invalidate notes that say something about
2428 the results of the insn and a LOG_LINK pointing to the insn. */
2431 adjust_for_new_dest (rtx_insn
*insn
)
2433 /* For notes, be conservative and simply remove them. */
2434 remove_reg_equal_equiv_notes (insn
);
2436 /* The new insn will have a destination that was previously the destination
2437 of an insn just above it. Call distribute_links to make a LOG_LINK from
2438 the next use of that destination. */
2440 rtx set
= single_set (insn
);
2443 rtx reg
= SET_DEST (set
);
2445 while (GET_CODE (reg
) == ZERO_EXTRACT
2446 || GET_CODE (reg
) == STRICT_LOW_PART
2447 || GET_CODE (reg
) == SUBREG
)
2448 reg
= XEXP (reg
, 0);
2449 gcc_assert (REG_P (reg
));
2451 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2453 df_insn_rescan (insn
);
2456 /* Return TRUE if combine can reuse reg X in mode MODE.
2457 ADDED_SETS is nonzero if the original set is still required. */
2459 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2467 /* Allow hard registers if the new mode is legal, and occupies no more
2468 registers than the old mode. */
2469 if (regno
< FIRST_PSEUDO_REGISTER
)
2470 return (HARD_REGNO_MODE_OK (regno
, mode
)
2471 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2473 /* Or a pseudo that is only used once. */
2474 return (regno
< reg_n_sets_max
2475 && REG_N_SETS (regno
) == 1
2477 && !REG_USERVAR_P (x
));
2481 /* Check whether X, the destination of a set, refers to part of
2482 the register specified by REG. */
2485 reg_subword_p (rtx x
, rtx reg
)
2487 /* Check that reg is an integer mode register. */
2488 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2491 if (GET_CODE (x
) == STRICT_LOW_PART
2492 || GET_CODE (x
) == ZERO_EXTRACT
)
2495 return GET_CODE (x
) == SUBREG
2496 && SUBREG_REG (x
) == reg
2497 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2500 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2501 Note that the INSN should be deleted *after* removing dead edges, so
2502 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2503 but not for a (set (pc) (label_ref FOO)). */
2506 update_cfg_for_uncondjump (rtx_insn
*insn
)
2508 basic_block bb
= BLOCK_FOR_INSN (insn
);
2509 gcc_assert (BB_END (bb
) == insn
);
2511 purge_dead_edges (bb
);
2514 if (EDGE_COUNT (bb
->succs
) == 1)
2518 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2520 /* Remove barriers from the footer if there are any. */
2521 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2522 if (BARRIER_P (insn
))
2524 if (PREV_INSN (insn
))
2525 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2527 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2528 if (NEXT_INSN (insn
))
2529 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2531 else if (LABEL_P (insn
))
2536 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2537 by an arbitrary number of CLOBBERs. */
2539 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2541 if (GET_CODE (pat
) != PARALLEL
)
2544 int len
= XVECLEN (pat
, 0);
2549 for (i
= 0; i
< n
; i
++)
2550 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2551 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2553 for ( ; i
< len
; i
++)
2554 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
2561 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2562 CLOBBERs), can be split into individual SETs in that order, without
2563 changing semantics. */
2565 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2567 if (!insn_nothrow_p (insn
))
2570 rtx pat
= PATTERN (insn
);
2573 for (i
= 0; i
< n
; i
++)
2575 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2578 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2580 for (j
= i
+ 1; j
< n
; j
++)
2581 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2589 /* Try to combine the insns I0, I1 and I2 into I3.
2590 Here I0, I1 and I2 appear earlier than I3.
2591 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2594 If we are combining more than two insns and the resulting insn is not
2595 recognized, try splitting it into two insns. If that happens, I2 and I3
2596 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2597 Otherwise, I0, I1 and I2 are pseudo-deleted.
2599 Return 0 if the combination does not work. Then nothing is changed.
2600 If we did the combination, return the insn at which combine should
2603 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2604 new direct jump instruction.
2606 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2607 been I3 passed to an earlier try_combine within the same basic
2611 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2612 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2614 /* New patterns for I3 and I2, respectively. */
2615 rtx newpat
, newi2pat
= 0;
2616 rtvec newpat_vec_with_clobbers
= 0;
2617 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2618 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2620 int added_sets_0
, added_sets_1
, added_sets_2
;
2621 /* Total number of SETs to put into I3. */
2623 /* Nonzero if I2's or I1's body now appears in I3. */
2624 int i2_is_used
= 0, i1_is_used
= 0;
2625 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2626 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2627 /* Contains I3 if the destination of I3 is used in its source, which means
2628 that the old life of I3 is being killed. If that usage is placed into
2629 I2 and not in I3, a REG_DEAD note must be made. */
2630 rtx i3dest_killed
= 0;
2631 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2632 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2633 /* Copy of SET_SRC of I1 and I0, if needed. */
2634 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2635 /* Set if I2DEST was reused as a scratch register. */
2636 bool i2scratch
= false;
2637 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2638 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2639 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2640 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2641 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2642 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2643 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2644 /* Notes that must be added to REG_NOTES in I3 and I2. */
2645 rtx new_i3_notes
, new_i2_notes
;
2646 /* Notes that we substituted I3 into I2 instead of the normal case. */
2647 int i3_subst_into_i2
= 0;
2648 /* Notes that I1, I2 or I3 is a MULT operation. */
2651 int changed_i3_dest
= 0;
2654 rtx_insn
*temp_insn
;
2656 struct insn_link
*link
;
2658 rtx new_other_notes
;
2661 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2663 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2666 /* Only try four-insn combinations when there's high likelihood of
2667 success. Look for simple insns, such as loads of constants or
2668 binary operations involving a constant. */
2676 if (!flag_expensive_optimizations
)
2679 for (i
= 0; i
< 4; i
++)
2681 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2682 rtx set
= single_set (insn
);
2686 src
= SET_SRC (set
);
2687 if (CONSTANT_P (src
))
2692 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2694 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2695 || GET_CODE (src
) == LSHIFTRT
)
2699 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2700 are likely manipulating its value. Ideally we'll be able to combine
2701 all four insns into a bitfield insertion of some kind.
2703 Note the source in I0 might be inside a sign/zero extension and the
2704 memory modes in I0 and I3 might be different. So extract the address
2705 from the destination of I3 and search for it in the source of I0.
2707 In the event that there's a match but the source/dest do not actually
2708 refer to the same memory, the worst that happens is we try some
2709 combinations that we wouldn't have otherwise. */
2710 if ((set0
= single_set (i0
))
2711 /* Ensure the source of SET0 is a MEM, possibly buried inside
2713 && (GET_CODE (SET_SRC (set0
)) == MEM
2714 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2715 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2716 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2717 && (set3
= single_set (i3
))
2718 /* Ensure the destination of SET3 is a MEM. */
2719 && GET_CODE (SET_DEST (set3
)) == MEM
2720 /* Would it be better to extract the base address for the MEM
2721 in SET3 and look for that? I don't have cases where it matters
2722 but I could envision such cases. */
2723 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2726 if (ngood
< 2 && nshift
< 2)
2730 /* Exit early if one of the insns involved can't be used for
2733 || (i1
&& CALL_P (i1
))
2734 || (i0
&& CALL_P (i0
))
2735 || cant_combine_insn_p (i3
)
2736 || cant_combine_insn_p (i2
)
2737 || (i1
&& cant_combine_insn_p (i1
))
2738 || (i0
&& cant_combine_insn_p (i0
))
2739 || likely_spilled_retval_p (i3
))
2743 undobuf
.other_insn
= 0;
2745 /* Reset the hard register usage information. */
2746 CLEAR_HARD_REG_SET (newpat_used_regs
);
2748 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2751 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2752 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2754 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2755 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2757 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2758 INSN_UID (i2
), INSN_UID (i3
));
2761 /* If multiple insns feed into one of I2 or I3, they can be in any
2762 order. To simplify the code below, reorder them in sequence. */
2763 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2764 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2765 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2766 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2767 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2768 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2770 added_links_insn
= 0;
2772 /* First check for one important special case that the code below will
2773 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2774 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2775 we may be able to replace that destination with the destination of I3.
2776 This occurs in the common code where we compute both a quotient and
2777 remainder into a structure, in which case we want to do the computation
2778 directly into the structure to avoid register-register copies.
2780 Note that this case handles both multiple sets in I2 and also cases
2781 where I2 has a number of CLOBBERs inside the PARALLEL.
2783 We make very conservative checks below and only try to handle the
2784 most common cases of this. For example, we only handle the case
2785 where I2 and I3 are adjacent to avoid making difficult register
2788 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2789 && REG_P (SET_SRC (PATTERN (i3
)))
2790 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2791 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2792 && GET_CODE (PATTERN (i2
)) == PARALLEL
2793 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2794 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2795 below would need to check what is inside (and reg_overlap_mentioned_p
2796 doesn't support those codes anyway). Don't allow those destinations;
2797 the resulting insn isn't likely to be recognized anyway. */
2798 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2799 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2800 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2801 SET_DEST (PATTERN (i3
)))
2802 && next_active_insn (i2
) == i3
)
2804 rtx p2
= PATTERN (i2
);
2806 /* Make sure that the destination of I3,
2807 which we are going to substitute into one output of I2,
2808 is not used within another output of I2. We must avoid making this:
2809 (parallel [(set (mem (reg 69)) ...)
2810 (set (reg 69) ...)])
2811 which is not well-defined as to order of actions.
2812 (Besides, reload can't handle output reloads for this.)
2814 The problem can also happen if the dest of I3 is a memory ref,
2815 if another dest in I2 is an indirect memory ref. */
2816 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2817 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2818 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2819 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2820 SET_DEST (XVECEXP (p2
, 0, i
))))
2823 /* Make sure this PARALLEL is not an asm. We do not allow combining
2824 that usually (see can_combine_p), so do not here either. */
2825 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2826 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2827 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2830 if (i
== XVECLEN (p2
, 0))
2831 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2832 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2833 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2838 subst_low_luid
= DF_INSN_LUID (i2
);
2840 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2841 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2842 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2843 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2845 /* Replace the dest in I2 with our dest and make the resulting
2846 insn the new pattern for I3. Then skip to where we validate
2847 the pattern. Everything was set up above. */
2848 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2850 i3_subst_into_i2
= 1;
2851 goto validate_replacement
;
2855 /* If I2 is setting a pseudo to a constant and I3 is setting some
2856 sub-part of it to another constant, merge them by making a new
2859 && (temp_expr
= single_set (i2
)) != 0
2860 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2861 && GET_CODE (PATTERN (i3
)) == SET
2862 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2863 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2865 rtx dest
= SET_DEST (PATTERN (i3
));
2869 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2871 if (CONST_INT_P (XEXP (dest
, 1))
2872 && CONST_INT_P (XEXP (dest
, 2)))
2874 width
= INTVAL (XEXP (dest
, 1));
2875 offset
= INTVAL (XEXP (dest
, 2));
2876 dest
= XEXP (dest
, 0);
2877 if (BITS_BIG_ENDIAN
)
2878 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2883 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2884 dest
= XEXP (dest
, 0);
2885 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2891 /* If this is the low part, we're done. */
2892 if (subreg_lowpart_p (dest
))
2894 /* Handle the case where inner is twice the size of outer. */
2895 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2896 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2897 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2898 /* Otherwise give up for now. */
2905 rtx inner
= SET_SRC (PATTERN (i3
));
2906 rtx outer
= SET_SRC (temp_expr
);
2909 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2910 std::make_pair (inner
, GET_MODE (dest
)),
2915 subst_low_luid
= DF_INSN_LUID (i2
);
2916 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2917 i2dest
= SET_DEST (temp_expr
);
2918 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2920 /* Replace the source in I2 with the new constant and make the
2921 resulting insn the new pattern for I3. Then skip to where we
2922 validate the pattern. Everything was set up above. */
2923 SUBST (SET_SRC (temp_expr
),
2924 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2926 newpat
= PATTERN (i2
);
2928 /* The dest of I3 has been replaced with the dest of I2. */
2929 changed_i3_dest
= 1;
2930 goto validate_replacement
;
2935 /* If we have no I1 and I2 looks like:
2936 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2938 make up a dummy I1 that is
2941 (set (reg:CC X) (compare:CC Y (const_int 0)))
2943 (We can ignore any trailing CLOBBERs.)
2945 This undoes a previous combination and allows us to match a branch-and-
2949 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2950 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2952 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2953 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2954 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2955 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2956 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2957 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2959 /* We make I1 with the same INSN_UID as I2. This gives it
2960 the same DF_INSN_LUID for value tracking. Our fake I1 will
2961 never appear in the insn stream so giving it the same INSN_UID
2962 as I2 will not cause a problem. */
2964 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2965 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2967 INSN_UID (i1
) = INSN_UID (i2
);
2969 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2970 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2971 SET_DEST (PATTERN (i1
)));
2972 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2973 SUBST_LINK (LOG_LINKS (i2
),
2974 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2977 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2978 make those two SETs separate I1 and I2 insns, and make an I0 that is
2981 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2982 && can_split_parallel_of_n_reg_sets (i2
, 2)
2983 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2984 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2986 /* If there is no I1, there is no I0 either. */
2989 /* We make I1 with the same INSN_UID as I2. This gives it
2990 the same DF_INSN_LUID for value tracking. Our fake I1 will
2991 never appear in the insn stream so giving it the same INSN_UID
2992 as I2 will not cause a problem. */
2994 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2995 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2997 INSN_UID (i1
) = INSN_UID (i2
);
2999 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
3003 /* Verify that I2 and I1 are valid for combining. */
3004 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
3005 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
3007 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
3014 /* Record whether I2DEST is used in I2SRC and similarly for the other
3015 cases. Knowing this will help in register status updating below. */
3016 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3017 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3018 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3019 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3020 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3021 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3022 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3023 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3024 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3026 /* For the earlier insns, determine which of the subsequent ones they
3028 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3029 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3030 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3031 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3032 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3034 /* Ensure that I3's pattern can be the destination of combines. */
3035 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3036 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3037 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3038 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3045 /* See if any of the insns is a MULT operation. Unless one is, we will
3046 reject a combination that is, since it must be slower. Be conservative
3048 if (GET_CODE (i2src
) == MULT
3049 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3050 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3051 || (GET_CODE (PATTERN (i3
)) == SET
3052 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3055 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3056 We used to do this EXCEPT in one case: I3 has a post-inc in an
3057 output operand. However, that exception can give rise to insns like
3059 which is a famous insn on the PDP-11 where the value of r3 used as the
3060 source was model-dependent. Avoid this sort of thing. */
3063 if (!(GET_CODE (PATTERN (i3
)) == SET
3064 && REG_P (SET_SRC (PATTERN (i3
)))
3065 && MEM_P (SET_DEST (PATTERN (i3
)))
3066 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3067 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3068 /* It's not the exception. */
3073 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3074 if (REG_NOTE_KIND (link
) == REG_INC
3075 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3077 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3085 /* See if the SETs in I1 or I2 need to be kept around in the merged
3086 instruction: whenever the value set there is still needed past I3.
3087 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3089 For the SET in I1, we have two cases: if I1 and I2 independently feed
3090 into I3, the set in I1 needs to be kept around unless I1DEST dies
3091 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3092 in I1 needs to be kept around unless I1DEST dies or is set in either
3093 I2 or I3. The same considerations apply to I0. */
3095 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3098 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3099 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3104 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3105 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3106 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3107 && dead_or_set_p (i2
, i0dest
)));
3111 /* We are about to copy insns for the case where they need to be kept
3112 around. Check that they can be copied in the merged instruction. */
3114 if (targetm
.cannot_copy_insn_p
3115 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3116 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3117 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3123 /* If the set in I2 needs to be kept around, we must make a copy of
3124 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3125 PATTERN (I2), we are only substituting for the original I1DEST, not into
3126 an already-substituted copy. This also prevents making self-referential
3127 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3132 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3133 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3135 i2pat
= copy_rtx (PATTERN (i2
));
3140 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3141 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3143 i1pat
= copy_rtx (PATTERN (i1
));
3148 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3149 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3151 i0pat
= copy_rtx (PATTERN (i0
));
3156 /* Substitute in the latest insn for the regs set by the earlier ones. */
3158 maxreg
= max_reg_num ();
3162 /* Many machines that don't use CC0 have insns that can both perform an
3163 arithmetic operation and set the condition code. These operations will
3164 be represented as a PARALLEL with the first element of the vector
3165 being a COMPARE of an arithmetic operation with the constant zero.
3166 The second element of the vector will set some pseudo to the result
3167 of the same arithmetic operation. If we simplify the COMPARE, we won't
3168 match such a pattern and so will generate an extra insn. Here we test
3169 for this case, where both the comparison and the operation result are
3170 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3171 I2SRC. Later we will make the PARALLEL that contains I2. */
3173 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3174 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3175 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3176 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3179 rtx
*cc_use_loc
= NULL
;
3180 rtx_insn
*cc_use_insn
= NULL
;
3181 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3182 machine_mode compare_mode
, orig_compare_mode
;
3183 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3185 newpat
= PATTERN (i3
);
3186 newpat_dest
= SET_DEST (newpat
);
3187 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3189 if (undobuf
.other_insn
== 0
3190 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3193 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3194 compare_code
= simplify_compare_const (compare_code
,
3195 GET_MODE (i2dest
), op0
, &op1
);
3196 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3199 /* Do the rest only if op1 is const0_rtx, which may be the
3200 result of simplification. */
3201 if (op1
== const0_rtx
)
3203 /* If a single use of the CC is found, prepare to modify it
3204 when SELECT_CC_MODE returns a new CC-class mode, or when
3205 the above simplify_compare_const() returned a new comparison
3206 operator. undobuf.other_insn is assigned the CC use insn
3207 when modifying it. */
3210 #ifdef SELECT_CC_MODE
3211 machine_mode new_mode
3212 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3213 if (new_mode
!= orig_compare_mode
3214 && can_change_dest_mode (SET_DEST (newpat
),
3215 added_sets_2
, new_mode
))
3217 unsigned int regno
= REGNO (newpat_dest
);
3218 compare_mode
= new_mode
;
3219 if (regno
< FIRST_PSEUDO_REGISTER
)
3220 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3223 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3224 newpat_dest
= regno_reg_rtx
[regno
];
3228 /* Cases for modifying the CC-using comparison. */
3229 if (compare_code
!= orig_compare_code
3230 /* ??? Do we need to verify the zero rtx? */
3231 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3233 /* Replace cc_use_loc with entire new RTX. */
3235 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3236 newpat_dest
, const0_rtx
));
3237 undobuf
.other_insn
= cc_use_insn
;
3239 else if (compare_mode
!= orig_compare_mode
)
3241 /* Just replace the CC reg with a new mode. */
3242 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3243 undobuf
.other_insn
= cc_use_insn
;
3247 /* Now we modify the current newpat:
3248 First, SET_DEST(newpat) is updated if the CC mode has been
3249 altered. For targets without SELECT_CC_MODE, this should be
3251 if (compare_mode
!= orig_compare_mode
)
3252 SUBST (SET_DEST (newpat
), newpat_dest
);
3253 /* This is always done to propagate i2src into newpat. */
3254 SUBST (SET_SRC (newpat
),
3255 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3256 /* Create new version of i2pat if needed; the below PARALLEL
3257 creation needs this to work correctly. */
3258 if (! rtx_equal_p (i2src
, op0
))
3259 i2pat
= gen_rtx_SET (i2dest
, op0
);
3264 if (i2_is_used
== 0)
3266 /* It is possible that the source of I2 or I1 may be performing
3267 an unneeded operation, such as a ZERO_EXTEND of something
3268 that is known to have the high part zero. Handle that case
3269 by letting subst look at the inner insns.
3271 Another way to do this would be to have a function that tries
3272 to simplify a single insn instead of merging two or more
3273 insns. We don't do this because of the potential of infinite
3274 loops and because of the potential extra memory required.
3275 However, doing it the way we are is a bit of a kludge and
3276 doesn't catch all cases.
3278 But only do this if -fexpensive-optimizations since it slows
3279 things down and doesn't usually win.
3281 This is not done in the COMPARE case above because the
3282 unmodified I2PAT is used in the PARALLEL and so a pattern
3283 with a modified I2SRC would not match. */
3285 if (flag_expensive_optimizations
)
3287 /* Pass pc_rtx so no substitutions are done, just
3291 subst_low_luid
= DF_INSN_LUID (i1
);
3292 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3295 subst_low_luid
= DF_INSN_LUID (i2
);
3296 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3299 n_occurrences
= 0; /* `subst' counts here */
3300 subst_low_luid
= DF_INSN_LUID (i2
);
3302 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3303 copy of I2SRC each time we substitute it, in order to avoid creating
3304 self-referential RTL when we will be substituting I1SRC for I1DEST
3305 later. Likewise if I0 feeds into I2, either directly or indirectly
3306 through I1, and I0DEST is in I0SRC. */
3307 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3308 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3309 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3310 && i0dest_in_i0src
));
3313 /* Record whether I2's body now appears within I3's body. */
3314 i2_is_used
= n_occurrences
;
3317 /* If we already got a failure, don't try to do more. Otherwise, try to
3318 substitute I1 if we have it. */
3320 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3322 /* Check that an autoincrement side-effect on I1 has not been lost.
3323 This happens if I1DEST is mentioned in I2 and dies there, and
3324 has disappeared from the new pattern. */
3325 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3327 && dead_or_set_p (i2
, i1dest
)
3328 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3329 /* Before we can do this substitution, we must redo the test done
3330 above (see detailed comments there) that ensures I1DEST isn't
3331 mentioned in any SETs in NEWPAT that are field assignments. */
3332 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3340 subst_low_luid
= DF_INSN_LUID (i1
);
3342 /* If the following substitution will modify I1SRC, make a copy of it
3343 for the case where it is substituted for I1DEST in I2PAT later. */
3344 if (added_sets_2
&& i1_feeds_i2_n
)
3345 i1src_copy
= copy_rtx (i1src
);
3347 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3348 copy of I1SRC each time we substitute it, in order to avoid creating
3349 self-referential RTL when we will be substituting I0SRC for I0DEST
3351 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3352 i0_feeds_i1_n
&& i0dest_in_i0src
);
3355 /* Record whether I1's body now appears within I3's body. */
3356 i1_is_used
= n_occurrences
;
3359 /* Likewise for I0 if we have it. */
3361 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3363 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3364 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3365 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3366 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3367 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3374 /* If the following substitution will modify I0SRC, make a copy of it
3375 for the case where it is substituted for I0DEST in I1PAT later. */
3376 if (added_sets_1
&& i0_feeds_i1_n
)
3377 i0src_copy
= copy_rtx (i0src
);
3378 /* And a copy for I0DEST in I2PAT substitution. */
3379 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3380 || (i0_feeds_i2_n
)))
3381 i0src_copy2
= copy_rtx (i0src
);
3384 subst_low_luid
= DF_INSN_LUID (i0
);
3385 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3389 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3390 to count all the ways that I2SRC and I1SRC can be used. */
3391 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3392 && i2_is_used
+ added_sets_2
> 1)
3393 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3394 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3396 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3397 && (n_occurrences
+ added_sets_0
3398 + (added_sets_1
&& i0_feeds_i1_n
)
3399 + (added_sets_2
&& i0_feeds_i2_n
)
3401 /* Fail if we tried to make a new register. */
3402 || max_reg_num () != maxreg
3403 /* Fail if we couldn't do something and have a CLOBBER. */
3404 || GET_CODE (newpat
) == CLOBBER
3405 /* Fail if this new pattern is a MULT and we didn't have one before
3406 at the outer level. */
3407 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3414 /* If the actions of the earlier insns must be kept
3415 in addition to substituting them into the latest one,
3416 we must make a new PARALLEL for the latest insn
3417 to hold additional the SETs. */
3419 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3421 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3424 if (GET_CODE (newpat
) == PARALLEL
)
3426 rtvec old
= XVEC (newpat
, 0);
3427 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3428 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3429 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3430 sizeof (old
->elem
[0]) * old
->num_elem
);
3435 total_sets
= 1 + extra_sets
;
3436 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3437 XVECEXP (newpat
, 0, 0) = old
;
3441 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3447 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3449 XVECEXP (newpat
, 0, --total_sets
) = t
;
3455 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3456 i0_feeds_i1_n
&& i0dest_in_i0src
);
3457 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3458 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3460 XVECEXP (newpat
, 0, --total_sets
) = t
;
3464 validate_replacement
:
3466 /* Note which hard regs this insn has as inputs. */
3467 mark_used_regs_combine (newpat
);
3469 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3470 consider splitting this pattern, we might need these clobbers. */
3471 if (i1
&& GET_CODE (newpat
) == PARALLEL
3472 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3474 int len
= XVECLEN (newpat
, 0);
3476 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3477 for (i
= 0; i
< len
; i
++)
3478 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3481 /* We have recognized nothing yet. */
3482 insn_code_number
= -1;
3484 /* See if this is a PARALLEL of two SETs where one SET's destination is
3485 a register that is unused and this isn't marked as an instruction that
3486 might trap in an EH region. In that case, we just need the other SET.
3487 We prefer this over the PARALLEL.
3489 This can occur when simplifying a divmod insn. We *must* test for this
3490 case here because the code below that splits two independent SETs doesn't
3491 handle this case correctly when it updates the register status.
3493 It's pointless doing this if we originally had two sets, one from
3494 i3, and one from i2. Combining then splitting the parallel results
3495 in the original i2 again plus an invalid insn (which we delete).
3496 The net effect is only to move instructions around, which makes
3497 debug info less accurate. */
3499 if (!(added_sets_2
&& i1
== 0)
3500 && is_parallel_of_n_reg_sets (newpat
, 2)
3501 && asm_noperands (newpat
) < 0)
3503 rtx set0
= XVECEXP (newpat
, 0, 0);
3504 rtx set1
= XVECEXP (newpat
, 0, 1);
3505 rtx oldpat
= newpat
;
3507 if (((REG_P (SET_DEST (set1
))
3508 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3509 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3510 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3511 && insn_nothrow_p (i3
)
3512 && !side_effects_p (SET_SRC (set1
)))
3515 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3518 else if (((REG_P (SET_DEST (set0
))
3519 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3520 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3521 && find_reg_note (i3
, REG_UNUSED
,
3522 SUBREG_REG (SET_DEST (set0
)))))
3523 && insn_nothrow_p (i3
)
3524 && !side_effects_p (SET_SRC (set0
)))
3527 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3529 if (insn_code_number
>= 0)
3530 changed_i3_dest
= 1;
3533 if (insn_code_number
< 0)
3537 /* Is the result of combination a valid instruction? */
3538 if (insn_code_number
< 0)
3539 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3541 /* If we were combining three insns and the result is a simple SET
3542 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3543 insns. There are two ways to do this. It can be split using a
3544 machine-specific method (like when you have an addition of a large
3545 constant) or by combine in the function find_split_point. */
3547 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3548 && asm_noperands (newpat
) < 0)
3550 rtx parallel
, *split
;
3551 rtx_insn
*m_split_insn
;
3553 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3554 use I2DEST as a scratch register will help. In the latter case,
3555 convert I2DEST to the mode of the source of NEWPAT if we can. */
3557 m_split_insn
= combine_split_insns (newpat
, i3
);
3559 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3560 inputs of NEWPAT. */
3562 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3563 possible to try that as a scratch reg. This would require adding
3564 more code to make it work though. */
3566 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3568 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3570 /* First try to split using the original register as a
3571 scratch register. */
3572 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3573 gen_rtvec (2, newpat
,
3574 gen_rtx_CLOBBER (VOIDmode
,
3576 m_split_insn
= combine_split_insns (parallel
, i3
);
3578 /* If that didn't work, try changing the mode of I2DEST if
3580 if (m_split_insn
== 0
3581 && new_mode
!= GET_MODE (i2dest
)
3582 && new_mode
!= VOIDmode
3583 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3585 machine_mode old_mode
= GET_MODE (i2dest
);
3588 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3589 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3592 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3593 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3596 parallel
= (gen_rtx_PARALLEL
3598 gen_rtvec (2, newpat
,
3599 gen_rtx_CLOBBER (VOIDmode
,
3601 m_split_insn
= combine_split_insns (parallel
, i3
);
3603 if (m_split_insn
== 0
3604 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3608 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3609 buf
= undobuf
.undos
;
3610 undobuf
.undos
= buf
->next
;
3611 buf
->next
= undobuf
.frees
;
3612 undobuf
.frees
= buf
;
3616 i2scratch
= m_split_insn
!= 0;
3619 /* If recog_for_combine has discarded clobbers, try to use them
3620 again for the split. */
3621 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3623 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3624 m_split_insn
= combine_split_insns (parallel
, i3
);
3627 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3629 rtx m_split_pat
= PATTERN (m_split_insn
);
3630 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3631 if (insn_code_number
>= 0)
3632 newpat
= m_split_pat
;
3634 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3635 && (next_nonnote_nondebug_insn (i2
) == i3
3636 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3639 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3640 newi2pat
= PATTERN (m_split_insn
);
3642 i3set
= single_set (NEXT_INSN (m_split_insn
));
3643 i2set
= single_set (m_split_insn
);
3645 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3647 /* If I2 or I3 has multiple SETs, we won't know how to track
3648 register status, so don't use these insns. If I2's destination
3649 is used between I2 and I3, we also can't use these insns. */
3651 if (i2_code_number
>= 0 && i2set
&& i3set
3652 && (next_nonnote_nondebug_insn (i2
) == i3
3653 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3654 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3656 if (insn_code_number
>= 0)
3659 /* It is possible that both insns now set the destination of I3.
3660 If so, we must show an extra use of it. */
3662 if (insn_code_number
>= 0)
3664 rtx new_i3_dest
= SET_DEST (i3set
);
3665 rtx new_i2_dest
= SET_DEST (i2set
);
3667 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3668 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3669 || GET_CODE (new_i3_dest
) == SUBREG
)
3670 new_i3_dest
= XEXP (new_i3_dest
, 0);
3672 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3673 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3674 || GET_CODE (new_i2_dest
) == SUBREG
)
3675 new_i2_dest
= XEXP (new_i2_dest
, 0);
3677 if (REG_P (new_i3_dest
)
3678 && REG_P (new_i2_dest
)
3679 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3680 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3681 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3685 /* If we can split it and use I2DEST, go ahead and see if that
3686 helps things be recognized. Verify that none of the registers
3687 are set between I2 and I3. */
3688 if (insn_code_number
< 0
3689 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3690 && (!HAVE_cc0
|| REG_P (i2dest
))
3691 /* We need I2DEST in the proper mode. If it is a hard register
3692 or the only use of a pseudo, we can change its mode.
3693 Make sure we don't change a hard register to have a mode that
3694 isn't valid for it, or change the number of registers. */
3695 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3696 || GET_MODE (*split
) == VOIDmode
3697 || can_change_dest_mode (i2dest
, added_sets_2
,
3699 && (next_nonnote_nondebug_insn (i2
) == i3
3700 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3701 /* We can't overwrite I2DEST if its value is still used by
3703 && ! reg_referenced_p (i2dest
, newpat
))
3705 rtx newdest
= i2dest
;
3706 enum rtx_code split_code
= GET_CODE (*split
);
3707 machine_mode split_mode
= GET_MODE (*split
);
3708 bool subst_done
= false;
3709 newi2pat
= NULL_RTX
;
3713 /* *SPLIT may be part of I2SRC, so make sure we have the
3714 original expression around for later debug processing.
3715 We should not need I2SRC any more in other cases. */
3716 if (MAY_HAVE_DEBUG_INSNS
)
3717 i2src
= copy_rtx (i2src
);
3721 /* Get NEWDEST as a register in the proper mode. We have already
3722 validated that we can do this. */
3723 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3725 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3726 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3729 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3730 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3734 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3735 an ASHIFT. This can occur if it was inside a PLUS and hence
3736 appeared to be a memory address. This is a kludge. */
3737 if (split_code
== MULT
3738 && CONST_INT_P (XEXP (*split
, 1))
3739 && INTVAL (XEXP (*split
, 1)) > 0
3740 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3742 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3743 XEXP (*split
, 0), GEN_INT (i
)));
3744 /* Update split_code because we may not have a multiply
3746 split_code
= GET_CODE (*split
);
3749 /* Similarly for (plus (mult FOO (const_int pow2))). */
3750 if (split_code
== PLUS
3751 && GET_CODE (XEXP (*split
, 0)) == MULT
3752 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3753 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3754 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3756 rtx nsplit
= XEXP (*split
, 0);
3757 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3758 XEXP (nsplit
, 0), GEN_INT (i
)));
3759 /* Update split_code because we may not have a multiply
3761 split_code
= GET_CODE (*split
);
3764 #ifdef INSN_SCHEDULING
3765 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3766 be written as a ZERO_EXTEND. */
3767 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3769 #ifdef LOAD_EXTEND_OP
3770 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3771 what it really is. */
3772 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3774 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3775 SUBREG_REG (*split
)));
3778 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3779 SUBREG_REG (*split
)));
3783 /* Attempt to split binary operators using arithmetic identities. */
3784 if (BINARY_P (SET_SRC (newpat
))
3785 && split_mode
== GET_MODE (SET_SRC (newpat
))
3786 && ! side_effects_p (SET_SRC (newpat
)))
3788 rtx setsrc
= SET_SRC (newpat
);
3789 machine_mode mode
= GET_MODE (setsrc
);
3790 enum rtx_code code
= GET_CODE (setsrc
);
3791 rtx src_op0
= XEXP (setsrc
, 0);
3792 rtx src_op1
= XEXP (setsrc
, 1);
3794 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3795 if (rtx_equal_p (src_op0
, src_op1
))
3797 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3798 SUBST (XEXP (setsrc
, 0), newdest
);
3799 SUBST (XEXP (setsrc
, 1), newdest
);
3802 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3803 else if ((code
== PLUS
|| code
== MULT
)
3804 && GET_CODE (src_op0
) == code
3805 && GET_CODE (XEXP (src_op0
, 0)) == code
3806 && (INTEGRAL_MODE_P (mode
)
3807 || (FLOAT_MODE_P (mode
)
3808 && flag_unsafe_math_optimizations
)))
3810 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3811 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3812 rtx r
= XEXP (src_op0
, 1);
3815 /* Split both "((X op Y) op X) op Y" and
3816 "((X op Y) op Y) op X" as "T op T" where T is
3818 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3819 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3821 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3822 SUBST (XEXP (setsrc
, 0), newdest
);
3823 SUBST (XEXP (setsrc
, 1), newdest
);
3826 /* Split "((X op X) op Y) op Y)" as "T op T" where
3828 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3830 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3831 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3832 SUBST (XEXP (setsrc
, 0), newdest
);
3833 SUBST (XEXP (setsrc
, 1), newdest
);
3841 newi2pat
= gen_rtx_SET (newdest
, *split
);
3842 SUBST (*split
, newdest
);
3845 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3847 /* recog_for_combine might have added CLOBBERs to newi2pat.
3848 Make sure NEWPAT does not depend on the clobbered regs. */
3849 if (GET_CODE (newi2pat
) == PARALLEL
)
3850 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3851 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3853 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3854 if (reg_overlap_mentioned_p (reg
, newpat
))
3861 /* If the split point was a MULT and we didn't have one before,
3862 don't use one now. */
3863 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3864 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3868 /* Check for a case where we loaded from memory in a narrow mode and
3869 then sign extended it, but we need both registers. In that case,
3870 we have a PARALLEL with both loads from the same memory location.
3871 We can split this into a load from memory followed by a register-register
3872 copy. This saves at least one insn, more if register allocation can
3875 We cannot do this if the destination of the first assignment is a
3876 condition code register or cc0. We eliminate this case by making sure
3877 the SET_DEST and SET_SRC have the same mode.
3879 We cannot do this if the destination of the second assignment is
3880 a register that we have already assumed is zero-extended. Similarly
3881 for a SUBREG of such a register. */
3883 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3884 && GET_CODE (newpat
) == PARALLEL
3885 && XVECLEN (newpat
, 0) == 2
3886 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3887 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3888 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3889 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3890 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3891 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3892 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3893 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3895 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3896 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3897 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3899 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3900 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3901 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3902 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3903 != GET_MODE_MASK (word_mode
))))
3904 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3905 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3907 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3908 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3909 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3910 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3911 != GET_MODE_MASK (word_mode
)))))
3912 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3913 SET_SRC (XVECEXP (newpat
, 0, 1)))
3914 && ! find_reg_note (i3
, REG_UNUSED
,
3915 SET_DEST (XVECEXP (newpat
, 0, 0))))
3919 newi2pat
= XVECEXP (newpat
, 0, 0);
3920 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3921 newpat
= XVECEXP (newpat
, 0, 1);
3922 SUBST (SET_SRC (newpat
),
3923 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3924 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3926 if (i2_code_number
>= 0)
3927 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3929 if (insn_code_number
>= 0)
3933 /* Similarly, check for a case where we have a PARALLEL of two independent
3934 SETs but we started with three insns. In this case, we can do the sets
3935 as two separate insns. This case occurs when some SET allows two
3936 other insns to combine, but the destination of that SET is still live.
3938 Also do this if we started with two insns and (at least) one of the
3939 resulting sets is a noop; this noop will be deleted later. */
3941 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3942 && GET_CODE (newpat
) == PARALLEL
3943 && XVECLEN (newpat
, 0) == 2
3944 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3945 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3946 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3947 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3948 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3949 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3950 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3951 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3952 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3953 XVECEXP (newpat
, 0, 0))
3954 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3955 XVECEXP (newpat
, 0, 1))
3956 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3957 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3959 rtx set0
= XVECEXP (newpat
, 0, 0);
3960 rtx set1
= XVECEXP (newpat
, 0, 1);
3962 /* Normally, it doesn't matter which of the two is done first,
3963 but the one that references cc0 can't be the second, and
3964 one which uses any regs/memory set in between i2 and i3 can't
3965 be first. The PARALLEL might also have been pre-existing in i3,
3966 so we need to make sure that we won't wrongly hoist a SET to i2
3967 that would conflict with a death note present in there. */
3968 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3969 && !(REG_P (SET_DEST (set1
))
3970 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3971 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3972 && find_reg_note (i2
, REG_DEAD
,
3973 SUBREG_REG (SET_DEST (set1
))))
3974 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3975 /* If I3 is a jump, ensure that set0 is a jump so that
3976 we do not create invalid RTL. */
3977 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3983 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3984 && !(REG_P (SET_DEST (set0
))
3985 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3986 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3987 && find_reg_note (i2
, REG_DEAD
,
3988 SUBREG_REG (SET_DEST (set0
))))
3989 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3990 /* If I3 is a jump, ensure that set1 is a jump so that
3991 we do not create invalid RTL. */
3992 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4004 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4006 if (i2_code_number
>= 0)
4008 /* recog_for_combine might have added CLOBBERs to newi2pat.
4009 Make sure NEWPAT does not depend on the clobbered regs. */
4010 if (GET_CODE (newi2pat
) == PARALLEL
)
4012 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4013 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4015 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4016 if (reg_overlap_mentioned_p (reg
, newpat
))
4024 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4028 /* If it still isn't recognized, fail and change things back the way they
4030 if ((insn_code_number
< 0
4031 /* Is the result a reasonable ASM_OPERANDS? */
4032 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4038 /* If we had to change another insn, make sure it is valid also. */
4039 if (undobuf
.other_insn
)
4041 CLEAR_HARD_REG_SET (newpat_used_regs
);
4043 other_pat
= PATTERN (undobuf
.other_insn
);
4044 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4047 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4054 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4055 they are adjacent to each other or not. */
4058 rtx_insn
*p
= prev_nonnote_insn (i3
);
4059 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4060 && sets_cc0_p (newi2pat
))
4067 /* Only allow this combination if insn_rtx_costs reports that the
4068 replacement instructions are cheaper than the originals. */
4069 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4075 if (MAY_HAVE_DEBUG_INSNS
)
4079 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4080 if (undo
->kind
== UNDO_MODE
)
4082 rtx reg
= *undo
->where
.r
;
4083 machine_mode new_mode
= GET_MODE (reg
);
4084 machine_mode old_mode
= undo
->old_contents
.m
;
4086 /* Temporarily revert mode back. */
4087 adjust_reg_mode (reg
, old_mode
);
4089 if (reg
== i2dest
&& i2scratch
)
4091 /* If we used i2dest as a scratch register with a
4092 different mode, substitute it for the original
4093 i2src while its original mode is temporarily
4094 restored, and then clear i2scratch so that we don't
4095 do it again later. */
4096 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4099 /* Put back the new mode. */
4100 adjust_reg_mode (reg
, new_mode
);
4104 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4105 rtx_insn
*first
, *last
;
4110 last
= last_combined_insn
;
4115 last
= undobuf
.other_insn
;
4117 if (DF_INSN_LUID (last
)
4118 < DF_INSN_LUID (last_combined_insn
))
4119 last
= last_combined_insn
;
4122 /* We're dealing with a reg that changed mode but not
4123 meaning, so we want to turn it into a subreg for
4124 the new mode. However, because of REG sharing and
4125 because its mode had already changed, we have to do
4126 it in two steps. First, replace any debug uses of
4127 reg, with its original mode temporarily restored,
4128 with this copy we have created; then, replace the
4129 copy with the SUBREG of the original shared reg,
4130 once again changed to the new mode. */
4131 propagate_for_debug (first
, last
, reg
, tempreg
,
4133 adjust_reg_mode (reg
, new_mode
);
4134 propagate_for_debug (first
, last
, tempreg
,
4135 lowpart_subreg (old_mode
, reg
, new_mode
),
4141 /* If we will be able to accept this, we have made a
4142 change to the destination of I3. This requires us to
4143 do a few adjustments. */
4145 if (changed_i3_dest
)
4147 PATTERN (i3
) = newpat
;
4148 adjust_for_new_dest (i3
);
4151 /* We now know that we can do this combination. Merge the insns and
4152 update the status of registers and LOG_LINKS. */
4154 if (undobuf
.other_insn
)
4158 PATTERN (undobuf
.other_insn
) = other_pat
;
4160 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4161 ensure that they are still valid. Then add any non-duplicate
4162 notes added by recog_for_combine. */
4163 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4165 next
= XEXP (note
, 1);
4167 if ((REG_NOTE_KIND (note
) == REG_DEAD
4168 && !reg_referenced_p (XEXP (note
, 0),
4169 PATTERN (undobuf
.other_insn
)))
4170 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4171 && !reg_set_p (XEXP (note
, 0),
4172 PATTERN (undobuf
.other_insn
))))
4173 remove_note (undobuf
.other_insn
, note
);
4176 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4177 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4184 struct insn_link
*link
;
4187 /* I3 now uses what used to be its destination and which is now
4188 I2's destination. This requires us to do a few adjustments. */
4189 PATTERN (i3
) = newpat
;
4190 adjust_for_new_dest (i3
);
4192 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4195 However, some later insn might be using I2's dest and have
4196 a LOG_LINK pointing at I3. We must remove this link.
4197 The simplest way to remove the link is to point it at I1,
4198 which we know will be a NOTE. */
4200 /* newi2pat is usually a SET here; however, recog_for_combine might
4201 have added some clobbers. */
4202 if (GET_CODE (newi2pat
) == PARALLEL
)
4203 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4205 ni2dest
= SET_DEST (newi2pat
);
4207 for (insn
= NEXT_INSN (i3
);
4208 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4209 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4210 insn
= NEXT_INSN (insn
))
4212 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4214 FOR_EACH_LOG_LINK (link
, insn
)
4215 if (link
->insn
== i3
)
4224 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4225 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4228 /* Compute which registers we expect to eliminate. newi2pat may be setting
4229 either i3dest or i2dest, so we must check it. */
4230 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4231 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4234 /* For i1, we need to compute both local elimination and global
4235 elimination information with respect to newi2pat because i1dest
4236 may be the same as i3dest, in which case newi2pat may be setting
4237 i1dest. Global information is used when distributing REG_DEAD
4238 note for i2 and i3, in which case it does matter if newi2pat sets
4241 Local information is used when distributing REG_DEAD note for i1,
4242 in which case it doesn't matter if newi2pat sets i1dest or not.
4243 See PR62151, if we have four insns combination:
4245 i1: r1 <- i1src (using r0)
4247 i2: r0 <- i2src (using r1)
4248 i3: r3 <- i3src (using r0)
4250 From i1's point of view, r0 is eliminated, no matter if it is set
4251 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4252 should be discarded.
4254 Note local information only affects cases in forms like "I1->I2->I3",
4255 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4256 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4258 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4261 rtx elim_i1
= (local_elim_i1
== 0
4262 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4264 /* Same case as i1. */
4265 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4267 rtx elim_i0
= (local_elim_i0
== 0
4268 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4271 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4273 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4274 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4276 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4278 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4280 /* Ensure that we do not have something that should not be shared but
4281 occurs multiple times in the new insns. Check this by first
4282 resetting all the `used' flags and then copying anything is shared. */
4284 reset_used_flags (i3notes
);
4285 reset_used_flags (i2notes
);
4286 reset_used_flags (i1notes
);
4287 reset_used_flags (i0notes
);
4288 reset_used_flags (newpat
);
4289 reset_used_flags (newi2pat
);
4290 if (undobuf
.other_insn
)
4291 reset_used_flags (PATTERN (undobuf
.other_insn
));
4293 i3notes
= copy_rtx_if_shared (i3notes
);
4294 i2notes
= copy_rtx_if_shared (i2notes
);
4295 i1notes
= copy_rtx_if_shared (i1notes
);
4296 i0notes
= copy_rtx_if_shared (i0notes
);
4297 newpat
= copy_rtx_if_shared (newpat
);
4298 newi2pat
= copy_rtx_if_shared (newi2pat
);
4299 if (undobuf
.other_insn
)
4300 reset_used_flags (PATTERN (undobuf
.other_insn
));
4302 INSN_CODE (i3
) = insn_code_number
;
4303 PATTERN (i3
) = newpat
;
4305 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4307 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4309 reset_used_flags (call_usage
);
4310 call_usage
= copy_rtx (call_usage
);
4314 /* I2SRC must still be meaningful at this point. Some splitting
4315 operations can invalidate I2SRC, but those operations do not
4318 replace_rtx (call_usage
, i2dest
, i2src
);
4322 replace_rtx (call_usage
, i1dest
, i1src
);
4324 replace_rtx (call_usage
, i0dest
, i0src
);
4326 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4329 if (undobuf
.other_insn
)
4330 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4332 /* We had one special case above where I2 had more than one set and
4333 we replaced a destination of one of those sets with the destination
4334 of I3. In that case, we have to update LOG_LINKS of insns later
4335 in this basic block. Note that this (expensive) case is rare.
4337 Also, in this case, we must pretend that all REG_NOTEs for I2
4338 actually came from I3, so that REG_UNUSED notes from I2 will be
4339 properly handled. */
4341 if (i3_subst_into_i2
)
4343 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4344 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4345 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4346 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4347 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4348 && ! find_reg_note (i2
, REG_UNUSED
,
4349 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4350 for (temp_insn
= NEXT_INSN (i2
);
4352 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4353 || BB_HEAD (this_basic_block
) != temp_insn
);
4354 temp_insn
= NEXT_INSN (temp_insn
))
4355 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4356 FOR_EACH_LOG_LINK (link
, temp_insn
)
4357 if (link
->insn
== i2
)
4363 while (XEXP (link
, 1))
4364 link
= XEXP (link
, 1);
4365 XEXP (link
, 1) = i2notes
;
4372 LOG_LINKS (i3
) = NULL
;
4374 LOG_LINKS (i2
) = NULL
;
4379 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4380 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4382 INSN_CODE (i2
) = i2_code_number
;
4383 PATTERN (i2
) = newi2pat
;
4387 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4388 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4390 SET_INSN_DELETED (i2
);
4395 LOG_LINKS (i1
) = NULL
;
4397 if (MAY_HAVE_DEBUG_INSNS
)
4398 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4400 SET_INSN_DELETED (i1
);
4405 LOG_LINKS (i0
) = NULL
;
4407 if (MAY_HAVE_DEBUG_INSNS
)
4408 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4410 SET_INSN_DELETED (i0
);
4413 /* Get death notes for everything that is now used in either I3 or
4414 I2 and used to die in a previous insn. If we built two new
4415 patterns, move from I1 to I2 then I2 to I3 so that we get the
4416 proper movement on registers that I2 modifies. */
4419 from_luid
= DF_INSN_LUID (i0
);
4421 from_luid
= DF_INSN_LUID (i1
);
4423 from_luid
= DF_INSN_LUID (i2
);
4425 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4426 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4428 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4430 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4431 elim_i2
, elim_i1
, elim_i0
);
4433 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4434 elim_i2
, elim_i1
, elim_i0
);
4436 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4437 elim_i2
, local_elim_i1
, local_elim_i0
);
4439 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4440 elim_i2
, elim_i1
, local_elim_i0
);
4442 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4443 elim_i2
, elim_i1
, elim_i0
);
4445 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4446 know these are REG_UNUSED and want them to go to the desired insn,
4447 so we always pass it as i3. */
4449 if (newi2pat
&& new_i2_notes
)
4450 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4454 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4457 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4458 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4459 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4460 in that case, it might delete I2. Similarly for I2 and I1.
4461 Show an additional death due to the REG_DEAD note we make here. If
4462 we discard it in distribute_notes, we will decrement it again. */
4466 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4467 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4468 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4471 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4472 elim_i2
, elim_i1
, elim_i0
);
4475 if (i2dest_in_i2src
)
4477 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4478 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4479 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4480 NULL_RTX
, NULL_RTX
);
4482 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4483 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4486 if (i1dest_in_i1src
)
4488 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4489 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4490 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4491 NULL_RTX
, NULL_RTX
);
4493 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4494 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4497 if (i0dest_in_i0src
)
4499 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4500 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4501 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4502 NULL_RTX
, NULL_RTX
);
4504 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4505 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4508 distribute_links (i3links
);
4509 distribute_links (i2links
);
4510 distribute_links (i1links
);
4511 distribute_links (i0links
);
4515 struct insn_link
*link
;
4516 rtx_insn
*i2_insn
= 0;
4517 rtx i2_val
= 0, set
;
4519 /* The insn that used to set this register doesn't exist, and
4520 this life of the register may not exist either. See if one of
4521 I3's links points to an insn that sets I2DEST. If it does,
4522 that is now the last known value for I2DEST. If we don't update
4523 this and I2 set the register to a value that depended on its old
4524 contents, we will get confused. If this insn is used, thing
4525 will be set correctly in combine_instructions. */
4526 FOR_EACH_LOG_LINK (link
, i3
)
4527 if ((set
= single_set (link
->insn
)) != 0
4528 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4529 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4531 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4533 /* If the reg formerly set in I2 died only once and that was in I3,
4534 zero its use count so it won't make `reload' do any work. */
4536 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4537 && ! i2dest_in_i2src
4538 && REGNO (i2dest
) < reg_n_sets_max
)
4539 INC_REG_N_SETS (REGNO (i2dest
), -1);
4542 if (i1
&& REG_P (i1dest
))
4544 struct insn_link
*link
;
4545 rtx_insn
*i1_insn
= 0;
4546 rtx i1_val
= 0, set
;
4548 FOR_EACH_LOG_LINK (link
, i3
)
4549 if ((set
= single_set (link
->insn
)) != 0
4550 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4551 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4553 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4556 && ! i1dest_in_i1src
4557 && REGNO (i1dest
) < reg_n_sets_max
)
4558 INC_REG_N_SETS (REGNO (i1dest
), -1);
4561 if (i0
&& REG_P (i0dest
))
4563 struct insn_link
*link
;
4564 rtx_insn
*i0_insn
= 0;
4565 rtx i0_val
= 0, set
;
4567 FOR_EACH_LOG_LINK (link
, i3
)
4568 if ((set
= single_set (link
->insn
)) != 0
4569 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4570 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4572 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4575 && ! i0dest_in_i0src
4576 && REGNO (i0dest
) < reg_n_sets_max
)
4577 INC_REG_N_SETS (REGNO (i0dest
), -1);
4580 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4581 been made to this insn. The order is important, because newi2pat
4582 can affect nonzero_bits of newpat. */
4584 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4585 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4588 if (undobuf
.other_insn
!= NULL_RTX
)
4592 fprintf (dump_file
, "modifying other_insn ");
4593 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4595 df_insn_rescan (undobuf
.other_insn
);
4598 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4602 fprintf (dump_file
, "modifying insn i0 ");
4603 dump_insn_slim (dump_file
, i0
);
4605 df_insn_rescan (i0
);
4608 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4612 fprintf (dump_file
, "modifying insn i1 ");
4613 dump_insn_slim (dump_file
, i1
);
4615 df_insn_rescan (i1
);
4618 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4622 fprintf (dump_file
, "modifying insn i2 ");
4623 dump_insn_slim (dump_file
, i2
);
4625 df_insn_rescan (i2
);
4628 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4632 fprintf (dump_file
, "modifying insn i3 ");
4633 dump_insn_slim (dump_file
, i3
);
4635 df_insn_rescan (i3
);
4638 /* Set new_direct_jump_p if a new return or simple jump instruction
4639 has been created. Adjust the CFG accordingly. */
4640 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4642 *new_direct_jump_p
= 1;
4643 mark_jump_label (PATTERN (i3
), i3
, 0);
4644 update_cfg_for_uncondjump (i3
);
4647 if (undobuf
.other_insn
!= NULL_RTX
4648 && (returnjump_p (undobuf
.other_insn
)
4649 || any_uncondjump_p (undobuf
.other_insn
)))
4651 *new_direct_jump_p
= 1;
4652 update_cfg_for_uncondjump (undobuf
.other_insn
);
4655 /* A noop might also need cleaning up of CFG, if it comes from the
4656 simplification of a jump. */
4658 && GET_CODE (newpat
) == SET
4659 && SET_SRC (newpat
) == pc_rtx
4660 && SET_DEST (newpat
) == pc_rtx
)
4662 *new_direct_jump_p
= 1;
4663 update_cfg_for_uncondjump (i3
);
4666 if (undobuf
.other_insn
!= NULL_RTX
4667 && JUMP_P (undobuf
.other_insn
)
4668 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4669 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4670 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4672 *new_direct_jump_p
= 1;
4673 update_cfg_for_uncondjump (undobuf
.other_insn
);
4676 combine_successes
++;
4679 if (added_links_insn
4680 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4681 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4682 return added_links_insn
;
4684 return newi2pat
? i2
: i3
;
4687 /* Get a marker for undoing to the current state. */
4690 get_undo_marker (void)
4692 return undobuf
.undos
;
4695 /* Undo the modifications up to the marker. */
4698 undo_to_marker (void *marker
)
4700 struct undo
*undo
, *next
;
4702 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4710 *undo
->where
.r
= undo
->old_contents
.r
;
4713 *undo
->where
.i
= undo
->old_contents
.i
;
4716 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4719 *undo
->where
.l
= undo
->old_contents
.l
;
4725 undo
->next
= undobuf
.frees
;
4726 undobuf
.frees
= undo
;
4729 undobuf
.undos
= (struct undo
*) marker
;
4732 /* Undo all the modifications recorded in undobuf. */
4740 /* We've committed to accepting the changes we made. Move all
4741 of the undos to the free list. */
4746 struct undo
*undo
, *next
;
4748 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4751 undo
->next
= undobuf
.frees
;
4752 undobuf
.frees
= undo
;
4757 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4758 where we have an arithmetic expression and return that point. LOC will
4761 try_combine will call this function to see if an insn can be split into
4765 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4768 enum rtx_code code
= GET_CODE (x
);
4770 unsigned HOST_WIDE_INT len
= 0;
4771 HOST_WIDE_INT pos
= 0;
4773 rtx inner
= NULL_RTX
;
4775 /* First special-case some codes. */
4779 #ifdef INSN_SCHEDULING
4780 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4782 if (MEM_P (SUBREG_REG (x
)))
4785 return find_split_point (&SUBREG_REG (x
), insn
, false);
4788 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4789 using LO_SUM and HIGH. */
4790 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4791 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4793 machine_mode address_mode
= get_address_mode (x
);
4796 gen_rtx_LO_SUM (address_mode
,
4797 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4799 return &XEXP (XEXP (x
, 0), 0);
4802 /* If we have a PLUS whose second operand is a constant and the
4803 address is not valid, perhaps will can split it up using
4804 the machine-specific way to split large constants. We use
4805 the first pseudo-reg (one of the virtual regs) as a placeholder;
4806 it will not remain in the result. */
4807 if (GET_CODE (XEXP (x
, 0)) == PLUS
4808 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4809 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4810 MEM_ADDR_SPACE (x
)))
4812 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4813 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4816 /* This should have produced two insns, each of which sets our
4817 placeholder. If the source of the second is a valid address,
4818 we can make put both sources together and make a split point
4822 && NEXT_INSN (seq
) != NULL_RTX
4823 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4824 && NONJUMP_INSN_P (seq
)
4825 && GET_CODE (PATTERN (seq
)) == SET
4826 && SET_DEST (PATTERN (seq
)) == reg
4827 && ! reg_mentioned_p (reg
,
4828 SET_SRC (PATTERN (seq
)))
4829 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4830 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4831 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4832 && memory_address_addr_space_p
4833 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4834 MEM_ADDR_SPACE (x
)))
4836 rtx src1
= SET_SRC (PATTERN (seq
));
4837 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4839 /* Replace the placeholder in SRC2 with SRC1. If we can
4840 find where in SRC2 it was placed, that can become our
4841 split point and we can replace this address with SRC2.
4842 Just try two obvious places. */
4844 src2
= replace_rtx (src2
, reg
, src1
);
4846 if (XEXP (src2
, 0) == src1
)
4847 split
= &XEXP (src2
, 0);
4848 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4849 && XEXP (XEXP (src2
, 0), 0) == src1
)
4850 split
= &XEXP (XEXP (src2
, 0), 0);
4854 SUBST (XEXP (x
, 0), src2
);
4859 /* If that didn't work, perhaps the first operand is complex and
4860 needs to be computed separately, so make a split point there.
4861 This will occur on machines that just support REG + CONST
4862 and have a constant moved through some previous computation. */
4864 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4865 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4866 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4867 return &XEXP (XEXP (x
, 0), 0);
4870 /* If we have a PLUS whose first operand is complex, try computing it
4871 separately by making a split there. */
4872 if (GET_CODE (XEXP (x
, 0)) == PLUS
4873 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4875 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4876 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4877 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4878 return &XEXP (XEXP (x
, 0), 0);
4882 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4883 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4884 we need to put the operand into a register. So split at that
4887 if (SET_DEST (x
) == cc0_rtx
4888 && GET_CODE (SET_SRC (x
)) != COMPARE
4889 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4890 && !OBJECT_P (SET_SRC (x
))
4891 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4892 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4893 return &SET_SRC (x
);
4895 /* See if we can split SET_SRC as it stands. */
4896 split
= find_split_point (&SET_SRC (x
), insn
, true);
4897 if (split
&& split
!= &SET_SRC (x
))
4900 /* See if we can split SET_DEST as it stands. */
4901 split
= find_split_point (&SET_DEST (x
), insn
, false);
4902 if (split
&& split
!= &SET_DEST (x
))
4905 /* See if this is a bitfield assignment with everything constant. If
4906 so, this is an IOR of an AND, so split it into that. */
4907 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4908 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4909 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4910 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4911 && CONST_INT_P (SET_SRC (x
))
4912 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4913 + INTVAL (XEXP (SET_DEST (x
), 2)))
4914 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4915 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4917 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4918 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4919 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4920 rtx dest
= XEXP (SET_DEST (x
), 0);
4921 machine_mode mode
= GET_MODE (dest
);
4922 unsigned HOST_WIDE_INT mask
4923 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4926 if (BITS_BIG_ENDIAN
)
4927 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4929 or_mask
= gen_int_mode (src
<< pos
, mode
);
4932 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4935 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4937 simplify_gen_binary (IOR
, mode
,
4938 simplify_gen_binary (AND
, mode
,
4943 SUBST (SET_DEST (x
), dest
);
4945 split
= find_split_point (&SET_SRC (x
), insn
, true);
4946 if (split
&& split
!= &SET_SRC (x
))
4950 /* Otherwise, see if this is an operation that we can split into two.
4951 If so, try to split that. */
4952 code
= GET_CODE (SET_SRC (x
));
4957 /* If we are AND'ing with a large constant that is only a single
4958 bit and the result is only being used in a context where we
4959 need to know if it is zero or nonzero, replace it with a bit
4960 extraction. This will avoid the large constant, which might
4961 have taken more than one insn to make. If the constant were
4962 not a valid argument to the AND but took only one insn to make,
4963 this is no worse, but if it took more than one insn, it will
4966 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4967 && REG_P (XEXP (SET_SRC (x
), 0))
4968 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4969 && REG_P (SET_DEST (x
))
4970 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4971 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4972 && XEXP (*split
, 0) == SET_DEST (x
)
4973 && XEXP (*split
, 1) == const0_rtx
)
4975 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4976 XEXP (SET_SRC (x
), 0),
4977 pos
, NULL_RTX
, 1, 1, 0, 0);
4978 if (extraction
!= 0)
4980 SUBST (SET_SRC (x
), extraction
);
4981 return find_split_point (loc
, insn
, false);
4987 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4988 is known to be on, this can be converted into a NEG of a shift. */
4989 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4990 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4991 && 1 <= (pos
= exact_log2
4992 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4993 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4995 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4999 gen_rtx_LSHIFTRT (mode
,
5000 XEXP (SET_SRC (x
), 0),
5003 split
= find_split_point (&SET_SRC (x
), insn
, true);
5004 if (split
&& split
!= &SET_SRC (x
))
5010 inner
= XEXP (SET_SRC (x
), 0);
5012 /* We can't optimize if either mode is a partial integer
5013 mode as we don't know how many bits are significant
5015 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5016 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5020 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5026 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5027 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5029 inner
= XEXP (SET_SRC (x
), 0);
5030 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5031 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5033 if (BITS_BIG_ENDIAN
)
5034 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5035 unsignedp
= (code
== ZERO_EXTRACT
);
5044 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5046 machine_mode mode
= GET_MODE (SET_SRC (x
));
5048 /* For unsigned, we have a choice of a shift followed by an
5049 AND or two shifts. Use two shifts for field sizes where the
5050 constant might be too large. We assume here that we can
5051 always at least get 8-bit constants in an AND insn, which is
5052 true for every current RISC. */
5054 if (unsignedp
&& len
<= 8)
5056 unsigned HOST_WIDE_INT mask
5057 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
5061 (mode
, gen_lowpart (mode
, inner
),
5063 gen_int_mode (mask
, mode
)));
5065 split
= find_split_point (&SET_SRC (x
), insn
, true);
5066 if (split
&& split
!= &SET_SRC (x
))
5073 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5074 gen_rtx_ASHIFT (mode
,
5075 gen_lowpart (mode
, inner
),
5076 GEN_INT (GET_MODE_PRECISION (mode
)
5078 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5080 split
= find_split_point (&SET_SRC (x
), insn
, true);
5081 if (split
&& split
!= &SET_SRC (x
))
5086 /* See if this is a simple operation with a constant as the second
5087 operand. It might be that this constant is out of range and hence
5088 could be used as a split point. */
5089 if (BINARY_P (SET_SRC (x
))
5090 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5091 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5092 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5093 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5094 return &XEXP (SET_SRC (x
), 1);
5096 /* Finally, see if this is a simple operation with its first operand
5097 not in a register. The operation might require this operand in a
5098 register, so return it as a split point. We can always do this
5099 because if the first operand were another operation, we would have
5100 already found it as a split point. */
5101 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5102 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5103 return &XEXP (SET_SRC (x
), 0);
5109 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5110 it is better to write this as (not (ior A B)) so we can split it.
5111 Similarly for IOR. */
5112 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5115 gen_rtx_NOT (GET_MODE (x
),
5116 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5118 XEXP (XEXP (x
, 0), 0),
5119 XEXP (XEXP (x
, 1), 0))));
5120 return find_split_point (loc
, insn
, set_src
);
5123 /* Many RISC machines have a large set of logical insns. If the
5124 second operand is a NOT, put it first so we will try to split the
5125 other operand first. */
5126 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5128 rtx tem
= XEXP (x
, 0);
5129 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5130 SUBST (XEXP (x
, 1), tem
);
5136 /* Canonicalization can produce (minus A (mult B C)), where C is a
5137 constant. It may be better to try splitting (plus (mult B -C) A)
5138 instead if this isn't a multiply by a power of two. */
5139 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5140 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5141 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
5143 machine_mode mode
= GET_MODE (x
);
5144 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5145 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5146 SUBST (*loc
, gen_rtx_PLUS (mode
,
5148 XEXP (XEXP (x
, 1), 0),
5149 gen_int_mode (other_int
,
5152 return find_split_point (loc
, insn
, set_src
);
5155 /* Split at a multiply-accumulate instruction. However if this is
5156 the SET_SRC, we likely do not have such an instruction and it's
5157 worthless to try this split. */
5159 && (GET_CODE (XEXP (x
, 0)) == MULT
5160 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5161 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5168 /* Otherwise, select our actions depending on our rtx class. */
5169 switch (GET_RTX_CLASS (code
))
5171 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5173 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5176 /* ... fall through ... */
5178 case RTX_COMM_ARITH
:
5180 case RTX_COMM_COMPARE
:
5181 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5184 /* ... fall through ... */
5186 /* Some machines have (and (shift ...) ...) insns. If X is not
5187 an AND, but XEXP (X, 0) is, use it as our split point. */
5188 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5189 return &XEXP (x
, 0);
5191 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5197 /* Otherwise, we don't have a split point. */
5202 /* Throughout X, replace FROM with TO, and return the result.
5203 The result is TO if X is FROM;
5204 otherwise the result is X, but its contents may have been modified.
5205 If they were modified, a record was made in undobuf so that
5206 undo_all will (among other things) return X to its original state.
5208 If the number of changes necessary is too much to record to undo,
5209 the excess changes are not made, so the result is invalid.
5210 The changes already made can still be undone.
5211 undobuf.num_undo is incremented for such changes, so by testing that
5212 the caller can tell whether the result is valid.
5214 `n_occurrences' is incremented each time FROM is replaced.
5216 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5218 IN_COND is nonzero if we are at the top level of a condition.
5220 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5221 by copying if `n_occurrences' is nonzero. */
5224 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5226 enum rtx_code code
= GET_CODE (x
);
5227 machine_mode op0_mode
= VOIDmode
;
5232 /* Two expressions are equal if they are identical copies of a shared
5233 RTX or if they are both registers with the same register number
5236 #define COMBINE_RTX_EQUAL_P(X,Y) \
5238 || (REG_P (X) && REG_P (Y) \
5239 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5241 /* Do not substitute into clobbers of regs -- this will never result in
5243 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5246 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5249 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5252 /* If X and FROM are the same register but different modes, they
5253 will not have been seen as equal above. However, the log links code
5254 will make a LOG_LINKS entry for that case. If we do nothing, we
5255 will try to rerecognize our original insn and, when it succeeds,
5256 we will delete the feeding insn, which is incorrect.
5258 So force this insn not to match in this (rare) case. */
5259 if (! in_dest
&& code
== REG
&& REG_P (from
)
5260 && reg_overlap_mentioned_p (x
, from
))
5261 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5263 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5264 of which may contain things that can be combined. */
5265 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5268 /* It is possible to have a subexpression appear twice in the insn.
5269 Suppose that FROM is a register that appears within TO.
5270 Then, after that subexpression has been scanned once by `subst',
5271 the second time it is scanned, TO may be found. If we were
5272 to scan TO here, we would find FROM within it and create a
5273 self-referent rtl structure which is completely wrong. */
5274 if (COMBINE_RTX_EQUAL_P (x
, to
))
5277 /* Parallel asm_operands need special attention because all of the
5278 inputs are shared across the arms. Furthermore, unsharing the
5279 rtl results in recognition failures. Failure to handle this case
5280 specially can result in circular rtl.
5282 Solve this by doing a normal pass across the first entry of the
5283 parallel, and only processing the SET_DESTs of the subsequent
5286 if (code
== PARALLEL
5287 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5288 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5290 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5292 /* If this substitution failed, this whole thing fails. */
5293 if (GET_CODE (new_rtx
) == CLOBBER
5294 && XEXP (new_rtx
, 0) == const0_rtx
)
5297 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5299 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5301 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5304 && GET_CODE (dest
) != CC0
5305 && GET_CODE (dest
) != PC
)
5307 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5309 /* If this substitution failed, this whole thing fails. */
5310 if (GET_CODE (new_rtx
) == CLOBBER
5311 && XEXP (new_rtx
, 0) == const0_rtx
)
5314 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5320 len
= GET_RTX_LENGTH (code
);
5321 fmt
= GET_RTX_FORMAT (code
);
5323 /* We don't need to process a SET_DEST that is a register, CC0,
5324 or PC, so set up to skip this common case. All other cases
5325 where we want to suppress replacing something inside a
5326 SET_SRC are handled via the IN_DEST operand. */
5328 && (REG_P (SET_DEST (x
))
5329 || GET_CODE (SET_DEST (x
)) == CC0
5330 || GET_CODE (SET_DEST (x
)) == PC
))
5333 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5336 op0_mode
= GET_MODE (XEXP (x
, 0));
5338 for (i
= 0; i
< len
; i
++)
5343 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5345 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5347 new_rtx
= (unique_copy
&& n_occurrences
5348 ? copy_rtx (to
) : to
);
5353 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5356 /* If this substitution failed, this whole thing
5358 if (GET_CODE (new_rtx
) == CLOBBER
5359 && XEXP (new_rtx
, 0) == const0_rtx
)
5363 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5366 else if (fmt
[i
] == 'e')
5368 /* If this is a register being set, ignore it. */
5369 new_rtx
= XEXP (x
, i
);
5372 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5374 || code
== STRICT_LOW_PART
))
5377 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5379 /* In general, don't install a subreg involving two
5380 modes not tieable. It can worsen register
5381 allocation, and can even make invalid reload
5382 insns, since the reg inside may need to be copied
5383 from in the outside mode, and that may be invalid
5384 if it is an fp reg copied in integer mode.
5386 We allow two exceptions to this: It is valid if
5387 it is inside another SUBREG and the mode of that
5388 SUBREG and the mode of the inside of TO is
5389 tieable and it is valid if X is a SET that copies
5392 if (GET_CODE (to
) == SUBREG
5393 && ! MODES_TIEABLE_P (GET_MODE (to
),
5394 GET_MODE (SUBREG_REG (to
)))
5395 && ! (code
== SUBREG
5396 && MODES_TIEABLE_P (GET_MODE (x
),
5397 GET_MODE (SUBREG_REG (to
))))
5399 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5402 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5406 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5407 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5410 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5412 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5416 /* If we are in a SET_DEST, suppress most cases unless we
5417 have gone inside a MEM, in which case we want to
5418 simplify the address. We assume here that things that
5419 are actually part of the destination have their inner
5420 parts in the first expression. This is true for SUBREG,
5421 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5422 things aside from REG and MEM that should appear in a
5424 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5426 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5427 || code
== ZERO_EXTRACT
))
5430 code
== IF_THEN_ELSE
&& i
== 0,
5433 /* If we found that we will have to reject this combination,
5434 indicate that by returning the CLOBBER ourselves, rather than
5435 an expression containing it. This will speed things up as
5436 well as prevent accidents where two CLOBBERs are considered
5437 to be equal, thus producing an incorrect simplification. */
5439 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5442 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5444 machine_mode mode
= GET_MODE (x
);
5446 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5447 GET_MODE (SUBREG_REG (x
)),
5450 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5452 else if (CONST_SCALAR_INT_P (new_rtx
)
5453 && GET_CODE (x
) == ZERO_EXTEND
)
5455 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5456 new_rtx
, GET_MODE (XEXP (x
, 0)));
5460 SUBST (XEXP (x
, i
), new_rtx
);
5465 /* Check if we are loading something from the constant pool via float
5466 extension; in this case we would undo compress_float_constant
5467 optimization and degenerate constant load to an immediate value. */
5468 if (GET_CODE (x
) == FLOAT_EXTEND
5469 && MEM_P (XEXP (x
, 0))
5470 && MEM_READONLY_P (XEXP (x
, 0)))
5472 rtx tmp
= avoid_constant_pool_reference (x
);
5477 /* Try to simplify X. If the simplification changed the code, it is likely
5478 that further simplification will help, so loop, but limit the number
5479 of repetitions that will be performed. */
5481 for (i
= 0; i
< 4; i
++)
5483 /* If X is sufficiently simple, don't bother trying to do anything
5485 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5486 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5488 if (GET_CODE (x
) == code
)
5491 code
= GET_CODE (x
);
5493 /* We no longer know the original mode of operand 0 since we
5494 have changed the form of X) */
5495 op0_mode
= VOIDmode
;
5501 /* Simplify X, a piece of RTL. We just operate on the expression at the
5502 outer level; call `subst' to simplify recursively. Return the new
5505 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5506 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5510 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5513 enum rtx_code code
= GET_CODE (x
);
5514 machine_mode mode
= GET_MODE (x
);
5518 /* If this is a commutative operation, put a constant last and a complex
5519 expression first. We don't need to do this for comparisons here. */
5520 if (COMMUTATIVE_ARITH_P (x
)
5521 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5524 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5525 SUBST (XEXP (x
, 1), temp
);
5528 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5529 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5530 things. Check for cases where both arms are testing the same
5533 Don't do anything if all operands are very simple. */
5536 && ((!OBJECT_P (XEXP (x
, 0))
5537 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5538 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5539 || (!OBJECT_P (XEXP (x
, 1))
5540 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5541 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5543 && (!OBJECT_P (XEXP (x
, 0))
5544 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5545 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5547 rtx cond
, true_rtx
, false_rtx
;
5549 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5551 /* If everything is a comparison, what we have is highly unlikely
5552 to be simpler, so don't use it. */
5553 && ! (COMPARISON_P (x
)
5554 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5556 rtx cop1
= const0_rtx
;
5557 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5559 if (cond_code
== NE
&& COMPARISON_P (cond
))
5562 /* Simplify the alternative arms; this may collapse the true and
5563 false arms to store-flag values. Be careful to use copy_rtx
5564 here since true_rtx or false_rtx might share RTL with x as a
5565 result of the if_then_else_cond call above. */
5566 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5567 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5569 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5570 is unlikely to be simpler. */
5571 if (general_operand (true_rtx
, VOIDmode
)
5572 && general_operand (false_rtx
, VOIDmode
))
5574 enum rtx_code reversed
;
5576 /* Restarting if we generate a store-flag expression will cause
5577 us to loop. Just drop through in this case. */
5579 /* If the result values are STORE_FLAG_VALUE and zero, we can
5580 just make the comparison operation. */
5581 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5582 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5584 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5585 && ((reversed
= reversed_comparison_code_parts
5586 (cond_code
, cond
, cop1
, NULL
))
5588 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5591 /* Likewise, we can make the negate of a comparison operation
5592 if the result values are - STORE_FLAG_VALUE and zero. */
5593 else if (CONST_INT_P (true_rtx
)
5594 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5595 && false_rtx
== const0_rtx
)
5596 x
= simplify_gen_unary (NEG
, mode
,
5597 simplify_gen_relational (cond_code
,
5601 else if (CONST_INT_P (false_rtx
)
5602 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5603 && true_rtx
== const0_rtx
5604 && ((reversed
= reversed_comparison_code_parts
5605 (cond_code
, cond
, cop1
, NULL
))
5607 x
= simplify_gen_unary (NEG
, mode
,
5608 simplify_gen_relational (reversed
,
5613 return gen_rtx_IF_THEN_ELSE (mode
,
5614 simplify_gen_relational (cond_code
,
5619 true_rtx
, false_rtx
);
5621 code
= GET_CODE (x
);
5622 op0_mode
= VOIDmode
;
5627 /* Try to fold this expression in case we have constants that weren't
5630 switch (GET_RTX_CLASS (code
))
5633 if (op0_mode
== VOIDmode
)
5634 op0_mode
= GET_MODE (XEXP (x
, 0));
5635 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5638 case RTX_COMM_COMPARE
:
5640 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5641 if (cmp_mode
== VOIDmode
)
5643 cmp_mode
= GET_MODE (XEXP (x
, 1));
5644 if (cmp_mode
== VOIDmode
)
5645 cmp_mode
= op0_mode
;
5647 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5648 XEXP (x
, 0), XEXP (x
, 1));
5651 case RTX_COMM_ARITH
:
5653 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5655 case RTX_BITFIELD_OPS
:
5657 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5658 XEXP (x
, 1), XEXP (x
, 2));
5667 code
= GET_CODE (temp
);
5668 op0_mode
= VOIDmode
;
5669 mode
= GET_MODE (temp
);
5672 /* First see if we can apply the inverse distributive law. */
5673 if (code
== PLUS
|| code
== MINUS
5674 || code
== AND
|| code
== IOR
|| code
== XOR
)
5676 x
= apply_distributive_law (x
);
5677 code
= GET_CODE (x
);
5678 op0_mode
= VOIDmode
;
5681 /* If CODE is an associative operation not otherwise handled, see if we
5682 can associate some operands. This can win if they are constants or
5683 if they are logically related (i.e. (a & b) & a). */
5684 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5685 || code
== AND
|| code
== IOR
|| code
== XOR
5686 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5687 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5688 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5690 if (GET_CODE (XEXP (x
, 0)) == code
)
5692 rtx other
= XEXP (XEXP (x
, 0), 0);
5693 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5694 rtx inner_op1
= XEXP (x
, 1);
5697 /* Make sure we pass the constant operand if any as the second
5698 one if this is a commutative operation. */
5699 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5701 rtx tem
= inner_op0
;
5702 inner_op0
= inner_op1
;
5705 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5706 : code
== DIV
? MULT
5708 mode
, inner_op0
, inner_op1
);
5710 /* For commutative operations, try the other pair if that one
5712 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5714 other
= XEXP (XEXP (x
, 0), 1);
5715 inner
= simplify_binary_operation (code
, mode
,
5716 XEXP (XEXP (x
, 0), 0),
5721 return simplify_gen_binary (code
, mode
, other
, inner
);
5725 /* A little bit of algebraic simplification here. */
5729 /* Ensure that our address has any ASHIFTs converted to MULT in case
5730 address-recognizing predicates are called later. */
5731 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5732 SUBST (XEXP (x
, 0), temp
);
5736 if (op0_mode
== VOIDmode
)
5737 op0_mode
= GET_MODE (SUBREG_REG (x
));
5739 /* See if this can be moved to simplify_subreg. */
5740 if (CONSTANT_P (SUBREG_REG (x
))
5741 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5742 /* Don't call gen_lowpart if the inner mode
5743 is VOIDmode and we cannot simplify it, as SUBREG without
5744 inner mode is invalid. */
5745 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5746 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5747 return gen_lowpart (mode
, SUBREG_REG (x
));
5749 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5753 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5758 /* If op is known to have all lower bits zero, the result is zero. */
5760 && SCALAR_INT_MODE_P (mode
)
5761 && SCALAR_INT_MODE_P (op0_mode
)
5762 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5763 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5764 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5765 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5766 & GET_MODE_MASK (mode
)) == 0)
5767 return CONST0_RTX (mode
);
5770 /* Don't change the mode of the MEM if that would change the meaning
5772 if (MEM_P (SUBREG_REG (x
))
5773 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5774 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5775 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5776 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5778 /* Note that we cannot do any narrowing for non-constants since
5779 we might have been counting on using the fact that some bits were
5780 zero. We now do this in the SET. */
5785 temp
= expand_compound_operation (XEXP (x
, 0));
5787 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5788 replaced by (lshiftrt X C). This will convert
5789 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5791 if (GET_CODE (temp
) == ASHIFTRT
5792 && CONST_INT_P (XEXP (temp
, 1))
5793 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5794 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5795 INTVAL (XEXP (temp
, 1)));
5797 /* If X has only a single bit that might be nonzero, say, bit I, convert
5798 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5799 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5800 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5801 or a SUBREG of one since we'd be making the expression more
5802 complex if it was just a register. */
5805 && ! (GET_CODE (temp
) == SUBREG
5806 && REG_P (SUBREG_REG (temp
)))
5807 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5809 rtx temp1
= simplify_shift_const
5810 (NULL_RTX
, ASHIFTRT
, mode
,
5811 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5812 GET_MODE_PRECISION (mode
) - 1 - i
),
5813 GET_MODE_PRECISION (mode
) - 1 - i
);
5815 /* If all we did was surround TEMP with the two shifts, we
5816 haven't improved anything, so don't use it. Otherwise,
5817 we are better off with TEMP1. */
5818 if (GET_CODE (temp1
) != ASHIFTRT
5819 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5820 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5826 /* We can't handle truncation to a partial integer mode here
5827 because we don't know the real bitsize of the partial
5829 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5832 if (HWI_COMPUTABLE_MODE_P (mode
))
5834 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5835 GET_MODE_MASK (mode
), 0));
5837 /* We can truncate a constant value and return it. */
5838 if (CONST_INT_P (XEXP (x
, 0)))
5839 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5841 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5842 whose value is a comparison can be replaced with a subreg if
5843 STORE_FLAG_VALUE permits. */
5844 if (HWI_COMPUTABLE_MODE_P (mode
)
5845 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5846 && (temp
= get_last_value (XEXP (x
, 0)))
5847 && COMPARISON_P (temp
))
5848 return gen_lowpart (mode
, XEXP (x
, 0));
5852 /* (const (const X)) can become (const X). Do it this way rather than
5853 returning the inner CONST since CONST can be shared with a
5855 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5856 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5860 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5861 can add in an offset. find_split_point will split this address up
5862 again if it doesn't match. */
5863 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5864 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5869 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5870 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5871 bit-field and can be replaced by either a sign_extend or a
5872 sign_extract. The `and' may be a zero_extend and the two
5873 <c>, -<c> constants may be reversed. */
5874 if (GET_CODE (XEXP (x
, 0)) == XOR
5875 && CONST_INT_P (XEXP (x
, 1))
5876 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5877 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5878 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5879 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5880 && HWI_COMPUTABLE_MODE_P (mode
)
5881 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5882 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5883 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5884 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5885 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5886 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5887 == (unsigned int) i
+ 1))))
5888 return simplify_shift_const
5889 (NULL_RTX
, ASHIFTRT
, mode
,
5890 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5891 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5892 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5893 GET_MODE_PRECISION (mode
) - (i
+ 1));
5895 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5896 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5897 the bitsize of the mode - 1. This allows simplification of
5898 "a = (b & 8) == 0;" */
5899 if (XEXP (x
, 1) == constm1_rtx
5900 && !REG_P (XEXP (x
, 0))
5901 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5902 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5903 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5904 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5905 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5906 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5907 GET_MODE_PRECISION (mode
) - 1),
5908 GET_MODE_PRECISION (mode
) - 1);
5910 /* If we are adding two things that have no bits in common, convert
5911 the addition into an IOR. This will often be further simplified,
5912 for example in cases like ((a & 1) + (a & 2)), which can
5915 if (HWI_COMPUTABLE_MODE_P (mode
)
5916 && (nonzero_bits (XEXP (x
, 0), mode
)
5917 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5919 /* Try to simplify the expression further. */
5920 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5921 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5923 /* If we could, great. If not, do not go ahead with the IOR
5924 replacement, since PLUS appears in many special purpose
5925 address arithmetic instructions. */
5926 if (GET_CODE (temp
) != CLOBBER
5927 && (GET_CODE (temp
) != IOR
5928 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5929 || XEXP (temp
, 1) != XEXP (x
, 1))
5930 && (XEXP (temp
, 0) != XEXP (x
, 1)
5931 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5937 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5938 (and <foo> (const_int pow2-1)) */
5939 if (GET_CODE (XEXP (x
, 1)) == AND
5940 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5941 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5942 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5943 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5944 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5948 /* If we have (mult (plus A B) C), apply the distributive law and then
5949 the inverse distributive law to see if things simplify. This
5950 occurs mostly in addresses, often when unrolling loops. */
5952 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5954 rtx result
= distribute_and_simplify_rtx (x
, 0);
5959 /* Try simplify a*(b/c) as (a*b)/c. */
5960 if (FLOAT_MODE_P (mode
) && flag_associative_math
5961 && GET_CODE (XEXP (x
, 0)) == DIV
)
5963 rtx tem
= simplify_binary_operation (MULT
, mode
,
5964 XEXP (XEXP (x
, 0), 0),
5967 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5972 /* If this is a divide by a power of two, treat it as a shift if
5973 its first operand is a shift. */
5974 if (CONST_INT_P (XEXP (x
, 1))
5975 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5976 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5977 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5978 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5979 || GET_CODE (XEXP (x
, 0)) == ROTATE
5980 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5981 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5985 case GT
: case GTU
: case GE
: case GEU
:
5986 case LT
: case LTU
: case LE
: case LEU
:
5987 case UNEQ
: case LTGT
:
5988 case UNGT
: case UNGE
:
5989 case UNLT
: case UNLE
:
5990 case UNORDERED
: case ORDERED
:
5991 /* If the first operand is a condition code, we can't do anything
5993 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5994 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5995 && ! CC0_P (XEXP (x
, 0))))
5997 rtx op0
= XEXP (x
, 0);
5998 rtx op1
= XEXP (x
, 1);
5999 enum rtx_code new_code
;
6001 if (GET_CODE (op0
) == COMPARE
)
6002 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6004 /* Simplify our comparison, if possible. */
6005 new_code
= simplify_comparison (code
, &op0
, &op1
);
6007 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6008 if only the low-order bit is possibly nonzero in X (such as when
6009 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6010 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6011 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6014 Remove any ZERO_EXTRACT we made when thinking this was a
6015 comparison. It may now be simpler to use, e.g., an AND. If a
6016 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6017 the call to make_compound_operation in the SET case.
6019 Don't apply these optimizations if the caller would
6020 prefer a comparison rather than a value.
6021 E.g., for the condition in an IF_THEN_ELSE most targets need
6022 an explicit comparison. */
6027 else if (STORE_FLAG_VALUE
== 1
6028 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6029 && op1
== const0_rtx
6030 && mode
== GET_MODE (op0
)
6031 && nonzero_bits (op0
, mode
) == 1)
6032 return gen_lowpart (mode
,
6033 expand_compound_operation (op0
));
6035 else if (STORE_FLAG_VALUE
== 1
6036 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6037 && op1
== const0_rtx
6038 && mode
== GET_MODE (op0
)
6039 && (num_sign_bit_copies (op0
, mode
)
6040 == GET_MODE_PRECISION (mode
)))
6042 op0
= expand_compound_operation (op0
);
6043 return simplify_gen_unary (NEG
, mode
,
6044 gen_lowpart (mode
, op0
),
6048 else if (STORE_FLAG_VALUE
== 1
6049 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6050 && op1
== const0_rtx
6051 && mode
== GET_MODE (op0
)
6052 && nonzero_bits (op0
, mode
) == 1)
6054 op0
= expand_compound_operation (op0
);
6055 return simplify_gen_binary (XOR
, mode
,
6056 gen_lowpart (mode
, op0
),
6060 else if (STORE_FLAG_VALUE
== 1
6061 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6062 && op1
== const0_rtx
6063 && mode
== GET_MODE (op0
)
6064 && (num_sign_bit_copies (op0
, mode
)
6065 == GET_MODE_PRECISION (mode
)))
6067 op0
= expand_compound_operation (op0
);
6068 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6071 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6076 else if (STORE_FLAG_VALUE
== -1
6077 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6078 && op1
== const0_rtx
6079 && mode
== GET_MODE (op0
)
6080 && (num_sign_bit_copies (op0
, mode
)
6081 == GET_MODE_PRECISION (mode
)))
6082 return gen_lowpart (mode
,
6083 expand_compound_operation (op0
));
6085 else if (STORE_FLAG_VALUE
== -1
6086 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6087 && op1
== const0_rtx
6088 && mode
== GET_MODE (op0
)
6089 && nonzero_bits (op0
, mode
) == 1)
6091 op0
= expand_compound_operation (op0
);
6092 return simplify_gen_unary (NEG
, mode
,
6093 gen_lowpart (mode
, op0
),
6097 else if (STORE_FLAG_VALUE
== -1
6098 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6099 && op1
== const0_rtx
6100 && mode
== GET_MODE (op0
)
6101 && (num_sign_bit_copies (op0
, mode
)
6102 == GET_MODE_PRECISION (mode
)))
6104 op0
= expand_compound_operation (op0
);
6105 return simplify_gen_unary (NOT
, mode
,
6106 gen_lowpart (mode
, op0
),
6110 /* If X is 0/1, (eq X 0) is X-1. */
6111 else if (STORE_FLAG_VALUE
== -1
6112 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6113 && op1
== const0_rtx
6114 && mode
== GET_MODE (op0
)
6115 && nonzero_bits (op0
, mode
) == 1)
6117 op0
= expand_compound_operation (op0
);
6118 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6121 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6122 one bit that might be nonzero, we can convert (ne x 0) to
6123 (ashift x c) where C puts the bit in the sign bit. Remove any
6124 AND with STORE_FLAG_VALUE when we are done, since we are only
6125 going to test the sign bit. */
6126 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6127 && HWI_COMPUTABLE_MODE_P (mode
)
6128 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6129 && op1
== const0_rtx
6130 && mode
== GET_MODE (op0
)
6131 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6133 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6134 expand_compound_operation (op0
),
6135 GET_MODE_PRECISION (mode
) - 1 - i
);
6136 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6142 /* If the code changed, return a whole new comparison.
6143 We also need to avoid using SUBST in cases where
6144 simplify_comparison has widened a comparison with a CONST_INT,
6145 since in that case the wider CONST_INT may fail the sanity
6146 checks in do_SUBST. */
6147 if (new_code
!= code
6148 || (CONST_INT_P (op1
)
6149 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6150 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6151 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6153 /* Otherwise, keep this operation, but maybe change its operands.
6154 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6155 SUBST (XEXP (x
, 0), op0
);
6156 SUBST (XEXP (x
, 1), op1
);
6161 return simplify_if_then_else (x
);
6167 /* If we are processing SET_DEST, we are done. */
6171 return expand_compound_operation (x
);
6174 return simplify_set (x
);
6178 return simplify_logical (x
);
6185 /* If this is a shift by a constant amount, simplify it. */
6186 if (CONST_INT_P (XEXP (x
, 1)))
6187 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6188 INTVAL (XEXP (x
, 1)));
6190 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6192 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6193 ((unsigned HOST_WIDE_INT
) 1
6194 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6206 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6209 simplify_if_then_else (rtx x
)
6211 machine_mode mode
= GET_MODE (x
);
6212 rtx cond
= XEXP (x
, 0);
6213 rtx true_rtx
= XEXP (x
, 1);
6214 rtx false_rtx
= XEXP (x
, 2);
6215 enum rtx_code true_code
= GET_CODE (cond
);
6216 int comparison_p
= COMPARISON_P (cond
);
6219 enum rtx_code false_code
;
6222 /* Simplify storing of the truth value. */
6223 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6224 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6225 XEXP (cond
, 0), XEXP (cond
, 1));
6227 /* Also when the truth value has to be reversed. */
6229 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6230 && (reversed
= reversed_comparison (cond
, mode
)))
6233 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6234 in it is being compared against certain values. Get the true and false
6235 comparisons and see if that says anything about the value of each arm. */
6238 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6240 && REG_P (XEXP (cond
, 0)))
6243 rtx from
= XEXP (cond
, 0);
6244 rtx true_val
= XEXP (cond
, 1);
6245 rtx false_val
= true_val
;
6248 /* If FALSE_CODE is EQ, swap the codes and arms. */
6250 if (false_code
== EQ
)
6252 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6253 std::swap (true_rtx
, false_rtx
);
6256 /* If we are comparing against zero and the expression being tested has
6257 only a single bit that might be nonzero, that is its value when it is
6258 not equal to zero. Similarly if it is known to be -1 or 0. */
6260 if (true_code
== EQ
&& true_val
== const0_rtx
6261 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6264 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6266 else if (true_code
== EQ
&& true_val
== const0_rtx
6267 && (num_sign_bit_copies (from
, GET_MODE (from
))
6268 == GET_MODE_PRECISION (GET_MODE (from
))))
6271 false_val
= constm1_rtx
;
6274 /* Now simplify an arm if we know the value of the register in the
6275 branch and it is used in the arm. Be careful due to the potential
6276 of locally-shared RTL. */
6278 if (reg_mentioned_p (from
, true_rtx
))
6279 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6281 pc_rtx
, pc_rtx
, 0, 0, 0);
6282 if (reg_mentioned_p (from
, false_rtx
))
6283 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6285 pc_rtx
, pc_rtx
, 0, 0, 0);
6287 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6288 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6290 true_rtx
= XEXP (x
, 1);
6291 false_rtx
= XEXP (x
, 2);
6292 true_code
= GET_CODE (cond
);
6295 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6296 reversed, do so to avoid needing two sets of patterns for
6297 subtract-and-branch insns. Similarly if we have a constant in the true
6298 arm, the false arm is the same as the first operand of the comparison, or
6299 the false arm is more complicated than the true arm. */
6302 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6303 && (true_rtx
== pc_rtx
6304 || (CONSTANT_P (true_rtx
)
6305 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6306 || true_rtx
== const0_rtx
6307 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6308 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6309 && !OBJECT_P (false_rtx
))
6310 || reg_mentioned_p (true_rtx
, false_rtx
)
6311 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6313 true_code
= reversed_comparison_code (cond
, NULL
);
6314 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6315 SUBST (XEXP (x
, 1), false_rtx
);
6316 SUBST (XEXP (x
, 2), true_rtx
);
6318 std::swap (true_rtx
, false_rtx
);
6321 /* It is possible that the conditional has been simplified out. */
6322 true_code
= GET_CODE (cond
);
6323 comparison_p
= COMPARISON_P (cond
);
6326 /* If the two arms are identical, we don't need the comparison. */
6328 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6331 /* Convert a == b ? b : a to "a". */
6332 if (true_code
== EQ
&& ! side_effects_p (cond
)
6333 && !HONOR_NANS (mode
)
6334 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6335 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6337 else if (true_code
== NE
&& ! side_effects_p (cond
)
6338 && !HONOR_NANS (mode
)
6339 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6340 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6343 /* Look for cases where we have (abs x) or (neg (abs X)). */
6345 if (GET_MODE_CLASS (mode
) == MODE_INT
6347 && XEXP (cond
, 1) == const0_rtx
6348 && GET_CODE (false_rtx
) == NEG
6349 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6350 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6351 && ! side_effects_p (true_rtx
))
6356 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6360 simplify_gen_unary (NEG
, mode
,
6361 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6367 /* Look for MIN or MAX. */
6369 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6371 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6372 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6373 && ! side_effects_p (cond
))
6378 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6381 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6384 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6387 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6392 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6393 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6394 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6395 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6396 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6397 neither 1 or -1, but it isn't worth checking for. */
6399 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6401 && GET_MODE_CLASS (mode
) == MODE_INT
6402 && ! side_effects_p (x
))
6404 rtx t
= make_compound_operation (true_rtx
, SET
);
6405 rtx f
= make_compound_operation (false_rtx
, SET
);
6406 rtx cond_op0
= XEXP (cond
, 0);
6407 rtx cond_op1
= XEXP (cond
, 1);
6408 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6409 machine_mode m
= mode
;
6410 rtx z
= 0, c1
= NULL_RTX
;
6412 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6413 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6414 || GET_CODE (t
) == ASHIFT
6415 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6416 && rtx_equal_p (XEXP (t
, 0), f
))
6417 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6419 /* If an identity-zero op is commutative, check whether there
6420 would be a match if we swapped the operands. */
6421 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6422 || GET_CODE (t
) == XOR
)
6423 && rtx_equal_p (XEXP (t
, 1), f
))
6424 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6425 else if (GET_CODE (t
) == SIGN_EXTEND
6426 && (GET_CODE (XEXP (t
, 0)) == PLUS
6427 || GET_CODE (XEXP (t
, 0)) == MINUS
6428 || GET_CODE (XEXP (t
, 0)) == IOR
6429 || GET_CODE (XEXP (t
, 0)) == XOR
6430 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6431 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6432 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6433 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6434 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6435 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6436 && (num_sign_bit_copies (f
, GET_MODE (f
))
6438 (GET_MODE_PRECISION (mode
)
6439 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6441 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6442 extend_op
= SIGN_EXTEND
;
6443 m
= GET_MODE (XEXP (t
, 0));
6445 else if (GET_CODE (t
) == SIGN_EXTEND
6446 && (GET_CODE (XEXP (t
, 0)) == PLUS
6447 || GET_CODE (XEXP (t
, 0)) == IOR
6448 || GET_CODE (XEXP (t
, 0)) == XOR
)
6449 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6450 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6451 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6452 && (num_sign_bit_copies (f
, GET_MODE (f
))
6454 (GET_MODE_PRECISION (mode
)
6455 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6457 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6458 extend_op
= SIGN_EXTEND
;
6459 m
= GET_MODE (XEXP (t
, 0));
6461 else if (GET_CODE (t
) == ZERO_EXTEND
6462 && (GET_CODE (XEXP (t
, 0)) == PLUS
6463 || GET_CODE (XEXP (t
, 0)) == MINUS
6464 || GET_CODE (XEXP (t
, 0)) == IOR
6465 || GET_CODE (XEXP (t
, 0)) == XOR
6466 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6467 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6468 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6469 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6470 && HWI_COMPUTABLE_MODE_P (mode
)
6471 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6472 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6473 && ((nonzero_bits (f
, GET_MODE (f
))
6474 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6477 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6478 extend_op
= ZERO_EXTEND
;
6479 m
= GET_MODE (XEXP (t
, 0));
6481 else if (GET_CODE (t
) == ZERO_EXTEND
6482 && (GET_CODE (XEXP (t
, 0)) == PLUS
6483 || GET_CODE (XEXP (t
, 0)) == IOR
6484 || GET_CODE (XEXP (t
, 0)) == XOR
)
6485 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6486 && HWI_COMPUTABLE_MODE_P (mode
)
6487 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6488 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6489 && ((nonzero_bits (f
, GET_MODE (f
))
6490 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6493 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6494 extend_op
= ZERO_EXTEND
;
6495 m
= GET_MODE (XEXP (t
, 0));
6500 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6501 cond_op0
, cond_op1
),
6502 pc_rtx
, pc_rtx
, 0, 0, 0);
6503 temp
= simplify_gen_binary (MULT
, m
, temp
,
6504 simplify_gen_binary (MULT
, m
, c1
,
6506 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6507 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6509 if (extend_op
!= UNKNOWN
)
6510 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6516 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6517 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6518 negation of a single bit, we can convert this operation to a shift. We
6519 can actually do this more generally, but it doesn't seem worth it. */
6521 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6522 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6523 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6524 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6525 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6526 == GET_MODE_PRECISION (mode
))
6527 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6529 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6530 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6532 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6533 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6534 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6535 && GET_MODE (XEXP (cond
, 0)) == mode
6536 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6537 == nonzero_bits (XEXP (cond
, 0), mode
)
6538 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6539 return XEXP (cond
, 0);
6544 /* Simplify X, a SET expression. Return the new expression. */
6547 simplify_set (rtx x
)
6549 rtx src
= SET_SRC (x
);
6550 rtx dest
= SET_DEST (x
);
6552 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6553 rtx_insn
*other_insn
;
6556 /* (set (pc) (return)) gets written as (return). */
6557 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6560 /* Now that we know for sure which bits of SRC we are using, see if we can
6561 simplify the expression for the object knowing that we only need the
6564 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6566 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6567 SUBST (SET_SRC (x
), src
);
6570 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6571 the comparison result and try to simplify it unless we already have used
6572 undobuf.other_insn. */
6573 if ((GET_MODE_CLASS (mode
) == MODE_CC
6574 || GET_CODE (src
) == COMPARE
6576 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6577 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6578 && COMPARISON_P (*cc_use
)
6579 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6581 enum rtx_code old_code
= GET_CODE (*cc_use
);
6582 enum rtx_code new_code
;
6584 int other_changed
= 0;
6585 rtx inner_compare
= NULL_RTX
;
6586 machine_mode compare_mode
= GET_MODE (dest
);
6588 if (GET_CODE (src
) == COMPARE
)
6590 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6591 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6593 inner_compare
= op0
;
6594 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6598 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6600 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6603 new_code
= old_code
;
6604 else if (!CONSTANT_P (tmp
))
6606 new_code
= GET_CODE (tmp
);
6607 op0
= XEXP (tmp
, 0);
6608 op1
= XEXP (tmp
, 1);
6612 rtx pat
= PATTERN (other_insn
);
6613 undobuf
.other_insn
= other_insn
;
6614 SUBST (*cc_use
, tmp
);
6616 /* Attempt to simplify CC user. */
6617 if (GET_CODE (pat
) == SET
)
6619 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6620 if (new_rtx
!= NULL_RTX
)
6621 SUBST (SET_SRC (pat
), new_rtx
);
6624 /* Convert X into a no-op move. */
6625 SUBST (SET_DEST (x
), pc_rtx
);
6626 SUBST (SET_SRC (x
), pc_rtx
);
6630 /* Simplify our comparison, if possible. */
6631 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6633 #ifdef SELECT_CC_MODE
6634 /* If this machine has CC modes other than CCmode, check to see if we
6635 need to use a different CC mode here. */
6636 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6637 compare_mode
= GET_MODE (op0
);
6638 else if (inner_compare
6639 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6640 && new_code
== old_code
6641 && op0
== XEXP (inner_compare
, 0)
6642 && op1
== XEXP (inner_compare
, 1))
6643 compare_mode
= GET_MODE (inner_compare
);
6645 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6647 /* If the mode changed, we have to change SET_DEST, the mode in the
6648 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6649 a hard register, just build new versions with the proper mode. If it
6650 is a pseudo, we lose unless it is only time we set the pseudo, in
6651 which case we can safely change its mode. */
6652 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6654 if (can_change_dest_mode (dest
, 0, compare_mode
))
6656 unsigned int regno
= REGNO (dest
);
6659 if (regno
< FIRST_PSEUDO_REGISTER
)
6660 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6663 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6664 new_dest
= regno_reg_rtx
[regno
];
6667 SUBST (SET_DEST (x
), new_dest
);
6668 SUBST (XEXP (*cc_use
, 0), new_dest
);
6674 #endif /* SELECT_CC_MODE */
6676 /* If the code changed, we have to build a new comparison in
6677 undobuf.other_insn. */
6678 if (new_code
!= old_code
)
6680 int other_changed_previously
= other_changed
;
6681 unsigned HOST_WIDE_INT mask
;
6682 rtx old_cc_use
= *cc_use
;
6684 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6688 /* If the only change we made was to change an EQ into an NE or
6689 vice versa, OP0 has only one bit that might be nonzero, and OP1
6690 is zero, check if changing the user of the condition code will
6691 produce a valid insn. If it won't, we can keep the original code
6692 in that insn by surrounding our operation with an XOR. */
6694 if (((old_code
== NE
&& new_code
== EQ
)
6695 || (old_code
== EQ
&& new_code
== NE
))
6696 && ! other_changed_previously
&& op1
== const0_rtx
6697 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6698 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6700 rtx pat
= PATTERN (other_insn
), note
= 0;
6702 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6703 && ! check_asm_operands (pat
)))
6705 *cc_use
= old_cc_use
;
6708 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6716 undobuf
.other_insn
= other_insn
;
6718 /* Don't generate a compare of a CC with 0, just use that CC. */
6719 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6721 SUBST (SET_SRC (x
), op0
);
6724 /* Otherwise, if we didn't previously have the same COMPARE we
6725 want, create it from scratch. */
6726 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6727 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6729 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6735 /* Get SET_SRC in a form where we have placed back any
6736 compound expressions. Then do the checks below. */
6737 src
= make_compound_operation (src
, SET
);
6738 SUBST (SET_SRC (x
), src
);
6741 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6742 and X being a REG or (subreg (reg)), we may be able to convert this to
6743 (set (subreg:m2 x) (op)).
6745 We can always do this if M1 is narrower than M2 because that means that
6746 we only care about the low bits of the result.
6748 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6749 perform a narrower operation than requested since the high-order bits will
6750 be undefined. On machine where it is defined, this transformation is safe
6751 as long as M1 and M2 have the same number of words. */
6753 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6754 && !OBJECT_P (SUBREG_REG (src
))
6755 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6757 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6758 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6759 #ifndef WORD_REGISTER_OPERATIONS
6760 && (GET_MODE_SIZE (GET_MODE (src
))
6761 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6763 #ifdef CANNOT_CHANGE_MODE_CLASS
6764 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6765 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6766 GET_MODE (SUBREG_REG (src
)),
6770 || (GET_CODE (dest
) == SUBREG
6771 && REG_P (SUBREG_REG (dest
)))))
6773 SUBST (SET_DEST (x
),
6774 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6776 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6778 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6781 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6784 && GET_CODE (src
) == SUBREG
6785 && subreg_lowpart_p (src
)
6786 && (GET_MODE_PRECISION (GET_MODE (src
))
6787 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6789 rtx inner
= SUBREG_REG (src
);
6790 machine_mode inner_mode
= GET_MODE (inner
);
6792 /* Here we make sure that we don't have a sign bit on. */
6793 if (val_signbit_known_clear_p (GET_MODE (src
),
6794 nonzero_bits (inner
, inner_mode
)))
6796 SUBST (SET_SRC (x
), inner
);
6801 #ifdef LOAD_EXTEND_OP
6802 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6803 would require a paradoxical subreg. Replace the subreg with a
6804 zero_extend to avoid the reload that would otherwise be required. */
6806 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6807 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6808 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6809 && SUBREG_BYTE (src
) == 0
6810 && paradoxical_subreg_p (src
)
6811 && MEM_P (SUBREG_REG (src
)))
6814 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6815 GET_MODE (src
), SUBREG_REG (src
)));
6821 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6822 are comparing an item known to be 0 or -1 against 0, use a logical
6823 operation instead. Check for one of the arms being an IOR of the other
6824 arm with some value. We compute three terms to be IOR'ed together. In
6825 practice, at most two will be nonzero. Then we do the IOR's. */
6827 if (GET_CODE (dest
) != PC
6828 && GET_CODE (src
) == IF_THEN_ELSE
6829 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6830 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6831 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6832 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6833 && (!HAVE_conditional_move
6834 || ! can_conditionally_move_p (GET_MODE (src
)))
6835 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6836 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6837 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6838 && ! side_effects_p (src
))
6840 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6841 ? XEXP (src
, 1) : XEXP (src
, 2));
6842 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6843 ? XEXP (src
, 2) : XEXP (src
, 1));
6844 rtx term1
= const0_rtx
, term2
, term3
;
6846 if (GET_CODE (true_rtx
) == IOR
6847 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6848 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6849 else if (GET_CODE (true_rtx
) == IOR
6850 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6851 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6852 else if (GET_CODE (false_rtx
) == IOR
6853 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6854 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6855 else if (GET_CODE (false_rtx
) == IOR
6856 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6857 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6859 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6860 XEXP (XEXP (src
, 0), 0), true_rtx
);
6861 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6862 simplify_gen_unary (NOT
, GET_MODE (src
),
6863 XEXP (XEXP (src
, 0), 0),
6868 simplify_gen_binary (IOR
, GET_MODE (src
),
6869 simplify_gen_binary (IOR
, GET_MODE (src
),
6876 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6877 whole thing fail. */
6878 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6880 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6883 /* Convert this into a field assignment operation, if possible. */
6884 return make_field_assignment (x
);
6887 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6891 simplify_logical (rtx x
)
6893 machine_mode mode
= GET_MODE (x
);
6894 rtx op0
= XEXP (x
, 0);
6895 rtx op1
= XEXP (x
, 1);
6897 switch (GET_CODE (x
))
6900 /* We can call simplify_and_const_int only if we don't lose
6901 any (sign) bits when converting INTVAL (op1) to
6902 "unsigned HOST_WIDE_INT". */
6903 if (CONST_INT_P (op1
)
6904 && (HWI_COMPUTABLE_MODE_P (mode
)
6905 || INTVAL (op1
) > 0))
6907 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6908 if (GET_CODE (x
) != AND
)
6915 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6916 apply the distributive law and then the inverse distributive
6917 law to see if things simplify. */
6918 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6920 rtx result
= distribute_and_simplify_rtx (x
, 0);
6924 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6926 rtx result
= distribute_and_simplify_rtx (x
, 1);
6933 /* If we have (ior (and A B) C), apply the distributive law and then
6934 the inverse distributive law to see if things simplify. */
6936 if (GET_CODE (op0
) == AND
)
6938 rtx result
= distribute_and_simplify_rtx (x
, 0);
6943 if (GET_CODE (op1
) == AND
)
6945 rtx result
= distribute_and_simplify_rtx (x
, 1);
6958 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6959 operations" because they can be replaced with two more basic operations.
6960 ZERO_EXTEND is also considered "compound" because it can be replaced with
6961 an AND operation, which is simpler, though only one operation.
6963 The function expand_compound_operation is called with an rtx expression
6964 and will convert it to the appropriate shifts and AND operations,
6965 simplifying at each stage.
6967 The function make_compound_operation is called to convert an expression
6968 consisting of shifts and ANDs into the equivalent compound expression.
6969 It is the inverse of this function, loosely speaking. */
6972 expand_compound_operation (rtx x
)
6974 unsigned HOST_WIDE_INT pos
= 0, len
;
6976 unsigned int modewidth
;
6979 switch (GET_CODE (x
))
6984 /* We can't necessarily use a const_int for a multiword mode;
6985 it depends on implicitly extending the value.
6986 Since we don't know the right way to extend it,
6987 we can't tell whether the implicit way is right.
6989 Even for a mode that is no wider than a const_int,
6990 we can't win, because we need to sign extend one of its bits through
6991 the rest of it, and we don't know which bit. */
6992 if (CONST_INT_P (XEXP (x
, 0)))
6995 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6996 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6997 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6998 reloaded. If not for that, MEM's would very rarely be safe.
7000 Reject MODEs bigger than a word, because we might not be able
7001 to reference a two-register group starting with an arbitrary register
7002 (and currently gen_lowpart might crash for a SUBREG). */
7004 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
7007 /* Reject MODEs that aren't scalar integers because turning vector
7008 or complex modes into shifts causes problems. */
7010 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7013 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7014 /* If the inner object has VOIDmode (the only way this can happen
7015 is if it is an ASM_OPERANDS), we can't do anything since we don't
7016 know how much masking to do. */
7025 /* ... fall through ... */
7028 /* If the operand is a CLOBBER, just return it. */
7029 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7032 if (!CONST_INT_P (XEXP (x
, 1))
7033 || !CONST_INT_P (XEXP (x
, 2))
7034 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7037 /* Reject MODEs that aren't scalar integers because turning vector
7038 or complex modes into shifts causes problems. */
7040 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7043 len
= INTVAL (XEXP (x
, 1));
7044 pos
= INTVAL (XEXP (x
, 2));
7046 /* This should stay within the object being extracted, fail otherwise. */
7047 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7050 if (BITS_BIG_ENDIAN
)
7051 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7058 /* Convert sign extension to zero extension, if we know that the high
7059 bit is not set, as this is easier to optimize. It will be converted
7060 back to cheaper alternative in make_extraction. */
7061 if (GET_CODE (x
) == SIGN_EXTEND
7062 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7063 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7064 & ~(((unsigned HOST_WIDE_INT
)
7065 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7069 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
7070 rtx temp2
= expand_compound_operation (temp
);
7072 /* Make sure this is a profitable operation. */
7073 if (set_src_cost (x
, optimize_this_for_speed_p
)
7074 > set_src_cost (temp2
, optimize_this_for_speed_p
))
7076 else if (set_src_cost (x
, optimize_this_for_speed_p
)
7077 > set_src_cost (temp
, optimize_this_for_speed_p
))
7083 /* We can optimize some special cases of ZERO_EXTEND. */
7084 if (GET_CODE (x
) == ZERO_EXTEND
)
7086 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7087 know that the last value didn't have any inappropriate bits
7089 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7090 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7091 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7092 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7093 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7094 return XEXP (XEXP (x
, 0), 0);
7096 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7097 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7098 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7099 && subreg_lowpart_p (XEXP (x
, 0))
7100 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7101 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7102 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7103 return SUBREG_REG (XEXP (x
, 0));
7105 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7106 is a comparison and STORE_FLAG_VALUE permits. This is like
7107 the first case, but it works even when GET_MODE (x) is larger
7108 than HOST_WIDE_INT. */
7109 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7110 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7111 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7112 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7113 <= HOST_BITS_PER_WIDE_INT
)
7114 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7115 return XEXP (XEXP (x
, 0), 0);
7117 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7118 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7119 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7120 && subreg_lowpart_p (XEXP (x
, 0))
7121 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7122 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7123 <= HOST_BITS_PER_WIDE_INT
)
7124 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7125 return SUBREG_REG (XEXP (x
, 0));
7129 /* If we reach here, we want to return a pair of shifts. The inner
7130 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7131 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7132 logical depending on the value of UNSIGNEDP.
7134 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7135 converted into an AND of a shift.
7137 We must check for the case where the left shift would have a negative
7138 count. This can happen in a case like (x >> 31) & 255 on machines
7139 that can't shift by a constant. On those machines, we would first
7140 combine the shift with the AND to produce a variable-position
7141 extraction. Then the constant of 31 would be substituted in
7142 to produce such a position. */
7144 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7145 if (modewidth
>= pos
+ len
)
7147 machine_mode mode
= GET_MODE (x
);
7148 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7149 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7151 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7152 tem
, modewidth
- pos
- len
);
7153 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7154 mode
, tem
, modewidth
- len
);
7156 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7157 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7158 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7161 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7163 /* Any other cases we can't handle. */
7166 /* If we couldn't do this for some reason, return the original
7168 if (GET_CODE (tem
) == CLOBBER
)
7174 /* X is a SET which contains an assignment of one object into
7175 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7176 or certain SUBREGS). If possible, convert it into a series of
7179 We half-heartedly support variable positions, but do not at all
7180 support variable lengths. */
7183 expand_field_assignment (const_rtx x
)
7186 rtx pos
; /* Always counts from low bit. */
7188 rtx mask
, cleared
, masked
;
7189 machine_mode compute_mode
;
7191 /* Loop until we find something we can't simplify. */
7194 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7195 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7197 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7198 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7199 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7201 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7202 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7204 inner
= XEXP (SET_DEST (x
), 0);
7205 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7206 pos
= XEXP (SET_DEST (x
), 2);
7208 /* A constant position should stay within the width of INNER. */
7209 if (CONST_INT_P (pos
)
7210 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7213 if (BITS_BIG_ENDIAN
)
7215 if (CONST_INT_P (pos
))
7216 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7218 else if (GET_CODE (pos
) == MINUS
7219 && CONST_INT_P (XEXP (pos
, 1))
7220 && (INTVAL (XEXP (pos
, 1))
7221 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7222 /* If position is ADJUST - X, new position is X. */
7223 pos
= XEXP (pos
, 0);
7226 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7227 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7228 gen_int_mode (prec
- len
,
7235 /* A SUBREG between two modes that occupy the same numbers of words
7236 can be done by moving the SUBREG to the source. */
7237 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7238 /* We need SUBREGs to compute nonzero_bits properly. */
7239 && nonzero_sign_valid
7240 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7241 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7242 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7243 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7245 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7247 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7254 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7255 inner
= SUBREG_REG (inner
);
7257 compute_mode
= GET_MODE (inner
);
7259 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7260 if (! SCALAR_INT_MODE_P (compute_mode
))
7264 /* Don't do anything for vector or complex integral types. */
7265 if (! FLOAT_MODE_P (compute_mode
))
7268 /* Try to find an integral mode to pun with. */
7269 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7270 if (imode
== BLKmode
)
7273 compute_mode
= imode
;
7274 inner
= gen_lowpart (imode
, inner
);
7277 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7278 if (len
>= HOST_BITS_PER_WIDE_INT
)
7281 /* Now compute the equivalent expression. Make a copy of INNER
7282 for the SET_DEST in case it is a MEM into which we will substitute;
7283 we don't want shared RTL in that case. */
7284 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7286 cleared
= simplify_gen_binary (AND
, compute_mode
,
7287 simplify_gen_unary (NOT
, compute_mode
,
7288 simplify_gen_binary (ASHIFT
,
7293 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7294 simplify_gen_binary (
7296 gen_lowpart (compute_mode
, SET_SRC (x
)),
7300 x
= gen_rtx_SET (copy_rtx (inner
),
7301 simplify_gen_binary (IOR
, compute_mode
,
7308 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7309 it is an RTX that represents the (variable) starting position; otherwise,
7310 POS is the (constant) starting bit position. Both are counted from the LSB.
7312 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7314 IN_DEST is nonzero if this is a reference in the destination of a SET.
7315 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7316 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7319 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7320 ZERO_EXTRACT should be built even for bits starting at bit 0.
7322 MODE is the desired mode of the result (if IN_DEST == 0).
7324 The result is an RTX for the extraction or NULL_RTX if the target
7328 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7329 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7330 int in_dest
, int in_compare
)
7332 /* This mode describes the size of the storage area
7333 to fetch the overall value from. Within that, we
7334 ignore the POS lowest bits, etc. */
7335 machine_mode is_mode
= GET_MODE (inner
);
7336 machine_mode inner_mode
;
7337 machine_mode wanted_inner_mode
;
7338 machine_mode wanted_inner_reg_mode
= word_mode
;
7339 machine_mode pos_mode
= word_mode
;
7340 machine_mode extraction_mode
= word_mode
;
7341 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7343 rtx orig_pos_rtx
= pos_rtx
;
7344 HOST_WIDE_INT orig_pos
;
7346 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7347 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7349 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7351 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7352 consider just the QI as the memory to extract from.
7353 The subreg adds or removes high bits; its mode is
7354 irrelevant to the meaning of this extraction,
7355 since POS and LEN count from the lsb. */
7356 if (MEM_P (SUBREG_REG (inner
)))
7357 is_mode
= GET_MODE (SUBREG_REG (inner
));
7358 inner
= SUBREG_REG (inner
);
7360 else if (GET_CODE (inner
) == ASHIFT
7361 && CONST_INT_P (XEXP (inner
, 1))
7362 && pos_rtx
== 0 && pos
== 0
7363 && len
> UINTVAL (XEXP (inner
, 1)))
7365 /* We're extracting the least significant bits of an rtx
7366 (ashift X (const_int C)), where LEN > C. Extract the
7367 least significant (LEN - C) bits of X, giving an rtx
7368 whose mode is MODE, then shift it left C times. */
7369 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7370 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7371 unsignedp
, in_dest
, in_compare
);
7373 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7375 else if (GET_CODE (inner
) == TRUNCATE
)
7376 inner
= XEXP (inner
, 0);
7378 inner_mode
= GET_MODE (inner
);
7380 /* See if this can be done without an extraction. We never can if the
7381 width of the field is not the same as that of some integer mode. For
7382 registers, we can only avoid the extraction if the position is at the
7383 low-order bit and this is either not in the destination or we have the
7384 appropriate STRICT_LOW_PART operation available.
7386 For MEM, we can avoid an extract if the field starts on an appropriate
7387 boundary and we can change the mode of the memory reference. */
7389 if (tmode
!= BLKmode
7390 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7392 && (inner_mode
== tmode
7394 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7395 || reg_truncated_to_mode (tmode
, inner
))
7398 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7399 || (MEM_P (inner
) && pos_rtx
== 0
7401 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7402 : BITS_PER_UNIT
)) == 0
7403 /* We can't do this if we are widening INNER_MODE (it
7404 may not be aligned, for one thing). */
7405 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7406 && (inner_mode
== tmode
7407 || (! mode_dependent_address_p (XEXP (inner
, 0),
7408 MEM_ADDR_SPACE (inner
))
7409 && ! MEM_VOLATILE_P (inner
))))))
7411 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7412 field. If the original and current mode are the same, we need not
7413 adjust the offset. Otherwise, we do if bytes big endian.
7415 If INNER is not a MEM, get a piece consisting of just the field
7416 of interest (in this case POS % BITS_PER_WORD must be 0). */
7420 HOST_WIDE_INT offset
;
7422 /* POS counts from lsb, but make OFFSET count in memory order. */
7423 if (BYTES_BIG_ENDIAN
)
7424 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7426 offset
= pos
/ BITS_PER_UNIT
;
7428 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7430 else if (REG_P (inner
))
7432 if (tmode
!= inner_mode
)
7434 /* We can't call gen_lowpart in a DEST since we
7435 always want a SUBREG (see below) and it would sometimes
7436 return a new hard register. */
7439 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7441 if (WORDS_BIG_ENDIAN
7442 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7443 final_word
= ((GET_MODE_SIZE (inner_mode
)
7444 - GET_MODE_SIZE (tmode
))
7445 / UNITS_PER_WORD
) - final_word
;
7447 final_word
*= UNITS_PER_WORD
;
7448 if (BYTES_BIG_ENDIAN
&&
7449 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7450 final_word
+= (GET_MODE_SIZE (inner_mode
)
7451 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7453 /* Avoid creating invalid subregs, for example when
7454 simplifying (x>>32)&255. */
7455 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7458 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7461 new_rtx
= gen_lowpart (tmode
, inner
);
7467 new_rtx
= force_to_mode (inner
, tmode
,
7468 len
>= HOST_BITS_PER_WIDE_INT
7469 ? ~(unsigned HOST_WIDE_INT
) 0
7470 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7473 /* If this extraction is going into the destination of a SET,
7474 make a STRICT_LOW_PART unless we made a MEM. */
7477 return (MEM_P (new_rtx
) ? new_rtx
7478 : (GET_CODE (new_rtx
) != SUBREG
7479 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7480 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7485 if (CONST_SCALAR_INT_P (new_rtx
))
7486 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7487 mode
, new_rtx
, tmode
);
7489 /* If we know that no extraneous bits are set, and that the high
7490 bit is not set, convert the extraction to the cheaper of
7491 sign and zero extension, that are equivalent in these cases. */
7492 if (flag_expensive_optimizations
7493 && (HWI_COMPUTABLE_MODE_P (tmode
)
7494 && ((nonzero_bits (new_rtx
, tmode
)
7495 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7498 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7499 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7501 /* Prefer ZERO_EXTENSION, since it gives more information to
7503 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7504 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7509 /* Otherwise, sign- or zero-extend unless we already are in the
7512 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7516 /* Unless this is a COMPARE or we have a funny memory reference,
7517 don't do anything with zero-extending field extracts starting at
7518 the low-order bit since they are simple AND operations. */
7519 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7520 && ! in_compare
&& unsignedp
)
7523 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7524 if the position is not a constant and the length is not 1. In all
7525 other cases, we would only be going outside our object in cases when
7526 an original shift would have been undefined. */
7528 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7529 || (pos_rtx
!= 0 && len
!= 1)))
7532 enum extraction_pattern pattern
= (in_dest
? EP_insv
7533 : unsignedp
? EP_extzv
: EP_extv
);
7535 /* If INNER is not from memory, we want it to have the mode of a register
7536 extraction pattern's structure operand, or word_mode if there is no
7537 such pattern. The same applies to extraction_mode and pos_mode
7538 and their respective operands.
7540 For memory, assume that the desired extraction_mode and pos_mode
7541 are the same as for a register operation, since at present we don't
7542 have named patterns for aligned memory structures. */
7543 struct extraction_insn insn
;
7544 if (get_best_reg_extraction_insn (&insn
, pattern
,
7545 GET_MODE_BITSIZE (inner_mode
), mode
))
7547 wanted_inner_reg_mode
= insn
.struct_mode
;
7548 pos_mode
= insn
.pos_mode
;
7549 extraction_mode
= insn
.field_mode
;
7552 /* Never narrow an object, since that might not be safe. */
7554 if (mode
!= VOIDmode
7555 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7556 extraction_mode
= mode
;
7559 wanted_inner_mode
= wanted_inner_reg_mode
;
7562 /* Be careful not to go beyond the extracted object and maintain the
7563 natural alignment of the memory. */
7564 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7565 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7566 > GET_MODE_BITSIZE (wanted_inner_mode
))
7568 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7569 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7575 if (BITS_BIG_ENDIAN
)
7577 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7578 BITS_BIG_ENDIAN style. If position is constant, compute new
7579 position. Otherwise, build subtraction.
7580 Note that POS is relative to the mode of the original argument.
7581 If it's a MEM we need to recompute POS relative to that.
7582 However, if we're extracting from (or inserting into) a register,
7583 we want to recompute POS relative to wanted_inner_mode. */
7584 int width
= (MEM_P (inner
)
7585 ? GET_MODE_BITSIZE (is_mode
)
7586 : GET_MODE_BITSIZE (wanted_inner_mode
));
7589 pos
= width
- len
- pos
;
7592 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7593 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7595 /* POS may be less than 0 now, but we check for that below.
7596 Note that it can only be less than 0 if !MEM_P (inner). */
7599 /* If INNER has a wider mode, and this is a constant extraction, try to
7600 make it smaller and adjust the byte to point to the byte containing
7602 if (wanted_inner_mode
!= VOIDmode
7603 && inner_mode
!= wanted_inner_mode
7605 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7607 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7608 && ! MEM_VOLATILE_P (inner
))
7612 /* The computations below will be correct if the machine is big
7613 endian in both bits and bytes or little endian in bits and bytes.
7614 If it is mixed, we must adjust. */
7616 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7617 adjust OFFSET to compensate. */
7618 if (BYTES_BIG_ENDIAN
7619 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7620 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7622 /* We can now move to the desired byte. */
7623 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7624 * GET_MODE_SIZE (wanted_inner_mode
);
7625 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7627 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7628 && is_mode
!= wanted_inner_mode
)
7629 offset
= (GET_MODE_SIZE (is_mode
)
7630 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7632 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7635 /* If INNER is not memory, get it into the proper mode. If we are changing
7636 its mode, POS must be a constant and smaller than the size of the new
7638 else if (!MEM_P (inner
))
7640 /* On the LHS, don't create paradoxical subregs implicitely truncating
7641 the register unless TRULY_NOOP_TRUNCATION. */
7643 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7647 if (GET_MODE (inner
) != wanted_inner_mode
7649 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7655 inner
= force_to_mode (inner
, wanted_inner_mode
,
7657 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7658 ? ~(unsigned HOST_WIDE_INT
) 0
7659 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7664 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7665 have to zero extend. Otherwise, we can just use a SUBREG. */
7667 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7669 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7670 GET_MODE (pos_rtx
));
7672 /* If we know that no extraneous bits are set, and that the high
7673 bit is not set, convert extraction to cheaper one - either
7674 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7676 if (flag_expensive_optimizations
7677 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7678 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7679 & ~(((unsigned HOST_WIDE_INT
)
7680 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7684 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7685 GET_MODE (pos_rtx
));
7687 /* Prefer ZERO_EXTENSION, since it gives more information to
7689 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7690 < set_src_cost (temp
, optimize_this_for_speed_p
))
7696 /* Make POS_RTX unless we already have it and it is correct. If we don't
7697 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7699 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7700 pos_rtx
= orig_pos_rtx
;
7702 else if (pos_rtx
== 0)
7703 pos_rtx
= GEN_INT (pos
);
7705 /* Make the required operation. See if we can use existing rtx. */
7706 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7707 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7709 new_rtx
= gen_lowpart (mode
, new_rtx
);
7714 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7715 with any other operations in X. Return X without that shift if so. */
7718 extract_left_shift (rtx x
, int count
)
7720 enum rtx_code code
= GET_CODE (x
);
7721 machine_mode mode
= GET_MODE (x
);
7727 /* This is the shift itself. If it is wide enough, we will return
7728 either the value being shifted if the shift count is equal to
7729 COUNT or a shift for the difference. */
7730 if (CONST_INT_P (XEXP (x
, 1))
7731 && INTVAL (XEXP (x
, 1)) >= count
)
7732 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7733 INTVAL (XEXP (x
, 1)) - count
);
7737 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7738 return simplify_gen_unary (code
, mode
, tem
, mode
);
7742 case PLUS
: case IOR
: case XOR
: case AND
:
7743 /* If we can safely shift this constant and we find the inner shift,
7744 make a new operation. */
7745 if (CONST_INT_P (XEXP (x
, 1))
7746 && (UINTVAL (XEXP (x
, 1))
7747 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7748 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7750 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7751 return simplify_gen_binary (code
, mode
, tem
,
7752 gen_int_mode (val
, mode
));
7763 /* Look at the expression rooted at X. Look for expressions
7764 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7765 Form these expressions.
7767 Return the new rtx, usually just X.
7769 Also, for machines like the VAX that don't have logical shift insns,
7770 try to convert logical to arithmetic shift operations in cases where
7771 they are equivalent. This undoes the canonicalizations to logical
7772 shifts done elsewhere.
7774 We try, as much as possible, to re-use rtl expressions to save memory.
7776 IN_CODE says what kind of expression we are processing. Normally, it is
7777 SET. In a memory address it is MEM. When processing the arguments of
7778 a comparison or a COMPARE against zero, it is COMPARE. */
7781 make_compound_operation (rtx x
, enum rtx_code in_code
)
7783 enum rtx_code code
= GET_CODE (x
);
7784 machine_mode mode
= GET_MODE (x
);
7785 int mode_width
= GET_MODE_PRECISION (mode
);
7787 enum rtx_code next_code
;
7793 /* Select the code to be used in recursive calls. Once we are inside an
7794 address, we stay there. If we have a comparison, set to COMPARE,
7795 but once inside, go back to our default of SET. */
7797 next_code
= (code
== MEM
? MEM
7798 : ((code
== COMPARE
|| COMPARISON_P (x
))
7799 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7800 : in_code
== COMPARE
? SET
: in_code
);
7802 /* Process depending on the code of this operation. If NEW is set
7803 nonzero, it will be returned. */
7808 /* Convert shifts by constants into multiplications if inside
7810 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7811 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7812 && INTVAL (XEXP (x
, 1)) >= 0
7813 && SCALAR_INT_MODE_P (mode
))
7815 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7816 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7818 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7819 if (GET_CODE (new_rtx
) == NEG
)
7821 new_rtx
= XEXP (new_rtx
, 0);
7824 multval
= trunc_int_for_mode (multval
, mode
);
7825 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7832 lhs
= make_compound_operation (lhs
, next_code
);
7833 rhs
= make_compound_operation (rhs
, next_code
);
7834 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7835 && SCALAR_INT_MODE_P (mode
))
7837 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7839 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7841 else if (GET_CODE (lhs
) == MULT
7842 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7844 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7845 simplify_gen_unary (NEG
, mode
,
7848 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7852 SUBST (XEXP (x
, 0), lhs
);
7853 SUBST (XEXP (x
, 1), rhs
);
7856 x
= gen_lowpart (mode
, new_rtx
);
7862 lhs
= make_compound_operation (lhs
, next_code
);
7863 rhs
= make_compound_operation (rhs
, next_code
);
7864 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7865 && SCALAR_INT_MODE_P (mode
))
7867 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7869 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7871 else if (GET_CODE (rhs
) == MULT
7872 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7874 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7875 simplify_gen_unary (NEG
, mode
,
7878 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7882 SUBST (XEXP (x
, 0), lhs
);
7883 SUBST (XEXP (x
, 1), rhs
);
7886 return gen_lowpart (mode
, new_rtx
);
7889 /* If the second operand is not a constant, we can't do anything
7891 if (!CONST_INT_P (XEXP (x
, 1)))
7894 /* If the constant is a power of two minus one and the first operand
7895 is a logical right shift, make an extraction. */
7896 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7897 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7899 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7900 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7901 0, in_code
== COMPARE
);
7904 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7905 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7906 && subreg_lowpart_p (XEXP (x
, 0))
7907 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7908 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7910 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7912 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7913 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7914 0, in_code
== COMPARE
);
7916 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7917 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7918 || GET_CODE (XEXP (x
, 0)) == IOR
)
7919 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7920 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7921 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7923 /* Apply the distributive law, and then try to make extractions. */
7924 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7925 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7927 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7929 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7932 /* If we are have (and (rotate X C) M) and C is larger than the number
7933 of bits in M, this is an extraction. */
7935 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7936 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7937 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7938 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7940 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7941 new_rtx
= make_extraction (mode
, new_rtx
,
7942 (GET_MODE_PRECISION (mode
)
7943 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7944 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7947 /* On machines without logical shifts, if the operand of the AND is
7948 a logical shift and our mask turns off all the propagated sign
7949 bits, we can replace the logical shift with an arithmetic shift. */
7950 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7951 && !have_insn_for (LSHIFTRT
, mode
)
7952 && have_insn_for (ASHIFTRT
, mode
)
7953 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7954 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7955 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7956 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7958 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7960 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7961 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7963 gen_rtx_ASHIFTRT (mode
,
7964 make_compound_operation
7965 (XEXP (XEXP (x
, 0), 0), next_code
),
7966 XEXP (XEXP (x
, 0), 1)));
7969 /* If the constant is one less than a power of two, this might be
7970 representable by an extraction even if no shift is present.
7971 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7972 we are in a COMPARE. */
7973 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7974 new_rtx
= make_extraction (mode
,
7975 make_compound_operation (XEXP (x
, 0),
7977 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7979 /* If we are in a comparison and this is an AND with a power of two,
7980 convert this into the appropriate bit extract. */
7981 else if (in_code
== COMPARE
7982 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7983 new_rtx
= make_extraction (mode
,
7984 make_compound_operation (XEXP (x
, 0),
7986 i
, NULL_RTX
, 1, 1, 0, 1);
7991 /* If the sign bit is known to be zero, replace this with an
7992 arithmetic shift. */
7993 if (have_insn_for (ASHIFTRT
, mode
)
7994 && ! have_insn_for (LSHIFTRT
, mode
)
7995 && mode_width
<= HOST_BITS_PER_WIDE_INT
7996 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7998 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7999 make_compound_operation (XEXP (x
, 0),
8005 /* ... fall through ... */
8011 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8012 this is a SIGN_EXTRACT. */
8013 if (CONST_INT_P (rhs
)
8014 && GET_CODE (lhs
) == ASHIFT
8015 && CONST_INT_P (XEXP (lhs
, 1))
8016 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8017 && INTVAL (XEXP (lhs
, 1)) >= 0
8018 && INTVAL (rhs
) < mode_width
)
8020 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8021 new_rtx
= make_extraction (mode
, new_rtx
,
8022 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8023 NULL_RTX
, mode_width
- INTVAL (rhs
),
8024 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8028 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8029 If so, try to merge the shifts into a SIGN_EXTEND. We could
8030 also do this for some cases of SIGN_EXTRACT, but it doesn't
8031 seem worth the effort; the case checked for occurs on Alpha. */
8034 && ! (GET_CODE (lhs
) == SUBREG
8035 && (OBJECT_P (SUBREG_REG (lhs
))))
8036 && CONST_INT_P (rhs
)
8037 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8038 && INTVAL (rhs
) < mode_width
8039 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8040 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8041 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8042 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8047 /* Call ourselves recursively on the inner expression. If we are
8048 narrowing the object and it has a different RTL code from
8049 what it originally did, do this SUBREG as a force_to_mode. */
8051 rtx inner
= SUBREG_REG (x
), simplified
;
8052 enum rtx_code subreg_code
= in_code
;
8054 /* If in_code is COMPARE, it isn't always safe to pass it through
8055 to the recursive make_compound_operation call. */
8056 if (subreg_code
== COMPARE
8057 && (!subreg_lowpart_p (x
)
8058 || GET_CODE (inner
) == SUBREG
8059 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8060 is (const_int 0), rather than
8061 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8062 || (GET_CODE (inner
) == AND
8063 && CONST_INT_P (XEXP (inner
, 1))
8064 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8065 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8066 >= GET_MODE_BITSIZE (mode
))))
8069 tem
= make_compound_operation (inner
, subreg_code
);
8072 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8076 if (GET_CODE (tem
) != GET_CODE (inner
)
8077 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8078 && subreg_lowpart_p (x
))
8081 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
8083 /* If we have something other than a SUBREG, we might have
8084 done an expansion, so rerun ourselves. */
8085 if (GET_CODE (newer
) != SUBREG
)
8086 newer
= make_compound_operation (newer
, in_code
);
8088 /* force_to_mode can expand compounds. If it just re-expanded the
8089 compound, use gen_lowpart to convert to the desired mode. */
8090 if (rtx_equal_p (newer
, x
)
8091 /* Likewise if it re-expanded the compound only partially.
8092 This happens for SUBREG of ZERO_EXTRACT if they extract
8093 the same number of bits. */
8094 || (GET_CODE (newer
) == SUBREG
8095 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8096 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8097 && GET_CODE (inner
) == AND
8098 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8099 return gen_lowpart (GET_MODE (x
), tem
);
8115 x
= gen_lowpart (mode
, new_rtx
);
8116 code
= GET_CODE (x
);
8119 /* Now recursively process each operand of this operation. We need to
8120 handle ZERO_EXTEND specially so that we don't lose track of the
8122 if (GET_CODE (x
) == ZERO_EXTEND
)
8124 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8125 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8126 new_rtx
, GET_MODE (XEXP (x
, 0)));
8129 SUBST (XEXP (x
, 0), new_rtx
);
8133 fmt
= GET_RTX_FORMAT (code
);
8134 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8137 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8138 SUBST (XEXP (x
, i
), new_rtx
);
8140 else if (fmt
[i
] == 'E')
8141 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8143 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8144 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8148 /* If this is a commutative operation, the changes to the operands
8149 may have made it noncanonical. */
8150 if (COMMUTATIVE_ARITH_P (x
)
8151 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
8154 SUBST (XEXP (x
, 0), XEXP (x
, 1));
8155 SUBST (XEXP (x
, 1), tem
);
8161 /* Given M see if it is a value that would select a field of bits
8162 within an item, but not the entire word. Return -1 if not.
8163 Otherwise, return the starting position of the field, where 0 is the
8166 *PLEN is set to the length of the field. */
8169 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8171 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8172 int pos
= m
? ctz_hwi (m
) : -1;
8176 /* Now shift off the low-order zero bits and see if we have a
8177 power of two minus 1. */
8178 len
= exact_log2 ((m
>> pos
) + 1);
8187 /* If X refers to a register that equals REG in value, replace these
8188 references with REG. */
8190 canon_reg_for_combine (rtx x
, rtx reg
)
8197 enum rtx_code code
= GET_CODE (x
);
8198 switch (GET_RTX_CLASS (code
))
8201 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8202 if (op0
!= XEXP (x
, 0))
8203 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8208 case RTX_COMM_ARITH
:
8209 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8210 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8211 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8212 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8216 case RTX_COMM_COMPARE
:
8217 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8218 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8219 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8220 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8221 GET_MODE (op0
), op0
, op1
);
8225 case RTX_BITFIELD_OPS
:
8226 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8227 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8228 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8229 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8230 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8231 GET_MODE (op0
), op0
, op1
, op2
);
8236 if (rtx_equal_p (get_last_value (reg
), x
)
8237 || rtx_equal_p (reg
, get_last_value (x
)))
8246 fmt
= GET_RTX_FORMAT (code
);
8248 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8251 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8252 if (op
!= XEXP (x
, i
))
8262 else if (fmt
[i
] == 'E')
8265 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8267 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8268 if (op
!= XVECEXP (x
, i
, j
))
8275 XVECEXP (x
, i
, j
) = op
;
8286 /* Return X converted to MODE. If the value is already truncated to
8287 MODE we can just return a subreg even though in the general case we
8288 would need an explicit truncation. */
8291 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8293 if (!CONST_INT_P (x
)
8294 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8295 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8296 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8298 /* Bit-cast X into an integer mode. */
8299 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8300 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8301 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8305 return gen_lowpart (mode
, x
);
8308 /* See if X can be simplified knowing that we will only refer to it in
8309 MODE and will only refer to those bits that are nonzero in MASK.
8310 If other bits are being computed or if masking operations are done
8311 that select a superset of the bits in MASK, they can sometimes be
8314 Return a possibly simplified expression, but always convert X to
8315 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8317 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8318 are all off in X. This is used when X will be complemented, by either
8319 NOT, NEG, or XOR. */
8322 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8325 enum rtx_code code
= GET_CODE (x
);
8326 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8327 machine_mode op_mode
;
8328 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8331 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8332 code below will do the wrong thing since the mode of such an
8333 expression is VOIDmode.
8335 Also do nothing if X is a CLOBBER; this can happen if X was
8336 the return value from a call to gen_lowpart. */
8337 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8340 /* We want to perform the operation in its present mode unless we know
8341 that the operation is valid in MODE, in which case we do the operation
8343 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8344 && have_insn_for (code
, mode
))
8345 ? mode
: GET_MODE (x
));
8347 /* It is not valid to do a right-shift in a narrower mode
8348 than the one it came in with. */
8349 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8350 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8351 op_mode
= GET_MODE (x
);
8353 /* Truncate MASK to fit OP_MODE. */
8355 mask
&= GET_MODE_MASK (op_mode
);
8357 /* When we have an arithmetic operation, or a shift whose count we
8358 do not know, we need to assume that all bits up to the highest-order
8359 bit in MASK will be needed. This is how we form such a mask. */
8360 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8361 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8363 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8366 /* Determine what bits of X are guaranteed to be (non)zero. */
8367 nonzero
= nonzero_bits (x
, mode
);
8369 /* If none of the bits in X are needed, return a zero. */
8370 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8373 /* If X is a CONST_INT, return a new one. Do this here since the
8374 test below will fail. */
8375 if (CONST_INT_P (x
))
8377 if (SCALAR_INT_MODE_P (mode
))
8378 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8381 x
= GEN_INT (INTVAL (x
) & mask
);
8382 return gen_lowpart_common (mode
, x
);
8386 /* If X is narrower than MODE and we want all the bits in X's mode, just
8387 get X in the proper mode. */
8388 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8389 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8390 return gen_lowpart (mode
, x
);
8392 /* We can ignore the effect of a SUBREG if it narrows the mode or
8393 if the constant masks to zero all the bits the mode doesn't have. */
8394 if (GET_CODE (x
) == SUBREG
8395 && subreg_lowpart_p (x
)
8396 && ((GET_MODE_SIZE (GET_MODE (x
))
8397 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8399 & GET_MODE_MASK (GET_MODE (x
))
8400 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8401 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8403 /* The arithmetic simplifications here only work for scalar integer modes. */
8404 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8405 return gen_lowpart_or_truncate (mode
, x
);
8410 /* If X is a (clobber (const_int)), return it since we know we are
8411 generating something that won't match. */
8418 x
= expand_compound_operation (x
);
8419 if (GET_CODE (x
) != code
)
8420 return force_to_mode (x
, mode
, mask
, next_select
);
8424 /* Similarly for a truncate. */
8425 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8428 /* If this is an AND with a constant, convert it into an AND
8429 whose constant is the AND of that constant with MASK. If it
8430 remains an AND of MASK, delete it since it is redundant. */
8432 if (CONST_INT_P (XEXP (x
, 1)))
8434 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8435 mask
& INTVAL (XEXP (x
, 1)));
8437 /* If X is still an AND, see if it is an AND with a mask that
8438 is just some low-order bits. If so, and it is MASK, we don't
8441 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8442 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8446 /* If it remains an AND, try making another AND with the bits
8447 in the mode mask that aren't in MASK turned on. If the
8448 constant in the AND is wide enough, this might make a
8449 cheaper constant. */
8451 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8452 && GET_MODE_MASK (GET_MODE (x
)) != mask
8453 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8455 unsigned HOST_WIDE_INT cval
8456 = UINTVAL (XEXP (x
, 1))
8457 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8460 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8461 gen_int_mode (cval
, GET_MODE (x
)));
8462 if (set_src_cost (y
, optimize_this_for_speed_p
)
8463 < set_src_cost (x
, optimize_this_for_speed_p
))
8473 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8474 low-order bits (as in an alignment operation) and FOO is already
8475 aligned to that boundary, mask C1 to that boundary as well.
8476 This may eliminate that PLUS and, later, the AND. */
8479 unsigned int width
= GET_MODE_PRECISION (mode
);
8480 unsigned HOST_WIDE_INT smask
= mask
;
8482 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8483 number, sign extend it. */
8485 if (width
< HOST_BITS_PER_WIDE_INT
8486 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8487 smask
|= HOST_WIDE_INT_M1U
<< width
;
8489 if (CONST_INT_P (XEXP (x
, 1))
8490 && exact_log2 (- smask
) >= 0
8491 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8492 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8493 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8494 (INTVAL (XEXP (x
, 1)) & smask
)),
8495 mode
, smask
, next_select
);
8498 /* ... fall through ... */
8501 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8502 most significant bit in MASK since carries from those bits will
8503 affect the bits we are interested in. */
8508 /* If X is (minus C Y) where C's least set bit is larger than any bit
8509 in the mask, then we may replace with (neg Y). */
8510 if (CONST_INT_P (XEXP (x
, 0))
8511 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8513 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8515 return force_to_mode (x
, mode
, mask
, next_select
);
8518 /* Similarly, if C contains every bit in the fuller_mask, then we may
8519 replace with (not Y). */
8520 if (CONST_INT_P (XEXP (x
, 0))
8521 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8523 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8524 XEXP (x
, 1), GET_MODE (x
));
8525 return force_to_mode (x
, mode
, mask
, next_select
);
8533 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8534 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8535 operation which may be a bitfield extraction. Ensure that the
8536 constant we form is not wider than the mode of X. */
8538 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8539 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8540 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8541 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8542 && CONST_INT_P (XEXP (x
, 1))
8543 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8544 + floor_log2 (INTVAL (XEXP (x
, 1))))
8545 < GET_MODE_PRECISION (GET_MODE (x
)))
8546 && (UINTVAL (XEXP (x
, 1))
8547 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8549 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8550 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8552 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8553 XEXP (XEXP (x
, 0), 0), temp
);
8554 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8555 XEXP (XEXP (x
, 0), 1));
8556 return force_to_mode (x
, mode
, mask
, next_select
);
8560 /* For most binary operations, just propagate into the operation and
8561 change the mode if we have an operation of that mode. */
8563 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8564 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8566 /* If we ended up truncating both operands, truncate the result of the
8567 operation instead. */
8568 if (GET_CODE (op0
) == TRUNCATE
8569 && GET_CODE (op1
) == TRUNCATE
)
8571 op0
= XEXP (op0
, 0);
8572 op1
= XEXP (op1
, 0);
8575 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8576 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8578 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8579 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8583 /* For left shifts, do the same, but just for the first operand.
8584 However, we cannot do anything with shifts where we cannot
8585 guarantee that the counts are smaller than the size of the mode
8586 because such a count will have a different meaning in a
8589 if (! (CONST_INT_P (XEXP (x
, 1))
8590 && INTVAL (XEXP (x
, 1)) >= 0
8591 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8592 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8593 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8594 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8597 /* If the shift count is a constant and we can do arithmetic in
8598 the mode of the shift, refine which bits we need. Otherwise, use the
8599 conservative form of the mask. */
8600 if (CONST_INT_P (XEXP (x
, 1))
8601 && INTVAL (XEXP (x
, 1)) >= 0
8602 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8603 && HWI_COMPUTABLE_MODE_P (op_mode
))
8604 mask
>>= INTVAL (XEXP (x
, 1));
8608 op0
= gen_lowpart_or_truncate (op_mode
,
8609 force_to_mode (XEXP (x
, 0), op_mode
,
8610 mask
, next_select
));
8612 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8613 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8617 /* Here we can only do something if the shift count is a constant,
8618 this shift constant is valid for the host, and we can do arithmetic
8621 if (CONST_INT_P (XEXP (x
, 1))
8622 && INTVAL (XEXP (x
, 1)) >= 0
8623 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8624 && HWI_COMPUTABLE_MODE_P (op_mode
))
8626 rtx inner
= XEXP (x
, 0);
8627 unsigned HOST_WIDE_INT inner_mask
;
8629 /* Select the mask of the bits we need for the shift operand. */
8630 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8632 /* We can only change the mode of the shift if we can do arithmetic
8633 in the mode of the shift and INNER_MASK is no wider than the
8634 width of X's mode. */
8635 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8636 op_mode
= GET_MODE (x
);
8638 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8640 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8641 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8644 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8645 shift and AND produces only copies of the sign bit (C2 is one less
8646 than a power of two), we can do this with just a shift. */
8648 if (GET_CODE (x
) == LSHIFTRT
8649 && CONST_INT_P (XEXP (x
, 1))
8650 /* The shift puts one of the sign bit copies in the least significant
8652 && ((INTVAL (XEXP (x
, 1))
8653 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8654 >= GET_MODE_PRECISION (GET_MODE (x
)))
8655 && exact_log2 (mask
+ 1) >= 0
8656 /* Number of bits left after the shift must be more than the mask
8658 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8659 <= GET_MODE_PRECISION (GET_MODE (x
)))
8660 /* Must be more sign bit copies than the mask needs. */
8661 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8662 >= exact_log2 (mask
+ 1)))
8663 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8664 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8665 - exact_log2 (mask
+ 1)));
8670 /* If we are just looking for the sign bit, we don't need this shift at
8671 all, even if it has a variable count. */
8672 if (val_signbit_p (GET_MODE (x
), mask
))
8673 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8675 /* If this is a shift by a constant, get a mask that contains those bits
8676 that are not copies of the sign bit. We then have two cases: If
8677 MASK only includes those bits, this can be a logical shift, which may
8678 allow simplifications. If MASK is a single-bit field not within
8679 those bits, we are requesting a copy of the sign bit and hence can
8680 shift the sign bit to the appropriate location. */
8682 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8683 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8687 /* If the considered data is wider than HOST_WIDE_INT, we can't
8688 represent a mask for all its bits in a single scalar.
8689 But we only care about the lower bits, so calculate these. */
8691 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8693 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8695 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8696 is the number of bits a full-width mask would have set.
8697 We need only shift if these are fewer than nonzero can
8698 hold. If not, we must keep all bits set in nonzero. */
8700 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8701 < HOST_BITS_PER_WIDE_INT
)
8702 nonzero
>>= INTVAL (XEXP (x
, 1))
8703 + HOST_BITS_PER_WIDE_INT
8704 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8708 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8709 nonzero
>>= INTVAL (XEXP (x
, 1));
8712 if ((mask
& ~nonzero
) == 0)
8714 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8715 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8716 if (GET_CODE (x
) != ASHIFTRT
)
8717 return force_to_mode (x
, mode
, mask
, next_select
);
8720 else if ((i
= exact_log2 (mask
)) >= 0)
8722 x
= simplify_shift_const
8723 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8724 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8726 if (GET_CODE (x
) != ASHIFTRT
)
8727 return force_to_mode (x
, mode
, mask
, next_select
);
8731 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8732 even if the shift count isn't a constant. */
8734 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8735 XEXP (x
, 0), XEXP (x
, 1));
8739 /* If this is a zero- or sign-extension operation that just affects bits
8740 we don't care about, remove it. Be sure the call above returned
8741 something that is still a shift. */
8743 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8744 && CONST_INT_P (XEXP (x
, 1))
8745 && INTVAL (XEXP (x
, 1)) >= 0
8746 && (INTVAL (XEXP (x
, 1))
8747 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8748 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8749 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8750 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8757 /* If the shift count is constant and we can do computations
8758 in the mode of X, compute where the bits we care about are.
8759 Otherwise, we can't do anything. Don't change the mode of
8760 the shift or propagate MODE into the shift, though. */
8761 if (CONST_INT_P (XEXP (x
, 1))
8762 && INTVAL (XEXP (x
, 1)) >= 0)
8764 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8766 gen_int_mode (mask
, GET_MODE (x
)),
8768 if (temp
&& CONST_INT_P (temp
))
8769 x
= simplify_gen_binary (code
, GET_MODE (x
),
8770 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8771 INTVAL (temp
), next_select
),
8777 /* If we just want the low-order bit, the NEG isn't needed since it
8778 won't change the low-order bit. */
8780 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8782 /* We need any bits less significant than the most significant bit in
8783 MASK since carries from those bits will affect the bits we are
8789 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8790 same as the XOR case above. Ensure that the constant we form is not
8791 wider than the mode of X. */
8793 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8794 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8795 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8796 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8797 < GET_MODE_PRECISION (GET_MODE (x
)))
8798 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8800 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8802 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8803 XEXP (XEXP (x
, 0), 0), temp
);
8804 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8805 temp
, XEXP (XEXP (x
, 0), 1));
8807 return force_to_mode (x
, mode
, mask
, next_select
);
8810 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8811 use the full mask inside the NOT. */
8815 op0
= gen_lowpart_or_truncate (op_mode
,
8816 force_to_mode (XEXP (x
, 0), mode
, mask
,
8818 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8819 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8823 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8824 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8825 which is equal to STORE_FLAG_VALUE. */
8826 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8827 && XEXP (x
, 1) == const0_rtx
8828 && GET_MODE (XEXP (x
, 0)) == mode
8829 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8830 && (nonzero_bits (XEXP (x
, 0), mode
)
8831 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8832 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8837 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8838 written in a narrower mode. We play it safe and do not do so. */
8840 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8841 force_to_mode (XEXP (x
, 1), mode
,
8842 mask
, next_select
));
8843 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8844 force_to_mode (XEXP (x
, 2), mode
,
8845 mask
, next_select
));
8846 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8847 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8848 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8856 /* Ensure we return a value of the proper mode. */
8857 return gen_lowpart_or_truncate (mode
, x
);
8860 /* Return nonzero if X is an expression that has one of two values depending on
8861 whether some other value is zero or nonzero. In that case, we return the
8862 value that is being tested, *PTRUE is set to the value if the rtx being
8863 returned has a nonzero value, and *PFALSE is set to the other alternative.
8865 If we return zero, we set *PTRUE and *PFALSE to X. */
8868 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8870 machine_mode mode
= GET_MODE (x
);
8871 enum rtx_code code
= GET_CODE (x
);
8872 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8873 unsigned HOST_WIDE_INT nz
;
8875 /* If we are comparing a value against zero, we are done. */
8876 if ((code
== NE
|| code
== EQ
)
8877 && XEXP (x
, 1) == const0_rtx
)
8879 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8880 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8884 /* If this is a unary operation whose operand has one of two values, apply
8885 our opcode to compute those values. */
8886 else if (UNARY_P (x
)
8887 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8889 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8890 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8891 GET_MODE (XEXP (x
, 0)));
8895 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8896 make can't possibly match and would suppress other optimizations. */
8897 else if (code
== COMPARE
)
8900 /* If this is a binary operation, see if either side has only one of two
8901 values. If either one does or if both do and they are conditional on
8902 the same value, compute the new true and false values. */
8903 else if (BINARY_P (x
))
8905 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8906 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8908 if ((cond0
!= 0 || cond1
!= 0)
8909 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8911 /* If if_then_else_cond returned zero, then true/false are the
8912 same rtl. We must copy one of them to prevent invalid rtl
8915 true0
= copy_rtx (true0
);
8916 else if (cond1
== 0)
8917 true1
= copy_rtx (true1
);
8919 if (COMPARISON_P (x
))
8921 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8923 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8928 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8929 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8932 return cond0
? cond0
: cond1
;
8935 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8936 operands is zero when the other is nonzero, and vice-versa,
8937 and STORE_FLAG_VALUE is 1 or -1. */
8939 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8940 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8942 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8944 rtx op0
= XEXP (XEXP (x
, 0), 1);
8945 rtx op1
= XEXP (XEXP (x
, 1), 1);
8947 cond0
= XEXP (XEXP (x
, 0), 0);
8948 cond1
= XEXP (XEXP (x
, 1), 0);
8950 if (COMPARISON_P (cond0
)
8951 && COMPARISON_P (cond1
)
8952 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8953 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8954 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8955 || ((swap_condition (GET_CODE (cond0
))
8956 == reversed_comparison_code (cond1
, NULL
))
8957 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8958 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8959 && ! side_effects_p (x
))
8961 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8962 *pfalse
= simplify_gen_binary (MULT
, mode
,
8964 ? simplify_gen_unary (NEG
, mode
,
8972 /* Similarly for MULT, AND and UMIN, except that for these the result
8974 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8975 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8976 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8978 cond0
= XEXP (XEXP (x
, 0), 0);
8979 cond1
= XEXP (XEXP (x
, 1), 0);
8981 if (COMPARISON_P (cond0
)
8982 && COMPARISON_P (cond1
)
8983 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8984 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8985 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8986 || ((swap_condition (GET_CODE (cond0
))
8987 == reversed_comparison_code (cond1
, NULL
))
8988 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8989 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8990 && ! side_effects_p (x
))
8992 *ptrue
= *pfalse
= const0_rtx
;
8998 else if (code
== IF_THEN_ELSE
)
9000 /* If we have IF_THEN_ELSE already, extract the condition and
9001 canonicalize it if it is NE or EQ. */
9002 cond0
= XEXP (x
, 0);
9003 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9004 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9005 return XEXP (cond0
, 0);
9006 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9008 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9009 return XEXP (cond0
, 0);
9015 /* If X is a SUBREG, we can narrow both the true and false values
9016 if the inner expression, if there is a condition. */
9017 else if (code
== SUBREG
9018 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9021 true0
= simplify_gen_subreg (mode
, true0
,
9022 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9023 false0
= simplify_gen_subreg (mode
, false0
,
9024 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9025 if (true0
&& false0
)
9033 /* If X is a constant, this isn't special and will cause confusions
9034 if we treat it as such. Likewise if it is equivalent to a constant. */
9035 else if (CONSTANT_P (x
)
9036 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9039 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9040 will be least confusing to the rest of the compiler. */
9041 else if (mode
== BImode
)
9043 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9047 /* If X is known to be either 0 or -1, those are the true and
9048 false values when testing X. */
9049 else if (x
== constm1_rtx
|| x
== const0_rtx
9050 || (mode
!= VOIDmode
9051 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9053 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9057 /* Likewise for 0 or a single bit. */
9058 else if (HWI_COMPUTABLE_MODE_P (mode
)
9059 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
9061 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9065 /* Otherwise fail; show no condition with true and false values the same. */
9066 *ptrue
= *pfalse
= x
;
9070 /* Return the value of expression X given the fact that condition COND
9071 is known to be true when applied to REG as its first operand and VAL
9072 as its second. X is known to not be shared and so can be modified in
9075 We only handle the simplest cases, and specifically those cases that
9076 arise with IF_THEN_ELSE expressions. */
9079 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9081 enum rtx_code code
= GET_CODE (x
);
9085 if (side_effects_p (x
))
9088 /* If either operand of the condition is a floating point value,
9089 then we have to avoid collapsing an EQ comparison. */
9091 && rtx_equal_p (x
, reg
)
9092 && ! FLOAT_MODE_P (GET_MODE (x
))
9093 && ! FLOAT_MODE_P (GET_MODE (val
)))
9096 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9099 /* If X is (abs REG) and we know something about REG's relationship
9100 with zero, we may be able to simplify this. */
9102 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9105 case GE
: case GT
: case EQ
:
9108 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9110 GET_MODE (XEXP (x
, 0)));
9115 /* The only other cases we handle are MIN, MAX, and comparisons if the
9116 operands are the same as REG and VAL. */
9118 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9120 if (rtx_equal_p (XEXP (x
, 0), val
))
9122 std::swap (val
, reg
);
9123 cond
= swap_condition (cond
);
9126 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9128 if (COMPARISON_P (x
))
9130 if (comparison_dominates_p (cond
, code
))
9131 return const_true_rtx
;
9133 code
= reversed_comparison_code (x
, NULL
);
9135 && comparison_dominates_p (cond
, code
))
9140 else if (code
== SMAX
|| code
== SMIN
9141 || code
== UMIN
|| code
== UMAX
)
9143 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9145 /* Do not reverse the condition when it is NE or EQ.
9146 This is because we cannot conclude anything about
9147 the value of 'SMAX (x, y)' when x is not equal to y,
9148 but we can when x equals y. */
9149 if ((code
== SMAX
|| code
== UMAX
)
9150 && ! (cond
== EQ
|| cond
== NE
))
9151 cond
= reverse_condition (cond
);
9156 return unsignedp
? x
: XEXP (x
, 1);
9158 return unsignedp
? x
: XEXP (x
, 0);
9160 return unsignedp
? XEXP (x
, 1) : x
;
9162 return unsignedp
? XEXP (x
, 0) : x
;
9169 else if (code
== SUBREG
)
9171 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9172 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9174 if (SUBREG_REG (x
) != r
)
9176 /* We must simplify subreg here, before we lose track of the
9177 original inner_mode. */
9178 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9179 inner_mode
, SUBREG_BYTE (x
));
9183 SUBST (SUBREG_REG (x
), r
);
9188 /* We don't have to handle SIGN_EXTEND here, because even in the
9189 case of replacing something with a modeless CONST_INT, a
9190 CONST_INT is already (supposed to be) a valid sign extension for
9191 its narrower mode, which implies it's already properly
9192 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9193 story is different. */
9194 else if (code
== ZERO_EXTEND
)
9196 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9197 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9199 if (XEXP (x
, 0) != r
)
9201 /* We must simplify the zero_extend here, before we lose
9202 track of the original inner_mode. */
9203 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9208 SUBST (XEXP (x
, 0), r
);
9214 fmt
= GET_RTX_FORMAT (code
);
9215 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9218 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9219 else if (fmt
[i
] == 'E')
9220 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9221 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9228 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9229 assignment as a field assignment. */
9232 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9234 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9236 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9238 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9240 /* For big endian, adjust the memory offset. */
9241 if (BYTES_BIG_ENDIAN
)
9242 x
= adjust_address_nv (x
, GET_MODE (y
),
9243 -subreg_lowpart_offset (GET_MODE (x
),
9246 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9249 if (x
== y
|| rtx_equal_p (x
, y
))
9252 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9255 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9256 Note that all SUBREGs of MEM are paradoxical; otherwise they
9257 would have been rewritten. */
9258 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9259 && MEM_P (SUBREG_REG (y
))
9260 && rtx_equal_p (SUBREG_REG (y
),
9261 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9264 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9265 && MEM_P (SUBREG_REG (x
))
9266 && rtx_equal_p (SUBREG_REG (x
),
9267 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9270 /* We used to see if get_last_value of X and Y were the same but that's
9271 not correct. In one direction, we'll cause the assignment to have
9272 the wrong destination and in the case, we'll import a register into this
9273 insn that might have already have been dead. So fail if none of the
9274 above cases are true. */
9278 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9279 Return that assignment if so.
9281 We only handle the most common cases. */
9284 make_field_assignment (rtx x
)
9286 rtx dest
= SET_DEST (x
);
9287 rtx src
= SET_SRC (x
);
9292 unsigned HOST_WIDE_INT len
;
9296 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9297 a clear of a one-bit field. We will have changed it to
9298 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9301 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9302 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9303 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9304 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9306 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9309 return gen_rtx_SET (assign
, const0_rtx
);
9313 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9314 && subreg_lowpart_p (XEXP (src
, 0))
9315 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9316 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9317 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9318 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9319 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9320 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9322 assign
= make_extraction (VOIDmode
, dest
, 0,
9323 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9326 return gen_rtx_SET (assign
, const0_rtx
);
9330 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9332 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9333 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9334 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9336 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9339 return gen_rtx_SET (assign
, const1_rtx
);
9343 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9344 SRC is an AND with all bits of that field set, then we can discard
9346 if (GET_CODE (dest
) == ZERO_EXTRACT
9347 && CONST_INT_P (XEXP (dest
, 1))
9348 && GET_CODE (src
) == AND
9349 && CONST_INT_P (XEXP (src
, 1)))
9351 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9352 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9353 unsigned HOST_WIDE_INT ze_mask
;
9355 if (width
>= HOST_BITS_PER_WIDE_INT
)
9358 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9360 /* Complete overlap. We can remove the source AND. */
9361 if ((and_mask
& ze_mask
) == ze_mask
)
9362 return gen_rtx_SET (dest
, XEXP (src
, 0));
9364 /* Partial overlap. We can reduce the source AND. */
9365 if ((and_mask
& ze_mask
) != and_mask
)
9367 mode
= GET_MODE (src
);
9368 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9369 gen_int_mode (and_mask
& ze_mask
, mode
));
9370 return gen_rtx_SET (dest
, src
);
9374 /* The other case we handle is assignments into a constant-position
9375 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9376 a mask that has all one bits except for a group of zero bits and
9377 OTHER is known to have zeros where C1 has ones, this is such an
9378 assignment. Compute the position and length from C1. Shift OTHER
9379 to the appropriate position, force it to the required mode, and
9380 make the extraction. Check for the AND in both operands. */
9382 /* One or more SUBREGs might obscure the constant-position field
9383 assignment. The first one we are likely to encounter is an outer
9384 narrowing SUBREG, which we can just strip for the purposes of
9385 identifying the constant-field assignment. */
9386 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9387 src
= SUBREG_REG (src
);
9389 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9392 rhs
= expand_compound_operation (XEXP (src
, 0));
9393 lhs
= expand_compound_operation (XEXP (src
, 1));
9395 if (GET_CODE (rhs
) == AND
9396 && CONST_INT_P (XEXP (rhs
, 1))
9397 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9398 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9399 /* The second SUBREG that might get in the way is a paradoxical
9400 SUBREG around the first operand of the AND. We want to
9401 pretend the operand is as wide as the destination here. We
9402 do this by adjusting the MEM to wider mode for the sole
9403 purpose of the call to rtx_equal_for_field_assignment_p. Also
9404 note this trick only works for MEMs. */
9405 else if (GET_CODE (rhs
) == AND
9406 && paradoxical_subreg_p (XEXP (rhs
, 0))
9407 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9408 && CONST_INT_P (XEXP (rhs
, 1))
9409 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9411 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9412 else if (GET_CODE (lhs
) == AND
9413 && CONST_INT_P (XEXP (lhs
, 1))
9414 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9415 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9416 /* The second SUBREG that might get in the way is a paradoxical
9417 SUBREG around the first operand of the AND. We want to
9418 pretend the operand is as wide as the destination here. We
9419 do this by adjusting the MEM to wider mode for the sole
9420 purpose of the call to rtx_equal_for_field_assignment_p. Also
9421 note this trick only works for MEMs. */
9422 else if (GET_CODE (lhs
) == AND
9423 && paradoxical_subreg_p (XEXP (lhs
, 0))
9424 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9425 && CONST_INT_P (XEXP (lhs
, 1))
9426 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9428 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9432 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9433 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9434 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9435 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9438 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9442 /* The mode to use for the source is the mode of the assignment, or of
9443 what is inside a possible STRICT_LOW_PART. */
9444 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9445 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9447 /* Shift OTHER right POS places and make it the source, restricting it
9448 to the proper length and mode. */
9450 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9454 src
= force_to_mode (src
, mode
,
9455 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9456 ? ~(unsigned HOST_WIDE_INT
) 0
9457 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9460 /* If SRC is masked by an AND that does not make a difference in
9461 the value being stored, strip it. */
9462 if (GET_CODE (assign
) == ZERO_EXTRACT
9463 && CONST_INT_P (XEXP (assign
, 1))
9464 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9465 && GET_CODE (src
) == AND
9466 && CONST_INT_P (XEXP (src
, 1))
9467 && UINTVAL (XEXP (src
, 1))
9468 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9469 src
= XEXP (src
, 0);
9471 return gen_rtx_SET (assign
, src
);
9474 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9478 apply_distributive_law (rtx x
)
9480 enum rtx_code code
= GET_CODE (x
);
9481 enum rtx_code inner_code
;
9482 rtx lhs
, rhs
, other
;
9485 /* Distributivity is not true for floating point as it can change the
9486 value. So we don't do it unless -funsafe-math-optimizations. */
9487 if (FLOAT_MODE_P (GET_MODE (x
))
9488 && ! flag_unsafe_math_optimizations
)
9491 /* The outer operation can only be one of the following: */
9492 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9493 && code
!= PLUS
&& code
!= MINUS
)
9499 /* If either operand is a primitive we can't do anything, so get out
9501 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9504 lhs
= expand_compound_operation (lhs
);
9505 rhs
= expand_compound_operation (rhs
);
9506 inner_code
= GET_CODE (lhs
);
9507 if (inner_code
!= GET_CODE (rhs
))
9510 /* See if the inner and outer operations distribute. */
9517 /* These all distribute except over PLUS. */
9518 if (code
== PLUS
|| code
== MINUS
)
9523 if (code
!= PLUS
&& code
!= MINUS
)
9528 /* This is also a multiply, so it distributes over everything. */
9531 /* This used to handle SUBREG, but this turned out to be counter-
9532 productive, since (subreg (op ...)) usually is not handled by
9533 insn patterns, and this "optimization" therefore transformed
9534 recognizable patterns into unrecognizable ones. Therefore the
9535 SUBREG case was removed from here.
9537 It is possible that distributing SUBREG over arithmetic operations
9538 leads to an intermediate result than can then be optimized further,
9539 e.g. by moving the outer SUBREG to the other side of a SET as done
9540 in simplify_set. This seems to have been the original intent of
9541 handling SUBREGs here.
9543 However, with current GCC this does not appear to actually happen,
9544 at least on major platforms. If some case is found where removing
9545 the SUBREG case here prevents follow-on optimizations, distributing
9546 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9552 /* Set LHS and RHS to the inner operands (A and B in the example
9553 above) and set OTHER to the common operand (C in the example).
9554 There is only one way to do this unless the inner operation is
9556 if (COMMUTATIVE_ARITH_P (lhs
)
9557 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9558 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9559 else if (COMMUTATIVE_ARITH_P (lhs
)
9560 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9561 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9562 else if (COMMUTATIVE_ARITH_P (lhs
)
9563 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9564 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9565 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9566 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9570 /* Form the new inner operation, seeing if it simplifies first. */
9571 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9573 /* There is one exception to the general way of distributing:
9574 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9575 if (code
== XOR
&& inner_code
== IOR
)
9578 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9581 /* We may be able to continuing distributing the result, so call
9582 ourselves recursively on the inner operation before forming the
9583 outer operation, which we return. */
9584 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9585 apply_distributive_law (tem
), other
);
9588 /* See if X is of the form (* (+ A B) C), and if so convert to
9589 (+ (* A C) (* B C)) and try to simplify.
9591 Most of the time, this results in no change. However, if some of
9592 the operands are the same or inverses of each other, simplifications
9595 For example, (and (ior A B) (not B)) can occur as the result of
9596 expanding a bit field assignment. When we apply the distributive
9597 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9598 which then simplifies to (and (A (not B))).
9600 Note that no checks happen on the validity of applying the inverse
9601 distributive law. This is pointless since we can do it in the
9602 few places where this routine is called.
9604 N is the index of the term that is decomposed (the arithmetic operation,
9605 i.e. (+ A B) in the first example above). !N is the index of the term that
9606 is distributed, i.e. of C in the first example above. */
9608 distribute_and_simplify_rtx (rtx x
, int n
)
9611 enum rtx_code outer_code
, inner_code
;
9612 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9614 /* Distributivity is not true for floating point as it can change the
9615 value. So we don't do it unless -funsafe-math-optimizations. */
9616 if (FLOAT_MODE_P (GET_MODE (x
))
9617 && ! flag_unsafe_math_optimizations
)
9620 decomposed
= XEXP (x
, n
);
9621 if (!ARITHMETIC_P (decomposed
))
9624 mode
= GET_MODE (x
);
9625 outer_code
= GET_CODE (x
);
9626 distributed
= XEXP (x
, !n
);
9628 inner_code
= GET_CODE (decomposed
);
9629 inner_op0
= XEXP (decomposed
, 0);
9630 inner_op1
= XEXP (decomposed
, 1);
9632 /* Special case (and (xor B C) (not A)), which is equivalent to
9633 (xor (ior A B) (ior A C)) */
9634 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9636 distributed
= XEXP (distributed
, 0);
9642 /* Distribute the second term. */
9643 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9644 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9648 /* Distribute the first term. */
9649 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9650 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9653 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9655 if (GET_CODE (tmp
) != outer_code
9656 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9657 < set_src_cost (x
, optimize_this_for_speed_p
)))
9663 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9664 in MODE. Return an equivalent form, if different from (and VAROP
9665 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9668 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9669 unsigned HOST_WIDE_INT constop
)
9671 unsigned HOST_WIDE_INT nonzero
;
9672 unsigned HOST_WIDE_INT orig_constop
;
9677 orig_constop
= constop
;
9678 if (GET_CODE (varop
) == CLOBBER
)
9681 /* Simplify VAROP knowing that we will be only looking at some of the
9684 Note by passing in CONSTOP, we guarantee that the bits not set in
9685 CONSTOP are not significant and will never be examined. We must
9686 ensure that is the case by explicitly masking out those bits
9687 before returning. */
9688 varop
= force_to_mode (varop
, mode
, constop
, 0);
9690 /* If VAROP is a CLOBBER, we will fail so return it. */
9691 if (GET_CODE (varop
) == CLOBBER
)
9694 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9695 to VAROP and return the new constant. */
9696 if (CONST_INT_P (varop
))
9697 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9699 /* See what bits may be nonzero in VAROP. Unlike the general case of
9700 a call to nonzero_bits, here we don't care about bits outside
9703 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9705 /* Turn off all bits in the constant that are known to already be zero.
9706 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9707 which is tested below. */
9711 /* If we don't have any bits left, return zero. */
9715 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9716 a power of two, we can replace this with an ASHIFT. */
9717 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9718 && (i
= exact_log2 (constop
)) >= 0)
9719 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9721 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9722 or XOR, then try to apply the distributive law. This may eliminate
9723 operations if either branch can be simplified because of the AND.
9724 It may also make some cases more complex, but those cases probably
9725 won't match a pattern either with or without this. */
9727 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9731 apply_distributive_law
9732 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9733 simplify_and_const_int (NULL_RTX
,
9737 simplify_and_const_int (NULL_RTX
,
9742 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9743 the AND and see if one of the operands simplifies to zero. If so, we
9744 may eliminate it. */
9746 if (GET_CODE (varop
) == PLUS
9747 && exact_log2 (constop
+ 1) >= 0)
9751 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9752 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9753 if (o0
== const0_rtx
)
9755 if (o1
== const0_rtx
)
9759 /* Make a SUBREG if necessary. If we can't make it, fail. */
9760 varop
= gen_lowpart (mode
, varop
);
9761 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9764 /* If we are only masking insignificant bits, return VAROP. */
9765 if (constop
== nonzero
)
9768 if (varop
== orig_varop
&& constop
== orig_constop
)
9771 /* Otherwise, return an AND. */
9772 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9776 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9779 Return an equivalent form, if different from X. Otherwise, return X. If
9780 X is zero, we are to always construct the equivalent form. */
9783 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9784 unsigned HOST_WIDE_INT constop
)
9786 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9791 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9792 gen_int_mode (constop
, mode
));
9793 if (GET_MODE (x
) != mode
)
9794 x
= gen_lowpart (mode
, x
);
9798 /* Given a REG, X, compute which bits in X can be nonzero.
9799 We don't care about bits outside of those defined in MODE.
9801 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9802 a shift, AND, or zero_extract, we can do better. */
9805 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9806 const_rtx known_x ATTRIBUTE_UNUSED
,
9807 machine_mode known_mode ATTRIBUTE_UNUSED
,
9808 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9809 unsigned HOST_WIDE_INT
*nonzero
)
9814 /* If X is a register whose nonzero bits value is current, use it.
9815 Otherwise, if X is a register whose value we can find, use that
9816 value. Otherwise, use the previously-computed global nonzero bits
9817 for this register. */
9819 rsp
= ®_stat
[REGNO (x
)];
9820 if (rsp
->last_set_value
!= 0
9821 && (rsp
->last_set_mode
== mode
9822 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9823 && GET_MODE_CLASS (mode
) == MODE_INT
))
9824 && ((rsp
->last_set_label
>= label_tick_ebb_start
9825 && rsp
->last_set_label
< label_tick
)
9826 || (rsp
->last_set_label
== label_tick
9827 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9828 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9829 && REGNO (x
) < reg_n_sets_max
9830 && REG_N_SETS (REGNO (x
)) == 1
9832 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9835 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9837 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9838 /* We don't know anything about the upper bits. */
9839 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9845 tem
= get_last_value (x
);
9849 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9850 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
9851 GET_MODE_PRECISION (mode
));
9855 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9857 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9859 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9860 /* We don't know anything about the upper bits. */
9861 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9869 /* Return the number of bits at the high-order end of X that are known to
9870 be equal to the sign bit. X will be used in mode MODE; if MODE is
9871 VOIDmode, X will be used in its own mode. The returned value will always
9872 be between 1 and the number of bits in MODE. */
9875 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9876 const_rtx known_x ATTRIBUTE_UNUSED
,
9877 machine_mode known_mode
9879 unsigned int known_ret ATTRIBUTE_UNUSED
,
9880 unsigned int *result
)
9885 rsp
= ®_stat
[REGNO (x
)];
9886 if (rsp
->last_set_value
!= 0
9887 && rsp
->last_set_mode
== mode
9888 && ((rsp
->last_set_label
>= label_tick_ebb_start
9889 && rsp
->last_set_label
< label_tick
)
9890 || (rsp
->last_set_label
== label_tick
9891 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9892 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9893 && REGNO (x
) < reg_n_sets_max
9894 && REG_N_SETS (REGNO (x
)) == 1
9896 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9899 *result
= rsp
->last_set_sign_bit_copies
;
9903 tem
= get_last_value (x
);
9907 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9908 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9909 *result
= rsp
->sign_bit_copies
;
9914 /* Return the number of "extended" bits there are in X, when interpreted
9915 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9916 unsigned quantities, this is the number of high-order zero bits.
9917 For signed quantities, this is the number of copies of the sign bit
9918 minus 1. In both case, this function returns the number of "spare"
9919 bits. For example, if two quantities for which this function returns
9920 at least 1 are added, the addition is known not to overflow.
9922 This function will always return 0 unless called during combine, which
9923 implies that it must be called from a define_split. */
9926 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9928 if (nonzero_sign_valid
== 0)
9932 ? (HWI_COMPUTABLE_MODE_P (mode
)
9933 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9934 - floor_log2 (nonzero_bits (x
, mode
)))
9936 : num_sign_bit_copies (x
, mode
) - 1);
9939 /* This function is called from `simplify_shift_const' to merge two
9940 outer operations. Specifically, we have already found that we need
9941 to perform operation *POP0 with constant *PCONST0 at the outermost
9942 position. We would now like to also perform OP1 with constant CONST1
9943 (with *POP0 being done last).
9945 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9946 the resulting operation. *PCOMP_P is set to 1 if we would need to
9947 complement the innermost operand, otherwise it is unchanged.
9949 MODE is the mode in which the operation will be done. No bits outside
9950 the width of this mode matter. It is assumed that the width of this mode
9951 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9953 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9954 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9955 result is simply *PCONST0.
9957 If the resulting operation cannot be expressed as one operation, we
9958 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9961 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
9963 enum rtx_code op0
= *pop0
;
9964 HOST_WIDE_INT const0
= *pconst0
;
9966 const0
&= GET_MODE_MASK (mode
);
9967 const1
&= GET_MODE_MASK (mode
);
9969 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9973 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9976 if (op1
== UNKNOWN
|| op0
== SET
)
9979 else if (op0
== UNKNOWN
)
9980 op0
= op1
, const0
= const1
;
9982 else if (op0
== op1
)
10006 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10007 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10010 /* If the two constants aren't the same, we can't do anything. The
10011 remaining six cases can all be done. */
10012 else if (const0
!= const1
)
10020 /* (a & b) | b == b */
10022 else /* op1 == XOR */
10023 /* (a ^ b) | b == a | b */
10029 /* (a & b) ^ b == (~a) & b */
10030 op0
= AND
, *pcomp_p
= 1;
10031 else /* op1 == IOR */
10032 /* (a | b) ^ b == a & ~b */
10033 op0
= AND
, const0
= ~const0
;
10038 /* (a | b) & b == b */
10040 else /* op1 == XOR */
10041 /* (a ^ b) & b) == (~a) & b */
10048 /* Check for NO-OP cases. */
10049 const0
&= GET_MODE_MASK (mode
);
10051 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10053 else if (const0
== 0 && op0
== AND
)
10055 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10061 /* ??? Slightly redundant with the above mask, but not entirely.
10062 Moving this above means we'd have to sign-extend the mode mask
10063 for the final test. */
10064 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10065 *pconst0
= trunc_int_for_mode (const0
, mode
);
10070 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10071 the shift in. The original shift operation CODE is performed on OP in
10072 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10073 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10074 result of the shift is subject to operation OUTER_CODE with operand
10077 static machine_mode
10078 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10079 machine_mode orig_mode
, machine_mode mode
,
10080 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10082 if (orig_mode
== mode
)
10084 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10086 /* In general we can't perform in wider mode for right shift and rotate. */
10090 /* We can still widen if the bits brought in from the left are identical
10091 to the sign bit of ORIG_MODE. */
10092 if (num_sign_bit_copies (op
, mode
)
10093 > (unsigned) (GET_MODE_PRECISION (mode
)
10094 - GET_MODE_PRECISION (orig_mode
)))
10099 /* Similarly here but with zero bits. */
10100 if (HWI_COMPUTABLE_MODE_P (mode
)
10101 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10104 /* We can also widen if the bits brought in will be masked off. This
10105 operation is performed in ORIG_MODE. */
10106 if (outer_code
== AND
)
10108 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10111 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10120 gcc_unreachable ();
10127 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10128 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10129 if we cannot simplify it. Otherwise, return a simplified value.
10131 The shift is normally computed in the widest mode we find in VAROP, as
10132 long as it isn't a different number of words than RESULT_MODE. Exceptions
10133 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10136 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10137 rtx varop
, int orig_count
)
10139 enum rtx_code orig_code
= code
;
10140 rtx orig_varop
= varop
;
10142 machine_mode mode
= result_mode
;
10143 machine_mode shift_mode
, tmode
;
10144 unsigned int mode_words
10145 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10146 /* We form (outer_op (code varop count) (outer_const)). */
10147 enum rtx_code outer_op
= UNKNOWN
;
10148 HOST_WIDE_INT outer_const
= 0;
10149 int complement_p
= 0;
10152 /* Make sure and truncate the "natural" shift on the way in. We don't
10153 want to do this inside the loop as it makes it more difficult to
10155 if (SHIFT_COUNT_TRUNCATED
)
10156 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
10158 /* If we were given an invalid count, don't do anything except exactly
10159 what was requested. */
10161 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
10164 count
= orig_count
;
10166 /* Unless one of the branches of the `if' in this loop does a `continue',
10167 we will `break' the loop after the `if'. */
10171 /* If we have an operand of (clobber (const_int 0)), fail. */
10172 if (GET_CODE (varop
) == CLOBBER
)
10175 /* Convert ROTATERT to ROTATE. */
10176 if (code
== ROTATERT
)
10178 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
10180 if (VECTOR_MODE_P (result_mode
))
10181 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
10183 count
= bitsize
- count
;
10186 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10187 mode
, outer_op
, outer_const
);
10189 /* Handle cases where the count is greater than the size of the mode
10190 minus 1. For ASHIFT, use the size minus one as the count (this can
10191 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10192 take the count modulo the size. For other shifts, the result is
10195 Since these shifts are being produced by the compiler by combining
10196 multiple operations, each of which are defined, we know what the
10197 result is supposed to be. */
10199 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
10201 if (code
== ASHIFTRT
)
10202 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10203 else if (code
== ROTATE
|| code
== ROTATERT
)
10204 count
%= GET_MODE_PRECISION (shift_mode
);
10207 /* We can't simply return zero because there may be an
10209 varop
= const0_rtx
;
10215 /* If we discovered we had to complement VAROP, leave. Making a NOT
10216 here would cause an infinite loop. */
10220 /* An arithmetic right shift of a quantity known to be -1 or 0
10222 if (code
== ASHIFTRT
10223 && (num_sign_bit_copies (varop
, shift_mode
)
10224 == GET_MODE_PRECISION (shift_mode
)))
10230 /* If we are doing an arithmetic right shift and discarding all but
10231 the sign bit copies, this is equivalent to doing a shift by the
10232 bitsize minus one. Convert it into that shift because it will often
10233 allow other simplifications. */
10235 if (code
== ASHIFTRT
10236 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
10237 >= GET_MODE_PRECISION (shift_mode
)))
10238 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10240 /* We simplify the tests below and elsewhere by converting
10241 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10242 `make_compound_operation' will convert it to an ASHIFTRT for
10243 those machines (such as VAX) that don't have an LSHIFTRT. */
10244 if (code
== ASHIFTRT
10245 && val_signbit_known_clear_p (shift_mode
,
10246 nonzero_bits (varop
, shift_mode
)))
10249 if (((code
== LSHIFTRT
10250 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10251 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10253 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10254 && !((nonzero_bits (varop
, shift_mode
) << count
)
10255 & GET_MODE_MASK (shift_mode
))))
10256 && !side_effects_p (varop
))
10257 varop
= const0_rtx
;
10259 switch (GET_CODE (varop
))
10265 new_rtx
= expand_compound_operation (varop
);
10266 if (new_rtx
!= varop
)
10274 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10275 minus the width of a smaller mode, we can do this with a
10276 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10277 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10278 && ! mode_dependent_address_p (XEXP (varop
, 0),
10279 MEM_ADDR_SPACE (varop
))
10280 && ! MEM_VOLATILE_P (varop
)
10281 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10282 MODE_INT
, 1)) != BLKmode
)
10284 new_rtx
= adjust_address_nv (varop
, tmode
,
10285 BYTES_BIG_ENDIAN
? 0
10286 : count
/ BITS_PER_UNIT
);
10288 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10289 : ZERO_EXTEND
, mode
, new_rtx
);
10296 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10297 the same number of words as what we've seen so far. Then store
10298 the widest mode in MODE. */
10299 if (subreg_lowpart_p (varop
)
10300 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10301 > GET_MODE_SIZE (GET_MODE (varop
)))
10302 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10303 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10305 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10306 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10308 varop
= SUBREG_REG (varop
);
10309 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10310 mode
= GET_MODE (varop
);
10316 /* Some machines use MULT instead of ASHIFT because MULT
10317 is cheaper. But it is still better on those machines to
10318 merge two shifts into one. */
10319 if (CONST_INT_P (XEXP (varop
, 1))
10320 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10323 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10325 GEN_INT (exact_log2 (
10326 UINTVAL (XEXP (varop
, 1)))));
10332 /* Similar, for when divides are cheaper. */
10333 if (CONST_INT_P (XEXP (varop
, 1))
10334 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10337 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10339 GEN_INT (exact_log2 (
10340 UINTVAL (XEXP (varop
, 1)))));
10346 /* If we are extracting just the sign bit of an arithmetic
10347 right shift, that shift is not needed. However, the sign
10348 bit of a wider mode may be different from what would be
10349 interpreted as the sign bit in a narrower mode, so, if
10350 the result is narrower, don't discard the shift. */
10351 if (code
== LSHIFTRT
10352 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10353 && (GET_MODE_BITSIZE (result_mode
)
10354 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10356 varop
= XEXP (varop
, 0);
10360 /* ... fall through ... */
10365 /* Here we have two nested shifts. The result is usually the
10366 AND of a new shift with a mask. We compute the result below. */
10367 if (CONST_INT_P (XEXP (varop
, 1))
10368 && INTVAL (XEXP (varop
, 1)) >= 0
10369 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10370 && HWI_COMPUTABLE_MODE_P (result_mode
)
10371 && HWI_COMPUTABLE_MODE_P (mode
)
10372 && !VECTOR_MODE_P (result_mode
))
10374 enum rtx_code first_code
= GET_CODE (varop
);
10375 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10376 unsigned HOST_WIDE_INT mask
;
10379 /* We have one common special case. We can't do any merging if
10380 the inner code is an ASHIFTRT of a smaller mode. However, if
10381 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10382 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10383 we can convert it to
10384 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10385 This simplifies certain SIGN_EXTEND operations. */
10386 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10387 && count
== (GET_MODE_PRECISION (result_mode
)
10388 - GET_MODE_PRECISION (GET_MODE (varop
))))
10390 /* C3 has the low-order C1 bits zero. */
10392 mask
= GET_MODE_MASK (mode
)
10393 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10395 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10396 XEXP (varop
, 0), mask
);
10397 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10399 count
= first_count
;
10404 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10405 than C1 high-order bits equal to the sign bit, we can convert
10406 this to either an ASHIFT or an ASHIFTRT depending on the
10409 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10411 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10412 && GET_MODE (varop
) == shift_mode
10413 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10416 varop
= XEXP (varop
, 0);
10417 count
-= first_count
;
10427 /* There are some cases we can't do. If CODE is ASHIFTRT,
10428 we can only do this if FIRST_CODE is also ASHIFTRT.
10430 We can't do the case when CODE is ROTATE and FIRST_CODE is
10433 If the mode of this shift is not the mode of the outer shift,
10434 we can't do this if either shift is a right shift or ROTATE.
10436 Finally, we can't do any of these if the mode is too wide
10437 unless the codes are the same.
10439 Handle the case where the shift codes are the same
10442 if (code
== first_code
)
10444 if (GET_MODE (varop
) != result_mode
10445 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10446 || code
== ROTATE
))
10449 count
+= first_count
;
10450 varop
= XEXP (varop
, 0);
10454 if (code
== ASHIFTRT
10455 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10456 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10457 || (GET_MODE (varop
) != result_mode
10458 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10459 || first_code
== ROTATE
10460 || code
== ROTATE
)))
10463 /* To compute the mask to apply after the shift, shift the
10464 nonzero bits of the inner shift the same way the
10465 outer shift will. */
10467 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10471 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10474 /* Give up if we can't compute an outer operation to use. */
10476 || !CONST_INT_P (mask_rtx
)
10477 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10479 result_mode
, &complement_p
))
10482 /* If the shifts are in the same direction, we add the
10483 counts. Otherwise, we subtract them. */
10484 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10485 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10486 count
+= first_count
;
10488 count
-= first_count
;
10490 /* If COUNT is positive, the new shift is usually CODE,
10491 except for the two exceptions below, in which case it is
10492 FIRST_CODE. If the count is negative, FIRST_CODE should
10495 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10496 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10498 else if (count
< 0)
10499 code
= first_code
, count
= -count
;
10501 varop
= XEXP (varop
, 0);
10505 /* If we have (A << B << C) for any shift, we can convert this to
10506 (A << C << B). This wins if A is a constant. Only try this if
10507 B is not a constant. */
10509 else if (GET_CODE (varop
) == code
10510 && CONST_INT_P (XEXP (varop
, 0))
10511 && !CONST_INT_P (XEXP (varop
, 1)))
10513 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10516 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10523 if (VECTOR_MODE_P (mode
))
10526 /* Make this fit the case below. */
10527 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10533 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10534 with C the size of VAROP - 1 and the shift is logical if
10535 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10536 we have an (le X 0) operation. If we have an arithmetic shift
10537 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10538 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10540 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10541 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10542 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10543 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10544 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10545 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10548 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10551 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10552 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10557 /* If we have (shift (logical)), move the logical to the outside
10558 to allow it to possibly combine with another logical and the
10559 shift to combine with another shift. This also canonicalizes to
10560 what a ZERO_EXTRACT looks like. Also, some machines have
10561 (and (shift)) insns. */
10563 if (CONST_INT_P (XEXP (varop
, 1))
10564 /* We can't do this if we have (ashiftrt (xor)) and the
10565 constant has its sign bit set in shift_mode with shift_mode
10566 wider than result_mode. */
10567 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10568 && result_mode
!= shift_mode
10569 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10571 && (new_rtx
= simplify_const_binary_operation
10572 (code
, result_mode
,
10573 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10574 GEN_INT (count
))) != 0
10575 && CONST_INT_P (new_rtx
)
10576 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10577 INTVAL (new_rtx
), result_mode
, &complement_p
))
10579 varop
= XEXP (varop
, 0);
10583 /* If we can't do that, try to simplify the shift in each arm of the
10584 logical expression, make a new logical expression, and apply
10585 the inverse distributive law. This also can't be done for
10586 (ashiftrt (xor)) where we've widened the shift and the constant
10587 changes the sign bit. */
10588 if (CONST_INT_P (XEXP (varop
, 1))
10589 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10590 && result_mode
!= shift_mode
10591 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10594 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10595 XEXP (varop
, 0), count
);
10596 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10597 XEXP (varop
, 1), count
);
10599 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10601 varop
= apply_distributive_law (varop
);
10609 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10610 says that the sign bit can be tested, FOO has mode MODE, C is
10611 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10612 that may be nonzero. */
10613 if (code
== LSHIFTRT
10614 && XEXP (varop
, 1) == const0_rtx
10615 && GET_MODE (XEXP (varop
, 0)) == result_mode
10616 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10617 && HWI_COMPUTABLE_MODE_P (result_mode
)
10618 && STORE_FLAG_VALUE
== -1
10619 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10620 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10623 varop
= XEXP (varop
, 0);
10630 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10631 than the number of bits in the mode is equivalent to A. */
10632 if (code
== LSHIFTRT
10633 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10634 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10636 varop
= XEXP (varop
, 0);
10641 /* NEG commutes with ASHIFT since it is multiplication. Move the
10642 NEG outside to allow shifts to combine. */
10644 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10647 varop
= XEXP (varop
, 0);
10653 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10654 is one less than the number of bits in the mode is
10655 equivalent to (xor A 1). */
10656 if (code
== LSHIFTRT
10657 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10658 && XEXP (varop
, 1) == constm1_rtx
10659 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10660 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10664 varop
= XEXP (varop
, 0);
10668 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10669 that might be nonzero in BAR are those being shifted out and those
10670 bits are known zero in FOO, we can replace the PLUS with FOO.
10671 Similarly in the other operand order. This code occurs when
10672 we are computing the size of a variable-size array. */
10674 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10675 && count
< HOST_BITS_PER_WIDE_INT
10676 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10677 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10678 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10680 varop
= XEXP (varop
, 0);
10683 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10684 && count
< HOST_BITS_PER_WIDE_INT
10685 && HWI_COMPUTABLE_MODE_P (result_mode
)
10686 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10688 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10689 & nonzero_bits (XEXP (varop
, 1),
10692 varop
= XEXP (varop
, 1);
10696 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10698 && CONST_INT_P (XEXP (varop
, 1))
10699 && (new_rtx
= simplify_const_binary_operation
10700 (ASHIFT
, result_mode
,
10701 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10702 GEN_INT (count
))) != 0
10703 && CONST_INT_P (new_rtx
)
10704 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10705 INTVAL (new_rtx
), result_mode
, &complement_p
))
10707 varop
= XEXP (varop
, 0);
10711 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10712 signbit', and attempt to change the PLUS to an XOR and move it to
10713 the outer operation as is done above in the AND/IOR/XOR case
10714 leg for shift(logical). See details in logical handling above
10715 for reasoning in doing so. */
10716 if (code
== LSHIFTRT
10717 && CONST_INT_P (XEXP (varop
, 1))
10718 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10719 && (new_rtx
= simplify_const_binary_operation
10720 (code
, result_mode
,
10721 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10722 GEN_INT (count
))) != 0
10723 && CONST_INT_P (new_rtx
)
10724 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10725 INTVAL (new_rtx
), result_mode
, &complement_p
))
10727 varop
= XEXP (varop
, 0);
10734 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10735 with C the size of VAROP - 1 and the shift is logical if
10736 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10737 we have a (gt X 0) operation. If the shift is arithmetic with
10738 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10739 we have a (neg (gt X 0)) operation. */
10741 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10742 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10743 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10744 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10745 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10746 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10747 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10750 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10753 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10754 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10761 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10762 if the truncate does not affect the value. */
10763 if (code
== LSHIFTRT
10764 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10765 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10766 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10767 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10768 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10770 rtx varop_inner
= XEXP (varop
, 0);
10773 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10774 XEXP (varop_inner
, 0),
10776 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10777 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10790 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10791 outer_op
, outer_const
);
10793 /* We have now finished analyzing the shift. The result should be
10794 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10795 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10796 to the result of the shift. OUTER_CONST is the relevant constant,
10797 but we must turn off all bits turned off in the shift. */
10799 if (outer_op
== UNKNOWN
10800 && orig_code
== code
&& orig_count
== count
10801 && varop
== orig_varop
10802 && shift_mode
== GET_MODE (varop
))
10805 /* Make a SUBREG if necessary. If we can't make it, fail. */
10806 varop
= gen_lowpart (shift_mode
, varop
);
10807 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10810 /* If we have an outer operation and we just made a shift, it is
10811 possible that we could have simplified the shift were it not
10812 for the outer operation. So try to do the simplification
10815 if (outer_op
!= UNKNOWN
)
10816 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10821 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10823 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10824 turn off all the bits that the shift would have turned off. */
10825 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10826 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10827 GET_MODE_MASK (result_mode
) >> orig_count
);
10829 /* Do the remainder of the processing in RESULT_MODE. */
10830 x
= gen_lowpart_or_truncate (result_mode
, x
);
10832 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10835 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10837 if (outer_op
!= UNKNOWN
)
10839 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10840 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10841 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10843 if (outer_op
== AND
)
10844 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10845 else if (outer_op
== SET
)
10847 /* This means that we have determined that the result is
10848 equivalent to a constant. This should be rare. */
10849 if (!side_effects_p (x
))
10850 x
= GEN_INT (outer_const
);
10852 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10853 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10855 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10856 GEN_INT (outer_const
));
10862 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10863 The result of the shift is RESULT_MODE. If we cannot simplify it,
10864 return X or, if it is NULL, synthesize the expression with
10865 simplify_gen_binary. Otherwise, return a simplified value.
10867 The shift is normally computed in the widest mode we find in VAROP, as
10868 long as it isn't a different number of words than RESULT_MODE. Exceptions
10869 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10872 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10873 rtx varop
, int count
)
10875 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10880 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10881 if (GET_MODE (x
) != result_mode
)
10882 x
= gen_lowpart (result_mode
, x
);
10887 /* A subroutine of recog_for_combine. See there for arguments and
10891 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10893 rtx pat
= *pnewpat
;
10894 rtx pat_without_clobbers
;
10895 int insn_code_number
;
10896 int num_clobbers_to_add
= 0;
10898 rtx notes
= NULL_RTX
;
10899 rtx old_notes
, old_pat
;
10902 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10903 we use to indicate that something didn't match. If we find such a
10904 thing, force rejection. */
10905 if (GET_CODE (pat
) == PARALLEL
)
10906 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10907 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10908 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10911 old_pat
= PATTERN (insn
);
10912 old_notes
= REG_NOTES (insn
);
10913 PATTERN (insn
) = pat
;
10914 REG_NOTES (insn
) = NULL_RTX
;
10916 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10917 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10919 if (insn_code_number
< 0)
10920 fputs ("Failed to match this instruction:\n", dump_file
);
10922 fputs ("Successfully matched this instruction:\n", dump_file
);
10923 print_rtl_single (dump_file
, pat
);
10926 /* If it isn't, there is the possibility that we previously had an insn
10927 that clobbered some register as a side effect, but the combined
10928 insn doesn't need to do that. So try once more without the clobbers
10929 unless this represents an ASM insn. */
10931 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10932 && GET_CODE (pat
) == PARALLEL
)
10936 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10937 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10940 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10944 SUBST_INT (XVECLEN (pat
, 0), pos
);
10947 pat
= XVECEXP (pat
, 0, 0);
10949 PATTERN (insn
) = pat
;
10950 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10951 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10953 if (insn_code_number
< 0)
10954 fputs ("Failed to match this instruction:\n", dump_file
);
10956 fputs ("Successfully matched this instruction:\n", dump_file
);
10957 print_rtl_single (dump_file
, pat
);
10961 pat_without_clobbers
= pat
;
10963 PATTERN (insn
) = old_pat
;
10964 REG_NOTES (insn
) = old_notes
;
10966 /* Recognize all noop sets, these will be killed by followup pass. */
10967 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10968 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10970 /* If we had any clobbers to add, make a new pattern than contains
10971 them. Then check to make sure that all of them are dead. */
10972 if (num_clobbers_to_add
)
10974 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10975 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10976 ? (XVECLEN (pat
, 0)
10977 + num_clobbers_to_add
)
10978 : num_clobbers_to_add
+ 1));
10980 if (GET_CODE (pat
) == PARALLEL
)
10981 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10982 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10984 XVECEXP (newpat
, 0, 0) = pat
;
10986 add_clobbers (newpat
, insn_code_number
);
10988 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10989 i
< XVECLEN (newpat
, 0); i
++)
10991 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10992 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10994 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10996 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10997 notes
= alloc_reg_note (REG_UNUSED
,
10998 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11004 if (insn_code_number
>= 0
11005 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11007 old_pat
= PATTERN (insn
);
11008 old_notes
= REG_NOTES (insn
);
11009 old_icode
= INSN_CODE (insn
);
11010 PATTERN (insn
) = pat
;
11011 REG_NOTES (insn
) = notes
;
11013 /* Allow targets to reject combined insn. */
11014 if (!targetm
.legitimate_combined_insn (insn
))
11016 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11017 fputs ("Instruction not appropriate for target.",
11020 /* Callers expect recog_for_combine to strip
11021 clobbers from the pattern on failure. */
11022 pat
= pat_without_clobbers
;
11025 insn_code_number
= -1;
11028 PATTERN (insn
) = old_pat
;
11029 REG_NOTES (insn
) = old_notes
;
11030 INSN_CODE (insn
) = old_icode
;
11036 return insn_code_number
;
11039 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11040 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11041 Return whether anything was so changed. */
11044 change_zero_ext (rtx
*src
)
11046 bool changed
= false;
11048 subrtx_ptr_iterator::array_type array
;
11049 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11052 machine_mode mode
= GET_MODE (x
);
11055 if (GET_CODE (x
) == ZERO_EXTRACT
11056 && CONST_INT_P (XEXP (x
, 1))
11057 && CONST_INT_P (XEXP (x
, 2))
11058 && GET_MODE (XEXP (x
, 0)) == mode
)
11060 size
= INTVAL (XEXP (x
, 1));
11062 int start
= INTVAL (XEXP (x
, 2));
11063 if (BITS_BIG_ENDIAN
)
11064 start
= GET_MODE_PRECISION (mode
) - size
- start
;
11066 x
= gen_rtx_LSHIFTRT (mode
, XEXP (x
, 0), GEN_INT (start
));
11068 else if (GET_CODE (x
) == ZERO_EXTEND
11069 && GET_CODE (XEXP (x
, 0)) == SUBREG
11070 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
11071 && subreg_lowpart_p (XEXP (x
, 0)))
11073 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11074 x
= SUBREG_REG (XEXP (x
, 0));
11079 unsigned HOST_WIDE_INT mask
= 1;
11083 x
= gen_rtx_AND (mode
, x
, GEN_INT (mask
));
11092 /* Like recog, but we receive the address of a pointer to a new pattern.
11093 We try to match the rtx that the pointer points to.
11094 If that fails, we may try to modify or replace the pattern,
11095 storing the replacement into the same pointer object.
11097 Modifications include deletion or addition of CLOBBERs. If the
11098 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11099 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11100 (and undo if that fails).
11102 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11103 the CLOBBERs are placed.
11105 The value is the final insn code from the pattern ultimately matched,
11109 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11111 rtx pat
= PATTERN (insn
);
11112 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11113 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11114 return insn_code_number
;
11116 void *marker
= get_undo_marker ();
11117 bool changed
= false;
11119 if (GET_CODE (pat
) == SET
)
11120 changed
= change_zero_ext (&SET_SRC (pat
));
11121 else if (GET_CODE (pat
) == PARALLEL
)
11124 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11126 rtx set
= XVECEXP (pat
, 0, i
);
11127 if (GET_CODE (set
) == SET
)
11128 changed
|= change_zero_ext (&SET_SRC (set
));
11134 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11136 if (insn_code_number
< 0)
11137 undo_to_marker (marker
);
11140 return insn_code_number
;
11143 /* Like gen_lowpart_general but for use by combine. In combine it
11144 is not possible to create any new pseudoregs. However, it is
11145 safe to create invalid memory addresses, because combine will
11146 try to recognize them and all they will do is make the combine
11149 If for some reason this cannot do its job, an rtx
11150 (clobber (const_int 0)) is returned.
11151 An insn containing that will not be recognized. */
11154 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11156 machine_mode imode
= GET_MODE (x
);
11157 unsigned int osize
= GET_MODE_SIZE (omode
);
11158 unsigned int isize
= GET_MODE_SIZE (imode
);
11161 if (omode
== imode
)
11164 /* We can only support MODE being wider than a word if X is a
11165 constant integer or has a mode the same size. */
11166 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11167 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11170 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11171 won't know what to do. So we will strip off the SUBREG here and
11172 process normally. */
11173 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11175 x
= SUBREG_REG (x
);
11177 /* For use in case we fall down into the address adjustments
11178 further below, we need to adjust the known mode and size of
11179 x; imode and isize, since we just adjusted x. */
11180 imode
= GET_MODE (x
);
11182 if (imode
== omode
)
11185 isize
= GET_MODE_SIZE (imode
);
11188 result
= gen_lowpart_common (omode
, x
);
11197 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11199 if (MEM_VOLATILE_P (x
)
11200 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11203 /* If we want to refer to something bigger than the original memref,
11204 generate a paradoxical subreg instead. That will force a reload
11205 of the original memref X. */
11207 return gen_rtx_SUBREG (omode
, x
, 0);
11209 if (WORDS_BIG_ENDIAN
)
11210 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11212 /* Adjust the address so that the address-after-the-data is
11214 if (BYTES_BIG_ENDIAN
)
11215 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11217 return adjust_address_nv (x
, omode
, offset
);
11220 /* If X is a comparison operator, rewrite it in a new mode. This
11221 probably won't match, but may allow further simplifications. */
11222 else if (COMPARISON_P (x
))
11223 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11225 /* If we couldn't simplify X any other way, just enclose it in a
11226 SUBREG. Normally, this SUBREG won't match, but some patterns may
11227 include an explicit SUBREG or we may simplify it further in combine. */
11233 offset
= subreg_lowpart_offset (omode
, imode
);
11234 if (imode
== VOIDmode
)
11236 imode
= int_mode_for_mode (omode
);
11237 x
= gen_lowpart_common (imode
, x
);
11241 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
11247 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11250 /* Try to simplify a comparison between OP0 and a constant OP1,
11251 where CODE is the comparison code that will be tested, into a
11252 (CODE OP0 const0_rtx) form.
11254 The result is a possibly different comparison code to use.
11255 *POP1 may be updated. */
11257 static enum rtx_code
11258 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11259 rtx op0
, rtx
*pop1
)
11261 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11262 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11264 /* Get the constant we are comparing against and turn off all bits
11265 not on in our mode. */
11266 if (mode
!= VOIDmode
)
11267 const_op
= trunc_int_for_mode (const_op
, mode
);
11269 /* If we are comparing against a constant power of two and the value
11270 being compared can only have that single bit nonzero (e.g., it was
11271 `and'ed with that bit), we can replace this with a comparison
11274 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11275 || code
== LT
|| code
== LTU
)
11276 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11277 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
11278 && (nonzero_bits (op0
, mode
)
11279 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11281 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11285 /* Similarly, if we are comparing a value known to be either -1 or
11286 0 with -1, change it to the opposite comparison against zero. */
11288 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11289 || code
== GEU
|| code
== LTU
)
11290 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11292 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11296 /* Do some canonicalizations based on the comparison code. We prefer
11297 comparisons against zero and then prefer equality comparisons.
11298 If we can reduce the size of a constant, we will do that too. */
11302 /* < C is equivalent to <= (C - 1) */
11307 /* ... fall through to LE case below. */
11313 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11320 /* If we are doing a <= 0 comparison on a value known to have
11321 a zero sign bit, we can replace this with == 0. */
11322 else if (const_op
== 0
11323 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11324 && (nonzero_bits (op0
, mode
)
11325 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11331 /* >= C is equivalent to > (C - 1). */
11336 /* ... fall through to GT below. */
11342 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11349 /* If we are doing a > 0 comparison on a value known to have
11350 a zero sign bit, we can replace this with != 0. */
11351 else if (const_op
== 0
11352 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11353 && (nonzero_bits (op0
, mode
)
11354 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11360 /* < C is equivalent to <= (C - 1). */
11365 /* ... fall through ... */
11367 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11368 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11369 && (unsigned HOST_WIDE_INT
) const_op
11370 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11380 /* unsigned <= 0 is equivalent to == 0 */
11383 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11384 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11385 && (unsigned HOST_WIDE_INT
) const_op
11386 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11394 /* >= C is equivalent to > (C - 1). */
11399 /* ... fall through ... */
11402 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11403 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11404 && (unsigned HOST_WIDE_INT
) const_op
11405 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11415 /* unsigned > 0 is equivalent to != 0 */
11418 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11419 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11420 && (unsigned HOST_WIDE_INT
) const_op
11421 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11432 *pop1
= GEN_INT (const_op
);
11436 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11437 comparison code that will be tested.
11439 The result is a possibly different comparison code to use. *POP0 and
11440 *POP1 may be updated.
11442 It is possible that we might detect that a comparison is either always
11443 true or always false. However, we do not perform general constant
11444 folding in combine, so this knowledge isn't useful. Such tautologies
11445 should have been detected earlier. Hence we ignore all such cases. */
11447 static enum rtx_code
11448 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11454 machine_mode mode
, tmode
;
11456 /* Try a few ways of applying the same transformation to both operands. */
11459 #ifndef WORD_REGISTER_OPERATIONS
11460 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11461 so check specially. */
11462 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11463 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11464 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11465 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11466 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11467 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11468 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11469 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11470 && CONST_INT_P (XEXP (op0
, 1))
11471 && XEXP (op0
, 1) == XEXP (op1
, 1)
11472 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11473 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11474 && (INTVAL (XEXP (op0
, 1))
11475 == (GET_MODE_PRECISION (GET_MODE (op0
))
11476 - (GET_MODE_PRECISION
11477 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11479 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11480 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11484 /* If both operands are the same constant shift, see if we can ignore the
11485 shift. We can if the shift is a rotate or if the bits shifted out of
11486 this shift are known to be zero for both inputs and if the type of
11487 comparison is compatible with the shift. */
11488 if (GET_CODE (op0
) == GET_CODE (op1
)
11489 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11490 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11491 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11492 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11493 || (GET_CODE (op0
) == ASHIFTRT
11494 && (code
!= GTU
&& code
!= LTU
11495 && code
!= GEU
&& code
!= LEU
)))
11496 && CONST_INT_P (XEXP (op0
, 1))
11497 && INTVAL (XEXP (op0
, 1)) >= 0
11498 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11499 && XEXP (op0
, 1) == XEXP (op1
, 1))
11501 machine_mode mode
= GET_MODE (op0
);
11502 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11503 int shift_count
= INTVAL (XEXP (op0
, 1));
11505 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11506 mask
&= (mask
>> shift_count
) << shift_count
;
11507 else if (GET_CODE (op0
) == ASHIFT
)
11508 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11510 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11511 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11512 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11517 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11518 SUBREGs are of the same mode, and, in both cases, the AND would
11519 be redundant if the comparison was done in the narrower mode,
11520 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11521 and the operand's possibly nonzero bits are 0xffffff01; in that case
11522 if we only care about QImode, we don't need the AND). This case
11523 occurs if the output mode of an scc insn is not SImode and
11524 STORE_FLAG_VALUE == 1 (e.g., the 386).
11526 Similarly, check for a case where the AND's are ZERO_EXTEND
11527 operations from some narrower mode even though a SUBREG is not
11530 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11531 && CONST_INT_P (XEXP (op0
, 1))
11532 && CONST_INT_P (XEXP (op1
, 1)))
11534 rtx inner_op0
= XEXP (op0
, 0);
11535 rtx inner_op1
= XEXP (op1
, 0);
11536 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11537 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11540 if (paradoxical_subreg_p (inner_op0
)
11541 && GET_CODE (inner_op1
) == SUBREG
11542 && (GET_MODE (SUBREG_REG (inner_op0
))
11543 == GET_MODE (SUBREG_REG (inner_op1
)))
11544 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11545 <= HOST_BITS_PER_WIDE_INT
)
11546 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11547 GET_MODE (SUBREG_REG (inner_op0
)))))
11548 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11549 GET_MODE (SUBREG_REG (inner_op1
))))))
11551 op0
= SUBREG_REG (inner_op0
);
11552 op1
= SUBREG_REG (inner_op1
);
11554 /* The resulting comparison is always unsigned since we masked
11555 off the original sign bit. */
11556 code
= unsigned_condition (code
);
11562 for (tmode
= GET_CLASS_NARROWEST_MODE
11563 (GET_MODE_CLASS (GET_MODE (op0
)));
11564 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11565 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11567 op0
= gen_lowpart (tmode
, inner_op0
);
11568 op1
= gen_lowpart (tmode
, inner_op1
);
11569 code
= unsigned_condition (code
);
11578 /* If both operands are NOT, we can strip off the outer operation
11579 and adjust the comparison code for swapped operands; similarly for
11580 NEG, except that this must be an equality comparison. */
11581 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11582 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11583 && (code
== EQ
|| code
== NE
)))
11584 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11590 /* If the first operand is a constant, swap the operands and adjust the
11591 comparison code appropriately, but don't do this if the second operand
11592 is already a constant integer. */
11593 if (swap_commutative_operands_p (op0
, op1
))
11595 std::swap (op0
, op1
);
11596 code
= swap_condition (code
);
11599 /* We now enter a loop during which we will try to simplify the comparison.
11600 For the most part, we only are concerned with comparisons with zero,
11601 but some things may really be comparisons with zero but not start
11602 out looking that way. */
11604 while (CONST_INT_P (op1
))
11606 machine_mode mode
= GET_MODE (op0
);
11607 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11608 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11609 int equality_comparison_p
;
11610 int sign_bit_comparison_p
;
11611 int unsigned_comparison_p
;
11612 HOST_WIDE_INT const_op
;
11614 /* We only want to handle integral modes. This catches VOIDmode,
11615 CCmode, and the floating-point modes. An exception is that we
11616 can handle VOIDmode if OP0 is a COMPARE or a comparison
11619 if (GET_MODE_CLASS (mode
) != MODE_INT
11620 && ! (mode
== VOIDmode
11621 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11624 /* Try to simplify the compare to constant, possibly changing the
11625 comparison op, and/or changing op1 to zero. */
11626 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11627 const_op
= INTVAL (op1
);
11629 /* Compute some predicates to simplify code below. */
11631 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11632 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11633 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11636 /* If this is a sign bit comparison and we can do arithmetic in
11637 MODE, say that we will only be needing the sign bit of OP0. */
11638 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11639 op0
= force_to_mode (op0
, mode
,
11640 (unsigned HOST_WIDE_INT
) 1
11641 << (GET_MODE_PRECISION (mode
) - 1),
11644 /* Now try cases based on the opcode of OP0. If none of the cases
11645 does a "continue", we exit this loop immediately after the
11648 switch (GET_CODE (op0
))
11651 /* If we are extracting a single bit from a variable position in
11652 a constant that has only a single bit set and are comparing it
11653 with zero, we can convert this into an equality comparison
11654 between the position and the location of the single bit. */
11655 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11656 have already reduced the shift count modulo the word size. */
11657 if (!SHIFT_COUNT_TRUNCATED
11658 && CONST_INT_P (XEXP (op0
, 0))
11659 && XEXP (op0
, 1) == const1_rtx
11660 && equality_comparison_p
&& const_op
== 0
11661 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11663 if (BITS_BIG_ENDIAN
)
11664 i
= BITS_PER_WORD
- 1 - i
;
11666 op0
= XEXP (op0
, 2);
11670 /* Result is nonzero iff shift count is equal to I. */
11671 code
= reverse_condition (code
);
11675 /* ... fall through ... */
11678 tem
= expand_compound_operation (op0
);
11687 /* If testing for equality, we can take the NOT of the constant. */
11688 if (equality_comparison_p
11689 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11691 op0
= XEXP (op0
, 0);
11696 /* If just looking at the sign bit, reverse the sense of the
11698 if (sign_bit_comparison_p
)
11700 op0
= XEXP (op0
, 0);
11701 code
= (code
== GE
? LT
: GE
);
11707 /* If testing for equality, we can take the NEG of the constant. */
11708 if (equality_comparison_p
11709 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11711 op0
= XEXP (op0
, 0);
11716 /* The remaining cases only apply to comparisons with zero. */
11720 /* When X is ABS or is known positive,
11721 (neg X) is < 0 if and only if X != 0. */
11723 if (sign_bit_comparison_p
11724 && (GET_CODE (XEXP (op0
, 0)) == ABS
11725 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11726 && (nonzero_bits (XEXP (op0
, 0), mode
)
11727 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11730 op0
= XEXP (op0
, 0);
11731 code
= (code
== LT
? NE
: EQ
);
11735 /* If we have NEG of something whose two high-order bits are the
11736 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11737 if (num_sign_bit_copies (op0
, mode
) >= 2)
11739 op0
= XEXP (op0
, 0);
11740 code
= swap_condition (code
);
11746 /* If we are testing equality and our count is a constant, we
11747 can perform the inverse operation on our RHS. */
11748 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11749 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11750 op1
, XEXP (op0
, 1))) != 0)
11752 op0
= XEXP (op0
, 0);
11757 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11758 a particular bit. Convert it to an AND of a constant of that
11759 bit. This will be converted into a ZERO_EXTRACT. */
11760 if (const_op
== 0 && sign_bit_comparison_p
11761 && CONST_INT_P (XEXP (op0
, 1))
11762 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11764 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11765 ((unsigned HOST_WIDE_INT
) 1
11767 - INTVAL (XEXP (op0
, 1)))));
11768 code
= (code
== LT
? NE
: EQ
);
11772 /* Fall through. */
11775 /* ABS is ignorable inside an equality comparison with zero. */
11776 if (const_op
== 0 && equality_comparison_p
)
11778 op0
= XEXP (op0
, 0);
11784 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11785 (compare FOO CONST) if CONST fits in FOO's mode and we
11786 are either testing inequality or have an unsigned
11787 comparison with ZERO_EXTEND or a signed comparison with
11788 SIGN_EXTEND. But don't do it if we don't have a compare
11789 insn of the given mode, since we'd have to revert it
11790 later on, and then we wouldn't know whether to sign- or
11792 mode
= GET_MODE (XEXP (op0
, 0));
11793 if (GET_MODE_CLASS (mode
) == MODE_INT
11794 && ! unsigned_comparison_p
11795 && HWI_COMPUTABLE_MODE_P (mode
)
11796 && trunc_int_for_mode (const_op
, mode
) == const_op
11797 && have_insn_for (COMPARE
, mode
))
11799 op0
= XEXP (op0
, 0);
11805 /* Check for the case where we are comparing A - C1 with C2, that is
11807 (subreg:MODE (plus (A) (-C1))) op (C2)
11809 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11810 comparison in the wider mode. One of the following two conditions
11811 must be true in order for this to be valid:
11813 1. The mode extension results in the same bit pattern being added
11814 on both sides and the comparison is equality or unsigned. As
11815 C2 has been truncated to fit in MODE, the pattern can only be
11818 2. The mode extension results in the sign bit being copied on
11821 The difficulty here is that we have predicates for A but not for
11822 (A - C1) so we need to check that C1 is within proper bounds so
11823 as to perturbate A as little as possible. */
11825 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11826 && subreg_lowpart_p (op0
)
11827 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11828 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11829 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11831 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11832 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11833 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11836 && (unsigned HOST_WIDE_INT
) c1
11837 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11838 && (equality_comparison_p
|| unsigned_comparison_p
)
11839 /* (A - C1) zero-extends if it is positive and sign-extends
11840 if it is negative, C2 both zero- and sign-extends. */
11841 && ((0 == (nonzero_bits (a
, inner_mode
)
11842 & ~GET_MODE_MASK (mode
))
11844 /* (A - C1) sign-extends if it is positive and 1-extends
11845 if it is negative, C2 both sign- and 1-extends. */
11846 || (num_sign_bit_copies (a
, inner_mode
)
11847 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11850 || ((unsigned HOST_WIDE_INT
) c1
11851 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11852 /* (A - C1) always sign-extends, like C2. */
11853 && num_sign_bit_copies (a
, inner_mode
)
11854 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11855 - (mode_width
- 1))))
11857 op0
= SUBREG_REG (op0
);
11862 /* If the inner mode is narrower and we are extracting the low part,
11863 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11864 if (subreg_lowpart_p (op0
)
11865 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11866 /* Fall through */ ;
11870 /* ... fall through ... */
11873 mode
= GET_MODE (XEXP (op0
, 0));
11874 if (GET_MODE_CLASS (mode
) == MODE_INT
11875 && (unsigned_comparison_p
|| equality_comparison_p
)
11876 && HWI_COMPUTABLE_MODE_P (mode
)
11877 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11879 && have_insn_for (COMPARE
, mode
))
11881 op0
= XEXP (op0
, 0);
11887 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11888 this for equality comparisons due to pathological cases involving
11890 if (equality_comparison_p
11891 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11892 op1
, XEXP (op0
, 1))))
11894 op0
= XEXP (op0
, 0);
11899 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11900 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11901 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11903 op0
= XEXP (XEXP (op0
, 0), 0);
11904 code
= (code
== LT
? EQ
: NE
);
11910 /* We used to optimize signed comparisons against zero, but that
11911 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11912 arrive here as equality comparisons, or (GEU, LTU) are
11913 optimized away. No need to special-case them. */
11915 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11916 (eq B (minus A C)), whichever simplifies. We can only do
11917 this for equality comparisons due to pathological cases involving
11919 if (equality_comparison_p
11920 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11921 XEXP (op0
, 1), op1
)))
11923 op0
= XEXP (op0
, 0);
11928 if (equality_comparison_p
11929 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11930 XEXP (op0
, 0), op1
)))
11932 op0
= XEXP (op0
, 1);
11937 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11938 of bits in X minus 1, is one iff X > 0. */
11939 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11940 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11941 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11942 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11944 op0
= XEXP (op0
, 1);
11945 code
= (code
== GE
? LE
: GT
);
11951 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11952 if C is zero or B is a constant. */
11953 if (equality_comparison_p
11954 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11955 XEXP (op0
, 1), op1
)))
11957 op0
= XEXP (op0
, 0);
11964 case UNEQ
: case LTGT
:
11965 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11966 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11967 case UNORDERED
: case ORDERED
:
11968 /* We can't do anything if OP0 is a condition code value, rather
11969 than an actual data value. */
11971 || CC0_P (XEXP (op0
, 0))
11972 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11975 /* Get the two operands being compared. */
11976 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11977 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11979 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11981 /* Check for the cases where we simply want the result of the
11982 earlier test or the opposite of that result. */
11983 if (code
== NE
|| code
== EQ
11984 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11985 && (code
== LT
|| code
== GE
)))
11987 enum rtx_code new_code
;
11988 if (code
== LT
|| code
== NE
)
11989 new_code
= GET_CODE (op0
);
11991 new_code
= reversed_comparison_code (op0
, NULL
);
11993 if (new_code
!= UNKNOWN
)
12004 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12006 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12007 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12008 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12010 op0
= XEXP (op0
, 1);
12011 code
= (code
== GE
? GT
: LE
);
12017 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12018 will be converted to a ZERO_EXTRACT later. */
12019 if (const_op
== 0 && equality_comparison_p
12020 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12021 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12023 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12024 XEXP (XEXP (op0
, 0), 1));
12025 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12029 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12030 zero and X is a comparison and C1 and C2 describe only bits set
12031 in STORE_FLAG_VALUE, we can compare with X. */
12032 if (const_op
== 0 && equality_comparison_p
12033 && mode_width
<= HOST_BITS_PER_WIDE_INT
12034 && CONST_INT_P (XEXP (op0
, 1))
12035 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12036 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12037 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12038 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12040 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12041 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12042 if ((~STORE_FLAG_VALUE
& mask
) == 0
12043 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12044 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12045 && COMPARISON_P (tem
))))
12047 op0
= XEXP (XEXP (op0
, 0), 0);
12052 /* If we are doing an equality comparison of an AND of a bit equal
12053 to the sign bit, replace this with a LT or GE comparison of
12054 the underlying value. */
12055 if (equality_comparison_p
12057 && CONST_INT_P (XEXP (op0
, 1))
12058 && mode_width
<= HOST_BITS_PER_WIDE_INT
12059 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12060 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
12062 op0
= XEXP (op0
, 0);
12063 code
= (code
== EQ
? GE
: LT
);
12067 /* If this AND operation is really a ZERO_EXTEND from a narrower
12068 mode, the constant fits within that mode, and this is either an
12069 equality or unsigned comparison, try to do this comparison in
12074 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12075 -> (ne:DI (reg:SI 4) (const_int 0))
12077 unless TRULY_NOOP_TRUNCATION allows it or the register is
12078 known to hold a value of the required mode the
12079 transformation is invalid. */
12080 if ((equality_comparison_p
|| unsigned_comparison_p
)
12081 && CONST_INT_P (XEXP (op0
, 1))
12082 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12083 & GET_MODE_MASK (mode
))
12085 && const_op
>> i
== 0
12086 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
12087 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
12088 || (REG_P (XEXP (op0
, 0))
12089 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
12091 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
12095 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12096 fits in both M1 and M2 and the SUBREG is either paradoxical
12097 or represents the low part, permute the SUBREG and the AND
12099 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
12101 unsigned HOST_WIDE_INT c1
;
12102 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12103 /* Require an integral mode, to avoid creating something like
12105 if (SCALAR_INT_MODE_P (tmode
)
12106 /* It is unsafe to commute the AND into the SUBREG if the
12107 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12108 not defined. As originally written the upper bits
12109 have a defined value due to the AND operation.
12110 However, if we commute the AND inside the SUBREG then
12111 they no longer have defined values and the meaning of
12112 the code has been changed. */
12114 #ifdef WORD_REGISTER_OPERATIONS
12115 || (mode_width
> GET_MODE_PRECISION (tmode
)
12116 && mode_width
<= BITS_PER_WORD
)
12118 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12119 && subreg_lowpart_p (XEXP (op0
, 0))))
12120 && CONST_INT_P (XEXP (op0
, 1))
12121 && mode_width
<= HOST_BITS_PER_WIDE_INT
12122 && HWI_COMPUTABLE_MODE_P (tmode
)
12123 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
12124 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12126 && c1
!= GET_MODE_MASK (tmode
))
12128 op0
= simplify_gen_binary (AND
, tmode
,
12129 SUBREG_REG (XEXP (op0
, 0)),
12130 gen_int_mode (c1
, tmode
));
12131 op0
= gen_lowpart (mode
, op0
);
12136 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12137 if (const_op
== 0 && equality_comparison_p
12138 && XEXP (op0
, 1) == const1_rtx
12139 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12141 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12142 XEXP (XEXP (op0
, 0), 0), 1);
12143 code
= (code
== NE
? EQ
: NE
);
12147 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12148 (eq (and (lshiftrt X) 1) 0).
12149 Also handle the case where (not X) is expressed using xor. */
12150 if (const_op
== 0 && equality_comparison_p
12151 && XEXP (op0
, 1) == const1_rtx
12152 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12154 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12155 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12157 if (GET_CODE (shift_op
) == NOT
12158 || (GET_CODE (shift_op
) == XOR
12159 && CONST_INT_P (XEXP (shift_op
, 1))
12160 && CONST_INT_P (shift_count
)
12161 && HWI_COMPUTABLE_MODE_P (mode
)
12162 && (UINTVAL (XEXP (shift_op
, 1))
12163 == (unsigned HOST_WIDE_INT
) 1
12164 << INTVAL (shift_count
))))
12167 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12168 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12169 code
= (code
== NE
? EQ
: NE
);
12176 /* If we have (compare (ashift FOO N) (const_int C)) and
12177 the high order N bits of FOO (N+1 if an inequality comparison)
12178 are known to be zero, we can do this by comparing FOO with C
12179 shifted right N bits so long as the low-order N bits of C are
12181 if (CONST_INT_P (XEXP (op0
, 1))
12182 && INTVAL (XEXP (op0
, 1)) >= 0
12183 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12184 < HOST_BITS_PER_WIDE_INT
)
12185 && (((unsigned HOST_WIDE_INT
) const_op
12186 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
12188 && mode_width
<= HOST_BITS_PER_WIDE_INT
12189 && (nonzero_bits (XEXP (op0
, 0), mode
)
12190 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12191 + ! equality_comparison_p
))) == 0)
12193 /* We must perform a logical shift, not an arithmetic one,
12194 as we want the top N bits of C to be zero. */
12195 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12197 temp
>>= INTVAL (XEXP (op0
, 1));
12198 op1
= gen_int_mode (temp
, mode
);
12199 op0
= XEXP (op0
, 0);
12203 /* If we are doing a sign bit comparison, it means we are testing
12204 a particular bit. Convert it to the appropriate AND. */
12205 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12206 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12208 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12209 ((unsigned HOST_WIDE_INT
) 1
12211 - INTVAL (XEXP (op0
, 1)))));
12212 code
= (code
== LT
? NE
: EQ
);
12216 /* If this an equality comparison with zero and we are shifting
12217 the low bit to the sign bit, we can convert this to an AND of the
12219 if (const_op
== 0 && equality_comparison_p
12220 && CONST_INT_P (XEXP (op0
, 1))
12221 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12223 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12229 /* If this is an equality comparison with zero, we can do this
12230 as a logical shift, which might be much simpler. */
12231 if (equality_comparison_p
&& const_op
== 0
12232 && CONST_INT_P (XEXP (op0
, 1)))
12234 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12236 INTVAL (XEXP (op0
, 1)));
12240 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12241 do the comparison in a narrower mode. */
12242 if (! unsigned_comparison_p
12243 && CONST_INT_P (XEXP (op0
, 1))
12244 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12245 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12246 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12247 MODE_INT
, 1)) != BLKmode
12248 && (((unsigned HOST_WIDE_INT
) const_op
12249 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12250 <= GET_MODE_MASK (tmode
)))
12252 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12256 /* Likewise if OP0 is a PLUS of a sign extension with a
12257 constant, which is usually represented with the PLUS
12258 between the shifts. */
12259 if (! unsigned_comparison_p
12260 && CONST_INT_P (XEXP (op0
, 1))
12261 && GET_CODE (XEXP (op0
, 0)) == PLUS
12262 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12263 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12264 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12265 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12266 MODE_INT
, 1)) != BLKmode
12267 && (((unsigned HOST_WIDE_INT
) const_op
12268 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12269 <= GET_MODE_MASK (tmode
)))
12271 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12272 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12273 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12274 add_const
, XEXP (op0
, 1));
12276 op0
= simplify_gen_binary (PLUS
, tmode
,
12277 gen_lowpart (tmode
, inner
),
12282 /* ... fall through ... */
12284 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12285 the low order N bits of FOO are known to be zero, we can do this
12286 by comparing FOO with C shifted left N bits so long as no
12287 overflow occurs. Even if the low order N bits of FOO aren't known
12288 to be zero, if the comparison is >= or < we can use the same
12289 optimization and for > or <= by setting all the low
12290 order N bits in the comparison constant. */
12291 if (CONST_INT_P (XEXP (op0
, 1))
12292 && INTVAL (XEXP (op0
, 1)) > 0
12293 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12294 && mode_width
<= HOST_BITS_PER_WIDE_INT
12295 && (((unsigned HOST_WIDE_INT
) const_op
12296 + (GET_CODE (op0
) != LSHIFTRT
12297 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12300 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12302 unsigned HOST_WIDE_INT low_bits
12303 = (nonzero_bits (XEXP (op0
, 0), mode
)
12304 & (((unsigned HOST_WIDE_INT
) 1
12305 << INTVAL (XEXP (op0
, 1))) - 1));
12306 if (low_bits
== 0 || !equality_comparison_p
)
12308 /* If the shift was logical, then we must make the condition
12310 if (GET_CODE (op0
) == LSHIFTRT
)
12311 code
= unsigned_condition (code
);
12313 const_op
<<= INTVAL (XEXP (op0
, 1));
12315 && (code
== GT
|| code
== GTU
12316 || code
== LE
|| code
== LEU
))
12318 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
12319 op1
= GEN_INT (const_op
);
12320 op0
= XEXP (op0
, 0);
12325 /* If we are using this shift to extract just the sign bit, we
12326 can replace this with an LT or GE comparison. */
12328 && (equality_comparison_p
|| sign_bit_comparison_p
)
12329 && CONST_INT_P (XEXP (op0
, 1))
12330 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12332 op0
= XEXP (op0
, 0);
12333 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12345 /* Now make any compound operations involved in this comparison. Then,
12346 check for an outmost SUBREG on OP0 that is not doing anything or is
12347 paradoxical. The latter transformation must only be performed when
12348 it is known that the "extra" bits will be the same in op0 and op1 or
12349 that they don't matter. There are three cases to consider:
12351 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12352 care bits and we can assume they have any convenient value. So
12353 making the transformation is safe.
12355 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12356 In this case the upper bits of op0 are undefined. We should not make
12357 the simplification in that case as we do not know the contents of
12360 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12361 UNKNOWN. In that case we know those bits are zeros or ones. We must
12362 also be sure that they are the same as the upper bits of op1.
12364 We can never remove a SUBREG for a non-equality comparison because
12365 the sign bit is in a different place in the underlying object. */
12367 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12368 op1
= make_compound_operation (op1
, SET
);
12370 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12371 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12372 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12373 && (code
== NE
|| code
== EQ
))
12375 if (paradoxical_subreg_p (op0
))
12377 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12379 if (REG_P (SUBREG_REG (op0
)))
12381 op0
= SUBREG_REG (op0
);
12382 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12385 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12386 <= HOST_BITS_PER_WIDE_INT
)
12387 && (nonzero_bits (SUBREG_REG (op0
),
12388 GET_MODE (SUBREG_REG (op0
)))
12389 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12391 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12393 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12394 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12395 op0
= SUBREG_REG (op0
), op1
= tem
;
12399 /* We now do the opposite procedure: Some machines don't have compare
12400 insns in all modes. If OP0's mode is an integer mode smaller than a
12401 word and we can't do a compare in that mode, see if there is a larger
12402 mode for which we can do the compare. There are a number of cases in
12403 which we can use the wider mode. */
12405 mode
= GET_MODE (op0
);
12406 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12407 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12408 && ! have_insn_for (COMPARE
, mode
))
12409 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12410 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12411 tmode
= GET_MODE_WIDER_MODE (tmode
))
12412 if (have_insn_for (COMPARE
, tmode
))
12416 /* If this is a test for negative, we can make an explicit
12417 test of the sign bit. Test this first so we can use
12418 a paradoxical subreg to extend OP0. */
12420 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12421 && HWI_COMPUTABLE_MODE_P (mode
))
12423 unsigned HOST_WIDE_INT sign
12424 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12425 op0
= simplify_gen_binary (AND
, tmode
,
12426 gen_lowpart (tmode
, op0
),
12427 gen_int_mode (sign
, tmode
));
12428 code
= (code
== LT
) ? NE
: EQ
;
12432 /* If the only nonzero bits in OP0 and OP1 are those in the
12433 narrower mode and this is an equality or unsigned comparison,
12434 we can use the wider mode. Similarly for sign-extended
12435 values, in which case it is true for all comparisons. */
12436 zero_extended
= ((code
== EQ
|| code
== NE
12437 || code
== GEU
|| code
== GTU
12438 || code
== LEU
|| code
== LTU
)
12439 && (nonzero_bits (op0
, tmode
)
12440 & ~GET_MODE_MASK (mode
)) == 0
12441 && ((CONST_INT_P (op1
)
12442 || (nonzero_bits (op1
, tmode
)
12443 & ~GET_MODE_MASK (mode
)) == 0)));
12446 || ((num_sign_bit_copies (op0
, tmode
)
12447 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12448 - GET_MODE_PRECISION (mode
)))
12449 && (num_sign_bit_copies (op1
, tmode
)
12450 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12451 - GET_MODE_PRECISION (mode
)))))
12453 /* If OP0 is an AND and we don't have an AND in MODE either,
12454 make a new AND in the proper mode. */
12455 if (GET_CODE (op0
) == AND
12456 && !have_insn_for (AND
, mode
))
12457 op0
= simplify_gen_binary (AND
, tmode
,
12458 gen_lowpart (tmode
,
12460 gen_lowpart (tmode
,
12466 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12467 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12471 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12472 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12479 /* We may have changed the comparison operands. Re-canonicalize. */
12480 if (swap_commutative_operands_p (op0
, op1
))
12482 std::swap (op0
, op1
);
12483 code
= swap_condition (code
);
12486 /* If this machine only supports a subset of valid comparisons, see if we
12487 can convert an unsupported one into a supported one. */
12488 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12496 /* Utility function for record_value_for_reg. Count number of
12501 enum rtx_code code
= GET_CODE (x
);
12505 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12506 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12508 rtx x0
= XEXP (x
, 0);
12509 rtx x1
= XEXP (x
, 1);
12512 return 1 + 2 * count_rtxs (x0
);
12514 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12515 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12516 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12517 return 2 + 2 * count_rtxs (x0
)
12518 + count_rtxs (x
== XEXP (x1
, 0)
12519 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12521 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12522 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12523 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12524 return 2 + 2 * count_rtxs (x1
)
12525 + count_rtxs (x
== XEXP (x0
, 0)
12526 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12529 fmt
= GET_RTX_FORMAT (code
);
12530 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12532 ret
+= count_rtxs (XEXP (x
, i
));
12533 else if (fmt
[i
] == 'E')
12534 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12535 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12540 /* Utility function for following routine. Called when X is part of a value
12541 being stored into last_set_value. Sets last_set_table_tick
12542 for each register mentioned. Similar to mention_regs in cse.c */
12545 update_table_tick (rtx x
)
12547 enum rtx_code code
= GET_CODE (x
);
12548 const char *fmt
= GET_RTX_FORMAT (code
);
12553 unsigned int regno
= REGNO (x
);
12554 unsigned int endregno
= END_REGNO (x
);
12557 for (r
= regno
; r
< endregno
; r
++)
12559 reg_stat_type
*rsp
= ®_stat
[r
];
12560 rsp
->last_set_table_tick
= label_tick
;
12566 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12569 /* Check for identical subexpressions. If x contains
12570 identical subexpression we only have to traverse one of
12572 if (i
== 0 && ARITHMETIC_P (x
))
12574 /* Note that at this point x1 has already been
12576 rtx x0
= XEXP (x
, 0);
12577 rtx x1
= XEXP (x
, 1);
12579 /* If x0 and x1 are identical then there is no need to
12584 /* If x0 is identical to a subexpression of x1 then while
12585 processing x1, x0 has already been processed. Thus we
12586 are done with x. */
12587 if (ARITHMETIC_P (x1
)
12588 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12591 /* If x1 is identical to a subexpression of x0 then we
12592 still have to process the rest of x0. */
12593 if (ARITHMETIC_P (x0
)
12594 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12596 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12601 update_table_tick (XEXP (x
, i
));
12603 else if (fmt
[i
] == 'E')
12604 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12605 update_table_tick (XVECEXP (x
, i
, j
));
12608 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12609 are saying that the register is clobbered and we no longer know its
12610 value. If INSN is zero, don't update reg_stat[].last_set; this is
12611 only permitted with VALUE also zero and is used to invalidate the
12615 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12617 unsigned int regno
= REGNO (reg
);
12618 unsigned int endregno
= END_REGNO (reg
);
12620 reg_stat_type
*rsp
;
12622 /* If VALUE contains REG and we have a previous value for REG, substitute
12623 the previous value. */
12624 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12628 /* Set things up so get_last_value is allowed to see anything set up to
12630 subst_low_luid
= DF_INSN_LUID (insn
);
12631 tem
= get_last_value (reg
);
12633 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12634 it isn't going to be useful and will take a lot of time to process,
12635 so just use the CLOBBER. */
12639 if (ARITHMETIC_P (tem
)
12640 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12641 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12642 tem
= XEXP (tem
, 0);
12643 else if (count_occurrences (value
, reg
, 1) >= 2)
12645 /* If there are two or more occurrences of REG in VALUE,
12646 prevent the value from growing too much. */
12647 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12648 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12651 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12655 /* For each register modified, show we don't know its value, that
12656 we don't know about its bitwise content, that its value has been
12657 updated, and that we don't know the location of the death of the
12659 for (i
= regno
; i
< endregno
; i
++)
12661 rsp
= ®_stat
[i
];
12664 rsp
->last_set
= insn
;
12666 rsp
->last_set_value
= 0;
12667 rsp
->last_set_mode
= VOIDmode
;
12668 rsp
->last_set_nonzero_bits
= 0;
12669 rsp
->last_set_sign_bit_copies
= 0;
12670 rsp
->last_death
= 0;
12671 rsp
->truncated_to_mode
= VOIDmode
;
12674 /* Mark registers that are being referenced in this value. */
12676 update_table_tick (value
);
12678 /* Now update the status of each register being set.
12679 If someone is using this register in this block, set this register
12680 to invalid since we will get confused between the two lives in this
12681 basic block. This makes using this register always invalid. In cse, we
12682 scan the table to invalidate all entries using this register, but this
12683 is too much work for us. */
12685 for (i
= regno
; i
< endregno
; i
++)
12687 rsp
= ®_stat
[i
];
12688 rsp
->last_set_label
= label_tick
;
12690 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12691 rsp
->last_set_invalid
= 1;
12693 rsp
->last_set_invalid
= 0;
12696 /* The value being assigned might refer to X (like in "x++;"). In that
12697 case, we must replace it with (clobber (const_int 0)) to prevent
12699 rsp
= ®_stat
[regno
];
12700 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12702 value
= copy_rtx (value
);
12703 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12707 /* For the main register being modified, update the value, the mode, the
12708 nonzero bits, and the number of sign bit copies. */
12710 rsp
->last_set_value
= value
;
12714 machine_mode mode
= GET_MODE (reg
);
12715 subst_low_luid
= DF_INSN_LUID (insn
);
12716 rsp
->last_set_mode
= mode
;
12717 if (GET_MODE_CLASS (mode
) == MODE_INT
12718 && HWI_COMPUTABLE_MODE_P (mode
))
12719 mode
= nonzero_bits_mode
;
12720 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12721 rsp
->last_set_sign_bit_copies
12722 = num_sign_bit_copies (value
, GET_MODE (reg
));
12726 /* Called via note_stores from record_dead_and_set_regs to handle one
12727 SET or CLOBBER in an insn. DATA is the instruction in which the
12728 set is occurring. */
12731 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12733 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12735 if (GET_CODE (dest
) == SUBREG
)
12736 dest
= SUBREG_REG (dest
);
12738 if (!record_dead_insn
)
12741 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12747 /* If we are setting the whole register, we know its value. Otherwise
12748 show that we don't know the value. We can handle SUBREG in
12750 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12751 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12752 else if (GET_CODE (setter
) == SET
12753 && GET_CODE (SET_DEST (setter
)) == SUBREG
12754 && SUBREG_REG (SET_DEST (setter
)) == dest
12755 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12756 && subreg_lowpart_p (SET_DEST (setter
)))
12757 record_value_for_reg (dest
, record_dead_insn
,
12758 gen_lowpart (GET_MODE (dest
),
12759 SET_SRC (setter
)));
12761 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12763 else if (MEM_P (dest
)
12764 /* Ignore pushes, they clobber nothing. */
12765 && ! push_operand (dest
, GET_MODE (dest
)))
12766 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12769 /* Update the records of when each REG was most recently set or killed
12770 for the things done by INSN. This is the last thing done in processing
12771 INSN in the combiner loop.
12773 We update reg_stat[], in particular fields last_set, last_set_value,
12774 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12775 last_death, and also the similar information mem_last_set (which insn
12776 most recently modified memory) and last_call_luid (which insn was the
12777 most recent subroutine call). */
12780 record_dead_and_set_regs (rtx_insn
*insn
)
12785 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12787 if (REG_NOTE_KIND (link
) == REG_DEAD
12788 && REG_P (XEXP (link
, 0)))
12790 unsigned int regno
= REGNO (XEXP (link
, 0));
12791 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12793 for (i
= regno
; i
< endregno
; i
++)
12795 reg_stat_type
*rsp
;
12797 rsp
= ®_stat
[i
];
12798 rsp
->last_death
= insn
;
12801 else if (REG_NOTE_KIND (link
) == REG_INC
)
12802 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12807 hard_reg_set_iterator hrsi
;
12808 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12810 reg_stat_type
*rsp
;
12812 rsp
= ®_stat
[i
];
12813 rsp
->last_set_invalid
= 1;
12814 rsp
->last_set
= insn
;
12815 rsp
->last_set_value
= 0;
12816 rsp
->last_set_mode
= VOIDmode
;
12817 rsp
->last_set_nonzero_bits
= 0;
12818 rsp
->last_set_sign_bit_copies
= 0;
12819 rsp
->last_death
= 0;
12820 rsp
->truncated_to_mode
= VOIDmode
;
12823 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12825 /* We can't combine into a call pattern. Remember, though, that
12826 the return value register is set at this LUID. We could
12827 still replace a register with the return value from the
12828 wrong subroutine call! */
12829 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12832 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12835 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12836 register present in the SUBREG, so for each such SUBREG go back and
12837 adjust nonzero and sign bit information of the registers that are
12838 known to have some zero/sign bits set.
12840 This is needed because when combine blows the SUBREGs away, the
12841 information on zero/sign bits is lost and further combines can be
12842 missed because of that. */
12845 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12847 struct insn_link
*links
;
12849 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12850 machine_mode mode
= GET_MODE (subreg
);
12852 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12855 for (links
= LOG_LINKS (insn
); links
;)
12857 reg_stat_type
*rsp
;
12859 insn
= links
->insn
;
12860 set
= single_set (insn
);
12862 if (! set
|| !REG_P (SET_DEST (set
))
12863 || REGNO (SET_DEST (set
)) != regno
12864 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12866 links
= links
->next
;
12870 rsp
= ®_stat
[regno
];
12871 if (rsp
->last_set
== insn
)
12873 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12874 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12877 if (REG_P (SET_SRC (set
)))
12879 regno
= REGNO (SET_SRC (set
));
12880 links
= LOG_LINKS (insn
);
12887 /* Check if X, a register, is known to contain a value already
12888 truncated to MODE. In this case we can use a subreg to refer to
12889 the truncated value even though in the generic case we would need
12890 an explicit truncation. */
12893 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12895 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12896 machine_mode truncated
= rsp
->truncated_to_mode
;
12899 || rsp
->truncation_label
< label_tick_ebb_start
)
12901 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12903 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12908 /* If X is a hard reg or a subreg record the mode that the register is
12909 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12910 to turn a truncate into a subreg using this information. Return true
12911 if traversing X is complete. */
12914 record_truncated_value (rtx x
)
12916 machine_mode truncated_mode
;
12917 reg_stat_type
*rsp
;
12919 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12921 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12922 truncated_mode
= GET_MODE (x
);
12924 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12927 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12930 x
= SUBREG_REG (x
);
12932 /* ??? For hard-regs we now record everything. We might be able to
12933 optimize this using last_set_mode. */
12934 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12935 truncated_mode
= GET_MODE (x
);
12939 rsp
= ®_stat
[REGNO (x
)];
12940 if (rsp
->truncated_to_mode
== 0
12941 || rsp
->truncation_label
< label_tick_ebb_start
12942 || (GET_MODE_SIZE (truncated_mode
)
12943 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12945 rsp
->truncated_to_mode
= truncated_mode
;
12946 rsp
->truncation_label
= label_tick
;
12952 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12953 the modes they are used in. This can help truning TRUNCATEs into
12957 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12959 subrtx_var_iterator::array_type array
;
12960 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12961 if (record_truncated_value (*iter
))
12962 iter
.skip_subrtxes ();
12965 /* Scan X for promoted SUBREGs. For each one found,
12966 note what it implies to the registers used in it. */
12969 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12971 if (GET_CODE (x
) == SUBREG
12972 && SUBREG_PROMOTED_VAR_P (x
)
12973 && REG_P (SUBREG_REG (x
)))
12974 record_promoted_value (insn
, x
);
12977 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12980 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12984 check_promoted_subreg (insn
, XEXP (x
, i
));
12988 if (XVEC (x
, i
) != 0)
12989 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12990 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12996 /* Verify that all the registers and memory references mentioned in *LOC are
12997 still valid. *LOC was part of a value set in INSN when label_tick was
12998 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12999 the invalid references with (clobber (const_int 0)) and return 1. This
13000 replacement is useful because we often can get useful information about
13001 the form of a value (e.g., if it was produced by a shift that always
13002 produces -1 or 0) even though we don't know exactly what registers it
13003 was produced from. */
13006 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13009 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13010 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13015 unsigned int regno
= REGNO (x
);
13016 unsigned int endregno
= END_REGNO (x
);
13019 for (j
= regno
; j
< endregno
; j
++)
13021 reg_stat_type
*rsp
= ®_stat
[j
];
13022 if (rsp
->last_set_invalid
13023 /* If this is a pseudo-register that was only set once and not
13024 live at the beginning of the function, it is always valid. */
13025 || (! (regno
>= FIRST_PSEUDO_REGISTER
13026 && regno
< reg_n_sets_max
13027 && REG_N_SETS (regno
) == 1
13028 && (!REGNO_REG_SET_P
13029 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13031 && rsp
->last_set_label
> tick
))
13034 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13041 /* If this is a memory reference, make sure that there were no stores after
13042 it that might have clobbered the value. We don't have alias info, so we
13043 assume any store invalidates it. Moreover, we only have local UIDs, so
13044 we also assume that there were stores in the intervening basic blocks. */
13045 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13046 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13049 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13053 for (i
= 0; i
< len
; i
++)
13057 /* Check for identical subexpressions. If x contains
13058 identical subexpression we only have to traverse one of
13060 if (i
== 1 && ARITHMETIC_P (x
))
13062 /* Note that at this point x0 has already been checked
13063 and found valid. */
13064 rtx x0
= XEXP (x
, 0);
13065 rtx x1
= XEXP (x
, 1);
13067 /* If x0 and x1 are identical then x is also valid. */
13071 /* If x1 is identical to a subexpression of x0 then
13072 while checking x0, x1 has already been checked. Thus
13073 it is valid and so as x. */
13074 if (ARITHMETIC_P (x0
)
13075 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13078 /* If x0 is identical to a subexpression of x1 then x is
13079 valid iff the rest of x1 is valid. */
13080 if (ARITHMETIC_P (x1
)
13081 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13083 get_last_value_validate (&XEXP (x1
,
13084 x0
== XEXP (x1
, 0) ? 1 : 0),
13085 insn
, tick
, replace
);
13088 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13092 else if (fmt
[i
] == 'E')
13093 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13094 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13095 insn
, tick
, replace
) == 0)
13099 /* If we haven't found a reason for it to be invalid, it is valid. */
13103 /* Get the last value assigned to X, if known. Some registers
13104 in the value may be replaced with (clobber (const_int 0)) if their value
13105 is known longer known reliably. */
13108 get_last_value (const_rtx x
)
13110 unsigned int regno
;
13112 reg_stat_type
*rsp
;
13114 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13115 then convert it to the desired mode. If this is a paradoxical SUBREG,
13116 we cannot predict what values the "extra" bits might have. */
13117 if (GET_CODE (x
) == SUBREG
13118 && subreg_lowpart_p (x
)
13119 && !paradoxical_subreg_p (x
)
13120 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13121 return gen_lowpart (GET_MODE (x
), value
);
13127 rsp
= ®_stat
[regno
];
13128 value
= rsp
->last_set_value
;
13130 /* If we don't have a value, or if it isn't for this basic block and
13131 it's either a hard register, set more than once, or it's a live
13132 at the beginning of the function, return 0.
13134 Because if it's not live at the beginning of the function then the reg
13135 is always set before being used (is never used without being set).
13136 And, if it's set only once, and it's always set before use, then all
13137 uses must have the same last value, even if it's not from this basic
13141 || (rsp
->last_set_label
< label_tick_ebb_start
13142 && (regno
< FIRST_PSEUDO_REGISTER
13143 || regno
>= reg_n_sets_max
13144 || REG_N_SETS (regno
) != 1
13146 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13149 /* If the value was set in a later insn than the ones we are processing,
13150 we can't use it even if the register was only set once. */
13151 if (rsp
->last_set_label
== label_tick
13152 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13155 /* If the value has all its registers valid, return it. */
13156 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13159 /* Otherwise, make a copy and replace any invalid register with
13160 (clobber (const_int 0)). If that fails for some reason, return 0. */
13162 value
= copy_rtx (value
);
13163 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13169 /* Return nonzero if expression X refers to a REG or to memory
13170 that is set in an instruction more recent than FROM_LUID. */
13173 use_crosses_set_p (const_rtx x
, int from_luid
)
13177 enum rtx_code code
= GET_CODE (x
);
13181 unsigned int regno
= REGNO (x
);
13182 unsigned endreg
= END_REGNO (x
);
13184 #ifdef PUSH_ROUNDING
13185 /* Don't allow uses of the stack pointer to be moved,
13186 because we don't know whether the move crosses a push insn. */
13187 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13190 for (; regno
< endreg
; regno
++)
13192 reg_stat_type
*rsp
= ®_stat
[regno
];
13194 && rsp
->last_set_label
== label_tick
13195 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13201 if (code
== MEM
&& mem_last_set
> from_luid
)
13204 fmt
= GET_RTX_FORMAT (code
);
13206 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13211 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13212 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13215 else if (fmt
[i
] == 'e'
13216 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13222 /* Define three variables used for communication between the following
13225 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13226 static int reg_dead_flag
;
13228 /* Function called via note_stores from reg_dead_at_p.
13230 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13231 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13234 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13236 unsigned int regno
, endregno
;
13241 regno
= REGNO (dest
);
13242 endregno
= END_REGNO (dest
);
13243 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13244 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13247 /* Return nonzero if REG is known to be dead at INSN.
13249 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13250 referencing REG, it is dead. If we hit a SET referencing REG, it is
13251 live. Otherwise, see if it is live or dead at the start of the basic
13252 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13253 must be assumed to be always live. */
13256 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13261 /* Set variables for reg_dead_at_p_1. */
13262 reg_dead_regno
= REGNO (reg
);
13263 reg_dead_endregno
= END_REGNO (reg
);
13267 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13268 we allow the machine description to decide whether use-and-clobber
13269 patterns are OK. */
13270 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13272 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13273 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13277 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13278 beginning of basic block. */
13279 block
= BLOCK_FOR_INSN (insn
);
13284 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13287 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13289 return reg_dead_flag
== 1 ? 1 : 0;
13291 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13295 if (insn
== BB_HEAD (block
))
13298 insn
= PREV_INSN (insn
);
13301 /* Look at live-in sets for the basic block that we were in. */
13302 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13303 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13309 /* Note hard registers in X that are used. */
13312 mark_used_regs_combine (rtx x
)
13314 RTX_CODE code
= GET_CODE (x
);
13315 unsigned int regno
;
13326 case ADDR_DIFF_VEC
:
13328 /* CC0 must die in the insn after it is set, so we don't need to take
13329 special note of it here. */
13334 /* If we are clobbering a MEM, mark any hard registers inside the
13335 address as used. */
13336 if (MEM_P (XEXP (x
, 0)))
13337 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13342 /* A hard reg in a wide mode may really be multiple registers.
13343 If so, mark all of them just like the first. */
13344 if (regno
< FIRST_PSEUDO_REGISTER
)
13346 /* None of this applies to the stack, frame or arg pointers. */
13347 if (regno
== STACK_POINTER_REGNUM
13348 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13349 || regno
== HARD_FRAME_POINTER_REGNUM
13351 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13352 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13353 || regno
== FRAME_POINTER_REGNUM
)
13356 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13362 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13364 rtx testreg
= SET_DEST (x
);
13366 while (GET_CODE (testreg
) == SUBREG
13367 || GET_CODE (testreg
) == ZERO_EXTRACT
13368 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13369 testreg
= XEXP (testreg
, 0);
13371 if (MEM_P (testreg
))
13372 mark_used_regs_combine (XEXP (testreg
, 0));
13374 mark_used_regs_combine (SET_SRC (x
));
13382 /* Recursively scan the operands of this expression. */
13385 const char *fmt
= GET_RTX_FORMAT (code
);
13387 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13390 mark_used_regs_combine (XEXP (x
, i
));
13391 else if (fmt
[i
] == 'E')
13395 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13396 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13402 /* Remove register number REGNO from the dead registers list of INSN.
13404 Return the note used to record the death, if there was one. */
13407 remove_death (unsigned int regno
, rtx_insn
*insn
)
13409 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13412 remove_note (insn
, note
);
13417 /* For each register (hardware or pseudo) used within expression X, if its
13418 death is in an instruction with luid between FROM_LUID (inclusive) and
13419 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13420 list headed by PNOTES.
13422 That said, don't move registers killed by maybe_kill_insn.
13424 This is done when X is being merged by combination into TO_INSN. These
13425 notes will then be distributed as needed. */
13428 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13433 enum rtx_code code
= GET_CODE (x
);
13437 unsigned int regno
= REGNO (x
);
13438 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13440 /* Don't move the register if it gets killed in between from and to. */
13441 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13442 && ! reg_referenced_p (x
, maybe_kill_insn
))
13446 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13447 && DF_INSN_LUID (where_dead
) >= from_luid
13448 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13450 rtx note
= remove_death (regno
, where_dead
);
13452 /* It is possible for the call above to return 0. This can occur
13453 when last_death points to I2 or I1 that we combined with.
13454 In that case make a new note.
13456 We must also check for the case where X is a hard register
13457 and NOTE is a death note for a range of hard registers
13458 including X. In that case, we must put REG_DEAD notes for
13459 the remaining registers in place of NOTE. */
13461 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13462 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13463 > GET_MODE_SIZE (GET_MODE (x
))))
13465 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13466 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13467 unsigned int ourend
= END_REGNO (x
);
13470 for (i
= deadregno
; i
< deadend
; i
++)
13471 if (i
< regno
|| i
>= ourend
)
13472 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13475 /* If we didn't find any note, or if we found a REG_DEAD note that
13476 covers only part of the given reg, and we have a multi-reg hard
13477 register, then to be safe we must check for REG_DEAD notes
13478 for each register other than the first. They could have
13479 their own REG_DEAD notes lying around. */
13480 else if ((note
== 0
13482 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13483 < GET_MODE_SIZE (GET_MODE (x
)))))
13484 && regno
< FIRST_PSEUDO_REGISTER
13485 && REG_NREGS (x
) > 1)
13487 unsigned int ourend
= END_REGNO (x
);
13488 unsigned int i
, offset
;
13492 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13496 for (i
= regno
+ offset
; i
< ourend
; i
++)
13497 move_deaths (regno_reg_rtx
[i
],
13498 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13501 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13503 XEXP (note
, 1) = *pnotes
;
13507 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13513 else if (GET_CODE (x
) == SET
)
13515 rtx dest
= SET_DEST (x
);
13517 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13519 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13520 that accesses one word of a multi-word item, some
13521 piece of everything register in the expression is used by
13522 this insn, so remove any old death. */
13523 /* ??? So why do we test for equality of the sizes? */
13525 if (GET_CODE (dest
) == ZERO_EXTRACT
13526 || GET_CODE (dest
) == STRICT_LOW_PART
13527 || (GET_CODE (dest
) == SUBREG
13528 && (((GET_MODE_SIZE (GET_MODE (dest
))
13529 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13530 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13531 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13533 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13537 /* If this is some other SUBREG, we know it replaces the entire
13538 value, so use that as the destination. */
13539 if (GET_CODE (dest
) == SUBREG
)
13540 dest
= SUBREG_REG (dest
);
13542 /* If this is a MEM, adjust deaths of anything used in the address.
13543 For a REG (the only other possibility), the entire value is
13544 being replaced so the old value is not used in this insn. */
13547 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13552 else if (GET_CODE (x
) == CLOBBER
)
13555 len
= GET_RTX_LENGTH (code
);
13556 fmt
= GET_RTX_FORMAT (code
);
13558 for (i
= 0; i
< len
; i
++)
13563 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13564 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13567 else if (fmt
[i
] == 'e')
13568 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13572 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13573 pattern of an insn. X must be a REG. */
13576 reg_bitfield_target_p (rtx x
, rtx body
)
13580 if (GET_CODE (body
) == SET
)
13582 rtx dest
= SET_DEST (body
);
13584 unsigned int regno
, tregno
, endregno
, endtregno
;
13586 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13587 target
= XEXP (dest
, 0);
13588 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13589 target
= SUBREG_REG (XEXP (dest
, 0));
13593 if (GET_CODE (target
) == SUBREG
)
13594 target
= SUBREG_REG (target
);
13596 if (!REG_P (target
))
13599 tregno
= REGNO (target
), regno
= REGNO (x
);
13600 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13601 return target
== x
;
13603 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13604 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13606 return endregno
> tregno
&& regno
< endtregno
;
13609 else if (GET_CODE (body
) == PARALLEL
)
13610 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13611 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13617 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13618 as appropriate. I3 and I2 are the insns resulting from the combination
13619 insns including FROM (I2 may be zero).
13621 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13622 not need REG_DEAD notes because they are being substituted for. This
13623 saves searching in the most common cases.
13625 Each note in the list is either ignored or placed on some insns, depending
13626 on the type of note. */
13629 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13630 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13632 rtx note
, next_note
;
13634 rtx_insn
*tem_insn
;
13636 for (note
= notes
; note
; note
= next_note
)
13638 rtx_insn
*place
= 0, *place2
= 0;
13640 next_note
= XEXP (note
, 1);
13641 switch (REG_NOTE_KIND (note
))
13645 /* Doesn't matter much where we put this, as long as it's somewhere.
13646 It is preferable to keep these notes on branches, which is most
13647 likely to be i3. */
13651 case REG_NON_LOCAL_GOTO
:
13656 gcc_assert (i2
&& JUMP_P (i2
));
13661 case REG_EH_REGION
:
13662 /* These notes must remain with the call or trapping instruction. */
13665 else if (i2
&& CALL_P (i2
))
13669 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13670 if (may_trap_p (i3
))
13672 else if (i2
&& may_trap_p (i2
))
13674 /* ??? Otherwise assume we've combined things such that we
13675 can now prove that the instructions can't trap. Drop the
13676 note in this case. */
13680 case REG_ARGS_SIZE
:
13681 /* ??? How to distribute between i3-i1. Assume i3 contains the
13682 entire adjustment. Assert i3 contains at least some adjust. */
13683 if (!noop_move_p (i3
))
13685 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13686 /* fixup_args_size_notes looks at REG_NORETURN note,
13687 so ensure the note is placed there first. */
13691 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13692 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13696 XEXP (n
, 1) = REG_NOTES (i3
);
13697 REG_NOTES (i3
) = n
;
13701 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13702 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13703 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13704 gcc_assert (old_size
!= args_size
13706 && !ACCUMULATE_OUTGOING_ARGS
13707 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13714 case REG_CALL_DECL
:
13715 /* These notes must remain with the call. It should not be
13716 possible for both I2 and I3 to be a call. */
13721 gcc_assert (i2
&& CALL_P (i2
));
13727 /* Any clobbers for i3 may still exist, and so we must process
13728 REG_UNUSED notes from that insn.
13730 Any clobbers from i2 or i1 can only exist if they were added by
13731 recog_for_combine. In that case, recog_for_combine created the
13732 necessary REG_UNUSED notes. Trying to keep any original
13733 REG_UNUSED notes from these insns can cause incorrect output
13734 if it is for the same register as the original i3 dest.
13735 In that case, we will notice that the register is set in i3,
13736 and then add a REG_UNUSED note for the destination of i3, which
13737 is wrong. However, it is possible to have REG_UNUSED notes from
13738 i2 or i1 for register which were both used and clobbered, so
13739 we keep notes from i2 or i1 if they will turn into REG_DEAD
13742 /* If this register is set or clobbered in I3, put the note there
13743 unless there is one already. */
13744 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13746 if (from_insn
!= i3
)
13749 if (! (REG_P (XEXP (note
, 0))
13750 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13751 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13754 /* Otherwise, if this register is used by I3, then this register
13755 now dies here, so we must put a REG_DEAD note here unless there
13757 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13758 && ! (REG_P (XEXP (note
, 0))
13759 ? find_regno_note (i3
, REG_DEAD
,
13760 REGNO (XEXP (note
, 0)))
13761 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13763 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13771 /* These notes say something about results of an insn. We can
13772 only support them if they used to be on I3 in which case they
13773 remain on I3. Otherwise they are ignored.
13775 If the note refers to an expression that is not a constant, we
13776 must also ignore the note since we cannot tell whether the
13777 equivalence is still true. It might be possible to do
13778 slightly better than this (we only have a problem if I2DEST
13779 or I1DEST is present in the expression), but it doesn't
13780 seem worth the trouble. */
13782 if (from_insn
== i3
13783 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13788 /* These notes say something about how a register is used. They must
13789 be present on any use of the register in I2 or I3. */
13790 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13793 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13802 case REG_LABEL_TARGET
:
13803 case REG_LABEL_OPERAND
:
13804 /* This can show up in several ways -- either directly in the
13805 pattern, or hidden off in the constant pool with (or without?)
13806 a REG_EQUAL note. */
13807 /* ??? Ignore the without-reg_equal-note problem for now. */
13808 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13809 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13810 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13811 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13815 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13816 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13817 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13818 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13826 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13827 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13829 if (place
&& JUMP_P (place
)
13830 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13831 && (JUMP_LABEL (place
) == NULL
13832 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13834 rtx label
= JUMP_LABEL (place
);
13837 JUMP_LABEL (place
) = XEXP (note
, 0);
13838 else if (LABEL_P (label
))
13839 LABEL_NUSES (label
)--;
13842 if (place2
&& JUMP_P (place2
)
13843 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13844 && (JUMP_LABEL (place2
) == NULL
13845 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13847 rtx label
= JUMP_LABEL (place2
);
13850 JUMP_LABEL (place2
) = XEXP (note
, 0);
13851 else if (LABEL_P (label
))
13852 LABEL_NUSES (label
)--;
13858 /* This note says something about the value of a register prior
13859 to the execution of an insn. It is too much trouble to see
13860 if the note is still correct in all situations. It is better
13861 to simply delete it. */
13865 /* If we replaced the right hand side of FROM_INSN with a
13866 REG_EQUAL note, the original use of the dying register
13867 will not have been combined into I3 and I2. In such cases,
13868 FROM_INSN is guaranteed to be the first of the combined
13869 instructions, so we simply need to search back before
13870 FROM_INSN for the previous use or set of this register,
13871 then alter the notes there appropriately.
13873 If the register is used as an input in I3, it dies there.
13874 Similarly for I2, if it is nonzero and adjacent to I3.
13876 If the register is not used as an input in either I3 or I2
13877 and it is not one of the registers we were supposed to eliminate,
13878 there are two possibilities. We might have a non-adjacent I2
13879 or we might have somehow eliminated an additional register
13880 from a computation. For example, we might have had A & B where
13881 we discover that B will always be zero. In this case we will
13882 eliminate the reference to A.
13884 In both cases, we must search to see if we can find a previous
13885 use of A and put the death note there. */
13888 && from_insn
== i2mod
13889 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13890 tem_insn
= from_insn
;
13894 && CALL_P (from_insn
)
13895 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13897 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13899 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13900 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13902 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13904 && reg_overlap_mentioned_p (XEXP (note
, 0),
13906 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13907 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13910 /* If the new I2 sets the same register that is marked dead
13911 in the note, the note now should not be put on I2, as the
13912 note refers to a previous incarnation of the reg. */
13913 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
13919 basic_block bb
= this_basic_block
;
13921 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13923 if (!NONDEBUG_INSN_P (tem_insn
))
13925 if (tem_insn
== BB_HEAD (bb
))
13930 /* If the register is being set at TEM_INSN, see if that is all
13931 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13932 into a REG_UNUSED note instead. Don't delete sets to
13933 global register vars. */
13934 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13935 || !global_regs
[REGNO (XEXP (note
, 0))])
13936 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13938 rtx set
= single_set (tem_insn
);
13939 rtx inner_dest
= 0;
13940 rtx_insn
*cc0_setter
= NULL
;
13943 for (inner_dest
= SET_DEST (set
);
13944 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13945 || GET_CODE (inner_dest
) == SUBREG
13946 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13947 inner_dest
= XEXP (inner_dest
, 0))
13950 /* Verify that it was the set, and not a clobber that
13951 modified the register.
13953 CC0 targets must be careful to maintain setter/user
13954 pairs. If we cannot delete the setter due to side
13955 effects, mark the user with an UNUSED note instead
13958 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13959 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13961 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13962 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13963 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13967 /* Move the notes and links of TEM_INSN elsewhere.
13968 This might delete other dead insns recursively.
13969 First set the pattern to something that won't use
13971 rtx old_notes
= REG_NOTES (tem_insn
);
13973 PATTERN (tem_insn
) = pc_rtx
;
13974 REG_NOTES (tem_insn
) = NULL
;
13976 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13977 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13978 distribute_links (LOG_LINKS (tem_insn
));
13980 SET_INSN_DELETED (tem_insn
);
13981 if (tem_insn
== i2
)
13984 /* Delete the setter too. */
13987 PATTERN (cc0_setter
) = pc_rtx
;
13988 old_notes
= REG_NOTES (cc0_setter
);
13989 REG_NOTES (cc0_setter
) = NULL
;
13991 distribute_notes (old_notes
, cc0_setter
,
13993 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13994 distribute_links (LOG_LINKS (cc0_setter
));
13996 SET_INSN_DELETED (cc0_setter
);
13997 if (cc0_setter
== i2
)
14003 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14005 /* If there isn't already a REG_UNUSED note, put one
14006 here. Do not place a REG_DEAD note, even if
14007 the register is also used here; that would not
14008 match the algorithm used in lifetime analysis
14009 and can cause the consistency check in the
14010 scheduler to fail. */
14011 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14012 REGNO (XEXP (note
, 0))))
14017 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14018 || (CALL_P (tem_insn
)
14019 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14023 /* If we are doing a 3->2 combination, and we have a
14024 register which formerly died in i3 and was not used
14025 by i2, which now no longer dies in i3 and is used in
14026 i2 but does not die in i2, and place is between i2
14027 and i3, then we may need to move a link from place to
14029 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14031 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14032 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14034 struct insn_link
*links
= LOG_LINKS (place
);
14035 LOG_LINKS (place
) = NULL
;
14036 distribute_links (links
);
14041 if (tem_insn
== BB_HEAD (bb
))
14047 /* If the register is set or already dead at PLACE, we needn't do
14048 anything with this note if it is still a REG_DEAD note.
14049 We check here if it is set at all, not if is it totally replaced,
14050 which is what `dead_or_set_p' checks, so also check for it being
14053 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14055 unsigned int regno
= REGNO (XEXP (note
, 0));
14056 reg_stat_type
*rsp
= ®_stat
[regno
];
14058 if (dead_or_set_p (place
, XEXP (note
, 0))
14059 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14061 /* Unless the register previously died in PLACE, clear
14062 last_death. [I no longer understand why this is
14064 if (rsp
->last_death
!= place
)
14065 rsp
->last_death
= 0;
14069 rsp
->last_death
= place
;
14071 /* If this is a death note for a hard reg that is occupying
14072 multiple registers, ensure that we are still using all
14073 parts of the object. If we find a piece of the object
14074 that is unused, we must arrange for an appropriate REG_DEAD
14075 note to be added for it. However, we can't just emit a USE
14076 and tag the note to it, since the register might actually
14077 be dead; so we recourse, and the recursive call then finds
14078 the previous insn that used this register. */
14080 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14082 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14083 bool all_used
= true;
14086 for (i
= regno
; i
< endregno
; i
++)
14087 if ((! refers_to_regno_p (i
, PATTERN (place
))
14088 && ! find_regno_fusage (place
, USE
, i
))
14089 || dead_or_set_regno_p (place
, i
))
14097 /* Put only REG_DEAD notes for pieces that are
14098 not already dead or set. */
14100 for (i
= regno
; i
< endregno
;
14101 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14103 rtx piece
= regno_reg_rtx
[i
];
14104 basic_block bb
= this_basic_block
;
14106 if (! dead_or_set_p (place
, piece
)
14107 && ! reg_bitfield_target_p (piece
,
14110 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14113 distribute_notes (new_note
, place
, place
,
14114 NULL
, NULL_RTX
, NULL_RTX
,
14117 else if (! refers_to_regno_p (i
, PATTERN (place
))
14118 && ! find_regno_fusage (place
, USE
, i
))
14119 for (tem_insn
= PREV_INSN (place
); ;
14120 tem_insn
= PREV_INSN (tem_insn
))
14122 if (!NONDEBUG_INSN_P (tem_insn
))
14124 if (tem_insn
== BB_HEAD (bb
))
14128 if (dead_or_set_p (tem_insn
, piece
)
14129 || reg_bitfield_target_p (piece
,
14130 PATTERN (tem_insn
)))
14132 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14145 /* Any other notes should not be present at this point in the
14147 gcc_unreachable ();
14152 XEXP (note
, 1) = REG_NOTES (place
);
14153 REG_NOTES (place
) = note
;
14157 add_shallow_copy_of_reg_note (place2
, note
);
14161 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14162 I3, I2, and I1 to new locations. This is also called to add a link
14163 pointing at I3 when I3's destination is changed. */
14166 distribute_links (struct insn_link
*links
)
14168 struct insn_link
*link
, *next_link
;
14170 for (link
= links
; link
; link
= next_link
)
14172 rtx_insn
*place
= 0;
14176 next_link
= link
->next
;
14178 /* If the insn that this link points to is a NOTE, ignore it. */
14179 if (NOTE_P (link
->insn
))
14183 rtx pat
= PATTERN (link
->insn
);
14184 if (GET_CODE (pat
) == SET
)
14186 else if (GET_CODE (pat
) == PARALLEL
)
14189 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14191 set
= XVECEXP (pat
, 0, i
);
14192 if (GET_CODE (set
) != SET
)
14195 reg
= SET_DEST (set
);
14196 while (GET_CODE (reg
) == ZERO_EXTRACT
14197 || GET_CODE (reg
) == STRICT_LOW_PART
14198 || GET_CODE (reg
) == SUBREG
)
14199 reg
= XEXP (reg
, 0);
14204 if (REGNO (reg
) == link
->regno
)
14207 if (i
== XVECLEN (pat
, 0))
14213 reg
= SET_DEST (set
);
14215 while (GET_CODE (reg
) == ZERO_EXTRACT
14216 || GET_CODE (reg
) == STRICT_LOW_PART
14217 || GET_CODE (reg
) == SUBREG
)
14218 reg
= XEXP (reg
, 0);
14220 /* A LOG_LINK is defined as being placed on the first insn that uses
14221 a register and points to the insn that sets the register. Start
14222 searching at the next insn after the target of the link and stop
14223 when we reach a set of the register or the end of the basic block.
14225 Note that this correctly handles the link that used to point from
14226 I3 to I2. Also note that not much searching is typically done here
14227 since most links don't point very far away. */
14229 for (insn
= NEXT_INSN (link
->insn
);
14230 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14231 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14232 insn
= NEXT_INSN (insn
))
14233 if (DEBUG_INSN_P (insn
))
14235 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14237 if (reg_referenced_p (reg
, PATTERN (insn
)))
14241 else if (CALL_P (insn
)
14242 && find_reg_fusage (insn
, USE
, reg
))
14247 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14250 /* If we found a place to put the link, place it there unless there
14251 is already a link to the same insn as LINK at that point. */
14255 struct insn_link
*link2
;
14257 FOR_EACH_LOG_LINK (link2
, place
)
14258 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14263 link
->next
= LOG_LINKS (place
);
14264 LOG_LINKS (place
) = link
;
14266 /* Set added_links_insn to the earliest insn we added a
14268 if (added_links_insn
== 0
14269 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14270 added_links_insn
= place
;
14276 /* Check for any register or memory mentioned in EQUIV that is not
14277 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14278 of EXPR where some registers may have been replaced by constants. */
14281 unmentioned_reg_p (rtx equiv
, rtx expr
)
14283 subrtx_iterator::array_type array
;
14284 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14286 const_rtx x
= *iter
;
14287 if ((REG_P (x
) || MEM_P (x
))
14288 && !reg_mentioned_p (x
, expr
))
14294 DEBUG_FUNCTION
void
14295 dump_combine_stats (FILE *file
)
14299 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14300 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14304 dump_combine_total_stats (FILE *file
)
14308 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14309 total_attempts
, total_merges
, total_extras
, total_successes
);
14312 /* Try combining insns through substitution. */
14313 static unsigned int
14314 rest_of_handle_combine (void)
14316 int rebuild_jump_labels_after_combine
;
14318 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14319 df_note_add_problem ();
14322 regstat_init_n_sets_and_refs ();
14323 reg_n_sets_max
= max_reg_num ();
14325 rebuild_jump_labels_after_combine
14326 = combine_instructions (get_insns (), max_reg_num ());
14328 /* Combining insns may have turned an indirect jump into a
14329 direct jump. Rebuild the JUMP_LABEL fields of jumping
14331 if (rebuild_jump_labels_after_combine
)
14333 timevar_push (TV_JUMP
);
14334 rebuild_jump_labels (get_insns ());
14336 timevar_pop (TV_JUMP
);
14339 regstat_free_n_sets_and_refs ();
14345 const pass_data pass_data_combine
=
14347 RTL_PASS
, /* type */
14348 "combine", /* name */
14349 OPTGROUP_NONE
, /* optinfo_flags */
14350 TV_COMBINE
, /* tv_id */
14351 PROP_cfglayout
, /* properties_required */
14352 0, /* properties_provided */
14353 0, /* properties_destroyed */
14354 0, /* todo_flags_start */
14355 TODO_df_finish
, /* todo_flags_finish */
14358 class pass_combine
: public rtl_opt_pass
14361 pass_combine (gcc::context
*ctxt
)
14362 : rtl_opt_pass (pass_data_combine
, ctxt
)
14365 /* opt_pass methods: */
14366 virtual bool gate (function
*) { return (optimize
> 0); }
14367 virtual unsigned int execute (function
*)
14369 return rest_of_handle_combine ();
14372 }; // class pass_combine
14374 } // anon namespace
14377 make_pass_combine (gcc::context
*ctxt
)
14379 return new pass_combine (ctxt
);