PR c/53037
[official-gcc.git] / gcc / recog.c
blob4f11c579137cfbca9533a8b8159055ec5d9191e0
1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "backend.h"
25 #include "target.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "cfghooks.h"
29 #include "df.h"
30 #include "memmodel.h"
31 #include "tm_p.h"
32 #include "insn-config.h"
33 #include "regs.h"
34 #include "emit-rtl.h"
35 #include "recog.h"
36 #include "insn-attr.h"
37 #include "addresses.h"
38 #include "cfgrtl.h"
39 #include "cfgbuild.h"
40 #include "cfgcleanup.h"
41 #include "reload.h"
42 #include "tree-pass.h"
44 #ifndef STACK_POP_CODE
45 #if STACK_GROWS_DOWNWARD
46 #define STACK_POP_CODE POST_INC
47 #else
48 #define STACK_POP_CODE POST_DEC
49 #endif
50 #endif
52 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool);
53 static void validate_replace_src_1 (rtx *, void *);
54 static rtx_insn *split_insn (rtx_insn *);
56 struct target_recog default_target_recog;
57 #if SWITCHABLE_TARGET
58 struct target_recog *this_target_recog = &default_target_recog;
59 #endif
61 /* Nonzero means allow operands to be volatile.
62 This should be 0 if you are generating rtl, such as if you are calling
63 the functions in optabs.c and expmed.c (most of the time).
64 This should be 1 if all valid insns need to be recognized,
65 such as in reginfo.c and final.c and reload.c.
67 init_recog and init_recog_no_volatile are responsible for setting this. */
69 int volatile_ok;
71 struct recog_data_d recog_data;
73 /* Contains a vector of operand_alternative structures, such that
74 operand OP of alternative A is at index A * n_operands + OP.
75 Set up by preprocess_constraints. */
76 const operand_alternative *recog_op_alt;
78 /* Used to provide recog_op_alt for asms. */
79 static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS
80 * MAX_RECOG_ALTERNATIVES];
82 /* On return from `constrain_operands', indicate which alternative
83 was satisfied. */
85 int which_alternative;
87 /* Nonzero after end of reload pass.
88 Set to 1 or 0 by toplev.c.
89 Controls the significance of (SUBREG (MEM)). */
91 int reload_completed;
93 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
94 int epilogue_completed;
96 /* Initialize data used by the function `recog'.
97 This must be called once in the compilation of a function
98 before any insn recognition may be done in the function. */
100 void
101 init_recog_no_volatile (void)
103 volatile_ok = 0;
106 void
107 init_recog (void)
109 volatile_ok = 1;
113 /* Return true if labels in asm operands BODY are LABEL_REFs. */
115 static bool
116 asm_labels_ok (rtx body)
118 rtx asmop;
119 int i;
121 asmop = extract_asm_operands (body);
122 if (asmop == NULL_RTX)
123 return true;
125 for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
126 if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
127 return false;
129 return true;
132 /* Check that X is an insn-body for an `asm' with operands
133 and that the operands mentioned in it are legitimate. */
136 check_asm_operands (rtx x)
138 int noperands;
139 rtx *operands;
140 const char **constraints;
141 int i;
143 if (!asm_labels_ok (x))
144 return 0;
146 /* Post-reload, be more strict with things. */
147 if (reload_completed)
149 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
150 rtx_insn *insn = make_insn_raw (x);
151 extract_insn (insn);
152 constrain_operands (1, get_enabled_alternatives (insn));
153 return which_alternative >= 0;
156 noperands = asm_noperands (x);
157 if (noperands < 0)
158 return 0;
159 if (noperands == 0)
160 return 1;
162 operands = XALLOCAVEC (rtx, noperands);
163 constraints = XALLOCAVEC (const char *, noperands);
165 decode_asm_operands (x, operands, NULL, constraints, NULL, NULL);
167 for (i = 0; i < noperands; i++)
169 const char *c = constraints[i];
170 if (c[0] == '%')
171 c++;
172 if (! asm_operand_ok (operands[i], c, constraints))
173 return 0;
176 return 1;
179 /* Static data for the next two routines. */
181 struct change_t
183 rtx object;
184 int old_code;
185 bool unshare;
186 rtx *loc;
187 rtx old;
190 static change_t *changes;
191 static int changes_allocated;
193 static int num_changes = 0;
195 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
196 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
197 the change is simply made.
199 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
200 will be called with the address and mode as parameters. If OBJECT is
201 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
202 the change in place.
204 IN_GROUP is nonzero if this is part of a group of changes that must be
205 performed as a group. In that case, the changes will be stored. The
206 function `apply_change_group' will validate and apply the changes.
208 If IN_GROUP is zero, this is a single change. Try to recognize the insn
209 or validate the memory reference with the change applied. If the result
210 is not valid for the machine, suppress the change and return zero.
211 Otherwise, perform the change and return 1. */
213 static bool
214 validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, bool unshare)
216 rtx old = *loc;
218 if (old == new_rtx || rtx_equal_p (old, new_rtx))
219 return 1;
221 gcc_assert (in_group != 0 || num_changes == 0);
223 *loc = new_rtx;
225 /* Save the information describing this change. */
226 if (num_changes >= changes_allocated)
228 if (changes_allocated == 0)
229 /* This value allows for repeated substitutions inside complex
230 indexed addresses, or changes in up to 5 insns. */
231 changes_allocated = MAX_RECOG_OPERANDS * 5;
232 else
233 changes_allocated *= 2;
235 changes = XRESIZEVEC (change_t, changes, changes_allocated);
238 changes[num_changes].object = object;
239 changes[num_changes].loc = loc;
240 changes[num_changes].old = old;
241 changes[num_changes].unshare = unshare;
243 if (object && !MEM_P (object))
245 /* Set INSN_CODE to force rerecognition of insn. Save old code in
246 case invalid. */
247 changes[num_changes].old_code = INSN_CODE (object);
248 INSN_CODE (object) = -1;
251 num_changes++;
253 /* If we are making a group of changes, return 1. Otherwise, validate the
254 change group we made. */
256 if (in_group)
257 return 1;
258 else
259 return apply_change_group ();
262 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
263 UNSHARE to false. */
265 bool
266 validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
268 return validate_change_1 (object, loc, new_rtx, in_group, false);
271 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
272 UNSHARE to true. */
274 bool
275 validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
277 return validate_change_1 (object, loc, new_rtx, in_group, true);
281 /* Keep X canonicalized if some changes have made it non-canonical; only
282 modifies the operands of X, not (for example) its code. Simplifications
283 are not the job of this routine.
285 Return true if anything was changed. */
286 bool
287 canonicalize_change_group (rtx_insn *insn, rtx x)
289 if (COMMUTATIVE_P (x)
290 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
292 /* Oops, the caller has made X no longer canonical.
293 Let's redo the changes in the correct order. */
294 rtx tem = XEXP (x, 0);
295 validate_unshare_change (insn, &XEXP (x, 0), XEXP (x, 1), 1);
296 validate_unshare_change (insn, &XEXP (x, 1), tem, 1);
297 return true;
299 else
300 return false;
304 /* This subroutine of apply_change_group verifies whether the changes to INSN
305 were valid; i.e. whether INSN can still be recognized.
307 If IN_GROUP is true clobbers which have to be added in order to
308 match the instructions will be added to the current change group.
309 Otherwise the changes will take effect immediately. */
312 insn_invalid_p (rtx_insn *insn, bool in_group)
314 rtx pat = PATTERN (insn);
315 int num_clobbers = 0;
316 /* If we are before reload and the pattern is a SET, see if we can add
317 clobbers. */
318 int icode = recog (pat, insn,
319 (GET_CODE (pat) == SET
320 && ! reload_completed
321 && ! reload_in_progress)
322 ? &num_clobbers : 0);
323 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
326 /* If this is an asm and the operand aren't legal, then fail. Likewise if
327 this is not an asm and the insn wasn't recognized. */
328 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
329 || (!is_asm && icode < 0))
330 return 1;
332 /* If we have to add CLOBBERs, fail if we have to add ones that reference
333 hard registers since our callers can't know if they are live or not.
334 Otherwise, add them. */
335 if (num_clobbers > 0)
337 rtx newpat;
339 if (added_clobbers_hard_reg_p (icode))
340 return 1;
342 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
343 XVECEXP (newpat, 0, 0) = pat;
344 add_clobbers (newpat, icode);
345 if (in_group)
346 validate_change (insn, &PATTERN (insn), newpat, 1);
347 else
348 PATTERN (insn) = pat = newpat;
351 /* After reload, verify that all constraints are satisfied. */
352 if (reload_completed)
354 extract_insn (insn);
356 if (! constrain_operands (1, get_preferred_alternatives (insn)))
357 return 1;
360 INSN_CODE (insn) = icode;
361 return 0;
364 /* Return number of changes made and not validated yet. */
366 num_changes_pending (void)
368 return num_changes;
371 /* Tentatively apply the changes numbered NUM and up.
372 Return 1 if all changes are valid, zero otherwise. */
375 verify_changes (int num)
377 int i;
378 rtx last_validated = NULL_RTX;
380 /* The changes have been applied and all INSN_CODEs have been reset to force
381 rerecognition.
383 The changes are valid if we aren't given an object, or if we are
384 given a MEM and it still is a valid address, or if this is in insn
385 and it is recognized. In the latter case, if reload has completed,
386 we also require that the operands meet the constraints for
387 the insn. */
389 for (i = num; i < num_changes; i++)
391 rtx object = changes[i].object;
393 /* If there is no object to test or if it is the same as the one we
394 already tested, ignore it. */
395 if (object == 0 || object == last_validated)
396 continue;
398 if (MEM_P (object))
400 if (! memory_address_addr_space_p (GET_MODE (object),
401 XEXP (object, 0),
402 MEM_ADDR_SPACE (object)))
403 break;
405 else if (/* changes[i].old might be zero, e.g. when putting a
406 REG_FRAME_RELATED_EXPR into a previously empty list. */
407 changes[i].old
408 && REG_P (changes[i].old)
409 && asm_noperands (PATTERN (object)) > 0
410 && REG_EXPR (changes[i].old) != NULL_TREE
411 && HAS_DECL_ASSEMBLER_NAME_P (REG_EXPR (changes[i].old))
412 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old))
413 && DECL_REGISTER (REG_EXPR (changes[i].old)))
415 /* Don't allow changes of hard register operands to inline
416 assemblies if they have been defined as register asm ("x"). */
417 break;
419 else if (DEBUG_INSN_P (object))
420 continue;
421 else if (insn_invalid_p (as_a <rtx_insn *> (object), true))
423 rtx pat = PATTERN (object);
425 /* Perhaps we couldn't recognize the insn because there were
426 extra CLOBBERs at the end. If so, try to re-recognize
427 without the last CLOBBER (later iterations will cause each of
428 them to be eliminated, in turn). But don't do this if we
429 have an ASM_OPERAND. */
430 if (GET_CODE (pat) == PARALLEL
431 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
432 && asm_noperands (PATTERN (object)) < 0)
434 rtx newpat;
436 if (XVECLEN (pat, 0) == 2)
437 newpat = XVECEXP (pat, 0, 0);
438 else
440 int j;
442 newpat
443 = gen_rtx_PARALLEL (VOIDmode,
444 rtvec_alloc (XVECLEN (pat, 0) - 1));
445 for (j = 0; j < XVECLEN (newpat, 0); j++)
446 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
449 /* Add a new change to this group to replace the pattern
450 with this new pattern. Then consider this change
451 as having succeeded. The change we added will
452 cause the entire call to fail if things remain invalid.
454 Note that this can lose if a later change than the one
455 we are processing specified &XVECEXP (PATTERN (object), 0, X)
456 but this shouldn't occur. */
458 validate_change (object, &PATTERN (object), newpat, 1);
459 continue;
461 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER
462 || GET_CODE (pat) == VAR_LOCATION)
463 /* If this insn is a CLOBBER or USE, it is always valid, but is
464 never recognized. */
465 continue;
466 else
467 break;
469 last_validated = object;
472 return (i == num_changes);
475 /* A group of changes has previously been issued with validate_change
476 and verified with verify_changes. Call df_insn_rescan for each of
477 the insn changed and clear num_changes. */
479 void
480 confirm_change_group (void)
482 int i;
483 rtx last_object = NULL;
485 for (i = 0; i < num_changes; i++)
487 rtx object = changes[i].object;
489 if (changes[i].unshare)
490 *changes[i].loc = copy_rtx (*changes[i].loc);
492 /* Avoid unnecessary rescanning when multiple changes to same instruction
493 are made. */
494 if (object)
496 if (object != last_object && last_object && INSN_P (last_object))
497 df_insn_rescan (as_a <rtx_insn *> (last_object));
498 last_object = object;
502 if (last_object && INSN_P (last_object))
503 df_insn_rescan (as_a <rtx_insn *> (last_object));
504 num_changes = 0;
507 /* Apply a group of changes previously issued with `validate_change'.
508 If all changes are valid, call confirm_change_group and return 1,
509 otherwise, call cancel_changes and return 0. */
512 apply_change_group (void)
514 if (verify_changes (0))
516 confirm_change_group ();
517 return 1;
519 else
521 cancel_changes (0);
522 return 0;
527 /* Return the number of changes so far in the current group. */
530 num_validated_changes (void)
532 return num_changes;
535 /* Retract the changes numbered NUM and up. */
537 void
538 cancel_changes (int num)
540 int i;
542 /* Back out all the changes. Do this in the opposite order in which
543 they were made. */
544 for (i = num_changes - 1; i >= num; i--)
546 *changes[i].loc = changes[i].old;
547 if (changes[i].object && !MEM_P (changes[i].object))
548 INSN_CODE (changes[i].object) = changes[i].old_code;
550 num_changes = num;
553 /* Reduce conditional compilation elsewhere. */
554 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
555 rtx. */
557 static void
558 simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object,
559 machine_mode op0_mode)
561 rtx x = *loc;
562 enum rtx_code code = GET_CODE (x);
563 rtx new_rtx = NULL_RTX;
564 scalar_int_mode is_mode;
566 if (SWAPPABLE_OPERANDS_P (x)
567 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
569 validate_unshare_change (object, loc,
570 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? code
571 : swap_condition (code),
572 GET_MODE (x), XEXP (x, 1),
573 XEXP (x, 0)), 1);
574 x = *loc;
575 code = GET_CODE (x);
578 /* Canonicalize arithmetics with all constant operands. */
579 switch (GET_RTX_CLASS (code))
581 case RTX_UNARY:
582 if (CONSTANT_P (XEXP (x, 0)))
583 new_rtx = simplify_unary_operation (code, GET_MODE (x), XEXP (x, 0),
584 op0_mode);
585 break;
586 case RTX_COMM_ARITH:
587 case RTX_BIN_ARITH:
588 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
589 new_rtx = simplify_binary_operation (code, GET_MODE (x), XEXP (x, 0),
590 XEXP (x, 1));
591 break;
592 case RTX_COMPARE:
593 case RTX_COMM_COMPARE:
594 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1)))
595 new_rtx = simplify_relational_operation (code, GET_MODE (x), op0_mode,
596 XEXP (x, 0), XEXP (x, 1));
597 break;
598 default:
599 break;
601 if (new_rtx)
603 validate_change (object, loc, new_rtx, 1);
604 return;
607 switch (code)
609 case PLUS:
610 /* If we have a PLUS whose second operand is now a CONST_INT, use
611 simplify_gen_binary to try to simplify it.
612 ??? We may want later to remove this, once simplification is
613 separated from this function. */
614 if (CONST_INT_P (XEXP (x, 1)) && XEXP (x, 1) == to)
615 validate_change (object, loc,
616 simplify_gen_binary
617 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
618 break;
619 case MINUS:
620 if (CONST_SCALAR_INT_P (XEXP (x, 1)))
621 validate_change (object, loc,
622 simplify_gen_binary
623 (PLUS, GET_MODE (x), XEXP (x, 0),
624 simplify_gen_unary (NEG,
625 GET_MODE (x), XEXP (x, 1),
626 GET_MODE (x))), 1);
627 break;
628 case ZERO_EXTEND:
629 case SIGN_EXTEND:
630 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
632 new_rtx = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0),
633 op0_mode);
634 /* If any of the above failed, substitute in something that
635 we know won't be recognized. */
636 if (!new_rtx)
637 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
638 validate_change (object, loc, new_rtx, 1);
640 break;
641 case SUBREG:
642 /* All subregs possible to simplify should be simplified. */
643 new_rtx = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode,
644 SUBREG_BYTE (x));
646 /* Subregs of VOIDmode operands are incorrect. */
647 if (!new_rtx && GET_MODE (SUBREG_REG (x)) == VOIDmode)
648 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
649 if (new_rtx)
650 validate_change (object, loc, new_rtx, 1);
651 break;
652 case ZERO_EXTRACT:
653 case SIGN_EXTRACT:
654 /* If we are replacing a register with memory, try to change the memory
655 to be the mode required for memory in extract operations (this isn't
656 likely to be an insertion operation; if it was, nothing bad will
657 happen, we might just fail in some cases). */
659 if (MEM_P (XEXP (x, 0))
660 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &is_mode)
661 && CONST_INT_P (XEXP (x, 1))
662 && CONST_INT_P (XEXP (x, 2))
663 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0),
664 MEM_ADDR_SPACE (XEXP (x, 0)))
665 && !MEM_VOLATILE_P (XEXP (x, 0)))
667 int pos = INTVAL (XEXP (x, 2));
668 machine_mode new_mode = is_mode;
669 if (GET_CODE (x) == ZERO_EXTRACT && targetm.have_extzv ())
670 new_mode = insn_data[targetm.code_for_extzv].operand[1].mode;
671 else if (GET_CODE (x) == SIGN_EXTRACT && targetm.have_extv ())
672 new_mode = insn_data[targetm.code_for_extv].operand[1].mode;
673 scalar_int_mode wanted_mode = (new_mode == VOIDmode
674 ? word_mode
675 : as_a <scalar_int_mode> (new_mode));
677 /* If we have a narrower mode, we can do something. */
678 if (GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
680 int offset = pos / BITS_PER_UNIT;
681 rtx newmem;
683 /* If the bytes and bits are counted differently, we
684 must adjust the offset. */
685 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
686 offset =
687 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
688 offset);
690 gcc_assert (GET_MODE_PRECISION (wanted_mode)
691 == GET_MODE_BITSIZE (wanted_mode));
692 pos %= GET_MODE_BITSIZE (wanted_mode);
694 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
696 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
697 validate_change (object, &XEXP (x, 0), newmem, 1);
701 break;
703 default:
704 break;
708 /* Replace every occurrence of FROM in X with TO. Mark each change with
709 validate_change passing OBJECT. */
711 static void
712 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
713 bool simplify)
715 int i, j;
716 const char *fmt;
717 rtx x = *loc;
718 enum rtx_code code;
719 machine_mode op0_mode = VOIDmode;
720 int prev_changes = num_changes;
722 if (!x)
723 return;
725 code = GET_CODE (x);
726 fmt = GET_RTX_FORMAT (code);
727 if (fmt[0] == 'e')
728 op0_mode = GET_MODE (XEXP (x, 0));
730 /* X matches FROM if it is the same rtx or they are both referring to the
731 same register in the same mode. Avoid calling rtx_equal_p unless the
732 operands look similar. */
734 if (x == from
735 || (REG_P (x) && REG_P (from)
736 && GET_MODE (x) == GET_MODE (from)
737 && REGNO (x) == REGNO (from))
738 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
739 && rtx_equal_p (x, from)))
741 validate_unshare_change (object, loc, to, 1);
742 return;
745 /* Call ourself recursively to perform the replacements.
746 We must not replace inside already replaced expression, otherwise we
747 get infinite recursion for replacements like (reg X)->(subreg (reg X))
748 so we must special case shared ASM_OPERANDS. */
750 if (GET_CODE (x) == PARALLEL)
752 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
754 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET
755 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS)
757 /* Verify that operands are really shared. */
758 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))
759 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
760 (x, 0, j))));
761 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)),
762 from, to, object, simplify);
764 else
765 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object,
766 simplify);
769 else
770 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
772 if (fmt[i] == 'e')
773 validate_replace_rtx_1 (&XEXP (x, i), from, to, object, simplify);
774 else if (fmt[i] == 'E')
775 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
776 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object,
777 simplify);
780 /* If we didn't substitute, there is nothing more to do. */
781 if (num_changes == prev_changes)
782 return;
784 /* ??? The regmove is no more, so is this aberration still necessary? */
785 /* Allow substituted expression to have different mode. This is used by
786 regmove to change mode of pseudo register. */
787 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
788 op0_mode = GET_MODE (XEXP (x, 0));
790 /* Do changes needed to keep rtx consistent. Don't do any other
791 simplifications, as it is not our job. */
792 if (simplify)
793 simplify_while_replacing (loc, to, object, op0_mode);
796 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
797 with TO. After all changes have been made, validate by seeing
798 if INSN is still valid. */
801 validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
803 validate_replace_rtx_1 (loc, from, to, insn, true);
804 return apply_change_group ();
807 /* Try replacing every occurrence of FROM in INSN with TO. After all
808 changes have been made, validate by seeing if INSN is still valid. */
811 validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
813 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
814 return apply_change_group ();
817 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
818 is a part of INSN. After all changes have been made, validate by seeing if
819 INSN is still valid.
820 validate_replace_rtx (from, to, insn) is equivalent to
821 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
824 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
826 validate_replace_rtx_1 (where, from, to, insn, true);
827 return apply_change_group ();
830 /* Same as above, but do not simplify rtx afterwards. */
832 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
833 rtx_insn *insn)
835 validate_replace_rtx_1 (where, from, to, insn, false);
836 return apply_change_group ();
840 /* Try replacing every occurrence of FROM in INSN with TO. This also
841 will replace in REG_EQUAL and REG_EQUIV notes. */
843 void
844 validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn)
846 rtx note;
847 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
848 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
849 if (REG_NOTE_KIND (note) == REG_EQUAL
850 || REG_NOTE_KIND (note) == REG_EQUIV)
851 validate_replace_rtx_1 (&XEXP (note, 0), from, to, insn, true);
854 /* Function called by note_uses to replace used subexpressions. */
855 struct validate_replace_src_data
857 rtx from; /* Old RTX */
858 rtx to; /* New RTX */
859 rtx_insn *insn; /* Insn in which substitution is occurring. */
862 static void
863 validate_replace_src_1 (rtx *x, void *data)
865 struct validate_replace_src_data *d
866 = (struct validate_replace_src_data *) data;
868 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
871 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
872 SET_DESTs. */
874 void
875 validate_replace_src_group (rtx from, rtx to, rtx_insn *insn)
877 struct validate_replace_src_data d;
879 d.from = from;
880 d.to = to;
881 d.insn = insn;
882 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
885 /* Try simplify INSN.
886 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
887 pattern and return true if something was simplified. */
889 bool
890 validate_simplify_insn (rtx_insn *insn)
892 int i;
893 rtx pat = NULL;
894 rtx newpat = NULL;
896 pat = PATTERN (insn);
898 if (GET_CODE (pat) == SET)
900 newpat = simplify_rtx (SET_SRC (pat));
901 if (newpat && !rtx_equal_p (SET_SRC (pat), newpat))
902 validate_change (insn, &SET_SRC (pat), newpat, 1);
903 newpat = simplify_rtx (SET_DEST (pat));
904 if (newpat && !rtx_equal_p (SET_DEST (pat), newpat))
905 validate_change (insn, &SET_DEST (pat), newpat, 1);
907 else if (GET_CODE (pat) == PARALLEL)
908 for (i = 0; i < XVECLEN (pat, 0); i++)
910 rtx s = XVECEXP (pat, 0, i);
912 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
914 newpat = simplify_rtx (SET_SRC (s));
915 if (newpat && !rtx_equal_p (SET_SRC (s), newpat))
916 validate_change (insn, &SET_SRC (s), newpat, 1);
917 newpat = simplify_rtx (SET_DEST (s));
918 if (newpat && !rtx_equal_p (SET_DEST (s), newpat))
919 validate_change (insn, &SET_DEST (s), newpat, 1);
922 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
925 /* Return 1 if the insn using CC0 set by INSN does not contain
926 any ordered tests applied to the condition codes.
927 EQ and NE tests do not count. */
930 next_insn_tests_no_inequality (rtx_insn *insn)
932 rtx_insn *next = next_cc0_user (insn);
934 /* If there is no next insn, we have to take the conservative choice. */
935 if (next == 0)
936 return 0;
938 return (INSN_P (next)
939 && ! inequality_comparisons_p (PATTERN (next)));
942 /* Return 1 if OP is a valid general operand for machine mode MODE.
943 This is either a register reference, a memory reference,
944 or a constant. In the case of a memory reference, the address
945 is checked for general validity for the target machine.
947 Register and memory references must have mode MODE in order to be valid,
948 but some constants have no machine mode and are valid for any mode.
950 If MODE is VOIDmode, OP is checked for validity for whatever mode
951 it has.
953 The main use of this function is as a predicate in match_operand
954 expressions in the machine description. */
957 general_operand (rtx op, machine_mode mode)
959 enum rtx_code code = GET_CODE (op);
961 if (mode == VOIDmode)
962 mode = GET_MODE (op);
964 /* Don't accept CONST_INT or anything similar
965 if the caller wants something floating. */
966 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
967 && GET_MODE_CLASS (mode) != MODE_INT
968 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
969 return 0;
971 if (CONST_INT_P (op)
972 && mode != VOIDmode
973 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
974 return 0;
976 if (CONSTANT_P (op))
977 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
978 || mode == VOIDmode)
979 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
980 && targetm.legitimate_constant_p (mode == VOIDmode
981 ? GET_MODE (op)
982 : mode, op));
984 /* Except for certain constants with VOIDmode, already checked for,
985 OP's mode must match MODE if MODE specifies a mode. */
987 if (GET_MODE (op) != mode)
988 return 0;
990 if (code == SUBREG)
992 rtx sub = SUBREG_REG (op);
994 #ifdef INSN_SCHEDULING
995 /* On machines that have insn scheduling, we want all memory
996 reference to be explicit, so outlaw paradoxical SUBREGs.
997 However, we must allow them after reload so that they can
998 get cleaned up by cleanup_subreg_operands. */
999 if (!reload_completed && MEM_P (sub)
1000 && paradoxical_subreg_p (op))
1001 return 0;
1002 #endif
1003 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1004 may result in incorrect reference. We should simplify all valid
1005 subregs of MEM anyway. But allow this after reload because we
1006 might be called from cleanup_subreg_operands.
1008 ??? This is a kludge. */
1009 if (!reload_completed && SUBREG_BYTE (op) != 0
1010 && MEM_P (sub))
1011 return 0;
1013 if (REG_P (sub)
1014 && REGNO (sub) < FIRST_PSEUDO_REGISTER
1015 && !REG_CAN_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)
1016 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT
1017 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT
1018 /* LRA can generate some invalid SUBREGS just for matched
1019 operand reload presentation. LRA needs to treat them as
1020 valid. */
1021 && ! LRA_SUBREG_P (op))
1022 return 0;
1024 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1025 create such rtl, and we must reject it. */
1026 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))
1027 /* LRA can use subreg to store a floating point value in an
1028 integer mode. Although the floating point and the
1029 integer modes need the same number of hard registers, the
1030 size of floating point mode can be less than the integer
1031 mode. */
1032 && ! lra_in_progress
1033 && paradoxical_subreg_p (op))
1034 return 0;
1036 op = sub;
1037 code = GET_CODE (op);
1040 if (code == REG)
1041 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
1042 || in_hard_reg_set_p (operand_reg_set, GET_MODE (op), REGNO (op)));
1044 if (code == MEM)
1046 rtx y = XEXP (op, 0);
1048 if (! volatile_ok && MEM_VOLATILE_P (op))
1049 return 0;
1051 /* Use the mem's mode, since it will be reloaded thus. LRA can
1052 generate move insn with invalid addresses which is made valid
1053 and efficiently calculated by LRA through further numerous
1054 transformations. */
1055 if (lra_in_progress
1056 || memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op)))
1057 return 1;
1060 return 0;
1063 /* Return 1 if OP is a valid memory address for a memory reference
1064 of mode MODE.
1066 The main use of this function is as a predicate in match_operand
1067 expressions in the machine description. */
1070 address_operand (rtx op, machine_mode mode)
1072 return memory_address_p (mode, op);
1075 /* Return 1 if OP is a register reference of mode MODE.
1076 If MODE is VOIDmode, accept a register in any mode.
1078 The main use of this function is as a predicate in match_operand
1079 expressions in the machine description. */
1082 register_operand (rtx op, machine_mode mode)
1084 if (GET_CODE (op) == SUBREG)
1086 rtx sub = SUBREG_REG (op);
1088 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1089 because it is guaranteed to be reloaded into one.
1090 Just make sure the MEM is valid in itself.
1091 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1092 but currently it does result from (SUBREG (REG)...) where the
1093 reg went on the stack.) */
1094 if (!REG_P (sub) && (reload_completed || !MEM_P (sub)))
1095 return 0;
1097 else if (!REG_P (op))
1098 return 0;
1099 return general_operand (op, mode);
1102 /* Return 1 for a register in Pmode; ignore the tested mode. */
1105 pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
1107 return register_operand (op, Pmode);
1110 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1111 or a hard register. */
1114 scratch_operand (rtx op, machine_mode mode)
1116 if (GET_MODE (op) != mode && mode != VOIDmode)
1117 return 0;
1119 return (GET_CODE (op) == SCRATCH
1120 || (REG_P (op)
1121 && (lra_in_progress
1122 || (REGNO (op) < FIRST_PSEUDO_REGISTER
1123 && REGNO_REG_CLASS (REGNO (op)) != NO_REGS))));
1126 /* Return 1 if OP is a valid immediate operand for mode MODE.
1128 The main use of this function is as a predicate in match_operand
1129 expressions in the machine description. */
1132 immediate_operand (rtx op, machine_mode mode)
1134 /* Don't accept CONST_INT or anything similar
1135 if the caller wants something floating. */
1136 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1137 && GET_MODE_CLASS (mode) != MODE_INT
1138 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1139 return 0;
1141 if (CONST_INT_P (op)
1142 && mode != VOIDmode
1143 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1144 return 0;
1146 return (CONSTANT_P (op)
1147 && (GET_MODE (op) == mode || mode == VOIDmode
1148 || GET_MODE (op) == VOIDmode)
1149 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1150 && targetm.legitimate_constant_p (mode == VOIDmode
1151 ? GET_MODE (op)
1152 : mode, op));
1155 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1158 const_int_operand (rtx op, machine_mode mode)
1160 if (!CONST_INT_P (op))
1161 return 0;
1163 if (mode != VOIDmode
1164 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1165 return 0;
1167 return 1;
1170 #if TARGET_SUPPORTS_WIDE_INT
1171 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1172 of mode MODE. */
1174 const_scalar_int_operand (rtx op, machine_mode mode)
1176 if (!CONST_SCALAR_INT_P (op))
1177 return 0;
1179 if (CONST_INT_P (op))
1180 return const_int_operand (op, mode);
1182 if (mode != VOIDmode)
1184 scalar_int_mode int_mode = as_a <scalar_int_mode> (mode);
1185 int prec = GET_MODE_PRECISION (int_mode);
1186 int bitsize = GET_MODE_BITSIZE (int_mode);
1188 if (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT > bitsize)
1189 return 0;
1191 if (prec == bitsize)
1192 return 1;
1193 else
1195 /* Multiword partial int. */
1196 HOST_WIDE_INT x
1197 = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1);
1198 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT - 1)) == x);
1201 return 1;
1204 /* Returns 1 if OP is an operand that is a constant integer or constant
1205 floating-point number of MODE. */
1208 const_double_operand (rtx op, machine_mode mode)
1210 return (GET_CODE (op) == CONST_DOUBLE)
1211 && (GET_MODE (op) == mode || mode == VOIDmode);
1213 #else
1214 /* Returns 1 if OP is an operand that is a constant integer or constant
1215 floating-point number of MODE. */
1218 const_double_operand (rtx op, machine_mode mode)
1220 /* Don't accept CONST_INT or anything similar
1221 if the caller wants something floating. */
1222 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1223 && GET_MODE_CLASS (mode) != MODE_INT
1224 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1225 return 0;
1227 return ((CONST_DOUBLE_P (op) || CONST_INT_P (op))
1228 && (mode == VOIDmode || GET_MODE (op) == mode
1229 || GET_MODE (op) == VOIDmode));
1231 #endif
1232 /* Return 1 if OP is a general operand that is not an immediate
1233 operand of mode MODE. */
1236 nonimmediate_operand (rtx op, machine_mode mode)
1238 return (general_operand (op, mode) && ! CONSTANT_P (op));
1241 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1244 nonmemory_operand (rtx op, machine_mode mode)
1246 if (CONSTANT_P (op))
1247 return immediate_operand (op, mode);
1248 return register_operand (op, mode);
1251 /* Return 1 if OP is a valid operand that stands for pushing a
1252 value of mode MODE onto the stack.
1254 The main use of this function is as a predicate in match_operand
1255 expressions in the machine description. */
1258 push_operand (rtx op, machine_mode mode)
1260 unsigned int rounded_size = GET_MODE_SIZE (mode);
1262 #ifdef PUSH_ROUNDING
1263 rounded_size = PUSH_ROUNDING (rounded_size);
1264 #endif
1266 if (!MEM_P (op))
1267 return 0;
1269 if (mode != VOIDmode && GET_MODE (op) != mode)
1270 return 0;
1272 op = XEXP (op, 0);
1274 if (rounded_size == GET_MODE_SIZE (mode))
1276 if (GET_CODE (op) != STACK_PUSH_CODE)
1277 return 0;
1279 else
1281 if (GET_CODE (op) != PRE_MODIFY
1282 || GET_CODE (XEXP (op, 1)) != PLUS
1283 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1284 || !CONST_INT_P (XEXP (XEXP (op, 1), 1))
1285 || INTVAL (XEXP (XEXP (op, 1), 1))
1286 != ((STACK_GROWS_DOWNWARD ? -1 : 1) * (int) rounded_size))
1287 return 0;
1290 return XEXP (op, 0) == stack_pointer_rtx;
1293 /* Return 1 if OP is a valid operand that stands for popping a
1294 value of mode MODE off the stack.
1296 The main use of this function is as a predicate in match_operand
1297 expressions in the machine description. */
1300 pop_operand (rtx op, machine_mode mode)
1302 if (!MEM_P (op))
1303 return 0;
1305 if (mode != VOIDmode && GET_MODE (op) != mode)
1306 return 0;
1308 op = XEXP (op, 0);
1310 if (GET_CODE (op) != STACK_POP_CODE)
1311 return 0;
1313 return XEXP (op, 0) == stack_pointer_rtx;
1316 /* Return 1 if ADDR is a valid memory address
1317 for mode MODE in address space AS. */
1320 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED,
1321 rtx addr, addr_space_t as)
1323 #ifdef GO_IF_LEGITIMATE_ADDRESS
1324 gcc_assert (ADDR_SPACE_GENERIC_P (as));
1325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1326 return 0;
1328 win:
1329 return 1;
1330 #else
1331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1332 #endif
1335 /* Return 1 if OP is a valid memory reference with mode MODE,
1336 including a valid address.
1338 The main use of this function is as a predicate in match_operand
1339 expressions in the machine description. */
1342 memory_operand (rtx op, machine_mode mode)
1344 rtx inner;
1346 if (! reload_completed)
1347 /* Note that no SUBREG is a memory operand before end of reload pass,
1348 because (SUBREG (MEM...)) forces reloading into a register. */
1349 return MEM_P (op) && general_operand (op, mode);
1351 if (mode != VOIDmode && GET_MODE (op) != mode)
1352 return 0;
1354 inner = op;
1355 if (GET_CODE (inner) == SUBREG)
1356 inner = SUBREG_REG (inner);
1358 return (MEM_P (inner) && general_operand (op, mode));
1361 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1362 that is, a memory reference whose address is a general_operand. */
1365 indirect_operand (rtx op, machine_mode mode)
1367 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1368 if (! reload_completed
1369 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
1371 int offset = SUBREG_BYTE (op);
1372 rtx inner = SUBREG_REG (op);
1374 if (mode != VOIDmode && GET_MODE (op) != mode)
1375 return 0;
1377 /* The only way that we can have a general_operand as the resulting
1378 address is if OFFSET is zero and the address already is an operand
1379 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1380 operand. */
1382 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1383 || (GET_CODE (XEXP (inner, 0)) == PLUS
1384 && CONST_INT_P (XEXP (XEXP (inner, 0), 1))
1385 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1386 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1389 return (MEM_P (op)
1390 && memory_operand (op, mode)
1391 && general_operand (XEXP (op, 0), Pmode));
1394 /* Return 1 if this is an ordered comparison operator (not including
1395 ORDERED and UNORDERED). */
1398 ordered_comparison_operator (rtx op, machine_mode mode)
1400 if (mode != VOIDmode && GET_MODE (op) != mode)
1401 return false;
1402 switch (GET_CODE (op))
1404 case EQ:
1405 case NE:
1406 case LT:
1407 case LTU:
1408 case LE:
1409 case LEU:
1410 case GT:
1411 case GTU:
1412 case GE:
1413 case GEU:
1414 return true;
1415 default:
1416 return false;
1420 /* Return 1 if this is a comparison operator. This allows the use of
1421 MATCH_OPERATOR to recognize all the branch insns. */
1424 comparison_operator (rtx op, machine_mode mode)
1426 return ((mode == VOIDmode || GET_MODE (op) == mode)
1427 && COMPARISON_P (op));
1430 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1433 extract_asm_operands (rtx body)
1435 rtx tmp;
1436 switch (GET_CODE (body))
1438 case ASM_OPERANDS:
1439 return body;
1441 case SET:
1442 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1443 tmp = SET_SRC (body);
1444 if (GET_CODE (tmp) == ASM_OPERANDS)
1445 return tmp;
1446 break;
1448 case PARALLEL:
1449 tmp = XVECEXP (body, 0, 0);
1450 if (GET_CODE (tmp) == ASM_OPERANDS)
1451 return tmp;
1452 if (GET_CODE (tmp) == SET)
1454 tmp = SET_SRC (tmp);
1455 if (GET_CODE (tmp) == ASM_OPERANDS)
1456 return tmp;
1458 break;
1460 default:
1461 break;
1463 return NULL;
1466 /* If BODY is an insn body that uses ASM_OPERANDS,
1467 return the number of operands (both input and output) in the insn.
1468 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1469 return 0.
1470 Otherwise return -1. */
1473 asm_noperands (const_rtx body)
1475 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body));
1476 int i, n_sets = 0;
1478 if (asm_op == NULL)
1480 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) >= 2
1481 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
1483 /* body is [(asm_input ...) (clobber (reg ...))...]. */
1484 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1485 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1486 return -1;
1487 return 0;
1489 return -1;
1492 if (GET_CODE (body) == SET)
1493 n_sets = 1;
1494 else if (GET_CODE (body) == PARALLEL)
1496 if (GET_CODE (XVECEXP (body, 0, 0)) == SET)
1498 /* Multiple output operands, or 1 output plus some clobbers:
1499 body is
1500 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1501 /* Count backwards through CLOBBERs to determine number of SETs. */
1502 for (i = XVECLEN (body, 0); i > 0; i--)
1504 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1505 break;
1506 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1507 return -1;
1510 /* N_SETS is now number of output operands. */
1511 n_sets = i;
1513 /* Verify that all the SETs we have
1514 came from a single original asm_operands insn
1515 (so that invalid combinations are blocked). */
1516 for (i = 0; i < n_sets; i++)
1518 rtx elt = XVECEXP (body, 0, i);
1519 if (GET_CODE (elt) != SET)
1520 return -1;
1521 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1522 return -1;
1523 /* If these ASM_OPERANDS rtx's came from different original insns
1524 then they aren't allowed together. */
1525 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1526 != ASM_OPERANDS_INPUT_VEC (asm_op))
1527 return -1;
1530 else
1532 /* 0 outputs, but some clobbers:
1533 body is [(asm_operands ...) (clobber (reg ...))...]. */
1534 /* Make sure all the other parallel things really are clobbers. */
1535 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1536 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1537 return -1;
1541 return (ASM_OPERANDS_INPUT_LENGTH (asm_op)
1542 + ASM_OPERANDS_LABEL_LENGTH (asm_op) + n_sets);
1545 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1546 copy its operands (both input and output) into the vector OPERANDS,
1547 the locations of the operands within the insn into the vector OPERAND_LOCS,
1548 and the constraints for the operands into CONSTRAINTS.
1549 Write the modes of the operands into MODES.
1550 Write the location info into LOC.
1551 Return the assembler-template.
1552 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1553 return the basic assembly string.
1555 If LOC, MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1556 we don't store that info. */
1558 const char *
1559 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
1560 const char **constraints, machine_mode *modes,
1561 location_t *loc)
1563 int nbase = 0, n, i;
1564 rtx asmop;
1566 switch (GET_CODE (body))
1568 case ASM_OPERANDS:
1569 /* Zero output asm: BODY is (asm_operands ...). */
1570 asmop = body;
1571 break;
1573 case SET:
1574 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1575 asmop = SET_SRC (body);
1577 /* The output is in the SET.
1578 Its constraint is in the ASM_OPERANDS itself. */
1579 if (operands)
1580 operands[0] = SET_DEST (body);
1581 if (operand_locs)
1582 operand_locs[0] = &SET_DEST (body);
1583 if (constraints)
1584 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1585 if (modes)
1586 modes[0] = GET_MODE (SET_DEST (body));
1587 nbase = 1;
1588 break;
1590 case PARALLEL:
1592 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1594 asmop = XVECEXP (body, 0, 0);
1595 if (GET_CODE (asmop) == SET)
1597 asmop = SET_SRC (asmop);
1599 /* At least one output, plus some CLOBBERs. The outputs are in
1600 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1601 for (i = 0; i < nparallel; i++)
1603 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1604 break; /* Past last SET */
1605 if (operands)
1606 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1607 if (operand_locs)
1608 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1609 if (constraints)
1610 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1611 if (modes)
1612 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1614 nbase = i;
1616 else if (GET_CODE (asmop) == ASM_INPUT)
1618 if (loc)
1619 *loc = ASM_INPUT_SOURCE_LOCATION (asmop);
1620 return XSTR (asmop, 0);
1622 break;
1625 default:
1626 gcc_unreachable ();
1629 n = ASM_OPERANDS_INPUT_LENGTH (asmop);
1630 for (i = 0; i < n; i++)
1632 if (operand_locs)
1633 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i);
1634 if (operands)
1635 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i);
1636 if (constraints)
1637 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1638 if (modes)
1639 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1641 nbase += n;
1643 n = ASM_OPERANDS_LABEL_LENGTH (asmop);
1644 for (i = 0; i < n; i++)
1646 if (operand_locs)
1647 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i);
1648 if (operands)
1649 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i);
1650 if (constraints)
1651 constraints[nbase + i] = "";
1652 if (modes)
1653 modes[nbase + i] = Pmode;
1656 if (loc)
1657 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop);
1659 return ASM_OPERANDS_TEMPLATE (asmop);
1662 /* Parse inline assembly string STRING and determine which operands are
1663 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1664 to true if operand I is referenced.
1666 This is intended to distinguish barrier-like asms such as:
1668 asm ("" : "=m" (...));
1670 from real references such as:
1672 asm ("sw\t$0, %0" : "=m" (...)); */
1674 void
1675 get_referenced_operands (const char *string, bool *used,
1676 unsigned int noperands)
1678 memset (used, 0, sizeof (bool) * noperands);
1679 const char *p = string;
1680 while (*p)
1681 switch (*p)
1683 case '%':
1684 p += 1;
1685 /* A letter followed by a digit indicates an operand number. */
1686 if (ISALPHA (p[0]) && ISDIGIT (p[1]))
1687 p += 1;
1688 if (ISDIGIT (*p))
1690 char *endptr;
1691 unsigned long opnum = strtoul (p, &endptr, 10);
1692 if (endptr != p && opnum < noperands)
1693 used[opnum] = true;
1694 p = endptr;
1696 else
1697 p += 1;
1698 break;
1700 default:
1701 p++;
1702 break;
1706 /* Check if an asm_operand matches its constraints.
1707 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1710 asm_operand_ok (rtx op, const char *constraint, const char **constraints)
1712 int result = 0;
1713 bool incdec_ok = false;
1715 /* Use constrain_operands after reload. */
1716 gcc_assert (!reload_completed);
1718 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1719 many alternatives as required to match the other operands. */
1720 if (*constraint == '\0')
1721 result = 1;
1723 while (*constraint)
1725 enum constraint_num cn;
1726 char c = *constraint;
1727 int len;
1728 switch (c)
1730 case ',':
1731 constraint++;
1732 continue;
1734 case '0': case '1': case '2': case '3': case '4':
1735 case '5': case '6': case '7': case '8': case '9':
1736 /* If caller provided constraints pointer, look up
1737 the matching constraint. Otherwise, our caller should have
1738 given us the proper matching constraint, but we can't
1739 actually fail the check if they didn't. Indicate that
1740 results are inconclusive. */
1741 if (constraints)
1743 char *end;
1744 unsigned long match;
1746 match = strtoul (constraint, &end, 10);
1747 if (!result)
1748 result = asm_operand_ok (op, constraints[match], NULL);
1749 constraint = (const char *) end;
1751 else
1754 constraint++;
1755 while (ISDIGIT (*constraint));
1756 if (! result)
1757 result = -1;
1759 continue;
1761 /* The rest of the compiler assumes that reloading the address
1762 of a MEM into a register will make it fit an 'o' constraint.
1763 That is, if it sees a MEM operand for an 'o' constraint,
1764 it assumes that (mem (base-reg)) will fit.
1766 That assumption fails on targets that don't have offsettable
1767 addresses at all. We therefore need to treat 'o' asm
1768 constraints as a special case and only accept operands that
1769 are already offsettable, thus proving that at least one
1770 offsettable address exists. */
1771 case 'o': /* offsettable */
1772 if (offsettable_nonstrict_memref_p (op))
1773 result = 1;
1774 break;
1776 case 'g':
1777 if (general_operand (op, VOIDmode))
1778 result = 1;
1779 break;
1781 case '<':
1782 case '>':
1783 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1784 to exist, excepting those that expand_call created. Further,
1785 on some machines which do not have generalized auto inc/dec,
1786 an inc/dec is not a memory_operand.
1788 Match any memory and hope things are resolved after reload. */
1789 incdec_ok = true;
1790 /* FALLTHRU */
1791 default:
1792 cn = lookup_constraint (constraint);
1793 switch (get_constraint_type (cn))
1795 case CT_REGISTER:
1796 if (!result
1797 && reg_class_for_constraint (cn) != NO_REGS
1798 && GET_MODE (op) != BLKmode
1799 && register_operand (op, VOIDmode))
1800 result = 1;
1801 break;
1803 case CT_CONST_INT:
1804 if (!result
1805 && CONST_INT_P (op)
1806 && insn_const_int_ok_for_constraint (INTVAL (op), cn))
1807 result = 1;
1808 break;
1810 case CT_MEMORY:
1811 case CT_SPECIAL_MEMORY:
1812 /* Every memory operand can be reloaded to fit. */
1813 result = result || memory_operand (op, VOIDmode);
1814 break;
1816 case CT_ADDRESS:
1817 /* Every address operand can be reloaded to fit. */
1818 result = result || address_operand (op, VOIDmode);
1819 break;
1821 case CT_FIXED_FORM:
1822 result = result || constraint_satisfied_p (op, cn);
1823 break;
1825 break;
1827 len = CONSTRAINT_LEN (c, constraint);
1829 constraint++;
1830 while (--len && *constraint);
1831 if (len)
1832 return 0;
1835 /* For operands without < or > constraints reject side-effects. */
1836 if (AUTO_INC_DEC && !incdec_ok && result && MEM_P (op))
1837 switch (GET_CODE (XEXP (op, 0)))
1839 case PRE_INC:
1840 case POST_INC:
1841 case PRE_DEC:
1842 case POST_DEC:
1843 case PRE_MODIFY:
1844 case POST_MODIFY:
1845 return 0;
1846 default:
1847 break;
1850 return result;
1853 /* Given an rtx *P, if it is a sum containing an integer constant term,
1854 return the location (type rtx *) of the pointer to that constant term.
1855 Otherwise, return a null pointer. */
1857 rtx *
1858 find_constant_term_loc (rtx *p)
1860 rtx *tem;
1861 enum rtx_code code = GET_CODE (*p);
1863 /* If *P IS such a constant term, P is its location. */
1865 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1866 || code == CONST)
1867 return p;
1869 /* Otherwise, if not a sum, it has no constant term. */
1871 if (GET_CODE (*p) != PLUS)
1872 return 0;
1874 /* If one of the summands is constant, return its location. */
1876 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1877 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1878 return p;
1880 /* Otherwise, check each summand for containing a constant term. */
1882 if (XEXP (*p, 0) != 0)
1884 tem = find_constant_term_loc (&XEXP (*p, 0));
1885 if (tem != 0)
1886 return tem;
1889 if (XEXP (*p, 1) != 0)
1891 tem = find_constant_term_loc (&XEXP (*p, 1));
1892 if (tem != 0)
1893 return tem;
1896 return 0;
1899 /* Return 1 if OP is a memory reference
1900 whose address contains no side effects
1901 and remains valid after the addition
1902 of a positive integer less than the
1903 size of the object being referenced.
1905 We assume that the original address is valid and do not check it.
1907 This uses strict_memory_address_p as a subroutine, so
1908 don't use it before reload. */
1911 offsettable_memref_p (rtx op)
1913 return ((MEM_P (op))
1914 && offsettable_address_addr_space_p (1, GET_MODE (op), XEXP (op, 0),
1915 MEM_ADDR_SPACE (op)));
1918 /* Similar, but don't require a strictly valid mem ref:
1919 consider pseudo-regs valid as index or base regs. */
1922 offsettable_nonstrict_memref_p (rtx op)
1924 return ((MEM_P (op))
1925 && offsettable_address_addr_space_p (0, GET_MODE (op), XEXP (op, 0),
1926 MEM_ADDR_SPACE (op)));
1929 /* Return 1 if Y is a memory address which contains no side effects
1930 and would remain valid for address space AS after the addition of
1931 a positive integer less than the size of that mode.
1933 We assume that the original address is valid and do not check it.
1934 We do check that it is valid for narrower modes.
1936 If STRICTP is nonzero, we require a strictly valid address,
1937 for the sake of use in reload.c. */
1940 offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y,
1941 addr_space_t as)
1943 enum rtx_code ycode = GET_CODE (y);
1944 rtx z;
1945 rtx y1 = y;
1946 rtx *y2;
1947 int (*addressp) (machine_mode, rtx, addr_space_t) =
1948 (strictp ? strict_memory_address_addr_space_p
1949 : memory_address_addr_space_p);
1950 unsigned int mode_sz = GET_MODE_SIZE (mode);
1952 if (CONSTANT_ADDRESS_P (y))
1953 return 1;
1955 /* Adjusting an offsettable address involves changing to a narrower mode.
1956 Make sure that's OK. */
1958 if (mode_dependent_address_p (y, as))
1959 return 0;
1961 machine_mode address_mode = GET_MODE (y);
1962 if (address_mode == VOIDmode)
1963 address_mode = targetm.addr_space.address_mode (as);
1964 #ifdef POINTERS_EXTEND_UNSIGNED
1965 machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
1966 #endif
1968 /* ??? How much offset does an offsettable BLKmode reference need?
1969 Clearly that depends on the situation in which it's being used.
1970 However, the current situation in which we test 0xffffffff is
1971 less than ideal. Caveat user. */
1972 if (mode_sz == 0)
1973 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1975 /* If the expression contains a constant term,
1976 see if it remains valid when max possible offset is added. */
1978 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1980 int good;
1982 y1 = *y2;
1983 *y2 = plus_constant (address_mode, *y2, mode_sz - 1);
1984 /* Use QImode because an odd displacement may be automatically invalid
1985 for any wider mode. But it should be valid for a single byte. */
1986 good = (*addressp) (QImode, y, as);
1988 /* In any case, restore old contents of memory. */
1989 *y2 = y1;
1990 return good;
1993 if (GET_RTX_CLASS (ycode) == RTX_AUTOINC)
1994 return 0;
1996 /* The offset added here is chosen as the maximum offset that
1997 any instruction could need to add when operating on something
1998 of the specified mode. We assume that if Y and Y+c are
1999 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2000 go inside a LO_SUM here, so we do so as well. */
2001 if (GET_CODE (y) == LO_SUM
2002 && mode != BLKmode
2003 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
2004 z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0),
2005 plus_constant (address_mode, XEXP (y, 1),
2006 mode_sz - 1));
2007 #ifdef POINTERS_EXTEND_UNSIGNED
2008 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2009 else if (POINTERS_EXTEND_UNSIGNED > 0
2010 && GET_CODE (y) == ZERO_EXTEND
2011 && GET_MODE (XEXP (y, 0)) == pointer_mode)
2012 z = gen_rtx_ZERO_EXTEND (address_mode,
2013 plus_constant (pointer_mode, XEXP (y, 0),
2014 mode_sz - 1));
2015 #endif
2016 else
2017 z = plus_constant (address_mode, y, mode_sz - 1);
2019 /* Use QImode because an odd displacement may be automatically invalid
2020 for any wider mode. But it should be valid for a single byte. */
2021 return (*addressp) (QImode, z, as);
2024 /* Return 1 if ADDR is an address-expression whose effect depends
2025 on the mode of the memory reference it is used in.
2027 ADDRSPACE is the address space associated with the address.
2029 Autoincrement addressing is a typical example of mode-dependence
2030 because the amount of the increment depends on the mode. */
2032 bool
2033 mode_dependent_address_p (rtx addr, addr_space_t addrspace)
2035 /* Auto-increment addressing with anything other than post_modify
2036 or pre_modify always introduces a mode dependency. Catch such
2037 cases now instead of deferring to the target. */
2038 if (GET_CODE (addr) == PRE_INC
2039 || GET_CODE (addr) == POST_INC
2040 || GET_CODE (addr) == PRE_DEC
2041 || GET_CODE (addr) == POST_DEC)
2042 return true;
2044 return targetm.mode_dependent_address_p (addr, addrspace);
2047 /* Return true if boolean attribute ATTR is supported. */
2049 static bool
2050 have_bool_attr (bool_attr attr)
2052 switch (attr)
2054 case BA_ENABLED:
2055 return HAVE_ATTR_enabled;
2056 case BA_PREFERRED_FOR_SIZE:
2057 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_size;
2058 case BA_PREFERRED_FOR_SPEED:
2059 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_speed;
2061 gcc_unreachable ();
2064 /* Return the value of ATTR for instruction INSN. */
2066 static bool
2067 get_bool_attr (rtx_insn *insn, bool_attr attr)
2069 switch (attr)
2071 case BA_ENABLED:
2072 return get_attr_enabled (insn);
2073 case BA_PREFERRED_FOR_SIZE:
2074 return get_attr_enabled (insn) && get_attr_preferred_for_size (insn);
2075 case BA_PREFERRED_FOR_SPEED:
2076 return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn);
2078 gcc_unreachable ();
2081 /* Like get_bool_attr_mask, but don't use the cache. */
2083 static alternative_mask
2084 get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr)
2086 /* Temporarily install enough information for get_attr_<foo> to assume
2087 that the insn operands are already cached. As above, the attribute
2088 mustn't depend on the values of operands, so we don't provide their
2089 real values here. */
2090 rtx_insn *old_insn = recog_data.insn;
2091 int old_alternative = which_alternative;
2093 recog_data.insn = insn;
2094 alternative_mask mask = ALL_ALTERNATIVES;
2095 int n_alternatives = insn_data[INSN_CODE (insn)].n_alternatives;
2096 for (int i = 0; i < n_alternatives; i++)
2098 which_alternative = i;
2099 if (!get_bool_attr (insn, attr))
2100 mask &= ~ALTERNATIVE_BIT (i);
2103 recog_data.insn = old_insn;
2104 which_alternative = old_alternative;
2105 return mask;
2108 /* Return the mask of operand alternatives that are allowed for INSN
2109 by boolean attribute ATTR. This mask depends only on INSN and on
2110 the current target; it does not depend on things like the values of
2111 operands. */
2113 static alternative_mask
2114 get_bool_attr_mask (rtx_insn *insn, bool_attr attr)
2116 /* Quick exit for asms and for targets that don't use these attributes. */
2117 int code = INSN_CODE (insn);
2118 if (code < 0 || !have_bool_attr (attr))
2119 return ALL_ALTERNATIVES;
2121 /* Calling get_attr_<foo> can be expensive, so cache the mask
2122 for speed. */
2123 if (!this_target_recog->x_bool_attr_masks[code][attr])
2124 this_target_recog->x_bool_attr_masks[code][attr]
2125 = get_bool_attr_mask_uncached (insn, attr);
2126 return this_target_recog->x_bool_attr_masks[code][attr];
2129 /* Return the set of alternatives of INSN that are allowed by the current
2130 target. */
2132 alternative_mask
2133 get_enabled_alternatives (rtx_insn *insn)
2135 return get_bool_attr_mask (insn, BA_ENABLED);
2138 /* Return the set of alternatives of INSN that are allowed by the current
2139 target and are preferred for the current size/speed optimization
2140 choice. */
2142 alternative_mask
2143 get_preferred_alternatives (rtx_insn *insn)
2145 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
2146 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2147 else
2148 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2151 /* Return the set of alternatives of INSN that are allowed by the current
2152 target and are preferred for the size/speed optimization choice
2153 associated with BB. Passing a separate BB is useful if INSN has not
2154 been emitted yet or if we are considering moving it to a different
2155 block. */
2157 alternative_mask
2158 get_preferred_alternatives (rtx_insn *insn, basic_block bb)
2160 if (optimize_bb_for_speed_p (bb))
2161 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2162 else
2163 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2166 /* Assert that the cached boolean attributes for INSN are still accurate.
2167 The backend is required to define these attributes in a way that only
2168 depends on the current target (rather than operands, compiler phase,
2169 etc.). */
2171 bool
2172 check_bool_attrs (rtx_insn *insn)
2174 int code = INSN_CODE (insn);
2175 if (code >= 0)
2176 for (int i = 0; i <= BA_LAST; ++i)
2178 enum bool_attr attr = (enum bool_attr) i;
2179 if (this_target_recog->x_bool_attr_masks[code][attr])
2180 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr]
2181 == get_bool_attr_mask_uncached (insn, attr));
2183 return true;
2186 /* Like extract_insn, but save insn extracted and don't extract again, when
2187 called again for the same insn expecting that recog_data still contain the
2188 valid information. This is used primary by gen_attr infrastructure that
2189 often does extract insn again and again. */
2190 void
2191 extract_insn_cached (rtx_insn *insn)
2193 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2194 return;
2195 extract_insn (insn);
2196 recog_data.insn = insn;
2199 /* Do uncached extract_insn, constrain_operands and complain about failures.
2200 This should be used when extracting a pre-existing constrained instruction
2201 if the caller wants to know which alternative was chosen. */
2202 void
2203 extract_constrain_insn (rtx_insn *insn)
2205 extract_insn (insn);
2206 if (!constrain_operands (reload_completed, get_enabled_alternatives (insn)))
2207 fatal_insn_not_found (insn);
2210 /* Do cached extract_insn, constrain_operands and complain about failures.
2211 Used by insn_attrtab. */
2212 void
2213 extract_constrain_insn_cached (rtx_insn *insn)
2215 extract_insn_cached (insn);
2216 if (which_alternative == -1
2217 && !constrain_operands (reload_completed,
2218 get_enabled_alternatives (insn)))
2219 fatal_insn_not_found (insn);
2222 /* Do cached constrain_operands on INSN and complain about failures. */
2224 constrain_operands_cached (rtx_insn *insn, int strict)
2226 if (which_alternative == -1)
2227 return constrain_operands (strict, get_enabled_alternatives (insn));
2228 else
2229 return 1;
2232 /* Analyze INSN and fill in recog_data. */
2234 void
2235 extract_insn (rtx_insn *insn)
2237 int i;
2238 int icode;
2239 int noperands;
2240 rtx body = PATTERN (insn);
2242 recog_data.n_operands = 0;
2243 recog_data.n_alternatives = 0;
2244 recog_data.n_dups = 0;
2245 recog_data.is_asm = false;
2247 switch (GET_CODE (body))
2249 case USE:
2250 case CLOBBER:
2251 case ASM_INPUT:
2252 case ADDR_VEC:
2253 case ADDR_DIFF_VEC:
2254 case VAR_LOCATION:
2255 return;
2257 case SET:
2258 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2259 goto asm_insn;
2260 else
2261 goto normal_insn;
2262 case PARALLEL:
2263 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2264 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2265 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS
2266 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT)
2267 goto asm_insn;
2268 else
2269 goto normal_insn;
2270 case ASM_OPERANDS:
2271 asm_insn:
2272 recog_data.n_operands = noperands = asm_noperands (body);
2273 if (noperands >= 0)
2275 /* This insn is an `asm' with operands. */
2277 /* expand_asm_operands makes sure there aren't too many operands. */
2278 gcc_assert (noperands <= MAX_RECOG_OPERANDS);
2280 /* Now get the operand values and constraints out of the insn. */
2281 decode_asm_operands (body, recog_data.operand,
2282 recog_data.operand_loc,
2283 recog_data.constraints,
2284 recog_data.operand_mode, NULL);
2285 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
2286 if (noperands > 0)
2288 const char *p = recog_data.constraints[0];
2289 recog_data.n_alternatives = 1;
2290 while (*p)
2291 recog_data.n_alternatives += (*p++ == ',');
2293 recog_data.is_asm = true;
2294 break;
2296 fatal_insn_not_found (insn);
2298 default:
2299 normal_insn:
2300 /* Ordinary insn: recognize it, get the operands via insn_extract
2301 and get the constraints. */
2303 icode = recog_memoized (insn);
2304 if (icode < 0)
2305 fatal_insn_not_found (insn);
2307 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2308 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2309 recog_data.n_dups = insn_data[icode].n_dups;
2311 insn_extract (insn);
2313 for (i = 0; i < noperands; i++)
2315 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2316 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
2317 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2318 /* VOIDmode match_operands gets mode from their real operand. */
2319 if (recog_data.operand_mode[i] == VOIDmode)
2320 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2323 for (i = 0; i < noperands; i++)
2324 recog_data.operand_type[i]
2325 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2326 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2327 : OP_IN);
2329 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES);
2331 recog_data.insn = NULL;
2332 which_alternative = -1;
2335 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2336 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2337 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2338 has N_OPERANDS entries. */
2340 void
2341 preprocess_constraints (int n_operands, int n_alternatives,
2342 const char **constraints,
2343 operand_alternative *op_alt_base)
2345 for (int i = 0; i < n_operands; i++)
2347 int j;
2348 struct operand_alternative *op_alt;
2349 const char *p = constraints[i];
2351 op_alt = op_alt_base;
2353 for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
2355 op_alt[i].cl = NO_REGS;
2356 op_alt[i].constraint = p;
2357 op_alt[i].matches = -1;
2358 op_alt[i].matched = -1;
2360 if (*p == '\0' || *p == ',')
2362 op_alt[i].anything_ok = 1;
2363 continue;
2366 for (;;)
2368 char c = *p;
2369 if (c == '#')
2371 c = *++p;
2372 while (c != ',' && c != '\0');
2373 if (c == ',' || c == '\0')
2375 p++;
2376 break;
2379 switch (c)
2381 case '?':
2382 op_alt[i].reject += 6;
2383 break;
2384 case '!':
2385 op_alt[i].reject += 600;
2386 break;
2387 case '&':
2388 op_alt[i].earlyclobber = 1;
2389 break;
2391 case '0': case '1': case '2': case '3': case '4':
2392 case '5': case '6': case '7': case '8': case '9':
2394 char *end;
2395 op_alt[i].matches = strtoul (p, &end, 10);
2396 op_alt[op_alt[i].matches].matched = i;
2397 p = end;
2399 continue;
2401 case 'X':
2402 op_alt[i].anything_ok = 1;
2403 break;
2405 case 'g':
2406 op_alt[i].cl =
2407 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS];
2408 break;
2410 default:
2411 enum constraint_num cn = lookup_constraint (p);
2412 enum reg_class cl;
2413 switch (get_constraint_type (cn))
2415 case CT_REGISTER:
2416 cl = reg_class_for_constraint (cn);
2417 if (cl != NO_REGS)
2418 op_alt[i].cl = reg_class_subunion[op_alt[i].cl][cl];
2419 break;
2421 case CT_CONST_INT:
2422 break;
2424 case CT_MEMORY:
2425 case CT_SPECIAL_MEMORY:
2426 op_alt[i].memory_ok = 1;
2427 break;
2429 case CT_ADDRESS:
2430 op_alt[i].is_address = 1;
2431 op_alt[i].cl
2432 = (reg_class_subunion
2433 [(int) op_alt[i].cl]
2434 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2435 ADDRESS, SCRATCH)]);
2436 break;
2438 case CT_FIXED_FORM:
2439 break;
2441 break;
2443 p += CONSTRAINT_LEN (c, p);
2449 /* Return an array of operand_alternative instructions for
2450 instruction ICODE. */
2452 const operand_alternative *
2453 preprocess_insn_constraints (unsigned int icode)
2455 gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1));
2456 if (this_target_recog->x_op_alt[icode])
2457 return this_target_recog->x_op_alt[icode];
2459 int n_operands = insn_data[icode].n_operands;
2460 if (n_operands == 0)
2461 return 0;
2462 /* Always provide at least one alternative so that which_op_alt ()
2463 works correctly. If the instruction has 0 alternatives (i.e. all
2464 constraint strings are empty) then each operand in this alternative
2465 will have anything_ok set. */
2466 int n_alternatives = MAX (insn_data[icode].n_alternatives, 1);
2467 int n_entries = n_operands * n_alternatives;
2469 operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries);
2470 const char **constraints = XALLOCAVEC (const char *, n_operands);
2472 for (int i = 0; i < n_operands; ++i)
2473 constraints[i] = insn_data[icode].operand[i].constraint;
2474 preprocess_constraints (n_operands, n_alternatives, constraints, op_alt);
2476 this_target_recog->x_op_alt[icode] = op_alt;
2477 return op_alt;
2480 /* After calling extract_insn, you can use this function to extract some
2481 information from the constraint strings into a more usable form.
2482 The collected data is stored in recog_op_alt. */
2484 void
2485 preprocess_constraints (rtx_insn *insn)
2487 int icode = INSN_CODE (insn);
2488 if (icode >= 0)
2489 recog_op_alt = preprocess_insn_constraints (icode);
2490 else
2492 int n_operands = recog_data.n_operands;
2493 int n_alternatives = recog_data.n_alternatives;
2494 int n_entries = n_operands * n_alternatives;
2495 memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative));
2496 preprocess_constraints (n_operands, n_alternatives,
2497 recog_data.constraints, asm_op_alt);
2498 recog_op_alt = asm_op_alt;
2502 /* Check the operands of an insn against the insn's operand constraints
2503 and return 1 if they match any of the alternatives in ALTERNATIVES.
2505 The information about the insn's operands, constraints, operand modes
2506 etc. is obtained from the global variables set up by extract_insn.
2508 WHICH_ALTERNATIVE is set to a number which indicates which
2509 alternative of constraints was matched: 0 for the first alternative,
2510 1 for the next, etc.
2512 In addition, when two operands are required to match
2513 and it happens that the output operand is (reg) while the
2514 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2515 make the output operand look like the input.
2516 This is because the output operand is the one the template will print.
2518 This is used in final, just before printing the assembler code and by
2519 the routines that determine an insn's attribute.
2521 If STRICT is a positive nonzero value, it means that we have been
2522 called after reload has been completed. In that case, we must
2523 do all checks strictly. If it is zero, it means that we have been called
2524 before reload has completed. In that case, we first try to see if we can
2525 find an alternative that matches strictly. If not, we try again, this
2526 time assuming that reload will fix up the insn. This provides a "best
2527 guess" for the alternative and is used to compute attributes of insns prior
2528 to reload. A negative value of STRICT is used for this internal call. */
2530 struct funny_match
2532 int this_op, other;
2536 constrain_operands (int strict, alternative_mask alternatives)
2538 const char *constraints[MAX_RECOG_OPERANDS];
2539 int matching_operands[MAX_RECOG_OPERANDS];
2540 int earlyclobber[MAX_RECOG_OPERANDS];
2541 int c;
2543 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2544 int funny_match_index;
2546 which_alternative = 0;
2547 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2548 return 1;
2550 for (c = 0; c < recog_data.n_operands; c++)
2552 constraints[c] = recog_data.constraints[c];
2553 matching_operands[c] = -1;
2558 int seen_earlyclobber_at = -1;
2559 int opno;
2560 int lose = 0;
2561 funny_match_index = 0;
2563 if (!TEST_BIT (alternatives, which_alternative))
2565 int i;
2567 for (i = 0; i < recog_data.n_operands; i++)
2568 constraints[i] = skip_alternative (constraints[i]);
2570 which_alternative++;
2571 continue;
2574 for (opno = 0; opno < recog_data.n_operands; opno++)
2576 rtx op = recog_data.operand[opno];
2577 machine_mode mode = GET_MODE (op);
2578 const char *p = constraints[opno];
2579 int offset = 0;
2580 int win = 0;
2581 int val;
2582 int len;
2584 earlyclobber[opno] = 0;
2586 /* A unary operator may be accepted by the predicate, but it
2587 is irrelevant for matching constraints. */
2588 if (UNARY_P (op))
2589 op = XEXP (op, 0);
2591 if (GET_CODE (op) == SUBREG)
2593 if (REG_P (SUBREG_REG (op))
2594 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2595 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
2596 GET_MODE (SUBREG_REG (op)),
2597 SUBREG_BYTE (op),
2598 GET_MODE (op));
2599 op = SUBREG_REG (op);
2602 /* An empty constraint or empty alternative
2603 allows anything which matched the pattern. */
2604 if (*p == 0 || *p == ',')
2605 win = 1;
2608 switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
2610 case '\0':
2611 len = 0;
2612 break;
2613 case ',':
2614 c = '\0';
2615 break;
2617 case '#':
2618 /* Ignore rest of this alternative as far as
2619 constraint checking is concerned. */
2621 p++;
2622 while (*p && *p != ',');
2623 len = 0;
2624 break;
2626 case '&':
2627 earlyclobber[opno] = 1;
2628 if (seen_earlyclobber_at < 0)
2629 seen_earlyclobber_at = opno;
2630 break;
2632 case '0': case '1': case '2': case '3': case '4':
2633 case '5': case '6': case '7': case '8': case '9':
2635 /* This operand must be the same as a previous one.
2636 This kind of constraint is used for instructions such
2637 as add when they take only two operands.
2639 Note that the lower-numbered operand is passed first.
2641 If we are not testing strictly, assume that this
2642 constraint will be satisfied. */
2644 char *end;
2645 int match;
2647 match = strtoul (p, &end, 10);
2648 p = end;
2650 if (strict < 0)
2651 val = 1;
2652 else
2654 rtx op1 = recog_data.operand[match];
2655 rtx op2 = recog_data.operand[opno];
2657 /* A unary operator may be accepted by the predicate,
2658 but it is irrelevant for matching constraints. */
2659 if (UNARY_P (op1))
2660 op1 = XEXP (op1, 0);
2661 if (UNARY_P (op2))
2662 op2 = XEXP (op2, 0);
2664 val = operands_match_p (op1, op2);
2667 matching_operands[opno] = match;
2668 matching_operands[match] = opno;
2670 if (val != 0)
2671 win = 1;
2673 /* If output is *x and input is *--x, arrange later
2674 to change the output to *--x as well, since the
2675 output op is the one that will be printed. */
2676 if (val == 2 && strict > 0)
2678 funny_match[funny_match_index].this_op = opno;
2679 funny_match[funny_match_index++].other = match;
2682 len = 0;
2683 break;
2685 case 'p':
2686 /* p is used for address_operands. When we are called by
2687 gen_reload, no one will have checked that the address is
2688 strictly valid, i.e., that all pseudos requiring hard regs
2689 have gotten them. */
2690 if (strict <= 0
2691 || (strict_memory_address_p (recog_data.operand_mode[opno],
2692 op)))
2693 win = 1;
2694 break;
2696 /* No need to check general_operand again;
2697 it was done in insn-recog.c. Well, except that reload
2698 doesn't check the validity of its replacements, but
2699 that should only matter when there's a bug. */
2700 case 'g':
2701 /* Anything goes unless it is a REG and really has a hard reg
2702 but the hard reg is not in the class GENERAL_REGS. */
2703 if (REG_P (op))
2705 if (strict < 0
2706 || GENERAL_REGS == ALL_REGS
2707 || (reload_in_progress
2708 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2709 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2710 win = 1;
2712 else if (strict < 0 || general_operand (op, mode))
2713 win = 1;
2714 break;
2716 default:
2718 enum constraint_num cn = lookup_constraint (p);
2719 enum reg_class cl = reg_class_for_constraint (cn);
2720 if (cl != NO_REGS)
2722 if (strict < 0
2723 || (strict == 0
2724 && REG_P (op)
2725 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2726 || (strict == 0 && GET_CODE (op) == SCRATCH)
2727 || (REG_P (op)
2728 && reg_fits_class_p (op, cl, offset, mode)))
2729 win = 1;
2732 else if (constraint_satisfied_p (op, cn))
2733 win = 1;
2735 else if (insn_extra_memory_constraint (cn)
2736 /* Every memory operand can be reloaded to fit. */
2737 && ((strict < 0 && MEM_P (op))
2738 /* Before reload, accept what reload can turn
2739 into a mem. */
2740 || (strict < 0 && CONSTANT_P (op))
2741 /* Before reload, accept a pseudo,
2742 since LRA can turn it into a mem. */
2743 || (strict < 0 && targetm.lra_p () && REG_P (op)
2744 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2745 /* During reload, accept a pseudo */
2746 || (reload_in_progress && REG_P (op)
2747 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
2748 win = 1;
2749 else if (insn_extra_address_constraint (cn)
2750 /* Every address operand can be reloaded to fit. */
2751 && strict < 0)
2752 win = 1;
2753 /* Cater to architectures like IA-64 that define extra memory
2754 constraints without using define_memory_constraint. */
2755 else if (reload_in_progress
2756 && REG_P (op)
2757 && REGNO (op) >= FIRST_PSEUDO_REGISTER
2758 && reg_renumber[REGNO (op)] < 0
2759 && reg_equiv_mem (REGNO (op)) != 0
2760 && constraint_satisfied_p
2761 (reg_equiv_mem (REGNO (op)), cn))
2762 win = 1;
2763 break;
2766 while (p += len, c);
2768 constraints[opno] = p;
2769 /* If this operand did not win somehow,
2770 this alternative loses. */
2771 if (! win)
2772 lose = 1;
2774 /* This alternative won; the operands are ok.
2775 Change whichever operands this alternative says to change. */
2776 if (! lose)
2778 int opno, eopno;
2780 /* See if any earlyclobber operand conflicts with some other
2781 operand. */
2783 if (strict > 0 && seen_earlyclobber_at >= 0)
2784 for (eopno = seen_earlyclobber_at;
2785 eopno < recog_data.n_operands;
2786 eopno++)
2787 /* Ignore earlyclobber operands now in memory,
2788 because we would often report failure when we have
2789 two memory operands, one of which was formerly a REG. */
2790 if (earlyclobber[eopno]
2791 && REG_P (recog_data.operand[eopno]))
2792 for (opno = 0; opno < recog_data.n_operands; opno++)
2793 if ((MEM_P (recog_data.operand[opno])
2794 || recog_data.operand_type[opno] != OP_OUT)
2795 && opno != eopno
2796 /* Ignore things like match_operator operands. */
2797 && *recog_data.constraints[opno] != 0
2798 && ! (matching_operands[opno] == eopno
2799 && operands_match_p (recog_data.operand[opno],
2800 recog_data.operand[eopno]))
2801 && ! safe_from_earlyclobber (recog_data.operand[opno],
2802 recog_data.operand[eopno]))
2803 lose = 1;
2805 if (! lose)
2807 while (--funny_match_index >= 0)
2809 recog_data.operand[funny_match[funny_match_index].other]
2810 = recog_data.operand[funny_match[funny_match_index].this_op];
2813 /* For operands without < or > constraints reject side-effects. */
2814 if (AUTO_INC_DEC && recog_data.is_asm)
2816 for (opno = 0; opno < recog_data.n_operands; opno++)
2817 if (MEM_P (recog_data.operand[opno]))
2818 switch (GET_CODE (XEXP (recog_data.operand[opno], 0)))
2820 case PRE_INC:
2821 case POST_INC:
2822 case PRE_DEC:
2823 case POST_DEC:
2824 case PRE_MODIFY:
2825 case POST_MODIFY:
2826 if (strchr (recog_data.constraints[opno], '<') == NULL
2827 && strchr (recog_data.constraints[opno], '>')
2828 == NULL)
2829 return 0;
2830 break;
2831 default:
2832 break;
2836 return 1;
2840 which_alternative++;
2842 while (which_alternative < recog_data.n_alternatives);
2844 which_alternative = -1;
2845 /* If we are about to reject this, but we are not to test strictly,
2846 try a very loose test. Only return failure if it fails also. */
2847 if (strict == 0)
2848 return constrain_operands (-1, alternatives);
2849 else
2850 return 0;
2853 /* Return true iff OPERAND (assumed to be a REG rtx)
2854 is a hard reg in class CLASS when its regno is offset by OFFSET
2855 and changed to mode MODE.
2856 If REG occupies multiple hard regs, all of them must be in CLASS. */
2858 bool
2859 reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset,
2860 machine_mode mode)
2862 unsigned int regno = REGNO (operand);
2864 if (cl == NO_REGS)
2865 return false;
2867 /* Regno must not be a pseudo register. Offset may be negative. */
2868 return (HARD_REGISTER_NUM_P (regno)
2869 && HARD_REGISTER_NUM_P (regno + offset)
2870 && in_hard_reg_set_p (reg_class_contents[(int) cl], mode,
2871 regno + offset));
2874 /* Split single instruction. Helper function for split_all_insns and
2875 split_all_insns_noflow. Return last insn in the sequence if successful,
2876 or NULL if unsuccessful. */
2878 static rtx_insn *
2879 split_insn (rtx_insn *insn)
2881 /* Split insns here to get max fine-grain parallelism. */
2882 rtx_insn *first = PREV_INSN (insn);
2883 rtx_insn *last = try_split (PATTERN (insn), insn, 1);
2884 rtx insn_set, last_set, note;
2886 if (last == insn)
2887 return NULL;
2889 /* If the original instruction was a single set that was known to be
2890 equivalent to a constant, see if we can say the same about the last
2891 instruction in the split sequence. The two instructions must set
2892 the same destination. */
2893 insn_set = single_set (insn);
2894 if (insn_set)
2896 last_set = single_set (last);
2897 if (last_set && rtx_equal_p (SET_DEST (last_set), SET_DEST (insn_set)))
2899 note = find_reg_equal_equiv_note (insn);
2900 if (note && CONSTANT_P (XEXP (note, 0)))
2901 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0));
2902 else if (CONSTANT_P (SET_SRC (insn_set)))
2903 set_unique_reg_note (last, REG_EQUAL,
2904 copy_rtx (SET_SRC (insn_set)));
2908 /* try_split returns the NOTE that INSN became. */
2909 SET_INSN_DELETED (insn);
2911 /* ??? Coddle to md files that generate subregs in post-reload
2912 splitters instead of computing the proper hard register. */
2913 if (reload_completed && first != last)
2915 first = NEXT_INSN (first);
2916 for (;;)
2918 if (INSN_P (first))
2919 cleanup_subreg_operands (first);
2920 if (first == last)
2921 break;
2922 first = NEXT_INSN (first);
2926 return last;
2929 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2931 void
2932 split_all_insns (void)
2934 bool changed;
2935 basic_block bb;
2937 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
2938 bitmap_clear (blocks);
2939 changed = false;
2941 FOR_EACH_BB_REVERSE_FN (bb, cfun)
2943 rtx_insn *insn, *next;
2944 bool finish = false;
2946 rtl_profile_for_bb (bb);
2947 for (insn = BB_HEAD (bb); !finish ; insn = next)
2949 /* Can't use `next_real_insn' because that might go across
2950 CODE_LABELS and short-out basic blocks. */
2951 next = NEXT_INSN (insn);
2952 finish = (insn == BB_END (bb));
2953 if (INSN_P (insn))
2955 rtx set = single_set (insn);
2957 /* Don't split no-op move insns. These should silently
2958 disappear later in final. Splitting such insns would
2959 break the code that handles LIBCALL blocks. */
2960 if (set && set_noop_p (set))
2962 /* Nops get in the way while scheduling, so delete them
2963 now if register allocation has already been done. It
2964 is too risky to try to do this before register
2965 allocation, and there are unlikely to be very many
2966 nops then anyways. */
2967 if (reload_completed)
2968 delete_insn_and_edges (insn);
2970 else
2972 if (split_insn (insn))
2974 bitmap_set_bit (blocks, bb->index);
2975 changed = true;
2982 default_rtl_profile ();
2983 if (changed)
2984 find_many_sub_basic_blocks (blocks);
2986 checking_verify_flow_info ();
2989 /* Same as split_all_insns, but do not expect CFG to be available.
2990 Used by machine dependent reorg passes. */
2992 unsigned int
2993 split_all_insns_noflow (void)
2995 rtx_insn *next, *insn;
2997 for (insn = get_insns (); insn; insn = next)
2999 next = NEXT_INSN (insn);
3000 if (INSN_P (insn))
3002 /* Don't split no-op move insns. These should silently
3003 disappear later in final. Splitting such insns would
3004 break the code that handles LIBCALL blocks. */
3005 rtx set = single_set (insn);
3006 if (set && set_noop_p (set))
3008 /* Nops get in the way while scheduling, so delete them
3009 now if register allocation has already been done. It
3010 is too risky to try to do this before register
3011 allocation, and there are unlikely to be very many
3012 nops then anyways.
3014 ??? Should we use delete_insn when the CFG isn't valid? */
3015 if (reload_completed)
3016 delete_insn_and_edges (insn);
3018 else
3019 split_insn (insn);
3022 return 0;
3025 struct peep2_insn_data
3027 rtx_insn *insn;
3028 regset live_before;
3031 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
3032 static int peep2_current;
3034 static bool peep2_do_rebuild_jump_labels;
3035 static bool peep2_do_cleanup_cfg;
3037 /* The number of instructions available to match a peep2. */
3038 int peep2_current_count;
3040 /* A marker indicating the last insn of the block. The live_before regset
3041 for this element is correct, indicating DF_LIVE_OUT for the block. */
3042 #define PEEP2_EOB invalid_insn_rtx
3044 /* Wrap N to fit into the peep2_insn_data buffer. */
3046 static int
3047 peep2_buf_position (int n)
3049 if (n >= MAX_INSNS_PER_PEEP2 + 1)
3050 n -= MAX_INSNS_PER_PEEP2 + 1;
3051 return n;
3054 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3055 does not exist. Used by the recognizer to find the next insn to match
3056 in a multi-insn pattern. */
3058 rtx_insn *
3059 peep2_next_insn (int n)
3061 gcc_assert (n <= peep2_current_count);
3063 n = peep2_buf_position (peep2_current + n);
3065 return peep2_insn_data[n].insn;
3068 /* Return true if REGNO is dead before the Nth non-note insn
3069 after `current'. */
3072 peep2_regno_dead_p (int ofs, int regno)
3074 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3076 ofs = peep2_buf_position (peep2_current + ofs);
3078 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3080 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
3083 /* Similarly for a REG. */
3086 peep2_reg_dead_p (int ofs, rtx reg)
3088 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
3090 ofs = peep2_buf_position (peep2_current + ofs);
3092 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3094 unsigned int end_regno = END_REGNO (reg);
3095 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
3096 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno))
3097 return 0;
3098 return 1;
3101 /* Regno offset to be used in the register search. */
3102 static int search_ofs;
3104 /* Try to find a hard register of mode MODE, matching the register class in
3105 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3106 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3107 in which case the only condition is that the register must be available
3108 before CURRENT_INSN.
3109 Registers that already have bits set in REG_SET will not be considered.
3111 If an appropriate register is available, it will be returned and the
3112 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3113 returned. */
3116 peep2_find_free_register (int from, int to, const char *class_str,
3117 machine_mode mode, HARD_REG_SET *reg_set)
3119 enum reg_class cl;
3120 HARD_REG_SET live;
3121 df_ref def;
3122 int i;
3124 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
3125 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
3127 from = peep2_buf_position (peep2_current + from);
3128 to = peep2_buf_position (peep2_current + to);
3130 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3131 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3133 while (from != to)
3135 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3137 /* Don't use registers set or clobbered by the insn. */
3138 FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn)
3139 SET_HARD_REG_BIT (live, DF_REF_REGNO (def));
3141 from = peep2_buf_position (from + 1);
3144 cl = reg_class_for_constraint (lookup_constraint (class_str));
3146 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3148 int raw_regno, regno, success, j;
3150 /* Distribute the free registers as much as possible. */
3151 raw_regno = search_ofs + i;
3152 if (raw_regno >= FIRST_PSEUDO_REGISTER)
3153 raw_regno -= FIRST_PSEUDO_REGISTER;
3154 #ifdef REG_ALLOC_ORDER
3155 regno = reg_alloc_order[raw_regno];
3156 #else
3157 regno = raw_regno;
3158 #endif
3160 /* Can it support the mode we need? */
3161 if (!targetm.hard_regno_mode_ok (regno, mode))
3162 continue;
3164 success = 1;
3165 for (j = 0; success && j < hard_regno_nregs (regno, mode); j++)
3167 /* Don't allocate fixed registers. */
3168 if (fixed_regs[regno + j])
3170 success = 0;
3171 break;
3173 /* Don't allocate global registers. */
3174 if (global_regs[regno + j])
3176 success = 0;
3177 break;
3179 /* Make sure the register is of the right class. */
3180 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j))
3182 success = 0;
3183 break;
3185 /* And that we don't create an extra save/restore. */
3186 if (! call_used_regs[regno + j] && ! df_regs_ever_live_p (regno + j))
3188 success = 0;
3189 break;
3192 if (! targetm.hard_regno_scratch_ok (regno + j))
3194 success = 0;
3195 break;
3198 /* And we don't clobber traceback for noreturn functions. */
3199 if ((regno + j == FRAME_POINTER_REGNUM
3200 || regno + j == HARD_FRAME_POINTER_REGNUM)
3201 && (! reload_completed || frame_pointer_needed))
3203 success = 0;
3204 break;
3207 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3208 || TEST_HARD_REG_BIT (live, regno + j))
3210 success = 0;
3211 break;
3215 if (success)
3217 add_to_hard_reg_set (reg_set, mode, regno);
3219 /* Start the next search with the next register. */
3220 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3221 raw_regno = 0;
3222 search_ofs = raw_regno;
3224 return gen_rtx_REG (mode, regno);
3228 search_ofs = 0;
3229 return NULL_RTX;
3232 /* Forget all currently tracked instructions, only remember current
3233 LIVE regset. */
3235 static void
3236 peep2_reinit_state (regset live)
3238 int i;
3240 /* Indicate that all slots except the last holds invalid data. */
3241 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3242 peep2_insn_data[i].insn = NULL;
3243 peep2_current_count = 0;
3245 /* Indicate that the last slot contains live_after data. */
3246 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3247 peep2_current = MAX_INSNS_PER_PEEP2;
3249 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3252 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3253 starting at INSN. Perform the replacement, removing the old insns and
3254 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3255 if the replacement is rejected. */
3257 static rtx_insn *
3258 peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt)
3260 int i;
3261 rtx_insn *last, *before_try, *x;
3262 rtx eh_note, as_note;
3263 rtx_insn *old_insn;
3264 rtx_insn *new_insn;
3265 bool was_call = false;
3267 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3268 match more than one insn, or to be split into more than one insn. */
3269 old_insn = peep2_insn_data[peep2_current].insn;
3270 if (RTX_FRAME_RELATED_P (old_insn))
3272 bool any_note = false;
3273 rtx note;
3275 if (match_len != 0)
3276 return NULL;
3278 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3279 may be in the stream for the purpose of register allocation. */
3280 if (active_insn_p (attempt))
3281 new_insn = attempt;
3282 else
3283 new_insn = next_active_insn (attempt);
3284 if (next_active_insn (new_insn))
3285 return NULL;
3287 /* We have a 1-1 replacement. Copy over any frame-related info. */
3288 RTX_FRAME_RELATED_P (new_insn) = 1;
3290 /* Allow the backend to fill in a note during the split. */
3291 for (note = REG_NOTES (new_insn); note ; note = XEXP (note, 1))
3292 switch (REG_NOTE_KIND (note))
3294 case REG_FRAME_RELATED_EXPR:
3295 case REG_CFA_DEF_CFA:
3296 case REG_CFA_ADJUST_CFA:
3297 case REG_CFA_OFFSET:
3298 case REG_CFA_REGISTER:
3299 case REG_CFA_EXPRESSION:
3300 case REG_CFA_RESTORE:
3301 case REG_CFA_SET_VDRAP:
3302 any_note = true;
3303 break;
3304 default:
3305 break;
3308 /* If the backend didn't supply a note, copy one over. */
3309 if (!any_note)
3310 for (note = REG_NOTES (old_insn); note ; note = XEXP (note, 1))
3311 switch (REG_NOTE_KIND (note))
3313 case REG_FRAME_RELATED_EXPR:
3314 case REG_CFA_DEF_CFA:
3315 case REG_CFA_ADJUST_CFA:
3316 case REG_CFA_OFFSET:
3317 case REG_CFA_REGISTER:
3318 case REG_CFA_EXPRESSION:
3319 case REG_CFA_RESTORE:
3320 case REG_CFA_SET_VDRAP:
3321 add_reg_note (new_insn, REG_NOTE_KIND (note), XEXP (note, 0));
3322 any_note = true;
3323 break;
3324 default:
3325 break;
3328 /* If there still isn't a note, make sure the unwind info sees the
3329 same expression as before the split. */
3330 if (!any_note)
3332 rtx old_set, new_set;
3334 /* The old insn had better have been simple, or annotated. */
3335 old_set = single_set (old_insn);
3336 gcc_assert (old_set != NULL);
3338 new_set = single_set (new_insn);
3339 if (!new_set || !rtx_equal_p (new_set, old_set))
3340 add_reg_note (new_insn, REG_FRAME_RELATED_EXPR, old_set);
3343 /* Copy prologue/epilogue status. This is required in order to keep
3344 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3345 maybe_copy_prologue_epilogue_insn (old_insn, new_insn);
3348 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3349 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3350 cfg-related call notes. */
3351 for (i = 0; i <= match_len; ++i)
3353 int j;
3354 rtx note;
3356 j = peep2_buf_position (peep2_current + i);
3357 old_insn = peep2_insn_data[j].insn;
3358 if (!CALL_P (old_insn))
3359 continue;
3360 was_call = true;
3362 new_insn = attempt;
3363 while (new_insn != NULL_RTX)
3365 if (CALL_P (new_insn))
3366 break;
3367 new_insn = NEXT_INSN (new_insn);
3370 gcc_assert (new_insn != NULL_RTX);
3372 CALL_INSN_FUNCTION_USAGE (new_insn)
3373 = CALL_INSN_FUNCTION_USAGE (old_insn);
3374 SIBLING_CALL_P (new_insn) = SIBLING_CALL_P (old_insn);
3376 for (note = REG_NOTES (old_insn);
3377 note;
3378 note = XEXP (note, 1))
3379 switch (REG_NOTE_KIND (note))
3381 case REG_NORETURN:
3382 case REG_SETJMP:
3383 case REG_TM:
3384 case REG_CALL_NOCF_CHECK:
3385 add_reg_note (new_insn, REG_NOTE_KIND (note),
3386 XEXP (note, 0));
3387 break;
3388 default:
3389 /* Discard all other reg notes. */
3390 break;
3393 /* Croak if there is another call in the sequence. */
3394 while (++i <= match_len)
3396 j = peep2_buf_position (peep2_current + i);
3397 old_insn = peep2_insn_data[j].insn;
3398 gcc_assert (!CALL_P (old_insn));
3400 break;
3403 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3404 move those notes over to the new sequence. */
3405 as_note = NULL;
3406 for (i = match_len; i >= 0; --i)
3408 int j = peep2_buf_position (peep2_current + i);
3409 old_insn = peep2_insn_data[j].insn;
3411 as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULL);
3412 if (as_note)
3413 break;
3416 i = peep2_buf_position (peep2_current + match_len);
3417 eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX);
3419 /* Replace the old sequence with the new. */
3420 rtx_insn *peepinsn = peep2_insn_data[i].insn;
3421 last = emit_insn_after_setloc (attempt,
3422 peep2_insn_data[i].insn,
3423 INSN_LOCATION (peepinsn));
3424 before_try = PREV_INSN (insn);
3425 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3427 /* Re-insert the EH_REGION notes. */
3428 if (eh_note || (was_call && nonlocal_goto_handler_labels))
3430 edge eh_edge;
3431 edge_iterator ei;
3433 FOR_EACH_EDGE (eh_edge, ei, bb->succs)
3434 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3435 break;
3437 if (eh_note)
3438 copy_reg_eh_region_note_backward (eh_note, last, before_try);
3440 if (eh_edge)
3441 for (x = last; x != before_try; x = PREV_INSN (x))
3442 if (x != BB_END (bb)
3443 && (can_throw_internal (x)
3444 || can_nonlocal_goto (x)))
3446 edge nfte, nehe;
3447 int flags;
3449 nfte = split_block (bb, x);
3450 flags = (eh_edge->flags
3451 & (EDGE_EH | EDGE_ABNORMAL));
3452 if (CALL_P (x))
3453 flags |= EDGE_ABNORMAL_CALL;
3454 nehe = make_edge (nfte->src, eh_edge->dest,
3455 flags);
3457 nehe->probability = eh_edge->probability;
3458 nfte->probability = nehe->probability.invert ();
3460 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3461 bb = nfte->src;
3462 eh_edge = nehe;
3465 /* Converting possibly trapping insn to non-trapping is
3466 possible. Zap dummy outgoing edges. */
3467 peep2_do_cleanup_cfg |= purge_dead_edges (bb);
3470 /* Re-insert the ARGS_SIZE notes. */
3471 if (as_note)
3472 fixup_args_size_notes (before_try, last, INTVAL (XEXP (as_note, 0)));
3474 /* If we generated a jump instruction, it won't have
3475 JUMP_LABEL set. Recompute after we're done. */
3476 for (x = last; x != before_try; x = PREV_INSN (x))
3477 if (JUMP_P (x))
3479 peep2_do_rebuild_jump_labels = true;
3480 break;
3483 return last;
3486 /* After performing a replacement in basic block BB, fix up the life
3487 information in our buffer. LAST is the last of the insns that we
3488 emitted as a replacement. PREV is the insn before the start of
3489 the replacement. MATCH_LEN is the number of instructions that were
3490 matched, and which now need to be replaced in the buffer. */
3492 static void
3493 peep2_update_life (basic_block bb, int match_len, rtx_insn *last,
3494 rtx_insn *prev)
3496 int i = peep2_buf_position (peep2_current + match_len + 1);
3497 rtx_insn *x;
3498 regset_head live;
3500 INIT_REG_SET (&live);
3501 COPY_REG_SET (&live, peep2_insn_data[i].live_before);
3503 gcc_assert (peep2_current_count >= match_len + 1);
3504 peep2_current_count -= match_len + 1;
3506 x = last;
3509 if (INSN_P (x))
3511 df_insn_rescan (x);
3512 if (peep2_current_count < MAX_INSNS_PER_PEEP2)
3514 peep2_current_count++;
3515 if (--i < 0)
3516 i = MAX_INSNS_PER_PEEP2;
3517 peep2_insn_data[i].insn = x;
3518 df_simulate_one_insn_backwards (bb, x, &live);
3519 COPY_REG_SET (peep2_insn_data[i].live_before, &live);
3522 x = PREV_INSN (x);
3524 while (x != prev);
3525 CLEAR_REG_SET (&live);
3527 peep2_current = i;
3530 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3531 Return true if we added it, false otherwise. The caller will try to match
3532 peepholes against the buffer if we return false; otherwise it will try to
3533 add more instructions to the buffer. */
3535 static bool
3536 peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live)
3538 int pos;
3540 /* Once we have filled the maximum number of insns the buffer can hold,
3541 allow the caller to match the insns against peepholes. We wait until
3542 the buffer is full in case the target has similar peepholes of different
3543 length; we always want to match the longest if possible. */
3544 if (peep2_current_count == MAX_INSNS_PER_PEEP2)
3545 return false;
3547 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3548 any other pattern, lest it change the semantics of the frame info. */
3549 if (RTX_FRAME_RELATED_P (insn))
3551 /* Let the buffer drain first. */
3552 if (peep2_current_count > 0)
3553 return false;
3554 /* Now the insn will be the only thing in the buffer. */
3557 pos = peep2_buf_position (peep2_current + peep2_current_count);
3558 peep2_insn_data[pos].insn = insn;
3559 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3560 peep2_current_count++;
3562 df_simulate_one_insn_forwards (bb, insn, live);
3563 return true;
3566 /* Perform the peephole2 optimization pass. */
3568 static void
3569 peephole2_optimize (void)
3571 rtx_insn *insn;
3572 bitmap live;
3573 int i;
3574 basic_block bb;
3576 peep2_do_cleanup_cfg = false;
3577 peep2_do_rebuild_jump_labels = false;
3579 df_set_flags (DF_LR_RUN_DCE);
3580 df_note_add_problem ();
3581 df_analyze ();
3583 /* Initialize the regsets we're going to use. */
3584 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3585 peep2_insn_data[i].live_before = BITMAP_ALLOC (&reg_obstack);
3586 search_ofs = 0;
3587 live = BITMAP_ALLOC (&reg_obstack);
3589 FOR_EACH_BB_REVERSE_FN (bb, cfun)
3591 bool past_end = false;
3592 int pos;
3594 rtl_profile_for_bb (bb);
3596 /* Start up propagation. */
3597 bitmap_copy (live, DF_LR_IN (bb));
3598 df_simulate_initialize_forwards (bb, live);
3599 peep2_reinit_state (live);
3601 insn = BB_HEAD (bb);
3602 for (;;)
3604 rtx_insn *attempt, *head;
3605 int match_len;
3607 if (!past_end && !NONDEBUG_INSN_P (insn))
3609 next_insn:
3610 insn = NEXT_INSN (insn);
3611 if (insn == NEXT_INSN (BB_END (bb)))
3612 past_end = true;
3613 continue;
3615 if (!past_end && peep2_fill_buffer (bb, insn, live))
3616 goto next_insn;
3618 /* If we did not fill an empty buffer, it signals the end of the
3619 block. */
3620 if (peep2_current_count == 0)
3621 break;
3623 /* The buffer filled to the current maximum, so try to match. */
3625 pos = peep2_buf_position (peep2_current + peep2_current_count);
3626 peep2_insn_data[pos].insn = PEEP2_EOB;
3627 COPY_REG_SET (peep2_insn_data[pos].live_before, live);
3629 /* Match the peephole. */
3630 head = peep2_insn_data[peep2_current].insn;
3631 attempt = peephole2_insns (PATTERN (head), head, &match_len);
3632 if (attempt != NULL)
3634 rtx_insn *last = peep2_attempt (bb, head, match_len, attempt);
3635 if (last)
3637 peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
3638 continue;
3642 /* No match: advance the buffer by one insn. */
3643 peep2_current = peep2_buf_position (peep2_current + 1);
3644 peep2_current_count--;
3648 default_rtl_profile ();
3649 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3650 BITMAP_FREE (peep2_insn_data[i].live_before);
3651 BITMAP_FREE (live);
3652 if (peep2_do_rebuild_jump_labels)
3653 rebuild_jump_labels (get_insns ());
3654 if (peep2_do_cleanup_cfg)
3655 cleanup_cfg (CLEANUP_CFG_CHANGED);
3658 /* Common predicates for use with define_bypass. */
3660 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3661 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3662 must be either a single_set or a PARALLEL with SETs inside. */
3665 store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3667 rtx out_set, in_set;
3668 rtx out_pat, in_pat;
3669 rtx out_exp, in_exp;
3670 int i, j;
3672 in_set = single_set (in_insn);
3673 if (in_set)
3675 if (!MEM_P (SET_DEST (in_set)))
3676 return false;
3678 out_set = single_set (out_insn);
3679 if (out_set)
3681 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)))
3682 return false;
3684 else
3686 out_pat = PATTERN (out_insn);
3688 if (GET_CODE (out_pat) != PARALLEL)
3689 return false;
3691 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3693 out_exp = XVECEXP (out_pat, 0, i);
3695 if (GET_CODE (out_exp) == CLOBBER)
3696 continue;
3698 gcc_assert (GET_CODE (out_exp) == SET);
3700 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set)))
3701 return false;
3705 else
3707 in_pat = PATTERN (in_insn);
3708 gcc_assert (GET_CODE (in_pat) == PARALLEL);
3710 for (i = 0; i < XVECLEN (in_pat, 0); i++)
3712 in_exp = XVECEXP (in_pat, 0, i);
3714 if (GET_CODE (in_exp) == CLOBBER)
3715 continue;
3717 gcc_assert (GET_CODE (in_exp) == SET);
3719 if (!MEM_P (SET_DEST (in_exp)))
3720 return false;
3722 out_set = single_set (out_insn);
3723 if (out_set)
3725 if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_exp)))
3726 return false;
3728 else
3730 out_pat = PATTERN (out_insn);
3731 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3733 for (j = 0; j < XVECLEN (out_pat, 0); j++)
3735 out_exp = XVECEXP (out_pat, 0, j);
3737 if (GET_CODE (out_exp) == CLOBBER)
3738 continue;
3740 gcc_assert (GET_CODE (out_exp) == SET);
3742 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_exp)))
3743 return false;
3749 return true;
3752 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3753 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3754 or multiple set; IN_INSN should be single_set for truth, but for convenience
3755 of insn categorization may be any JUMP or CALL insn. */
3758 if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
3760 rtx out_set, in_set;
3762 in_set = single_set (in_insn);
3763 if (! in_set)
3765 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn));
3766 return false;
3769 if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
3770 return false;
3771 in_set = SET_SRC (in_set);
3773 out_set = single_set (out_insn);
3774 if (out_set)
3776 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3777 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3778 return false;
3780 else
3782 rtx out_pat;
3783 int i;
3785 out_pat = PATTERN (out_insn);
3786 gcc_assert (GET_CODE (out_pat) == PARALLEL);
3788 for (i = 0; i < XVECLEN (out_pat, 0); i++)
3790 rtx exp = XVECEXP (out_pat, 0, i);
3792 if (GET_CODE (exp) == CLOBBER)
3793 continue;
3795 gcc_assert (GET_CODE (exp) == SET);
3797 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
3798 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
3799 return false;
3803 return true;
3806 static unsigned int
3807 rest_of_handle_peephole2 (void)
3809 if (HAVE_peephole2)
3810 peephole2_optimize ();
3812 return 0;
3815 namespace {
3817 const pass_data pass_data_peephole2 =
3819 RTL_PASS, /* type */
3820 "peephole2", /* name */
3821 OPTGROUP_NONE, /* optinfo_flags */
3822 TV_PEEPHOLE2, /* tv_id */
3823 0, /* properties_required */
3824 0, /* properties_provided */
3825 0, /* properties_destroyed */
3826 0, /* todo_flags_start */
3827 TODO_df_finish, /* todo_flags_finish */
3830 class pass_peephole2 : public rtl_opt_pass
3832 public:
3833 pass_peephole2 (gcc::context *ctxt)
3834 : rtl_opt_pass (pass_data_peephole2, ctxt)
3837 /* opt_pass methods: */
3838 /* The epiphany backend creates a second instance of this pass, so we need
3839 a clone method. */
3840 opt_pass * clone () { return new pass_peephole2 (m_ctxt); }
3841 virtual bool gate (function *) { return (optimize > 0 && flag_peephole2); }
3842 virtual unsigned int execute (function *)
3844 return rest_of_handle_peephole2 ();
3847 }; // class pass_peephole2
3849 } // anon namespace
3851 rtl_opt_pass *
3852 make_pass_peephole2 (gcc::context *ctxt)
3854 return new pass_peephole2 (ctxt);
3857 namespace {
3859 const pass_data pass_data_split_all_insns =
3861 RTL_PASS, /* type */
3862 "split1", /* name */
3863 OPTGROUP_NONE, /* optinfo_flags */
3864 TV_NONE, /* tv_id */
3865 0, /* properties_required */
3866 PROP_rtl_split_insns, /* properties_provided */
3867 0, /* properties_destroyed */
3868 0, /* todo_flags_start */
3869 0, /* todo_flags_finish */
3872 class pass_split_all_insns : public rtl_opt_pass
3874 public:
3875 pass_split_all_insns (gcc::context *ctxt)
3876 : rtl_opt_pass (pass_data_split_all_insns, ctxt)
3879 /* opt_pass methods: */
3880 /* The epiphany backend creates a second instance of this pass, so
3881 we need a clone method. */
3882 opt_pass * clone () { return new pass_split_all_insns (m_ctxt); }
3883 virtual unsigned int execute (function *)
3885 split_all_insns ();
3886 return 0;
3889 }; // class pass_split_all_insns
3891 } // anon namespace
3893 rtl_opt_pass *
3894 make_pass_split_all_insns (gcc::context *ctxt)
3896 return new pass_split_all_insns (ctxt);
3899 namespace {
3901 const pass_data pass_data_split_after_reload =
3903 RTL_PASS, /* type */
3904 "split2", /* name */
3905 OPTGROUP_NONE, /* optinfo_flags */
3906 TV_NONE, /* tv_id */
3907 0, /* properties_required */
3908 0, /* properties_provided */
3909 0, /* properties_destroyed */
3910 0, /* todo_flags_start */
3911 0, /* todo_flags_finish */
3914 class pass_split_after_reload : public rtl_opt_pass
3916 public:
3917 pass_split_after_reload (gcc::context *ctxt)
3918 : rtl_opt_pass (pass_data_split_after_reload, ctxt)
3921 /* opt_pass methods: */
3922 virtual bool gate (function *)
3924 /* If optimizing, then go ahead and split insns now. */
3925 if (optimize > 0)
3926 return true;
3928 #ifdef STACK_REGS
3929 return true;
3930 #else
3931 return false;
3932 #endif
3935 virtual unsigned int execute (function *)
3937 split_all_insns ();
3938 return 0;
3941 }; // class pass_split_after_reload
3943 } // anon namespace
3945 rtl_opt_pass *
3946 make_pass_split_after_reload (gcc::context *ctxt)
3948 return new pass_split_after_reload (ctxt);
3951 namespace {
3953 const pass_data pass_data_split_before_regstack =
3955 RTL_PASS, /* type */
3956 "split3", /* name */
3957 OPTGROUP_NONE, /* optinfo_flags */
3958 TV_NONE, /* tv_id */
3959 0, /* properties_required */
3960 0, /* properties_provided */
3961 0, /* properties_destroyed */
3962 0, /* todo_flags_start */
3963 0, /* todo_flags_finish */
3966 class pass_split_before_regstack : public rtl_opt_pass
3968 public:
3969 pass_split_before_regstack (gcc::context *ctxt)
3970 : rtl_opt_pass (pass_data_split_before_regstack, ctxt)
3973 /* opt_pass methods: */
3974 virtual bool gate (function *);
3975 virtual unsigned int execute (function *)
3977 split_all_insns ();
3978 return 0;
3981 }; // class pass_split_before_regstack
3983 bool
3984 pass_split_before_regstack::gate (function *)
3986 #if HAVE_ATTR_length && defined (STACK_REGS)
3987 /* If flow2 creates new instructions which need splitting
3988 and scheduling after reload is not done, they might not be
3989 split until final which doesn't allow splitting
3990 if HAVE_ATTR_length. */
3991 # ifdef INSN_SCHEDULING
3992 return (optimize && !flag_schedule_insns_after_reload);
3993 # else
3994 return (optimize);
3995 # endif
3996 #else
3997 return 0;
3998 #endif
4001 } // anon namespace
4003 rtl_opt_pass *
4004 make_pass_split_before_regstack (gcc::context *ctxt)
4006 return new pass_split_before_regstack (ctxt);
4009 static unsigned int
4010 rest_of_handle_split_before_sched2 (void)
4012 #ifdef INSN_SCHEDULING
4013 split_all_insns ();
4014 #endif
4015 return 0;
4018 namespace {
4020 const pass_data pass_data_split_before_sched2 =
4022 RTL_PASS, /* type */
4023 "split4", /* name */
4024 OPTGROUP_NONE, /* optinfo_flags */
4025 TV_NONE, /* tv_id */
4026 0, /* properties_required */
4027 0, /* properties_provided */
4028 0, /* properties_destroyed */
4029 0, /* todo_flags_start */
4030 0, /* todo_flags_finish */
4033 class pass_split_before_sched2 : public rtl_opt_pass
4035 public:
4036 pass_split_before_sched2 (gcc::context *ctxt)
4037 : rtl_opt_pass (pass_data_split_before_sched2, ctxt)
4040 /* opt_pass methods: */
4041 virtual bool gate (function *)
4043 #ifdef INSN_SCHEDULING
4044 return optimize > 0 && flag_schedule_insns_after_reload;
4045 #else
4046 return false;
4047 #endif
4050 virtual unsigned int execute (function *)
4052 return rest_of_handle_split_before_sched2 ();
4055 }; // class pass_split_before_sched2
4057 } // anon namespace
4059 rtl_opt_pass *
4060 make_pass_split_before_sched2 (gcc::context *ctxt)
4062 return new pass_split_before_sched2 (ctxt);
4065 namespace {
4067 const pass_data pass_data_split_for_shorten_branches =
4069 RTL_PASS, /* type */
4070 "split5", /* name */
4071 OPTGROUP_NONE, /* optinfo_flags */
4072 TV_NONE, /* tv_id */
4073 0, /* properties_required */
4074 0, /* properties_provided */
4075 0, /* properties_destroyed */
4076 0, /* todo_flags_start */
4077 0, /* todo_flags_finish */
4080 class pass_split_for_shorten_branches : public rtl_opt_pass
4082 public:
4083 pass_split_for_shorten_branches (gcc::context *ctxt)
4084 : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt)
4087 /* opt_pass methods: */
4088 virtual bool gate (function *)
4090 /* The placement of the splitting that we do for shorten_branches
4091 depends on whether regstack is used by the target or not. */
4092 #if HAVE_ATTR_length && !defined (STACK_REGS)
4093 return true;
4094 #else
4095 return false;
4096 #endif
4099 virtual unsigned int execute (function *)
4101 return split_all_insns_noflow ();
4104 }; // class pass_split_for_shorten_branches
4106 } // anon namespace
4108 rtl_opt_pass *
4109 make_pass_split_for_shorten_branches (gcc::context *ctxt)
4111 return new pass_split_for_shorten_branches (ctxt);
4114 /* (Re)initialize the target information after a change in target. */
4116 void
4117 recog_init ()
4119 /* The information is zero-initialized, so we don't need to do anything
4120 first time round. */
4121 if (!this_target_recog->x_initialized)
4123 this_target_recog->x_initialized = true;
4124 return;
4126 memset (this_target_recog->x_bool_attr_masks, 0,
4127 sizeof (this_target_recog->x_bool_attr_masks));
4128 for (unsigned int i = 0; i < NUM_INSN_CODES; ++i)
4129 if (this_target_recog->x_op_alt[i])
4131 free (this_target_recog->x_op_alt[i]);
4132 this_target_recog->x_op_alt[i] = 0;