1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
44 /* 1 if the caller has placed an "unimp" insn immediately after the call.
45 This is used in v8 code when calling a function that returns a structure.
46 v9 doesn't have this. Be careful to have this test be the same as that
49 #define SKIP_CALLERS_UNIMP_P \
50 (!TARGET_ARCH64 && current_function_returns_struct \
51 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
52 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
55 /* Global variables for machine-dependent things. */
57 /* Size of frame. Need to know this to emit return insns from leaf procedures.
58 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
59 reload pass. This is important as the value is later used in insn
60 scheduling (to see what can go in a delay slot).
61 APPARENT_FSIZE is the size of the stack less the register save area and less
62 the outgoing argument area. It is used when saving call preserved regs. */
63 static int apparent_fsize
;
64 static int actual_fsize
;
66 /* Number of live general or floating point registers needed to be saved
67 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
68 static int num_gfregs
;
70 /* Save the operands last given to a compare for use when we
71 generate a scc or bcc insn. */
73 rtx sparc_compare_op0
, sparc_compare_op1
;
75 /* We may need an epilogue if we spill too many registers.
76 If this is non-zero, then we branch here for the epilogue. */
77 static rtx leaf_label
;
81 /* Vector to say how input registers are mapped to output
82 registers. FRAME_POINTER_REGNUM cannot be remapped by
83 this function to eliminate it. You must use -fomit-frame-pointer
85 char leaf_reg_remap
[] =
86 { 0, 1, 2, 3, 4, 5, 6, 7,
87 -1, -1, -1, -1, -1, -1, 14, -1,
88 -1, -1, -1, -1, -1, -1, -1, -1,
89 8, 9, 10, 11, 12, 13, -1, 15,
91 32, 33, 34, 35, 36, 37, 38, 39,
92 40, 41, 42, 43, 44, 45, 46, 47,
93 48, 49, 50, 51, 52, 53, 54, 55,
94 56, 57, 58, 59, 60, 61, 62, 63,
95 64, 65, 66, 67, 68, 69, 70, 71,
96 72, 73, 74, 75, 76, 77, 78, 79,
97 80, 81, 82, 83, 84, 85, 86, 87,
98 88, 89, 90, 91, 92, 93, 94, 95,
103 /* Name of where we pretend to think the frame pointer points.
104 Normally, this is "%fp", but if we are in a leaf procedure,
105 this is "%sp+something". We record "something" separately as it may be
106 too big for reg+constant addressing. */
108 static const char *frame_base_name
;
109 static int frame_base_offset
;
111 static rtx pic_setup_code
PROTO((void));
112 static void sparc_init_modes
PROTO((void));
113 static int save_regs
PROTO((FILE *, int, int, const char *,
115 static int restore_regs
PROTO((FILE *, int, int, const char *, int, int));
116 static void build_big_number
PROTO((FILE *, int, const char *));
117 static int function_arg_slotno
PROTO((const CUMULATIVE_ARGS
*,
118 enum machine_mode
, tree
, int, int,
121 static int supersparc_adjust_cost
PROTO((rtx
, rtx
, rtx
, int));
122 static int hypersparc_adjust_cost
PROTO((rtx
, rtx
, rtx
, int));
123 static int ultrasparc_adjust_cost
PROTO((rtx
, rtx
, rtx
, int));
125 static void sparc_output_addr_vec
PROTO((rtx
));
126 static void sparc_output_addr_diff_vec
PROTO((rtx
));
127 static void sparc_output_deferred_case_vectors
PROTO((void));
128 static void sparc_add_gc_roots
PROTO ((void));
129 static void mark_ultrasparc_pipeline_state
PROTO ((void *));
130 static int check_return_regs
PROTO ((rtx
));
131 static int epilogue_renumber
PROTO ((rtx
*, int));
132 static int ultra_cmove_results_ready_p
PROTO ((rtx
));
133 static int ultra_fpmode_conflict_exists
PROTO ((enum machine_mode
));
134 static rtx
*ultra_find_type
PROTO ((int, rtx
*, int));
135 static void ultra_build_types_avail
PROTO ((rtx
*, int));
136 static void ultra_flush_pipeline
PROTO ((void));
137 static void ultra_rescan_pipeline_state
PROTO ((rtx
*, int));
138 static int set_extends
PROTO ((rtx
, rtx
));
140 /* Option handling. */
142 /* Code model option as passed by user. */
143 const char *sparc_cmodel_string
;
145 enum cmodel sparc_cmodel
;
147 char sparc_hard_reg_printed
[8];
149 struct sparc_cpu_select sparc_select
[] =
151 /* switch name, tune arch */
152 { (char *)0, "default", 1, 1 },
153 { (char *)0, "-mcpu=", 1, 1 },
154 { (char *)0, "-mtune=", 1, 0 },
158 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
159 enum processor_type sparc_cpu
;
161 /* Validate and override various options, and do some machine dependent
165 sparc_override_options ()
167 static struct code_model
{
172 { "medlow", CM_MEDLOW
},
173 { "medmid", CM_MEDMID
},
174 { "medany", CM_MEDANY
},
175 { "embmedany", CM_EMBMEDANY
},
178 struct code_model
*cmodel
;
179 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
180 static struct cpu_default
{
184 /* There must be one entry here for each TARGET_CPU value. */
185 { TARGET_CPU_sparc
, "cypress" },
186 { TARGET_CPU_sparclet
, "tsc701" },
187 { TARGET_CPU_sparclite
, "f930" },
188 { TARGET_CPU_v8
, "v8" },
189 { TARGET_CPU_hypersparc
, "hypersparc" },
190 { TARGET_CPU_sparclite86x
, "sparclite86x" },
191 { TARGET_CPU_supersparc
, "supersparc" },
192 { TARGET_CPU_v9
, "v9" },
193 { TARGET_CPU_ultrasparc
, "ultrasparc" },
196 struct cpu_default
*def
;
197 /* Table of values for -m{cpu,tune}=. */
198 static struct cpu_table
{
200 enum processor_type processor
;
204 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
205 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
206 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
207 /* TI TMS390Z55 supersparc */
208 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
209 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
210 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
211 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
212 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
213 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
214 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
215 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
217 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
219 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
220 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
221 /* TI ultrasparc I, II, IIi */
222 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
223 /* Although insns using %y are deprecated, it is a clear win on current
225 |MASK_DEPRECATED_V8_INSNS
},
228 struct cpu_table
*cpu
;
229 struct sparc_cpu_select
*sel
;
232 #ifndef SPARC_BI_ARCH
233 /* Check for unsupported architecture size. */
234 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
236 error ("%s is not supported by this configuration",
237 DEFAULT_ARCH32_P
? "-m64" : "-m32");
241 /* At the moment we don't allow different pointer size and architecture */
242 if (! TARGET_64BIT
!= ! TARGET_PTR64
)
244 error ("-mptr%d not allowed on -m%d",
245 TARGET_PTR64
? 64 : 32, TARGET_64BIT
? 64 : 32);
247 target_flags
|= MASK_PTR64
;
249 target_flags
&= ~MASK_PTR64
;
252 /* Code model selection. */
253 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
257 sparc_cmodel
= CM_32
;
260 if (sparc_cmodel_string
!= NULL
)
264 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
265 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
267 if (cmodel
->name
== NULL
)
268 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
270 sparc_cmodel
= cmodel
->value
;
273 error ("-mcmodel= is not supported on 32 bit systems");
276 fpu
= TARGET_FPU
; /* save current -mfpu status */
278 /* Set the default CPU. */
279 for (def
= &cpu_default
[0]; def
->name
; ++def
)
280 if (def
->cpu
== TARGET_CPU_DEFAULT
)
284 sparc_select
[0].string
= def
->name
;
286 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
290 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
291 if (! strcmp (sel
->string
, cpu
->name
))
294 sparc_cpu
= cpu
->processor
;
298 target_flags
&= ~cpu
->disable
;
299 target_flags
|= cpu
->enable
;
305 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
309 /* If -mfpu or -mno-fpu was explicitly used, don't override with
310 the processor default. Clear MASK_FPU_SET to avoid confusing
311 the reverse mapping from switch values to names. */
314 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
315 target_flags
&= ~MASK_FPU_SET
;
318 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
319 if (TARGET_V9
&& TARGET_ARCH32
)
320 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
322 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
323 if (! TARGET_V9
|| TARGET_ARCH64
)
324 target_flags
&= ~MASK_V8PLUS
;
326 /* Don't use stack biasing in 32 bit mode. */
328 target_flags
&= ~MASK_STACK_BIAS
;
330 /* Don't allow -mvis if FPU is disabled. */
332 target_flags
&= ~MASK_VIS
;
334 /* Supply a default value for align_functions. */
335 if (align_functions
== 0 && sparc_cpu
== PROCESSOR_ULTRASPARC
)
336 align_functions
= 32;
338 /* Validate PCC_STRUCT_RETURN. */
339 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
340 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
342 /* Do various machine dependent initializations. */
345 if ((profile_flag
|| profile_block_flag
)
346 && sparc_cmodel
!= CM_MEDLOW
)
348 error ("profiling does not support code models other than medlow");
351 /* Register global variables with the garbage collector. */
352 sparc_add_gc_roots ();
355 /* Miscellaneous utilities. */
357 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
358 or branch on register contents instructions. */
364 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
365 || code
== LE
|| code
== GT
);
369 /* Operand constraints. */
371 /* Return non-zero only if OP is a register of mode MODE,
372 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
373 %g0 may contain anything. */
376 reg_or_0_operand (op
, mode
)
378 enum machine_mode mode
;
380 if (register_operand (op
, mode
))
384 if (op
== const0_rtx
)
386 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
387 && CONST_DOUBLE_HIGH (op
) == 0
388 && CONST_DOUBLE_LOW (op
) == 0)
390 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
391 && GET_CODE (op
) == CONST_DOUBLE
392 && fp_zero_operand (op
))
397 /* Nonzero if OP is a floating point value with value 0.0. */
405 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
406 return (REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
));
409 /* Nonzero if OP is an integer register. */
412 intreg_operand (op
, mode
)
414 enum machine_mode mode ATTRIBUTE_UNUSED
;
416 return (register_operand (op
, SImode
)
417 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
420 /* Nonzero if OP is a floating point condition code register. */
423 fcc_reg_operand (op
, mode
)
425 enum machine_mode mode
;
427 /* This can happen when recog is called from combine. Op may be a MEM.
428 Fail instead of calling abort in this case. */
429 if (GET_CODE (op
) != REG
)
432 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
435 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
438 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
439 if (reg_renumber
== 0)
440 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
441 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
443 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
447 /* Nonzero if OP is an integer or floating point condition code register. */
450 icc_or_fcc_reg_operand (op
, mode
)
452 enum machine_mode mode
;
454 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
456 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
459 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
464 return fcc_reg_operand (op
, mode
);
467 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
469 restore_operand (op
, mode
)
471 enum machine_mode mode
;
473 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
474 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
477 /* Call insn on SPARC can take a PC-relative constant address, or any regular
481 call_operand (op
, mode
)
483 enum machine_mode mode
;
485 if (GET_CODE (op
) != MEM
)
488 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
492 call_operand_address (op
, mode
)
494 enum machine_mode mode
;
496 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
499 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
500 reference and a constant. */
503 symbolic_operand (op
, mode
)
505 enum machine_mode mode
;
507 enum machine_mode omode
= GET_MODE (op
);
509 if (omode
!= mode
&& omode
!= VOIDmode
&& mode
!= VOIDmode
)
512 switch (GET_CODE (op
))
520 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
521 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
522 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
529 /* Return truth value of statement that OP is a symbolic memory
530 operand of mode MODE. */
533 symbolic_memory_operand (op
, mode
)
535 enum machine_mode mode ATTRIBUTE_UNUSED
;
537 if (GET_CODE (op
) == SUBREG
)
538 op
= SUBREG_REG (op
);
539 if (GET_CODE (op
) != MEM
)
542 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
543 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
546 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
549 label_ref_operand (op
, mode
)
551 enum machine_mode mode
;
553 if (GET_CODE (op
) != LABEL_REF
)
555 if (GET_MODE (op
) != mode
)
560 /* Return 1 if the operand is an argument used in generating pic references
561 in either the medium/low or medium/anywhere code models of sparc64. */
564 sp64_medium_pic_operand (op
, mode
)
566 enum machine_mode mode ATTRIBUTE_UNUSED
;
568 /* Check for (const (minus (symbol_ref:GOT)
569 (const (minus (label) (pc))))). */
570 if (GET_CODE (op
) != CONST
)
573 if (GET_CODE (op
) != MINUS
)
575 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
577 /* ??? Ensure symbol is GOT. */
578 if (GET_CODE (XEXP (op
, 1)) != CONST
)
580 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
585 /* Return 1 if the operand is a data segment reference. This includes
586 the readonly data segment, or in other words anything but the text segment.
587 This is needed in the medium/anywhere code model on v9. These values
588 are accessed with EMBMEDANY_BASE_REG. */
591 data_segment_operand (op
, mode
)
593 enum machine_mode mode ATTRIBUTE_UNUSED
;
595 switch (GET_CODE (op
))
598 return ! SYMBOL_REF_FLAG (op
);
600 /* Assume canonical format of symbol + constant.
603 return data_segment_operand (XEXP (op
, 0), VOIDmode
);
609 /* Return 1 if the operand is a text segment reference.
610 This is needed in the medium/anywhere code model on v9. */
613 text_segment_operand (op
, mode
)
615 enum machine_mode mode ATTRIBUTE_UNUSED
;
617 switch (GET_CODE (op
))
622 return SYMBOL_REF_FLAG (op
);
624 /* Assume canonical format of symbol + constant.
627 return text_segment_operand (XEXP (op
, 0), VOIDmode
);
633 /* Return 1 if the operand is either a register or a memory operand that is
637 reg_or_nonsymb_mem_operand (op
, mode
)
639 enum machine_mode mode
;
641 if (register_operand (op
, mode
))
644 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
651 splittable_symbolic_memory_operand (op
, mode
)
653 enum machine_mode mode ATTRIBUTE_UNUSED
;
655 if (GET_CODE (op
) != MEM
)
657 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
663 splittable_immediate_memory_operand (op
, mode
)
665 enum machine_mode mode ATTRIBUTE_UNUSED
;
667 if (GET_CODE (op
) != MEM
)
669 if (! immediate_operand (XEXP (op
, 0), Pmode
))
674 /* Return truth value of whether OP is EQ or NE. */
679 enum machine_mode mode ATTRIBUTE_UNUSED
;
681 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
684 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
685 or LTU for non-floating-point. We handle those specially. */
688 normal_comp_operator (op
, mode
)
690 enum machine_mode mode ATTRIBUTE_UNUSED
;
692 enum rtx_code code
= GET_CODE (op
);
694 if (GET_RTX_CLASS (code
) != '<')
697 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
698 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
701 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
704 /* Return 1 if this is a comparison operator. This allows the use of
705 MATCH_OPERATOR to recognize all the branch insns. */
708 noov_compare_op (op
, mode
)
710 enum machine_mode mode ATTRIBUTE_UNUSED
;
712 enum rtx_code code
= GET_CODE (op
);
714 if (GET_RTX_CLASS (code
) != '<')
717 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
)
718 /* These are the only branches which work with CC_NOOVmode. */
719 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
723 /* Nonzero if OP is a comparison operator suitable for use in v9
724 conditional move or branch on register contents instructions. */
727 v9_regcmp_op (op
, mode
)
729 enum machine_mode mode ATTRIBUTE_UNUSED
;
731 enum rtx_code code
= GET_CODE (op
);
733 if (GET_RTX_CLASS (code
) != '<')
736 return v9_regcmp_p (code
);
739 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
744 enum machine_mode mode ATTRIBUTE_UNUSED
;
746 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
749 /* Return nonzero if OP is an operator of mode MODE which can set
750 the condition codes explicitly. We do not include PLUS and MINUS
751 because these require CC_NOOVmode, which we handle explicitly. */
754 cc_arithop (op
, mode
)
756 enum machine_mode mode ATTRIBUTE_UNUSED
;
758 if (GET_CODE (op
) == AND
759 || GET_CODE (op
) == IOR
760 || GET_CODE (op
) == XOR
)
766 /* Return nonzero if OP is an operator of mode MODE which can bitwise
767 complement its second operand and set the condition codes explicitly. */
770 cc_arithopn (op
, mode
)
772 enum machine_mode mode ATTRIBUTE_UNUSED
;
774 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
775 and (xor ... (not ...)) to (not (xor ...)). */
776 return (GET_CODE (op
) == AND
777 || GET_CODE (op
) == IOR
);
780 /* Return true if OP is a register, or is a CONST_INT that can fit in a
781 signed 13 bit immediate field. This is an acceptable SImode operand for
782 most 3 address instructions. */
785 arith_operand (op
, mode
)
787 enum machine_mode mode
;
790 if (register_operand (op
, mode
))
792 if (GET_CODE (op
) != CONST_INT
)
794 val
= INTVAL (op
) & 0xffffffff;
795 return SPARC_SIMM13_P (val
);
798 /* Return true if OP is a constant 4096 */
801 arith_4096_operand (op
, mode
)
803 enum machine_mode mode ATTRIBUTE_UNUSED
;
806 if (GET_CODE (op
) != CONST_INT
)
808 val
= INTVAL (op
) & 0xffffffff;
812 /* Return true if OP is suitable as second operand for add/sub */
815 arith_add_operand (op
, mode
)
817 enum machine_mode mode
;
819 return arith_operand (op
, mode
) || arith_4096_operand (op
, mode
);
822 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
823 immediate field of OR and XOR instructions. Used for 64-bit
824 constant formation patterns. */
826 const64_operand (op
, mode
)
828 enum machine_mode mode ATTRIBUTE_UNUSED
;
830 return ((GET_CODE (op
) == CONST_INT
831 && SPARC_SIMM13_P (INTVAL (op
)))
832 #if HOST_BITS_PER_WIDE_INT != 64
833 || (GET_CODE (op
) == CONST_DOUBLE
834 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
835 && (CONST_DOUBLE_HIGH (op
) ==
836 ((CONST_DOUBLE_LOW (op
) & 0x80000000) != 0 ?
837 (HOST_WIDE_INT
)0xffffffff : 0)))
842 /* The same, but only for sethi instructions. */
844 const64_high_operand (op
, mode
)
846 enum machine_mode mode ATTRIBUTE_UNUSED
;
848 return ((GET_CODE (op
) == CONST_INT
849 && (INTVAL (op
) & 0xfffffc00) != 0
850 && SPARC_SETHI_P (INTVAL (op
))
851 #if HOST_BITS_PER_WIDE_INT != 64
852 /* Must be positive on non-64bit host else the
853 optimizer is fooled into thinking that sethi
854 sign extends, even though it does not. */
858 || (GET_CODE (op
) == CONST_DOUBLE
859 && CONST_DOUBLE_HIGH (op
) == 0
860 && (CONST_DOUBLE_LOW (op
) & 0xfffffc00) != 0
861 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
))));
864 /* Return true if OP is a register, or is a CONST_INT that can fit in a
865 signed 11 bit immediate field. This is an acceptable SImode operand for
866 the movcc instructions. */
869 arith11_operand (op
, mode
)
871 enum machine_mode mode
;
873 return (register_operand (op
, mode
)
874 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
877 /* Return true if OP is a register, or is a CONST_INT that can fit in a
878 signed 10 bit immediate field. This is an acceptable SImode operand for
879 the movrcc instructions. */
882 arith10_operand (op
, mode
)
884 enum machine_mode mode
;
886 return (register_operand (op
, mode
)
887 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
890 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
891 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
893 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
894 can fit in a 13 bit immediate field. This is an acceptable DImode operand
895 for most 3 address instructions. */
898 arith_double_operand (op
, mode
)
900 enum machine_mode mode
;
902 return (register_operand (op
, mode
)
903 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
905 && GET_CODE (op
) == CONST_DOUBLE
906 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
907 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
909 && GET_CODE (op
) == CONST_DOUBLE
910 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
911 && ((CONST_DOUBLE_HIGH (op
) == -1
912 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
913 || (CONST_DOUBLE_HIGH (op
) == 0
914 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
917 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
920 arith_double_4096_operand (op
, mode
)
922 enum machine_mode mode ATTRIBUTE_UNUSED
;
924 return (TARGET_ARCH64
&&
925 ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 4096) ||
926 (GET_CODE (op
) == CONST_DOUBLE
&&
927 CONST_DOUBLE_LOW (op
) == 4096 &&
928 CONST_DOUBLE_HIGH (op
) == 0)));
931 /* Return true if OP is suitable as second operand for add/sub in DImode */
934 arith_double_add_operand (op
, mode
)
936 enum machine_mode mode
;
938 return arith_double_operand (op
, mode
) || arith_double_4096_operand (op
, mode
);
941 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
942 can fit in an 11 bit immediate field. This is an acceptable DImode
943 operand for the movcc instructions. */
944 /* ??? Replace with arith11_operand? */
947 arith11_double_operand (op
, mode
)
949 enum machine_mode mode
;
951 return (register_operand (op
, mode
)
952 || (GET_CODE (op
) == CONST_DOUBLE
953 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
954 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
955 && ((CONST_DOUBLE_HIGH (op
) == -1
956 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
957 || (CONST_DOUBLE_HIGH (op
) == 0
958 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
959 || (GET_CODE (op
) == CONST_INT
960 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
961 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
964 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
965 can fit in an 10 bit immediate field. This is an acceptable DImode
966 operand for the movrcc instructions. */
967 /* ??? Replace with arith10_operand? */
970 arith10_double_operand (op
, mode
)
972 enum machine_mode mode
;
974 return (register_operand (op
, mode
)
975 || (GET_CODE (op
) == CONST_DOUBLE
976 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
977 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
978 && ((CONST_DOUBLE_HIGH (op
) == -1
979 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
980 || (CONST_DOUBLE_HIGH (op
) == 0
981 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
982 || (GET_CODE (op
) == CONST_INT
983 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
984 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
987 /* Return truth value of whether OP is a integer which fits the
988 range constraining immediate operands in most three-address insns,
989 which have a 13 bit immediate field. */
994 enum machine_mode mode ATTRIBUTE_UNUSED
;
996 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
1000 small_int_or_double (op
, mode
)
1002 enum machine_mode mode ATTRIBUTE_UNUSED
;
1004 return ((GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1005 || (GET_CODE (op
) == CONST_DOUBLE
1006 && CONST_DOUBLE_HIGH (op
) == 0
1007 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))));
1010 /* Recognize operand values for the umul instruction. That instruction sign
1011 extends immediate values just like all other sparc instructions, but
1012 interprets the extended result as an unsigned number. */
1015 uns_small_int (op
, mode
)
1017 enum machine_mode mode ATTRIBUTE_UNUSED
;
1019 #if HOST_BITS_PER_WIDE_INT > 32
1020 /* All allowed constants will fit a CONST_INT. */
1021 return (GET_CODE (op
) == CONST_INT
1022 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
1023 || (INTVAL (op
) >= 0xFFFFF000
1024 && INTVAL (op
) < 0x100000000)));
1026 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
1027 || (GET_CODE (op
) == CONST_DOUBLE
1028 && CONST_DOUBLE_HIGH (op
) == 0
1029 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
1034 uns_arith_operand (op
, mode
)
1036 enum machine_mode mode
;
1038 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
1041 /* Return truth value of statement that OP is a call-clobbered register. */
1043 clobbered_register (op
, mode
)
1045 enum machine_mode mode ATTRIBUTE_UNUSED
;
1047 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
1050 /* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
1053 zero_operand (op
, mode
)
1055 enum machine_mode mode ATTRIBUTE_UNUSED
;
1057 return op
== const0_rtx
;
1060 /* Return 1 if OP is a valid operand for the source of a move insn. */
1063 input_operand (op
, mode
)
1065 enum machine_mode mode
;
1067 /* If both modes are non-void they must be the same. */
1068 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1071 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1072 if (GET_CODE (op
) == CONST
&& GET_CODE (XEXP (op
, 0)) == CONSTANT_P_RTX
)
1075 /* Allow any one instruction integer constant, and all CONST_INT
1076 variants when we are working in DImode and !arch64. */
1077 if (GET_MODE_CLASS (mode
) == MODE_INT
1078 && ((GET_CODE (op
) == CONST_INT
1079 && ((SPARC_SETHI_P (INTVAL (op
))
1081 || (INTVAL (op
) >= 0)
1085 || SPARC_SIMM13_P (INTVAL (op
))
1087 && ! TARGET_ARCH64
)))
1089 && GET_CODE (op
) == CONST_DOUBLE
1090 && ((CONST_DOUBLE_HIGH (op
) == 0
1091 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
)))
1093 #if HOST_BITS_PER_WIDE_INT == 64
1094 (CONST_DOUBLE_HIGH (op
) == 0
1095 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
)))
1097 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1098 && (((CONST_DOUBLE_LOW (op
) & 0x80000000) == 0
1099 && CONST_DOUBLE_HIGH (op
) == 0)
1100 || (CONST_DOUBLE_HIGH (op
) == -1)))
1105 /* If !arch64 and this is a DImode const, allow it so that
1106 the splits can be generated. */
1109 && GET_CODE (op
) == CONST_DOUBLE
)
1112 if (register_operand (op
, mode
))
1115 /* If this is a SUBREG, look inside so that we handle
1116 paradoxical ones. */
1117 if (GET_CODE (op
) == SUBREG
)
1118 op
= SUBREG_REG (op
);
1120 /* Check for valid MEM forms. */
1121 if (GET_CODE (op
) == MEM
)
1123 rtx inside
= XEXP (op
, 0);
1125 if (GET_CODE (inside
) == LO_SUM
)
1127 /* We can't allow these because all of the splits
1128 (eventually as they trickle down into DFmode
1129 splits) require offsettable memory references. */
1131 && GET_MODE (op
) == TFmode
)
1134 return (register_operand (XEXP (inside
, 0), Pmode
)
1135 && CONSTANT_P (XEXP (inside
, 1)));
1137 return memory_address_p (mode
, inside
);
1144 /* We know it can't be done in one insn when we get here,
1145 the movsi expander guarentees this. */
1147 sparc_emit_set_const32 (op0
, op1
)
1151 enum machine_mode mode
= GET_MODE (op0
);
1154 if (GET_CODE (op1
) == CONST_INT
)
1156 HOST_WIDE_INT value
= INTVAL (op1
);
1158 if (SPARC_SETHI_P (value
)
1159 || SPARC_SIMM13_P (value
))
1163 /* Full 2-insn decomposition is needed. */
1164 if (reload_in_progress
|| reload_completed
)
1167 temp
= gen_reg_rtx (mode
);
1169 if (GET_CODE (op1
) == CONST_INT
)
1171 /* Emit them as real moves instead of a HIGH/LO_SUM,
1172 this way CSE can see everything and reuse intermediate
1173 values if it wants. */
1175 && HOST_BITS_PER_WIDE_INT
!= 64
1176 && (INTVAL (op1
) & 0x80000000) != 0)
1178 emit_insn (gen_rtx_SET (VOIDmode
,
1180 gen_rtx_CONST_DOUBLE (VOIDmode
, const0_rtx
,
1181 INTVAL (op1
) & 0xfffffc00, 0)));
1185 emit_insn (gen_rtx_SET (VOIDmode
,
1187 GEN_INT (INTVAL (op1
) & 0xfffffc00)));
1189 emit_insn (gen_rtx_SET (VOIDmode
,
1193 GEN_INT (INTVAL (op1
) & 0x3ff))));
1197 /* A symbol, emit in the traditional way. */
1198 emit_insn (gen_rtx_SET (VOIDmode
,
1202 emit_insn (gen_rtx_SET (VOIDmode
,
1204 gen_rtx_LO_SUM (mode
,
1212 /* Sparc-v9 code-model support. */
1214 sparc_emit_set_symbolic_const64 (op0
, op1
, temp1
)
1219 switch (sparc_cmodel
)
1222 /* The range spanned by all instructions in the object is less
1223 than 2^31 bytes (2GB) and the distance from any instruction
1224 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1225 than 2^31 bytes (2GB).
1227 The executable must be in the low 4TB of the virtual address
1230 sethi %hi(symbol), %temp
1231 or %temp, %lo(symbol), %reg */
1232 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1233 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1237 /* The range spanned by all instructions in the object is less
1238 than 2^31 bytes (2GB) and the distance from any instruction
1239 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1240 than 2^31 bytes (2GB).
1242 The executable must be in the low 16TB of the virtual address
1245 sethi %h44(symbol), %temp1
1246 or %temp1, %m44(symbol), %temp2
1247 sllx %temp2, 12, %temp3
1248 or %temp3, %l44(symbol), %reg */
1249 emit_insn (gen_seth44 (op0
, op1
));
1250 emit_insn (gen_setm44 (op0
, op0
, op1
));
1251 emit_insn (gen_rtx_SET (VOIDmode
, temp1
,
1252 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (12))));
1253 emit_insn (gen_setl44 (op0
, temp1
, op1
));
1257 /* The range spanned by all instructions in the object is less
1258 than 2^31 bytes (2GB) and the distance from any instruction
1259 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1260 than 2^31 bytes (2GB).
1262 The executable can be placed anywhere in the virtual address
1265 sethi %hh(symbol), %temp1
1266 sethi %lm(symbol), %temp2
1267 or %temp1, %hm(symbol), %temp3
1268 or %temp2, %lo(symbol), %temp4
1269 sllx %temp3, 32, %temp5
1270 or %temp4, %temp5, %reg */
1272 /* Getting this right wrt. reloading is really tricky.
1273 We _MUST_ have a separate temporary at this point,
1274 if we don't barf immediately instead of generating
1279 emit_insn (gen_sethh (op0
, op1
));
1280 emit_insn (gen_setlm (temp1
, op1
));
1281 emit_insn (gen_sethm (op0
, op0
, op1
));
1282 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1283 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1284 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1285 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1286 emit_insn (gen_setlo (op0
, op0
, op1
));
1290 /* Old old old backwards compatibility kruft here.
1291 Essentially it is MEDLOW with a fixed 64-bit
1292 virtual base added to all data segment addresses.
1293 Text-segment stuff is computed like MEDANY, we can't
1294 reuse the code above because the relocation knobs
1297 Data segment: sethi %hi(symbol), %temp1
1298 or %temp1, %lo(symbol), %temp2
1299 add %temp2, EMBMEDANY_BASE_REG, %reg
1301 Text segment: sethi %uhi(symbol), %temp1
1302 sethi %hi(symbol), %temp2
1303 or %temp1, %ulo(symbol), %temp3
1304 or %temp2, %lo(symbol), %temp4
1305 sllx %temp3, 32, %temp5
1306 or %temp4, %temp5, %reg */
1307 if (data_segment_operand (op1
, GET_MODE (op1
)))
1309 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1310 emit_insn (gen_embmedany_brsum (op0
, temp1
));
1311 emit_insn (gen_embmedany_losum (op0
, op0
, op1
));
1315 /* Getting this right wrt. reloading is really tricky.
1316 We _MUST_ have a separate temporary at this point,
1317 so we barf immediately instead of generating
1322 emit_insn (gen_embmedany_textuhi (op0
, op1
));
1323 emit_insn (gen_embmedany_texthi (temp1
, op1
));
1324 emit_insn (gen_embmedany_textulo (op0
, op0
, op1
));
1325 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1326 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1327 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1328 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1329 emit_insn (gen_embmedany_textlo (op0
, op0
, op1
));
1338 /* These avoid problems when cross compiling. If we do not
1339 go through all this hair then the optimizer will see
1340 invalid REG_EQUAL notes or in some cases none at all. */
1341 static void sparc_emit_set_safe_HIGH64
PROTO ((rtx
, HOST_WIDE_INT
));
1342 static rtx gen_safe_SET64
PROTO ((rtx
, HOST_WIDE_INT
));
1343 static rtx gen_safe_OR64
PROTO ((rtx
, HOST_WIDE_INT
));
1344 static rtx gen_safe_XOR64
PROTO ((rtx
, HOST_WIDE_INT
));
1346 #if HOST_BITS_PER_WIDE_INT == 64
1347 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1348 #define GEN_INT64(__x) GEN_INT (__x)
1350 #define GEN_HIGHINT64(__x) \
1351 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1352 (__x) & 0xfffffc00, 0)
1353 #define GEN_INT64(__x) \
1354 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1355 (__x) & 0xffffffff, \
1356 ((__x) & 0x80000000 \
1360 /* The optimizer is not to assume anything about exactly
1361 which bits are set for a HIGH, they are unspecified.
1362 Unfortunately this leads to many missed optimizations
1363 during CSE. We mask out the non-HIGH bits, and matches
1364 a plain movdi, to alleviate this problem. */
1366 sparc_emit_set_safe_HIGH64 (dest
, val
)
1370 emit_insn (gen_rtx_SET (VOIDmode
, dest
, GEN_HIGHINT64 (val
)));
1374 gen_safe_SET64 (dest
, val
)
1378 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT64 (val
));
1382 gen_safe_OR64 (src
, val
)
1386 return gen_rtx_IOR (DImode
, src
, GEN_INT64 (val
));
1390 gen_safe_XOR64 (src
, val
)
1394 return gen_rtx_XOR (DImode
, src
, GEN_INT64 (val
));
1397 /* Worker routines for 64-bit constant formation on arch64.
1398 One of the key things to be doing in these emissions is
1399 to create as many temp REGs as possible. This makes it
1400 possible for half-built constants to be used later when
1401 such values are similar to something required later on.
1402 Without doing this, the optimizer cannot see such
1405 static void sparc_emit_set_const64_quick1
1406 PROTO((rtx
, rtx
, unsigned HOST_WIDE_INT
, int));
1409 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
, is_neg
)
1412 unsigned HOST_WIDE_INT low_bits
;
1415 unsigned HOST_WIDE_INT high_bits
;
1418 high_bits
= (~low_bits
) & 0xffffffff;
1420 high_bits
= low_bits
;
1422 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1425 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1426 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1430 /* If we are XOR'ing with -1, then we should emit a one's complement
1431 instead. This way the combiner will notice logical operations
1432 such as ANDN later on and substitute. */
1433 if ((low_bits
& 0x3ff) == 0x3ff)
1435 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1436 gen_rtx_NOT (DImode
, temp
)));
1440 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1441 gen_safe_XOR64 (temp
,
1442 (-0x400 | (low_bits
& 0x3ff)))));
1447 static void sparc_emit_set_const64_quick2
1448 PROTO((rtx
, rtx
, unsigned HOST_WIDE_INT
,
1449 unsigned HOST_WIDE_INT
, int));
1452 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_immediate
, shift_count
)
1455 unsigned HOST_WIDE_INT high_bits
;
1456 unsigned HOST_WIDE_INT low_immediate
;
1461 if ((high_bits
& 0xfffffc00) != 0)
1463 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1464 if ((high_bits
& ~0xfffffc00) != 0)
1465 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1466 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1472 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1476 /* Now shift it up into place. */
1477 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1478 gen_rtx_ASHIFT (DImode
, temp2
,
1479 GEN_INT (shift_count
))));
1481 /* If there is a low immediate part piece, finish up by
1482 putting that in as well. */
1483 if (low_immediate
!= 0)
1484 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1485 gen_safe_OR64 (op0
, low_immediate
)));
1488 static void sparc_emit_set_const64_longway
1489 PROTO((rtx
, rtx
, unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1491 /* Full 64-bit constant decomposition. Even though this is the
1492 'worst' case, we still optimize a few things away. */
1494 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
)
1497 unsigned HOST_WIDE_INT high_bits
;
1498 unsigned HOST_WIDE_INT low_bits
;
1502 if (reload_in_progress
|| reload_completed
)
1505 sub_temp
= gen_reg_rtx (DImode
);
1507 if ((high_bits
& 0xfffffc00) != 0)
1509 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1510 if ((high_bits
& ~0xfffffc00) != 0)
1511 emit_insn (gen_rtx_SET (VOIDmode
,
1513 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1519 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1523 if (!reload_in_progress
&& !reload_completed
)
1525 rtx temp2
= gen_reg_rtx (DImode
);
1526 rtx temp3
= gen_reg_rtx (DImode
);
1527 rtx temp4
= gen_reg_rtx (DImode
);
1529 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1530 gen_rtx_ASHIFT (DImode
, sub_temp
,
1533 sparc_emit_set_safe_HIGH64 (temp2
, low_bits
);
1534 if ((low_bits
& ~0xfffffc00) != 0)
1536 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1537 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1538 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1539 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1543 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1544 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1549 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1550 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1551 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1554 /* We are in the middle of reload, so this is really
1555 painful. However we do still make an attempt to
1556 avoid emitting truly stupid code. */
1557 if (low1
!= const0_rtx
)
1559 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1560 gen_rtx_ASHIFT (DImode
, sub_temp
,
1561 GEN_INT (to_shift
))));
1562 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1563 gen_rtx_IOR (DImode
, op0
, low1
)));
1571 if (low2
!= const0_rtx
)
1573 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1574 gen_rtx_ASHIFT (DImode
, sub_temp
,
1575 GEN_INT (to_shift
))));
1576 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1577 gen_rtx_IOR (DImode
, op0
, low2
)));
1585 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1586 gen_rtx_ASHIFT (DImode
, sub_temp
,
1587 GEN_INT (to_shift
))));
1588 if (low3
!= const0_rtx
)
1589 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1590 gen_rtx_IOR (DImode
, op0
, low3
)));
1595 /* Analyze a 64-bit constant for certain properties. */
1596 static void analyze_64bit_constant
1597 PROTO((unsigned HOST_WIDE_INT
,
1598 unsigned HOST_WIDE_INT
,
1599 int *, int *, int *));
1602 analyze_64bit_constant (high_bits
, low_bits
, hbsp
, lbsp
, abbasp
)
1603 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1604 int *hbsp
, *lbsp
, *abbasp
;
1606 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1609 lowest_bit_set
= highest_bit_set
= -1;
1613 if ((lowest_bit_set
== -1)
1614 && ((low_bits
>> i
) & 1))
1616 if ((highest_bit_set
== -1)
1617 && ((high_bits
>> (32 - i
- 1)) & 1))
1618 highest_bit_set
= (64 - i
- 1);
1621 && ((highest_bit_set
== -1)
1622 || (lowest_bit_set
== -1)));
1628 if ((lowest_bit_set
== -1)
1629 && ((high_bits
>> i
) & 1))
1630 lowest_bit_set
= i
+ 32;
1631 if ((highest_bit_set
== -1)
1632 && ((low_bits
>> (32 - i
- 1)) & 1))
1633 highest_bit_set
= 32 - i
- 1;
1636 && ((highest_bit_set
== -1)
1637 || (lowest_bit_set
== -1)));
1639 /* If there are no bits set this should have gone out
1640 as one instruction! */
1641 if (lowest_bit_set
== -1
1642 || highest_bit_set
== -1)
1644 all_bits_between_are_set
= 1;
1645 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1649 if ((low_bits
& (1 << i
)) != 0)
1654 if ((high_bits
& (1 << (i
- 32))) != 0)
1657 all_bits_between_are_set
= 0;
1660 *hbsp
= highest_bit_set
;
1661 *lbsp
= lowest_bit_set
;
1662 *abbasp
= all_bits_between_are_set
;
1665 static int const64_is_2insns
1666 PROTO((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1669 const64_is_2insns (high_bits
, low_bits
)
1670 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1672 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1675 || high_bits
== 0xffffffff)
1678 analyze_64bit_constant (high_bits
, low_bits
,
1679 &highest_bit_set
, &lowest_bit_set
,
1680 &all_bits_between_are_set
);
1682 if ((highest_bit_set
== 63
1683 || lowest_bit_set
== 0)
1684 && all_bits_between_are_set
!= 0)
1687 if ((highest_bit_set
- lowest_bit_set
) < 21)
1693 static unsigned HOST_WIDE_INT create_simple_focus_bits
1694 PROTO((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
,
1697 static unsigned HOST_WIDE_INT
1698 create_simple_focus_bits (high_bits
, low_bits
, lowest_bit_set
, shift
)
1699 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1700 int lowest_bit_set
, shift
;
1702 HOST_WIDE_INT hi
, lo
;
1704 if (lowest_bit_set
< 32)
1706 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1707 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1712 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1719 /* Here we are sure to be arch64 and this is an integer constant
1720 being loaded into a register. Emit the most efficient
1721 insn sequence possible. Detection of all the 1-insn cases
1722 has been done already. */
1724 sparc_emit_set_const64 (op0
, op1
)
1728 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1729 int lowest_bit_set
, highest_bit_set
;
1730 int all_bits_between_are_set
;
1733 /* Sanity check that we know what we are working with. */
1735 || GET_CODE (op0
) != REG
1736 || (REGNO (op0
) >= SPARC_FIRST_FP_REG
1737 && REGNO (op0
) <= SPARC_LAST_V9_FP_REG
))
1740 if (reload_in_progress
|| reload_completed
)
1743 temp
= gen_reg_rtx (DImode
);
1745 if (GET_CODE (op1
) != CONST_DOUBLE
1746 && GET_CODE (op1
) != CONST_INT
)
1748 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1752 if (GET_CODE (op1
) == CONST_DOUBLE
)
1754 #if HOST_BITS_PER_WIDE_INT == 64
1755 high_bits
= (CONST_DOUBLE_LOW (op1
) >> 32) & 0xffffffff;
1756 low_bits
= CONST_DOUBLE_LOW (op1
) & 0xffffffff;
1758 high_bits
= CONST_DOUBLE_HIGH (op1
);
1759 low_bits
= CONST_DOUBLE_LOW (op1
);
1764 #if HOST_BITS_PER_WIDE_INT == 64
1765 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1766 low_bits
= (INTVAL (op1
) & 0xffffffff);
1768 high_bits
= ((INTVAL (op1
) < 0) ?
1771 low_bits
= INTVAL (op1
);
1775 /* low_bits bits 0 --> 31
1776 high_bits bits 32 --> 63 */
1778 analyze_64bit_constant (high_bits
, low_bits
,
1779 &highest_bit_set
, &lowest_bit_set
,
1780 &all_bits_between_are_set
);
1782 /* First try for a 2-insn sequence. */
1784 /* These situations are preferred because the optimizer can
1785 * do more things with them:
1787 * sllx %reg, shift, %reg
1789 * srlx %reg, shift, %reg
1790 * 3) mov some_small_const, %reg
1791 * sllx %reg, shift, %reg
1793 if (((highest_bit_set
== 63
1794 || lowest_bit_set
== 0)
1795 && all_bits_between_are_set
!= 0)
1796 || ((highest_bit_set
- lowest_bit_set
) < 12))
1798 HOST_WIDE_INT the_const
= -1;
1799 int shift
= lowest_bit_set
;
1801 if ((highest_bit_set
!= 63
1802 && lowest_bit_set
!= 0)
1803 || all_bits_between_are_set
== 0)
1806 create_simple_focus_bits (high_bits
, low_bits
,
1809 else if (lowest_bit_set
== 0)
1810 shift
= -(63 - highest_bit_set
);
1812 if (! SPARC_SIMM13_P (the_const
))
1815 emit_insn (gen_safe_SET64 (temp
, the_const
));
1817 emit_insn (gen_rtx_SET (VOIDmode
,
1819 gen_rtx_ASHIFT (DImode
,
1823 emit_insn (gen_rtx_SET (VOIDmode
,
1825 gen_rtx_LSHIFTRT (DImode
,
1827 GEN_INT (-shift
))));
1833 /* Now a range of 22 or less bits set somewhere.
1834 * 1) sethi %hi(focus_bits), %reg
1835 * sllx %reg, shift, %reg
1836 * 2) sethi %hi(focus_bits), %reg
1837 * srlx %reg, shift, %reg
1839 if ((highest_bit_set
- lowest_bit_set
) < 21)
1841 unsigned HOST_WIDE_INT focus_bits
=
1842 create_simple_focus_bits (high_bits
, low_bits
,
1843 lowest_bit_set
, 10);
1845 if (! SPARC_SETHI_P (focus_bits
))
1848 sparc_emit_set_safe_HIGH64 (temp
, focus_bits
);
1850 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1851 if (lowest_bit_set
< 10)
1852 emit_insn (gen_rtx_SET (VOIDmode
,
1854 gen_rtx_LSHIFTRT (DImode
, temp
,
1855 GEN_INT (10 - lowest_bit_set
))));
1856 else if (lowest_bit_set
> 10)
1857 emit_insn (gen_rtx_SET (VOIDmode
,
1859 gen_rtx_ASHIFT (DImode
, temp
,
1860 GEN_INT (lowest_bit_set
- 10))));
1866 /* 1) sethi %hi(low_bits), %reg
1867 * or %reg, %lo(low_bits), %reg
1868 * 2) sethi %hi(~low_bits), %reg
1869 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1872 || high_bits
== 0xffffffff)
1874 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1875 (high_bits
== 0xffffffff));
1879 /* Now, try 3-insn sequences. */
1881 /* 1) sethi %hi(high_bits), %reg
1882 * or %reg, %lo(high_bits), %reg
1883 * sllx %reg, 32, %reg
1887 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1891 /* We may be able to do something quick
1892 when the constant is negated, so try that. */
1893 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1894 (~low_bits
) & 0xfffffc00))
1896 /* NOTE: The trailing bits get XOR'd so we need the
1897 non-negated bits, not the negated ones. */
1898 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1900 if ((((~high_bits
) & 0xffffffff) == 0
1901 && ((~low_bits
) & 0x80000000) == 0)
1902 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1903 && ((~low_bits
) & 0x80000000) != 0))
1905 int fast_int
= (~low_bits
& 0xffffffff);
1907 if ((SPARC_SETHI_P (fast_int
)
1908 && (~high_bits
& 0xffffffff) == 0)
1909 || SPARC_SIMM13_P (fast_int
))
1910 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1912 sparc_emit_set_const64 (temp
, GEN_INT64 (fast_int
));
1917 #if HOST_BITS_PER_WIDE_INT == 64
1918 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
1919 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
1921 negated_const
= gen_rtx_CONST_DOUBLE (DImode
, const0_rtx
,
1922 (~low_bits
) & 0xfffffc00,
1923 (~high_bits
) & 0xffffffff);
1925 sparc_emit_set_const64 (temp
, negated_const
);
1928 /* If we are XOR'ing with -1, then we should emit a one's complement
1929 instead. This way the combiner will notice logical operations
1930 such as ANDN later on and substitute. */
1931 if (trailing_bits
== 0x3ff)
1933 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1934 gen_rtx_NOT (DImode
, temp
)));
1938 emit_insn (gen_rtx_SET (VOIDmode
,
1940 gen_safe_XOR64 (temp
,
1941 (-0x400 | trailing_bits
))));
1946 /* 1) sethi %hi(xxx), %reg
1947 * or %reg, %lo(xxx), %reg
1948 * sllx %reg, yyy, %reg
1950 * ??? This is just a generalized version of the low_bits==0
1951 * thing above, FIXME...
1953 if ((highest_bit_set
- lowest_bit_set
) < 32)
1955 unsigned HOST_WIDE_INT focus_bits
=
1956 create_simple_focus_bits (high_bits
, low_bits
,
1959 /* We can't get here in this state. */
1960 if (highest_bit_set
< 32
1961 || lowest_bit_set
>= 32)
1964 /* So what we know is that the set bits straddle the
1965 middle of the 64-bit word. */
1966 sparc_emit_set_const64_quick2 (op0
, temp
,
1972 /* 1) sethi %hi(high_bits), %reg
1973 * or %reg, %lo(high_bits), %reg
1974 * sllx %reg, 32, %reg
1975 * or %reg, low_bits, %reg
1977 if (SPARC_SIMM13_P(low_bits
)
1978 && ((int)low_bits
> 0))
1980 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
1984 /* The easiest way when all else fails, is full decomposition. */
1986 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1987 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
1989 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
1992 /* X and Y are two things to compare using CODE. Emit the compare insn and
1993 return the rtx for the cc reg in the proper mode. */
1996 gen_compare_reg (code
, x
, y
)
2000 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
2003 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2004 fcc regs (cse can't tell they're really call clobbered regs and will
2005 remove a duplicate comparison even if there is an intervening function
2006 call - it will then try to reload the cc reg via an int reg which is why
2007 we need the movcc patterns). It is possible to provide the movcc
2008 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2009 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2010 to tell cse that CCFPE mode registers (even pseudos) are call
2013 /* ??? This is an experiment. Rather than making changes to cse which may
2014 or may not be easy/clean, we do our own cse. This is possible because
2015 we will generate hard registers. Cse knows they're call clobbered (it
2016 doesn't know the same thing about pseudos). If we guess wrong, no big
2017 deal, but if we win, great! */
2019 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2020 #if 1 /* experiment */
2023 /* We cycle through the registers to ensure they're all exercised. */
2024 static int next_fcc_reg
= 0;
2025 /* Previous x,y for each fcc reg. */
2026 static rtx prev_args
[4][2];
2028 /* Scan prev_args for x,y. */
2029 for (reg
= 0; reg
< 4; reg
++)
2030 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2035 prev_args
[reg
][0] = x
;
2036 prev_args
[reg
][1] = y
;
2037 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2039 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2042 cc_reg
= gen_reg_rtx (mode
);
2043 #endif /* ! experiment */
2044 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2045 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2047 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2049 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
2050 gen_rtx_COMPARE (mode
, x
, y
)));
2055 /* This function is used for v9 only.
2056 CODE is the code for an Scc's comparison.
2057 OPERANDS[0] is the target of the Scc insn.
2058 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2059 been generated yet).
2061 This function is needed to turn
2064 (gt (reg:CCX 100 %icc)
2068 (gt:DI (reg:CCX 100 %icc)
2071 IE: The instruction recognizer needs to see the mode of the comparison to
2072 find the right instruction. We could use "gt:DI" right in the
2073 define_expand, but leaving it out allows us to handle DI, SI, etc.
2075 We refer to the global sparc compare operands sparc_compare_op0 and
2076 sparc_compare_op1. */
2079 gen_v9_scc (compare_code
, operands
)
2080 enum rtx_code compare_code
;
2081 register rtx
*operands
;
2086 && (GET_MODE (sparc_compare_op0
) == DImode
2087 || GET_MODE (operands
[0]) == DImode
))
2090 /* Handle the case where operands[0] == sparc_compare_op0.
2091 We "early clobber" the result. */
2092 if (REGNO (operands
[0]) == REGNO (sparc_compare_op0
))
2094 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2095 emit_move_insn (op0
, sparc_compare_op0
);
2098 op0
= sparc_compare_op0
;
2099 /* For consistency in the following. */
2100 op1
= sparc_compare_op1
;
2102 /* Try to use the movrCC insns. */
2104 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
2105 && op1
== const0_rtx
2106 && v9_regcmp_p (compare_code
))
2108 /* Special case for op0 != 0. This can be done with one instruction if
2109 operands[0] == sparc_compare_op0. We don't assume they are equal
2112 if (compare_code
== NE
2113 && GET_MODE (operands
[0]) == DImode
2114 && GET_MODE (op0
) == DImode
)
2116 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], op0
));
2117 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2118 gen_rtx_IF_THEN_ELSE (DImode
,
2119 gen_rtx_fmt_ee (compare_code
, DImode
,
2126 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2127 if (GET_MODE (op0
) != DImode
)
2129 temp
= gen_reg_rtx (DImode
);
2130 convert_move (temp
, op0
, 0);
2134 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2135 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2136 gen_rtx_fmt_ee (compare_code
, DImode
,
2144 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
2146 switch (GET_MODE (operands
[1]))
2156 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2157 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2158 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2159 gen_rtx_fmt_ee (compare_code
,
2160 GET_MODE (operands
[1]),
2161 operands
[1], const0_rtx
),
2162 const1_rtx
, operands
[0])));
2167 /* Emit a conditional jump insn for the v9 architecture using comparison code
2168 CODE and jump target LABEL.
2169 This function exists to take advantage of the v9 brxx insns. */
2172 emit_v9_brxx_insn (code
, op0
, label
)
2176 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2178 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2179 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2181 gen_rtx_LABEL_REF (VOIDmode
, label
),
2185 /* Return nonzero if a return peephole merging return with
2186 setting of output register is ok. */
2188 leaf_return_peephole_ok ()
2190 return (actual_fsize
== 0);
2193 /* Return nonzero if TRIAL can go into the function epilogue's
2194 delay slot. SLOT is the slot we are trying to fill. */
2197 eligible_for_epilogue_delay (trial
, slot
)
2206 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2209 if (get_attr_length (trial
) != 1)
2212 /* If %g0 is live, there are lots of things we can't handle.
2213 Rather than trying to find them all now, let's punt and only
2214 optimize things as necessary. */
2218 /* If there are any call-saved registers, we should scan TRIAL if it
2219 does not reference them. For now just make it easy. */
2223 /* In the case of a true leaf function, anything can go into the delay slot.
2224 A delay slot only exists however if the frame size is zero, otherwise
2225 we will put an insn to adjust the stack after the return. */
2226 if (current_function_uses_only_leaf_regs
)
2228 if (leaf_return_peephole_ok ())
2229 return ((get_attr_in_uncond_branch_delay (trial
)
2230 == IN_BRANCH_DELAY_TRUE
));
2234 /* If only trivial `restore' insns work, nothing can go in the
2236 else if (TARGET_BROKEN_SAVERESTORE
)
2239 pat
= PATTERN (trial
);
2241 /* Otherwise, only operations which can be done in tandem with
2242 a `restore' or `return' insn can go into the delay slot. */
2243 if (GET_CODE (SET_DEST (pat
)) != REG
2244 || REGNO (SET_DEST (pat
)) >= 32
2245 || REGNO (SET_DEST (pat
)) < 24)
2248 /* The set of insns matched here must agree precisely with the set of
2249 patterns paired with a RETURN in sparc.md. */
2251 src
= SET_SRC (pat
);
2253 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2254 if (arith_operand (src
, GET_MODE (src
)))
2257 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2259 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2262 /* This matches "*return_di". */
2263 else if (arith_double_operand (src
, GET_MODE (src
)))
2264 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2266 /* This matches "*return_sf_no_fpu". */
2267 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2268 && register_operand (src
, SFmode
))
2271 /* If we have return instruction, anything that does not use
2272 local or output registers and can go into a delay slot wins. */
2273 else if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2274 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2277 /* This matches "*return_addsi". */
2278 else if (GET_CODE (src
) == PLUS
2279 && arith_operand (XEXP (src
, 0), SImode
)
2280 && arith_operand (XEXP (src
, 1), SImode
)
2281 && (register_operand (XEXP (src
, 0), SImode
)
2282 || register_operand (XEXP (src
, 1), SImode
)))
2285 /* This matches "*return_adddi". */
2286 else if (GET_CODE (src
) == PLUS
2287 && arith_double_operand (XEXP (src
, 0), DImode
)
2288 && arith_double_operand (XEXP (src
, 1), DImode
)
2289 && (register_operand (XEXP (src
, 0), DImode
)
2290 || register_operand (XEXP (src
, 1), DImode
)))
2293 /* This can match "*return_losum_[sd]i".
2294 Catch only some cases, so that return_losum* don't have
2296 else if (GET_CODE (src
) == LO_SUM
2297 && ! TARGET_CM_MEDMID
2298 && ((register_operand (XEXP (src
, 0), SImode
)
2299 && immediate_operand (XEXP (src
, 1), SImode
))
2301 && register_operand (XEXP (src
, 0), DImode
)
2302 && immediate_operand (XEXP (src
, 1), DImode
))))
2305 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2306 else if (GET_CODE (src
) == ASHIFT
2307 && (register_operand (XEXP (src
, 0), SImode
)
2308 || register_operand (XEXP (src
, 0), DImode
))
2309 && XEXP (src
, 1) == const1_rtx
)
2316 check_return_regs (x
)
2319 switch (GET_CODE (x
))
2322 return IN_OR_GLOBAL_P (x
);
2337 if (check_return_regs (XEXP (x
, 1)) == 0)
2342 return check_return_regs (XEXP (x
, 0));
2350 /* Return 1 if TRIAL references only in and global registers. */
2352 eligible_for_return_delay (trial
)
2355 if (GET_CODE (PATTERN (trial
)) != SET
)
2358 return check_return_regs (PATTERN (trial
));
2362 short_branch (uid1
, uid2
)
2365 unsigned int delta
= insn_addresses
[uid1
] - insn_addresses
[uid2
];
2366 if (delta
+ 1024 < 2048)
2368 /* warning ("long branch, distance %d", delta); */
2372 /* Return non-zero if REG is not used after INSN.
2373 We assume REG is a reload reg, and therefore does
2374 not live past labels or calls or jumps. */
2376 reg_unused_after (reg
, insn
)
2380 enum rtx_code code
, prev_code
= UNKNOWN
;
2382 while ((insn
= NEXT_INSN (insn
)))
2384 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2387 code
= GET_CODE (insn
);
2388 if (GET_CODE (insn
) == CODE_LABEL
)
2391 if (GET_RTX_CLASS (code
) == 'i')
2393 rtx set
= single_set (insn
);
2394 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
2397 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2399 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
2407 /* The table we use to reference PIC data. */
2408 static rtx global_offset_table
;
2410 /* The function we use to get at it. */
2411 static rtx get_pc_symbol
;
2412 static char get_pc_symbol_name
[256];
2414 /* Ensure that we are not using patterns that are not OK with PIC. */
2423 if (GET_CODE (recog_data
.operand
[i
]) == SYMBOL_REF
2424 || (GET_CODE (recog_data
.operand
[i
]) == CONST
2425 && ! (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
2426 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
2427 == global_offset_table
)
2428 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
2437 /* Return true if X is an address which needs a temporary register when
2438 reloaded while generating PIC code. */
2441 pic_address_needs_scratch (x
)
2444 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2445 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
2446 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2447 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2448 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
2454 /* Legitimize PIC addresses. If the address is already position-independent,
2455 we return ORIG. Newly generated position-independent addresses go into a
2456 reg. This is REG if non zero, otherwise we allocate register(s) as
2460 legitimize_pic_address (orig
, mode
, reg
)
2462 enum machine_mode mode ATTRIBUTE_UNUSED
;
2465 if (GET_CODE (orig
) == SYMBOL_REF
)
2467 rtx pic_ref
, address
;
2472 if (reload_in_progress
|| reload_completed
)
2475 reg
= gen_reg_rtx (Pmode
);
2480 /* If not during reload, allocate another temp reg here for loading
2481 in the address, so that these instructions can be optimized
2483 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
2484 ? reg
: gen_reg_rtx (Pmode
));
2486 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2487 won't get confused into thinking that these two instructions
2488 are loading in the true address of the symbol. If in the
2489 future a PIC rtx exists, that should be used instead. */
2490 if (Pmode
== SImode
)
2492 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
2493 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
2497 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
2498 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
2505 pic_ref
= gen_rtx_MEM (Pmode
,
2506 gen_rtx_PLUS (Pmode
,
2507 pic_offset_table_rtx
, address
));
2508 current_function_uses_pic_offset_table
= 1;
2509 RTX_UNCHANGING_P (pic_ref
) = 1;
2510 insn
= emit_move_insn (reg
, pic_ref
);
2511 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2513 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2517 else if (GET_CODE (orig
) == CONST
)
2521 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2522 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2527 if (reload_in_progress
|| reload_completed
)
2530 reg
= gen_reg_rtx (Pmode
);
2533 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2535 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2536 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2537 base
== reg
? 0 : reg
);
2542 if (GET_CODE (offset
) == CONST_INT
)
2544 if (SMALL_INT (offset
))
2545 return plus_constant_for_output (base
, INTVAL (offset
));
2546 else if (! reload_in_progress
&& ! reload_completed
)
2547 offset
= force_reg (Pmode
, offset
);
2549 /* If we reach here, then something is seriously wrong. */
2552 return gen_rtx_PLUS (Pmode
, base
, offset
);
2554 else if (GET_CODE (orig
) == LABEL_REF
)
2555 /* ??? Why do we do this? */
2556 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2557 the register is live instead, in case it is eliminated. */
2558 current_function_uses_pic_offset_table
= 1;
2563 /* Return the RTX for insns to set the PIC register. */
2571 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
2573 seq
= gen_sequence ();
2579 /* Emit special PIC prologues and epilogues. */
2584 /* Labels to get the PC in the prologue of this function. */
2585 int orig_flag_pic
= flag_pic
;
2588 if (current_function_uses_pic_offset_table
== 0)
2594 /* If we havn't emitted the special get_pc helper function, do so now. */
2595 if (get_pc_symbol_name
[0] == 0)
2599 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name
, "LGETPC", 0);
2602 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
2604 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
2605 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LGETPC", 0);
2606 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file
);
2609 /* Initialize every time through, since we can't easily
2610 know this to be permanent. */
2611 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2612 get_pc_symbol
= gen_rtx_SYMBOL_REF (Pmode
, get_pc_symbol_name
);
2615 emit_insn_after (pic_setup_code (), get_insns ());
2617 /* Insert the code in each nonlocal goto receiver.
2618 If you make changes here or to the nonlocal_goto_receiver
2619 pattern, make sure the unspec_volatile numbers still
2621 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
2622 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
2623 && XINT (PATTERN (insn
), 1) == 5)
2624 emit_insn_after (pic_setup_code (), insn
);
2626 flag_pic
= orig_flag_pic
;
2628 /* Need to emit this whether or not we obey regdecls,
2629 since setjmp/longjmp can cause life info to screw up.
2630 ??? In the case where we don't obey regdecls, this is not sufficient
2631 since we may not fall out the bottom. */
2632 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2635 /* Return 1 if RTX is a MEM which is known to be aligned to at
2636 least an 8 byte boundary. */
2639 mem_min_alignment (mem
, desired
)
2643 rtx addr
, base
, offset
;
2645 /* If it's not a MEM we can't accept it. */
2646 if (GET_CODE (mem
) != MEM
)
2649 addr
= XEXP (mem
, 0);
2650 base
= offset
= NULL_RTX
;
2651 if (GET_CODE (addr
) == PLUS
)
2653 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2655 base
= XEXP (addr
, 0);
2657 /* What we are saying here is that if the base
2658 REG is aligned properly, the compiler will make
2659 sure any REG based index upon it will be so
2661 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2662 offset
= XEXP (addr
, 1);
2664 offset
= const0_rtx
;
2667 else if (GET_CODE (addr
) == REG
)
2670 offset
= const0_rtx
;
2673 if (base
!= NULL_RTX
)
2675 int regno
= REGNO (base
);
2677 if (regno
!= FRAME_POINTER_REGNUM
2678 && regno
!= STACK_POINTER_REGNUM
)
2680 /* Check if the compiler has recorded some information
2681 about the alignment of the base REG. If reload has
2682 completed, we already matched with proper alignments. */
2683 if (((current_function
!= 0
2684 && REGNO_POINTER_ALIGN (regno
) >= desired
)
2685 || reload_completed
)
2686 && ((INTVAL (offset
) & (desired
- 1)) == 0))
2691 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
2695 else if (! TARGET_UNALIGNED_DOUBLES
2696 || CONSTANT_P (addr
)
2697 || GET_CODE (addr
) == LO_SUM
)
2699 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2700 is true, in which case we can only assume that an access is aligned if
2701 it is to a constant address, or the address involves a LO_SUM. */
2705 /* An obviously unaligned address. */
2710 /* Vectors to keep interesting information about registers where it can easily
2711 be got. We use to use the actual mode value as the bit number, but there
2712 are more than 32 modes now. Instead we use two tables: one indexed by
2713 hard register number, and one indexed by mode. */
2715 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2716 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2717 mapped into one sparc_mode_class mode. */
2719 enum sparc_mode_class
{
2720 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
2721 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
2725 /* Modes for single-word and smaller quantities. */
2726 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2728 /* Modes for double-word and smaller quantities. */
2729 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2731 /* Modes for quad-word and smaller quantities. */
2732 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2734 /* Modes for 8-word and smaller quantities. */
2735 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
2737 /* Modes for single-float quantities. We must allow any single word or
2738 smaller quantity. This is because the fix/float conversion instructions
2739 take integer inputs/outputs from the float registers. */
2740 #define SF_MODES (S_MODES)
2742 /* Modes for double-float and smaller quantities. */
2743 #define DF_MODES (S_MODES | D_MODES)
2745 /* Modes for double-float only quantities. */
2746 #define DF_MODES_NO_S (D_MODES)
2748 /* Modes for quad-float only quantities. */
2749 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2751 /* Modes for quad-float and smaller quantities. */
2752 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2754 /* Modes for quad-float and double-float quantities. */
2755 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
2757 /* Modes for quad-float pair only quantities. */
2758 #define OF_ONLY_MODES (1 << (int) OF_MODE)
2760 /* Modes for quad-float pairs and smaller quantities. */
2761 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
2763 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
2765 /* Modes for condition codes. */
2766 #define CC_MODES (1 << (int) CC_MODE)
2767 #define CCFP_MODES (1 << (int) CCFP_MODE)
2769 /* Value is 1 if register/mode pair is acceptable on sparc.
2770 The funny mixture of D and T modes is because integer operations
2771 do not specially operate on tetra quantities, so non-quad-aligned
2772 registers can hold quadword quantities (except %o4 and %i4 because
2773 they cross fixed registers). */
2775 /* This points to either the 32 bit or the 64 bit version. */
2776 int *hard_regno_mode_classes
;
2778 static int hard_32bit_mode_classes
[] = {
2779 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2780 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
2781 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2782 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
2784 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2785 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2786 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2787 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2789 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2790 and none can hold SFmode/SImode values. */
2791 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
2792 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
2793 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
2794 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
2797 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
2803 static int hard_64bit_mode_classes
[] = {
2804 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
2805 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
2806 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
2807 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
2809 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2810 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2811 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2812 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2814 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2815 and none can hold SFmode/SImode values. */
2816 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
2817 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
2818 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
2819 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
2822 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
2828 int sparc_mode_class
[NUM_MACHINE_MODES
];
2830 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
2837 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
2839 switch (GET_MODE_CLASS (i
))
2842 case MODE_PARTIAL_INT
:
2843 case MODE_COMPLEX_INT
:
2844 if (GET_MODE_SIZE (i
) <= 4)
2845 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
2846 else if (GET_MODE_SIZE (i
) == 8)
2847 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
2848 else if (GET_MODE_SIZE (i
) == 16)
2849 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
2850 else if (GET_MODE_SIZE (i
) == 32)
2851 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
2853 sparc_mode_class
[i
] = 0;
2856 case MODE_COMPLEX_FLOAT
:
2857 if (GET_MODE_SIZE (i
) <= 4)
2858 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
2859 else if (GET_MODE_SIZE (i
) == 8)
2860 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
2861 else if (GET_MODE_SIZE (i
) == 16)
2862 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
2863 else if (GET_MODE_SIZE (i
) == 32)
2864 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
2866 sparc_mode_class
[i
] = 0;
2870 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2871 we must explicitly check for them here. */
2872 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
2873 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
2874 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
2875 || i
== (int) CCXmode
|| i
== (int) CCX_NOOVmode
)
2876 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
2878 sparc_mode_class
[i
] = 0;
2884 hard_regno_mode_classes
= hard_64bit_mode_classes
;
2886 hard_regno_mode_classes
= hard_32bit_mode_classes
;
2888 /* Initialize the array used by REGNO_REG_CLASS. */
2889 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2891 if (i
< 16 && TARGET_V8PLUS
)
2892 sparc_regno_reg_class
[i
] = I64_REGS
;
2894 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
2896 sparc_regno_reg_class
[i
] = FP_REGS
;
2898 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
2900 sparc_regno_reg_class
[i
] = FPCC_REGS
;
2902 sparc_regno_reg_class
[i
] = NO_REGS
;
2906 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2907 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2908 v9 int regs as it simplifies the code. */
2911 save_regs (file
, low
, high
, base
, offset
, n_regs
, real_offset
)
2921 if (TARGET_ARCH64
&& high
<= 32)
2923 for (i
= low
; i
< high
; i
++)
2925 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2927 fprintf (file
, "\tstx\t%s, [%s+%d]\n",
2928 reg_names
[i
], base
, offset
+ 4 * n_regs
);
2929 if (dwarf2out_do_frame ())
2930 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
2937 for (i
= low
; i
< high
; i
+= 2)
2939 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2941 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2943 fprintf (file
, "\tstd\t%s, [%s+%d]\n",
2944 reg_names
[i
], base
, offset
+ 4 * n_regs
);
2945 if (dwarf2out_do_frame ())
2947 char *l
= dwarf2out_cfi_label ();
2948 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
2949 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
2955 fprintf (file
, "\tst\t%s, [%s+%d]\n",
2956 reg_names
[i
], base
, offset
+ 4 * n_regs
);
2957 if (dwarf2out_do_frame ())
2958 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
2964 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2966 fprintf (file
, "\tst\t%s, [%s+%d]\n",
2967 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
2968 if (dwarf2out_do_frame ())
2969 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
2978 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2980 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2981 v9 int regs as it simplifies the code. */
2984 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
2993 if (TARGET_ARCH64
&& high
<= 32)
2995 for (i
= low
; i
< high
; i
++)
2997 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2998 fprintf (file
, "\tldx\t[%s+%d], %s\n",
2999 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3005 for (i
= low
; i
< high
; i
+= 2)
3007 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3008 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3009 fprintf (file
, "\tldd\t[%s+%d], %s\n",
3010 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3013 fprintf (file
, "\tld\t[%s+%d],%s\n",
3014 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3016 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3017 fprintf (file
, "\tld\t[%s+%d],%s\n",
3018 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
3025 /* Compute the frame size required by the function. This function is called
3026 during the reload pass and also by output_function_prologue(). */
3029 compute_frame_size (size
, leaf_function
)
3034 int outgoing_args_size
= (current_function_outgoing_args_size
3035 + REG_PARM_STACK_SPACE (current_function_decl
));
3037 if (TARGET_EPILOGUE
)
3039 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3040 even to v9 int regs to be consistent with save_regs/restore_regs. */
3044 for (i
= 0; i
< 8; i
++)
3045 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3050 for (i
= 0; i
< 8; i
+= 2)
3051 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3052 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3056 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3057 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3058 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3062 /* Set up values for use in `function_epilogue'. */
3063 num_gfregs
= n_regs
;
3065 if (leaf_function
&& n_regs
== 0
3066 && size
== 0 && current_function_outgoing_args_size
== 0)
3068 actual_fsize
= apparent_fsize
= 0;
3072 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3073 The stack bias (if any) is taken out to undo its effects. */
3074 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ SPARC_STACK_BIAS
+ 7) & -8;
3075 apparent_fsize
+= n_regs
* 4;
3076 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3079 /* Make sure nothing can clobber our register windows.
3080 If a SAVE must be done, or there is a stack-local variable,
3081 the register window area must be allocated.
3082 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3083 if (leaf_function
== 0 || size
> 0)
3084 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
3086 return SPARC_STACK_ALIGN (actual_fsize
);
3089 /* Build a (32 bit) big number in a register. */
3090 /* ??? We may be able to use the set macro here too. */
3093 build_big_number (file
, num
, reg
)
3098 if (num
>= 0 || ! TARGET_ARCH64
)
3100 fprintf (file
, "\tsethi\t%%hi(%d), %s\n", num
, reg
);
3101 if ((num
& 0x3ff) != 0)
3102 fprintf (file
, "\tor\t%s, %%lo(%d), %s\n", reg
, num
, reg
);
3104 else /* num < 0 && TARGET_ARCH64 */
3106 /* Sethi does not sign extend, so we must use a little trickery
3107 to use it for negative numbers. Invert the constant before
3108 loading it in, then use xor immediate to invert the loaded bits
3109 (along with the upper 32 bits) to the desired constant. This
3110 works because the sethi and immediate fields overlap. */
3113 int low
= -0x400 + (asize
& 0x3FF);
3115 fprintf (file
, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3116 inv
, reg
, reg
, low
, reg
);
3120 /* Output any necessary .register pseudo-ops. */
3122 sparc_output_scratch_registers (file
)
3125 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3131 /* Check if %g[2367] were used without
3132 .register being printed for them already. */
3133 for (i
= 2; i
< 8; i
++)
3135 if (regs_ever_live
[i
]
3136 && ! sparc_hard_reg_printed
[i
])
3138 sparc_hard_reg_printed
[i
] = 1;
3139 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
3146 /* Output code for the function prologue. */
3149 output_function_prologue (file
, size
, leaf_function
)
3154 sparc_output_scratch_registers (file
);
3156 /* Need to use actual_fsize, since we are also allocating
3157 space for our callee (and our own register save area). */
3158 actual_fsize
= compute_frame_size (size
, leaf_function
);
3162 frame_base_name
= "%sp";
3163 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3167 frame_base_name
= "%fp";
3168 frame_base_offset
= SPARC_STACK_BIAS
;
3171 /* This is only for the human reader. */
3172 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
3174 if (actual_fsize
== 0)
3176 else if (! leaf_function
&& ! TARGET_BROKEN_SAVERESTORE
)
3178 if (actual_fsize
<= 4096)
3179 fprintf (file
, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize
);
3180 else if (actual_fsize
<= 8192)
3182 fprintf (file
, "\tsave\t%%sp, -4096, %%sp\n");
3183 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3187 build_big_number (file
, -actual_fsize
, "%g1");
3188 fprintf (file
, "\tsave\t%%sp, %%g1, %%sp\n");
3191 else if (! leaf_function
&& TARGET_BROKEN_SAVERESTORE
)
3193 /* We assume the environment will properly handle or otherwise avoid
3194 trouble associated with an interrupt occurring after the `save' or
3195 trap occurring during it. */
3196 fprintf (file
, "\tsave\n");
3198 if (actual_fsize
<= 4096)
3199 fprintf (file
, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize
);
3200 else if (actual_fsize
<= 8192)
3202 fprintf (file
, "\tadd\t%%fp, -4096, %%sp\n");
3203 fprintf (file
, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize
- 4096);
3207 build_big_number (file
, -actual_fsize
, "%g1");
3208 fprintf (file
, "\tadd\t%%fp, %%g1, %%sp\n");
3211 else /* leaf function */
3213 if (actual_fsize
<= 4096)
3214 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
);
3215 else if (actual_fsize
<= 8192)
3217 fprintf (file
, "\tadd\t%%sp, -4096, %%sp\n");
3218 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3222 build_big_number (file
, -actual_fsize
, "%g1");
3223 fprintf (file
, "\tadd\t%%sp, %%g1, %%sp\n");
3227 if (dwarf2out_do_frame () && actual_fsize
)
3229 char *label
= dwarf2out_cfi_label ();
3231 /* The canonical frame address refers to the top of the frame. */
3232 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
3233 : FRAME_POINTER_REGNUM
),
3236 if (! leaf_function
)
3238 /* Note the register window save. This tells the unwinder that
3239 it needs to restore the window registers from the previous
3240 frame's window save area at 0(cfa). */
3241 dwarf2out_window_save (label
);
3243 /* The return address (-8) is now in %i7. */
3244 dwarf2out_return_reg (label
, 31);
3248 /* If doing anything with PIC, do it now. */
3250 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
3252 /* Call saved registers are saved just above the outgoing argument area. */
3255 int offset
, real_offset
, n_regs
;
3258 real_offset
= -apparent_fsize
;
3259 offset
= -apparent_fsize
+ frame_base_offset
;
3260 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
3262 /* ??? This might be optimized a little as %g1 might already have a
3263 value close enough that a single add insn will do. */
3264 /* ??? Although, all of this is probably only a temporary fix
3265 because if %g1 can hold a function result, then
3266 output_function_epilogue will lose (the result will get
3268 build_big_number (file
, offset
, "%g1");
3269 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3275 base
= frame_base_name
;
3279 if (TARGET_EPILOGUE
&& ! leaf_function
)
3280 /* ??? Originally saved regs 0-15 here. */
3281 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3282 else if (leaf_function
)
3283 /* ??? Originally saved regs 0-31 here. */
3284 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3285 if (TARGET_EPILOGUE
)
3286 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
3291 if (leaf_function
&& actual_fsize
!= 0)
3293 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3294 if (! TARGET_EPILOGUE
)
3295 leaf_label
= gen_label_rtx ();
3299 /* Output code for the function epilogue. */
3302 output_function_epilogue (file
, size
, leaf_function
)
3304 int size ATTRIBUTE_UNUSED
;
3311 emit_label_after (leaf_label
, get_last_insn ());
3312 final_scan_insn (get_last_insn (), file
, 0, 0, 1);
3315 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3316 else if (profile_block_flag
== 2)
3318 FUNCTION_BLOCK_PROFILER_EXIT(file
);
3322 else if (current_function_epilogue_delay_list
== 0)
3324 /* If code does not drop into the epilogue, we need
3325 do nothing except output pending case vectors. */
3326 rtx insn
= get_last_insn ();
3327 if (GET_CODE (insn
) == NOTE
)
3328 insn
= prev_nonnote_insn (insn
);
3329 if (insn
&& GET_CODE (insn
) == BARRIER
)
3330 goto output_vectors
;
3333 /* Restore any call saved registers. */
3339 offset
= -apparent_fsize
+ frame_base_offset
;
3340 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
3342 build_big_number (file
, offset
, "%g1");
3343 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3349 base
= frame_base_name
;
3353 if (TARGET_EPILOGUE
&& ! leaf_function
)
3354 /* ??? Originally saved regs 0-15 here. */
3355 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3356 else if (leaf_function
)
3357 /* ??? Originally saved regs 0-31 here. */
3358 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3359 if (TARGET_EPILOGUE
)
3360 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
3363 /* Work out how to skip the caller's unimp instruction if required. */
3365 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%o7+12" : "retl");
3367 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%i7+12" : "ret");
3369 if (TARGET_EPILOGUE
|| leaf_label
)
3371 int old_target_epilogue
= TARGET_EPILOGUE
;
3372 target_flags
&= ~old_target_epilogue
;
3374 if (! leaf_function
)
3376 /* If we wound up with things in our delay slot, flush them here. */
3377 if (current_function_epilogue_delay_list
)
3379 rtx delay
= PATTERN (XEXP (current_function_epilogue_delay_list
, 0));
3381 if (TARGET_V9
&& ! epilogue_renumber (&delay
, 1))
3383 epilogue_renumber (&delay
, 0);
3384 fputs (SKIP_CALLERS_UNIMP_P
3385 ? "\treturn\t%i7+12\n"
3386 : "\treturn\t%i7+8\n", file
);
3387 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0), file
, 1, 0, 0);
3391 rtx insn
= emit_jump_insn_after (gen_rtx_RETURN (VOIDmode
),
3395 if (GET_CODE (delay
) != SET
)
3398 src
= SET_SRC (delay
);
3399 if (GET_CODE (src
) == ASHIFT
)
3401 if (XEXP (src
, 1) != const1_rtx
)
3403 SET_SRC (delay
) = gen_rtx_PLUS (GET_MODE (src
), XEXP (src
, 0),
3407 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
,
3408 gen_rtvec (2, delay
, PATTERN (insn
)));
3409 final_scan_insn (insn
, file
, 1, 0, 1);
3412 else if (TARGET_V9
&& ! SKIP_CALLERS_UNIMP_P
)
3413 fputs ("\treturn\t%i7+8\n\tnop\n", file
);
3415 fprintf (file
, "\t%s\n\trestore\n", ret
);
3417 /* All of the following cases are for leaf functions. */
3418 else if (current_function_epilogue_delay_list
)
3420 /* eligible_for_epilogue_delay_slot ensures that if this is a
3421 leaf function, then we will only have insn in the delay slot
3422 if the frame size is zero, thus no adjust for the stack is
3424 if (actual_fsize
!= 0)
3426 fprintf (file
, "\t%s\n", ret
);
3427 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
3430 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3431 avoid generating confusing assembly language output. */
3432 else if (actual_fsize
== 0)
3433 fprintf (file
, "\t%s\n\tnop\n", ret
);
3434 else if (actual_fsize
<= 4096)
3435 fprintf (file
, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret
, actual_fsize
);
3436 else if (actual_fsize
<= 8192)
3437 fprintf (file
, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
3438 ret
, actual_fsize
- 4096);
3439 else if ((actual_fsize
& 0x3ff) == 0)
3440 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3443 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
3444 actual_fsize
, actual_fsize
, ret
);
3445 target_flags
|= old_target_epilogue
;
3449 sparc_output_deferred_case_vectors ();
3452 /* Functions for handling argument passing.
3454 For v8 the first six args are normally in registers and the rest are
3455 pushed. Any arg that starts within the first 6 words is at least
3456 partially passed in a register unless its data type forbids.
3458 For v9, the argument registers are laid out as an array of 16 elements
3459 and arguments are added sequentially. The first 6 int args and up to the
3460 first 16 fp args (depending on size) are passed in regs.
3462 Slot Stack Integral Float Float in structure Double Long Double
3463 ---- ----- -------- ----- ------------------ ------ -----------
3464 15 [SP+248] %f31 %f30,%f31 %d30
3465 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3466 13 [SP+232] %f27 %f26,%f27 %d26
3467 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3468 11 [SP+216] %f23 %f22,%f23 %d22
3469 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3470 9 [SP+200] %f19 %f18,%f19 %d18
3471 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3472 7 [SP+184] %f15 %f14,%f15 %d14
3473 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3474 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3475 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3476 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3477 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3478 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3479 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3481 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3483 Integral arguments are always passed as 64 bit quantities appropriately
3486 Passing of floating point values is handled as follows.
3487 If a prototype is in scope:
3488 If the value is in a named argument (i.e. not a stdarg function or a
3489 value not part of the `...') then the value is passed in the appropriate
3491 If the value is part of the `...' and is passed in one of the first 6
3492 slots then the value is passed in the appropriate int reg.
3493 If the value is part of the `...' and is not passed in one of the first 6
3494 slots then the value is passed in memory.
3495 If a prototype is not in scope:
3496 If the value is one of the first 6 arguments the value is passed in the
3497 appropriate integer reg and the appropriate fp reg.
3498 If the value is not one of the first 6 arguments the value is passed in
3499 the appropriate fp reg and in memory.
3502 /* Maximum number of int regs for args. */
3503 #define SPARC_INT_ARG_MAX 6
3504 /* Maximum number of fp regs for args. */
3505 #define SPARC_FP_ARG_MAX 16
3507 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3509 /* Handle the INIT_CUMULATIVE_ARGS macro.
3510 Initialize a variable CUM of type CUMULATIVE_ARGS
3511 for a call to a function whose data type is FNTYPE.
3512 For a library call, FNTYPE is 0. */
3515 init_cumulative_args (cum
, fntype
, libname
, indirect
)
3516 CUMULATIVE_ARGS
*cum
;
3518 rtx libname ATTRIBUTE_UNUSED
;
3519 int indirect ATTRIBUTE_UNUSED
;
3522 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
3523 cum
->libcall_p
= fntype
== 0;
3526 /* Compute the slot number to pass an argument in.
3527 Returns the slot number or -1 if passing on the stack.
3529 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3530 the preceding args and about the function being called.
3531 MODE is the argument's machine mode.
3532 TYPE is the data type of the argument (as a tree).
3533 This is null for libcalls where that information may
3535 NAMED is nonzero if this argument is a named parameter
3536 (otherwise it is an extra parameter matching an ellipsis).
3537 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3538 *PREGNO records the register number to use if scalar type.
3539 *PPADDING records the amount of padding needed in words. */
3542 function_arg_slotno (cum
, mode
, type
, named
, incoming_p
, pregno
, ppadding
)
3543 const CUMULATIVE_ARGS
*cum
;
3544 enum machine_mode mode
;
3551 int regbase
= (incoming_p
3552 ? SPARC_INCOMING_INT_ARG_FIRST
3553 : SPARC_OUTGOING_INT_ARG_FIRST
);
3554 int slotno
= cum
->words
;
3559 if (type
!= 0 && TREE_ADDRESSABLE (type
))
3562 && type
!= 0 && mode
== BLKmode
3563 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
3569 /* MODE is VOIDmode when generating the actual call.
3573 case QImode
: case CQImode
:
3574 case HImode
: case CHImode
:
3575 case SImode
: case CSImode
:
3576 case DImode
: case CDImode
:
3577 if (slotno
>= SPARC_INT_ARG_MAX
)
3579 regno
= regbase
+ slotno
;
3582 case SFmode
: case SCmode
:
3583 case DFmode
: case DCmode
:
3584 case TFmode
: case TCmode
:
3587 if (slotno
>= SPARC_INT_ARG_MAX
)
3589 regno
= regbase
+ slotno
;
3593 if ((mode
== TFmode
|| mode
== TCmode
)
3594 && (slotno
& 1) != 0)
3595 slotno
++, *ppadding
= 1;
3596 if (TARGET_FPU
&& named
)
3598 if (slotno
>= SPARC_FP_ARG_MAX
)
3600 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
3606 if (slotno
>= SPARC_INT_ARG_MAX
)
3608 regno
= regbase
+ slotno
;
3614 /* For sparc64, objects requiring 16 byte alignment get it. */
3617 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
3618 slotno
++, *ppadding
= 1;
3622 || (type
&& TREE_CODE (type
) == UNION_TYPE
))
3624 if (slotno
>= SPARC_INT_ARG_MAX
)
3626 regno
= regbase
+ slotno
;
3631 int intregs_p
= 0, fpregs_p
= 0;
3632 /* The ABI obviously doesn't specify how packed
3633 structures are passed. These are defined to be passed
3634 in int regs if possible, otherwise memory. */
3637 /* First see what kinds of registers we need. */
3638 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3640 if (TREE_CODE (field
) == FIELD_DECL
)
3642 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3647 if (DECL_PACKED (field
))
3651 if (packed_p
|| !named
)
3652 fpregs_p
= 0, intregs_p
= 1;
3654 /* If all arg slots are filled, then must pass on stack. */
3655 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
3657 /* If there are only int args and all int arg slots are filled,
3658 then must pass on stack. */
3659 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
3661 /* Note that even if all int arg slots are filled, fp members may
3662 still be passed in regs if such regs are available.
3663 *PREGNO isn't set because there may be more than one, it's up
3664 to the caller to compute them. */
3677 /* Handle recursive register counting for structure field layout. */
3679 struct function_arg_record_value_parms
3682 int slotno
, named
, regbase
;
3683 int nregs
, intoffset
;
3686 static void function_arg_record_value_3
3687 PROTO((int, struct function_arg_record_value_parms
*));
3688 static void function_arg_record_value_2
3689 PROTO((tree
, int, struct function_arg_record_value_parms
*));
3690 static void function_arg_record_value_1
3691 PROTO((tree
, int, struct function_arg_record_value_parms
*));
3692 static rtx function_arg_record_value
3693 PROTO((tree
, enum machine_mode
, int, int, int));
3696 function_arg_record_value_1 (type
, startbitpos
, parms
)
3699 struct function_arg_record_value_parms
*parms
;
3703 /* The ABI obviously doesn't specify how packed structures are
3704 passed. These are defined to be passed in int regs if possible,
3705 otherwise memory. */
3708 /* We need to compute how many registers are needed so we can
3709 allocate the PARALLEL but before we can do that we need to know
3710 whether there are any packed fields. If there are, int regs are
3711 used regardless of whether there are fp values present. */
3712 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3714 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
3721 /* Compute how many registers we need. */
3722 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3724 if (TREE_CODE (field
) == FIELD_DECL
)
3726 int bitpos
= startbitpos
;
3727 if (DECL_FIELD_BITPOS (field
))
3728 bitpos
+= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
));
3729 /* ??? FIXME: else assume zero offset. */
3731 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
3733 function_arg_record_value_1 (TREE_TYPE (field
), bitpos
, parms
);
3735 else if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3740 if (parms
->intoffset
!= -1)
3742 int intslots
, this_slotno
;
3744 intslots
= (bitpos
- parms
->intoffset
+ BITS_PER_WORD
- 1)
3746 this_slotno
= parms
->slotno
+ parms
->intoffset
3749 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
3750 intslots
= MAX (intslots
, 0);
3751 parms
->nregs
+= intslots
;
3752 parms
->intoffset
= -1;
3755 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3756 If it wasn't true we wouldn't be here. */
3761 if (parms
->intoffset
== -1)
3762 parms
->intoffset
= bitpos
;
3768 /* Handle recursive structure field register assignment. */
3771 function_arg_record_value_3 (bitpos
, parms
)
3773 struct function_arg_record_value_parms
*parms
;
3775 enum machine_mode mode
;
3776 int regno
, this_slotno
, intslots
, intoffset
;
3779 if (parms
->intoffset
== -1)
3781 intoffset
= parms
->intoffset
;
3782 parms
->intoffset
= -1;
3784 intslots
= (bitpos
- intoffset
+ BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3785 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
3787 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
3791 /* If this is the trailing part of a word, only load that much into
3792 the register. Otherwise load the whole register. Note that in
3793 the latter case we may pick up unwanted bits. It's not a problem
3794 at the moment but may wish to revisit. */
3796 if (intoffset
% BITS_PER_WORD
!= 0)
3798 mode
= mode_for_size (BITS_PER_WORD
- intoffset
%BITS_PER_WORD
,
3804 intoffset
/= BITS_PER_UNIT
;
3807 regno
= parms
->regbase
+ this_slotno
;
3808 reg
= gen_rtx_REG (mode
, regno
);
3809 XVECEXP (parms
->ret
, 0, parms
->nregs
)
3810 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
3813 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
3817 while (intslots
> 0);
3821 function_arg_record_value_2 (type
, startbitpos
, parms
)
3824 struct function_arg_record_value_parms
*parms
;
3829 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3831 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
3838 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3840 if (TREE_CODE (field
) == FIELD_DECL
)
3842 int bitpos
= startbitpos
;
3843 if (DECL_FIELD_BITPOS (field
))
3844 bitpos
+= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
));
3845 /* ??? FIXME: else assume zero offset. */
3847 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
3849 function_arg_record_value_2 (TREE_TYPE (field
), bitpos
, parms
);
3851 else if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3856 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
3859 function_arg_record_value_3 (bitpos
, parms
);
3861 reg
= gen_rtx_REG (DECL_MODE (field
),
3862 (SPARC_FP_ARG_FIRST
+ this_slotno
* 2
3863 + (DECL_MODE (field
) == SFmode
3864 && (bitpos
& 32) != 0)));
3865 XVECEXP (parms
->ret
, 0, parms
->nregs
)
3866 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
3867 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3872 if (parms
->intoffset
== -1)
3873 parms
->intoffset
= bitpos
;
3880 function_arg_record_value (type
, mode
, slotno
, named
, regbase
)
3882 enum machine_mode mode
;
3883 int slotno
, named
, regbase
;
3885 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
3886 struct function_arg_record_value_parms parms
;
3889 parms
.ret
= NULL_RTX
;
3890 parms
.slotno
= slotno
;
3891 parms
.named
= named
;
3892 parms
.regbase
= regbase
;
3894 /* Compute how many registers we need. */
3896 parms
.intoffset
= 0;
3897 function_arg_record_value_1 (type
, 0, &parms
);
3899 if (parms
.intoffset
!= -1)
3901 int intslots
, this_slotno
;
3903 intslots
= (typesize
*BITS_PER_UNIT
- parms
.intoffset
+ BITS_PER_WORD
- 1)
3905 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
3907 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
3908 intslots
= MAX (intslots
, 0);
3910 parms
.nregs
+= intslots
;
3912 nregs
= parms
.nregs
;
3914 /* Allocate the vector and handle some annoying special cases. */
3917 /* ??? Empty structure has no value? Duh? */
3920 /* Though there's nothing really to store, return a word register
3921 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
3922 leads to breakage due to the fact that there are zero bytes to
3924 return gen_rtx_REG (mode
, regbase
);
3928 /* ??? C++ has structures with no fields, and yet a size. Give up
3929 for now and pass everything back in integer registers. */
3930 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3932 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
3933 nregs
= SPARC_INT_ARG_MAX
- slotno
;
3938 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nregs
));
3940 /* Fill in the entries. */
3942 parms
.intoffset
= 0;
3943 function_arg_record_value_2 (type
, 0, &parms
);
3944 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
3946 if (parms
.nregs
!= nregs
)
3952 /* Handle the FUNCTION_ARG macro.
3953 Determine where to put an argument to a function.
3954 Value is zero to push the argument on the stack,
3955 or a hard register in which to store the argument.
3957 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3958 the preceding args and about the function being called.
3959 MODE is the argument's machine mode.
3960 TYPE is the data type of the argument (as a tree).
3961 This is null for libcalls where that information may
3963 NAMED is nonzero if this argument is a named parameter
3964 (otherwise it is an extra parameter matching an ellipsis).
3965 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3968 function_arg (cum
, mode
, type
, named
, incoming_p
)
3969 const CUMULATIVE_ARGS
*cum
;
3970 enum machine_mode mode
;
3975 int regbase
= (incoming_p
3976 ? SPARC_INCOMING_INT_ARG_FIRST
3977 : SPARC_OUTGOING_INT_ARG_FIRST
);
3978 int slotno
, regno
, padding
;
3981 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
3989 reg
= gen_rtx_REG (mode
, regno
);
3993 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3994 but also have the slot allocated for them.
3995 If no prototype is in scope fp values in register slots get passed
3996 in two places, either fp regs and int regs or fp regs and memory. */
3997 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3998 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3999 && SPARC_FP_REG_P (regno
))
4001 reg
= gen_rtx_REG (mode
, regno
);
4002 if (cum
->prototype_p
|| cum
->libcall_p
)
4004 /* "* 2" because fp reg numbers are recorded in 4 byte
4007 /* ??? This will cause the value to be passed in the fp reg and
4008 in the stack. When a prototype exists we want to pass the
4009 value in the reg but reserve space on the stack. That's an
4010 optimization, and is deferred [for a bit]. */
4011 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
4012 return gen_rtx_PARALLEL (mode
,
4014 gen_rtx_EXPR_LIST (VOIDmode
,
4015 NULL_RTX
, const0_rtx
),
4016 gen_rtx_EXPR_LIST (VOIDmode
,
4020 /* ??? It seems that passing back a register even when past
4021 the area declared by REG_PARM_STACK_SPACE will allocate
4022 space appropriately, and will not copy the data onto the
4023 stack, exactly as we desire.
4025 This is due to locate_and_pad_parm being called in
4026 expand_call whenever reg_parm_stack_space > 0, which
4027 while benefical to our example here, would seem to be
4028 in error from what had been intended. Ho hum... -- r~ */
4036 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
4040 /* On incoming, we don't need to know that the value
4041 is passed in %f0 and %i0, and it confuses other parts
4042 causing needless spillage even on the simplest cases. */
4046 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
4047 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
4049 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4050 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
4052 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4056 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4057 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4058 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4062 else if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
4064 /* Structures up to 16 bytes in size are passed in arg slots on the
4065 stack and are promoted to registers where possible. */
4067 if (int_size_in_bytes (type
) > 16)
4068 abort (); /* shouldn't get here */
4070 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
4072 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
4074 enum machine_mode mode
;
4075 int bytes
= int_size_in_bytes (type
);
4080 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4081 reg
= gen_rtx_REG (mode
, regno
);
4085 /* Scalar or complex int. */
4086 reg
= gen_rtx_REG (mode
, regno
);
4092 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4093 For an arg passed partly in registers and partly in memory,
4094 this is the number of registers used.
4095 For args passed entirely in registers or entirely in memory, zero.
4097 Any arg that starts in the first 6 regs but won't entirely fit in them
4098 needs partial registers on v8. On v9, structures with integer
4099 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4100 values that begin in the last fp reg [where "last fp reg" varies with the
4101 mode] will be split between that reg and memory. */
4104 function_arg_partial_nregs (cum
, mode
, type
, named
)
4105 const CUMULATIVE_ARGS
*cum
;
4106 enum machine_mode mode
;
4110 int slotno
, regno
, padding
;
4112 /* We pass 0 for incoming_p here, it doesn't matter. */
4113 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4120 if ((slotno
+ (mode
== BLKmode
4121 ? ROUND_ADVANCE (int_size_in_bytes (type
))
4122 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
4123 > NPARM_REGS (SImode
))
4124 return NPARM_REGS (SImode
) - slotno
;
4129 if (type
&& AGGREGATE_TYPE_P (type
))
4131 int size
= int_size_in_bytes (type
);
4132 int align
= TYPE_ALIGN (type
);
4135 slotno
+= slotno
& 1;
4136 if (size
> 8 && size
<= 16
4137 && slotno
== SPARC_INT_ARG_MAX
- 1)
4140 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
4141 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4144 if (GET_MODE_ALIGNMENT (mode
) == 128)
4146 slotno
+= slotno
& 1;
4147 if (slotno
== SPARC_INT_ARG_MAX
- 2)
4152 if (slotno
== SPARC_INT_ARG_MAX
- 1)
4156 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4158 if (GET_MODE_ALIGNMENT (mode
) == 128)
4159 slotno
+= slotno
& 1;
4160 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
4168 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4169 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4170 quad-precision floats by invisible reference.
4171 v9: Aggregates greater than 16 bytes are passed by reference.
4172 For Pascal, also pass arrays by reference. */
4175 function_arg_pass_by_reference (cum
, mode
, type
, named
)
4176 const CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
4177 enum machine_mode mode
;
4179 int named ATTRIBUTE_UNUSED
;
4183 return ((type
&& AGGREGATE_TYPE_P (type
))
4184 || mode
== TFmode
|| mode
== TCmode
);
4188 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
4189 /* Consider complex values as aggregates, so care for TCmode. */
4190 || GET_MODE_SIZE (mode
) > 16
4191 || (type
&& AGGREGATE_TYPE_P (type
)
4192 && int_size_in_bytes (type
) > 16));
4196 /* Handle the FUNCTION_ARG_ADVANCE macro.
4197 Update the data in CUM to advance over an argument
4198 of mode MODE and data type TYPE.
4199 TYPE is null for libcalls where that information may not be available. */
4202 function_arg_advance (cum
, mode
, type
, named
)
4203 CUMULATIVE_ARGS
*cum
;
4204 enum machine_mode mode
;
4208 int slotno
, regno
, padding
;
4210 /* We pass 0 for incoming_p here, it doesn't matter. */
4211 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4213 /* If register required leading padding, add it. */
4215 cum
->words
+= padding
;
4219 cum
->words
+= (mode
!= BLKmode
4220 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
4221 : ROUND_ADVANCE (int_size_in_bytes (type
)));
4225 if (type
&& AGGREGATE_TYPE_P (type
))
4227 int size
= int_size_in_bytes (type
);
4231 else if (size
<= 16)
4233 else /* passed by reference */
4236 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
4240 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4242 cum
->words
+= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4246 cum
->words
+= (mode
!= BLKmode
4247 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
4248 : ROUND_ADVANCE (int_size_in_bytes (type
)));
4253 /* Handle the FUNCTION_ARG_PADDING macro.
4254 For the 64 bit ABI structs are always stored left shifted in their
4258 function_arg_padding (mode
, type
)
4259 enum machine_mode mode
;
4262 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
4265 /* This is the default definition. */
4266 return (! BYTES_BIG_ENDIAN
4269 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
4270 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
4271 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
4272 ? downward
: upward
));
4275 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4276 For v9, function return values are subject to the same rules as arguments,
4277 except that up to 32-bytes may be returned in registers. */
4280 function_value (type
, mode
, incoming_p
)
4282 enum machine_mode mode
;
4286 int regbase
= (incoming_p
4287 ? SPARC_OUTGOING_INT_ARG_FIRST
4288 : SPARC_INCOMING_INT_ARG_FIRST
);
4290 if (TARGET_ARCH64
&& type
)
4292 if (TREE_CODE (type
) == RECORD_TYPE
)
4294 /* Structures up to 32 bytes in size are passed in registers,
4295 promoted to fp registers where possible. */
4297 if (int_size_in_bytes (type
) > 32)
4298 abort (); /* shouldn't get here */
4300 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
4302 else if (TREE_CODE (type
) == UNION_TYPE
)
4304 int bytes
= int_size_in_bytes (type
);
4309 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4314 && GET_MODE_CLASS (mode
) == MODE_INT
4315 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
4316 && type
&& TREE_CODE (type
) != UNION_TYPE
)
4320 regno
= BASE_RETURN_VALUE_REG (mode
);
4322 regno
= BASE_OUTGOING_VALUE_REG (mode
);
4324 return gen_rtx_REG (mode
, regno
);
4327 /* Do what is necessary for `va_start'. We look at the current function
4328 to determine if stdarg or varargs is used and return the address of
4329 the first unnamed parameter. */
4332 sparc_builtin_saveregs ()
4334 int first_reg
= current_function_args_info
.words
;
4338 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
4339 emit_move_insn (gen_rtx_MEM (word_mode
,
4340 gen_rtx_PLUS (Pmode
,
4342 GEN_INT (STACK_POINTER_OFFSET
4343 + UNITS_PER_WORD
* regno
))),
4344 gen_rtx_REG (word_mode
,
4345 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
4347 address
= gen_rtx_PLUS (Pmode
,
4349 GEN_INT (STACK_POINTER_OFFSET
4350 + UNITS_PER_WORD
* first_reg
));
4352 if (current_function_check_memory_usage
4353 && first_reg
< NPARM_REGS (word_mode
))
4354 emit_library_call (chkr_set_right_libfunc
, 1, VOIDmode
, 3,
4356 GEN_INT (UNITS_PER_WORD
4357 * (NPARM_REGS (word_mode
) - first_reg
)),
4358 TYPE_MODE (sizetype
), GEN_INT (MEMORY_USE_RW
),
4359 TYPE_MODE (integer_type_node
));
4364 /* Implement `va_start' for varargs and stdarg. */
4367 sparc_va_start (stdarg_p
, valist
, nextarg
)
4368 int stdarg_p ATTRIBUTE_UNUSED
;
4372 nextarg
= expand_builtin_saveregs ();
4373 std_expand_builtin_va_start (1, valist
, nextarg
);
4376 /* Implement `va_arg'. */
4379 sparc_va_arg (valist
, type
)
4382 HOST_WIDE_INT size
, rsize
, align
;
4387 /* Round up sizeof(type) to a word. */
4388 size
= int_size_in_bytes (type
);
4389 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4394 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
)
4395 align
= 2 * UNITS_PER_WORD
;
4397 if (AGGREGATE_TYPE_P (type
))
4402 size
= rsize
= UNITS_PER_WORD
;
4410 if (AGGREGATE_TYPE_P (type
)
4411 || TYPE_MODE (type
) == TFmode
4412 || TYPE_MODE (type
) == TCmode
)
4415 size
= rsize
= UNITS_PER_WORD
;
4419 /* ??? The old va-sparc.h implementation, for 8 byte objects
4420 copied stuff to a temporary -- I don't see that that
4421 provides any more alignment than the stack slot did. */
4428 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
4429 build_int_2 (align
- 1, 0)));
4430 incr
= fold (build (BIT_AND_EXPR
, ptr_type_node
, incr
,
4431 build_int_2 (-align
, -1)));
4434 addr
= incr
= save_expr (incr
);
4435 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
4437 addr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
4438 build_int_2 (rsize
- size
, 0)));
4440 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
4441 build_int_2 (rsize
, 0)));
4443 incr
= build (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
4444 TREE_SIDE_EFFECTS (incr
) = 1;
4445 expand_expr (incr
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4447 addr_rtx
= expand_expr (addr
, NULL
, Pmode
, EXPAND_NORMAL
);
4451 addr_rtx
= force_reg (Pmode
, addr_rtx
);
4452 addr_rtx
= gen_rtx_MEM (Pmode
, addr_rtx
);
4453 MEM_ALIAS_SET (addr_rtx
) = get_varargs_alias_set ();
4459 /* Return the string to output a conditional branch to LABEL, which is
4460 the operand number of the label. OP is the conditional expression.
4461 XEXP (OP, 0) is assumed to be a condition code register (integer or
4462 floating point) and its mode specifies what kind of comparison we made.
4464 REVERSED is non-zero if we should reverse the sense of the comparison.
4466 ANNUL is non-zero if we should generate an annulling branch.
4468 NOOP is non-zero if we have to follow this branch by a noop.
4470 INSN, if set, is the insn. */
4473 output_cbranch (op
, label
, reversed
, annul
, noop
, insn
)
4476 int reversed
, annul
, noop
;
4479 static char string
[32];
4480 enum rtx_code code
= GET_CODE (op
);
4481 rtx cc_reg
= XEXP (op
, 0);
4482 enum machine_mode mode
= GET_MODE (cc_reg
);
4483 static char v8_labelno
[] = "%lX";
4484 static char v9_icc_labelno
[] = "%%icc, %lX";
4485 static char v9_xcc_labelno
[] = "%%xcc, %lX";
4486 static char v9_fcc_labelno
[] = "%%fccX, %lY";
4488 int labeloff
, spaces
= 8;
4490 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4491 Because there is currently no concept of pre-delay slots, we can fix
4492 this only by always emitting a nop before a floating point branch. */
4494 if ((mode
== CCFPmode
|| mode
== CCFPEmode
) && ! TARGET_V9
)
4495 strcpy (string
, "nop\n\t");
4499 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4501 && ((mode
!= CCFPmode
&& mode
!= CCFPEmode
) || code
== EQ
|| code
== NE
))
4502 code
= reverse_condition (code
), reversed
= 0;
4504 /* Start by writing the branch condition. */
4508 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4510 strcat (string
, "fbne");
4515 strcpy (string
, "bne");
4521 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4523 strcat (string
, "fbe");
4528 strcpy (string
, "be");
4534 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4537 strcat (string
, "fbul");
4539 strcat (string
, "fbge");
4542 else if (mode
== CC_NOOVmode
)
4544 strcpy (string
, "bpos");
4549 strcpy (string
, "bge");
4555 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4559 strcat (string
, "fbule");
4564 strcat (string
, "fbg");
4570 strcpy (string
, "bg");
4576 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4579 strcat (string
, "fbug");
4581 strcat (string
, "fble");
4586 strcpy (string
, "ble");
4592 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4596 strcat (string
, "fbuge");
4601 strcat (string
, "fbl");
4605 else if (mode
== CC_NOOVmode
)
4607 strcpy (string
, "bneg");
4612 strcpy (string
, "bl");
4618 strcpy (string
, "bgeu");
4623 strcpy (string
, "bgu");
4628 strcpy (string
, "bleu");
4633 strcpy (string
, "blu");
4641 /* Now add the annulling, the label, and a possible noop. */
4644 strcat (string
, ",a");
4651 labelno
= v8_labelno
;
4657 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PRED
, NULL_RTX
)))
4660 INTVAL (XEXP (note
, 0)) & ATTR_FLAG_likely
? ",pt" : ",pn");
4665 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4668 labelno
= v9_fcc_labelno
;
4669 /* Set the char indicating the number of the fcc reg to use. */
4670 labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
4672 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
4673 labelno
= v9_xcc_labelno
;
4675 labelno
= v9_icc_labelno
;
4677 /* Set the char indicating the number of the operand containing the
4679 labelno
[labeloff
] = label
+ '0';
4681 strcat (string
, "\t");
4683 strcat (string
, " ");
4684 strcat (string
, labelno
);
4687 strcat (string
, "\n\tnop");
4692 /* Return the string to output a conditional branch to LABEL, testing
4693 register REG. LABEL is the operand number of the label; REG is the
4694 operand number of the reg. OP is the conditional expression. The mode
4695 of REG says what kind of comparison we made.
4697 REVERSED is non-zero if we should reverse the sense of the comparison.
4699 ANNUL is non-zero if we should generate an annulling branch.
4701 NOOP is non-zero if we have to follow this branch by a noop. */
4704 output_v9branch (op
, reg
, label
, reversed
, annul
, noop
, insn
)
4707 int reversed
, annul
, noop
;
4710 static char string
[20];
4711 enum rtx_code code
= GET_CODE (op
);
4712 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
4713 static char labelno
[] = "%X, %lX";
4717 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4719 code
= reverse_condition (code
), reversed
= 0;
4721 /* Only 64 bit versions of these instructions exist. */
4725 /* Start by writing the branch condition. */
4730 strcpy (string
, "brnz");
4735 strcpy (string
, "brz");
4740 strcpy (string
, "brgez");
4745 strcpy (string
, "brlz");
4750 strcpy (string
, "brlez");
4755 strcpy (string
, "brgz");
4763 /* Now add the annulling, reg, label, and nop. */
4766 strcat (string
, ",a");
4770 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PRED
, NULL_RTX
)))
4773 INTVAL (XEXP (note
, 0)) & ATTR_FLAG_likely
? ",pt" : ",pn");
4777 labelno
[1] = reg
+ '0';
4778 labelno
[6] = label
+ '0';
4780 strcat (string
, "\t");
4782 strcat (string
, " ");
4783 strcat (string
, labelno
);
4786 strcat (string
, "\n\tnop");
4791 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
4792 Such instructions cannot be used in the delay slot of return insn on v9.
4793 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
4797 epilogue_renumber (where
, test
)
4798 register rtx
*where
;
4801 register const char *fmt
;
4803 register enum rtx_code code
;
4808 code
= GET_CODE (*where
);
4813 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
4815 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
4816 *where
= gen_rtx (REG
, GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
4825 fmt
= GET_RTX_FORMAT (code
);
4827 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4832 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
4833 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
4836 else if (fmt
[i
] == 'e'
4837 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
4843 /* Output assembler code to return from a function. */
4846 output_return (operands
)
4849 rtx delay
= final_sequence
? XVECEXP (final_sequence
, 0, 1) : 0;
4853 operands
[0] = leaf_label
;
4856 else if (current_function_uses_only_leaf_regs
)
4858 /* No delay slot in a leaf function. */
4862 /* If we didn't allocate a frame pointer for the current function,
4863 the stack pointer might have been adjusted. Output code to
4866 operands
[0] = GEN_INT (actual_fsize
);
4868 /* Use sub of negated value in first two cases instead of add to
4869 allow actual_fsize == 4096. */
4871 if (actual_fsize
<= 4096)
4873 if (SKIP_CALLERS_UNIMP_P
)
4874 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4876 return "retl\n\tsub\t%%sp, -%0, %%sp";
4878 else if (actual_fsize
<= 8192)
4880 operands
[0] = GEN_INT (actual_fsize
- 4096);
4881 if (SKIP_CALLERS_UNIMP_P
)
4882 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
4884 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
4886 else if (SKIP_CALLERS_UNIMP_P
)
4888 if ((actual_fsize
& 0x3ff) != 0)
4889 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4891 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
4895 if ((actual_fsize
& 0x3ff) != 0)
4896 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4898 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4905 epilogue_renumber (&SET_DEST (PATTERN (delay
)), 0);
4906 epilogue_renumber (&SET_SRC (PATTERN (delay
)), 0);
4908 if (SKIP_CALLERS_UNIMP_P
)
4909 return "return\t%%i7+12%#";
4911 return "return\t%%i7+8%#";
4917 if (SKIP_CALLERS_UNIMP_P
)
4918 return "jmp\t%%i7+12\n\trestore";
4920 return "ret\n\trestore";
4924 /* Leaf functions and non-leaf functions have different needs. */
4927 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
4930 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
4932 static int *reg_alloc_orders
[] = {
4933 reg_leaf_alloc_order
,
4934 reg_nonleaf_alloc_order
};
4937 order_regs_for_local_alloc ()
4939 static int last_order_nonleaf
= 1;
4941 if (regs_ever_live
[15] != last_order_nonleaf
)
4943 last_order_nonleaf
= !last_order_nonleaf
;
4944 bcopy ((char *) reg_alloc_orders
[last_order_nonleaf
],
4945 (char *) reg_alloc_order
, FIRST_PSEUDO_REGISTER
* sizeof (int));
4949 /* Return 1 if REG and MEM are legitimate enough to allow the various
4950 mem<-->reg splits to be run. */
4953 sparc_splitdi_legitimate (reg
, mem
)
4957 /* Punt if we are here by mistake. */
4958 if (! reload_completed
)
4961 /* We must have an offsettable memory reference. */
4962 if (! offsettable_memref_p (mem
))
4965 /* If we have legitimate args for ldd/std, we do not want
4966 the split to happen. */
4967 if ((REGNO (reg
) % 2) == 0
4968 && mem_min_alignment (mem
, 8))
4975 /* Return 1 if x and y are some kind of REG and they refer to
4976 different hard registers. This test is guarenteed to be
4977 run after reload. */
4980 sparc_absnegfloat_split_legitimate (x
, y
)
4983 if (GET_CODE (x
) == SUBREG
)
4984 x
= alter_subreg (x
);
4985 if (GET_CODE (x
) != REG
)
4987 if (GET_CODE (y
) == SUBREG
)
4988 y
= alter_subreg (y
);
4989 if (GET_CODE (y
) != REG
)
4991 if (REGNO (x
) == REGNO (y
))
4996 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4997 This makes them candidates for using ldd and std insns.
4999 Note reg1 and reg2 *must* be hard registers. */
5002 registers_ok_for_ldd_peep (reg1
, reg2
)
5005 /* We might have been passed a SUBREG. */
5006 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
5009 if (REGNO (reg1
) % 2 != 0)
5012 /* Integer ldd is deprecated in SPARC V9 */
5013 if (TARGET_V9
&& REGNO (reg1
) < 32)
5016 return (REGNO (reg1
) == REGNO (reg2
) - 1);
5019 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
5022 This can only happen when addr1 and addr2 are consecutive memory
5023 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
5024 64 bit boundary (addr1 % 8 == 0).
5026 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
5027 registers are assumed to *never* be properly aligned and are
5030 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
5031 need only check that the offset for addr1 % 8 == 0. */
5034 addrs_ok_for_ldd_peep (addr1
, addr2
)
5039 /* Extract a register number and offset (if used) from the first addr. */
5040 if (GET_CODE (addr1
) == PLUS
)
5042 /* If not a REG, return zero. */
5043 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
5047 reg1
= REGNO (XEXP (addr1
, 0));
5048 /* The offset must be constant! */
5049 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
5051 offset1
= INTVAL (XEXP (addr1
, 1));
5054 else if (GET_CODE (addr1
) != REG
)
5058 reg1
= REGNO (addr1
);
5059 /* This was a simple (mem (reg)) expression. Offset is 0. */
5063 /* Make sure the second address is a (mem (plus (reg) (const_int). */
5064 if (GET_CODE (addr2
) != PLUS
)
5067 if (GET_CODE (XEXP (addr2
, 0)) != REG
5068 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
5071 /* Only %fp and %sp are allowed. Additionally both addresses must
5072 use the same register. */
5073 if (reg1
!= FRAME_POINTER_REGNUM
&& reg1
!= STACK_POINTER_REGNUM
)
5076 if (reg1
!= REGNO (XEXP (addr2
, 0)))
5079 /* The first offset must be evenly divisible by 8 to ensure the
5080 address is 64 bit aligned. */
5081 if (offset1
% 8 != 0)
5084 /* The offset for the second addr must be 4 more than the first addr. */
5085 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
5088 /* All the tests passed. addr1 and addr2 are valid for ldd and std
5093 /* Return 1 if reg is a pseudo, or is the first register in
5094 a hard register pair. This makes it a candidate for use in
5095 ldd and std insns. */
5098 register_ok_for_ldd (reg
)
5101 /* We might have been passed a SUBREG. */
5102 if (GET_CODE (reg
) != REG
)
5105 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
5106 return (REGNO (reg
) % 2 == 0);
5111 /* Print operand X (an rtx) in assembler syntax to file FILE.
5112 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5113 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5116 print_operand (file
, x
, code
)
5124 /* Output a 'nop' if there's nothing for the delay slot. */
5125 if (dbr_sequence_length () == 0)
5126 fputs ("\n\t nop", file
);
5129 /* Output an annul flag if there's nothing for the delay slot and we
5130 are optimizing. This is always used with '(' below. */
5131 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
5132 this is a dbx bug. So, we only do this when optimizing. */
5133 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
5134 Always emit a nop in case the next instruction is a branch. */
5135 if (dbr_sequence_length () == 0
5136 && (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
5140 /* Output a 'nop' if there's nothing for the delay slot and we are
5141 not optimizing. This is always used with '*' above. */
5142 if (dbr_sequence_length () == 0
5143 && ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
5144 fputs ("\n\t nop", file
);
5147 /* Output the Embedded Medium/Anywhere code model base register. */
5148 fputs (EMBMEDANY_BASE_REG
, file
);
5151 /* Print out what we are using as the frame pointer. This might
5152 be %fp, or might be %sp+offset. */
5153 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
5154 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
5157 /* Adjust the operand to take into account a RESTORE operation. */
5158 if (GET_CODE (x
) == CONST_INT
)
5160 else if (GET_CODE (x
) != REG
)
5161 output_operand_lossage ("Invalid %%Y operand");
5162 else if (REGNO (x
) < 8)
5163 fputs (reg_names
[REGNO (x
)], file
);
5164 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
5165 fputs (reg_names
[REGNO (x
)-16], file
);
5167 output_operand_lossage ("Invalid %%Y operand");
5170 /* Print out the low order register name of a register pair. */
5171 if (WORDS_BIG_ENDIAN
)
5172 fputs (reg_names
[REGNO (x
)+1], file
);
5174 fputs (reg_names
[REGNO (x
)], file
);
5177 /* Print out the high order register name of a register pair. */
5178 if (WORDS_BIG_ENDIAN
)
5179 fputs (reg_names
[REGNO (x
)], file
);
5181 fputs (reg_names
[REGNO (x
)+1], file
);
5184 /* Print out the second register name of a register pair or quad.
5185 I.e., R (%o0) => %o1. */
5186 fputs (reg_names
[REGNO (x
)+1], file
);
5189 /* Print out the third register name of a register quad.
5190 I.e., S (%o0) => %o2. */
5191 fputs (reg_names
[REGNO (x
)+2], file
);
5194 /* Print out the fourth register name of a register quad.
5195 I.e., T (%o0) => %o3. */
5196 fputs (reg_names
[REGNO (x
)+3], file
);
5199 /* Print a condition code register. */
5200 if (REGNO (x
) == SPARC_ICC_REG
)
5202 /* We don't handle CC[X]_NOOVmode because they're not supposed
5204 if (GET_MODE (x
) == CCmode
)
5205 fputs ("%icc", file
);
5206 else if (GET_MODE (x
) == CCXmode
)
5207 fputs ("%xcc", file
);
5212 /* %fccN register */
5213 fputs (reg_names
[REGNO (x
)], file
);
5216 /* Print the operand's address only. */
5217 output_address (XEXP (x
, 0));
5220 /* In this case we need a register. Use %g0 if the
5221 operand is const0_rtx. */
5223 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
5225 fputs ("%g0", file
);
5232 switch (GET_CODE (x
))
5234 case IOR
: fputs ("or", file
); break;
5235 case AND
: fputs ("and", file
); break;
5236 case XOR
: fputs ("xor", file
); break;
5237 default: output_operand_lossage ("Invalid %%A operand");
5242 switch (GET_CODE (x
))
5244 case IOR
: fputs ("orn", file
); break;
5245 case AND
: fputs ("andn", file
); break;
5246 case XOR
: fputs ("xnor", file
); break;
5247 default: output_operand_lossage ("Invalid %%B operand");
5251 /* These are used by the conditional move instructions. */
5255 enum rtx_code rc
= (code
== 'c'
5256 ? reverse_condition (GET_CODE (x
))
5260 case NE
: fputs ("ne", file
); break;
5261 case EQ
: fputs ("e", file
); break;
5262 case GE
: fputs ("ge", file
); break;
5263 case GT
: fputs ("g", file
); break;
5264 case LE
: fputs ("le", file
); break;
5265 case LT
: fputs ("l", file
); break;
5266 case GEU
: fputs ("geu", file
); break;
5267 case GTU
: fputs ("gu", file
); break;
5268 case LEU
: fputs ("leu", file
); break;
5269 case LTU
: fputs ("lu", file
); break;
5270 default: output_operand_lossage (code
== 'c'
5271 ? "Invalid %%c operand"
5272 : "Invalid %%C operand");
5277 /* These are used by the movr instruction pattern. */
5281 enum rtx_code rc
= (code
== 'd'
5282 ? reverse_condition (GET_CODE (x
))
5286 case NE
: fputs ("ne", file
); break;
5287 case EQ
: fputs ("e", file
); break;
5288 case GE
: fputs ("gez", file
); break;
5289 case LT
: fputs ("lz", file
); break;
5290 case LE
: fputs ("lez", file
); break;
5291 case GT
: fputs ("gz", file
); break;
5292 default: output_operand_lossage (code
== 'd'
5293 ? "Invalid %%d operand"
5294 : "Invalid %%D operand");
5301 /* Print a sign-extended character. */
5302 int i
= INTVAL (x
) & 0xff;
5305 fprintf (file
, "%d", i
);
5310 /* Operand must be a MEM; write its address. */
5311 if (GET_CODE (x
) != MEM
)
5312 output_operand_lossage ("Invalid %%f operand");
5313 output_address (XEXP (x
, 0));
5317 /* Do nothing special. */
5321 /* Undocumented flag. */
5322 output_operand_lossage ("invalid operand output code");
5325 if (GET_CODE (x
) == REG
)
5326 fputs (reg_names
[REGNO (x
)], file
);
5327 else if (GET_CODE (x
) == MEM
)
5330 /* Poor Sun assembler doesn't understand absolute addressing. */
5331 if (CONSTANT_P (XEXP (x
, 0))
5332 && ! TARGET_LIVE_G0
)
5333 fputs ("%g0+", file
);
5334 output_address (XEXP (x
, 0));
5337 else if (GET_CODE (x
) == HIGH
)
5339 fputs ("%hi(", file
);
5340 output_addr_const (file
, XEXP (x
, 0));
5343 else if (GET_CODE (x
) == LO_SUM
)
5345 print_operand (file
, XEXP (x
, 0), 0);
5346 if (TARGET_CM_MEDMID
)
5347 fputs ("+%l44(", file
);
5349 fputs ("+%lo(", file
);
5350 output_addr_const (file
, XEXP (x
, 1));
5353 else if (GET_CODE (x
) == CONST_DOUBLE
5354 && (GET_MODE (x
) == VOIDmode
5355 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
5357 if (CONST_DOUBLE_HIGH (x
) == 0)
5358 fprintf (file
, "%u", CONST_DOUBLE_LOW (x
));
5359 else if (CONST_DOUBLE_HIGH (x
) == -1
5360 && CONST_DOUBLE_LOW (x
) < 0)
5361 fprintf (file
, "%d", CONST_DOUBLE_LOW (x
));
5363 output_operand_lossage ("long long constant not a valid immediate operand");
5365 else if (GET_CODE (x
) == CONST_DOUBLE
)
5366 output_operand_lossage ("floating point constant not a valid immediate operand");
5367 else { output_addr_const (file
, x
); }
5370 /* This function outputs assembler code for VALUE to FILE, where VALUE is
5371 a 64 bit (DImode) value. */
5373 /* ??? If there is a 64 bit counterpart to .word that the assembler
5374 understands, then using that would simply this code greatly. */
5375 /* ??? We only output .xword's for symbols and only then in environments
5376 where the assembler can handle them. */
5379 output_double_int (file
, value
)
5383 if (GET_CODE (value
) == CONST_INT
)
5385 /* ??? This has endianness issues. */
5386 #if HOST_BITS_PER_WIDE_INT == 64
5387 HOST_WIDE_INT xword
= INTVAL (value
);
5388 HOST_WIDE_INT high
, low
;
5390 high
= (xword
>> 32) & 0xffffffff;
5391 low
= xword
& 0xffffffff;
5392 ASM_OUTPUT_INT (file
, GEN_INT (high
));
5393 ASM_OUTPUT_INT (file
, GEN_INT (low
));
5395 if (INTVAL (value
) < 0)
5396 ASM_OUTPUT_INT (file
, constm1_rtx
);
5398 ASM_OUTPUT_INT (file
, const0_rtx
);
5399 ASM_OUTPUT_INT (file
, value
);
5402 else if (GET_CODE (value
) == CONST_DOUBLE
)
5404 ASM_OUTPUT_INT (file
, GEN_INT (CONST_DOUBLE_HIGH (value
)));
5405 ASM_OUTPUT_INT (file
, GEN_INT (CONST_DOUBLE_LOW (value
)));
5407 else if (GET_CODE (value
) == SYMBOL_REF
5408 || GET_CODE (value
) == CONST
5409 || GET_CODE (value
) == PLUS
5410 || (TARGET_ARCH64
&&
5411 (GET_CODE (value
) == LABEL_REF
5412 || GET_CODE (value
) == CODE_LABEL
5413 || GET_CODE (value
) == MINUS
)))
5417 ASM_OUTPUT_INT (file
, const0_rtx
);
5418 ASM_OUTPUT_INT (file
, value
);
5422 fprintf (file
, "\t%s\t", ASM_LONGLONG
);
5423 output_addr_const (file
, value
);
5424 fprintf (file
, "\n");
5431 /* Return the value of a code used in the .proc pseudo-op that says
5432 what kind of result this function returns. For non-C types, we pick
5433 the closest C type. */
5435 #ifndef CHAR_TYPE_SIZE
5436 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5439 #ifndef SHORT_TYPE_SIZE
5440 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5443 #ifndef INT_TYPE_SIZE
5444 #define INT_TYPE_SIZE BITS_PER_WORD
5447 #ifndef LONG_TYPE_SIZE
5448 #define LONG_TYPE_SIZE BITS_PER_WORD
5451 #ifndef LONG_LONG_TYPE_SIZE
5452 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5455 #ifndef FLOAT_TYPE_SIZE
5456 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5459 #ifndef DOUBLE_TYPE_SIZE
5460 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5463 #ifndef LONG_DOUBLE_TYPE_SIZE
5464 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5468 sparc_type_code (type
)
5471 register unsigned long qualifiers
= 0;
5472 register unsigned shift
;
5474 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5475 setting more, since some assemblers will give an error for this. Also,
5476 we must be careful to avoid shifts of 32 bits or more to avoid getting
5477 unpredictable results. */
5479 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
5481 switch (TREE_CODE (type
))
5487 qualifiers
|= (3 << shift
);
5492 qualifiers
|= (2 << shift
);
5496 case REFERENCE_TYPE
:
5498 qualifiers
|= (1 << shift
);
5502 return (qualifiers
| 8);
5505 case QUAL_UNION_TYPE
:
5506 return (qualifiers
| 9);
5509 return (qualifiers
| 10);
5512 return (qualifiers
| 16);
5515 /* If this is a range type, consider it to be the underlying
5517 if (TREE_TYPE (type
) != 0)
5520 /* Carefully distinguish all the standard types of C,
5521 without messing up if the language is not C. We do this by
5522 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5523 look at both the names and the above fields, but that's redundant.
5524 Any type whose size is between two C types will be considered
5525 to be the wider of the two types. Also, we do not have a
5526 special code to use for "long long", so anything wider than
5527 long is treated the same. Note that we can't distinguish
5528 between "int" and "long" in this code if they are the same
5529 size, but that's fine, since neither can the assembler. */
5531 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
5532 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
5534 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
5535 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
5537 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
5538 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
5541 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
5544 /* If this is a range type, consider it to be the underlying
5546 if (TREE_TYPE (type
) != 0)
5549 /* Carefully distinguish all the standard types of C,
5550 without messing up if the language is not C. */
5552 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
5553 return (qualifiers
| 6);
5556 return (qualifiers
| 7);
5558 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
5559 /* ??? We need to distinguish between double and float complex types,
5560 but I don't know how yet because I can't reach this code from
5561 existing front-ends. */
5562 return (qualifiers
| 7); /* Who knows? */
5564 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
5565 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
5566 case FILE_TYPE
: /* GNU Pascal FILE type. */
5567 case SET_TYPE
: /* GNU Pascal SET type. */
5568 case LANG_TYPE
: /* ? */
5572 abort (); /* Not a type! */
5579 /* Nested function support. */
5581 /* Emit RTL insns to initialize the variable parts of a trampoline.
5582 FNADDR is an RTX for the address of the function's pure code.
5583 CXT is an RTX for the static chain value for the function.
5585 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5586 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5587 (to store insns). This is a bit excessive. Perhaps a different
5588 mechanism would be better here.
5590 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5593 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
5594 rtx tramp
, fnaddr
, cxt
;
5596 /* SPARC 32 bit trampoline:
5599 sethi %hi(static), %g2
5601 or %g2, %lo(static), %g2
5603 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
5604 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
5606 #ifdef TRANSFER_FROM_TRAMPOLINE
5607 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
5608 0, VOIDmode
, 1, tramp
, Pmode
);
5611 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
5612 expand_binop (SImode
, ior_optab
,
5613 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
5614 size_int (10), 0, 1),
5615 GEN_INT (0x03000000),
5616 NULL_RTX
, 1, OPTAB_DIRECT
));
5618 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
5619 expand_binop (SImode
, ior_optab
,
5620 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
5621 size_int (10), 0, 1),
5622 GEN_INT (0x05000000),
5623 NULL_RTX
, 1, OPTAB_DIRECT
));
5625 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
5626 expand_binop (SImode
, ior_optab
,
5627 expand_and (fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
5628 GEN_INT (0x81c06000),
5629 NULL_RTX
, 1, OPTAB_DIRECT
));
5631 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
5632 expand_binop (SImode
, ior_optab
,
5633 expand_and (cxt
, GEN_INT (0x3ff), NULL_RTX
),
5634 GEN_INT (0x8410a000),
5635 NULL_RTX
, 1, OPTAB_DIRECT
));
5637 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
5638 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
5639 aligned on a 16 byte boundary so one flush clears it all. */
5640 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
)
5641 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
5642 plus_constant (tramp
, 8)))));
5645 /* The 64 bit version is simpler because it makes more sense to load the
5646 values as "immediate" data out of the trampoline. It's also easier since
5647 we can read the PC without clobbering a register. */
5650 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
5651 rtx tramp
, fnaddr
, cxt
;
5653 #ifdef TRANSFER_FROM_TRAMPOLINE
5654 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
5655 0, VOIDmode
, 1, tramp
, Pmode
);
5666 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
5667 GEN_INT (0x83414000));
5668 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
5669 GEN_INT (0xca586018));
5670 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
5671 GEN_INT (0x81c14000));
5672 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
5673 GEN_INT (0xca586010));
5674 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
5675 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
5676 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
5678 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
)
5679 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
5682 /* Subroutines to support a flat (single) register window calling
5685 /* Single-register window sparc stack frames look like:
5687 Before call After call
5688 +-----------------------+ +-----------------------+
5690 mem | caller's temps. | | caller's temps. |
5692 +-----------------------+ +-----------------------+
5694 | arguments on stack. | | arguments on stack. |
5696 +-----------------------+FP+92->+-----------------------+
5697 | 6 words to save | | 6 words to save |
5698 | arguments passed | | arguments passed |
5699 | in registers, even | | in registers, even |
5700 | if not passed. | | if not passed. |
5701 SP+68->+-----------------------+FP+68->+-----------------------+
5702 | 1 word struct addr | | 1 word struct addr |
5703 +-----------------------+FP+64->+-----------------------+
5705 | 16 word reg save area | | 16 word reg save area |
5707 SP->+-----------------------+ FP->+-----------------------+
5709 | fp/alu reg moves |
5710 FP-16->+-----------------------+
5714 +-----------------------+
5716 | fp register save |
5718 +-----------------------+
5720 | gp register save |
5722 +-----------------------+
5724 | alloca allocations |
5726 +-----------------------+
5728 | arguments on stack |
5730 SP+92->+-----------------------+
5732 | arguments passed |
5733 | in registers, even |
5734 low | if not passed. |
5735 memory SP+68->+-----------------------+
5736 | 1 word struct addr |
5737 SP+64->+-----------------------+
5739 I 16 word reg save area |
5741 SP->+-----------------------+ */
5743 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5744 save masks, and offsets for the current function. */
5746 struct sparc_frame_info
5748 unsigned long total_size
; /* # bytes that the entire frame takes up. */
5749 unsigned long var_size
; /* # bytes that variables take up. */
5750 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
5751 unsigned long extra_size
; /* # bytes of extra gunk. */
5752 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
5753 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
5754 unsigned long gmask
; /* Mask of saved gp registers. */
5755 unsigned long fmask
; /* Mask of saved fp registers. */
5756 unsigned long reg_offset
; /* Offset from new sp to store regs. */
5757 int initialized
; /* Nonzero if frame size already calculated. */
5760 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5761 struct sparc_frame_info current_frame_info
;
5763 /* Zero structure to initialize current_frame_info. */
5764 struct sparc_frame_info zero_frame_info
;
5766 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5768 #define RETURN_ADDR_REGNUM 15
5769 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5770 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5772 #define MUST_SAVE_REGISTER(regno) \
5773 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5774 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5775 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5777 /* Return the bytes needed to compute the frame pointer from the current
5781 sparc_flat_compute_frame_size (size
)
5782 int size
; /* # of var. bytes allocated. */
5785 unsigned long total_size
; /* # bytes that the entire frame takes up. */
5786 unsigned long var_size
; /* # bytes that variables take up. */
5787 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
5788 unsigned long extra_size
; /* # extra bytes. */
5789 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
5790 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
5791 unsigned long gmask
; /* Mask of saved gp registers. */
5792 unsigned long fmask
; /* Mask of saved fp registers. */
5793 unsigned long reg_offset
; /* Offset to register save area. */
5794 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
5796 /* This is the size of the 16 word reg save area, 1 word struct addr
5797 area, and 4 word fp/alu register copy area. */
5798 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
5808 if (!leaf_function_p ())
5810 /* Also include the size needed for the 6 parameter registers. */
5811 args_size
= current_function_outgoing_args_size
+ 24;
5813 total_size
= var_size
+ args_size
;
5815 /* Calculate space needed for gp registers. */
5816 for (regno
= 1; regno
<= 31; regno
++)
5818 if (MUST_SAVE_REGISTER (regno
))
5820 /* If we need to save two regs in a row, ensure there's room to bump
5821 up the address to align it to a doubleword boundary. */
5822 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
5824 if (gp_reg_size
% 8 != 0)
5826 gp_reg_size
+= 2 * UNITS_PER_WORD
;
5827 gmask
|= 3 << regno
;
5833 gp_reg_size
+= UNITS_PER_WORD
;
5834 gmask
|= 1 << regno
;
5839 /* Calculate space needed for fp registers. */
5840 for (regno
= 32; regno
<= 63; regno
++)
5842 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
5844 fp_reg_size
+= UNITS_PER_WORD
;
5845 fmask
|= 1 << (regno
- 32);
5852 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
5853 /* Ensure save area is 8 byte aligned if we need it. */
5855 if (need_aligned_p
&& n
!= 0)
5857 total_size
+= 8 - n
;
5858 reg_offset
+= 8 - n
;
5860 total_size
+= gp_reg_size
+ fp_reg_size
;
5863 /* If we must allocate a stack frame at all, we must also allocate
5864 room for register window spillage, so as to be binary compatible
5865 with libraries and operating systems that do not use -mflat. */
5867 total_size
+= extra_size
;
5871 total_size
= SPARC_STACK_ALIGN (total_size
);
5873 /* Save other computed information. */
5874 current_frame_info
.total_size
= total_size
;
5875 current_frame_info
.var_size
= var_size
;
5876 current_frame_info
.args_size
= args_size
;
5877 current_frame_info
.extra_size
= extra_size
;
5878 current_frame_info
.gp_reg_size
= gp_reg_size
;
5879 current_frame_info
.fp_reg_size
= fp_reg_size
;
5880 current_frame_info
.gmask
= gmask
;
5881 current_frame_info
.fmask
= fmask
;
5882 current_frame_info
.reg_offset
= reg_offset
;
5883 current_frame_info
.initialized
= reload_completed
;
5885 /* Ok, we're done. */
5889 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5892 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5893 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5894 [BASE_REG+OFFSET] will always be a valid address.
5896 WORD_OP is either "st" for save, "ld" for restore.
5897 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5900 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
,
5901 doubleword_op
, base_offset
)
5903 const char *base_reg
;
5904 unsigned int offset
;
5905 unsigned long gmask
;
5906 unsigned long fmask
;
5907 const char *word_op
;
5908 const char *doubleword_op
;
5909 unsigned long base_offset
;
5913 if (gmask
== 0 && fmask
== 0)
5916 /* Save registers starting from high to low. We've already saved the
5917 previous frame pointer and previous return address for the debugger's
5918 sake. The debugger allows us to not need a nop in the epilog if at least
5919 one register is reloaded in addition to return address. */
5923 for (regno
= 1; regno
<= 31; regno
++)
5925 if ((gmask
& (1L << regno
)) != 0)
5927 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
5929 /* We can save two registers in a row. If we're not at a
5930 double word boundary, move to one.
5931 sparc_flat_compute_frame_size ensures there's room to do
5933 if (offset
% 8 != 0)
5934 offset
+= UNITS_PER_WORD
;
5936 if (word_op
[0] == 's')
5938 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
5939 doubleword_op
, reg_names
[regno
],
5941 if (dwarf2out_do_frame ())
5943 char *l
= dwarf2out_cfi_label ();
5944 dwarf2out_reg_save (l
, regno
, offset
+ base_offset
);
5946 (l
, regno
+1, offset
+base_offset
+ UNITS_PER_WORD
);
5950 fprintf (file
, "\t%s\t[%s+%d], %s\n",
5951 doubleword_op
, base_reg
, offset
,
5954 offset
+= 2 * UNITS_PER_WORD
;
5959 if (word_op
[0] == 's')
5961 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
5962 word_op
, reg_names
[regno
],
5964 if (dwarf2out_do_frame ())
5965 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
5968 fprintf (file
, "\t%s\t[%s+%d], %s\n",
5969 word_op
, base_reg
, offset
, reg_names
[regno
]);
5971 offset
+= UNITS_PER_WORD
;
5979 for (regno
= 32; regno
<= 63; regno
++)
5981 if ((fmask
& (1L << (regno
- 32))) != 0)
5983 if (word_op
[0] == 's')
5985 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
5986 word_op
, reg_names
[regno
],
5988 if (dwarf2out_do_frame ())
5989 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
5992 fprintf (file
, "\t%s\t[%s+%d], %s\n",
5993 word_op
, base_reg
, offset
, reg_names
[regno
]);
5995 offset
+= UNITS_PER_WORD
;
6001 /* Set up the stack and frame (if desired) for the function. */
6004 sparc_flat_output_function_prologue (file
, size
)
6008 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
6009 unsigned long gmask
= current_frame_info
.gmask
;
6011 sparc_output_scratch_registers (file
);
6013 /* This is only for the human reader. */
6014 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
6015 fprintf (file
, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6017 current_frame_info
.var_size
,
6018 current_frame_info
.gp_reg_size
/ 4,
6019 current_frame_info
.fp_reg_size
/ 4,
6020 current_function_outgoing_args_size
,
6021 current_frame_info
.extra_size
);
6023 size
= SPARC_STACK_ALIGN (size
);
6024 size
= (! current_frame_info
.initialized
6025 ? sparc_flat_compute_frame_size (size
)
6026 : current_frame_info
.total_size
);
6028 /* These cases shouldn't happen. Catch them now. */
6029 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
6032 /* Allocate our stack frame by decrementing %sp.
6033 At present, the only algorithm gdb can use to determine if this is a
6034 flat frame is if we always set %i7 if we set %sp. This can be optimized
6035 in the future by putting in some sort of debugging information that says
6036 this is a `flat' function. However, there is still the case of debugging
6037 code without such debugging information (including cases where most fns
6038 have such info, but there is one that doesn't). So, always do this now
6039 so we don't get a lot of code out there that gdb can't handle.
6040 If the frame pointer isn't needn't then that's ok - gdb won't be able to
6041 distinguish us from a non-flat function but there won't (and shouldn't)
6042 be any differences anyway. The return pc is saved (if necessary) right
6043 after %i7 so gdb won't have to look too far to find it. */
6046 unsigned int reg_offset
= current_frame_info
.reg_offset
;
6047 const char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
6048 const char *t1_str
= "%g1";
6050 /* Things get a little tricky if local variables take up more than ~4096
6051 bytes and outgoing arguments take up more than ~4096 bytes. When that
6052 happens, the register save area can't be accessed from either end of
6053 the frame. Handle this by decrementing %sp to the start of the gp
6054 register save area, save the regs, update %i7, and then set %sp to its
6055 final value. Given that we only have one scratch register to play
6056 with it is the cheapest solution, and it helps gdb out as it won't
6057 slow down recognition of flat functions.
6058 Don't change the order of insns emitted here without checking with
6059 the gdb folk first. */
6061 /* Is the entire register save area offsettable from %sp? */
6062 if (reg_offset
< 4096 - 64 * UNITS_PER_WORD
)
6066 fprintf (file
, "\tadd\t%s, %d, %s\n",
6067 sp_str
, -size
, sp_str
);
6068 if (gmask
& FRAME_POINTER_MASK
)
6070 fprintf (file
, "\tst\t%s, [%s+%d]\n",
6071 fp_str
, sp_str
, reg_offset
);
6072 fprintf (file
, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6073 sp_str
, -size
, fp_str
, ASM_COMMENT_START
);
6079 fprintf (file
, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6080 size
, t1_str
, sp_str
, t1_str
, sp_str
);
6081 if (gmask
& FRAME_POINTER_MASK
)
6083 fprintf (file
, "\tst\t%s, [%s+%d]\n",
6084 fp_str
, sp_str
, reg_offset
);
6085 fprintf (file
, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6086 sp_str
, t1_str
, fp_str
, ASM_COMMENT_START
);
6090 if (dwarf2out_do_frame ())
6092 char *l
= dwarf2out_cfi_label ();
6093 if (gmask
& FRAME_POINTER_MASK
)
6095 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
,
6096 reg_offset
- 4 - size
);
6097 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, 0);
6100 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size
);
6102 if (gmask
& RETURN_ADDR_MASK
)
6104 fprintf (file
, "\tst\t%s, [%s+%d]\n",
6105 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
6106 if (dwarf2out_do_frame ())
6107 dwarf2out_return_save ("", reg_offset
- size
);
6110 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
6111 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
6112 current_frame_info
.fmask
,
6113 "st", "std", -size
);
6117 /* Subtract %sp in two steps, but make sure there is always a
6118 64 byte register save area, and %sp is properly aligned. */
6119 /* Amount to decrement %sp by, the first time. */
6120 unsigned int size1
= ((size
- reg_offset
+ 64) + 15) & -16;
6121 /* Offset to register save area from %sp. */
6122 unsigned int offset
= size1
- (size
- reg_offset
);
6126 fprintf (file
, "\tadd\t%s, %d, %s\n",
6127 sp_str
, -size1
, sp_str
);
6128 if (gmask
& FRAME_POINTER_MASK
)
6130 fprintf (file
, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
6131 fp_str
, sp_str
, offset
, sp_str
, -size1
, fp_str
,
6138 fprintf (file
, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6139 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
6140 if (gmask
& FRAME_POINTER_MASK
)
6142 fprintf (file
, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
6143 fp_str
, sp_str
, offset
, sp_str
, t1_str
, fp_str
,
6148 if (dwarf2out_do_frame ())
6150 char *l
= dwarf2out_cfi_label ();
6151 if (gmask
& FRAME_POINTER_MASK
)
6153 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
,
6154 offset
- 4 - size1
);
6155 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, 0);
6158 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size1
);
6160 if (gmask
& RETURN_ADDR_MASK
)
6162 fprintf (file
, "\tst\t%s, [%s+%d]\n",
6163 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, offset
);
6164 if (dwarf2out_do_frame ())
6165 /* offset - size1 == reg_offset - size
6166 if reg_offset were updated above like offset. */
6167 dwarf2out_return_save ("", offset
- size1
);
6170 sparc_flat_save_restore (file
, sp_str
, offset
,
6171 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
6172 current_frame_info
.fmask
,
6173 "st", "std", -size1
);
6174 fprintf (file
, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
6175 size
- size1
, t1_str
, sp_str
, t1_str
, sp_str
);
6176 if (dwarf2out_do_frame ())
6177 if (! (gmask
& FRAME_POINTER_MASK
))
6178 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, size
);
6182 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
6185 /* Do any necessary cleanup after a function to restore stack, frame,
6189 sparc_flat_output_function_epilogue (file
, size
)
6193 rtx epilogue_delay
= current_function_epilogue_delay_list
;
6194 int noepilogue
= FALSE
;
6196 /* This is only for the human reader. */
6197 fprintf (file
, "\t%s#EPILOGUE#\n", ASM_COMMENT_START
);
6199 /* The epilogue does not depend on any registers, but the stack
6200 registers, so we assume that if we have 1 pending nop, it can be
6201 ignored, and 2 it must be filled (2 nops occur for integer
6202 multiply and divide). */
6204 size
= SPARC_STACK_ALIGN (size
);
6205 size
= (!current_frame_info
.initialized
6206 ? sparc_flat_compute_frame_size (size
)
6207 : current_frame_info
.total_size
);
6209 if (size
== 0 && epilogue_delay
== 0)
6211 rtx insn
= get_last_insn ();
6213 /* If the last insn was a BARRIER, we don't have to write any code
6214 because a jump (aka return) was put there. */
6215 if (GET_CODE (insn
) == NOTE
)
6216 insn
= prev_nonnote_insn (insn
);
6217 if (insn
&& GET_CODE (insn
) == BARRIER
)
6223 unsigned int reg_offset
= current_frame_info
.reg_offset
;
6225 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
6226 const char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
6227 const char *t1_str
= "%g1";
6229 /* In the reload sequence, we don't need to fill the load delay
6230 slots for most of the loads, also see if we can fill the final
6231 delay slot if not otherwise filled by the reload sequence. */
6234 fprintf (file
, "\tset\t%d, %s\n", size
, t1_str
);
6236 if (frame_pointer_needed
)
6239 fprintf (file
,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
6240 fp_str
, t1_str
, sp_str
, ASM_COMMENT_START
);
6242 fprintf (file
,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
6243 fp_str
, size
, sp_str
, ASM_COMMENT_START
);
6246 /* Is the entire register save area offsettable from %sp? */
6247 if (reg_offset
< 4096 - 64 * UNITS_PER_WORD
)
6253 /* Restore %sp in two steps, but make sure there is always a
6254 64 byte register save area, and %sp is properly aligned. */
6255 /* Amount to increment %sp by, the first time. */
6256 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
6257 /* Offset to register save area from %sp. */
6258 reg_offset
= size1
- reg_offset
;
6260 fprintf (file
, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
6261 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
6264 /* We must restore the frame pointer and return address reg first
6265 because they are treated specially by the prologue output code. */
6266 if (current_frame_info
.gmask
& FRAME_POINTER_MASK
)
6268 fprintf (file
, "\tld\t[%s+%d], %s\n",
6269 sp_str
, reg_offset
, fp_str
);
6272 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
6274 fprintf (file
, "\tld\t[%s+%d], %s\n",
6275 sp_str
, reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
6279 /* Restore any remaining saved registers. */
6280 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
6281 current_frame_info
.gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
6282 current_frame_info
.fmask
,
6285 /* If we had to increment %sp in two steps, record it so the second
6286 restoration in the epilogue finishes up. */
6291 fprintf (file
, "\tset\t%d, %s\n",
6295 if (current_function_returns_struct
)
6296 fprintf (file
, "\tjmp\t%%o7+12\n");
6298 fprintf (file
, "\tretl\n");
6300 /* If the only register saved is the return address, we need a
6301 nop, unless we have an instruction to put into it. Otherwise
6302 we don't since reloading multiple registers doesn't reference
6303 the register being loaded. */
6309 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
6312 else if (size
> 4095)
6313 fprintf (file
, "\tadd\t%s, %s, %s\n", sp_str
, t1_str
, sp_str
);
6316 fprintf (file
, "\tadd\t%s, %d, %s\n", sp_str
, size
, sp_str
);
6319 fprintf (file
, "\tnop\n");
6322 /* Reset state info for each function. */
6323 current_frame_info
= zero_frame_info
;
6325 sparc_output_deferred_case_vectors ();
6328 /* Define the number of delay slots needed for the function epilogue.
6330 On the sparc, we need a slot if either no stack has been allocated,
6331 or the only register saved is the return register. */
6334 sparc_flat_epilogue_delay_slots ()
6336 if (!current_frame_info
.initialized
)
6337 (void) sparc_flat_compute_frame_size (get_frame_size ());
6339 if (current_frame_info
.total_size
== 0)
6345 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
6346 Any single length instruction which doesn't reference the stack or frame
6350 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
6352 int slot ATTRIBUTE_UNUSED
;
6354 rtx pat
= PATTERN (trial
);
6356 if (get_attr_length (trial
) != 1)
6359 /* If %g0 is live, there are lots of things we can't handle.
6360 Rather than trying to find them all now, let's punt and only
6361 optimize things as necessary. */
6365 if (! reg_mentioned_p (stack_pointer_rtx
, pat
)
6366 && ! reg_mentioned_p (frame_pointer_rtx
, pat
))
6372 /* Adjust the cost of a scheduling dependency. Return the new cost of
6373 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6376 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
6382 enum attr_type insn_type
;
6384 if (! recog_memoized (insn
))
6387 insn_type
= get_attr_type (insn
);
6389 if (REG_NOTE_KIND (link
) == 0)
6391 /* Data dependency; DEP_INSN writes a register that INSN reads some
6394 /* if a load, then the dependence must be on the memory address;
6395 add an extra "cycle". Note that the cost could be two cycles
6396 if the reg was written late in an instruction group; we ca not tell
6398 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
6401 /* Get the delay only if the address of the store is the dependence. */
6402 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
6404 rtx pat
= PATTERN(insn
);
6405 rtx dep_pat
= PATTERN (dep_insn
);
6407 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
6408 return cost
; /* This should not happen! */
6410 /* The dependency between the two instructions was on the data that
6411 is being stored. Assume that this implies that the address of the
6412 store is not dependent. */
6413 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
6416 return cost
+ 3; /* An approximation. */
6419 /* A shift instruction cannot receive its data from an instruction
6420 in the same cycle; add a one cycle penalty. */
6421 if (insn_type
== TYPE_SHIFT
)
6422 return cost
+ 3; /* Split before cascade into shift. */
6426 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6427 INSN writes some cycles later. */
6429 /* These are only significant for the fpu unit; writing a fp reg before
6430 the fpu has finished with it stalls the processor. */
6432 /* Reusing an integer register causes no problems. */
6433 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
6441 hypersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
6447 enum attr_type insn_type
, dep_type
;
6448 rtx pat
= PATTERN(insn
);
6449 rtx dep_pat
= PATTERN (dep_insn
);
6451 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
6454 insn_type
= get_attr_type (insn
);
6455 dep_type
= get_attr_type (dep_insn
);
6457 switch (REG_NOTE_KIND (link
))
6460 /* Data dependency; DEP_INSN writes a register that INSN reads some
6467 /* Get the delay iff the address of the store is the dependence. */
6468 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
6471 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
6478 /* If a load, then the dependence must be on the memory address. If
6479 the addresses aren't equal, then it might be a false dependency */
6480 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
6482 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
6483 || GET_CODE (SET_DEST (dep_pat
)) != MEM
6484 || GET_CODE (SET_SRC (pat
)) != MEM
6485 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
6486 XEXP (SET_SRC (pat
), 0)))
6494 /* Compare to branch latency is 0. There is no benefit from
6495 separating compare and branch. */
6496 if (dep_type
== TYPE_COMPARE
)
6498 /* Floating point compare to branch latency is less than
6499 compare to conditional move. */
6500 if (dep_type
== TYPE_FPCMP
)
6509 /* Anti-dependencies only penalize the fpu unit. */
6510 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
6522 ultrasparc_adjust_cost (insn
, link
, dep_insn
, cost
)
6528 enum attr_type insn_type
, dep_type
;
6529 rtx pat
= PATTERN(insn
);
6530 rtx dep_pat
= PATTERN (dep_insn
);
6532 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
6535 insn_type
= get_attr_type (insn
);
6536 dep_type
= get_attr_type (dep_insn
);
6538 /* Nothing issues in parallel with integer multiplies, so
6539 mark as zero cost since the scheduler can not do anything
6541 if (insn_type
== TYPE_IMUL
)
6544 #define SLOW_FP(dep_type) \
6545 (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \
6546 dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
6548 switch (REG_NOTE_KIND (link
))
6551 /* Data dependency; DEP_INSN writes a register that INSN reads some
6554 if (dep_type
== TYPE_CMOVE
)
6556 /* Instructions that read the result of conditional moves cannot
6557 be in the same group or the following group. */
6563 /* UltraSPARC can dual issue a store and an instruction setting
6564 the value stored, except for divide and square root. */
6566 if (! SLOW_FP (dep_type
))
6571 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
6574 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
6575 /* The dependency between the two instructions is on the data
6576 that is being stored. Assume that the address of the store
6577 is not also dependent. */
6584 /* A load does not return data until at least 11 cycles after
6585 a store to the same location. 3 cycles are accounted for
6586 in the load latency; add the other 8 here. */
6587 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
6589 /* If the addresses are not equal this may be a false
6590 dependency because pointer aliasing could not be
6591 determined. Add only 2 cycles in that case. 2 is
6592 an arbitrary compromise between 8, which would cause
6593 the scheduler to generate worse code elsewhere to
6594 compensate for a dependency which might not really
6596 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
6597 || GET_CODE (SET_SRC (pat
)) != MEM
6598 || GET_CODE (SET_DEST (dep_pat
)) != MEM
6599 || ! rtx_equal_p (XEXP (SET_SRC (pat
), 0),
6600 XEXP (SET_DEST (dep_pat
), 0)))
6608 /* Compare to branch latency is 0. There is no benefit from
6609 separating compare and branch. */
6610 if (dep_type
== TYPE_COMPARE
)
6612 /* Floating point compare to branch latency is less than
6613 compare to conditional move. */
6614 if (dep_type
== TYPE_FPCMP
)
6619 /* FMOVR class instructions can not issue in the same cycle
6620 or the cycle after an instruction which writes any
6621 integer register. Model this as cost 2 for dependent
6623 if ((dep_type
== TYPE_IALU
|| dep_type
== TYPE_UNARY
6624 || dep_type
== TYPE_BINARY
)
6627 /* Otherwise check as for integer conditional moves. */
6630 /* Conditional moves involving integer registers wait until
6631 3 cycles after loads return data. The interlock applies
6632 to all loads, not just dependent loads, but that is hard
6634 if (dep_type
== TYPE_LOAD
|| dep_type
== TYPE_SLOAD
)
6644 /* Divide and square root lock destination registers for full latency. */
6645 if (! SLOW_FP (dep_type
))
6649 case REG_DEP_OUTPUT
:
6650 /* IEU and FPU instruction that have the same destination
6651 register cannot be grouped together. */
6658 /* Other costs not accounted for:
6659 - Single precision floating point loads lock the other half of
6660 the even/odd register pair.
6661 - Several hazards associated with ldd/std are ignored because these
6662 instructions are rarely generated for V9.
6663 - The floating point pipeline can not have both a single and double
6664 precision operation active at the same time. Format conversions
6665 and graphics instructions are given honorary double precision status.
6666 - call and jmpl are always the first instruction in a group. */
6674 sparc_adjust_cost(insn
, link
, dep
, cost
)
6682 case PROCESSOR_SUPERSPARC
:
6683 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
6685 case PROCESSOR_HYPERSPARC
:
6686 case PROCESSOR_SPARCLITE86X
:
6687 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
6689 case PROCESSOR_ULTRASPARC
:
6690 cost
= ultrasparc_adjust_cost (insn
, link
, dep
, cost
);
6698 /* This describes the state of the UltraSPARC pipeline during
6699 instruction scheduling. */
6701 #define TMASK(__x) ((unsigned)1 << ((int)(__x)))
6702 #define UMASK(__x) ((unsigned)1 << ((int)(__x)))
6704 enum ultra_code
{ NONE
=0, /* no insn at all */
6705 IEU0
, /* shifts and conditional moves */
6706 IEU1
, /* condition code setting insns, calls+jumps */
6707 IEUN
, /* all other single cycle ieu insns */
6708 LSU
, /* loads and stores */
6710 FPM
, /* FPU pipeline 1, multiplies and divides */
6711 FPA
, /* FPU pipeline 2, all other operations */
6712 SINGLE
, /* single issue instructions */
6715 static enum ultra_code ultra_code_from_mask
PROTO ((int));
6716 static void ultra_schedule_insn
PROTO ((rtx
*, rtx
*, int, enum ultra_code
));
6718 static const char *ultra_code_names
[NUM_ULTRA_CODES
] = {
6719 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
6720 "FPM", "FPA", "SINGLE" };
6722 struct ultrasparc_pipeline_state
{
6723 /* The insns in this group. */
6726 /* The code for each insn. */
6727 enum ultra_code codes
[4];
6729 /* Which insns in this group have been committed by the
6730 scheduler. This is how we determine how many more
6731 can issue this cycle. */
6734 /* How many insns in this group. */
6737 /* Mask of free slots still in this group. */
6738 char free_slot_mask
;
6740 /* The slotter uses the following to determine what other
6741 insn types can still make their way into this group. */
6742 char contents
[NUM_ULTRA_CODES
];
6746 #define ULTRA_NUM_HIST 8
6747 static struct ultrasparc_pipeline_state ultra_pipe_hist
[ULTRA_NUM_HIST
];
6748 static int ultra_cur_hist
;
6749 static int ultra_cycles_elapsed
;
6751 #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
6753 /* Given TYPE_MASK compute the ultra_code it has. */
6754 static enum ultra_code
6755 ultra_code_from_mask (type_mask
)
6758 if (type_mask
& (TMASK (TYPE_SHIFT
) | TMASK (TYPE_CMOVE
)))
6760 else if (type_mask
& (TMASK (TYPE_COMPARE
) |
6762 TMASK (TYPE_UNCOND_BRANCH
)))
6764 else if (type_mask
& (TMASK (TYPE_IALU
) | TMASK (TYPE_BINARY
) |
6765 TMASK (TYPE_MOVE
) | TMASK (TYPE_UNARY
)))
6767 else if (type_mask
& (TMASK (TYPE_LOAD
) | TMASK (TYPE_SLOAD
) |
6768 TMASK (TYPE_STORE
) | TMASK (TYPE_FPLOAD
) |
6769 TMASK (TYPE_FPSTORE
)))
6771 else if (type_mask
& (TMASK (TYPE_FPMUL
) | TMASK (TYPE_FPDIVS
) |
6772 TMASK (TYPE_FPDIVD
) | TMASK (TYPE_FPSQRTS
) |
6773 TMASK (TYPE_FPSQRTD
)))
6775 else if (type_mask
& (TMASK (TYPE_FPMOVE
) | TMASK (TYPE_FPCMOVE
) |
6776 TMASK (TYPE_FP
) | TMASK (TYPE_FPCMP
)))
6778 else if (type_mask
& TMASK (TYPE_BRANCH
))
6784 /* Check INSN (a conditional move) and make sure that it's
6785 results are available at this cycle. Return 1 if the
6786 results are in fact ready. */
6788 ultra_cmove_results_ready_p (insn
)
6791 struct ultrasparc_pipeline_state
*up
;
6794 /* If this got dispatched in the previous
6795 group, the results are not ready. */
6796 entry
= (ultra_cur_hist
- 1) % (ULTRA_NUM_HIST
- 1);
6797 up
= &ultra_pipe_hist
[entry
];
6800 if (up
->group
[slot
] == insn
)
6806 /* Walk backwards in pipeline history looking for FPU
6807 operations which use a mode different than FPMODE and
6808 will create a stall if an insn using FPMODE were to be
6809 dispatched this cycle. */
6811 ultra_fpmode_conflict_exists (fpmode
)
6812 enum machine_mode fpmode
;
6817 hist_ent
= (ultra_cur_hist
- 1) % (ULTRA_NUM_HIST
- 1);
6818 if (ultra_cycles_elapsed
< 4)
6819 hist_lim
= ultra_cycles_elapsed
;
6822 while (hist_lim
> 0)
6824 struct ultrasparc_pipeline_state
*up
= &ultra_pipe_hist
[hist_ent
];
6829 rtx insn
= up
->group
[slot
];
6830 enum machine_mode this_mode
;
6834 || GET_CODE (insn
) != INSN
6835 || (pat
= PATTERN (insn
)) == 0
6836 || GET_CODE (pat
) != SET
)
6839 this_mode
= GET_MODE (SET_DEST (pat
));
6840 if ((this_mode
!= SFmode
6841 && this_mode
!= DFmode
)
6842 || this_mode
== fpmode
)
6845 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
6846 we will get a stall. Loads and stores are independant
6848 if (GET_CODE (SET_SRC (pat
)) != ABS
6849 && GET_CODE (SET_SRC (pat
)) != NEG
6850 && ((TMASK (get_attr_type (insn
)) &
6851 (TMASK (TYPE_FPDIVS
) | TMASK (TYPE_FPDIVD
) |
6852 TMASK (TYPE_FPMOVE
) | TMASK (TYPE_FPSQRTS
) |
6853 TMASK (TYPE_FPSQRTD
) |
6854 TMASK (TYPE_LOAD
) | TMASK (TYPE_STORE
))) == 0))
6858 hist_ent
= (hist_ent
- 1) % (ULTRA_NUM_HIST
- 1);
6861 /* No conflicts, safe to dispatch. */
6865 /* Find an instruction in LIST which has one of the
6866 type attributes enumerated in TYPE_MASK. START
6867 says where to begin the search.
6869 NOTE: This scheme depends upon the fact that we
6870 have less than 32 distinct type attributes. */
6872 static int ultra_types_avail
;
6875 ultra_find_type (type_mask
, list
, start
)
6882 /* Short circuit if no such insn exists in the ready
6884 if ((type_mask
& ultra_types_avail
) == 0)
6887 for (i
= start
; i
>= 0; i
--)
6891 if (recog_memoized (insn
) >= 0
6892 && (TMASK(get_attr_type (insn
)) & type_mask
))
6894 enum machine_mode fpmode
= SFmode
;
6897 int check_depend
= 0;
6898 int check_fpmode_conflict
= 0;
6900 if (GET_CODE (insn
) == INSN
6901 && (pat
= PATTERN(insn
)) != 0
6902 && GET_CODE (pat
) == SET
6903 && !(type_mask
& (TMASK (TYPE_STORE
) |
6904 TMASK (TYPE_FPSTORE
))))
6907 if (GET_MODE (SET_DEST (pat
)) == SFmode
6908 || GET_MODE (SET_DEST (pat
)) == DFmode
)
6910 fpmode
= GET_MODE (SET_DEST (pat
));
6911 check_fpmode_conflict
= 1;
6918 rtx slot_insn
= ultra_pipe
.group
[slot
];
6921 /* Already issued, bad dependency, or FPU
6924 && (slot_pat
= PATTERN (slot_insn
)) != 0
6925 && ((insn
== slot_insn
)
6926 || (check_depend
== 1
6927 && GET_CODE (slot_insn
) == INSN
6928 && GET_CODE (slot_pat
) == SET
6929 && ((GET_CODE (SET_DEST (slot_pat
)) == REG
6930 && GET_CODE (SET_SRC (pat
)) == REG
6931 && REGNO (SET_DEST (slot_pat
)) ==
6932 REGNO (SET_SRC (pat
)))
6933 || (GET_CODE (SET_DEST (slot_pat
)) == SUBREG
6934 && GET_CODE (SET_SRC (pat
)) == SUBREG
6935 && REGNO (SUBREG_REG (SET_DEST (slot_pat
))) ==
6936 REGNO (SUBREG_REG (SET_SRC (pat
)))
6937 && SUBREG_WORD (SET_DEST (slot_pat
)) ==
6938 SUBREG_WORD (SET_SRC (pat
)))))
6939 || (check_fpmode_conflict
== 1
6940 && GET_CODE (slot_insn
) == INSN
6941 && GET_CODE (slot_pat
) == SET
6942 && (GET_MODE (SET_DEST (slot_pat
)) == SFmode
6943 || GET_MODE (SET_DEST (slot_pat
)) == DFmode
)
6944 && GET_MODE (SET_DEST (slot_pat
)) != fpmode
)))
6948 /* Check for peculiar result availability and dispatch
6949 interference situations. */
6951 && ultra_cycles_elapsed
> 0)
6955 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
6957 rtx link_insn
= XEXP (link
, 0);
6958 if (GET_CODE (link_insn
) == INSN
6959 && recog_memoized (link_insn
) >= 0
6960 && (TMASK (get_attr_type (link_insn
)) &
6961 (TMASK (TYPE_CMOVE
) | TMASK (TYPE_FPCMOVE
)))
6962 && ! ultra_cmove_results_ready_p (link_insn
))
6966 if (check_fpmode_conflict
6967 && ultra_fpmode_conflict_exists (fpmode
))
6980 ultra_build_types_avail (ready
, n_ready
)
6984 int i
= n_ready
- 1;
6986 ultra_types_avail
= 0;
6989 rtx insn
= ready
[i
];
6991 if (recog_memoized (insn
) >= 0)
6992 ultra_types_avail
|= TMASK (get_attr_type (insn
));
6998 /* Place insn pointed to my IP into the pipeline.
6999 Make element THIS of READY be that insn if it
7000 is not already. TYPE indicates the pipeline class
7001 this insn falls into. */
7003 ultra_schedule_insn (ip
, ready
, this, type
)
7007 enum ultra_code type
;
7010 char mask
= ultra_pipe
.free_slot_mask
;
7013 /* Obtain free slot. */
7014 for (pipe_slot
= 0; pipe_slot
< 4; pipe_slot
++)
7015 if ((mask
& (1 << pipe_slot
)) != 0)
7020 /* In it goes, and it hasn't been committed yet. */
7021 ultra_pipe
.group
[pipe_slot
] = *ip
;
7022 ultra_pipe
.codes
[pipe_slot
] = type
;
7023 ultra_pipe
.contents
[type
] = 1;
7025 (UMASK (IEUN
) | UMASK (IEU0
) | UMASK (IEU1
)))
7026 ultra_pipe
.num_ieu_insns
+= 1;
7028 ultra_pipe
.free_slot_mask
= (mask
& ~(1 << pipe_slot
));
7029 ultra_pipe
.group_size
+= 1;
7030 ultra_pipe
.commit
[pipe_slot
] = 0;
7032 /* Update ready list. */
7034 while (ip
!= &ready
[this])
7042 /* Advance to the next pipeline group. */
7044 ultra_flush_pipeline ()
7046 ultra_cur_hist
= (ultra_cur_hist
+ 1) % (ULTRA_NUM_HIST
- 1);
7047 ultra_cycles_elapsed
+= 1;
7048 bzero ((char *) &ultra_pipe
, sizeof ultra_pipe
);
7049 ultra_pipe
.free_slot_mask
= 0xf;
7052 /* Init our data structures for this current block. */
7054 ultrasparc_sched_init (dump
, sched_verbose
)
7055 FILE *dump ATTRIBUTE_UNUSED
;
7056 int sched_verbose ATTRIBUTE_UNUSED
;
7058 bzero ((char *) ultra_pipe_hist
, sizeof ultra_pipe_hist
);
7060 ultra_cycles_elapsed
= 0;
7061 ultra_pipe
.free_slot_mask
= 0xf;
7064 /* INSN has been scheduled, update pipeline commit state
7065 and return how many instructions are still to be
7066 scheduled in this group. */
7068 ultrasparc_variable_issue (insn
)
7071 struct ultrasparc_pipeline_state
*up
= &ultra_pipe
;
7072 int i
, left_to_fire
;
7075 for (i
= 0; i
< 4; i
++)
7077 if (up
->group
[i
] == 0)
7080 if (up
->group
[i
] == insn
)
7084 else if (! up
->commit
[i
])
7088 return left_to_fire
;
7091 /* In actual_hazard_this_instance, we may have yanked some
7092 instructions from the ready list due to conflict cost
7093 adjustments. If so, and such an insn was in our pipeline
7094 group, remove it and update state. */
7096 ultra_rescan_pipeline_state (ready
, n_ready
)
7100 struct ultrasparc_pipeline_state
*up
= &ultra_pipe
;
7103 for (i
= 0; i
< 4; i
++)
7105 rtx insn
= up
->group
[i
];
7111 /* If it has been committed, then it was removed from
7112 the ready list because it was actually scheduled,
7113 and that is not the case we are searching for here. */
7114 if (up
->commit
[i
] != 0)
7117 for (j
= n_ready
- 1; j
>= 0; j
--)
7118 if (ready
[j
] == insn
)
7121 /* If we didn't find it, toss it. */
7124 enum ultra_code ucode
= up
->codes
[i
];
7127 up
->codes
[i
] = NONE
;
7128 up
->contents
[ucode
] = 0;
7130 (UMASK (IEUN
) | UMASK (IEU0
) | UMASK (IEU1
)))
7131 up
->num_ieu_insns
-= 1;
7133 up
->free_slot_mask
|= (1 << i
);
7134 up
->group_size
-= 1;
7141 ultrasparc_sched_reorder (dump
, sched_verbose
, ready
, n_ready
)
7147 struct ultrasparc_pipeline_state
*up
= &ultra_pipe
;
7154 fprintf (dump
, "\n;;\tUltraSPARC Looking at [");
7155 for (n
= n_ready
- 1; n
>= 0; n
--)
7157 rtx insn
= ready
[n
];
7158 enum ultra_code ucode
;
7160 if (recog_memoized (insn
) < 0)
7162 ucode
= ultra_code_from_mask (TMASK (get_attr_type (insn
)));
7164 fprintf (dump
, "%s(%d) ",
7165 ultra_code_names
[ucode
],
7168 fprintf (dump
, "%s(%d)",
7169 ultra_code_names
[ucode
],
7172 fprintf (dump
, "]\n");
7175 this_insn
= n_ready
- 1;
7177 /* Skip over junk we don't understand. */
7178 while ((this_insn
>= 0)
7179 && recog_memoized (ready
[this_insn
]) < 0)
7182 ultra_build_types_avail (ready
, this_insn
+ 1);
7184 while (this_insn
>= 0) {
7185 int old_group_size
= up
->group_size
;
7187 if (up
->group_size
!= 0)
7191 num_committed
= (up
->commit
[0] + up
->commit
[1] +
7192 up
->commit
[2] + up
->commit
[3]);
7193 /* If nothing has been commited from our group, or all of
7194 them have. Clear out the (current cycle's) pipeline
7195 state and start afresh. */
7196 if (num_committed
== 0
7197 || num_committed
== up
->group_size
)
7199 ultra_flush_pipeline ();
7205 /* OK, some ready list insns got requeued and thus removed
7206 from the ready list. Account for this fact. */
7207 ultra_rescan_pipeline_state (ready
, n_ready
);
7209 /* Something "changed", make this look like a newly
7210 formed group so the code at the end of the loop
7211 knows that progress was in fact made. */
7212 if (up
->group_size
!= old_group_size
)
7217 if (up
->group_size
== 0)
7219 /* If the pipeline is (still) empty and we have any single
7220 group insns, get them out now as this is a good time. */
7221 rtx
*ip
= ultra_find_type ((TMASK (TYPE_RETURN
) | TMASK (TYPE_ADDRESS
) |
7222 TMASK (TYPE_IMUL
) | TMASK (TYPE_CMOVE
) |
7223 TMASK (TYPE_MULTI
) | TMASK (TYPE_MISC
)),
7227 ultra_schedule_insn (ip
, ready
, this_insn
, SINGLE
);
7231 /* If we are not in the process of emptying out the pipe, try to
7232 obtain an instruction which must be the first in it's group. */
7233 ip
= ultra_find_type ((TMASK (TYPE_CALL
) |
7234 TMASK (TYPE_CALL_NO_DELAY_SLOT
) |
7235 TMASK (TYPE_UNCOND_BRANCH
)),
7239 ultra_schedule_insn (ip
, ready
, this_insn
, IEU1
);
7242 else if ((ip
= ultra_find_type ((TMASK (TYPE_FPDIVS
) |
7243 TMASK (TYPE_FPDIVD
) |
7244 TMASK (TYPE_FPSQRTS
) |
7245 TMASK (TYPE_FPSQRTD
)),
7246 ready
, this_insn
)) != 0)
7248 ultra_schedule_insn (ip
, ready
, this_insn
, FPM
);
7253 /* Try to fill the integer pipeline. First, look for an IEU0 specific
7254 operation. We can't do more IEU operations if the first 3 slots are
7255 all full or we have dispatched two IEU insns already. */
7256 if ((up
->free_slot_mask
& 0x7) != 0
7257 && up
->num_ieu_insns
< 2
7258 && up
->contents
[IEU0
] == 0
7259 && up
->contents
[IEUN
] == 0)
7261 rtx
*ip
= ultra_find_type (TMASK(TYPE_SHIFT
), ready
, this_insn
);
7264 ultra_schedule_insn (ip
, ready
, this_insn
, IEU0
);
7269 /* If we can, try to find an IEU1 specific or an unnamed
7271 if ((up
->free_slot_mask
& 0x7) != 0
7272 && up
->num_ieu_insns
< 2)
7274 rtx
*ip
= ultra_find_type ((TMASK (TYPE_IALU
) | TMASK (TYPE_BINARY
) |
7275 TMASK (TYPE_MOVE
) | TMASK (TYPE_UNARY
) |
7276 (up
->contents
[IEU1
] == 0 ? TMASK (TYPE_COMPARE
) : 0)),
7282 ultra_schedule_insn (ip
, ready
, this_insn
,
7283 (!up
->contents
[IEU1
]
7284 && get_attr_type (insn
) == TYPE_COMPARE
)
7290 /* If only one IEU insn has been found, try to find another unnamed
7291 IEU operation or an IEU1 specific one. */
7292 if ((up
->free_slot_mask
& 0x7) != 0
7293 && up
->num_ieu_insns
< 2)
7296 int tmask
= (TMASK (TYPE_IALU
) | TMASK (TYPE_BINARY
) |
7297 TMASK (TYPE_MOVE
) | TMASK (TYPE_UNARY
));
7299 if (!up
->contents
[IEU1
])
7300 tmask
|= TMASK (TYPE_COMPARE
);
7301 ip
= ultra_find_type (tmask
, ready
, this_insn
);
7306 ultra_schedule_insn (ip
, ready
, this_insn
,
7307 (!up
->contents
[IEU1
]
7308 && get_attr_type (insn
) == TYPE_COMPARE
)
7314 /* Try for a load or store, but such an insn can only be issued
7315 if it is within' one of the first 3 slots. */
7316 if ((up
->free_slot_mask
& 0x7) != 0
7317 && up
->contents
[LSU
] == 0)
7319 rtx
*ip
= ultra_find_type ((TMASK (TYPE_LOAD
) | TMASK (TYPE_SLOAD
) |
7320 TMASK (TYPE_STORE
) | TMASK (TYPE_FPLOAD
) |
7321 TMASK (TYPE_FPSTORE
)), ready
, this_insn
);
7324 ultra_schedule_insn (ip
, ready
, this_insn
, LSU
);
7329 /* Now find FPU operations, first FPM class. But not divisions or
7330 square-roots because those will break the group up. Unlike all
7331 the previous types, these can go in any slot. */
7332 if (up
->free_slot_mask
!= 0
7333 && up
->contents
[FPM
] == 0)
7335 rtx
*ip
= ultra_find_type (TMASK (TYPE_FPMUL
), ready
, this_insn
);
7338 ultra_schedule_insn (ip
, ready
, this_insn
, FPM
);
7343 /* Continue on with FPA class if we have not filled the group already. */
7344 if (up
->free_slot_mask
!= 0
7345 && up
->contents
[FPA
] == 0)
7347 rtx
*ip
= ultra_find_type ((TMASK (TYPE_FPMOVE
) | TMASK (TYPE_FPCMOVE
) |
7348 TMASK (TYPE_FP
) | TMASK (TYPE_FPCMP
)),
7352 ultra_schedule_insn (ip
, ready
, this_insn
, FPA
);
7357 /* Finally, maybe stick a branch in here. */
7358 if (up
->free_slot_mask
!= 0
7359 && up
->contents
[CTI
] == 0)
7361 rtx
*ip
= ultra_find_type (TMASK (TYPE_BRANCH
), ready
, this_insn
);
7363 /* Try to slip in a branch only if it is one of the
7364 next 2 in the ready list. */
7365 if (ip
&& ((&ready
[this_insn
] - ip
) < 2))
7367 ultra_schedule_insn (ip
, ready
, this_insn
, CTI
);
7373 for (i
= 0; i
< 4; i
++)
7374 if ((up
->free_slot_mask
& (1 << i
)) == 0)
7377 /* See if we made any progress... */
7378 if (old_group_size
!= up
->group_size
)
7381 /* Clean out the (current cycle's) pipeline state
7382 and try once more. If we placed no instructions
7383 into the pipeline at all, it means a real hard
7384 conflict exists with some earlier issued instruction
7385 so we must advance to the next cycle to clear it up. */
7386 if (up
->group_size
== 0)
7388 ultra_flush_pipeline ();
7393 bzero ((char *) &ultra_pipe
, sizeof ultra_pipe
);
7394 ultra_pipe
.free_slot_mask
= 0xf;
7402 fprintf (dump
, ";;\tUltraSPARC Launched [");
7403 gsize
= up
->group_size
;
7404 for (n
= 0; n
< 4; n
++)
7406 rtx insn
= up
->group
[n
];
7413 fprintf (dump
, "%s(%d) ",
7414 ultra_code_names
[up
->codes
[n
]],
7417 fprintf (dump
, "%s(%d)",
7418 ultra_code_names
[up
->codes
[n
]],
7421 fprintf (dump
, "]\n");
7433 /* Assume V9 processors are capable of at least dual-issue. */
7435 case PROCESSOR_SUPERSPARC
:
7437 case PROCESSOR_HYPERSPARC
:
7438 case PROCESSOR_SPARCLITE86X
:
7440 case PROCESSOR_ULTRASPARC
:
7446 set_extends(x
, insn
)
7449 register rtx pat
= PATTERN (insn
);
7451 switch (GET_CODE (SET_SRC (pat
)))
7453 /* Load and some shift instructions zero extend. */
7456 /* sethi clears the high bits */
7458 /* LO_SUM is used with sethi. sethi cleared the high
7459 bits and the values used with lo_sum are positive */
7461 /* Store flag stores 0 or 1 */
7471 rtx op1
= XEXP (SET_SRC (pat
), 1);
7472 if (GET_CODE (op1
) == CONST_INT
)
7473 return INTVAL (op1
) >= 0;
7474 if (GET_CODE (XEXP (SET_SRC (pat
), 0)) == REG
7475 && sparc_check_64 (XEXP (SET_SRC (pat
), 0), insn
) == 1)
7477 if (GET_CODE (op1
) == REG
7478 && sparc_check_64 ((op1
), insn
) == 1)
7483 return GET_MODE (SET_SRC (pat
)) == SImode
;
7484 /* Positive integers leave the high bits zero. */
7486 return ! (CONST_DOUBLE_LOW (x
) & 0x80000000);
7488 return ! (INTVAL (x
) & 0x80000000);
7491 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7497 /* We _ought_ to have only one kind per function, but... */
7498 static rtx sparc_addr_diff_list
;
7499 static rtx sparc_addr_list
;
7502 sparc_defer_case_vector (lab
, vec
, diff
)
7506 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7508 sparc_addr_diff_list
7509 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7511 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7515 sparc_output_addr_vec (vec
)
7518 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7519 int idx
, vlen
= XVECLEN (body
, 0);
7521 #ifdef ASM_OUTPUT_ADDR_VEC_START
7522 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7525 #ifdef ASM_OUTPUT_CASE_LABEL
7526 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7529 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7532 for (idx
= 0; idx
< vlen
; idx
++)
7534 ASM_OUTPUT_ADDR_VEC_ELT
7535 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7538 #ifdef ASM_OUTPUT_ADDR_VEC_END
7539 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7544 sparc_output_addr_diff_vec (vec
)
7547 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7548 rtx base
= XEXP (XEXP (body
, 0), 0);
7549 int idx
, vlen
= XVECLEN (body
, 1);
7551 #ifdef ASM_OUTPUT_ADDR_VEC_START
7552 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7555 #ifdef ASM_OUTPUT_CASE_LABEL
7556 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7559 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7562 for (idx
= 0; idx
< vlen
; idx
++)
7564 ASM_OUTPUT_ADDR_DIFF_ELT
7567 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7568 CODE_LABEL_NUMBER (base
));
7571 #ifdef ASM_OUTPUT_ADDR_VEC_END
7572 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7577 sparc_output_deferred_case_vectors ()
7582 if (sparc_addr_list
== NULL_RTX
7583 && sparc_addr_diff_list
== NULL_RTX
)
7586 /* Align to cache line in the function's code section. */
7587 function_section (current_function_decl
);
7589 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7591 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7593 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7594 sparc_output_addr_vec (XEXP (t
, 0));
7595 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7596 sparc_output_addr_diff_vec (XEXP (t
, 0));
7598 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7601 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7602 unknown. Return 1 if the high bits are zero, -1 if the register is
7605 sparc_check_64 (x
, insn
)
7608 /* If a register is set only once it is safe to ignore insns this
7609 code does not know how to handle. The loop will either recognize
7610 the single set and return the correct value or fail to recognize
7614 if (GET_CODE (x
) == REG
7615 && flag_expensive_optimizations
7616 && REG_N_SETS (REGNO (x
)) == 1)
7622 insn
= get_last_insn_anywhere ();
7627 while ((insn
= PREV_INSN (insn
)))
7629 switch (GET_CODE (insn
))
7642 rtx pat
= PATTERN (insn
);
7643 if (GET_CODE (pat
) != SET
)
7645 if (rtx_equal_p (x
, SET_DEST (pat
)))
7646 return set_extends (x
, insn
);
7647 if (reg_overlap_mentioned_p (SET_DEST (pat
), x
))
7656 sparc_v8plus_shift (operands
, insn
, opcode
)
7661 static char asm_code
[60];
7663 if (GET_CODE (operands
[3]) == SCRATCH
)
7664 operands
[3] = operands
[0];
7665 if (GET_CODE (operands
[1]) == CONST_INT
)
7667 output_asm_insn ("mov %1,%3", operands
);
7671 output_asm_insn ("sllx %H1,32,%3", operands
);
7672 if (sparc_check_64 (operands
[1], insn
) <= 0)
7673 output_asm_insn ("srl %L1,0,%L1", operands
);
7674 output_asm_insn ("or %L1,%3,%3", operands
);
7677 strcpy(asm_code
, opcode
);
7678 if (which_alternative
!= 2)
7679 return strcat (asm_code
, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
7681 return strcat (asm_code
, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
7685 /* Return 1 if DEST and SRC reference only global and in registers. */
7688 sparc_return_peephole_ok (dest
, src
)
7693 if (current_function_uses_only_leaf_regs
)
7695 if (GET_CODE (src
) != CONST_INT
7696 && (GET_CODE (src
) != REG
|| ! IN_OR_GLOBAL_P (src
)))
7698 return IN_OR_GLOBAL_P (dest
);
7701 /* Output assembler code to FILE to increment profiler label # LABELNO
7702 for profiling a function entry.
7704 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
7705 during profiling so we need to save/restore it around the call to mcount.
7706 We're guaranteed that a save has just been done, and we use the space
7707 allocated for intreg/fpreg value passing. */
7710 sparc_function_profiler (file
, labelno
)
7715 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
7717 if (! TARGET_ARCH64
)
7718 fputs ("\tst\t%g2,[%fp-4]\n", file
);
7720 fputs ("\tsethi\t%hi(", file
);
7721 assemble_name (file
, buf
);
7722 fputs ("),%o0\n", file
);
7724 fputs ("\tcall\t", file
);
7725 assemble_name (file
, MCOUNT_FUNCTION
);
7728 fputs ("\t or\t%o0,%lo(", file
);
7729 assemble_name (file
, buf
);
7730 fputs ("),%o0\n", file
);
7732 if (! TARGET_ARCH64
)
7733 fputs ("\tld\t[%fp-4],%g2\n", file
);
7737 /* The following macro shall output assembler code to FILE
7738 to initialize basic-block profiling.
7740 If profile_block_flag == 2
7742 Output code to call the subroutine `__bb_init_trace_func'
7743 and pass two parameters to it. The first parameter is
7744 the address of a block allocated in the object module.
7745 The second parameter is the number of the first basic block
7748 The name of the block is a local symbol made with this statement:
7750 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
7752 Of course, since you are writing the definition of
7753 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
7754 can take a short cut in the definition of this macro and use the
7755 name that you know will result.
7757 The number of the first basic block of the function is
7758 passed to the macro in BLOCK_OR_LABEL.
7760 If described in a virtual assembler language the code to be
7764 parameter2 <- BLOCK_OR_LABEL
7765 call __bb_init_trace_func
7767 else if profile_block_flag != 0
7769 Output code to call the subroutine `__bb_init_func'
7770 and pass one single parameter to it, which is the same
7771 as the first parameter to `__bb_init_trace_func'.
7773 The first word of this parameter is a flag which will be nonzero if
7774 the object module has already been initialized. So test this word
7775 first, and do not call `__bb_init_func' if the flag is nonzero.
7776 Note: When profile_block_flag == 2 the test need not be done
7777 but `__bb_init_trace_func' *must* be called.
7779 BLOCK_OR_LABEL may be used to generate a label number as a
7780 branch destination in case `__bb_init_func' will not be called.
7782 If described in a virtual assembler language the code to be
7794 sparc_function_block_profiler(file
, block_or_label
)
7799 ASM_GENERATE_INTERNAL_LABEL (LPBX
, "LPBX", 0);
7801 if (profile_block_flag
== 2)
7803 fputs ("\tsethi\t%hi(", file
);
7804 assemble_name (file
, LPBX
);
7805 fputs ("),%o0\n", file
);
7807 fprintf (file
, "\tsethi\t%%hi(%d),%%o1\n", block_or_label
);
7809 fputs ("\tor\t%o0,%lo(", file
);
7810 assemble_name (file
, LPBX
);
7811 fputs ("),%o0\n", file
);
7813 fprintf (file
, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix
);
7815 fprintf (file
, "\t or\t%%o1,%%lo(%d),%%o1\n", block_or_label
);
7817 else if (profile_block_flag
!= 0)
7820 ASM_GENERATE_INTERNAL_LABEL (LPBY
, "LPBY", block_or_label
);
7822 fputs ("\tsethi\t%hi(", file
);
7823 assemble_name (file
, LPBX
);
7824 fputs ("),%o0\n", file
);
7826 fputs ("\tld\t[%lo(", file
);
7827 assemble_name (file
, LPBX
);
7828 fputs (")+%o0],%o1\n", file
);
7830 fputs ("\ttst\t%o1\n", file
);
7834 fputs ("\tbne,pn\t%icc,", file
);
7835 assemble_name (file
, LPBY
);
7840 fputs ("\tbne\t", file
);
7841 assemble_name (file
, LPBY
);
7845 fputs ("\t or\t%o0,%lo(", file
);
7846 assemble_name (file
, LPBX
);
7847 fputs ("),%o0\n", file
);
7849 fprintf (file
, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix
);
7851 ASM_OUTPUT_INTERNAL_LABEL (file
, "LPBY", block_or_label
);
7855 /* The following macro shall output assembler code to FILE
7856 to increment a counter associated with basic block number BLOCKNO.
7858 If profile_block_flag == 2
7860 Output code to initialize the global structure `__bb' and
7861 call the function `__bb_trace_func' which will increment the
7864 `__bb' consists of two words. In the first word the number
7865 of the basic block has to be stored. In the second word
7866 the address of a block allocated in the object module
7869 The basic block number is given by BLOCKNO.
7871 The address of the block is given by the label created with
7873 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
7875 by FUNCTION_BLOCK_PROFILER.
7877 Of course, since you are writing the definition of
7878 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
7879 can take a short cut in the definition of this macro and use the
7880 name that you know will result.
7882 If described in a virtual assembler language the code to be
7885 move BLOCKNO -> (__bb)
7886 move LPBX0 -> (__bb+4)
7887 call __bb_trace_func
7889 Note that function `__bb_trace_func' must not change the
7890 machine state, especially the flag register. To grant
7891 this, you must output code to save and restore registers
7892 either in this macro or in the macros MACHINE_STATE_SAVE
7893 and MACHINE_STATE_RESTORE. The last two macros will be
7894 used in the function `__bb_trace_func', so you must make
7895 sure that the function prologue does not change any
7896 register prior to saving it with MACHINE_STATE_SAVE.
7898 else if profile_block_flag != 0
7900 Output code to increment the counter directly.
7901 Basic blocks are numbered separately from zero within each
7902 compiled object module. The count associated with block number
7903 BLOCKNO is at index BLOCKNO in an array of words; the name of
7904 this array is a local symbol made with this statement:
7906 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
7908 Of course, since you are writing the definition of
7909 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
7910 can take a short cut in the definition of this macro and use the
7911 name that you know will result.
7913 If described in a virtual assembler language, the code to be
7916 inc (LPBX2+4*BLOCKNO)
7921 sparc_block_profiler(file
, blockno
)
7927 if (profile_block_flag
== 2)
7929 ASM_GENERATE_INTERNAL_LABEL (LPBX
, "LPBX", 0);
7931 fprintf (file
, "\tsethi\t%%hi(%s__bb),%%g1\n", user_label_prefix
);
7932 fprintf (file
, "\tsethi\t%%hi(%d),%%g2\n", blockno
);
7933 fprintf (file
, "\tor\t%%g1,%%lo(%s__bb),%%g1\n", user_label_prefix
);
7934 fprintf (file
, "\tor\t%%g2,%%lo(%d),%%g2\n", blockno
);
7936 fputs ("\tst\t%g2,[%g1]\n", file
);
7938 fputs ("\tsethi\t%hi(", file
);
7939 assemble_name (file
, LPBX
);
7940 fputs ("),%g2\n", file
);
7942 fputs ("\tor\t%o2,%lo(", file
);
7943 assemble_name (file
, LPBX
);
7944 fputs ("),%g2\n", file
);
7946 fputs ("\tst\t%g2,[%g1+4]\n", file
);
7947 fputs ("\tmov\t%o7,%g2\n", file
);
7949 fprintf (file
, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix
);
7951 fputs ("\tmov\t%g2,%o7\n", file
);
7953 else if (profile_block_flag
!= 0)
7955 ASM_GENERATE_INTERNAL_LABEL (LPBX
, "LPBX", 2);
7957 fputs ("\tsethi\t%hi(", file
);
7958 assemble_name (file
, LPBX
);
7959 fprintf (file
, "+%d),%%g1\n", blockno
*4);
7961 fputs ("\tld\t[%g1+%lo(", file
);
7962 assemble_name (file
, LPBX
);
7963 fprintf (file
, "+%d)],%%g2\n", blockno
*4);
7965 fputs ("\tadd\t%g2,1,%g2\n", file
);
7967 fputs ("\tst\t%g2,[%g1+%lo(", file
);
7968 assemble_name (file
, LPBX
);
7969 fprintf (file
, "+%d)]\n", blockno
*4);
7973 /* The following macro shall output assembler code to FILE
7974 to indicate a return from function during basic-block profiling.
7976 If profile_block_flag == 2:
7978 Output assembler code to call function `__bb_trace_ret'.
7980 Note that function `__bb_trace_ret' must not change the
7981 machine state, especially the flag register. To grant
7982 this, you must output code to save and restore registers
7983 either in this macro or in the macros MACHINE_STATE_SAVE_RET
7984 and MACHINE_STATE_RESTORE_RET. The last two macros will be
7985 used in the function `__bb_trace_ret', so you must make
7986 sure that the function prologue does not change any
7987 register prior to saving it with MACHINE_STATE_SAVE_RET.
7989 else if profile_block_flag != 0:
7991 The macro will not be used, so it need not distinguish
7996 sparc_function_block_profiler_exit(file
)
7999 if (profile_block_flag
== 2)
8000 fprintf (file
, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix
);
8005 /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for
8009 mark_ultrasparc_pipeline_state (arg
)
8012 struct ultrasparc_pipeline_state
*ups
;
8015 ups
= (struct ultrasparc_pipeline_state
*) arg
;
8016 for (i
= 0; i
< sizeof (ups
->group
) / sizeof (rtx
); ++i
)
8017 ggc_mark_rtx (ups
->group
[i
]);
8020 /* Called to register all of our global variables with the garbage
8024 sparc_add_gc_roots ()
8026 ggc_add_rtx_root (&sparc_compare_op0
, 1);
8027 ggc_add_rtx_root (&sparc_compare_op1
, 1);
8028 ggc_add_rtx_root (&leaf_label
, 1);
8029 ggc_add_rtx_root (&global_offset_table
, 1);
8030 ggc_add_rtx_root (&get_pc_symbol
, 1);
8031 ggc_add_rtx_root (&sparc_addr_diff_list
, 1);
8032 ggc_add_rtx_root (&sparc_addr_list
, 1);
8033 ggc_add_root (ultra_pipe_hist
,
8034 sizeof (ultra_pipe_hist
) / sizeof (ultra_pipe_hist
[0]),
8035 sizeof (ultra_pipe_hist
[0]),
8036 &mark_ultrasparc_pipeline_state
);