| blob | 6617608cfd3078a4a0b173f5c0a81e938e307a41 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
59 /* Not really meaningful values, but at least something. */
60 #ifndef SIMULTANEOUS_PREFETCHES
61 #define SIMULTANEOUS_PREFETCHES 3
62 #endif
63 #ifndef PREFETCH_BLOCK
64 #define PREFETCH_BLOCK 32
65 #endif
66 #ifndef HAVE_prefetch
67 #define HAVE_prefetch 0
68 #define CODE_FOR_prefetch 0
69 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
70 #endif
72 /* Give up the prefetch optimizations once we exceed a given threshhold.
73 It is unlikely that we would be able to optimize something in a loop
74 with so many detected prefetches. */
75 #define MAX_PREFETCHES 100
76 /* The number of prefetch blocks that are beneficial to fetch at once before
77 a loop with a known (and low) iteration count. */
78 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
79 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
80 since it is likely that the data are already in the cache. */
81 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
82 /* The minimal number of prefetch blocks that a loop must consume to make
83 the emitting of prefetch instruction in the body of loop worthwhile. */
84 #define PREFETCH_BLOCKS_IN_LOOP_MIN 6
86 /* Parameterize some prefetch heuristics so they can be turned on and off
87 easily for performance testing on new architecures. These can be
88 defined in target-dependent files. */
90 /* Prefetch is worthwhile only when loads/stores are dense. */
91 #ifndef PREFETCH_ONLY_DENSE_MEM
92 #define PREFETCH_ONLY_DENSE_MEM 1
93 #endif
95 /* Define what we mean by "dense" loads and stores; This value divided by 256
96 is the minimum percentage of memory references that worth prefetching. */
97 #ifndef PREFETCH_DENSE_MEM
98 #define PREFETCH_DENSE_MEM 220
99 #endif
101 /* Do not prefetch for a loop whose iteration count is known to be low. */
102 #ifndef PREFETCH_NO_LOW_LOOPCNT
103 #define PREFETCH_NO_LOW_LOOPCNT 1
104 #endif
106 /* Define what we mean by a "low" iteration count. */
107 #ifndef PREFETCH_LOW_LOOPCNT
108 #define PREFETCH_LOW_LOOPCNT 32
109 #endif
111 /* Do not prefetch for a loop that contains a function call; such a loop is
112 probably not an internal loop. */
113 #ifndef PREFETCH_NO_CALL
114 #define PREFETCH_NO_CALL 1
115 #endif
117 /* Do not prefetch accesses with an extreme stride. */
118 #ifndef PREFETCH_NO_EXTREME_STRIDE
119 #define PREFETCH_NO_EXTREME_STRIDE 1
120 #endif
122 /* Define what we mean by an "extreme" stride. */
123 #ifndef PREFETCH_EXTREME_STRIDE
124 #define PREFETCH_EXTREME_STRIDE 4096
125 #endif
127 /* Do not handle reversed order prefetches (negative stride). */
128 #ifndef PREFETCH_NO_REVERSE_ORDER
129 #define PREFETCH_NO_REVERSE_ORDER 1
130 #endif
132 /* Prefetch even if the GIV is not always executed. */
133 #ifndef PREFETCH_NOT_ALWAYS
134 #define PREFETCH_NOT_ALWAYS 0
135 #endif
137 /* If the loop requires more prefetches than the target can process in
138 parallel then don't prefetch anything in that loop. */
139 #ifndef PREFETCH_LIMIT_TO_SIMULTANEOUS
140 #define PREFETCH_LIMIT_TO_SIMULTANEOUS 1
141 #endif
143 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
144 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
146 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
147 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
148 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
150 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
151 ((REGNO) < FIRST_PSEUDO_REGISTER \
152 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
155 /* Vector mapping INSN_UIDs to luids.
156 The luids are like uids but increase monotonically always.
157 We use them to see whether a jump comes from outside a given loop. */
161 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
162 number the insn is contained in. */
166 /* 1 + largest uid of any insn. */
170 /* 1 + luid of last insn. */
174 /* Number of loops detected in current function. Used as index to the
175 next few tables. */
179 /* Bound on pseudo register number before loop optimization.
180 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
183 /* The value to pass to the next call of reg_scan_update. */
186 #define obstack_chunk_alloc xmalloc
187 #define obstack_chunk_free free
188 \f
189 /* During the analysis of a loop, a chain of `struct movable's
190 is made to record all the movable insns found.
191 Then the entire chain can be scanned to decide which to move. */
193 struct movable
194 {
199 of any registers used within the LIBCALL. */
201 that must be moved with this one. */
204 may be adjusted when matching movables
205 that load the same value are found. */
207 including other movables that force this
208 or match this one. */
212 /* If PARTIAL is 1, GLOBAL means something different:
213 that the reg is live outside the range from where it is set
214 to the following label. */
218 In particular, moving it does not make it
219 invariant. */
221 load SRC, rather than copying INSN. */
223 first insn of a consecutive sets group. */
226 that we should avoid changing when clearing
227 the rest of the reg. */
231 };
236 /* Forward declarations. */
250 #if 0
252 #endif
282 rtx *));
364 {
365 rtx r1;
366 rtx r2;
370 {
371 rtx match;
372 rtx replacement;
373 rtx insn;
376 /* Nonzero iff INSN is between START and END, inclusive. */
377 #define INSN_IN_RANGE_P(INSN, START, END) \
378 (INSN_UID (INSN) < max_uid_for_loop \
379 && INSN_LUID (INSN) >= INSN_LUID (START) \
380 && INSN_LUID (INSN) <= INSN_LUID (END))
382 /* Indirect_jump_in_function is computed once per function. */
390 rtx));
391 \f
392 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
393 copy the value of the strength reduced giv to its original register. */
396 /* Cost of using a register, to normalize the benefits of a giv. */
399 void
401 {
407 }
408 \f
409 /* Compute the mapping from uids to luids.
410 LUIDs are numbers assigned to insns, like uids,
411 except that luids increase monotonically through the code.
412 Start at insn START and stop just before END. Assign LUIDs
413 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
414 static int
418 {
420 rtx insn;
423 {
426 /* Don't assign luids to line-number NOTEs, so that the distance in
427 luids between two insns is not affected by -g. */
431 else
432 /* Give a line number note the same luid as preceding insn. */
434 }
436 }
437 \f
438 /* Entry point of this file. Perform loop optimization
439 on the current function. F is the first insn of the function
440 and DUMPFILE is a stream for output of a trace of actions taken
441 (or 0 if none should be output). */
443 void
445 /* f is the first instruction of a chain of insns for one function */
446 rtx f;
449 {
450 rtx insn;
465 /* Count the number of loops. */
469 {
472 max_loop_num++;
473 }
475 /* Don't waste time if no loops. */
481 /* Get size to use for tables indexed by uids.
482 Leave some space for labels allocated by find_and_verify_loops. */
489 /* Allocate storage for array of loops. */
493 /* Find and process each loop.
494 First, find them, and record them in order of their beginnings. */
497 /* Allocate and initialize auxiliary loop information. */
502 /* Now find all register lifetimes. This must be done after
503 find_and_verify_loops, because it might reorder the insns in the
504 function. */
507 /* This must occur after reg_scan so that registers created by gcse
508 will have entries in the register tables.
510 We could have added a call to reg_scan after gcse_main in toplev.c,
511 but moving this call to init_alias_analysis is more efficient. */
514 /* See if we went too far. Note that get_max_uid already returns
515 one more that the maximum uid of all insn. */
518 /* Now reset it to the actual size we need. See above. */
521 /* find_and_verify_loops has already called compute_luids, but it
522 might have rearranged code afterwards, so we need to recompute
523 the luids now. */
526 /* Don't leave gaps in uid_luid for insns that have been
527 deleted. It is possible that the first or last insn
528 using some register has been deleted by cross-jumping.
529 Make sure that uid_luid for that former insn's uid
530 points to the general area where that insn used to be. */
532 {
536 }
541 /* Determine if the function has indirect jump. On some systems
542 this prevents low overhead loop instructions from being used. */
545 /* Now scan the loops, last ones first, since this means inner ones are done
546 before outer ones. */
548 {
553 }
555 /* If there were lexical blocks inside the loop, they have been
556 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
557 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
558 the BLOCKs as well. */
564 /* Clean up. */
569 }
570 \f
571 /* Returns the next insn, in execution order, after INSN. START and
572 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
573 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
574 insn-stream; it is used with loops that are entered near the
575 bottom. */
577 static rtx
580 rtx insn;
581 {
585 {
587 /* Go to the top of the loop, and continue there. */
589 else
590 /* We're done. */
592 }
595 /* We're done. */
599 }
601 /* Optimize one loop described by LOOP. */
603 /* ??? Could also move memory writes out of loops if the destination address
604 is invariant, the source is invariant, the memory write is not volatile,
605 and if we can prove that no read inside the loop can read this address
606 before the write occurs. If there is a read of this address after the
607 write, then we can also mark the memory read as invariant. */
609 static void
613 {
619 rtx p;
620 /* 1 if we are scanning insns that could be executed zero times. */
622 /* 1 if we are scanning insns that might never be executed
623 due to a subroutine call which might exit before they are reached. */
625 /* Jump insn that enters the loop, or 0 if control drops in. */
627 /* Number of insns in the loop. */
631 /* The SET from an insn, if it is the only SET in the insn. */
633 /* Chain describing insns movable in current loop. */
635 /* Ratio of extra register life span we can justify
636 for saving an instruction. More if loop doesn't call subroutines
637 since in that case saving an insn makes more difference
638 and more registers are available. */
640 /* Nonzero if we are scanning instructions in a sub-loop. */
648 /* Determine whether this loop starts with a jump down to a test at
649 the end. This will occur for a small number of loops with a test
650 that is too complex to duplicate in front of the loop.
652 We search for the first insn or label in the loop, skipping NOTEs.
653 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
654 (because we might have a loop executed only once that contains a
655 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
656 (in case we have a degenerate loop).
658 Note that if we mistakenly think that a loop is entered at the top
659 when, in fact, it is entered at the exit test, the only effect will be
660 slightly poorer optimization. Making the opposite error can generate
661 incorrect code. Since very few loops now start with a jump to the
662 exit test, the code here to detect that case is very conservative. */
665 p != loop_end
671 ;
675 /* If loop end is the end of the current function, then emit a
676 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
677 note insn. This is the position we use when sinking insns out of
678 the loop. */
681 else
684 /* Set up variables describing this loop. */
688 /* If loop has a jump before the first label,
689 the true entry is the target of that jump.
690 Start scan from there.
691 But record in LOOP->TOP the place where the end-test jumps
692 back to so we can scan that after the end of the loop. */
694 {
697 /* Loop entry must be unconditional jump (and not a RETURN) */
700 /* Check to see whether the jump actually
701 jumps out of the loop (meaning it's no loop).
702 This case can happen for things like
703 do {..} while (0). If this label was generated previously
704 by loop, we can't tell anything about it and have to reject
705 the loop. */
707 {
710 }
711 }
713 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
714 as required by loop_reg_used_before_p. So skip such loops. (This
715 test may never be true, but it's best to play it safe.)
717 Also, skip loops where we do not start scanning at a label. This
718 test also rejects loops starting with a JUMP_INSN that failed the
719 test above. */
723 {
728 }
730 /* Allocate extra space for REGs that might be created by load_mems.
731 We allocate a little extra slop as well, in the hopes that we
732 won't have to reallocate the regs array. */
737 {
743 }
745 /* Scan through the loop finding insns that are safe to move.
746 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
747 this reg will be considered invariant for subsequent insns.
748 We consider whether subsequent insns use the reg
749 in deciding whether it is worth actually moving.
751 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
752 and therefore it is possible that the insns we are scanning
753 would never be executed. At such times, we must make sure
754 that it is safe to execute the insn once instead of zero times.
755 When MAYBE_NEVER is 0, all insns will be executed at least once
756 so that is not a problem. */
761 {
765 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
767 #endif
769 {
776 /* Figure out what to use as a source of this insn. If a REG_EQUIV
777 note is given or if a REG_EQUAL note with a constant operand is
778 specified, use it as the source and mark that we should move
779 this insn by calling emit_move_insn rather that duplicating the
780 insn.
782 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
783 is present. */
787 else
788 {
793 {
795 /* A libcall block can use regs that don't appear in
796 the equivalent expression. To move the libcall,
797 we must move those regs too. */
799 }
800 }
802 /* For parallels, add any possible uses to the depencies, as we can't move
803 the insn without resolving them first. */
805 {
807 {
811 }
812 }
814 /* Don't try to optimize a register that was made
815 by loop-optimization for an inner loop.
816 We don't know its life-span, so we can't compute the benefit. */
818 ;
820 than the one where it is set (meaning that
821 something after this point in the loop might
822 depend on its value before the set). */
824 /* And the set is not guaranteed to be executed once
825 the loop starts, or the value before the set is
826 needed before the set occurs...
828 ??? Note we have quadratic behaviour here, mitigated
829 by the fact that the previous test will often fail for
830 large loops. Rather than re-scanning the entire loop
831 each time for register usage, we should build tables
832 of the register usage and use them here instead. */
833 && (maybe_never
835 /* It is unsafe to move the set.
837 This code used to consider it OK to move a set of a variable
838 which was not created by the user and not used in an exit test.
839 That behavior is incorrect and was removed. */
840 ;
845 || (tem1
846 = consec_sets_invariant_p
849 p)))
850 /* If the insn can cause a trap (such as divide by zero),
851 can't move it unless it's guaranteed to be executed
852 once loop is entered. Even a function call might
853 prevent the trap insn from being reached
854 (since it might exit!) */
857 {
861 /* A potential lossage is where we have a case where two insns
862 can be combined as long as they are both in the loop, but
863 we move one of them outside the loop. For large loops,
864 this can lose. The most common case of this is the address
865 of a function being called.
867 Therefore, if this register is marked as being used exactly
868 once if we are in a loop with calls (a "large loop"), see if
869 we can replace the usage of this register with the source
870 of this SET. If we can, delete this insn.
872 Don't do this if P has a REG_RETVAL note or if we have
873 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
885 && (! SMALL_REGISTER_CLASSES
888 /* This test is not redundant; SET_SRC (set) might be
889 a call-clobbered register and the life of REGNO
890 might span a call. */
896 {
897 /* Replace any usage in a REG_EQUAL note. Must copy the
898 new source, so that we don't get rtx sharing between the
899 SET_SOURCE and REG_NOTES of insn p. */
908 }
926 /* Set M->cond if either loop_invariant_p
927 or consec_sets_invariant_p returned 2
928 (only conditionally invariant). */
938 /* Add M to the end of the chain MOVABLES. */
942 {
943 /* It is possible for the first instruction to have a
944 REG_EQUAL note but a non-invariant SET_SRC, so we must
945 remember the status of the first instruction in case
946 the last instruction doesn't have a REG_EQUAL note. */
949 /* Skip this insn, not checking REG_LIBCALL notes. */
951 /* Skip the consecutive insns, if there are any. */
953 /* Back up to the last insn of the consecutive group. */
956 /* We must now reset m->move_insn, m->is_equiv, and possibly
957 m->set_src to correspond to the effects of all the
958 insns. */
962 else
963 {
967 else
970 }
972 }
973 }
974 /* If this register is always set within a STRICT_LOW_PART
975 or set to zero, then its high bytes are constant.
976 So clear them outside the loop and within the loop
977 just load the low bytes.
978 We must check that the machine has an instruction to do so.
979 Also, if the value loaded into the register
980 depends on the same register, this cannot be done. */
990 {
993 {
1007 /* If the insn may not be executed on some cycles,
1008 we can't clear the whole reg; clear just high part.
1009 Not even if the reg is used only within this loop.
1010 Consider this:
1011 while (1)
1012 while (s != t) {
1013 if (foo ()) x = *s;
1014 use (x);
1015 }
1016 Clearing x before the inner loop could clobber a value
1017 being saved from the last time around the outer loop.
1018 However, if the reg is not used outside this loop
1019 and all uses of the register are in the same
1020 basic block as the store, there is no problem.
1022 If this insn was made by loop, we don't know its
1023 INSN_LUID and hence must make a conservative
1024 assumption. */
1027 || (labels_in_range_p
1031 else
1040 /* Add M to the end of the chain MOVABLES. */
1042 }
1043 }
1044 }
1045 /* Past a call insn, we get to insns which might not be executed
1046 because the call might exit. This matters for insns that trap.
1047 Constant and pure call insns always return, so they don't count. */
1050 /* Past a label or a jump, we get to insns for which we
1051 can't count on whether or how many times they will be
1052 executed during each iteration. Therefore, we can
1053 only move out sets of trivial variables
1054 (those not used after the loop). */
1055 /* Similar code appears twice in strength_reduce. */
1057 /* If we enter the loop in the middle, and scan around to the
1058 beginning, don't set maybe_never for that. This must be an
1059 unconditional jump, otherwise the code at the top of the
1060 loop might never be executed. Unconditional jumps are
1061 followed by a barrier then the loop_end. */
1067 {
1068 /* At the virtual top of a converted loop, insns are again known to
1069 be executed: logically, the loop begins here even though the exit
1070 code has been duplicated. */
1074 loop_depth++;
1076 loop_depth--;
1077 }
1078 }
1080 /* If one movable subsumes another, ignore that other. */
1084 /* For each movable insn, see if the reg that it loads
1085 leads when it dies right into another conditionally movable insn.
1086 If so, record that the second insn "forces" the first one,
1087 since the second can be moved only if the first is. */
1091 /* See if there are multiple movable insns that load the same value.
1092 If there are, make all but the first point at the first one
1093 through the `match' field, and add the priorities of them
1094 all together as the priority of the first. */
1098 /* Now consider each movable insn to decide whether it is worth moving.
1099 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1101 Generally this increases code size, so do not move moveables when
1102 optimizing for code size. */
1105 {
1108 /* Recalculate regs->array if move_movables has created new
1109 registers. */
1111 {
1117 ;
1122 }
1123 }
1125 /* Now candidates that still are negative are those not moved.
1126 Change regs->array[I].set_in_loop to indicate that those are not actually
1127 invariant. */
1132 /* Now that we've moved some things out of the loop, we might be able to
1133 hoist even more memory references. */
1136 /* Recalculate regs->array if load_mems has created new registers. */
1144 ;
1151 {
1153 /* Ensure our label doesn't go away. */
1164 }
1167 /* The movable information is required for strength reduction. */
1173 }
1174 \f
1175 /* Add elements to *OUTPUT to record all the pseudo-regs
1176 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1178 void
1182 {
1190 {
1208 }
1212 {
1216 {
1225 }
1226 }
1227 }
1228 \f
1229 /* Check what regs are referred to in the libcall block ending with INSN,
1230 aside from those mentioned in the equivalent value.
1231 If there are none, return 0.
1232 If there are one or more, return an EXPR_LIST containing all of them. */
1234 rtx
1237 {
1242 /* First, find all the regs used in the libcall block
1243 that are not mentioned as inputs to the result. */
1246 {
1251 }
1254 }
1255 \f
1256 /* Return 1 if all uses of REG
1257 are between INSN and the end of the basic block. */
1259 static int
1262 {
1264 rtx p;
1269 /* Search this basic block for the already recorded last use of the reg. */
1271 {
1273 {
1279 /* Ordinary insn: if this is the last use, we win. */
1285 /* Jump insn: if this is the last use, we win. */
1288 /* Otherwise, it's the end of the basic block, so we lose. */
1293 /* It's the end of the basic block, so we lose. */
1298 }
1299 }
1301 /* The "last use" that was recorded can't be found after the first
1302 use. This can happen when the last use was deleted while
1303 processing an inner loop, this inner loop was then completely
1304 unrolled, and the outer loop is always exited after the inner loop,
1305 so that everything after the first use becomes a single basic block. */
1307 }
1308 \f
1309 /* Compute the benefit of eliminating the insns in the block whose
1310 last insn is LAST. This may be a group of insns used to compute a
1311 value directly or can contain a library call. */
1313 static int
1315 rtx last;
1316 {
1317 rtx insn;
1322 {
1325 routine. */
1329 benefit++;
1330 }
1333 }
1334 \f
1335 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1337 static rtx
1339 rtx insn;
1341 {
1343 {
1344 rtx temp;
1346 /* If first insn of libcall sequence, skip to end. */
1347 /* Do this at start of loop, since INSN is guaranteed to
1348 be an insn here. */
1353 do
1356 }
1359 }
1361 /* Ignore any movable whose insn falls within a libcall
1362 which is part of another movable.
1363 We make use of the fact that the movable for the libcall value
1364 was made later and so appears later on the chain. */
1366 static void
1369 {
1373 {
1374 /* Is this a movable for the value of a libcall? */
1377 {
1378 rtx insn;
1379 /* Check for earlier movables inside that range,
1380 and mark them invalid. We cannot use LUIDs here because
1381 insns created by loop.c for prior loops don't have LUIDs.
1382 Rather than reject all such insns from movables, we just
1383 explicitly check each insn in the libcall (since invariant
1384 libcalls aren't that common). */
1389 }
1390 }
1391 }
1393 /* For each movable insn, see if the reg that it loads
1394 leads when it dies right into another conditionally movable insn.
1395 If so, record that the second insn "forces" the first one,
1396 since the second can be moved only if the first is. */
1398 static void
1401 {
1405 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1407 {
1410 /* ??? Could this be a bug? What if CSE caused the
1411 register of M1 to be used after this insn?
1412 Since CSE does not update regno_last_uid,
1413 this insn M->insn might not be where it dies.
1414 But very likely this doesn't matter; what matters is
1415 that M's reg is computed from M1's reg. */
1420 /* If m->consec, m->set_src isn't valid. */
1424 /* Increase the priority of the moving the first insn
1425 since it permits the second to be moved as well. */
1427 {
1431 }
1432 }
1433 }
1434 \f
1435 /* Find invariant expressions that are equal and can be combined into
1436 one register. */
1438 static void
1442 {
1447 /* Regs that are set more than once are not allowed to match
1448 or be matched. I'm no longer sure why not. */
1449 /* Perhaps testing m->consec_sets would be more appropriate here? */
1454 {
1461 /* We want later insns to match the first one. Don't make the first
1462 one match any later ones. So start this loop at m->next. */
1464 /* ??? HACK! move_movables does not verify that the replacement
1465 is valid, which can have disasterous effects with hard regs
1466 and match_dup. Turn combination off for now. */
1469 /* A reg used outside the loop mustn't be eliminated. */
1471 /* A reg used for zero-extending mustn't be eliminated. */
1474 ||
1475 (
1476 /* Can combine regs with different modes loaded from the
1477 same constant only if the modes are the same or
1478 if both are integer modes with M wider or the same
1479 width as M1. The check for integer is redundant, but
1480 safe, since the only case of differing destination
1481 modes with equal sources is when both sources are
1482 VOIDmode, i.e., CONST_INT. */
1488 /* See if the source of M1 says it matches M. */
1495 {
1501 }
1502 }
1504 /* Now combine the regs used for zero-extension.
1505 This can be done for those not marked `global'
1506 provided their lives don't overlap. */
1510 {
1513 /* Combine all the registers for extension from mode MODE.
1514 Don't combine any that are used outside this loop. */
1518 {
1525 {
1526 /* First one: don't check for overlap, just record it. */
1529 }
1531 /* Make sure they extend to the same mode.
1532 (Almost always true.) */
1536 /* We already have one: check for overlap with those
1537 already combined together. */
1544 /* No overlap: we can combine this with the others. */
1550 overlap:
1551 ;
1552 }
1553 }
1555 /* Clean up. */
1557 }
1559 /* Returns the number of movable instructions in LOOP that were not
1560 moved outside the loop. */
1562 static int
1565 {
1574 }
1576 \f
1577 /* Return 1 if regs X and Y will become the same if moved. */
1579 static int
1583 {
1600 }
1602 /* Return 1 if X and Y are identical-looking rtx's.
1603 This is the Lisp function EQUAL for rtx arguments.
1605 If two registers are matching movables or a movable register and an
1606 equivalent constant, consider them equal. */
1608 static int
1613 {
1627 /* If we have a register and a constant, they may sometimes be
1628 equal. */
1631 {
1636 }
1639 {
1644 }
1646 /* Otherwise, rtx's of different codes cannot be equal. */
1650 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1651 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1656 /* These three types of rtx's can be compared nonrecursively. */
1665 /* Compare the elements. If any pair of corresponding elements
1666 fail to match, return 0 for the whole things. */
1670 {
1672 {
1684 /* Two vectors must have the same length. */
1688 /* And the corresponding elements must match. */
1707 /* These are just backpointers, so they don't matter. */
1713 /* It is believed that rtx's at this level will never
1714 contain anything but integers and other rtx's,
1715 except for within LABEL_REFs and SYMBOL_REFs. */
1718 }
1719 }
1721 }
1722 \f
1723 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1724 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1725 references is incremented once for each added note. */
1727 static void
1729 rtx x;
1730 rtx insns;
1731 {
1735 rtx insn;
1738 {
1739 /* This code used to ignore labels that referred to dispatch tables to
1740 avoid flow generating (slighly) worse code.
1742 We no longer ignore such label references (see LABEL_REF handling in
1743 mark_jump_label for additional information). */
1746 {
1751 }
1752 }
1756 {
1762 }
1763 }
1764 \f
1765 /* Scan MOVABLES, and move the insns that deserve to be moved.
1766 If two matching movables are combined, replace one reg with the
1767 other throughout. */
1769 static void
1775 {
1780 rtx p;
1783 /* Map of pseudo-register replacements to handle combining
1784 when we move several insns that load the same value
1785 into different pseudo-registers. */
1790 {
1791 /* Describe this movable insn. */
1794 {
1815 }
1817 /* Ignore the insn if it's already done (it matched something else).
1818 Otherwise, see if it is now safe to move. */
1830 {
1832 rtx p;
1835 /* We have an insn that is safe to move.
1836 Compute its desirability. */
1847 /* An insn MUST be moved if we already moved something else
1848 which is safe only if this one is moved too: that is,
1849 if already_moved[REGNO] is nonzero. */
1851 /* An insn is desirable to move if the new lifetime of the
1852 register is no more than THRESHOLD times the old lifetime.
1853 If it's not desirable, it means the loop is so big
1854 that moving won't speed things up much,
1855 and it is liable to make register usage worse. */
1857 /* It is also desirable to move if it can be moved at no
1858 extra cost because something else was already moved. */
1861 || flag_move_all_movables
1866 {
1871 /* Now move the insns that set the reg. */
1874 {
1877 /* Find the end of this chain of matching regs.
1878 Thus, we load each reg in the chain from that one reg.
1879 And that reg is loaded with 0 directly,
1880 since it has ->match == 0. */
1886 /* Mark the moved, invariant reg as being allowed to
1887 share a hard reg with the other matching invariant. */
1891 regs_may_share
1894 regs_may_share));
1902 }
1903 /* If we are to re-generate the item being moved with a
1904 new move insn, first delete what we have and then emit
1905 the move insn before the loop. */
1907 {
1911 {
1912 /* If this is the first insn of a library call sequence,
1913 skip to the end. */
1918 /* If this is the last insn of a libcall sequence, then
1919 delete every insn in the sequence except the last.
1920 The last insn is handled in the normal manner. */
1923 {
1927 }
1932 /* simplify_giv_expr expects that it can walk the insns
1933 at m->insn forwards and see this old sequence we are
1934 tossing here. delete_insn does preserve the next
1935 pointers, but when we skip over a NOTE we must fix
1936 it up. Otherwise that code walks into the non-deleted
1937 insn stream. */
1940 }
1959 /* The more regs we move, the less we like moving them. */
1961 }
1962 else
1963 {
1965 {
1968 /* If first insn of libcall sequence, skip to end. */
1969 /* Do this at start of loop, since p is guaranteed to
1970 be an insn here. */
1975 /* If last insn of libcall sequence, move all
1976 insns except the last before the loop. The last
1977 insn is handled in the normal manner. */
1980 {
1988 {
1989 rtx body;
1990 rtx n;
1991 rtx next;
1998 /* Find the next insn after TEMP,
1999 not counting USE or NOTE insns. */
2007 /* If that is the call, this may be the insn
2008 that loads the function address.
2010 Extract the function address from the insn
2011 that loads it into a register.
2012 If this insn was cse'd, we get incorrect code.
2014 So emit a new move insn that copies the
2015 function address into the register that the
2016 call insn will use. flow.c will delete any
2017 redundant stores that we have created. */
2022 NULL_RTX)))
2023 {
2029 }
2030 /* We have the call insn.
2031 If it uses the register we suspect it might,
2032 load it with the correct address directly. */
2037 gen_move_insn
2041 {
2043 /* Because the USAGE information potentially
2044 contains objects other than hard registers
2045 we need to copy it. */
2049 }
2050 else
2059 }
2062 }
2064 {
2065 /* P sets REG to zero; but we should clear only
2066 the bits that are not covered by the mode
2067 m->savemode. */
2069 rtx sequence;
2070 rtx tem;
2073 tem = expand_simple_binop
2086 }
2088 {
2090 /* Because the USAGE information potentially
2091 contains objects other than hard registers
2092 we need to copy it. */
2096 }
2098 {
2099 rtx seq;
2100 /* The SET_SRC might not be invariant, so we must
2101 use the REG_EQUAL note. */
2114 }
2115 else
2119 {
2123 /* If there is a REG_EQUAL note present whose value
2124 is not loop invariant, then delete it, since it
2125 may cause problems with later optimization passes.
2126 It is possible for cse to create such notes
2127 like this as a result of record_jump_cond. */
2132 }
2141 /* If library call, now fix the REG_NOTES that contain
2142 insn pointers, namely REG_LIBCALL on FIRST
2143 and REG_RETVAL on I1. */
2145 {
2149 }
2155 /* simplify_giv_expr expects that it can walk the insns
2156 at m->insn forwards and see this old sequence we are
2157 tossing here. delete_insn does preserve the next
2158 pointers, but when we skip over a NOTE we must fix
2159 it up. Otherwise that code walks into the non-deleted
2160 insn stream. */
2163 }
2165 /* The more regs we move, the less we like moving them. */
2167 }
2169 /* Any other movable that loads the same register
2170 MUST be moved. */
2173 /* This reg has been moved out of one loop. */
2176 /* The reg set here is now invariant. */
2178 {
2182 }
2186 /* Change the length-of-life info for the register
2187 to say it lives at least the full length of this loop.
2188 This will help guide optimizations in outer loops. */
2191 /* This is the old insn before all the moved insns.
2192 We can't use the moved insn because it is out of range
2193 in uid_luid. Only the old insns have luids. */
2198 /* Combine with this moved insn any other matching movables. */
2203 {
2204 rtx temp;
2206 /* Schedule the reg loaded by M1
2207 for replacement so that shares the reg of M.
2208 If the modes differ (only possible in restricted
2209 circumstances, make a SUBREG.
2211 Note this assumes that the target dependent files
2212 treat REG and SUBREG equally, including within
2213 GO_IF_LEGITIMATE_ADDRESS and in all the
2214 predicates since we never verify that replacing the
2215 original register with a SUBREG results in a
2216 recognizable insn. */
2219 else
2224 /* Get rid of the matching insn
2225 and prevent further processing of it. */
2228 /* if library call, delete all insns. */
2230 NULL_RTX)))
2232 else
2235 /* Any other movable that loads the same register
2236 MUST be moved. */
2239 /* The reg merged here is now invariant,
2240 if the reg it matches is invariant. */
2242 {
2246 i++)
2248 }
2249 }
2250 }
2253 }
2259 }
2264 /* Go through all the instructions in the loop, making
2265 all the register substitutions scheduled in REG_MAP. */
2269 {
2273 }
2275 /* Clean up. */
2278 }
2281 static void
2285 {
2288 else
2291 }
2294 static void
2297 {
2302 {
2305 }
2306 }
2307 \f
2308 #if 0
2309 /* Scan X and replace the address of any MEM in it with ADDR.
2310 REG is the address that MEM should have before the replacement. */
2312 static void
2315 {
2324 {
2336 /* Short cut for very common case. */
2341 /* Short cut for very common case. */
2346 /* If this MEM uses a reg other than the one we expected,
2347 something is wrong. */
2355 }
2359 {
2363 {
2367 }
2368 }
2369 }
2370 #endif
2371 \f
2372 /* Return the number of memory refs to addresses that vary
2373 in the rtx X. */
2375 static int
2378 rtx x;
2379 {
2390 {
2407 }
2412 {
2416 {
2420 }
2421 }
2423 }
2424 \f
2425 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2426 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2427 `unknown_address_altered', `unknown_constant_address_altered', and
2428 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2429 list `store_mems' in LOOP. */
2431 static void
2434 {
2436 rtx insn;
2440 /* The label after END. Jumping here is just like falling off the
2441 end of the loop. We use next_nonnote_insn instead of next_label
2442 as a hedge against the (pathological) case where some actual insn
2443 might end up between the two. */
2465 {
2467 {
2470 }
2471 }
2475 {
2477 {
2480 {
2482 /* Count number of loops contained in this one. */
2484 }
2491 {
2494 }
2502 {
2506 {
2511 {
2514 }
2515 else
2516 {
2519 }
2521 do
2522 {
2524 {
2526 {
2527 /* Something tricky. */
2530 }
2533 {
2534 /* A jump outside the current loop. */
2537 }
2538 }
2542 }
2544 }
2545 else
2546 {
2547 /* A return, or something tricky. */
2549 }
2550 }
2551 /* FALLTHRU */
2572 }
2573 }
2575 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2577 anywhere. */
2579 /* We don't want loads for MEMs moved to a location before the
2580 one at which their stack memory becomes allocated. (Note
2581 that this is not a problem for malloc, etc., since those
2582 require actual function calls. */
2583 && ! current_function_calls_alloca
2584 /* There are ways to leave the loop other than falling off the
2585 end. */
2591 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2592 that loop_invariant_p and load_mems can use true_dependence
2593 to determine what is really clobbered. */
2595 {
2598 loop_info->store_mems
2600 }
2602 {
2606 loop_info->store_mems
2608 }
2609 }
2610 \f
2611 /* Scan the function looking for loops. Record the start and end of each loop.
2612 Also mark as invalid loops any loops that contain a setjmp or are branched
2613 to from outside the loop. */
2615 static void
2617 rtx f;
2619 {
2620 rtx insn;
2621 rtx label;
2631 /* If there are jumps to undefined labels,
2632 treat them as jumps out of any/all loops.
2633 This also avoids writing past end of tables when there are no loops. */
2636 /* Find boundaries of loops, mark which loops are contained within
2637 loops, and invalidate loops that have setjmp. */
2642 {
2645 {
2649 num_loops++;
2673 }
2677 {
2678 /* In this case, we must invalidate our current loop and any
2679 enclosing loop. */
2681 {
2687 }
2688 }
2690 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2691 enclosing loop, but this doesn't matter. */
2693 }
2695 /* Any loop containing a label used in an initializer must be invalidated,
2696 because it can be jumped into from anywhere. */
2699 {
2703 }
2705 /* Any loop containing a label used for an exception handler must be
2706 invalidated, because it can be jumped into from anywhere. */
2709 {
2713 }
2715 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2716 loop that it is not contained within, that loop is marked invalid.
2717 If any INSN or CALL_INSN uses a label's address, then the loop containing
2718 that label is marked invalid, because it could be jumped into from
2719 anywhere.
2721 Also look for blocks of code ending in an unconditional branch that
2722 exits the loop. If such a block is surrounded by a conditional
2723 branch around the block, move the block elsewhere (see below) and
2724 invert the jump to point to the code block. This may eliminate a
2725 label in our loop and will simplify processing by both us and a
2726 possible second cse pass. */
2730 {
2734 {
2737 {
2741 }
2742 }
2749 /* See if this is an unconditional branch outside the loop. */
2757 {
2758 rtx p;
2764 /* Go backwards until we reach the start of the loop, a label,
2765 or a JUMP_INSN. */
2772 ;
2774 /* Check for the case where we have a jump to an inner nested
2775 loop, and do not perform the optimization in that case. */
2778 {
2781 {
2786 }
2787 }
2789 /* Make sure that the target of P is within the current loop. */
2795 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2796 we have a block of code to try to move.
2798 We look backward and then forward from the target of INSN
2799 to find a BARRIER at the same loop depth as the target.
2800 If we find such a BARRIER, we make a new label for the start
2801 of the block, invert the jump in P and point it to that label,
2802 and move the block of code to the spot we found. */
2807 /* Just ignore jumps to labels that were never emitted.
2808 These always indicate compilation errors. */
2812 /* If it's not safe to move the sequence, then we
2813 mustn't try. */
2816 {
2817 rtx target
2821 rtx tmp;
2823 /* Search for possible garbage past the conditional jumps
2824 and look for the last barrier. */
2832 /* Don't move things inside a tablejump. */
2845 /* Don't move things inside a tablejump. */
2856 {
2860 /* Ensure our label doesn't go away. */
2863 /* Verify that uid_loop is large enough and that
2864 we can invert P. */
2866 {
2869 /* If no suitable BARRIER was found, create a suitable
2870 one before TARGET. Since TARGET is a fall through
2871 path, we'll need to insert an jump around our block
2872 and add a BARRIER before TARGET.
2874 This creates an extra unconditional jump outside
2875 the loop. However, the benefits of removing rarely
2876 executed instructions from inside the loop usually
2877 outweighs the cost of the extra unconditional jump
2878 outside the loop. */
2880 {
2881 rtx temp;
2888 }
2890 /* Include the BARRIER after INSN and copy the
2891 block after LOC. */
2896 /* All those insns are now in TARGET_LOOP. */
2902 /* The label jumped to by INSN is no longer a loop
2903 exit. Unless INSN does not have a label (e.g.,
2904 it is a RETURN insn), search loop->exit_labels
2905 to find its label_ref, and remove it. Also turn
2906 off LABEL_OUTSIDE_LOOP_P bit. */
2908 {
2910 r;
2913 {
2917 else
2920 }
2926 /* If we didn't find it, then something is
2927 wrong. */
2930 }
2932 /* P is now a jump outside the loop, so it must be put
2933 in loop->exit_labels, and marked as such.
2934 The easiest way to do this is to just call
2935 mark_loop_jump again for P. */
2938 /* If INSN now jumps to the insn after it,
2939 delete INSN. */
2944 }
2946 /* Continue the loop after where the conditional
2947 branch used to jump, since the only branch insn
2948 in the block (if it still remains) is an inter-loop
2949 branch and hence needs no processing. */
2955 /* This loop will be continued with NEXT_INSN (insn). */
2957 }
2958 }
2959 }
2960 }
2961 }
2963 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2964 loops it is contained in, mark the target loop invalid.
2966 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2968 static void
2970 rtx x;
2972 {
2978 {
2990 /* There could be a label reference in here. */
3002 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3014 /* Link together all labels that branch outside the loop. This
3015 is used by final_[bg]iv_value and the loop unrolling code. Also
3016 mark this LABEL_REF so we know that this branch should predict
3017 false. */
3019 /* A check to make sure the label is not in an inner nested loop,
3020 since this does not count as a loop exit. */
3022 {
3027 }
3028 else
3032 {
3041 }
3043 /* If this is inside a loop, but not in the current loop or one enclosed
3044 by it, it invalidates at least one loop. */
3049 /* We must invalidate every nested loop containing the target of this
3050 label, except those that also contain the jump insn. */
3053 {
3054 /* Stop when we reach a loop that also contains the jump insn. */
3059 /* If we get here, we know we need to invalidate a loop. */
3066 }
3070 /* If this is not setting pc, ignore. */
3092 /* Strictly speaking this is not a jump into the loop, only a possible
3093 jump out of the loop. However, we have no way to link the destination
3094 of this jump onto the list of exit labels. To be safe we mark this
3095 loop and any containing loops as invalid. */
3097 {
3099 {
3105 }
3106 }
3108 }
3109 }
3110 \f
3111 /* Return nonzero if there is a label in the range from
3112 insn INSN to and including the insn whose luid is END
3113 INSN must have an assigned luid (i.e., it must not have
3114 been previously created by loop.c). */
3116 static int
3118 rtx insn;
3120 {
3122 {
3126 }
3129 }
3131 /* Record that a memory reference X is being set. */
3133 static void
3135 rtx x;
3136 rtx y ATTRIBUTE_UNUSED;
3138 {
3144 /* Count number of memory writes.
3145 This affects heuristics in strength_reduce. */
3148 /* BLKmode MEM means all memory is clobbered. */
3150 {
3153 else
3157 }
3161 }
3163 /* X is a value modified by an INSN that references a biv inside a loop
3164 exit test (ie, X is somehow related to the value of the biv). If X
3165 is a pseudo that is used more than once, then the biv is (effectively)
3166 used more than once. DATA is a pointer to a loop_regs structure. */
3168 static void
3170 rtx x;
3171 rtx y ATTRIBUTE_UNUSED;
3173 {
3188 /* If we do not have usage information, or if we know the register
3189 is used more than once, note that fact for check_dbra_loop. */
3194 }
3195 \f
3196 /* Return nonzero if the rtx X is invariant over the current loop.
3198 The value is 2 if we refer to something only conditionally invariant.
3200 A memory ref is invariant if it is not volatile and does not conflict
3201 with anything stored in `loop_info->store_mems'. */
3203 int
3206 rtx x;
3207 {
3214 rtx mem_list_entry;
3220 {
3228 /* A LABEL_REF is normally invariant, however, if we are unrolling
3229 loops, and this label is inside the loop, then it isn't invariant.
3230 This is because each unrolled copy of the loop body will have
3231 a copy of this label. If this was invariant, then an insn loading
3232 the address of this label into a register might get moved outside
3233 the loop, and then each loop body would end up using the same label.
3235 We don't know the loop bounds here though, so just fail for all
3236 labels. */
3239 else
3248 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3249 since the reg might be set by initialization within the loop. */
3266 /* Volatile memory references must be rejected. Do this before
3267 checking for read-only items, so that volatile read-only items
3268 will be rejected also. */
3272 /* See if there is any dependence between a store and this load. */
3275 {
3281 }
3283 /* It's not invalidated by a store in memory
3284 but we must still verify the address is invariant. */
3288 /* Don't mess with insns declared volatile. */
3295 }
3299 {
3301 {
3307 }
3309 {
3312 {
3318 }
3320 }
3321 }
3324 }
3325 \f
3326 /* Return nonzero if all the insns in the loop that set REG
3327 are INSN and the immediately following insns,
3328 and if each of those insns sets REG in an invariant way
3329 (not counting uses of REG in them).
3331 The value is 2 if some of these insns are only conditionally invariant.
3333 We assume that INSN itself is the first set of REG
3334 and that its source is invariant. */
3336 static int
3341 {
3345 rtx temp;
3346 /* Number of sets we have to insist on finding after INSN. */
3352 /* If N_SETS hit the limit, we can't rely on its value. */
3359 {
3361 rtx set;
3366 /* If library call, skip to end of it. */
3375 {
3380 {
3381 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3382 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3383 notes are OK. */
3389 }
3390 }
3392 count--;
3394 {
3397 }
3398 }
3401 /* If loop_invariant_p ever returned 2, we return 2. */
3403 }
3405 #if 0
3406 /* I don't think this condition is sufficient to allow INSN
3407 to be moved, so we no longer test it. */
3409 /* Return 1 if all insns in the basic block of INSN and following INSN
3410 that set REG are invariant according to TABLE. */
3412 static int
3416 {
3421 {
3430 {
3433 }
3434 }
3435 }
3437 \f
3438 /* Look at all uses (not sets) of registers in X. For each, if it is
3439 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3440 a different insn, set USAGE[REGNO] to const0_rtx. */
3442 static void
3445 rtx insn;
3446 rtx x;
3447 {
3459 {
3460 /* Don't count SET_DEST if it is a REG; otherwise count things
3461 in SET_DEST because if a register is partially modified, it won't
3462 show up as a potential movable so we don't care how USAGE is set
3463 for it. */
3467 }
3468 else
3470 {
3476 }
3477 }
3478 \f
3479 /* Count and record any set in X which is contained in INSN. Update
3480 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3481 in X. */
3483 static void
3488 {
3490 /* Don't move a reg that has an explicit clobber.
3491 It's not worth the pain to try to do it correctly. */
3495 {
3503 {
3507 {
3508 /* If this is the first setting of this reg
3509 in current basic block, and it was set before,
3510 it must be set in two basic blocks, so it cannot
3511 be moved out of the loop. */
3515 /* If this is not first setting in current basic block,
3516 see if reg was used in between previous one and this.
3517 If so, neither one can be moved. */
3524 }
3525 }
3526 }
3527 }
3528 \f
3529 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3530 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3531 contained in insn INSN is used by any insn that precedes INSN in
3532 cyclic order starting from the loop entry point.
3534 We don't want to use INSN_LUID here because if we restrict INSN to those
3535 that have a valid INSN_LUID, it means we cannot move an invariant out
3536 from an inner loop past two loops. */
3538 static int
3542 {
3544 rtx p;
3546 /* Scan forward checking for register usage. If we hit INSN, we
3547 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3549 {
3555 }
3558 }
3559 \f
3561 /* Information we collect about arrays that we might want to prefetch. */
3562 struct prefetch_info
3563 {
3567 index. */
3568 HOST_WIDE_INT index;
3570 iteration. */
3572 prefetch area in one iteration. */
3574 This is set only for loops with known
3575 iteration counts and is 0xffffffff
3576 otherwise. */
3579 /* 1 for those chosen for prefetching. */
3581 /* 1 for those chosen for prefetching. */
3582 };
3584 /* Data used by check_store function. */
3585 struct check_store_data
3586 {
3587 rtx mem_address;
3589 };
3595 /* Set mem_write when mem_address is found. Used as callback to
3596 note_stores. */
3597 static void
3601 {
3606 }
3607 \f
3608 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3609 important to get some addresses combined. Later more sophisticated
3610 transformations can be added when necesary.
3612 ??? Same trick with swapping operand is done at several other places.
3613 It can be nice to develop some common way to handle this. */
3615 static int
3618 {
3632 {
3637 }
3638 /* Compare the elements. If any pair of corresponding elements fails to
3639 match, return 0 for the whole thing. */
3643 {
3645 {
3657 /* Two vectors must have the same length. */
3661 /* And the corresponding elements must match. */
3679 /* These are just backpointers, so they don't matter. */
3685 /* It is believed that rtx's at this level will never
3686 contain anything but integers and other rtx's,
3687 except for within LABEL_REFs and SYMBOL_REFs. */
3690 }
3691 }
3693 }
3694 \f
3695 /* Remove constant addition value from the expression X (when present)
3696 and return it. */
3698 static HOST_WIDE_INT
3701 {
3705 /* Avoid clobbering a shared CONST expression. */
3707 {
3711 {
3714 }
3716 }
3719 {
3722 }
3724 /* For plus expression recurse on ourself. */
3726 {
3730 /* In case our parameter was constant, remove extra zero from the
3731 expression. */
3736 }
3739 }
3741 /* Attempt to identify accesses to arrays that are most likely to cause cache
3742 misses, and emit prefetch instructions a few prefetch blocks forward.
3744 To detect the arrays we use the GIV information that was collected by the
3745 strength reduction pass.
3747 The prefetch instructions are generated after the GIV information is done
3748 and before the strength reduction process. The new GIVs are injected into
3749 the strength reduction tables, so the prefetch addresses are optimized as
3750 well.
3752 GIVs are split into base address, stride, and constant addition values.
3753 GIVs with the same address, stride and close addition values are combined
3754 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3755 for write instructions can be used for the block we write to, on machines
3756 that support write prefetches.
3758 Several heuristics are used to determine when to prefetch. They are
3759 controlled by defined symbols that can be overridden for each target. */
3761 static void
3764 {
3778 /* Consider only loops w/o calls. When a call is done, the loop is probably
3779 slow enough to read the memory. */
3781 {
3786 }
3791 {
3796 }
3798 /* Search all induction variables and pick those interesting for the prefetch
3799 machinery. */
3801 {
3807 /* Expect all BIVs to be executed in each iteration. This makes our
3808 analysis more conservative. */
3810 {
3811 /* Discard non-constant additions that we can't handle well yet, and
3812 BIVs that are executed multiple times; such BIVs ought to be
3813 handled in the nested loop. We accept not_every_iteration BIVs,
3814 since these only result in larger strides and make our
3815 heuristics more conservative.
3816 ??? What does the last sentence mean? */
3818 {
3820 {
3826 }
3828 }
3831 {
3833 {
3839 }
3841 }
3845 }
3851 {
3852 rtx address;
3853 rtx temp;
3856 HOST_WIDE_INT stride;
3860 /* There are several reasons why an induction variable is not
3861 interesting to us. */
3863 /* We are interested only in constant stride memory references
3864 in order to be able to compute density easily. */
3866 /* Don't handle reversed order prefetches, since they are usually
3867 ineffective. Later we may be able to reverse such BIVs. */
3868 || (PREFETCH_NO_REVERSE_ORDER
3870 /* Prefetching of accesses with such an extreme stride is probably
3871 not worthwhile, either. */
3872 || (PREFETCH_NO_EXTREME_STRIDE
3874 /* Ignore GIVs with varying add values; we can't predict the
3875 value for the next iteration. */
3877 /* Ignore GIVs in the nested loops; they ought to have been
3878 handled already. */
3880 {
3885 }
3887 /* Determine the pointer to the basic array we are examining. It is
3888 the sum of the BIV's initial value and the GIV's add_val. */
3901 /* When the GIV is not always executed, we might be better off by
3902 not dirtying the cache pages. */
3906 /* Attempt to find another prefetch to the same array and see if we
3907 can merge this one. */
3911 {
3912 /* In case both access same array (same location
3913 just with small difference in constant indexes), merge
3914 the prefetches. Just do the later and the earlier will
3915 get prefetched from previous iteration.
3916 4096 is artificial threshold. It should not be too small,
3917 but also not bigger than small portion of memory usually
3918 traversed by single loop. */
3920 {
3929 }
3932 {
3937 }
3938 }
3940 /* Merging failed. */
3942 {
3950 num_prefetches++;
3952 {
3957 }
3958 }
3959 }
3960 }
3963 {
3964 /* Attempt to calculate the number of bytes fetched by the loop.
3965 Avoid overflow. */
3970 else
3973 /* Prefetch is worthwhile only when the loads/stores are dense. */
3978 {
3983 }
3984 else
3988 {
3992 num_real_write_prefetches
3994 }
3995 }
3998 {
4000 {
4015 }
4019 }
4030 {
4032 {
4037 {
4039 rtx insn;
4044 /* We can save some effort by offsetting the address on
4045 architectures with offsettable memory references. */
4048 else
4049 {
4055 }
4057 /* Make sure the address operand is valid for prefetch. */
4064 before_insn);
4066 /* Check all insns emitted and record the new GIV
4067 information. */
4070 {
4075 }
4076 }
4077 }
4080 {
4083 /* Emit INSNs before the loop to fetch the first cache lines. */
4087 {
4099 loop_start);
4100 }
4101 }
4102 }
4105 }
4106 \f
4107 /* A "basic induction variable" or biv is a pseudo reg that is set
4108 (within this loop) only by incrementing or decrementing it. */
4109 /* A "general induction variable" or giv is a pseudo reg whose
4110 value is a linear function of a biv. */
4112 /* Bivs are recognized by `basic_induction_var';
4113 Givs by `general_induction_var'. */
4115 /* Communication with routines called via `note_stores'. */
4119 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4123 /* ??? Unfinished optimizations, and possible future optimizations,
4124 for the strength reduction code. */
4126 /* ??? The interaction of biv elimination, and recognition of 'constant'
4127 bivs, may cause problems. */
4129 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4130 performance problems.
4132 Perhaps don't eliminate things that can be combined with an addressing
4133 mode. Find all givs that have the same biv, mult_val, and add_val;
4134 then for each giv, check to see if its only use dies in a following
4135 memory address. If so, generate a new memory address and check to see
4136 if it is valid. If it is valid, then store the modified memory address,
4137 otherwise, mark the giv as not done so that it will get its own iv. */
4139 /* ??? Could try to optimize branches when it is known that a biv is always
4140 positive. */
4142 /* ??? When replace a biv in a compare insn, we should replace with closest
4143 giv so that an optimized branch can still be recognized by the combiner,
4144 e.g. the VAX acb insn. */
4146 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4147 was rerun in loop_optimize whenever a register was added or moved.
4148 Also, some of the optimizations could be a little less conservative. */
4149 \f
4150 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4151 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4152 callback.
4154 NOT_EVERY_ITERATION if current insn is not executed at least once for every
4155 loop iteration except for the last one.
4157 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4158 loop iteration.
4159 */
4160 void
4163 loop_insn_callback fncall;
4164 {
4165 /* This is 1 if current insn is not executed at least once for every loop
4166 iteration. */
4171 rtx p;
4173 /* If loop_scan_start points to the loop exit test, we have to be wary of
4174 subversive use of gotos inside expression statements. */
4178 /* Scan through loop to find all possible bivs. */
4183 {
4186 /* Past CODE_LABEL, we get to insns that may be executed multiple
4187 times. The only way we can be sure that they can't is if every
4188 jump insn between here and the end of the loop either
4189 returns, exits the loop, is a jump to a location that is still
4190 behind the label, or is a jump to the loop start. */
4193 {
4199 {
4204 {
4207 else
4211 }
4219 {
4222 }
4223 }
4224 }
4226 /* Past a jump, we get to insns for which we can't count
4227 on whether they will be executed during each iteration. */
4228 /* This code appears twice in strength_reduce. There is also similar
4229 code in scan_loop. */
4231 /* If we enter the loop in the middle, and scan around to the
4232 beginning, don't set not_every_iteration for that.
4233 This can be any kind of jump, since we want to know if insns
4234 will be executed if the loop is executed. */
4239 {
4242 /* If this is a jump outside the loop, then it also doesn't
4243 matter. Check to see if the target of this branch is on the
4244 loop->exits_labels list. */
4252 }
4255 {
4256 /* At the virtual top of a converted loop, insns are again known to
4257 be executed each iteration: logically, the loop begins here
4258 even though the exit code has been duplicated.
4260 Insns are also again known to be executed each iteration at
4261 the LOOP_CONT note. */
4267 loop_depth++;
4269 loop_depth--;
4270 }
4272 /* Note if we pass a loop latch. If we do, then we can not clear
4273 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4274 a loop since a jump before the last CODE_LABEL may have started
4275 a new loop iteration.
4277 Note that LOOP_TOP is only set for rotated loops and we need
4278 this check for all loops, so compare against the CODE_LABEL
4279 which immediately follows LOOP_START. */
4284 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4285 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4286 or not an insn is known to be executed each iteration of the
4287 loop, whether or not any iterations are known to occur.
4289 Therefore, if we have just passed a label and have no more labels
4290 between here and the test insn of the loop, and we have not passed
4291 a jump to the top of the loop, then we know these insns will be
4292 executed each iteration. */
4295 && !past_loop_latch
4300 }
4301 }
4302 \f
4303 static void
4306 {
4309 /* Temporary list pointers for traversing ivs->list. */
4316 /* Scan ivs->list to remove all regs that proved not to be bivs.
4317 Make a sanity check against regs->n_times_set. */
4319 {
4321 /* Above happens if register modified by subreg, etc. */
4322 /* Make sure it is not recognized as a basic induction var: */
4324 /* If never incremented, it is invariant that we decided not to
4325 move. So leave it alone. */
4327 {
4338 }
4339 else
4340 {
4345 }
4346 }
4347 }
4350 /* Determine how BIVS are initialised by looking through pre-header
4351 extended basic block. */
4352 static void
4355 {
4357 /* Temporary list pointers for traversing ivs->list. */
4360 rtx p;
4362 /* Find initial value for each biv by searching backwards from loop_start,
4363 halting at first label. Also record any test condition. */
4367 {
4368 rtx test;
4378 /* Record any test of a biv that branches around the loop if no store
4379 between it and the start of loop. We only care about tests with
4380 constants and registers and only certain of those. */
4390 {
4391 /* If an NE test, we have an initial value! */
4393 {
4397 }
4398 else
4400 }
4401 }
4402 }
4405 /* Look at the each biv and see if we can say anything better about its
4406 initial value from any initializing insns set up above. (This is done
4407 in two passes to avoid missing SETs in a PARALLEL.) */
4408 static void
4411 {
4413 /* Temporary list pointers for traversing ivs->list. */
4418 {
4419 rtx src;
4420 rtx note;
4425 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4426 is a constant, use the value of that. */
4432 else
4445 {
4449 {
4452 }
4453 }
4454 /* If we can't make it a giv,
4455 let biv keep initial value of "itself". */
4458 }
4459 }
4462 /* Search the loop for general induction variables. */
4464 static void
4467 {
4469 }
4472 /* For each giv for which we still don't know whether or not it is
4473 replaceable, check to see if it is replaceable because its final value
4474 can be calculated. */
4476 static void
4479 {
4484 {
4490 }
4491 }
4494 /* Return non-zero if it is possible to eliminate the biv BL provided
4495 all givs are reduced. This is possible if either the reg is not
4496 used outside the loop, or we can compute what its final value will
4497 be. */
4499 static int
4505 {
4506 /* For architectures with a decrement_and_branch_until_zero insn,
4507 don't do this if we put a REG_NONNEG note on the endtest for this
4508 biv. */
4510 #ifdef HAVE_decrement_and_branch_until_zero
4512 {
4517 }
4518 #endif
4520 /* Check that biv is used outside loop or if it has a final value.
4521 Compare against bl->init_insn rather than loop->start. We aren't
4522 concerned with any uses of the biv between init_insn and
4523 loop->start since these won't be affected by the value of the biv
4524 elsewhere in the function, so long as init_insn doesn't use the
4525 biv itself. */
4536 {
4544 }
4546 }
4549 /* Reduce each giv of BL that we have decided to reduce. */
4551 static void
4555 {
4559 {
4562 {
4565 /* If the code for derived givs immediately below has already
4566 allocated a new_reg, we must keep it. */
4570 #ifdef AUTO_INC_DEC
4571 /* If the target has auto-increment addressing modes, and
4572 this is an address giv, then try to put the increment
4573 immediately after its use, so that flow can create an
4574 auto-increment addressing mode. */
4577 /* We don't handle reversed biv's because bl->biv->insn
4578 does not have a valid INSN_LUID. */
4582 {
4583 /* If other giv's have been combined with this one, then
4584 this will work only if all uses of the other giv's occur
4585 before this giv's insn. This is difficult to check.
4587 We simplify this by looking for the common case where
4588 there is one DEST_REG giv, and this giv's insn is the
4589 last use of the dest_reg of that DEST_REG giv. If the
4590 increment occurs after the address giv, then we can
4591 perform the optimization. (Otherwise, the increment
4592 would have to go before other_giv, and we would not be
4593 able to combine it with the address giv to get an
4594 auto-inc address.) */
4596 {
4601 {
4604 else
4606 }
4613 }
4614 /* Check for case where increment is before the address
4615 giv. Do this test in "loop order". */
4624 else
4627 #ifdef HAVE_cc0
4628 {
4629 rtx prev;
4631 /* We can't put an insn immediately after one setting
4632 cc0, or immediately before one using cc0. */
4639 }
4640 #endif
4644 }
4645 #endif
4647 /* For each place where the biv is incremented, add an insn
4648 to increment the new, reduced reg for the giv. */
4650 {
4651 rtx insert_before;
4657 else
4665 /* A multiply is acceptable here
4666 since this is presumed to be seldom executed. */
4670 }
4672 /* Add code at loop start to initialize giv's reduced reg. */
4677 }
4678 }
4679 }
4682 /* Check for givs whose first use is their definition and whose
4683 last use is the definition of another giv. If so, it is likely
4684 dead and should not be used to derive another giv nor to
4685 eliminate a biv. */
4687 static void
4691 {
4695 {
4702 {
4708 }
4709 }
4710 }
4713 static void
4718 {
4722 {
4729 /* Update expression if this was combined, in case other giv was
4730 replaced. */
4735 /* See if this register is known to be a pointer to something. If
4736 so, see if we can find the alignment. First see if there is a
4737 destination register that is a pointer. If so, this shares the
4738 alignment too. Next see if we can deduce anything from the
4739 computational information. If not, and this is a DEST_ADDR
4740 giv, at least we know that it's a pointer, though we don't know
4741 the alignment. */
4749 {
4758 }
4762 {
4770 }
4775 /* Store reduced reg as the address in the memref where we found
4776 this giv. */
4779 {
4781 }
4782 else
4783 {
4784 /* Not replaceable; emit an insn to set the original giv reg from
4785 the reduced giv, same as above. */
4788 }
4790 /* When a loop is reversed, givs which depend on the reversed
4791 biv, and which are live outside the loop, must be set to their
4792 correct final value. This insn is only needed if the giv is
4793 not replaceable. The correct final value is the same as the
4794 value that the giv starts the reversed loop with. */
4804 {
4809 }
4810 }
4811 }
4814 static int
4819 rtx test_reg;
4820 {
4829 /* Reduce benefit if not replaceable, since we will insert a
4830 move-insn to replace the insn that calculates this giv. Don't do
4831 this unless the giv is a user variable, since it will often be
4832 marked non-replaceable because of the duplication of the exit
4833 code outside the loop. In such a case, the copies we insert are
4834 dead and will be deleted. So they don't have a cost. Similar
4835 situations exist. */
4836 /* ??? The new final_[bg]iv_value code does a much better job of
4837 finding replaceable giv's, and hence this code may no longer be
4838 necessary. */
4843 /* Decrease the benefit to count the add-insns that we will insert
4844 to increment the reduced reg for the giv. ??? This can
4845 overestimate the run-time cost of the additional insns, e.g. if
4846 there are multiple basic blocks that increment the biv, but only
4847 one of these blocks is executed during each iteration. There is
4848 no good way to detect cases like this with the current structure
4849 of the loop optimizer. This code is more accurate for
4850 determining code size than run-time benefits. */
4853 /* Decide whether to strength-reduce this giv or to leave the code
4854 unchanged (recompute it from the biv each time it is used). This
4855 decision can be made independently for each giv. */
4857 #ifdef AUTO_INC_DEC
4858 /* Attempt to guess whether autoincrement will handle some of the
4859 new add insns; if so, increase BENEFIT (undo the subtraction of
4860 add_cost that was done above). */
4862 /* Increasing the benefit is risky, since this is only a guess.
4863 Avoid increasing register pressure in cases where there would
4864 be no other benefit from reducing this giv. */
4867 {
4882 }
4883 #endif
4886 }
4889 /* Free IV structures for LOOP. */
4891 static void
4894 {
4901 {
4907 {
4910 }
4912 {
4915 }
4919 }
4920 }
4923 /* Perform strength reduction and induction variable elimination.
4925 Pseudo registers created during this function will be beyond the
4926 last valid index in several tables including
4927 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4928 problem here, because the added registers cannot be givs outside of
4929 their loop, and hence will never be reconsidered. But scan_loop
4930 must check regnos to make sure they are in bounds. */
4932 static void
4936 {
4940 rtx p;
4941 /* Temporary list pointer for traversing ivs->list. */
4943 /* Ratio of extra register life span we can justify
4944 for saving an instruction. More if loop doesn't call subroutines
4945 since in that case saving an insn makes more difference
4946 and more registers are available. */
4947 /* ??? could set this to last value of threshold in move_movables */
4949 /* Map of pseudo-register replacements. */
4961 /* Find all BIVs in loop. */
4964 /* Exit if there are no bivs. */
4966 {
4967 /* Can still unroll the loop anyways, but indicate that there is no
4968 strength reduction info available. */
4974 }
4976 /* Determine how BIVS are initialised by looking through pre-header
4977 extended basic block. */
4980 /* Look at the each biv and see if we can say anything better about its
4981 initial value from any initializing insns set up above. */
4984 /* Search the loop for general induction variables. */
4987 /* Try to calculate and save the number of loop iterations. This is
4988 set to zero if the actual number can not be calculated. This must
4989 be called after all giv's have been identified, since otherwise it may
4990 fail if the iteration variable is a giv. */
4993 #ifdef HAVE_prefetch
4996 #endif
4998 /* Now for each giv for which we still don't know whether or not it is
4999 replaceable, check to see if it is replaceable because its final value
5000 can be calculated. This must be done after loop_iterations is called,
5001 so that final_giv_value will work correctly. */
5004 /* Try to prove that the loop counter variable (if any) is always
5005 nonnegative; if so, record that fact with a REG_NONNEG note
5006 so that "decrement and branch until zero" insn can be used. */
5009 /* Create reg_map to hold substitutions for replaceable giv regs.
5010 Some givs might have been made from biv increments, so look at
5011 ivs->reg_iv_type for a suitable size. */
5015 /* Examine each iv class for feasibility of strength reduction/induction
5016 variable elimination. */
5019 {
5023 /* Test whether it will be possible to eliminate this biv
5024 provided all givs are reduced. */
5027 /* This will be true at the end, if all givs which depend on this
5028 biv have been strength reduced.
5029 We can't (currently) eliminate the biv unless this is so. */
5032 /* Check each extension dependent giv in this class to see if its
5033 root biv is safe from wrapping in the interior mode. */
5036 /* Combine all giv's for this iv_class. */
5040 {
5048 /* If an insn is not to be strength reduced, then set its ignore
5049 flag, and clear bl->all_reduced. */
5051 /* A giv that depends on a reversed biv must be reduced if it is
5052 used after the loop exit, otherwise, it would have the wrong
5053 value after the loop exit. To make it simple, just reduce all
5054 of such giv's whether or not we know they are used after the loop
5055 exit. */
5060 {
5068 }
5069 else
5070 {
5071 /* Check that we can increment the reduced giv without a
5072 multiply insn. If not, reject it. */
5077 {
5085 }
5086 }
5087 }
5089 /* Check for givs whose first use is their definition and whose
5090 last use is the definition of another giv. If so, it is likely
5091 dead and should not be used to derive another giv nor to
5092 eliminate a biv. */
5095 /* Reduce each giv that we decided to reduce. */
5098 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5099 as not reduced.
5101 For each giv register that can be reduced now: if replaceable,
5102 substitute reduced reg wherever the old giv occurs;
5103 else add new move insn "giv_reg = reduced_reg". */
5106 /* All the givs based on the biv bl have been reduced if they
5107 merit it. */
5109 /* For each giv not marked as maybe dead that has been combined with a
5110 second giv, clear any "maybe dead" mark on that second giv.
5111 v->new_reg will either be or refer to the register of the giv it
5112 combined with.
5114 Doing this clearing avoids problems in biv elimination where
5115 a giv's new_reg is a complex value that can't be put in the
5116 insn but the giv combined with (with a reg as new_reg) is
5117 marked maybe_dead. Since the register will be used in either
5118 case, we'd prefer it be used from the simpler giv. */
5124 /* Try to eliminate the biv, if it is a candidate.
5125 This won't work if ! bl->all_reduced,
5126 since the givs we planned to use might not have been reduced.
5128 We have to be careful that we didn't initially think we could
5129 eliminate this biv because of a giv that we now think may be
5130 dead and shouldn't be used as a biv replacement.
5132 Also, there is the possibility that we may have a giv that looks
5133 like it can be used to eliminate a biv, but the resulting insn
5134 isn't valid. This can happen, for example, on the 88k, where a
5135 JUMP_INSN can compare a register only with zero. Attempts to
5136 replace it with a compare with a constant will fail.
5138 Note that in cases where this call fails, we may have replaced some
5139 of the occurrences of the biv with a giv, but no harm was done in
5140 doing so in the rare cases where it can occur. */
5144 {
5145 /* ?? If we created a new test to bypass the loop entirely,
5146 or otherwise drop straight in, based on this test, then
5147 we might want to rewrite it also. This way some later
5148 pass has more hope of removing the initialization of this
5149 biv entirely. */
5151 /* If final_value != 0, then the biv may be used after loop end
5152 and we must emit an insn to set it just in case.
5154 Reversed bivs already have an insn after the loop setting their
5155 value, so we don't need another one. We can't calculate the
5156 proper final value for such a biv here anyways. */
5164 }
5165 /* See above note wrt final_value. But since we couldn't eliminate
5166 the biv, we must set the value after the loop instead of before. */
5170 }
5172 /* Go through all the instructions in the loop, making all the
5173 register substitutions scheduled in REG_MAP. */
5178 {
5182 }
5185 {
5186 /* When we completely unroll a loop we will likely not need the increment
5187 of the loop BIV and we will not need the conditional branch at the
5188 end of the loop. */
5191 #ifdef HAVE_cc0
5192 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5193 need the comparison before the conditional branch at the end of the
5194 loop. */
5196 #endif
5198 /* We'll need one copy for each loop iteration. */
5201 /* A little slop to account for the ability to remove initialization
5202 code, better CSE, and other secondary benefits of completely
5203 unrolling some loops. */
5206 /* Clamp the value. */
5209 }
5211 /* Unroll loops from within strength reduction so that we can use the
5212 induction variable information that strength_reduce has already
5213 collected. Always unroll loops that would be as small or smaller
5214 unrolled than when rolled. */
5220 #ifdef HAVE_doloop_end
5225 /* In case number of iterations is known, drop branch prediction note
5226 in the branch. Do that only in second loop pass, as loop unrolling
5227 may change the number of iterations performed. */
5229 {
5230 unsigned HOST_WIDE_INT n
5235 }
5243 }
5244 \f
5245 /*Record all basic induction variables calculated in the insn. */
5246 static rtx
5249 rtx p;
5252 {
5254 rtx set;
5255 rtx dest_reg;
5256 rtx inc_val;
5257 rtx mult_val;
5263 {
5268 {
5273 {
5274 /* It is a possible basic induction variable.
5275 Create and initialize an induction structure for it. */
5283 }
5286 }
5287 }
5289 }
5290 \f
5291 /* Record all givs calculated in the insn.
5292 A register is a giv if: it is only set once, it is a function of a
5293 biv and a constant (or invariant), and it is not a biv. */
5294 static rtx
5297 rtx p;
5300 {
5303 rtx set;
5304 /* Look for a general induction variable in a register. */
5309 {
5310 rtx src_reg;
5311 rtx dest_reg;
5312 rtx add_val;
5313 rtx mult_val;
5314 rtx ext_val;
5317 rtx last_consec_insn;
5326 /* Equivalent expression is a giv. */
5331 /* Don't try to handle any regs made by loop optimization.
5332 We have nothing on them in regno_first_uid, etc. */
5334 /* Don't recognize a BASIC_INDUCT_VAR here. */
5336 /* This must be the only place where the register is set. */
5338 /* or all sets must be consecutive and make a giv. */
5343 {
5347 /* If this is a library call, increase benefit. */
5351 /* Skip the consecutive insns, if there are any. */
5359 }
5360 }
5362 #ifndef DONT_REDUCE_ADDR
5363 /* Look for givs which are memory addresses. */
5364 /* This resulted in worse code on a VAX 8600. I wonder if it
5365 still does. */
5368 maybe_multiple);
5369 #endif
5371 /* Update the status of whether giv can derive other givs. This can
5372 change when we pass a label or an insn that updates a biv. */
5377 }
5378 \f
5379 /* Return 1 if X is a valid source for an initial value (or as value being
5380 compared against in an initial test).
5382 X must be either a register or constant and must not be clobbered between
5383 the current insn and the start of the loop.
5385 INSN is the insn containing X. */
5387 static int
5389 rtx x;
5390 rtx insn;
5392 rtx loop_start;
5393 {
5397 /* Only consider pseudos we know about initialized in insns whose luids
5398 we know. */
5403 /* Don't use call-clobbered registers across a call which clobbers it. On
5404 some machines, don't use any hard registers at all. */
5406 && (SMALL_REGISTER_CLASSES
5410 /* Don't use registers that have been clobbered before the start of the
5411 loop. */
5416 }
5417 \f
5418 /* Scan X for memory refs and check each memory address
5419 as a possible giv. INSN is the insn whose pattern X comes from.
5420 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5421 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5422 more thanonce in each loop iteration. */
5424 static void
5427 rtx x;
5428 rtx insn;
5430 {
5440 {
5456 {
5457 rtx src_reg;
5458 rtx add_val;
5459 rtx mult_val;
5460 rtx ext_val;
5463 /* This code used to disable creating GIVs with mult_val == 1 and
5464 add_val == 0. However, this leads to lost optimizations when
5465 it comes time to combine a set of related DEST_ADDR GIVs, since
5466 this one would not be seen. */
5471 {
5472 /* Found one; record it. */
5481 }
5482 }
5487 }
5489 /* Recursively scan the subexpressions for other mem refs. */
5495 maybe_multiple);
5499 maybe_multiple);
5500 }
5501 \f
5502 /* Fill in the data about one biv update.
5503 V is the `struct induction' in which we record the biv. (It is
5504 allocated by the caller, with alloca.)
5505 INSN is the insn that sets it.
5506 DEST_REG is the biv's reg.
5508 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5509 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5510 being set to INC_VAL.
5512 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5513 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5514 can be executed more than once per iteration. If MAYBE_MULTIPLE
5515 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5516 executed exactly once per iteration. */
5518 static void
5523 rtx insn;
5524 rtx dest_reg;
5525 rtx inc_val;
5526 rtx mult_val;
5530 {
5546 /* Add this to the reg's iv_class, creating a class
5547 if this is the first incrementation of the reg. */
5551 {
5552 /* Create and initialize new iv_class. */
5562 /* Set initial value to the reg itself. */
5565 /* We haven't seen the initializing insn yet */
5575 /* Add this class to ivs->list. */
5579 /* Put it in the array of biv register classes. */
5581 }
5583 /* Update IV_CLASS entry for this biv. */
5592 }
5593 \f
5594 /* Fill in the data about one giv.
5595 V is the `struct induction' in which we record the giv. (It is
5596 allocated by the caller, with alloca.)
5597 INSN is the insn that sets it.
5598 BENEFIT estimates the savings from deleting this insn.
5599 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5600 into a register or is used as a memory address.
5602 SRC_REG is the biv reg which the giv is computed from.
5603 DEST_REG is the giv's reg (if the giv is stored in a reg).
5604 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5605 LOCATION points to the place where this giv's value appears in INSN. */
5607 static void
5612 rtx insn;
5613 rtx src_reg;
5614 rtx dest_reg;
5620 {
5625 rtx temp;
5627 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5628 undo the MULT canonicalization that we performed earlier. */
5658 /* The v->always_computable field is used in update_giv_derive, to
5659 determine whether a giv can be used to derive another giv. For a
5660 DEST_REG giv, INSN computes a new value for the giv, so its value
5661 isn't computable if INSN insn't executed every iteration.
5662 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5663 it does not compute a new value. Hence the value is always computable
5664 regardless of whether INSN is executed each iteration. */
5668 else
5674 {
5677 }
5679 {
5684 /* If the lifetime is zero, it means that this register is
5685 really a dead store. So mark this as a giv that can be
5686 ignored. This will not prevent the biv from being eliminated. */
5692 }
5694 /* Add the giv to the class of givs computed from one biv. */
5698 {
5701 /* Don't count DEST_ADDR. This is supposed to count the number of
5702 insns that calculate givs. */
5706 }
5707 else
5708 /* Fatal error, biv missing for this giv? */
5713 else
5714 {
5715 /* The giv can be replaced outright by the reduced register only if all
5716 of the following conditions are true:
5717 - the insn that sets the giv is always executed on any iteration
5718 on which the giv is used at all
5719 (there are two ways to deduce this:
5720 either the insn is executed on every iteration,
5721 or all uses follow that insn in the same basic block),
5722 - the giv is not used outside the loop
5723 - no assignments to the biv occur during the giv's lifetime. */
5726 /* Previous line always fails if INSN was moved by loop opt. */
5729 && (! not_every_iteration
5731 {
5732 /* Now check that there are no assignments to the biv within the
5733 giv's lifetime. This requires two separate checks. */
5735 /* Check each biv update, and fail if any are between the first
5736 and last use of the giv.
5738 If this loop contains an inner loop that was unrolled, then
5739 the insn modifying the biv may have been emitted by the loop
5740 unrolling code, and hence does not have a valid luid. Just
5741 mark the biv as not replaceable in this case. It is not very
5742 useful as a biv, because it is used in two different loops.
5743 It is very unlikely that we would be able to optimize the giv
5744 using this biv anyways. */
5748 {
5754 {
5758 }
5759 }
5761 /* If there are any backwards branches that go from after the
5762 biv update to before it, then this giv is not replaceable. */
5766 {
5770 }
5771 }
5772 else
5773 {
5774 /* May still be replaceable, we don't have enough info here to
5775 decide. */
5778 }
5779 }
5781 /* Record whether the add_val contains a const_int, for later use by
5782 combine_givs. */
5783 {
5788 ;
5792 {
5794 {
5799 else
5801 }
5804 }
5805 }
5809 }
5811 /* All this does is determine whether a giv can be made replaceable because
5812 its final value can be calculated. This code can not be part of record_giv
5813 above, because final_giv_value requires that the number of loop iterations
5814 be known, and that can not be accurately calculated until after all givs
5815 have been identified. */
5817 static void
5821 {
5828 /* DEST_ADDR givs will never reach here, because they are always marked
5829 replaceable above in record_giv. */
5831 /* The giv can be replaced outright by the reduced register only if all
5832 of the following conditions are true:
5833 - the insn that sets the giv is always executed on any iteration
5834 on which the giv is used at all
5835 (there are two ways to deduce this:
5836 either the insn is executed on every iteration,
5837 or all uses follow that insn in the same basic block),
5838 - its final value can be calculated (this condition is different
5839 than the one above in record_giv)
5840 - it's not used before the it's set
5841 - no assignments to the biv occur during the giv's lifetime. */
5843 #if 0
5844 /* This is only called now when replaceable is known to be false. */
5845 /* Clear replaceable, so that it won't confuse final_giv_value. */
5847 #endif
5851 {
5854 rtx last_giv_use;
5858 /* When trying to determine whether or not a biv increment occurs
5859 during the lifetime of the giv, we can ignore uses of the variable
5860 outside the loop because final_value is true. Hence we can not
5861 use regno_last_uid and regno_first_uid as above in record_giv. */
5863 /* Search the loop to determine whether any assignments to the
5864 biv occur during the giv's lifetime. Start with the insn
5865 that sets the giv, and search around the loop until we come
5866 back to that insn again.
5868 Also fail if there is a jump within the giv's lifetime that jumps
5869 to somewhere outside the lifetime but still within the loop. This
5870 catches spaghetti code where the execution order is not linear, and
5871 hence the above test fails. Here we assume that the giv lifetime
5872 does not extend from one iteration of the loop to the next, so as
5873 to make the test easier. Since the lifetime isn't known yet,
5874 this requires two loops. See also record_giv above. */
5879 {
5882 {
5885 }
5891 {
5892 /* It is possible for the BIV increment to use the GIV if we
5893 have a cycle. Thus we must be sure to check each insn for
5894 both BIV and GIV uses, and we must check for BIV uses
5895 first. */
5902 {
5904 {
5908 }
5910 }
5911 }
5912 }
5914 /* Now that the lifetime of the giv is known, check for branches
5915 from within the lifetime to outside the lifetime if it is still
5916 replaceable. */
5919 {
5922 {
5935 {
5944 }
5945 }
5946 }
5948 /* If it is replaceable, then save the final value. */
5951 }
5956 }
5957 \f
5958 /* Update the status of whether a giv can derive other givs.
5960 We need to do something special if there is or may be an update to the biv
5961 between the time the giv is defined and the time it is used to derive
5962 another giv.
5964 In addition, a giv that is only conditionally set is not allowed to
5965 derive another giv once a label has been passed.
5967 The cases we look at are when a label or an update to a biv is passed. */
5969 static void
5972 rtx p;
5973 {
5977 rtx tem;
5980 /* Search all IV classes, then all bivs, and finally all givs.
5982 There are three cases we are concerned with. First we have the situation
5983 of a giv that is only updated conditionally. In that case, it may not
5984 derive any givs after a label is passed.
5986 The second case is when a biv update occurs, or may occur, after the
5987 definition of a giv. For certain biv updates (see below) that are
5988 known to occur between the giv definition and use, we can adjust the
5989 giv definition. For others, or when the biv update is conditional,
5990 we must prevent the giv from deriving any other givs. There are two
5991 sub-cases within this case.
5993 If this is a label, we are concerned with any biv update that is done
5994 conditionally, since it may be done after the giv is defined followed by
5995 a branch here (actually, we need to pass both a jump and a label, but
5996 this extra tracking doesn't seem worth it).
5998 If this is a jump, we are concerned about any biv update that may be
5999 executed multiple times. We are actually only concerned about
6000 backward jumps, but it is probably not worth performing the test
6001 on the jump again here.
6003 If this is a biv update, we must adjust the giv status to show that a
6004 subsequent biv update was performed. If this adjustment cannot be done,
6005 the giv cannot derive further givs. */
6011 {
6013 {
6014 /* If cant_derive is already true, there is no point in
6015 checking all of these conditions again. */
6019 /* If this giv is conditionally set and we have passed a label,
6020 it cannot derive anything. */
6024 /* Skip givs that have mult_val == 0, since
6025 they are really invariants. Also skip those that are
6026 replaceable, since we know their lifetime doesn't contain
6027 any biv update. */
6031 /* The only way we can allow this giv to derive another
6032 is if this is a biv increment and we can form the product
6033 of biv->add_val and giv->mult_val. In this case, we will
6034 be able to compute a compensation. */
6036 {
6037 rtx ext_val_dummy;
6048 tem = simplify_giv_expr
6055 else
6057 }
6061 }
6062 }
6063 }
6064 \f
6065 /* Check whether an insn is an increment legitimate for a basic induction var.
6066 X is the source of insn P, or a part of it.
6067 MODE is the mode in which X should be interpreted.
6069 DEST_REG is the putative biv, also the destination of the insn.
6070 We accept patterns of these forms:
6071 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6072 REG = INVARIANT + REG
6074 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6075 store the additive term into *INC_VAL, and store the place where
6076 we found the additive term into *LOCATION.
6078 If X is an assignment of an invariant into DEST_REG, we set
6079 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6081 We also want to detect a BIV when it corresponds to a variable
6082 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6083 of the variable may be a PLUS that adds a SUBREG of that variable to
6084 an invariant and then sign- or zero-extends the result of the PLUS
6085 into the variable.
6087 Most GIVs in such cases will be in the promoted mode, since that is the
6088 probably the natural computation mode (and almost certainly the mode
6089 used for addresses) on the machine. So we view the pseudo-reg containing
6090 the variable as the BIV, as if it were simply incremented.
6092 Note that treating the entire pseudo as a BIV will result in making
6093 simple increments to any GIVs based on it. However, if the variable
6094 overflows in its declared mode but not its promoted mode, the result will
6095 be incorrect. This is acceptable if the variable is signed, since
6096 overflows in such cases are undefined, but not if it is unsigned, since
6097 those overflows are defined. So we only check for SIGN_EXTEND and
6098 not ZERO_EXTEND.
6100 If we cannot find a biv, we return 0. */
6102 static int
6105 rtx x;
6107 rtx dest_reg;
6108 rtx p;
6112 {
6120 {
6126 {
6128 }
6133 {
6135 }
6136 else
6149 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6150 handle addition of promoted variables.
6151 ??? The comment at the start of this function is wrong: promoted
6152 variable increments don't look like it says they do. */
6158 /* If this register is assigned in a previous insn, look at its
6159 source, but don't go outside the loop or past a label. */
6161 /* If this sets a register to itself, we would repeat any previous
6162 biv increment if we applied this strategy blindly. */
6168 {
6169 rtx dest;
6170 do
6171 {
6173 }
6202 }
6203 /* Fall through. */
6205 /* Can accept constant setting of biv only when inside inner most loop.
6206 Otherwise, a biv of an inner loop may be incorrectly recognized
6207 as a biv of the outer loop,
6208 causing code to be moved INTO the inner loop. */
6215 /* convert_modes aborts if we try to convert to or from CCmode, so just
6216 exclude that case. It is very unlikely that a condition code value
6217 would be a useful iterator anyways. convert_modes aborts if we try to
6218 convert a float mode to non-float or vice versa too. */
6222 {
6223 /* Possible bug here? Perhaps we don't know the mode of X. */
6227 }
6228 else
6236 /* Similar, since this can be a sign extension. */
6241 ;
6255 location);
6260 }
6261 }
6262 \f
6263 /* A general induction variable (giv) is any quantity that is a linear
6264 function of a basic induction variable,
6265 i.e. giv = biv * mult_val + add_val.
6266 The coefficients can be any loop invariant quantity.
6267 A giv need not be computed directly from the biv;
6268 it can be computed by way of other givs. */
6270 /* Determine whether X computes a giv.
6271 If it does, return a nonzero value
6272 which is the benefit from eliminating the computation of X;
6273 set *SRC_REG to the register of the biv that it is computed from;
6274 set *ADD_VAL and *MULT_VAL to the coefficients,
6275 such that the value of X is biv * mult + add; */
6277 static int
6281 rtx x;
6289 {
6293 /* If this is an invariant, forget it, it isn't a giv. */
6304 {
6307 /* Since this is now an invariant and wasn't before, it must be a giv
6308 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6309 with. */
6316 /* This is equivalent to a BIV. */
6323 /* Either (plus (biv) (invar)) or
6324 (plus (mult (biv) (invar_1)) (invar_2)). */
6326 {
6329 }
6330 else
6331 {
6334 }
6339 /* ADD_VAL is zero. */
6347 }
6349 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6350 unless they are CONST_INT). */
6358 else
6361 /* Always return true if this is a giv so it will be detected as such,
6362 even if the benefit is zero or negative. This allows elimination
6363 of bivs that might otherwise not be eliminated. */
6365 }
6366 \f
6367 /* Given an expression, X, try to form it as a linear function of a biv.
6368 We will canonicalize it to be of the form
6369 (plus (mult (BIV) (invar_1))
6370 (invar_2))
6371 with possible degeneracies.
6373 The invariant expressions must each be of a form that can be used as a
6374 machine operand. We surround then with a USE rtx (a hack, but localized
6375 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6376 routine; it is the caller's responsibility to strip them.
6378 If no such canonicalization is possible (i.e., two biv's are used or an
6379 expression that is neither invariant nor a biv or giv), this routine
6380 returns 0.
6382 For a non-zero return, the result will have a code of CONST_INT, USE,
6383 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6385 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6390 static rtx
6393 rtx x;
6396 {
6401 rtx tem;
6403 /* If this is not an integer mode, or if we cannot do arithmetic in this
6404 mode, this can't be a giv. */
6411 {
6418 /* Put constant last, CONST_INT last if both constant. */
6426 /* Handle addition of zero, then addition of an invariant. */
6431 {
6434 /* Adding two invariants must result in an invariant, so enclose
6435 addition operation inside a USE and return it. */
6445 else
6454 /* biv + invar or mult + invar. Return sum. */
6458 /* (a + invar_1) + invar_2. Associate. */
6459 return
6465 arg1)),
6470 }
6472 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6473 MULT to reduce cases. */
6479 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6480 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6481 Recurse to associate the second PLUS. */
6486 return
6494 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6510 /* Handle "a - b" as "a + b * (-1)". */
6516 constm1_rtx)),
6525 /* Put constant last, CONST_INT last if both constant. */
6530 /* If second argument is not now constant, not giv. */
6534 /* Handle multiply by 0 or 1. */
6542 {
6544 /* biv * invar. Done. */
6548 /* Product of two constants. */
6552 /* invar * invar is a giv, but attempt to simplify it somehow. */
6558 {
6559 /* (invar_0 * invar_1) * invar_2. Associate. */
6566 arg1)),
6568 }
6569 /* Porpagate the MULT expressions to the intermost nodes. */
6571 {
6572 /* (invar_0 + invar_1) * invar_2. Distribute. */
6578 arg1),
6582 arg1)),
6584 }
6588 /* (a * invar_1) * invar_2. Associate. */
6594 arg1)),
6598 /* (a + invar_1) * invar_2. Distribute. */
6603 arg1),
6606 arg1)),
6611 }
6614 /* Shift by constant is multiply by power of two. */
6618 return
6627 /* "-a" is "a * (-1)" */
6633 /* "~a" is "-a - 1". Silly, but easy. */
6637 const1_rtx),
6641 /* Already in proper form for invariant. */
6647 /* Conditionally recognize extensions of simple IVs. After we've
6648 computed loop traversal counts and verified the range of the
6649 source IV, we'll reevaluate this as a GIV. */
6651 {
6654 {
6657 }
6658 }
6662 /* If this is a new register, we can't deal with it. */
6666 /* Check for biv or giv. */
6668 {
6672 {
6675 /* Form expression from giv and add benefit. Ensure this giv
6676 can derive another and subtract any needed adjustment if so. */
6678 /* Increasing the benefit here is risky. The only case in which it
6679 is arguably correct is if this is the only use of V. In other
6680 cases, this will artificially inflate the benefit of the current
6681 giv, and lead to suboptimal code. Thus, it is disabled, since
6682 potentially not reducing an only marginally beneficial giv is
6683 less harmful than reducing many givs that are not really
6684 beneficial. */
6685 {
6689 }
6702 {
6705 }
6706 else
6707 {
6710 }
6712 }
6715 do_default:
6716 /* If it isn't an induction variable, and it is invariant, we
6717 may be able to simplify things further by looking through
6718 the bits we just moved outside the loop. */
6720 {
6726 {
6727 /* Ok, we found a match. Substitute and simplify. */
6729 /* If we match another movable, we must use that, as
6730 this one is going away. */
6735 /* If consec is non-zero, this is a member of a group of
6736 instructions that were moved together. We handle this
6737 case only to the point of seeking to the last insn and
6738 looking for a REG_EQUAL. Fail if we don't find one. */
6740 {
6743 do
6744 {
6746 }
6752 }
6753 else
6754 {
6758 }
6761 {
6762 /* What we are most interested in is pointer
6763 arithmetic on invariants -- only take
6764 patterns we may be able to do something with. */
6770 {
6772 benefit);
6775 }
6780 {
6785 }
6786 }
6788 }
6789 }
6791 }
6793 /* Fall through to general case. */
6795 /* If invariant, return as USE (unless CONST_INT).
6796 Otherwise, not giv. */
6801 {
6810 }
6811 else
6813 }
6814 }
6816 /* This routine folds invariants such that there is only ever one
6817 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6819 static rtx
6822 {
6828 {
6831 }
6834 {
6837 }
6838 else
6839 {
6842 }
6843 }
6845 static rtx
6849 {
6851 {
6855 else
6858 }
6861 else
6864 }
6865 \f
6866 /* Help detect a giv that is calculated by several consecutive insns;
6867 for example,
6868 giv = biv * M
6869 giv = giv + A
6870 The caller has already identified the first insn P as having a giv as dest;
6871 we check that all other insns that set the same register follow
6872 immediately after P, that they alter nothing else,
6873 and that the result of the last is still a giv.
6875 The value is 0 if the reg set in P is not really a giv.
6876 Otherwise, the value is the amount gained by eliminating
6877 all the consecutive insns that compute the value.
6879 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6880 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6882 The coefficients of the ultimate giv value are stored in
6883 *MULT_VAL and *ADD_VAL. */
6885 static int
6890 rtx p;
6891 rtx src_reg;
6892 rtx dest_reg;
6897 {
6903 rtx temp;
6904 rtx set;
6906 /* Indicate that this is a giv so that we can update the value produced in
6907 each insn of the multi-insn sequence.
6909 This induction structure will be used only by the call to
6910 general_induction_var below, so we can allocate it on our stack.
6911 If this is a giv, our caller will replace the induct var entry with
6912 a new induction structure. */
6933 {
6937 /* If libcall, skip to end of call sequence. */
6948 /* Giv created by equivalent expression. */
6954 {
6958 count--;
6962 }
6964 {
6965 /* Allow insns that set something other than this giv to a
6966 constant. Such insns are needed on machines which cannot
6967 include long constants and should not disqualify a giv. */
6976 }
6977 }
6982 }
6983 \f
6984 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6985 represented by G1. If no such expression can be found, or it is clear that
6986 it cannot possibly be a valid address, 0 is returned.
6988 To perform the computation, we note that
6989 G1 = x * v + a and
6990 G2 = y * v + b
6991 where `v' is the biv.
6993 So G2 = (y/b) * G1 + (b - a*y/x).
6995 Note that MULT = y/x.
6997 Update: A and B are now allowed to be additive expressions such that
6998 B contains all variables in A. That is, computing B-A will not require
6999 subtracting variables. */
7001 static rtx
7004 {
7005 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7010 /* If MULT is not 1, we cannot handle A with non-constants, since we
7011 would then be required to subtract multiples of the registers in A.
7012 This is theoretically possible, and may even apply to some Fortran
7013 constructs, but it is a lot of work and we do not attempt it here. */
7018 /* In general these structures are sorted top to bottom (down the PLUS
7019 chain), but not left to right across the PLUS. If B is a higher
7020 order giv than A, we can strip one level and recurse. If A is higher
7021 order, we'll eventually bail out, but won't know that until the end.
7022 If they are the same, we'll strip one level around this loop. */
7025 {
7037 /* We matched: remove one reg completely. */
7040 /* An alternate match. */
7043 /* An alternate match. */
7045 else
7046 {
7047 /* Indicates an extra register in B. Strip one level from B and
7048 recurse, hoping B was the higher order expression. */
7053 }
7054 }
7056 /* Here we are at the last level of A, go through the cases hoping to
7057 get rid of everything but a constant. */
7060 {
7073 }
7075 {
7077 }
7079 {
7084 }
7086 {
7091 else
7093 }
7098 }
7100 rtx
7103 {
7106 /* The value that G1 will be multiplied by must be a constant integer. Also,
7107 the only chance we have of getting a valid address is if b*c/a (see above
7108 for notation) is also an integer. */
7111 {
7116 }
7119 else
7120 {
7121 /* ??? Find out if the one is a multiple of the other? */
7123 }
7127 {
7128 /* Failed. If we've got a multiplication factor between G1 and G2,
7129 scale G1's addend and try again. */
7131 {
7135 {
7136 HOST_WIDE_INT m;
7140 }
7141 else
7142 {
7144 mult);
7145 }
7148 }
7149 }
7153 /* Form simplified final result. */
7158 else
7163 else
7164 {
7167 {
7171 }
7174 }
7175 }
7176 \f
7177 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7178 represented by G1. This indicates that G2 should be combined with G1 and
7179 that G2 can use (either directly or via an address expression) a register
7180 used to represent G1. */
7182 static rtx
7185 {
7188 /* With the introduction of ext dependent givs, we must care for modes.
7189 G2 must not use a wider mode than G1. */
7199 /* If these givs are identical, they can be combined. We use the results
7200 of express_from because the addends are not in a canonical form, so
7201 rtx_equal_p is a weaker test. */
7202 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7203 combination to be the other way round. */
7206 {
7208 }
7210 /* If G2 can be expressed as a function of G1 and that function is valid
7211 as an address and no more expensive than using a register for G2,
7212 the expression of G2 in terms of G1 can be used. */
7216 /* ??? Looses, especially with -fforce-addr, where *g2->location
7217 will always be a register, and so anything more complicated
7218 gets discarded. */
7219 #if 0
7220 #ifdef ADDRESS_COST
7222 #else
7224 #endif
7225 #endif
7226 )
7227 {
7229 }
7232 }
7233 \f
7234 /* Check each extension dependent giv in this class to see if its
7235 root biv is safe from wrapping in the interior mode, which would
7236 make the giv illegal. */
7238 static void
7242 {
7245 HOST_WIDE_INT start_val;
7251 /* Make sure the iteration data is available. We must have
7252 constants in order to be certain of no overflow. */
7253 /* ??? An unknown iteration count with an increment of +-1
7254 combined with friendly exit tests of against an invariant
7255 value is also ameanable to optimization. Not implemented. */
7261 /* Make sure the host can represent the arithmetic. */
7263 {
7265 HOST_WIDE_INT s_end_val;
7277 /* Check for host arithmatic overflow. */
7279 {
7281 HOST_WIDE_INT s_max;
7288 /* Check zero extension of biv ok. */
7290 /* Check for host arithmatic overflow. */
7291 && (neg_incr
7294 /* Check for target arithmetic overflow. */
7295 && (neg_incr
7298 {
7300 }
7302 /* Check sign extension of biv ok. */
7303 /* ??? While it is true that overflow with signed and pointer
7304 arithmetic is undefined, I fear too many programmers don't
7305 keep this fact in mind -- myself included on occasion.
7306 So leave alone with the signed overflow optimizations. */
7308 /* Check for host arithmatic overflow. */
7309 && (neg_incr
7312 /* Check for target arithmetic overflow. */
7313 && (neg_incr
7316 {
7318 }
7319 }
7320 }
7322 /* Invalidate givs that fail the tests. */
7325 {
7330 {
7339 /* We don't know whether this value is being used as either
7340 signed or unsigned, so to safely truncate we must satisfy
7341 both. The initial check here verifies the BIV itself;
7342 once that is successful we may check its range wrt the
7343 derived GIV. */
7345 {
7349 /* We know from the above that both endpoints are nonnegative,
7350 and that there is no wrapping. Verify that both endpoints
7351 are within the (signed) range of the outer mode. */
7354 }
7359 }
7362 {
7364 {
7368 }
7369 }
7370 else
7371 {
7373 {
7378 else
7379 {
7384 else
7386 }
7391 }
7394 }
7395 }
7396 }
7398 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7400 rtx
7403 rtx value;
7404 {
7410 /* Recall that check_ext_dependent_givs verified that the known bounds
7411 of a biv did not overflow or wrap with respect to the extension for
7412 the giv. Therefore, constants need no additional adjustment. */
7416 /* Otherwise, we must adjust the value to compensate for the
7417 differing modes of the biv and the giv. */
7419 }
7420 \f
7421 struct combine_givs_stats
7422 {
7425 };
7427 static int
7431 {
7438 /* Stabilize the sort. */
7442 }
7444 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7445 any other. If so, point SAME to the giv combined with and set NEW_REG to
7446 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7447 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7449 static void
7453 {
7454 /* Additional benefit to add for being combined multiple times. */
7462 /* Count givs, because bl->giv_count is incorrect here. */
7466 giv_count++;
7468 giv_array
7479 {
7481 rtx single_use;
7486 /* If a DEST_REG GIV is used only once, do not allow it to combine
7487 with anything, for in doing so we will gain nothing that cannot
7488 be had by simply letting the GIV with which we would have combined
7489 to be reduced on its own. The losage shows up in particular with
7490 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7491 be seen elsewhere as well. */
7498 /* Add an additional weight for zero addends. */
7503 {
7504 rtx this_combine;
7509 {
7512 }
7513 }
7515 }
7517 /* Iterate, combining until we can't. */
7518 restart:
7522 {
7525 {
7531 }
7533 }
7536 {
7542 /* If it has already been combined, skip. */
7547 {
7550 /* If it has already been combined, skip. */
7552 {
7557 /* For destination, we now may replace by mem expression instead
7558 of register. This changes the costs considerably, so add the
7559 compensation. */
7569 /* ??? The new final_[bg]iv_value code does a much better job
7570 of finding replaceable giv's, and hence this code may no
7571 longer be necessary. */
7575 /* To help optimize the next set of combinations, remove
7576 this giv from the benefits of other potential mates. */
7578 {
7582 }
7589 }
7590 }
7592 /* To help optimize the next set of combinations, remove
7593 this giv from the benefits of other potential mates. */
7595 {
7597 {
7601 }
7605 /* We've finished with this giv, and everything it touched.
7606 Restart the combination so that proper weights for the
7607 rest of the givs are properly taken into account. */
7608 /* ??? Ideally we would compact the arrays at this point, so
7609 as to not cover old ground. But sanely compacting
7610 can_combine is tricky. */
7612 }
7613 }
7615 /* Clean up. */
7618 }
7619 \f
7620 /* Generate sequence for REG = B * M + A. */
7622 static rtx
7628 {
7629 rtx seq;
7630 rtx result;
7633 /* Use unsigned arithmetic. */
7641 }
7644 /* Update registers created in insn sequence SEQ. */
7646 static void
7649 rtx seq;
7650 {
7651 /* Update register info for alias analysis. */
7654 {
7657 {
7661 }
7662 }
7663 else
7664 {
7668 }
7669 }
7672 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7674 void
7681 basic_block before_bb;
7682 rtx before_insn;
7683 {
7684 rtx seq;
7687 {
7690 }
7692 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7695 /* Increase the lifetime of any invariants moved further in code. */
7702 /* It is possible that the expansion created lots of new registers.
7703 Iterate over the sequence we just created and record them all. */
7705 }
7708 /* Emit insns in loop pre-header to set REG = B * M + A. */
7710 void
7717 {
7718 rtx seq;
7720 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7723 /* Increase the lifetime of any invariants moved further in code.
7724 ???? Is this really necessary? */
7731 /* It is possible that the expansion created lots of new registers.
7732 Iterate over the sequence we just created and record them all. */
7734 }
7737 /* Emit insns after loop to set REG = B * M + A. */
7739 void
7746 {
7747 rtx seq;
7749 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7754 /* It is possible that the expansion created lots of new registers.
7755 Iterate over the sequence we just created and record them all. */
7757 }
7761 /* Similar to gen_add_mult, but compute cost rather than generating
7762 sequence. */
7764 static int
7770 {
7780 {
7785 }
7788 }
7789 \f
7790 /* Test whether A * B can be computed without
7791 an actual multiply insn. Value is 1 if so. */
7793 static int
7795 rtx a;
7796 rtx b;
7797 {
7799 rtx tmp;
7802 /* If only one is constant, make it B. */
7806 /* If first constant, both constant, so don't need multiply. */
7810 /* If second not constant, neither is constant, so would need multiply. */
7814 /* One operand is constant, so might not need multiply insn. Generate the
7815 code for the multiply and see if a call or multiply, or long sequence
7816 of insns is generated. */
7824 {
7829 else
7831 {
7840 {
7843 }
7844 }
7845 }
7855 }
7856 \f
7857 /* Check to see if loop can be terminated by a "decrement and branch until
7858 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7859 Also try reversing an increment loop to a decrement loop
7860 to see if the optimization can be performed.
7861 Value is nonzero if optimization was performed. */
7863 /* This is useful even if the architecture doesn't have such an insn,
7864 because it might change a loops which increments from 0 to n to a loop
7865 which decrements from n to 0. A loop that decrements to zero is usually
7866 faster than one that increments from zero. */
7868 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7869 such as approx_final_value, biv_total_increment, loop_iterations, and
7870 final_[bg]iv_value. */
7872 static int
7876 {
7881 rtx reg;
7882 rtx jump_label;
7883 rtx final_value;
7884 rtx start_value;
7885 rtx new_add_val;
7886 rtx comparison;
7887 rtx before_comparison;
7888 rtx p;
7889 rtx jump;
7890 rtx first_compare;
7895 /* If last insn is a conditional branch, and the insn before tests a
7896 register value, try to optimize it. Otherwise, we can't do anything. */
7905 /* Try to compute whether the compare/branch at the loop end is one or
7906 two instructions. */
7912 else
7915 {
7916 /* If more than one condition is present to control the loop, then
7917 do not proceed, as this function does not know how to rewrite
7918 loop tests with more than one condition.
7920 Look backwards from the first insn in the last comparison
7921 sequence and see if we've got another comparison sequence. */
7923 rtx jump1;
7927 }
7929 /* Check all of the bivs to see if the compare uses one of them.
7930 Skip biv's set more than once because we can't guarantee that
7931 it will be zero on the last iteration. Also skip if the biv is
7932 used between its update and the test insn. */
7935 {
7940 first_compare))
7942 }
7947 /* Look for the case where the basic induction variable is always
7948 nonnegative, and equals zero on the last iteration.
7949 In this case, add a reg_note REG_NONNEG, which allows the
7950 m68k DBRA instruction to be used. */
7958 {
7959 /* Initial value must be greater than 0,
7960 init_val % -dec_value == 0 to ensure that it equals zero on
7961 the last iteration */
7967 {
7968 /* register always nonnegative, add REG_NOTE to branch */
7976 }
7978 /* If the decrement is 1 and the value was tested as >= 0 before
7979 the loop, then we can safely optimize. */
7981 {
7994 {
8002 }
8003 }
8004 }
8007 {
8008 /* Try to change inc to dec, so can apply above optimization. */
8009 /* Can do this if:
8010 all registers modified are induction variables or invariant,
8011 all memory references have non-overlapping addresses
8012 (obviously true if only one write)
8013 allow 2 insns for the compare/jump at the end of the loop. */
8014 /* Also, we must avoid any instructions which use both the reversed
8015 biv and another biv. Such instructions will fail if the loop is
8016 reversed. We meet this condition by requiring that either
8017 no_use_except_counting is true, or else that there is only
8018 one biv. */
8020 /* 1 if the iteration var is used only to count iterations. */
8022 /* 1 if the loop has no memory store, or it has a single memory store
8023 which is reversible. */
8029 {
8033 /* If there are no givs for this biv, and the only exit is the
8034 fall through at the end of the loop, then
8035 see if perhaps there are no uses except to count. */
8039 {
8044 /* An insn that sets the biv is okay. */
8045 ;
8049 {
8050 /* If either of these insns uses the biv and sets a pseudo
8051 that has more than one usage, then the biv has uses
8052 other than counting since it's used to derive a value
8053 that is used more than one time. */
8055 regs);
8057 {
8060 }
8061 }
8063 {
8066 }
8067 }
8069 /* A biv has uses besides counting if it is used to set
8070 another biv. */
8074 {
8077 }
8078 }
8081 /* No need to worry about MEMs. */
8082 ;
8084 {
8089 /* If the loop has a single store, and the destination address is
8090 invariant, then we can't reverse the loop, because this address
8091 might then have the wrong value at loop exit.
8092 This would work if the source was invariant also, however, in that
8093 case, the insn should have been moved out of the loop. */
8096 {
8099 /* If we could prove that each of the memory locations
8100 written to was different, then we could reverse the
8101 store -- but we don't presently have any way of
8102 knowing that. */
8105 /* If the store depends on a register that is set after the
8106 store, it depends on the initial value, and is thus not
8107 reversible. */
8109 {
8116 }
8117 }
8118 }
8119 else
8122 /* This code only acts for innermost loops. Also it simplifies
8123 the memory address check by only reversing loops with
8124 zero or one memory access.
8125 Two memory accesses could involve parts of the same array,
8126 and that can't be reversed.
8127 If the biv is used only for counting, than we don't need to worry
8128 about all these things. */
8133 && reversible_mem_store
8138 {
8139 rtx tem;
8141 /* Loop can be reversed. */
8145 /* Now check other conditions:
8147 The increment must be a constant, as must the initial value,
8148 and the comparison code must be LT.
8150 This test can probably be improved since +/- 1 in the constant
8151 can be obtained by changing LT to LE and vice versa; this is
8152 confusing. */
8155 /* for constants, LE gets turned into LT */
8159 {
8170 comparison_const_width
8172 else
8173 comparison_const_width
8177 comparison_sign_mask
8180 /* If the comparison value is not a loop invariant, then we
8181 can not reverse this loop.
8183 ??? If the insns which initialize the comparison value as
8184 a whole compute an invariant result, then we could move
8185 them out of the loop and proceed with loop reversal. */
8193 /* Normalize the initial value if it is an integer and
8194 has no other use except as a counter. This will allow
8195 a few more loops to be reversed. */
8199 {
8201 /* The code below requires comparison_val to be a multiple
8202 of add_val in order to do the loop reversal, so
8203 round up comparison_val to a multiple of add_val.
8204 Since comparison_value is constant, we know that the
8205 current comparison code is LT. */
8207 comparison_val
8209 /* We postpone overflow checks for COMPARISON_VAL here;
8210 even if there is an overflow, we might still be able to
8211 reverse the loop, if converting the loop exit test to
8212 NE is possible. */
8214 }
8216 /* First check if we can do a vanilla loop reversal. */
8218 /* If we have a decrement_and_branch_on_count,
8219 prefer the NE test, since this will allow that
8220 instruction to be generated. Note that we must
8221 use a vanilla loop reversal if the biv is used to
8222 calculate a giv or has a non-counting use. */
8223 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8224 && defined (HAVE_decrement_and_branch_on_count)
8228 #endif
8230 /* Now do postponed overflow checks on COMPARISON_VAL. */
8233 {
8234 /* Register will always be nonnegative, with value
8235 0 on last iteration */
8239 }
8243 {
8246 }
8247 else
8253 /* If the initial value is not zero, or if the comparison
8254 value is not an exact multiple of the increment, then we
8255 can not reverse this loop. */
8258 {
8261 }
8262 else
8263 {
8266 }
8270 /* Reset these in case we normalized the initial value
8271 and comparison value above. */
8274 {
8276 final_value
8278 }
8281 /* Save some info needed to produce the new insns. */
8286 /* Set start_value; if this is not a CONST_INT, we need
8287 to generate a SUB.
8288 Initialize biv to start_value before loop start.
8289 The old initializing insn will be deleted as a
8290 dead store by flow.c. */
8293 {
8296 }
8298 {
8306 start_value
8312 }
8314 {
8317 initial_value);
8321 start_value
8324 }
8325 else
8326 /* We could handle the other cases too, but it'll be
8327 better to have a testcase first. */
8330 /* We may not have a single insn which can increment a reg, so
8331 create a sequence to hold all the insns from expand_inc. */
8340 /* Update biv info to reflect its new status. */
8345 /* Update loop info. */
8354 /* Inc LABEL_NUSES so that delete_insn will
8355 not delete the label. */
8358 /* Emit an insn after the end of the loop to set the biv's
8359 proper exit value if it is used anywhere outside the loop. */
8365 /* Delete compare/branch at end of loop. */
8370 /* Add new compare/branch insn at end of loop. */
8382 ;
8388 {
8390 {
8391 /* Increment of LABEL_NUSES done above. */
8392 /* Register is now always nonnegative,
8393 so add REG_NONNEG note to the branch. */
8396 }
8398 }
8400 /* No insn may reference both the reversed and another biv or it
8401 will fail (see comment near the top of the loop reversal
8402 code).
8403 Earlier on, we have verified that the biv has no use except
8404 counting, or it is the only biv in this function.
8405 However, the code that computes no_use_except_counting does
8406 not verify reg notes. It's possible to have an insn that
8407 references another biv, and has a REG_EQUAL note with an
8408 expression based on the reversed biv. To avoid this case,
8409 remove all REG_EQUAL notes based on the reversed biv
8410 here. */
8413 {
8416 /* If this is a set of a GIV based on the reversed biv, any
8417 REG_EQUAL notes should still be correct. */
8424 {
8429 else
8431 }
8432 }
8434 /* Mark that this biv has been reversed. Each giv which depends
8435 on this biv, and which is also live past the end of the loop
8436 will have to be fixed up. */
8441 {
8445 else
8447 }
8450 }
8451 }
8452 }
8455 }
8456 \f
8457 /* Verify whether the biv BL appears to be eliminable,
8458 based on the insns in the loop that refer to it.
8460 If ELIMINATE_P is non-zero, actually do the elimination.
8462 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8463 determine whether invariant insns should be placed inside or at the
8464 start of the loop. */
8466 static int
8472 {
8475 rtx p;
8477 /* Scan all insns in the loop, stopping if we find one that uses the
8478 biv in a way that we cannot eliminate. */
8481 {
8486 /* If this is a libcall that sets a giv, skip ahead to its end. */
8488 {
8492 {
8497 {
8504 }
8505 }
8506 }
8511 {
8517 }
8518 }
8521 {
8526 }
8529 }
8530 \f
8531 /* INSN and REFERENCE are instructions in the same insn chain.
8532 Return non-zero if INSN is first. */
8534 int
8537 {
8541 {
8542 /* Start with test for not first so that INSN == REFERENCE yields not
8543 first. */
8549 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8550 previous insn, hence the <= comparison below does not work if
8551 P is a note. */
8562 }
8563 }
8565 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8566 the offset that we have to take into account due to auto-increment /
8567 div derivation is zero. */
8568 static int
8571 rtx insn;
8572 {
8573 /* If the giv V had the auto-inc address optimization applied
8574 to it, and INSN occurs between the giv insn and the biv
8575 insn, then we'd have to adjust the value used here.
8576 This is rare, so we don't bother to make this possible. */
8585 }
8587 /* If BL appears in X (part of the pattern of INSN), see if we can
8588 eliminate its use. If so, return 1. If not, return 0.
8590 If BIV does not appear in X, return 1.
8592 If ELIMINATE_P is non-zero, actually do the elimination.
8593 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8594 Depending on how many items have been moved out of the loop, it
8595 will either be before INSN (when WHERE_INSN is non-zero) or at the
8596 start of the loop (when WHERE_INSN is zero). */
8598 static int
8604 basic_block where_bb;
8605 rtx where_insn;
8606 {
8612 #ifdef HAVE_cc0
8614 #endif
8620 {
8622 /* If we haven't already been able to do something with this BIV,
8623 we can't eliminate it. */
8629 /* If this sets the BIV, it is not a problem. */
8633 /* If this is an insn that defines a giv, it is also ok because
8634 it will go away when the giv is reduced. */
8639 #ifdef HAVE_cc0
8641 {
8642 /* Can replace with any giv that was reduced and
8643 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8644 Require a constant for MULT_VAL, so we know it's nonzero.
8645 ??? We disable this optimization to avoid potential
8646 overflows. */
8654 {
8661 /* If the giv has the opposite direction of change,
8662 then reverse the comparison. */
8666 else
8669 /* We can probably test that giv's reduced reg. */
8672 }
8674 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8675 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8676 Require a constant for MULT_VAL, so we know it's nonzero.
8677 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8678 overflow problem. */
8690 {
8697 /* If the giv has the opposite direction of change,
8698 then reverse the comparison. */
8702 else
8706 /* Replace biv with the giv's reduced register. */
8711 /* Insn doesn't support that constant or invariant. Copy it
8712 into a register (it will be a loop invariant.) */
8719 /* Substitute the new register for its invariant value in
8720 the compare expression. */
8724 }
8725 }
8726 #endif
8733 /* See if either argument is the biv. */
8738 else
8742 {
8743 /* First try to replace with any giv that has constant positive
8744 mult_val and constant add_val. We might be able to support
8745 negative mult_val, but it seems complex to do it in general. */
8757 {
8764 /* Replace biv with the giv's reduced reg. */
8767 /* If all constants are actually constant integers and
8768 the derived constant can be directly placed in the COMPARE,
8769 do so. */
8773 {
8778 }
8779 else
8780 {
8781 /* Otherwise, load it into a register. */
8787 }
8790 }
8792 /* Look for giv with positive constant mult_val and nonconst add_val.
8793 Insert insns to calculate new compare value.
8794 ??? Turn this off due to possible overflow. */
8802 {
8803 rtx tem;
8813 /* Replace biv with giv's reduced register. */
8817 /* Compute value to compare against. */
8821 /* Use it in this insn. */
8825 }
8826 }
8828 {
8830 {
8831 /* Look for giv with constant positive mult_val and nonconst
8832 add_val. Insert insns to compute new compare value.
8833 ??? Turn this off due to possible overflow. */
8840 {
8841 rtx tem;
8851 /* Replace biv with giv's reduced register. */
8855 /* Compute value to compare against. */
8862 }
8863 }
8865 /* This code has problems. Basically, you can't know when
8866 seeing if we will eliminate BL, whether a particular giv
8867 of ARG will be reduced. If it isn't going to be reduced,
8868 we can't eliminate BL. We can try forcing it to be reduced,
8869 but that can generate poor code.
8871 The problem is that the benefit of reducing TV, below should
8872 be increased if BL can actually be eliminated, but this means
8873 we might have to do a topological sort of the order in which
8874 we try to process biv. It doesn't seem worthwhile to do
8875 this sort of thing now. */
8877 #if 0
8878 /* Otherwise the reg compared with had better be a biv. */
8883 /* Look for a pair of givs, one for each biv,
8884 with identical coefficients. */
8886 {
8898 {
8905 /* Replace biv with its giv's reduced reg. */
8907 /* Replace other operand with the other giv's
8908 reduced reg. */
8911 }
8912 }
8913 #endif
8914 }
8916 /* If we get here, the biv can't be eliminated. */
8920 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8921 biv is used in it, since it will be replaced. */
8929 }
8931 /* See if any subexpression fails elimination. */
8934 {
8936 {
8949 }
8950 }
8953 }
8954 \f
8955 /* Return nonzero if the last use of REG
8956 is in an insn following INSN in the same basic block. */
8958 static int
8960 rtx reg;
8961 rtx insn;
8962 {
8963 rtx n;
8967 {
8970 }
8972 }
8973 \f
8974 /* Called via `note_stores' to record the initial value of a biv. Here we
8975 just record the location of the set and process it later. */
8977 static void
8979 rtx dest;
8980 rtx set;
8982 {
8993 /* If this is the first set found, record it. */
8995 {
8998 }
8999 }
9000 \f
9001 /* If any of the registers in X are "old" and currently have a last use earlier
9002 than INSN, update them to have a last use of INSN. Their actual last use
9003 will be the previous insn but it will not have a valid uid_luid so we can't
9004 use it. X must be a source expression only. */
9006 static void
9008 rtx x;
9009 rtx insn;
9010 {
9011 /* Check for the case where INSN does not have a valid luid. In this case,
9012 there is no need to modify the regno_last_uid, as this can only happen
9013 when code is inserted after the loop_end to set a pseudo's final value,
9014 and hence this insn will never be the last use of x.
9015 ???? This comment is not correct. See for example loop_givs_reduce.
9016 This may insert an insn before another new insn. */
9020 {
9022 }
9023 else
9024 {
9028 {
9034 }
9035 }
9036 }
9037 \f
9038 /* Given an insn INSN and condition COND, return the condition in a
9039 canonical form to simplify testing by callers. Specifically:
9041 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9042 (2) Both operands will be machine operands; (cc0) will have been replaced.
9043 (3) If an operand is a constant, it will be the second operand.
9044 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9045 for GE, GEU, and LEU.
9047 If the condition cannot be understood, or is an inequality floating-point
9048 comparison which needs to be reversed, 0 will be returned.
9050 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9052 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9053 insn used in locating the condition was found. If a replacement test
9054 of the condition is desired, it should be placed in front of that
9055 insn and we will be sure that the inputs are still valid.
9057 If WANT_REG is non-zero, we wish the condition to be relative to that
9058 register, if possible. Therefore, do not canonicalize the condition
9059 further. */
9061 rtx
9063 rtx insn;
9064 rtx cond;
9067 rtx want_reg;
9068 {
9071 rtx set;
9072 rtx tem;
9090 /* If we are comparing a register with zero, see if the register is set
9091 in the previous insn to a COMPARE or a comparison operation. Perform
9092 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9093 in cse.c */
9098 {
9099 /* Set non-zero when we find something of interest. */
9102 #ifdef HAVE_cc0
9103 /* If comparison with cc0, import actual comparison from compare
9104 insn. */
9106 {
9117 }
9118 #endif
9120 /* If this is a COMPARE, pick up the two things being compared. */
9122 {
9126 }
9130 /* Go back to the previous insn. Stop if it is not an INSN. We also
9131 stop if it isn't a single set or if it has a REG_INC note because
9132 we don't want to bother dealing with it. */
9146 /* If this is setting OP0, get what it sets it to if it looks
9147 relevant. */
9149 {
9152 /* ??? We may not combine comparisons done in a CCmode with
9153 comparisons not done in a CCmode. This is to aid targets
9154 like Alpha that have an IEEE compliant EQ instruction, and
9155 a non-IEEE compliant BEQ instruction. The use of CCmode is
9156 actually artificial, simply to prevent the combination, but
9157 should not affect other platforms.
9159 However, we must allow VOIDmode comparisons to match either
9160 CCmode or non-CCmode comparison, because some ports have
9161 modeless comparisons inside branch patterns.
9163 ??? This mode check should perhaps look more like the mode check
9164 in simplify_comparison in combine. */
9172 && (STORE_FLAG_VALUE
9175 #ifdef FLOAT_STORE_FLAG_VALUE
9178 && (REAL_VALUE_NEGATIVE
9180 #endif
9181 ))
9192 && (STORE_FLAG_VALUE
9195 #ifdef FLOAT_STORE_FLAG_VALUE
9198 && (REAL_VALUE_NEGATIVE
9200 #endif
9201 ))
9207 {
9210 }
9211 else
9213 }
9216 /* If this sets OP0, but not directly, we have to give up. */
9220 {
9224 {
9229 }
9234 }
9235 }
9237 /* If constant is first, put it last. */
9241 /* If OP0 is the result of a comparison, we weren't able to find what
9242 was really being compared, so fail. */
9246 /* Canonicalize any ordered comparison with integers involving equality
9247 if we can do computations in the relevant mode and we do not
9248 overflow. */
9253 {
9256 unsigned HOST_WIDE_INT max_val
9260 {
9266 /* When cross-compiling, const_val might be sign-extended from
9267 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9287 }
9288 }
9290 #ifdef HAVE_cc0
9291 /* Never return CC0; return zero instead. */
9294 #endif
9297 }
9299 /* Given a jump insn JUMP, return the condition that will cause it to branch
9300 to its JUMP_LABEL. If the condition cannot be understood, or is an
9301 inequality floating-point comparison which needs to be reversed, 0 will
9302 be returned.
9304 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9305 insn used in locating the condition was found. If a replacement test
9306 of the condition is desired, it should be placed in front of that
9307 insn and we will be sure that the inputs are still valid. */
9309 rtx
9311 rtx jump;
9313 {
9314 rtx cond;
9316 rtx set;
9318 /* If this is not a standard conditional jump, we can't parse it. */
9326 /* If this branches to JUMP_LABEL when the condition is false, reverse
9327 the condition. */
9328 reverse
9333 }
9335 /* Similar to above routine, except that we also put an invariant last
9336 unless both operands are invariants. */
9338 rtx
9341 rtx x;
9342 {
9352 }
9354 /* Scan the function and determine whether it has indirect (computed) jumps.
9356 This is taken mostly from flow.c; similar code exists elsewhere
9357 in the compiler. It may be useful to put this into rtlanal.c. */
9358 static int
9360 rtx start;
9361 {
9362 rtx insn;
9369 }
9371 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9372 documentation for LOOP_MEMS for the definition of `appropriate'.
9373 This function is called from prescan_loop via for_each_rtx. */
9375 static int
9379 {
9388 {
9393 /* We're not interested in MEMs that are only clobbered. */
9397 /* We're not interested in the MEM associated with a
9398 CONST_DOUBLE, so there's no need to traverse into this. */
9402 /* We're not interested in any MEMs that only appear in notes. */
9406 /* This is not a MEM. */
9408 }
9410 /* See if we've already seen this MEM. */
9413 {
9415 /* The modes of the two memory accesses are different. If
9416 this happens, something tricky is going on, and we just
9417 don't optimize accesses to this MEM. */
9421 }
9423 /* Resize the array, if necessary. */
9425 {
9428 else
9434 }
9436 /* Actually insert the MEM. */
9438 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9439 because we can't put it in a register. We still store it in the
9440 table, though, so that if we see the same address later, but in a
9441 non-BLK mode, we'll not think we can optimize it at that point. */
9447 }
9450 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9452 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9453 register that is modified by an insn between FROM and TO. If the
9454 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9455 more, stop incrementing it, to avoid overflow.
9457 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9458 register I is used, if it is only used once. Otherwise, it is set
9459 to 0 (for no uses) or const0_rtx for more than one use. This
9460 parameter may be zero, in which case this processing is not done.
9462 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9463 optimize register I. */
9465 static void
9469 {
9472 /* last_set[n] is nonzero iff reg n has been set in the current
9473 basic block. In that case, it is the insn that last set reg n. */
9475 rtx insn;
9481 /* Grow the regs array if not allocated or too small. */
9483 {
9489 /* Zero the new elements. */
9492 }
9494 /* Clear previously scanned fields but do not clear n_times_set. */
9496 {
9500 }
9504 /* Scan the loop, recording register usage. */
9507 {
9509 {
9510 /* Record registers that have exactly one use. */
9513 /* Include uses in REG_EQUAL notes. */
9521 {
9525 last_set);
9526 }
9527 }
9531 }
9533 /* Invalidate all hard registers clobbered by calls. With one exception:
9534 a call-clobbered PIC register is still function-invariant for our
9535 purposes, since we can hoist any PIC calculations out of the loop.
9536 Thus the call to rtx_varies_p. */
9541 {
9544 }
9546 #ifdef AVOID_CCMODE_COPIES
9547 /* Don't try to move insns which set CC registers if we should not
9548 create CCmode register copies. */
9552 #endif
9554 /* Set regs->array[I].n_times_set for the new registers. */
9559 }
9561 /* Returns the number of real INSNs in the LOOP. */
9563 static int
9566 {
9568 rtx insn;
9576 }
9578 /* Move MEMs into registers for the duration of the loop. */
9580 static void
9583 {
9590 rtx end_label;
9591 /* Nonzero if the next instruction may never be executed. */
9598 /* We cannot use next_label here because it skips over normal insns. */
9603 /* Check to see if it's possible that some instructions in the loop are
9604 never executed. Also check if there is a goto out of the loop other
9605 than right after the end of the loop. */
9609 {
9613 /* If we enter the loop in the middle, and scan
9614 around to the beginning, don't set maybe_never
9615 for that. This must be an unconditional jump,
9616 otherwise the code at the top of the loop might
9617 never be executed. Unconditional jumps are
9618 followed a by barrier then loop end. */
9623 {
9624 /* If this is a jump outside of the loop but not right
9625 after the end of the loop, we would have to emit new fixup
9626 sequences for each such label. */
9628 JUMP_INSN is executed, we must be conservative. */
9637 /* Something complicated. */
9639 else
9640 /* If there are any more instructions in the loop, they
9641 might not be reached. */
9643 }
9646 }
9648 /* Find start of the extended basic block that enters the loop. */
9652 ;
9657 /* Build table of mems that get set to constant values before the
9658 loop. */
9662 /* Actually move the MEMs. */
9664 {
9665 regset_head load_copies;
9666 regset_head store_copies;
9668 rtx reg;
9670 rtx mem_list_entry;
9674 /* There's no telling whether or not MEM is modified. */
9677 /* Go through the MEMs written to in the loop to see if this
9678 one is aliased by one of them. */
9681 {
9686 {
9687 /* MEM is indeed aliased by this store. */
9690 }
9692 }
9698 /* If this MEM is written to, we must be sure that there
9699 are no reads from another MEM that aliases this one. */
9701 {
9705 {
9709 VOIDmode,
9711 rtx_varies_p))
9712 {
9713 /* It's not safe to hoist loop_info->mems[i] out of
9714 the loop because writes to it might not be
9715 seen by reads from loop_info->mems[j]. */
9718 }
9719 }
9720 }
9723 /* We can't access the MEM outside the loop; it might
9724 cause a trap that wouldn't have happened otherwise. */
9728 /* We thought we were going to lift this MEM out of the
9729 loop, but later discovered that we could not. */
9735 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9736 order to keep scan_loop from moving stores to this MEM
9737 out of the loop just because this REG is neither a
9738 user-variable nor used in the loop test. */
9743 /* Now, replace all references to the MEM with the
9744 corresponding pseudos. */
9749 {
9751 {
9752 rtx set;
9756 /* See if this copies the mem into a register that isn't
9757 modified afterwards. We'll try to do copy propagation
9758 a little further on. */
9760 /* @@@ This test is _way_ too conservative. */
9761 && ! maybe_never
9769 /* See if this copies the mem from a register that isn't
9770 modified afterwards. We'll try to remove the
9771 redundant copy later on by doing a little register
9772 renaming and copy propagation. This will help
9773 to untangle things for the BIV detection code. */
9775 && ! maybe_never
9783 /* Replace the memory reference with the shadow register. */
9786 }
9791 }
9794 /* We couldn't replace all occurrences of the MEM. */
9796 else
9797 {
9798 /* Load the memory immediately before LOOP->START, which is
9799 the NOTE_LOOP_BEG. */
9801 rtx set;
9807 {
9811 {
9815 /* Extending hard register lifetimes causes crash
9816 on SRC targets. Doing so on non-SRC is
9817 probably also not good idea, since we most
9818 probably have pseudoregister equivalence as
9819 well. */
9822 }
9823 /* Use the constant equivalence if that is cheap enough. */
9829 {
9832 }
9834 /* If best_equiv is nonzero, we know that MEM is set to a
9835 constant or register before the loop. We will use this
9836 knowledge to initialize the shadow register with that
9837 constant or reg rather than by loading from MEM. */
9840 }
9845 {
9848 {
9851 }
9852 }
9858 {
9860 {
9863 }
9865 /* Store the memory immediately after END, which is
9866 the NOTE_LOOP_END. */
9869 }
9872 {
9877 }
9879 /* Attempt a bit of copy propagation. This helps untangle the
9880 data flow, and enables {basic,general}_induction_var to find
9881 more bivs/givs. */
9882 EXECUTE_IF_SET_IN_REG_SET
9884 {
9886 });
9889 EXECUTE_IF_SET_IN_REG_SET
9891 {
9893 });
9895 }
9896 }
9899 {
9900 /* Now, we need to replace all references to the previous exit
9901 label with the new one. */
9902 rtx_pair rr;
9907 {
9910 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9911 field. This is not handled by for_each_rtx because it doesn't
9912 handle unprinted ('0') fields. We need to update JUMP_LABEL
9913 because the immediately following unroll pass will use it.
9914 replace_label would not work anyways, because that only handles
9915 LABEL_REFs. */
9918 }
9919 }
9922 }
9924 /* For communication between note_reg_stored and its caller. */
9925 struct note_reg_stored_arg
9926 {
9928 rtx reg;
9929 };
9931 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9932 is equal to ARG. */
9933 static void
9937 {
9941 }
9943 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9944 There must be exactly one insn that sets this pseudo; it will be
9945 deleted if all replacements succeed and we can prove that the register
9946 is not used after the loop. */
9948 static void
9951 rtx replacement;
9953 {
9954 /* This is the reg that we are copying from. */
9957 rtx insn;
9958 /* These help keep track of whether we replaced all uses of the reg. */
9965 {
9966 rtx set;
9968 /* Only substitute within one extended basic block from the initializing
9969 insn. */
9976 /* Is this the initializing insn? */
9981 {
9988 }
9990 /* Only substitute after seeing the initializing insn. */
9992 {
9999 /* Stop replacing when REPLACEMENT is modified. */
10004 {
10007 /* It is possible that we've turned previously valid REG_EQUAL to
10008 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10009 REPLACEMENT is modified, we get different meaning. */
10013 }
10014 }
10015 }
10019 {
10023 {
10024 rtx first;
10025 rtx retval_note;
10027 /* Assume we're just deleting INIT_INSN. */
10029 /* Look for REG_RETVAL note. If we're deleting the end of
10030 the libcall sequence, the whole sequence can go. */
10032 /* If we found a REG_RETVAL note, find the first instruction
10033 in the sequence. */
10037 /* Delete the instructions. */
10039 }
10042 }
10043 }
10045 /* Replace all the instructions from FIRST up to and including LAST
10046 with NOTE_INSN_DELETED notes. */
10048 static void
10050 rtx first;
10051 rtx last;
10052 {
10054 {
10060 /* If this was the LAST instructions we're supposed to delete,
10061 we're done. */
10066 }
10067 }
10069 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10070 loop LOOP if the order of the sets of these registers can be
10071 swapped. There must be exactly one insn within the loop that sets
10072 this pseudo followed immediately by a move insn that sets
10073 REPLACEMENT with REGNO. */
10074 static void
10077 rtx replacement;
10079 {
10080 rtx insn;
10089 {
10090 /* Search for the insn that copies REGNO to NEW_REGNO? */
10098 }
10101 {
10102 rtx prev_insn;
10103 rtx prev_set;
10105 /* Some DEF-USE info would come in handy here to make this
10106 function more general. For now, just check the previous insn
10107 which is the most likely candidate for setting REGNO. */
10115 {
10116 /* We have:
10117 (set (reg regno) (expr))
10118 (set (reg new_regno) (reg regno))
10120 so try converting this to:
10121 (set (reg new_regno) (expr))
10122 (set (reg regno) (reg new_regno))
10124 The former construct is often generated when a global
10125 variable used for an induction variable is shadowed by a
10126 register (NEW_REGNO). The latter construct improves the
10127 chances of GIV replacement and BIV elimination. */
10137 {
10144 /* Update first use of REGNO. */
10148 /* Now perform copy propagation to hopefully
10149 remove all uses of REGNO within the loop. */
10151 }
10152 }
10153 }
10154 }
10156 /* Replace MEM with its associated pseudo register. This function is
10157 called from load_mems via for_each_rtx. DATA is actually a pointer
10158 to a structure describing the instruction currently being scanned
10159 and the MEM we are currently replacing. */
10161 static int
10165 {
10173 {
10178 /* We're not interested in the MEM associated with a
10179 CONST_DOUBLE, so there's no need to traverse into one. */
10183 /* This is not a MEM. */
10185 }
10188 /* This is not the MEM we are currently replacing. */
10191 /* Actually replace the MEM. */
10195 }
10197 static void
10199 rtx insn;
10200 rtx mem;
10201 rtx reg;
10202 {
10203 loop_replace_args args;
10210 }
10212 /* Replace one register with another. Called through for_each_rtx; PX points
10213 to the rtx being scanned. DATA is actually a pointer to
10214 a structure of arguments. */
10216 static int
10220 {
10231 }
10233 static void
10235 rtx insn;
10236 rtx reg;
10237 rtx replacement;
10238 {
10239 loop_replace_args args;
10246 }
10248 /* Replace occurrences of the old exit label for the loop with the new
10249 one. DATA is an rtx_pair containing the old and new labels,
10250 respectively. */
10252 static int
10256 {
10275 }
10276 \f
10277 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10278 (ignored in the interim). */
10280 static rtx
10283 basic_block where_bb ATTRIBUTE_UNUSED;
10284 rtx where_insn;
10285 rtx pattern;
10286 {
10288 }
10291 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10292 in basic block WHERE_BB (ignored in the interim) within the loop
10293 otherwise hoist PATTERN into the loop pre-header. */
10295 rtx
10298 basic_block where_bb ATTRIBUTE_UNUSED;
10299 rtx where_insn;
10300 rtx pattern;
10301 {
10305 }
10308 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10309 WHERE_BB (ignored in the interim) within the loop. */
10311 static rtx
10314 basic_block where_bb ATTRIBUTE_UNUSED;
10315 rtx where_insn;
10316 rtx pattern;
10317 {
10319 }
10322 /* Hoist insn for PATTERN into the loop pre-header. */
10324 rtx
10327 rtx pattern;
10328 {
10330 }
10333 /* Hoist call insn for PATTERN into the loop pre-header. */
10335 static rtx
10338 rtx pattern;
10339 {
10341 }
10344 /* Sink insn for PATTERN after the loop end. */
10346 rtx
10349 rtx pattern;
10350 {
10352 }
10355 /* If the loop has multiple exits, emit insn for PATTERN before the
10356 loop to ensure that it will always be executed no matter how the
10357 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10358 since this is slightly more efficient. */
10360 static rtx
10363 rtx pattern;
10364 {
10367 else
10369 }
10370 \f
10371 static void
10376 {
10384 iv_num++;
10389 {
10392 }
10393 }
10396 static void
10401 {
10403 rtx incr;
10414 {
10417 }
10419 {
10422 }
10426 {
10430 }
10433 {
10437 }
10439 /* List the increments. */
10441 {
10445 }
10447 /* List the givs. */
10449 {
10454 else
10457 }
10458 }
10461 static void
10466 {
10477 {
10481 }
10484 }
10487 static void
10492 {
10499 else
10515 {
10517 {
10529 }
10530 }
10541 {
10545 }
10548 }
10551 void
10554 {
10556 }
10559 void
10562 {
10564 }
10567 void
10570 {
10572 }
10575 void
10578 {
10580 }
10583 #define LOOP_BLOCK_NUM_1(INSN) \
10584 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10586 /* The notes do not have an assigned block, so look at the next insn. */
10587 #define LOOP_BLOCK_NUM(INSN) \
10588 ((INSN) ? (GET_CODE (INSN) == NOTE \
10589 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10590 : LOOP_BLOCK_NUM_1 (INSN)) \
10591 : -1)
10593 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10595 static void
10600 {
10601 rtx label;
10606 /* Print diagnostics to compare our concept of a loop with
10607 what the loop notes say. */
10622 {
10642 {
10645 {
10648 }
10649 }
10652 /* This can happen when a marked loop appears as two nested loops,
10653 say from while (a || b) {}. The inner loop won't match
10654 the loop markers but the outer one will. */
10657 }
10658 }
10660 /* Call this function from the debugger to dump LOOP. */
10662 void
10665 {
10667 }
10669 /* Call this function from the debugger to dump LOOPS. */
10671 void
10674 {
10676 }