1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(x, y) 2
48 static void init_reg_sets_1
PARAMS ((void));
49 static void init_reg_modes
PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set
;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set
;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set
;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set
;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs
;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs
[FIRST_PSEUDO_REGISTER
];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order
[FIRST_PSEUDO_REGISTER
];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
139 = REG_CLASS_CONTENTS
;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size
[N_REG_CLASSES
];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
163 /* Array containing all of the register names */
165 const char *reg_names
[] = REGISTER_NAMES
;
167 /* For each hard register, the widest mode object that it can contain.
168 This will be a MODE_INT mode if the register can hold integers. Otherwise
169 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
172 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
174 /* Maximum cost of moving from a register in one class to a register in
175 another class. Based on REGISTER_MOVE_COST. */
177 static int move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
179 /* Similar, but here we don't have to move if the first index is a subset
180 of the second so in that case the cost is zero. */
182 static int may_move_in_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
184 /* Similar, but here we don't have to move if the first index is a superset
185 of the second so in that case the cost is zero. */
187 static int may_move_out_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
189 #ifdef FORBIDDEN_INC_DEC_CLASSES
191 /* These are the classes that regs which are auto-incremented or decremented
194 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
196 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
199 static char *in_inc_dec
;
201 #endif /* FORBIDDEN_INC_DEC_CLASSES */
203 #ifdef HAVE_SECONDARY_RELOADS
205 /* Sample MEM values for use by memory_move_secondary_cost. */
207 static rtx top_of_stack
[MAX_MACHINE_MODE
];
209 #endif /* HAVE_SECONDARY_RELOADS */
211 /* Linked list of reg_info structures allocated for reg_n_info array.
212 Grouping all of the allocated structures together in one lump
213 means only one call to bzero to clear them, rather than n smaller
215 struct reg_info_data
{
216 struct reg_info_data
*next
; /* next set of reg_info structures */
217 size_t min_index
; /* minimum index # */
218 size_t max_index
; /* maximum index # */
219 char used_p
; /* non-zero if this has been used previously */
220 reg_info data
[1]; /* beginning of the reg_info data */
223 static struct reg_info_data
*reg_info_head
;
225 /* No more global register variables may be declared; true once
226 regclass has been initialized. */
228 static int no_global_reg_vars
= 0;
231 /* Function called only once to initialize the above data on reg usage.
232 Once this is done, various switches may override. */
239 /* First copy the register information from the initial int form into
242 for (i
= 0; i
< N_REG_CLASSES
; i
++)
244 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
246 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
247 if (int_reg_class_contents
[i
][j
/ HOST_BITS_PER_INT
]
248 & ((unsigned) 1 << (j
% HOST_BITS_PER_INT
)))
249 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
252 bcopy (initial_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
253 bcopy (initial_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
254 bzero (global_regs
, sizeof global_regs
);
256 /* Do any additional initialization regsets may need */
257 INIT_ONCE_REG_SET ();
259 #ifdef REG_ALLOC_ORDER
260 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
261 inv_reg_alloc_order
[reg_alloc_order
[i
]] = i
;
265 /* After switches have been processed, which perhaps alter
266 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
271 register unsigned int i
, j
;
273 /* This macro allows the fixed or call-used registers
274 and the register classes to depend on target flags. */
276 #ifdef CONDITIONAL_REGISTER_USAGE
277 CONDITIONAL_REGISTER_USAGE
;
280 /* Compute number of hard regs in each class. */
282 bzero ((char *) reg_class_size
, sizeof reg_class_size
);
283 for (i
= 0; i
< N_REG_CLASSES
; i
++)
284 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
285 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
288 /* Initialize the table of subunions.
289 reg_class_subunion[I][J] gets the largest-numbered reg-class
290 that is contained in the union of classes I and J. */
292 for (i
= 0; i
< N_REG_CLASSES
; i
++)
294 for (j
= 0; j
< N_REG_CLASSES
; j
++)
297 register /* Declare it register if it's a scalar. */
302 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
303 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
304 for (k
= 0; k
< N_REG_CLASSES
; k
++)
306 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
311 /* keep the largest subclass */ /* SPEE 900308 */
312 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
313 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
315 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
322 /* Initialize the table of superunions.
323 reg_class_superunion[I][J] gets the smallest-numbered reg-class
324 containing the union of classes I and J. */
326 for (i
= 0; i
< N_REG_CLASSES
; i
++)
328 for (j
= 0; j
< N_REG_CLASSES
; j
++)
331 register /* Declare it register if it's a scalar. */
336 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
337 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
338 for (k
= 0; k
< N_REG_CLASSES
; k
++)
339 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
342 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
346 /* Initialize the tables of subclasses and superclasses of each reg class.
347 First clear the whole table, then add the elements as they are found. */
349 for (i
= 0; i
< N_REG_CLASSES
; i
++)
351 for (j
= 0; j
< N_REG_CLASSES
; j
++)
353 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
354 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
358 for (i
= 0; i
< N_REG_CLASSES
; i
++)
360 if (i
== (int) NO_REGS
)
363 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
367 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
371 /* Reg class I is a subclass of J.
372 Add J to the table of superclasses of I. */
373 p
= ®_class_superclasses
[i
][0];
374 while (*p
!= LIM_REG_CLASSES
) p
++;
375 *p
= (enum reg_class
) j
;
376 /* Add I to the table of superclasses of J. */
377 p
= ®_class_subclasses
[j
][0];
378 while (*p
!= LIM_REG_CLASSES
) p
++;
379 *p
= (enum reg_class
) i
;
383 /* Initialize "constant" tables. */
385 CLEAR_HARD_REG_SET (fixed_reg_set
);
386 CLEAR_HARD_REG_SET (call_used_reg_set
);
387 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
389 bcopy (fixed_regs
, call_fixed_regs
, sizeof call_fixed_regs
);
391 n_non_fixed_regs
= 0;
393 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
396 SET_HARD_REG_BIT (fixed_reg_set
, i
);
400 if (call_used_regs
[i
])
401 SET_HARD_REG_BIT (call_used_reg_set
, i
);
402 if (call_fixed_regs
[i
])
403 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
404 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
405 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
408 /* Initialize the move cost table. Find every subset of each class
409 and take the maximum cost of moving any subset to any other. */
411 for (i
= 0; i
< N_REG_CLASSES
; i
++)
412 for (j
= 0; j
< N_REG_CLASSES
; j
++)
414 int cost
= i
== j
? 2 : REGISTER_MOVE_COST (i
, j
);
415 enum reg_class
*p1
, *p2
;
417 for (p2
= ®_class_subclasses
[j
][0]; *p2
!= LIM_REG_CLASSES
; p2
++)
419 cost
= MAX (cost
, REGISTER_MOVE_COST (i
, *p2
));
421 for (p1
= ®_class_subclasses
[i
][0]; *p1
!= LIM_REG_CLASSES
; p1
++)
424 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, j
));
426 for (p2
= ®_class_subclasses
[j
][0];
427 *p2
!= LIM_REG_CLASSES
; p2
++)
429 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, *p2
));
432 move_cost
[i
][j
] = cost
;
434 if (reg_class_subset_p (i
, j
))
435 may_move_in_cost
[i
][j
] = 0;
437 may_move_in_cost
[i
][j
] = cost
;
439 if (reg_class_subset_p (j
, i
))
440 may_move_out_cost
[i
][j
] = 0;
442 may_move_out_cost
[i
][j
] = cost
;
446 /* Compute the table of register modes.
447 These values are used to record death information for individual registers
448 (as opposed to a multi-register mode). */
455 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
457 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1);
459 /* If we couldn't find a valid mode, just use the previous mode.
460 ??? One situation in which we need to do this is on the mips where
461 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
462 to use DF mode for the even registers and VOIDmode for the odd
463 (for the cpu models where the odd ones are inaccessible). */
464 if (reg_raw_mode
[i
] == VOIDmode
)
465 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
469 /* Finish initializing the register sets and
470 initialize the register modes. */
475 /* This finishes what was started by init_reg_sets, but couldn't be done
476 until after register usage was specified. */
481 #ifdef HAVE_SECONDARY_RELOADS
483 /* Make some fake stack-frame MEM references for use in
484 memory_move_secondary_cost. */
486 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
487 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
488 ggc_add_rtx_root (top_of_stack
, MAX_MACHINE_MODE
);
493 #ifdef HAVE_SECONDARY_RELOADS
495 /* Compute extra cost of moving registers to/from memory due to reloads.
496 Only needed if secondary reloads are required for memory moves. */
499 memory_move_secondary_cost (mode
, class, in
)
500 enum machine_mode mode
;
501 enum reg_class
class;
504 enum reg_class altclass
;
505 int partial_cost
= 0;
506 /* We need a memory reference to feed to SECONDARY... macros. */
507 /* mem may be unused even if the SECONDARY_ macros are defined. */
508 rtx mem ATTRIBUTE_UNUSED
= top_of_stack
[(int) mode
];
513 #ifdef SECONDARY_INPUT_RELOAD_CLASS
514 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
521 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
522 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
528 if (altclass
== NO_REGS
)
532 partial_cost
= REGISTER_MOVE_COST (altclass
, class);
534 partial_cost
= REGISTER_MOVE_COST (class, altclass
);
536 if (class == altclass
)
537 /* This isn't simply a copy-to-temporary situation. Can't guess
538 what it is, so MEMORY_MOVE_COST really ought not to be calling
541 I'm tempted to put in an abort here, but returning this will
542 probably only give poor estimates, which is what we would've
543 had before this code anyways. */
546 /* Check if the secondary reload register will also need a
548 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
552 /* Return a machine mode that is legitimate for hard reg REGNO and large
553 enough to save nregs. If we can't find one, return VOIDmode. */
556 choose_hard_reg_mode (regno
, nregs
)
557 unsigned int regno ATTRIBUTE_UNUSED
;
560 enum machine_mode found_mode
= VOIDmode
, mode
;
562 /* We first look for the largest integer mode that can be validly
563 held in REGNO. If none, we look for the largest floating-point mode.
564 If we still didn't find a valid mode, try CCmode. */
566 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
568 mode
= GET_MODE_WIDER_MODE (mode
))
569 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
570 && HARD_REGNO_MODE_OK (regno
, mode
))
573 if (found_mode
!= VOIDmode
)
576 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
578 mode
= GET_MODE_WIDER_MODE (mode
))
579 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
580 && HARD_REGNO_MODE_OK (regno
, mode
))
583 if (found_mode
!= VOIDmode
)
586 if (HARD_REGNO_NREGS (regno
, CCmode
) == nregs
587 && HARD_REGNO_MODE_OK (regno
, CCmode
))
590 /* We can't find a mode valid for this register. */
594 /* Specify the usage characteristics of the register named NAME.
595 It should be a fixed register if FIXED and a
596 call-used register if CALL_USED. */
599 fix_register (name
, fixed
, call_used
)
601 int fixed
, call_used
;
605 /* Decode the name and update the primary form of
606 the register info. */
608 if ((i
= decode_reg_name (name
)) >= 0)
610 if ((i
== STACK_POINTER_REGNUM
611 #ifdef HARD_FRAME_POINTER_REGNUM
612 || i
== HARD_FRAME_POINTER_REGNUM
614 || i
== FRAME_POINTER_REGNUM
617 && (fixed
== 0 || call_used
== 0))
619 static const char * const what_option
[2][2] = {
620 { "call-saved", "call-used" },
621 { "no-such-option", "fixed" }};
623 error ("can't use '%s' as a %s register", name
,
624 what_option
[fixed
][call_used
]);
628 fixed_regs
[i
] = fixed
;
629 call_used_regs
[i
] = call_used
;
634 warning ("unknown register name: %s", name
);
638 /* Mark register number I as global. */
644 if (fixed_regs
[i
] == 0 && no_global_reg_vars
)
645 error ("global register variable follows a function definition");
649 warning ("register used for two global register variables");
653 if (call_used_regs
[i
] && ! fixed_regs
[i
])
654 warning ("call-clobbered register used for global register variable");
658 /* If already fixed, nothing else to do. */
662 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
665 SET_HARD_REG_BIT (fixed_reg_set
, i
);
666 SET_HARD_REG_BIT (call_used_reg_set
, i
);
667 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
670 /* Now the data and code for the `regclass' pass, which happens
671 just before local-alloc. */
673 /* The `costs' struct records the cost of using a hard register of each class
674 and of using memory for each pseudo. We use this data to set up
675 register class preferences. */
679 int cost
[N_REG_CLASSES
];
683 /* Structure used to record preferrences of given pseudo. */
686 /* (enum reg_class) prefclass is the preferred class. */
689 /* altclass is a register class that we should use for allocating
690 pseudo if no register in the preferred class is available.
691 If no register in this class is available, memory is preferred.
693 It might appear to be more general to have a bitmask of classes here,
694 but since it is recommended that there be a class corresponding to the
695 union of most major pair of classes, that generality is not required. */
699 /* Record the cost of each class for each pseudo. */
701 static struct costs
*costs
;
703 /* Initialized once, and used to initialize cost values for each insn. */
705 static struct costs init_cost
;
707 /* Record preferrences of each pseudo.
708 This is available after `regclass' is run. */
710 static struct reg_pref
*reg_pref
;
712 /* Allocated buffers for reg_pref. */
714 static struct reg_pref
*reg_pref_buffer
;
716 /* Account for the fact that insns within a loop are executed very commonly,
717 but don't keep doing this as loops go too deep. */
719 static int loop_cost
;
721 static rtx scan_one_insn
PARAMS ((rtx
, int));
722 static void record_operand_costs
PARAMS ((rtx
, struct costs
*, struct reg_pref
*));
723 static void dump_regclass
PARAMS ((FILE *));
724 static void record_reg_classes
PARAMS ((int, int, rtx
*, enum machine_mode
*,
725 char *, const char **, rtx
,
726 struct costs
*, struct reg_pref
*));
727 static int copy_cost
PARAMS ((rtx
, enum machine_mode
,
728 enum reg_class
, int));
729 static void record_address_regs
PARAMS ((rtx
, enum reg_class
, int));
730 #ifdef FORBIDDEN_INC_DEC_CLASSES
731 static int auto_inc_dec_reg_p
PARAMS ((rtx
, enum machine_mode
));
733 static void reg_scan_mark_refs
PARAMS ((rtx
, rtx
, int, unsigned int));
735 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
736 This function is sometimes called before the info has been computed.
737 When that happens, just return GENERAL_REGS, which is innocuous. */
740 reg_preferred_class (regno
)
745 return (enum reg_class
) reg_pref
[regno
].prefclass
;
749 reg_alternate_class (regno
)
755 return (enum reg_class
) reg_pref
[regno
].altclass
;
758 /* Initialize some global data for this pass. */
765 init_cost
.mem_cost
= 10000;
766 for (i
= 0; i
< N_REG_CLASSES
; i
++)
767 init_cost
.cost
[i
] = 10000;
769 /* This prevents dump_flow_info from losing if called
770 before regclass is run. */
773 /* No more global register variables may be declared. */
774 no_global_reg_vars
= 1;
777 /* Dump register costs. */
782 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
784 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
786 enum reg_class
class;
789 fprintf (dump
, " Register %i costs:", i
);
790 for (class = 0; class < N_REG_CLASSES
; class++)
791 fprintf (dump
, " %s:%i", reg_class_names
[(int) class],
792 costs
[i
].cost
[class]);
793 fprintf (dump
, " MEM:%i\n", costs
[i
].mem_cost
);
799 /* Calculate the costs of insn operands. */
802 record_operand_costs (insn
, op_costs
, reg_pref
)
804 struct costs
*op_costs
;
805 struct reg_pref
*reg_pref
;
807 const char *constraints
[MAX_RECOG_OPERANDS
];
808 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
809 char subreg_changes_size
[MAX_RECOG_OPERANDS
];
812 for (i
= 0; i
< recog_data
.n_operands
; i
++)
814 constraints
[i
] = recog_data
.constraints
[i
];
815 modes
[i
] = recog_data
.operand_mode
[i
];
817 memset (subreg_changes_size
, 0, sizeof (subreg_changes_size
));
819 /* If we get here, we are set up to record the costs of all the
820 operands for this insn. Start by initializing the costs.
821 Then handle any address registers. Finally record the desired
822 classes for any pseudos, doing it twice if some pair of
823 operands are commutative. */
825 for (i
= 0; i
< recog_data
.n_operands
; i
++)
827 op_costs
[i
] = init_cost
;
829 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
831 rtx inner
= SUBREG_REG (recog_data
.operand
[i
]);
832 if (GET_MODE_SIZE (modes
[i
]) != GET_MODE_SIZE (GET_MODE (inner
)))
833 subreg_changes_size
[i
] = 1;
834 recog_data
.operand
[i
] = inner
;
837 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
838 record_address_regs (XEXP (recog_data
.operand
[i
], 0),
839 BASE_REG_CLASS
, loop_cost
* 2);
840 else if (constraints
[i
][0] == 'p')
841 record_address_regs (recog_data
.operand
[i
],
842 BASE_REG_CLASS
, loop_cost
* 2);
845 /* Check for commutative in a separate loop so everything will
846 have been initialized. We must do this even if one operand
847 is a constant--see addsi3 in m68k.md. */
849 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
850 if (constraints
[i
][0] == '%')
852 const char *xconstraints
[MAX_RECOG_OPERANDS
];
855 /* Handle commutative operands by swapping the constraints.
856 We assume the modes are the same. */
858 for (j
= 0; j
< recog_data
.n_operands
; j
++)
859 xconstraints
[j
] = constraints
[j
];
861 xconstraints
[i
] = constraints
[i
+1];
862 xconstraints
[i
+1] = constraints
[i
];
863 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
864 recog_data
.operand
, modes
, subreg_changes_size
,
865 xconstraints
, insn
, op_costs
, reg_pref
);
868 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
869 recog_data
.operand
, modes
, subreg_changes_size
,
870 constraints
, insn
, op_costs
, reg_pref
);
873 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
874 time it would save code to put a certain register in a certain class.
875 PASS, when nonzero, inhibits some optimizations which need only be done
877 Return the last insn processed, so that the scan can be continued from
881 scan_one_insn (insn
, pass
)
885 enum rtx_code code
= GET_CODE (insn
);
886 enum rtx_code pat_code
;
889 struct costs op_costs
[MAX_RECOG_OPERANDS
];
891 if (GET_RTX_CLASS (code
) != 'i')
894 pat_code
= GET_CODE (PATTERN (insn
));
896 || pat_code
== CLOBBER
897 || pat_code
== ASM_INPUT
898 || pat_code
== ADDR_VEC
899 || pat_code
== ADDR_DIFF_VEC
)
902 set
= single_set (insn
);
905 /* If this insn loads a parameter from its stack slot, then
906 it represents a savings, rather than a cost, if the
907 parameter is stored in memory. Record this fact. */
909 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
910 && GET_CODE (SET_SRC (set
)) == MEM
911 && (note
= find_reg_note (insn
, REG_EQUIV
,
913 && GET_CODE (XEXP (note
, 0)) == MEM
)
915 costs
[REGNO (SET_DEST (set
))].mem_cost
916 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
919 record_address_regs (XEXP (SET_SRC (set
), 0),
920 BASE_REG_CLASS
, loop_cost
* 2);
924 /* Improve handling of two-address insns such as
925 (set X (ashift CONST Y)) where CONST must be made to
926 match X. Change it into two insns: (set X CONST)
927 (set X (ashift X Y)). If we left this for reloading, it
928 would probably get three insns because X and Y might go
929 in the same place. This prevents X and Y from receiving
932 We can only do this if the modes of operands 0 and 1
933 (which might not be the same) are tieable and we only need
934 do this during our first pass. */
936 if (pass
== 0 && optimize
937 && recog_data
.n_operands
>= 3
938 && recog_data
.constraints
[1][0] == '0'
939 && recog_data
.constraints
[1][1] == 0
940 && CONSTANT_P (recog_data
.operand
[1])
941 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
942 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
943 && GET_CODE (recog_data
.operand
[0]) == REG
944 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
945 recog_data
.operand_mode
[1]))
947 rtx previnsn
= prev_real_insn (insn
);
949 = gen_lowpart (recog_data
.operand_mode
[1],
950 recog_data
.operand
[0]);
952 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
954 /* If this insn was the start of a basic block,
955 include the new insn in that block.
956 We need not check for code_label here;
957 while a basic block can start with a code_label,
958 INSN could not be at the beginning of that block. */
959 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
962 for (b
= 0; b
< n_basic_blocks
; b
++)
963 if (insn
== BLOCK_HEAD (b
))
964 BLOCK_HEAD (b
) = newinsn
;
967 /* This makes one more setting of new insns's dest. */
968 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
970 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
971 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
972 if (recog_data
.dup_num
[i
] == 1)
973 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
975 return PREV_INSN (newinsn
);
978 record_operand_costs (insn
, op_costs
, reg_pref
);
980 /* Now add the cost for each operand to the total costs for
983 for (i
= 0; i
< recog_data
.n_operands
; i
++)
984 if (GET_CODE (recog_data
.operand
[i
]) == REG
985 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
987 int regno
= REGNO (recog_data
.operand
[i
]);
988 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
990 p
->mem_cost
+= q
->mem_cost
* loop_cost
;
991 for (j
= 0; j
< N_REG_CLASSES
; j
++)
992 p
->cost
[j
] += q
->cost
[j
] * loop_cost
;
998 /* This is a pass of the compiler that scans all instructions
999 and calculates the preferred class for each pseudo-register.
1000 This information can be accessed later by calling `reg_preferred_class'.
1001 This pass comes just before local register allocation. */
1004 regclass (f
, nregs
, dump
)
1015 costs
= (struct costs
*) xmalloc (nregs
* sizeof (struct costs
));
1017 #ifdef FORBIDDEN_INC_DEC_CLASSES
1019 in_inc_dec
= (char *) xmalloc (nregs
);
1021 /* Initialize information about which register classes can be used for
1022 pseudos that are auto-incremented or auto-decremented. It would
1023 seem better to put this in init_reg_sets, but we need to be able
1024 to allocate rtx, which we can't do that early. */
1026 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1028 rtx r
= gen_rtx_REG (VOIDmode
, 0);
1029 enum machine_mode m
;
1032 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1033 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
1037 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
1038 m
= (enum machine_mode
) ((int) m
+ 1))
1039 if (HARD_REGNO_MODE_OK (j
, m
))
1043 /* If a register is not directly suitable for an
1044 auto-increment or decrement addressing mode and
1045 requires secondary reloads, disallow its class from
1046 being used in such addresses. */
1049 #ifdef SECONDARY_RELOAD_CLASS
1050 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1053 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1054 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1057 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1058 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1063 && ! auto_inc_dec_reg_p (r
, m
))
1064 forbidden_inc_dec_class
[i
] = 1;
1068 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1070 /* Normally we scan the insns once and determine the best class to use for
1071 each register. However, if -fexpensive_optimizations are on, we do so
1072 twice, the second time using the tentative best classes to guide the
1075 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1080 fprintf (dump
, "\n\nPass %i\n\n",pass
);
1081 /* Zero out our accumulation of the cost of each class for each reg. */
1083 bzero ((char *) costs
, nregs
* sizeof (struct costs
));
1085 #ifdef FORBIDDEN_INC_DEC_CLASSES
1086 bzero (in_inc_dec
, nregs
);
1089 /* Scan the instructions and record each time it would
1090 save code to put a certain register in a certain class. */
1095 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1096 insn
= scan_one_insn (insn
, pass
);
1099 for (index
= 0; index
< n_basic_blocks
; index
++)
1101 basic_block bb
= BASIC_BLOCK (index
);
1103 /* Show that an insn inside a loop is likely to be executed three
1104 times more than insns outside a loop. This is much more
1105 aggressive than the assumptions made elsewhere and is being
1106 tried as an experiment. */
1110 loop_cost
= 1 << (2 * MIN (bb
->loop_depth
, 5));
1111 for (insn
= bb
->head
; ; insn
= NEXT_INSN (insn
))
1113 insn
= scan_one_insn (insn
, pass
);
1114 if (insn
== bb
->end
)
1119 /* Now for each register look at how desirable each class is
1120 and find which class is preferred. Store that in
1121 `prefclass'. Record in `altclass' the largest register
1122 class any of whose registers is better than memory. */
1125 reg_pref
= reg_pref_buffer
;
1129 dump_regclass (dump
);
1130 fprintf (dump
,"\n");
1132 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1134 register int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1135 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1136 /* This is an enum reg_class, but we call it an int
1137 to save lots of casts. */
1139 register struct costs
*p
= &costs
[i
];
1141 /* In non-optimizing compilation REG_N_REFS is not initialized
1143 if (optimize
&& !REG_N_REFS (i
))
1146 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1148 /* Ignore classes that are too small for this operand or
1149 invalid for a operand that was auto-incremented. */
1150 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i
))
1151 > reg_class_size
[class]
1152 #ifdef FORBIDDEN_INC_DEC_CLASSES
1153 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1157 else if (p
->cost
[class] < best_cost
)
1159 best_cost
= p
->cost
[class];
1160 best
= (enum reg_class
) class;
1162 else if (p
->cost
[class] == best_cost
)
1163 best
= reg_class_subunion
[(int)best
][class];
1166 /* Record the alternate register class; i.e., a class for which
1167 every register in it is better than using memory. If adding a
1168 class would make a smaller class (i.e., no union of just those
1169 classes exists), skip that class. The major unions of classes
1170 should be provided as a register class. Don't do this if we
1171 will be doing it again later. */
1173 if ((pass
== 1 || dump
) || ! flag_expensive_optimizations
)
1174 for (class = 0; class < N_REG_CLASSES
; class++)
1175 if (p
->cost
[class] < p
->mem_cost
1176 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1177 > reg_class_size
[(int) alt
])
1178 #ifdef FORBIDDEN_INC_DEC_CLASSES
1179 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1182 alt
= reg_class_subunion
[(int) alt
][class];
1184 /* If we don't add any classes, nothing to try. */
1189 && (reg_pref
[i
].prefclass
!= (int) best
1190 || reg_pref
[i
].altclass
!= (int) alt
))
1192 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1193 fprintf (dump
, " Register %i", i
);
1194 if (alt
== ALL_REGS
|| best
== ALL_REGS
)
1195 fprintf (dump
, " pref %s\n", reg_class_names
[(int) best
]);
1196 else if (alt
== NO_REGS
)
1197 fprintf (dump
, " pref %s or none\n", reg_class_names
[(int) best
]);
1199 fprintf (dump
, " pref %s, else %s\n",
1200 reg_class_names
[(int) best
],
1201 reg_class_names
[(int) alt
]);
1204 /* We cast to (int) because (char) hits bugs in some compilers. */
1205 reg_pref
[i
].prefclass
= (int) best
;
1206 reg_pref
[i
].altclass
= (int) alt
;
1210 #ifdef FORBIDDEN_INC_DEC_CLASSES
1216 /* Record the cost of using memory or registers of various classes for
1217 the operands in INSN.
1219 N_ALTS is the number of alternatives.
1221 N_OPS is the number of operands.
1223 OPS is an array of the operands.
1225 MODES are the modes of the operands, in case any are VOIDmode.
1227 CONSTRAINTS are the constraints to use for the operands. This array
1228 is modified by this procedure.
1230 This procedure works alternative by alternative. For each alternative
1231 we assume that we will be able to allocate all pseudos to their ideal
1232 register class and calculate the cost of using that alternative. Then
1233 we compute for each operand that is a pseudo-register, the cost of
1234 having the pseudo allocated to each register class and using it in that
1235 alternative. To this cost is added the cost of the alternative.
1237 The cost of each class for this insn is its lowest cost among all the
1241 record_reg_classes (n_alts
, n_ops
, ops
, modes
, subreg_changes_size
,
1242 constraints
, insn
, op_costs
, reg_pref
)
1246 enum machine_mode
*modes
;
1247 char *subreg_changes_size ATTRIBUTE_UNUSED
;
1248 const char **constraints
;
1250 struct costs
*op_costs
;
1251 struct reg_pref
*reg_pref
;
1257 /* Process each alternative, each time minimizing an operand's cost with
1258 the cost for each operand in that alternative. */
1260 for (alt
= 0; alt
< n_alts
; alt
++)
1262 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1265 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1266 int allows_mem
[MAX_RECOG_OPERANDS
];
1269 for (i
= 0; i
< n_ops
; i
++)
1271 const char *p
= constraints
[i
];
1273 enum machine_mode mode
= modes
[i
];
1274 int allows_addr
= 0;
1278 /* Initially show we know nothing about the register class. */
1279 classes
[i
] = NO_REGS
;
1282 /* If this operand has no constraints at all, we can conclude
1283 nothing about it since anything is valid. */
1287 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1288 bzero ((char *) &this_op_costs
[i
], sizeof this_op_costs
[i
]);
1293 /* If this alternative is only relevant when this operand
1294 matches a previous operand, we do different things depending
1295 on whether this operand is a pseudo-reg or not. We must process
1296 any modifiers for the operand before we can make this test. */
1298 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1301 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1303 /* Copy class and whether memory is allowed from the matching
1304 alternative. Then perform any needed cost computations
1305 and/or adjustments. */
1307 classes
[i
] = classes
[j
];
1308 allows_mem
[i
] = allows_mem
[j
];
1310 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1312 /* If this matches the other operand, we have no added
1314 if (rtx_equal_p (ops
[j
], op
))
1317 /* If we can put the other operand into a register, add to
1318 the cost of this alternative the cost to copy this
1319 operand to the register used for the other operand. */
1321 else if (classes
[j
] != NO_REGS
)
1322 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1324 else if (GET_CODE (ops
[j
]) != REG
1325 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1327 /* This op is a pseudo but the one it matches is not. */
1329 /* If we can't put the other operand into a register, this
1330 alternative can't be used. */
1332 if (classes
[j
] == NO_REGS
)
1335 /* Otherwise, add to the cost of this alternative the cost
1336 to copy the other operand to the register used for this
1340 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1344 /* The costs of this operand are not the same as the other
1345 operand since move costs are not symmetric. Moreover,
1346 if we cannot tie them, this alternative needs to do a
1347 copy, which is one instruction. */
1349 struct costs
*pp
= &this_op_costs
[i
];
1351 for (class = 0; class < N_REG_CLASSES
; class++)
1353 = ((recog_data
.operand_type
[i
] != OP_OUT
1354 ? may_move_in_cost
[class][(int) classes
[i
]]
1356 + (recog_data
.operand_type
[i
] != OP_IN
1357 ? may_move_out_cost
[(int) classes
[i
]][class]
1360 /* If the alternative actually allows memory, make things
1361 a bit cheaper since we won't need an extra insn to
1365 = ((recog_data
.operand_type
[i
] != OP_IN
1366 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1368 + (recog_data
.operand_type
[i
] != OP_OUT
1369 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1370 : 0) - allows_mem
[i
]);
1372 /* If we have assigned a class to this register in our
1373 first pass, add a cost to this alternative corresponding
1374 to what we would add if this register were not in the
1375 appropriate class. */
1379 += (may_move_in_cost
[(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1380 [(int) classes
[i
]]);
1382 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1383 && ! find_reg_note (insn
, REG_DEAD
, op
))
1386 /* This is in place of ordinary cost computation
1387 for this operand, so skip to the end of the
1388 alternative (should be just one character). */
1389 while (*p
&& *p
++ != ',')
1397 /* Scan all the constraint letters. See if the operand matches
1398 any of the constraints. Collect the valid register classes
1399 and see if this operand accepts memory. */
1401 while (*p
&& (c
= *p
++) != ',')
1405 /* Ignore the next letter for this pass. */
1411 case '!': case '#': case '&':
1412 case '0': case '1': case '2': case '3': case '4':
1413 case '5': case '6': case '7': case '8': case '9':
1418 win
= address_operand (op
, GET_MODE (op
));
1419 /* We know this operand is an address, so we want it to be
1420 allocated to a register that can be the base of an
1421 address, ie BASE_REG_CLASS. */
1423 = reg_class_subunion
[(int) classes
[i
]]
1424 [(int) BASE_REG_CLASS
];
1427 case 'm': case 'o': case 'V':
1428 /* It doesn't seem worth distinguishing between offsettable
1429 and non-offsettable addresses here. */
1431 if (GET_CODE (op
) == MEM
)
1436 if (GET_CODE (op
) == MEM
1437 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1438 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1443 if (GET_CODE (op
) == MEM
1444 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1445 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1450 #ifndef REAL_ARITHMETIC
1451 /* Match any floating double constant, but only if
1452 we can examine the bits of it reliably. */
1453 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1454 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1455 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1458 if (GET_CODE (op
) == CONST_DOUBLE
)
1463 if (GET_CODE (op
) == CONST_DOUBLE
)
1469 if (GET_CODE (op
) == CONST_DOUBLE
1470 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1475 if (GET_CODE (op
) == CONST_INT
1476 || (GET_CODE (op
) == CONST_DOUBLE
1477 && GET_MODE (op
) == VOIDmode
))
1481 #ifdef LEGITIMATE_PIC_OPERAND_P
1482 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1489 if (GET_CODE (op
) == CONST_INT
1490 || (GET_CODE (op
) == CONST_DOUBLE
1491 && GET_MODE (op
) == VOIDmode
))
1503 if (GET_CODE (op
) == CONST_INT
1504 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1512 #ifdef EXTRA_CONSTRAINT
1518 if (EXTRA_CONSTRAINT (op
, c
))
1524 if (GET_CODE (op
) == MEM
1526 #ifdef LEGITIMATE_PIC_OPERAND_P
1527 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1534 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1539 = reg_class_subunion
[(int) classes
[i
]]
1540 [(int) REG_CLASS_FROM_LETTER (c
)];
1545 #ifdef CLASS_CANNOT_CHANGE_SIZE
1546 /* If we noted a subreg earlier, and the selected class is a
1547 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1548 if (subreg_changes_size
[i
]
1549 && (reg_class_subunion
[(int) CLASS_CANNOT_CHANGE_SIZE
]
1551 == CLASS_CANNOT_CHANGE_SIZE
))
1552 classes
[i
] = NO_REGS
;
1555 /* How we account for this operand now depends on whether it is a
1556 pseudo register or not. If it is, we first check if any
1557 register classes are valid. If not, we ignore this alternative,
1558 since we want to assume that all pseudos get allocated for
1559 register preferencing. If some register class is valid, compute
1560 the costs of moving the pseudo into that class. */
1562 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1564 if (classes
[i
] == NO_REGS
)
1566 /* We must always fail if the operand is a REG, but
1567 we did not find a suitable class.
1569 Otherwise we may perform an uninitialized read
1570 from this_op_costs after the `continue' statement
1576 struct costs
*pp
= &this_op_costs
[i
];
1578 for (class = 0; class < N_REG_CLASSES
; class++)
1580 = ((recog_data
.operand_type
[i
] != OP_OUT
1581 ? may_move_in_cost
[class][(int) classes
[i
]]
1583 + (recog_data
.operand_type
[i
] != OP_IN
1584 ? may_move_out_cost
[(int) classes
[i
]][class]
1587 /* If the alternative actually allows memory, make things
1588 a bit cheaper since we won't need an extra insn to
1592 = ((recog_data
.operand_type
[i
] != OP_IN
1593 ? MEMORY_MOVE_COST (mode
, classes
[i
], 0)
1595 + (recog_data
.operand_type
[i
] != OP_OUT
1596 ? MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1597 : 0) - allows_mem
[i
]);
1599 /* If we have assigned a class to this register in our
1600 first pass, add a cost to this alternative corresponding
1601 to what we would add if this register were not in the
1602 appropriate class. */
1606 += (may_move_in_cost
[(unsigned char) reg_pref
[REGNO (op
)].prefclass
]
1607 [(int) classes
[i
]]);
1611 /* Otherwise, if this alternative wins, either because we
1612 have already determined that or if we have a hard register of
1613 the proper class, there is no cost for this alternative. */
1616 || (GET_CODE (op
) == REG
1617 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1620 /* If registers are valid, the cost of this alternative includes
1621 copying the object to and/or from a register. */
1623 else if (classes
[i
] != NO_REGS
)
1625 if (recog_data
.operand_type
[i
] != OP_OUT
)
1626 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1628 if (recog_data
.operand_type
[i
] != OP_IN
)
1629 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1632 /* The only other way this alternative can be used is if this is a
1633 constant that could be placed into memory. */
1635 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1636 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1644 /* Finally, update the costs with the information we've calculated
1645 about this alternative. */
1647 for (i
= 0; i
< n_ops
; i
++)
1648 if (GET_CODE (ops
[i
]) == REG
1649 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1651 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1652 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1654 pp
->mem_cost
= MIN (pp
->mem_cost
,
1655 (qq
->mem_cost
+ alt_cost
) * scale
);
1657 for (class = 0; class < N_REG_CLASSES
; class++)
1658 pp
->cost
[class] = MIN (pp
->cost
[class],
1659 (qq
->cost
[class] + alt_cost
) * scale
);
1663 /* If this insn is a single set copying operand 1 to operand 0
1664 and one operand is a pseudo with the other a hard reg or a pseudo
1665 that prefers a register that is in its own register class then
1666 we may want to adjust the cost of that register class to -1.
1668 Avoid the adjustment if the source does not die to avoid stressing of
1669 register allocator by preferrencing two coliding registers into single
1672 Also avoid the adjustment if a copy between registers of the class
1673 is expensive (ten times the cost of a default copy is considered
1674 arbitrarily expensive). This avoids losing when the preferred class
1675 is very expensive as the source of a copy instruction. */
1677 if ((set
= single_set (insn
)) != 0
1678 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1679 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
1680 && find_regno_note (insn
, REG_DEAD
, REGNO (ops
[1])))
1681 for (i
= 0; i
<= 1; i
++)
1682 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1684 unsigned int regno
= REGNO (ops
[!i
]);
1685 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1689 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_pref
!= 0)
1691 enum reg_class pref
= reg_pref
[regno
].prefclass
;
1693 if ((reg_class_size
[(unsigned char) pref
]
1694 == CLASS_MAX_NREGS (pref
, mode
))
1695 && REGISTER_MOVE_COST (pref
, pref
) < 10 * 2)
1696 op_costs
[i
].cost
[(unsigned char) pref
] = -1;
1698 else if (regno
< FIRST_PSEUDO_REGISTER
)
1699 for (class = 0; class < N_REG_CLASSES
; class++)
1700 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1701 && reg_class_size
[class] == CLASS_MAX_NREGS (class, mode
))
1703 if (reg_class_size
[class] == 1)
1704 op_costs
[i
].cost
[class] = -1;
1707 for (nr
= 0; nr
< HARD_REGNO_NREGS (regno
, mode
); nr
++)
1709 if (! TEST_HARD_REG_BIT (reg_class_contents
[class],
1714 if (nr
== HARD_REGNO_NREGS (regno
,mode
))
1715 op_costs
[i
].cost
[class] = -1;
1721 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1722 TO_P is zero) a register of class CLASS in mode MODE.
1724 X must not be a pseudo. */
1727 copy_cost (x
, mode
, class, to_p
)
1729 enum machine_mode mode ATTRIBUTE_UNUSED
;
1730 enum reg_class
class;
1731 int to_p ATTRIBUTE_UNUSED
;
1733 #ifdef HAVE_SECONDARY_RELOADS
1734 enum reg_class secondary_class
= NO_REGS
;
1737 /* If X is a SCRATCH, there is actually nothing to move since we are
1738 assuming optimal allocation. */
1740 if (GET_CODE (x
) == SCRATCH
)
1743 /* Get the class we will actually use for a reload. */
1744 class = PREFERRED_RELOAD_CLASS (x
, class);
1746 #ifdef HAVE_SECONDARY_RELOADS
1747 /* If we need a secondary reload (we assume here that we are using
1748 the secondary reload as an intermediate, not a scratch register), the
1749 cost is that to load the input into the intermediate register, then
1750 to copy them. We use a special value of TO_P to avoid recursion. */
1752 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1754 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1757 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1759 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1762 if (secondary_class
!= NO_REGS
)
1763 return (move_cost
[(int) secondary_class
][(int) class]
1764 + copy_cost (x
, mode
, secondary_class
, 2));
1765 #endif /* HAVE_SECONDARY_RELOADS */
1767 /* For memory, use the memory move cost, for (hard) registers, use the
1768 cost to move between the register classes, and use 2 for everything
1769 else (constants). */
1771 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1772 return MEMORY_MOVE_COST (mode
, class, to_p
);
1774 else if (GET_CODE (x
) == REG
)
1775 return move_cost
[(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1778 /* If this is a constant, we may eventually want to call rtx_cost here. */
1782 /* Record the pseudo registers we must reload into hard registers
1783 in a subexpression of a memory address, X.
1785 CLASS is the class that the register needs to be in and is either
1786 BASE_REG_CLASS or INDEX_REG_CLASS.
1788 SCALE is twice the amount to multiply the cost by (it is twice so we
1789 can represent half-cost adjustments). */
1792 record_address_regs (x
, class, scale
)
1794 enum reg_class
class;
1797 register enum rtx_code code
= GET_CODE (x
);
1810 /* When we have an address that is a sum,
1811 we must determine whether registers are "base" or "index" regs.
1812 If there is a sum of two registers, we must choose one to be
1813 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1814 to make a good choice most of the time. We only need to do this
1815 on machines that can have two registers in an address and where
1816 the base and index register classes are different.
1818 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1819 that seems bogus since it should only be set when we are sure
1820 the register is being used as a pointer. */
1823 rtx arg0
= XEXP (x
, 0);
1824 rtx arg1
= XEXP (x
, 1);
1825 register enum rtx_code code0
= GET_CODE (arg0
);
1826 register enum rtx_code code1
= GET_CODE (arg1
);
1828 /* Look inside subregs. */
1829 if (code0
== SUBREG
)
1830 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1831 if (code1
== SUBREG
)
1832 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1834 /* If this machine only allows one register per address, it must
1835 be in the first operand. */
1837 if (MAX_REGS_PER_ADDRESS
== 1)
1838 record_address_regs (arg0
, class, scale
);
1840 /* If index and base registers are the same on this machine, just
1841 record registers in any non-constant operands. We assume here,
1842 as well as in the tests below, that all addresses are in
1845 else if (INDEX_REG_CLASS
== BASE_REG_CLASS
)
1847 record_address_regs (arg0
, class, scale
);
1848 if (! CONSTANT_P (arg1
))
1849 record_address_regs (arg1
, class, scale
);
1852 /* If the second operand is a constant integer, it doesn't change
1853 what class the first operand must be. */
1855 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1856 record_address_regs (arg0
, class, scale
);
1858 /* If the second operand is a symbolic constant, the first operand
1859 must be an index register. */
1861 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1862 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1864 /* If both operands are registers but one is already a hard register
1865 of index or base class, give the other the class that the hard
1868 #ifdef REG_OK_FOR_BASE_P
1869 else if (code0
== REG
&& code1
== REG
1870 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1871 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
1872 record_address_regs (arg1
,
1873 REG_OK_FOR_BASE_P (arg0
)
1874 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1876 else if (code0
== REG
&& code1
== REG
1877 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1878 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
1879 record_address_regs (arg0
,
1880 REG_OK_FOR_BASE_P (arg1
)
1881 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1885 /* If one operand is known to be a pointer, it must be the base
1886 with the other operand the index. Likewise if the other operand
1889 else if ((code0
== REG
&& REGNO_POINTER_FLAG (REGNO (arg0
)))
1892 record_address_regs (arg0
, BASE_REG_CLASS
, scale
);
1893 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
1895 else if ((code1
== REG
&& REGNO_POINTER_FLAG (REGNO (arg1
)))
1898 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1899 record_address_regs (arg1
, BASE_REG_CLASS
, scale
);
1902 /* Otherwise, count equal chances that each might be a base
1903 or index register. This case should be rare. */
1907 record_address_regs (arg0
, BASE_REG_CLASS
, scale
/ 2);
1908 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
1909 record_address_regs (arg1
, BASE_REG_CLASS
, scale
/ 2);
1910 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
1919 /* Double the importance of a pseudo register that is incremented
1920 or decremented, since it would take two extra insns
1921 if it ends up in the wrong place. If the operand is a pseudo,
1922 show it is being used in an INC_DEC context. */
1924 #ifdef FORBIDDEN_INC_DEC_CLASSES
1925 if (GET_CODE (XEXP (x
, 0)) == REG
1926 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
1927 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
1930 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
1935 register struct costs
*pp
= &costs
[REGNO (x
)];
1938 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
1940 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1941 pp
->cost
[i
] += (may_move_in_cost
[i
][(int) class] * scale
) / 2;
1947 register const char *fmt
= GET_RTX_FORMAT (code
);
1949 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1951 record_address_regs (XEXP (x
, i
), class, scale
);
1956 #ifdef FORBIDDEN_INC_DEC_CLASSES
1958 /* Return 1 if REG is valid as an auto-increment memory reference
1959 to an object of MODE. */
1962 auto_inc_dec_reg_p (reg
, mode
)
1964 enum machine_mode mode
;
1966 if (HAVE_POST_INCREMENT
1967 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
1970 if (HAVE_POST_DECREMENT
1971 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
1974 if (HAVE_PRE_INCREMENT
1975 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
1978 if (HAVE_PRE_DECREMENT
1979 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
1986 static short *renumber
;
1987 static size_t regno_allocated
;
1988 static unsigned int reg_n_max
;
1990 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1991 reg_scan and flow_analysis that are indexed by the register number. If
1992 NEW_P is non zero, initialize all of the registers, otherwise only
1993 initialize the new registers allocated. The same table is kept from
1994 function to function, only reallocating it when we need more room. If
1995 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1998 allocate_reg_info (num_regs
, new_p
, renumber_p
)
2004 size_t size_renumber
;
2005 size_t min
= (new_p
) ? 0 : reg_n_max
;
2006 struct reg_info_data
*reg_data
;
2008 if (num_regs
> regno_allocated
)
2010 size_t old_allocated
= regno_allocated
;
2012 regno_allocated
= num_regs
+ (num_regs
/ 20); /* add some slop space */
2013 size_renumber
= regno_allocated
* sizeof (short);
2017 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
2018 renumber
= (short *) xmalloc (size_renumber
);
2019 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2020 * sizeof (struct reg_pref
));
2025 VARRAY_GROW (reg_n_info
, regno_allocated
);
2027 if (new_p
) /* if we're zapping everything, no need to realloc */
2029 free ((char *)renumber
);
2030 free ((char *)reg_pref
);
2031 renumber
= (short *) xmalloc (size_renumber
);
2032 reg_pref_buffer
= (struct reg_pref
*) xmalloc (regno_allocated
2033 * sizeof (struct reg_pref
));
2038 renumber
= (short *) xrealloc ((char *)renumber
, size_renumber
);
2039 reg_pref_buffer
= (struct reg_pref
*) xrealloc ((char *)reg_pref_buffer
,
2041 * sizeof (struct reg_pref
));
2045 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
2046 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
2047 reg_data
= (struct reg_info_data
*) xcalloc (size_info
, 1);
2048 reg_data
->min_index
= old_allocated
;
2049 reg_data
->max_index
= regno_allocated
- 1;
2050 reg_data
->next
= reg_info_head
;
2051 reg_info_head
= reg_data
;
2054 reg_n_max
= num_regs
;
2057 /* Loop through each of the segments allocated for the actual
2058 reg_info pages, and set up the pointers, zero the pages, etc. */
2059 for (reg_data
= reg_info_head
;
2060 reg_data
&& reg_data
->max_index
>= min
;
2061 reg_data
= reg_data
->next
)
2063 size_t min_index
= reg_data
->min_index
;
2064 size_t max_index
= reg_data
->max_index
;
2065 size_t max
= MIN (max_index
, num_regs
);
2066 size_t local_min
= min
- min_index
;
2069 if (reg_data
->min_index
> num_regs
)
2072 if (min
< min_index
)
2074 if (!reg_data
->used_p
) /* page just allocated with calloc */
2075 reg_data
->used_p
= 1; /* no need to zero */
2077 bzero ((char *) ®_data
->data
[local_min
],
2078 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
2080 for (i
= min_index
+local_min
; i
<= max
; i
++)
2082 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
2083 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
2085 reg_pref_buffer
[i
].prefclass
= (char) NO_REGS
;
2086 reg_pref_buffer
[i
].altclass
= (char) NO_REGS
;
2091 /* If {pref,alt}class have already been allocated, update the pointers to
2092 the newly realloced ones. */
2094 reg_pref
= reg_pref_buffer
;
2097 reg_renumber
= renumber
;
2099 /* Tell the regset code about the new number of registers */
2100 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
2103 /* Free up the space allocated by allocate_reg_info. */
2109 struct reg_info_data
*reg_data
;
2110 struct reg_info_data
*reg_next
;
2112 VARRAY_FREE (reg_n_info
);
2113 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
2115 reg_next
= reg_data
->next
;
2116 free ((char *)reg_data
);
2119 free (reg_pref_buffer
);
2120 reg_pref_buffer
= (struct reg_pref
*)0;
2121 reg_info_head
= (struct reg_info_data
*)0;
2122 renumber
= (short *)0;
2124 regno_allocated
= 0;
2128 /* This is the `regscan' pass of the compiler, run just before cse
2129 and again just before loop.
2131 It finds the first and last use of each pseudo-register
2132 and records them in the vectors regno_first_uid, regno_last_uid
2133 and counts the number of sets in the vector reg_n_sets.
2135 REPEAT is nonzero the second time this is called. */
2137 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2138 Always at least 3, since the combiner could put that many together
2139 and we want this to remain correct for all the remaining passes. */
2144 reg_scan (f
, nregs
, repeat
)
2147 int repeat ATTRIBUTE_UNUSED
;
2151 allocate_reg_info (nregs
, TRUE
, FALSE
);
2154 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2155 if (GET_CODE (insn
) == INSN
2156 || GET_CODE (insn
) == CALL_INSN
2157 || GET_CODE (insn
) == JUMP_INSN
)
2159 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2160 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2161 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2162 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, 0);
2164 if (REG_NOTES (insn
))
2165 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
2169 /* Update 'regscan' information by looking at the insns
2170 from FIRST to LAST. Some new REGs have been created,
2171 and any REG with number greater than OLD_MAX_REGNO is
2172 such a REG. We only update information for those. */
2175 reg_scan_update (first
, last
, old_max_regno
)
2178 unsigned int old_max_regno
;
2182 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
2184 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
2185 if (GET_CODE (insn
) == INSN
2186 || GET_CODE (insn
) == CALL_INSN
2187 || GET_CODE (insn
) == JUMP_INSN
)
2189 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2190 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2191 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2192 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, old_max_regno
);
2194 if (REG_NOTES (insn
))
2195 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2199 /* X is the expression to scan. INSN is the insn it appears in.
2200 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2201 We should only record information for REGs with numbers
2202 greater than or equal to MIN_REGNO. */
2205 reg_scan_mark_refs (x
, insn
, note_flag
, min_regno
)
2209 unsigned int min_regno
;
2211 register enum rtx_code code
;
2215 code
= GET_CODE (x
);
2231 unsigned int regno
= REGNO (x
);
2233 if (regno
>= min_regno
)
2235 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2237 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2238 if (REGNO_FIRST_UID (regno
) == 0)
2239 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2246 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2248 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2253 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2257 /* Count a set of the destination if it is a register. */
2258 for (dest
= SET_DEST (x
);
2259 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2260 || GET_CODE (dest
) == ZERO_EXTEND
;
2261 dest
= XEXP (dest
, 0))
2264 if (GET_CODE (dest
) == REG
2265 && REGNO (dest
) >= min_regno
)
2266 REG_N_SETS (REGNO (dest
))++;
2268 /* If this is setting a pseudo from another pseudo or the sum of a
2269 pseudo and a constant integer and the other pseudo is known to be
2270 a pointer, set the destination to be a pointer as well.
2272 Likewise if it is setting the destination from an address or from a
2273 value equivalent to an address or to the sum of an address and
2276 But don't do any of this if the pseudo corresponds to a user
2277 variable since it should have already been set as a pointer based
2280 if (GET_CODE (SET_DEST (x
)) == REG
2281 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2282 && REGNO (SET_DEST (x
)) >= min_regno
2283 /* If the destination pseudo is set more than once, then other
2284 sets might not be to a pointer value (consider access to a
2285 union in two threads of control in the presense of global
2286 optimizations). So only set REGNO_POINTER_FLAG on the destination
2287 pseudo if this is the only set of that pseudo. */
2288 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2289 && ! REG_USERVAR_P (SET_DEST (x
))
2290 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x
)))
2291 && ((GET_CODE (SET_SRC (x
)) == REG
2292 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x
))))
2293 || ((GET_CODE (SET_SRC (x
)) == PLUS
2294 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2295 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2296 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2297 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x
), 0))))
2298 || GET_CODE (SET_SRC (x
)) == CONST
2299 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2300 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2301 || (GET_CODE (SET_SRC (x
)) == HIGH
2302 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2303 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2304 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2305 || ((GET_CODE (SET_SRC (x
)) == PLUS
2306 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2307 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2308 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2309 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2310 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2311 && (GET_CODE (XEXP (note
, 0)) == CONST
2312 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2313 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2314 REGNO_POINTER_FLAG (REGNO (SET_DEST (x
))) = 1;
2316 /* ... fall through ... */
2320 register const char *fmt
= GET_RTX_FORMAT (code
);
2322 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2325 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2326 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2329 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2330 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2337 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2341 reg_class_subset_p (c1
, c2
)
2342 register enum reg_class c1
;
2343 register enum reg_class c2
;
2345 if (c1
== c2
) return 1;
2350 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int)c1
],
2351 reg_class_contents
[(int)c2
],
2356 /* Return nonzero if there is a register that is in both C1 and C2. */
2359 reg_classes_intersect_p (c1
, c2
)
2360 register enum reg_class c1
;
2361 register enum reg_class c2
;
2368 if (c1
== c2
) return 1;
2370 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2373 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2374 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2376 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2383 /* Release any memory allocated by register sets. */
2386 regset_release_memory ()
2388 bitmap_release_memory ();