Merged r158465 through r158660 into branch.
[official-gcc.git] / gcc / config / ia64 / ia64.c
blob983ecf40372e78532b8e3d474e29cd5990442a11
1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by James E. Wilson <wilson@cygnus.com> and
6 David Mosberger <davidm@hpl.hp.com>.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "real.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "recog.h"
39 #include "expr.h"
40 #include "optabs.h"
41 #include "except.h"
42 #include "function.h"
43 #include "ggc.h"
44 #include "basic-block.h"
45 #include "libfuncs.h"
46 #include "toplev.h"
47 #include "sched-int.h"
48 #include "timevar.h"
49 #include "target.h"
50 #include "target-def.h"
51 #include "tm_p.h"
52 #include "hashtab.h"
53 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "gimple.h"
56 #include "intl.h"
57 #include "df.h"
58 #include "debug.h"
59 #include "params.h"
60 #include "dbgcnt.h"
61 #include "tm-constrs.h"
62 #include "sel-sched.h"
64 /* This is used for communication between ASM_OUTPUT_LABEL and
65 ASM_OUTPUT_LABELREF. */
66 int ia64_asm_output_label = 0;
68 /* Register names for ia64_expand_prologue. */
69 static const char * const ia64_reg_numbers[96] =
70 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
71 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
72 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
73 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
74 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
75 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
76 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
77 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
78 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
79 "r104","r105","r106","r107","r108","r109","r110","r111",
80 "r112","r113","r114","r115","r116","r117","r118","r119",
81 "r120","r121","r122","r123","r124","r125","r126","r127"};
83 /* ??? These strings could be shared with REGISTER_NAMES. */
84 static const char * const ia64_input_reg_names[8] =
85 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
87 /* ??? These strings could be shared with REGISTER_NAMES. */
88 static const char * const ia64_local_reg_names[80] =
89 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
90 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
91 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
92 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
93 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
94 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
95 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
96 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
97 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
98 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
100 /* ??? These strings could be shared with REGISTER_NAMES. */
101 static const char * const ia64_output_reg_names[8] =
102 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
104 /* Which cpu are we scheduling for. */
105 enum processor_type ia64_tune = PROCESSOR_ITANIUM2;
107 /* Determines whether we run our final scheduling pass or not. We always
108 avoid the normal second scheduling pass. */
109 static int ia64_flag_schedule_insns2;
111 /* Determines whether we run variable tracking in machine dependent
112 reorganization. */
113 static int ia64_flag_var_tracking;
115 /* Variables which are this size or smaller are put in the sdata/sbss
116 sections. */
118 unsigned int ia64_section_threshold;
120 /* The following variable is used by the DFA insn scheduler. The value is
121 TRUE if we do insn bundling instead of insn scheduling. */
122 int bundling_p = 0;
124 enum ia64_frame_regs
126 reg_fp,
127 reg_save_b0,
128 reg_save_pr,
129 reg_save_ar_pfs,
130 reg_save_ar_unat,
131 reg_save_ar_lc,
132 reg_save_gp,
133 number_of_ia64_frame_regs
136 /* Structure to be filled in by ia64_compute_frame_size with register
137 save masks and offsets for the current function. */
139 struct ia64_frame_info
141 HOST_WIDE_INT total_size; /* size of the stack frame, not including
142 the caller's scratch area. */
143 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
144 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
145 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
146 HARD_REG_SET mask; /* mask of saved registers. */
147 unsigned int gr_used_mask; /* mask of registers in use as gr spill
148 registers or long-term scratches. */
149 int n_spilled; /* number of spilled registers. */
150 int r[number_of_ia64_frame_regs]; /* Frame related registers. */
151 int n_input_regs; /* number of input registers used. */
152 int n_local_regs; /* number of local registers used. */
153 int n_output_regs; /* number of output registers used. */
154 int n_rotate_regs; /* number of rotating registers used. */
156 char need_regstk; /* true if a .regstk directive needed. */
157 char initialized; /* true if the data is finalized. */
160 /* Current frame information calculated by ia64_compute_frame_size. */
161 static struct ia64_frame_info current_frame_info;
162 /* The actual registers that are emitted. */
163 static int emitted_frame_related_regs[number_of_ia64_frame_regs];
165 static int ia64_first_cycle_multipass_dfa_lookahead (void);
166 static void ia64_dependencies_evaluation_hook (rtx, rtx);
167 static void ia64_init_dfa_pre_cycle_insn (void);
168 static rtx ia64_dfa_pre_cycle_insn (void);
169 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
170 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx);
171 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
172 static void ia64_h_i_d_extended (void);
173 static void * ia64_alloc_sched_context (void);
174 static void ia64_init_sched_context (void *, bool);
175 static void ia64_set_sched_context (void *);
176 static void ia64_clear_sched_context (void *);
177 static void ia64_free_sched_context (void *);
178 static int ia64_mode_to_int (enum machine_mode);
179 static void ia64_set_sched_flags (spec_info_t);
180 static ds_t ia64_get_insn_spec_ds (rtx);
181 static ds_t ia64_get_insn_checked_ds (rtx);
182 static bool ia64_skip_rtx_p (const_rtx);
183 static int ia64_speculate_insn (rtx, ds_t, rtx *);
184 static bool ia64_needs_block_p (int);
185 static rtx ia64_gen_spec_check (rtx, rtx, ds_t);
186 static int ia64_spec_check_p (rtx);
187 static int ia64_spec_check_src_p (rtx);
188 static rtx gen_tls_get_addr (void);
189 static rtx gen_thread_pointer (void);
190 static int find_gr_spill (enum ia64_frame_regs, int);
191 static int next_scratch_gr_reg (void);
192 static void mark_reg_gr_used_mask (rtx, void *);
193 static void ia64_compute_frame_size (HOST_WIDE_INT);
194 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
195 static void finish_spill_pointers (void);
196 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
197 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
198 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
199 static rtx gen_movdi_x (rtx, rtx, rtx);
200 static rtx gen_fr_spill_x (rtx, rtx, rtx);
201 static rtx gen_fr_restore_x (rtx, rtx, rtx);
203 static bool ia64_can_eliminate (const int, const int);
204 static enum machine_mode hfa_element_mode (const_tree, bool);
205 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
206 tree, int *, int);
207 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
208 tree, bool);
209 static bool ia64_function_ok_for_sibcall (tree, tree);
210 static bool ia64_return_in_memory (const_tree, const_tree);
211 static bool ia64_rtx_costs (rtx, int, int, int *, bool);
212 static int ia64_unspec_may_trap_p (const_rtx, unsigned);
213 static void fix_range (const char *);
214 static bool ia64_handle_option (size_t, const char *, int);
215 static struct machine_function * ia64_init_machine_status (void);
216 static void emit_insn_group_barriers (FILE *);
217 static void emit_all_insn_group_barriers (FILE *);
218 static void final_emit_insn_group_barriers (FILE *);
219 static void emit_predicate_relation_info (void);
220 static void ia64_reorg (void);
221 static bool ia64_in_small_data_p (const_tree);
222 static void process_epilogue (FILE *, rtx, bool, bool);
223 static int process_set (FILE *, rtx, rtx, bool, bool);
225 static bool ia64_assemble_integer (rtx, unsigned int, int);
226 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
227 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
228 static void ia64_output_function_end_prologue (FILE *);
230 static int ia64_issue_rate (void);
231 static int ia64_adjust_cost_2 (rtx, int, rtx, int, dw_t);
232 static void ia64_sched_init (FILE *, int, int);
233 static void ia64_sched_init_global (FILE *, int, int);
234 static void ia64_sched_finish_global (FILE *, int);
235 static void ia64_sched_finish (FILE *, int);
236 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
237 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
238 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
239 static int ia64_variable_issue (FILE *, int, rtx, int);
241 static struct bundle_state *get_free_bundle_state (void);
242 static void free_bundle_state (struct bundle_state *);
243 static void initiate_bundle_states (void);
244 static void finish_bundle_states (void);
245 static unsigned bundle_state_hash (const void *);
246 static int bundle_state_eq_p (const void *, const void *);
247 static int insert_bundle_state (struct bundle_state *);
248 static void initiate_bundle_state_table (void);
249 static void finish_bundle_state_table (void);
250 static int try_issue_nops (struct bundle_state *, int);
251 static int try_issue_insn (struct bundle_state *, rtx);
252 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
253 static int get_max_pos (state_t);
254 static int get_template (state_t, int);
256 static rtx get_next_important_insn (rtx, rtx);
257 static bool important_for_bundling_p (rtx);
258 static void bundling (FILE *, int, rtx, rtx);
260 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
261 HOST_WIDE_INT, tree);
262 static void ia64_file_start (void);
263 static void ia64_globalize_decl_name (FILE *, tree);
265 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
266 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
267 static section *ia64_select_rtx_section (enum machine_mode, rtx,
268 unsigned HOST_WIDE_INT);
269 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
270 ATTRIBUTE_UNUSED;
271 static unsigned int ia64_section_type_flags (tree, const char *, int);
272 static void ia64_init_libfuncs (void)
273 ATTRIBUTE_UNUSED;
274 static void ia64_hpux_init_libfuncs (void)
275 ATTRIBUTE_UNUSED;
276 static void ia64_sysv4_init_libfuncs (void)
277 ATTRIBUTE_UNUSED;
278 static void ia64_vms_init_libfuncs (void)
279 ATTRIBUTE_UNUSED;
280 static void ia64_soft_fp_init_libfuncs (void)
281 ATTRIBUTE_UNUSED;
282 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode)
283 ATTRIBUTE_UNUSED;
284 static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *)
285 ATTRIBUTE_UNUSED;
287 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
288 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
289 static void ia64_encode_section_info (tree, rtx, int);
290 static rtx ia64_struct_value_rtx (tree, int);
291 static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
292 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
293 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
294 static bool ia64_cannot_force_const_mem (rtx);
295 static const char *ia64_mangle_type (const_tree);
296 static const char *ia64_invalid_conversion (const_tree, const_tree);
297 static const char *ia64_invalid_unary_op (int, const_tree);
298 static const char *ia64_invalid_binary_op (int, const_tree, const_tree);
299 static enum machine_mode ia64_c_mode_for_suffix (char);
300 static enum machine_mode ia64_promote_function_mode (const_tree,
301 enum machine_mode,
302 int *,
303 const_tree,
304 int);
305 static void ia64_trampoline_init (rtx, tree, rtx);
306 static void ia64_override_options_after_change (void);
308 /* Table of valid machine attributes. */
309 static const struct attribute_spec ia64_attribute_table[] =
311 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
312 { "syscall_linkage", 0, 0, false, true, true, NULL },
313 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
314 #if TARGET_ABI_OPEN_VMS
315 { "common_object", 1, 1, true, false, false, ia64_vms_common_object_attribute},
316 #endif
317 { "version_id", 1, 1, true, false, false,
318 ia64_handle_version_id_attribute },
319 { NULL, 0, 0, false, false, false, NULL }
322 /* Initialize the GCC target structure. */
323 #undef TARGET_ATTRIBUTE_TABLE
324 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
326 #undef TARGET_INIT_BUILTINS
327 #define TARGET_INIT_BUILTINS ia64_init_builtins
329 #undef TARGET_EXPAND_BUILTIN
330 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
332 #undef TARGET_ASM_BYTE_OP
333 #define TARGET_ASM_BYTE_OP "\tdata1\t"
334 #undef TARGET_ASM_ALIGNED_HI_OP
335 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
336 #undef TARGET_ASM_ALIGNED_SI_OP
337 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
338 #undef TARGET_ASM_ALIGNED_DI_OP
339 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
340 #undef TARGET_ASM_UNALIGNED_HI_OP
341 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
342 #undef TARGET_ASM_UNALIGNED_SI_OP
343 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
344 #undef TARGET_ASM_UNALIGNED_DI_OP
345 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
346 #undef TARGET_ASM_INTEGER
347 #define TARGET_ASM_INTEGER ia64_assemble_integer
349 #undef TARGET_ASM_FUNCTION_PROLOGUE
350 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
351 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
352 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
353 #undef TARGET_ASM_FUNCTION_EPILOGUE
354 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
356 #undef TARGET_IN_SMALL_DATA_P
357 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
359 #undef TARGET_SCHED_ADJUST_COST_2
360 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
361 #undef TARGET_SCHED_ISSUE_RATE
362 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
363 #undef TARGET_SCHED_VARIABLE_ISSUE
364 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
365 #undef TARGET_SCHED_INIT
366 #define TARGET_SCHED_INIT ia64_sched_init
367 #undef TARGET_SCHED_FINISH
368 #define TARGET_SCHED_FINISH ia64_sched_finish
369 #undef TARGET_SCHED_INIT_GLOBAL
370 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
371 #undef TARGET_SCHED_FINISH_GLOBAL
372 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
373 #undef TARGET_SCHED_REORDER
374 #define TARGET_SCHED_REORDER ia64_sched_reorder
375 #undef TARGET_SCHED_REORDER2
376 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
378 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
379 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
381 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
382 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
384 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
385 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
386 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
387 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
389 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
390 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
391 ia64_first_cycle_multipass_dfa_lookahead_guard
393 #undef TARGET_SCHED_DFA_NEW_CYCLE
394 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
396 #undef TARGET_SCHED_H_I_D_EXTENDED
397 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
399 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
400 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
402 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
403 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
405 #undef TARGET_SCHED_SET_SCHED_CONTEXT
406 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
408 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
409 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
411 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
412 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
414 #undef TARGET_SCHED_SET_SCHED_FLAGS
415 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
417 #undef TARGET_SCHED_GET_INSN_SPEC_DS
418 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
420 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
421 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
423 #undef TARGET_SCHED_SPECULATE_INSN
424 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
426 #undef TARGET_SCHED_NEEDS_BLOCK_P
427 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
429 #undef TARGET_SCHED_GEN_SPEC_CHECK
430 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
432 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
433 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
434 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
436 #undef TARGET_SCHED_SKIP_RTX_P
437 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
439 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
440 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
441 #undef TARGET_ARG_PARTIAL_BYTES
442 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
444 #undef TARGET_ASM_OUTPUT_MI_THUNK
445 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
446 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
447 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
449 #undef TARGET_ASM_FILE_START
450 #define TARGET_ASM_FILE_START ia64_file_start
452 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
453 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
455 #undef TARGET_RTX_COSTS
456 #define TARGET_RTX_COSTS ia64_rtx_costs
457 #undef TARGET_ADDRESS_COST
458 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
460 #undef TARGET_UNSPEC_MAY_TRAP_P
461 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
463 #undef TARGET_MACHINE_DEPENDENT_REORG
464 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
466 #undef TARGET_ENCODE_SECTION_INFO
467 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
469 #undef TARGET_SECTION_TYPE_FLAGS
470 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
472 #ifdef HAVE_AS_TLS
473 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
474 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
475 #endif
477 #undef TARGET_PROMOTE_FUNCTION_MODE
478 #define TARGET_PROMOTE_FUNCTION_MODE ia64_promote_function_mode
480 /* ??? Investigate. */
481 #if 0
482 #undef TARGET_PROMOTE_PROTOTYPES
483 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
484 #endif
486 #undef TARGET_STRUCT_VALUE_RTX
487 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
488 #undef TARGET_RETURN_IN_MEMORY
489 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
490 #undef TARGET_SETUP_INCOMING_VARARGS
491 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
492 #undef TARGET_STRICT_ARGUMENT_NAMING
493 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
494 #undef TARGET_MUST_PASS_IN_STACK
495 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
497 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
498 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
500 #undef TARGET_UNWIND_EMIT
501 #define TARGET_UNWIND_EMIT process_for_unwind_directive
503 #undef TARGET_SCALAR_MODE_SUPPORTED_P
504 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
505 #undef TARGET_VECTOR_MODE_SUPPORTED_P
506 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
508 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
509 in an order different from the specified program order. */
510 #undef TARGET_RELAXED_ORDERING
511 #define TARGET_RELAXED_ORDERING true
513 #undef TARGET_DEFAULT_TARGET_FLAGS
514 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
515 #undef TARGET_HANDLE_OPTION
516 #define TARGET_HANDLE_OPTION ia64_handle_option
518 #undef TARGET_CANNOT_FORCE_CONST_MEM
519 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
521 #undef TARGET_MANGLE_TYPE
522 #define TARGET_MANGLE_TYPE ia64_mangle_type
524 #undef TARGET_INVALID_CONVERSION
525 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
526 #undef TARGET_INVALID_UNARY_OP
527 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
528 #undef TARGET_INVALID_BINARY_OP
529 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
531 #undef TARGET_C_MODE_FOR_SUFFIX
532 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
534 #undef TARGET_CAN_ELIMINATE
535 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
537 #undef TARGET_TRAMPOLINE_INIT
538 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
540 #undef TARGET_INVALID_WITHIN_DOLOOP
541 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
543 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
544 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
546 struct gcc_target targetm = TARGET_INITIALIZER;
548 typedef enum
550 ADDR_AREA_NORMAL, /* normal address area */
551 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
553 ia64_addr_area;
555 static GTY(()) tree small_ident1;
556 static GTY(()) tree small_ident2;
558 static void
559 init_idents (void)
561 if (small_ident1 == 0)
563 small_ident1 = get_identifier ("small");
564 small_ident2 = get_identifier ("__small__");
568 /* Retrieve the address area that has been chosen for the given decl. */
570 static ia64_addr_area
571 ia64_get_addr_area (tree decl)
573 tree model_attr;
575 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
576 if (model_attr)
578 tree id;
580 init_idents ();
581 id = TREE_VALUE (TREE_VALUE (model_attr));
582 if (id == small_ident1 || id == small_ident2)
583 return ADDR_AREA_SMALL;
585 return ADDR_AREA_NORMAL;
588 static tree
589 ia64_handle_model_attribute (tree *node, tree name, tree args,
590 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
592 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
593 ia64_addr_area area;
594 tree arg, decl = *node;
596 init_idents ();
597 arg = TREE_VALUE (args);
598 if (arg == small_ident1 || arg == small_ident2)
600 addr_area = ADDR_AREA_SMALL;
602 else
604 warning (OPT_Wattributes, "invalid argument of %qE attribute",
605 name);
606 *no_add_attrs = true;
609 switch (TREE_CODE (decl))
611 case VAR_DECL:
612 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
613 == FUNCTION_DECL)
614 && !TREE_STATIC (decl))
616 error_at (DECL_SOURCE_LOCATION (decl),
617 "an address area attribute cannot be specified for "
618 "local variables");
619 *no_add_attrs = true;
621 area = ia64_get_addr_area (decl);
622 if (area != ADDR_AREA_NORMAL && addr_area != area)
624 error ("address area of %q+D conflicts with previous "
625 "declaration", decl);
626 *no_add_attrs = true;
628 break;
630 case FUNCTION_DECL:
631 error_at (DECL_SOURCE_LOCATION (decl),
632 "address area attribute cannot be specified for "
633 "functions");
634 *no_add_attrs = true;
635 break;
637 default:
638 warning (OPT_Wattributes, "%qE attribute ignored",
639 name);
640 *no_add_attrs = true;
641 break;
644 return NULL_TREE;
647 /* The section must have global and overlaid attributes. */
648 #define SECTION_VMS_OVERLAY SECTION_MACH_DEP
650 /* Part of the low level implementation of DEC Ada pragma Common_Object which
651 enables the shared use of variables stored in overlaid linker areas
652 corresponding to the use of Fortran COMMON. */
654 static tree
655 ia64_vms_common_object_attribute (tree *node, tree name, tree args,
656 int flags ATTRIBUTE_UNUSED,
657 bool *no_add_attrs)
659 tree decl = *node;
660 tree id, val;
661 if (! DECL_P (decl))
662 abort ();
664 DECL_COMMON (decl) = 1;
665 id = TREE_VALUE (args);
666 if (TREE_CODE (id) == IDENTIFIER_NODE)
667 val = build_string (IDENTIFIER_LENGTH (id), IDENTIFIER_POINTER (id));
668 else if (TREE_CODE (id) == STRING_CST)
669 val = id;
670 else
672 warning (OPT_Wattributes,
673 "%qE attribute requires a string constant argument", name);
674 *no_add_attrs = true;
675 return NULL_TREE;
677 DECL_SECTION_NAME (decl) = val;
678 return NULL_TREE;
681 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
683 void
684 ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name,
685 unsigned HOST_WIDE_INT size,
686 unsigned int align)
688 tree attr = DECL_ATTRIBUTES (decl);
690 /* As common_object attribute set DECL_SECTION_NAME check it before
691 looking up the attribute. */
692 if (DECL_SECTION_NAME (decl) && attr)
693 attr = lookup_attribute ("common_object", attr);
694 else
695 attr = NULL_TREE;
697 if (!attr)
699 /* Code from elfos.h. */
700 fprintf (file, "%s", COMMON_ASM_OP);
701 assemble_name (file, name);
702 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
703 size, align / BITS_PER_UNIT);
705 else
707 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
708 ASM_OUTPUT_LABEL (file, name);
709 ASM_OUTPUT_SKIP (file, size ? size : 1);
713 /* Definition of TARGET_ASM_NAMED_SECTION for VMS. */
715 void
716 ia64_vms_elf_asm_named_section (const char *name, unsigned int flags,
717 tree decl)
719 if (!(flags & SECTION_VMS_OVERLAY))
721 default_elf_asm_named_section (name, flags, decl);
722 return;
724 if (flags != (SECTION_VMS_OVERLAY | SECTION_WRITE))
725 abort ();
727 if (flags & SECTION_DECLARED)
729 fprintf (asm_out_file, "\t.section\t%s\n", name);
730 return;
733 fprintf (asm_out_file, "\t.section\t%s,\"awgO\"\n", name);
736 static void
737 ia64_encode_addr_area (tree decl, rtx symbol)
739 int flags;
741 flags = SYMBOL_REF_FLAGS (symbol);
742 switch (ia64_get_addr_area (decl))
744 case ADDR_AREA_NORMAL: break;
745 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
746 default: gcc_unreachable ();
748 SYMBOL_REF_FLAGS (symbol) = flags;
751 static void
752 ia64_encode_section_info (tree decl, rtx rtl, int first)
754 default_encode_section_info (decl, rtl, first);
756 /* Careful not to prod global register variables. */
757 if (TREE_CODE (decl) == VAR_DECL
758 && GET_CODE (DECL_RTL (decl)) == MEM
759 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
760 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
761 ia64_encode_addr_area (decl, XEXP (rtl, 0));
764 /* Return 1 if the operands of a move are ok. */
767 ia64_move_ok (rtx dst, rtx src)
769 /* If we're under init_recog_no_volatile, we'll not be able to use
770 memory_operand. So check the code directly and don't worry about
771 the validity of the underlying address, which should have been
772 checked elsewhere anyway. */
773 if (GET_CODE (dst) != MEM)
774 return 1;
775 if (GET_CODE (src) == MEM)
776 return 0;
777 if (register_operand (src, VOIDmode))
778 return 1;
780 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
781 if (INTEGRAL_MODE_P (GET_MODE (dst)))
782 return src == const0_rtx;
783 else
784 return satisfies_constraint_G (src);
787 /* Return 1 if the operands are ok for a floating point load pair. */
790 ia64_load_pair_ok (rtx dst, rtx src)
792 if (GET_CODE (dst) != REG || !FP_REGNO_P (REGNO (dst)))
793 return 0;
794 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
795 return 0;
796 switch (GET_CODE (XEXP (src, 0)))
798 case REG:
799 case POST_INC:
800 break;
801 case POST_DEC:
802 return 0;
803 case POST_MODIFY:
805 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
807 if (GET_CODE (adjust) != CONST_INT
808 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
809 return 0;
811 break;
812 default:
813 abort ();
815 return 1;
819 addp4_optimize_ok (rtx op1, rtx op2)
821 return (basereg_operand (op1, GET_MODE(op1)) !=
822 basereg_operand (op2, GET_MODE(op2)));
825 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
826 Return the length of the field, or <= 0 on failure. */
829 ia64_depz_field_mask (rtx rop, rtx rshift)
831 unsigned HOST_WIDE_INT op = INTVAL (rop);
832 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
834 /* Get rid of the zero bits we're shifting in. */
835 op >>= shift;
837 /* We must now have a solid block of 1's at bit 0. */
838 return exact_log2 (op + 1);
841 /* Return the TLS model to use for ADDR. */
843 static enum tls_model
844 tls_symbolic_operand_type (rtx addr)
846 enum tls_model tls_kind = TLS_MODEL_NONE;
848 if (GET_CODE (addr) == CONST)
850 if (GET_CODE (XEXP (addr, 0)) == PLUS
851 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
852 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
854 else if (GET_CODE (addr) == SYMBOL_REF)
855 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
857 return tls_kind;
860 /* Return true if X is a constant that is valid for some immediate
861 field in an instruction. */
863 bool
864 ia64_legitimate_constant_p (rtx x)
866 switch (GET_CODE (x))
868 case CONST_INT:
869 case LABEL_REF:
870 return true;
872 case CONST_DOUBLE:
873 if (GET_MODE (x) == VOIDmode || GET_MODE (x) == SFmode
874 || GET_MODE (x) == DFmode)
875 return true;
876 return satisfies_constraint_G (x);
878 case CONST:
879 case SYMBOL_REF:
880 /* ??? Short term workaround for PR 28490. We must make the code here
881 match the code in ia64_expand_move and move_operand, even though they
882 are both technically wrong. */
883 if (tls_symbolic_operand_type (x) == 0)
885 HOST_WIDE_INT addend = 0;
886 rtx op = x;
888 if (GET_CODE (op) == CONST
889 && GET_CODE (XEXP (op, 0)) == PLUS
890 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
892 addend = INTVAL (XEXP (XEXP (op, 0), 1));
893 op = XEXP (XEXP (op, 0), 0);
896 if (any_offset_symbol_operand (op, GET_MODE (op))
897 || function_operand (op, GET_MODE (op)))
898 return true;
899 if (aligned_offset_symbol_operand (op, GET_MODE (op)))
900 return (addend & 0x3fff) == 0;
901 return false;
903 return false;
905 case CONST_VECTOR:
907 enum machine_mode mode = GET_MODE (x);
909 if (mode == V2SFmode)
910 return satisfies_constraint_Y (x);
912 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
913 && GET_MODE_SIZE (mode) <= 8);
916 default:
917 return false;
921 /* Don't allow TLS addresses to get spilled to memory. */
923 static bool
924 ia64_cannot_force_const_mem (rtx x)
926 if (GET_MODE (x) == RFmode)
927 return true;
928 return tls_symbolic_operand_type (x) != 0;
931 /* Expand a symbolic constant load. */
933 bool
934 ia64_expand_load_address (rtx dest, rtx src)
936 gcc_assert (GET_CODE (dest) == REG);
938 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
939 having to pointer-extend the value afterward. Other forms of address
940 computation below are also more natural to compute as 64-bit quantities.
941 If we've been given an SImode destination register, change it. */
942 if (GET_MODE (dest) != Pmode)
943 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest),
944 byte_lowpart_offset (Pmode, GET_MODE (dest)));
946 if (TARGET_NO_PIC)
947 return false;
948 if (small_addr_symbolic_operand (src, VOIDmode))
949 return false;
951 if (TARGET_AUTO_PIC)
952 emit_insn (gen_load_gprel64 (dest, src));
953 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
954 emit_insn (gen_load_fptr (dest, src));
955 else if (sdata_symbolic_operand (src, VOIDmode))
956 emit_insn (gen_load_gprel (dest, src));
957 else
959 HOST_WIDE_INT addend = 0;
960 rtx tmp;
962 /* We did split constant offsets in ia64_expand_move, and we did try
963 to keep them split in move_operand, but we also allowed reload to
964 rematerialize arbitrary constants rather than spill the value to
965 the stack and reload it. So we have to be prepared here to split
966 them apart again. */
967 if (GET_CODE (src) == CONST)
969 HOST_WIDE_INT hi, lo;
971 hi = INTVAL (XEXP (XEXP (src, 0), 1));
972 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
973 hi = hi - lo;
975 if (lo != 0)
977 addend = lo;
978 src = plus_constant (XEXP (XEXP (src, 0), 0), hi);
982 tmp = gen_rtx_HIGH (Pmode, src);
983 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
984 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
986 tmp = gen_rtx_LO_SUM (Pmode, dest, src);
987 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
989 if (addend)
991 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
992 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
996 return true;
999 static GTY(()) rtx gen_tls_tga;
1000 static rtx
1001 gen_tls_get_addr (void)
1003 if (!gen_tls_tga)
1004 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1005 return gen_tls_tga;
1008 static GTY(()) rtx thread_pointer_rtx;
1009 static rtx
1010 gen_thread_pointer (void)
1012 if (!thread_pointer_rtx)
1013 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1014 return thread_pointer_rtx;
1017 static rtx
1018 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
1019 rtx orig_op1, HOST_WIDE_INT addend)
1021 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1022 rtx orig_op0 = op0;
1023 HOST_WIDE_INT addend_lo, addend_hi;
1025 switch (tls_kind)
1027 case TLS_MODEL_GLOBAL_DYNAMIC:
1028 start_sequence ();
1030 tga_op1 = gen_reg_rtx (Pmode);
1031 emit_insn (gen_load_dtpmod (tga_op1, op1));
1033 tga_op2 = gen_reg_rtx (Pmode);
1034 emit_insn (gen_load_dtprel (tga_op2, op1));
1036 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1037 LCT_CONST, Pmode, 2, tga_op1,
1038 Pmode, tga_op2, Pmode);
1040 insns = get_insns ();
1041 end_sequence ();
1043 if (GET_MODE (op0) != Pmode)
1044 op0 = tga_ret;
1045 emit_libcall_block (insns, op0, tga_ret, op1);
1046 break;
1048 case TLS_MODEL_LOCAL_DYNAMIC:
1049 /* ??? This isn't the completely proper way to do local-dynamic
1050 If the call to __tls_get_addr is used only by a single symbol,
1051 then we should (somehow) move the dtprel to the second arg
1052 to avoid the extra add. */
1053 start_sequence ();
1055 tga_op1 = gen_reg_rtx (Pmode);
1056 emit_insn (gen_load_dtpmod (tga_op1, op1));
1058 tga_op2 = const0_rtx;
1060 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1061 LCT_CONST, Pmode, 2, tga_op1,
1062 Pmode, tga_op2, Pmode);
1064 insns = get_insns ();
1065 end_sequence ();
1067 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1068 UNSPEC_LD_BASE);
1069 tmp = gen_reg_rtx (Pmode);
1070 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1072 if (!register_operand (op0, Pmode))
1073 op0 = gen_reg_rtx (Pmode);
1074 if (TARGET_TLS64)
1076 emit_insn (gen_load_dtprel (op0, op1));
1077 emit_insn (gen_adddi3 (op0, tmp, op0));
1079 else
1080 emit_insn (gen_add_dtprel (op0, op1, tmp));
1081 break;
1083 case TLS_MODEL_INITIAL_EXEC:
1084 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1085 addend_hi = addend - addend_lo;
1087 op1 = plus_constant (op1, addend_hi);
1088 addend = addend_lo;
1090 tmp = gen_reg_rtx (Pmode);
1091 emit_insn (gen_load_tprel (tmp, op1));
1093 if (!register_operand (op0, Pmode))
1094 op0 = gen_reg_rtx (Pmode);
1095 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1096 break;
1098 case TLS_MODEL_LOCAL_EXEC:
1099 if (!register_operand (op0, Pmode))
1100 op0 = gen_reg_rtx (Pmode);
1102 op1 = orig_op1;
1103 addend = 0;
1104 if (TARGET_TLS64)
1106 emit_insn (gen_load_tprel (op0, op1));
1107 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1109 else
1110 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1111 break;
1113 default:
1114 gcc_unreachable ();
1117 if (addend)
1118 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1119 orig_op0, 1, OPTAB_DIRECT);
1120 if (orig_op0 == op0)
1121 return NULL_RTX;
1122 if (GET_MODE (orig_op0) == Pmode)
1123 return op0;
1124 return gen_lowpart (GET_MODE (orig_op0), op0);
1128 ia64_expand_move (rtx op0, rtx op1)
1130 enum machine_mode mode = GET_MODE (op0);
1132 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1133 op1 = force_reg (mode, op1);
1135 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1137 HOST_WIDE_INT addend = 0;
1138 enum tls_model tls_kind;
1139 rtx sym = op1;
1141 if (GET_CODE (op1) == CONST
1142 && GET_CODE (XEXP (op1, 0)) == PLUS
1143 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1145 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1146 sym = XEXP (XEXP (op1, 0), 0);
1149 tls_kind = tls_symbolic_operand_type (sym);
1150 if (tls_kind)
1151 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1153 if (any_offset_symbol_operand (sym, mode))
1154 addend = 0;
1155 else if (aligned_offset_symbol_operand (sym, mode))
1157 HOST_WIDE_INT addend_lo, addend_hi;
1159 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1160 addend_hi = addend - addend_lo;
1162 if (addend_lo != 0)
1164 op1 = plus_constant (sym, addend_hi);
1165 addend = addend_lo;
1167 else
1168 addend = 0;
1170 else
1171 op1 = sym;
1173 if (reload_completed)
1175 /* We really should have taken care of this offset earlier. */
1176 gcc_assert (addend == 0);
1177 if (ia64_expand_load_address (op0, op1))
1178 return NULL_RTX;
1181 if (addend)
1183 rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode);
1185 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1187 op1 = expand_simple_binop (mode, PLUS, subtarget,
1188 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1189 if (op0 == op1)
1190 return NULL_RTX;
1194 return op1;
1197 /* Split a move from OP1 to OP0 conditional on COND. */
1199 void
1200 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1202 rtx insn, first = get_last_insn ();
1204 emit_move_insn (op0, op1);
1206 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1207 if (INSN_P (insn))
1208 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1209 PATTERN (insn));
1212 /* Split a post-reload TImode or TFmode reference into two DImode
1213 components. This is made extra difficult by the fact that we do
1214 not get any scratch registers to work with, because reload cannot
1215 be prevented from giving us a scratch that overlaps the register
1216 pair involved. So instead, when addressing memory, we tweak the
1217 pointer register up and back down with POST_INCs. Or up and not
1218 back down when we can get away with it.
1220 REVERSED is true when the loads must be done in reversed order
1221 (high word first) for correctness. DEAD is true when the pointer
1222 dies with the second insn we generate and therefore the second
1223 address must not carry a postmodify.
1225 May return an insn which is to be emitted after the moves. */
1227 static rtx
1228 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1230 rtx fixup = 0;
1232 switch (GET_CODE (in))
1234 case REG:
1235 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1236 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1237 break;
1239 case CONST_INT:
1240 case CONST_DOUBLE:
1241 /* Cannot occur reversed. */
1242 gcc_assert (!reversed);
1244 if (GET_MODE (in) != TFmode)
1245 split_double (in, &out[0], &out[1]);
1246 else
1247 /* split_double does not understand how to split a TFmode
1248 quantity into a pair of DImode constants. */
1250 REAL_VALUE_TYPE r;
1251 unsigned HOST_WIDE_INT p[2];
1252 long l[4]; /* TFmode is 128 bits */
1254 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1255 real_to_target (l, &r, TFmode);
1257 if (FLOAT_WORDS_BIG_ENDIAN)
1259 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1260 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1262 else
1264 p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1265 p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1267 out[0] = GEN_INT (p[0]);
1268 out[1] = GEN_INT (p[1]);
1270 break;
1272 case MEM:
1274 rtx base = XEXP (in, 0);
1275 rtx offset;
1277 switch (GET_CODE (base))
1279 case REG:
1280 if (!reversed)
1282 out[0] = adjust_automodify_address
1283 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1284 out[1] = adjust_automodify_address
1285 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1287 else
1289 /* Reversal requires a pre-increment, which can only
1290 be done as a separate insn. */
1291 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1292 out[0] = adjust_automodify_address
1293 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1294 out[1] = adjust_address (in, DImode, 0);
1296 break;
1298 case POST_INC:
1299 gcc_assert (!reversed && !dead);
1301 /* Just do the increment in two steps. */
1302 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1303 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1304 break;
1306 case POST_DEC:
1307 gcc_assert (!reversed && !dead);
1309 /* Add 8, subtract 24. */
1310 base = XEXP (base, 0);
1311 out[0] = adjust_automodify_address
1312 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1313 out[1] = adjust_automodify_address
1314 (in, DImode,
1315 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1317 break;
1319 case POST_MODIFY:
1320 gcc_assert (!reversed && !dead);
1322 /* Extract and adjust the modification. This case is
1323 trickier than the others, because we might have an
1324 index register, or we might have a combined offset that
1325 doesn't fit a signed 9-bit displacement field. We can
1326 assume the incoming expression is already legitimate. */
1327 offset = XEXP (base, 1);
1328 base = XEXP (base, 0);
1330 out[0] = adjust_automodify_address
1331 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1333 if (GET_CODE (XEXP (offset, 1)) == REG)
1335 /* Can't adjust the postmodify to match. Emit the
1336 original, then a separate addition insn. */
1337 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1338 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1340 else
1342 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1343 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1345 /* Again the postmodify cannot be made to match,
1346 but in this case it's more efficient to get rid
1347 of the postmodify entirely and fix up with an
1348 add insn. */
1349 out[1] = adjust_automodify_address (in, DImode, base, 8);
1350 fixup = gen_adddi3
1351 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1353 else
1355 /* Combined offset still fits in the displacement field.
1356 (We cannot overflow it at the high end.) */
1357 out[1] = adjust_automodify_address
1358 (in, DImode, gen_rtx_POST_MODIFY
1359 (Pmode, base, gen_rtx_PLUS
1360 (Pmode, base,
1361 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1365 break;
1367 default:
1368 gcc_unreachable ();
1370 break;
1373 default:
1374 gcc_unreachable ();
1377 return fixup;
1380 /* Split a TImode or TFmode move instruction after reload.
1381 This is used by *movtf_internal and *movti_internal. */
1382 void
1383 ia64_split_tmode_move (rtx operands[])
1385 rtx in[2], out[2], insn;
1386 rtx fixup[2];
1387 bool dead = false;
1388 bool reversed = false;
1390 /* It is possible for reload to decide to overwrite a pointer with
1391 the value it points to. In that case we have to do the loads in
1392 the appropriate order so that the pointer is not destroyed too
1393 early. Also we must not generate a postmodify for that second
1394 load, or rws_access_regno will die. */
1395 if (GET_CODE (operands[1]) == MEM
1396 && reg_overlap_mentioned_p (operands[0], operands[1]))
1398 rtx base = XEXP (operands[1], 0);
1399 while (GET_CODE (base) != REG)
1400 base = XEXP (base, 0);
1402 if (REGNO (base) == REGNO (operands[0]))
1403 reversed = true;
1404 dead = true;
1406 /* Another reason to do the moves in reversed order is if the first
1407 element of the target register pair is also the second element of
1408 the source register pair. */
1409 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1410 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1411 reversed = true;
1413 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1414 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1416 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1417 if (GET_CODE (EXP) == MEM \
1418 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1419 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1420 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1421 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1423 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1424 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1425 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1427 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1428 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1429 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1431 if (fixup[0])
1432 emit_insn (fixup[0]);
1433 if (fixup[1])
1434 emit_insn (fixup[1]);
1436 #undef MAYBE_ADD_REG_INC_NOTE
1439 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1440 through memory plus an extra GR scratch register. Except that you can
1441 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1442 SECONDARY_RELOAD_CLASS, but not both.
1444 We got into problems in the first place by allowing a construct like
1445 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1446 This solution attempts to prevent this situation from occurring. When
1447 we see something like the above, we spill the inner register to memory. */
1449 static rtx
1450 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1452 if (GET_CODE (in) == SUBREG
1453 && GET_MODE (SUBREG_REG (in)) == TImode
1454 && GET_CODE (SUBREG_REG (in)) == REG)
1456 rtx memt = assign_stack_temp (TImode, 16, 0);
1457 emit_move_insn (memt, SUBREG_REG (in));
1458 return adjust_address (memt, mode, 0);
1460 else if (force && GET_CODE (in) == REG)
1462 rtx memx = assign_stack_temp (mode, 16, 0);
1463 emit_move_insn (memx, in);
1464 return memx;
1466 else
1467 return in;
1470 /* Expand the movxf or movrf pattern (MODE says which) with the given
1471 OPERANDS, returning true if the pattern should then invoke
1472 DONE. */
1474 bool
1475 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1477 rtx op0 = operands[0];
1479 if (GET_CODE (op0) == SUBREG)
1480 op0 = SUBREG_REG (op0);
1482 /* We must support XFmode loads into general registers for stdarg/vararg,
1483 unprototyped calls, and a rare case where a long double is passed as
1484 an argument after a float HFA fills the FP registers. We split them into
1485 DImode loads for convenience. We also need to support XFmode stores
1486 for the last case. This case does not happen for stdarg/vararg routines,
1487 because we do a block store to memory of unnamed arguments. */
1489 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1491 rtx out[2];
1493 /* We're hoping to transform everything that deals with XFmode
1494 quantities and GR registers early in the compiler. */
1495 gcc_assert (can_create_pseudo_p ());
1497 /* Struct to register can just use TImode instead. */
1498 if ((GET_CODE (operands[1]) == SUBREG
1499 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1500 || (GET_CODE (operands[1]) == REG
1501 && GR_REGNO_P (REGNO (operands[1]))))
1503 rtx op1 = operands[1];
1505 if (GET_CODE (op1) == SUBREG)
1506 op1 = SUBREG_REG (op1);
1507 else
1508 op1 = gen_rtx_REG (TImode, REGNO (op1));
1510 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1511 return true;
1514 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1516 /* Don't word-swap when reading in the constant. */
1517 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1518 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1519 0, mode));
1520 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1521 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1522 0, mode));
1523 return true;
1526 /* If the quantity is in a register not known to be GR, spill it. */
1527 if (register_operand (operands[1], mode))
1528 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1530 gcc_assert (GET_CODE (operands[1]) == MEM);
1532 /* Don't word-swap when reading in the value. */
1533 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1534 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1536 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1537 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1538 return true;
1541 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1543 /* We're hoping to transform everything that deals with XFmode
1544 quantities and GR registers early in the compiler. */
1545 gcc_assert (can_create_pseudo_p ());
1547 /* Op0 can't be a GR_REG here, as that case is handled above.
1548 If op0 is a register, then we spill op1, so that we now have a
1549 MEM operand. This requires creating an XFmode subreg of a TImode reg
1550 to force the spill. */
1551 if (register_operand (operands[0], mode))
1553 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1554 op1 = gen_rtx_SUBREG (mode, op1, 0);
1555 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1558 else
1560 rtx in[2];
1562 gcc_assert (GET_CODE (operands[0]) == MEM);
1564 /* Don't word-swap when writing out the value. */
1565 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1566 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1568 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1569 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1570 return true;
1574 if (!reload_in_progress && !reload_completed)
1576 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1578 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1580 rtx memt, memx, in = operands[1];
1581 if (CONSTANT_P (in))
1582 in = validize_mem (force_const_mem (mode, in));
1583 if (GET_CODE (in) == MEM)
1584 memt = adjust_address (in, TImode, 0);
1585 else
1587 memt = assign_stack_temp (TImode, 16, 0);
1588 memx = adjust_address (memt, mode, 0);
1589 emit_move_insn (memx, in);
1591 emit_move_insn (op0, memt);
1592 return true;
1595 if (!ia64_move_ok (operands[0], operands[1]))
1596 operands[1] = force_reg (mode, operands[1]);
1599 return false;
1602 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1603 with the expression that holds the compare result (in VOIDmode). */
1605 static GTY(()) rtx cmptf_libfunc;
1607 void
1608 ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1)
1610 enum rtx_code code = GET_CODE (*expr);
1611 rtx cmp;
1613 /* If we have a BImode input, then we already have a compare result, and
1614 do not need to emit another comparison. */
1615 if (GET_MODE (*op0) == BImode)
1617 gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx);
1618 cmp = *op0;
1620 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1621 magic number as its third argument, that indicates what to do.
1622 The return value is an integer to be compared against zero. */
1623 else if (TARGET_HPUX && GET_MODE (*op0) == TFmode)
1625 enum qfcmp_magic {
1626 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1627 QCMP_UNORD = 2,
1628 QCMP_EQ = 4,
1629 QCMP_LT = 8,
1630 QCMP_GT = 16
1632 int magic;
1633 enum rtx_code ncode;
1634 rtx ret, insns;
1636 gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode);
1637 switch (code)
1639 /* 1 = equal, 0 = not equal. Equality operators do
1640 not raise FP_INVALID when given an SNaN operand. */
1641 case EQ: magic = QCMP_EQ; ncode = NE; break;
1642 case NE: magic = QCMP_EQ; ncode = EQ; break;
1643 /* isunordered() from C99. */
1644 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1645 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1646 /* Relational operators raise FP_INVALID when given
1647 an SNaN operand. */
1648 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1649 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1650 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1651 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1652 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1653 Expanders for buneq etc. weuld have to be added to ia64.md
1654 for this to be useful. */
1655 default: gcc_unreachable ();
1658 start_sequence ();
1660 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1661 *op0, TFmode, *op1, TFmode,
1662 GEN_INT (magic), DImode);
1663 cmp = gen_reg_rtx (BImode);
1664 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1665 gen_rtx_fmt_ee (ncode, BImode,
1666 ret, const0_rtx)));
1668 insns = get_insns ();
1669 end_sequence ();
1671 emit_libcall_block (insns, cmp, cmp,
1672 gen_rtx_fmt_ee (code, BImode, *op0, *op1));
1673 code = NE;
1675 else
1677 cmp = gen_reg_rtx (BImode);
1678 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1679 gen_rtx_fmt_ee (code, BImode, *op0, *op1)));
1680 code = NE;
1683 *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx);
1684 *op0 = cmp;
1685 *op1 = const0_rtx;
1688 /* Generate an integral vector comparison. Return true if the condition has
1689 been reversed, and so the sense of the comparison should be inverted. */
1691 static bool
1692 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1693 rtx dest, rtx op0, rtx op1)
1695 bool negate = false;
1696 rtx x;
1698 /* Canonicalize the comparison to EQ, GT, GTU. */
1699 switch (code)
1701 case EQ:
1702 case GT:
1703 case GTU:
1704 break;
1706 case NE:
1707 case LE:
1708 case LEU:
1709 code = reverse_condition (code);
1710 negate = true;
1711 break;
1713 case GE:
1714 case GEU:
1715 code = reverse_condition (code);
1716 negate = true;
1717 /* FALLTHRU */
1719 case LT:
1720 case LTU:
1721 code = swap_condition (code);
1722 x = op0, op0 = op1, op1 = x;
1723 break;
1725 default:
1726 gcc_unreachable ();
1729 /* Unsigned parallel compare is not supported by the hardware. Play some
1730 tricks to turn this into a signed comparison against 0. */
1731 if (code == GTU)
1733 switch (mode)
1735 case V2SImode:
1737 rtx t1, t2, mask;
1739 /* Subtract (-(INT MAX) - 1) from both operands to make
1740 them signed. */
1741 mask = GEN_INT (0x80000000);
1742 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1743 mask = force_reg (mode, mask);
1744 t1 = gen_reg_rtx (mode);
1745 emit_insn (gen_subv2si3 (t1, op0, mask));
1746 t2 = gen_reg_rtx (mode);
1747 emit_insn (gen_subv2si3 (t2, op1, mask));
1748 op0 = t1;
1749 op1 = t2;
1750 code = GT;
1752 break;
1754 case V8QImode:
1755 case V4HImode:
1756 /* Perform a parallel unsigned saturating subtraction. */
1757 x = gen_reg_rtx (mode);
1758 emit_insn (gen_rtx_SET (VOIDmode, x,
1759 gen_rtx_US_MINUS (mode, op0, op1)));
1761 code = EQ;
1762 op0 = x;
1763 op1 = CONST0_RTX (mode);
1764 negate = !negate;
1765 break;
1767 default:
1768 gcc_unreachable ();
1772 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1773 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1775 return negate;
1778 /* Emit an integral vector conditional move. */
1780 void
1781 ia64_expand_vecint_cmov (rtx operands[])
1783 enum machine_mode mode = GET_MODE (operands[0]);
1784 enum rtx_code code = GET_CODE (operands[3]);
1785 bool negate;
1786 rtx cmp, x, ot, of;
1788 cmp = gen_reg_rtx (mode);
1789 negate = ia64_expand_vecint_compare (code, mode, cmp,
1790 operands[4], operands[5]);
1792 ot = operands[1+negate];
1793 of = operands[2-negate];
1795 if (ot == CONST0_RTX (mode))
1797 if (of == CONST0_RTX (mode))
1799 emit_move_insn (operands[0], ot);
1800 return;
1803 x = gen_rtx_NOT (mode, cmp);
1804 x = gen_rtx_AND (mode, x, of);
1805 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1807 else if (of == CONST0_RTX (mode))
1809 x = gen_rtx_AND (mode, cmp, ot);
1810 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1812 else
1814 rtx t, f;
1816 t = gen_reg_rtx (mode);
1817 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1818 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1820 f = gen_reg_rtx (mode);
1821 x = gen_rtx_NOT (mode, cmp);
1822 x = gen_rtx_AND (mode, x, operands[2-negate]);
1823 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1825 x = gen_rtx_IOR (mode, t, f);
1826 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1830 /* Emit an integral vector min or max operation. Return true if all done. */
1832 bool
1833 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1834 rtx operands[])
1836 rtx xops[6];
1838 /* These four combinations are supported directly. */
1839 if (mode == V8QImode && (code == UMIN || code == UMAX))
1840 return false;
1841 if (mode == V4HImode && (code == SMIN || code == SMAX))
1842 return false;
1844 /* This combination can be implemented with only saturating subtraction. */
1845 if (mode == V4HImode && code == UMAX)
1847 rtx x, tmp = gen_reg_rtx (mode);
1849 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1850 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
1852 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
1853 return true;
1856 /* Everything else implemented via vector comparisons. */
1857 xops[0] = operands[0];
1858 xops[4] = xops[1] = operands[1];
1859 xops[5] = xops[2] = operands[2];
1861 switch (code)
1863 case UMIN:
1864 code = LTU;
1865 break;
1866 case UMAX:
1867 code = GTU;
1868 break;
1869 case SMIN:
1870 code = LT;
1871 break;
1872 case SMAX:
1873 code = GT;
1874 break;
1875 default:
1876 gcc_unreachable ();
1878 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1880 ia64_expand_vecint_cmov (xops);
1881 return true;
1884 /* Emit an integral vector widening sum operations. */
1886 void
1887 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
1889 rtx l, h, x, s;
1890 enum machine_mode wmode, mode;
1891 rtx (*unpack_l) (rtx, rtx, rtx);
1892 rtx (*unpack_h) (rtx, rtx, rtx);
1893 rtx (*plus) (rtx, rtx, rtx);
1895 wmode = GET_MODE (operands[0]);
1896 mode = GET_MODE (operands[1]);
1898 switch (mode)
1900 case V8QImode:
1901 unpack_l = gen_unpack1_l;
1902 unpack_h = gen_unpack1_h;
1903 plus = gen_addv4hi3;
1904 break;
1905 case V4HImode:
1906 unpack_l = gen_unpack2_l;
1907 unpack_h = gen_unpack2_h;
1908 plus = gen_addv2si3;
1909 break;
1910 default:
1911 gcc_unreachable ();
1914 /* Fill in x with the sign extension of each element in op1. */
1915 if (unsignedp)
1916 x = CONST0_RTX (mode);
1917 else
1919 bool neg;
1921 x = gen_reg_rtx (mode);
1923 neg = ia64_expand_vecint_compare (LT, mode, x, operands[1],
1924 CONST0_RTX (mode));
1925 gcc_assert (!neg);
1928 l = gen_reg_rtx (wmode);
1929 h = gen_reg_rtx (wmode);
1930 s = gen_reg_rtx (wmode);
1932 emit_insn (unpack_l (gen_lowpart (mode, l), operands[1], x));
1933 emit_insn (unpack_h (gen_lowpart (mode, h), operands[1], x));
1934 emit_insn (plus (s, l, operands[2]));
1935 emit_insn (plus (operands[0], h, s));
1938 /* Emit a signed or unsigned V8QI dot product operation. */
1940 void
1941 ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp)
1943 rtx l1, l2, h1, h2, x1, x2, p1, p2, p3, p4, s1, s2, s3;
1945 /* Fill in x1 and x2 with the sign extension of each element. */
1946 if (unsignedp)
1947 x1 = x2 = CONST0_RTX (V8QImode);
1948 else
1950 bool neg;
1952 x1 = gen_reg_rtx (V8QImode);
1953 x2 = gen_reg_rtx (V8QImode);
1955 neg = ia64_expand_vecint_compare (LT, V8QImode, x1, operands[1],
1956 CONST0_RTX (V8QImode));
1957 gcc_assert (!neg);
1958 neg = ia64_expand_vecint_compare (LT, V8QImode, x2, operands[2],
1959 CONST0_RTX (V8QImode));
1960 gcc_assert (!neg);
1963 l1 = gen_reg_rtx (V4HImode);
1964 l2 = gen_reg_rtx (V4HImode);
1965 h1 = gen_reg_rtx (V4HImode);
1966 h2 = gen_reg_rtx (V4HImode);
1968 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l1), operands[1], x1));
1969 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l2), operands[2], x2));
1970 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h1), operands[1], x1));
1971 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h2), operands[2], x2));
1973 p1 = gen_reg_rtx (V2SImode);
1974 p2 = gen_reg_rtx (V2SImode);
1975 p3 = gen_reg_rtx (V2SImode);
1976 p4 = gen_reg_rtx (V2SImode);
1977 emit_insn (gen_pmpy2_r (p1, l1, l2));
1978 emit_insn (gen_pmpy2_l (p2, l1, l2));
1979 emit_insn (gen_pmpy2_r (p3, h1, h2));
1980 emit_insn (gen_pmpy2_l (p4, h1, h2));
1982 s1 = gen_reg_rtx (V2SImode);
1983 s2 = gen_reg_rtx (V2SImode);
1984 s3 = gen_reg_rtx (V2SImode);
1985 emit_insn (gen_addv2si3 (s1, p1, p2));
1986 emit_insn (gen_addv2si3 (s2, p3, p4));
1987 emit_insn (gen_addv2si3 (s3, s1, operands[3]));
1988 emit_insn (gen_addv2si3 (operands[0], s2, s3));
1991 /* Emit the appropriate sequence for a call. */
1993 void
1994 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
1995 int sibcall_p)
1997 rtx insn, b0;
1999 addr = XEXP (addr, 0);
2000 addr = convert_memory_address (DImode, addr);
2001 b0 = gen_rtx_REG (DImode, R_BR (0));
2003 /* ??? Should do this for functions known to bind local too. */
2004 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
2006 if (sibcall_p)
2007 insn = gen_sibcall_nogp (addr);
2008 else if (! retval)
2009 insn = gen_call_nogp (addr, b0);
2010 else
2011 insn = gen_call_value_nogp (retval, addr, b0);
2012 insn = emit_call_insn (insn);
2014 else
2016 if (sibcall_p)
2017 insn = gen_sibcall_gp (addr);
2018 else if (! retval)
2019 insn = gen_call_gp (addr, b0);
2020 else
2021 insn = gen_call_value_gp (retval, addr, b0);
2022 insn = emit_call_insn (insn);
2024 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2027 if (sibcall_p)
2028 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
2030 if (TARGET_ABI_OPEN_VMS)
2031 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2032 gen_rtx_REG (DImode, GR_REG (25)));
2035 static void
2036 reg_emitted (enum ia64_frame_regs r)
2038 if (emitted_frame_related_regs[r] == 0)
2039 emitted_frame_related_regs[r] = current_frame_info.r[r];
2040 else
2041 gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]);
2044 static int
2045 get_reg (enum ia64_frame_regs r)
2047 reg_emitted (r);
2048 return current_frame_info.r[r];
2051 static bool
2052 is_emitted (int regno)
2054 unsigned int r;
2056 for (r = reg_fp; r < number_of_ia64_frame_regs; r++)
2057 if (emitted_frame_related_regs[r] == regno)
2058 return true;
2059 return false;
2062 void
2063 ia64_reload_gp (void)
2065 rtx tmp;
2067 if (current_frame_info.r[reg_save_gp])
2069 tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
2071 else
2073 HOST_WIDE_INT offset;
2074 rtx offset_r;
2076 offset = (current_frame_info.spill_cfa_off
2077 + current_frame_info.spill_size);
2078 if (frame_pointer_needed)
2080 tmp = hard_frame_pointer_rtx;
2081 offset = -offset;
2083 else
2085 tmp = stack_pointer_rtx;
2086 offset = current_frame_info.total_size - offset;
2089 offset_r = GEN_INT (offset);
2090 if (satisfies_constraint_I (offset_r))
2091 emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r));
2092 else
2094 emit_move_insn (pic_offset_table_rtx, offset_r);
2095 emit_insn (gen_adddi3 (pic_offset_table_rtx,
2096 pic_offset_table_rtx, tmp));
2099 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2102 emit_move_insn (pic_offset_table_rtx, tmp);
2105 void
2106 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2107 rtx scratch_b, int noreturn_p, int sibcall_p)
2109 rtx insn;
2110 bool is_desc = false;
2112 /* If we find we're calling through a register, then we're actually
2113 calling through a descriptor, so load up the values. */
2114 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2116 rtx tmp;
2117 bool addr_dead_p;
2119 /* ??? We are currently constrained to *not* use peep2, because
2120 we can legitimately change the global lifetime of the GP
2121 (in the form of killing where previously live). This is
2122 because a call through a descriptor doesn't use the previous
2123 value of the GP, while a direct call does, and we do not
2124 commit to either form until the split here.
2126 That said, this means that we lack precise life info for
2127 whether ADDR is dead after this call. This is not terribly
2128 important, since we can fix things up essentially for free
2129 with the POST_DEC below, but it's nice to not use it when we
2130 can immediately tell it's not necessary. */
2131 addr_dead_p = ((noreturn_p || sibcall_p
2132 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2133 REGNO (addr)))
2134 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2136 /* Load the code address into scratch_b. */
2137 tmp = gen_rtx_POST_INC (Pmode, addr);
2138 tmp = gen_rtx_MEM (Pmode, tmp);
2139 emit_move_insn (scratch_r, tmp);
2140 emit_move_insn (scratch_b, scratch_r);
2142 /* Load the GP address. If ADDR is not dead here, then we must
2143 revert the change made above via the POST_INCREMENT. */
2144 if (!addr_dead_p)
2145 tmp = gen_rtx_POST_DEC (Pmode, addr);
2146 else
2147 tmp = addr;
2148 tmp = gen_rtx_MEM (Pmode, tmp);
2149 emit_move_insn (pic_offset_table_rtx, tmp);
2151 is_desc = true;
2152 addr = scratch_b;
2155 if (sibcall_p)
2156 insn = gen_sibcall_nogp (addr);
2157 else if (retval)
2158 insn = gen_call_value_nogp (retval, addr, retaddr);
2159 else
2160 insn = gen_call_nogp (addr, retaddr);
2161 emit_call_insn (insn);
2163 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2164 ia64_reload_gp ();
2167 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2169 This differs from the generic code in that we know about the zero-extending
2170 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2171 also know that ld.acq+cmpxchg.rel equals a full barrier.
2173 The loop we want to generate looks like
2175 cmp_reg = mem;
2176 label:
2177 old_reg = cmp_reg;
2178 new_reg = cmp_reg op val;
2179 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2180 if (cmp_reg != old_reg)
2181 goto label;
2183 Note that we only do the plain load from memory once. Subsequent
2184 iterations use the value loaded by the compare-and-swap pattern. */
2186 void
2187 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2188 rtx old_dst, rtx new_dst)
2190 enum machine_mode mode = GET_MODE (mem);
2191 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2192 enum insn_code icode;
2194 /* Special case for using fetchadd. */
2195 if ((mode == SImode || mode == DImode)
2196 && (code == PLUS || code == MINUS)
2197 && fetchadd_operand (val, mode))
2199 if (code == MINUS)
2200 val = GEN_INT (-INTVAL (val));
2202 if (!old_dst)
2203 old_dst = gen_reg_rtx (mode);
2205 emit_insn (gen_memory_barrier ());
2207 if (mode == SImode)
2208 icode = CODE_FOR_fetchadd_acq_si;
2209 else
2210 icode = CODE_FOR_fetchadd_acq_di;
2211 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2213 if (new_dst)
2215 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2216 true, OPTAB_WIDEN);
2217 if (new_reg != new_dst)
2218 emit_move_insn (new_dst, new_reg);
2220 return;
2223 /* Because of the volatile mem read, we get an ld.acq, which is the
2224 front half of the full barrier. The end half is the cmpxchg.rel. */
2225 gcc_assert (MEM_VOLATILE_P (mem));
2227 old_reg = gen_reg_rtx (DImode);
2228 cmp_reg = gen_reg_rtx (DImode);
2229 label = gen_label_rtx ();
2231 if (mode != DImode)
2233 val = simplify_gen_subreg (DImode, val, mode, 0);
2234 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2236 else
2237 emit_move_insn (cmp_reg, mem);
2239 emit_label (label);
2241 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2242 emit_move_insn (old_reg, cmp_reg);
2243 emit_move_insn (ar_ccv, cmp_reg);
2245 if (old_dst)
2246 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2248 new_reg = cmp_reg;
2249 if (code == NOT)
2251 new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2252 true, OPTAB_DIRECT);
2253 new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2255 else
2256 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2257 true, OPTAB_DIRECT);
2259 if (mode != DImode)
2260 new_reg = gen_lowpart (mode, new_reg);
2261 if (new_dst)
2262 emit_move_insn (new_dst, new_reg);
2264 switch (mode)
2266 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2267 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2268 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2269 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2270 default:
2271 gcc_unreachable ();
2274 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2276 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2279 /* Begin the assembly file. */
2281 static void
2282 ia64_file_start (void)
2284 /* Variable tracking should be run after all optimizations which change order
2285 of insns. It also needs a valid CFG. This can't be done in
2286 ia64_override_options, because flag_var_tracking is finalized after
2287 that. */
2288 ia64_flag_var_tracking = flag_var_tracking;
2289 flag_var_tracking = 0;
2291 default_file_start ();
2292 emit_safe_across_calls ();
2295 void
2296 emit_safe_across_calls (void)
2298 unsigned int rs, re;
2299 int out_state;
2301 rs = 1;
2302 out_state = 0;
2303 while (1)
2305 while (rs < 64 && call_used_regs[PR_REG (rs)])
2306 rs++;
2307 if (rs >= 64)
2308 break;
2309 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2310 continue;
2311 if (out_state == 0)
2313 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2314 out_state = 1;
2316 else
2317 fputc (',', asm_out_file);
2318 if (re == rs + 1)
2319 fprintf (asm_out_file, "p%u", rs);
2320 else
2321 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2322 rs = re + 1;
2324 if (out_state)
2325 fputc ('\n', asm_out_file);
2328 /* Globalize a declaration. */
2330 static void
2331 ia64_globalize_decl_name (FILE * stream, tree decl)
2333 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2334 tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl));
2335 if (version_attr)
2337 tree v = TREE_VALUE (TREE_VALUE (version_attr));
2338 const char *p = TREE_STRING_POINTER (v);
2339 fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p);
2341 targetm.asm_out.globalize_label (stream, name);
2342 if (TREE_CODE (decl) == FUNCTION_DECL)
2343 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function");
2346 /* Helper function for ia64_compute_frame_size: find an appropriate general
2347 register to spill some special register to. SPECIAL_SPILL_MASK contains
2348 bits in GR0 to GR31 that have already been allocated by this routine.
2349 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2351 static int
2352 find_gr_spill (enum ia64_frame_regs r, int try_locals)
2354 int regno;
2356 if (emitted_frame_related_regs[r] != 0)
2358 regno = emitted_frame_related_regs[r];
2359 if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed)
2360 && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1)
2361 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2362 else if (current_function_is_leaf
2363 && regno >= GR_REG (1) && regno <= GR_REG (31))
2364 current_frame_info.gr_used_mask |= 1 << regno;
2366 return regno;
2369 /* If this is a leaf function, first try an otherwise unused
2370 call-clobbered register. */
2371 if (current_function_is_leaf)
2373 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2374 if (! df_regs_ever_live_p (regno)
2375 && call_used_regs[regno]
2376 && ! fixed_regs[regno]
2377 && ! global_regs[regno]
2378 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0
2379 && ! is_emitted (regno))
2381 current_frame_info.gr_used_mask |= 1 << regno;
2382 return regno;
2386 if (try_locals)
2388 regno = current_frame_info.n_local_regs;
2389 /* If there is a frame pointer, then we can't use loc79, because
2390 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2391 reg_name switching code in ia64_expand_prologue. */
2392 while (regno < (80 - frame_pointer_needed))
2393 if (! is_emitted (LOC_REG (regno++)))
2395 current_frame_info.n_local_regs = regno;
2396 return LOC_REG (regno - 1);
2400 /* Failed to find a general register to spill to. Must use stack. */
2401 return 0;
2404 /* In order to make for nice schedules, we try to allocate every temporary
2405 to a different register. We must of course stay away from call-saved,
2406 fixed, and global registers. We must also stay away from registers
2407 allocated in current_frame_info.gr_used_mask, since those include regs
2408 used all through the prologue.
2410 Any register allocated here must be used immediately. The idea is to
2411 aid scheduling, not to solve data flow problems. */
2413 static int last_scratch_gr_reg;
2415 static int
2416 next_scratch_gr_reg (void)
2418 int i, regno;
2420 for (i = 0; i < 32; ++i)
2422 regno = (last_scratch_gr_reg + i + 1) & 31;
2423 if (call_used_regs[regno]
2424 && ! fixed_regs[regno]
2425 && ! global_regs[regno]
2426 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2428 last_scratch_gr_reg = regno;
2429 return regno;
2433 /* There must be _something_ available. */
2434 gcc_unreachable ();
2437 /* Helper function for ia64_compute_frame_size, called through
2438 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2440 static void
2441 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2443 unsigned int regno = REGNO (reg);
2444 if (regno < 32)
2446 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2447 for (i = 0; i < n; ++i)
2448 current_frame_info.gr_used_mask |= 1 << (regno + i);
2453 /* Returns the number of bytes offset between the frame pointer and the stack
2454 pointer for the current function. SIZE is the number of bytes of space
2455 needed for local variables. */
2457 static void
2458 ia64_compute_frame_size (HOST_WIDE_INT size)
2460 HOST_WIDE_INT total_size;
2461 HOST_WIDE_INT spill_size = 0;
2462 HOST_WIDE_INT extra_spill_size = 0;
2463 HOST_WIDE_INT pretend_args_size;
2464 HARD_REG_SET mask;
2465 int n_spilled = 0;
2466 int spilled_gr_p = 0;
2467 int spilled_fr_p = 0;
2468 unsigned int regno;
2469 int min_regno;
2470 int max_regno;
2471 int i;
2473 if (current_frame_info.initialized)
2474 return;
2476 memset (&current_frame_info, 0, sizeof current_frame_info);
2477 CLEAR_HARD_REG_SET (mask);
2479 /* Don't allocate scratches to the return register. */
2480 diddle_return_value (mark_reg_gr_used_mask, NULL);
2482 /* Don't allocate scratches to the EH scratch registers. */
2483 if (cfun->machine->ia64_eh_epilogue_sp)
2484 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2485 if (cfun->machine->ia64_eh_epilogue_bsp)
2486 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2488 /* Find the size of the register stack frame. We have only 80 local
2489 registers, because we reserve 8 for the inputs and 8 for the
2490 outputs. */
2492 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2493 since we'll be adjusting that down later. */
2494 regno = LOC_REG (78) + ! frame_pointer_needed;
2495 for (; regno >= LOC_REG (0); regno--)
2496 if (df_regs_ever_live_p (regno) && !is_emitted (regno))
2497 break;
2498 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2500 /* For functions marked with the syscall_linkage attribute, we must mark
2501 all eight input registers as in use, so that locals aren't visible to
2502 the caller. */
2504 if (cfun->machine->n_varargs > 0
2505 || lookup_attribute ("syscall_linkage",
2506 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2507 current_frame_info.n_input_regs = 8;
2508 else
2510 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2511 if (df_regs_ever_live_p (regno))
2512 break;
2513 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2516 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2517 if (df_regs_ever_live_p (regno))
2518 break;
2519 i = regno - OUT_REG (0) + 1;
2521 #ifndef PROFILE_HOOK
2522 /* When -p profiling, we need one output register for the mcount argument.
2523 Likewise for -a profiling for the bb_init_func argument. For -ax
2524 profiling, we need two output registers for the two bb_init_trace_func
2525 arguments. */
2526 if (crtl->profile)
2527 i = MAX (i, 1);
2528 #endif
2529 current_frame_info.n_output_regs = i;
2531 /* ??? No rotating register support yet. */
2532 current_frame_info.n_rotate_regs = 0;
2534 /* Discover which registers need spilling, and how much room that
2535 will take. Begin with floating point and general registers,
2536 which will always wind up on the stack. */
2538 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2539 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2541 SET_HARD_REG_BIT (mask, regno);
2542 spill_size += 16;
2543 n_spilled += 1;
2544 spilled_fr_p = 1;
2547 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2548 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2550 SET_HARD_REG_BIT (mask, regno);
2551 spill_size += 8;
2552 n_spilled += 1;
2553 spilled_gr_p = 1;
2556 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2557 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2559 SET_HARD_REG_BIT (mask, regno);
2560 spill_size += 8;
2561 n_spilled += 1;
2564 /* Now come all special registers that might get saved in other
2565 general registers. */
2567 if (frame_pointer_needed)
2569 current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1);
2570 /* If we did not get a register, then we take LOC79. This is guaranteed
2571 to be free, even if regs_ever_live is already set, because this is
2572 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2573 as we don't count loc79 above. */
2574 if (current_frame_info.r[reg_fp] == 0)
2576 current_frame_info.r[reg_fp] = LOC_REG (79);
2577 current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1;
2581 if (! current_function_is_leaf)
2583 /* Emit a save of BR0 if we call other functions. Do this even
2584 if this function doesn't return, as EH depends on this to be
2585 able to unwind the stack. */
2586 SET_HARD_REG_BIT (mask, BR_REG (0));
2588 current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1);
2589 if (current_frame_info.r[reg_save_b0] == 0)
2591 extra_spill_size += 8;
2592 n_spilled += 1;
2595 /* Similarly for ar.pfs. */
2596 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2597 current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1);
2598 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2600 extra_spill_size += 8;
2601 n_spilled += 1;
2604 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2605 registers are clobbered, so we fall back to the stack. */
2606 current_frame_info.r[reg_save_gp]
2607 = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1));
2608 if (current_frame_info.r[reg_save_gp] == 0)
2610 SET_HARD_REG_BIT (mask, GR_REG (1));
2611 spill_size += 8;
2612 n_spilled += 1;
2615 else
2617 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)])
2619 SET_HARD_REG_BIT (mask, BR_REG (0));
2620 extra_spill_size += 8;
2621 n_spilled += 1;
2624 if (df_regs_ever_live_p (AR_PFS_REGNUM))
2626 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2627 current_frame_info.r[reg_save_ar_pfs]
2628 = find_gr_spill (reg_save_ar_pfs, 1);
2629 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2631 extra_spill_size += 8;
2632 n_spilled += 1;
2637 /* Unwind descriptor hackery: things are most efficient if we allocate
2638 consecutive GR save registers for RP, PFS, FP in that order. However,
2639 it is absolutely critical that FP get the only hard register that's
2640 guaranteed to be free, so we allocated it first. If all three did
2641 happen to be allocated hard regs, and are consecutive, rearrange them
2642 into the preferred order now.
2644 If we have already emitted code for any of those registers,
2645 then it's already too late to change. */
2646 min_regno = MIN (current_frame_info.r[reg_fp],
2647 MIN (current_frame_info.r[reg_save_b0],
2648 current_frame_info.r[reg_save_ar_pfs]));
2649 max_regno = MAX (current_frame_info.r[reg_fp],
2650 MAX (current_frame_info.r[reg_save_b0],
2651 current_frame_info.r[reg_save_ar_pfs]));
2652 if (min_regno > 0
2653 && min_regno + 2 == max_regno
2654 && (current_frame_info.r[reg_fp] == min_regno + 1
2655 || current_frame_info.r[reg_save_b0] == min_regno + 1
2656 || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1)
2657 && (emitted_frame_related_regs[reg_save_b0] == 0
2658 || emitted_frame_related_regs[reg_save_b0] == min_regno)
2659 && (emitted_frame_related_regs[reg_save_ar_pfs] == 0
2660 || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1)
2661 && (emitted_frame_related_regs[reg_fp] == 0
2662 || emitted_frame_related_regs[reg_fp] == min_regno + 2))
2664 current_frame_info.r[reg_save_b0] = min_regno;
2665 current_frame_info.r[reg_save_ar_pfs] = min_regno + 1;
2666 current_frame_info.r[reg_fp] = min_regno + 2;
2669 /* See if we need to store the predicate register block. */
2670 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2671 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2672 break;
2673 if (regno <= PR_REG (63))
2675 SET_HARD_REG_BIT (mask, PR_REG (0));
2676 current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1);
2677 if (current_frame_info.r[reg_save_pr] == 0)
2679 extra_spill_size += 8;
2680 n_spilled += 1;
2683 /* ??? Mark them all as used so that register renaming and such
2684 are free to use them. */
2685 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2686 df_set_regs_ever_live (regno, true);
2689 /* If we're forced to use st8.spill, we're forced to save and restore
2690 ar.unat as well. The check for existing liveness allows inline asm
2691 to touch ar.unat. */
2692 if (spilled_gr_p || cfun->machine->n_varargs
2693 || df_regs_ever_live_p (AR_UNAT_REGNUM))
2695 df_set_regs_ever_live (AR_UNAT_REGNUM, true);
2696 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2697 current_frame_info.r[reg_save_ar_unat]
2698 = find_gr_spill (reg_save_ar_unat, spill_size == 0);
2699 if (current_frame_info.r[reg_save_ar_unat] == 0)
2701 extra_spill_size += 8;
2702 n_spilled += 1;
2706 if (df_regs_ever_live_p (AR_LC_REGNUM))
2708 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2709 current_frame_info.r[reg_save_ar_lc]
2710 = find_gr_spill (reg_save_ar_lc, spill_size == 0);
2711 if (current_frame_info.r[reg_save_ar_lc] == 0)
2713 extra_spill_size += 8;
2714 n_spilled += 1;
2718 /* If we have an odd number of words of pretend arguments written to
2719 the stack, then the FR save area will be unaligned. We round the
2720 size of this area up to keep things 16 byte aligned. */
2721 if (spilled_fr_p)
2722 pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size);
2723 else
2724 pretend_args_size = crtl->args.pretend_args_size;
2726 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2727 + crtl->outgoing_args_size);
2728 total_size = IA64_STACK_ALIGN (total_size);
2730 /* We always use the 16-byte scratch area provided by the caller, but
2731 if we are a leaf function, there's no one to which we need to provide
2732 a scratch area. */
2733 if (current_function_is_leaf)
2734 total_size = MAX (0, total_size - 16);
2736 current_frame_info.total_size = total_size;
2737 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2738 current_frame_info.spill_size = spill_size;
2739 current_frame_info.extra_spill_size = extra_spill_size;
2740 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2741 current_frame_info.n_spilled = n_spilled;
2742 current_frame_info.initialized = reload_completed;
2745 /* Worker function for TARGET_CAN_ELIMINATE. */
2747 bool
2748 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
2750 return (to == BR_REG (0) ? current_function_is_leaf : true);
2753 /* Compute the initial difference between the specified pair of registers. */
2755 HOST_WIDE_INT
2756 ia64_initial_elimination_offset (int from, int to)
2758 HOST_WIDE_INT offset;
2760 ia64_compute_frame_size (get_frame_size ());
2761 switch (from)
2763 case FRAME_POINTER_REGNUM:
2764 switch (to)
2766 case HARD_FRAME_POINTER_REGNUM:
2767 if (current_function_is_leaf)
2768 offset = -current_frame_info.total_size;
2769 else
2770 offset = -(current_frame_info.total_size
2771 - crtl->outgoing_args_size - 16);
2772 break;
2774 case STACK_POINTER_REGNUM:
2775 if (current_function_is_leaf)
2776 offset = 0;
2777 else
2778 offset = 16 + crtl->outgoing_args_size;
2779 break;
2781 default:
2782 gcc_unreachable ();
2784 break;
2786 case ARG_POINTER_REGNUM:
2787 /* Arguments start above the 16 byte save area, unless stdarg
2788 in which case we store through the 16 byte save area. */
2789 switch (to)
2791 case HARD_FRAME_POINTER_REGNUM:
2792 offset = 16 - crtl->args.pretend_args_size;
2793 break;
2795 case STACK_POINTER_REGNUM:
2796 offset = (current_frame_info.total_size
2797 + 16 - crtl->args.pretend_args_size);
2798 break;
2800 default:
2801 gcc_unreachable ();
2803 break;
2805 default:
2806 gcc_unreachable ();
2809 return offset;
2812 /* If there are more than a trivial number of register spills, we use
2813 two interleaved iterators so that we can get two memory references
2814 per insn group.
2816 In order to simplify things in the prologue and epilogue expanders,
2817 we use helper functions to fix up the memory references after the
2818 fact with the appropriate offsets to a POST_MODIFY memory mode.
2819 The following data structure tracks the state of the two iterators
2820 while insns are being emitted. */
2822 struct spill_fill_data
2824 rtx init_after; /* point at which to emit initializations */
2825 rtx init_reg[2]; /* initial base register */
2826 rtx iter_reg[2]; /* the iterator registers */
2827 rtx *prev_addr[2]; /* address of last memory use */
2828 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2829 HOST_WIDE_INT prev_off[2]; /* last offset */
2830 int n_iter; /* number of iterators in use */
2831 int next_iter; /* next iterator to use */
2832 unsigned int save_gr_used_mask;
2835 static struct spill_fill_data spill_fill_data;
2837 static void
2838 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2840 int i;
2842 spill_fill_data.init_after = get_last_insn ();
2843 spill_fill_data.init_reg[0] = init_reg;
2844 spill_fill_data.init_reg[1] = init_reg;
2845 spill_fill_data.prev_addr[0] = NULL;
2846 spill_fill_data.prev_addr[1] = NULL;
2847 spill_fill_data.prev_insn[0] = NULL;
2848 spill_fill_data.prev_insn[1] = NULL;
2849 spill_fill_data.prev_off[0] = cfa_off;
2850 spill_fill_data.prev_off[1] = cfa_off;
2851 spill_fill_data.next_iter = 0;
2852 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2854 spill_fill_data.n_iter = 1 + (n_spills > 2);
2855 for (i = 0; i < spill_fill_data.n_iter; ++i)
2857 int regno = next_scratch_gr_reg ();
2858 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2859 current_frame_info.gr_used_mask |= 1 << regno;
2863 static void
2864 finish_spill_pointers (void)
2866 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2869 static rtx
2870 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2872 int iter = spill_fill_data.next_iter;
2873 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2874 rtx disp_rtx = GEN_INT (disp);
2875 rtx mem;
2877 if (spill_fill_data.prev_addr[iter])
2879 if (satisfies_constraint_N (disp_rtx))
2881 *spill_fill_data.prev_addr[iter]
2882 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2883 gen_rtx_PLUS (DImode,
2884 spill_fill_data.iter_reg[iter],
2885 disp_rtx));
2886 add_reg_note (spill_fill_data.prev_insn[iter],
2887 REG_INC, spill_fill_data.iter_reg[iter]);
2889 else
2891 /* ??? Could use register post_modify for loads. */
2892 if (!satisfies_constraint_I (disp_rtx))
2894 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2895 emit_move_insn (tmp, disp_rtx);
2896 disp_rtx = tmp;
2898 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2899 spill_fill_data.iter_reg[iter], disp_rtx));
2902 /* Micro-optimization: if we've created a frame pointer, it's at
2903 CFA 0, which may allow the real iterator to be initialized lower,
2904 slightly increasing parallelism. Also, if there are few saves
2905 it may eliminate the iterator entirely. */
2906 else if (disp == 0
2907 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2908 && frame_pointer_needed)
2910 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2911 set_mem_alias_set (mem, get_varargs_alias_set ());
2912 return mem;
2914 else
2916 rtx seq, insn;
2918 if (disp == 0)
2919 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2920 spill_fill_data.init_reg[iter]);
2921 else
2923 start_sequence ();
2925 if (!satisfies_constraint_I (disp_rtx))
2927 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2928 emit_move_insn (tmp, disp_rtx);
2929 disp_rtx = tmp;
2932 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2933 spill_fill_data.init_reg[iter],
2934 disp_rtx));
2936 seq = get_insns ();
2937 end_sequence ();
2940 /* Careful for being the first insn in a sequence. */
2941 if (spill_fill_data.init_after)
2942 insn = emit_insn_after (seq, spill_fill_data.init_after);
2943 else
2945 rtx first = get_insns ();
2946 if (first)
2947 insn = emit_insn_before (seq, first);
2948 else
2949 insn = emit_insn (seq);
2951 spill_fill_data.init_after = insn;
2954 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2956 /* ??? Not all of the spills are for varargs, but some of them are.
2957 The rest of the spills belong in an alias set of their own. But
2958 it doesn't actually hurt to include them here. */
2959 set_mem_alias_set (mem, get_varargs_alias_set ());
2961 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2962 spill_fill_data.prev_off[iter] = cfa_off;
2964 if (++iter >= spill_fill_data.n_iter)
2965 iter = 0;
2966 spill_fill_data.next_iter = iter;
2968 return mem;
2971 static void
2972 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
2973 rtx frame_reg)
2975 int iter = spill_fill_data.next_iter;
2976 rtx mem, insn;
2978 mem = spill_restore_mem (reg, cfa_off);
2979 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2980 spill_fill_data.prev_insn[iter] = insn;
2982 if (frame_reg)
2984 rtx base;
2985 HOST_WIDE_INT off;
2987 RTX_FRAME_RELATED_P (insn) = 1;
2989 /* Don't even pretend that the unwind code can intuit its way
2990 through a pair of interleaved post_modify iterators. Just
2991 provide the correct answer. */
2993 if (frame_pointer_needed)
2995 base = hard_frame_pointer_rtx;
2996 off = - cfa_off;
2998 else
3000 base = stack_pointer_rtx;
3001 off = current_frame_info.total_size - cfa_off;
3004 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3005 gen_rtx_SET (VOIDmode,
3006 gen_rtx_MEM (GET_MODE (reg),
3007 plus_constant (base, off)),
3008 frame_reg));
3012 static void
3013 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
3015 int iter = spill_fill_data.next_iter;
3016 rtx insn;
3018 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
3019 GEN_INT (cfa_off)));
3020 spill_fill_data.prev_insn[iter] = insn;
3023 /* Wrapper functions that discards the CONST_INT spill offset. These
3024 exist so that we can give gr_spill/gr_fill the offset they need and
3025 use a consistent function interface. */
3027 static rtx
3028 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3030 return gen_movdi (dest, src);
3033 static rtx
3034 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3036 return gen_fr_spill (dest, src);
3039 static rtx
3040 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3042 return gen_fr_restore (dest, src);
3045 /* Called after register allocation to add any instructions needed for the
3046 prologue. Using a prologue insn is favored compared to putting all of the
3047 instructions in output_function_prologue(), since it allows the scheduler
3048 to intermix instructions with the saves of the caller saved registers. In
3049 some cases, it might be necessary to emit a barrier instruction as the last
3050 insn to prevent such scheduling.
3052 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3053 so that the debug info generation code can handle them properly.
3055 The register save area is layed out like so:
3056 cfa+16
3057 [ varargs spill area ]
3058 [ fr register spill area ]
3059 [ br register spill area ]
3060 [ ar register spill area ]
3061 [ pr register spill area ]
3062 [ gr register spill area ] */
3064 /* ??? Get inefficient code when the frame size is larger than can fit in an
3065 adds instruction. */
3067 void
3068 ia64_expand_prologue (void)
3070 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
3071 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
3072 rtx reg, alt_reg;
3074 ia64_compute_frame_size (get_frame_size ());
3075 last_scratch_gr_reg = 15;
3077 if (dump_file)
3079 fprintf (dump_file, "ia64 frame related registers "
3080 "recorded in current_frame_info.r[]:\n");
3081 #define PRINTREG(a) if (current_frame_info.r[a]) \
3082 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3083 PRINTREG(reg_fp);
3084 PRINTREG(reg_save_b0);
3085 PRINTREG(reg_save_pr);
3086 PRINTREG(reg_save_ar_pfs);
3087 PRINTREG(reg_save_ar_unat);
3088 PRINTREG(reg_save_ar_lc);
3089 PRINTREG(reg_save_gp);
3090 #undef PRINTREG
3093 /* If there is no epilogue, then we don't need some prologue insns.
3094 We need to avoid emitting the dead prologue insns, because flow
3095 will complain about them. */
3096 if (optimize)
3098 edge e;
3099 edge_iterator ei;
3101 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
3102 if ((e->flags & EDGE_FAKE) == 0
3103 && (e->flags & EDGE_FALLTHRU) != 0)
3104 break;
3105 epilogue_p = (e != NULL);
3107 else
3108 epilogue_p = 1;
3110 /* Set the local, input, and output register names. We need to do this
3111 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3112 half. If we use in/loc/out register names, then we get assembler errors
3113 in crtn.S because there is no alloc insn or regstk directive in there. */
3114 if (! TARGET_REG_NAMES)
3116 int inputs = current_frame_info.n_input_regs;
3117 int locals = current_frame_info.n_local_regs;
3118 int outputs = current_frame_info.n_output_regs;
3120 for (i = 0; i < inputs; i++)
3121 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
3122 for (i = 0; i < locals; i++)
3123 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
3124 for (i = 0; i < outputs; i++)
3125 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
3128 /* Set the frame pointer register name. The regnum is logically loc79,
3129 but of course we'll not have allocated that many locals. Rather than
3130 worrying about renumbering the existing rtxs, we adjust the name. */
3131 /* ??? This code means that we can never use one local register when
3132 there is a frame pointer. loc79 gets wasted in this case, as it is
3133 renamed to a register that will never be used. See also the try_locals
3134 code in find_gr_spill. */
3135 if (current_frame_info.r[reg_fp])
3137 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3138 reg_names[HARD_FRAME_POINTER_REGNUM]
3139 = reg_names[current_frame_info.r[reg_fp]];
3140 reg_names[current_frame_info.r[reg_fp]] = tmp;
3143 /* We don't need an alloc instruction if we've used no outputs or locals. */
3144 if (current_frame_info.n_local_regs == 0
3145 && current_frame_info.n_output_regs == 0
3146 && current_frame_info.n_input_regs <= crtl->args.info.int_regs
3147 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3149 /* If there is no alloc, but there are input registers used, then we
3150 need a .regstk directive. */
3151 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
3152 ar_pfs_save_reg = NULL_RTX;
3154 else
3156 current_frame_info.need_regstk = 0;
3158 if (current_frame_info.r[reg_save_ar_pfs])
3160 regno = current_frame_info.r[reg_save_ar_pfs];
3161 reg_emitted (reg_save_ar_pfs);
3163 else
3164 regno = next_scratch_gr_reg ();
3165 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3167 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
3168 GEN_INT (current_frame_info.n_input_regs),
3169 GEN_INT (current_frame_info.n_local_regs),
3170 GEN_INT (current_frame_info.n_output_regs),
3171 GEN_INT (current_frame_info.n_rotate_regs)));
3172 RTX_FRAME_RELATED_P (insn) = (current_frame_info.r[reg_save_ar_pfs] != 0);
3175 /* Set up frame pointer, stack pointer, and spill iterators. */
3177 n_varargs = cfun->machine->n_varargs;
3178 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3179 stack_pointer_rtx, 0);
3181 if (frame_pointer_needed)
3183 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3184 RTX_FRAME_RELATED_P (insn) = 1;
3187 if (current_frame_info.total_size != 0)
3189 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3190 rtx offset;
3192 if (satisfies_constraint_I (frame_size_rtx))
3193 offset = frame_size_rtx;
3194 else
3196 regno = next_scratch_gr_reg ();
3197 offset = gen_rtx_REG (DImode, regno);
3198 emit_move_insn (offset, frame_size_rtx);
3201 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3202 stack_pointer_rtx, offset));
3204 if (! frame_pointer_needed)
3206 RTX_FRAME_RELATED_P (insn) = 1;
3207 if (GET_CODE (offset) != CONST_INT)
3208 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3209 gen_rtx_SET (VOIDmode,
3210 stack_pointer_rtx,
3211 gen_rtx_PLUS (DImode,
3212 stack_pointer_rtx,
3213 frame_size_rtx)));
3216 /* ??? At this point we must generate a magic insn that appears to
3217 modify the stack pointer, the frame pointer, and all spill
3218 iterators. This would allow the most scheduling freedom. For
3219 now, just hard stop. */
3220 emit_insn (gen_blockage ());
3223 /* Must copy out ar.unat before doing any integer spills. */
3224 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3226 if (current_frame_info.r[reg_save_ar_unat])
3228 ar_unat_save_reg
3229 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3230 reg_emitted (reg_save_ar_unat);
3232 else
3234 alt_regno = next_scratch_gr_reg ();
3235 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3236 current_frame_info.gr_used_mask |= 1 << alt_regno;
3239 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3240 insn = emit_move_insn (ar_unat_save_reg, reg);
3241 RTX_FRAME_RELATED_P (insn) = (current_frame_info.r[reg_save_ar_unat] != 0);
3243 /* Even if we're not going to generate an epilogue, we still
3244 need to save the register so that EH works. */
3245 if (! epilogue_p && current_frame_info.r[reg_save_ar_unat])
3246 emit_insn (gen_prologue_use (ar_unat_save_reg));
3248 else
3249 ar_unat_save_reg = NULL_RTX;
3251 /* Spill all varargs registers. Do this before spilling any GR registers,
3252 since we want the UNAT bits for the GR registers to override the UNAT
3253 bits from varargs, which we don't care about. */
3255 cfa_off = -16;
3256 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3258 reg = gen_rtx_REG (DImode, regno);
3259 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3262 /* Locate the bottom of the register save area. */
3263 cfa_off = (current_frame_info.spill_cfa_off
3264 + current_frame_info.spill_size
3265 + current_frame_info.extra_spill_size);
3267 /* Save the predicate register block either in a register or in memory. */
3268 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3270 reg = gen_rtx_REG (DImode, PR_REG (0));
3271 if (current_frame_info.r[reg_save_pr] != 0)
3273 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3274 reg_emitted (reg_save_pr);
3275 insn = emit_move_insn (alt_reg, reg);
3277 /* ??? Denote pr spill/fill by a DImode move that modifies all
3278 64 hard registers. */
3279 RTX_FRAME_RELATED_P (insn) = 1;
3280 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3281 gen_rtx_SET (VOIDmode, alt_reg, reg));
3283 /* Even if we're not going to generate an epilogue, we still
3284 need to save the register so that EH works. */
3285 if (! epilogue_p)
3286 emit_insn (gen_prologue_use (alt_reg));
3288 else
3290 alt_regno = next_scratch_gr_reg ();
3291 alt_reg = gen_rtx_REG (DImode, alt_regno);
3292 insn = emit_move_insn (alt_reg, reg);
3293 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3294 cfa_off -= 8;
3298 /* Handle AR regs in numerical order. All of them get special handling. */
3299 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3300 && current_frame_info.r[reg_save_ar_unat] == 0)
3302 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3303 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3304 cfa_off -= 8;
3307 /* The alloc insn already copied ar.pfs into a general register. The
3308 only thing we have to do now is copy that register to a stack slot
3309 if we'd not allocated a local register for the job. */
3310 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3311 && current_frame_info.r[reg_save_ar_pfs] == 0)
3313 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3314 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3315 cfa_off -= 8;
3318 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3320 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3321 if (current_frame_info.r[reg_save_ar_lc] != 0)
3323 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3324 reg_emitted (reg_save_ar_lc);
3325 insn = emit_move_insn (alt_reg, reg);
3326 RTX_FRAME_RELATED_P (insn) = 1;
3328 /* Even if we're not going to generate an epilogue, we still
3329 need to save the register so that EH works. */
3330 if (! epilogue_p)
3331 emit_insn (gen_prologue_use (alt_reg));
3333 else
3335 alt_regno = next_scratch_gr_reg ();
3336 alt_reg = gen_rtx_REG (DImode, alt_regno);
3337 emit_move_insn (alt_reg, reg);
3338 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3339 cfa_off -= 8;
3343 /* Save the return pointer. */
3344 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3346 reg = gen_rtx_REG (DImode, BR_REG (0));
3347 if (current_frame_info.r[reg_save_b0] != 0)
3349 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3350 reg_emitted (reg_save_b0);
3351 insn = emit_move_insn (alt_reg, reg);
3352 RTX_FRAME_RELATED_P (insn) = 1;
3354 /* Even if we're not going to generate an epilogue, we still
3355 need to save the register so that EH works. */
3356 if (! epilogue_p)
3357 emit_insn (gen_prologue_use (alt_reg));
3359 else
3361 alt_regno = next_scratch_gr_reg ();
3362 alt_reg = gen_rtx_REG (DImode, alt_regno);
3363 emit_move_insn (alt_reg, reg);
3364 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3365 cfa_off -= 8;
3369 if (current_frame_info.r[reg_save_gp])
3371 reg_emitted (reg_save_gp);
3372 insn = emit_move_insn (gen_rtx_REG (DImode,
3373 current_frame_info.r[reg_save_gp]),
3374 pic_offset_table_rtx);
3377 /* We should now be at the base of the gr/br/fr spill area. */
3378 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3379 + current_frame_info.spill_size));
3381 /* Spill all general registers. */
3382 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3383 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3385 reg = gen_rtx_REG (DImode, regno);
3386 do_spill (gen_gr_spill, reg, cfa_off, reg);
3387 cfa_off -= 8;
3390 /* Spill the rest of the BR registers. */
3391 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3392 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3394 alt_regno = next_scratch_gr_reg ();
3395 alt_reg = gen_rtx_REG (DImode, alt_regno);
3396 reg = gen_rtx_REG (DImode, regno);
3397 emit_move_insn (alt_reg, reg);
3398 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3399 cfa_off -= 8;
3402 /* Align the frame and spill all FR registers. */
3403 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3404 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3406 gcc_assert (!(cfa_off & 15));
3407 reg = gen_rtx_REG (XFmode, regno);
3408 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3409 cfa_off -= 16;
3412 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3414 finish_spill_pointers ();
3417 /* Called after register allocation to add any instructions needed for the
3418 epilogue. Using an epilogue insn is favored compared to putting all of the
3419 instructions in output_function_prologue(), since it allows the scheduler
3420 to intermix instructions with the saves of the caller saved registers. In
3421 some cases, it might be necessary to emit a barrier instruction as the last
3422 insn to prevent such scheduling. */
3424 void
3425 ia64_expand_epilogue (int sibcall_p)
3427 rtx insn, reg, alt_reg, ar_unat_save_reg;
3428 int regno, alt_regno, cfa_off;
3430 ia64_compute_frame_size (get_frame_size ());
3432 /* If there is a frame pointer, then we use it instead of the stack
3433 pointer, so that the stack pointer does not need to be valid when
3434 the epilogue starts. See EXIT_IGNORE_STACK. */
3435 if (frame_pointer_needed)
3436 setup_spill_pointers (current_frame_info.n_spilled,
3437 hard_frame_pointer_rtx, 0);
3438 else
3439 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3440 current_frame_info.total_size);
3442 if (current_frame_info.total_size != 0)
3444 /* ??? At this point we must generate a magic insn that appears to
3445 modify the spill iterators and the frame pointer. This would
3446 allow the most scheduling freedom. For now, just hard stop. */
3447 emit_insn (gen_blockage ());
3450 /* Locate the bottom of the register save area. */
3451 cfa_off = (current_frame_info.spill_cfa_off
3452 + current_frame_info.spill_size
3453 + current_frame_info.extra_spill_size);
3455 /* Restore the predicate registers. */
3456 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3458 if (current_frame_info.r[reg_save_pr] != 0)
3460 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3461 reg_emitted (reg_save_pr);
3463 else
3465 alt_regno = next_scratch_gr_reg ();
3466 alt_reg = gen_rtx_REG (DImode, alt_regno);
3467 do_restore (gen_movdi_x, alt_reg, cfa_off);
3468 cfa_off -= 8;
3470 reg = gen_rtx_REG (DImode, PR_REG (0));
3471 emit_move_insn (reg, alt_reg);
3474 /* Restore the application registers. */
3476 /* Load the saved unat from the stack, but do not restore it until
3477 after the GRs have been restored. */
3478 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3480 if (current_frame_info.r[reg_save_ar_unat] != 0)
3482 ar_unat_save_reg
3483 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3484 reg_emitted (reg_save_ar_unat);
3486 else
3488 alt_regno = next_scratch_gr_reg ();
3489 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3490 current_frame_info.gr_used_mask |= 1 << alt_regno;
3491 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3492 cfa_off -= 8;
3495 else
3496 ar_unat_save_reg = NULL_RTX;
3498 if (current_frame_info.r[reg_save_ar_pfs] != 0)
3500 reg_emitted (reg_save_ar_pfs);
3501 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
3502 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3503 emit_move_insn (reg, alt_reg);
3505 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3507 alt_regno = next_scratch_gr_reg ();
3508 alt_reg = gen_rtx_REG (DImode, alt_regno);
3509 do_restore (gen_movdi_x, alt_reg, cfa_off);
3510 cfa_off -= 8;
3511 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3512 emit_move_insn (reg, alt_reg);
3515 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3517 if (current_frame_info.r[reg_save_ar_lc] != 0)
3519 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3520 reg_emitted (reg_save_ar_lc);
3522 else
3524 alt_regno = next_scratch_gr_reg ();
3525 alt_reg = gen_rtx_REG (DImode, alt_regno);
3526 do_restore (gen_movdi_x, alt_reg, cfa_off);
3527 cfa_off -= 8;
3529 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3530 emit_move_insn (reg, alt_reg);
3533 /* Restore the return pointer. */
3534 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3536 if (current_frame_info.r[reg_save_b0] != 0)
3538 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3539 reg_emitted (reg_save_b0);
3541 else
3543 alt_regno = next_scratch_gr_reg ();
3544 alt_reg = gen_rtx_REG (DImode, alt_regno);
3545 do_restore (gen_movdi_x, alt_reg, cfa_off);
3546 cfa_off -= 8;
3548 reg = gen_rtx_REG (DImode, BR_REG (0));
3549 emit_move_insn (reg, alt_reg);
3552 /* We should now be at the base of the gr/br/fr spill area. */
3553 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3554 + current_frame_info.spill_size));
3556 /* The GP may be stored on the stack in the prologue, but it's
3557 never restored in the epilogue. Skip the stack slot. */
3558 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3559 cfa_off -= 8;
3561 /* Restore all general registers. */
3562 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3563 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3565 reg = gen_rtx_REG (DImode, regno);
3566 do_restore (gen_gr_restore, reg, cfa_off);
3567 cfa_off -= 8;
3570 /* Restore the branch registers. */
3571 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3572 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3574 alt_regno = next_scratch_gr_reg ();
3575 alt_reg = gen_rtx_REG (DImode, alt_regno);
3576 do_restore (gen_movdi_x, alt_reg, cfa_off);
3577 cfa_off -= 8;
3578 reg = gen_rtx_REG (DImode, regno);
3579 emit_move_insn (reg, alt_reg);
3582 /* Restore floating point registers. */
3583 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3584 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3586 gcc_assert (!(cfa_off & 15));
3587 reg = gen_rtx_REG (XFmode, regno);
3588 do_restore (gen_fr_restore_x, reg, cfa_off);
3589 cfa_off -= 16;
3592 /* Restore ar.unat for real. */
3593 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3595 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3596 emit_move_insn (reg, ar_unat_save_reg);
3599 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3601 finish_spill_pointers ();
3603 if (current_frame_info.total_size
3604 || cfun->machine->ia64_eh_epilogue_sp
3605 || frame_pointer_needed)
3607 /* ??? At this point we must generate a magic insn that appears to
3608 modify the spill iterators, the stack pointer, and the frame
3609 pointer. This would allow the most scheduling freedom. For now,
3610 just hard stop. */
3611 emit_insn (gen_blockage ());
3614 if (cfun->machine->ia64_eh_epilogue_sp)
3615 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3616 else if (frame_pointer_needed)
3618 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3619 RTX_FRAME_RELATED_P (insn) = 1;
3621 else if (current_frame_info.total_size)
3623 rtx offset, frame_size_rtx;
3625 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3626 if (satisfies_constraint_I (frame_size_rtx))
3627 offset = frame_size_rtx;
3628 else
3630 regno = next_scratch_gr_reg ();
3631 offset = gen_rtx_REG (DImode, regno);
3632 emit_move_insn (offset, frame_size_rtx);
3635 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3636 offset));
3638 RTX_FRAME_RELATED_P (insn) = 1;
3639 if (GET_CODE (offset) != CONST_INT)
3640 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3641 gen_rtx_SET (VOIDmode,
3642 stack_pointer_rtx,
3643 gen_rtx_PLUS (DImode,
3644 stack_pointer_rtx,
3645 frame_size_rtx)));
3648 if (cfun->machine->ia64_eh_epilogue_bsp)
3649 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3651 if (! sibcall_p)
3652 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3653 else
3655 int fp = GR_REG (2);
3656 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3657 first available call clobbered register. If there was a frame_pointer
3658 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3659 so we have to make sure we're using the string "r2" when emitting
3660 the register name for the assembler. */
3661 if (current_frame_info.r[reg_fp]
3662 && current_frame_info.r[reg_fp] == GR_REG (2))
3663 fp = HARD_FRAME_POINTER_REGNUM;
3665 /* We must emit an alloc to force the input registers to become output
3666 registers. Otherwise, if the callee tries to pass its parameters
3667 through to another call without an intervening alloc, then these
3668 values get lost. */
3669 /* ??? We don't need to preserve all input registers. We only need to
3670 preserve those input registers used as arguments to the sibling call.
3671 It is unclear how to compute that number here. */
3672 if (current_frame_info.n_input_regs != 0)
3674 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
3675 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3676 const0_rtx, const0_rtx,
3677 n_inputs, const0_rtx));
3678 RTX_FRAME_RELATED_P (insn) = 1;
3683 /* Return 1 if br.ret can do all the work required to return from a
3684 function. */
3687 ia64_direct_return (void)
3689 if (reload_completed && ! frame_pointer_needed)
3691 ia64_compute_frame_size (get_frame_size ());
3693 return (current_frame_info.total_size == 0
3694 && current_frame_info.n_spilled == 0
3695 && current_frame_info.r[reg_save_b0] == 0
3696 && current_frame_info.r[reg_save_pr] == 0
3697 && current_frame_info.r[reg_save_ar_pfs] == 0
3698 && current_frame_info.r[reg_save_ar_unat] == 0
3699 && current_frame_info.r[reg_save_ar_lc] == 0);
3701 return 0;
3704 /* Return the magic cookie that we use to hold the return address
3705 during early compilation. */
3708 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3710 if (count != 0)
3711 return NULL;
3712 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3715 /* Split this value after reload, now that we know where the return
3716 address is saved. */
3718 void
3719 ia64_split_return_addr_rtx (rtx dest)
3721 rtx src;
3723 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3725 if (current_frame_info.r[reg_save_b0] != 0)
3727 src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3728 reg_emitted (reg_save_b0);
3730 else
3732 HOST_WIDE_INT off;
3733 unsigned int regno;
3734 rtx off_r;
3736 /* Compute offset from CFA for BR0. */
3737 /* ??? Must be kept in sync with ia64_expand_prologue. */
3738 off = (current_frame_info.spill_cfa_off
3739 + current_frame_info.spill_size);
3740 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3741 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3742 off -= 8;
3744 /* Convert CFA offset to a register based offset. */
3745 if (frame_pointer_needed)
3746 src = hard_frame_pointer_rtx;
3747 else
3749 src = stack_pointer_rtx;
3750 off += current_frame_info.total_size;
3753 /* Load address into scratch register. */
3754 off_r = GEN_INT (off);
3755 if (satisfies_constraint_I (off_r))
3756 emit_insn (gen_adddi3 (dest, src, off_r));
3757 else
3759 emit_move_insn (dest, off_r);
3760 emit_insn (gen_adddi3 (dest, src, dest));
3763 src = gen_rtx_MEM (Pmode, dest);
3766 else
3767 src = gen_rtx_REG (DImode, BR_REG (0));
3769 emit_move_insn (dest, src);
3773 ia64_hard_regno_rename_ok (int from, int to)
3775 /* Don't clobber any of the registers we reserved for the prologue. */
3776 unsigned int r;
3778 for (r = reg_fp; r <= reg_save_ar_lc; r++)
3779 if (to == current_frame_info.r[r]
3780 || from == current_frame_info.r[r]
3781 || to == emitted_frame_related_regs[r]
3782 || from == emitted_frame_related_regs[r])
3783 return 0;
3785 /* Don't use output registers outside the register frame. */
3786 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3787 return 0;
3789 /* Retain even/oddness on predicate register pairs. */
3790 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3791 return (from & 1) == (to & 1);
3793 return 1;
3796 /* Target hook for assembling integer objects. Handle word-sized
3797 aligned objects and detect the cases when @fptr is needed. */
3799 static bool
3800 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3802 if (size == POINTER_SIZE / BITS_PER_UNIT
3803 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3804 && GET_CODE (x) == SYMBOL_REF
3805 && SYMBOL_REF_FUNCTION_P (x))
3807 static const char * const directive[2][2] = {
3808 /* 64-bit pointer */ /* 32-bit pointer */
3809 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3810 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3812 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
3813 output_addr_const (asm_out_file, x);
3814 fputs (")\n", asm_out_file);
3815 return true;
3817 return default_assemble_integer (x, size, aligned_p);
3820 /* Emit the function prologue. */
3822 static void
3823 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3825 int mask, grsave, grsave_prev;
3827 if (current_frame_info.need_regstk)
3828 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3829 current_frame_info.n_input_regs,
3830 current_frame_info.n_local_regs,
3831 current_frame_info.n_output_regs,
3832 current_frame_info.n_rotate_regs);
3834 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3835 return;
3837 /* Emit the .prologue directive. */
3839 mask = 0;
3840 grsave = grsave_prev = 0;
3841 if (current_frame_info.r[reg_save_b0] != 0)
3843 mask |= 8;
3844 grsave = grsave_prev = current_frame_info.r[reg_save_b0];
3846 if (current_frame_info.r[reg_save_ar_pfs] != 0
3847 && (grsave_prev == 0
3848 || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1))
3850 mask |= 4;
3851 if (grsave_prev == 0)
3852 grsave = current_frame_info.r[reg_save_ar_pfs];
3853 grsave_prev = current_frame_info.r[reg_save_ar_pfs];
3855 if (current_frame_info.r[reg_fp] != 0
3856 && (grsave_prev == 0
3857 || current_frame_info.r[reg_fp] == grsave_prev + 1))
3859 mask |= 2;
3860 if (grsave_prev == 0)
3861 grsave = HARD_FRAME_POINTER_REGNUM;
3862 grsave_prev = current_frame_info.r[reg_fp];
3864 if (current_frame_info.r[reg_save_pr] != 0
3865 && (grsave_prev == 0
3866 || current_frame_info.r[reg_save_pr] == grsave_prev + 1))
3868 mask |= 1;
3869 if (grsave_prev == 0)
3870 grsave = current_frame_info.r[reg_save_pr];
3873 if (mask && TARGET_GNU_AS)
3874 fprintf (file, "\t.prologue %d, %d\n", mask,
3875 ia64_dbx_register_number (grsave));
3876 else
3877 fputs ("\t.prologue\n", file);
3879 /* Emit a .spill directive, if necessary, to relocate the base of
3880 the register spill area. */
3881 if (current_frame_info.spill_cfa_off != -16)
3882 fprintf (file, "\t.spill %ld\n",
3883 (long) (current_frame_info.spill_cfa_off
3884 + current_frame_info.spill_size));
3887 /* Emit the .body directive at the scheduled end of the prologue. */
3889 static void
3890 ia64_output_function_end_prologue (FILE *file)
3892 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3893 return;
3895 fputs ("\t.body\n", file);
3898 /* Emit the function epilogue. */
3900 static void
3901 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3902 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3904 int i;
3906 if (current_frame_info.r[reg_fp])
3908 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3909 reg_names[HARD_FRAME_POINTER_REGNUM]
3910 = reg_names[current_frame_info.r[reg_fp]];
3911 reg_names[current_frame_info.r[reg_fp]] = tmp;
3912 reg_emitted (reg_fp);
3914 if (! TARGET_REG_NAMES)
3916 for (i = 0; i < current_frame_info.n_input_regs; i++)
3917 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3918 for (i = 0; i < current_frame_info.n_local_regs; i++)
3919 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3920 for (i = 0; i < current_frame_info.n_output_regs; i++)
3921 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3924 current_frame_info.initialized = 0;
3928 ia64_dbx_register_number (int regno)
3930 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3931 from its home at loc79 to something inside the register frame. We
3932 must perform the same renumbering here for the debug info. */
3933 if (current_frame_info.r[reg_fp])
3935 if (regno == HARD_FRAME_POINTER_REGNUM)
3936 regno = current_frame_info.r[reg_fp];
3937 else if (regno == current_frame_info.r[reg_fp])
3938 regno = HARD_FRAME_POINTER_REGNUM;
3941 if (IN_REGNO_P (regno))
3942 return 32 + regno - IN_REG (0);
3943 else if (LOC_REGNO_P (regno))
3944 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3945 else if (OUT_REGNO_P (regno))
3946 return (32 + current_frame_info.n_input_regs
3947 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3948 else
3949 return regno;
3952 /* Implement TARGET_TRAMPOLINE_INIT.
3954 The trampoline should set the static chain pointer to value placed
3955 into the trampoline and should branch to the specified routine.
3956 To make the normal indirect-subroutine calling convention work,
3957 the trampoline must look like a function descriptor; the first
3958 word being the target address and the second being the target's
3959 global pointer.
3961 We abuse the concept of a global pointer by arranging for it
3962 to point to the data we need to load. The complete trampoline
3963 has the following form:
3965 +-------------------+ \
3966 TRAMP: | __ia64_trampoline | |
3967 +-------------------+ > fake function descriptor
3968 | TRAMP+16 | |
3969 +-------------------+ /
3970 | target descriptor |
3971 +-------------------+
3972 | static link |
3973 +-------------------+
3976 static void
3977 ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
3979 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
3980 rtx addr, addr_reg, tramp, eight = GEN_INT (8);
3982 /* The Intel assembler requires that the global __ia64_trampoline symbol
3983 be declared explicitly */
3984 if (!TARGET_GNU_AS)
3986 static bool declared_ia64_trampoline = false;
3988 if (!declared_ia64_trampoline)
3990 declared_ia64_trampoline = true;
3991 (*targetm.asm_out.globalize_label) (asm_out_file,
3992 "__ia64_trampoline");
3996 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3997 addr = convert_memory_address (Pmode, XEXP (m_tramp, 0));
3998 fnaddr = convert_memory_address (Pmode, fnaddr);
3999 static_chain = convert_memory_address (Pmode, static_chain);
4001 /* Load up our iterator. */
4002 addr_reg = copy_to_reg (addr);
4003 m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0);
4005 /* The first two words are the fake descriptor:
4006 __ia64_trampoline, ADDR+16. */
4007 tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline");
4008 if (TARGET_ABI_OPEN_VMS)
4010 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4011 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4012 relocation against function symbols to make it identical to the
4013 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4014 strict ELF and dereference to get the bare code address. */
4015 rtx reg = gen_reg_rtx (Pmode);
4016 SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION;
4017 emit_move_insn (reg, tramp);
4018 emit_move_insn (reg, gen_rtx_MEM (Pmode, reg));
4019 tramp = reg;
4021 emit_move_insn (m_tramp, tramp);
4022 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4023 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4025 emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (addr, 16)));
4026 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4027 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4029 /* The third word is the target descriptor. */
4030 emit_move_insn (m_tramp, force_reg (Pmode, fnaddr));
4031 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4032 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4034 /* The fourth word is the static chain. */
4035 emit_move_insn (m_tramp, static_chain);
4038 /* Do any needed setup for a variadic function. CUM has not been updated
4039 for the last named argument which has type TYPE and mode MODE.
4041 We generate the actual spill instructions during prologue generation. */
4043 static void
4044 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4045 tree type, int * pretend_size,
4046 int second_time ATTRIBUTE_UNUSED)
4048 CUMULATIVE_ARGS next_cum = *cum;
4050 /* Skip the current argument. */
4051 ia64_function_arg_advance (&next_cum, mode, type, 1);
4053 if (next_cum.words < MAX_ARGUMENT_SLOTS)
4055 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
4056 *pretend_size = n * UNITS_PER_WORD;
4057 cfun->machine->n_varargs = n;
4061 /* Check whether TYPE is a homogeneous floating point aggregate. If
4062 it is, return the mode of the floating point type that appears
4063 in all leafs. If it is not, return VOIDmode.
4065 An aggregate is a homogeneous floating point aggregate is if all
4066 fields/elements in it have the same floating point type (e.g,
4067 SFmode). 128-bit quad-precision floats are excluded.
4069 Variable sized aggregates should never arrive here, since we should
4070 have already decided to pass them by reference. Top-level zero-sized
4071 aggregates are excluded because our parallels crash the middle-end. */
4073 static enum machine_mode
4074 hfa_element_mode (const_tree type, bool nested)
4076 enum machine_mode element_mode = VOIDmode;
4077 enum machine_mode mode;
4078 enum tree_code code = TREE_CODE (type);
4079 int know_element_mode = 0;
4080 tree t;
4082 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
4083 return VOIDmode;
4085 switch (code)
4087 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
4088 case BOOLEAN_TYPE: case POINTER_TYPE:
4089 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
4090 case LANG_TYPE: case FUNCTION_TYPE:
4091 return VOIDmode;
4093 /* Fortran complex types are supposed to be HFAs, so we need to handle
4094 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4095 types though. */
4096 case COMPLEX_TYPE:
4097 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
4098 && TYPE_MODE (type) != TCmode)
4099 return GET_MODE_INNER (TYPE_MODE (type));
4100 else
4101 return VOIDmode;
4103 case REAL_TYPE:
4104 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4105 mode if this is contained within an aggregate. */
4106 if (nested && TYPE_MODE (type) != TFmode)
4107 return TYPE_MODE (type);
4108 else
4109 return VOIDmode;
4111 case ARRAY_TYPE:
4112 return hfa_element_mode (TREE_TYPE (type), 1);
4114 case RECORD_TYPE:
4115 case UNION_TYPE:
4116 case QUAL_UNION_TYPE:
4117 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
4119 if (TREE_CODE (t) != FIELD_DECL)
4120 continue;
4122 mode = hfa_element_mode (TREE_TYPE (t), 1);
4123 if (know_element_mode)
4125 if (mode != element_mode)
4126 return VOIDmode;
4128 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
4129 return VOIDmode;
4130 else
4132 know_element_mode = 1;
4133 element_mode = mode;
4136 return element_mode;
4138 default:
4139 /* If we reach here, we probably have some front-end specific type
4140 that the backend doesn't know about. This can happen via the
4141 aggregate_value_p call in init_function_start. All we can do is
4142 ignore unknown tree types. */
4143 return VOIDmode;
4146 return VOIDmode;
4149 /* Return the number of words required to hold a quantity of TYPE and MODE
4150 when passed as an argument. */
4151 static int
4152 ia64_function_arg_words (tree type, enum machine_mode mode)
4154 int words;
4156 if (mode == BLKmode)
4157 words = int_size_in_bytes (type);
4158 else
4159 words = GET_MODE_SIZE (mode);
4161 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
4164 /* Return the number of registers that should be skipped so the current
4165 argument (described by TYPE and WORDS) will be properly aligned.
4167 Integer and float arguments larger than 8 bytes start at the next
4168 even boundary. Aggregates larger than 8 bytes start at the next
4169 even boundary if the aggregate has 16 byte alignment. Note that
4170 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4171 but are still to be aligned in registers.
4173 ??? The ABI does not specify how to handle aggregates with
4174 alignment from 9 to 15 bytes, or greater than 16. We handle them
4175 all as if they had 16 byte alignment. Such aggregates can occur
4176 only if gcc extensions are used. */
4177 static int
4178 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
4180 /* No registers are skipped on VMS. */
4181 if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0)
4182 return 0;
4184 if (type
4185 && TREE_CODE (type) != INTEGER_TYPE
4186 && TREE_CODE (type) != REAL_TYPE)
4187 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
4188 else
4189 return words > 1;
4192 /* Return rtx for register where argument is passed, or zero if it is passed
4193 on the stack. */
4194 /* ??? 128-bit quad-precision floats are always passed in general
4195 registers. */
4198 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
4199 int named, int incoming)
4201 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
4202 int words = ia64_function_arg_words (type, mode);
4203 int offset = ia64_function_arg_offset (cum, type, words);
4204 enum machine_mode hfa_mode = VOIDmode;
4206 /* For OPEN VMS, emit the instruction setting up the argument register here,
4207 when we know this will be together with the other arguments setup related
4208 insns. This is not the conceptually best place to do this, but this is
4209 the easiest as we have convenient access to cumulative args info. */
4211 if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node
4212 && named == 1)
4214 unsigned HOST_WIDE_INT regval = cum->words;
4215 int i;
4217 for (i = 0; i < 8; i++)
4218 regval |= ((int) cum->atypes[i]) << (i * 3 + 8);
4220 emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
4221 GEN_INT (regval));
4224 /* If all argument slots are used, then it must go on the stack. */
4225 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4226 return 0;
4228 /* Check for and handle homogeneous FP aggregates. */
4229 if (type)
4230 hfa_mode = hfa_element_mode (type, 0);
4232 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4233 and unprototyped hfas are passed specially. */
4234 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4236 rtx loc[16];
4237 int i = 0;
4238 int fp_regs = cum->fp_regs;
4239 int int_regs = cum->words + offset;
4240 int hfa_size = GET_MODE_SIZE (hfa_mode);
4241 int byte_size;
4242 int args_byte_size;
4244 /* If prototyped, pass it in FR regs then GR regs.
4245 If not prototyped, pass it in both FR and GR regs.
4247 If this is an SFmode aggregate, then it is possible to run out of
4248 FR regs while GR regs are still left. In that case, we pass the
4249 remaining part in the GR regs. */
4251 /* Fill the FP regs. We do this always. We stop if we reach the end
4252 of the argument, the last FP register, or the last argument slot. */
4254 byte_size = ((mode == BLKmode)
4255 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4256 args_byte_size = int_regs * UNITS_PER_WORD;
4257 offset = 0;
4258 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4259 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4261 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4262 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4263 + fp_regs)),
4264 GEN_INT (offset));
4265 offset += hfa_size;
4266 args_byte_size += hfa_size;
4267 fp_regs++;
4270 /* If no prototype, then the whole thing must go in GR regs. */
4271 if (! cum->prototype)
4272 offset = 0;
4273 /* If this is an SFmode aggregate, then we might have some left over
4274 that needs to go in GR regs. */
4275 else if (byte_size != offset)
4276 int_regs += offset / UNITS_PER_WORD;
4278 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4280 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4282 enum machine_mode gr_mode = DImode;
4283 unsigned int gr_size;
4285 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4286 then this goes in a GR reg left adjusted/little endian, right
4287 adjusted/big endian. */
4288 /* ??? Currently this is handled wrong, because 4-byte hunks are
4289 always right adjusted/little endian. */
4290 if (offset & 0x4)
4291 gr_mode = SImode;
4292 /* If we have an even 4 byte hunk because the aggregate is a
4293 multiple of 4 bytes in size, then this goes in a GR reg right
4294 adjusted/little endian. */
4295 else if (byte_size - offset == 4)
4296 gr_mode = SImode;
4298 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4299 gen_rtx_REG (gr_mode, (basereg
4300 + int_regs)),
4301 GEN_INT (offset));
4303 gr_size = GET_MODE_SIZE (gr_mode);
4304 offset += gr_size;
4305 if (gr_size == UNITS_PER_WORD
4306 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4307 int_regs++;
4308 else if (gr_size > UNITS_PER_WORD)
4309 int_regs += gr_size / UNITS_PER_WORD;
4311 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4314 /* On OpenVMS variable argument is either in Rn or Fn. */
4315 else if (TARGET_ABI_OPEN_VMS && named == 0)
4317 if (FLOAT_MODE_P (mode))
4318 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words);
4319 else
4320 return gen_rtx_REG (mode, basereg + cum->words);
4323 /* Integral and aggregates go in general registers. If we have run out of
4324 FR registers, then FP values must also go in general registers. This can
4325 happen when we have a SFmode HFA. */
4326 else if (mode == TFmode || mode == TCmode
4327 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4329 int byte_size = ((mode == BLKmode)
4330 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4331 if (BYTES_BIG_ENDIAN
4332 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4333 && byte_size < UNITS_PER_WORD
4334 && byte_size > 0)
4336 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4337 gen_rtx_REG (DImode,
4338 (basereg + cum->words
4339 + offset)),
4340 const0_rtx);
4341 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4343 else
4344 return gen_rtx_REG (mode, basereg + cum->words + offset);
4348 /* If there is a prototype, then FP values go in a FR register when
4349 named, and in a GR register when unnamed. */
4350 else if (cum->prototype)
4352 if (named)
4353 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4354 /* In big-endian mode, an anonymous SFmode value must be represented
4355 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4356 the value into the high half of the general register. */
4357 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4358 return gen_rtx_PARALLEL (mode,
4359 gen_rtvec (1,
4360 gen_rtx_EXPR_LIST (VOIDmode,
4361 gen_rtx_REG (DImode, basereg + cum->words + offset),
4362 const0_rtx)));
4363 else
4364 return gen_rtx_REG (mode, basereg + cum->words + offset);
4366 /* If there is no prototype, then FP values go in both FR and GR
4367 registers. */
4368 else
4370 /* See comment above. */
4371 enum machine_mode inner_mode =
4372 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4374 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4375 gen_rtx_REG (mode, (FR_ARG_FIRST
4376 + cum->fp_regs)),
4377 const0_rtx);
4378 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4379 gen_rtx_REG (inner_mode,
4380 (basereg + cum->words
4381 + offset)),
4382 const0_rtx);
4384 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4388 /* Return number of bytes, at the beginning of the argument, that must be
4389 put in registers. 0 is the argument is entirely in registers or entirely
4390 in memory. */
4392 static int
4393 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4394 tree type, bool named ATTRIBUTE_UNUSED)
4396 int words = ia64_function_arg_words (type, mode);
4397 int offset = ia64_function_arg_offset (cum, type, words);
4399 /* If all argument slots are used, then it must go on the stack. */
4400 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4401 return 0;
4403 /* It doesn't matter whether the argument goes in FR or GR regs. If
4404 it fits within the 8 argument slots, then it goes entirely in
4405 registers. If it extends past the last argument slot, then the rest
4406 goes on the stack. */
4408 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4409 return 0;
4411 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4414 /* Return ivms_arg_type based on machine_mode. */
4416 static enum ivms_arg_type
4417 ia64_arg_type (enum machine_mode mode)
4419 switch (mode)
4421 case SFmode:
4422 return FS;
4423 case DFmode:
4424 return FT;
4425 default:
4426 return I64;
4430 /* Update CUM to point after this argument. This is patterned after
4431 ia64_function_arg. */
4433 void
4434 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4435 tree type, int named)
4437 int words = ia64_function_arg_words (type, mode);
4438 int offset = ia64_function_arg_offset (cum, type, words);
4439 enum machine_mode hfa_mode = VOIDmode;
4441 /* If all arg slots are already full, then there is nothing to do. */
4442 if (cum->words >= MAX_ARGUMENT_SLOTS)
4444 cum->words += words + offset;
4445 return;
4448 cum->atypes[cum->words] = ia64_arg_type (mode);
4449 cum->words += words + offset;
4451 /* Check for and handle homogeneous FP aggregates. */
4452 if (type)
4453 hfa_mode = hfa_element_mode (type, 0);
4455 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4456 and unprototyped hfas are passed specially. */
4457 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4459 int fp_regs = cum->fp_regs;
4460 /* This is the original value of cum->words + offset. */
4461 int int_regs = cum->words - words;
4462 int hfa_size = GET_MODE_SIZE (hfa_mode);
4463 int byte_size;
4464 int args_byte_size;
4466 /* If prototyped, pass it in FR regs then GR regs.
4467 If not prototyped, pass it in both FR and GR regs.
4469 If this is an SFmode aggregate, then it is possible to run out of
4470 FR regs while GR regs are still left. In that case, we pass the
4471 remaining part in the GR regs. */
4473 /* Fill the FP regs. We do this always. We stop if we reach the end
4474 of the argument, the last FP register, or the last argument slot. */
4476 byte_size = ((mode == BLKmode)
4477 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4478 args_byte_size = int_regs * UNITS_PER_WORD;
4479 offset = 0;
4480 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4481 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4483 offset += hfa_size;
4484 args_byte_size += hfa_size;
4485 fp_regs++;
4488 cum->fp_regs = fp_regs;
4491 /* On OpenVMS variable argument is either in Rn or Fn. */
4492 else if (TARGET_ABI_OPEN_VMS && named == 0)
4494 cum->int_regs = cum->words;
4495 cum->fp_regs = cum->words;
4498 /* Integral and aggregates go in general registers. So do TFmode FP values.
4499 If we have run out of FR registers, then other FP values must also go in
4500 general registers. This can happen when we have a SFmode HFA. */
4501 else if (mode == TFmode || mode == TCmode
4502 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4503 cum->int_regs = cum->words;
4505 /* If there is a prototype, then FP values go in a FR register when
4506 named, and in a GR register when unnamed. */
4507 else if (cum->prototype)
4509 if (! named)
4510 cum->int_regs = cum->words;
4511 else
4512 /* ??? Complex types should not reach here. */
4513 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4515 /* If there is no prototype, then FP values go in both FR and GR
4516 registers. */
4517 else
4519 /* ??? Complex types should not reach here. */
4520 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4521 cum->int_regs = cum->words;
4525 /* Arguments with alignment larger than 8 bytes start at the next even
4526 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4527 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4530 ia64_function_arg_boundary (enum machine_mode mode, tree type)
4533 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4534 return PARM_BOUNDARY * 2;
4536 if (type)
4538 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
4539 return PARM_BOUNDARY * 2;
4540 else
4541 return PARM_BOUNDARY;
4544 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4545 return PARM_BOUNDARY * 2;
4546 else
4547 return PARM_BOUNDARY;
4550 /* True if it is OK to do sibling call optimization for the specified
4551 call expression EXP. DECL will be the called function, or NULL if
4552 this is an indirect call. */
4553 static bool
4554 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4556 /* We can't perform a sibcall if the current function has the syscall_linkage
4557 attribute. */
4558 if (lookup_attribute ("syscall_linkage",
4559 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4560 return false;
4562 /* We must always return with our current GP. This means we can
4563 only sibcall to functions defined in the current module unless
4564 TARGET_CONST_GP is set to true. */
4565 return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP;
4569 /* Implement va_arg. */
4571 static tree
4572 ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
4573 gimple_seq *post_p)
4575 /* Variable sized types are passed by reference. */
4576 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4578 tree ptrtype = build_pointer_type (type);
4579 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
4580 return build_va_arg_indirect_ref (addr);
4583 /* Aggregate arguments with alignment larger than 8 bytes start at
4584 the next even boundary. Integer and floating point arguments
4585 do so if they are larger than 8 bytes, whether or not they are
4586 also aligned larger than 8 bytes. */
4587 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
4588 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
4590 tree t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (valist), valist,
4591 size_int (2 * UNITS_PER_WORD - 1));
4592 t = fold_convert (sizetype, t);
4593 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4594 size_int (-2 * UNITS_PER_WORD));
4595 t = fold_convert (TREE_TYPE (valist), t);
4596 gimplify_assign (unshare_expr (valist), t, pre_p);
4599 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4602 /* Return 1 if function return value returned in memory. Return 0 if it is
4603 in a register. */
4605 static bool
4606 ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED)
4608 enum machine_mode mode;
4609 enum machine_mode hfa_mode;
4610 HOST_WIDE_INT byte_size;
4612 mode = TYPE_MODE (valtype);
4613 byte_size = GET_MODE_SIZE (mode);
4614 if (mode == BLKmode)
4616 byte_size = int_size_in_bytes (valtype);
4617 if (byte_size < 0)
4618 return true;
4621 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4623 hfa_mode = hfa_element_mode (valtype, 0);
4624 if (hfa_mode != VOIDmode)
4626 int hfa_size = GET_MODE_SIZE (hfa_mode);
4628 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4629 return true;
4630 else
4631 return false;
4633 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4634 return true;
4635 else
4636 return false;
4639 /* Return rtx for register that holds the function return value. */
4642 ia64_function_value (const_tree valtype, const_tree func)
4644 enum machine_mode mode;
4645 enum machine_mode hfa_mode;
4646 int unsignedp;
4648 mode = TYPE_MODE (valtype);
4649 hfa_mode = hfa_element_mode (valtype, 0);
4651 if (hfa_mode != VOIDmode)
4653 rtx loc[8];
4654 int i;
4655 int hfa_size;
4656 int byte_size;
4657 int offset;
4659 hfa_size = GET_MODE_SIZE (hfa_mode);
4660 byte_size = ((mode == BLKmode)
4661 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4662 offset = 0;
4663 for (i = 0; offset < byte_size; i++)
4665 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4666 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4667 GEN_INT (offset));
4668 offset += hfa_size;
4670 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4672 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4673 return gen_rtx_REG (mode, FR_ARG_FIRST);
4674 else
4676 bool need_parallel = false;
4678 /* In big-endian mode, we need to manage the layout of aggregates
4679 in the registers so that we get the bits properly aligned in
4680 the highpart of the registers. */
4681 if (BYTES_BIG_ENDIAN
4682 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4683 need_parallel = true;
4685 /* Something like struct S { long double x; char a[0] } is not an
4686 HFA structure, and therefore doesn't go in fp registers. But
4687 the middle-end will give it XFmode anyway, and XFmode values
4688 don't normally fit in integer registers. So we need to smuggle
4689 the value inside a parallel. */
4690 else if (mode == XFmode || mode == XCmode || mode == RFmode)
4691 need_parallel = true;
4693 if (need_parallel)
4695 rtx loc[8];
4696 int offset;
4697 int bytesize;
4698 int i;
4700 offset = 0;
4701 bytesize = int_size_in_bytes (valtype);
4702 /* An empty PARALLEL is invalid here, but the return value
4703 doesn't matter for empty structs. */
4704 if (bytesize == 0)
4705 return gen_rtx_REG (mode, GR_RET_FIRST);
4706 for (i = 0; offset < bytesize; i++)
4708 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4709 gen_rtx_REG (DImode,
4710 GR_RET_FIRST + i),
4711 GEN_INT (offset));
4712 offset += UNITS_PER_WORD;
4714 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4717 mode = ia64_promote_function_mode (valtype, mode, &unsignedp,
4718 func ? TREE_TYPE (func) : NULL_TREE,
4719 true);
4721 return gen_rtx_REG (mode, GR_RET_FIRST);
4725 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4726 We need to emit DTP-relative relocations. */
4728 static void
4729 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4731 gcc_assert (size == 4 || size == 8);
4732 if (size == 4)
4733 fputs ("\tdata4.ua\t@dtprel(", file);
4734 else
4735 fputs ("\tdata8.ua\t@dtprel(", file);
4736 output_addr_const (file, x);
4737 fputs (")", file);
4740 /* Print a memory address as an operand to reference that memory location. */
4742 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4743 also call this from ia64_print_operand for memory addresses. */
4745 void
4746 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4747 rtx address ATTRIBUTE_UNUSED)
4751 /* Print an operand to an assembler instruction.
4752 C Swap and print a comparison operator.
4753 D Print an FP comparison operator.
4754 E Print 32 - constant, for SImode shifts as extract.
4755 e Print 64 - constant, for DImode rotates.
4756 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4757 a floating point register emitted normally.
4758 G A floating point constant.
4759 I Invert a predicate register by adding 1.
4760 J Select the proper predicate register for a condition.
4761 j Select the inverse predicate register for a condition.
4762 O Append .acq for volatile load.
4763 P Postincrement of a MEM.
4764 Q Append .rel for volatile store.
4765 R Print .s .d or nothing for a single, double or no truncation.
4766 S Shift amount for shladd instruction.
4767 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4768 for Intel assembler.
4769 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4770 for Intel assembler.
4771 X A pair of floating point registers.
4772 r Print register name, or constant 0 as r0. HP compatibility for
4773 Linux kernel.
4774 v Print vector constant value as an 8-byte integer value. */
4776 void
4777 ia64_print_operand (FILE * file, rtx x, int code)
4779 const char *str;
4781 switch (code)
4783 case 0:
4784 /* Handled below. */
4785 break;
4787 case 'C':
4789 enum rtx_code c = swap_condition (GET_CODE (x));
4790 fputs (GET_RTX_NAME (c), file);
4791 return;
4794 case 'D':
4795 switch (GET_CODE (x))
4797 case NE:
4798 str = "neq";
4799 break;
4800 case UNORDERED:
4801 str = "unord";
4802 break;
4803 case ORDERED:
4804 str = "ord";
4805 break;
4806 case UNLT:
4807 str = "nge";
4808 break;
4809 case UNLE:
4810 str = "ngt";
4811 break;
4812 case UNGT:
4813 str = "nle";
4814 break;
4815 case UNGE:
4816 str = "nlt";
4817 break;
4818 default:
4819 str = GET_RTX_NAME (GET_CODE (x));
4820 break;
4822 fputs (str, file);
4823 return;
4825 case 'E':
4826 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4827 return;
4829 case 'e':
4830 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4831 return;
4833 case 'F':
4834 if (x == CONST0_RTX (GET_MODE (x)))
4835 str = reg_names [FR_REG (0)];
4836 else if (x == CONST1_RTX (GET_MODE (x)))
4837 str = reg_names [FR_REG (1)];
4838 else
4840 gcc_assert (GET_CODE (x) == REG);
4841 str = reg_names [REGNO (x)];
4843 fputs (str, file);
4844 return;
4846 case 'G':
4848 long val[4];
4849 REAL_VALUE_TYPE rv;
4850 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
4851 real_to_target (val, &rv, GET_MODE (x));
4852 if (GET_MODE (x) == SFmode)
4853 fprintf (file, "0x%08lx", val[0] & 0xffffffff);
4854 else if (GET_MODE (x) == DFmode)
4855 fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1])
4856 & 0xffffffff,
4857 (WORDS_BIG_ENDIAN ? val[1] : val[0])
4858 & 0xffffffff);
4859 else
4860 output_operand_lossage ("invalid %%G mode");
4862 return;
4864 case 'I':
4865 fputs (reg_names [REGNO (x) + 1], file);
4866 return;
4868 case 'J':
4869 case 'j':
4871 unsigned int regno = REGNO (XEXP (x, 0));
4872 if (GET_CODE (x) == EQ)
4873 regno += 1;
4874 if (code == 'j')
4875 regno ^= 1;
4876 fputs (reg_names [regno], file);
4878 return;
4880 case 'O':
4881 if (MEM_VOLATILE_P (x))
4882 fputs(".acq", file);
4883 return;
4885 case 'P':
4887 HOST_WIDE_INT value;
4889 switch (GET_CODE (XEXP (x, 0)))
4891 default:
4892 return;
4894 case POST_MODIFY:
4895 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
4896 if (GET_CODE (x) == CONST_INT)
4897 value = INTVAL (x);
4898 else
4900 gcc_assert (GET_CODE (x) == REG);
4901 fprintf (file, ", %s", reg_names[REGNO (x)]);
4902 return;
4904 break;
4906 case POST_INC:
4907 value = GET_MODE_SIZE (GET_MODE (x));
4908 break;
4910 case POST_DEC:
4911 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
4912 break;
4915 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
4916 return;
4919 case 'Q':
4920 if (MEM_VOLATILE_P (x))
4921 fputs(".rel", file);
4922 return;
4924 case 'R':
4925 if (x == CONST0_RTX (GET_MODE (x)))
4926 fputs(".s", file);
4927 else if (x == CONST1_RTX (GET_MODE (x)))
4928 fputs(".d", file);
4929 else if (x == CONST2_RTX (GET_MODE (x)))
4931 else
4932 output_operand_lossage ("invalid %%R value");
4933 return;
4935 case 'S':
4936 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4937 return;
4939 case 'T':
4940 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4942 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
4943 return;
4945 break;
4947 case 'U':
4948 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4950 const char *prefix = "0x";
4951 if (INTVAL (x) & 0x80000000)
4953 fprintf (file, "0xffffffff");
4954 prefix = "";
4956 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
4957 return;
4959 break;
4961 case 'X':
4963 unsigned int regno = REGNO (x);
4964 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
4966 return;
4968 case 'r':
4969 /* If this operand is the constant zero, write it as register zero.
4970 Any register, zero, or CONST_INT value is OK here. */
4971 if (GET_CODE (x) == REG)
4972 fputs (reg_names[REGNO (x)], file);
4973 else if (x == CONST0_RTX (GET_MODE (x)))
4974 fputs ("r0", file);
4975 else if (GET_CODE (x) == CONST_INT)
4976 output_addr_const (file, x);
4977 else
4978 output_operand_lossage ("invalid %%r value");
4979 return;
4981 case 'v':
4982 gcc_assert (GET_CODE (x) == CONST_VECTOR);
4983 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
4984 break;
4986 case '+':
4988 const char *which;
4990 /* For conditional branches, returns or calls, substitute
4991 sptk, dptk, dpnt, or spnt for %s. */
4992 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4993 if (x)
4995 int pred_val = INTVAL (XEXP (x, 0));
4997 /* Guess top and bottom 10% statically predicted. */
4998 if (pred_val < REG_BR_PROB_BASE / 50
4999 && br_prob_note_reliable_p (x))
5000 which = ".spnt";
5001 else if (pred_val < REG_BR_PROB_BASE / 2)
5002 which = ".dpnt";
5003 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
5004 || !br_prob_note_reliable_p (x))
5005 which = ".dptk";
5006 else
5007 which = ".sptk";
5009 else if (GET_CODE (current_output_insn) == CALL_INSN)
5010 which = ".sptk";
5011 else
5012 which = ".dptk";
5014 fputs (which, file);
5015 return;
5018 case ',':
5019 x = current_insn_predicate;
5020 if (x)
5022 unsigned int regno = REGNO (XEXP (x, 0));
5023 if (GET_CODE (x) == EQ)
5024 regno += 1;
5025 fprintf (file, "(%s) ", reg_names [regno]);
5027 return;
5029 default:
5030 output_operand_lossage ("ia64_print_operand: unknown code");
5031 return;
5034 switch (GET_CODE (x))
5036 /* This happens for the spill/restore instructions. */
5037 case POST_INC:
5038 case POST_DEC:
5039 case POST_MODIFY:
5040 x = XEXP (x, 0);
5041 /* ... fall through ... */
5043 case REG:
5044 fputs (reg_names [REGNO (x)], file);
5045 break;
5047 case MEM:
5049 rtx addr = XEXP (x, 0);
5050 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
5051 addr = XEXP (addr, 0);
5052 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
5053 break;
5056 default:
5057 output_addr_const (file, x);
5058 break;
5061 return;
5064 /* Compute a (partial) cost for rtx X. Return true if the complete
5065 cost has been computed, and false if subexpressions should be
5066 scanned. In either case, *TOTAL contains the cost result. */
5067 /* ??? This is incomplete. */
5069 static bool
5070 ia64_rtx_costs (rtx x, int code, int outer_code, int *total,
5071 bool speed ATTRIBUTE_UNUSED)
5073 switch (code)
5075 case CONST_INT:
5076 switch (outer_code)
5078 case SET:
5079 *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1);
5080 return true;
5081 case PLUS:
5082 if (satisfies_constraint_I (x))
5083 *total = 0;
5084 else if (satisfies_constraint_J (x))
5085 *total = 1;
5086 else
5087 *total = COSTS_N_INSNS (1);
5088 return true;
5089 default:
5090 if (satisfies_constraint_K (x) || satisfies_constraint_L (x))
5091 *total = 0;
5092 else
5093 *total = COSTS_N_INSNS (1);
5094 return true;
5097 case CONST_DOUBLE:
5098 *total = COSTS_N_INSNS (1);
5099 return true;
5101 case CONST:
5102 case SYMBOL_REF:
5103 case LABEL_REF:
5104 *total = COSTS_N_INSNS (3);
5105 return true;
5107 case MULT:
5108 /* For multiplies wider than HImode, we have to go to the FPU,
5109 which normally involves copies. Plus there's the latency
5110 of the multiply itself, and the latency of the instructions to
5111 transfer integer regs to FP regs. */
5112 /* ??? Check for FP mode. */
5113 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
5114 *total = COSTS_N_INSNS (10);
5115 else
5116 *total = COSTS_N_INSNS (2);
5117 return true;
5119 case PLUS:
5120 case MINUS:
5121 case ASHIFT:
5122 case ASHIFTRT:
5123 case LSHIFTRT:
5124 *total = COSTS_N_INSNS (1);
5125 return true;
5127 case DIV:
5128 case UDIV:
5129 case MOD:
5130 case UMOD:
5131 /* We make divide expensive, so that divide-by-constant will be
5132 optimized to a multiply. */
5133 *total = COSTS_N_INSNS (60);
5134 return true;
5136 default:
5137 return false;
5141 /* Calculate the cost of moving data from a register in class FROM to
5142 one in class TO, using MODE. */
5145 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
5146 enum reg_class to)
5148 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5149 if (to == ADDL_REGS)
5150 to = GR_REGS;
5151 if (from == ADDL_REGS)
5152 from = GR_REGS;
5154 /* All costs are symmetric, so reduce cases by putting the
5155 lower number class as the destination. */
5156 if (from < to)
5158 enum reg_class tmp = to;
5159 to = from, from = tmp;
5162 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5163 so that we get secondary memory reloads. Between FR_REGS,
5164 we have to make this at least as expensive as MEMORY_MOVE_COST
5165 to avoid spectacularly poor register class preferencing. */
5166 if (mode == XFmode || mode == RFmode)
5168 if (to != GR_REGS || from != GR_REGS)
5169 return MEMORY_MOVE_COST (mode, to, 0);
5170 else
5171 return 3;
5174 switch (to)
5176 case PR_REGS:
5177 /* Moving between PR registers takes two insns. */
5178 if (from == PR_REGS)
5179 return 3;
5180 /* Moving between PR and anything but GR is impossible. */
5181 if (from != GR_REGS)
5182 return MEMORY_MOVE_COST (mode, to, 0);
5183 break;
5185 case BR_REGS:
5186 /* Moving between BR and anything but GR is impossible. */
5187 if (from != GR_REGS && from != GR_AND_BR_REGS)
5188 return MEMORY_MOVE_COST (mode, to, 0);
5189 break;
5191 case AR_I_REGS:
5192 case AR_M_REGS:
5193 /* Moving between AR and anything but GR is impossible. */
5194 if (from != GR_REGS)
5195 return MEMORY_MOVE_COST (mode, to, 0);
5196 break;
5198 case GR_REGS:
5199 case FR_REGS:
5200 case FP_REGS:
5201 case GR_AND_FR_REGS:
5202 case GR_AND_BR_REGS:
5203 case ALL_REGS:
5204 break;
5206 default:
5207 gcc_unreachable ();
5210 return 2;
5213 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on RCLASS
5214 to use when copying X into that class. */
5216 enum reg_class
5217 ia64_preferred_reload_class (rtx x, enum reg_class rclass)
5219 switch (rclass)
5221 case FR_REGS:
5222 case FP_REGS:
5223 /* Don't allow volatile mem reloads into floating point registers.
5224 This is defined to force reload to choose the r/m case instead
5225 of the f/f case when reloading (set (reg fX) (mem/v)). */
5226 if (MEM_P (x) && MEM_VOLATILE_P (x))
5227 return NO_REGS;
5229 /* Force all unrecognized constants into the constant pool. */
5230 if (CONSTANT_P (x))
5231 return NO_REGS;
5232 break;
5234 case AR_M_REGS:
5235 case AR_I_REGS:
5236 if (!OBJECT_P (x))
5237 return NO_REGS;
5238 break;
5240 default:
5241 break;
5244 return rclass;
5247 /* This function returns the register class required for a secondary
5248 register when copying between one of the registers in RCLASS, and X,
5249 using MODE. A return value of NO_REGS means that no secondary register
5250 is required. */
5252 enum reg_class
5253 ia64_secondary_reload_class (enum reg_class rclass,
5254 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5256 int regno = -1;
5258 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5259 regno = true_regnum (x);
5261 switch (rclass)
5263 case BR_REGS:
5264 case AR_M_REGS:
5265 case AR_I_REGS:
5266 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5267 interaction. We end up with two pseudos with overlapping lifetimes
5268 both of which are equiv to the same constant, and both which need
5269 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5270 changes depending on the path length, which means the qty_first_reg
5271 check in make_regs_eqv can give different answers at different times.
5272 At some point I'll probably need a reload_indi pattern to handle
5273 this.
5275 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5276 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5277 non-general registers for good measure. */
5278 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
5279 return GR_REGS;
5281 /* This is needed if a pseudo used as a call_operand gets spilled to a
5282 stack slot. */
5283 if (GET_CODE (x) == MEM)
5284 return GR_REGS;
5285 break;
5287 case FR_REGS:
5288 case FP_REGS:
5289 /* Need to go through general registers to get to other class regs. */
5290 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
5291 return GR_REGS;
5293 /* This can happen when a paradoxical subreg is an operand to the
5294 muldi3 pattern. */
5295 /* ??? This shouldn't be necessary after instruction scheduling is
5296 enabled, because paradoxical subregs are not accepted by
5297 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5298 stop the paradoxical subreg stupidity in the *_operand functions
5299 in recog.c. */
5300 if (GET_CODE (x) == MEM
5301 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
5302 || GET_MODE (x) == QImode))
5303 return GR_REGS;
5305 /* This can happen because of the ior/and/etc patterns that accept FP
5306 registers as operands. If the third operand is a constant, then it
5307 needs to be reloaded into a FP register. */
5308 if (GET_CODE (x) == CONST_INT)
5309 return GR_REGS;
5311 /* This can happen because of register elimination in a muldi3 insn.
5312 E.g. `26107 * (unsigned long)&u'. */
5313 if (GET_CODE (x) == PLUS)
5314 return GR_REGS;
5315 break;
5317 case PR_REGS:
5318 /* ??? This happens if we cse/gcse a BImode value across a call,
5319 and the function has a nonlocal goto. This is because global
5320 does not allocate call crossing pseudos to hard registers when
5321 crtl->has_nonlocal_goto is true. This is relatively
5322 common for C++ programs that use exceptions. To reproduce,
5323 return NO_REGS and compile libstdc++. */
5324 if (GET_CODE (x) == MEM)
5325 return GR_REGS;
5327 /* This can happen when we take a BImode subreg of a DImode value,
5328 and that DImode value winds up in some non-GR register. */
5329 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5330 return GR_REGS;
5331 break;
5333 default:
5334 break;
5337 return NO_REGS;
5341 /* Implement targetm.unspec_may_trap_p hook. */
5342 static int
5343 ia64_unspec_may_trap_p (const_rtx x, unsigned flags)
5345 if (GET_CODE (x) == UNSPEC)
5347 switch (XINT (x, 1))
5349 case UNSPEC_LDA:
5350 case UNSPEC_LDS:
5351 case UNSPEC_LDSA:
5352 case UNSPEC_LDCCLR:
5353 case UNSPEC_CHKACLR:
5354 case UNSPEC_CHKS:
5355 /* These unspecs are just wrappers. */
5356 return may_trap_p_1 (XVECEXP (x, 0, 0), flags);
5360 return default_unspec_may_trap_p (x, flags);
5364 /* Parse the -mfixed-range= option string. */
5366 static void
5367 fix_range (const char *const_str)
5369 int i, first, last;
5370 char *str, *dash, *comma;
5372 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5373 REG2 are either register names or register numbers. The effect
5374 of this option is to mark the registers in the range from REG1 to
5375 REG2 as ``fixed'' so they won't be used by the compiler. This is
5376 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5378 i = strlen (const_str);
5379 str = (char *) alloca (i + 1);
5380 memcpy (str, const_str, i + 1);
5382 while (1)
5384 dash = strchr (str, '-');
5385 if (!dash)
5387 warning (0, "value of -mfixed-range must have form REG1-REG2");
5388 return;
5390 *dash = '\0';
5392 comma = strchr (dash + 1, ',');
5393 if (comma)
5394 *comma = '\0';
5396 first = decode_reg_name (str);
5397 if (first < 0)
5399 warning (0, "unknown register name: %s", str);
5400 return;
5403 last = decode_reg_name (dash + 1);
5404 if (last < 0)
5406 warning (0, "unknown register name: %s", dash + 1);
5407 return;
5410 *dash = '-';
5412 if (first > last)
5414 warning (0, "%s-%s is an empty range", str, dash + 1);
5415 return;
5418 for (i = first; i <= last; ++i)
5419 fixed_regs[i] = call_used_regs[i] = 1;
5421 if (!comma)
5422 break;
5424 *comma = ',';
5425 str = comma + 1;
5429 /* Implement TARGET_HANDLE_OPTION. */
5431 static bool
5432 ia64_handle_option (size_t code, const char *arg, int value)
5434 switch (code)
5436 case OPT_mfixed_range_:
5437 fix_range (arg);
5438 return true;
5440 case OPT_mtls_size_:
5441 if (value != 14 && value != 22 && value != 64)
5442 error ("bad value %<%s%> for -mtls-size= switch", arg);
5443 return true;
5445 case OPT_mtune_:
5447 static struct pta
5449 const char *name; /* processor name or nickname. */
5450 enum processor_type processor;
5452 const processor_alias_table[] =
5454 {"itanium2", PROCESSOR_ITANIUM2},
5455 {"mckinley", PROCESSOR_ITANIUM2},
5457 int const pta_size = ARRAY_SIZE (processor_alias_table);
5458 int i;
5460 for (i = 0; i < pta_size; i++)
5461 if (!strcmp (arg, processor_alias_table[i].name))
5463 ia64_tune = processor_alias_table[i].processor;
5464 break;
5466 if (i == pta_size)
5467 error ("bad value %<%s%> for -mtune= switch", arg);
5468 return true;
5471 default:
5472 return true;
5476 /* Implement OVERRIDE_OPTIONS. */
5478 void
5479 ia64_override_options (void)
5481 if (TARGET_AUTO_PIC)
5482 target_flags |= MASK_CONST_GP;
5484 /* Numerous experiment shows that IRA based loop pressure
5485 calculation works better for RTL loop invariant motion on targets
5486 with enough (>= 32) registers. It is an expensive optimization.
5487 So it is on only for peak performance. */
5488 if (optimize >= 3)
5489 flag_ira_loop_pressure = 1;
5492 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
5494 init_machine_status = ia64_init_machine_status;
5496 if (align_functions <= 0)
5497 align_functions = 64;
5498 if (align_loops <= 0)
5499 align_loops = 32;
5500 if (TARGET_ABI_OPEN_VMS)
5501 flag_no_common = 1;
5503 ia64_override_options_after_change();
5506 /* Implement targetm.override_options_after_change. */
5508 static void
5509 ia64_override_options_after_change (void)
5511 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
5512 flag_schedule_insns_after_reload = 0;
5514 if (optimize >= 3
5515 && ! sel_sched_switch_set)
5517 flag_selective_scheduling2 = 1;
5518 flag_sel_sched_pipelining = 1;
5520 if (mflag_sched_control_spec == 2)
5522 /* Control speculation is on by default for the selective scheduler,
5523 but not for the Haifa scheduler. */
5524 mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
5526 if (flag_sel_sched_pipelining && flag_auto_inc_dec)
5528 /* FIXME: remove this when we'd implement breaking autoinsns as
5529 a transformation. */
5530 flag_auto_inc_dec = 0;
5534 /* Initialize the record of emitted frame related registers. */
5536 void ia64_init_expanders (void)
5538 memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs));
5541 static struct machine_function *
5542 ia64_init_machine_status (void)
5544 return GGC_CNEW (struct machine_function);
5547 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
5548 static enum attr_type ia64_safe_type (rtx);
5550 static enum attr_itanium_class
5551 ia64_safe_itanium_class (rtx insn)
5553 if (recog_memoized (insn) >= 0)
5554 return get_attr_itanium_class (insn);
5555 else if (DEBUG_INSN_P (insn))
5556 return ITANIUM_CLASS_IGNORE;
5557 else
5558 return ITANIUM_CLASS_UNKNOWN;
5561 static enum attr_type
5562 ia64_safe_type (rtx insn)
5564 if (recog_memoized (insn) >= 0)
5565 return get_attr_type (insn);
5566 else
5567 return TYPE_UNKNOWN;
5570 /* The following collection of routines emit instruction group stop bits as
5571 necessary to avoid dependencies. */
5573 /* Need to track some additional registers as far as serialization is
5574 concerned so we can properly handle br.call and br.ret. We could
5575 make these registers visible to gcc, but since these registers are
5576 never explicitly used in gcc generated code, it seems wasteful to
5577 do so (plus it would make the call and return patterns needlessly
5578 complex). */
5579 #define REG_RP (BR_REG (0))
5580 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
5581 /* This is used for volatile asms which may require a stop bit immediately
5582 before and after them. */
5583 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
5584 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
5585 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
5587 /* For each register, we keep track of how it has been written in the
5588 current instruction group.
5590 If a register is written unconditionally (no qualifying predicate),
5591 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
5593 If a register is written if its qualifying predicate P is true, we
5594 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
5595 may be written again by the complement of P (P^1) and when this happens,
5596 WRITE_COUNT gets set to 2.
5598 The result of this is that whenever an insn attempts to write a register
5599 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
5601 If a predicate register is written by a floating-point insn, we set
5602 WRITTEN_BY_FP to true.
5604 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
5605 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
5607 #if GCC_VERSION >= 4000
5608 #define RWS_FIELD_TYPE __extension__ unsigned short
5609 #else
5610 #define RWS_FIELD_TYPE unsigned int
5611 #endif
5612 struct reg_write_state
5614 RWS_FIELD_TYPE write_count : 2;
5615 RWS_FIELD_TYPE first_pred : 10;
5616 RWS_FIELD_TYPE written_by_fp : 1;
5617 RWS_FIELD_TYPE written_by_and : 1;
5618 RWS_FIELD_TYPE written_by_or : 1;
5621 /* Cumulative info for the current instruction group. */
5622 struct reg_write_state rws_sum[NUM_REGS];
5623 #ifdef ENABLE_CHECKING
5624 /* Bitmap whether a register has been written in the current insn. */
5625 HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1)
5626 / HOST_BITS_PER_WIDEST_FAST_INT];
5628 static inline void
5629 rws_insn_set (int regno)
5631 gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno));
5632 SET_HARD_REG_BIT (rws_insn, regno);
5635 static inline int
5636 rws_insn_test (int regno)
5638 return TEST_HARD_REG_BIT (rws_insn, regno);
5640 #else
5641 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
5642 unsigned char rws_insn[2];
5644 static inline void
5645 rws_insn_set (int regno)
5647 if (regno == REG_AR_CFM)
5648 rws_insn[0] = 1;
5649 else if (regno == REG_VOLATILE)
5650 rws_insn[1] = 1;
5653 static inline int
5654 rws_insn_test (int regno)
5656 if (regno == REG_AR_CFM)
5657 return rws_insn[0];
5658 if (regno == REG_VOLATILE)
5659 return rws_insn[1];
5660 return 0;
5662 #endif
5664 /* Indicates whether this is the first instruction after a stop bit,
5665 in which case we don't need another stop bit. Without this,
5666 ia64_variable_issue will die when scheduling an alloc. */
5667 static int first_instruction;
5669 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5670 RTL for one instruction. */
5671 struct reg_flags
5673 unsigned int is_write : 1; /* Is register being written? */
5674 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
5675 unsigned int is_branch : 1; /* Is register used as part of a branch? */
5676 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
5677 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
5678 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
5681 static void rws_update (int, struct reg_flags, int);
5682 static int rws_access_regno (int, struct reg_flags, int);
5683 static int rws_access_reg (rtx, struct reg_flags, int);
5684 static void update_set_flags (rtx, struct reg_flags *);
5685 static int set_src_needs_barrier (rtx, struct reg_flags, int);
5686 static int rtx_needs_barrier (rtx, struct reg_flags, int);
5687 static void init_insn_group_barriers (void);
5688 static int group_barrier_needed (rtx);
5689 static int safe_group_barrier_needed (rtx);
5690 static int in_safe_group_barrier;
5692 /* Update *RWS for REGNO, which is being written by the current instruction,
5693 with predicate PRED, and associated register flags in FLAGS. */
5695 static void
5696 rws_update (int regno, struct reg_flags flags, int pred)
5698 if (pred)
5699 rws_sum[regno].write_count++;
5700 else
5701 rws_sum[regno].write_count = 2;
5702 rws_sum[regno].written_by_fp |= flags.is_fp;
5703 /* ??? Not tracking and/or across differing predicates. */
5704 rws_sum[regno].written_by_and = flags.is_and;
5705 rws_sum[regno].written_by_or = flags.is_or;
5706 rws_sum[regno].first_pred = pred;
5709 /* Handle an access to register REGNO of type FLAGS using predicate register
5710 PRED. Update rws_sum array. Return 1 if this access creates
5711 a dependency with an earlier instruction in the same group. */
5713 static int
5714 rws_access_regno (int regno, struct reg_flags flags, int pred)
5716 int need_barrier = 0;
5718 gcc_assert (regno < NUM_REGS);
5720 if (! PR_REGNO_P (regno))
5721 flags.is_and = flags.is_or = 0;
5723 if (flags.is_write)
5725 int write_count;
5727 rws_insn_set (regno);
5728 write_count = rws_sum[regno].write_count;
5730 switch (write_count)
5732 case 0:
5733 /* The register has not been written yet. */
5734 if (!in_safe_group_barrier)
5735 rws_update (regno, flags, pred);
5736 break;
5738 case 1:
5739 /* The register has been written via a predicate. If this is
5740 not a complementary predicate, then we need a barrier. */
5741 /* ??? This assumes that P and P+1 are always complementary
5742 predicates for P even. */
5743 if (flags.is_and && rws_sum[regno].written_by_and)
5745 else if (flags.is_or && rws_sum[regno].written_by_or)
5747 else if ((rws_sum[regno].first_pred ^ 1) != pred)
5748 need_barrier = 1;
5749 if (!in_safe_group_barrier)
5750 rws_update (regno, flags, pred);
5751 break;
5753 case 2:
5754 /* The register has been unconditionally written already. We
5755 need a barrier. */
5756 if (flags.is_and && rws_sum[regno].written_by_and)
5758 else if (flags.is_or && rws_sum[regno].written_by_or)
5760 else
5761 need_barrier = 1;
5762 if (!in_safe_group_barrier)
5764 rws_sum[regno].written_by_and = flags.is_and;
5765 rws_sum[regno].written_by_or = flags.is_or;
5767 break;
5769 default:
5770 gcc_unreachable ();
5773 else
5775 if (flags.is_branch)
5777 /* Branches have several RAW exceptions that allow to avoid
5778 barriers. */
5780 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
5781 /* RAW dependencies on branch regs are permissible as long
5782 as the writer is a non-branch instruction. Since we
5783 never generate code that uses a branch register written
5784 by a branch instruction, handling this case is
5785 easy. */
5786 return 0;
5788 if (REGNO_REG_CLASS (regno) == PR_REGS
5789 && ! rws_sum[regno].written_by_fp)
5790 /* The predicates of a branch are available within the
5791 same insn group as long as the predicate was written by
5792 something other than a floating-point instruction. */
5793 return 0;
5796 if (flags.is_and && rws_sum[regno].written_by_and)
5797 return 0;
5798 if (flags.is_or && rws_sum[regno].written_by_or)
5799 return 0;
5801 switch (rws_sum[regno].write_count)
5803 case 0:
5804 /* The register has not been written yet. */
5805 break;
5807 case 1:
5808 /* The register has been written via a predicate. If this is
5809 not a complementary predicate, then we need a barrier. */
5810 /* ??? This assumes that P and P+1 are always complementary
5811 predicates for P even. */
5812 if ((rws_sum[regno].first_pred ^ 1) != pred)
5813 need_barrier = 1;
5814 break;
5816 case 2:
5817 /* The register has been unconditionally written already. We
5818 need a barrier. */
5819 need_barrier = 1;
5820 break;
5822 default:
5823 gcc_unreachable ();
5827 return need_barrier;
5830 static int
5831 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5833 int regno = REGNO (reg);
5834 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5836 if (n == 1)
5837 return rws_access_regno (regno, flags, pred);
5838 else
5840 int need_barrier = 0;
5841 while (--n >= 0)
5842 need_barrier |= rws_access_regno (regno + n, flags, pred);
5843 return need_barrier;
5847 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5848 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5850 static void
5851 update_set_flags (rtx x, struct reg_flags *pflags)
5853 rtx src = SET_SRC (x);
5855 switch (GET_CODE (src))
5857 case CALL:
5858 return;
5860 case IF_THEN_ELSE:
5861 /* There are four cases here:
5862 (1) The destination is (pc), in which case this is a branch,
5863 nothing here applies.
5864 (2) The destination is ar.lc, in which case this is a
5865 doloop_end_internal,
5866 (3) The destination is an fp register, in which case this is
5867 an fselect instruction.
5868 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
5869 this is a check load.
5870 In all cases, nothing we do in this function applies. */
5871 return;
5873 default:
5874 if (COMPARISON_P (src)
5875 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
5876 /* Set pflags->is_fp to 1 so that we know we're dealing
5877 with a floating point comparison when processing the
5878 destination of the SET. */
5879 pflags->is_fp = 1;
5881 /* Discover if this is a parallel comparison. We only handle
5882 and.orcm and or.andcm at present, since we must retain a
5883 strict inverse on the predicate pair. */
5884 else if (GET_CODE (src) == AND)
5885 pflags->is_and = 1;
5886 else if (GET_CODE (src) == IOR)
5887 pflags->is_or = 1;
5889 break;
5893 /* Subroutine of rtx_needs_barrier; this function determines whether the
5894 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5895 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5896 for this insn. */
5898 static int
5899 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
5901 int need_barrier = 0;
5902 rtx dst;
5903 rtx src = SET_SRC (x);
5905 if (GET_CODE (src) == CALL)
5906 /* We don't need to worry about the result registers that
5907 get written by subroutine call. */
5908 return rtx_needs_barrier (src, flags, pred);
5909 else if (SET_DEST (x) == pc_rtx)
5911 /* X is a conditional branch. */
5912 /* ??? This seems redundant, as the caller sets this bit for
5913 all JUMP_INSNs. */
5914 if (!ia64_spec_check_src_p (src))
5915 flags.is_branch = 1;
5916 return rtx_needs_barrier (src, flags, pred);
5919 if (ia64_spec_check_src_p (src))
5920 /* Avoid checking one register twice (in condition
5921 and in 'then' section) for ldc pattern. */
5923 gcc_assert (REG_P (XEXP (src, 2)));
5924 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
5926 /* We process MEM below. */
5927 src = XEXP (src, 1);
5930 need_barrier |= rtx_needs_barrier (src, flags, pred);
5932 dst = SET_DEST (x);
5933 if (GET_CODE (dst) == ZERO_EXTRACT)
5935 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
5936 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
5938 return need_barrier;
5941 /* Handle an access to rtx X of type FLAGS using predicate register
5942 PRED. Return 1 if this access creates a dependency with an earlier
5943 instruction in the same group. */
5945 static int
5946 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
5948 int i, j;
5949 int is_complemented = 0;
5950 int need_barrier = 0;
5951 const char *format_ptr;
5952 struct reg_flags new_flags;
5953 rtx cond;
5955 if (! x)
5956 return 0;
5958 new_flags = flags;
5960 switch (GET_CODE (x))
5962 case SET:
5963 update_set_flags (x, &new_flags);
5964 need_barrier = set_src_needs_barrier (x, new_flags, pred);
5965 if (GET_CODE (SET_SRC (x)) != CALL)
5967 new_flags.is_write = 1;
5968 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
5970 break;
5972 case CALL:
5973 new_flags.is_write = 0;
5974 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5976 /* Avoid multiple register writes, in case this is a pattern with
5977 multiple CALL rtx. This avoids a failure in rws_access_reg. */
5978 if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM))
5980 new_flags.is_write = 1;
5981 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
5982 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
5983 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5985 break;
5987 case COND_EXEC:
5988 /* X is a predicated instruction. */
5990 cond = COND_EXEC_TEST (x);
5991 gcc_assert (!pred);
5992 need_barrier = rtx_needs_barrier (cond, flags, 0);
5994 if (GET_CODE (cond) == EQ)
5995 is_complemented = 1;
5996 cond = XEXP (cond, 0);
5997 gcc_assert (GET_CODE (cond) == REG
5998 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
5999 pred = REGNO (cond);
6000 if (is_complemented)
6001 ++pred;
6003 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
6004 return need_barrier;
6006 case CLOBBER:
6007 case USE:
6008 /* Clobber & use are for earlier compiler-phases only. */
6009 break;
6011 case ASM_OPERANDS:
6012 case ASM_INPUT:
6013 /* We always emit stop bits for traditional asms. We emit stop bits
6014 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6015 if (GET_CODE (x) != ASM_OPERANDS
6016 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
6018 /* Avoid writing the register multiple times if we have multiple
6019 asm outputs. This avoids a failure in rws_access_reg. */
6020 if (! rws_insn_test (REG_VOLATILE))
6022 new_flags.is_write = 1;
6023 rws_access_regno (REG_VOLATILE, new_flags, pred);
6025 return 1;
6028 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6029 We cannot just fall through here since then we would be confused
6030 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6031 traditional asms unlike their normal usage. */
6033 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
6034 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
6035 need_barrier = 1;
6036 break;
6038 case PARALLEL:
6039 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6041 rtx pat = XVECEXP (x, 0, i);
6042 switch (GET_CODE (pat))
6044 case SET:
6045 update_set_flags (pat, &new_flags);
6046 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
6047 break;
6049 case USE:
6050 case CALL:
6051 case ASM_OPERANDS:
6052 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6053 break;
6055 case CLOBBER:
6056 case RETURN:
6057 break;
6059 default:
6060 gcc_unreachable ();
6063 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6065 rtx pat = XVECEXP (x, 0, i);
6066 if (GET_CODE (pat) == SET)
6068 if (GET_CODE (SET_SRC (pat)) != CALL)
6070 new_flags.is_write = 1;
6071 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
6072 pred);
6075 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
6076 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6078 break;
6080 case SUBREG:
6081 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
6082 break;
6083 case REG:
6084 if (REGNO (x) == AR_UNAT_REGNUM)
6086 for (i = 0; i < 64; ++i)
6087 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
6089 else
6090 need_barrier = rws_access_reg (x, flags, pred);
6091 break;
6093 case MEM:
6094 /* Find the regs used in memory address computation. */
6095 new_flags.is_write = 0;
6096 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6097 break;
6099 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
6100 case SYMBOL_REF: case LABEL_REF: case CONST:
6101 break;
6103 /* Operators with side-effects. */
6104 case POST_INC: case POST_DEC:
6105 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6107 new_flags.is_write = 0;
6108 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6109 new_flags.is_write = 1;
6110 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6111 break;
6113 case POST_MODIFY:
6114 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6116 new_flags.is_write = 0;
6117 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6118 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6119 new_flags.is_write = 1;
6120 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6121 break;
6123 /* Handle common unary and binary ops for efficiency. */
6124 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
6125 case MOD: case UDIV: case UMOD: case AND: case IOR:
6126 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
6127 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
6128 case NE: case EQ: case GE: case GT: case LE:
6129 case LT: case GEU: case GTU: case LEU: case LTU:
6130 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6131 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6132 break;
6134 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
6135 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
6136 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
6137 case SQRT: case FFS: case POPCOUNT:
6138 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6139 break;
6141 case VEC_SELECT:
6142 /* VEC_SELECT's second argument is a PARALLEL with integers that
6143 describe the elements selected. On ia64, those integers are
6144 always constants. Avoid walking the PARALLEL so that we don't
6145 get confused with "normal" parallels and then die. */
6146 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6147 break;
6149 case UNSPEC:
6150 switch (XINT (x, 1))
6152 case UNSPEC_LTOFF_DTPMOD:
6153 case UNSPEC_LTOFF_DTPREL:
6154 case UNSPEC_DTPREL:
6155 case UNSPEC_LTOFF_TPREL:
6156 case UNSPEC_TPREL:
6157 case UNSPEC_PRED_REL_MUTEX:
6158 case UNSPEC_PIC_CALL:
6159 case UNSPEC_MF:
6160 case UNSPEC_FETCHADD_ACQ:
6161 case UNSPEC_BSP_VALUE:
6162 case UNSPEC_FLUSHRS:
6163 case UNSPEC_BUNDLE_SELECTOR:
6164 break;
6166 case UNSPEC_GR_SPILL:
6167 case UNSPEC_GR_RESTORE:
6169 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
6170 HOST_WIDE_INT bit = (offset >> 3) & 63;
6172 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6173 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
6174 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
6175 new_flags, pred);
6176 break;
6179 case UNSPEC_FR_SPILL:
6180 case UNSPEC_FR_RESTORE:
6181 case UNSPEC_GETF_EXP:
6182 case UNSPEC_SETF_EXP:
6183 case UNSPEC_ADDP4:
6184 case UNSPEC_FR_SQRT_RECIP_APPROX:
6185 case UNSPEC_FR_SQRT_RECIP_APPROX_RES:
6186 case UNSPEC_LDA:
6187 case UNSPEC_LDS:
6188 case UNSPEC_LDS_A:
6189 case UNSPEC_LDSA:
6190 case UNSPEC_CHKACLR:
6191 case UNSPEC_CHKS:
6192 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6193 break;
6195 case UNSPEC_FR_RECIP_APPROX:
6196 case UNSPEC_SHRP:
6197 case UNSPEC_COPYSIGN:
6198 case UNSPEC_FR_RECIP_APPROX_RES:
6199 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6200 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6201 break;
6203 case UNSPEC_CMPXCHG_ACQ:
6204 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6205 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
6206 break;
6208 default:
6209 gcc_unreachable ();
6211 break;
6213 case UNSPEC_VOLATILE:
6214 switch (XINT (x, 1))
6216 case UNSPECV_ALLOC:
6217 /* Alloc must always be the first instruction of a group.
6218 We force this by always returning true. */
6219 /* ??? We might get better scheduling if we explicitly check for
6220 input/local/output register dependencies, and modify the
6221 scheduler so that alloc is always reordered to the start of
6222 the current group. We could then eliminate all of the
6223 first_instruction code. */
6224 rws_access_regno (AR_PFS_REGNUM, flags, pred);
6226 new_flags.is_write = 1;
6227 rws_access_regno (REG_AR_CFM, new_flags, pred);
6228 return 1;
6230 case UNSPECV_SET_BSP:
6231 need_barrier = 1;
6232 break;
6234 case UNSPECV_BLOCKAGE:
6235 case UNSPECV_INSN_GROUP_BARRIER:
6236 case UNSPECV_BREAK:
6237 case UNSPECV_PSAC_ALL:
6238 case UNSPECV_PSAC_NORMAL:
6239 return 0;
6241 default:
6242 gcc_unreachable ();
6244 break;
6246 case RETURN:
6247 new_flags.is_write = 0;
6248 need_barrier = rws_access_regno (REG_RP, flags, pred);
6249 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
6251 new_flags.is_write = 1;
6252 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6253 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6254 break;
6256 default:
6257 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
6258 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6259 switch (format_ptr[i])
6261 case '0': /* unused field */
6262 case 'i': /* integer */
6263 case 'n': /* note */
6264 case 'w': /* wide integer */
6265 case 's': /* pointer to string */
6266 case 'S': /* optional pointer to string */
6267 break;
6269 case 'e':
6270 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
6271 need_barrier = 1;
6272 break;
6274 case 'E':
6275 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
6276 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
6277 need_barrier = 1;
6278 break;
6280 default:
6281 gcc_unreachable ();
6283 break;
6285 return need_barrier;
6288 /* Clear out the state for group_barrier_needed at the start of a
6289 sequence of insns. */
6291 static void
6292 init_insn_group_barriers (void)
6294 memset (rws_sum, 0, sizeof (rws_sum));
6295 first_instruction = 1;
6298 /* Given the current state, determine whether a group barrier (a stop bit) is
6299 necessary before INSN. Return nonzero if so. This modifies the state to
6300 include the effects of INSN as a side-effect. */
6302 static int
6303 group_barrier_needed (rtx insn)
6305 rtx pat;
6306 int need_barrier = 0;
6307 struct reg_flags flags;
6309 memset (&flags, 0, sizeof (flags));
6310 switch (GET_CODE (insn))
6312 case NOTE:
6313 case DEBUG_INSN:
6314 break;
6316 case BARRIER:
6317 /* A barrier doesn't imply an instruction group boundary. */
6318 break;
6320 case CODE_LABEL:
6321 memset (rws_insn, 0, sizeof (rws_insn));
6322 return 1;
6324 case CALL_INSN:
6325 flags.is_branch = 1;
6326 flags.is_sibcall = SIBLING_CALL_P (insn);
6327 memset (rws_insn, 0, sizeof (rws_insn));
6329 /* Don't bundle a call following another call. */
6330 if ((pat = prev_active_insn (insn))
6331 && GET_CODE (pat) == CALL_INSN)
6333 need_barrier = 1;
6334 break;
6337 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
6338 break;
6340 case JUMP_INSN:
6341 if (!ia64_spec_check_p (insn))
6342 flags.is_branch = 1;
6344 /* Don't bundle a jump following a call. */
6345 if ((pat = prev_active_insn (insn))
6346 && GET_CODE (pat) == CALL_INSN)
6348 need_barrier = 1;
6349 break;
6351 /* FALLTHRU */
6353 case INSN:
6354 if (GET_CODE (PATTERN (insn)) == USE
6355 || GET_CODE (PATTERN (insn)) == CLOBBER)
6356 /* Don't care about USE and CLOBBER "insns"---those are used to
6357 indicate to the optimizer that it shouldn't get rid of
6358 certain operations. */
6359 break;
6361 pat = PATTERN (insn);
6363 /* Ug. Hack hacks hacked elsewhere. */
6364 switch (recog_memoized (insn))
6366 /* We play dependency tricks with the epilogue in order
6367 to get proper schedules. Undo this for dv analysis. */
6368 case CODE_FOR_epilogue_deallocate_stack:
6369 case CODE_FOR_prologue_allocate_stack:
6370 pat = XVECEXP (pat, 0, 0);
6371 break;
6373 /* The pattern we use for br.cloop confuses the code above.
6374 The second element of the vector is representative. */
6375 case CODE_FOR_doloop_end_internal:
6376 pat = XVECEXP (pat, 0, 1);
6377 break;
6379 /* Doesn't generate code. */
6380 case CODE_FOR_pred_rel_mutex:
6381 case CODE_FOR_prologue_use:
6382 return 0;
6384 default:
6385 break;
6388 memset (rws_insn, 0, sizeof (rws_insn));
6389 need_barrier = rtx_needs_barrier (pat, flags, 0);
6391 /* Check to see if the previous instruction was a volatile
6392 asm. */
6393 if (! need_barrier)
6394 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
6396 break;
6398 default:
6399 gcc_unreachable ();
6402 if (first_instruction && INSN_P (insn)
6403 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6404 && GET_CODE (PATTERN (insn)) != USE
6405 && GET_CODE (PATTERN (insn)) != CLOBBER)
6407 need_barrier = 0;
6408 first_instruction = 0;
6411 return need_barrier;
6414 /* Like group_barrier_needed, but do not clobber the current state. */
6416 static int
6417 safe_group_barrier_needed (rtx insn)
6419 int saved_first_instruction;
6420 int t;
6422 saved_first_instruction = first_instruction;
6423 in_safe_group_barrier = 1;
6425 t = group_barrier_needed (insn);
6427 first_instruction = saved_first_instruction;
6428 in_safe_group_barrier = 0;
6430 return t;
6433 /* Scan the current function and insert stop bits as necessary to
6434 eliminate dependencies. This function assumes that a final
6435 instruction scheduling pass has been run which has already
6436 inserted most of the necessary stop bits. This function only
6437 inserts new ones at basic block boundaries, since these are
6438 invisible to the scheduler. */
6440 static void
6441 emit_insn_group_barriers (FILE *dump)
6443 rtx insn;
6444 rtx last_label = 0;
6445 int insns_since_last_label = 0;
6447 init_insn_group_barriers ();
6449 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6451 if (GET_CODE (insn) == CODE_LABEL)
6453 if (insns_since_last_label)
6454 last_label = insn;
6455 insns_since_last_label = 0;
6457 else if (GET_CODE (insn) == NOTE
6458 && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK)
6460 if (insns_since_last_label)
6461 last_label = insn;
6462 insns_since_last_label = 0;
6464 else if (GET_CODE (insn) == INSN
6465 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6466 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6468 init_insn_group_barriers ();
6469 last_label = 0;
6471 else if (NONDEBUG_INSN_P (insn))
6473 insns_since_last_label = 1;
6475 if (group_barrier_needed (insn))
6477 if (last_label)
6479 if (dump)
6480 fprintf (dump, "Emitting stop before label %d\n",
6481 INSN_UID (last_label));
6482 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6483 insn = last_label;
6485 init_insn_group_barriers ();
6486 last_label = 0;
6493 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6494 This function has to emit all necessary group barriers. */
6496 static void
6497 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
6499 rtx insn;
6501 init_insn_group_barriers ();
6503 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6505 if (GET_CODE (insn) == BARRIER)
6507 rtx last = prev_active_insn (insn);
6509 if (! last)
6510 continue;
6511 if (GET_CODE (last) == JUMP_INSN
6512 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6513 last = prev_active_insn (last);
6514 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6515 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6517 init_insn_group_barriers ();
6519 else if (NONDEBUG_INSN_P (insn))
6521 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6522 init_insn_group_barriers ();
6523 else if (group_barrier_needed (insn))
6525 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
6526 init_insn_group_barriers ();
6527 group_barrier_needed (insn);
6535 /* Instruction scheduling support. */
6537 #define NR_BUNDLES 10
6539 /* A list of names of all available bundles. */
6541 static const char *bundle_name [NR_BUNDLES] =
6543 ".mii",
6544 ".mmi",
6545 ".mfi",
6546 ".mmf",
6547 #if NR_BUNDLES == 10
6548 ".bbb",
6549 ".mbb",
6550 #endif
6551 ".mib",
6552 ".mmb",
6553 ".mfb",
6554 ".mlx"
6557 /* Nonzero if we should insert stop bits into the schedule. */
6559 int ia64_final_schedule = 0;
6561 /* Codes of the corresponding queried units: */
6563 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
6564 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
6566 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
6567 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
6569 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
6571 /* The following variable value is an insn group barrier. */
6573 static rtx dfa_stop_insn;
6575 /* The following variable value is the last issued insn. */
6577 static rtx last_scheduled_insn;
6579 /* The following variable value is pointer to a DFA state used as
6580 temporary variable. */
6582 static state_t temp_dfa_state = NULL;
6584 /* The following variable value is DFA state after issuing the last
6585 insn. */
6587 static state_t prev_cycle_state = NULL;
6589 /* The following array element values are TRUE if the corresponding
6590 insn requires to add stop bits before it. */
6592 static char *stops_p = NULL;
6594 /* The following variable is used to set up the mentioned above array. */
6596 static int stop_before_p = 0;
6598 /* The following variable value is length of the arrays `clocks' and
6599 `add_cycles'. */
6601 static int clocks_length;
6603 /* The following variable value is number of data speculations in progress. */
6604 static int pending_data_specs = 0;
6606 /* Number of memory references on current and three future processor cycles. */
6607 static char mem_ops_in_group[4];
6609 /* Number of current processor cycle (from scheduler's point of view). */
6610 static int current_cycle;
6612 static rtx ia64_single_set (rtx);
6613 static void ia64_emit_insn_before (rtx, rtx);
6615 /* Map a bundle number to its pseudo-op. */
6617 const char *
6618 get_bundle_name (int b)
6620 return bundle_name[b];
6624 /* Return the maximum number of instructions a cpu can issue. */
6626 static int
6627 ia64_issue_rate (void)
6629 return 6;
6632 /* Helper function - like single_set, but look inside COND_EXEC. */
6634 static rtx
6635 ia64_single_set (rtx insn)
6637 rtx x = PATTERN (insn), ret;
6638 if (GET_CODE (x) == COND_EXEC)
6639 x = COND_EXEC_CODE (x);
6640 if (GET_CODE (x) == SET)
6641 return x;
6643 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6644 Although they are not classical single set, the second set is there just
6645 to protect it from moving past FP-relative stack accesses. */
6646 switch (recog_memoized (insn))
6648 case CODE_FOR_prologue_allocate_stack:
6649 case CODE_FOR_epilogue_deallocate_stack:
6650 ret = XVECEXP (x, 0, 0);
6651 break;
6653 default:
6654 ret = single_set_2 (insn, x);
6655 break;
6658 return ret;
6661 /* Adjust the cost of a scheduling dependency.
6662 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
6663 COST is the current cost, DW is dependency weakness. */
6664 static int
6665 ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost, dw_t dw)
6667 enum reg_note dep_type = (enum reg_note) dep_type1;
6668 enum attr_itanium_class dep_class;
6669 enum attr_itanium_class insn_class;
6671 insn_class = ia64_safe_itanium_class (insn);
6672 dep_class = ia64_safe_itanium_class (dep_insn);
6674 /* Treat true memory dependencies separately. Ignore apparent true
6675 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
6676 if (dep_type == REG_DEP_TRUE
6677 && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF)
6678 && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL))
6679 return 0;
6681 if (dw == MIN_DEP_WEAK)
6682 /* Store and load are likely to alias, use higher cost to avoid stall. */
6683 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST);
6684 else if (dw > MIN_DEP_WEAK)
6686 /* Store and load are less likely to alias. */
6687 if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF)
6688 /* Assume there will be no cache conflict for floating-point data.
6689 For integer data, L1 conflict penalty is huge (17 cycles), so we
6690 never assume it will not cause a conflict. */
6691 return 0;
6692 else
6693 return cost;
6696 if (dep_type != REG_DEP_OUTPUT)
6697 return cost;
6699 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6700 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6701 return 0;
6703 return cost;
6706 /* Like emit_insn_before, but skip cycle_display notes.
6707 ??? When cycle display notes are implemented, update this. */
6709 static void
6710 ia64_emit_insn_before (rtx insn, rtx before)
6712 emit_insn_before (insn, before);
6715 /* The following function marks insns who produce addresses for load
6716 and store insns. Such insns will be placed into M slots because it
6717 decrease latency time for Itanium1 (see function
6718 `ia64_produce_address_p' and the DFA descriptions). */
6720 static void
6721 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6723 rtx insn, next, next_tail;
6725 /* Before reload, which_alternative is not set, which means that
6726 ia64_safe_itanium_class will produce wrong results for (at least)
6727 move instructions. */
6728 if (!reload_completed)
6729 return;
6731 next_tail = NEXT_INSN (tail);
6732 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6733 if (INSN_P (insn))
6734 insn->call = 0;
6735 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6736 if (INSN_P (insn)
6737 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6739 sd_iterator_def sd_it;
6740 dep_t dep;
6741 bool has_mem_op_consumer_p = false;
6743 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
6745 enum attr_itanium_class c;
6747 if (DEP_TYPE (dep) != REG_DEP_TRUE)
6748 continue;
6750 next = DEP_CON (dep);
6751 c = ia64_safe_itanium_class (next);
6752 if ((c == ITANIUM_CLASS_ST
6753 || c == ITANIUM_CLASS_STF)
6754 && ia64_st_address_bypass_p (insn, next))
6756 has_mem_op_consumer_p = true;
6757 break;
6759 else if ((c == ITANIUM_CLASS_LD
6760 || c == ITANIUM_CLASS_FLD
6761 || c == ITANIUM_CLASS_FLDP)
6762 && ia64_ld_address_bypass_p (insn, next))
6764 has_mem_op_consumer_p = true;
6765 break;
6769 insn->call = has_mem_op_consumer_p;
6773 /* We're beginning a new block. Initialize data structures as necessary. */
6775 static void
6776 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6777 int sched_verbose ATTRIBUTE_UNUSED,
6778 int max_ready ATTRIBUTE_UNUSED)
6780 #ifdef ENABLE_CHECKING
6781 rtx insn;
6783 if (!sel_sched_p () && reload_completed)
6784 for (insn = NEXT_INSN (current_sched_info->prev_head);
6785 insn != current_sched_info->next_tail;
6786 insn = NEXT_INSN (insn))
6787 gcc_assert (!SCHED_GROUP_P (insn));
6788 #endif
6789 last_scheduled_insn = NULL_RTX;
6790 init_insn_group_barriers ();
6792 current_cycle = 0;
6793 memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group));
6796 /* We're beginning a scheduling pass. Check assertion. */
6798 static void
6799 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
6800 int sched_verbose ATTRIBUTE_UNUSED,
6801 int max_ready ATTRIBUTE_UNUSED)
6803 gcc_assert (pending_data_specs == 0);
6806 /* Scheduling pass is now finished. Free/reset static variable. */
6807 static void
6808 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6809 int sched_verbose ATTRIBUTE_UNUSED)
6811 gcc_assert (pending_data_specs == 0);
6814 /* Return TRUE if INSN is a load (either normal or speculative, but not a
6815 speculation check), FALSE otherwise. */
6816 static bool
6817 is_load_p (rtx insn)
6819 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
6821 return
6822 ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD)
6823 && get_attr_check_load (insn) == CHECK_LOAD_NO);
6826 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
6827 (taking account for 3-cycle cache reference postponing for stores: Intel
6828 Itanium 2 Reference Manual for Software Development and Optimization,
6829 6.7.3.1). */
6830 static void
6831 record_memory_reference (rtx insn)
6833 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
6835 switch (insn_class) {
6836 case ITANIUM_CLASS_FLD:
6837 case ITANIUM_CLASS_LD:
6838 mem_ops_in_group[current_cycle % 4]++;
6839 break;
6840 case ITANIUM_CLASS_STF:
6841 case ITANIUM_CLASS_ST:
6842 mem_ops_in_group[(current_cycle + 3) % 4]++;
6843 break;
6844 default:;
6848 /* We are about to being issuing insns for this clock cycle.
6849 Override the default sort algorithm to better slot instructions. */
6851 static int
6852 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6853 int *pn_ready, int clock_var,
6854 int reorder_type)
6856 int n_asms;
6857 int n_ready = *pn_ready;
6858 rtx *e_ready = ready + n_ready;
6859 rtx *insnp;
6861 if (sched_verbose)
6862 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
6864 if (reorder_type == 0)
6866 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6867 n_asms = 0;
6868 for (insnp = ready; insnp < e_ready; insnp++)
6869 if (insnp < e_ready)
6871 rtx insn = *insnp;
6872 enum attr_type t = ia64_safe_type (insn);
6873 if (t == TYPE_UNKNOWN)
6875 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6876 || asm_noperands (PATTERN (insn)) >= 0)
6878 rtx lowest = ready[n_asms];
6879 ready[n_asms] = insn;
6880 *insnp = lowest;
6881 n_asms++;
6883 else
6885 rtx highest = ready[n_ready - 1];
6886 ready[n_ready - 1] = insn;
6887 *insnp = highest;
6888 return 1;
6893 if (n_asms < n_ready)
6895 /* Some normal insns to process. Skip the asms. */
6896 ready += n_asms;
6897 n_ready -= n_asms;
6899 else if (n_ready > 0)
6900 return 1;
6903 if (ia64_final_schedule)
6905 int deleted = 0;
6906 int nr_need_stop = 0;
6908 for (insnp = ready; insnp < e_ready; insnp++)
6909 if (safe_group_barrier_needed (*insnp))
6910 nr_need_stop++;
6912 if (reorder_type == 1 && n_ready == nr_need_stop)
6913 return 0;
6914 if (reorder_type == 0)
6915 return 1;
6916 insnp = e_ready;
6917 /* Move down everything that needs a stop bit, preserving
6918 relative order. */
6919 while (insnp-- > ready + deleted)
6920 while (insnp >= ready + deleted)
6922 rtx insn = *insnp;
6923 if (! safe_group_barrier_needed (insn))
6924 break;
6925 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6926 *ready = insn;
6927 deleted++;
6929 n_ready -= deleted;
6930 ready += deleted;
6933 current_cycle = clock_var;
6934 if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns)
6936 int moved = 0;
6938 insnp = e_ready;
6939 /* Move down loads/stores, preserving relative order. */
6940 while (insnp-- > ready + moved)
6941 while (insnp >= ready + moved)
6943 rtx insn = *insnp;
6944 if (! is_load_p (insn))
6945 break;
6946 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6947 *ready = insn;
6948 moved++;
6950 n_ready -= moved;
6951 ready += moved;
6954 return 1;
6957 /* We are about to being issuing insns for this clock cycle. Override
6958 the default sort algorithm to better slot instructions. */
6960 static int
6961 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
6962 int clock_var)
6964 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
6965 pn_ready, clock_var, 0);
6968 /* Like ia64_sched_reorder, but called after issuing each insn.
6969 Override the default sort algorithm to better slot instructions. */
6971 static int
6972 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
6973 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
6974 int *pn_ready, int clock_var)
6976 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
6977 clock_var, 1);
6980 /* We are about to issue INSN. Return the number of insns left on the
6981 ready queue that can be issued this cycle. */
6983 static int
6984 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
6985 int sched_verbose ATTRIBUTE_UNUSED,
6986 rtx insn ATTRIBUTE_UNUSED,
6987 int can_issue_more ATTRIBUTE_UNUSED)
6989 if (sched_deps_info->generate_spec_deps && !sel_sched_p ())
6990 /* Modulo scheduling does not extend h_i_d when emitting
6991 new instructions. Don't use h_i_d, if we don't have to. */
6993 if (DONE_SPEC (insn) & BEGIN_DATA)
6994 pending_data_specs++;
6995 if (CHECK_SPEC (insn) & BEGIN_DATA)
6996 pending_data_specs--;
6999 if (DEBUG_INSN_P (insn))
7000 return 1;
7002 last_scheduled_insn = insn;
7003 memcpy (prev_cycle_state, curr_state, dfa_state_size);
7004 if (reload_completed)
7006 int needed = group_barrier_needed (insn);
7008 gcc_assert (!needed);
7009 if (GET_CODE (insn) == CALL_INSN)
7010 init_insn_group_barriers ();
7011 stops_p [INSN_UID (insn)] = stop_before_p;
7012 stop_before_p = 0;
7014 record_memory_reference (insn);
7016 return 1;
7019 /* We are choosing insn from the ready queue. Return nonzero if INSN
7020 can be chosen. */
7022 static int
7023 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
7025 gcc_assert (insn && INSN_P (insn));
7026 return ((!reload_completed
7027 || !safe_group_barrier_needed (insn))
7028 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn)
7029 && (!mflag_sched_mem_insns_hard_limit
7030 || !is_load_p (insn)
7031 || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns));
7034 /* We are choosing insn from the ready queue. Return nonzero if INSN
7035 can be chosen. */
7037 static bool
7038 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn)
7040 gcc_assert (insn && INSN_P (insn));
7041 /* Size of ALAT is 32. As far as we perform conservative data speculation,
7042 we keep ALAT half-empty. */
7043 return (pending_data_specs < 16
7044 || !(TODO_SPEC (insn) & BEGIN_DATA));
7047 /* The following variable value is pseudo-insn used by the DFA insn
7048 scheduler to change the DFA state when the simulated clock is
7049 increased. */
7051 static rtx dfa_pre_cycle_insn;
7053 /* Returns 1 when a meaningful insn was scheduled between the last group
7054 barrier and LAST. */
7055 static int
7056 scheduled_good_insn (rtx last)
7058 if (last && recog_memoized (last) >= 0)
7059 return 1;
7061 for ( ;
7062 last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last)
7063 && !stops_p[INSN_UID (last)];
7064 last = PREV_INSN (last))
7065 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7066 the ebb we're scheduling. */
7067 if (INSN_P (last) && recog_memoized (last) >= 0)
7068 return 1;
7070 return 0;
7073 /* We are about to being issuing INSN. Return nonzero if we cannot
7074 issue it on given cycle CLOCK and return zero if we should not sort
7075 the ready queue on the next clock start. */
7077 static int
7078 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
7079 int clock, int *sort_p)
7081 gcc_assert (insn && INSN_P (insn));
7083 if (DEBUG_INSN_P (insn))
7084 return 0;
7086 /* When a group barrier is needed for insn, last_scheduled_insn
7087 should be set. */
7088 gcc_assert (!(reload_completed && safe_group_barrier_needed (insn))
7089 || last_scheduled_insn);
7091 if ((reload_completed
7092 && (safe_group_barrier_needed (insn)
7093 || (mflag_sched_stop_bits_after_every_cycle
7094 && last_clock != clock
7095 && last_scheduled_insn
7096 && scheduled_good_insn (last_scheduled_insn))))
7097 || (last_scheduled_insn
7098 && (GET_CODE (last_scheduled_insn) == CALL_INSN
7099 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
7100 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
7102 init_insn_group_barriers ();
7104 if (verbose && dump)
7105 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
7106 last_clock == clock ? " + cycle advance" : "");
7108 stop_before_p = 1;
7109 current_cycle = clock;
7110 mem_ops_in_group[current_cycle % 4] = 0;
7112 if (last_clock == clock)
7114 state_transition (curr_state, dfa_stop_insn);
7115 if (TARGET_EARLY_STOP_BITS)
7116 *sort_p = (last_scheduled_insn == NULL_RTX
7117 || GET_CODE (last_scheduled_insn) != CALL_INSN);
7118 else
7119 *sort_p = 0;
7120 return 1;
7123 if (last_scheduled_insn)
7125 if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
7126 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)
7127 state_reset (curr_state);
7128 else
7130 memcpy (curr_state, prev_cycle_state, dfa_state_size);
7131 state_transition (curr_state, dfa_stop_insn);
7132 state_transition (curr_state, dfa_pre_cycle_insn);
7133 state_transition (curr_state, NULL);
7137 return 0;
7140 /* Implement targetm.sched.h_i_d_extended hook.
7141 Extend internal data structures. */
7142 static void
7143 ia64_h_i_d_extended (void)
7145 if (stops_p != NULL)
7147 int new_clocks_length = get_max_uid () * 3 / 2;
7148 stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
7149 clocks_length = new_clocks_length;
7154 /* This structure describes the data used by the backend to guide scheduling.
7155 When the current scheduling point is switched, this data should be saved
7156 and restored later, if the scheduler returns to this point. */
7157 struct _ia64_sched_context
7159 state_t prev_cycle_state;
7160 rtx last_scheduled_insn;
7161 struct reg_write_state rws_sum[NUM_REGS];
7162 struct reg_write_state rws_insn[NUM_REGS];
7163 int first_instruction;
7164 int pending_data_specs;
7165 int current_cycle;
7166 char mem_ops_in_group[4];
7168 typedef struct _ia64_sched_context *ia64_sched_context_t;
7170 /* Allocates a scheduling context. */
7171 static void *
7172 ia64_alloc_sched_context (void)
7174 return xmalloc (sizeof (struct _ia64_sched_context));
7177 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7178 the global context otherwise. */
7179 static void
7180 ia64_init_sched_context (void *_sc, bool clean_p)
7182 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7184 sc->prev_cycle_state = xmalloc (dfa_state_size);
7185 if (clean_p)
7187 state_reset (sc->prev_cycle_state);
7188 sc->last_scheduled_insn = NULL_RTX;
7189 memset (sc->rws_sum, 0, sizeof (rws_sum));
7190 memset (sc->rws_insn, 0, sizeof (rws_insn));
7191 sc->first_instruction = 1;
7192 sc->pending_data_specs = 0;
7193 sc->current_cycle = 0;
7194 memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7196 else
7198 memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size);
7199 sc->last_scheduled_insn = last_scheduled_insn;
7200 memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum));
7201 memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn));
7202 sc->first_instruction = first_instruction;
7203 sc->pending_data_specs = pending_data_specs;
7204 sc->current_cycle = current_cycle;
7205 memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group));
7209 /* Sets the global scheduling context to the one pointed to by _SC. */
7210 static void
7211 ia64_set_sched_context (void *_sc)
7213 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7215 gcc_assert (sc != NULL);
7217 memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size);
7218 last_scheduled_insn = sc->last_scheduled_insn;
7219 memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum));
7220 memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn));
7221 first_instruction = sc->first_instruction;
7222 pending_data_specs = sc->pending_data_specs;
7223 current_cycle = sc->current_cycle;
7224 memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group));
7227 /* Clears the data in the _SC scheduling context. */
7228 static void
7229 ia64_clear_sched_context (void *_sc)
7231 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7233 free (sc->prev_cycle_state);
7234 sc->prev_cycle_state = NULL;
7237 /* Frees the _SC scheduling context. */
7238 static void
7239 ia64_free_sched_context (void *_sc)
7241 gcc_assert (_sc != NULL);
7243 free (_sc);
7246 typedef rtx (* gen_func_t) (rtx, rtx);
7248 /* Return a function that will generate a load of mode MODE_NO
7249 with speculation types TS. */
7250 static gen_func_t
7251 get_spec_load_gen_function (ds_t ts, int mode_no)
7253 static gen_func_t gen_ld_[] = {
7254 gen_movbi,
7255 gen_movqi_internal,
7256 gen_movhi_internal,
7257 gen_movsi_internal,
7258 gen_movdi_internal,
7259 gen_movsf_internal,
7260 gen_movdf_internal,
7261 gen_movxf_internal,
7262 gen_movti_internal,
7263 gen_zero_extendqidi2,
7264 gen_zero_extendhidi2,
7265 gen_zero_extendsidi2,
7268 static gen_func_t gen_ld_a[] = {
7269 gen_movbi_advanced,
7270 gen_movqi_advanced,
7271 gen_movhi_advanced,
7272 gen_movsi_advanced,
7273 gen_movdi_advanced,
7274 gen_movsf_advanced,
7275 gen_movdf_advanced,
7276 gen_movxf_advanced,
7277 gen_movti_advanced,
7278 gen_zero_extendqidi2_advanced,
7279 gen_zero_extendhidi2_advanced,
7280 gen_zero_extendsidi2_advanced,
7282 static gen_func_t gen_ld_s[] = {
7283 gen_movbi_speculative,
7284 gen_movqi_speculative,
7285 gen_movhi_speculative,
7286 gen_movsi_speculative,
7287 gen_movdi_speculative,
7288 gen_movsf_speculative,
7289 gen_movdf_speculative,
7290 gen_movxf_speculative,
7291 gen_movti_speculative,
7292 gen_zero_extendqidi2_speculative,
7293 gen_zero_extendhidi2_speculative,
7294 gen_zero_extendsidi2_speculative,
7296 static gen_func_t gen_ld_sa[] = {
7297 gen_movbi_speculative_advanced,
7298 gen_movqi_speculative_advanced,
7299 gen_movhi_speculative_advanced,
7300 gen_movsi_speculative_advanced,
7301 gen_movdi_speculative_advanced,
7302 gen_movsf_speculative_advanced,
7303 gen_movdf_speculative_advanced,
7304 gen_movxf_speculative_advanced,
7305 gen_movti_speculative_advanced,
7306 gen_zero_extendqidi2_speculative_advanced,
7307 gen_zero_extendhidi2_speculative_advanced,
7308 gen_zero_extendsidi2_speculative_advanced,
7310 static gen_func_t gen_ld_s_a[] = {
7311 gen_movbi_speculative_a,
7312 gen_movqi_speculative_a,
7313 gen_movhi_speculative_a,
7314 gen_movsi_speculative_a,
7315 gen_movdi_speculative_a,
7316 gen_movsf_speculative_a,
7317 gen_movdf_speculative_a,
7318 gen_movxf_speculative_a,
7319 gen_movti_speculative_a,
7320 gen_zero_extendqidi2_speculative_a,
7321 gen_zero_extendhidi2_speculative_a,
7322 gen_zero_extendsidi2_speculative_a,
7325 gen_func_t *gen_ld;
7327 if (ts & BEGIN_DATA)
7329 if (ts & BEGIN_CONTROL)
7330 gen_ld = gen_ld_sa;
7331 else
7332 gen_ld = gen_ld_a;
7334 else if (ts & BEGIN_CONTROL)
7336 if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL)
7337 || ia64_needs_block_p (ts))
7338 gen_ld = gen_ld_s;
7339 else
7340 gen_ld = gen_ld_s_a;
7342 else if (ts == 0)
7343 gen_ld = gen_ld_;
7344 else
7345 gcc_unreachable ();
7347 return gen_ld[mode_no];
7350 /* Constants that help mapping 'enum machine_mode' to int. */
7351 enum SPEC_MODES
7353 SPEC_MODE_INVALID = -1,
7354 SPEC_MODE_FIRST = 0,
7355 SPEC_MODE_FOR_EXTEND_FIRST = 1,
7356 SPEC_MODE_FOR_EXTEND_LAST = 3,
7357 SPEC_MODE_LAST = 8
7360 enum
7362 /* Offset to reach ZERO_EXTEND patterns. */
7363 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1
7366 /* Return index of the MODE. */
7367 static int
7368 ia64_mode_to_int (enum machine_mode mode)
7370 switch (mode)
7372 case BImode: return 0; /* SPEC_MODE_FIRST */
7373 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7374 case HImode: return 2;
7375 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7376 case DImode: return 4;
7377 case SFmode: return 5;
7378 case DFmode: return 6;
7379 case XFmode: return 7;
7380 case TImode:
7381 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7382 mentioned in itanium[12].md. Predicate fp_register_operand also
7383 needs to be defined. Bottom line: better disable for now. */
7384 return SPEC_MODE_INVALID;
7385 default: return SPEC_MODE_INVALID;
7389 /* Provide information about speculation capabilities. */
7390 static void
7391 ia64_set_sched_flags (spec_info_t spec_info)
7393 unsigned int *flags = &(current_sched_info->flags);
7395 if (*flags & SCHED_RGN
7396 || *flags & SCHED_EBB
7397 || *flags & SEL_SCHED)
7399 int mask = 0;
7401 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
7402 || (mflag_sched_ar_data_spec && reload_completed))
7404 mask |= BEGIN_DATA;
7406 if (!sel_sched_p ()
7407 && ((mflag_sched_br_in_data_spec && !reload_completed)
7408 || (mflag_sched_ar_in_data_spec && reload_completed)))
7409 mask |= BE_IN_DATA;
7412 if (mflag_sched_control_spec
7413 && (!sel_sched_p ()
7414 || reload_completed))
7416 mask |= BEGIN_CONTROL;
7418 if (!sel_sched_p () && mflag_sched_in_control_spec)
7419 mask |= BE_IN_CONTROL;
7422 spec_info->mask = mask;
7424 if (mask)
7426 *flags |= USE_DEPS_LIST | DO_SPECULATION;
7428 if (mask & BE_IN_SPEC)
7429 *flags |= NEW_BBS;
7431 spec_info->flags = 0;
7433 if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns)
7434 spec_info->flags |= PREFER_NON_DATA_SPEC;
7436 if (mask & CONTROL_SPEC)
7438 if (mflag_sched_prefer_non_control_spec_insns)
7439 spec_info->flags |= PREFER_NON_CONTROL_SPEC;
7441 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec)
7442 spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL;
7445 if (sched_verbose >= 1)
7446 spec_info->dump = sched_dump;
7447 else
7448 spec_info->dump = 0;
7450 if (mflag_sched_count_spec_in_critical_path)
7451 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
7454 else
7455 spec_info->mask = 0;
7458 /* If INSN is an appropriate load return its mode.
7459 Return -1 otherwise. */
7460 static int
7461 get_mode_no_for_insn (rtx insn)
7463 rtx reg, mem, mode_rtx;
7464 int mode_no;
7465 bool extend_p;
7467 extract_insn_cached (insn);
7469 /* We use WHICH_ALTERNATIVE only after reload. This will
7470 guarantee that reload won't touch a speculative insn. */
7472 if (recog_data.n_operands != 2)
7473 return -1;
7475 reg = recog_data.operand[0];
7476 mem = recog_data.operand[1];
7478 /* We should use MEM's mode since REG's mode in presence of
7479 ZERO_EXTEND will always be DImode. */
7480 if (get_attr_speculable1 (insn) == SPECULABLE1_YES)
7481 /* Process non-speculative ld. */
7483 if (!reload_completed)
7485 /* Do not speculate into regs like ar.lc. */
7486 if (!REG_P (reg) || AR_REGNO_P (REGNO (reg)))
7487 return -1;
7489 if (!MEM_P (mem))
7490 return -1;
7493 rtx mem_reg = XEXP (mem, 0);
7495 if (!REG_P (mem_reg))
7496 return -1;
7499 mode_rtx = mem;
7501 else if (get_attr_speculable2 (insn) == SPECULABLE2_YES)
7503 gcc_assert (REG_P (reg) && MEM_P (mem));
7504 mode_rtx = mem;
7506 else
7507 return -1;
7509 else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES
7510 || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES
7511 || get_attr_check_load (insn) == CHECK_LOAD_YES)
7512 /* Process speculative ld or ld.c. */
7514 gcc_assert (REG_P (reg) && MEM_P (mem));
7515 mode_rtx = mem;
7517 else
7519 enum attr_itanium_class attr_class = get_attr_itanium_class (insn);
7521 if (attr_class == ITANIUM_CLASS_CHK_A
7522 || attr_class == ITANIUM_CLASS_CHK_S_I
7523 || attr_class == ITANIUM_CLASS_CHK_S_F)
7524 /* Process chk. */
7525 mode_rtx = reg;
7526 else
7527 return -1;
7530 mode_no = ia64_mode_to_int (GET_MODE (mode_rtx));
7532 if (mode_no == SPEC_MODE_INVALID)
7533 return -1;
7535 extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx));
7537 if (extend_p)
7539 if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
7540 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST))
7541 return -1;
7543 mode_no += SPEC_GEN_EXTEND_OFFSET;
7546 return mode_no;
7549 /* If X is an unspec part of a speculative load, return its code.
7550 Return -1 otherwise. */
7551 static int
7552 get_spec_unspec_code (const_rtx x)
7554 if (GET_CODE (x) != UNSPEC)
7555 return -1;
7558 int code;
7560 code = XINT (x, 1);
7562 switch (code)
7564 case UNSPEC_LDA:
7565 case UNSPEC_LDS:
7566 case UNSPEC_LDS_A:
7567 case UNSPEC_LDSA:
7568 return code;
7570 default:
7571 return -1;
7576 /* Implement skip_rtx_p hook. */
7577 static bool
7578 ia64_skip_rtx_p (const_rtx x)
7580 return get_spec_unspec_code (x) != -1;
7583 /* If INSN is a speculative load, return its UNSPEC code.
7584 Return -1 otherwise. */
7585 static int
7586 get_insn_spec_code (const_rtx insn)
7588 rtx pat, reg, mem;
7590 pat = PATTERN (insn);
7592 if (GET_CODE (pat) == COND_EXEC)
7593 pat = COND_EXEC_CODE (pat);
7595 if (GET_CODE (pat) != SET)
7596 return -1;
7598 reg = SET_DEST (pat);
7599 if (!REG_P (reg))
7600 return -1;
7602 mem = SET_SRC (pat);
7603 if (GET_CODE (mem) == ZERO_EXTEND)
7604 mem = XEXP (mem, 0);
7606 return get_spec_unspec_code (mem);
7609 /* If INSN is a speculative load, return a ds with the speculation types.
7610 Otherwise [if INSN is a normal instruction] return 0. */
7611 static ds_t
7612 ia64_get_insn_spec_ds (rtx insn)
7614 int code = get_insn_spec_code (insn);
7616 switch (code)
7618 case UNSPEC_LDA:
7619 return BEGIN_DATA;
7621 case UNSPEC_LDS:
7622 case UNSPEC_LDS_A:
7623 return BEGIN_CONTROL;
7625 case UNSPEC_LDSA:
7626 return BEGIN_DATA | BEGIN_CONTROL;
7628 default:
7629 return 0;
7633 /* If INSN is a speculative load return a ds with the speculation types that
7634 will be checked.
7635 Otherwise [if INSN is a normal instruction] return 0. */
7636 static ds_t
7637 ia64_get_insn_checked_ds (rtx insn)
7639 int code = get_insn_spec_code (insn);
7641 switch (code)
7643 case UNSPEC_LDA:
7644 return BEGIN_DATA | BEGIN_CONTROL;
7646 case UNSPEC_LDS:
7647 return BEGIN_CONTROL;
7649 case UNSPEC_LDS_A:
7650 case UNSPEC_LDSA:
7651 return BEGIN_DATA | BEGIN_CONTROL;
7653 default:
7654 return 0;
7658 /* If GEN_P is true, calculate the index of needed speculation check and return
7659 speculative pattern for INSN with speculative mode TS, machine mode
7660 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
7661 If GEN_P is false, just calculate the index of needed speculation check. */
7662 static rtx
7663 ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no)
7665 rtx pat, new_pat;
7666 gen_func_t gen_load;
7668 gen_load = get_spec_load_gen_function (ts, mode_no);
7670 new_pat = gen_load (copy_rtx (recog_data.operand[0]),
7671 copy_rtx (recog_data.operand[1]));
7673 pat = PATTERN (insn);
7674 if (GET_CODE (pat) == COND_EXEC)
7675 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
7676 new_pat);
7678 return new_pat;
7681 static bool
7682 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED,
7683 ds_t ds ATTRIBUTE_UNUSED)
7685 return false;
7688 /* Implement targetm.sched.speculate_insn hook.
7689 Check if the INSN can be TS speculative.
7690 If 'no' - return -1.
7691 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
7692 If current pattern of the INSN already provides TS speculation,
7693 return 0. */
7694 static int
7695 ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat)
7697 int mode_no;
7698 int res;
7700 gcc_assert (!(ts & ~SPECULATIVE));
7702 if (ia64_spec_check_p (insn))
7703 return -1;
7705 if ((ts & BE_IN_SPEC)
7706 && !insn_can_be_in_speculative_p (insn, ts))
7707 return -1;
7709 mode_no = get_mode_no_for_insn (insn);
7711 if (mode_no != SPEC_MODE_INVALID)
7713 if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts))
7714 res = 0;
7715 else
7717 res = 1;
7718 *new_pat = ia64_gen_spec_load (insn, ts, mode_no);
7721 else
7722 res = -1;
7724 return res;
7727 /* Return a function that will generate a check for speculation TS with mode
7728 MODE_NO.
7729 If simple check is needed, pass true for SIMPLE_CHECK_P.
7730 If clearing check is needed, pass true for CLEARING_CHECK_P. */
7731 static gen_func_t
7732 get_spec_check_gen_function (ds_t ts, int mode_no,
7733 bool simple_check_p, bool clearing_check_p)
7735 static gen_func_t gen_ld_c_clr[] = {
7736 gen_movbi_clr,
7737 gen_movqi_clr,
7738 gen_movhi_clr,
7739 gen_movsi_clr,
7740 gen_movdi_clr,
7741 gen_movsf_clr,
7742 gen_movdf_clr,
7743 gen_movxf_clr,
7744 gen_movti_clr,
7745 gen_zero_extendqidi2_clr,
7746 gen_zero_extendhidi2_clr,
7747 gen_zero_extendsidi2_clr,
7749 static gen_func_t gen_ld_c_nc[] = {
7750 gen_movbi_nc,
7751 gen_movqi_nc,
7752 gen_movhi_nc,
7753 gen_movsi_nc,
7754 gen_movdi_nc,
7755 gen_movsf_nc,
7756 gen_movdf_nc,
7757 gen_movxf_nc,
7758 gen_movti_nc,
7759 gen_zero_extendqidi2_nc,
7760 gen_zero_extendhidi2_nc,
7761 gen_zero_extendsidi2_nc,
7763 static gen_func_t gen_chk_a_clr[] = {
7764 gen_advanced_load_check_clr_bi,
7765 gen_advanced_load_check_clr_qi,
7766 gen_advanced_load_check_clr_hi,
7767 gen_advanced_load_check_clr_si,
7768 gen_advanced_load_check_clr_di,
7769 gen_advanced_load_check_clr_sf,
7770 gen_advanced_load_check_clr_df,
7771 gen_advanced_load_check_clr_xf,
7772 gen_advanced_load_check_clr_ti,
7773 gen_advanced_load_check_clr_di,
7774 gen_advanced_load_check_clr_di,
7775 gen_advanced_load_check_clr_di,
7777 static gen_func_t gen_chk_a_nc[] = {
7778 gen_advanced_load_check_nc_bi,
7779 gen_advanced_load_check_nc_qi,
7780 gen_advanced_load_check_nc_hi,
7781 gen_advanced_load_check_nc_si,
7782 gen_advanced_load_check_nc_di,
7783 gen_advanced_load_check_nc_sf,
7784 gen_advanced_load_check_nc_df,
7785 gen_advanced_load_check_nc_xf,
7786 gen_advanced_load_check_nc_ti,
7787 gen_advanced_load_check_nc_di,
7788 gen_advanced_load_check_nc_di,
7789 gen_advanced_load_check_nc_di,
7791 static gen_func_t gen_chk_s[] = {
7792 gen_speculation_check_bi,
7793 gen_speculation_check_qi,
7794 gen_speculation_check_hi,
7795 gen_speculation_check_si,
7796 gen_speculation_check_di,
7797 gen_speculation_check_sf,
7798 gen_speculation_check_df,
7799 gen_speculation_check_xf,
7800 gen_speculation_check_ti,
7801 gen_speculation_check_di,
7802 gen_speculation_check_di,
7803 gen_speculation_check_di,
7806 gen_func_t *gen_check;
7808 if (ts & BEGIN_DATA)
7810 /* We don't need recovery because even if this is ld.sa
7811 ALAT entry will be allocated only if NAT bit is set to zero.
7812 So it is enough to use ld.c here. */
7814 if (simple_check_p)
7816 gcc_assert (mflag_sched_spec_ldc);
7818 if (clearing_check_p)
7819 gen_check = gen_ld_c_clr;
7820 else
7821 gen_check = gen_ld_c_nc;
7823 else
7825 if (clearing_check_p)
7826 gen_check = gen_chk_a_clr;
7827 else
7828 gen_check = gen_chk_a_nc;
7831 else if (ts & BEGIN_CONTROL)
7833 if (simple_check_p)
7834 /* We might want to use ld.sa -> ld.c instead of
7835 ld.s -> chk.s. */
7837 gcc_assert (!ia64_needs_block_p (ts));
7839 if (clearing_check_p)
7840 gen_check = gen_ld_c_clr;
7841 else
7842 gen_check = gen_ld_c_nc;
7844 else
7846 gen_check = gen_chk_s;
7849 else
7850 gcc_unreachable ();
7852 gcc_assert (mode_no >= 0);
7853 return gen_check[mode_no];
7856 /* Return nonzero, if INSN needs branchy recovery check. */
7857 static bool
7858 ia64_needs_block_p (ds_t ts)
7860 if (ts & BEGIN_DATA)
7861 return !mflag_sched_spec_ldc;
7863 gcc_assert ((ts & BEGIN_CONTROL) != 0);
7865 return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc);
7868 /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN.
7869 If (LABEL != 0 || MUTATE_P), generate branchy recovery check.
7870 Otherwise, generate a simple check. */
7871 static rtx
7872 ia64_gen_spec_check (rtx insn, rtx label, ds_t ds)
7874 rtx op1, pat, check_pat;
7875 gen_func_t gen_check;
7876 int mode_no;
7878 mode_no = get_mode_no_for_insn (insn);
7879 gcc_assert (mode_no >= 0);
7881 if (label)
7882 op1 = label;
7883 else
7885 gcc_assert (!ia64_needs_block_p (ds));
7886 op1 = copy_rtx (recog_data.operand[1]);
7889 gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX,
7890 true);
7892 check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1);
7894 pat = PATTERN (insn);
7895 if (GET_CODE (pat) == COND_EXEC)
7896 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
7897 check_pat);
7899 return check_pat;
7902 /* Return nonzero, if X is branchy recovery check. */
7903 static int
7904 ia64_spec_check_p (rtx x)
7906 x = PATTERN (x);
7907 if (GET_CODE (x) == COND_EXEC)
7908 x = COND_EXEC_CODE (x);
7909 if (GET_CODE (x) == SET)
7910 return ia64_spec_check_src_p (SET_SRC (x));
7911 return 0;
7914 /* Return nonzero, if SRC belongs to recovery check. */
7915 static int
7916 ia64_spec_check_src_p (rtx src)
7918 if (GET_CODE (src) == IF_THEN_ELSE)
7920 rtx t;
7922 t = XEXP (src, 0);
7923 if (GET_CODE (t) == NE)
7925 t = XEXP (t, 0);
7927 if (GET_CODE (t) == UNSPEC)
7929 int code;
7931 code = XINT (t, 1);
7933 if (code == UNSPEC_LDCCLR
7934 || code == UNSPEC_LDCNC
7935 || code == UNSPEC_CHKACLR
7936 || code == UNSPEC_CHKANC
7937 || code == UNSPEC_CHKS)
7939 gcc_assert (code != 0);
7940 return code;
7945 return 0;
7949 /* The following page contains abstract data `bundle states' which are
7950 used for bundling insns (inserting nops and template generation). */
7952 /* The following describes state of insn bundling. */
7954 struct bundle_state
7956 /* Unique bundle state number to identify them in the debugging
7957 output */
7958 int unique_num;
7959 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
7960 /* number nops before and after the insn */
7961 short before_nops_num, after_nops_num;
7962 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
7963 insn */
7964 int cost; /* cost of the state in cycles */
7965 int accumulated_insns_num; /* number of all previous insns including
7966 nops. L is considered as 2 insns */
7967 int branch_deviation; /* deviation of previous branches from 3rd slots */
7968 int middle_bundle_stops; /* number of stop bits in the middle of bundles */
7969 struct bundle_state *next; /* next state with the same insn_num */
7970 struct bundle_state *originator; /* originator (previous insn state) */
7971 /* All bundle states are in the following chain. */
7972 struct bundle_state *allocated_states_chain;
7973 /* The DFA State after issuing the insn and the nops. */
7974 state_t dfa_state;
7977 /* The following is map insn number to the corresponding bundle state. */
7979 static struct bundle_state **index_to_bundle_states;
7981 /* The unique number of next bundle state. */
7983 static int bundle_states_num;
7985 /* All allocated bundle states are in the following chain. */
7987 static struct bundle_state *allocated_bundle_states_chain;
7989 /* All allocated but not used bundle states are in the following
7990 chain. */
7992 static struct bundle_state *free_bundle_state_chain;
7995 /* The following function returns a free bundle state. */
7997 static struct bundle_state *
7998 get_free_bundle_state (void)
8000 struct bundle_state *result;
8002 if (free_bundle_state_chain != NULL)
8004 result = free_bundle_state_chain;
8005 free_bundle_state_chain = result->next;
8007 else
8009 result = XNEW (struct bundle_state);
8010 result->dfa_state = xmalloc (dfa_state_size);
8011 result->allocated_states_chain = allocated_bundle_states_chain;
8012 allocated_bundle_states_chain = result;
8014 result->unique_num = bundle_states_num++;
8015 return result;
8019 /* The following function frees given bundle state. */
8021 static void
8022 free_bundle_state (struct bundle_state *state)
8024 state->next = free_bundle_state_chain;
8025 free_bundle_state_chain = state;
8028 /* Start work with abstract data `bundle states'. */
8030 static void
8031 initiate_bundle_states (void)
8033 bundle_states_num = 0;
8034 free_bundle_state_chain = NULL;
8035 allocated_bundle_states_chain = NULL;
8038 /* Finish work with abstract data `bundle states'. */
8040 static void
8041 finish_bundle_states (void)
8043 struct bundle_state *curr_state, *next_state;
8045 for (curr_state = allocated_bundle_states_chain;
8046 curr_state != NULL;
8047 curr_state = next_state)
8049 next_state = curr_state->allocated_states_chain;
8050 free (curr_state->dfa_state);
8051 free (curr_state);
8055 /* Hash table of the bundle states. The key is dfa_state and insn_num
8056 of the bundle states. */
8058 static htab_t bundle_state_table;
8060 /* The function returns hash of BUNDLE_STATE. */
8062 static unsigned
8063 bundle_state_hash (const void *bundle_state)
8065 const struct bundle_state *const state
8066 = (const struct bundle_state *) bundle_state;
8067 unsigned result, i;
8069 for (result = i = 0; i < dfa_state_size; i++)
8070 result += (((unsigned char *) state->dfa_state) [i]
8071 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
8072 return result + state->insn_num;
8075 /* The function returns nonzero if the bundle state keys are equal. */
8077 static int
8078 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
8080 const struct bundle_state *const state1
8081 = (const struct bundle_state *) bundle_state_1;
8082 const struct bundle_state *const state2
8083 = (const struct bundle_state *) bundle_state_2;
8085 return (state1->insn_num == state2->insn_num
8086 && memcmp (state1->dfa_state, state2->dfa_state,
8087 dfa_state_size) == 0);
8090 /* The function inserts the BUNDLE_STATE into the hash table. The
8091 function returns nonzero if the bundle has been inserted into the
8092 table. The table contains the best bundle state with given key. */
8094 static int
8095 insert_bundle_state (struct bundle_state *bundle_state)
8097 void **entry_ptr;
8099 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, INSERT);
8100 if (*entry_ptr == NULL)
8102 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
8103 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
8104 *entry_ptr = (void *) bundle_state;
8105 return TRUE;
8107 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
8108 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
8109 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
8110 > bundle_state->accumulated_insns_num
8111 || (((struct bundle_state *)
8112 *entry_ptr)->accumulated_insns_num
8113 == bundle_state->accumulated_insns_num
8114 && (((struct bundle_state *)
8115 *entry_ptr)->branch_deviation
8116 > bundle_state->branch_deviation
8117 || (((struct bundle_state *)
8118 *entry_ptr)->branch_deviation
8119 == bundle_state->branch_deviation
8120 && ((struct bundle_state *)
8121 *entry_ptr)->middle_bundle_stops
8122 > bundle_state->middle_bundle_stops))))))
8125 struct bundle_state temp;
8127 temp = *(struct bundle_state *) *entry_ptr;
8128 *(struct bundle_state *) *entry_ptr = *bundle_state;
8129 ((struct bundle_state *) *entry_ptr)->next = temp.next;
8130 *bundle_state = temp;
8132 return FALSE;
8135 /* Start work with the hash table. */
8137 static void
8138 initiate_bundle_state_table (void)
8140 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
8141 (htab_del) 0);
8144 /* Finish work with the hash table. */
8146 static void
8147 finish_bundle_state_table (void)
8149 htab_delete (bundle_state_table);
8154 /* The following variable is a insn `nop' used to check bundle states
8155 with different number of inserted nops. */
8157 static rtx ia64_nop;
8159 /* The following function tries to issue NOPS_NUM nops for the current
8160 state without advancing processor cycle. If it failed, the
8161 function returns FALSE and frees the current state. */
8163 static int
8164 try_issue_nops (struct bundle_state *curr_state, int nops_num)
8166 int i;
8168 for (i = 0; i < nops_num; i++)
8169 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
8171 free_bundle_state (curr_state);
8172 return FALSE;
8174 return TRUE;
8177 /* The following function tries to issue INSN for the current
8178 state without advancing processor cycle. If it failed, the
8179 function returns FALSE and frees the current state. */
8181 static int
8182 try_issue_insn (struct bundle_state *curr_state, rtx insn)
8184 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
8186 free_bundle_state (curr_state);
8187 return FALSE;
8189 return TRUE;
8192 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8193 starting with ORIGINATOR without advancing processor cycle. If
8194 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8195 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8196 If it was successful, the function creates new bundle state and
8197 insert into the hash table and into `index_to_bundle_states'. */
8199 static void
8200 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
8201 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
8203 struct bundle_state *curr_state;
8205 curr_state = get_free_bundle_state ();
8206 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
8207 curr_state->insn = insn;
8208 curr_state->insn_num = originator->insn_num + 1;
8209 curr_state->cost = originator->cost;
8210 curr_state->originator = originator;
8211 curr_state->before_nops_num = before_nops_num;
8212 curr_state->after_nops_num = 0;
8213 curr_state->accumulated_insns_num
8214 = originator->accumulated_insns_num + before_nops_num;
8215 curr_state->branch_deviation = originator->branch_deviation;
8216 curr_state->middle_bundle_stops = originator->middle_bundle_stops;
8217 gcc_assert (insn);
8218 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
8220 gcc_assert (GET_MODE (insn) != TImode);
8221 if (!try_issue_nops (curr_state, before_nops_num))
8222 return;
8223 if (!try_issue_insn (curr_state, insn))
8224 return;
8225 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
8226 if (curr_state->accumulated_insns_num % 3 != 0)
8227 curr_state->middle_bundle_stops++;
8228 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
8229 && curr_state->accumulated_insns_num % 3 != 0)
8231 free_bundle_state (curr_state);
8232 return;
8235 else if (GET_MODE (insn) != TImode)
8237 if (!try_issue_nops (curr_state, before_nops_num))
8238 return;
8239 if (!try_issue_insn (curr_state, insn))
8240 return;
8241 curr_state->accumulated_insns_num++;
8242 gcc_assert (GET_CODE (PATTERN (insn)) != ASM_INPUT
8243 && asm_noperands (PATTERN (insn)) < 0);
8245 if (ia64_safe_type (insn) == TYPE_L)
8246 curr_state->accumulated_insns_num++;
8248 else
8250 /* If this is an insn that must be first in a group, then don't allow
8251 nops to be emitted before it. Currently, alloc is the only such
8252 supported instruction. */
8253 /* ??? The bundling automatons should handle this for us, but they do
8254 not yet have support for the first_insn attribute. */
8255 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
8257 free_bundle_state (curr_state);
8258 return;
8261 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
8262 state_transition (curr_state->dfa_state, NULL);
8263 curr_state->cost++;
8264 if (!try_issue_nops (curr_state, before_nops_num))
8265 return;
8266 if (!try_issue_insn (curr_state, insn))
8267 return;
8268 curr_state->accumulated_insns_num++;
8269 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
8270 || asm_noperands (PATTERN (insn)) >= 0)
8272 /* Finish bundle containing asm insn. */
8273 curr_state->after_nops_num
8274 = 3 - curr_state->accumulated_insns_num % 3;
8275 curr_state->accumulated_insns_num
8276 += 3 - curr_state->accumulated_insns_num % 3;
8278 else if (ia64_safe_type (insn) == TYPE_L)
8279 curr_state->accumulated_insns_num++;
8281 if (ia64_safe_type (insn) == TYPE_B)
8282 curr_state->branch_deviation
8283 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
8284 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
8286 if (!only_bundle_end_p && insert_bundle_state (curr_state))
8288 state_t dfa_state;
8289 struct bundle_state *curr_state1;
8290 struct bundle_state *allocated_states_chain;
8292 curr_state1 = get_free_bundle_state ();
8293 dfa_state = curr_state1->dfa_state;
8294 allocated_states_chain = curr_state1->allocated_states_chain;
8295 *curr_state1 = *curr_state;
8296 curr_state1->dfa_state = dfa_state;
8297 curr_state1->allocated_states_chain = allocated_states_chain;
8298 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
8299 dfa_state_size);
8300 curr_state = curr_state1;
8302 if (!try_issue_nops (curr_state,
8303 3 - curr_state->accumulated_insns_num % 3))
8304 return;
8305 curr_state->after_nops_num
8306 = 3 - curr_state->accumulated_insns_num % 3;
8307 curr_state->accumulated_insns_num
8308 += 3 - curr_state->accumulated_insns_num % 3;
8310 if (!insert_bundle_state (curr_state))
8311 free_bundle_state (curr_state);
8312 return;
8315 /* The following function returns position in the two window bundle
8316 for given STATE. */
8318 static int
8319 get_max_pos (state_t state)
8321 if (cpu_unit_reservation_p (state, pos_6))
8322 return 6;
8323 else if (cpu_unit_reservation_p (state, pos_5))
8324 return 5;
8325 else if (cpu_unit_reservation_p (state, pos_4))
8326 return 4;
8327 else if (cpu_unit_reservation_p (state, pos_3))
8328 return 3;
8329 else if (cpu_unit_reservation_p (state, pos_2))
8330 return 2;
8331 else if (cpu_unit_reservation_p (state, pos_1))
8332 return 1;
8333 else
8334 return 0;
8337 /* The function returns code of a possible template for given position
8338 and state. The function should be called only with 2 values of
8339 position equal to 3 or 6. We avoid generating F NOPs by putting
8340 templates containing F insns at the end of the template search
8341 because undocumented anomaly in McKinley derived cores which can
8342 cause stalls if an F-unit insn (including a NOP) is issued within a
8343 six-cycle window after reading certain application registers (such
8344 as ar.bsp). Furthermore, power-considerations also argue against
8345 the use of F-unit instructions unless they're really needed. */
8347 static int
8348 get_template (state_t state, int pos)
8350 switch (pos)
8352 case 3:
8353 if (cpu_unit_reservation_p (state, _0mmi_))
8354 return 1;
8355 else if (cpu_unit_reservation_p (state, _0mii_))
8356 return 0;
8357 else if (cpu_unit_reservation_p (state, _0mmb_))
8358 return 7;
8359 else if (cpu_unit_reservation_p (state, _0mib_))
8360 return 6;
8361 else if (cpu_unit_reservation_p (state, _0mbb_))
8362 return 5;
8363 else if (cpu_unit_reservation_p (state, _0bbb_))
8364 return 4;
8365 else if (cpu_unit_reservation_p (state, _0mmf_))
8366 return 3;
8367 else if (cpu_unit_reservation_p (state, _0mfi_))
8368 return 2;
8369 else if (cpu_unit_reservation_p (state, _0mfb_))
8370 return 8;
8371 else if (cpu_unit_reservation_p (state, _0mlx_))
8372 return 9;
8373 else
8374 gcc_unreachable ();
8375 case 6:
8376 if (cpu_unit_reservation_p (state, _1mmi_))
8377 return 1;
8378 else if (cpu_unit_reservation_p (state, _1mii_))
8379 return 0;
8380 else if (cpu_unit_reservation_p (state, _1mmb_))
8381 return 7;
8382 else if (cpu_unit_reservation_p (state, _1mib_))
8383 return 6;
8384 else if (cpu_unit_reservation_p (state, _1mbb_))
8385 return 5;
8386 else if (cpu_unit_reservation_p (state, _1bbb_))
8387 return 4;
8388 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
8389 return 3;
8390 else if (cpu_unit_reservation_p (state, _1mfi_))
8391 return 2;
8392 else if (cpu_unit_reservation_p (state, _1mfb_))
8393 return 8;
8394 else if (cpu_unit_reservation_p (state, _1mlx_))
8395 return 9;
8396 else
8397 gcc_unreachable ();
8398 default:
8399 gcc_unreachable ();
8403 /* True when INSN is important for bundling. */
8404 static bool
8405 important_for_bundling_p (rtx insn)
8407 return (INSN_P (insn)
8408 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8409 && GET_CODE (PATTERN (insn)) != USE
8410 && GET_CODE (PATTERN (insn)) != CLOBBER);
8413 /* The following function returns an insn important for insn bundling
8414 followed by INSN and before TAIL. */
8416 static rtx
8417 get_next_important_insn (rtx insn, rtx tail)
8419 for (; insn && insn != tail; insn = NEXT_INSN (insn))
8420 if (important_for_bundling_p (insn))
8421 return insn;
8422 return NULL_RTX;
8425 /* Add a bundle selector TEMPLATE0 before INSN. */
8427 static void
8428 ia64_add_bundle_selector_before (int template0, rtx insn)
8430 rtx b = gen_bundle_selector (GEN_INT (template0));
8432 ia64_emit_insn_before (b, insn);
8433 #if NR_BUNDLES == 10
8434 if ((template0 == 4 || template0 == 5)
8435 && (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
8437 int i;
8438 rtx note = NULL_RTX;
8440 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8441 first or second slot. If it is and has REG_EH_NOTE set, copy it
8442 to following nops, as br.call sets rp to the address of following
8443 bundle and therefore an EH region end must be on a bundle
8444 boundary. */
8445 insn = PREV_INSN (insn);
8446 for (i = 0; i < 3; i++)
8449 insn = next_active_insn (insn);
8450 while (GET_CODE (insn) == INSN
8451 && get_attr_empty (insn) == EMPTY_YES);
8452 if (GET_CODE (insn) == CALL_INSN)
8453 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8454 else if (note)
8456 int code;
8458 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
8459 || code == CODE_FOR_nop_b);
8460 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
8461 note = NULL_RTX;
8462 else
8463 add_reg_note (insn, REG_EH_REGION, XEXP (note, 0));
8467 #endif
8470 /* The following function does insn bundling. Bundling means
8471 inserting templates and nop insns to fit insn groups into permitted
8472 templates. Instruction scheduling uses NDFA (non-deterministic
8473 finite automata) encoding informations about the templates and the
8474 inserted nops. Nondeterminism of the automata permits follows
8475 all possible insn sequences very fast.
8477 Unfortunately it is not possible to get information about inserting
8478 nop insns and used templates from the automata states. The
8479 automata only says that we can issue an insn possibly inserting
8480 some nops before it and using some template. Therefore insn
8481 bundling in this function is implemented by using DFA
8482 (deterministic finite automata). We follow all possible insn
8483 sequences by inserting 0-2 nops (that is what the NDFA describe for
8484 insn scheduling) before/after each insn being bundled. We know the
8485 start of simulated processor cycle from insn scheduling (insn
8486 starting a new cycle has TImode).
8488 Simple implementation of insn bundling would create enormous
8489 number of possible insn sequences satisfying information about new
8490 cycle ticks taken from the insn scheduling. To make the algorithm
8491 practical we use dynamic programming. Each decision (about
8492 inserting nops and implicitly about previous decisions) is described
8493 by structure bundle_state (see above). If we generate the same
8494 bundle state (key is automaton state after issuing the insns and
8495 nops for it), we reuse already generated one. As consequence we
8496 reject some decisions which cannot improve the solution and
8497 reduce memory for the algorithm.
8499 When we reach the end of EBB (extended basic block), we choose the
8500 best sequence and then, moving back in EBB, insert templates for
8501 the best alternative. The templates are taken from querying
8502 automaton state for each insn in chosen bundle states.
8504 So the algorithm makes two (forward and backward) passes through
8505 EBB. */
8507 static void
8508 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
8510 struct bundle_state *curr_state, *next_state, *best_state;
8511 rtx insn, next_insn;
8512 int insn_num;
8513 int i, bundle_end_p, only_bundle_end_p, asm_p;
8514 int pos = 0, max_pos, template0, template1;
8515 rtx b;
8516 rtx nop;
8517 enum attr_type type;
8519 insn_num = 0;
8520 /* Count insns in the EBB. */
8521 for (insn = NEXT_INSN (prev_head_insn);
8522 insn && insn != tail;
8523 insn = NEXT_INSN (insn))
8524 if (INSN_P (insn))
8525 insn_num++;
8526 if (insn_num == 0)
8527 return;
8528 bundling_p = 1;
8529 dfa_clean_insn_cache ();
8530 initiate_bundle_state_table ();
8531 index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2);
8532 /* First (forward) pass -- generation of bundle states. */
8533 curr_state = get_free_bundle_state ();
8534 curr_state->insn = NULL;
8535 curr_state->before_nops_num = 0;
8536 curr_state->after_nops_num = 0;
8537 curr_state->insn_num = 0;
8538 curr_state->cost = 0;
8539 curr_state->accumulated_insns_num = 0;
8540 curr_state->branch_deviation = 0;
8541 curr_state->middle_bundle_stops = 0;
8542 curr_state->next = NULL;
8543 curr_state->originator = NULL;
8544 state_reset (curr_state->dfa_state);
8545 index_to_bundle_states [0] = curr_state;
8546 insn_num = 0;
8547 /* Shift cycle mark if it is put on insn which could be ignored. */
8548 for (insn = NEXT_INSN (prev_head_insn);
8549 insn != tail;
8550 insn = NEXT_INSN (insn))
8551 if (INSN_P (insn)
8552 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
8553 || GET_CODE (PATTERN (insn)) == USE
8554 || GET_CODE (PATTERN (insn)) == CLOBBER)
8555 && GET_MODE (insn) == TImode)
8557 PUT_MODE (insn, VOIDmode);
8558 for (next_insn = NEXT_INSN (insn);
8559 next_insn != tail;
8560 next_insn = NEXT_INSN (next_insn))
8561 if (INSN_P (next_insn)
8562 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
8563 && GET_CODE (PATTERN (next_insn)) != USE
8564 && GET_CODE (PATTERN (next_insn)) != CLOBBER
8565 && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier)
8567 PUT_MODE (next_insn, TImode);
8568 break;
8571 /* Forward pass: generation of bundle states. */
8572 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
8573 insn != NULL_RTX;
8574 insn = next_insn)
8576 gcc_assert (INSN_P (insn)
8577 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8578 && GET_CODE (PATTERN (insn)) != USE
8579 && GET_CODE (PATTERN (insn)) != CLOBBER);
8580 type = ia64_safe_type (insn);
8581 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
8582 insn_num++;
8583 index_to_bundle_states [insn_num] = NULL;
8584 for (curr_state = index_to_bundle_states [insn_num - 1];
8585 curr_state != NULL;
8586 curr_state = next_state)
8588 pos = curr_state->accumulated_insns_num % 3;
8589 next_state = curr_state->next;
8590 /* We must fill up the current bundle in order to start a
8591 subsequent asm insn in a new bundle. Asm insn is always
8592 placed in a separate bundle. */
8593 only_bundle_end_p
8594 = (next_insn != NULL_RTX
8595 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
8596 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
8597 /* We may fill up the current bundle if it is the cycle end
8598 without a group barrier. */
8599 bundle_end_p
8600 = (only_bundle_end_p || next_insn == NULL_RTX
8601 || (GET_MODE (next_insn) == TImode
8602 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
8603 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
8604 || type == TYPE_S)
8605 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
8606 only_bundle_end_p);
8607 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
8608 only_bundle_end_p);
8609 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
8610 only_bundle_end_p);
8612 gcc_assert (index_to_bundle_states [insn_num]);
8613 for (curr_state = index_to_bundle_states [insn_num];
8614 curr_state != NULL;
8615 curr_state = curr_state->next)
8616 if (verbose >= 2 && dump)
8618 /* This structure is taken from generated code of the
8619 pipeline hazard recognizer (see file insn-attrtab.c).
8620 Please don't forget to change the structure if a new
8621 automaton is added to .md file. */
8622 struct DFA_chip
8624 unsigned short one_automaton_state;
8625 unsigned short oneb_automaton_state;
8626 unsigned short two_automaton_state;
8627 unsigned short twob_automaton_state;
8630 fprintf
8631 (dump,
8632 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
8633 curr_state->unique_num,
8634 (curr_state->originator == NULL
8635 ? -1 : curr_state->originator->unique_num),
8636 curr_state->cost,
8637 curr_state->before_nops_num, curr_state->after_nops_num,
8638 curr_state->accumulated_insns_num, curr_state->branch_deviation,
8639 curr_state->middle_bundle_stops,
8640 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
8641 INSN_UID (insn));
8645 /* We should find a solution because the 2nd insn scheduling has
8646 found one. */
8647 gcc_assert (index_to_bundle_states [insn_num]);
8648 /* Find a state corresponding to the best insn sequence. */
8649 best_state = NULL;
8650 for (curr_state = index_to_bundle_states [insn_num];
8651 curr_state != NULL;
8652 curr_state = curr_state->next)
8653 /* We are just looking at the states with fully filled up last
8654 bundle. The first we prefer insn sequences with minimal cost
8655 then with minimal inserted nops and finally with branch insns
8656 placed in the 3rd slots. */
8657 if (curr_state->accumulated_insns_num % 3 == 0
8658 && (best_state == NULL || best_state->cost > curr_state->cost
8659 || (best_state->cost == curr_state->cost
8660 && (curr_state->accumulated_insns_num
8661 < best_state->accumulated_insns_num
8662 || (curr_state->accumulated_insns_num
8663 == best_state->accumulated_insns_num
8664 && (curr_state->branch_deviation
8665 < best_state->branch_deviation
8666 || (curr_state->branch_deviation
8667 == best_state->branch_deviation
8668 && curr_state->middle_bundle_stops
8669 < best_state->middle_bundle_stops)))))))
8670 best_state = curr_state;
8671 /* Second (backward) pass: adding nops and templates. */
8672 gcc_assert (best_state);
8673 insn_num = best_state->before_nops_num;
8674 template0 = template1 = -1;
8675 for (curr_state = best_state;
8676 curr_state->originator != NULL;
8677 curr_state = curr_state->originator)
8679 insn = curr_state->insn;
8680 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
8681 || asm_noperands (PATTERN (insn)) >= 0);
8682 insn_num++;
8683 if (verbose >= 2 && dump)
8685 struct DFA_chip
8687 unsigned short one_automaton_state;
8688 unsigned short oneb_automaton_state;
8689 unsigned short two_automaton_state;
8690 unsigned short twob_automaton_state;
8693 fprintf
8694 (dump,
8695 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
8696 curr_state->unique_num,
8697 (curr_state->originator == NULL
8698 ? -1 : curr_state->originator->unique_num),
8699 curr_state->cost,
8700 curr_state->before_nops_num, curr_state->after_nops_num,
8701 curr_state->accumulated_insns_num, curr_state->branch_deviation,
8702 curr_state->middle_bundle_stops,
8703 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
8704 INSN_UID (insn));
8706 /* Find the position in the current bundle window. The window can
8707 contain at most two bundles. Two bundle window means that
8708 the processor will make two bundle rotation. */
8709 max_pos = get_max_pos (curr_state->dfa_state);
8710 if (max_pos == 6
8711 /* The following (negative template number) means that the
8712 processor did one bundle rotation. */
8713 || (max_pos == 3 && template0 < 0))
8715 /* We are at the end of the window -- find template(s) for
8716 its bundle(s). */
8717 pos = max_pos;
8718 if (max_pos == 3)
8719 template0 = get_template (curr_state->dfa_state, 3);
8720 else
8722 template1 = get_template (curr_state->dfa_state, 3);
8723 template0 = get_template (curr_state->dfa_state, 6);
8726 if (max_pos > 3 && template1 < 0)
8727 /* It may happen when we have the stop inside a bundle. */
8729 gcc_assert (pos <= 3);
8730 template1 = get_template (curr_state->dfa_state, 3);
8731 pos += 3;
8733 if (!asm_p)
8734 /* Emit nops after the current insn. */
8735 for (i = 0; i < curr_state->after_nops_num; i++)
8737 nop = gen_nop ();
8738 emit_insn_after (nop, insn);
8739 pos--;
8740 gcc_assert (pos >= 0);
8741 if (pos % 3 == 0)
8743 /* We are at the start of a bundle: emit the template
8744 (it should be defined). */
8745 gcc_assert (template0 >= 0);
8746 ia64_add_bundle_selector_before (template0, nop);
8747 /* If we have two bundle window, we make one bundle
8748 rotation. Otherwise template0 will be undefined
8749 (negative value). */
8750 template0 = template1;
8751 template1 = -1;
8754 /* Move the position backward in the window. Group barrier has
8755 no slot. Asm insn takes all bundle. */
8756 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8757 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8758 && asm_noperands (PATTERN (insn)) < 0)
8759 pos--;
8760 /* Long insn takes 2 slots. */
8761 if (ia64_safe_type (insn) == TYPE_L)
8762 pos--;
8763 gcc_assert (pos >= 0);
8764 if (pos % 3 == 0
8765 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8766 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8767 && asm_noperands (PATTERN (insn)) < 0)
8769 /* The current insn is at the bundle start: emit the
8770 template. */
8771 gcc_assert (template0 >= 0);
8772 ia64_add_bundle_selector_before (template0, insn);
8773 b = PREV_INSN (insn);
8774 insn = b;
8775 /* See comment above in analogous place for emitting nops
8776 after the insn. */
8777 template0 = template1;
8778 template1 = -1;
8780 /* Emit nops after the current insn. */
8781 for (i = 0; i < curr_state->before_nops_num; i++)
8783 nop = gen_nop ();
8784 ia64_emit_insn_before (nop, insn);
8785 nop = PREV_INSN (insn);
8786 insn = nop;
8787 pos--;
8788 gcc_assert (pos >= 0);
8789 if (pos % 3 == 0)
8791 /* See comment above in analogous place for emitting nops
8792 after the insn. */
8793 gcc_assert (template0 >= 0);
8794 ia64_add_bundle_selector_before (template0, insn);
8795 b = PREV_INSN (insn);
8796 insn = b;
8797 template0 = template1;
8798 template1 = -1;
8803 #ifdef ENABLE_CHECKING
8805 /* Assert right calculation of middle_bundle_stops. */
8806 int num = best_state->middle_bundle_stops;
8807 bool start_bundle = true, end_bundle = false;
8809 for (insn = NEXT_INSN (prev_head_insn);
8810 insn && insn != tail;
8811 insn = NEXT_INSN (insn))
8813 if (!INSN_P (insn))
8814 continue;
8815 if (recog_memoized (insn) == CODE_FOR_bundle_selector)
8816 start_bundle = true;
8817 else
8819 rtx next_insn;
8821 for (next_insn = NEXT_INSN (insn);
8822 next_insn && next_insn != tail;
8823 next_insn = NEXT_INSN (next_insn))
8824 if (INSN_P (next_insn)
8825 && (ia64_safe_itanium_class (next_insn)
8826 != ITANIUM_CLASS_IGNORE
8827 || recog_memoized (next_insn)
8828 == CODE_FOR_bundle_selector)
8829 && GET_CODE (PATTERN (next_insn)) != USE
8830 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
8831 break;
8833 end_bundle = next_insn == NULL_RTX
8834 || next_insn == tail
8835 || (INSN_P (next_insn)
8836 && recog_memoized (next_insn)
8837 == CODE_FOR_bundle_selector);
8838 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier
8839 && !start_bundle && !end_bundle
8840 && next_insn
8841 && GET_CODE (PATTERN (next_insn)) != ASM_INPUT
8842 && asm_noperands (PATTERN (next_insn)) < 0)
8843 num--;
8845 start_bundle = false;
8849 gcc_assert (num == 0);
8851 #endif
8853 free (index_to_bundle_states);
8854 finish_bundle_state_table ();
8855 bundling_p = 0;
8856 dfa_clean_insn_cache ();
8859 /* The following function is called at the end of scheduling BB or
8860 EBB. After reload, it inserts stop bits and does insn bundling. */
8862 static void
8863 ia64_sched_finish (FILE *dump, int sched_verbose)
8865 if (sched_verbose)
8866 fprintf (dump, "// Finishing schedule.\n");
8867 if (!reload_completed)
8868 return;
8869 if (reload_completed)
8871 final_emit_insn_group_barriers (dump);
8872 bundling (dump, sched_verbose, current_sched_info->prev_head,
8873 current_sched_info->next_tail);
8874 if (sched_verbose && dump)
8875 fprintf (dump, "// finishing %d-%d\n",
8876 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
8877 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
8879 return;
8883 /* The following function inserts stop bits in scheduled BB or EBB. */
8885 static void
8886 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
8888 rtx insn;
8889 int need_barrier_p = 0;
8890 int seen_good_insn = 0;
8892 init_insn_group_barriers ();
8894 for (insn = NEXT_INSN (current_sched_info->prev_head);
8895 insn != current_sched_info->next_tail;
8896 insn = NEXT_INSN (insn))
8898 if (GET_CODE (insn) == BARRIER)
8900 rtx last = prev_active_insn (insn);
8902 if (! last)
8903 continue;
8904 if (GET_CODE (last) == JUMP_INSN
8905 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
8906 last = prev_active_insn (last);
8907 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
8908 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
8910 init_insn_group_barriers ();
8911 seen_good_insn = 0;
8912 need_barrier_p = 0;
8914 else if (NONDEBUG_INSN_P (insn))
8916 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
8918 init_insn_group_barriers ();
8919 seen_good_insn = 0;
8920 need_barrier_p = 0;
8922 else if (need_barrier_p || group_barrier_needed (insn)
8923 || (mflag_sched_stop_bits_after_every_cycle
8924 && GET_MODE (insn) == TImode
8925 && seen_good_insn))
8927 if (TARGET_EARLY_STOP_BITS)
8929 rtx last;
8931 for (last = insn;
8932 last != current_sched_info->prev_head;
8933 last = PREV_INSN (last))
8934 if (INSN_P (last) && GET_MODE (last) == TImode
8935 && stops_p [INSN_UID (last)])
8936 break;
8937 if (last == current_sched_info->prev_head)
8938 last = insn;
8939 last = prev_active_insn (last);
8940 if (last
8941 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
8942 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
8943 last);
8944 init_insn_group_barriers ();
8945 for (last = NEXT_INSN (last);
8946 last != insn;
8947 last = NEXT_INSN (last))
8948 if (INSN_P (last))
8950 group_barrier_needed (last);
8951 if (recog_memoized (last) >= 0
8952 && important_for_bundling_p (last))
8953 seen_good_insn = 1;
8956 else
8958 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
8959 insn);
8960 init_insn_group_barriers ();
8961 seen_good_insn = 0;
8963 group_barrier_needed (insn);
8964 if (recog_memoized (insn) >= 0
8965 && important_for_bundling_p (insn))
8966 seen_good_insn = 1;
8968 else if (recog_memoized (insn) >= 0
8969 && important_for_bundling_p (insn))
8970 seen_good_insn = 1;
8971 need_barrier_p = (GET_CODE (insn) == CALL_INSN
8972 || GET_CODE (PATTERN (insn)) == ASM_INPUT
8973 || asm_noperands (PATTERN (insn)) >= 0);
8980 /* If the following function returns TRUE, we will use the DFA
8981 insn scheduler. */
8983 static int
8984 ia64_first_cycle_multipass_dfa_lookahead (void)
8986 return (reload_completed ? 6 : 4);
8989 /* The following function initiates variable `dfa_pre_cycle_insn'. */
8991 static void
8992 ia64_init_dfa_pre_cycle_insn (void)
8994 if (temp_dfa_state == NULL)
8996 dfa_state_size = state_size ();
8997 temp_dfa_state = xmalloc (dfa_state_size);
8998 prev_cycle_state = xmalloc (dfa_state_size);
9000 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
9001 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
9002 recog_memoized (dfa_pre_cycle_insn);
9003 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9004 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
9005 recog_memoized (dfa_stop_insn);
9008 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9009 used by the DFA insn scheduler. */
9011 static rtx
9012 ia64_dfa_pre_cycle_insn (void)
9014 return dfa_pre_cycle_insn;
9017 /* The following function returns TRUE if PRODUCER (of type ilog or
9018 ld) produces address for CONSUMER (of type st or stf). */
9021 ia64_st_address_bypass_p (rtx producer, rtx consumer)
9023 rtx dest, reg, mem;
9025 gcc_assert (producer && consumer);
9026 dest = ia64_single_set (producer);
9027 gcc_assert (dest);
9028 reg = SET_DEST (dest);
9029 gcc_assert (reg);
9030 if (GET_CODE (reg) == SUBREG)
9031 reg = SUBREG_REG (reg);
9032 gcc_assert (GET_CODE (reg) == REG);
9034 dest = ia64_single_set (consumer);
9035 gcc_assert (dest);
9036 mem = SET_DEST (dest);
9037 gcc_assert (mem && GET_CODE (mem) == MEM);
9038 return reg_mentioned_p (reg, mem);
9041 /* The following function returns TRUE if PRODUCER (of type ilog or
9042 ld) produces address for CONSUMER (of type ld or fld). */
9045 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
9047 rtx dest, src, reg, mem;
9049 gcc_assert (producer && consumer);
9050 dest = ia64_single_set (producer);
9051 gcc_assert (dest);
9052 reg = SET_DEST (dest);
9053 gcc_assert (reg);
9054 if (GET_CODE (reg) == SUBREG)
9055 reg = SUBREG_REG (reg);
9056 gcc_assert (GET_CODE (reg) == REG);
9058 src = ia64_single_set (consumer);
9059 gcc_assert (src);
9060 mem = SET_SRC (src);
9061 gcc_assert (mem);
9063 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
9064 mem = XVECEXP (mem, 0, 0);
9065 else if (GET_CODE (mem) == IF_THEN_ELSE)
9066 /* ??? Is this bypass necessary for ld.c? */
9068 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
9069 mem = XEXP (mem, 1);
9072 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
9073 mem = XEXP (mem, 0);
9075 if (GET_CODE (mem) == UNSPEC)
9077 int c = XINT (mem, 1);
9079 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A
9080 || c == UNSPEC_LDSA);
9081 mem = XVECEXP (mem, 0, 0);
9084 /* Note that LO_SUM is used for GOT loads. */
9085 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
9087 return reg_mentioned_p (reg, mem);
9090 /* The following function returns TRUE if INSN produces address for a
9091 load/store insn. We will place such insns into M slot because it
9092 decreases its latency time. */
9095 ia64_produce_address_p (rtx insn)
9097 return insn->call;
9101 /* Emit pseudo-ops for the assembler to describe predicate relations.
9102 At present this assumes that we only consider predicate pairs to
9103 be mutex, and that the assembler can deduce proper values from
9104 straight-line code. */
9106 static void
9107 emit_predicate_relation_info (void)
9109 basic_block bb;
9111 FOR_EACH_BB_REVERSE (bb)
9113 int r;
9114 rtx head = BB_HEAD (bb);
9116 /* We only need such notes at code labels. */
9117 if (GET_CODE (head) != CODE_LABEL)
9118 continue;
9119 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head)))
9120 head = NEXT_INSN (head);
9122 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9123 grabbing the entire block of predicate registers. */
9124 for (r = PR_REG (2); r < PR_REG (64); r += 2)
9125 if (REGNO_REG_SET_P (df_get_live_in (bb), r))
9127 rtx p = gen_rtx_REG (BImode, r);
9128 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
9129 if (head == BB_END (bb))
9130 BB_END (bb) = n;
9131 head = n;
9135 /* Look for conditional calls that do not return, and protect predicate
9136 relations around them. Otherwise the assembler will assume the call
9137 returns, and complain about uses of call-clobbered predicates after
9138 the call. */
9139 FOR_EACH_BB_REVERSE (bb)
9141 rtx insn = BB_HEAD (bb);
9143 while (1)
9145 if (GET_CODE (insn) == CALL_INSN
9146 && GET_CODE (PATTERN (insn)) == COND_EXEC
9147 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
9149 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
9150 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
9151 if (BB_HEAD (bb) == insn)
9152 BB_HEAD (bb) = b;
9153 if (BB_END (bb) == insn)
9154 BB_END (bb) = a;
9157 if (insn == BB_END (bb))
9158 break;
9159 insn = NEXT_INSN (insn);
9164 /* Perform machine dependent operations on the rtl chain INSNS. */
9166 static void
9167 ia64_reorg (void)
9169 /* We are freeing block_for_insn in the toplev to keep compatibility
9170 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9171 compute_bb_for_insn ();
9173 /* If optimizing, we'll have split before scheduling. */
9174 if (optimize == 0)
9175 split_all_insns ();
9177 if (optimize && ia64_flag_schedule_insns2
9178 && dbg_cnt (ia64_sched2))
9180 timevar_push (TV_SCHED2);
9181 ia64_final_schedule = 1;
9183 initiate_bundle_states ();
9184 ia64_nop = make_insn_raw (gen_nop ());
9185 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
9186 recog_memoized (ia64_nop);
9187 clocks_length = get_max_uid () + 1;
9188 stops_p = XCNEWVEC (char, clocks_length);
9190 if (ia64_tune == PROCESSOR_ITANIUM2)
9192 pos_1 = get_cpu_unit_code ("2_1");
9193 pos_2 = get_cpu_unit_code ("2_2");
9194 pos_3 = get_cpu_unit_code ("2_3");
9195 pos_4 = get_cpu_unit_code ("2_4");
9196 pos_5 = get_cpu_unit_code ("2_5");
9197 pos_6 = get_cpu_unit_code ("2_6");
9198 _0mii_ = get_cpu_unit_code ("2b_0mii.");
9199 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
9200 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
9201 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
9202 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
9203 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
9204 _0mib_ = get_cpu_unit_code ("2b_0mib.");
9205 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
9206 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
9207 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
9208 _1mii_ = get_cpu_unit_code ("2b_1mii.");
9209 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
9210 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
9211 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
9212 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
9213 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
9214 _1mib_ = get_cpu_unit_code ("2b_1mib.");
9215 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
9216 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
9217 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
9219 else
9221 pos_1 = get_cpu_unit_code ("1_1");
9222 pos_2 = get_cpu_unit_code ("1_2");
9223 pos_3 = get_cpu_unit_code ("1_3");
9224 pos_4 = get_cpu_unit_code ("1_4");
9225 pos_5 = get_cpu_unit_code ("1_5");
9226 pos_6 = get_cpu_unit_code ("1_6");
9227 _0mii_ = get_cpu_unit_code ("1b_0mii.");
9228 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
9229 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
9230 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
9231 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
9232 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
9233 _0mib_ = get_cpu_unit_code ("1b_0mib.");
9234 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
9235 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
9236 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
9237 _1mii_ = get_cpu_unit_code ("1b_1mii.");
9238 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
9239 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
9240 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
9241 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
9242 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
9243 _1mib_ = get_cpu_unit_code ("1b_1mib.");
9244 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
9245 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
9246 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
9249 if (flag_selective_scheduling2
9250 && !maybe_skip_selective_scheduling ())
9251 run_selective_scheduling ();
9252 else
9253 schedule_ebbs ();
9255 /* Redo alignment computation, as it might gone wrong. */
9256 compute_alignments ();
9258 /* We cannot reuse this one because it has been corrupted by the
9259 evil glat. */
9260 finish_bundle_states ();
9261 free (stops_p);
9262 stops_p = NULL;
9263 emit_insn_group_barriers (dump_file);
9265 ia64_final_schedule = 0;
9266 timevar_pop (TV_SCHED2);
9268 else
9269 emit_all_insn_group_barriers (dump_file);
9271 df_analyze ();
9273 /* A call must not be the last instruction in a function, so that the
9274 return address is still within the function, so that unwinding works
9275 properly. Note that IA-64 differs from dwarf2 on this point. */
9276 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
9278 rtx insn;
9279 int saw_stop = 0;
9281 insn = get_last_insn ();
9282 if (! INSN_P (insn))
9283 insn = prev_active_insn (insn);
9284 if (insn)
9286 /* Skip over insns that expand to nothing. */
9287 while (GET_CODE (insn) == INSN
9288 && get_attr_empty (insn) == EMPTY_YES)
9290 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
9291 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
9292 saw_stop = 1;
9293 insn = prev_active_insn (insn);
9295 if (GET_CODE (insn) == CALL_INSN)
9297 if (! saw_stop)
9298 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9299 emit_insn (gen_break_f ());
9300 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9305 emit_predicate_relation_info ();
9307 if (ia64_flag_var_tracking)
9309 timevar_push (TV_VAR_TRACKING);
9310 variable_tracking_main ();
9311 timevar_pop (TV_VAR_TRACKING);
9313 df_finish_pass (false);
9316 /* Return true if REGNO is used by the epilogue. */
9319 ia64_epilogue_uses (int regno)
9321 switch (regno)
9323 case R_GR (1):
9324 /* With a call to a function in another module, we will write a new
9325 value to "gp". After returning from such a call, we need to make
9326 sure the function restores the original gp-value, even if the
9327 function itself does not use the gp anymore. */
9328 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
9330 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9331 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9332 /* For functions defined with the syscall_linkage attribute, all
9333 input registers are marked as live at all function exits. This
9334 prevents the register allocator from using the input registers,
9335 which in turn makes it possible to restart a system call after
9336 an interrupt without having to save/restore the input registers.
9337 This also prevents kernel data from leaking to application code. */
9338 return lookup_attribute ("syscall_linkage",
9339 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
9341 case R_BR (0):
9342 /* Conditional return patterns can't represent the use of `b0' as
9343 the return address, so we force the value live this way. */
9344 return 1;
9346 case AR_PFS_REGNUM:
9347 /* Likewise for ar.pfs, which is used by br.ret. */
9348 return 1;
9350 default:
9351 return 0;
9355 /* Return true if REGNO is used by the frame unwinder. */
9358 ia64_eh_uses (int regno)
9360 unsigned int r;
9362 if (! reload_completed)
9363 return 0;
9365 if (regno == 0)
9366 return 0;
9368 for (r = reg_save_b0; r <= reg_save_ar_lc; r++)
9369 if (regno == current_frame_info.r[r]
9370 || regno == emitted_frame_related_regs[r])
9371 return 1;
9373 return 0;
9376 /* Return true if this goes in small data/bss. */
9378 /* ??? We could also support own long data here. Generating movl/add/ld8
9379 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9380 code faster because there is one less load. This also includes incomplete
9381 types which can't go in sdata/sbss. */
9383 static bool
9384 ia64_in_small_data_p (const_tree exp)
9386 if (TARGET_NO_SDATA)
9387 return false;
9389 /* We want to merge strings, so we never consider them small data. */
9390 if (TREE_CODE (exp) == STRING_CST)
9391 return false;
9393 /* Functions are never small data. */
9394 if (TREE_CODE (exp) == FUNCTION_DECL)
9395 return false;
9397 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
9399 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
9401 if (strcmp (section, ".sdata") == 0
9402 || strncmp (section, ".sdata.", 7) == 0
9403 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9404 || strcmp (section, ".sbss") == 0
9405 || strncmp (section, ".sbss.", 6) == 0
9406 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9407 return true;
9409 else
9411 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
9413 /* If this is an incomplete type with size 0, then we can't put it
9414 in sdata because it might be too big when completed. */
9415 if (size > 0 && size <= ia64_section_threshold)
9416 return true;
9419 return false;
9422 /* Output assembly directives for prologue regions. */
9424 /* The current basic block number. */
9426 static bool last_block;
9428 /* True if we need a copy_state command at the start of the next block. */
9430 static bool need_copy_state;
9432 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9433 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9434 #endif
9436 /* Emit a debugging label after a call-frame-related insn. We'd
9437 rather output the label right away, but we'd have to output it
9438 after, not before, the instruction, and the instruction has not
9439 been output yet. So we emit the label after the insn, delete it to
9440 avoid introducing basic blocks, and mark it as preserved, such that
9441 it is still output, given that it is referenced in debug info. */
9443 static const char *
9444 ia64_emit_deleted_label_after_insn (rtx insn)
9446 char label[MAX_ARTIFICIAL_LABEL_BYTES];
9447 rtx lb = gen_label_rtx ();
9448 rtx label_insn = emit_label_after (lb, insn);
9450 LABEL_PRESERVE_P (lb) = 1;
9452 delete_insn (label_insn);
9454 ASM_GENERATE_INTERNAL_LABEL (label, "L", CODE_LABEL_NUMBER (label_insn));
9456 return xstrdup (label);
9459 /* Define the CFA after INSN with the steady-state definition. */
9461 static void
9462 ia64_dwarf2out_def_steady_cfa (rtx insn, bool frame)
9464 rtx fp = frame_pointer_needed
9465 ? hard_frame_pointer_rtx
9466 : stack_pointer_rtx;
9467 const char *label = ia64_emit_deleted_label_after_insn (insn);
9469 if (!frame)
9470 return;
9472 dwarf2out_def_cfa
9473 (label, REGNO (fp),
9474 ia64_initial_elimination_offset
9475 (REGNO (arg_pointer_rtx), REGNO (fp))
9476 + ARG_POINTER_CFA_OFFSET (current_function_decl));
9479 /* The generic dwarf2 frame debug info generator does not define a
9480 separate region for the very end of the epilogue, so refrain from
9481 doing so in the IA64-specific code as well. */
9483 #define IA64_CHANGE_CFA_IN_EPILOGUE 0
9485 /* The function emits unwind directives for the start of an epilogue. */
9487 static void
9488 process_epilogue (FILE *asm_out_file, rtx insn, bool unwind, bool frame)
9490 /* If this isn't the last block of the function, then we need to label the
9491 current state, and copy it back in at the start of the next block. */
9493 if (!last_block)
9495 if (unwind)
9496 fprintf (asm_out_file, "\t.label_state %d\n",
9497 ++cfun->machine->state_num);
9498 need_copy_state = true;
9501 if (unwind)
9502 fprintf (asm_out_file, "\t.restore sp\n");
9503 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
9504 dwarf2out_def_cfa (ia64_emit_deleted_label_after_insn (insn),
9505 STACK_POINTER_REGNUM, INCOMING_FRAME_SP_OFFSET);
9508 /* This function processes a SET pattern looking for specific patterns
9509 which result in emitting an assembly directive required for unwinding. */
9511 static int
9512 process_set (FILE *asm_out_file, rtx pat, rtx insn, bool unwind, bool frame)
9514 rtx src = SET_SRC (pat);
9515 rtx dest = SET_DEST (pat);
9516 int src_regno, dest_regno;
9518 /* Look for the ALLOC insn. */
9519 if (GET_CODE (src) == UNSPEC_VOLATILE
9520 && XINT (src, 1) == UNSPECV_ALLOC
9521 && GET_CODE (dest) == REG)
9523 dest_regno = REGNO (dest);
9525 /* If this is the final destination for ar.pfs, then this must
9526 be the alloc in the prologue. */
9527 if (dest_regno == current_frame_info.r[reg_save_ar_pfs])
9529 if (unwind)
9530 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
9531 ia64_dbx_register_number (dest_regno));
9533 else
9535 /* This must be an alloc before a sibcall. We must drop the
9536 old frame info. The easiest way to drop the old frame
9537 info is to ensure we had a ".restore sp" directive
9538 followed by a new prologue. If the procedure doesn't
9539 have a memory-stack frame, we'll issue a dummy ".restore
9540 sp" now. */
9541 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
9542 /* if haven't done process_epilogue() yet, do it now */
9543 process_epilogue (asm_out_file, insn, unwind, frame);
9544 if (unwind)
9545 fprintf (asm_out_file, "\t.prologue\n");
9547 return 1;
9550 /* Look for SP = .... */
9551 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
9553 if (GET_CODE (src) == PLUS)
9555 rtx op0 = XEXP (src, 0);
9556 rtx op1 = XEXP (src, 1);
9558 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
9560 if (INTVAL (op1) < 0)
9562 gcc_assert (!frame_pointer_needed);
9563 if (unwind)
9564 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
9565 -INTVAL (op1));
9566 ia64_dwarf2out_def_steady_cfa (insn, frame);
9568 else
9569 process_epilogue (asm_out_file, insn, unwind, frame);
9571 else
9573 gcc_assert (GET_CODE (src) == REG
9574 && REGNO (src) == HARD_FRAME_POINTER_REGNUM);
9575 process_epilogue (asm_out_file, insn, unwind, frame);
9578 return 1;
9581 /* Register move we need to look at. */
9582 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
9584 src_regno = REGNO (src);
9585 dest_regno = REGNO (dest);
9587 switch (src_regno)
9589 case BR_REG (0):
9590 /* Saving return address pointer. */
9591 gcc_assert (dest_regno == current_frame_info.r[reg_save_b0]);
9592 if (unwind)
9593 fprintf (asm_out_file, "\t.save rp, r%d\n",
9594 ia64_dbx_register_number (dest_regno));
9595 return 1;
9597 case PR_REG (0):
9598 gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]);
9599 if (unwind)
9600 fprintf (asm_out_file, "\t.save pr, r%d\n",
9601 ia64_dbx_register_number (dest_regno));
9602 return 1;
9604 case AR_UNAT_REGNUM:
9605 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]);
9606 if (unwind)
9607 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
9608 ia64_dbx_register_number (dest_regno));
9609 return 1;
9611 case AR_LC_REGNUM:
9612 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]);
9613 if (unwind)
9614 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
9615 ia64_dbx_register_number (dest_regno));
9616 return 1;
9618 case STACK_POINTER_REGNUM:
9619 gcc_assert (dest_regno == HARD_FRAME_POINTER_REGNUM
9620 && frame_pointer_needed);
9621 if (unwind)
9622 fprintf (asm_out_file, "\t.vframe r%d\n",
9623 ia64_dbx_register_number (dest_regno));
9624 ia64_dwarf2out_def_steady_cfa (insn, frame);
9625 return 1;
9627 default:
9628 /* Everything else should indicate being stored to memory. */
9629 gcc_unreachable ();
9633 /* Memory store we need to look at. */
9634 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
9636 long off;
9637 rtx base;
9638 const char *saveop;
9640 if (GET_CODE (XEXP (dest, 0)) == REG)
9642 base = XEXP (dest, 0);
9643 off = 0;
9645 else
9647 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
9648 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
9649 base = XEXP (XEXP (dest, 0), 0);
9650 off = INTVAL (XEXP (XEXP (dest, 0), 1));
9653 if (base == hard_frame_pointer_rtx)
9655 saveop = ".savepsp";
9656 off = - off;
9658 else
9660 gcc_assert (base == stack_pointer_rtx);
9661 saveop = ".savesp";
9664 src_regno = REGNO (src);
9665 switch (src_regno)
9667 case BR_REG (0):
9668 gcc_assert (!current_frame_info.r[reg_save_b0]);
9669 if (unwind)
9670 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
9671 return 1;
9673 case PR_REG (0):
9674 gcc_assert (!current_frame_info.r[reg_save_pr]);
9675 if (unwind)
9676 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
9677 return 1;
9679 case AR_LC_REGNUM:
9680 gcc_assert (!current_frame_info.r[reg_save_ar_lc]);
9681 if (unwind)
9682 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
9683 return 1;
9685 case AR_PFS_REGNUM:
9686 gcc_assert (!current_frame_info.r[reg_save_ar_pfs]);
9687 if (unwind)
9688 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
9689 return 1;
9691 case AR_UNAT_REGNUM:
9692 gcc_assert (!current_frame_info.r[reg_save_ar_unat]);
9693 if (unwind)
9694 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
9695 return 1;
9697 case GR_REG (4):
9698 case GR_REG (5):
9699 case GR_REG (6):
9700 case GR_REG (7):
9701 if (unwind)
9702 fprintf (asm_out_file, "\t.save.g 0x%x\n",
9703 1 << (src_regno - GR_REG (4)));
9704 return 1;
9706 case BR_REG (1):
9707 case BR_REG (2):
9708 case BR_REG (3):
9709 case BR_REG (4):
9710 case BR_REG (5):
9711 if (unwind)
9712 fprintf (asm_out_file, "\t.save.b 0x%x\n",
9713 1 << (src_regno - BR_REG (1)));
9714 return 1;
9716 case FR_REG (2):
9717 case FR_REG (3):
9718 case FR_REG (4):
9719 case FR_REG (5):
9720 if (unwind)
9721 fprintf (asm_out_file, "\t.save.f 0x%x\n",
9722 1 << (src_regno - FR_REG (2)));
9723 return 1;
9725 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
9726 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
9727 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
9728 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
9729 if (unwind)
9730 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
9731 1 << (src_regno - FR_REG (12)));
9732 return 1;
9734 default:
9735 return 0;
9739 return 0;
9743 /* This function looks at a single insn and emits any directives
9744 required to unwind this insn. */
9745 void
9746 process_for_unwind_directive (FILE *asm_out_file, rtx insn)
9748 bool unwind = (flag_unwind_tables
9749 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS));
9750 bool frame = dwarf2out_do_frame ();
9752 if (unwind || frame)
9754 rtx pat;
9756 if (NOTE_INSN_BASIC_BLOCK_P (insn))
9758 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
9760 /* Restore unwind state from immediately before the epilogue. */
9761 if (need_copy_state)
9763 if (unwind)
9765 fprintf (asm_out_file, "\t.body\n");
9766 fprintf (asm_out_file, "\t.copy_state %d\n",
9767 cfun->machine->state_num);
9769 if (IA64_CHANGE_CFA_IN_EPILOGUE)
9770 ia64_dwarf2out_def_steady_cfa (insn, frame);
9771 need_copy_state = false;
9775 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
9776 return;
9778 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
9779 if (pat)
9780 pat = XEXP (pat, 0);
9781 else
9782 pat = PATTERN (insn);
9784 switch (GET_CODE (pat))
9786 case SET:
9787 process_set (asm_out_file, pat, insn, unwind, frame);
9788 break;
9790 case PARALLEL:
9792 int par_index;
9793 int limit = XVECLEN (pat, 0);
9794 for (par_index = 0; par_index < limit; par_index++)
9796 rtx x = XVECEXP (pat, 0, par_index);
9797 if (GET_CODE (x) == SET)
9798 process_set (asm_out_file, x, insn, unwind, frame);
9800 break;
9803 default:
9804 gcc_unreachable ();
9810 enum ia64_builtins
9812 IA64_BUILTIN_BSP,
9813 IA64_BUILTIN_COPYSIGNQ,
9814 IA64_BUILTIN_FABSQ,
9815 IA64_BUILTIN_FLUSHRS,
9816 IA64_BUILTIN_INFQ,
9817 IA64_BUILTIN_HUGE_VALQ
9820 void
9821 ia64_init_builtins (void)
9823 tree fpreg_type;
9824 tree float80_type;
9826 /* The __fpreg type. */
9827 fpreg_type = make_node (REAL_TYPE);
9828 TYPE_PRECISION (fpreg_type) = 82;
9829 layout_type (fpreg_type);
9830 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
9832 /* The __float80 type. */
9833 float80_type = make_node (REAL_TYPE);
9834 TYPE_PRECISION (float80_type) = 80;
9835 layout_type (float80_type);
9836 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
9838 /* The __float128 type. */
9839 if (!TARGET_HPUX)
9841 tree ftype, decl;
9842 tree float128_type = make_node (REAL_TYPE);
9844 TYPE_PRECISION (float128_type) = 128;
9845 layout_type (float128_type);
9846 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
9848 /* TFmode support builtins. */
9849 ftype = build_function_type (float128_type, void_list_node);
9850 add_builtin_function ("__builtin_infq", ftype,
9851 IA64_BUILTIN_INFQ, BUILT_IN_MD,
9852 NULL, NULL_TREE);
9854 add_builtin_function ("__builtin_huge_valq", ftype,
9855 IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
9856 NULL, NULL_TREE);
9858 ftype = build_function_type_list (float128_type,
9859 float128_type,
9860 NULL_TREE);
9861 decl = add_builtin_function ("__builtin_fabsq", ftype,
9862 IA64_BUILTIN_FABSQ, BUILT_IN_MD,
9863 "__fabstf2", NULL_TREE);
9864 TREE_READONLY (decl) = 1;
9866 ftype = build_function_type_list (float128_type,
9867 float128_type,
9868 float128_type,
9869 NULL_TREE);
9870 decl = add_builtin_function ("__builtin_copysignq", ftype,
9871 IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
9872 "__copysigntf3", NULL_TREE);
9873 TREE_READONLY (decl) = 1;
9875 else
9876 /* Under HPUX, this is a synonym for "long double". */
9877 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
9878 "__float128");
9880 /* Fwrite on VMS is non-standard. */
9881 if (TARGET_ABI_OPEN_VMS)
9883 implicit_built_in_decls[(int) BUILT_IN_FWRITE] = NULL_TREE;
9884 implicit_built_in_decls[(int) BUILT_IN_FWRITE_UNLOCKED] = NULL_TREE;
9887 #define def_builtin(name, type, code) \
9888 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
9889 NULL, NULL_TREE)
9891 def_builtin ("__builtin_ia64_bsp",
9892 build_function_type (ptr_type_node, void_list_node),
9893 IA64_BUILTIN_BSP);
9895 def_builtin ("__builtin_ia64_flushrs",
9896 build_function_type (void_type_node, void_list_node),
9897 IA64_BUILTIN_FLUSHRS);
9899 #undef def_builtin
9901 if (TARGET_HPUX)
9903 if (built_in_decls [BUILT_IN_FINITE])
9904 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE],
9905 "_Isfinite");
9906 if (built_in_decls [BUILT_IN_FINITEF])
9907 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF],
9908 "_Isfinitef");
9909 if (built_in_decls [BUILT_IN_FINITEL])
9910 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEL],
9911 "_Isfinitef128");
9916 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9917 enum machine_mode mode ATTRIBUTE_UNUSED,
9918 int ignore ATTRIBUTE_UNUSED)
9920 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9921 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9923 switch (fcode)
9925 case IA64_BUILTIN_BSP:
9926 if (! target || ! register_operand (target, DImode))
9927 target = gen_reg_rtx (DImode);
9928 emit_insn (gen_bsp_value (target));
9929 #ifdef POINTERS_EXTEND_UNSIGNED
9930 target = convert_memory_address (ptr_mode, target);
9931 #endif
9932 return target;
9934 case IA64_BUILTIN_FLUSHRS:
9935 emit_insn (gen_flushrs ());
9936 return const0_rtx;
9938 case IA64_BUILTIN_INFQ:
9939 case IA64_BUILTIN_HUGE_VALQ:
9941 REAL_VALUE_TYPE inf;
9942 rtx tmp;
9944 real_inf (&inf);
9945 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
9947 tmp = validize_mem (force_const_mem (mode, tmp));
9949 if (target == 0)
9950 target = gen_reg_rtx (mode);
9952 emit_move_insn (target, tmp);
9953 return target;
9956 case IA64_BUILTIN_FABSQ:
9957 case IA64_BUILTIN_COPYSIGNQ:
9958 return expand_call (exp, target, ignore);
9960 default:
9961 gcc_unreachable ();
9964 return NULL_RTX;
9967 /* For the HP-UX IA64 aggregate parameters are passed stored in the
9968 most significant bits of the stack slot. */
9970 enum direction
9971 ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type)
9973 /* Exception to normal case for structures/unions/etc. */
9975 if (type && AGGREGATE_TYPE_P (type)
9976 && int_size_in_bytes (type) < UNITS_PER_WORD)
9977 return upward;
9979 /* Fall back to the default. */
9980 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
9983 /* Emit text to declare externally defined variables and functions, because
9984 the Intel assembler does not support undefined externals. */
9986 void
9987 ia64_asm_output_external (FILE *file, tree decl, const char *name)
9989 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
9990 set in order to avoid putting out names that are never really
9991 used. */
9992 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
9994 /* maybe_assemble_visibility will return 1 if the assembler
9995 visibility directive is output. */
9996 int need_visibility = ((*targetm.binds_local_p) (decl)
9997 && maybe_assemble_visibility (decl));
9999 #ifdef DO_CRTL_NAMES
10000 DO_CRTL_NAMES;
10001 #endif
10003 /* GNU as does not need anything here, but the HP linker does
10004 need something for external functions. */
10005 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
10006 && TREE_CODE (decl) == FUNCTION_DECL)
10007 (*targetm.asm_out.globalize_decl_name) (file, decl);
10008 else if (need_visibility && !TARGET_GNU_AS)
10009 (*targetm.asm_out.globalize_label) (file, name);
10013 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10014 modes of word_mode and larger. Rename the TFmode libfuncs using the
10015 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10016 backward compatibility. */
10018 static void
10019 ia64_init_libfuncs (void)
10021 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
10022 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
10023 set_optab_libfunc (smod_optab, SImode, "__modsi3");
10024 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
10026 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
10027 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
10028 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
10029 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
10030 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
10032 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
10033 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
10034 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
10035 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
10036 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
10037 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
10039 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
10040 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
10041 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
10042 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
10043 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
10045 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
10046 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
10047 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
10048 /* HP-UX 11.23 libc does not have a function for unsigned
10049 SImode-to-TFmode conversion. */
10050 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
10053 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10055 static void
10056 ia64_hpux_init_libfuncs (void)
10058 ia64_init_libfuncs ();
10060 /* The HP SI millicode division and mod functions expect DI arguments.
10061 By turning them off completely we avoid using both libgcc and the
10062 non-standard millicode routines and use the HP DI millicode routines
10063 instead. */
10065 set_optab_libfunc (sdiv_optab, SImode, 0);
10066 set_optab_libfunc (udiv_optab, SImode, 0);
10067 set_optab_libfunc (smod_optab, SImode, 0);
10068 set_optab_libfunc (umod_optab, SImode, 0);
10070 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10071 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10072 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10073 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10075 /* HP-UX libc has TF min/max/abs routines in it. */
10076 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
10077 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
10078 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
10080 /* ia64_expand_compare uses this. */
10081 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
10083 /* These should never be used. */
10084 set_optab_libfunc (eq_optab, TFmode, 0);
10085 set_optab_libfunc (ne_optab, TFmode, 0);
10086 set_optab_libfunc (gt_optab, TFmode, 0);
10087 set_optab_libfunc (ge_optab, TFmode, 0);
10088 set_optab_libfunc (lt_optab, TFmode, 0);
10089 set_optab_libfunc (le_optab, TFmode, 0);
10092 /* Rename the division and modulus functions in VMS. */
10094 static void
10095 ia64_vms_init_libfuncs (void)
10097 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10098 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10099 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10100 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10101 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10102 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10103 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10104 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10105 abort_libfunc = init_one_libfunc ("decc$abort");
10106 memcmp_libfunc = init_one_libfunc ("decc$memcmp");
10107 #ifdef MEM_LIBFUNCS_INIT
10108 MEM_LIBFUNCS_INIT;
10109 #endif
10112 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10113 the HPUX conventions. */
10115 static void
10116 ia64_sysv4_init_libfuncs (void)
10118 ia64_init_libfuncs ();
10120 /* These functions are not part of the HPUX TFmode interface. We
10121 use them instead of _U_Qfcmp, which doesn't work the way we
10122 expect. */
10123 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
10124 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
10125 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
10126 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
10127 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
10128 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
10130 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10131 glibc doesn't have them. */
10134 /* Use soft-fp. */
10136 static void
10137 ia64_soft_fp_init_libfuncs (void)
10141 static bool
10142 ia64_vms_valid_pointer_mode (enum machine_mode mode)
10144 return (mode == SImode || mode == DImode);
10147 /* For HPUX, it is illegal to have relocations in shared segments. */
10149 static int
10150 ia64_hpux_reloc_rw_mask (void)
10152 return 3;
10155 /* For others, relax this so that relocations to local data goes in
10156 read-only segments, but we still cannot allow global relocations
10157 in read-only segments. */
10159 static int
10160 ia64_reloc_rw_mask (void)
10162 return flag_pic ? 3 : 2;
10165 /* Return the section to use for X. The only special thing we do here
10166 is to honor small data. */
10168 static section *
10169 ia64_select_rtx_section (enum machine_mode mode, rtx x,
10170 unsigned HOST_WIDE_INT align)
10172 if (GET_MODE_SIZE (mode) > 0
10173 && GET_MODE_SIZE (mode) <= ia64_section_threshold
10174 && !TARGET_NO_SDATA)
10175 return sdata_section;
10176 else
10177 return default_elf_select_rtx_section (mode, x, align);
10180 static unsigned int
10181 ia64_section_type_flags (tree decl, const char *name, int reloc)
10183 unsigned int flags = 0;
10185 if (strcmp (name, ".sdata") == 0
10186 || strncmp (name, ".sdata.", 7) == 0
10187 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
10188 || strncmp (name, ".sdata2.", 8) == 0
10189 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
10190 || strcmp (name, ".sbss") == 0
10191 || strncmp (name, ".sbss.", 6) == 0
10192 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
10193 flags = SECTION_SMALL;
10195 #if TARGET_ABI_OPEN_VMS
10196 if (decl && DECL_ATTRIBUTES (decl)
10197 && lookup_attribute ("common_object", DECL_ATTRIBUTES (decl)))
10198 flags |= SECTION_VMS_OVERLAY;
10199 #endif
10201 flags |= default_section_type_flags (decl, name, reloc);
10202 return flags;
10205 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10206 structure type and that the address of that type should be passed
10207 in out0, rather than in r8. */
10209 static bool
10210 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
10212 tree ret_type = TREE_TYPE (fntype);
10214 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10215 as the structure return address parameter, if the return value
10216 type has a non-trivial copy constructor or destructor. It is not
10217 clear if this same convention should be used for other
10218 programming languages. Until G++ 3.4, we incorrectly used r8 for
10219 these return values. */
10220 return (abi_version_at_least (2)
10221 && ret_type
10222 && TYPE_MODE (ret_type) == BLKmode
10223 && TREE_ADDRESSABLE (ret_type)
10224 && strcmp (lang_hooks.name, "GNU C++") == 0);
10227 /* Output the assembler code for a thunk function. THUNK_DECL is the
10228 declaration for the thunk function itself, FUNCTION is the decl for
10229 the target function. DELTA is an immediate constant offset to be
10230 added to THIS. If VCALL_OFFSET is nonzero, the word at
10231 *(*this + vcall_offset) should be added to THIS. */
10233 static void
10234 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10235 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10236 tree function)
10238 rtx this_rtx, insn, funexp;
10239 unsigned int this_parmno;
10240 unsigned int this_regno;
10241 rtx delta_rtx;
10243 reload_completed = 1;
10244 epilogue_completed = 1;
10246 /* Set things up as ia64_expand_prologue might. */
10247 last_scratch_gr_reg = 15;
10249 memset (&current_frame_info, 0, sizeof (current_frame_info));
10250 current_frame_info.spill_cfa_off = -16;
10251 current_frame_info.n_input_regs = 1;
10252 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
10254 /* Mark the end of the (empty) prologue. */
10255 emit_note (NOTE_INSN_PROLOGUE_END);
10257 /* Figure out whether "this" will be the first parameter (the
10258 typical case) or the second parameter (as happens when the
10259 virtual function returns certain class objects). */
10260 this_parmno
10261 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
10262 ? 1 : 0);
10263 this_regno = IN_REG (this_parmno);
10264 if (!TARGET_REG_NAMES)
10265 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
10267 this_rtx = gen_rtx_REG (Pmode, this_regno);
10269 /* Apply the constant offset, if required. */
10270 delta_rtx = GEN_INT (delta);
10271 if (TARGET_ILP32)
10273 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
10274 REG_POINTER (tmp) = 1;
10275 if (delta && satisfies_constraint_I (delta_rtx))
10277 emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx));
10278 delta = 0;
10280 else
10281 emit_insn (gen_ptr_extend (this_rtx, tmp));
10283 if (delta)
10285 if (!satisfies_constraint_I (delta_rtx))
10287 rtx tmp = gen_rtx_REG (Pmode, 2);
10288 emit_move_insn (tmp, delta_rtx);
10289 delta_rtx = tmp;
10291 emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx));
10294 /* Apply the offset from the vtable, if required. */
10295 if (vcall_offset)
10297 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10298 rtx tmp = gen_rtx_REG (Pmode, 2);
10300 if (TARGET_ILP32)
10302 rtx t = gen_rtx_REG (ptr_mode, 2);
10303 REG_POINTER (t) = 1;
10304 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx));
10305 if (satisfies_constraint_I (vcall_offset_rtx))
10307 emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx));
10308 vcall_offset = 0;
10310 else
10311 emit_insn (gen_ptr_extend (tmp, t));
10313 else
10314 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
10316 if (vcall_offset)
10318 if (!satisfies_constraint_J (vcall_offset_rtx))
10320 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
10321 emit_move_insn (tmp2, vcall_offset_rtx);
10322 vcall_offset_rtx = tmp2;
10324 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
10327 if (TARGET_ILP32)
10328 emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp)));
10329 else
10330 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
10332 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
10335 /* Generate a tail call to the target function. */
10336 if (! TREE_USED (function))
10338 assemble_external (function);
10339 TREE_USED (function) = 1;
10341 funexp = XEXP (DECL_RTL (function), 0);
10342 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10343 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
10344 insn = get_last_insn ();
10345 SIBLING_CALL_P (insn) = 1;
10347 /* Code generation for calls relies on splitting. */
10348 reload_completed = 1;
10349 epilogue_completed = 1;
10350 try_split (PATTERN (insn), insn, 0);
10352 emit_barrier ();
10354 /* Run just enough of rest_of_compilation to get the insns emitted.
10355 There's not really enough bulk here to make other passes such as
10356 instruction scheduling worth while. Note that use_thunk calls
10357 assemble_start_function and assemble_end_function. */
10359 insn_locators_alloc ();
10360 emit_all_insn_group_barriers (NULL);
10361 insn = get_insns ();
10362 shorten_branches (insn);
10363 final_start_function (insn, file, 1);
10364 final (insn, file, 1);
10365 final_end_function ();
10367 reload_completed = 0;
10368 epilogue_completed = 0;
10371 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10373 static rtx
10374 ia64_struct_value_rtx (tree fntype,
10375 int incoming ATTRIBUTE_UNUSED)
10377 if (TARGET_ABI_OPEN_VMS ||
10378 (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype)))
10379 return NULL_RTX;
10380 return gen_rtx_REG (Pmode, GR_REG (8));
10383 static bool
10384 ia64_scalar_mode_supported_p (enum machine_mode mode)
10386 switch (mode)
10388 case QImode:
10389 case HImode:
10390 case SImode:
10391 case DImode:
10392 case TImode:
10393 return true;
10395 case SFmode:
10396 case DFmode:
10397 case XFmode:
10398 case RFmode:
10399 return true;
10401 case TFmode:
10402 return true;
10404 default:
10405 return false;
10409 static bool
10410 ia64_vector_mode_supported_p (enum machine_mode mode)
10412 switch (mode)
10414 case V8QImode:
10415 case V4HImode:
10416 case V2SImode:
10417 return true;
10419 case V2SFmode:
10420 return true;
10422 default:
10423 return false;
10427 /* Implement the FUNCTION_PROFILER macro. */
10429 void
10430 ia64_output_function_profiler (FILE *file, int labelno)
10432 bool indirect_call;
10434 /* If the function needs a static chain and the static chain
10435 register is r15, we use an indirect call so as to bypass
10436 the PLT stub in case the executable is dynamically linked,
10437 because the stub clobbers r15 as per 5.3.6 of the psABI.
10438 We don't need to do that in non canonical PIC mode. */
10440 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
10442 gcc_assert (STATIC_CHAIN_REGNUM == 15);
10443 indirect_call = true;
10445 else
10446 indirect_call = false;
10448 if (TARGET_GNU_AS)
10449 fputs ("\t.prologue 4, r40\n", file);
10450 else
10451 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
10452 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
10454 if (NO_PROFILE_COUNTERS)
10455 fputs ("\tmov out3 = r0\n", file);
10456 else
10458 char buf[20];
10459 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10461 if (TARGET_AUTO_PIC)
10462 fputs ("\tmovl out3 = @gprel(", file);
10463 else
10464 fputs ("\taddl out3 = @ltoff(", file);
10465 assemble_name (file, buf);
10466 if (TARGET_AUTO_PIC)
10467 fputs (")\n", file);
10468 else
10469 fputs ("), r1\n", file);
10472 if (indirect_call)
10473 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
10474 fputs ("\t;;\n", file);
10476 fputs ("\t.save rp, r42\n", file);
10477 fputs ("\tmov out2 = b0\n", file);
10478 if (indirect_call)
10479 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
10480 fputs ("\t.body\n", file);
10481 fputs ("\tmov out1 = r1\n", file);
10482 if (indirect_call)
10484 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
10485 fputs ("\tmov b6 = r16\n", file);
10486 fputs ("\tld8 r1 = [r14]\n", file);
10487 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
10489 else
10490 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
10493 static GTY(()) rtx mcount_func_rtx;
10494 static rtx
10495 gen_mcount_func_rtx (void)
10497 if (!mcount_func_rtx)
10498 mcount_func_rtx = init_one_libfunc ("_mcount");
10499 return mcount_func_rtx;
10502 void
10503 ia64_profile_hook (int labelno)
10505 rtx label, ip;
10507 if (NO_PROFILE_COUNTERS)
10508 label = const0_rtx;
10509 else
10511 char buf[30];
10512 const char *label_name;
10513 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10514 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
10515 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
10516 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
10518 ip = gen_reg_rtx (Pmode);
10519 emit_insn (gen_ip_value (ip));
10520 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
10521 VOIDmode, 3,
10522 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
10523 ip, Pmode,
10524 label, Pmode);
10527 /* Return the mangling of TYPE if it is an extended fundamental type. */
10529 static const char *
10530 ia64_mangle_type (const_tree type)
10532 type = TYPE_MAIN_VARIANT (type);
10534 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
10535 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
10536 return NULL;
10538 /* On HP-UX, "long double" is mangled as "e" so __float128 is
10539 mangled as "e". */
10540 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
10541 return "g";
10542 /* On HP-UX, "e" is not available as a mangling of __float80 so use
10543 an extended mangling. Elsewhere, "e" is available since long
10544 double is 80 bits. */
10545 if (TYPE_MODE (type) == XFmode)
10546 return TARGET_HPUX ? "u9__float80" : "e";
10547 if (TYPE_MODE (type) == RFmode)
10548 return "u7__fpreg";
10549 return NULL;
10552 /* Return the diagnostic message string if conversion from FROMTYPE to
10553 TOTYPE is not allowed, NULL otherwise. */
10554 static const char *
10555 ia64_invalid_conversion (const_tree fromtype, const_tree totype)
10557 /* Reject nontrivial conversion to or from __fpreg. */
10558 if (TYPE_MODE (fromtype) == RFmode
10559 && TYPE_MODE (totype) != RFmode
10560 && TYPE_MODE (totype) != VOIDmode)
10561 return N_("invalid conversion from %<__fpreg%>");
10562 if (TYPE_MODE (totype) == RFmode
10563 && TYPE_MODE (fromtype) != RFmode)
10564 return N_("invalid conversion to %<__fpreg%>");
10565 return NULL;
10568 /* Return the diagnostic message string if the unary operation OP is
10569 not permitted on TYPE, NULL otherwise. */
10570 static const char *
10571 ia64_invalid_unary_op (int op, const_tree type)
10573 /* Reject operations on __fpreg other than unary + or &. */
10574 if (TYPE_MODE (type) == RFmode
10575 && op != CONVERT_EXPR
10576 && op != ADDR_EXPR)
10577 return N_("invalid operation on %<__fpreg%>");
10578 return NULL;
10581 /* Return the diagnostic message string if the binary operation OP is
10582 not permitted on TYPE1 and TYPE2, NULL otherwise. */
10583 static const char *
10584 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2)
10586 /* Reject operations on __fpreg. */
10587 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
10588 return N_("invalid operation on %<__fpreg%>");
10589 return NULL;
10592 /* Implement overriding of the optimization options. */
10593 void
10594 ia64_optimization_options (int level ATTRIBUTE_UNUSED,
10595 int size ATTRIBUTE_UNUSED)
10597 /* Let the scheduler form additional regions. */
10598 set_param_value ("max-sched-extend-regions-iters", 2);
10600 /* Set the default values for cache-related parameters. */
10601 set_param_value ("simultaneous-prefetches", 6);
10602 set_param_value ("l1-cache-line-size", 32);
10604 set_param_value("sched-mem-true-dep-cost", 4);
10607 /* HP-UX version_id attribute.
10608 For object foo, if the version_id is set to 1234 put out an alias
10609 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
10610 other than an alias statement because it is an illegal symbol name. */
10612 static tree
10613 ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED,
10614 tree name ATTRIBUTE_UNUSED,
10615 tree args,
10616 int flags ATTRIBUTE_UNUSED,
10617 bool *no_add_attrs)
10619 tree arg = TREE_VALUE (args);
10621 if (TREE_CODE (arg) != STRING_CST)
10623 error("version attribute is not a string");
10624 *no_add_attrs = true;
10625 return NULL_TREE;
10627 return NULL_TREE;
10630 /* Target hook for c_mode_for_suffix. */
10632 static enum machine_mode
10633 ia64_c_mode_for_suffix (char suffix)
10635 if (suffix == 'q')
10636 return TFmode;
10637 if (suffix == 'w')
10638 return XFmode;
10640 return VOIDmode;
10643 static enum machine_mode
10644 ia64_promote_function_mode (const_tree type,
10645 enum machine_mode mode,
10646 int *punsignedp,
10647 const_tree funtype,
10648 int for_return)
10650 /* Special processing required for OpenVMS ... */
10652 if (!TARGET_ABI_OPEN_VMS)
10653 return default_promote_function_mode(type, mode, punsignedp, funtype,
10654 for_return);
10656 /* HP OpenVMS Calling Standard dated June, 2004, that describes
10657 HP OpenVMS I64 Version 8.2EFT,
10658 chapter 4 "OpenVMS I64 Conventions"
10659 section 4.7 "Procedure Linkage"
10660 subsection 4.7.5.2, "Normal Register Parameters"
10662 "Unsigned integral (except unsigned 32-bit), set, and VAX floating-point
10663 values passed in registers are zero-filled; signed integral values as
10664 well as unsigned 32-bit integral values are sign-extended to 64 bits.
10665 For all other types passed in the general registers, unused bits are
10666 undefined." */
10668 if (!AGGREGATE_TYPE_P (type)
10669 && GET_MODE_CLASS (mode) == MODE_INT
10670 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
10672 if (mode == SImode)
10673 *punsignedp = 0;
10674 return DImode;
10676 else
10677 return promote_mode (type, mode, punsignedp);
10680 static GTY(()) rtx ia64_dconst_0_5_rtx;
10683 ia64_dconst_0_5 (void)
10685 if (! ia64_dconst_0_5_rtx)
10687 REAL_VALUE_TYPE rv;
10688 real_from_string (&rv, "0.5");
10689 ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode);
10691 return ia64_dconst_0_5_rtx;
10694 static GTY(()) rtx ia64_dconst_0_375_rtx;
10697 ia64_dconst_0_375 (void)
10699 if (! ia64_dconst_0_375_rtx)
10701 REAL_VALUE_TYPE rv;
10702 real_from_string (&rv, "0.375");
10703 ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode);
10705 return ia64_dconst_0_375_rtx;
10709 #include "gt-ia64.h"