1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_register_constraint "k" "STACK_REG"
22 "@internal The stack register.")
24 (define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
25 "@internal Registers suitable for an indirect tail call")
27 (define_register_constraint "w" "FP_REGS"
28 "Floating point and SIMD vector registers.")
30 (define_register_constraint "Upa" "PR_REGS"
31 "SVE predicate registers p0 - p15.")
33 (define_register_constraint "Upl" "PR_LO_REGS"
34 "SVE predicate registers p0 - p7.")
36 (define_register_constraint "x" "FP_LO_REGS"
37 "Floating point and SIMD vector registers V0 - V15.")
39 (define_constraint "I"
40 "A constant that can be used with an ADD operation."
41 (and (match_code "const_int")
42 (match_test "aarch64_uimm12_shift (ival)")))
44 (define_constraint "Uaa"
45 "@internal A constant that matches two uses of add instructions."
46 (and (match_code "const_int")
47 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
49 (define_constraint "Uav"
51 A constraint that matches a VG-based constant that can be added by
52 a single ADDVL or ADDPL."
53 (match_operand 0 "aarch64_sve_addvl_addpl_immediate"))
55 (define_constraint "Uat"
57 A constraint that matches a VG-based constant that can be added by
58 using multiple instructions, with one temporary register."
59 (match_operand 0 "aarch64_split_add_offset_immediate"))
61 (define_constraint "J"
62 "A constant that can be used with a SUB operation (once negated)."
63 (and (match_code "const_int")
64 (match_test "aarch64_uimm12_shift (-ival)")))
66 ;; We can't use the mode of a CONST_INT to determine the context in
67 ;; which it is being used, so we must have a separate constraint for
70 (define_constraint "K"
71 "A constant that can be used with a 32-bit logical operation."
72 (and (match_code "const_int")
73 (match_test "aarch64_bitmask_imm (ival, SImode)")))
75 (define_constraint "L"
76 "A constant that can be used with a 64-bit logical operation."
77 (and (match_code "const_int")
78 (match_test "aarch64_bitmask_imm (ival, DImode)")))
80 (define_constraint "M"
81 "A constant that can be used with a 32-bit MOV immediate operation."
82 (and (match_code "const_int")
83 (match_test "aarch64_move_imm (ival, SImode)")))
85 (define_constraint "N"
86 "A constant that can be used with a 64-bit MOV immediate operation."
87 (and (match_code "const_int")
88 (match_test "aarch64_move_imm (ival, DImode)")))
90 (define_constraint "Uti"
91 "A constant that can be used with a 128-bit MOV immediate operation."
92 (and (ior (match_code "const_int")
93 (match_code "const_wide_int"))
94 (match_test "aarch64_mov128_immediate (op)")))
96 (define_constraint "UsO"
97 "A constant that can be used with a 32-bit and operation."
98 (and (match_code "const_int")
99 (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
101 (define_constraint "UsP"
102 "A constant that can be used with a 64-bit and operation."
103 (and (match_code "const_int")
104 (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
106 (define_constraint "S"
107 "A constraint that matches an absolute symbolic address."
108 (and (match_code "const,symbol_ref,label_ref")
109 (match_test "aarch64_symbolic_address_p (op)")))
111 (define_constraint "Y"
112 "Floating point constant zero."
113 (and (match_code "const_double")
114 (match_test "aarch64_float_const_zero_rtx_p (op)")))
116 (define_constraint "Z"
117 "Integer constant zero."
118 (match_test "op == const0_rtx"))
120 (define_constraint "Ush"
121 "A constraint that matches an absolute symbolic address high part."
122 (and (match_code "high")
123 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
125 (define_constraint "Usa"
127 A constraint that matches an absolute symbolic address that can be
128 loaded by a single ADR."
129 (and (match_code "const,symbol_ref,label_ref")
130 (match_test "aarch64_symbolic_address_p (op)")
131 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
133 (define_constraint "Uss"
135 A constraint that matches an immediate shift constant in SImode."
136 (and (match_code "const_int")
137 (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
139 (define_constraint "Usn"
140 "A constant that can be used with a CCMN operation (once negated)."
141 (and (match_code "const_int")
142 (match_test "IN_RANGE (ival, -31, 0)")))
144 (define_constraint "Usd"
146 A constraint that matches an immediate shift constant in DImode."
147 (and (match_code "const_int")
148 (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
150 (define_constraint "Usf"
151 "@internal Usf is a symbol reference under the context where plt stub allowed."
152 (and (match_code "symbol_ref")
153 (match_test "!(aarch64_is_noplt_call_p (op)
154 || aarch64_is_long_call_p (op))")))
156 (define_constraint "UsM"
158 A constraint that matches the immediate constant -1."
159 (match_test "op == constm1_rtx"))
161 (define_constraint "Usv"
163 A constraint that matches a VG-based constant that can be loaded by
165 (match_operand 0 "aarch64_sve_cnt_immediate"))
167 (define_constraint "Usi"
169 A constraint that matches an immediate operand valid for
170 the SVE INDEX instruction."
171 (match_operand 0 "aarch64_sve_index_immediate"))
173 (define_constraint "Ui1"
175 A constraint that matches the immediate constant +1."
176 (match_test "op == const1_rtx"))
178 (define_constraint "Ui2"
180 A constraint that matches the integers 0...3."
181 (and (match_code "const_int")
182 (match_test "(unsigned HOST_WIDE_INT) ival <= 3")))
184 (define_constraint "Ui3"
186 A constraint that matches the integers 0...4."
187 (and (match_code "const_int")
188 (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
190 (define_constraint "Ui7"
192 A constraint that matches the integers 0...7."
193 (and (match_code "const_int")
194 (match_test "(unsigned HOST_WIDE_INT) ival <= 7")))
196 (define_constraint "Up3"
198 A constraint that matches the integers 2^(0...4)."
199 (and (match_code "const_int")
200 (match_test "(unsigned) exact_log2 (ival) <= 4")))
202 (define_memory_constraint "Q"
203 "A memory address which uses a single base register with no offset."
204 (and (match_code "mem")
205 (match_test "REG_P (XEXP (op, 0))")))
207 (define_memory_constraint "Umq"
209 A memory address which uses a base register with an offset small enough for
210 a load/store pair operation in DI mode."
211 (and (match_code "mem")
212 (match_test "aarch64_legitimate_address_p (DImode, XEXP (op, 0), false,
213 ADDR_QUERY_LDP_STP)")))
215 (define_memory_constraint "Ump"
217 A memory address suitable for a load/store pair operation."
218 (and (match_code "mem")
219 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
220 true, ADDR_QUERY_LDP_STP)")))
222 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
223 ;; as a 128-bit vec_concat.
224 (define_memory_constraint "Uml"
226 A memory address suitable for a load/store pair operation."
227 (and (match_code "mem")
228 (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1,
229 ADDR_QUERY_LDP_STP)")))
231 (define_memory_constraint "Utr"
233 An address valid for SVE LDR and STR instructions (as distinct from
234 LD[1234] and ST[1234] patterns)."
235 (and (match_code "mem")
236 (match_test "aarch64_sve_ldr_operand_p (op)")))
238 (define_memory_constraint "Utv"
240 An address valid for loading/storing opaque structure
241 types wider than TImode."
242 (and (match_code "mem")
243 (match_test "aarch64_simd_mem_operand_p (op)")))
245 (define_memory_constraint "Utq"
247 An address valid for loading or storing a 128-bit AdvSIMD register"
248 (and (match_code "mem")
249 (match_test "aarch64_legitimate_address_p (V2DImode,
252 (define_memory_constraint "Uty"
254 An address valid for SVE LD1Rs."
255 (and (match_code "mem")
256 (match_test "aarch64_sve_ld1r_operand_p (op)")))
258 (define_memory_constraint "Utx"
260 An address valid for SVE structure mov patterns (as distinct from
261 LD[234] and ST[234] patterns)."
262 (match_operand 0 "aarch64_sve_struct_memory_operand"))
264 (define_constraint "Ufc"
265 "A floating point constant which can be used with an\
266 FMOV immediate operation."
267 (and (match_code "const_double")
268 (match_test "aarch64_float_const_representable_p (op)")))
270 (define_constraint "Uvi"
271 "A floating point constant which can be used with a\
272 MOVI immediate operation."
273 (and (match_code "const_double")
274 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
276 (define_constraint "Do"
278 A constraint that matches vector of immediates for orr."
279 (and (match_code "const_vector")
280 (match_test "aarch64_simd_valid_immediate (op, NULL,
281 AARCH64_CHECK_ORR)")))
283 (define_constraint "Db"
285 A constraint that matches vector of immediates for bic."
286 (and (match_code "const_vector")
287 (match_test "aarch64_simd_valid_immediate (op, NULL,
288 AARCH64_CHECK_BIC)")))
290 (define_constraint "Dn"
292 A constraint that matches vector of immediates."
293 (and (match_code "const,const_vector")
294 (match_test "aarch64_simd_valid_immediate (op, NULL)")))
296 (define_constraint "Dh"
298 A constraint that matches an immediate operand valid for\
299 AdvSIMD scalar move in HImode."
300 (and (match_code "const_int")
301 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
304 (define_constraint "Dq"
306 A constraint that matches an immediate operand valid for\
307 AdvSIMD scalar move in QImode."
308 (and (match_code "const_int")
309 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
312 (define_constraint "Dl"
314 A constraint that matches vector of immediates for left shifts."
315 (and (match_code "const,const_vector")
316 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
319 (define_constraint "Dr"
321 A constraint that matches vector of immediates for right shifts."
322 (and (match_code "const,const_vector")
323 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
325 (define_constraint "Dz"
327 A constraint that matches a vector of immediate zero."
328 (and (match_code "const,const_vector")
329 (match_test "op == CONST0_RTX (GET_MODE (op))")))
331 (define_constraint "Dm"
333 A constraint that matches a vector of immediate minus one."
334 (and (match_code "const,const_vector")
335 (match_test "op == CONST1_RTX (GET_MODE (op))")))
337 (define_constraint "Dd"
339 A constraint that matches an integer immediate operand valid\
340 for AdvSIMD scalar operations in DImode."
341 (and (match_code "const_int")
342 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
344 (define_constraint "Ds"
346 A constraint that matches an integer immediate operand valid\
347 for AdvSIMD scalar operations in SImode."
348 (and (match_code "const_int")
349 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
351 (define_address_constraint "Dp"
353 An address valid for a prefetch instruction."
354 (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))
356 (define_constraint "vsa"
358 A constraint that matches an immediate operand valid for SVE
359 arithmetic instructions."
360 (match_operand 0 "aarch64_sve_arith_immediate"))
362 (define_constraint "vsc"
364 A constraint that matches a signed immediate operand valid for SVE
366 (match_operand 0 "aarch64_sve_cmp_vsc_immediate"))
368 (define_constraint "vsd"
370 A constraint that matches an unsigned immediate operand valid for SVE
372 (match_operand 0 "aarch64_sve_cmp_vsd_immediate"))
374 (define_constraint "vsi"
376 A constraint that matches a vector count operand valid for SVE INC and
378 (match_operand 0 "aarch64_sve_inc_dec_immediate"))
380 (define_constraint "vsn"
382 A constraint that matches an immediate operand whose negative
383 is valid for SVE SUB instructions."
384 (match_operand 0 "aarch64_sve_sub_arith_immediate"))
386 (define_constraint "vsl"
388 A constraint that matches an immediate operand valid for SVE logical
390 (match_operand 0 "aarch64_sve_logical_immediate"))
392 (define_constraint "vsm"
394 A constraint that matches an immediate operand valid for SVE MUL
396 (match_operand 0 "aarch64_sve_mul_immediate"))
398 (define_constraint "vsA"
400 A constraint that matches an immediate operand valid for SVE FADD
401 and FSUB operations."
402 (match_operand 0 "aarch64_sve_float_arith_immediate"))
404 (define_constraint "vsM"
406 A constraint that matches an imediate operand valid for SVE FMUL
408 (match_operand 0 "aarch64_sve_float_mul_immediate"))
410 (define_constraint "vsN"
412 A constraint that matches the negative of vsA"
413 (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate"))