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* Merge from mainline
[official-gcc.git] / gcc / config / s390 / s390.c
blobf1b83621b5fc0a11980f31712861cd49b90a2ed7
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 02110-1301, USA. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "tm_p.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "except.h"
40 #include "function.h"
41 #include "recog.h"
42 #include "expr.h"
43 #include "reload.h"
44 #include "toplev.h"
45 #include "basic-block.h"
46 #include "integrate.h"
47 #include "ggc.h"
48 #include "target.h"
49 #include "target-def.h"
50 #include "debug.h"
51 #include "langhooks.h"
52 #include "optabs.h"
53 #include "tree-gimple.h"
54
55
56 /* Define the specific costs for a given cpu. */
57
58 struct processor_costs
59 {
60 /* multiplication */
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
74 /* square root */
75 const int sqdbr; /* cost of square root in DFmode. */
76 const int sqebr; /* cost of square root in SFmode. */
77 /* multiply and add */
78 const int madbr; /* cost of multiply and add in DFmode. */
79 const int maebr; /* cost of multiply and add in SFmode. */
80 /* division */
81 const int ddbr;
82 const int ddr;
83 const int debr;
84 const int der;
85 const int dlgr;
86 const int dlr;
87 const int dr;
88 const int dsgfr;
89 const int dsgr;
90 };
91
92 const struct processor_costs *s390_cost;
93
94 static const
95 struct processor_costs z900_cost =
96 {
97 COSTS_N_INSNS (5), /* M */
98 COSTS_N_INSNS (10), /* MGHI */
99 COSTS_N_INSNS (5), /* MH */
100 COSTS_N_INSNS (4), /* MHI */
101 COSTS_N_INSNS (5), /* ML */
102 COSTS_N_INSNS (5), /* MR */
103 COSTS_N_INSNS (4), /* MS */
104 COSTS_N_INSNS (15), /* MSG */
105 COSTS_N_INSNS (7), /* MSGF */
106 COSTS_N_INSNS (7), /* MSGFR */
107 COSTS_N_INSNS (10), /* MSGR */
108 COSTS_N_INSNS (4), /* MSR */
109 COSTS_N_INSNS (7), /* multiplication in DFmode */
110 COSTS_N_INSNS (44), /* SQDBR */
111 COSTS_N_INSNS (35), /* SQEBR */
112 COSTS_N_INSNS (18), /* MADBR */
113 COSTS_N_INSNS (13), /* MAEBR */
114 COSTS_N_INSNS (30), /* DDBR */
115 COSTS_N_INSNS (30), /* DDR */
116 COSTS_N_INSNS (27), /* DEBR */
117 COSTS_N_INSNS (26), /* DER */
118 COSTS_N_INSNS (220), /* DLGR */
119 COSTS_N_INSNS (34), /* DLR */
120 COSTS_N_INSNS (34), /* DR */
121 COSTS_N_INSNS (32), /* DSGFR */
122 COSTS_N_INSNS (32), /* DSGR */
123 };
124
125 static const
126 struct processor_costs z990_cost =
127 {
128 COSTS_N_INSNS (4), /* M */
129 COSTS_N_INSNS (2), /* MGHI */
130 COSTS_N_INSNS (2), /* MH */
131 COSTS_N_INSNS (2), /* MHI */
132 COSTS_N_INSNS (4), /* ML */
133 COSTS_N_INSNS (4), /* MR */
134 COSTS_N_INSNS (5), /* MS */
135 COSTS_N_INSNS (6), /* MSG */
136 COSTS_N_INSNS (4), /* MSGF */
137 COSTS_N_INSNS (4), /* MSGFR */
138 COSTS_N_INSNS (4), /* MSGR */
139 COSTS_N_INSNS (4), /* MSR */
140 COSTS_N_INSNS (1), /* multiplication in DFmode */
141 COSTS_N_INSNS (66), /* SQDBR */
142 COSTS_N_INSNS (38), /* SQEBR */
143 COSTS_N_INSNS (1), /* MADBR */
144 COSTS_N_INSNS (1), /* MAEBR */
145 COSTS_N_INSNS (40), /* DDBR */
146 COSTS_N_INSNS (44), /* DDR */
147 COSTS_N_INSNS (26), /* DDBR */
148 COSTS_N_INSNS (28), /* DER */
149 COSTS_N_INSNS (176), /* DLGR */
150 COSTS_N_INSNS (31), /* DLR */
151 COSTS_N_INSNS (31), /* DR */
152 COSTS_N_INSNS (31), /* DSGFR */
153 COSTS_N_INSNS (31), /* DSGR */
154 };
155
156 static const
157 struct processor_costs z9_109_cost =
158 {
159 COSTS_N_INSNS (4), /* M */
160 COSTS_N_INSNS (2), /* MGHI */
161 COSTS_N_INSNS (2), /* MH */
162 COSTS_N_INSNS (2), /* MHI */
163 COSTS_N_INSNS (4), /* ML */
164 COSTS_N_INSNS (4), /* MR */
165 COSTS_N_INSNS (5), /* MS */
166 COSTS_N_INSNS (6), /* MSG */
167 COSTS_N_INSNS (4), /* MSGF */
168 COSTS_N_INSNS (4), /* MSGFR */
169 COSTS_N_INSNS (4), /* MSGR */
170 COSTS_N_INSNS (4), /* MSR */
171 COSTS_N_INSNS (1), /* multiplication in DFmode */
172 COSTS_N_INSNS (66), /* SQDBR */
173 COSTS_N_INSNS (38), /* SQEBR */
174 COSTS_N_INSNS (1), /* MADBR */
175 COSTS_N_INSNS (1), /* MAEBR */
176 COSTS_N_INSNS (40), /* DDBR */
177 COSTS_N_INSNS (37), /* DDR */
178 COSTS_N_INSNS (26), /* DDBR */
179 COSTS_N_INSNS (28), /* DER */
180 COSTS_N_INSNS (30), /* DLGR */
181 COSTS_N_INSNS (23), /* DLR */
182 COSTS_N_INSNS (23), /* DR */
183 COSTS_N_INSNS (24), /* DSGFR */
184 COSTS_N_INSNS (24), /* DSGR */
185 };
186
187 extern int reload_completed;
188
189 /* Save information from a "cmpxx" operation until the branch or scc is
190 emitted. */
191 rtx s390_compare_op0, s390_compare_op1;
192
193 /* Save the result of a compare_and_swap until the branch or scc is
194 emitted. */
195 rtx s390_compare_emitted = NULL_RTX;
196
197 /* Structure used to hold the components of a S/390 memory
198 address. A legitimate address on S/390 is of the general
199 form
200 base + index + displacement
201 where any of the components is optional.
202
203 base and index are registers of the class ADDR_REGS,
204 displacement is an unsigned 12-bit immediate constant. */
205
206 struct s390_address
207 {
208 rtx base;
209 rtx indx;
210 rtx disp;
211 bool pointer;
212 bool literal_pool;
213 };
214
215 /* Which cpu are we tuning for. */
216 enum processor_type s390_tune = PROCESSOR_max;
217 enum processor_flags s390_tune_flags;
218 /* Which instruction set architecture to use. */
219 enum processor_type s390_arch;
220 enum processor_flags s390_arch_flags;
221
222 HOST_WIDE_INT s390_warn_framesize = 0;
223 HOST_WIDE_INT s390_stack_size = 0;
224 HOST_WIDE_INT s390_stack_guard = 0;
225
226 /* The following structure is embedded in the machine
227 specific part of struct function. */
228
229 struct s390_frame_layout GTY (())
230 {
231 /* Offset within stack frame. */
232 HOST_WIDE_INT gprs_offset;
233 HOST_WIDE_INT f0_offset;
234 HOST_WIDE_INT f4_offset;
235 HOST_WIDE_INT f8_offset;
236 HOST_WIDE_INT backchain_offset;
237
238 /* Number of first and last gpr where slots in the register
239 save area are reserved for. */
240 int first_save_gpr_slot;
241 int last_save_gpr_slot;
242
243 /* Number of first and last gpr to be saved, restored. */
244 int first_save_gpr;
245 int first_restore_gpr;
246 int last_save_gpr;
247 int last_restore_gpr;
248
249 /* Bits standing for floating point registers. Set, if the
250 respective register has to be saved. Starting with reg 16 (f0)
251 at the rightmost bit.
252 Bit 15 - 8 7 6 5 4 3 2 1 0
253 fpr 15 - 8 7 5 3 1 6 4 2 0
254 reg 31 - 24 23 22 21 20 19 18 17 16 */
255 unsigned int fpr_bitmap;
256
257 /* Number of floating point registers f8-f15 which must be saved. */
258 int high_fprs;
259
260 /* Set if return address needs to be saved.
261 This flag is set by s390_return_addr_rtx if it could not use
262 the initial value of r14 and therefore depends on r14 saved
263 to the stack. */
264 bool save_return_addr_p;
265
266 /* Size of stack frame. */
267 HOST_WIDE_INT frame_size;
268 };
269
270 /* Define the structure for the machine field in struct function. */
271
272 struct machine_function GTY(())
273 {
274 struct s390_frame_layout frame_layout;
275
276 /* Literal pool base register. */
277 rtx base_reg;
278
279 /* True if we may need to perform branch splitting. */
280 bool split_branches_pending_p;
281
282 /* Some local-dynamic TLS symbol name. */
283 const char *some_ld_name;
284
285 bool has_landing_pad_p;
286 };
287
288 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
289
290 #define cfun_frame_layout (cfun->machine->frame_layout)
291 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
292 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
293 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
294 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
295 (1 << (BITNUM)))
296 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
297 (1 << (BITNUM))))
298
299 /* Number of GPRs and FPRs used for argument passing. */
300 #define GP_ARG_NUM_REG 5
301 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
302
303 /* A couple of shortcuts. */
304 #define CONST_OK_FOR_J(x) \
305 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
306 #define CONST_OK_FOR_K(x) \
307 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
308 #define CONST_OK_FOR_Os(x) \
309 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
310 #define CONST_OK_FOR_Op(x) \
311 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
312 #define CONST_OK_FOR_On(x) \
313 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
314
315 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
316
317 void
318 s390_set_has_landing_pad_p (bool value)
319 {
320 cfun->machine->has_landing_pad_p = value;
321 }
322
323 /* If two condition code modes are compatible, return a condition code
324 mode which is compatible with both. Otherwise, return
325 VOIDmode. */
326
327 static enum machine_mode
328 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
329 {
330 if (m1 == m2)
331 return m1;
332
333 switch (m1)
334 {
335 case CCZmode:
336 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
337 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
338 return m2;
339 return VOIDmode;
340
341 case CCSmode:
342 case CCUmode:
343 case CCTmode:
344 case CCSRmode:
345 case CCURmode:
346 case CCZ1mode:
347 if (m2 == CCZmode)
348 return m1;
349
350 return VOIDmode;
351
352 default:
353 return VOIDmode;
354 }
355 return VOIDmode;
356 }
357
358 /* Return true if SET either doesn't set the CC register, or else
359 the source and destination have matching CC modes and that
360 CC mode is at least as constrained as REQ_MODE. */
361
362 static bool
363 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
364 {
365 enum machine_mode set_mode;
366
367 gcc_assert (GET_CODE (set) == SET);
368
369 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
370 return 1;
371
372 set_mode = GET_MODE (SET_DEST (set));
373 switch (set_mode)
374 {
375 case CCSmode:
376 case CCSRmode:
377 case CCUmode:
378 case CCURmode:
379 case CCLmode:
380 case CCL1mode:
381 case CCL2mode:
382 case CCL3mode:
383 case CCT1mode:
384 case CCT2mode:
385 case CCT3mode:
386 if (req_mode != set_mode)
387 return 0;
388 break;
389
390 case CCZmode:
391 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
392 && req_mode != CCSRmode && req_mode != CCURmode)
393 return 0;
394 break;
395
396 case CCAPmode:
397 case CCANmode:
398 if (req_mode != CCAmode)
399 return 0;
400 break;
401
402 default:
403 gcc_unreachable ();
404 }
405
406 return (GET_MODE (SET_SRC (set)) == set_mode);
407 }
408
409 /* Return true if every SET in INSN that sets the CC register
410 has source and destination with matching CC modes and that
411 CC mode is at least as constrained as REQ_MODE.
412 If REQ_MODE is VOIDmode, always return false. */
413
414 bool
415 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
416 {
417 int i;
418
419 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
420 if (req_mode == VOIDmode)
421 return false;
422
423 if (GET_CODE (PATTERN (insn)) == SET)
424 return s390_match_ccmode_set (PATTERN (insn), req_mode);
425
426 if (GET_CODE (PATTERN (insn)) == PARALLEL)
427 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
428 {
429 rtx set = XVECEXP (PATTERN (insn), 0, i);
430 if (GET_CODE (set) == SET)
431 if (!s390_match_ccmode_set (set, req_mode))
432 return false;
433 }
434
435 return true;
436 }
437
438 /* If a test-under-mask instruction can be used to implement
439 (compare (and ... OP1) OP2), return the CC mode required
440 to do that. Otherwise, return VOIDmode.
441 MIXED is true if the instruction can distinguish between
442 CC1 and CC2 for mixed selected bits (TMxx), it is false
443 if the instruction cannot (TM). */
444
445 enum machine_mode
446 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
447 {
448 int bit0, bit1;
449
450 /* ??? Fixme: should work on CONST_DOUBLE as well. */
451 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
452 return VOIDmode;
453
454 /* Selected bits all zero: CC0.
455 e.g.: int a; if ((a & (16 + 128)) == 0) */
456 if (INTVAL (op2) == 0)
457 return CCTmode;
458
459 /* Selected bits all one: CC3.
460 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
461 if (INTVAL (op2) == INTVAL (op1))
462 return CCT3mode;
463
464 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
465 int a;
466 if ((a & (16 + 128)) == 16) -> CCT1
467 if ((a & (16 + 128)) == 128) -> CCT2 */
468 if (mixed)
469 {
470 bit1 = exact_log2 (INTVAL (op2));
471 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
472 if (bit0 != -1 && bit1 != -1)
473 return bit0 > bit1 ? CCT1mode : CCT2mode;
474 }
475
476 return VOIDmode;
477 }
478
479 /* Given a comparison code OP (EQ, NE, etc.) and the operands
480 OP0 and OP1 of a COMPARE, return the mode to be used for the
481 comparison. */
482
483 enum machine_mode
484 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
485 {
486 switch (code)
487 {
488 case EQ:
489 case NE:
490 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
491 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
492 return CCAPmode;
493 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
494 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
495 return CCAPmode;
496 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
497 || GET_CODE (op1) == NEG)
498 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
499 return CCLmode;
500
501 if (GET_CODE (op0) == AND)
502 {
503 /* Check whether we can potentially do it via TM. */
504 enum machine_mode ccmode;
505 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
506 if (ccmode != VOIDmode)
507 {
508 /* Relax CCTmode to CCZmode to allow fall-back to AND
509 if that turns out to be beneficial. */
510 return ccmode == CCTmode ? CCZmode : ccmode;
511 }
512 }
513
514 if (register_operand (op0, HImode)
515 && GET_CODE (op1) == CONST_INT
516 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
517 return CCT3mode;
518 if (register_operand (op0, QImode)
519 && GET_CODE (op1) == CONST_INT
520 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
521 return CCT3mode;
522
523 return CCZmode;
524
525 case LE:
526 case LT:
527 case GE:
528 case GT:
529 /* The only overflow condition of NEG and ABS happens when
530 -INT_MAX is used as parameter, which stays negative. So
531 we have an overflow from a positive value to a negative.
532 Using CCAP mode the resulting cc can be used for comparisons. */
533 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
534 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
535 return CCAPmode;
536
537 /* If constants are involved in an add instruction it is possible to use
538 the resulting cc for comparisons with zero. Knowing the sign of the
539 constant the overflow behavior gets predictable. e.g.:
540 int a, b; if ((b = a + c) > 0)
541 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
542 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
543 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
544 {
545 if (INTVAL (XEXP((op0), 1)) < 0)
546 return CCANmode;
547 else
548 return CCAPmode;
549 }
550 /* Fall through. */
551 case UNORDERED:
552 case ORDERED:
553 case UNEQ:
554 case UNLE:
555 case UNLT:
556 case UNGE:
557 case UNGT:
558 case LTGT:
559 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
560 && GET_CODE (op1) != CONST_INT)
561 return CCSRmode;
562 return CCSmode;
563
564 case LTU:
565 case GEU:
566 if (GET_CODE (op0) == PLUS
567 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
568 return CCL1mode;
569
570 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
571 && GET_CODE (op1) != CONST_INT)
572 return CCURmode;
573 return CCUmode;
574
575 case LEU:
576 case GTU:
577 if (GET_CODE (op0) == MINUS
578 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
579 return CCL2mode;
580
581 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
582 && GET_CODE (op1) != CONST_INT)
583 return CCURmode;
584 return CCUmode;
585
586 default:
587 gcc_unreachable ();
588 }
589 }
590
591 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
592 that we can implement more efficiently. */
593
594 void
595 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
596 {
597 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
598 if ((*code == EQ || *code == NE)
599 && *op1 == const0_rtx
600 && GET_CODE (*op0) == ZERO_EXTRACT
601 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
602 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
603 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
604 {
605 rtx inner = XEXP (*op0, 0);
606 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
607 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
608 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
609
610 if (len > 0 && len < modesize
611 && pos >= 0 && pos + len <= modesize
612 && modesize <= HOST_BITS_PER_WIDE_INT)
613 {
614 unsigned HOST_WIDE_INT block;
615 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
616 block <<= modesize - pos - len;
617
618 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
619 gen_int_mode (block, GET_MODE (inner)));
620 }
621 }
622
623 /* Narrow AND of memory against immediate to enable TM. */
624 if ((*code == EQ || *code == NE)
625 && *op1 == const0_rtx
626 && GET_CODE (*op0) == AND
627 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
628 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
629 {
630 rtx inner = XEXP (*op0, 0);
631 rtx mask = XEXP (*op0, 1);
632
633 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
634 if (GET_CODE (inner) == SUBREG
635 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
636 && (GET_MODE_SIZE (GET_MODE (inner))
637 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
638 && ((INTVAL (mask)
639 & GET_MODE_MASK (GET_MODE (inner))
640 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
641 == 0))
642 inner = SUBREG_REG (inner);
643
644 /* Do not change volatile MEMs. */
645 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
646 {
647 int part = s390_single_part (XEXP (*op0, 1),
648 GET_MODE (inner), QImode, 0);
649 if (part >= 0)
650 {
651 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
652 inner = adjust_address_nv (inner, QImode, part);
653 *op0 = gen_rtx_AND (QImode, inner, mask);
654 }
655 }
656 }
657
658 /* Narrow comparisons against 0xffff to HImode if possible. */
659 if ((*code == EQ || *code == NE)
660 && GET_CODE (*op1) == CONST_INT
661 && INTVAL (*op1) == 0xffff
662 && SCALAR_INT_MODE_P (GET_MODE (*op0))
663 && (nonzero_bits (*op0, GET_MODE (*op0))
664 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
665 {
666 *op0 = gen_lowpart (HImode, *op0);
667 *op1 = constm1_rtx;
668 }
669
670
671 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
672 if (GET_CODE (*op0) == UNSPEC
673 && XINT (*op0, 1) == UNSPEC_CMPINT
674 && XVECLEN (*op0, 0) == 1
675 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
676 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
677 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
678 && *op1 == const0_rtx)
679 {
680 enum rtx_code new_code = UNKNOWN;
681 switch (*code)
682 {
683 case EQ: new_code = EQ; break;
684 case NE: new_code = NE; break;
685 case LT: new_code = GTU; break;
686 case GT: new_code = LTU; break;
687 case LE: new_code = GEU; break;
688 case GE: new_code = LEU; break;
689 default: break;
690 }
691
692 if (new_code != UNKNOWN)
693 {
694 *op0 = XVECEXP (*op0, 0, 0);
695 *code = new_code;
696 }
697 }
698
699 /* Simplify cascaded EQ, NE with const0_rtx. */
700 if ((*code == NE || *code == EQ)
701 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
702 && GET_MODE (*op0) == SImode
703 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
704 && REG_P (XEXP (*op0, 0))
705 && XEXP (*op0, 1) == const0_rtx
706 && *op1 == const0_rtx)
707 {
708 if ((*code == EQ && GET_CODE (*op0) == NE)
709 || (*code == NE && GET_CODE (*op0) == EQ))
710 *code = EQ;
711 else
712 *code = NE;
713 *op0 = XEXP (*op0, 0);
714 }
715
716 /* Prefer register over memory as first operand. */
717 if (MEM_P (*op0) && REG_P (*op1))
718 {
719 rtx tem = *op0; *op0 = *op1; *op1 = tem;
720 *code = swap_condition (*code);
721 }
722 }
723
724 /* Emit a compare instruction suitable to implement the comparison
725 OP0 CODE OP1. Return the correct condition RTL to be placed in
726 the IF_THEN_ELSE of the conditional branch testing the result. */
727
728 rtx
729 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
730 {
731 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
732 rtx ret = NULL_RTX;
733
734 /* Do not output a redundant compare instruction if a compare_and_swap
735 pattern already computed the result and the machine modes are compatible. */
736 if (s390_compare_emitted
737 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
738 == GET_MODE (s390_compare_emitted)))
739 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
740 else
741 {
742 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
743
744 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
745 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
746 }
747 s390_compare_emitted = NULL_RTX;
748 return ret;
749 }
750
751 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
752 unconditional jump, else a conditional jump under condition COND. */
753
754 void
755 s390_emit_jump (rtx target, rtx cond)
756 {
757 rtx insn;
758
759 target = gen_rtx_LABEL_REF (VOIDmode, target);
760 if (cond)
761 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
762
763 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
764 emit_jump_insn (insn);
765 }
766
767 /* Return branch condition mask to implement a branch
768 specified by CODE. Return -1 for invalid comparisons. */
769
770 int
771 s390_branch_condition_mask (rtx code)
772 {
773 const int CC0 = 1 << 3;
774 const int CC1 = 1 << 2;
775 const int CC2 = 1 << 1;
776 const int CC3 = 1 << 0;
777
778 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
779 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
780 gcc_assert (XEXP (code, 1) == const0_rtx);
781
782 switch (GET_MODE (XEXP (code, 0)))
783 {
784 case CCZmode:
785 case CCZ1mode:
786 switch (GET_CODE (code))
787 {
788 case EQ: return CC0;
789 case NE: return CC1 | CC2 | CC3;
790 default: return -1;
791 }
792 break;
793
794 case CCT1mode:
795 switch (GET_CODE (code))
796 {
797 case EQ: return CC1;
798 case NE: return CC0 | CC2 | CC3;
799 default: return -1;
800 }
801 break;
802
803 case CCT2mode:
804 switch (GET_CODE (code))
805 {
806 case EQ: return CC2;
807 case NE: return CC0 | CC1 | CC3;
808 default: return -1;
809 }
810 break;
811
812 case CCT3mode:
813 switch (GET_CODE (code))
814 {
815 case EQ: return CC3;
816 case NE: return CC0 | CC1 | CC2;
817 default: return -1;
818 }
819 break;
820
821 case CCLmode:
822 switch (GET_CODE (code))
823 {
824 case EQ: return CC0 | CC2;
825 case NE: return CC1 | CC3;
826 default: return -1;
827 }
828 break;
829
830 case CCL1mode:
831 switch (GET_CODE (code))
832 {
833 case LTU: return CC2 | CC3; /* carry */
834 case GEU: return CC0 | CC1; /* no carry */
835 default: return -1;
836 }
837 break;
838
839 case CCL2mode:
840 switch (GET_CODE (code))
841 {
842 case GTU: return CC0 | CC1; /* borrow */
843 case LEU: return CC2 | CC3; /* no borrow */
844 default: return -1;
845 }
846 break;
847
848 case CCL3mode:
849 switch (GET_CODE (code))
850 {
851 case EQ: return CC0 | CC2;
852 case NE: return CC1 | CC3;
853 case LTU: return CC1;
854 case GTU: return CC3;
855 case LEU: return CC1 | CC2;
856 case GEU: return CC2 | CC3;
857 default: return -1;
858 }
859
860 case CCUmode:
861 switch (GET_CODE (code))
862 {
863 case EQ: return CC0;
864 case NE: return CC1 | CC2 | CC3;
865 case LTU: return CC1;
866 case GTU: return CC2;
867 case LEU: return CC0 | CC1;
868 case GEU: return CC0 | CC2;
869 default: return -1;
870 }
871 break;
872
873 case CCURmode:
874 switch (GET_CODE (code))
875 {
876 case EQ: return CC0;
877 case NE: return CC2 | CC1 | CC3;
878 case LTU: return CC2;
879 case GTU: return CC1;
880 case LEU: return CC0 | CC2;
881 case GEU: return CC0 | CC1;
882 default: return -1;
883 }
884 break;
885
886 case CCAPmode:
887 switch (GET_CODE (code))
888 {
889 case EQ: return CC0;
890 case NE: return CC1 | CC2 | CC3;
891 case LT: return CC1 | CC3;
892 case GT: return CC2;
893 case LE: return CC0 | CC1 | CC3;
894 case GE: return CC0 | CC2;
895 default: return -1;
896 }
897 break;
898
899 case CCANmode:
900 switch (GET_CODE (code))
901 {
902 case EQ: return CC0;
903 case NE: return CC1 | CC2 | CC3;
904 case LT: return CC1;
905 case GT: return CC2 | CC3;
906 case LE: return CC0 | CC1;
907 case GE: return CC0 | CC2 | CC3;
908 default: return -1;
909 }
910 break;
911
912 case CCSmode:
913 switch (GET_CODE (code))
914 {
915 case EQ: return CC0;
916 case NE: return CC1 | CC2 | CC3;
917 case LT: return CC1;
918 case GT: return CC2;
919 case LE: return CC0 | CC1;
920 case GE: return CC0 | CC2;
921 case UNORDERED: return CC3;
922 case ORDERED: return CC0 | CC1 | CC2;
923 case UNEQ: return CC0 | CC3;
924 case UNLT: return CC1 | CC3;
925 case UNGT: return CC2 | CC3;
926 case UNLE: return CC0 | CC1 | CC3;
927 case UNGE: return CC0 | CC2 | CC3;
928 case LTGT: return CC1 | CC2;
929 default: return -1;
930 }
931 break;
932
933 case CCSRmode:
934 switch (GET_CODE (code))
935 {
936 case EQ: return CC0;
937 case NE: return CC2 | CC1 | CC3;
938 case LT: return CC2;
939 case GT: return CC1;
940 case LE: return CC0 | CC2;
941 case GE: return CC0 | CC1;
942 case UNORDERED: return CC3;
943 case ORDERED: return CC0 | CC2 | CC1;
944 case UNEQ: return CC0 | CC3;
945 case UNLT: return CC2 | CC3;
946 case UNGT: return CC1 | CC3;
947 case UNLE: return CC0 | CC2 | CC3;
948 case UNGE: return CC0 | CC1 | CC3;
949 case LTGT: return CC2 | CC1;
950 default: return -1;
951 }
952 break;
953
954 default:
955 return -1;
956 }
957 }
958
959 /* If INV is false, return assembler mnemonic string to implement
960 a branch specified by CODE. If INV is true, return mnemonic
961 for the corresponding inverted branch. */
962
963 static const char *
964 s390_branch_condition_mnemonic (rtx code, int inv)
965 {
966 static const char *const mnemonic[16] =
967 {
968 NULL, "o", "h", "nle",
969 "l", "nhe", "lh", "ne",
970 "e", "nlh", "he", "nl",
971 "le", "nh", "no", NULL
972 };
973
974 int mask = s390_branch_condition_mask (code);
975 gcc_assert (mask >= 0);
976
977 if (inv)
978 mask ^= 15;
979
980 gcc_assert (mask >= 1 && mask <= 14);
981
982 return mnemonic[mask];
983 }
984
985 /* Return the part of op which has a value different from def.
986 The size of the part is determined by mode.
987 Use this function only if you already know that op really
988 contains such a part. */
989
990 unsigned HOST_WIDE_INT
991 s390_extract_part (rtx op, enum machine_mode mode, int def)
992 {
993 unsigned HOST_WIDE_INT value = 0;
994 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
995 int part_bits = GET_MODE_BITSIZE (mode);
996 unsigned HOST_WIDE_INT part_mask
997 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
998 int i;
999
1000 for (i = 0; i < max_parts; i++)
1001 {
1002 if (i == 0)
1003 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1004 else
1005 value >>= part_bits;
1006
1007 if ((value & part_mask) != (def & part_mask))
1008 return value & part_mask;
1009 }
1010
1011 gcc_unreachable ();
1012 }
1013
1014 /* If OP is an integer constant of mode MODE with exactly one
1015 part of mode PART_MODE unequal to DEF, return the number of that
1016 part. Otherwise, return -1. */
1017
1018 int
1019 s390_single_part (rtx op,
1020 enum machine_mode mode,
1021 enum machine_mode part_mode,
1022 int def)
1023 {
1024 unsigned HOST_WIDE_INT value = 0;
1025 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1026 unsigned HOST_WIDE_INT part_mask
1027 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1028 int i, part = -1;
1029
1030 if (GET_CODE (op) != CONST_INT)
1031 return -1;
1032
1033 for (i = 0; i < n_parts; i++)
1034 {
1035 if (i == 0)
1036 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1037 else
1038 value >>= GET_MODE_BITSIZE (part_mode);
1039
1040 if ((value & part_mask) != (def & part_mask))
1041 {
1042 if (part != -1)
1043 return -1;
1044 else
1045 part = i;
1046 }
1047 }
1048 return part == -1 ? -1 : n_parts - 1 - part;
1049 }
1050
1051 /* Check whether we can (and want to) split a double-word
1052 move in mode MODE from SRC to DST into two single-word
1053 moves, moving the subword FIRST_SUBWORD first. */
1054
1055 bool
1056 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1057 {
1058 /* Floating point registers cannot be split. */
1059 if (FP_REG_P (src) || FP_REG_P (dst))
1060 return false;
1061
1062 /* We don't need to split if operands are directly accessible. */
1063 if (s_operand (src, mode) || s_operand (dst, mode))
1064 return false;
1065
1066 /* Non-offsettable memory references cannot be split. */
1067 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1068 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1069 return false;
1070
1071 /* Moving the first subword must not clobber a register
1072 needed to move the second subword. */
1073 if (register_operand (dst, mode))
1074 {
1075 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1076 if (reg_overlap_mentioned_p (subreg, src))
1077 return false;
1078 }
1079
1080 return true;
1081 }
1082
1083 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1084 and [MEM2, MEM2 + SIZE] do overlap and false
1085 otherwise. */
1086
1087 bool
1088 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1089 {
1090 rtx addr1, addr2, addr_delta;
1091 HOST_WIDE_INT delta;
1092
1093 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1094 return true;
1095
1096 if (size == 0)
1097 return false;
1098
1099 addr1 = XEXP (mem1, 0);
1100 addr2 = XEXP (mem2, 0);
1101
1102 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1103
1104 /* This overlapping check is used by peepholes merging memory block operations.
1105 Overlapping operations would otherwise be recognized by the S/390 hardware
1106 and would fall back to a slower implementation. Allowing overlapping
1107 operations would lead to slow code but not to wrong code. Therefore we are
1108 somewhat optimistic if we cannot prove that the memory blocks are
1109 overlapping.
1110 That's why we return false here although this may accept operations on
1111 overlapping memory areas. */
1112 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1113 return false;
1114
1115 delta = INTVAL (addr_delta);
1116
1117 if (delta == 0
1118 || (delta > 0 && delta < size)
1119 || (delta < 0 && -delta < size))
1120 return true;
1121
1122 return false;
1123 }
1124
1125 /* Check whether the address of memory reference MEM2 equals exactly
1126 the address of memory reference MEM1 plus DELTA. Return true if
1127 we can prove this to be the case, false otherwise. */
1128
1129 bool
1130 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1131 {
1132 rtx addr1, addr2, addr_delta;
1133
1134 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1135 return false;
1136
1137 addr1 = XEXP (mem1, 0);
1138 addr2 = XEXP (mem2, 0);
1139
1140 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1141 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1142 return false;
1143
1144 return true;
1145 }
1146
1147 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1148
1149 void
1150 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1151 rtx *operands)
1152 {
1153 enum machine_mode wmode = mode;
1154 rtx dst = operands[0];
1155 rtx src1 = operands[1];
1156 rtx src2 = operands[2];
1157 rtx op, clob, tem;
1158
1159 /* If we cannot handle the operation directly, use a temp register. */
1160 if (!s390_logical_operator_ok_p (operands))
1161 dst = gen_reg_rtx (mode);
1162
1163 /* QImode and HImode patterns make sense only if we have a destination
1164 in memory. Otherwise perform the operation in SImode. */
1165 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1166 wmode = SImode;
1167
1168 /* Widen operands if required. */
1169 if (mode != wmode)
1170 {
1171 if (GET_CODE (dst) == SUBREG
1172 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1173 dst = tem;
1174 else if (REG_P (dst))
1175 dst = gen_rtx_SUBREG (wmode, dst, 0);
1176 else
1177 dst = gen_reg_rtx (wmode);
1178
1179 if (GET_CODE (src1) == SUBREG
1180 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1181 src1 = tem;
1182 else if (GET_MODE (src1) != VOIDmode)
1183 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1184
1185 if (GET_CODE (src2) == SUBREG
1186 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1187 src2 = tem;
1188 else if (GET_MODE (src2) != VOIDmode)
1189 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1190 }
1191
1192 /* Emit the instruction. */
1193 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1194 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1195 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1196
1197 /* Fix up the destination if needed. */
1198 if (dst != operands[0])
1199 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1200 }
1201
1202 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1203
1204 bool
1205 s390_logical_operator_ok_p (rtx *operands)
1206 {
1207 /* If the destination operand is in memory, it needs to coincide
1208 with one of the source operands. After reload, it has to be
1209 the first source operand. */
1210 if (GET_CODE (operands[0]) == MEM)
1211 return rtx_equal_p (operands[0], operands[1])
1212 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1213
1214 return true;
1215 }
1216
1217 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1218 operand IMMOP to switch from SS to SI type instructions. */
1219
1220 void
1221 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1222 {
1223 int def = code == AND ? -1 : 0;
1224 HOST_WIDE_INT mask;
1225 int part;
1226
1227 gcc_assert (GET_CODE (*memop) == MEM);
1228 gcc_assert (!MEM_VOLATILE_P (*memop));
1229
1230 mask = s390_extract_part (*immop, QImode, def);
1231 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1232 gcc_assert (part >= 0);
1233
1234 *memop = adjust_address (*memop, QImode, part);
1235 *immop = gen_int_mode (mask, QImode);
1236 }
1237
1238
1239 /* How to allocate a 'struct machine_function'. */
1240
1241 static struct machine_function *
1242 s390_init_machine_status (void)
1243 {
1244 return ggc_alloc_cleared (sizeof (struct machine_function));
1245 }
1246
1247 /* Change optimizations to be performed, depending on the
1248 optimization level.
1249
1250 LEVEL is the optimization level specified; 2 if `-O2' is
1251 specified, 1 if `-O' is specified, and 0 if neither is specified.
1252
1253 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1254
1255 void
1256 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1257 {
1258 /* ??? There are apparently still problems with -fcaller-saves. */
1259 flag_caller_saves = 0;
1260
1261 /* By default, always emit DWARF-2 unwind info. This allows debugging
1262 without maintaining a stack frame back-chain. */
1263 flag_asynchronous_unwind_tables = 1;
1264
1265 /* Use MVCLE instructions to decrease code size if requested. */
1266 if (size != 0)
1267 target_flags |= MASK_MVCLE;
1268 }
1269
1270 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1271 to the associated processor_type and processor_flags if so. */
1272
1273 static bool
1274 s390_handle_arch_option (const char *arg,
1275 enum processor_type *type,
1276 enum processor_flags *flags)
1277 {
1278 static struct pta
1279 {
1280 const char *const name; /* processor name or nickname. */
1281 const enum processor_type processor;
1282 const enum processor_flags flags;
1283 }
1284 const processor_alias_table[] =
1285 {
1286 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1287 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1288 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1289 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1290 | PF_LONG_DISPLACEMENT},
1291 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1292 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1293 };
1294 size_t i;
1295
1296 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1297 if (strcmp (arg, processor_alias_table[i].name) == 0)
1298 {
1299 *type = processor_alias_table[i].processor;
1300 *flags = processor_alias_table[i].flags;
1301 return true;
1302 }
1303 return false;
1304 }
1305
1306 /* Implement TARGET_HANDLE_OPTION. */
1307
1308 static bool
1309 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1310 {
1311 switch (code)
1312 {
1313 case OPT_march_:
1314 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1315
1316 case OPT_mstack_guard_:
1317 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1318 return false;
1319 if (exact_log2 (s390_stack_guard) == -1)
1320 error ("stack guard value must be an exact power of 2");
1321 return true;
1322
1323 case OPT_mstack_size_:
1324 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1325 return false;
1326 if (exact_log2 (s390_stack_size) == -1)
1327 error ("stack size must be an exact power of 2");
1328 return true;
1329
1330 case OPT_mtune_:
1331 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1332
1333 case OPT_mwarn_framesize_:
1334 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1335
1336 default:
1337 return true;
1338 }
1339 }
1340
1341 void
1342 override_options (void)
1343 {
1344 /* Set up function hooks. */
1345 init_machine_status = s390_init_machine_status;
1346
1347 /* Architecture mode defaults according to ABI. */
1348 if (!(target_flags_explicit & MASK_ZARCH))
1349 {
1350 if (TARGET_64BIT)
1351 target_flags |= MASK_ZARCH;
1352 else
1353 target_flags &= ~MASK_ZARCH;
1354 }
1355
1356 /* Determine processor architectural level. */
1357 if (!s390_arch_string)
1358 {
1359 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1360 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1361 }
1362
1363 /* Determine processor to tune for. */
1364 if (s390_tune == PROCESSOR_max)
1365 {
1366 s390_tune = s390_arch;
1367 s390_tune_flags = s390_arch_flags;
1368 }
1369
1370 /* Sanity checks. */
1371 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1372 error ("z/Architecture mode not supported on %s", s390_arch_string);
1373 if (TARGET_64BIT && !TARGET_ZARCH)
1374 error ("64-bit ABI not supported in ESA/390 mode");
1375
1376 /* Set processor cost function. */
1377 if (s390_tune == PROCESSOR_2094_Z9_109)
1378 s390_cost = &z9_109_cost;
1379 else if (s390_tune == PROCESSOR_2084_Z990)
1380 s390_cost = &z990_cost;
1381 else
1382 s390_cost = &z900_cost;
1383
1384 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1385 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1386 "in combination");
1387
1388 if (s390_stack_size)
1389 {
1390 if (!s390_stack_guard)
1391 error ("-mstack-size implies use of -mstack-guard");
1392 else if (s390_stack_guard >= s390_stack_size)
1393 error ("stack size must be greater than the stack guard value");
1394 else if (s390_stack_size > 1 << 16)
1395 error ("stack size must not be greater than 64k");
1396 }
1397 else if (s390_stack_guard)
1398 error ("-mstack-guard implies use of -mstack-size");
1399 }
1400
1401 /* Map for smallest class containing reg regno. */
1402
1403 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1404 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1405 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1406 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1407 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1408 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1409 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1410 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1411 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1412 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1413 ACCESS_REGS, ACCESS_REGS
1414 };
1415
1416 /* Return attribute type of insn. */
1417
1418 static enum attr_type
1419 s390_safe_attr_type (rtx insn)
1420 {
1421 if (recog_memoized (insn) >= 0)
1422 return get_attr_type (insn);
1423 else
1424 return TYPE_NONE;
1425 }
1426
1427 /* Return true if DISP is a valid short displacement. */
1428
1429 static bool
1430 s390_short_displacement (rtx disp)
1431 {
1432 /* No displacement is OK. */
1433 if (!disp)
1434 return true;
1435
1436 /* Integer displacement in range. */
1437 if (GET_CODE (disp) == CONST_INT)
1438 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1439
1440 /* GOT offset is not OK, the GOT can be large. */
1441 if (GET_CODE (disp) == CONST
1442 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1443 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1444 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1445 return false;
1446
1447 /* All other symbolic constants are literal pool references,
1448 which are OK as the literal pool must be small. */
1449 if (GET_CODE (disp) == CONST)
1450 return true;
1451
1452 return false;
1453 }
1454
1455 /* Decompose a RTL expression ADDR for a memory address into
1456 its components, returned in OUT.
1457
1458 Returns false if ADDR is not a valid memory address, true
1459 otherwise. If OUT is NULL, don't return the components,
1460 but check for validity only.
1461
1462 Note: Only addresses in canonical form are recognized.
1463 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1464 canonical form so that they will be recognized. */
1465
1466 static int
1467 s390_decompose_address (rtx addr, struct s390_address *out)
1468 {
1469 HOST_WIDE_INT offset = 0;
1470 rtx base = NULL_RTX;
1471 rtx indx = NULL_RTX;
1472 rtx disp = NULL_RTX;
1473 rtx orig_disp;
1474 bool pointer = false;
1475 bool base_ptr = false;
1476 bool indx_ptr = false;
1477 bool literal_pool = false;
1478
1479 /* We may need to substitute the literal pool base register into the address
1480 below. However, at this point we do not know which register is going to
1481 be used as base, so we substitute the arg pointer register. This is going
1482 to be treated as holding a pointer below -- it shouldn't be used for any
1483 other purpose. */
1484 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1485
1486 /* Decompose address into base + index + displacement. */
1487
1488 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1489 base = addr;
1490
1491 else if (GET_CODE (addr) == PLUS)
1492 {
1493 rtx op0 = XEXP (addr, 0);
1494 rtx op1 = XEXP (addr, 1);
1495 enum rtx_code code0 = GET_CODE (op0);
1496 enum rtx_code code1 = GET_CODE (op1);
1497
1498 if (code0 == REG || code0 == UNSPEC)
1499 {
1500 if (code1 == REG || code1 == UNSPEC)
1501 {
1502 indx = op0; /* index + base */
1503 base = op1;
1504 }
1505
1506 else
1507 {
1508 base = op0; /* base + displacement */
1509 disp = op1;
1510 }
1511 }
1512
1513 else if (code0 == PLUS)
1514 {
1515 indx = XEXP (op0, 0); /* index + base + disp */
1516 base = XEXP (op0, 1);
1517 disp = op1;
1518 }
1519
1520 else
1521 {
1522 return false;
1523 }
1524 }
1525
1526 else
1527 disp = addr; /* displacement */
1528
1529 /* Extract integer part of displacement. */
1530 orig_disp = disp;
1531 if (disp)
1532 {
1533 if (GET_CODE (disp) == CONST_INT)
1534 {
1535 offset = INTVAL (disp);
1536 disp = NULL_RTX;
1537 }
1538 else if (GET_CODE (disp) == CONST
1539 && GET_CODE (XEXP (disp, 0)) == PLUS
1540 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1541 {
1542 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1543 disp = XEXP (XEXP (disp, 0), 0);
1544 }
1545 }
1546
1547 /* Strip off CONST here to avoid special case tests later. */
1548 if (disp && GET_CODE (disp) == CONST)
1549 disp = XEXP (disp, 0);
1550
1551 /* We can convert literal pool addresses to
1552 displacements by basing them off the base register. */
1553 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1554 {
1555 /* Either base or index must be free to hold the base register. */
1556 if (!base)
1557 base = fake_pool_base, literal_pool = true;
1558 else if (!indx)
1559 indx = fake_pool_base, literal_pool = true;
1560 else
1561 return false;
1562
1563 /* Mark up the displacement. */
1564 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1565 UNSPEC_LTREL_OFFSET);
1566 }
1567
1568 /* Validate base register. */
1569 if (base)
1570 {
1571 if (GET_CODE (base) == UNSPEC)
1572 switch (XINT (base, 1))
1573 {
1574 case UNSPEC_LTREF:
1575 if (!disp)
1576 disp = gen_rtx_UNSPEC (Pmode,
1577 gen_rtvec (1, XVECEXP (base, 0, 0)),
1578 UNSPEC_LTREL_OFFSET);
1579 else
1580 return false;
1581
1582 base = XVECEXP (base, 0, 1);
1583 break;
1584
1585 case UNSPEC_LTREL_BASE:
1586 if (XVECLEN (base, 0) == 1)
1587 base = fake_pool_base, literal_pool = true;
1588 else
1589 base = XVECEXP (base, 0, 1);
1590 break;
1591
1592 default:
1593 return false;
1594 }
1595
1596 if (GET_CODE (base) != REG || GET_MODE (base) != Pmode)
1597 return false;
1598
1599 if (REGNO (base) == STACK_POINTER_REGNUM
1600 || REGNO (base) == FRAME_POINTER_REGNUM
1601 || ((reload_completed || reload_in_progress)
1602 && frame_pointer_needed
1603 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1604 || REGNO (base) == ARG_POINTER_REGNUM
1605 || (flag_pic
1606 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1607 pointer = base_ptr = true;
1608
1609 if ((reload_completed || reload_in_progress)
1610 && base == cfun->machine->base_reg)
1611 pointer = base_ptr = literal_pool = true;
1612 }
1613
1614 /* Validate index register. */
1615 if (indx)
1616 {
1617 if (GET_CODE (indx) == UNSPEC)
1618 switch (XINT (indx, 1))
1619 {
1620 case UNSPEC_LTREF:
1621 if (!disp)
1622 disp = gen_rtx_UNSPEC (Pmode,
1623 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1624 UNSPEC_LTREL_OFFSET);
1625 else
1626 return false;
1627
1628 indx = XVECEXP (indx, 0, 1);
1629 break;
1630
1631 case UNSPEC_LTREL_BASE:
1632 if (XVECLEN (indx, 0) == 1)
1633 indx = fake_pool_base, literal_pool = true;
1634 else
1635 indx = XVECEXP (indx, 0, 1);
1636 break;
1637
1638 default:
1639 return false;
1640 }
1641
1642 if (GET_CODE (indx) != REG || GET_MODE (indx) != Pmode)
1643 return false;
1644
1645 if (REGNO (indx) == STACK_POINTER_REGNUM
1646 || REGNO (indx) == FRAME_POINTER_REGNUM
1647 || ((reload_completed || reload_in_progress)
1648 && frame_pointer_needed
1649 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1650 || REGNO (indx) == ARG_POINTER_REGNUM
1651 || (flag_pic
1652 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1653 pointer = indx_ptr = true;
1654
1655 if ((reload_completed || reload_in_progress)
1656 && indx == cfun->machine->base_reg)
1657 pointer = indx_ptr = literal_pool = true;
1658 }
1659
1660 /* Prefer to use pointer as base, not index. */
1661 if (base && indx && !base_ptr
1662 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1663 {
1664 rtx tmp = base;
1665 base = indx;
1666 indx = tmp;
1667 }
1668
1669 /* Validate displacement. */
1670 if (!disp)
1671 {
1672 /* If virtual registers are involved, the displacement will change later
1673 anyway as the virtual registers get eliminated. This could make a
1674 valid displacement invalid, but it is more likely to make an invalid
1675 displacement valid, because we sometimes access the register save area
1676 via negative offsets to one of those registers.
1677 Thus we don't check the displacement for validity here. If after
1678 elimination the displacement turns out to be invalid after all,
1679 this is fixed up by reload in any case. */
1680 if (base != arg_pointer_rtx
1681 && indx != arg_pointer_rtx
1682 && base != return_address_pointer_rtx
1683 && indx != return_address_pointer_rtx
1684 && base != frame_pointer_rtx
1685 && indx != frame_pointer_rtx
1686 && base != virtual_stack_vars_rtx
1687 && indx != virtual_stack_vars_rtx)
1688 if (!DISP_IN_RANGE (offset))
1689 return false;
1690 }
1691 else
1692 {
1693 /* All the special cases are pointers. */
1694 pointer = true;
1695
1696 /* In the small-PIC case, the linker converts @GOT
1697 and @GOTNTPOFF offsets to possible displacements. */
1698 if (GET_CODE (disp) == UNSPEC
1699 && (XINT (disp, 1) == UNSPEC_GOT
1700 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1701 && offset == 0
1702 && flag_pic == 1)
1703 {
1704 ;
1705 }
1706
1707 /* Accept chunkified literal pool symbol references. */
1708 else if (GET_CODE (disp) == MINUS
1709 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1710 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1711 {
1712 ;
1713 }
1714
1715 /* Accept literal pool references. */
1716 else if (GET_CODE (disp) == UNSPEC
1717 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1718 {
1719 orig_disp = gen_rtx_CONST (Pmode, disp);
1720 if (offset)
1721 {
1722 /* If we have an offset, make sure it does not
1723 exceed the size of the constant pool entry. */
1724 rtx sym = XVECEXP (disp, 0, 0);
1725 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1726 return false;
1727
1728 orig_disp = plus_constant (orig_disp, offset);
1729 }
1730 }
1731
1732 else
1733 return false;
1734 }
1735
1736 if (!base && !indx)
1737 pointer = true;
1738
1739 if (out)
1740 {
1741 out->base = base;
1742 out->indx = indx;
1743 out->disp = orig_disp;
1744 out->pointer = pointer;
1745 out->literal_pool = literal_pool;
1746 }
1747
1748 return true;
1749 }
1750
1751 /* Decompose a RTL expression OP for a shift count into its components,
1752 and return the base register in BASE and the offset in OFFSET.
1753
1754 Return true if OP is a valid shift count, false if not. */
1755
1756 bool
1757 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1758 {
1759 HOST_WIDE_INT off = 0;
1760
1761 /* We can have an integer constant, an address register,
1762 or a sum of the two. */
1763 if (GET_CODE (op) == CONST_INT)
1764 {
1765 off = INTVAL (op);
1766 op = NULL_RTX;
1767 }
1768 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
1769 {
1770 off = INTVAL (XEXP (op, 1));
1771 op = XEXP (op, 0);
1772 }
1773 while (op && GET_CODE (op) == SUBREG)
1774 op = SUBREG_REG (op);
1775
1776 if (op && GET_CODE (op) != REG)
1777 return false;
1778
1779 if (offset)
1780 *offset = off;
1781 if (base)
1782 *base = op;
1783
1784 return true;
1785 }
1786
1787
1788 /* Return true if CODE is a valid address without index. */
1789
1790 bool
1791 s390_legitimate_address_without_index_p (rtx op)
1792 {
1793 struct s390_address addr;
1794
1795 if (!s390_decompose_address (XEXP (op, 0), &addr))
1796 return false;
1797 if (addr.indx)
1798 return false;
1799
1800 return true;
1801 }
1802
1803 /* Return 1 if OP is a valid operand for a C constraint, 0 else. */
1804
1805 int
1806 s390_extra_constraint_str (rtx op, int c, const char * str)
1807 {
1808 struct s390_address addr;
1809
1810 gcc_assert (c == str[0]);
1811
1812 /* Check for offsettable variants of memory constraints. */
1813 if (c == 'A')
1814 {
1815 /* Only accept non-volatile MEMs. */
1816 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1817 return 0;
1818
1819 if ((reload_completed || reload_in_progress)
1820 ? !offsettable_memref_p (op)
1821 : !offsettable_nonstrict_memref_p (op))
1822 return 0;
1823
1824 c = str[1];
1825 }
1826
1827 /* Check for non-literal-pool variants of memory constraints. */
1828 else if (c == 'B')
1829 {
1830 if (GET_CODE (op) != MEM)
1831 return 0;
1832 if (!s390_decompose_address (XEXP (op, 0), &addr))
1833 return 0;
1834 if (addr.literal_pool)
1835 return 0;
1836
1837 c = str[1];
1838 }
1839
1840 switch (c)
1841 {
1842 case 'Q':
1843 if (GET_CODE (op) != MEM)
1844 return 0;
1845 if (!s390_decompose_address (XEXP (op, 0), &addr))
1846 return 0;
1847 if (addr.indx)
1848 return 0;
1849
1850 if (TARGET_LONG_DISPLACEMENT)
1851 {
1852 if (!s390_short_displacement (addr.disp))
1853 return 0;
1854 }
1855 break;
1856
1857 case 'R':
1858 if (GET_CODE (op) != MEM)
1859 return 0;
1860
1861 if (TARGET_LONG_DISPLACEMENT)
1862 {
1863 if (!s390_decompose_address (XEXP (op, 0), &addr))
1864 return 0;
1865 if (!s390_short_displacement (addr.disp))
1866 return 0;
1867 }
1868 break;
1869
1870 case 'S':
1871 if (!TARGET_LONG_DISPLACEMENT)
1872 return 0;
1873 if (GET_CODE (op) != MEM)
1874 return 0;
1875 if (!s390_decompose_address (XEXP (op, 0), &addr))
1876 return 0;
1877 if (addr.indx)
1878 return 0;
1879 if (s390_short_displacement (addr.disp))
1880 return 0;
1881 break;
1882
1883 case 'T':
1884 if (!TARGET_LONG_DISPLACEMENT)
1885 return 0;
1886 if (GET_CODE (op) != MEM)
1887 return 0;
1888 /* Any invalid address here will be fixed up by reload,
1889 so accept it for the most generic constraint. */
1890 if (s390_decompose_address (XEXP (op, 0), &addr)
1891 && s390_short_displacement (addr.disp))
1892 return 0;
1893 break;
1894
1895 case 'U':
1896 if (TARGET_LONG_DISPLACEMENT)
1897 {
1898 if (!s390_decompose_address (op, &addr))
1899 return 0;
1900 if (!s390_short_displacement (addr.disp))
1901 return 0;
1902 }
1903 break;
1904
1905 case 'W':
1906 if (!TARGET_LONG_DISPLACEMENT)
1907 return 0;
1908 /* Any invalid address here will be fixed up by reload,
1909 so accept it for the most generic constraint. */
1910 if (s390_decompose_address (op, &addr)
1911 && s390_short_displacement (addr.disp))
1912 return 0;
1913 break;
1914
1915 case 'Y':
1916 /* Simply check for the basic form of a shift count. Reload will
1917 take care of making sure we have a proper base register. */
1918 if (!s390_decompose_shift_count (op, NULL, NULL))
1919 return 0;
1920 break;
1921
1922 default:
1923 return 0;
1924 }
1925
1926 return 1;
1927 }
1928
1929 /* Return true if VALUE matches the constraint STR. */
1930
1931 int
1932 s390_const_double_ok_for_constraint_p (rtx value,
1933 int c,
1934 const char * str)
1935 {
1936 gcc_assert (c == str[0]);
1937
1938 switch (str[0])
1939 {
1940 case 'G':
1941 /* The floating point zero constant. */
1942 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1943 && value == CONST0_RTX (GET_MODE (value)));
1944
1945 default:
1946 return 0;
1947 }
1948 }
1949
1950 /* Return true if VALUE matches the constraint STR. */
1951
1952 int
1953 s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1954 int c,
1955 const char * str)
1956 {
1957 enum machine_mode mode, part_mode;
1958 int def;
1959 int part, part_goal;
1960
1961 gcc_assert (c == str[0]);
1962
1963 switch (str[0])
1964 {
1965 case 'I':
1966 return (unsigned int)value < 256;
1967
1968 case 'J':
1969 return (unsigned int)value < 4096;
1970
1971 case 'K':
1972 return value >= -32768 && value < 32768;
1973
1974 case 'L':
1975 return (TARGET_LONG_DISPLACEMENT ?
1976 (value >= -524288 && value <= 524287)
1977 : (value >= 0 && value <= 4095));
1978 case 'M':
1979 return value == 2147483647;
1980
1981 case 'N':
1982 if (str[1] == 'x')
1983 part_goal = -1;
1984 else
1985 part_goal = str[1] - '0';
1986
1987 switch (str[2])
1988 {
1989 case 'Q': part_mode = QImode; break;
1990 case 'H': part_mode = HImode; break;
1991 case 'S': part_mode = SImode; break;
1992 default: return 0;
1993 }
1994
1995 switch (str[3])
1996 {
1997 case 'H': mode = HImode; break;
1998 case 'S': mode = SImode; break;
1999 case 'D': mode = DImode; break;
2000 default: return 0;
2001 }
2002
2003 switch (str[4])
2004 {
2005 case '0': def = 0; break;
2006 case 'F': def = -1; break;
2007 default: return 0;
2008 }
2009
2010 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2011 return 0;
2012
2013 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2014 if (part < 0)
2015 return 0;
2016 if (part_goal != -1 && part_goal != part)
2017 return 0;
2018
2019 break;
2020
2021 case 'O':
2022 if (!TARGET_EXTIMM)
2023 return 0;
2024
2025 switch (str[1])
2026 {
2027 case 's':
2028 return trunc_int_for_mode (value, SImode) == value;
2029
2030 case 'p':
2031 return value == 0
2032 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2033
2034 case 'n':
2035 return value == -1
2036 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
2037
2038 default:
2039 gcc_unreachable ();
2040 }
2041 break;
2042
2043 case 'P':
2044 return legitimate_reload_constant_p (GEN_INT (value));
2045
2046 default:
2047 return 0;
2048 }
2049
2050 return 1;
2051 }
2052
2053 /* Compute a (partial) cost for rtx X. Return true if the complete
2054 cost has been computed, and false if subexpressions should be
2055 scanned. In either case, *TOTAL contains the cost result.
2056 CODE contains GET_CODE (x), OUTER_CODE contains the code
2057 of the superexpression of x. */
2058
2059 static bool
2060 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2061 {
2062 switch (code)
2063 {
2064 case CONST:
2065 case CONST_INT:
2066 case LABEL_REF:
2067 case SYMBOL_REF:
2068 case CONST_DOUBLE:
2069 case MEM:
2070 *total = 0;
2071 return true;
2072
2073 case ASHIFT:
2074 case ASHIFTRT:
2075 case LSHIFTRT:
2076 case ROTATE:
2077 case ROTATERT:
2078 case AND:
2079 case IOR:
2080 case XOR:
2081 case NEG:
2082 case NOT:
2083 *total = COSTS_N_INSNS (1);
2084 return false;
2085
2086 case PLUS:
2087 case MINUS:
2088 /* Check for multiply and add. */
2089 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2090 && GET_CODE (XEXP (x, 0)) == MULT
2091 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2092 {
2093 /* This is the multiply and add case. */
2094 if (GET_MODE (x) == DFmode)
2095 *total = s390_cost->madbr;
2096 else
2097 *total = s390_cost->maebr;
2098 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2099 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2100 + rtx_cost (XEXP (x, 1), code);
2101 return true; /* Do not do an additional recursive descent. */
2102 }
2103 *total = COSTS_N_INSNS (1);
2104 return false;
2105
2106 case MULT:
2107 switch (GET_MODE (x))
2108 {
2109 case SImode:
2110 {
2111 rtx left = XEXP (x, 0);
2112 rtx right = XEXP (x, 1);
2113 if (GET_CODE (right) == CONST_INT
2114 && CONST_OK_FOR_K (INTVAL (right)))
2115 *total = s390_cost->mhi;
2116 else if (GET_CODE (left) == SIGN_EXTEND)
2117 *total = s390_cost->mh;
2118 else
2119 *total = s390_cost->ms; /* msr, ms, msy */
2120 break;
2121 }
2122 case DImode:
2123 {
2124 rtx left = XEXP (x, 0);
2125 rtx right = XEXP (x, 1);
2126 if (TARGET_64BIT)
2127 {
2128 if (GET_CODE (right) == CONST_INT
2129 && CONST_OK_FOR_K (INTVAL (right)))
2130 *total = s390_cost->mghi;
2131 else if (GET_CODE (left) == SIGN_EXTEND)
2132 *total = s390_cost->msgf;
2133 else
2134 *total = s390_cost->msg; /* msgr, msg */
2135 }
2136 else /* TARGET_31BIT */
2137 {
2138 if (GET_CODE (left) == SIGN_EXTEND
2139 && GET_CODE (right) == SIGN_EXTEND)
2140 /* mulsidi case: mr, m */
2141 *total = s390_cost->m;
2142 else if (GET_CODE (left) == ZERO_EXTEND
2143 && GET_CODE (right) == ZERO_EXTEND
2144 && TARGET_CPU_ZARCH)
2145 /* umulsidi case: ml, mlr */
2146 *total = s390_cost->ml;
2147 else
2148 /* Complex calculation is required. */
2149 *total = COSTS_N_INSNS (40);
2150 }
2151 break;
2152 }
2153 case SFmode:
2154 case DFmode:
2155 *total = s390_cost->mult_df;
2156 break;
2157 default:
2158 return false;
2159 }
2160 return false;
2161
2162 case UDIV:
2163 case UMOD:
2164 if (GET_MODE (x) == TImode) /* 128 bit division */
2165 *total = s390_cost->dlgr;
2166 else if (GET_MODE (x) == DImode)
2167 {
2168 rtx right = XEXP (x, 1);
2169 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2170 *total = s390_cost->dlr;
2171 else /* 64 by 64 bit division */
2172 *total = s390_cost->dlgr;
2173 }
2174 else if (GET_MODE (x) == SImode) /* 32 bit division */
2175 *total = s390_cost->dlr;
2176 return false;
2177
2178 case DIV:
2179 case MOD:
2180 if (GET_MODE (x) == DImode)
2181 {
2182 rtx right = XEXP (x, 1);
2183 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2184 if (TARGET_64BIT)
2185 *total = s390_cost->dsgfr;
2186 else
2187 *total = s390_cost->dr;
2188 else /* 64 by 64 bit division */
2189 *total = s390_cost->dsgr;
2190 }
2191 else if (GET_MODE (x) == SImode) /* 32 bit division */
2192 *total = s390_cost->dlr;
2193 else if (GET_MODE (x) == SFmode)
2194 {
2195 if (TARGET_IEEE_FLOAT)
2196 *total = s390_cost->debr;
2197 else /* TARGET_IBM_FLOAT */
2198 *total = s390_cost->der;
2199 }
2200 else if (GET_MODE (x) == DFmode)
2201 {
2202 if (TARGET_IEEE_FLOAT)
2203 *total = s390_cost->ddbr;
2204 else /* TARGET_IBM_FLOAT */
2205 *total = s390_cost->ddr;
2206 }
2207 return false;
2208
2209 case SQRT:
2210 if (GET_MODE (x) == SFmode)
2211 *total = s390_cost->sqebr;
2212 else /* DFmode */
2213 *total = s390_cost->sqdbr;
2214 return false;
2215
2216 case SIGN_EXTEND:
2217 case ZERO_EXTEND:
2218 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2219 || outer_code == PLUS || outer_code == MINUS
2220 || outer_code == COMPARE)
2221 *total = 0;
2222 return false;
2223
2224 case COMPARE:
2225 *total = COSTS_N_INSNS (1);
2226 if (GET_CODE (XEXP (x, 0)) == AND
2227 && GET_CODE (XEXP (x, 1)) == CONST_INT
2228 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2229 {
2230 rtx op0 = XEXP (XEXP (x, 0), 0);
2231 rtx op1 = XEXP (XEXP (x, 0), 1);
2232 rtx op2 = XEXP (x, 1);
2233
2234 if (memory_operand (op0, GET_MODE (op0))
2235 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2236 return true;
2237 if (register_operand (op0, GET_MODE (op0))
2238 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2239 return true;
2240 }
2241 return false;
2242
2243 default:
2244 return false;
2245 }
2246 }
2247
2248 /* Return the cost of an address rtx ADDR. */
2249
2250 static int
2251 s390_address_cost (rtx addr)
2252 {
2253 struct s390_address ad;
2254 if (!s390_decompose_address (addr, &ad))
2255 return 1000;
2256
2257 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2258 }
2259
2260 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2261 otherwise return 0. */
2262
2263 int
2264 tls_symbolic_operand (rtx op)
2265 {
2266 if (GET_CODE (op) != SYMBOL_REF)
2267 return 0;
2268 return SYMBOL_REF_TLS_MODEL (op);
2269 }
2270 \f
2271 /* Split DImode access register reference REG (on 64-bit) into its constituent
2272 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2273 gen_highpart cannot be used as they assume all registers are word-sized,
2274 while our access registers have only half that size. */
2275
2276 void
2277 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2278 {
2279 gcc_assert (TARGET_64BIT);
2280 gcc_assert (ACCESS_REG_P (reg));
2281 gcc_assert (GET_MODE (reg) == DImode);
2282 gcc_assert (!(REGNO (reg) & 1));
2283
2284 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2285 *hi = gen_rtx_REG (SImode, REGNO (reg));
2286 }
2287
2288 /* Return true if OP contains a symbol reference */
2289
2290 bool
2291 symbolic_reference_mentioned_p (rtx op)
2292 {
2293 const char *fmt;
2294 int i;
2295
2296 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2297 return 1;
2298
2299 fmt = GET_RTX_FORMAT (GET_CODE (op));
2300 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2301 {
2302 if (fmt[i] == 'E')
2303 {
2304 int j;
2305
2306 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2307 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2308 return 1;
2309 }
2310
2311 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2312 return 1;
2313 }
2314
2315 return 0;
2316 }
2317
2318 /* Return true if OP contains a reference to a thread-local symbol. */
2319
2320 bool
2321 tls_symbolic_reference_mentioned_p (rtx op)
2322 {
2323 const char *fmt;
2324 int i;
2325
2326 if (GET_CODE (op) == SYMBOL_REF)
2327 return tls_symbolic_operand (op);
2328
2329 fmt = GET_RTX_FORMAT (GET_CODE (op));
2330 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2331 {
2332 if (fmt[i] == 'E')
2333 {
2334 int j;
2335
2336 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2337 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2338 return true;
2339 }
2340
2341 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2342 return true;
2343 }
2344
2345 return false;
2346 }
2347
2348
2349 /* Return true if OP is a legitimate general operand when
2350 generating PIC code. It is given that flag_pic is on
2351 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2352
2353 int
2354 legitimate_pic_operand_p (rtx op)
2355 {
2356 /* Accept all non-symbolic constants. */
2357 if (!SYMBOLIC_CONST (op))
2358 return 1;
2359
2360 /* Reject everything else; must be handled
2361 via emit_symbolic_move. */
2362 return 0;
2363 }
2364
2365 /* Returns true if the constant value OP is a legitimate general operand.
2366 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2367
2368 int
2369 legitimate_constant_p (rtx op)
2370 {
2371 /* Accept all non-symbolic constants. */
2372 if (!SYMBOLIC_CONST (op))
2373 return 1;
2374
2375 /* Accept immediate LARL operands. */
2376 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2377 return 1;
2378
2379 /* Thread-local symbols are never legal constants. This is
2380 so that emit_call knows that computing such addresses
2381 might require a function call. */
2382 if (TLS_SYMBOLIC_CONST (op))
2383 return 0;
2384
2385 /* In the PIC case, symbolic constants must *not* be
2386 forced into the literal pool. We accept them here,
2387 so that they will be handled by emit_symbolic_move. */
2388 if (flag_pic)
2389 return 1;
2390
2391 /* All remaining non-PIC symbolic constants are
2392 forced into the literal pool. */
2393 return 0;
2394 }
2395
2396 /* Determine if it's legal to put X into the constant pool. This
2397 is not possible if X contains the address of a symbol that is
2398 not constant (TLS) or not known at final link time (PIC). */
2399
2400 static bool
2401 s390_cannot_force_const_mem (rtx x)
2402 {
2403 switch (GET_CODE (x))
2404 {
2405 case CONST_INT:
2406 case CONST_DOUBLE:
2407 /* Accept all non-symbolic constants. */
2408 return false;
2409
2410 case LABEL_REF:
2411 /* Labels are OK iff we are non-PIC. */
2412 return flag_pic != 0;
2413
2414 case SYMBOL_REF:
2415 /* 'Naked' TLS symbol references are never OK,
2416 non-TLS symbols are OK iff we are non-PIC. */
2417 if (tls_symbolic_operand (x))
2418 return true;
2419 else
2420 return flag_pic != 0;
2421
2422 case CONST:
2423 return s390_cannot_force_const_mem (XEXP (x, 0));
2424 case PLUS:
2425 case MINUS:
2426 return s390_cannot_force_const_mem (XEXP (x, 0))
2427 || s390_cannot_force_const_mem (XEXP (x, 1));
2428
2429 case UNSPEC:
2430 switch (XINT (x, 1))
2431 {
2432 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2433 case UNSPEC_LTREL_OFFSET:
2434 case UNSPEC_GOT:
2435 case UNSPEC_GOTOFF:
2436 case UNSPEC_PLTOFF:
2437 case UNSPEC_TLSGD:
2438 case UNSPEC_TLSLDM:
2439 case UNSPEC_NTPOFF:
2440 case UNSPEC_DTPOFF:
2441 case UNSPEC_GOTNTPOFF:
2442 case UNSPEC_INDNTPOFF:
2443 return false;
2444
2445 /* If the literal pool shares the code section, be put
2446 execute template placeholders into the pool as well. */
2447 case UNSPEC_INSN:
2448 return TARGET_CPU_ZARCH;
2449
2450 default:
2451 return true;
2452 }
2453 break;
2454
2455 default:
2456 gcc_unreachable ();
2457 }
2458 }
2459
2460 /* Returns true if the constant value OP is a legitimate general
2461 operand during and after reload. The difference to
2462 legitimate_constant_p is that this function will not accept
2463 a constant that would need to be forced to the literal pool
2464 before it can be used as operand. */
2465
2466 bool
2467 legitimate_reload_constant_p (rtx op)
2468 {
2469 /* Accept la(y) operands. */
2470 if (GET_CODE (op) == CONST_INT
2471 && DISP_IN_RANGE (INTVAL (op)))
2472 return true;
2473
2474 /* Accept l(g)hi/l(g)fi operands. */
2475 if (GET_CODE (op) == CONST_INT
2476 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2477 return true;
2478
2479 /* Accept lliXX operands. */
2480 if (TARGET_ZARCH
2481 && GET_CODE (op) == CONST_INT
2482 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2483 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2484 return true;
2485
2486 if (TARGET_EXTIMM
2487 && GET_CODE (op) == CONST_INT
2488 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2489 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2490 return true;
2491
2492 /* Accept larl operands. */
2493 if (TARGET_CPU_ZARCH
2494 && larl_operand (op, VOIDmode))
2495 return true;
2496
2497 /* Accept lzXX operands. */
2498 if (GET_CODE (op) == CONST_DOUBLE
2499 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2500 return true;
2501
2502 /* Accept double-word operands that can be split. */
2503 if (GET_CODE (op) == CONST_INT
2504 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2505 {
2506 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2507 rtx hi = operand_subword (op, 0, 0, dword_mode);
2508 rtx lo = operand_subword (op, 1, 0, dword_mode);
2509 return legitimate_reload_constant_p (hi)
2510 && legitimate_reload_constant_p (lo);
2511 }
2512
2513 /* Everything else cannot be handled without reload. */
2514 return false;
2515 }
2516
2517 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2518 return the class of reg to actually use. */
2519
2520 enum reg_class
2521 s390_preferred_reload_class (rtx op, enum reg_class class)
2522 {
2523 switch (GET_CODE (op))
2524 {
2525 /* Constants we cannot reload must be forced into the
2526 literal pool. */
2527
2528 case CONST_DOUBLE:
2529 case CONST_INT:
2530 if (legitimate_reload_constant_p (op))
2531 return class;
2532 else
2533 return NO_REGS;
2534
2535 /* If a symbolic constant or a PLUS is reloaded,
2536 it is most likely being used as an address, so
2537 prefer ADDR_REGS. If 'class' is not a superset
2538 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2539 case PLUS:
2540 case LABEL_REF:
2541 case SYMBOL_REF:
2542 case CONST:
2543 if (reg_class_subset_p (ADDR_REGS, class))
2544 return ADDR_REGS;
2545 else
2546 return NO_REGS;
2547
2548 default:
2549 break;
2550 }
2551
2552 return class;
2553 }
2554
2555 /* Return the register class of a scratch register needed to
2556 load IN into a register of class CLASS in MODE.
2557
2558 We need a temporary when loading a PLUS expression which
2559 is not a legitimate operand of the LOAD ADDRESS instruction. */
2560
2561 enum reg_class
2562 s390_secondary_input_reload_class (enum reg_class class,
2563 enum machine_mode mode, rtx in)
2564 {
2565 if (s390_plus_operand (in, mode))
2566 return ADDR_REGS;
2567
2568 if (reg_classes_intersect_p (CC_REGS, class))
2569 return GENERAL_REGS;
2570
2571 return NO_REGS;
2572 }
2573
2574 /* Return the register class of a scratch register needed to
2575 store a register of class CLASS in MODE into OUT:
2576
2577 We need a temporary when storing a double-word to a
2578 non-offsettable memory address. */
2579
2580 enum reg_class
2581 s390_secondary_output_reload_class (enum reg_class class,
2582 enum machine_mode mode, rtx out)
2583 {
2584 if ((TARGET_64BIT ? mode == TImode
2585 : (mode == DImode || mode == DFmode))
2586 && reg_classes_intersect_p (GENERAL_REGS, class)
2587 && GET_CODE (out) == MEM
2588 && GET_CODE (XEXP (out, 0)) == PLUS
2589 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2590 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2591 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2592 + GET_MODE_SIZE (mode) - 1))
2593 return ADDR_REGS;
2594
2595 if (reg_classes_intersect_p (CC_REGS, class))
2596 return GENERAL_REGS;
2597
2598 return NO_REGS;
2599 }
2600
2601 /* Generate code to load SRC, which is PLUS that is not a
2602 legitimate operand for the LA instruction, into TARGET.
2603 SCRATCH may be used as scratch register. */
2604
2605 void
2606 s390_expand_plus_operand (rtx target, rtx src,
2607 rtx scratch)
2608 {
2609 rtx sum1, sum2;
2610 struct s390_address ad;
2611
2612 /* src must be a PLUS; get its two operands. */
2613 gcc_assert (GET_CODE (src) == PLUS);
2614 gcc_assert (GET_MODE (src) == Pmode);
2615
2616 /* Check if any of the two operands is already scheduled
2617 for replacement by reload. This can happen e.g. when
2618 float registers occur in an address. */
2619 sum1 = find_replacement (&XEXP (src, 0));
2620 sum2 = find_replacement (&XEXP (src, 1));
2621 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2622
2623 /* If the address is already strictly valid, there's nothing to do. */
2624 if (!s390_decompose_address (src, &ad)
2625 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2626 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
2627 {
2628 /* Otherwise, one of the operands cannot be an address register;
2629 we reload its value into the scratch register. */
2630 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2631 {
2632 emit_move_insn (scratch, sum1);
2633 sum1 = scratch;
2634 }
2635 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2636 {
2637 emit_move_insn (scratch, sum2);
2638 sum2 = scratch;
2639 }
2640
2641 /* According to the way these invalid addresses are generated
2642 in reload.c, it should never happen (at least on s390) that
2643 *neither* of the PLUS components, after find_replacements
2644 was applied, is an address register. */
2645 if (sum1 == scratch && sum2 == scratch)
2646 {
2647 debug_rtx (src);
2648 gcc_unreachable ();
2649 }
2650
2651 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2652 }
2653
2654 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2655 is only ever performed on addresses, so we can mark the
2656 sum as legitimate for LA in any case. */
2657 s390_load_address (target, src);
2658 }
2659
2660
2661 /* Return true if ADDR is a valid memory address.
2662 STRICT specifies whether strict register checking applies. */
2663
2664 bool
2665 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2666 rtx addr, int strict)
2667 {
2668 struct s390_address ad;
2669 if (!s390_decompose_address (addr, &ad))
2670 return false;
2671
2672 if (strict)
2673 {
2674 if (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2675 return false;
2676 if (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx))
2677 return false;
2678 }
2679 else
2680 {
2681 if (ad.base && !REG_OK_FOR_BASE_NONSTRICT_P (ad.base))
2682 return false;
2683 if (ad.indx && !REG_OK_FOR_INDEX_NONSTRICT_P (ad.indx))
2684 return false;
2685 }
2686
2687 return true;
2688 }
2689
2690 /* Return true if OP is a valid operand for the LA instruction.
2691 In 31-bit, we need to prove that the result is used as an
2692 address, as LA performs only a 31-bit addition. */
2693
2694 bool
2695 legitimate_la_operand_p (rtx op)
2696 {
2697 struct s390_address addr;
2698 if (!s390_decompose_address (op, &addr))
2699 return false;
2700
2701 return (TARGET_64BIT || addr.pointer);
2702 }
2703
2704 /* Return true if it is valid *and* preferable to use LA to
2705 compute the sum of OP1 and OP2. */
2706
2707 bool
2708 preferred_la_operand_p (rtx op1, rtx op2)
2709 {
2710 struct s390_address addr;
2711
2712 if (op2 != const0_rtx)
2713 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2714
2715 if (!s390_decompose_address (op1, &addr))
2716 return false;
2717 if (addr.base && !REG_OK_FOR_BASE_STRICT_P (addr.base))
2718 return false;
2719 if (addr.indx && !REG_OK_FOR_INDEX_STRICT_P (addr.indx))
2720 return false;
2721
2722 if (!TARGET_64BIT && !addr.pointer)
2723 return false;
2724
2725 if (addr.pointer)
2726 return true;
2727
2728 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2729 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2730 return true;
2731
2732 return false;
2733 }
2734
2735 /* Emit a forced load-address operation to load SRC into DST.
2736 This will use the LOAD ADDRESS instruction even in situations
2737 where legitimate_la_operand_p (SRC) returns false. */
2738
2739 void
2740 s390_load_address (rtx dst, rtx src)
2741 {
2742 if (TARGET_64BIT)
2743 emit_move_insn (dst, src);
2744 else
2745 emit_insn (gen_force_la_31 (dst, src));
2746 }
2747
2748 /* Return a legitimate reference for ORIG (an address) using the
2749 register REG. If REG is 0, a new pseudo is generated.
2750
2751 There are two types of references that must be handled:
2752
2753 1. Global data references must load the address from the GOT, via
2754 the PIC reg. An insn is emitted to do this load, and the reg is
2755 returned.
2756
2757 2. Static data references, constant pool addresses, and code labels
2758 compute the address as an offset from the GOT, whose base is in
2759 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2760 differentiate them from global data objects. The returned
2761 address is the PIC reg + an unspec constant.
2762
2763 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2764 reg also appears in the address. */
2765
2766 rtx
2767 legitimize_pic_address (rtx orig, rtx reg)
2768 {
2769 rtx addr = orig;
2770 rtx new = orig;
2771 rtx base;
2772
2773 if (GET_CODE (addr) == LABEL_REF
2774 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2775 {
2776 /* This is a local symbol. */
2777 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2778 {
2779 /* Access local symbols PC-relative via LARL.
2780 This is the same as in the non-PIC case, so it is
2781 handled automatically ... */
2782 }
2783 else
2784 {
2785 /* Access local symbols relative to the GOT. */
2786
2787 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2788
2789 if (reload_in_progress || reload_completed)
2790 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2791
2792 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2793 addr = gen_rtx_CONST (Pmode, addr);
2794 addr = force_const_mem (Pmode, addr);
2795 emit_move_insn (temp, addr);
2796
2797 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2798 if (reg != 0)
2799 {
2800 s390_load_address (reg, new);
2801 new = reg;
2802 }
2803 }
2804 }
2805 else if (GET_CODE (addr) == SYMBOL_REF)
2806 {
2807 if (reg == 0)
2808 reg = gen_reg_rtx (Pmode);
2809
2810 if (flag_pic == 1)
2811 {
2812 /* Assume GOT offset < 4k. This is handled the same way
2813 in both 31- and 64-bit code (@GOT). */
2814
2815 if (reload_in_progress || reload_completed)
2816 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2817
2818 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2819 new = gen_rtx_CONST (Pmode, new);
2820 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2821 new = gen_const_mem (Pmode, new);
2822 emit_move_insn (reg, new);
2823 new = reg;
2824 }
2825 else if (TARGET_CPU_ZARCH)
2826 {
2827 /* If the GOT offset might be >= 4k, we determine the position
2828 of the GOT entry via a PC-relative LARL (@GOTENT). */
2829
2830 rtx temp = gen_reg_rtx (Pmode);
2831
2832 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2833 new = gen_rtx_CONST (Pmode, new);
2834 emit_move_insn (temp, new);
2835
2836 new = gen_const_mem (Pmode, temp);
2837 emit_move_insn (reg, new);
2838 new = reg;
2839 }
2840 else
2841 {
2842 /* If the GOT offset might be >= 4k, we have to load it
2843 from the literal pool (@GOT). */
2844
2845 rtx temp = gen_reg_rtx (Pmode);
2846
2847 if (reload_in_progress || reload_completed)
2848 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2849
2850 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2851 addr = gen_rtx_CONST (Pmode, addr);
2852 addr = force_const_mem (Pmode, addr);
2853 emit_move_insn (temp, addr);
2854
2855 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2856 new = gen_const_mem (Pmode, new);
2857 emit_move_insn (reg, new);
2858 new = reg;
2859 }
2860 }
2861 else
2862 {
2863 if (GET_CODE (addr) == CONST)
2864 {
2865 addr = XEXP (addr, 0);
2866 if (GET_CODE (addr) == UNSPEC)
2867 {
2868 gcc_assert (XVECLEN (addr, 0) == 1);
2869 switch (XINT (addr, 1))
2870 {
2871 /* If someone moved a GOT-relative UNSPEC
2872 out of the literal pool, force them back in. */
2873 case UNSPEC_GOTOFF:
2874 case UNSPEC_PLTOFF:
2875 new = force_const_mem (Pmode, orig);
2876 break;
2877
2878 /* @GOT is OK as is if small. */
2879 case UNSPEC_GOT:
2880 if (flag_pic == 2)
2881 new = force_const_mem (Pmode, orig);
2882 break;
2883
2884 /* @GOTENT is OK as is. */
2885 case UNSPEC_GOTENT:
2886 break;
2887
2888 /* @PLT is OK as is on 64-bit, must be converted to
2889 GOT-relative @PLTOFF on 31-bit. */
2890 case UNSPEC_PLT:
2891 if (!TARGET_CPU_ZARCH)
2892 {
2893 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2894
2895 if (reload_in_progress || reload_completed)
2896 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2897
2898 addr = XVECEXP (addr, 0, 0);
2899 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2900 UNSPEC_PLTOFF);
2901 addr = gen_rtx_CONST (Pmode, addr);
2902 addr = force_const_mem (Pmode, addr);
2903 emit_move_insn (temp, addr);
2904
2905 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2906 if (reg != 0)
2907 {
2908 s390_load_address (reg, new);
2909 new = reg;
2910 }
2911 }
2912 break;
2913
2914 /* Everything else cannot happen. */
2915 default:
2916 gcc_unreachable ();
2917 }
2918 }
2919 else
2920 gcc_assert (GET_CODE (addr) == PLUS);
2921 }
2922 if (GET_CODE (addr) == PLUS)
2923 {
2924 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2925 /* Check first to see if this is a constant offset
2926 from a local symbol reference. */
2927 if ((GET_CODE (op0) == LABEL_REF
2928 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
2929 && GET_CODE (op1) == CONST_INT)
2930 {
2931 if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
2932 {
2933 if (INTVAL (op1) & 1)
2934 {
2935 /* LARL can't handle odd offsets, so emit a
2936 pair of LARL and LA. */
2937 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2938
2939 if (!DISP_IN_RANGE (INTVAL (op1)))
2940 {
2941 int even = INTVAL (op1) - 1;
2942 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
2943 op0 = gen_rtx_CONST (Pmode, op0);
2944 op1 = const1_rtx;
2945 }
2946
2947 emit_move_insn (temp, op0);
2948 new = gen_rtx_PLUS (Pmode, temp, op1);
2949
2950 if (reg != 0)
2951 {
2952 s390_load_address (reg, new);
2953 new = reg;
2954 }
2955 }
2956 else
2957 {
2958 /* If the offset is even, we can just use LARL.
2959 This will happen automatically. */
2960 }
2961 }
2962 else
2963 {
2964 /* Access local symbols relative to the GOT. */
2965
2966 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2967
2968 if (reload_in_progress || reload_completed)
2969 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2970
2971 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
2972 UNSPEC_GOTOFF);
2973 addr = gen_rtx_PLUS (Pmode, addr, op1);
2974 addr = gen_rtx_CONST (Pmode, addr);
2975 addr = force_const_mem (Pmode, addr);
2976 emit_move_insn (temp, addr);
2977
2978 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2979 if (reg != 0)
2980 {
2981 s390_load_address (reg, new);
2982 new = reg;
2983 }
2984 }
2985 }
2986
2987 /* Now, check whether it is a GOT relative symbol plus offset
2988 that was pulled out of the literal pool. Force it back in. */
2989
2990 else if (GET_CODE (op0) == UNSPEC
2991 && GET_CODE (op1) == CONST_INT
2992 && XINT (op0, 1) == UNSPEC_GOTOFF)
2993 {
2994 gcc_assert (XVECLEN (op0, 0) == 1);
2995
2996 new = force_const_mem (Pmode, orig);
2997 }
2998
2999 /* Otherwise, compute the sum. */
3000 else
3001 {
3002 base = legitimize_pic_address (XEXP (addr, 0), reg);
3003 new = legitimize_pic_address (XEXP (addr, 1),
3004 base == reg ? NULL_RTX : reg);
3005 if (GET_CODE (new) == CONST_INT)
3006 new = plus_constant (base, INTVAL (new));
3007 else
3008 {
3009 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
3010 {
3011 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
3012 new = XEXP (new, 1);
3013 }
3014 new = gen_rtx_PLUS (Pmode, base, new);
3015 }
3016
3017 if (GET_CODE (new) == CONST)
3018 new = XEXP (new, 0);
3019 new = force_operand (new, 0);
3020 }
3021 }
3022 }
3023 return new;
3024 }
3025
3026 /* Load the thread pointer into a register. */
3027
3028 rtx
3029 s390_get_thread_pointer (void)
3030 {
3031 rtx tp = gen_reg_rtx (Pmode);
3032
3033 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3034 mark_reg_pointer (tp, BITS_PER_WORD);
3035
3036 return tp;
3037 }
3038
3039 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3040 in s390_tls_symbol which always refers to __tls_get_offset.
3041 The returned offset is written to RESULT_REG and an USE rtx is
3042 generated for TLS_CALL. */
3043
3044 static GTY(()) rtx s390_tls_symbol;
3045
3046 static void
3047 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3048 {
3049 rtx insn;
3050
3051 gcc_assert (flag_pic);
3052
3053 if (!s390_tls_symbol)
3054 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3055
3056 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3057 gen_rtx_REG (Pmode, RETURN_REGNUM));
3058
3059 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3060 CONST_OR_PURE_CALL_P (insn) = 1;
3061 }
3062
3063 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3064 this (thread-local) address. REG may be used as temporary. */
3065
3066 static rtx
3067 legitimize_tls_address (rtx addr, rtx reg)
3068 {
3069 rtx new, tls_call, temp, base, r2, insn;
3070
3071 if (GET_CODE (addr) == SYMBOL_REF)
3072 switch (tls_symbolic_operand (addr))
3073 {
3074 case TLS_MODEL_GLOBAL_DYNAMIC:
3075 start_sequence ();
3076 r2 = gen_rtx_REG (Pmode, 2);
3077 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3078 new = gen_rtx_CONST (Pmode, tls_call);
3079 new = force_const_mem (Pmode, new);
3080 emit_move_insn (r2, new);
3081 s390_emit_tls_call_insn (r2, tls_call);
3082 insn = get_insns ();
3083 end_sequence ();
3084
3085 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3086 temp = gen_reg_rtx (Pmode);
3087 emit_libcall_block (insn, temp, r2, new);
3088
3089 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3090 if (reg != 0)
3091 {
3092 s390_load_address (reg, new);
3093 new = reg;
3094 }
3095 break;
3096
3097 case TLS_MODEL_LOCAL_DYNAMIC:
3098 start_sequence ();
3099 r2 = gen_rtx_REG (Pmode, 2);
3100 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3101 new = gen_rtx_CONST (Pmode, tls_call);
3102 new = force_const_mem (Pmode, new);
3103 emit_move_insn (r2, new);
3104 s390_emit_tls_call_insn (r2, tls_call);
3105 insn = get_insns ();
3106 end_sequence ();
3107
3108 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3109 temp = gen_reg_rtx (Pmode);
3110 emit_libcall_block (insn, temp, r2, new);
3111
3112 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3113 base = gen_reg_rtx (Pmode);
3114 s390_load_address (base, new);
3115
3116 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3117 new = gen_rtx_CONST (Pmode, new);
3118 new = force_const_mem (Pmode, new);
3119 temp = gen_reg_rtx (Pmode);
3120 emit_move_insn (temp, new);
3121
3122 new = gen_rtx_PLUS (Pmode, base, temp);
3123 if (reg != 0)
3124 {
3125 s390_load_address (reg, new);
3126 new = reg;
3127 }
3128 break;
3129
3130 case TLS_MODEL_INITIAL_EXEC:
3131 if (flag_pic == 1)
3132 {
3133 /* Assume GOT offset < 4k. This is handled the same way
3134 in both 31- and 64-bit code. */
3135
3136 if (reload_in_progress || reload_completed)
3137 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3138
3139 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3140 new = gen_rtx_CONST (Pmode, new);
3141 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3142 new = gen_const_mem (Pmode, new);
3143 temp = gen_reg_rtx (Pmode);
3144 emit_move_insn (temp, new);
3145 }
3146 else if (TARGET_CPU_ZARCH)
3147 {
3148 /* If the GOT offset might be >= 4k, we determine the position
3149 of the GOT entry via a PC-relative LARL. */
3150
3151 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3152 new = gen_rtx_CONST (Pmode, new);
3153 temp = gen_reg_rtx (Pmode);
3154 emit_move_insn (temp, new);
3155
3156 new = gen_const_mem (Pmode, temp);
3157 temp = gen_reg_rtx (Pmode);
3158 emit_move_insn (temp, new);
3159 }
3160 else if (flag_pic)
3161 {
3162 /* If the GOT offset might be >= 4k, we have to load it
3163 from the literal pool. */
3164
3165 if (reload_in_progress || reload_completed)
3166 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3167
3168 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3169 new = gen_rtx_CONST (Pmode, new);
3170 new = force_const_mem (Pmode, new);
3171 temp = gen_reg_rtx (Pmode);
3172 emit_move_insn (temp, new);
3173
3174 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3175 new = gen_const_mem (Pmode, new);
3176
3177 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3178 temp = gen_reg_rtx (Pmode);
3179 emit_insn (gen_rtx_SET (Pmode, temp, new));
3180 }
3181 else
3182 {
3183 /* In position-dependent code, load the absolute address of
3184 the GOT entry from the literal pool. */
3185
3186 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3187 new = gen_rtx_CONST (Pmode, new);
3188 new = force_const_mem (Pmode, new);
3189 temp = gen_reg_rtx (Pmode);
3190 emit_move_insn (temp, new);
3191
3192 new = temp;
3193 new = gen_const_mem (Pmode, new);
3194 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3195 temp = gen_reg_rtx (Pmode);
3196 emit_insn (gen_rtx_SET (Pmode, temp, new));
3197 }
3198
3199 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3200 if (reg != 0)
3201 {
3202 s390_load_address (reg, new);
3203 new = reg;
3204 }
3205 break;
3206
3207 case TLS_MODEL_LOCAL_EXEC:
3208 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3209 new = gen_rtx_CONST (Pmode, new);
3210 new = force_const_mem (Pmode, new);
3211 temp = gen_reg_rtx (Pmode);
3212 emit_move_insn (temp, new);
3213
3214 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3215 if (reg != 0)
3216 {
3217 s390_load_address (reg, new);
3218 new = reg;
3219 }
3220 break;
3221
3222 default:
3223 gcc_unreachable ();
3224 }
3225
3226 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3227 {
3228 switch (XINT (XEXP (addr, 0), 1))
3229 {
3230 case UNSPEC_INDNTPOFF:
3231 gcc_assert (TARGET_CPU_ZARCH);
3232 new = addr;
3233 break;
3234
3235 default:
3236 gcc_unreachable ();
3237 }
3238 }
3239
3240 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3241 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3242 {
3243 new = XEXP (XEXP (addr, 0), 0);
3244 if (GET_CODE (new) != SYMBOL_REF)
3245 new = gen_rtx_CONST (Pmode, new);
3246
3247 new = legitimize_tls_address (new, reg);
3248 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3249 new = force_operand (new, 0);
3250 }
3251
3252 else
3253 gcc_unreachable (); /* for now ... */
3254
3255 return new;
3256 }
3257
3258 /* Emit insns to move operands[1] into operands[0]. */
3259
3260 void
3261 emit_symbolic_move (rtx *operands)
3262 {
3263 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3264
3265 if (GET_CODE (operands[0]) == MEM)
3266 operands[1] = force_reg (Pmode, operands[1]);
3267 else if (TLS_SYMBOLIC_CONST (operands[1]))
3268 operands[1] = legitimize_tls_address (operands[1], temp);
3269 else if (flag_pic)
3270 operands[1] = legitimize_pic_address (operands[1], temp);
3271 }
3272
3273 /* Try machine-dependent ways of modifying an illegitimate address X
3274 to be legitimate. If we find one, return the new, valid address.
3275
3276 OLDX is the address as it was before break_out_memory_refs was called.
3277 In some cases it is useful to look at this to decide what needs to be done.
3278
3279 MODE is the mode of the operand pointed to by X.
3280
3281 When -fpic is used, special handling is needed for symbolic references.
3282 See comments by legitimize_pic_address for details. */
3283
3284 rtx
3285 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3286 enum machine_mode mode ATTRIBUTE_UNUSED)
3287 {
3288 rtx constant_term = const0_rtx;
3289
3290 if (TLS_SYMBOLIC_CONST (x))
3291 {
3292 x = legitimize_tls_address (x, 0);
3293
3294 if (legitimate_address_p (mode, x, FALSE))
3295 return x;
3296 }
3297 else if (flag_pic)
3298 {
3299 if (SYMBOLIC_CONST (x)
3300 || (GET_CODE (x) == PLUS
3301 && (SYMBOLIC_CONST (XEXP (x, 0))
3302 || SYMBOLIC_CONST (XEXP (x, 1)))))
3303 x = legitimize_pic_address (x, 0);
3304
3305 if (legitimate_address_p (mode, x, FALSE))
3306 return x;
3307 }
3308
3309 x = eliminate_constant_term (x, &constant_term);
3310
3311 /* Optimize loading of large displacements by splitting them
3312 into the multiple of 4K and the rest; this allows the
3313 former to be CSE'd if possible.
3314
3315 Don't do this if the displacement is added to a register
3316 pointing into the stack frame, as the offsets will
3317 change later anyway. */
3318
3319 if (GET_CODE (constant_term) == CONST_INT
3320 && !TARGET_LONG_DISPLACEMENT
3321 && !DISP_IN_RANGE (INTVAL (constant_term))
3322 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3323 {
3324 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3325 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3326
3327 rtx temp = gen_reg_rtx (Pmode);
3328 rtx val = force_operand (GEN_INT (upper), temp);
3329 if (val != temp)
3330 emit_move_insn (temp, val);
3331
3332 x = gen_rtx_PLUS (Pmode, x, temp);
3333 constant_term = GEN_INT (lower);
3334 }
3335
3336 if (GET_CODE (x) == PLUS)
3337 {
3338 if (GET_CODE (XEXP (x, 0)) == REG)
3339 {
3340 rtx temp = gen_reg_rtx (Pmode);
3341 rtx val = force_operand (XEXP (x, 1), temp);
3342 if (val != temp)
3343 emit_move_insn (temp, val);
3344
3345 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3346 }
3347
3348 else if (GET_CODE (XEXP (x, 1)) == REG)
3349 {
3350 rtx temp = gen_reg_rtx (Pmode);
3351 rtx val = force_operand (XEXP (x, 0), temp);
3352 if (val != temp)
3353 emit_move_insn (temp, val);
3354
3355 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3356 }
3357 }
3358
3359 if (constant_term != const0_rtx)
3360 x = gen_rtx_PLUS (Pmode, x, constant_term);
3361
3362 return x;
3363 }
3364
3365 /* Try a machine-dependent way of reloading an illegitimate address AD
3366 operand. If we find one, push the reload and and return the new address.
3367
3368 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3369 and TYPE is the reload type of the current reload. */
3370
3371 rtx
3372 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3373 int opnum, int type)
3374 {
3375 if (!optimize || TARGET_LONG_DISPLACEMENT)
3376 return NULL_RTX;
3377
3378 if (GET_CODE (ad) == PLUS)
3379 {
3380 rtx tem = simplify_binary_operation (PLUS, Pmode,
3381 XEXP (ad, 0), XEXP (ad, 1));
3382 if (tem)
3383 ad = tem;
3384 }
3385
3386 if (GET_CODE (ad) == PLUS
3387 && GET_CODE (XEXP (ad, 0)) == REG
3388 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3389 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3390 {
3391 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3392 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3393 rtx cst, tem, new;
3394
3395 cst = GEN_INT (upper);
3396 if (!legitimate_reload_constant_p (cst))
3397 cst = force_const_mem (Pmode, cst);
3398
3399 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3400 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3401
3402 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3403 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3404 opnum, (enum reload_type) type);
3405 return new;
3406 }
3407
3408 return NULL_RTX;
3409 }
3410
3411 /* Emit code to move LEN bytes from DST to SRC. */
3412
3413 void
3414 s390_expand_movmem (rtx dst, rtx src, rtx len)
3415 {
3416 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3417 {
3418 if (INTVAL (len) > 0)
3419 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3420 }
3421
3422 else if (TARGET_MVCLE)
3423 {
3424 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3425 }
3426
3427 else
3428 {
3429 rtx dst_addr, src_addr, count, blocks, temp;
3430 rtx loop_start_label = gen_label_rtx ();
3431 rtx loop_end_label = gen_label_rtx ();
3432 rtx end_label = gen_label_rtx ();
3433 enum machine_mode mode;
3434
3435 mode = GET_MODE (len);
3436 if (mode == VOIDmode)
3437 mode = Pmode;
3438
3439 dst_addr = gen_reg_rtx (Pmode);
3440 src_addr = gen_reg_rtx (Pmode);
3441 count = gen_reg_rtx (mode);
3442 blocks = gen_reg_rtx (mode);
3443
3444 convert_move (count, len, 1);
3445 emit_cmp_and_jump_insns (count, const0_rtx,
3446 EQ, NULL_RTX, mode, 1, end_label);
3447
3448 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3449 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3450 dst = change_address (dst, VOIDmode, dst_addr);
3451 src = change_address (src, VOIDmode, src_addr);
3452
3453 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3454 if (temp != count)
3455 emit_move_insn (count, temp);
3456
3457 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3458 if (temp != blocks)
3459 emit_move_insn (blocks, temp);
3460
3461 emit_cmp_and_jump_insns (blocks, const0_rtx,
3462 EQ, NULL_RTX, mode, 1, loop_end_label);
3463
3464 emit_label (loop_start_label);
3465
3466 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3467 s390_load_address (dst_addr,
3468 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3469 s390_load_address (src_addr,
3470 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3471
3472 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3473 if (temp != blocks)
3474 emit_move_insn (blocks, temp);
3475
3476 emit_cmp_and_jump_insns (blocks, const0_rtx,
3477 EQ, NULL_RTX, mode, 1, loop_end_label);
3478
3479 emit_jump (loop_start_label);
3480 emit_label (loop_end_label);
3481
3482 emit_insn (gen_movmem_short (dst, src,
3483 convert_to_mode (Pmode, count, 1)));
3484 emit_label (end_label);
3485 }
3486 }
3487
3488 /* Emit code to set LEN bytes at DST to VAL.
3489 Make use of clrmem if VAL is zero. */
3490
3491 void
3492 s390_expand_setmem (rtx dst, rtx len, rtx val)
3493 {
3494 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3495 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3496
3497 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3498 {
3499 if (val == const0_rtx && INTVAL (len) <= 256)
3500 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3501 else
3502 {
3503 /* Initialize memory by storing the first byte. */
3504 emit_move_insn (adjust_address (dst, QImode, 0), val);
3505
3506 if (INTVAL (len) > 1)
3507 {
3508 /* Initiate 1 byte overlap move.
3509 The first byte of DST is propagated through DSTP1.
3510 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3511 DST is set to size 1 so the rest of the memory location
3512 does not count as source operand. */
3513 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3514 set_mem_size (dst, const1_rtx);
3515
3516 emit_insn (gen_movmem_short (dstp1, dst,
3517 GEN_INT (INTVAL (len) - 2)));
3518 }
3519 }
3520 }
3521
3522 else if (TARGET_MVCLE)
3523 {
3524 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3525 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3526 }
3527
3528 else
3529 {
3530 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3531 rtx loop_start_label = gen_label_rtx ();
3532 rtx loop_end_label = gen_label_rtx ();
3533 rtx end_label = gen_label_rtx ();
3534 enum machine_mode mode;
3535
3536 mode = GET_MODE (len);
3537 if (mode == VOIDmode)
3538 mode = Pmode;
3539
3540 dst_addr = gen_reg_rtx (Pmode);
3541 src_addr = gen_reg_rtx (Pmode);
3542 count = gen_reg_rtx (mode);
3543 blocks = gen_reg_rtx (mode);
3544
3545 convert_move (count, len, 1);
3546 emit_cmp_and_jump_insns (count, const0_rtx,
3547 EQ, NULL_RTX, mode, 1, end_label);
3548
3549 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3550 dst = change_address (dst, VOIDmode, dst_addr);
3551
3552 if (val == const0_rtx)
3553 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3554 else
3555 {
3556 dstp1 = adjust_address (dst, VOIDmode, 1);
3557 set_mem_size (dst, const1_rtx);
3558
3559 /* Initialize memory by storing the first byte. */
3560 emit_move_insn (adjust_address (dst, QImode, 0), val);
3561
3562 /* If count is 1 we are done. */
3563 emit_cmp_and_jump_insns (count, const1_rtx,
3564 EQ, NULL_RTX, mode, 1, end_label);
3565
3566 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3567 }
3568 if (temp != count)
3569 emit_move_insn (count, temp);
3570
3571 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3572 if (temp != blocks)
3573 emit_move_insn (blocks, temp);
3574
3575 emit_cmp_and_jump_insns (blocks, const0_rtx,
3576 EQ, NULL_RTX, mode, 1, loop_end_label);
3577
3578 emit_label (loop_start_label);
3579
3580 if (val == const0_rtx)
3581 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3582 else
3583 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3584 s390_load_address (dst_addr,
3585 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3586
3587 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3588 if (temp != blocks)
3589 emit_move_insn (blocks, temp);
3590
3591 emit_cmp_and_jump_insns (blocks, const0_rtx,
3592 EQ, NULL_RTX, mode, 1, loop_end_label);
3593
3594 emit_jump (loop_start_label);
3595 emit_label (loop_end_label);
3596
3597 if (val == const0_rtx)
3598 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3599 else
3600 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3601 emit_label (end_label);
3602 }
3603 }
3604
3605 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3606 and return the result in TARGET. */
3607
3608 void
3609 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3610 {
3611 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3612 rtx tmp;
3613
3614 /* As the result of CMPINT is inverted compared to what we need,
3615 we have to swap the operands. */
3616 tmp = op0; op0 = op1; op1 = tmp;
3617
3618 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3619 {
3620 if (INTVAL (len) > 0)
3621 {
3622 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3623 emit_insn (gen_cmpint (target, ccreg));
3624 }
3625 else
3626 emit_move_insn (target, const0_rtx);
3627 }
3628 else if (TARGET_MVCLE)
3629 {
3630 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3631 emit_insn (gen_cmpint (target, ccreg));
3632 }
3633 else
3634 {
3635 rtx addr0, addr1, count, blocks, temp;
3636 rtx loop_start_label = gen_label_rtx ();
3637 rtx loop_end_label = gen_label_rtx ();
3638 rtx end_label = gen_label_rtx ();
3639 enum machine_mode mode;
3640
3641 mode = GET_MODE (len);
3642 if (mode == VOIDmode)
3643 mode = Pmode;
3644
3645 addr0 = gen_reg_rtx (Pmode);
3646 addr1 = gen_reg_rtx (Pmode);
3647 count = gen_reg_rtx (mode);
3648 blocks = gen_reg_rtx (mode);
3649
3650 convert_move (count, len, 1);
3651 emit_cmp_and_jump_insns (count, const0_rtx,
3652 EQ, NULL_RTX, mode, 1, end_label);
3653
3654 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3655 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3656 op0 = change_address (op0, VOIDmode, addr0);
3657 op1 = change_address (op1, VOIDmode, addr1);
3658
3659 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3660 if (temp != count)
3661 emit_move_insn (count, temp);
3662
3663 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3664 if (temp != blocks)
3665 emit_move_insn (blocks, temp);
3666
3667 emit_cmp_and_jump_insns (blocks, const0_rtx,
3668 EQ, NULL_RTX, mode, 1, loop_end_label);
3669
3670 emit_label (loop_start_label);
3671
3672 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3673 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3674 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3675 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3676 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3677 emit_jump_insn (temp);
3678
3679 s390_load_address (addr0,
3680 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3681 s390_load_address (addr1,
3682 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3683
3684 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3685 if (temp != blocks)
3686 emit_move_insn (blocks, temp);
3687
3688 emit_cmp_and_jump_insns (blocks, const0_rtx,
3689 EQ, NULL_RTX, mode, 1, loop_end_label);
3690
3691 emit_jump (loop_start_label);
3692 emit_label (loop_end_label);
3693
3694 emit_insn (gen_cmpmem_short (op0, op1,
3695 convert_to_mode (Pmode, count, 1)));
3696 emit_label (end_label);
3697
3698 emit_insn (gen_cmpint (target, ccreg));
3699 }
3700 }
3701
3702
3703 /* Expand conditional increment or decrement using alc/slb instructions.
3704 Should generate code setting DST to either SRC or SRC + INCREMENT,
3705 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3706 Returns true if successful, false otherwise.
3707
3708 That makes it possible to implement some if-constructs without jumps e.g.:
3709 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3710 unsigned int a, b, c;
3711 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3712 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3713 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3714 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3715
3716 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3717 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3718 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3719 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3720 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3721
3722 bool
3723 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3724 rtx dst, rtx src, rtx increment)
3725 {
3726 enum machine_mode cmp_mode;
3727 enum machine_mode cc_mode;
3728 rtx op_res;
3729 rtx insn;
3730 rtvec p;
3731 int ret;
3732
3733 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3734 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3735 cmp_mode = SImode;
3736 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3737 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3738 cmp_mode = DImode;
3739 else
3740 return false;
3741
3742 /* Try ADD LOGICAL WITH CARRY. */
3743 if (increment == const1_rtx)
3744 {
3745 /* Determine CC mode to use. */
3746 if (cmp_code == EQ || cmp_code == NE)
3747 {
3748 if (cmp_op1 != const0_rtx)
3749 {
3750 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3751 NULL_RTX, 0, OPTAB_WIDEN);
3752 cmp_op1 = const0_rtx;
3753 }
3754
3755 cmp_code = cmp_code == EQ ? LEU : GTU;
3756 }
3757
3758 if (cmp_code == LTU || cmp_code == LEU)
3759 {
3760 rtx tem = cmp_op0;
3761 cmp_op0 = cmp_op1;
3762 cmp_op1 = tem;
3763 cmp_code = swap_condition (cmp_code);
3764 }
3765
3766 switch (cmp_code)
3767 {
3768 case GTU:
3769 cc_mode = CCUmode;
3770 break;
3771
3772 case GEU:
3773 cc_mode = CCL3mode;
3774 break;
3775
3776 default:
3777 return false;
3778 }
3779
3780 /* Emit comparison instruction pattern. */
3781 if (!register_operand (cmp_op0, cmp_mode))
3782 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3783
3784 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3785 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3786 /* We use insn_invalid_p here to add clobbers if required. */
3787 ret = insn_invalid_p (emit_insn (insn));
3788 gcc_assert (!ret);
3789
3790 /* Emit ALC instruction pattern. */
3791 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3792 gen_rtx_REG (cc_mode, CC_REGNUM),
3793 const0_rtx);
3794
3795 if (src != const0_rtx)
3796 {
3797 if (!register_operand (src, GET_MODE (dst)))
3798 src = force_reg (GET_MODE (dst), src);
3799
3800 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3801 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3802 }
3803
3804 p = rtvec_alloc (2);
3805 RTVEC_ELT (p, 0) =
3806 gen_rtx_SET (VOIDmode, dst, op_res);
3807 RTVEC_ELT (p, 1) =
3808 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3809 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3810
3811 return true;
3812 }
3813
3814 /* Try SUBTRACT LOGICAL WITH BORROW. */
3815 if (increment == constm1_rtx)
3816 {
3817 /* Determine CC mode to use. */
3818 if (cmp_code == EQ || cmp_code == NE)
3819 {
3820 if (cmp_op1 != const0_rtx)
3821 {
3822 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3823 NULL_RTX, 0, OPTAB_WIDEN);
3824 cmp_op1 = const0_rtx;
3825 }
3826
3827 cmp_code = cmp_code == EQ ? LEU : GTU;
3828 }
3829
3830 if (cmp_code == GTU || cmp_code == GEU)
3831 {
3832 rtx tem = cmp_op0;
3833 cmp_op0 = cmp_op1;
3834 cmp_op1 = tem;
3835 cmp_code = swap_condition (cmp_code);
3836 }
3837
3838 switch (cmp_code)
3839 {
3840 case LEU:
3841 cc_mode = CCUmode;
3842 break;
3843
3844 case LTU:
3845 cc_mode = CCL3mode;
3846 break;
3847
3848 default:
3849 return false;
3850 }
3851
3852 /* Emit comparison instruction pattern. */
3853 if (!register_operand (cmp_op0, cmp_mode))
3854 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3855
3856 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3857 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3858 /* We use insn_invalid_p here to add clobbers if required. */
3859 ret = insn_invalid_p (emit_insn (insn));
3860 gcc_assert (!ret);
3861
3862 /* Emit SLB instruction pattern. */
3863 if (!register_operand (src, GET_MODE (dst)))
3864 src = force_reg (GET_MODE (dst), src);
3865
3866 op_res = gen_rtx_MINUS (GET_MODE (dst),
3867 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3868 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3869 gen_rtx_REG (cc_mode, CC_REGNUM),
3870 const0_rtx));
3871 p = rtvec_alloc (2);
3872 RTVEC_ELT (p, 0) =
3873 gen_rtx_SET (VOIDmode, dst, op_res);
3874 RTVEC_ELT (p, 1) =
3875 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3876 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3877
3878 return true;
3879 }
3880
3881 return false;
3882 }
3883
3884 /* Expand code for the insv template. Return true if successful, false else. */
3885
3886 bool
3887 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
3888 {
3889 int bitsize = INTVAL (op1);
3890 int bitpos = INTVAL (op2);
3891
3892 /* We need byte alignment. */
3893 if (bitsize % BITS_PER_UNIT)
3894 return false;
3895
3896 if (bitpos == 0
3897 && memory_operand (dest, VOIDmode)
3898 && (register_operand (src, word_mode)
3899 || const_int_operand (src, VOIDmode)))
3900 {
3901 /* Emit standard pattern if possible. */
3902 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
3903 if (GET_MODE_BITSIZE (mode) == bitsize)
3904 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
3905
3906 /* (set (ze (mem)) (const_int)). */
3907 else if (const_int_operand (src, VOIDmode))
3908 {
3909 int size = bitsize / BITS_PER_UNIT;
3910 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
3911 GET_MODE_SIZE (word_mode) - size);
3912
3913 dest = adjust_address (dest, BLKmode, 0);
3914 set_mem_size (dest, GEN_INT (size));
3915 s390_expand_movmem (dest, src_mem, GEN_INT (size));
3916 }
3917
3918 /* (set (ze (mem)) (reg)). */
3919 else if (register_operand (src, word_mode))
3920 {
3921 if (bitsize <= GET_MODE_BITSIZE (SImode))
3922 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
3923 const0_rtx), src);
3924 else
3925 {
3926 /* Emit st,stcmh sequence. */
3927 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
3928 int size = stcmh_width / BITS_PER_UNIT;
3929
3930 emit_move_insn (adjust_address (dest, SImode, size),
3931 gen_lowpart (SImode, src));
3932 set_mem_size (dest, GEN_INT (size));
3933 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
3934 (stcmh_width), const0_rtx),
3935 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
3936 (GET_MODE_BITSIZE (SImode))));
3937 }
3938 }
3939 else
3940 return false;
3941
3942 return true;
3943 }
3944
3945 /* (set (ze (reg)) (const_int)). */
3946 if (TARGET_ZARCH
3947 && register_operand (dest, word_mode)
3948 && (bitpos % 16) == 0
3949 && (bitsize % 16) == 0
3950 && const_int_operand (src, VOIDmode))
3951 {
3952 HOST_WIDE_INT val = INTVAL (src);
3953 int regpos = bitpos + bitsize;
3954
3955 while (regpos > bitpos)
3956 {
3957 enum machine_mode putmode;
3958 int putsize;
3959
3960 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
3961 putmode = SImode;
3962 else
3963 putmode = HImode;
3964
3965 putsize = GET_MODE_BITSIZE (putmode);
3966 regpos -= putsize;
3967 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
3968 GEN_INT (putsize),
3969 GEN_INT (regpos)),
3970 gen_int_mode (val, putmode));
3971 val >>= putsize;
3972 }
3973 gcc_assert (regpos == bitpos);
3974 return true;
3975 }
3976
3977 return false;
3978 }
3979
3980 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
3981 register that holds VAL of mode MODE shifted by COUNT bits. */
3982
3983 static inline rtx
3984 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
3985 {
3986 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
3987 NULL_RTX, 1, OPTAB_DIRECT);
3988 return expand_simple_binop (SImode, ASHIFT, val, count,
3989 NULL_RTX, 1, OPTAB_DIRECT);
3990 }
3991
3992 /* Structure to hold the initial parameters for a compare_and_swap operation
3993 in HImode and QImode. */
3994
3995 struct alignment_context
3996 {
3997 rtx memsi; /* SI aligned memory location. */
3998 rtx shift; /* Bit offset with regard to lsb. */
3999 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4000 rtx modemaski; /* ~modemask */
4001 bool aligned; /* True if memory is aligned, false else. */
4002 };
4003
4004 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4005 structure AC for transparent simplifying, if the memory alignment is known
4006 to be at least 32bit. MEM is the memory location for the actual operation
4007 and MODE its mode. */
4008
4009 static void
4010 init_alignment_context (struct alignment_context *ac, rtx mem,
4011 enum machine_mode mode)
4012 {
4013 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4014 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4015
4016 if (ac->aligned)
4017 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4018 else
4019 {
4020 /* Alignment is unknown. */
4021 rtx byteoffset, addr, align;
4022
4023 /* Force the address into a register. */
4024 addr = force_reg (Pmode, XEXP (mem, 0));
4025
4026 /* Align it to SImode. */
4027 align = expand_simple_binop (Pmode, AND, addr,
4028 GEN_INT (-GET_MODE_SIZE (SImode)),
4029 NULL_RTX, 1, OPTAB_DIRECT);
4030 /* Generate MEM. */
4031 ac->memsi = gen_rtx_MEM (SImode, align);
4032 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4033 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4034
4035 /* Calculate shiftcount. */
4036 byteoffset = expand_simple_binop (Pmode, AND, addr,
4037 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4038 NULL_RTX, 1, OPTAB_DIRECT);
4039 /* As we already have some offset, evaluate the remaining distance. */
4040 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4041 NULL_RTX, 1, OPTAB_DIRECT);
4042
4043 }
4044 /* Shift is the byte count, but we need the bitcount. */
4045 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4046 NULL_RTX, 1, OPTAB_DIRECT);
4047 /* Calculate masks. */
4048 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4049 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4050 NULL_RTX, 1, OPTAB_DIRECT);
4051 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4052 }
4053
4054 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4055 the memory location, CMP the old value to compare MEM with and NEW the value
4056 to set if CMP == MEM.
4057 CMP is never in memory for compare_and_swap_cc because
4058 expand_bool_compare_and_swap puts it into a register for later compare. */
4059
4060 void
4061 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new)
4062 {
4063 struct alignment_context ac;
4064 rtx cmpv, newv, val, resv, cc;
4065 rtx res = gen_reg_rtx (SImode);
4066 rtx csloop = gen_label_rtx ();
4067 rtx csend = gen_label_rtx ();
4068
4069 gcc_assert (register_operand (target, VOIDmode));
4070 gcc_assert (MEM_P (mem));
4071
4072 init_alignment_context (&ac, mem, mode);
4073
4074 /* Shift the values to the correct bit positions. */
4075 if (!(ac.aligned && MEM_P (cmp)))
4076 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4077 if (!(ac.aligned && MEM_P (new)))
4078 new = s390_expand_mask_and_shift (new, mode, ac.shift);
4079
4080 /* Load full word. Subsequent loads are performed by CS. */
4081 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4082 NULL_RTX, 1, OPTAB_DIRECT);
4083
4084 /* Start CS loop. */
4085 emit_label (csloop);
4086 /* val = "<mem>00..0<mem>"
4087 * cmp = "00..0<cmp>00..0"
4088 * new = "00..0<new>00..0"
4089 */
4090
4091 /* Patch cmp and new with val at correct position. */
4092 if (ac.aligned && MEM_P (cmp))
4093 {
4094 cmpv = force_reg (SImode, val);
4095 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4096 }
4097 else
4098 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4099 NULL_RTX, 1, OPTAB_DIRECT));
4100 if (ac.aligned && MEM_P (new))
4101 {
4102 newv = force_reg (SImode, val);
4103 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new);
4104 }
4105 else
4106 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
4107 NULL_RTX, 1, OPTAB_DIRECT));
4108
4109 /* Emit compare_and_swap pattern. */
4110 emit_insn (gen_sync_compare_and_swap_ccsi (res, ac.memsi, cmpv, newv));
4111
4112 /* Jump to end if we're done (likely?). */
4113 s390_emit_jump (csend, s390_emit_compare (EQ, cmpv, ac.memsi));
4114
4115 /* Check for changes outside mode. */
4116 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4117 NULL_RTX, 1, OPTAB_DIRECT);
4118 cc = s390_emit_compare (NE, resv, val);
4119 emit_move_insn (val, resv);
4120 /* Loop internal if so. */
4121 s390_emit_jump (csloop, cc);
4122
4123 emit_label (csend);
4124
4125 /* Return the correct part of the bitfield. */
4126 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4127 NULL_RTX, 1, OPTAB_DIRECT), 1);
4128 }
4129
4130 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4131 and VAL the value to play with. If AFTER is true then store the the value
4132 MEM holds after the operation, if AFTER is false then store the value MEM
4133 holds before the operation. If TARGET is zero then discard that value, else
4134 store it to TARGET. */
4135
4136 void
4137 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4138 rtx target, rtx mem, rtx val, bool after)
4139 {
4140 struct alignment_context ac;
4141 rtx cmp;
4142 rtx new = gen_reg_rtx (SImode);
4143 rtx orig = gen_reg_rtx (SImode);
4144 rtx csloop = gen_label_rtx ();
4145
4146 gcc_assert (!target || register_operand (target, VOIDmode));
4147 gcc_assert (MEM_P (mem));
4148
4149 init_alignment_context (&ac, mem, mode);
4150
4151 /* Shift val to the correct bit positions.
4152 Preserve "icm", but prevent "ex icm". */
4153 if (!(ac.aligned && code == SET && MEM_P (val)))
4154 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4155
4156 /* Further preparation insns. */
4157 if (code == PLUS || code == MINUS)
4158 emit_move_insn (orig, val);
4159 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4160 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4161 NULL_RTX, 1, OPTAB_DIRECT);
4162
4163 /* Load full word. Subsequent loads are performed by CS. */
4164 cmp = force_reg (SImode, ac.memsi);
4165
4166 /* Start CS loop. */
4167 emit_label (csloop);
4168 emit_move_insn (new, cmp);
4169
4170 /* Patch new with val at correct position. */
4171 switch (code)
4172 {
4173 case PLUS:
4174 case MINUS:
4175 val = expand_simple_binop (SImode, code, new, orig,
4176 NULL_RTX, 1, OPTAB_DIRECT);
4177 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4178 NULL_RTX, 1, OPTAB_DIRECT);
4179 /* FALLTHRU */
4180 case SET:
4181 if (ac.aligned && MEM_P (val))
4182 store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val);
4183 else
4184 {
4185 new = expand_simple_binop (SImode, AND, new, ac.modemaski,
4186 NULL_RTX, 1, OPTAB_DIRECT);
4187 new = expand_simple_binop (SImode, IOR, new, val,
4188 NULL_RTX, 1, OPTAB_DIRECT);
4189 }
4190 break;
4191 case AND:
4192 case IOR:
4193 case XOR:
4194 new = expand_simple_binop (SImode, code, new, val,
4195 NULL_RTX, 1, OPTAB_DIRECT);
4196 break;
4197 case MULT: /* NAND */
4198 new = expand_simple_binop (SImode, XOR, new, ac.modemask,
4199 NULL_RTX, 1, OPTAB_DIRECT);
4200 new = expand_simple_binop (SImode, AND, new, val,
4201 NULL_RTX, 1, OPTAB_DIRECT);
4202 break;
4203 default:
4204 gcc_unreachable ();
4205 }
4206 /* Emit compare_and_swap pattern. */
4207 emit_insn (gen_sync_compare_and_swap_ccsi (cmp, ac.memsi, cmp, new));
4208
4209 /* Loop until swapped (unlikely?). */
4210 s390_emit_jump (csloop, gen_rtx_fmt_ee (NE, CCZ1mode,
4211 gen_rtx_REG (CCZ1mode, CC_REGNUM),
4212 const0_rtx));
4213
4214 /* Return the correct part of the bitfield. */
4215 if (target)
4216 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4217 after ? new : cmp, ac.shift,
4218 NULL_RTX, 1, OPTAB_DIRECT), 1);
4219 }
4220
4221 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4222 We need to emit DTP-relative relocations. */
4223
4224 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4225
4226 static void
4227 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4228 {
4229 switch (size)
4230 {
4231 case 4:
4232 fputs ("\t.long\t", file);
4233 break;
4234 case 8:
4235 fputs ("\t.quad\t", file);
4236 break;
4237 default:
4238 gcc_unreachable ();
4239 }
4240 output_addr_const (file, x);
4241 fputs ("@DTPOFF", file);
4242 }
4243
4244 /* In the name of slightly smaller debug output, and to cater to
4245 general assembler lossage, recognize various UNSPEC sequences
4246 and turn them back into a direct symbol reference. */
4247
4248 static rtx
4249 s390_delegitimize_address (rtx orig_x)
4250 {
4251 rtx x = orig_x, y;
4252
4253 if (GET_CODE (x) != MEM)
4254 return orig_x;
4255
4256 x = XEXP (x, 0);
4257 if (GET_CODE (x) == PLUS
4258 && GET_CODE (XEXP (x, 1)) == CONST
4259 && GET_CODE (XEXP (x, 0)) == REG
4260 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4261 {
4262 y = XEXP (XEXP (x, 1), 0);
4263 if (GET_CODE (y) == UNSPEC
4264 && XINT (y, 1) == UNSPEC_GOT)
4265 return XVECEXP (y, 0, 0);
4266 return orig_x;
4267 }
4268
4269 if (GET_CODE (x) == CONST)
4270 {
4271 y = XEXP (x, 0);
4272 if (GET_CODE (y) == UNSPEC
4273 && XINT (y, 1) == UNSPEC_GOTENT)
4274 return XVECEXP (y, 0, 0);
4275 return orig_x;
4276 }
4277
4278 return orig_x;
4279 }
4280
4281 /* Output operand OP to stdio stream FILE.
4282 OP is an address (register + offset) which is not used to address data;
4283 instead the rightmost bits are interpreted as the value. */
4284
4285 static void
4286 print_shift_count_operand (FILE *file, rtx op)
4287 {
4288 HOST_WIDE_INT offset = 0;
4289
4290 /* Extract base register and offset. */
4291 if (!s390_decompose_shift_count (op, &base, &offset))
4292 gcc_unreachable ();
4293
4294 op = XEXP (op, 0);
4295 }
4296
4297 /* We can have an integer constant, an address register,
4298 or a sum of the two. */
4299 if (GET_CODE (op) == CONST_INT)
4300 {
4301 offset = INTVAL (op);
4302 op = NULL_RTX;
4303 }
4304 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
4305 {
4306 offset = INTVAL (XEXP (op, 1));
4307 op = XEXP (op, 0);
4308 }
4309 while (op && GET_CODE (op) == SUBREG)
4310 op = SUBREG_REG (op);
4311
4312 /* Sanity check. */
4313 if (op)
4314 {
4315 gcc_assert (GET_CODE (op) == REG);
4316 gcc_assert (REGNO (op) < FIRST_PSEUDO_REGISTER);
4317 gcc_assert (REGNO_REG_CLASS (REGNO (op)) == ADDR_REGS);
4318 }
4319
4320 /* Offsets are constricted to twelve bits. */
4321 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4322 if (op)
4323 fprintf (file, "(%s)", reg_names[REGNO (op)]);
4324 }
4325
4326 /* See 'get_some_local_dynamic_name'. */
4327
4328 static int
4329 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4330 {
4331 rtx x = *px;
4332
4333 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4334 {
4335 x = get_pool_constant (x);
4336 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4337 }
4338
4339 if (GET_CODE (x) == SYMBOL_REF
4340 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4341 {
4342 cfun->machine->some_ld_name = XSTR (x, 0);
4343 return 1;
4344 }
4345
4346 return 0;
4347 }
4348
4349 /* Locate some local-dynamic symbol still in use by this function
4350 so that we can print its name in local-dynamic base patterns. */
4351
4352 static const char *
4353 get_some_local_dynamic_name (void)
4354 {
4355 rtx insn;
4356
4357 if (cfun->machine->some_ld_name)
4358 return cfun->machine->some_ld_name;
4359
4360 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4361 if (INSN_P (insn)
4362 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4363 return cfun->machine->some_ld_name;
4364
4365 gcc_unreachable ();
4366 }
4367
4368 /* Output machine-dependent UNSPECs occurring in address constant X
4369 in assembler syntax to stdio stream FILE. Returns true if the
4370 constant X could be recognized, false otherwise. */
4371
4372 bool
4373 s390_output_addr_const_extra (FILE *file, rtx x)
4374 {
4375 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4376 switch (XINT (x, 1))
4377 {
4378 case UNSPEC_GOTENT:
4379 output_addr_const (file, XVECEXP (x, 0, 0));
4380 fprintf (file, "@GOTENT");
4381 return true;
4382 case UNSPEC_GOT:
4383 output_addr_const (file, XVECEXP (x, 0, 0));
4384 fprintf (file, "@GOT");
4385 return true;
4386 case UNSPEC_GOTOFF:
4387 output_addr_const (file, XVECEXP (x, 0, 0));
4388 fprintf (file, "@GOTOFF");
4389 return true;
4390 case UNSPEC_PLT:
4391 output_addr_const (file, XVECEXP (x, 0, 0));
4392 fprintf (file, "@PLT");
4393 return true;
4394 case UNSPEC_PLTOFF:
4395 output_addr_const (file, XVECEXP (x, 0, 0));
4396 fprintf (file, "@PLTOFF");
4397 return true;
4398 case UNSPEC_TLSGD:
4399 output_addr_const (file, XVECEXP (x, 0, 0));
4400 fprintf (file, "@TLSGD");
4401 return true;
4402 case UNSPEC_TLSLDM:
4403 assemble_name (file, get_some_local_dynamic_name ());
4404 fprintf (file, "@TLSLDM");
4405 return true;
4406 case UNSPEC_DTPOFF:
4407 output_addr_const (file, XVECEXP (x, 0, 0));
4408 fprintf (file, "@DTPOFF");
4409 return true;
4410 case UNSPEC_NTPOFF:
4411 output_addr_const (file, XVECEXP (x, 0, 0));
4412 fprintf (file, "@NTPOFF");
4413 return true;
4414 case UNSPEC_GOTNTPOFF:
4415 output_addr_const (file, XVECEXP (x, 0, 0));
4416 fprintf (file, "@GOTNTPOFF");
4417 return true;
4418 case UNSPEC_INDNTPOFF:
4419 output_addr_const (file, XVECEXP (x, 0, 0));
4420 fprintf (file, "@INDNTPOFF");
4421 return true;
4422 }
4423
4424 return false;
4425 }
4426
4427 /* Output address operand ADDR in assembler syntax to
4428 stdio stream FILE. */
4429
4430 void
4431 print_operand_address (FILE *file, rtx addr)
4432 {
4433 struct s390_address ad;
4434
4435 if (!s390_decompose_address (addr, &ad)
4436 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
4437 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
4438 output_operand_lossage ("cannot decompose address");
4439
4440 if (ad.disp)
4441 output_addr_const (file, ad.disp);
4442 else
4443 fprintf (file, "0");
4444
4445 if (ad.base && ad.indx)
4446 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4447 reg_names[REGNO (ad.base)]);
4448 else if (ad.base)
4449 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4450 }
4451
4452 /* Output operand X in assembler syntax to stdio stream FILE.
4453 CODE specified the format flag. The following format flags
4454 are recognized:
4455
4456 'C': print opcode suffix for branch condition.
4457 'D': print opcode suffix for inverse branch condition.
4458 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4459 'G': print the size of the operand in bytes.
4460 'O': print only the displacement of a memory reference.
4461 'R': print only the base register of a memory reference.
4462 'S': print S-type memory reference (base+displacement).
4463 'N': print the second word of a DImode operand.
4464 'M': print the second word of a TImode operand.
4465 'Y': print shift count operand.
4466
4467 'b': print integer X as if it's an unsigned byte.
4468 'x': print integer X as if it's an unsigned halfword.
4469 'h': print integer X as if it's a signed halfword.
4470 'i': print the first nonzero HImode part of X.
4471 'j': print the first HImode part unequal to -1 of X.
4472 'k': print the first nonzero SImode part of X.
4473 'm': print the first SImode part unequal to -1 of X.
4474 'o': print integer X as if it's an unsigned 32bit word. */
4475
4476 void
4477 print_operand (FILE *file, rtx x, int code)
4478 {
4479 switch (code)
4480 {
4481 case 'C':
4482 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4483 return;
4484
4485 case 'D':
4486 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4487 return;
4488
4489 case 'J':
4490 if (GET_CODE (x) == SYMBOL_REF)
4491 {
4492 fprintf (file, "%s", ":tls_load:");
4493 output_addr_const (file, x);
4494 }
4495 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4496 {
4497 fprintf (file, "%s", ":tls_gdcall:");
4498 output_addr_const (file, XVECEXP (x, 0, 0));
4499 }
4500 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4501 {
4502 fprintf (file, "%s", ":tls_ldcall:");
4503 assemble_name (file, get_some_local_dynamic_name ());
4504 }
4505 else
4506 gcc_unreachable ();
4507 return;
4508
4509 case 'G':
4510 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4511 return;
4512
4513 case 'O':
4514 {
4515 struct s390_address ad;
4516 int ret;
4517
4518 gcc_assert (GET_CODE (x) == MEM);
4519 ret = s390_decompose_address (XEXP (x, 0), &ad);
4520 gcc_assert (ret);
4521 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4522 gcc_assert (!ad.indx);
4523
4524 if (ad.disp)
4525 output_addr_const (file, ad.disp);
4526 else
4527 fprintf (file, "0");
4528 }
4529 return;
4530
4531 case 'R':
4532 {
4533 struct s390_address ad;
4534 int ret;
4535
4536 gcc_assert (GET_CODE (x) == MEM);
4537 ret = s390_decompose_address (XEXP (x, 0), &ad);
4538 gcc_assert (ret);
4539 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4540 gcc_assert (!ad.indx);
4541
4542 if (ad.base)
4543 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4544 else
4545 fprintf (file, "0");
4546 }
4547 return;
4548
4549 case 'S':
4550 {
4551 struct s390_address ad;
4552 int ret;
4553
4554 gcc_assert (GET_CODE (x) == MEM);
4555 ret = s390_decompose_address (XEXP (x, 0), &ad);
4556 gcc_assert (ret);
4557 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4558 gcc_assert (!ad.indx);
4559
4560 if (ad.disp)
4561 output_addr_const (file, ad.disp);
4562 else
4563 fprintf (file, "0");
4564
4565 if (ad.base)
4566 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4567 }
4568 return;
4569
4570 case 'N':
4571 if (GET_CODE (x) == REG)
4572 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4573 else if (GET_CODE (x) == MEM)
4574 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4575 else
4576 gcc_unreachable ();
4577 break;
4578
4579 case 'M':
4580 if (GET_CODE (x) == REG)
4581 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4582 else if (GET_CODE (x) == MEM)
4583 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4584 else
4585 gcc_unreachable ();
4586 break;
4587
4588 case 'Y':
4589 print_shift_count_operand (file, x);
4590 return;
4591 }
4592
4593 switch (GET_CODE (x))
4594 {
4595 case REG:
4596 fprintf (file, "%s", reg_names[REGNO (x)]);
4597 break;
4598
4599 case MEM:
4600 output_address (XEXP (x, 0));
4601 break;
4602
4603 case CONST:
4604 case CODE_LABEL:
4605 case LABEL_REF:
4606 case SYMBOL_REF:
4607 output_addr_const (file, x);
4608 break;
4609
4610 case CONST_INT:
4611 if (code == 'b')
4612 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4613 else if (code == 'x')
4614 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4615 else if (code == 'h')
4616 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4617 else if (code == 'i')
4618 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4619 s390_extract_part (x, HImode, 0));
4620 else if (code == 'j')
4621 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4622 s390_extract_part (x, HImode, -1));
4623 else if (code == 'k')
4624 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4625 s390_extract_part (x, SImode, 0));
4626 else if (code == 'm')
4627 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4628 s390_extract_part (x, SImode, -1));
4629 else if (code == 'o')
4630 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4631 else
4632 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4633 break;
4634
4635 case CONST_DOUBLE:
4636 gcc_assert (GET_MODE (x) == VOIDmode);
4637 if (code == 'b')
4638 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4639 else if (code == 'x')
4640 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4641 else if (code == 'h')
4642 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4643 else
4644 gcc_unreachable ();
4645 break;
4646
4647 default:
4648 fatal_insn ("UNKNOWN in print_operand !?", x);
4649 break;
4650 }
4651 }
4652
4653 /* Target hook for assembling integer objects. We need to define it
4654 here to work a round a bug in some versions of GAS, which couldn't
4655 handle values smaller than INT_MIN when printed in decimal. */
4656
4657 static bool
4658 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4659 {
4660 if (size == 8 && aligned_p
4661 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4662 {
4663 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4664 INTVAL (x));
4665 return true;
4666 }
4667 return default_assemble_integer (x, size, aligned_p);
4668 }
4669
4670 /* Returns true if register REGNO is used for forming
4671 a memory address in expression X. */
4672
4673 static bool
4674 reg_used_in_mem_p (int regno, rtx x)
4675 {
4676 enum rtx_code code = GET_CODE (x);
4677 int i, j;
4678 const char *fmt;
4679
4680 if (code == MEM)
4681 {
4682 if (refers_to_regno_p (regno, regno+1,
4683 XEXP (x, 0), 0))
4684 return true;
4685 }
4686 else if (code == SET
4687 && GET_CODE (SET_DEST (x)) == PC)
4688 {
4689 if (refers_to_regno_p (regno, regno+1,
4690 SET_SRC (x), 0))
4691 return true;
4692 }
4693
4694 fmt = GET_RTX_FORMAT (code);
4695 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4696 {
4697 if (fmt[i] == 'e'
4698 && reg_used_in_mem_p (regno, XEXP (x, i)))
4699 return true;
4700
4701 else if (fmt[i] == 'E')
4702 for (j = 0; j < XVECLEN (x, i); j++)
4703 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4704 return true;
4705 }
4706 return false;
4707 }
4708
4709 /* Returns true if expression DEP_RTX sets an address register
4710 used by instruction INSN to address memory. */
4711
4712 static bool
4713 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4714 {
4715 rtx target, pat;
4716
4717 if (GET_CODE (dep_rtx) == INSN)
4718 dep_rtx = PATTERN (dep_rtx);
4719
4720 if (GET_CODE (dep_rtx) == SET)
4721 {
4722 target = SET_DEST (dep_rtx);
4723 if (GET_CODE (target) == STRICT_LOW_PART)
4724 target = XEXP (target, 0);
4725 while (GET_CODE (target) == SUBREG)
4726 target = SUBREG_REG (target);
4727
4728 if (GET_CODE (target) == REG)
4729 {
4730 int regno = REGNO (target);
4731
4732 if (s390_safe_attr_type (insn) == TYPE_LA)
4733 {
4734 pat = PATTERN (insn);
4735 if (GET_CODE (pat) == PARALLEL)
4736 {
4737 gcc_assert (XVECLEN (pat, 0) == 2);
4738 pat = XVECEXP (pat, 0, 0);
4739 }
4740 gcc_assert (GET_CODE (pat) == SET);
4741 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4742 }
4743 else if (get_attr_atype (insn) == ATYPE_AGEN)
4744 return reg_used_in_mem_p (regno, PATTERN (insn));
4745 }
4746 }
4747 return false;
4748 }
4749
4750 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4751
4752 int
4753 s390_agen_dep_p (rtx dep_insn, rtx insn)
4754 {
4755 rtx dep_rtx = PATTERN (dep_insn);
4756 int i;
4757
4758 if (GET_CODE (dep_rtx) == SET
4759 && addr_generation_dependency_p (dep_rtx, insn))
4760 return 1;
4761 else if (GET_CODE (dep_rtx) == PARALLEL)
4762 {
4763 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4764 {
4765 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4766 return 1;
4767 }
4768 }
4769 return 0;
4770 }
4771
4772 /* A C statement (sans semicolon) to update the integer scheduling priority
4773 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4774 reduce the priority to execute INSN later. Do not define this macro if
4775 you do not need to adjust the scheduling priorities of insns.
4776
4777 A STD instruction should be scheduled earlier,
4778 in order to use the bypass. */
4779
4780 static int
4781 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4782 {
4783 if (! INSN_P (insn))
4784 return priority;
4785
4786 if (s390_tune != PROCESSOR_2084_Z990
4787 && s390_tune != PROCESSOR_2094_Z9_109)
4788 return priority;
4789
4790 switch (s390_safe_attr_type (insn))
4791 {
4792 case TYPE_FSTOREDF:
4793 case TYPE_FSTORESF:
4794 priority = priority << 3;
4795 break;
4796 case TYPE_STORE:
4797 case TYPE_STM:
4798 priority = priority << 1;
4799 break;
4800 default:
4801 break;
4802 }
4803 return priority;
4804 }
4805
4806 /* The number of instructions that can be issued per cycle. */
4807
4808 static int
4809 s390_issue_rate (void)
4810 {
4811 if (s390_tune == PROCESSOR_2084_Z990
4812 || s390_tune == PROCESSOR_2094_Z9_109)
4813 return 3;
4814 return 1;
4815 }
4816
4817 static int
4818 s390_first_cycle_multipass_dfa_lookahead (void)
4819 {
4820 return 4;
4821 }
4822
4823
4824 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4825 Fix up MEMs as required. */
4826
4827 static void
4828 annotate_constant_pool_refs (rtx *x)
4829 {
4830 int i, j;
4831 const char *fmt;
4832
4833 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4834 || !CONSTANT_POOL_ADDRESS_P (*x));
4835
4836 /* Literal pool references can only occur inside a MEM ... */
4837 if (GET_CODE (*x) == MEM)
4838 {
4839 rtx memref = XEXP (*x, 0);
4840
4841 if (GET_CODE (memref) == SYMBOL_REF
4842 && CONSTANT_POOL_ADDRESS_P (memref))
4843 {
4844 rtx base = cfun->machine->base_reg;
4845 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4846 UNSPEC_LTREF);
4847
4848 *x = replace_equiv_address (*x, addr);
4849 return;
4850 }
4851
4852 if (GET_CODE (memref) == CONST
4853 && GET_CODE (XEXP (memref, 0)) == PLUS
4854 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4855 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4856 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4857 {
4858 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4859 rtx sym = XEXP (XEXP (memref, 0), 0);
4860 rtx base = cfun->machine->base_reg;
4861 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4862 UNSPEC_LTREF);
4863
4864 *x = replace_equiv_address (*x, plus_constant (addr, off));
4865 return;
4866 }
4867 }
4868
4869 /* ... or a load-address type pattern. */
4870 if (GET_CODE (*x) == SET)
4871 {
4872 rtx addrref = SET_SRC (*x);
4873
4874 if (GET_CODE (addrref) == SYMBOL_REF
4875 && CONSTANT_POOL_ADDRESS_P (addrref))
4876 {
4877 rtx base = cfun->machine->base_reg;
4878 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4879 UNSPEC_LTREF);
4880
4881 SET_SRC (*x) = addr;
4882 return;
4883 }
4884
4885 if (GET_CODE (addrref) == CONST
4886 && GET_CODE (XEXP (addrref, 0)) == PLUS
4887 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4888 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4889 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4890 {
4891 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4892 rtx sym = XEXP (XEXP (addrref, 0), 0);
4893 rtx base = cfun->machine->base_reg;
4894 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4895 UNSPEC_LTREF);
4896
4897 SET_SRC (*x) = plus_constant (addr, off);
4898 return;
4899 }
4900 }
4901
4902 /* Annotate LTREL_BASE as well. */
4903 if (GET_CODE (*x) == UNSPEC
4904 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4905 {
4906 rtx base = cfun->machine->base_reg;
4907 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4908 UNSPEC_LTREL_BASE);
4909 return;
4910 }
4911
4912 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4913 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4914 {
4915 if (fmt[i] == 'e')
4916 {
4917 annotate_constant_pool_refs (&XEXP (*x, i));
4918 }
4919 else if (fmt[i] == 'E')
4920 {
4921 for (j = 0; j < XVECLEN (*x, i); j++)
4922 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
4923 }
4924 }
4925 }
4926
4927 /* Split all branches that exceed the maximum distance.
4928 Returns true if this created a new literal pool entry. */
4929
4930 static int
4931 s390_split_branches (void)
4932 {
4933 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
4934 int new_literal = 0, ret;
4935 rtx insn, pat, tmp, target;
4936 rtx *label;
4937
4938 /* We need correct insn addresses. */
4939
4940 shorten_branches (get_insns ());
4941
4942 /* Find all branches that exceed 64KB, and split them. */
4943
4944 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4945 {
4946 if (GET_CODE (insn) != JUMP_INSN)
4947 continue;
4948
4949 pat = PATTERN (insn);
4950 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
4951 pat = XVECEXP (pat, 0, 0);
4952 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
4953 continue;
4954
4955 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
4956 {
4957 label = &SET_SRC (pat);
4958 }
4959 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
4960 {
4961 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
4962 label = &XEXP (SET_SRC (pat), 1);
4963 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
4964 label = &XEXP (SET_SRC (pat), 2);
4965 else
4966 continue;
4967 }
4968 else
4969 continue;
4970
4971 if (get_attr_length (insn) <= 4)
4972 continue;
4973
4974 /* We are going to use the return register as scratch register,
4975 make sure it will be saved/restored by the prologue/epilogue. */
4976 cfun_frame_layout.save_return_addr_p = 1;
4977
4978 if (!flag_pic)
4979 {
4980 new_literal = 1;
4981 tmp = force_const_mem (Pmode, *label);
4982 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
4983 INSN_ADDRESSES_NEW (tmp, -1);
4984 annotate_constant_pool_refs (&PATTERN (tmp));
4985
4986 target = temp_reg;
4987 }
4988 else
4989 {
4990 new_literal = 1;
4991 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
4992 UNSPEC_LTREL_OFFSET);
4993 target = gen_rtx_CONST (Pmode, target);
4994 target = force_const_mem (Pmode, target);
4995 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
4996 INSN_ADDRESSES_NEW (tmp, -1);
4997 annotate_constant_pool_refs (&PATTERN (tmp));
4998
4999 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5000 cfun->machine->base_reg),
5001 UNSPEC_LTREL_BASE);
5002 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5003 }
5004
5005 ret = validate_change (insn, label, target, 0);
5006 gcc_assert (ret);
5007 }
5008
5009 return new_literal;
5010 }
5011
5012
5013 /* Find an annotated literal pool symbol referenced in RTX X,
5014 and store it at REF. Will abort if X contains references to
5015 more than one such pool symbol; multiple references to the same
5016 symbol are allowed, however.
5017
5018 The rtx pointed to by REF must be initialized to NULL_RTX
5019 by the caller before calling this routine. */
5020
5021 static void
5022 find_constant_pool_ref (rtx x, rtx *ref)
5023 {
5024 int i, j;
5025 const char *fmt;
5026
5027 /* Ignore LTREL_BASE references. */
5028 if (GET_CODE (x) == UNSPEC
5029 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5030 return;
5031 /* Likewise POOL_ENTRY insns. */
5032 if (GET_CODE (x) == UNSPEC_VOLATILE
5033 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5034 return;
5035
5036 gcc_assert (GET_CODE (x) != SYMBOL_REF
5037 || !CONSTANT_POOL_ADDRESS_P (x));
5038
5039 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5040 {
5041 rtx sym = XVECEXP (x, 0, 0);
5042 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5043 && CONSTANT_POOL_ADDRESS_P (sym));
5044
5045 if (*ref == NULL_RTX)
5046 *ref = sym;
5047 else
5048 gcc_assert (*ref == sym);
5049
5050 return;
5051 }
5052
5053 fmt = GET_RTX_FORMAT (GET_CODE (x));
5054 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5055 {
5056 if (fmt[i] == 'e')
5057 {
5058 find_constant_pool_ref (XEXP (x, i), ref);
5059 }
5060 else if (fmt[i] == 'E')
5061 {
5062 for (j = 0; j < XVECLEN (x, i); j++)
5063 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5064 }
5065 }
5066 }
5067
5068 /* Replace every reference to the annotated literal pool
5069 symbol REF in X by its base plus OFFSET. */
5070
5071 static void
5072 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5073 {
5074 int i, j;
5075 const char *fmt;
5076
5077 gcc_assert (*x != ref);
5078
5079 if (GET_CODE (*x) == UNSPEC
5080 && XINT (*x, 1) == UNSPEC_LTREF
5081 && XVECEXP (*x, 0, 0) == ref)
5082 {
5083 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5084 return;
5085 }
5086
5087 if (GET_CODE (*x) == PLUS
5088 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5089 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5090 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5091 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5092 {
5093 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5094 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5095 return;
5096 }
5097
5098 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5099 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5100 {
5101 if (fmt[i] == 'e')
5102 {
5103 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5104 }
5105 else if (fmt[i] == 'E')
5106 {
5107 for (j = 0; j < XVECLEN (*x, i); j++)
5108 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5109 }
5110 }
5111 }
5112
5113 /* Check whether X contains an UNSPEC_LTREL_BASE.
5114 Return its constant pool symbol if found, NULL_RTX otherwise. */
5115
5116 static rtx
5117 find_ltrel_base (rtx x)
5118 {
5119 int i, j;
5120 const char *fmt;
5121
5122 if (GET_CODE (x) == UNSPEC
5123 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5124 return XVECEXP (x, 0, 0);
5125
5126 fmt = GET_RTX_FORMAT (GET_CODE (x));
5127 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5128 {
5129 if (fmt[i] == 'e')
5130 {
5131 rtx fnd = find_ltrel_base (XEXP (x, i));
5132 if (fnd)
5133 return fnd;
5134 }
5135 else if (fmt[i] == 'E')
5136 {
5137 for (j = 0; j < XVECLEN (x, i); j++)
5138 {
5139 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5140 if (fnd)
5141 return fnd;
5142 }
5143 }
5144 }
5145
5146 return NULL_RTX;
5147 }
5148
5149 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5150
5151 static void
5152 replace_ltrel_base (rtx *x)
5153 {
5154 int i, j;
5155 const char *fmt;
5156
5157 if (GET_CODE (*x) == UNSPEC
5158 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5159 {
5160 *x = XVECEXP (*x, 0, 1);
5161 return;
5162 }
5163
5164 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5165 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5166 {
5167 if (fmt[i] == 'e')
5168 {
5169 replace_ltrel_base (&XEXP (*x, i));
5170 }
5171 else if (fmt[i] == 'E')
5172 {
5173 for (j = 0; j < XVECLEN (*x, i); j++)
5174 replace_ltrel_base (&XVECEXP (*x, i, j));
5175 }
5176 }
5177 }
5178
5179
5180 /* We keep a list of constants which we have to add to internal
5181 constant tables in the middle of large functions. */
5182
5183 #define NR_C_MODES 7
5184 enum machine_mode constant_modes[NR_C_MODES] =
5185 {
5186 TImode,
5187 DFmode, DImode,
5188 SFmode, SImode,
5189 HImode,
5190 QImode
5191 };
5192
5193 struct constant
5194 {
5195 struct constant *next;
5196 rtx value;
5197 rtx label;
5198 };
5199
5200 struct constant_pool
5201 {
5202 struct constant_pool *next;
5203 rtx first_insn;
5204 rtx pool_insn;
5205 bitmap insns;
5206
5207 struct constant *constants[NR_C_MODES];
5208 struct constant *execute;
5209 rtx label;
5210 int size;
5211 };
5212
5213 /* Allocate new constant_pool structure. */
5214
5215 static struct constant_pool *
5216 s390_alloc_pool (void)
5217 {
5218 struct constant_pool *pool;
5219 int i;
5220
5221 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5222 pool->next = NULL;
5223 for (i = 0; i < NR_C_MODES; i++)
5224 pool->constants[i] = NULL;
5225
5226 pool->execute = NULL;
5227 pool->label = gen_label_rtx ();
5228 pool->first_insn = NULL_RTX;
5229 pool->pool_insn = NULL_RTX;
5230 pool->insns = BITMAP_ALLOC (NULL);
5231 pool->size = 0;
5232
5233 return pool;
5234 }
5235
5236 /* Create new constant pool covering instructions starting at INSN
5237 and chain it to the end of POOL_LIST. */
5238
5239 static struct constant_pool *
5240 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5241 {
5242 struct constant_pool *pool, **prev;
5243
5244 pool = s390_alloc_pool ();
5245 pool->first_insn = insn;
5246
5247 for (prev = pool_list; *prev; prev = &(*prev)->next)
5248 ;
5249 *prev = pool;
5250
5251 return pool;
5252 }
5253
5254 /* End range of instructions covered by POOL at INSN and emit
5255 placeholder insn representing the pool. */
5256
5257 static void
5258 s390_end_pool (struct constant_pool *pool, rtx insn)
5259 {
5260 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5261
5262 if (!insn)
5263 insn = get_last_insn ();
5264
5265 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5266 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5267 }
5268
5269 /* Add INSN to the list of insns covered by POOL. */
5270
5271 static void
5272 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5273 {
5274 bitmap_set_bit (pool->insns, INSN_UID (insn));
5275 }
5276
5277 /* Return pool out of POOL_LIST that covers INSN. */
5278
5279 static struct constant_pool *
5280 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5281 {
5282 struct constant_pool *pool;
5283
5284 for (pool = pool_list; pool; pool = pool->next)
5285 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5286 break;
5287
5288 return pool;
5289 }
5290
5291 /* Add constant VAL of mode MODE to the constant pool POOL. */
5292
5293 static void
5294 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5295 {
5296 struct constant *c;
5297 int i;
5298
5299 for (i = 0; i < NR_C_MODES; i++)
5300 if (constant_modes[i] == mode)
5301 break;
5302 gcc_assert (i != NR_C_MODES);
5303
5304 for (c = pool->constants[i]; c != NULL; c = c->next)
5305 if (rtx_equal_p (val, c->value))
5306 break;
5307
5308 if (c == NULL)
5309 {
5310 c = (struct constant *) xmalloc (sizeof *c);
5311 c->value = val;
5312 c->label = gen_label_rtx ();
5313 c->next = pool->constants[i];
5314 pool->constants[i] = c;
5315 pool->size += GET_MODE_SIZE (mode);
5316 }
5317 }
5318
5319 /* Find constant VAL of mode MODE in the constant pool POOL.
5320 Return an RTX describing the distance from the start of
5321 the pool to the location of the new constant. */
5322
5323 static rtx
5324 s390_find_constant (struct constant_pool *pool, rtx val,
5325 enum machine_mode mode)
5326 {
5327 struct constant *c;
5328 rtx offset;
5329 int i;
5330
5331 for (i = 0; i < NR_C_MODES; i++)
5332 if (constant_modes[i] == mode)
5333 break;
5334 gcc_assert (i != NR_C_MODES);
5335
5336 for (c = pool->constants[i]; c != NULL; c = c->next)
5337 if (rtx_equal_p (val, c->value))
5338 break;
5339
5340 gcc_assert (c);
5341
5342 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5343 gen_rtx_LABEL_REF (Pmode, pool->label));
5344 offset = gen_rtx_CONST (Pmode, offset);
5345 return offset;
5346 }
5347
5348 /* Check whether INSN is an execute. Return the label_ref to its
5349 execute target template if so, NULL_RTX otherwise. */
5350
5351 static rtx
5352 s390_execute_label (rtx insn)
5353 {
5354 if (GET_CODE (insn) == INSN
5355 && GET_CODE (PATTERN (insn)) == PARALLEL
5356 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5357 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5358 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5359
5360 return NULL_RTX;
5361 }
5362
5363 /* Add execute target for INSN to the constant pool POOL. */
5364
5365 static void
5366 s390_add_execute (struct constant_pool *pool, rtx insn)
5367 {
5368 struct constant *c;
5369
5370 for (c = pool->execute; c != NULL; c = c->next)
5371 if (INSN_UID (insn) == INSN_UID (c->value))
5372 break;
5373
5374 if (c == NULL)
5375 {
5376 c = (struct constant *) xmalloc (sizeof *c);
5377 c->value = insn;
5378 c->label = gen_label_rtx ();
5379 c->next = pool->execute;
5380 pool->execute = c;
5381 pool->size += 6;
5382 }
5383 }
5384
5385 /* Find execute target for INSN in the constant pool POOL.
5386 Return an RTX describing the distance from the start of
5387 the pool to the location of the execute target. */
5388
5389 static rtx
5390 s390_find_execute (struct constant_pool *pool, rtx insn)
5391 {
5392 struct constant *c;
5393 rtx offset;
5394
5395 for (c = pool->execute; c != NULL; c = c->next)
5396 if (INSN_UID (insn) == INSN_UID (c->value))
5397 break;
5398
5399 gcc_assert (c);
5400
5401 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5402 gen_rtx_LABEL_REF (Pmode, pool->label));
5403 offset = gen_rtx_CONST (Pmode, offset);
5404 return offset;
5405 }
5406
5407 /* For an execute INSN, extract the execute target template. */
5408
5409 static rtx
5410 s390_execute_target (rtx insn)
5411 {
5412 rtx pattern = PATTERN (insn);
5413 gcc_assert (s390_execute_label (insn));
5414
5415 if (XVECLEN (pattern, 0) == 2)
5416 {
5417 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5418 }
5419 else
5420 {
5421 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5422 int i;
5423
5424 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5425 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5426
5427 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5428 }
5429
5430 return pattern;
5431 }
5432
5433 /* Indicate that INSN cannot be duplicated. This is the case for
5434 execute insns that carry a unique label. */
5435
5436 static bool
5437 s390_cannot_copy_insn_p (rtx insn)
5438 {
5439 rtx label = s390_execute_label (insn);
5440 return label && label != const0_rtx;
5441 }
5442
5443 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5444 do not emit the pool base label. */
5445
5446 static void
5447 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5448 {
5449 struct constant *c;
5450 rtx insn = pool->pool_insn;
5451 int i;
5452
5453 /* Switch to rodata section. */
5454 if (TARGET_CPU_ZARCH)
5455 {
5456 insn = emit_insn_after (gen_pool_section_start (), insn);
5457 INSN_ADDRESSES_NEW (insn, -1);
5458 }
5459
5460 /* Ensure minimum pool alignment. */
5461 if (TARGET_CPU_ZARCH)
5462 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5463 else
5464 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5465 INSN_ADDRESSES_NEW (insn, -1);
5466
5467 /* Emit pool base label. */
5468 if (!remote_label)
5469 {
5470 insn = emit_label_after (pool->label, insn);
5471 INSN_ADDRESSES_NEW (insn, -1);
5472 }
5473
5474 /* Dump constants in descending alignment requirement order,
5475 ensuring proper alignment for every constant. */
5476 for (i = 0; i < NR_C_MODES; i++)
5477 for (c = pool->constants[i]; c; c = c->next)
5478 {
5479 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5480 rtx value = c->value;
5481 if (GET_CODE (value) == CONST
5482 && GET_CODE (XEXP (value, 0)) == UNSPEC
5483 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5484 && XVECLEN (XEXP (value, 0), 0) == 1)
5485 {
5486 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5487 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5488 value = gen_rtx_CONST (VOIDmode, value);
5489 }
5490
5491 insn = emit_label_after (c->label, insn);
5492 INSN_ADDRESSES_NEW (insn, -1);
5493
5494 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5495 gen_rtvec (1, value),
5496 UNSPECV_POOL_ENTRY);
5497 insn = emit_insn_after (value, insn);
5498 INSN_ADDRESSES_NEW (insn, -1);
5499 }
5500
5501 /* Ensure minimum alignment for instructions. */
5502 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5503 INSN_ADDRESSES_NEW (insn, -1);
5504
5505 /* Output in-pool execute template insns. */
5506 for (c = pool->execute; c; c = c->next)
5507 {
5508 insn = emit_label_after (c->label, insn);
5509 INSN_ADDRESSES_NEW (insn, -1);
5510
5511 insn = emit_insn_after (s390_execute_target (c->value), insn);
5512 INSN_ADDRESSES_NEW (insn, -1);
5513 }
5514
5515 /* Switch back to previous section. */
5516 if (TARGET_CPU_ZARCH)
5517 {
5518 insn = emit_insn_after (gen_pool_section_end (), insn);
5519 INSN_ADDRESSES_NEW (insn, -1);
5520 }
5521
5522 insn = emit_barrier_after (insn);
5523 INSN_ADDRESSES_NEW (insn, -1);
5524
5525 /* Remove placeholder insn. */
5526 remove_insn (pool->pool_insn);
5527 }
5528
5529 /* Free all memory used by POOL. */
5530
5531 static void
5532 s390_free_pool (struct constant_pool *pool)
5533 {
5534 struct constant *c, *next;
5535 int i;
5536
5537 for (i = 0; i < NR_C_MODES; i++)
5538 for (c = pool->constants[i]; c; c = next)
5539 {
5540 next = c->next;
5541 free (c);
5542 }
5543
5544 for (c = pool->execute; c; c = next)
5545 {
5546 next = c->next;
5547 free (c);
5548 }
5549
5550 BITMAP_FREE (pool->insns);
5551 free (pool);
5552 }
5553
5554
5555 /* Collect main literal pool. Return NULL on overflow. */
5556
5557 static struct constant_pool *
5558 s390_mainpool_start (void)
5559 {
5560 struct constant_pool *pool;
5561 rtx insn;
5562
5563 pool = s390_alloc_pool ();
5564
5565 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5566 {
5567 if (GET_CODE (insn) == INSN
5568 && GET_CODE (PATTERN (insn)) == SET
5569 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5570 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5571 {
5572 gcc_assert (!pool->pool_insn);
5573 pool->pool_insn = insn;
5574 }
5575
5576 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5577 {
5578 s390_add_execute (pool, insn);
5579 }
5580 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5581 {
5582 rtx pool_ref = NULL_RTX;
5583 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5584 if (pool_ref)
5585 {
5586 rtx constant = get_pool_constant (pool_ref);
5587 enum machine_mode mode = get_pool_mode (pool_ref);
5588 s390_add_constant (pool, constant, mode);
5589 }
5590 }
5591 }
5592
5593 gcc_assert (pool->pool_insn || pool->size == 0);
5594
5595 if (pool->size >= 4096)
5596 {
5597 /* We're going to chunkify the pool, so remove the main
5598 pool placeholder insn. */
5599 remove_insn (pool->pool_insn);
5600
5601 s390_free_pool (pool);
5602 pool = NULL;
5603 }
5604
5605 return pool;
5606 }
5607
5608 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5609 Modify the current function to output the pool constants as well as
5610 the pool register setup instruction. */
5611
5612 static void
5613 s390_mainpool_finish (struct constant_pool *pool)
5614 {
5615 rtx base_reg = cfun->machine->base_reg;
5616 rtx insn;
5617
5618 /* If the pool is empty, we're done. */
5619 if (pool->size == 0)
5620 {
5621 /* We don't actually need a base register after all. */
5622 cfun->machine->base_reg = NULL_RTX;
5623
5624 if (pool->pool_insn)
5625 remove_insn (pool->pool_insn);
5626 s390_free_pool (pool);
5627 return;
5628 }
5629
5630 /* We need correct insn addresses. */
5631 shorten_branches (get_insns ());
5632
5633 /* On zSeries, we use a LARL to load the pool register. The pool is
5634 located in the .rodata section, so we emit it after the function. */
5635 if (TARGET_CPU_ZARCH)
5636 {
5637 insn = gen_main_base_64 (base_reg, pool->label);
5638 insn = emit_insn_after (insn, pool->pool_insn);
5639 INSN_ADDRESSES_NEW (insn, -1);
5640 remove_insn (pool->pool_insn);
5641
5642 insn = get_last_insn ();
5643 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5644 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5645
5646 s390_dump_pool (pool, 0);
5647 }
5648
5649 /* On S/390, if the total size of the function's code plus literal pool
5650 does not exceed 4096 bytes, we use BASR to set up a function base
5651 pointer, and emit the literal pool at the end of the function. */
5652 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5653 + pool->size + 8 /* alignment slop */ < 4096)
5654 {
5655 insn = gen_main_base_31_small (base_reg, pool->label);
5656 insn = emit_insn_after (insn, pool->pool_insn);
5657 INSN_ADDRESSES_NEW (insn, -1);
5658 remove_insn (pool->pool_insn);
5659
5660 insn = emit_label_after (pool->label, insn);
5661 INSN_ADDRESSES_NEW (insn, -1);
5662
5663 insn = get_last_insn ();
5664 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5665 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5666
5667 s390_dump_pool (pool, 1);
5668 }
5669
5670 /* Otherwise, we emit an inline literal pool and use BASR to branch
5671 over it, setting up the pool register at the same time. */
5672 else
5673 {
5674 rtx pool_end = gen_label_rtx ();
5675
5676 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5677 insn = emit_insn_after (insn, pool->pool_insn);
5678 INSN_ADDRESSES_NEW (insn, -1);
5679 remove_insn (pool->pool_insn);
5680
5681 insn = emit_label_after (pool->label, insn);
5682 INSN_ADDRESSES_NEW (insn, -1);
5683
5684 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5685 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5686
5687 insn = emit_label_after (pool_end, pool->pool_insn);
5688 INSN_ADDRESSES_NEW (insn, -1);
5689
5690 s390_dump_pool (pool, 1);
5691 }
5692
5693
5694 /* Replace all literal pool references. */
5695
5696 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5697 {
5698 if (INSN_P (insn))
5699 replace_ltrel_base (&PATTERN (insn));
5700
5701 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5702 {
5703 rtx addr, pool_ref = NULL_RTX;
5704 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5705 if (pool_ref)
5706 {
5707 if (s390_execute_label (insn))
5708 addr = s390_find_execute (pool, insn);
5709 else
5710 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5711 get_pool_mode (pool_ref));
5712
5713 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5714 INSN_CODE (insn) = -1;
5715 }
5716 }
5717 }
5718
5719
5720 /* Free the pool. */
5721 s390_free_pool (pool);
5722 }
5723
5724 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5725 We have decided we cannot use this pool, so revert all changes
5726 to the current function that were done by s390_mainpool_start. */
5727 static void
5728 s390_mainpool_cancel (struct constant_pool *pool)
5729 {
5730 /* We didn't actually change the instruction stream, so simply
5731 free the pool memory. */
5732 s390_free_pool (pool);
5733 }
5734
5735
5736 /* Chunkify the literal pool. */
5737
5738 #define S390_POOL_CHUNK_MIN 0xc00
5739 #define S390_POOL_CHUNK_MAX 0xe00
5740
5741 static struct constant_pool *
5742 s390_chunkify_start (void)
5743 {
5744 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5745 int extra_size = 0;
5746 bitmap far_labels;
5747 rtx pending_ltrel = NULL_RTX;
5748 rtx insn;
5749
5750 rtx (*gen_reload_base) (rtx, rtx) =
5751 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5752
5753
5754 /* We need correct insn addresses. */
5755
5756 shorten_branches (get_insns ());
5757
5758 /* Scan all insns and move literals to pool chunks. */
5759
5760 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5761 {
5762 /* Check for pending LTREL_BASE. */
5763 if (INSN_P (insn))
5764 {
5765 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5766 if (ltrel_base)
5767 {
5768 gcc_assert (ltrel_base == pending_ltrel);
5769 pending_ltrel = NULL_RTX;
5770 }
5771 }
5772
5773 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5774 {
5775 if (!curr_pool)
5776 curr_pool = s390_start_pool (&pool_list, insn);
5777
5778 s390_add_execute (curr_pool, insn);
5779 s390_add_pool_insn (curr_pool, insn);
5780 }
5781 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5782 {
5783 rtx pool_ref = NULL_RTX;
5784 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5785 if (pool_ref)
5786 {
5787 rtx constant = get_pool_constant (pool_ref);
5788 enum machine_mode mode = get_pool_mode (pool_ref);
5789
5790 if (!curr_pool)
5791 curr_pool = s390_start_pool (&pool_list, insn);
5792
5793 s390_add_constant (curr_pool, constant, mode);
5794 s390_add_pool_insn (curr_pool, insn);
5795
5796 /* Don't split the pool chunk between a LTREL_OFFSET load
5797 and the corresponding LTREL_BASE. */
5798 if (GET_CODE (constant) == CONST
5799 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5800 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5801 {
5802 gcc_assert (!pending_ltrel);
5803 pending_ltrel = pool_ref;
5804 }
5805 }
5806 }
5807
5808 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5809 {
5810 if (curr_pool)
5811 s390_add_pool_insn (curr_pool, insn);
5812 /* An LTREL_BASE must follow within the same basic block. */
5813 gcc_assert (!pending_ltrel);
5814 }
5815
5816 if (!curr_pool
5817 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5818 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5819 continue;
5820
5821 if (TARGET_CPU_ZARCH)
5822 {
5823 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5824 continue;
5825
5826 s390_end_pool (curr_pool, NULL_RTX);
5827 curr_pool = NULL;
5828 }
5829 else
5830 {
5831 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5832 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5833 + extra_size;
5834
5835 /* We will later have to insert base register reload insns.
5836 Those will have an effect on code size, which we need to
5837 consider here. This calculation makes rather pessimistic
5838 worst-case assumptions. */
5839 if (GET_CODE (insn) == CODE_LABEL)
5840 extra_size += 6;
5841
5842 if (chunk_size < S390_POOL_CHUNK_MIN
5843 && curr_pool->size < S390_POOL_CHUNK_MIN)
5844 continue;
5845
5846 /* Pool chunks can only be inserted after BARRIERs ... */
5847 if (GET_CODE (insn) == BARRIER)
5848 {
5849 s390_end_pool (curr_pool, insn);
5850 curr_pool = NULL;
5851 extra_size = 0;
5852 }
5853
5854 /* ... so if we don't find one in time, create one. */
5855 else if ((chunk_size > S390_POOL_CHUNK_MAX
5856 || curr_pool->size > S390_POOL_CHUNK_MAX))
5857 {
5858 rtx label, jump, barrier;
5859
5860 /* We can insert the barrier only after a 'real' insn. */
5861 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5862 continue;
5863 if (get_attr_length (insn) == 0)
5864 continue;
5865
5866 /* Don't separate LTREL_BASE from the corresponding
5867 LTREL_OFFSET load. */
5868 if (pending_ltrel)
5869 continue;
5870
5871 label = gen_label_rtx ();
5872 jump = emit_jump_insn_after (gen_jump (label), insn);
5873 barrier = emit_barrier_after (jump);
5874 insn = emit_label_after (label, barrier);
5875 JUMP_LABEL (jump) = label;
5876 LABEL_NUSES (label) = 1;
5877
5878 INSN_ADDRESSES_NEW (jump, -1);
5879 INSN_ADDRESSES_NEW (barrier, -1);
5880 INSN_ADDRESSES_NEW (insn, -1);
5881
5882 s390_end_pool (curr_pool, barrier);
5883 curr_pool = NULL;
5884 extra_size = 0;
5885 }
5886 }
5887 }
5888
5889 if (curr_pool)
5890 s390_end_pool (curr_pool, NULL_RTX);
5891 gcc_assert (!pending_ltrel);
5892
5893 /* Find all labels that are branched into
5894 from an insn belonging to a different chunk. */
5895
5896 far_labels = BITMAP_ALLOC (NULL);
5897
5898 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5899 {
5900 /* Labels marked with LABEL_PRESERVE_P can be target
5901 of non-local jumps, so we have to mark them.
5902 The same holds for named labels.
5903
5904 Don't do that, however, if it is the label before
5905 a jump table. */
5906
5907 if (GET_CODE (insn) == CODE_LABEL
5908 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5909 {
5910 rtx vec_insn = next_real_insn (insn);
5911 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5912 PATTERN (vec_insn) : NULL_RTX;
5913 if (!vec_pat
5914 || !(GET_CODE (vec_pat) == ADDR_VEC
5915 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5916 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
5917 }
5918
5919 /* If we have a direct jump (conditional or unconditional)
5920 or a casesi jump, check all potential targets. */
5921 else if (GET_CODE (insn) == JUMP_INSN)
5922 {
5923 rtx pat = PATTERN (insn);
5924 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5925 pat = XVECEXP (pat, 0, 0);
5926
5927 if (GET_CODE (pat) == SET)
5928 {
5929 rtx label = JUMP_LABEL (insn);
5930 if (label)
5931 {
5932 if (s390_find_pool (pool_list, label)
5933 != s390_find_pool (pool_list, insn))
5934 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5935 }
5936 }
5937 else if (GET_CODE (pat) == PARALLEL
5938 && XVECLEN (pat, 0) == 2
5939 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
5940 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
5941 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
5942 {
5943 /* Find the jump table used by this casesi jump. */
5944 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
5945 rtx vec_insn = next_real_insn (vec_label);
5946 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5947 PATTERN (vec_insn) : NULL_RTX;
5948 if (vec_pat
5949 && (GET_CODE (vec_pat) == ADDR_VEC
5950 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5951 {
5952 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
5953
5954 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
5955 {
5956 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
5957
5958 if (s390_find_pool (pool_list, label)
5959 != s390_find_pool (pool_list, insn))
5960 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5961 }
5962 }
5963 }
5964 }
5965 }
5966
5967 /* Insert base register reload insns before every pool. */
5968
5969 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5970 {
5971 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
5972 curr_pool->label);
5973 rtx insn = curr_pool->first_insn;
5974 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
5975 }
5976
5977 /* Insert base register reload insns at every far label. */
5978
5979 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5980 if (GET_CODE (insn) == CODE_LABEL
5981 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
5982 {
5983 struct constant_pool *pool = s390_find_pool (pool_list, insn);
5984 if (pool)
5985 {
5986 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
5987 pool->label);
5988 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
5989 }
5990 }
5991
5992
5993 BITMAP_FREE (far_labels);
5994
5995
5996 /* Recompute insn addresses. */
5997
5998 init_insn_lengths ();
5999 shorten_branches (get_insns ());
6000
6001 return pool_list;
6002 }
6003
6004 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6005 After we have decided to use this list, finish implementing
6006 all changes to the current function as required. */
6007
6008 static void
6009 s390_chunkify_finish (struct constant_pool *pool_list)
6010 {
6011 struct constant_pool *curr_pool = NULL;
6012 rtx insn;
6013
6014
6015 /* Replace all literal pool references. */
6016
6017 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6018 {
6019 if (INSN_P (insn))
6020 replace_ltrel_base (&PATTERN (insn));
6021
6022 curr_pool = s390_find_pool (pool_list, insn);
6023 if (!curr_pool)
6024 continue;
6025
6026 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6027 {
6028 rtx addr, pool_ref = NULL_RTX;
6029 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6030 if (pool_ref)
6031 {
6032 if (s390_execute_label (insn))
6033 addr = s390_find_execute (curr_pool, insn);
6034 else
6035 addr = s390_find_constant (curr_pool,
6036 get_pool_constant (pool_ref),
6037 get_pool_mode (pool_ref));
6038
6039 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6040 INSN_CODE (insn) = -1;
6041 }
6042 }
6043 }
6044
6045 /* Dump out all literal pools. */
6046
6047 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6048 s390_dump_pool (curr_pool, 0);
6049
6050 /* Free pool list. */
6051
6052 while (pool_list)
6053 {
6054 struct constant_pool *next = pool_list->next;
6055 s390_free_pool (pool_list);
6056 pool_list = next;
6057 }
6058 }
6059
6060 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6061 We have decided we cannot use this list, so revert all changes
6062 to the current function that were done by s390_chunkify_start. */
6063
6064 static void
6065 s390_chunkify_cancel (struct constant_pool *pool_list)
6066 {
6067 struct constant_pool *curr_pool = NULL;
6068 rtx insn;
6069
6070 /* Remove all pool placeholder insns. */
6071
6072 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6073 {
6074 /* Did we insert an extra barrier? Remove it. */
6075 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6076 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6077 rtx label = NEXT_INSN (curr_pool->pool_insn);
6078
6079 if (jump && GET_CODE (jump) == JUMP_INSN
6080 && barrier && GET_CODE (barrier) == BARRIER
6081 && label && GET_CODE (label) == CODE_LABEL
6082 && GET_CODE (PATTERN (jump)) == SET
6083 && SET_DEST (PATTERN (jump)) == pc_rtx
6084 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6085 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6086 {
6087 remove_insn (jump);
6088 remove_insn (barrier);
6089 remove_insn (label);
6090 }
6091
6092 remove_insn (curr_pool->pool_insn);
6093 }
6094
6095 /* Remove all base register reload insns. */
6096
6097 for (insn = get_insns (); insn; )
6098 {
6099 rtx next_insn = NEXT_INSN (insn);
6100
6101 if (GET_CODE (insn) == INSN
6102 && GET_CODE (PATTERN (insn)) == SET
6103 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6104 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6105 remove_insn (insn);
6106
6107 insn = next_insn;
6108 }
6109
6110 /* Free pool list. */
6111
6112 while (pool_list)
6113 {
6114 struct constant_pool *next = pool_list->next;
6115 s390_free_pool (pool_list);
6116 pool_list = next;
6117 }
6118 }
6119
6120
6121 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6122
6123 void
6124 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6125 {
6126 REAL_VALUE_TYPE r;
6127
6128 switch (GET_MODE_CLASS (mode))
6129 {
6130 case MODE_FLOAT:
6131 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6132
6133 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6134 assemble_real (r, mode, align);
6135 break;
6136
6137 case MODE_INT:
6138 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6139 break;
6140
6141 default:
6142 gcc_unreachable ();
6143 }
6144 }
6145
6146
6147 /* Return an RTL expression representing the value of the return address
6148 for the frame COUNT steps up from the current frame. FRAME is the
6149 frame pointer of that frame. */
6150
6151 rtx
6152 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6153 {
6154 int offset;
6155 rtx addr;
6156
6157 /* Without backchain, we fail for all but the current frame. */
6158
6159 if (!TARGET_BACKCHAIN && count > 0)
6160 return NULL_RTX;
6161
6162 /* For the current frame, we need to make sure the initial
6163 value of RETURN_REGNUM is actually saved. */
6164
6165 if (count == 0)
6166 {
6167 /* On non-z architectures branch splitting could overwrite r14. */
6168 if (TARGET_CPU_ZARCH)
6169 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6170 else
6171 {
6172 cfun_frame_layout.save_return_addr_p = true;
6173 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6174 }
6175 }
6176
6177 if (TARGET_PACKED_STACK)
6178 offset = -2 * UNITS_PER_WORD;
6179 else
6180 offset = RETURN_REGNUM * UNITS_PER_WORD;
6181
6182 addr = plus_constant (frame, offset);
6183 addr = memory_address (Pmode, addr);
6184 return gen_rtx_MEM (Pmode, addr);
6185 }
6186
6187 /* Return an RTL expression representing the back chain stored in
6188 the current stack frame. */
6189
6190 rtx
6191 s390_back_chain_rtx (void)
6192 {
6193 rtx chain;
6194
6195 gcc_assert (TARGET_BACKCHAIN);
6196
6197 if (TARGET_PACKED_STACK)
6198 chain = plus_constant (stack_pointer_rtx,
6199 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6200 else
6201 chain = stack_pointer_rtx;
6202
6203 chain = gen_rtx_MEM (Pmode, chain);
6204 return chain;
6205 }
6206
6207 /* Find first call clobbered register unused in a function.
6208 This could be used as base register in a leaf function
6209 or for holding the return address before epilogue. */
6210
6211 static int
6212 find_unused_clobbered_reg (void)
6213 {
6214 int i;
6215 for (i = 0; i < 6; i++)
6216 if (!regs_ever_live[i])
6217 return i;
6218 return 0;
6219 }
6220
6221
6222 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6223 clobbered hard regs in SETREG. */
6224
6225 static void
6226 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
6227 {
6228 int *regs_ever_clobbered = (int *)data;
6229 unsigned int i, regno;
6230 enum machine_mode mode = GET_MODE (setreg);
6231
6232 if (GET_CODE (setreg) == SUBREG)
6233 {
6234 rtx inner = SUBREG_REG (setreg);
6235 if (!GENERAL_REG_P (inner))
6236 return;
6237 regno = subreg_regno (setreg);
6238 }
6239 else if (GENERAL_REG_P (setreg))
6240 regno = REGNO (setreg);
6241 else
6242 return;
6243
6244 for (i = regno;
6245 i < regno + HARD_REGNO_NREGS (regno, mode);
6246 i++)
6247 regs_ever_clobbered[i] = 1;
6248 }
6249
6250 /* Walks through all basic blocks of the current function looking
6251 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6252 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6253 each of those regs. */
6254
6255 static void
6256 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6257 {
6258 basic_block cur_bb;
6259 rtx cur_insn;
6260 unsigned int i;
6261
6262 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6263
6264 /* For non-leaf functions we have to consider all call clobbered regs to be
6265 clobbered. */
6266 if (!current_function_is_leaf)
6267 {
6268 for (i = 0; i < 16; i++)
6269 regs_ever_clobbered[i] = call_really_used_regs[i];
6270 }
6271
6272 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6273 this work is done by liveness analysis (mark_regs_live_at_end).
6274 Special care is needed for functions containing landing pads. Landing pads
6275 may use the eh registers, but the code which sets these registers is not
6276 contained in that function. Hence s390_regs_ever_clobbered is not able to
6277 deal with this automatically. */
6278 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
6279 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6280 if (current_function_calls_eh_return
6281 || (cfun->machine->has_landing_pad_p
6282 && regs_ever_live [EH_RETURN_DATA_REGNO (i)]))
6283 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6284
6285 /* For nonlocal gotos all call-saved registers have to be saved.
6286 This flag is also set for the unwinding code in libgcc.
6287 See expand_builtin_unwind_init. For regs_ever_live this is done by
6288 reload. */
6289 if (current_function_has_nonlocal_label)
6290 for (i = 0; i < 16; i++)
6291 if (!call_really_used_regs[i])
6292 regs_ever_clobbered[i] = 1;
6293
6294 FOR_EACH_BB (cur_bb)
6295 {
6296 FOR_BB_INSNS (cur_bb, cur_insn)
6297 {
6298 if (INSN_P (cur_insn))
6299 note_stores (PATTERN (cur_insn),
6300 s390_reg_clobbered_rtx,
6301 regs_ever_clobbered);
6302 }
6303 }
6304 }
6305
6306 /* Determine the frame area which actually has to be accessed
6307 in the function epilogue. The values are stored at the
6308 given pointers AREA_BOTTOM (address of the lowest used stack
6309 address) and AREA_TOP (address of the first item which does
6310 not belong to the stack frame). */
6311
6312 static void
6313 s390_frame_area (int *area_bottom, int *area_top)
6314 {
6315 int b, t;
6316 int i;
6317
6318 b = INT_MAX;
6319 t = INT_MIN;
6320
6321 if (cfun_frame_layout.first_restore_gpr != -1)
6322 {
6323 b = (cfun_frame_layout.gprs_offset
6324 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6325 t = b + (cfun_frame_layout.last_restore_gpr
6326 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6327 }
6328
6329 if (TARGET_64BIT && cfun_save_high_fprs_p)
6330 {
6331 b = MIN (b, cfun_frame_layout.f8_offset);
6332 t = MAX (t, (cfun_frame_layout.f8_offset
6333 + cfun_frame_layout.high_fprs * 8));
6334 }
6335
6336 if (!TARGET_64BIT)
6337 for (i = 2; i < 4; i++)
6338 if (cfun_fpr_bit_p (i))
6339 {
6340 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6341 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6342 }
6343
6344 *area_bottom = b;
6345 *area_top = t;
6346 }
6347
6348 /* Fill cfun->machine with info about register usage of current function.
6349 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6350
6351 static void
6352 s390_register_info (int clobbered_regs[])
6353 {
6354 int i, j;
6355
6356 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6357 cfun_frame_layout.fpr_bitmap = 0;
6358 cfun_frame_layout.high_fprs = 0;
6359 if (TARGET_64BIT)
6360 for (i = 24; i < 32; i++)
6361 if (regs_ever_live[i] && !global_regs[i])
6362 {
6363 cfun_set_fpr_bit (i - 16);
6364 cfun_frame_layout.high_fprs++;
6365 }
6366
6367 /* Find first and last gpr to be saved. We trust regs_ever_live
6368 data, except that we don't save and restore global registers.
6369
6370 Also, all registers with special meaning to the compiler need
6371 to be handled extra. */
6372
6373 s390_regs_ever_clobbered (clobbered_regs);
6374
6375 for (i = 0; i < 16; i++)
6376 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6377
6378 if (frame_pointer_needed)
6379 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6380
6381 if (flag_pic)
6382 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6383 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6384
6385 clobbered_regs[BASE_REGNUM]
6386 |= (cfun->machine->base_reg
6387 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6388
6389 clobbered_regs[RETURN_REGNUM]
6390 |= (!current_function_is_leaf
6391 || TARGET_TPF_PROFILING
6392 || cfun->machine->split_branches_pending_p
6393 || cfun_frame_layout.save_return_addr_p
6394 || current_function_calls_eh_return
6395 || current_function_stdarg);
6396
6397 clobbered_regs[STACK_POINTER_REGNUM]
6398 |= (!current_function_is_leaf
6399 || TARGET_TPF_PROFILING
6400 || cfun_save_high_fprs_p
6401 || get_frame_size () > 0
6402 || current_function_calls_alloca
6403 || current_function_stdarg);
6404
6405 for (i = 6; i < 16; i++)
6406 if (regs_ever_live[i] || clobbered_regs[i])
6407 break;
6408 for (j = 15; j > i; j--)
6409 if (regs_ever_live[j] || clobbered_regs[j])
6410 break;
6411
6412 if (i == 16)
6413 {
6414 /* Nothing to save/restore. */
6415 cfun_frame_layout.first_save_gpr_slot = -1;
6416 cfun_frame_layout.last_save_gpr_slot = -1;
6417 cfun_frame_layout.first_save_gpr = -1;
6418 cfun_frame_layout.first_restore_gpr = -1;
6419 cfun_frame_layout.last_save_gpr = -1;
6420 cfun_frame_layout.last_restore_gpr = -1;
6421 }
6422 else
6423 {
6424 /* Save slots for gprs from i to j. */
6425 cfun_frame_layout.first_save_gpr_slot = i;
6426 cfun_frame_layout.last_save_gpr_slot = j;
6427
6428 for (i = cfun_frame_layout.first_save_gpr_slot;
6429 i < cfun_frame_layout.last_save_gpr_slot + 1;
6430 i++)
6431 if (clobbered_regs[i])
6432 break;
6433
6434 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6435 if (clobbered_regs[j])
6436 break;
6437
6438 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6439 {
6440 /* Nothing to save/restore. */
6441 cfun_frame_layout.first_save_gpr = -1;
6442 cfun_frame_layout.first_restore_gpr = -1;
6443 cfun_frame_layout.last_save_gpr = -1;
6444 cfun_frame_layout.last_restore_gpr = -1;
6445 }
6446 else
6447 {
6448 /* Save / Restore from gpr i to j. */
6449 cfun_frame_layout.first_save_gpr = i;
6450 cfun_frame_layout.first_restore_gpr = i;
6451 cfun_frame_layout.last_save_gpr = j;
6452 cfun_frame_layout.last_restore_gpr = j;
6453 }
6454 }
6455
6456 if (current_function_stdarg)
6457 {
6458 /* Varargs functions need to save gprs 2 to 6. */
6459 if (cfun->va_list_gpr_size
6460 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6461 {
6462 int min_gpr = current_function_args_info.gprs;
6463 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6464 if (max_gpr > GP_ARG_NUM_REG)
6465 max_gpr = GP_ARG_NUM_REG;
6466
6467 if (cfun_frame_layout.first_save_gpr == -1
6468 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6469 {
6470 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6471 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
6472 }
6473
6474 if (cfun_frame_layout.last_save_gpr == -1
6475 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6476 {
6477 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6478 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
6479 }
6480 }
6481
6482 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6483 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6484 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6485 {
6486 int min_fpr = current_function_args_info.fprs;
6487 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6488 if (max_fpr > FP_ARG_NUM_REG)
6489 max_fpr = FP_ARG_NUM_REG;
6490
6491 /* ??? This is currently required to ensure proper location
6492 of the fpr save slots within the va_list save area. */
6493 if (TARGET_PACKED_STACK)
6494 min_fpr = 0;
6495
6496 for (i = min_fpr; i < max_fpr; i++)
6497 cfun_set_fpr_bit (i);
6498 }
6499 }
6500
6501 if (!TARGET_64BIT)
6502 for (i = 2; i < 4; i++)
6503 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6504 cfun_set_fpr_bit (i);
6505 }
6506
6507 /* Fill cfun->machine with info about frame of current function. */
6508
6509 static void
6510 s390_frame_info (void)
6511 {
6512 int i;
6513
6514 cfun_frame_layout.frame_size = get_frame_size ();
6515 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6516 fatal_error ("total size of local variables exceeds architecture limit");
6517
6518 if (!TARGET_PACKED_STACK)
6519 {
6520 cfun_frame_layout.backchain_offset = 0;
6521 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6522 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6523 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6524 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
6525 * UNITS_PER_WORD);
6526 }
6527 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6528 {
6529 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6530 - UNITS_PER_WORD);
6531 cfun_frame_layout.gprs_offset
6532 = (cfun_frame_layout.backchain_offset
6533 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
6534 * UNITS_PER_WORD);
6535
6536 if (TARGET_64BIT)
6537 {
6538 cfun_frame_layout.f4_offset
6539 = (cfun_frame_layout.gprs_offset
6540 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6541
6542 cfun_frame_layout.f0_offset
6543 = (cfun_frame_layout.f4_offset
6544 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6545 }
6546 else
6547 {
6548 /* On 31 bit we have to care about alignment of the
6549 floating point regs to provide fastest access. */
6550 cfun_frame_layout.f0_offset
6551 = ((cfun_frame_layout.gprs_offset
6552 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6553 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6554
6555 cfun_frame_layout.f4_offset
6556 = (cfun_frame_layout.f0_offset
6557 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6558 }
6559 }
6560 else /* no backchain */
6561 {
6562 cfun_frame_layout.f4_offset
6563 = (STACK_POINTER_OFFSET
6564 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6565
6566 cfun_frame_layout.f0_offset
6567 = (cfun_frame_layout.f4_offset
6568 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6569
6570 cfun_frame_layout.gprs_offset
6571 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6572 }
6573
6574 if (current_function_is_leaf
6575 && !TARGET_TPF_PROFILING
6576 && cfun_frame_layout.frame_size == 0
6577 && !cfun_save_high_fprs_p
6578 && !current_function_calls_alloca
6579 && !current_function_stdarg)
6580 return;
6581
6582 if (!TARGET_PACKED_STACK)
6583 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6584 + current_function_outgoing_args_size
6585 + cfun_frame_layout.high_fprs * 8);
6586 else
6587 {
6588 if (TARGET_BACKCHAIN)
6589 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6590
6591 /* No alignment trouble here because f8-f15 are only saved under
6592 64 bit. */
6593 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6594 cfun_frame_layout.f4_offset),
6595 cfun_frame_layout.gprs_offset)
6596 - cfun_frame_layout.high_fprs * 8);
6597
6598 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6599
6600 for (i = 0; i < 8; i++)
6601 if (cfun_fpr_bit_p (i))
6602 cfun_frame_layout.frame_size += 8;
6603
6604 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6605
6606 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6607 the frame size to sustain 8 byte alignment of stack frames. */
6608 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6609 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6610 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6611
6612 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6613 }
6614 }
6615
6616 /* Generate frame layout. Fills in register and frame data for the current
6617 function in cfun->machine. This routine can be called multiple times;
6618 it will re-do the complete frame layout every time. */
6619
6620 static void
6621 s390_init_frame_layout (void)
6622 {
6623 HOST_WIDE_INT frame_size;
6624 int base_used;
6625 int clobbered_regs[16];
6626
6627 /* On S/390 machines, we may need to perform branch splitting, which
6628 will require both base and return address register. We have no
6629 choice but to assume we're going to need them until right at the
6630 end of the machine dependent reorg phase. */
6631 if (!TARGET_CPU_ZARCH)
6632 cfun->machine->split_branches_pending_p = true;
6633
6634 do
6635 {
6636 frame_size = cfun_frame_layout.frame_size;
6637
6638 /* Try to predict whether we'll need the base register. */
6639 base_used = cfun->machine->split_branches_pending_p
6640 || current_function_uses_const_pool
6641 || (!DISP_IN_RANGE (-frame_size)
6642 && !CONST_OK_FOR_K (-frame_size));
6643
6644 /* Decide which register to use as literal pool base. In small
6645 leaf functions, try to use an unused call-clobbered register
6646 as base register to avoid save/restore overhead. */
6647 if (!base_used)
6648 cfun->machine->base_reg = NULL_RTX;
6649 else if (current_function_is_leaf && !regs_ever_live[5])
6650 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6651 else
6652 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6653
6654 s390_register_info (clobbered_regs);
6655 s390_frame_info ();
6656 }
6657 while (frame_size != cfun_frame_layout.frame_size);
6658 }
6659
6660 /* Update frame layout. Recompute actual register save data based on
6661 current info and update regs_ever_live for the special registers.
6662 May be called multiple times, but may never cause *more* registers
6663 to be saved than s390_init_frame_layout allocated room for. */
6664
6665 static void
6666 s390_update_frame_layout (void)
6667 {
6668 int clobbered_regs[16];
6669
6670 s390_register_info (clobbered_regs);
6671
6672 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6673 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6674 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6675
6676 if (cfun->machine->base_reg)
6677 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6678 }
6679
6680 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6681
6682 bool
6683 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6684 {
6685 /* Once we've decided upon a register to use as base register, it must
6686 no longer be used for any other purpose. */
6687 if (cfun->machine->base_reg)
6688 if (REGNO (cfun->machine->base_reg) == old_reg
6689 || REGNO (cfun->machine->base_reg) == new_reg)
6690 return false;
6691
6692 return true;
6693 }
6694
6695 /* Return true if register FROM can be eliminated via register TO. */
6696
6697 bool
6698 s390_can_eliminate (int from, int to)
6699 {
6700 /* On zSeries machines, we have not marked the base register as fixed.
6701 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6702 If a function requires the base register, we say here that this
6703 elimination cannot be performed. This will cause reload to free
6704 up the base register (as if it were fixed). On the other hand,
6705 if the current function does *not* require the base register, we
6706 say here the elimination succeeds, which in turn allows reload
6707 to allocate the base register for any other purpose. */
6708 if (from == BASE_REGNUM && to == BASE_REGNUM)
6709 {
6710 if (TARGET_CPU_ZARCH)
6711 {
6712 s390_init_frame_layout ();
6713 return cfun->machine->base_reg == NULL_RTX;
6714 }
6715
6716 return false;
6717 }
6718
6719 /* Everything else must point into the stack frame. */
6720 gcc_assert (to == STACK_POINTER_REGNUM
6721 || to == HARD_FRAME_POINTER_REGNUM);
6722
6723 gcc_assert (from == FRAME_POINTER_REGNUM
6724 || from == ARG_POINTER_REGNUM
6725 || from == RETURN_ADDRESS_POINTER_REGNUM);
6726
6727 /* Make sure we actually saved the return address. */
6728 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6729 if (!current_function_calls_eh_return
6730 && !current_function_stdarg
6731 && !cfun_frame_layout.save_return_addr_p)
6732 return false;
6733
6734 return true;
6735 }
6736
6737 /* Return offset between register FROM and TO initially after prolog. */
6738
6739 HOST_WIDE_INT
6740 s390_initial_elimination_offset (int from, int to)
6741 {
6742 HOST_WIDE_INT offset;
6743 int index;
6744
6745 /* ??? Why are we called for non-eliminable pairs? */
6746 if (!s390_can_eliminate (from, to))
6747 return 0;
6748
6749 switch (from)
6750 {
6751 case FRAME_POINTER_REGNUM:
6752 offset = (get_frame_size()
6753 + STACK_POINTER_OFFSET
6754 + current_function_outgoing_args_size);
6755 break;
6756
6757 case ARG_POINTER_REGNUM:
6758 s390_init_frame_layout ();
6759 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6760 break;
6761
6762 case RETURN_ADDRESS_POINTER_REGNUM:
6763 s390_init_frame_layout ();
6764 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
6765 gcc_assert (index >= 0);
6766 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6767 offset += index * UNITS_PER_WORD;
6768 break;
6769
6770 case BASE_REGNUM:
6771 offset = 0;
6772 break;
6773
6774 default:
6775 gcc_unreachable ();
6776 }
6777
6778 return offset;
6779 }
6780
6781 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6782 to register BASE. Return generated insn. */
6783
6784 static rtx
6785 save_fpr (rtx base, int offset, int regnum)
6786 {
6787 rtx addr;
6788 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6789
6790 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6791 set_mem_alias_set (addr, get_varargs_alias_set ());
6792 else
6793 set_mem_alias_set (addr, get_frame_alias_set ());
6794
6795 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6796 }
6797
6798 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6799 to register BASE. Return generated insn. */
6800
6801 static rtx
6802 restore_fpr (rtx base, int offset, int regnum)
6803 {
6804 rtx addr;
6805 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6806 set_mem_alias_set (addr, get_frame_alias_set ());
6807
6808 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6809 }
6810
6811 /* Generate insn to save registers FIRST to LAST into
6812 the register save area located at offset OFFSET
6813 relative to register BASE. */
6814
6815 static rtx
6816 save_gprs (rtx base, int offset, int first, int last)
6817 {
6818 rtx addr, insn, note;
6819 int i;
6820
6821 addr = plus_constant (base, offset);
6822 addr = gen_rtx_MEM (Pmode, addr);
6823
6824 set_mem_alias_set (addr, get_frame_alias_set ());
6825
6826 /* Special-case single register. */
6827 if (first == last)
6828 {
6829 if (TARGET_64BIT)
6830 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6831 else
6832 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6833
6834 RTX_FRAME_RELATED_P (insn) = 1;
6835 return insn;
6836 }
6837
6838
6839 insn = gen_store_multiple (addr,
6840 gen_rtx_REG (Pmode, first),
6841 GEN_INT (last - first + 1));
6842
6843 if (first <= 6 && current_function_stdarg)
6844 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6845 {
6846 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
6847
6848 if (first + i <= 6)
6849 set_mem_alias_set (mem, get_varargs_alias_set ());
6850 }
6851
6852 /* We need to set the FRAME_RELATED flag on all SETs
6853 inside the store-multiple pattern.
6854
6855 However, we must not emit DWARF records for registers 2..5
6856 if they are stored for use by variable arguments ...
6857
6858 ??? Unfortunately, it is not enough to simply not the
6859 FRAME_RELATED flags for those SETs, because the first SET
6860 of the PARALLEL is always treated as if it had the flag
6861 set, even if it does not. Therefore we emit a new pattern
6862 without those registers as REG_FRAME_RELATED_EXPR note. */
6863
6864 if (first >= 6)
6865 {
6866 rtx pat = PATTERN (insn);
6867
6868 for (i = 0; i < XVECLEN (pat, 0); i++)
6869 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
6870 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
6871
6872 RTX_FRAME_RELATED_P (insn) = 1;
6873 }
6874 else if (last >= 6)
6875 {
6876 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
6877 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
6878 gen_rtx_REG (Pmode, 6),
6879 GEN_INT (last - 6 + 1));
6880 note = PATTERN (note);
6881
6882 REG_NOTES (insn) =
6883 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6884 note, REG_NOTES (insn));
6885
6886 for (i = 0; i < XVECLEN (note, 0); i++)
6887 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
6888 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
6889
6890 RTX_FRAME_RELATED_P (insn) = 1;
6891 }
6892
6893 return insn;
6894 }
6895
6896 /* Generate insn to restore registers FIRST to LAST from
6897 the register save area located at offset OFFSET
6898 relative to register BASE. */
6899
6900 static rtx
6901 restore_gprs (rtx base, int offset, int first, int last)
6902 {
6903 rtx addr, insn;
6904
6905 addr = plus_constant (base, offset);
6906 addr = gen_rtx_MEM (Pmode, addr);
6907 set_mem_alias_set (addr, get_frame_alias_set ());
6908
6909 /* Special-case single register. */
6910 if (first == last)
6911 {
6912 if (TARGET_64BIT)
6913 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
6914 else
6915 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
6916
6917 return insn;
6918 }
6919
6920 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
6921 addr,
6922 GEN_INT (last - first + 1));
6923 return insn;
6924 }
6925
6926 /* Return insn sequence to load the GOT register. */
6927
6928 static GTY(()) rtx got_symbol;
6929 rtx
6930 s390_load_got (void)
6931 {
6932 rtx insns;
6933
6934 if (!got_symbol)
6935 {
6936 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
6937 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
6938 }
6939
6940 start_sequence ();
6941
6942 if (TARGET_CPU_ZARCH)
6943 {
6944 emit_move_insn (pic_offset_table_rtx, got_symbol);
6945 }
6946 else
6947 {
6948 rtx offset;
6949
6950 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
6951 UNSPEC_LTREL_OFFSET);
6952 offset = gen_rtx_CONST (Pmode, offset);
6953 offset = force_const_mem (Pmode, offset);
6954
6955 emit_move_insn (pic_offset_table_rtx, offset);
6956
6957 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
6958 UNSPEC_LTREL_BASE);
6959 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
6960
6961 emit_move_insn (pic_offset_table_rtx, offset);
6962 }
6963
6964 insns = get_insns ();
6965 end_sequence ();
6966 return insns;
6967 }
6968
6969 /* Expand the prologue into a bunch of separate insns. */
6970
6971 void
6972 s390_emit_prologue (void)
6973 {
6974 rtx insn, addr;
6975 rtx temp_reg;
6976 int i;
6977 int offset;
6978 int next_fpr = 0;
6979
6980 /* Complete frame layout. */
6981
6982 s390_update_frame_layout ();
6983
6984 /* Annotate all constant pool references to let the scheduler know
6985 they implicitly use the base register. */
6986
6987 push_topmost_sequence ();
6988
6989 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6990 if (INSN_P (insn))
6991 annotate_constant_pool_refs (&PATTERN (insn));
6992
6993 pop_topmost_sequence ();
6994
6995 /* Choose best register to use for temp use within prologue.
6996 See below for why TPF must use the register 1. */
6997
6998 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
6999 && !current_function_is_leaf
7000 && !TARGET_TPF_PROFILING)
7001 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7002 else
7003 temp_reg = gen_rtx_REG (Pmode, 1);
7004
7005 /* Save call saved gprs. */
7006 if (cfun_frame_layout.first_save_gpr != -1)
7007 {
7008 insn = save_gprs (stack_pointer_rtx,
7009 cfun_frame_layout.gprs_offset +
7010 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7011 - cfun_frame_layout.first_save_gpr_slot),
7012 cfun_frame_layout.first_save_gpr,
7013 cfun_frame_layout.last_save_gpr);
7014 emit_insn (insn);
7015 }
7016
7017 /* Dummy insn to mark literal pool slot. */
7018
7019 if (cfun->machine->base_reg)
7020 emit_insn (gen_main_pool (cfun->machine->base_reg));
7021
7022 offset = cfun_frame_layout.f0_offset;
7023
7024 /* Save f0 and f2. */
7025 for (i = 0; i < 2; i++)
7026 {
7027 if (cfun_fpr_bit_p (i))
7028 {
7029 save_fpr (stack_pointer_rtx, offset, i + 16);
7030 offset += 8;
7031 }
7032 else if (!TARGET_PACKED_STACK)
7033 offset += 8;
7034 }
7035
7036 /* Save f4 and f6. */
7037 offset = cfun_frame_layout.f4_offset;
7038 for (i = 2; i < 4; i++)
7039 {
7040 if (cfun_fpr_bit_p (i))
7041 {
7042 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7043 offset += 8;
7044
7045 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7046 therefore are not frame related. */
7047 if (!call_really_used_regs[i + 16])
7048 RTX_FRAME_RELATED_P (insn) = 1;
7049 }
7050 else if (!TARGET_PACKED_STACK)
7051 offset += 8;
7052 }
7053
7054 if (TARGET_PACKED_STACK
7055 && cfun_save_high_fprs_p
7056 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7057 {
7058 offset = (cfun_frame_layout.f8_offset
7059 + (cfun_frame_layout.high_fprs - 1) * 8);
7060
7061 for (i = 15; i > 7 && offset >= 0; i--)
7062 if (cfun_fpr_bit_p (i))
7063 {
7064 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7065
7066 RTX_FRAME_RELATED_P (insn) = 1;
7067 offset -= 8;
7068 }
7069 if (offset >= cfun_frame_layout.f8_offset)
7070 next_fpr = i + 16;
7071 }
7072
7073 if (!TARGET_PACKED_STACK)
7074 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7075
7076 /* Decrement stack pointer. */
7077
7078 if (cfun_frame_layout.frame_size > 0)
7079 {
7080 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7081
7082 if (s390_stack_size)
7083 {
7084 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7085 & ~(s390_stack_guard - 1));
7086 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7087 GEN_INT (stack_check_mask));
7088
7089 if (TARGET_64BIT)
7090 gen_cmpdi (t, const0_rtx);
7091 else
7092 gen_cmpsi (t, const0_rtx);
7093
7094 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7095 gen_rtx_REG (CCmode,
7096 CC_REGNUM),
7097 const0_rtx),
7098 const0_rtx));
7099 }
7100
7101 if (s390_warn_framesize > 0
7102 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7103 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7104 current_function_name (), cfun_frame_layout.frame_size);
7105
7106 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7107 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7108
7109 /* Save incoming stack pointer into temp reg. */
7110 if (TARGET_BACKCHAIN || next_fpr)
7111 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7112
7113 /* Subtract frame size from stack pointer. */
7114
7115 if (DISP_IN_RANGE (INTVAL (frame_off)))
7116 {
7117 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7118 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7119 frame_off));
7120 insn = emit_insn (insn);
7121 }
7122 else
7123 {
7124 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7125 frame_off = force_const_mem (Pmode, frame_off);
7126
7127 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7128 annotate_constant_pool_refs (&PATTERN (insn));
7129 }
7130
7131 RTX_FRAME_RELATED_P (insn) = 1;
7132 REG_NOTES (insn) =
7133 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7134 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7135 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7136 GEN_INT (-cfun_frame_layout.frame_size))),
7137 REG_NOTES (insn));
7138
7139 /* Set backchain. */
7140
7141 if (TARGET_BACKCHAIN)
7142 {
7143 if (cfun_frame_layout.backchain_offset)
7144 addr = gen_rtx_MEM (Pmode,
7145 plus_constant (stack_pointer_rtx,
7146 cfun_frame_layout.backchain_offset));
7147 else
7148 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7149 set_mem_alias_set (addr, get_frame_alias_set ());
7150 insn = emit_insn (gen_move_insn (addr, temp_reg));
7151 }
7152
7153 /* If we support asynchronous exceptions (e.g. for Java),
7154 we need to make sure the backchain pointer is set up
7155 before any possibly trapping memory access. */
7156
7157 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7158 {
7159 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7160 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
7161 }
7162 }
7163
7164 /* Save fprs 8 - 15 (64 bit ABI). */
7165
7166 if (cfun_save_high_fprs_p && next_fpr)
7167 {
7168 insn = emit_insn (gen_add2_insn (temp_reg,
7169 GEN_INT (cfun_frame_layout.f8_offset)));
7170
7171 offset = 0;
7172
7173 for (i = 24; i <= next_fpr; i++)
7174 if (cfun_fpr_bit_p (i - 16))
7175 {
7176 rtx addr = plus_constant (stack_pointer_rtx,
7177 cfun_frame_layout.frame_size
7178 + cfun_frame_layout.f8_offset
7179 + offset);
7180
7181 insn = save_fpr (temp_reg, offset, i);
7182 offset += 8;
7183 RTX_FRAME_RELATED_P (insn) = 1;
7184 REG_NOTES (insn) =
7185 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7186 gen_rtx_SET (VOIDmode,
7187 gen_rtx_MEM (DFmode, addr),
7188 gen_rtx_REG (DFmode, i)),
7189 REG_NOTES (insn));
7190 }
7191 }
7192
7193 /* Set frame pointer, if needed. */
7194
7195 if (frame_pointer_needed)
7196 {
7197 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7198 RTX_FRAME_RELATED_P (insn) = 1;
7199 }
7200
7201 /* Set up got pointer, if needed. */
7202
7203 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7204 {
7205 rtx insns = s390_load_got ();
7206
7207 for (insn = insns; insn; insn = NEXT_INSN (insn))
7208 {
7209 annotate_constant_pool_refs (&PATTERN (insn));
7210
7211 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7212 REG_NOTES (insn));
7213 }
7214
7215 emit_insn (insns);
7216 }
7217
7218 if (TARGET_TPF_PROFILING)
7219 {
7220 /* Generate a BAS instruction to serve as a function
7221 entry intercept to facilitate the use of tracing
7222 algorithms located at the branch target. */
7223 emit_insn (gen_prologue_tpf ());
7224
7225 /* Emit a blockage here so that all code
7226 lies between the profiling mechanisms. */
7227 emit_insn (gen_blockage ());
7228 }
7229 }
7230
7231 /* Expand the epilogue into a bunch of separate insns. */
7232
7233 void
7234 s390_emit_epilogue (bool sibcall)
7235 {
7236 rtx frame_pointer, return_reg;
7237 int area_bottom, area_top, offset = 0;
7238 int next_offset;
7239 rtvec p;
7240 int i;
7241
7242 if (TARGET_TPF_PROFILING)
7243 {
7244
7245 /* Generate a BAS instruction to serve as a function
7246 entry intercept to facilitate the use of tracing
7247 algorithms located at the branch target. */
7248
7249 /* Emit a blockage here so that all code
7250 lies between the profiling mechanisms. */
7251 emit_insn (gen_blockage ());
7252
7253 emit_insn (gen_epilogue_tpf ());
7254 }
7255
7256 /* Check whether to use frame or stack pointer for restore. */
7257
7258 frame_pointer = (frame_pointer_needed
7259 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7260
7261 s390_frame_area (&area_bottom, &area_top);
7262
7263 /* Check whether we can access the register save area.
7264 If not, increment the frame pointer as required. */
7265
7266 if (area_top <= area_bottom)
7267 {
7268 /* Nothing to restore. */
7269 }
7270 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7271 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7272 {
7273 /* Area is in range. */
7274 offset = cfun_frame_layout.frame_size;
7275 }
7276 else
7277 {
7278 rtx insn, frame_off;
7279
7280 offset = area_bottom < 0 ? -area_bottom : 0;
7281 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7282
7283 if (DISP_IN_RANGE (INTVAL (frame_off)))
7284 {
7285 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7286 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7287 insn = emit_insn (insn);
7288 }
7289 else
7290 {
7291 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7292 frame_off = force_const_mem (Pmode, frame_off);
7293
7294 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7295 annotate_constant_pool_refs (&PATTERN (insn));
7296 }
7297 }
7298
7299 /* Restore call saved fprs. */
7300
7301 if (TARGET_64BIT)
7302 {
7303 if (cfun_save_high_fprs_p)
7304 {
7305 next_offset = cfun_frame_layout.f8_offset;
7306 for (i = 24; i < 32; i++)
7307 {
7308 if (cfun_fpr_bit_p (i - 16))
7309 {
7310 restore_fpr (frame_pointer,
7311 offset + next_offset, i);
7312 next_offset += 8;
7313 }
7314 }
7315 }
7316
7317 }
7318 else
7319 {
7320 next_offset = cfun_frame_layout.f4_offset;
7321 for (i = 18; i < 20; i++)
7322 {
7323 if (cfun_fpr_bit_p (i - 16))
7324 {
7325 restore_fpr (frame_pointer,
7326 offset + next_offset, i);
7327 next_offset += 8;
7328 }
7329 else if (!TARGET_PACKED_STACK)
7330 next_offset += 8;
7331 }
7332
7333 }
7334
7335 /* Return register. */
7336
7337 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7338
7339 /* Restore call saved gprs. */
7340
7341 if (cfun_frame_layout.first_restore_gpr != -1)
7342 {
7343 rtx insn, addr;
7344 int i;
7345
7346 /* Check for global register and save them
7347 to stack location from where they get restored. */
7348
7349 for (i = cfun_frame_layout.first_restore_gpr;
7350 i <= cfun_frame_layout.last_restore_gpr;
7351 i++)
7352 {
7353 /* These registers are special and need to be
7354 restored in any case. */
7355 if (i == STACK_POINTER_REGNUM
7356 || i == RETURN_REGNUM
7357 || i == BASE_REGNUM
7358 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7359 continue;
7360
7361 if (global_regs[i])
7362 {
7363 addr = plus_constant (frame_pointer,
7364 offset + cfun_frame_layout.gprs_offset
7365 + (i - cfun_frame_layout.first_save_gpr_slot)
7366 * UNITS_PER_WORD);
7367 addr = gen_rtx_MEM (Pmode, addr);
7368 set_mem_alias_set (addr, get_frame_alias_set ());
7369 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7370 }
7371 }
7372
7373 if (! sibcall)
7374 {
7375 /* Fetch return address from stack before load multiple,
7376 this will do good for scheduling. */
7377
7378 if (cfun_frame_layout.save_return_addr_p
7379 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7380 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7381 {
7382 int return_regnum = find_unused_clobbered_reg();
7383 if (!return_regnum)
7384 return_regnum = 4;
7385 return_reg = gen_rtx_REG (Pmode, return_regnum);
7386
7387 addr = plus_constant (frame_pointer,
7388 offset + cfun_frame_layout.gprs_offset
7389 + (RETURN_REGNUM
7390 - cfun_frame_layout.first_save_gpr_slot)
7391 * UNITS_PER_WORD);
7392 addr = gen_rtx_MEM (Pmode, addr);
7393 set_mem_alias_set (addr, get_frame_alias_set ());
7394 emit_move_insn (return_reg, addr);
7395 }
7396 }
7397
7398 insn = restore_gprs (frame_pointer,
7399 offset + cfun_frame_layout.gprs_offset
7400 + (cfun_frame_layout.first_restore_gpr
7401 - cfun_frame_layout.first_save_gpr_slot)
7402 * UNITS_PER_WORD,
7403 cfun_frame_layout.first_restore_gpr,
7404 cfun_frame_layout.last_restore_gpr);
7405 emit_insn (insn);
7406 }
7407
7408 if (! sibcall)
7409 {
7410
7411 /* Return to caller. */
7412
7413 p = rtvec_alloc (2);
7414
7415 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7416 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7417 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7418 }
7419 }
7420
7421
7422 /* Return the size in bytes of a function argument of
7423 type TYPE and/or mode MODE. At least one of TYPE or
7424 MODE must be specified. */
7425
7426 static int
7427 s390_function_arg_size (enum machine_mode mode, tree type)
7428 {
7429 if (type)
7430 return int_size_in_bytes (type);
7431
7432 /* No type info available for some library calls ... */
7433 if (mode != BLKmode)
7434 return GET_MODE_SIZE (mode);
7435
7436 /* If we have neither type nor mode, abort */
7437 gcc_unreachable ();
7438 }
7439
7440 /* Return true if a function argument of type TYPE and mode MODE
7441 is to be passed in a floating-point register, if available. */
7442
7443 static bool
7444 s390_function_arg_float (enum machine_mode mode, tree type)
7445 {
7446 int size = s390_function_arg_size (mode, type);
7447 if (size > 8)
7448 return false;
7449
7450 /* Soft-float changes the ABI: no floating-point registers are used. */
7451 if (TARGET_SOFT_FLOAT)
7452 return false;
7453
7454 /* No type info available for some library calls ... */
7455 if (!type)
7456 return mode == SFmode || mode == DFmode;
7457
7458 /* The ABI says that record types with a single member are treated
7459 just like that member would be. */
7460 while (TREE_CODE (type) == RECORD_TYPE)
7461 {
7462 tree field, single = NULL_TREE;
7463
7464 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7465 {
7466 if (TREE_CODE (field) != FIELD_DECL)
7467 continue;
7468
7469 if (single == NULL_TREE)
7470 single = TREE_TYPE (field);
7471 else
7472 return false;
7473 }
7474
7475 if (single == NULL_TREE)
7476 return false;
7477 else
7478 type = single;
7479 }
7480
7481 return TREE_CODE (type) == REAL_TYPE;
7482 }
7483
7484 /* Return true if a function argument of type TYPE and mode MODE
7485 is to be passed in an integer register, or a pair of integer
7486 registers, if available. */
7487
7488 static bool
7489 s390_function_arg_integer (enum machine_mode mode, tree type)
7490 {
7491 int size = s390_function_arg_size (mode, type);
7492 if (size > 8)
7493 return false;
7494
7495 /* No type info available for some library calls ... */
7496 if (!type)
7497 return GET_MODE_CLASS (mode) == MODE_INT
7498 || (TARGET_SOFT_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT);
7499
7500 /* We accept small integral (and similar) types. */
7501 if (INTEGRAL_TYPE_P (type)
7502 || POINTER_TYPE_P (type)
7503 || TREE_CODE (type) == OFFSET_TYPE
7504 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7505 return true;
7506
7507 /* We also accept structs of size 1, 2, 4, 8 that are not
7508 passed in floating-point registers. */
7509 if (AGGREGATE_TYPE_P (type)
7510 && exact_log2 (size) >= 0
7511 && !s390_function_arg_float (mode, type))
7512 return true;
7513
7514 return false;
7515 }
7516
7517 /* Return 1 if a function argument of type TYPE and mode MODE
7518 is to be passed by reference. The ABI specifies that only
7519 structures of size 1, 2, 4, or 8 bytes are passed by value,
7520 all other structures (and complex numbers) are passed by
7521 reference. */
7522
7523 static bool
7524 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7525 enum machine_mode mode, tree type,
7526 bool named ATTRIBUTE_UNUSED)
7527 {
7528 int size = s390_function_arg_size (mode, type);
7529 if (size > 8)
7530 return true;
7531
7532 if (type)
7533 {
7534 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7535 return 1;
7536
7537 if (TREE_CODE (type) == COMPLEX_TYPE
7538 || TREE_CODE (type) == VECTOR_TYPE)
7539 return 1;
7540 }
7541
7542 return 0;
7543 }
7544
7545 /* Update the data in CUM to advance over an argument of mode MODE and
7546 data type TYPE. (TYPE is null for libcalls where that information
7547 may not be available.). The boolean NAMED specifies whether the
7548 argument is a named argument (as opposed to an unnamed argument
7549 matching an ellipsis). */
7550
7551 void
7552 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7553 tree type, int named ATTRIBUTE_UNUSED)
7554 {
7555 if (s390_function_arg_float (mode, type))
7556 {
7557 cum->fprs += 1;
7558 }
7559 else if (s390_function_arg_integer (mode, type))
7560 {
7561 int size = s390_function_arg_size (mode, type);
7562 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7563 }
7564 else
7565 gcc_unreachable ();
7566 }
7567
7568 /* Define where to put the arguments to a function.
7569 Value is zero to push the argument on the stack,
7570 or a hard register in which to store the argument.
7571
7572 MODE is the argument's machine mode.
7573 TYPE is the data type of the argument (as a tree).
7574 This is null for libcalls where that information may
7575 not be available.
7576 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7577 the preceding args and about the function being called.
7578 NAMED is nonzero if this argument is a named parameter
7579 (otherwise it is an extra parameter matching an ellipsis).
7580
7581 On S/390, we use general purpose registers 2 through 6 to
7582 pass integer, pointer, and certain structure arguments, and
7583 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7584 to pass floating point arguments. All remaining arguments
7585 are pushed to the stack. */
7586
7587 rtx
7588 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7589 int named ATTRIBUTE_UNUSED)
7590 {
7591 if (s390_function_arg_float (mode, type))
7592 {
7593 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7594 return 0;
7595 else
7596 return gen_rtx_REG (mode, cum->fprs + 16);
7597 }
7598 else if (s390_function_arg_integer (mode, type))
7599 {
7600 int size = s390_function_arg_size (mode, type);
7601 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7602
7603 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7604 return 0;
7605 else
7606 return gen_rtx_REG (mode, cum->gprs + 2);
7607 }
7608
7609 /* After the real arguments, expand_call calls us once again
7610 with a void_type_node type. Whatever we return here is
7611 passed as operand 2 to the call expanders.
7612
7613 We don't need this feature ... */
7614 else if (type == void_type_node)
7615 return const0_rtx;
7616
7617 gcc_unreachable ();
7618 }
7619
7620 /* Return true if return values of type TYPE should be returned
7621 in a memory buffer whose address is passed by the caller as
7622 hidden first argument. */
7623
7624 static bool
7625 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7626 {
7627 /* We accept small integral (and similar) types. */
7628 if (INTEGRAL_TYPE_P (type)
7629 || POINTER_TYPE_P (type)
7630 || TREE_CODE (type) == OFFSET_TYPE
7631 || TREE_CODE (type) == REAL_TYPE)
7632 return int_size_in_bytes (type) > 8;
7633
7634 /* Aggregates and similar constructs are always returned
7635 in memory. */
7636 if (AGGREGATE_TYPE_P (type)
7637 || TREE_CODE (type) == COMPLEX_TYPE
7638 || TREE_CODE (type) == VECTOR_TYPE)
7639 return true;
7640
7641 /* ??? We get called on all sorts of random stuff from
7642 aggregate_value_p. We can't abort, but it's not clear
7643 what's safe to return. Pretend it's a struct I guess. */
7644 return true;
7645 }
7646
7647 /* Define where to return a (scalar) value of type TYPE.
7648 If TYPE is null, define where to return a (scalar)
7649 value of mode MODE from a libcall. */
7650
7651 rtx
7652 s390_function_value (tree type, enum machine_mode mode)
7653 {
7654 if (type)
7655 {
7656 int unsignedp = TYPE_UNSIGNED (type);
7657 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7658 }
7659
7660 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
7661 || GET_MODE_CLASS (mode) == MODE_FLOAT);
7662 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7663
7664 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
7665 return gen_rtx_REG (mode, 16);
7666 else
7667 return gen_rtx_REG (mode, 2);
7668 }
7669
7670
7671 /* Create and return the va_list datatype.
7672
7673 On S/390, va_list is an array type equivalent to
7674
7675 typedef struct __va_list_tag
7676 {
7677 long __gpr;
7678 long __fpr;
7679 void *__overflow_arg_area;
7680 void *__reg_save_area;
7681 } va_list[1];
7682
7683 where __gpr and __fpr hold the number of general purpose
7684 or floating point arguments used up to now, respectively,
7685 __overflow_arg_area points to the stack location of the
7686 next argument passed on the stack, and __reg_save_area
7687 always points to the start of the register area in the
7688 call frame of the current function. The function prologue
7689 saves all registers used for argument passing into this
7690 area if the function uses variable arguments. */
7691
7692 static tree
7693 s390_build_builtin_va_list (void)
7694 {
7695 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7696
7697 record = lang_hooks.types.make_type (RECORD_TYPE);
7698
7699 type_decl =
7700 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7701
7702 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7703 long_integer_type_node);
7704 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7705 long_integer_type_node);
7706 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7707 ptr_type_node);
7708 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7709 ptr_type_node);
7710
7711 va_list_gpr_counter_field = f_gpr;
7712 va_list_fpr_counter_field = f_fpr;
7713
7714 DECL_FIELD_CONTEXT (f_gpr) = record;
7715 DECL_FIELD_CONTEXT (f_fpr) = record;
7716 DECL_FIELD_CONTEXT (f_ovf) = record;
7717 DECL_FIELD_CONTEXT (f_sav) = record;
7718
7719 TREE_CHAIN (record) = type_decl;
7720 TYPE_NAME (record) = type_decl;
7721 TYPE_FIELDS (record) = f_gpr;
7722 TREE_CHAIN (f_gpr) = f_fpr;
7723 TREE_CHAIN (f_fpr) = f_ovf;
7724 TREE_CHAIN (f_ovf) = f_sav;
7725
7726 layout_type (record);
7727
7728 /* The correct type is an array type of one element. */
7729 return build_array_type (record, build_index_type (size_zero_node));
7730 }
7731
7732 /* Implement va_start by filling the va_list structure VALIST.
7733 STDARG_P is always true, and ignored.
7734 NEXTARG points to the first anonymous stack argument.
7735
7736 The following global variables are used to initialize
7737 the va_list structure:
7738
7739 current_function_args_info:
7740 holds number of gprs and fprs used for named arguments.
7741 current_function_arg_offset_rtx:
7742 holds the offset of the first anonymous stack argument
7743 (relative to the virtual arg pointer). */
7744
7745 void
7746 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7747 {
7748 HOST_WIDE_INT n_gpr, n_fpr;
7749 int off;
7750 tree f_gpr, f_fpr, f_ovf, f_sav;
7751 tree gpr, fpr, ovf, sav, t;
7752
7753 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7754 f_fpr = TREE_CHAIN (f_gpr);
7755 f_ovf = TREE_CHAIN (f_fpr);
7756 f_sav = TREE_CHAIN (f_ovf);
7757
7758 valist = build_va_arg_indirect_ref (valist);
7759 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7760 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7761 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7762 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7763
7764 /* Count number of gp and fp argument registers used. */
7765
7766 n_gpr = current_function_args_info.gprs;
7767 n_fpr = current_function_args_info.fprs;
7768
7769 if (cfun->va_list_gpr_size)
7770 {
7771 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7772 build_int_cst (NULL_TREE, n_gpr));
7773 TREE_SIDE_EFFECTS (t) = 1;
7774 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7775 }
7776
7777 if (cfun->va_list_fpr_size)
7778 {
7779 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7780 build_int_cst (NULL_TREE, n_fpr));
7781 TREE_SIDE_EFFECTS (t) = 1;
7782 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7783 }
7784
7785 /* Find the overflow area. */
7786 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7787 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7788 {
7789 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7790
7791 off = INTVAL (current_function_arg_offset_rtx);
7792 off = off < 0 ? 0 : off;
7793 if (TARGET_DEBUG_ARG)
7794 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7795 (int)n_gpr, (int)n_fpr, off);
7796
7797 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7798
7799 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7800 TREE_SIDE_EFFECTS (t) = 1;
7801 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7802 }
7803
7804 /* Find the register save area. */
7805 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7806 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7807 {
7808 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7809 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
7810 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7811
7812 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7813 TREE_SIDE_EFFECTS (t) = 1;
7814 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7815 }
7816 }
7817
7818 /* Implement va_arg by updating the va_list structure
7819 VALIST as required to retrieve an argument of type
7820 TYPE, and returning that argument.
7821
7822 Generates code equivalent to:
7823
7824 if (integral value) {
7825 if (size <= 4 && args.gpr < 5 ||
7826 size > 4 && args.gpr < 4 )
7827 ret = args.reg_save_area[args.gpr+8]
7828 else
7829 ret = *args.overflow_arg_area++;
7830 } else if (float value) {
7831 if (args.fgpr < 2)
7832 ret = args.reg_save_area[args.fpr+64]
7833 else
7834 ret = *args.overflow_arg_area++;
7835 } else if (aggregate value) {
7836 if (args.gpr < 5)
7837 ret = *args.reg_save_area[args.gpr]
7838 else
7839 ret = **args.overflow_arg_area++;
7840 } */
7841
7842 static tree
7843 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
7844 tree *post_p ATTRIBUTE_UNUSED)
7845 {
7846 tree f_gpr, f_fpr, f_ovf, f_sav;
7847 tree gpr, fpr, ovf, sav, reg, t, u;
7848 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
7849 tree lab_false, lab_over, addr;
7850
7851 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7852 f_fpr = TREE_CHAIN (f_gpr);
7853 f_ovf = TREE_CHAIN (f_fpr);
7854 f_sav = TREE_CHAIN (f_ovf);
7855
7856 valist = build_va_arg_indirect_ref (valist);
7857 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7858 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7859 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7860 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7861
7862 size = int_size_in_bytes (type);
7863
7864 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
7865 {
7866 if (TARGET_DEBUG_ARG)
7867 {
7868 fprintf (stderr, "va_arg: aggregate type");
7869 debug_tree (type);
7870 }
7871
7872 /* Aggregates are passed by reference. */
7873 indirect_p = 1;
7874 reg = gpr;
7875 n_reg = 1;
7876
7877 /* kernel stack layout on 31 bit: It is assumed here that no padding
7878 will be added by s390_frame_info because for va_args always an even
7879 number of gprs has to be saved r15-r2 = 14 regs. */
7880 sav_ofs = 2 * UNITS_PER_WORD;
7881 sav_scale = UNITS_PER_WORD;
7882 size = UNITS_PER_WORD;
7883 max_reg = GP_ARG_NUM_REG - n_reg;
7884 }
7885 else if (s390_function_arg_float (TYPE_MODE (type), type))
7886 {
7887 if (TARGET_DEBUG_ARG)
7888 {
7889 fprintf (stderr, "va_arg: float type");
7890 debug_tree (type);
7891 }
7892
7893 /* FP args go in FP registers, if present. */
7894 indirect_p = 0;
7895 reg = fpr;
7896 n_reg = 1;
7897 sav_ofs = 16 * UNITS_PER_WORD;
7898 sav_scale = 8;
7899 max_reg = FP_ARG_NUM_REG - n_reg;
7900 }
7901 else
7902 {
7903 if (TARGET_DEBUG_ARG)
7904 {
7905 fprintf (stderr, "va_arg: other type");
7906 debug_tree (type);
7907 }
7908
7909 /* Otherwise into GP registers. */
7910 indirect_p = 0;
7911 reg = gpr;
7912 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7913
7914 /* kernel stack layout on 31 bit: It is assumed here that no padding
7915 will be added by s390_frame_info because for va_args always an even
7916 number of gprs has to be saved r15-r2 = 14 regs. */
7917 sav_ofs = 2 * UNITS_PER_WORD;
7918
7919 if (size < UNITS_PER_WORD)
7920 sav_ofs += UNITS_PER_WORD - size;
7921
7922 sav_scale = UNITS_PER_WORD;
7923 max_reg = GP_ARG_NUM_REG - n_reg;
7924 }
7925
7926 /* Pull the value out of the saved registers ... */
7927
7928 lab_false = create_artificial_label ();
7929 lab_over = create_artificial_label ();
7930 addr = create_tmp_var (ptr_type_node, "addr");
7931 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
7932
7933 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
7934 t = build2 (GT_EXPR, boolean_type_node, reg, t);
7935 u = build1 (GOTO_EXPR, void_type_node, lab_false);
7936 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
7937 gimplify_and_add (t, pre_p);
7938
7939 t = build2 (PLUS_EXPR, ptr_type_node, sav,
7940 fold_convert (ptr_type_node, size_int (sav_ofs)));
7941 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
7942 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
7943 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
7944
7945 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
7946 gimplify_and_add (t, pre_p);
7947
7948 t = build1 (GOTO_EXPR, void_type_node, lab_over);
7949 gimplify_and_add (t, pre_p);
7950
7951 t = build1 (LABEL_EXPR, void_type_node, lab_false);
7952 append_to_statement_list (t, pre_p);
7953
7954
7955 /* ... Otherwise out of the overflow area. */
7956
7957 t = ovf;
7958 if (size < UNITS_PER_WORD)
7959 t = build2 (PLUS_EXPR, ptr_type_node, t,
7960 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
7961
7962 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7963
7964 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
7965 gimplify_and_add (u, pre_p);
7966
7967 t = build2 (PLUS_EXPR, ptr_type_node, t,
7968 fold_convert (ptr_type_node, size_int (size)));
7969 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
7970 gimplify_and_add (t, pre_p);
7971
7972 t = build1 (LABEL_EXPR, void_type_node, lab_over);
7973 append_to_statement_list (t, pre_p);
7974
7975
7976 /* Increment register save count. */
7977
7978 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
7979 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
7980 gimplify_and_add (u, pre_p);
7981
7982 if (indirect_p)
7983 {
7984 t = build_pointer_type (build_pointer_type (type));
7985 addr = fold_convert (t, addr);
7986 addr = build_va_arg_indirect_ref (addr);
7987 }
7988 else
7989 {
7990 t = build_pointer_type (type);
7991 addr = fold_convert (t, addr);
7992 }
7993
7994 return build_va_arg_indirect_ref (addr);
7995 }
7996
7997
7998 /* Builtins. */
7999
8000 enum s390_builtin
8001 {
8002 S390_BUILTIN_THREAD_POINTER,
8003 S390_BUILTIN_SET_THREAD_POINTER,
8004
8005 S390_BUILTIN_max
8006 };
8007
8008 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8009 CODE_FOR_get_tp_64,
8010 CODE_FOR_set_tp_64
8011 };
8012
8013 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8014 CODE_FOR_get_tp_31,
8015 CODE_FOR_set_tp_31
8016 };
8017
8018 static void
8019 s390_init_builtins (void)
8020 {
8021 tree ftype;
8022
8023 ftype = build_function_type (ptr_type_node, void_list_node);
8024 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
8025 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8026 NULL, NULL_TREE);
8027
8028 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8029 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
8030 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8031 NULL, NULL_TREE);
8032 }
8033
8034 /* Expand an expression EXP that calls a built-in function,
8035 with result going to TARGET if that's convenient
8036 (and in mode MODE if that's convenient).
8037 SUBTARGET may be used as the target for computing one of EXP's operands.
8038 IGNORE is nonzero if the value is to be ignored. */
8039
8040 static rtx
8041 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8042 enum machine_mode mode ATTRIBUTE_UNUSED,
8043 int ignore ATTRIBUTE_UNUSED)
8044 {
8045 #define MAX_ARGS 2
8046
8047 unsigned int const *code_for_builtin =
8048 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8049
8050 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8051 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8052 tree arglist = TREE_OPERAND (exp, 1);
8053 enum insn_code icode;
8054 rtx op[MAX_ARGS], pat;
8055 int arity;
8056 bool nonvoid;
8057
8058 if (fcode >= S390_BUILTIN_max)
8059 internal_error ("bad builtin fcode");
8060 icode = code_for_builtin[fcode];
8061 if (icode == 0)
8062 internal_error ("bad builtin fcode");
8063
8064 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8065
8066 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
8067 arglist;
8068 arglist = TREE_CHAIN (arglist), arity++)
8069 {
8070 const struct insn_operand_data *insn_op;
8071
8072 tree arg = TREE_VALUE (arglist);
8073 if (arg == error_mark_node)
8074 return NULL_RTX;
8075 if (arity > MAX_ARGS)
8076 return NULL_RTX;
8077
8078 insn_op = &insn_data[icode].operand[arity + nonvoid];
8079
8080 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8081
8082 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8083 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8084 }
8085
8086 if (nonvoid)
8087 {
8088 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8089 if (!target
8090 || GET_MODE (target) != tmode
8091 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8092 target = gen_reg_rtx (tmode);
8093 }
8094
8095 switch (arity)
8096 {
8097 case 0:
8098 pat = GEN_FCN (icode) (target);
8099 break;
8100 case 1:
8101 if (nonvoid)
8102 pat = GEN_FCN (icode) (target, op[0]);
8103 else
8104 pat = GEN_FCN (icode) (op[0]);
8105 break;
8106 case 2:
8107 pat = GEN_FCN (icode) (target, op[0], op[1]);
8108 break;
8109 default:
8110 gcc_unreachable ();
8111 }
8112 if (!pat)
8113 return NULL_RTX;
8114 emit_insn (pat);
8115
8116 if (nonvoid)
8117 return target;
8118 else
8119 return const0_rtx;
8120 }
8121
8122
8123 /* Output assembly code for the trampoline template to
8124 stdio stream FILE.
8125
8126 On S/390, we use gpr 1 internally in the trampoline code;
8127 gpr 0 is used to hold the static chain. */
8128
8129 void
8130 s390_trampoline_template (FILE *file)
8131 {
8132 rtx op[2];
8133 op[0] = gen_rtx_REG (Pmode, 0);
8134 op[1] = gen_rtx_REG (Pmode, 1);
8135
8136 if (TARGET_64BIT)
8137 {
8138 output_asm_insn ("basr\t%1,0", op);
8139 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8140 output_asm_insn ("br\t%1", op);
8141 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8142 }
8143 else
8144 {
8145 output_asm_insn ("basr\t%1,0", op);
8146 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8147 output_asm_insn ("br\t%1", op);
8148 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8149 }
8150 }
8151
8152 /* Emit RTL insns to initialize the variable parts of a trampoline.
8153 FNADDR is an RTX for the address of the function's pure code.
8154 CXT is an RTX for the static chain value for the function. */
8155
8156 void
8157 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8158 {
8159 emit_move_insn (gen_rtx_MEM (Pmode,
8160 memory_address (Pmode,
8161 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8162 emit_move_insn (gen_rtx_MEM (Pmode,
8163 memory_address (Pmode,
8164 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8165 }
8166
8167 /* Return rtx for 64-bit constant formed from the 32-bit subwords
8168 LOW and HIGH, independent of the host word size. */
8169
8170 rtx
8171 s390_gen_rtx_const_DI (int high, int low)
8172 {
8173 #if HOST_BITS_PER_WIDE_INT >= 64
8174 HOST_WIDE_INT val;
8175 val = (HOST_WIDE_INT)high;
8176 val <<= 32;
8177 val |= (HOST_WIDE_INT)low;
8178
8179 return GEN_INT (val);
8180 #else
8181 #if HOST_BITS_PER_WIDE_INT >= 32
8182 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
8183 #else
8184 gcc_unreachable ();
8185 #endif
8186 #endif
8187 }
8188
8189 /* Output assembler code to FILE to increment profiler label # LABELNO
8190 for profiling a function entry. */
8191
8192 void
8193 s390_function_profiler (FILE *file, int labelno)
8194 {
8195 rtx op[7];
8196
8197 char label[128];
8198 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8199
8200 fprintf (file, "# function profiler \n");
8201
8202 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8203 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8204 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8205
8206 op[2] = gen_rtx_REG (Pmode, 1);
8207 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8208 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8209
8210 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8211 if (flag_pic)
8212 {
8213 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8214 op[4] = gen_rtx_CONST (Pmode, op[4]);
8215 }
8216
8217 if (TARGET_64BIT)
8218 {
8219 output_asm_insn ("stg\t%0,%1", op);
8220 output_asm_insn ("larl\t%2,%3", op);
8221 output_asm_insn ("brasl\t%0,%4", op);
8222 output_asm_insn ("lg\t%0,%1", op);
8223 }
8224 else if (!flag_pic)
8225 {
8226 op[6] = gen_label_rtx ();
8227
8228 output_asm_insn ("st\t%0,%1", op);
8229 output_asm_insn ("bras\t%2,%l6", op);
8230 output_asm_insn (".long\t%4", op);
8231 output_asm_insn (".long\t%3", op);
8232 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8233 output_asm_insn ("l\t%0,0(%2)", op);
8234 output_asm_insn ("l\t%2,4(%2)", op);
8235 output_asm_insn ("basr\t%0,%0", op);
8236 output_asm_insn ("l\t%0,%1", op);
8237 }
8238 else
8239 {
8240 op[5] = gen_label_rtx ();
8241 op[6] = gen_label_rtx ();
8242
8243 output_asm_insn ("st\t%0,%1", op);
8244 output_asm_insn ("bras\t%2,%l6", op);
8245 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8246 output_asm_insn (".long\t%4-%l5", op);
8247 output_asm_insn (".long\t%3-%l5", op);
8248 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8249 output_asm_insn ("lr\t%0,%2", op);
8250 output_asm_insn ("a\t%0,0(%2)", op);
8251 output_asm_insn ("a\t%2,4(%2)", op);
8252 output_asm_insn ("basr\t%0,%0", op);
8253 output_asm_insn ("l\t%0,%1", op);
8254 }
8255 }
8256
8257 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8258 into its SYMBOL_REF_FLAGS. */
8259
8260 static void
8261 s390_encode_section_info (tree decl, rtx rtl, int first)
8262 {
8263 default_encode_section_info (decl, rtl, first);
8264
8265 /* If a variable has a forced alignment to < 2 bytes, mark it with
8266 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8267 if (TREE_CODE (decl) == VAR_DECL
8268 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8269 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8270 }
8271
8272 /* Output thunk to FILE that implements a C++ virtual function call (with
8273 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8274 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8275 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8276 relative to the resulting this pointer. */
8277
8278 static void
8279 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8280 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8281 tree function)
8282 {
8283 rtx op[10];
8284 int nonlocal = 0;
8285
8286 /* Operand 0 is the target function. */
8287 op[0] = XEXP (DECL_RTL (function), 0);
8288 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8289 {
8290 nonlocal = 1;
8291 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8292 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8293 op[0] = gen_rtx_CONST (Pmode, op[0]);
8294 }
8295
8296 /* Operand 1 is the 'this' pointer. */
8297 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8298 op[1] = gen_rtx_REG (Pmode, 3);
8299 else
8300 op[1] = gen_rtx_REG (Pmode, 2);
8301
8302 /* Operand 2 is the delta. */
8303 op[2] = GEN_INT (delta);
8304
8305 /* Operand 3 is the vcall_offset. */
8306 op[3] = GEN_INT (vcall_offset);
8307
8308 /* Operand 4 is the temporary register. */
8309 op[4] = gen_rtx_REG (Pmode, 1);
8310
8311 /* Operands 5 to 8 can be used as labels. */
8312 op[5] = NULL_RTX;
8313 op[6] = NULL_RTX;
8314 op[7] = NULL_RTX;
8315 op[8] = NULL_RTX;
8316
8317 /* Operand 9 can be used for temporary register. */
8318 op[9] = NULL_RTX;
8319
8320 /* Generate code. */
8321 if (TARGET_64BIT)
8322 {
8323 /* Setup literal pool pointer if required. */
8324 if ((!DISP_IN_RANGE (delta)
8325 && !CONST_OK_FOR_K (delta)
8326 && !CONST_OK_FOR_Os (delta))
8327 || (!DISP_IN_RANGE (vcall_offset)
8328 && !CONST_OK_FOR_K (vcall_offset)
8329 && !CONST_OK_FOR_Os (vcall_offset)))
8330 {
8331 op[5] = gen_label_rtx ();
8332 output_asm_insn ("larl\t%4,%5", op);
8333 }
8334
8335 /* Add DELTA to this pointer. */
8336 if (delta)
8337 {
8338 if (CONST_OK_FOR_J (delta))
8339 output_asm_insn ("la\t%1,%2(%1)", op);
8340 else if (DISP_IN_RANGE (delta))
8341 output_asm_insn ("lay\t%1,%2(%1)", op);
8342 else if (CONST_OK_FOR_K (delta))
8343 output_asm_insn ("aghi\t%1,%2", op);
8344 else if (CONST_OK_FOR_Os (delta))
8345 output_asm_insn ("agfi\t%1,%2", op);
8346 else
8347 {
8348 op[6] = gen_label_rtx ();
8349 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8350 }
8351 }
8352
8353 /* Perform vcall adjustment. */
8354 if (vcall_offset)
8355 {
8356 if (DISP_IN_RANGE (vcall_offset))
8357 {
8358 output_asm_insn ("lg\t%4,0(%1)", op);
8359 output_asm_insn ("ag\t%1,%3(%4)", op);
8360 }
8361 else if (CONST_OK_FOR_K (vcall_offset))
8362 {
8363 output_asm_insn ("lghi\t%4,%3", op);
8364 output_asm_insn ("ag\t%4,0(%1)", op);
8365 output_asm_insn ("ag\t%1,0(%4)", op);
8366 }
8367 else if (CONST_OK_FOR_Os (vcall_offset))
8368 {
8369 output_asm_insn ("lgfi\t%4,%3", op);
8370 output_asm_insn ("ag\t%4,0(%1)", op);
8371 output_asm_insn ("ag\t%1,0(%4)", op);
8372 }
8373 else
8374 {
8375 op[7] = gen_label_rtx ();
8376 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8377 output_asm_insn ("ag\t%4,0(%1)", op);
8378 output_asm_insn ("ag\t%1,0(%4)", op);
8379 }
8380 }
8381
8382 /* Jump to target. */
8383 output_asm_insn ("jg\t%0", op);
8384
8385 /* Output literal pool if required. */
8386 if (op[5])
8387 {
8388 output_asm_insn (".align\t4", op);
8389 targetm.asm_out.internal_label (file, "L",
8390 CODE_LABEL_NUMBER (op[5]));
8391 }
8392 if (op[6])
8393 {
8394 targetm.asm_out.internal_label (file, "L",
8395 CODE_LABEL_NUMBER (op[6]));
8396 output_asm_insn (".long\t%2", op);
8397 }
8398 if (op[7])
8399 {
8400 targetm.asm_out.internal_label (file, "L",
8401 CODE_LABEL_NUMBER (op[7]));
8402 output_asm_insn (".long\t%3", op);
8403 }
8404 }
8405 else
8406 {
8407 /* Setup base pointer if required. */
8408 if (!vcall_offset
8409 || (!DISP_IN_RANGE (delta)
8410 && !CONST_OK_FOR_K (delta)
8411 && !CONST_OK_FOR_Os (delta))
8412 || (!DISP_IN_RANGE (delta)
8413 && !CONST_OK_FOR_K (vcall_offset)
8414 && !CONST_OK_FOR_Os (vcall_offset)))
8415 {
8416 op[5] = gen_label_rtx ();
8417 output_asm_insn ("basr\t%4,0", op);
8418 targetm.asm_out.internal_label (file, "L",
8419 CODE_LABEL_NUMBER (op[5]));
8420 }
8421
8422 /* Add DELTA to this pointer. */
8423 if (delta)
8424 {
8425 if (CONST_OK_FOR_J (delta))
8426 output_asm_insn ("la\t%1,%2(%1)", op);
8427 else if (DISP_IN_RANGE (delta))
8428 output_asm_insn ("lay\t%1,%2(%1)", op);
8429 else if (CONST_OK_FOR_K (delta))
8430 output_asm_insn ("ahi\t%1,%2", op);
8431 else if (CONST_OK_FOR_Os (delta))
8432 output_asm_insn ("afi\t%1,%2", op);
8433 else
8434 {
8435 op[6] = gen_label_rtx ();
8436 output_asm_insn ("a\t%1,%6-%5(%4)", op);
8437 }
8438 }
8439
8440 /* Perform vcall adjustment. */
8441 if (vcall_offset)
8442 {
8443 if (CONST_OK_FOR_J (vcall_offset))
8444 {
8445 output_asm_insn ("l\t%4,0(%1)", op);
8446 output_asm_insn ("a\t%1,%3(%4)", op);
8447 }
8448 else if (DISP_IN_RANGE (vcall_offset))
8449 {
8450 output_asm_insn ("l\t%4,0(%1)", op);
8451 output_asm_insn ("ay\t%1,%3(%4)", op);
8452 }
8453 else if (CONST_OK_FOR_K (vcall_offset))
8454 {
8455 output_asm_insn ("lhi\t%4,%3", op);
8456 output_asm_insn ("a\t%4,0(%1)", op);
8457 output_asm_insn ("a\t%1,0(%4)", op);
8458 }
8459 else if (CONST_OK_FOR_Os (vcall_offset))
8460 {
8461 output_asm_insn ("iilf\t%4,%3", op);
8462 output_asm_insn ("a\t%4,0(%1)", op);
8463 output_asm_insn ("a\t%1,0(%4)", op);
8464 }
8465 else
8466 {
8467 op[7] = gen_label_rtx ();
8468 output_asm_insn ("l\t%4,%7-%5(%4)", op);
8469 output_asm_insn ("a\t%4,0(%1)", op);
8470 output_asm_insn ("a\t%1,0(%4)", op);
8471 }
8472
8473 /* We had to clobber the base pointer register.
8474 Re-setup the base pointer (with a different base). */
8475 op[5] = gen_label_rtx ();
8476 output_asm_insn ("basr\t%4,0", op);
8477 targetm.asm_out.internal_label (file, "L",
8478 CODE_LABEL_NUMBER (op[5]));
8479 }
8480
8481 /* Jump to target. */
8482 op[8] = gen_label_rtx ();
8483
8484 if (!flag_pic)
8485 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8486 else if (!nonlocal)
8487 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8488 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8489 else if (flag_pic == 1)
8490 {
8491 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8492 output_asm_insn ("l\t%4,%0(%4)", op);
8493 }
8494 else if (flag_pic == 2)
8495 {
8496 op[9] = gen_rtx_REG (Pmode, 0);
8497 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8498 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8499 output_asm_insn ("ar\t%4,%9", op);
8500 output_asm_insn ("l\t%4,0(%4)", op);
8501 }
8502
8503 output_asm_insn ("br\t%4", op);
8504
8505 /* Output literal pool. */
8506 output_asm_insn (".align\t4", op);
8507
8508 if (nonlocal && flag_pic == 2)
8509 output_asm_insn (".long\t%0", op);
8510 if (nonlocal)
8511 {
8512 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8513 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8514 }
8515
8516 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8517 if (!flag_pic)
8518 output_asm_insn (".long\t%0", op);
8519 else
8520 output_asm_insn (".long\t%0-%5", op);
8521
8522 if (op[6])
8523 {
8524 targetm.asm_out.internal_label (file, "L",
8525 CODE_LABEL_NUMBER (op[6]));
8526 output_asm_insn (".long\t%2", op);
8527 }
8528 if (op[7])
8529 {
8530 targetm.asm_out.internal_label (file, "L",
8531 CODE_LABEL_NUMBER (op[7]));
8532 output_asm_insn (".long\t%3", op);
8533 }
8534 }
8535 }
8536
8537 static bool
8538 s390_valid_pointer_mode (enum machine_mode mode)
8539 {
8540 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8541 }
8542
8543 /* Checks whether the given ARGUMENT_LIST would use a caller
8544 saved register. This is used to decide whether sibling call
8545 optimization could be performed on the respective function
8546 call. */
8547
8548 static bool
8549 s390_call_saved_register_used (tree argument_list)
8550 {
8551 CUMULATIVE_ARGS cum;
8552 tree parameter;
8553 enum machine_mode mode;
8554 tree type;
8555 rtx parm_rtx;
8556 int reg;
8557
8558 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8559
8560 while (argument_list)
8561 {
8562 parameter = TREE_VALUE (argument_list);
8563 argument_list = TREE_CHAIN (argument_list);
8564
8565 gcc_assert (parameter);
8566
8567 /* For an undeclared variable passed as parameter we will get
8568 an ERROR_MARK node here. */
8569 if (TREE_CODE (parameter) == ERROR_MARK)
8570 return true;
8571
8572 type = TREE_TYPE (parameter);
8573 gcc_assert (type);
8574
8575 mode = TYPE_MODE (type);
8576 gcc_assert (mode);
8577
8578 if (pass_by_reference (&cum, mode, type, true))
8579 {
8580 mode = Pmode;
8581 type = build_pointer_type (type);
8582 }
8583
8584 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8585
8586 s390_function_arg_advance (&cum, mode, type, 0);
8587
8588 if (parm_rtx && REG_P (parm_rtx))
8589 {
8590 for (reg = 0;
8591 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8592 reg++)
8593 if (! call_used_regs[reg + REGNO (parm_rtx)])
8594 return true;
8595 }
8596 }
8597 return false;
8598 }
8599
8600 /* Return true if the given call expression can be
8601 turned into a sibling call.
8602 DECL holds the declaration of the function to be called whereas
8603 EXP is the call expression itself. */
8604
8605 static bool
8606 s390_function_ok_for_sibcall (tree decl, tree exp)
8607 {
8608 /* The TPF epilogue uses register 1. */
8609 if (TARGET_TPF_PROFILING)
8610 return false;
8611
8612 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8613 which would have to be restored before the sibcall. */
8614 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
8615 return false;
8616
8617 /* Register 6 on s390 is available as an argument register but unfortunately
8618 "caller saved". This makes functions needing this register for arguments
8619 not suitable for sibcalls. */
8620 if (TREE_OPERAND (exp, 1)
8621 && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8622 return false;
8623
8624 return true;
8625 }
8626
8627 /* Return the fixed registers used for condition codes. */
8628
8629 static bool
8630 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8631 {
8632 *p1 = CC_REGNUM;
8633 *p2 = INVALID_REGNUM;
8634
8635 return true;
8636 }
8637
8638 /* This function is used by the call expanders of the machine description.
8639 It emits the call insn itself together with the necessary operations
8640 to adjust the target address and returns the emitted insn.
8641 ADDR_LOCATION is the target address rtx
8642 TLS_CALL the location of the thread-local symbol
8643 RESULT_REG the register where the result of the call should be stored
8644 RETADDR_REG the register where the return address should be stored
8645 If this parameter is NULL_RTX the call is considered
8646 to be a sibling call. */
8647
8648 rtx
8649 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8650 rtx retaddr_reg)
8651 {
8652 bool plt_call = false;
8653 rtx insn;
8654 rtx call;
8655 rtx clobber;
8656 rtvec vec;
8657
8658 /* Direct function calls need special treatment. */
8659 if (GET_CODE (addr_location) == SYMBOL_REF)
8660 {
8661 /* When calling a global routine in PIC mode, we must
8662 replace the symbol itself with the PLT stub. */
8663 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8664 {
8665 addr_location = gen_rtx_UNSPEC (Pmode,
8666 gen_rtvec (1, addr_location),
8667 UNSPEC_PLT);
8668 addr_location = gen_rtx_CONST (Pmode, addr_location);
8669 plt_call = true;
8670 }
8671
8672 /* Unless we can use the bras(l) insn, force the
8673 routine address into a register. */
8674 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8675 {
8676 if (flag_pic)
8677 addr_location = legitimize_pic_address (addr_location, 0);
8678 else
8679 addr_location = force_reg (Pmode, addr_location);
8680 }
8681 }
8682
8683 /* If it is already an indirect call or the code above moved the
8684 SYMBOL_REF to somewhere else make sure the address can be found in
8685 register 1. */
8686 if (retaddr_reg == NULL_RTX
8687 && GET_CODE (addr_location) != SYMBOL_REF
8688 && !plt_call)
8689 {
8690 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8691 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8692 }
8693
8694 addr_location = gen_rtx_MEM (QImode, addr_location);
8695 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8696
8697 if (result_reg != NULL_RTX)
8698 call = gen_rtx_SET (VOIDmode, result_reg, call);
8699
8700 if (retaddr_reg != NULL_RTX)
8701 {
8702 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8703
8704 if (tls_call != NULL_RTX)
8705 vec = gen_rtvec (3, call, clobber,
8706 gen_rtx_USE (VOIDmode, tls_call));
8707 else
8708 vec = gen_rtvec (2, call, clobber);
8709
8710 call = gen_rtx_PARALLEL (VOIDmode, vec);
8711 }
8712
8713 insn = emit_call_insn (call);
8714
8715 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8716 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8717 {
8718 /* s390_function_ok_for_sibcall should
8719 have denied sibcalls in this case. */
8720 gcc_assert (retaddr_reg != NULL_RTX);
8721
8722 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8723 }
8724 return insn;
8725 }
8726
8727 /* Implement CONDITIONAL_REGISTER_USAGE. */
8728
8729 void
8730 s390_conditional_register_usage (void)
8731 {
8732 int i;
8733
8734 if (flag_pic)
8735 {
8736 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8737 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8738 }
8739 if (TARGET_CPU_ZARCH)
8740 {
8741 fixed_regs[BASE_REGNUM] = 0;
8742 call_used_regs[BASE_REGNUM] = 0;
8743 fixed_regs[RETURN_REGNUM] = 0;
8744 call_used_regs[RETURN_REGNUM] = 0;
8745 }
8746 if (TARGET_64BIT)
8747 {
8748 for (i = 24; i < 32; i++)
8749 call_used_regs[i] = call_really_used_regs[i] = 0;
8750 }
8751 else
8752 {
8753 for (i = 18; i < 20; i++)
8754 call_used_regs[i] = call_really_used_regs[i] = 0;
8755 }
8756
8757 if (TARGET_SOFT_FLOAT)
8758 {
8759 for (i = 16; i < 32; i++)
8760 call_used_regs[i] = fixed_regs[i] = 1;
8761 }
8762 }
8763
8764 /* Corresponding function to eh_return expander. */
8765
8766 static GTY(()) rtx s390_tpf_eh_return_symbol;
8767 void
8768 s390_emit_tpf_eh_return (rtx target)
8769 {
8770 rtx insn, reg;
8771
8772 if (!s390_tpf_eh_return_symbol)
8773 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8774
8775 reg = gen_rtx_REG (Pmode, 2);
8776
8777 emit_move_insn (reg, target);
8778 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8779 gen_rtx_REG (Pmode, RETURN_REGNUM));
8780 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8781
8782 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8783 }
8784
8785 /* Rework the prologue/epilogue to avoid saving/restoring
8786 registers unnecessarily. */
8787
8788 static void
8789 s390_optimize_prologue (void)
8790 {
8791 rtx insn, new_insn, next_insn;
8792
8793 /* Do a final recompute of the frame-related data. */
8794
8795 s390_update_frame_layout ();
8796
8797 /* If all special registers are in fact used, there's nothing we
8798 can do, so no point in walking the insn list. */
8799
8800 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8801 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8802 && (TARGET_CPU_ZARCH
8803 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8804 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8805 return;
8806
8807 /* Search for prologue/epilogue insns and replace them. */
8808
8809 for (insn = get_insns (); insn; insn = next_insn)
8810 {
8811 int first, last, off;
8812 rtx set, base, offset;
8813
8814 next_insn = NEXT_INSN (insn);
8815
8816 if (GET_CODE (insn) != INSN)
8817 continue;
8818
8819 if (GET_CODE (PATTERN (insn)) == PARALLEL
8820 && store_multiple_operation (PATTERN (insn), VOIDmode))
8821 {
8822 set = XVECEXP (PATTERN (insn), 0, 0);
8823 first = REGNO (SET_SRC (set));
8824 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8825 offset = const0_rtx;
8826 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8827 off = INTVAL (offset);
8828
8829 if (GET_CODE (base) != REG || off < 0)
8830 continue;
8831 if (cfun_frame_layout.first_save_gpr != -1
8832 && (cfun_frame_layout.first_save_gpr < first
8833 || cfun_frame_layout.last_save_gpr > last))
8834 continue;
8835 if (REGNO (base) != STACK_POINTER_REGNUM
8836 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8837 continue;
8838 if (first > BASE_REGNUM || last < BASE_REGNUM)
8839 continue;
8840
8841 if (cfun_frame_layout.first_save_gpr != -1)
8842 {
8843 new_insn = save_gprs (base,
8844 off + (cfun_frame_layout.first_save_gpr
8845 - first) * UNITS_PER_WORD,
8846 cfun_frame_layout.first_save_gpr,
8847 cfun_frame_layout.last_save_gpr);
8848 new_insn = emit_insn_before (new_insn, insn);
8849 INSN_ADDRESSES_NEW (new_insn, -1);
8850 }
8851
8852 remove_insn (insn);
8853 continue;
8854 }
8855
8856 if (cfun_frame_layout.first_save_gpr == -1
8857 && GET_CODE (PATTERN (insn)) == SET
8858 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
8859 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
8860 || (!TARGET_CPU_ZARCH
8861 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
8862 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
8863 {
8864 set = PATTERN (insn);
8865 first = REGNO (SET_SRC (set));
8866 offset = const0_rtx;
8867 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8868 off = INTVAL (offset);
8869
8870 if (GET_CODE (base) != REG || off < 0)
8871 continue;
8872 if (REGNO (base) != STACK_POINTER_REGNUM
8873 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8874 continue;
8875
8876 remove_insn (insn);
8877 continue;
8878 }
8879
8880 if (GET_CODE (PATTERN (insn)) == PARALLEL
8881 && load_multiple_operation (PATTERN (insn), VOIDmode))
8882 {
8883 set = XVECEXP (PATTERN (insn), 0, 0);
8884 first = REGNO (SET_DEST (set));
8885 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8886 offset = const0_rtx;
8887 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8888 off = INTVAL (offset);
8889
8890 if (GET_CODE (base) != REG || off < 0)
8891 continue;
8892 if (cfun_frame_layout.first_restore_gpr != -1
8893 && (cfun_frame_layout.first_restore_gpr < first
8894 || cfun_frame_layout.last_restore_gpr > last))
8895 continue;
8896 if (REGNO (base) != STACK_POINTER_REGNUM
8897 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8898 continue;
8899 if (first > BASE_REGNUM || last < BASE_REGNUM)
8900 continue;
8901
8902 if (cfun_frame_layout.first_restore_gpr != -1)
8903 {
8904 new_insn = restore_gprs (base,
8905 off + (cfun_frame_layout.first_restore_gpr
8906 - first) * UNITS_PER_WORD,
8907 cfun_frame_layout.first_restore_gpr,
8908 cfun_frame_layout.last_restore_gpr);
8909 new_insn = emit_insn_before (new_insn, insn);
8910 INSN_ADDRESSES_NEW (new_insn, -1);
8911 }
8912
8913 remove_insn (insn);
8914 continue;
8915 }
8916
8917 if (cfun_frame_layout.first_restore_gpr == -1
8918 && GET_CODE (PATTERN (insn)) == SET
8919 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
8920 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
8921 || (!TARGET_CPU_ZARCH
8922 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
8923 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
8924 {
8925 set = PATTERN (insn);
8926 first = REGNO (SET_DEST (set));
8927 offset = const0_rtx;
8928 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8929 off = INTVAL (offset);
8930
8931 if (GET_CODE (base) != REG || off < 0)
8932 continue;
8933 if (REGNO (base) != STACK_POINTER_REGNUM
8934 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8935 continue;
8936
8937 remove_insn (insn);
8938 continue;
8939 }
8940 }
8941 }
8942
8943 /* Perform machine-dependent processing. */
8944
8945 static void
8946 s390_reorg (void)
8947 {
8948 bool pool_overflow = false;
8949
8950 /* Make sure all splits have been performed; splits after
8951 machine_dependent_reorg might confuse insn length counts. */
8952 split_all_insns_noflow ();
8953
8954
8955 /* Install the main literal pool and the associated base
8956 register load insns.
8957
8958 In addition, there are two problematic situations we need
8959 to correct:
8960
8961 - the literal pool might be > 4096 bytes in size, so that
8962 some of its elements cannot be directly accessed
8963
8964 - a branch target might be > 64K away from the branch, so that
8965 it is not possible to use a PC-relative instruction.
8966
8967 To fix those, we split the single literal pool into multiple
8968 pool chunks, reloading the pool base register at various
8969 points throughout the function to ensure it always points to
8970 the pool chunk the following code expects, and / or replace
8971 PC-relative branches by absolute branches.
8972
8973 However, the two problems are interdependent: splitting the
8974 literal pool can move a branch further away from its target,
8975 causing the 64K limit to overflow, and on the other hand,
8976 replacing a PC-relative branch by an absolute branch means
8977 we need to put the branch target address into the literal
8978 pool, possibly causing it to overflow.
8979
8980 So, we loop trying to fix up both problems until we manage
8981 to satisfy both conditions at the same time. Note that the
8982 loop is guaranteed to terminate as every pass of the loop
8983 strictly decreases the total number of PC-relative branches
8984 in the function. (This is not completely true as there
8985 might be branch-over-pool insns introduced by chunkify_start.
8986 Those never need to be split however.) */
8987
8988 for (;;)
8989 {
8990 struct constant_pool *pool = NULL;
8991
8992 /* Collect the literal pool. */
8993 if (!pool_overflow)
8994 {
8995 pool = s390_mainpool_start ();
8996 if (!pool)
8997 pool_overflow = true;
8998 }
8999
9000 /* If literal pool overflowed, start to chunkify it. */
9001 if (pool_overflow)
9002 pool = s390_chunkify_start ();
9003
9004 /* Split out-of-range branches. If this has created new
9005 literal pool entries, cancel current chunk list and
9006 recompute it. zSeries machines have large branch
9007 instructions, so we never need to split a branch. */
9008 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9009 {
9010 if (pool_overflow)
9011 s390_chunkify_cancel (pool);
9012 else
9013 s390_mainpool_cancel (pool);
9014
9015 continue;
9016 }
9017
9018 /* If we made it up to here, both conditions are satisfied.
9019 Finish up literal pool related changes. */
9020 if (pool_overflow)
9021 s390_chunkify_finish (pool);
9022 else
9023 s390_mainpool_finish (pool);
9024
9025 /* We're done splitting branches. */
9026 cfun->machine->split_branches_pending_p = false;
9027 break;
9028 }
9029
9030 /* Generate out-of-pool execute target insns. */
9031 if (TARGET_CPU_ZARCH)
9032 {
9033 rtx insn, label, target;
9034
9035 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9036 {
9037 label = s390_execute_label (insn);
9038 if (!label)
9039 continue;
9040
9041 gcc_assert (label != const0_rtx);
9042
9043 target = emit_label (XEXP (label, 0));
9044 INSN_ADDRESSES_NEW (target, -1);
9045
9046 target = emit_insn (s390_execute_target (insn));
9047 INSN_ADDRESSES_NEW (target, -1);
9048 }
9049 }
9050
9051 /* Try to optimize prologue and epilogue further. */
9052 s390_optimize_prologue ();
9053 }
9054
9055
9056 /* Initialize GCC target structure. */
9057
9058 #undef TARGET_ASM_ALIGNED_HI_OP
9059 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9060 #undef TARGET_ASM_ALIGNED_DI_OP
9061 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9062 #undef TARGET_ASM_INTEGER
9063 #define TARGET_ASM_INTEGER s390_assemble_integer
9064
9065 #undef TARGET_ASM_OPEN_PAREN
9066 #define TARGET_ASM_OPEN_PAREN ""
9067
9068 #undef TARGET_ASM_CLOSE_PAREN
9069 #define TARGET_ASM_CLOSE_PAREN ""
9070
9071 #undef TARGET_DEFAULT_TARGET_FLAGS
9072 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9073 #undef TARGET_HANDLE_OPTION
9074 #define TARGET_HANDLE_OPTION s390_handle_option
9075
9076 #undef TARGET_ENCODE_SECTION_INFO
9077 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9078
9079 #ifdef HAVE_AS_TLS
9080 #undef TARGET_HAVE_TLS
9081 #define TARGET_HAVE_TLS true
9082 #endif
9083 #undef TARGET_CANNOT_FORCE_CONST_MEM
9084 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9085
9086 #undef TARGET_DELEGITIMIZE_ADDRESS
9087 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9088
9089 #undef TARGET_RETURN_IN_MEMORY
9090 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9091
9092 #undef TARGET_INIT_BUILTINS
9093 #define TARGET_INIT_BUILTINS s390_init_builtins
9094 #undef TARGET_EXPAND_BUILTIN
9095 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9096
9097 #undef TARGET_ASM_OUTPUT_MI_THUNK
9098 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9099 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9100 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9101
9102 #undef TARGET_SCHED_ADJUST_PRIORITY
9103 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9104 #undef TARGET_SCHED_ISSUE_RATE
9105 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9106 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9107 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9108
9109 #undef TARGET_CANNOT_COPY_INSN_P
9110 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9111 #undef TARGET_RTX_COSTS
9112 #define TARGET_RTX_COSTS s390_rtx_costs
9113 #undef TARGET_ADDRESS_COST
9114 #define TARGET_ADDRESS_COST s390_address_cost
9115
9116 #undef TARGET_MACHINE_DEPENDENT_REORG
9117 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9118
9119 #undef TARGET_VALID_POINTER_MODE
9120 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9121
9122 #undef TARGET_BUILD_BUILTIN_VA_LIST
9123 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9124 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9125 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9126
9127 #undef TARGET_PROMOTE_FUNCTION_ARGS
9128 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9129 #undef TARGET_PROMOTE_FUNCTION_RETURN
9130 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9131 #undef TARGET_PASS_BY_REFERENCE
9132 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9133
9134 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9135 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9136
9137 #undef TARGET_FIXED_CONDITION_CODE_REGS
9138 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9139
9140 #undef TARGET_CC_MODES_COMPATIBLE
9141 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9142
9143 #undef TARGET_INVALID_WITHIN_DOLOOP
9144 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9145
9146 #ifdef HAVE_AS_TLS
9147 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9148 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9149 #endif
9150
9151 struct gcc_target targetm = TARGET_INITIALIZER;
9152
9153 #include "gt-s390.h"
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