| blob | 6f8995a6648e564627340802dd0ccc1c0789fbbb |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
58 /* Not really meaningful values, but at least something. */
59 #ifndef SIMULTANEOUS_PREFETCHES
60 #define SIMULTANEOUS_PREFETCHES 3
61 #endif
62 #ifndef PREFETCH_BLOCK
63 #define PREFETCH_BLOCK 32
64 #endif
65 #ifndef HAVE_prefetch
66 #define HAVE_prefetch 0
67 #define CODE_FOR_prefetch 0
68 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
69 #endif
71 /* Give up the prefetch optimizations once we exceed a given threshhold.
72 It is unlikely that we would be able to optimize something in a loop
73 with so many detected prefetches. */
74 #define MAX_PREFETCHES 100
75 /* The number of prefetch blocks that are beneficial to fetch at once before
76 a loop with a known (and low) iteration count. */
77 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
78 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
79 since it is likely that the data are already in the cache. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
82 /* Parameterize some prefetch heuristics so they can be turned on and off
83 easily for performance testing on new architecures. These can be
84 defined in target-dependent files. */
86 /* Prefetch is worthwhile only when loads/stores are dense. */
87 #ifndef PREFETCH_ONLY_DENSE_MEM
88 #define PREFETCH_ONLY_DENSE_MEM 1
89 #endif
91 /* Define what we mean by "dense" loads and stores; This value divided by 256
92 is the minimum percentage of memory references that worth prefetching. */
93 #ifndef PREFETCH_DENSE_MEM
94 #define PREFETCH_DENSE_MEM 220
95 #endif
97 /* Do not prefetch for a loop whose iteration count is known to be low. */
98 #ifndef PREFETCH_NO_LOW_LOOPCNT
99 #define PREFETCH_NO_LOW_LOOPCNT 1
100 #endif
102 /* Define what we mean by a "low" iteration count. */
103 #ifndef PREFETCH_LOW_LOOPCNT
104 #define PREFETCH_LOW_LOOPCNT 32
105 #endif
107 /* Do not prefetch for a loop that contains a function call; such a loop is
108 probably not an internal loop. */
109 #ifndef PREFETCH_NO_CALL
110 #define PREFETCH_NO_CALL 1
111 #endif
113 /* Do not prefetch accesses with an extreme stride. */
114 #ifndef PREFETCH_NO_EXTREME_STRIDE
115 #define PREFETCH_NO_EXTREME_STRIDE 1
116 #endif
118 /* Define what we mean by an "extreme" stride. */
119 #ifndef PREFETCH_EXTREME_STRIDE
120 #define PREFETCH_EXTREME_STRIDE 4096
121 #endif
123 /* Define a limit to how far apart indices can be and still be merged
124 into a single prefetch. */
125 #ifndef PREFETCH_EXTREME_DIFFERENCE
126 #define PREFETCH_EXTREME_DIFFERENCE 4096
127 #endif
129 /* Issue prefetch instructions before the loop to fetch data to be used
130 in the first few loop iterations. */
131 #ifndef PREFETCH_BEFORE_LOOP
132 #define PREFETCH_BEFORE_LOOP 1
133 #endif
135 /* Do not handle reversed order prefetches (negative stride). */
136 #ifndef PREFETCH_NO_REVERSE_ORDER
137 #define PREFETCH_NO_REVERSE_ORDER 1
138 #endif
140 /* Prefetch even if the GIV is in conditional code. */
141 #ifndef PREFETCH_CONDITIONAL
142 #define PREFETCH_CONDITIONAL 1
143 #endif
145 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
146 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
148 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
150 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
152 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
153 ((REGNO) < FIRST_PSEUDO_REGISTER \
154 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
157 /* Vector mapping INSN_UIDs to luids.
158 The luids are like uids but increase monotonically always.
159 We use them to see whether a jump comes from outside a given loop. */
163 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
164 number the insn is contained in. */
168 /* 1 + largest uid of any insn. */
172 /* 1 + luid of last insn. */
176 /* Number of loops detected in current function. Used as index to the
177 next few tables. */
181 /* Bound on pseudo register number before loop optimization.
182 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
185 /* The value to pass to the next call of reg_scan_update. */
187 \f
188 /* During the analysis of a loop, a chain of `struct movable's
189 is made to record all the movable insns found.
190 Then the entire chain can be scanned to decide which to move. */
192 struct movable
193 {
198 of any registers used within the LIBCALL. */
200 that must be moved with this one. */
203 may be adjusted when matching movables
204 that load the same value are found. */
206 including other movables that force this
207 or match this one. */
211 /* If PARTIAL is 1, GLOBAL means something different:
212 that the reg is live outside the range from where it is set
213 to the following label. */
217 In particular, moving it does not make it
218 invariant. */
220 load SRC, rather than copying INSN. */
222 first insn of a consecutive sets group. */
225 that we should avoid changing when clearing
226 the rest of the reg. */
230 };
235 /* Forward declarations. */
250 #if 0
252 #endif
282 rtx *));
365 {
366 rtx r1;
367 rtx r2;
371 {
372 rtx match;
373 rtx replacement;
374 rtx insn;
377 /* Nonzero iff INSN is between START and END, inclusive. */
378 #define INSN_IN_RANGE_P(INSN, START, END) \
379 (INSN_UID (INSN) < max_uid_for_loop \
380 && INSN_LUID (INSN) >= INSN_LUID (START) \
381 && INSN_LUID (INSN) <= INSN_LUID (END))
383 /* Indirect_jump_in_function is computed once per function. */
391 rtx));
392 \f
393 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
394 copy the value of the strength reduced giv to its original register. */
397 /* Cost of using a register, to normalize the benefits of a giv. */
400 void
402 {
408 }
409 \f
410 /* Compute the mapping from uids to luids.
411 LUIDs are numbers assigned to insns, like uids,
412 except that luids increase monotonically through the code.
413 Start at insn START and stop just before END. Assign LUIDs
414 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
415 static int
419 {
421 rtx insn;
424 {
427 /* Don't assign luids to line-number NOTEs, so that the distance in
428 luids between two insns is not affected by -g. */
432 else
433 /* Give a line number note the same luid as preceding insn. */
435 }
437 }
438 \f
439 /* Entry point of this file. Perform loop optimization
440 on the current function. F is the first insn of the function
441 and DUMPFILE is a stream for output of a trace of actions taken
442 (or 0 if none should be output). */
444 void
446 /* f is the first instruction of a chain of insns for one function */
447 rtx f;
450 {
451 rtx insn;
466 /* Count the number of loops. */
470 {
473 max_loop_num++;
474 }
476 /* Don't waste time if no loops. */
482 /* Get size to use for tables indexed by uids.
483 Leave some space for labels allocated by find_and_verify_loops. */
490 /* Allocate storage for array of loops. */
494 /* Find and process each loop.
495 First, find them, and record them in order of their beginnings. */
498 /* Allocate and initialize auxiliary loop information. */
503 /* Now find all register lifetimes. This must be done after
504 find_and_verify_loops, because it might reorder the insns in the
505 function. */
508 /* This must occur after reg_scan so that registers created by gcse
509 will have entries in the register tables.
511 We could have added a call to reg_scan after gcse_main in toplev.c,
512 but moving this call to init_alias_analysis is more efficient. */
515 /* See if we went too far. Note that get_max_uid already returns
516 one more that the maximum uid of all insn. */
519 /* Now reset it to the actual size we need. See above. */
522 /* find_and_verify_loops has already called compute_luids, but it
523 might have rearranged code afterwards, so we need to recompute
524 the luids now. */
527 /* Don't leave gaps in uid_luid for insns that have been
528 deleted. It is possible that the first or last insn
529 using some register has been deleted by cross-jumping.
530 Make sure that uid_luid for that former insn's uid
531 points to the general area where that insn used to be. */
533 {
537 }
542 /* Determine if the function has indirect jump. On some systems
543 this prevents low overhead loop instructions from being used. */
546 /* Now scan the loops, last ones first, since this means inner ones are done
547 before outer ones. */
549 {
554 }
558 /* Clean up. */
563 }
564 \f
565 /* Returns the next insn, in execution order, after INSN. START and
566 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
567 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
568 insn-stream; it is used with loops that are entered near the
569 bottom. */
571 static rtx
574 rtx insn;
575 {
579 {
581 /* Go to the top of the loop, and continue there. */
583 else
584 /* We're done. */
586 }
589 /* We're done. */
593 }
595 /* Optimize one loop described by LOOP. */
597 /* ??? Could also move memory writes out of loops if the destination address
598 is invariant, the source is invariant, the memory write is not volatile,
599 and if we can prove that no read inside the loop can read this address
600 before the write occurs. If there is a read of this address after the
601 write, then we can also mark the memory read as invariant. */
603 static void
607 {
613 rtx p;
614 /* 1 if we are scanning insns that could be executed zero times. */
616 /* 1 if we are scanning insns that might never be executed
617 due to a subroutine call which might exit before they are reached. */
619 /* Jump insn that enters the loop, or 0 if control drops in. */
621 /* Number of insns in the loop. */
625 /* The SET from an insn, if it is the only SET in the insn. */
627 /* Chain describing insns movable in current loop. */
629 /* Ratio of extra register life span we can justify
630 for saving an instruction. More if loop doesn't call subroutines
631 since in that case saving an insn makes more difference
632 and more registers are available. */
634 /* Nonzero if we are scanning instructions in a sub-loop. */
643 /* Determine whether this loop starts with a jump down to a test at
644 the end. This will occur for a small number of loops with a test
645 that is too complex to duplicate in front of the loop.
647 We search for the first insn or label in the loop, skipping NOTEs.
648 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
649 (because we might have a loop executed only once that contains a
650 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
651 (in case we have a degenerate loop).
653 Note that if we mistakenly think that a loop is entered at the top
654 when, in fact, it is entered at the exit test, the only effect will be
655 slightly poorer optimization. Making the opposite error can generate
656 incorrect code. Since very few loops now start with a jump to the
657 exit test, the code here to detect that case is very conservative. */
660 p != loop_end
666 ;
670 /* If loop end is the end of the current function, then emit a
671 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
672 note insn. This is the position we use when sinking insns out of
673 the loop. */
676 else
679 /* Set up variables describing this loop. */
683 /* If loop has a jump before the first label,
684 the true entry is the target of that jump.
685 Start scan from there.
686 But record in LOOP->TOP the place where the end-test jumps
687 back to so we can scan that after the end of the loop. */
689 {
692 /* Loop entry must be unconditional jump (and not a RETURN) */
695 /* Check to see whether the jump actually
696 jumps out of the loop (meaning it's no loop).
697 This case can happen for things like
698 do {..} while (0). If this label was generated previously
699 by loop, we can't tell anything about it and have to reject
700 the loop. */
702 {
705 }
706 }
708 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
709 as required by loop_reg_used_before_p. So skip such loops. (This
710 test may never be true, but it's best to play it safe.)
712 Also, skip loops where we do not start scanning at a label. This
713 test also rejects loops starting with a JUMP_INSN that failed the
714 test above. */
718 {
723 }
725 /* Allocate extra space for REGs that might be created by load_mems.
726 We allocate a little extra slop as well, in the hopes that we
727 won't have to reallocate the regs array. */
732 {
738 }
740 /* Scan through the loop finding insns that are safe to move.
741 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
742 this reg will be considered invariant for subsequent insns.
743 We consider whether subsequent insns use the reg
744 in deciding whether it is worth actually moving.
746 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
747 and therefore it is possible that the insns we are scanning
748 would never be executed. At such times, we must make sure
749 that it is safe to execute the insn once instead of zero times.
750 When MAYBE_NEVER is 0, all insns will be executed at least once
751 so that is not a problem. */
756 {
758 in_libcall--;
760 {
763 in_libcall++;
767 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
769 #endif
771 {
778 /* Figure out what to use as a source of this insn. If a
779 REG_EQUIV note is given or if a REG_EQUAL note with a
780 constant operand is specified, use it as the source and
781 mark that we should move this insn by calling
782 emit_move_insn rather that duplicating the insn.
784 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
785 note is present. */
789 else
790 {
795 {
797 /* A libcall block can use regs that don't appear in
798 the equivalent expression. To move the libcall,
799 we must move those regs too. */
801 }
802 }
804 /* For parallels, add any possible uses to the depencies, as
805 we can't move the insn without resolving them first. */
807 {
809 {
812 dependencies
814 dependencies);
815 }
816 }
818 /* Don't try to optimize a register that was made
819 by loop-optimization for an inner loop.
820 We don't know its life-span, so we can't compute
821 the benefit. */
823 ;
825 than the one where it is set (meaning that
826 something after this point in the loop might
827 depend on its value before the set). */
829 /* And the set is not guaranteed to be executed once
830 the loop starts, or the value before the set is
831 needed before the set occurs...
833 ??? Note we have quadratic behaviour here, mitigated
834 by the fact that the previous test will often fail for
835 large loops. Rather than re-scanning the entire loop
836 each time for register usage, we should build tables
837 of the register usage and use them here instead. */
838 && (maybe_never
840 /* It is unsafe to move the set.
842 This code used to consider it OK to move a set of a variable
843 which was not created by the user and not used in an exit
844 test.
845 That behavior is incorrect and was removed. */
846 ;
849 || (tem2
852 || (tem1
853 = consec_sets_invariant_p
856 p)))
857 /* If the insn can cause a trap (such as divide by zero),
858 can't move it unless it's guaranteed to be executed
859 once loop is entered. Even a function call might
860 prevent the trap insn from being reached
861 (since it might exit!) */
864 {
868 /* A potential lossage is where we have a case where two insns
869 can be combined as long as they are both in the loop, but
870 we move one of them outside the loop. For large loops,
871 this can lose. The most common case of this is the address
872 of a function being called.
874 Therefore, if this register is marked as being used
875 exactly once if we are in a loop with calls
876 (a "large loop"), see if we can replace the usage of
877 this register with the source of this SET. If we can,
878 delete this insn.
880 Don't do this if P has a REG_RETVAL note or if we have
881 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
893 && (! SMALL_REGISTER_CLASSES
897 /* This test is not redundant; SET_SRC (set) might be
898 a call-clobbered register and the life of REGNO
899 might span a call. */
906 {
907 /* Replace any usage in a REG_EQUAL note. Must copy
908 the new source, so that we don't get rtx sharing
909 between the SET_SOURCE and REG_NOTES of insn p. */
911 = (replace_rtx
917 i++)
920 }
929 m->consec
939 /* Set M->cond if either loop_invariant_p
940 or consec_sets_invariant_p returned 2
941 (only conditionally invariant). */
951 /* Add M to the end of the chain MOVABLES. */
955 {
956 /* It is possible for the first instruction to have a
957 REG_EQUAL note but a non-invariant SET_SRC, so we must
958 remember the status of the first instruction in case
959 the last instruction doesn't have a REG_EQUAL note. */
962 /* Skip this insn, not checking REG_LIBCALL notes. */
964 /* Skip the consecutive insns, if there are any. */
966 /* Back up to the last insn of the consecutive group. */
969 /* We must now reset m->move_insn, m->is_equiv, and
970 possibly m->set_src to correspond to the effects of
971 all the insns. */
975 else
976 {
980 else
983 }
984 m->is_equiv
986 }
987 }
988 /* If this register is always set within a STRICT_LOW_PART
989 or set to zero, then its high bytes are constant.
990 So clear them outside the loop and within the loop
991 just load the low bytes.
992 We must check that the machine has an instruction to do so.
993 Also, if the value loaded into the register
994 depends on the same register, this cannot be done. */
1004 {
1007 {
1021 /* If the insn may not be executed on some cycles,
1022 we can't clear the whole reg; clear just high part.
1023 Not even if the reg is used only within this loop.
1024 Consider this:
1025 while (1)
1026 while (s != t) {
1027 if (foo ()) x = *s;
1028 use (x);
1029 }
1030 Clearing x before the inner loop could clobber a value
1031 being saved from the last time around the outer loop.
1032 However, if the reg is not used outside this loop
1033 and all uses of the register are in the same
1034 basic block as the store, there is no problem.
1036 If this insn was made by loop, we don't know its
1037 INSN_LUID and hence must make a conservative
1038 assumption. */
1041 || (labels_in_range_p
1045 else
1054 i++)
1056 /* Add M to the end of the chain MOVABLES. */
1058 }
1059 }
1060 }
1061 }
1062 /* Past a call insn, we get to insns which might not be executed
1063 because the call might exit. This matters for insns that trap.
1064 Constant and pure call insns always return, so they don't count. */
1067 /* Past a label or a jump, we get to insns for which we
1068 can't count on whether or how many times they will be
1069 executed during each iteration. Therefore, we can
1070 only move out sets of trivial variables
1071 (those not used after the loop). */
1072 /* Similar code appears twice in strength_reduce. */
1074 /* If we enter the loop in the middle, and scan around to the
1075 beginning, don't set maybe_never for that. This must be an
1076 unconditional jump, otherwise the code at the top of the
1077 loop might never be executed. Unconditional jumps are
1078 followed by a barrier then the loop_end. */
1084 {
1085 /* At the virtual top of a converted loop, insns are again known to
1086 be executed: logically, the loop begins here even though the exit
1087 code has been duplicated. */
1091 loop_depth++;
1093 loop_depth--;
1094 }
1095 }
1097 /* If one movable subsumes another, ignore that other. */
1101 /* For each movable insn, see if the reg that it loads
1102 leads when it dies right into another conditionally movable insn.
1103 If so, record that the second insn "forces" the first one,
1104 since the second can be moved only if the first is. */
1108 /* See if there are multiple movable insns that load the same value.
1109 If there are, make all but the first point at the first one
1110 through the `match' field, and add the priorities of them
1111 all together as the priority of the first. */
1115 /* Now consider each movable insn to decide whether it is worth moving.
1116 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1118 Generally this increases code size, so do not move moveables when
1119 optimizing for code size. */
1122 {
1125 /* Recalculate regs->array if move_movables has created new
1126 registers. */
1128 {
1134 ;
1139 }
1140 }
1142 /* Now candidates that still are negative are those not moved.
1143 Change regs->array[I].set_in_loop to indicate that those are not actually
1144 invariant. */
1149 /* Now that we've moved some things out of the loop, we might be able to
1150 hoist even more memory references. */
1153 /* Recalculate regs->array if load_mems has created new registers. */
1161 ;
1168 {
1170 /* Ensure our label doesn't go away. */
1181 }
1184 /* The movable information is required for strength reduction. */
1190 }
1191 \f
1192 /* Add elements to *OUTPUT to record all the pseudo-regs
1193 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1195 void
1199 {
1207 {
1225 }
1229 {
1233 {
1242 }
1243 }
1244 }
1245 \f
1246 /* Check what regs are referred to in the libcall block ending with INSN,
1247 aside from those mentioned in the equivalent value.
1248 If there are none, return 0.
1249 If there are one or more, return an EXPR_LIST containing all of them. */
1251 rtx
1254 {
1259 /* First, find all the regs used in the libcall block
1260 that are not mentioned as inputs to the result. */
1263 {
1268 }
1271 }
1272 \f
1273 /* Return 1 if all uses of REG
1274 are between INSN and the end of the basic block. */
1276 static int
1279 {
1281 rtx p;
1286 /* Search this basic block for the already recorded last use of the reg. */
1288 {
1290 {
1296 /* Ordinary insn: if this is the last use, we win. */
1302 /* Jump insn: if this is the last use, we win. */
1305 /* Otherwise, it's the end of the basic block, so we lose. */
1310 /* It's the end of the basic block, so we lose. */
1315 }
1316 }
1318 /* The "last use" that was recorded can't be found after the first
1319 use. This can happen when the last use was deleted while
1320 processing an inner loop, this inner loop was then completely
1321 unrolled, and the outer loop is always exited after the inner loop,
1322 so that everything after the first use becomes a single basic block. */
1324 }
1325 \f
1326 /* Compute the benefit of eliminating the insns in the block whose
1327 last insn is LAST. This may be a group of insns used to compute a
1328 value directly or can contain a library call. */
1330 static int
1332 rtx last;
1333 {
1334 rtx insn;
1339 {
1342 routine. */
1346 benefit++;
1347 }
1350 }
1351 \f
1352 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1354 static rtx
1356 rtx insn;
1358 {
1360 {
1361 rtx temp;
1363 /* If first insn of libcall sequence, skip to end. */
1364 /* Do this at start of loop, since INSN is guaranteed to
1365 be an insn here. */
1370 do
1373 }
1376 }
1378 /* Ignore any movable whose insn falls within a libcall
1379 which is part of another movable.
1380 We make use of the fact that the movable for the libcall value
1381 was made later and so appears later on the chain. */
1383 static void
1386 {
1390 {
1391 /* Is this a movable for the value of a libcall? */
1394 {
1395 rtx insn;
1396 /* Check for earlier movables inside that range,
1397 and mark them invalid. We cannot use LUIDs here because
1398 insns created by loop.c for prior loops don't have LUIDs.
1399 Rather than reject all such insns from movables, we just
1400 explicitly check each insn in the libcall (since invariant
1401 libcalls aren't that common). */
1406 }
1407 }
1408 }
1410 /* For each movable insn, see if the reg that it loads
1411 leads when it dies right into another conditionally movable insn.
1412 If so, record that the second insn "forces" the first one,
1413 since the second can be moved only if the first is. */
1415 static void
1418 {
1422 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1424 {
1427 /* ??? Could this be a bug? What if CSE caused the
1428 register of M1 to be used after this insn?
1429 Since CSE does not update regno_last_uid,
1430 this insn M->insn might not be where it dies.
1431 But very likely this doesn't matter; what matters is
1432 that M's reg is computed from M1's reg. */
1437 /* If m->consec, m->set_src isn't valid. */
1441 /* Increase the priority of the moving the first insn
1442 since it permits the second to be moved as well. */
1444 {
1448 }
1449 }
1450 }
1451 \f
1452 /* Find invariant expressions that are equal and can be combined into
1453 one register. */
1455 static void
1459 {
1464 /* Regs that are set more than once are not allowed to match
1465 or be matched. I'm no longer sure why not. */
1466 /* Only pseudo registers are allowed to match or be matched,
1467 since move_movables does not validate the change. */
1468 /* Perhaps testing m->consec_sets would be more appropriate here? */
1474 {
1481 /* We want later insns to match the first one. Don't make the first
1482 one match any later ones. So start this loop at m->next. */
1487 /* A reg used outside the loop mustn't be eliminated. */
1489 /* A reg used for zero-extending mustn't be eliminated. */
1492 ||
1493 (
1494 /* Can combine regs with different modes loaded from the
1495 same constant only if the modes are the same or
1496 if both are integer modes with M wider or the same
1497 width as M1. The check for integer is redundant, but
1498 safe, since the only case of differing destination
1499 modes with equal sources is when both sources are
1500 VOIDmode, i.e., CONST_INT. */
1506 /* See if the source of M1 says it matches M. */
1513 {
1519 }
1520 }
1522 /* Now combine the regs used for zero-extension.
1523 This can be done for those not marked `global'
1524 provided their lives don't overlap. */
1528 {
1531 /* Combine all the registers for extension from mode MODE.
1532 Don't combine any that are used outside this loop. */
1536 {
1543 {
1544 /* First one: don't check for overlap, just record it. */
1547 }
1549 /* Make sure they extend to the same mode.
1550 (Almost always true.) */
1554 /* We already have one: check for overlap with those
1555 already combined together. */
1562 /* No overlap: we can combine this with the others. */
1568 overlap:
1569 ;
1570 }
1571 }
1573 /* Clean up. */
1575 }
1577 /* Returns the number of movable instructions in LOOP that were not
1578 moved outside the loop. */
1580 static int
1583 {
1592 }
1594 \f
1595 /* Return 1 if regs X and Y will become the same if moved. */
1597 static int
1601 {
1618 }
1620 /* Return 1 if X and Y are identical-looking rtx's.
1621 This is the Lisp function EQUAL for rtx arguments.
1623 If two registers are matching movables or a movable register and an
1624 equivalent constant, consider them equal. */
1626 static int
1631 {
1645 /* If we have a register and a constant, they may sometimes be
1646 equal. */
1649 {
1654 }
1657 {
1662 }
1664 /* Otherwise, rtx's of different codes cannot be equal. */
1668 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1669 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1674 /* These three types of rtx's can be compared nonrecursively. */
1683 /* Compare the elements. If any pair of corresponding elements
1684 fail to match, return 0 for the whole things. */
1688 {
1690 {
1702 /* Two vectors must have the same length. */
1706 /* And the corresponding elements must match. */
1725 /* These are just backpointers, so they don't matter. */
1731 /* It is believed that rtx's at this level will never
1732 contain anything but integers and other rtx's,
1733 except for within LABEL_REFs and SYMBOL_REFs. */
1736 }
1737 }
1739 }
1740 \f
1741 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1742 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1743 references is incremented once for each added note. */
1745 static void
1747 rtx x;
1748 rtx insns;
1749 {
1753 rtx insn;
1756 {
1757 /* This code used to ignore labels that referred to dispatch tables to
1758 avoid flow generating (slighly) worse code.
1760 We no longer ignore such label references (see LABEL_REF handling in
1761 mark_jump_label for additional information). */
1764 {
1769 }
1770 }
1774 {
1780 }
1781 }
1782 \f
1783 /* Scan MOVABLES, and move the insns that deserve to be moved.
1784 If two matching movables are combined, replace one reg with the
1785 other throughout. */
1787 static void
1793 {
1798 rtx p;
1801 /* Map of pseudo-register replacements to handle combining
1802 when we move several insns that load the same value
1803 into different pseudo-registers. */
1808 {
1809 /* Describe this movable insn. */
1812 {
1833 }
1835 /* Ignore the insn if it's already done (it matched something else).
1836 Otherwise, see if it is now safe to move. */
1848 {
1850 rtx p;
1853 /* We have an insn that is safe to move.
1854 Compute its desirability. */
1865 /* An insn MUST be moved if we already moved something else
1866 which is safe only if this one is moved too: that is,
1867 if already_moved[REGNO] is nonzero. */
1869 /* An insn is desirable to move if the new lifetime of the
1870 register is no more than THRESHOLD times the old lifetime.
1871 If it's not desirable, it means the loop is so big
1872 that moving won't speed things up much,
1873 and it is liable to make register usage worse. */
1875 /* It is also desirable to move if it can be moved at no
1876 extra cost because something else was already moved. */
1879 || flag_move_all_movables
1884 {
1889 /* Now move the insns that set the reg. */
1892 {
1895 /* Find the end of this chain of matching regs.
1896 Thus, we load each reg in the chain from that one reg.
1897 And that reg is loaded with 0 directly,
1898 since it has ->match == 0. */
1904 /* Mark the moved, invariant reg as being allowed to
1905 share a hard reg with the other matching invariant. */
1909 regs_may_share
1912 regs_may_share));
1920 }
1921 /* If we are to re-generate the item being moved with a
1922 new move insn, first delete what we have and then emit
1923 the move insn before the loop. */
1925 {
1929 {
1930 /* If this is the first insn of a library call sequence,
1931 something is very wrong. */
1936 /* If this is the last insn of a libcall sequence, then
1937 delete every insn in the sequence except the last.
1938 The last insn is handled in the normal manner. */
1941 {
1945 }
1950 /* simplify_giv_expr expects that it can walk the insns
1951 at m->insn forwards and see this old sequence we are
1952 tossing here. delete_insn does preserve the next
1953 pointers, but when we skip over a NOTE we must fix
1954 it up. Otherwise that code walks into the non-deleted
1955 insn stream. */
1958 }
1976 /* The more regs we move, the less we like moving them. */
1978 }
1979 else
1980 {
1982 {
1985 /* If first insn of libcall sequence, skip to end. */
1986 /* Do this at start of loop, since p is guaranteed to
1987 be an insn here. */
1992 /* If last insn of libcall sequence, move all
1993 insns except the last before the loop. The last
1994 insn is handled in the normal manner. */
1997 {
2005 {
2006 rtx body;
2007 rtx n;
2008 rtx next;
2015 /* Find the next insn after TEMP,
2016 not counting USE or NOTE insns. */
2024 /* If that is the call, this may be the insn
2025 that loads the function address.
2027 Extract the function address from the insn
2028 that loads it into a register.
2029 If this insn was cse'd, we get incorrect code.
2031 So emit a new move insn that copies the
2032 function address into the register that the
2033 call insn will use. flow.c will delete any
2034 redundant stores that we have created. */
2039 NULL_RTX)))
2040 {
2046 }
2047 /* We have the call insn.
2048 If it uses the register we suspect it might,
2049 load it with the correct address directly. */
2054 gen_move_insn
2058 {
2060 /* Because the USAGE information potentially
2061 contains objects other than hard registers
2062 we need to copy it. */
2066 }
2067 else
2076 }
2079 }
2081 {
2082 /* P sets REG to zero; but we should clear only
2083 the bits that are not covered by the mode
2084 m->savemode. */
2086 rtx sequence;
2087 rtx tem;
2090 tem = expand_simple_binop
2103 }
2105 {
2107 /* Because the USAGE information potentially
2108 contains objects other than hard registers
2109 we need to copy it. */
2113 }
2115 {
2116 rtx seq;
2117 /* The SET_SRC might not be invariant, so we must
2118 use the REG_EQUAL note. */
2130 }
2131 else
2135 {
2139 /* If there is a REG_EQUAL note present whose value
2140 is not loop invariant, then delete it, since it
2141 may cause problems with later optimization passes.
2142 It is possible for cse to create such notes
2143 like this as a result of record_jump_cond. */
2148 }
2157 /* If library call, now fix the REG_NOTES that contain
2158 insn pointers, namely REG_LIBCALL on FIRST
2159 and REG_RETVAL on I1. */
2161 {
2165 }
2171 /* simplify_giv_expr expects that it can walk the insns
2172 at m->insn forwards and see this old sequence we are
2173 tossing here. delete_insn does preserve the next
2174 pointers, but when we skip over a NOTE we must fix
2175 it up. Otherwise that code walks into the non-deleted
2176 insn stream. */
2179 }
2181 /* The more regs we move, the less we like moving them. */
2183 }
2185 /* Any other movable that loads the same register
2186 MUST be moved. */
2189 /* This reg has been moved out of one loop. */
2192 /* The reg set here is now invariant. */
2194 {
2198 }
2202 /* Change the length-of-life info for the register
2203 to say it lives at least the full length of this loop.
2204 This will help guide optimizations in outer loops. */
2207 /* This is the old insn before all the moved insns.
2208 We can't use the moved insn because it is out of range
2209 in uid_luid. Only the old insns have luids. */
2214 /* Combine with this moved insn any other matching movables. */
2219 {
2220 rtx temp;
2222 /* Schedule the reg loaded by M1
2223 for replacement so that shares the reg of M.
2224 If the modes differ (only possible in restricted
2225 circumstances, make a SUBREG.
2227 Note this assumes that the target dependent files
2228 treat REG and SUBREG equally, including within
2229 GO_IF_LEGITIMATE_ADDRESS and in all the
2230 predicates since we never verify that replacing the
2231 original register with a SUBREG results in a
2232 recognizable insn. */
2235 else
2240 /* Get rid of the matching insn
2241 and prevent further processing of it. */
2244 /* if library call, delete all insns. */
2246 NULL_RTX)))
2248 else
2251 /* Any other movable that loads the same register
2252 MUST be moved. */
2255 /* The reg merged here is now invariant,
2256 if the reg it matches is invariant. */
2258 {
2262 i++)
2264 }
2265 }
2266 }
2269 }
2275 }
2280 /* Go through all the instructions in the loop, making
2281 all the register substitutions scheduled in REG_MAP. */
2285 {
2289 }
2291 /* Clean up. */
2294 }
2297 static void
2301 {
2304 else
2307 }
2310 static void
2313 {
2318 {
2321 }
2322 }
2323 \f
2324 #if 0
2325 /* Scan X and replace the address of any MEM in it with ADDR.
2326 REG is the address that MEM should have before the replacement. */
2328 static void
2331 {
2340 {
2352 /* Short cut for very common case. */
2357 /* Short cut for very common case. */
2362 /* If this MEM uses a reg other than the one we expected,
2363 something is wrong. */
2371 }
2375 {
2379 {
2383 }
2384 }
2385 }
2386 #endif
2387 \f
2388 /* Return the number of memory refs to addresses that vary
2389 in the rtx X. */
2391 static int
2394 rtx x;
2395 {
2406 {
2423 }
2428 {
2432 {
2436 }
2437 }
2439 }
2440 \f
2441 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2442 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2443 `unknown_address_altered', `unknown_constant_address_altered', and
2444 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2445 list `store_mems' in LOOP. */
2447 static void
2450 {
2452 rtx insn;
2456 /* The label after END. Jumping here is just like falling off the
2457 end of the loop. We use next_nonnote_insn instead of next_label
2458 as a hedge against the (pathological) case where some actual insn
2459 might end up between the two. */
2482 {
2484 {
2487 }
2488 }
2492 {
2494 {
2497 {
2499 /* Count number of loops contained in this one. */
2501 }
2508 {
2511 }
2521 {
2525 {
2530 {
2533 }
2534 else
2535 {
2538 }
2540 do
2541 {
2543 {
2545 {
2546 /* Something tricky. */
2549 }
2552 {
2553 /* A jump outside the current loop. */
2556 }
2557 }
2561 }
2563 }
2564 else
2565 {
2566 /* A return, or something tricky. */
2568 }
2569 }
2570 /* FALLTHRU */
2591 }
2592 }
2594 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2596 anywhere. */
2598 /* We don't want loads for MEMs moved to a location before the
2599 one at which their stack memory becomes allocated. (Note
2600 that this is not a problem for malloc, etc., since those
2601 require actual function calls. */
2602 && ! current_function_calls_alloca
2603 /* There are ways to leave the loop other than falling off the
2604 end. */
2610 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2611 that loop_invariant_p and load_mems can use true_dependence
2612 to determine what is really clobbered. */
2614 {
2617 loop_info->store_mems
2619 }
2621 {
2625 loop_info->store_mems
2627 }
2628 }
2629 \f
2630 /* Invalidate all loops containing LABEL. */
2632 static void
2634 rtx label;
2635 {
2639 }
2641 /* Scan the function looking for loops. Record the start and end of each loop.
2642 Also mark as invalid loops any loops that contain a setjmp or are branched
2643 to from outside the loop. */
2645 static void
2647 rtx f;
2649 {
2650 rtx insn;
2651 rtx label;
2661 /* If there are jumps to undefined labels,
2662 treat them as jumps out of any/all loops.
2663 This also avoids writing past end of tables when there are no loops. */
2666 /* Find boundaries of loops, mark which loops are contained within
2667 loops, and invalidate loops that have setjmp. */
2672 {
2675 {
2679 num_loops++;
2703 }
2707 {
2708 /* In this case, we must invalidate our current loop and any
2709 enclosing loop. */
2711 {
2717 }
2718 }
2720 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2721 enclosing loop, but this doesn't matter. */
2723 }
2725 /* Any loop containing a label used in an initializer must be invalidated,
2726 because it can be jumped into from anywhere. */
2730 /* Any loop containing a label used for an exception handler must be
2731 invalidated, because it can be jumped into from anywhere. */
2734 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2735 loop that it is not contained within, that loop is marked invalid.
2736 If any INSN or CALL_INSN uses a label's address, then the loop containing
2737 that label is marked invalid, because it could be jumped into from
2738 anywhere.
2740 Also look for blocks of code ending in an unconditional branch that
2741 exits the loop. If such a block is surrounded by a conditional
2742 branch around the block, move the block elsewhere (see below) and
2743 invert the jump to point to the code block. This may eliminate a
2744 label in our loop and will simplify processing by both us and a
2745 possible second cse pass. */
2749 {
2753 {
2757 }
2764 /* See if this is an unconditional branch outside the loop. */
2772 {
2773 rtx p;
2779 /* Go backwards until we reach the start of the loop, a label,
2780 or a JUMP_INSN. */
2787 ;
2789 /* Check for the case where we have a jump to an inner nested
2790 loop, and do not perform the optimization in that case. */
2793 {
2796 {
2801 }
2802 }
2804 /* Make sure that the target of P is within the current loop. */
2810 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2811 we have a block of code to try to move.
2813 We look backward and then forward from the target of INSN
2814 to find a BARRIER at the same loop depth as the target.
2815 If we find such a BARRIER, we make a new label for the start
2816 of the block, invert the jump in P and point it to that label,
2817 and move the block of code to the spot we found. */
2822 /* Just ignore jumps to labels that were never emitted.
2823 These always indicate compilation errors. */
2827 /* If it's not safe to move the sequence, then we
2828 mustn't try. */
2831 {
2832 rtx target
2836 rtx tmp;
2838 /* Search for possible garbage past the conditional jumps
2839 and look for the last barrier. */
2847 /* Don't move things inside a tablejump. */
2860 /* Don't move things inside a tablejump. */
2871 {
2875 /* Ensure our label doesn't go away. */
2878 /* Verify that uid_loop is large enough and that
2879 we can invert P. */
2881 {
2884 /* If no suitable BARRIER was found, create a suitable
2885 one before TARGET. Since TARGET is a fall through
2886 path, we'll need to insert an jump around our block
2887 and add a BARRIER before TARGET.
2889 This creates an extra unconditional jump outside
2890 the loop. However, the benefits of removing rarely
2891 executed instructions from inside the loop usually
2892 outweighs the cost of the extra unconditional jump
2893 outside the loop. */
2895 {
2896 rtx temp;
2903 }
2905 /* Include the BARRIER after INSN and copy the
2906 block after LOC. */
2911 /* All those insns are now in TARGET_LOOP. */
2917 /* The label jumped to by INSN is no longer a loop
2918 exit. Unless INSN does not have a label (e.g.,
2919 it is a RETURN insn), search loop->exit_labels
2920 to find its label_ref, and remove it. Also turn
2921 off LABEL_OUTSIDE_LOOP_P bit. */
2923 {
2925 r;
2928 {
2932 else
2935 }
2941 /* If we didn't find it, then something is
2942 wrong. */
2945 }
2947 /* P is now a jump outside the loop, so it must be put
2948 in loop->exit_labels, and marked as such.
2949 The easiest way to do this is to just call
2950 mark_loop_jump again for P. */
2953 /* If INSN now jumps to the insn after it,
2954 delete INSN. */
2959 }
2961 /* Continue the loop after where the conditional
2962 branch used to jump, since the only branch insn
2963 in the block (if it still remains) is an inter-loop
2964 branch and hence needs no processing. */
2970 /* This loop will be continued with NEXT_INSN (insn). */
2972 }
2973 }
2974 }
2975 }
2976 }
2978 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2979 loops it is contained in, mark the target loop invalid.
2981 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2983 static void
2985 rtx x;
2987 {
2993 {
3005 /* There could be a label reference in here. */
3017 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3029 /* Link together all labels that branch outside the loop. This
3030 is used by final_[bg]iv_value and the loop unrolling code. Also
3031 mark this LABEL_REF so we know that this branch should predict
3032 false. */
3034 /* A check to make sure the label is not in an inner nested loop,
3035 since this does not count as a loop exit. */
3037 {
3042 }
3043 else
3047 {
3056 }
3058 /* If this is inside a loop, but not in the current loop or one enclosed
3059 by it, it invalidates at least one loop. */
3064 /* We must invalidate every nested loop containing the target of this
3065 label, except those that also contain the jump insn. */
3068 {
3069 /* Stop when we reach a loop that also contains the jump insn. */
3074 /* If we get here, we know we need to invalidate a loop. */
3081 }
3085 /* If this is not setting pc, ignore. */
3107 /* Strictly speaking this is not a jump into the loop, only a possible
3108 jump out of the loop. However, we have no way to link the destination
3109 of this jump onto the list of exit labels. To be safe we mark this
3110 loop and any containing loops as invalid. */
3112 {
3114 {
3120 }
3121 }
3123 }
3124 }
3125 \f
3126 /* Return nonzero if there is a label in the range from
3127 insn INSN to and including the insn whose luid is END
3128 INSN must have an assigned luid (i.e., it must not have
3129 been previously created by loop.c). */
3131 static int
3133 rtx insn;
3135 {
3137 {
3141 }
3144 }
3146 /* Record that a memory reference X is being set. */
3148 static void
3150 rtx x;
3151 rtx y ATTRIBUTE_UNUSED;
3153 {
3159 /* Count number of memory writes.
3160 This affects heuristics in strength_reduce. */
3163 /* BLKmode MEM means all memory is clobbered. */
3165 {
3168 else
3172 }
3176 }
3178 /* X is a value modified by an INSN that references a biv inside a loop
3179 exit test (ie, X is somehow related to the value of the biv). If X
3180 is a pseudo that is used more than once, then the biv is (effectively)
3181 used more than once. DATA is a pointer to a loop_regs structure. */
3183 static void
3185 rtx x;
3186 rtx y ATTRIBUTE_UNUSED;
3188 {
3203 /* If we do not have usage information, or if we know the register
3204 is used more than once, note that fact for check_dbra_loop. */
3209 }
3210 \f
3211 /* Return nonzero if the rtx X is invariant over the current loop.
3213 The value is 2 if we refer to something only conditionally invariant.
3215 A memory ref is invariant if it is not volatile and does not conflict
3216 with anything stored in `loop_info->store_mems'. */
3218 int
3221 rtx x;
3222 {
3229 rtx mem_list_entry;
3235 {
3243 /* A LABEL_REF is normally invariant, however, if we are unrolling
3244 loops, and this label is inside the loop, then it isn't invariant.
3245 This is because each unrolled copy of the loop body will have
3246 a copy of this label. If this was invariant, then an insn loading
3247 the address of this label into a register might get moved outside
3248 the loop, and then each loop body would end up using the same label.
3250 We don't know the loop bounds here though, so just fail for all
3251 labels. */
3254 else
3263 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3264 since the reg might be set by initialization within the loop. */
3281 /* Volatile memory references must be rejected. Do this before
3282 checking for read-only items, so that volatile read-only items
3283 will be rejected also. */
3287 /* See if there is any dependence between a store and this load. */
3290 {
3296 }
3298 /* It's not invalidated by a store in memory
3299 but we must still verify the address is invariant. */
3303 /* Don't mess with insns declared volatile. */
3310 }
3314 {
3316 {
3322 }
3324 {
3327 {
3333 }
3335 }
3336 }
3339 }
3340 \f
3341 /* Return nonzero if all the insns in the loop that set REG
3342 are INSN and the immediately following insns,
3343 and if each of those insns sets REG in an invariant way
3344 (not counting uses of REG in them).
3346 The value is 2 if some of these insns are only conditionally invariant.
3348 We assume that INSN itself is the first set of REG
3349 and that its source is invariant. */
3351 static int
3356 {
3360 rtx temp;
3361 /* Number of sets we have to insist on finding after INSN. */
3367 /* If N_SETS hit the limit, we can't rely on its value. */
3374 {
3376 rtx set;
3381 /* If library call, skip to end of it. */
3390 {
3395 {
3396 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3397 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3398 notes are OK. */
3404 }
3405 }
3407 count--;
3409 {
3412 }
3413 }
3416 /* If loop_invariant_p ever returned 2, we return 2. */
3418 }
3420 #if 0
3421 /* I don't think this condition is sufficient to allow INSN
3422 to be moved, so we no longer test it. */
3424 /* Return 1 if all insns in the basic block of INSN and following INSN
3425 that set REG are invariant according to TABLE. */
3427 static int
3431 {
3436 {
3445 {
3448 }
3449 }
3450 }
3452 \f
3453 /* Look at all uses (not sets) of registers in X. For each, if it is
3454 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3455 a different insn, set USAGE[REGNO] to const0_rtx. */
3457 static void
3460 rtx insn;
3461 rtx x;
3462 {
3474 {
3475 /* Don't count SET_DEST if it is a REG; otherwise count things
3476 in SET_DEST because if a register is partially modified, it won't
3477 show up as a potential movable so we don't care how USAGE is set
3478 for it. */
3482 }
3483 else
3485 {
3491 }
3492 }
3493 \f
3494 /* Count and record any set in X which is contained in INSN. Update
3495 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3496 in X. */
3498 static void
3503 {
3505 /* Don't move a reg that has an explicit clobber.
3506 It's not worth the pain to try to do it correctly. */
3510 {
3518 {
3522 {
3523 /* If this is the first setting of this reg
3524 in current basic block, and it was set before,
3525 it must be set in two basic blocks, so it cannot
3526 be moved out of the loop. */
3530 /* If this is not first setting in current basic block,
3531 see if reg was used in between previous one and this.
3532 If so, neither one can be moved. */
3539 }
3540 }
3541 }
3542 }
3543 \f
3544 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3545 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3546 contained in insn INSN is used by any insn that precedes INSN in
3547 cyclic order starting from the loop entry point.
3549 We don't want to use INSN_LUID here because if we restrict INSN to those
3550 that have a valid INSN_LUID, it means we cannot move an invariant out
3551 from an inner loop past two loops. */
3553 static int
3557 {
3559 rtx p;
3561 /* Scan forward checking for register usage. If we hit INSN, we
3562 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3564 {
3570 }
3573 }
3574 \f
3576 /* Information we collect about arrays that we might want to prefetch. */
3577 struct prefetch_info
3578 {
3582 index. */
3583 HOST_WIDE_INT index;
3585 iteration. */
3587 prefetch area in one iteration. */
3589 This is set only for loops with known
3590 iteration counts and is 0xffffffff
3591 otherwise. */
3595 };
3597 /* Data used by check_store function. */
3598 struct check_store_data
3599 {
3600 rtx mem_address;
3602 };
3608 /* Set mem_write when mem_address is found. Used as callback to
3609 note_stores. */
3610 static void
3614 {
3619 }
3620 \f
3621 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3622 important to get some addresses combined. Later more sophisticated
3623 transformations can be added when necesary.
3625 ??? Same trick with swapping operand is done at several other places.
3626 It can be nice to develop some common way to handle this. */
3628 static int
3631 {
3645 {
3650 }
3651 /* Compare the elements. If any pair of corresponding elements fails to
3652 match, return 0 for the whole thing. */
3656 {
3658 {
3670 /* Two vectors must have the same length. */
3674 /* And the corresponding elements must match. */
3692 /* These are just backpointers, so they don't matter. */
3698 /* It is believed that rtx's at this level will never
3699 contain anything but integers and other rtx's,
3700 except for within LABEL_REFs and SYMBOL_REFs. */
3703 }
3704 }
3706 }
3707 \f
3708 /* Remove constant addition value from the expression X (when present)
3709 and return it. */
3711 static HOST_WIDE_INT
3714 {
3718 /* Avoid clobbering a shared CONST expression. */
3720 {
3724 {
3727 }
3729 }
3732 {
3735 }
3737 /* For plus expression recurse on ourself. */
3739 {
3743 /* In case our parameter was constant, remove extra zero from the
3744 expression. */
3749 }
3752 }
3754 /* Attempt to identify accesses to arrays that are most likely to cause cache
3755 misses, and emit prefetch instructions a few prefetch blocks forward.
3757 To detect the arrays we use the GIV information that was collected by the
3758 strength reduction pass.
3760 The prefetch instructions are generated after the GIV information is done
3761 and before the strength reduction process. The new GIVs are injected into
3762 the strength reduction tables, so the prefetch addresses are optimized as
3763 well.
3765 GIVs are split into base address, stride, and constant addition values.
3766 GIVs with the same address, stride and close addition values are combined
3767 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3768 for write instructions can be used for the block we write to, on machines
3769 that support write prefetches.
3771 Several heuristics are used to determine when to prefetch. They are
3772 controlled by defined symbols that can be overridden for each target. */
3774 static void
3777 {
3793 /* Consider only loops w/o calls. When a call is done, the loop is probably
3794 slow enough to read the memory. */
3796 {
3801 }
3803 /* Don't prefetch in loops known to have few iterations. */
3807 {
3812 }
3814 /* Search all induction variables and pick those interesting for the prefetch
3815 machinery. */
3817 {
3823 /* Expect all BIVs to be executed in each iteration. This makes our
3824 analysis more conservative. */
3826 {
3827 /* Discard non-constant additions that we can't handle well yet, and
3828 BIVs that are executed multiple times; such BIVs ought to be
3829 handled in the nested loop. We accept not_every_iteration BIVs,
3830 since these only result in larger strides and make our
3831 heuristics more conservative. */
3833 {
3835 {
3841 }
3843 }
3846 {
3848 {
3854 }
3856 }
3860 }
3866 {
3867 rtx address;
3868 rtx temp;
3877 /* See whether an induction variable is interesting to us and if
3878 not, report the reason. */
3882 /* We are interested only in constant stride memory references
3883 in order to be able to compute density easily. */
3887 else
3888 {
3891 {
3894 }
3896 /* On some targets, reversed order prefetches are not
3897 worthwhile. */
3901 /* Prefetch of accesses with an extreme stride might not be
3902 worthwhile, either. */
3907 /* Ignore GIVs with varying add values; we can't predict the
3908 value for the next iteration. */
3912 /* Ignore GIVs in the nested loops; they ought to have been
3913 handled already. */
3916 }
3919 {
3925 }
3927 /* Determine the pointer to the basic array we are examining. It is
3928 the sum of the BIV's initial value and the GIV's add_val. */
3938 /* When the GIV is not always executed, we might be better off by
3939 not dirtying the cache pages. */
3942 else
3943 {
3948 }
3950 /* Attempt to find another prefetch to the same array and see if we
3951 can merge this one. */
3955 {
3956 /* In case both access same array (same location
3957 just with small difference in constant indexes), merge
3958 the prefetches. Just do the later and the earlier will
3959 get prefetched from previous iteration.
3960 The artificial threshold should not be too small,
3961 but also not bigger than small portion of memory usually
3962 traversed by single loop. */
3965 {
3974 }
3978 {
3983 }
3984 }
3986 /* Merging failed. */
3988 {
3996 num_prefetches++;
3998 {
4003 }
4004 }
4005 }
4006 }
4009 {
4012 /* Attempt to calculate the total number of bytes fetched by all
4013 iterations of the loop. Avoid overflow. */
4018 else
4023 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4028 {
4033 }
4034 else
4035 {
4041 }
4042 else
4045 /* Find how many prefetch instructions we'll use within the loop. */
4047 {
4053 }
4054 }
4056 /* Determine how many iterations ahead to prefetch within the loop, based
4057 on how many prefetches we currently expect to do within the loop. */
4059 {
4061 {
4067 }
4068 }
4069 /* We'll also use AHEAD to determine how many prefetch instructions to
4070 emit before a loop, so don't leave it zero. */
4075 {
4076 /* Update if we've decided not to prefetch anything within the loop. */
4080 /* Find how many prefetch instructions we'll use before the loop. */
4082 {
4090 }
4093 {
4115 }
4116 }
4119 {
4120 /* Record that this loop uses prefetch instructions. */
4124 {
4129 }
4130 }
4133 {
4137 {
4139 rtx insn;
4143 rtx seq;
4145 /* We can save some effort by offsetting the address on
4146 architectures with offsettable memory references. */
4149 else
4150 {
4156 }
4159 /* Make sure the address operand is valid for prefetch. */
4169 /* Check all insns emitted and record the new GIV
4170 information. */
4173 {
4178 }
4179 }
4182 {
4183 /* Emit insns before the loop to fetch the first cache lines or,
4184 if we're not prefetching within the loop, everything we expect
4185 to need. */
4187 {
4195 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4196 non-constant INIT_VAL to have the same mode as REG, which
4197 in this case we know to be Pmode. */
4205 loop_start);
4206 }
4207 }
4208 }
4211 }
4212 \f
4213 /* A "basic induction variable" or biv is a pseudo reg that is set
4214 (within this loop) only by incrementing or decrementing it. */
4215 /* A "general induction variable" or giv is a pseudo reg whose
4216 value is a linear function of a biv. */
4218 /* Bivs are recognized by `basic_induction_var';
4219 Givs by `general_induction_var'. */
4221 /* Communication with routines called via `note_stores'. */
4225 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4229 /* ??? Unfinished optimizations, and possible future optimizations,
4230 for the strength reduction code. */
4232 /* ??? The interaction of biv elimination, and recognition of 'constant'
4233 bivs, may cause problems. */
4235 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4236 performance problems.
4238 Perhaps don't eliminate things that can be combined with an addressing
4239 mode. Find all givs that have the same biv, mult_val, and add_val;
4240 then for each giv, check to see if its only use dies in a following
4241 memory address. If so, generate a new memory address and check to see
4242 if it is valid. If it is valid, then store the modified memory address,
4243 otherwise, mark the giv as not done so that it will get its own iv. */
4245 /* ??? Could try to optimize branches when it is known that a biv is always
4246 positive. */
4248 /* ??? When replace a biv in a compare insn, we should replace with closest
4249 giv so that an optimized branch can still be recognized by the combiner,
4250 e.g. the VAX acb insn. */
4252 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4253 was rerun in loop_optimize whenever a register was added or moved.
4254 Also, some of the optimizations could be a little less conservative. */
4255 \f
4256 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4257 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4258 callback.
4260 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4261 least once for every loop iteration except for the last one.
4263 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4264 loop iteration.
4265 */
4266 void
4269 loop_insn_callback fncall;
4270 {
4275 rtx p;
4277 /* If loop_scan_start points to the loop exit test, we have to be wary of
4278 subversive use of gotos inside expression statements. */
4282 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4286 {
4289 /* Past CODE_LABEL, we get to insns that may be executed multiple
4290 times. The only way we can be sure that they can't is if every
4291 jump insn between here and the end of the loop either
4292 returns, exits the loop, is a jump to a location that is still
4293 behind the label, or is a jump to the loop start. */
4296 {
4302 {
4307 {
4310 else
4314 }
4322 {
4325 }
4326 }
4327 }
4329 /* Past a jump, we get to insns for which we can't count
4330 on whether they will be executed during each iteration. */
4331 /* This code appears twice in strength_reduce. There is also similar
4332 code in scan_loop. */
4334 /* If we enter the loop in the middle, and scan around to the
4335 beginning, don't set not_every_iteration for that.
4336 This can be any kind of jump, since we want to know if insns
4337 will be executed if the loop is executed. */
4342 {
4345 /* If this is a jump outside the loop, then it also doesn't
4346 matter. Check to see if the target of this branch is on the
4347 loop->exits_labels list. */
4355 }
4358 {
4359 /* At the virtual top of a converted loop, insns are again known to
4360 be executed each iteration: logically, the loop begins here
4361 even though the exit code has been duplicated.
4363 Insns are also again known to be executed each iteration at
4364 the LOOP_CONT note. */
4370 loop_depth++;
4372 loop_depth--;
4373 }
4375 /* Note if we pass a loop latch. If we do, then we can not clear
4376 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4377 a loop since a jump before the last CODE_LABEL may have started
4378 a new loop iteration.
4380 Note that LOOP_TOP is only set for rotated loops and we need
4381 this check for all loops, so compare against the CODE_LABEL
4382 which immediately follows LOOP_START. */
4387 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4388 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4389 or not an insn is known to be executed each iteration of the
4390 loop, whether or not any iterations are known to occur.
4392 Therefore, if we have just passed a label and have no more labels
4393 between here and the test insn of the loop, and we have not passed
4394 a jump to the top of the loop, then we know these insns will be
4395 executed each iteration. */
4398 && !past_loop_latch
4403 }
4404 }
4405 \f
4406 static void
4409 {
4412 /* Temporary list pointers for traversing ivs->list. */
4419 /* Scan ivs->list to remove all regs that proved not to be bivs.
4420 Make a sanity check against regs->n_times_set. */
4422 {
4424 /* Above happens if register modified by subreg, etc. */
4425 /* Make sure it is not recognized as a basic induction var: */
4427 /* If never incremented, it is invariant that we decided not to
4428 move. So leave it alone. */
4430 {
4441 }
4442 else
4443 {
4448 }
4449 }
4450 }
4453 /* Determine how BIVS are initialised by looking through pre-header
4454 extended basic block. */
4455 static void
4458 {
4460 /* Temporary list pointers for traversing ivs->list. */
4463 rtx p;
4465 /* Find initial value for each biv by searching backwards from loop_start,
4466 halting at first label. Also record any test condition. */
4470 {
4471 rtx test;
4481 /* Record any test of a biv that branches around the loop if no store
4482 between it and the start of loop. We only care about tests with
4483 constants and registers and only certain of those. */
4493 {
4494 /* If an NE test, we have an initial value! */
4496 {
4500 }
4501 else
4503 }
4504 }
4505 }
4508 /* Look at the each biv and see if we can say anything better about its
4509 initial value from any initializing insns set up above. (This is done
4510 in two passes to avoid missing SETs in a PARALLEL.) */
4511 static void
4514 {
4516 /* Temporary list pointers for traversing ivs->list. */
4521 {
4522 rtx src;
4523 rtx note;
4528 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4529 is a constant, use the value of that. */
4535 else
4548 {
4552 {
4555 }
4556 }
4557 /* If we can't make it a giv,
4558 let biv keep initial value of "itself". */
4561 }
4562 }
4565 /* Search the loop for general induction variables. */
4567 static void
4570 {
4572 }
4575 /* For each giv for which we still don't know whether or not it is
4576 replaceable, check to see if it is replaceable because its final value
4577 can be calculated. */
4579 static void
4582 {
4587 {
4593 }
4594 }
4597 /* Return non-zero if it is possible to eliminate the biv BL provided
4598 all givs are reduced. This is possible if either the reg is not
4599 used outside the loop, or we can compute what its final value will
4600 be. */
4602 static int
4608 {
4609 /* For architectures with a decrement_and_branch_until_zero insn,
4610 don't do this if we put a REG_NONNEG note on the endtest for this
4611 biv. */
4613 #ifdef HAVE_decrement_and_branch_until_zero
4615 {
4620 }
4621 #endif
4623 /* Check that biv is used outside loop or if it has a final value.
4624 Compare against bl->init_insn rather than loop->start. We aren't
4625 concerned with any uses of the biv between init_insn and
4626 loop->start since these won't be affected by the value of the biv
4627 elsewhere in the function, so long as init_insn doesn't use the
4628 biv itself. */
4639 {
4647 }
4649 }
4652 /* Reduce each giv of BL that we have decided to reduce. */
4654 static void
4658 {
4662 {
4665 {
4668 /* If the code for derived givs immediately below has already
4669 allocated a new_reg, we must keep it. */
4673 #ifdef AUTO_INC_DEC
4674 /* If the target has auto-increment addressing modes, and
4675 this is an address giv, then try to put the increment
4676 immediately after its use, so that flow can create an
4677 auto-increment addressing mode. */
4680 /* We don't handle reversed biv's because bl->biv->insn
4681 does not have a valid INSN_LUID. */
4685 {
4686 /* If other giv's have been combined with this one, then
4687 this will work only if all uses of the other giv's occur
4688 before this giv's insn. This is difficult to check.
4690 We simplify this by looking for the common case where
4691 there is one DEST_REG giv, and this giv's insn is the
4692 last use of the dest_reg of that DEST_REG giv. If the
4693 increment occurs after the address giv, then we can
4694 perform the optimization. (Otherwise, the increment
4695 would have to go before other_giv, and we would not be
4696 able to combine it with the address giv to get an
4697 auto-inc address.) */
4699 {
4704 {
4707 else
4709 }
4716 }
4717 /* Check for case where increment is before the address
4718 giv. Do this test in "loop order". */
4727 else
4730 #ifdef HAVE_cc0
4731 {
4732 rtx prev;
4734 /* We can't put an insn immediately after one setting
4735 cc0, or immediately before one using cc0. */
4742 }
4743 #endif
4747 }
4748 #endif
4750 /* For each place where the biv is incremented, add an insn
4751 to increment the new, reduced reg for the giv. */
4753 {
4754 rtx insert_before;
4760 else
4768 /* A multiply is acceptable here
4769 since this is presumed to be seldom executed. */
4773 }
4775 /* Add code at loop start to initialize giv's reduced reg. */
4780 }
4781 }
4782 }
4785 /* Check for givs whose first use is their definition and whose
4786 last use is the definition of another giv. If so, it is likely
4787 dead and should not be used to derive another giv nor to
4788 eliminate a biv. */
4790 static void
4794 {
4798 {
4805 {
4811 }
4812 }
4813 }
4816 static void
4821 {
4825 {
4832 /* Update expression if this was combined, in case other giv was
4833 replaced. */
4838 /* See if this register is known to be a pointer to something. If
4839 so, see if we can find the alignment. First see if there is a
4840 destination register that is a pointer. If so, this shares the
4841 alignment too. Next see if we can deduce anything from the
4842 computational information. If not, and this is a DEST_ADDR
4843 giv, at least we know that it's a pointer, though we don't know
4844 the alignment. */
4852 {
4861 }
4865 {
4873 }
4878 /* Store reduced reg as the address in the memref where we found
4879 this giv. */
4882 {
4884 }
4885 else
4886 {
4888 rtx note;
4890 /* Not replaceable; emit an insn to set the original giv reg from
4891 the reduced giv, same as above. */
4896 /* The original insn may have a REG_EQUAL note. This note is
4897 now incorrect and may result in invalid substitutions later.
4898 The original insn is dead, but may be part of a libcall
4899 sequence, which doesn't seem worth the bother of handling. */
4903 }
4905 /* When a loop is reversed, givs which depend on the reversed
4906 biv, and which are live outside the loop, must be set to their
4907 correct final value. This insn is only needed if the giv is
4908 not replaceable. The correct final value is the same as the
4909 value that the giv starts the reversed loop with. */
4920 {
4925 }
4926 }
4927 }
4930 static int
4935 rtx test_reg;
4936 {
4945 /* Reduce benefit if not replaceable, since we will insert a
4946 move-insn to replace the insn that calculates this giv. Don't do
4947 this unless the giv is a user variable, since it will often be
4948 marked non-replaceable because of the duplication of the exit
4949 code outside the loop. In such a case, the copies we insert are
4950 dead and will be deleted. So they don't have a cost. Similar
4951 situations exist. */
4952 /* ??? The new final_[bg]iv_value code does a much better job of
4953 finding replaceable giv's, and hence this code may no longer be
4954 necessary. */
4959 /* Decrease the benefit to count the add-insns that we will insert
4960 to increment the reduced reg for the giv. ??? This can
4961 overestimate the run-time cost of the additional insns, e.g. if
4962 there are multiple basic blocks that increment the biv, but only
4963 one of these blocks is executed during each iteration. There is
4964 no good way to detect cases like this with the current structure
4965 of the loop optimizer. This code is more accurate for
4966 determining code size than run-time benefits. */
4969 /* Decide whether to strength-reduce this giv or to leave the code
4970 unchanged (recompute it from the biv each time it is used). This
4971 decision can be made independently for each giv. */
4973 #ifdef AUTO_INC_DEC
4974 /* Attempt to guess whether autoincrement will handle some of the
4975 new add insns; if so, increase BENEFIT (undo the subtraction of
4976 add_cost that was done above). */
4978 /* Increasing the benefit is risky, since this is only a guess.
4979 Avoid increasing register pressure in cases where there would
4980 be no other benefit from reducing this giv. */
4983 {
4998 }
4999 #endif
5002 }
5005 /* Free IV structures for LOOP. */
5007 static void
5010 {
5017 {
5023 {
5026 }
5028 {
5031 }
5035 }
5036 }
5039 /* Perform strength reduction and induction variable elimination.
5041 Pseudo registers created during this function will be beyond the
5042 last valid index in several tables including
5043 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5044 problem here, because the added registers cannot be givs outside of
5045 their loop, and hence will never be reconsidered. But scan_loop
5046 must check regnos to make sure they are in bounds. */
5048 static void
5052 {
5056 rtx p;
5057 /* Temporary list pointer for traversing ivs->list. */
5059 /* Ratio of extra register life span we can justify
5060 for saving an instruction. More if loop doesn't call subroutines
5061 since in that case saving an insn makes more difference
5062 and more registers are available. */
5063 /* ??? could set this to last value of threshold in move_movables */
5065 /* Map of pseudo-register replacements. */
5077 /* Find all BIVs in loop. */
5080 /* Exit if there are no bivs. */
5082 {
5083 /* Can still unroll the loop anyways, but indicate that there is no
5084 strength reduction info available. */
5090 }
5092 /* Determine how BIVS are initialised by looking through pre-header
5093 extended basic block. */
5096 /* Look at the each biv and see if we can say anything better about its
5097 initial value from any initializing insns set up above. */
5100 /* Search the loop for general induction variables. */
5103 /* Try to calculate and save the number of loop iterations. This is
5104 set to zero if the actual number can not be calculated. This must
5105 be called after all giv's have been identified, since otherwise it may
5106 fail if the iteration variable is a giv. */
5109 #ifdef HAVE_prefetch
5112 #endif
5114 /* Now for each giv for which we still don't know whether or not it is
5115 replaceable, check to see if it is replaceable because its final value
5116 can be calculated. This must be done after loop_iterations is called,
5117 so that final_giv_value will work correctly. */
5120 /* Try to prove that the loop counter variable (if any) is always
5121 nonnegative; if so, record that fact with a REG_NONNEG note
5122 so that "decrement and branch until zero" insn can be used. */
5125 /* Create reg_map to hold substitutions for replaceable giv regs.
5126 Some givs might have been made from biv increments, so look at
5127 ivs->reg_iv_type for a suitable size. */
5131 /* Examine each iv class for feasibility of strength reduction/induction
5132 variable elimination. */
5135 {
5139 /* Test whether it will be possible to eliminate this biv
5140 provided all givs are reduced. */
5143 /* This will be true at the end, if all givs which depend on this
5144 biv have been strength reduced.
5145 We can't (currently) eliminate the biv unless this is so. */
5148 /* Check each extension dependent giv in this class to see if its
5149 root biv is safe from wrapping in the interior mode. */
5152 /* Combine all giv's for this iv_class. */
5156 {
5164 /* If an insn is not to be strength reduced, then set its ignore
5165 flag, and clear bl->all_reduced. */
5167 /* A giv that depends on a reversed biv must be reduced if it is
5168 used after the loop exit, otherwise, it would have the wrong
5169 value after the loop exit. To make it simple, just reduce all
5170 of such giv's whether or not we know they are used after the loop
5171 exit. */
5176 {
5184 }
5185 else
5186 {
5187 /* Check that we can increment the reduced giv without a
5188 multiply insn. If not, reject it. */
5193 {
5201 }
5202 }
5203 }
5205 /* Check for givs whose first use is their definition and whose
5206 last use is the definition of another giv. If so, it is likely
5207 dead and should not be used to derive another giv nor to
5208 eliminate a biv. */
5211 /* Reduce each giv that we decided to reduce. */
5214 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5215 as not reduced.
5217 For each giv register that can be reduced now: if replaceable,
5218 substitute reduced reg wherever the old giv occurs;
5219 else add new move insn "giv_reg = reduced_reg". */
5222 /* All the givs based on the biv bl have been reduced if they
5223 merit it. */
5225 /* For each giv not marked as maybe dead that has been combined with a
5226 second giv, clear any "maybe dead" mark on that second giv.
5227 v->new_reg will either be or refer to the register of the giv it
5228 combined with.
5230 Doing this clearing avoids problems in biv elimination where
5231 a giv's new_reg is a complex value that can't be put in the
5232 insn but the giv combined with (with a reg as new_reg) is
5233 marked maybe_dead. Since the register will be used in either
5234 case, we'd prefer it be used from the simpler giv. */
5240 /* Try to eliminate the biv, if it is a candidate.
5241 This won't work if ! bl->all_reduced,
5242 since the givs we planned to use might not have been reduced.
5244 We have to be careful that we didn't initially think we could
5245 eliminate this biv because of a giv that we now think may be
5246 dead and shouldn't be used as a biv replacement.
5248 Also, there is the possibility that we may have a giv that looks
5249 like it can be used to eliminate a biv, but the resulting insn
5250 isn't valid. This can happen, for example, on the 88k, where a
5251 JUMP_INSN can compare a register only with zero. Attempts to
5252 replace it with a compare with a constant will fail.
5254 Note that in cases where this call fails, we may have replaced some
5255 of the occurrences of the biv with a giv, but no harm was done in
5256 doing so in the rare cases where it can occur. */
5260 {
5261 /* ?? If we created a new test to bypass the loop entirely,
5262 or otherwise drop straight in, based on this test, then
5263 we might want to rewrite it also. This way some later
5264 pass has more hope of removing the initialization of this
5265 biv entirely. */
5267 /* If final_value != 0, then the biv may be used after loop end
5268 and we must emit an insn to set it just in case.
5270 Reversed bivs already have an insn after the loop setting their
5271 value, so we don't need another one. We can't calculate the
5272 proper final value for such a biv here anyways. */
5281 }
5282 /* See above note wrt final_value. But since we couldn't eliminate
5283 the biv, we must set the value after the loop instead of before. */
5287 }
5289 /* Go through all the instructions in the loop, making all the
5290 register substitutions scheduled in REG_MAP. */
5295 {
5299 }
5302 {
5303 /* When we completely unroll a loop we will likely not need the increment
5304 of the loop BIV and we will not need the conditional branch at the
5305 end of the loop. */
5308 #ifdef HAVE_cc0
5309 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5310 need the comparison before the conditional branch at the end of the
5311 loop. */
5313 #endif
5315 /* We'll need one copy for each loop iteration. */
5318 /* A little slop to account for the ability to remove initialization
5319 code, better CSE, and other secondary benefits of completely
5320 unrolling some loops. */
5323 /* Clamp the value. */
5326 }
5328 /* Unroll loops from within strength reduction so that we can use the
5329 induction variable information that strength_reduce has already
5330 collected. Always unroll loops that would be as small or smaller
5331 unrolled than when rolled. */
5338 #ifdef HAVE_doloop_end
5343 /* In case number of iterations is known, drop branch prediction note
5344 in the branch. Do that only in second loop pass, as loop unrolling
5345 may change the number of iterations performed. */
5347 {
5348 unsigned HOST_WIDE_INT n
5353 }
5361 }
5362 \f
5363 /*Record all basic induction variables calculated in the insn. */
5364 static rtx
5367 rtx p;
5370 {
5372 rtx set;
5373 rtx dest_reg;
5374 rtx inc_val;
5375 rtx mult_val;
5381 {
5386 {
5391 {
5392 /* It is a possible basic induction variable.
5393 Create and initialize an induction structure for it. */
5401 }
5404 }
5405 }
5407 }
5408 \f
5409 /* Record all givs calculated in the insn.
5410 A register is a giv if: it is only set once, it is a function of a
5411 biv and a constant (or invariant), and it is not a biv. */
5412 static rtx
5415 rtx p;
5418 {
5421 rtx set;
5422 /* Look for a general induction variable in a register. */
5427 {
5428 rtx src_reg;
5429 rtx dest_reg;
5430 rtx add_val;
5431 rtx mult_val;
5432 rtx ext_val;
5435 rtx last_consec_insn;
5444 /* Equivalent expression is a giv. */
5449 /* Don't try to handle any regs made by loop optimization.
5450 We have nothing on them in regno_first_uid, etc. */
5452 /* Don't recognize a BASIC_INDUCT_VAR here. */
5454 /* This must be the only place where the register is set. */
5456 /* or all sets must be consecutive and make a giv. */
5461 {
5465 /* If this is a library call, increase benefit. */
5469 /* Skip the consecutive insns, if there are any. */
5477 }
5478 }
5480 #ifndef DONT_REDUCE_ADDR
5481 /* Look for givs which are memory addresses. */
5482 /* This resulted in worse code on a VAX 8600. I wonder if it
5483 still does. */
5486 maybe_multiple);
5487 #endif
5489 /* Update the status of whether giv can derive other givs. This can
5490 change when we pass a label or an insn that updates a biv. */
5495 }
5496 \f
5497 /* Return 1 if X is a valid source for an initial value (or as value being
5498 compared against in an initial test).
5500 X must be either a register or constant and must not be clobbered between
5501 the current insn and the start of the loop.
5503 INSN is the insn containing X. */
5505 static int
5507 rtx x;
5508 rtx insn;
5510 rtx loop_start;
5511 {
5515 /* Only consider pseudos we know about initialized in insns whose luids
5516 we know. */
5521 /* Don't use call-clobbered registers across a call which clobbers it. On
5522 some machines, don't use any hard registers at all. */
5524 && (SMALL_REGISTER_CLASSES
5528 /* Don't use registers that have been clobbered before the start of the
5529 loop. */
5534 }
5535 \f
5536 /* Scan X for memory refs and check each memory address
5537 as a possible giv. INSN is the insn whose pattern X comes from.
5538 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5539 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5540 more thanonce in each loop iteration. */
5542 static void
5545 rtx x;
5546 rtx insn;
5548 {
5558 {
5574 {
5575 rtx src_reg;
5576 rtx add_val;
5577 rtx mult_val;
5578 rtx ext_val;
5581 /* This code used to disable creating GIVs with mult_val == 1 and
5582 add_val == 0. However, this leads to lost optimizations when
5583 it comes time to combine a set of related DEST_ADDR GIVs, since
5584 this one would not be seen. */
5589 {
5590 /* Found one; record it. */
5599 }
5600 }
5605 }
5607 /* Recursively scan the subexpressions for other mem refs. */
5613 maybe_multiple);
5617 maybe_multiple);
5618 }
5619 \f
5620 /* Fill in the data about one biv update.
5621 V is the `struct induction' in which we record the biv. (It is
5622 allocated by the caller, with alloca.)
5623 INSN is the insn that sets it.
5624 DEST_REG is the biv's reg.
5626 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5627 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5628 being set to INC_VAL.
5630 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5631 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5632 can be executed more than once per iteration. If MAYBE_MULTIPLE
5633 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5634 executed exactly once per iteration. */
5636 static void
5641 rtx insn;
5642 rtx dest_reg;
5643 rtx inc_val;
5644 rtx mult_val;
5648 {
5664 /* Add this to the reg's iv_class, creating a class
5665 if this is the first incrementation of the reg. */
5669 {
5670 /* Create and initialize new iv_class. */
5680 /* Set initial value to the reg itself. */
5683 /* We haven't seen the initializing insn yet */
5693 /* Add this class to ivs->list. */
5697 /* Put it in the array of biv register classes. */
5699 }
5701 /* Update IV_CLASS entry for this biv. */
5710 }
5711 \f
5712 /* Fill in the data about one giv.
5713 V is the `struct induction' in which we record the giv. (It is
5714 allocated by the caller, with alloca.)
5715 INSN is the insn that sets it.
5716 BENEFIT estimates the savings from deleting this insn.
5717 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5718 into a register or is used as a memory address.
5720 SRC_REG is the biv reg which the giv is computed from.
5721 DEST_REG is the giv's reg (if the giv is stored in a reg).
5722 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5723 LOCATION points to the place where this giv's value appears in INSN. */
5725 static void
5730 rtx insn;
5731 rtx src_reg;
5732 rtx dest_reg;
5738 {
5743 rtx temp;
5745 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5746 undo the MULT canonicalization that we performed earlier. */
5776 /* The v->always_computable field is used in update_giv_derive, to
5777 determine whether a giv can be used to derive another giv. For a
5778 DEST_REG giv, INSN computes a new value for the giv, so its value
5779 isn't computable if INSN insn't executed every iteration.
5780 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5781 it does not compute a new value. Hence the value is always computable
5782 regardless of whether INSN is executed each iteration. */
5786 else
5792 {
5795 }
5797 {
5802 /* If the lifetime is zero, it means that this register is
5803 really a dead store. So mark this as a giv that can be
5804 ignored. This will not prevent the biv from being eliminated. */
5810 }
5812 /* Add the giv to the class of givs computed from one biv. */
5816 {
5819 /* Don't count DEST_ADDR. This is supposed to count the number of
5820 insns that calculate givs. */
5824 }
5825 else
5826 /* Fatal error, biv missing for this giv? */
5831 else
5832 {
5833 /* The giv can be replaced outright by the reduced register only if all
5834 of the following conditions are true:
5835 - the insn that sets the giv is always executed on any iteration
5836 on which the giv is used at all
5837 (there are two ways to deduce this:
5838 either the insn is executed on every iteration,
5839 or all uses follow that insn in the same basic block),
5840 - the giv is not used outside the loop
5841 - no assignments to the biv occur during the giv's lifetime. */
5844 /* Previous line always fails if INSN was moved by loop opt. */
5847 && (! not_every_iteration
5849 {
5850 /* Now check that there are no assignments to the biv within the
5851 giv's lifetime. This requires two separate checks. */
5853 /* Check each biv update, and fail if any are between the first
5854 and last use of the giv.
5856 If this loop contains an inner loop that was unrolled, then
5857 the insn modifying the biv may have been emitted by the loop
5858 unrolling code, and hence does not have a valid luid. Just
5859 mark the biv as not replaceable in this case. It is not very
5860 useful as a biv, because it is used in two different loops.
5861 It is very unlikely that we would be able to optimize the giv
5862 using this biv anyways. */
5866 {
5872 {
5876 }
5877 }
5879 /* If there are any backwards branches that go from after the
5880 biv update to before it, then this giv is not replaceable. */
5884 {
5888 }
5889 }
5890 else
5891 {
5892 /* May still be replaceable, we don't have enough info here to
5893 decide. */
5896 }
5897 }
5899 /* Record whether the add_val contains a const_int, for later use by
5900 combine_givs. */
5901 {
5906 ;
5910 {
5912 {
5917 else
5919 }
5922 }
5923 }
5927 }
5929 /* All this does is determine whether a giv can be made replaceable because
5930 its final value can be calculated. This code can not be part of record_giv
5931 above, because final_giv_value requires that the number of loop iterations
5932 be known, and that can not be accurately calculated until after all givs
5933 have been identified. */
5935 static void
5939 {
5946 /* DEST_ADDR givs will never reach here, because they are always marked
5947 replaceable above in record_giv. */
5949 /* The giv can be replaced outright by the reduced register only if all
5950 of the following conditions are true:
5951 - the insn that sets the giv is always executed on any iteration
5952 on which the giv is used at all
5953 (there are two ways to deduce this:
5954 either the insn is executed on every iteration,
5955 or all uses follow that insn in the same basic block),
5956 - its final value can be calculated (this condition is different
5957 than the one above in record_giv)
5958 - it's not used before the it's set
5959 - no assignments to the biv occur during the giv's lifetime. */
5961 #if 0
5962 /* This is only called now when replaceable is known to be false. */
5963 /* Clear replaceable, so that it won't confuse final_giv_value. */
5965 #endif
5970 {
5973 rtx last_giv_use;
5977 /* When trying to determine whether or not a biv increment occurs
5978 during the lifetime of the giv, we can ignore uses of the variable
5979 outside the loop because final_value is true. Hence we can not
5980 use regno_last_uid and regno_first_uid as above in record_giv. */
5982 /* Search the loop to determine whether any assignments to the
5983 biv occur during the giv's lifetime. Start with the insn
5984 that sets the giv, and search around the loop until we come
5985 back to that insn again.
5987 Also fail if there is a jump within the giv's lifetime that jumps
5988 to somewhere outside the lifetime but still within the loop. This
5989 catches spaghetti code where the execution order is not linear, and
5990 hence the above test fails. Here we assume that the giv lifetime
5991 does not extend from one iteration of the loop to the next, so as
5992 to make the test easier. Since the lifetime isn't known yet,
5993 this requires two loops. See also record_giv above. */
5998 {
6001 {
6004 }
6010 {
6011 /* It is possible for the BIV increment to use the GIV if we
6012 have a cycle. Thus we must be sure to check each insn for
6013 both BIV and GIV uses, and we must check for BIV uses
6014 first. */
6021 {
6023 {
6027 }
6029 }
6030 }
6031 }
6033 /* Now that the lifetime of the giv is known, check for branches
6034 from within the lifetime to outside the lifetime if it is still
6035 replaceable. */
6038 {
6041 {
6054 {
6063 }
6064 }
6065 }
6067 /* If it is replaceable, then save the final value. */
6070 }
6075 }
6076 \f
6077 /* Update the status of whether a giv can derive other givs.
6079 We need to do something special if there is or may be an update to the biv
6080 between the time the giv is defined and the time it is used to derive
6081 another giv.
6083 In addition, a giv that is only conditionally set is not allowed to
6084 derive another giv once a label has been passed.
6086 The cases we look at are when a label or an update to a biv is passed. */
6088 static void
6091 rtx p;
6092 {
6096 rtx tem;
6099 /* Search all IV classes, then all bivs, and finally all givs.
6101 There are three cases we are concerned with. First we have the situation
6102 of a giv that is only updated conditionally. In that case, it may not
6103 derive any givs after a label is passed.
6105 The second case is when a biv update occurs, or may occur, after the
6106 definition of a giv. For certain biv updates (see below) that are
6107 known to occur between the giv definition and use, we can adjust the
6108 giv definition. For others, or when the biv update is conditional,
6109 we must prevent the giv from deriving any other givs. There are two
6110 sub-cases within this case.
6112 If this is a label, we are concerned with any biv update that is done
6113 conditionally, since it may be done after the giv is defined followed by
6114 a branch here (actually, we need to pass both a jump and a label, but
6115 this extra tracking doesn't seem worth it).
6117 If this is a jump, we are concerned about any biv update that may be
6118 executed multiple times. We are actually only concerned about
6119 backward jumps, but it is probably not worth performing the test
6120 on the jump again here.
6122 If this is a biv update, we must adjust the giv status to show that a
6123 subsequent biv update was performed. If this adjustment cannot be done,
6124 the giv cannot derive further givs. */
6130 {
6132 {
6133 /* If cant_derive is already true, there is no point in
6134 checking all of these conditions again. */
6138 /* If this giv is conditionally set and we have passed a label,
6139 it cannot derive anything. */
6143 /* Skip givs that have mult_val == 0, since
6144 they are really invariants. Also skip those that are
6145 replaceable, since we know their lifetime doesn't contain
6146 any biv update. */
6150 /* The only way we can allow this giv to derive another
6151 is if this is a biv increment and we can form the product
6152 of biv->add_val and giv->mult_val. In this case, we will
6153 be able to compute a compensation. */
6155 {
6156 rtx ext_val_dummy;
6167 tem = simplify_giv_expr
6174 else
6176 }
6180 }
6181 }
6182 }
6183 \f
6184 /* Check whether an insn is an increment legitimate for a basic induction var.
6185 X is the source of insn P, or a part of it.
6186 MODE is the mode in which X should be interpreted.
6188 DEST_REG is the putative biv, also the destination of the insn.
6189 We accept patterns of these forms:
6190 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6191 REG = INVARIANT + REG
6193 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6194 store the additive term into *INC_VAL, and store the place where
6195 we found the additive term into *LOCATION.
6197 If X is an assignment of an invariant into DEST_REG, we set
6198 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6200 We also want to detect a BIV when it corresponds to a variable
6201 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6202 of the variable may be a PLUS that adds a SUBREG of that variable to
6203 an invariant and then sign- or zero-extends the result of the PLUS
6204 into the variable.
6206 Most GIVs in such cases will be in the promoted mode, since that is the
6207 probably the natural computation mode (and almost certainly the mode
6208 used for addresses) on the machine. So we view the pseudo-reg containing
6209 the variable as the BIV, as if it were simply incremented.
6211 Note that treating the entire pseudo as a BIV will result in making
6212 simple increments to any GIVs based on it. However, if the variable
6213 overflows in its declared mode but not its promoted mode, the result will
6214 be incorrect. This is acceptable if the variable is signed, since
6215 overflows in such cases are undefined, but not if it is unsigned, since
6216 those overflows are defined. So we only check for SIGN_EXTEND and
6217 not ZERO_EXTEND.
6219 If we cannot find a biv, we return 0. */
6221 static int
6224 rtx x;
6226 rtx dest_reg;
6227 rtx p;
6231 {
6239 {
6245 {
6247 }
6252 {
6254 }
6255 else
6268 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6269 handle addition of promoted variables.
6270 ??? The comment at the start of this function is wrong: promoted
6271 variable increments don't look like it says they do. */
6277 /* If this register is assigned in a previous insn, look at its
6278 source, but don't go outside the loop or past a label. */
6280 /* If this sets a register to itself, we would repeat any previous
6281 biv increment if we applied this strategy blindly. */
6287 {
6288 rtx dest;
6289 do
6290 {
6292 }
6321 }
6322 /* Fall through. */
6324 /* Can accept constant setting of biv only when inside inner most loop.
6325 Otherwise, a biv of an inner loop may be incorrectly recognized
6326 as a biv of the outer loop,
6327 causing code to be moved INTO the inner loop. */
6334 /* convert_modes aborts if we try to convert to or from CCmode, so just
6335 exclude that case. It is very unlikely that a condition code value
6336 would be a useful iterator anyways. convert_modes aborts if we try to
6337 convert a float mode to non-float or vice versa too. */
6341 {
6342 /* Possible bug here? Perhaps we don't know the mode of X. */
6346 }
6347 else
6355 /* Similar, since this can be a sign extension. */
6360 ;
6374 location);
6379 }
6380 }
6381 \f
6382 /* A general induction variable (giv) is any quantity that is a linear
6383 function of a basic induction variable,
6384 i.e. giv = biv * mult_val + add_val.
6385 The coefficients can be any loop invariant quantity.
6386 A giv need not be computed directly from the biv;
6387 it can be computed by way of other givs. */
6389 /* Determine whether X computes a giv.
6390 If it does, return a nonzero value
6391 which is the benefit from eliminating the computation of X;
6392 set *SRC_REG to the register of the biv that it is computed from;
6393 set *ADD_VAL and *MULT_VAL to the coefficients,
6394 such that the value of X is biv * mult + add; */
6396 static int
6400 rtx x;
6408 {
6412 /* If this is an invariant, forget it, it isn't a giv. */
6423 {
6426 /* Since this is now an invariant and wasn't before, it must be a giv
6427 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6428 with. */
6435 /* This is equivalent to a BIV. */
6442 /* Either (plus (biv) (invar)) or
6443 (plus (mult (biv) (invar_1)) (invar_2)). */
6445 {
6448 }
6449 else
6450 {
6453 }
6458 /* ADD_VAL is zero. */
6466 }
6468 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6469 unless they are CONST_INT). */
6477 else
6480 /* Always return true if this is a giv so it will be detected as such,
6481 even if the benefit is zero or negative. This allows elimination
6482 of bivs that might otherwise not be eliminated. */
6484 }
6485 \f
6486 /* Given an expression, X, try to form it as a linear function of a biv.
6487 We will canonicalize it to be of the form
6488 (plus (mult (BIV) (invar_1))
6489 (invar_2))
6490 with possible degeneracies.
6492 The invariant expressions must each be of a form that can be used as a
6493 machine operand. We surround then with a USE rtx (a hack, but localized
6494 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6495 routine; it is the caller's responsibility to strip them.
6497 If no such canonicalization is possible (i.e., two biv's are used or an
6498 expression that is neither invariant nor a biv or giv), this routine
6499 returns 0.
6501 For a non-zero return, the result will have a code of CONST_INT, USE,
6502 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6504 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6509 static rtx
6512 rtx x;
6515 {
6520 rtx tem;
6522 /* If this is not an integer mode, or if we cannot do arithmetic in this
6523 mode, this can't be a giv. */
6530 {
6537 /* Put constant last, CONST_INT last if both constant. */
6545 /* Handle addition of zero, then addition of an invariant. */
6550 {
6553 /* Adding two invariants must result in an invariant, so enclose
6554 addition operation inside a USE and return it. */
6564 else
6573 /* biv + invar or mult + invar. Return sum. */
6577 /* (a + invar_1) + invar_2. Associate. */
6578 return
6584 arg1)),
6589 }
6591 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6592 MULT to reduce cases. */
6598 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6599 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6600 Recurse to associate the second PLUS. */
6605 return
6613 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6629 /* Handle "a - b" as "a + b * (-1)". */
6635 constm1_rtx)),
6644 /* Put constant last, CONST_INT last if both constant. */
6649 /* If second argument is not now constant, not giv. */
6653 /* Handle multiply by 0 or 1. */
6661 {
6663 /* biv * invar. Done. */
6667 /* Product of two constants. */
6671 /* invar * invar is a giv, but attempt to simplify it somehow. */
6677 {
6678 /* (invar_0 * invar_1) * invar_2. Associate. */
6685 arg1)),
6687 }
6688 /* Porpagate the MULT expressions to the intermost nodes. */
6690 {
6691 /* (invar_0 + invar_1) * invar_2. Distribute. */
6697 arg1),
6701 arg1)),
6703 }
6707 /* (a * invar_1) * invar_2. Associate. */
6713 arg1)),
6717 /* (a + invar_1) * invar_2. Distribute. */
6722 arg1),
6725 arg1)),
6730 }
6733 /* Shift by constant is multiply by power of two. */
6737 return
6746 /* "-a" is "a * (-1)" */
6752 /* "~a" is "-a - 1". Silly, but easy. */
6756 const1_rtx),
6760 /* Already in proper form for invariant. */
6766 /* Conditionally recognize extensions of simple IVs. After we've
6767 computed loop traversal counts and verified the range of the
6768 source IV, we'll reevaluate this as a GIV. */
6770 {
6773 {
6776 }
6777 }
6781 /* If this is a new register, we can't deal with it. */
6785 /* Check for biv or giv. */
6787 {
6791 {
6794 /* Form expression from giv and add benefit. Ensure this giv
6795 can derive another and subtract any needed adjustment if so. */
6797 /* Increasing the benefit here is risky. The only case in which it
6798 is arguably correct is if this is the only use of V. In other
6799 cases, this will artificially inflate the benefit of the current
6800 giv, and lead to suboptimal code. Thus, it is disabled, since
6801 potentially not reducing an only marginally beneficial giv is
6802 less harmful than reducing many givs that are not really
6803 beneficial. */
6804 {
6808 }
6821 {
6824 }
6825 else
6826 {
6829 }
6831 }
6834 do_default:
6835 /* If it isn't an induction variable, and it is invariant, we
6836 may be able to simplify things further by looking through
6837 the bits we just moved outside the loop. */
6839 {
6845 {
6846 /* Ok, we found a match. Substitute and simplify. */
6848 /* If we match another movable, we must use that, as
6849 this one is going away. */
6854 /* If consec is non-zero, this is a member of a group of
6855 instructions that were moved together. We handle this
6856 case only to the point of seeking to the last insn and
6857 looking for a REG_EQUAL. Fail if we don't find one. */
6859 {
6862 do
6863 {
6865 }
6871 }
6872 else
6873 {
6877 }
6880 {
6881 /* What we are most interested in is pointer
6882 arithmetic on invariants -- only take
6883 patterns we may be able to do something with. */
6889 {
6891 benefit);
6894 }
6899 {
6904 }
6905 }
6907 }
6908 }
6910 }
6912 /* Fall through to general case. */
6914 /* If invariant, return as USE (unless CONST_INT).
6915 Otherwise, not giv. */
6920 {
6929 }
6930 else
6932 }
6933 }
6935 /* This routine folds invariants such that there is only ever one
6936 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6938 static rtx
6941 {
6947 {
6950 }
6953 {
6956 }
6957 else
6958 {
6961 }
6962 }
6964 static rtx
6968 {
6970 {
6974 else
6977 }
6980 else
6983 }
6984 \f
6985 /* Help detect a giv that is calculated by several consecutive insns;
6986 for example,
6987 giv = biv * M
6988 giv = giv + A
6989 The caller has already identified the first insn P as having a giv as dest;
6990 we check that all other insns that set the same register follow
6991 immediately after P, that they alter nothing else,
6992 and that the result of the last is still a giv.
6994 The value is 0 if the reg set in P is not really a giv.
6995 Otherwise, the value is the amount gained by eliminating
6996 all the consecutive insns that compute the value.
6998 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6999 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7001 The coefficients of the ultimate giv value are stored in
7002 *MULT_VAL and *ADD_VAL. */
7004 static int
7009 rtx p;
7010 rtx src_reg;
7011 rtx dest_reg;
7016 {
7022 rtx temp;
7023 rtx set;
7025 /* Indicate that this is a giv so that we can update the value produced in
7026 each insn of the multi-insn sequence.
7028 This induction structure will be used only by the call to
7029 general_induction_var below, so we can allocate it on our stack.
7030 If this is a giv, our caller will replace the induct var entry with
7031 a new induction structure. */
7052 {
7056 /* If libcall, skip to end of call sequence. */
7067 /* Giv created by equivalent expression. */
7073 {
7077 count--;
7081 }
7083 {
7084 /* Allow insns that set something other than this giv to a
7085 constant. Such insns are needed on machines which cannot
7086 include long constants and should not disqualify a giv. */
7095 }
7096 }
7101 }
7102 \f
7103 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7104 represented by G1. If no such expression can be found, or it is clear that
7105 it cannot possibly be a valid address, 0 is returned.
7107 To perform the computation, we note that
7108 G1 = x * v + a and
7109 G2 = y * v + b
7110 where `v' is the biv.
7112 So G2 = (y/b) * G1 + (b - a*y/x).
7114 Note that MULT = y/x.
7116 Update: A and B are now allowed to be additive expressions such that
7117 B contains all variables in A. That is, computing B-A will not require
7118 subtracting variables. */
7120 static rtx
7123 {
7124 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7129 /* If MULT is not 1, we cannot handle A with non-constants, since we
7130 would then be required to subtract multiples of the registers in A.
7131 This is theoretically possible, and may even apply to some Fortran
7132 constructs, but it is a lot of work and we do not attempt it here. */
7137 /* In general these structures are sorted top to bottom (down the PLUS
7138 chain), but not left to right across the PLUS. If B is a higher
7139 order giv than A, we can strip one level and recurse. If A is higher
7140 order, we'll eventually bail out, but won't know that until the end.
7141 If they are the same, we'll strip one level around this loop. */
7144 {
7156 /* We matched: remove one reg completely. */
7159 /* An alternate match. */
7162 /* An alternate match. */
7164 else
7165 {
7166 /* Indicates an extra register in B. Strip one level from B and
7167 recurse, hoping B was the higher order expression. */
7172 }
7173 }
7175 /* Here we are at the last level of A, go through the cases hoping to
7176 get rid of everything but a constant. */
7179 {
7192 }
7194 {
7196 }
7198 {
7203 }
7205 {
7210 else
7212 }
7217 }
7219 rtx
7222 {
7225 /* The value that G1 will be multiplied by must be a constant integer. Also,
7226 the only chance we have of getting a valid address is if b*c/a (see above
7227 for notation) is also an integer. */
7230 {
7235 }
7238 else
7239 {
7240 /* ??? Find out if the one is a multiple of the other? */
7242 }
7246 {
7247 /* Failed. If we've got a multiplication factor between G1 and G2,
7248 scale G1's addend and try again. */
7250 {
7254 {
7255 HOST_WIDE_INT m;
7259 }
7260 else
7261 {
7263 mult);
7264 }
7267 }
7268 }
7272 /* Form simplified final result. */
7277 else
7282 else
7283 {
7286 {
7290 }
7293 }
7294 }
7295 \f
7296 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7297 represented by G1. This indicates that G2 should be combined with G1 and
7298 that G2 can use (either directly or via an address expression) a register
7299 used to represent G1. */
7301 static rtx
7304 {
7307 /* With the introduction of ext dependent givs, we must care for modes.
7308 G2 must not use a wider mode than G1. */
7318 /* If these givs are identical, they can be combined. We use the results
7319 of express_from because the addends are not in a canonical form, so
7320 rtx_equal_p is a weaker test. */
7321 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7322 combination to be the other way round. */
7325 {
7327 }
7329 /* If G2 can be expressed as a function of G1 and that function is valid
7330 as an address and no more expensive than using a register for G2,
7331 the expression of G2 in terms of G1 can be used. */
7335 /* ??? Looses, especially with -fforce-addr, where *g2->location
7336 will always be a register, and so anything more complicated
7337 gets discarded. */
7338 #if 0
7339 #ifdef ADDRESS_COST
7341 #else
7343 #endif
7344 #endif
7345 )
7346 {
7348 }
7351 }
7352 \f
7353 /* Check each extension dependent giv in this class to see if its
7354 root biv is safe from wrapping in the interior mode, which would
7355 make the giv illegal. */
7357 static void
7361 {
7364 HOST_WIDE_INT start_val;
7370 /* Make sure the iteration data is available. We must have
7371 constants in order to be certain of no overflow. */
7372 /* ??? An unknown iteration count with an increment of +-1
7373 combined with friendly exit tests of against an invariant
7374 value is also ameanable to optimization. Not implemented. */
7380 /* Make sure the host can represent the arithmetic. */
7382 {
7384 HOST_WIDE_INT s_end_val;
7396 /* Check for host arithmatic overflow. */
7398 {
7400 HOST_WIDE_INT s_max;
7407 /* Check zero extension of biv ok. */
7409 /* Check for host arithmatic overflow. */
7410 && (neg_incr
7413 /* Check for target arithmetic overflow. */
7414 && (neg_incr
7417 {
7419 }
7421 /* Check sign extension of biv ok. */
7422 /* ??? While it is true that overflow with signed and pointer
7423 arithmetic is undefined, I fear too many programmers don't
7424 keep this fact in mind -- myself included on occasion.
7425 So leave alone with the signed overflow optimizations. */
7427 /* Check for host arithmatic overflow. */
7428 && (neg_incr
7431 /* Check for target arithmetic overflow. */
7432 && (neg_incr
7435 {
7437 }
7438 }
7439 }
7441 /* Invalidate givs that fail the tests. */
7444 {
7449 {
7458 /* We don't know whether this value is being used as either
7459 signed or unsigned, so to safely truncate we must satisfy
7460 both. The initial check here verifies the BIV itself;
7461 once that is successful we may check its range wrt the
7462 derived GIV. */
7464 {
7468 /* We know from the above that both endpoints are nonnegative,
7469 and that there is no wrapping. Verify that both endpoints
7470 are within the (signed) range of the outer mode. */
7473 }
7478 }
7481 {
7483 {
7487 }
7488 }
7489 else
7490 {
7492 {
7497 else
7498 {
7503 else
7505 }
7510 }
7513 }
7514 }
7515 }
7517 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7519 rtx
7522 rtx value;
7523 {
7529 /* Recall that check_ext_dependent_givs verified that the known bounds
7530 of a biv did not overflow or wrap with respect to the extension for
7531 the giv. Therefore, constants need no additional adjustment. */
7535 /* Otherwise, we must adjust the value to compensate for the
7536 differing modes of the biv and the giv. */
7538 }
7539 \f
7540 struct combine_givs_stats
7541 {
7544 };
7546 static int
7550 {
7557 /* Stabilize the sort. */
7561 }
7563 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7564 any other. If so, point SAME to the giv combined with and set NEW_REG to
7565 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7566 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7568 static void
7572 {
7573 /* Additional benefit to add for being combined multiple times. */
7581 /* Count givs, because bl->giv_count is incorrect here. */
7585 giv_count++;
7587 giv_array
7598 {
7600 rtx single_use;
7605 /* If a DEST_REG GIV is used only once, do not allow it to combine
7606 with anything, for in doing so we will gain nothing that cannot
7607 be had by simply letting the GIV with which we would have combined
7608 to be reduced on its own. The losage shows up in particular with
7609 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7610 be seen elsewhere as well. */
7617 /* Add an additional weight for zero addends. */
7622 {
7623 rtx this_combine;
7628 {
7631 }
7632 }
7634 }
7636 /* Iterate, combining until we can't. */
7637 restart:
7641 {
7644 {
7650 }
7652 }
7655 {
7661 /* If it has already been combined, skip. */
7666 {
7669 /* If it has already been combined, skip. */
7671 {
7676 /* For destination, we now may replace by mem expression instead
7677 of register. This changes the costs considerably, so add the
7678 compensation. */
7688 /* ??? The new final_[bg]iv_value code does a much better job
7689 of finding replaceable giv's, and hence this code may no
7690 longer be necessary. */
7694 /* To help optimize the next set of combinations, remove
7695 this giv from the benefits of other potential mates. */
7697 {
7701 }
7708 }
7709 }
7711 /* To help optimize the next set of combinations, remove
7712 this giv from the benefits of other potential mates. */
7714 {
7716 {
7720 }
7724 /* We've finished with this giv, and everything it touched.
7725 Restart the combination so that proper weights for the
7726 rest of the givs are properly taken into account. */
7727 /* ??? Ideally we would compact the arrays at this point, so
7728 as to not cover old ground. But sanely compacting
7729 can_combine is tricky. */
7731 }
7732 }
7734 /* Clean up. */
7737 }
7738 \f
7739 /* Generate sequence for REG = B * M + A. */
7741 static rtx
7747 {
7748 rtx seq;
7749 rtx result;
7752 /* Use unsigned arithmetic. */
7760 }
7763 /* Update registers created in insn sequence SEQ. */
7765 static void
7768 rtx seq;
7769 {
7770 rtx insn;
7772 /* Update register info for alias analysis. */
7778 {
7781 {
7788 }
7789 }
7793 }
7796 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7798 void
7805 basic_block before_bb;
7806 rtx before_insn;
7807 {
7808 rtx seq;
7811 {
7814 }
7816 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7819 /* Increase the lifetime of any invariants moved further in code. */
7826 /* It is possible that the expansion created lots of new registers.
7827 Iterate over the sequence we just created and record them all. */
7829 }
7832 /* Emit insns in loop pre-header to set REG = B * M + A. */
7834 void
7841 {
7842 rtx seq;
7844 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7847 /* Increase the lifetime of any invariants moved further in code.
7848 ???? Is this really necessary? */
7855 /* It is possible that the expansion created lots of new registers.
7856 Iterate over the sequence we just created and record them all. */
7858 }
7861 /* Emit insns after loop to set REG = B * M + A. */
7863 void
7870 {
7871 rtx seq;
7873 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7878 /* It is possible that the expansion created lots of new registers.
7879 Iterate over the sequence we just created and record them all. */
7881 }
7885 /* Similar to gen_add_mult, but compute cost rather than generating
7886 sequence. */
7888 static int
7894 {
7904 {
7909 }
7912 }
7913 \f
7914 /* Test whether A * B can be computed without
7915 an actual multiply insn. Value is 1 if so.
7917 ??? This function stinks because it generates a ton of wasted RTL
7918 ??? and as a result fragments GC memory to no end. There are other
7919 ??? places in the compiler which are invoked a lot and do the same
7920 ??? thing, generate wasted RTL just to see if something is possible. */
7922 static int
7924 rtx a;
7925 rtx b;
7926 {
7927 rtx tmp;
7930 /* If only one is constant, make it B. */
7934 /* If first constant, both constant, so don't need multiply. */
7938 /* If second not constant, neither is constant, so would need multiply. */
7942 /* One operand is constant, so might not need multiply insn. Generate the
7943 code for the multiply and see if a call or multiply, or long sequence
7944 of insns is generated. */
7953 {
7956 {
7966 {
7969 }
7972 }
7973 }
7983 }
7984 \f
7985 /* Check to see if loop can be terminated by a "decrement and branch until
7986 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7987 Also try reversing an increment loop to a decrement loop
7988 to see if the optimization can be performed.
7989 Value is nonzero if optimization was performed. */
7991 /* This is useful even if the architecture doesn't have such an insn,
7992 because it might change a loops which increments from 0 to n to a loop
7993 which decrements from n to 0. A loop that decrements to zero is usually
7994 faster than one that increments from zero. */
7996 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7997 such as approx_final_value, biv_total_increment, loop_iterations, and
7998 final_[bg]iv_value. */
8000 static int
8004 {
8009 rtx reg;
8010 rtx jump_label;
8011 rtx final_value;
8012 rtx start_value;
8013 rtx new_add_val;
8014 rtx comparison;
8015 rtx before_comparison;
8016 rtx p;
8017 rtx jump;
8018 rtx first_compare;
8023 /* If last insn is a conditional branch, and the insn before tests a
8024 register value, try to optimize it. Otherwise, we can't do anything. */
8033 /* Try to compute whether the compare/branch at the loop end is one or
8034 two instructions. */
8040 else
8043 {
8044 /* If more than one condition is present to control the loop, then
8045 do not proceed, as this function does not know how to rewrite
8046 loop tests with more than one condition.
8048 Look backwards from the first insn in the last comparison
8049 sequence and see if we've got another comparison sequence. */
8051 rtx jump1;
8055 }
8057 /* Check all of the bivs to see if the compare uses one of them.
8058 Skip biv's set more than once because we can't guarantee that
8059 it will be zero on the last iteration. Also skip if the biv is
8060 used between its update and the test insn. */
8063 {
8068 first_compare))
8070 }
8075 /* Look for the case where the basic induction variable is always
8076 nonnegative, and equals zero on the last iteration.
8077 In this case, add a reg_note REG_NONNEG, which allows the
8078 m68k DBRA instruction to be used. */
8086 {
8087 /* Initial value must be greater than 0,
8088 init_val % -dec_value == 0 to ensure that it equals zero on
8089 the last iteration */
8095 {
8096 /* register always nonnegative, add REG_NOTE to branch */
8104 }
8106 /* If the decrement is 1 and the value was tested as >= 0 before
8107 the loop, then we can safely optimize. */
8109 {
8122 {
8130 }
8131 }
8132 }
8135 {
8136 /* Try to change inc to dec, so can apply above optimization. */
8137 /* Can do this if:
8138 all registers modified are induction variables or invariant,
8139 all memory references have non-overlapping addresses
8140 (obviously true if only one write)
8141 allow 2 insns for the compare/jump at the end of the loop. */
8142 /* Also, we must avoid any instructions which use both the reversed
8143 biv and another biv. Such instructions will fail if the loop is
8144 reversed. We meet this condition by requiring that either
8145 no_use_except_counting is true, or else that there is only
8146 one biv. */
8148 /* 1 if the iteration var is used only to count iterations. */
8150 /* 1 if the loop has no memory store, or it has a single memory store
8151 which is reversible. */
8157 {
8161 /* If there are no givs for this biv, and the only exit is the
8162 fall through at the end of the loop, then
8163 see if perhaps there are no uses except to count. */
8167 {
8172 /* An insn that sets the biv is okay. */
8173 ;
8177 {
8178 /* If either of these insns uses the biv and sets a pseudo
8179 that has more than one usage, then the biv has uses
8180 other than counting since it's used to derive a value
8181 that is used more than one time. */
8183 regs);
8185 {
8188 }
8189 }
8191 {
8194 }
8195 }
8197 /* A biv has uses besides counting if it is used to set
8198 another biv. */
8202 {
8205 }
8206 }
8209 /* No need to worry about MEMs. */
8210 ;
8212 {
8217 /* If the loop has a single store, and the destination address is
8218 invariant, then we can't reverse the loop, because this address
8219 might then have the wrong value at loop exit.
8220 This would work if the source was invariant also, however, in that
8221 case, the insn should have been moved out of the loop. */
8224 {
8227 /* If we could prove that each of the memory locations
8228 written to was different, then we could reverse the
8229 store -- but we don't presently have any way of
8230 knowing that. */
8233 /* If the store depends on a register that is set after the
8234 store, it depends on the initial value, and is thus not
8235 reversible. */
8237 {
8244 }
8245 }
8246 }
8247 else
8250 /* This code only acts for innermost loops. Also it simplifies
8251 the memory address check by only reversing loops with
8252 zero or one memory access.
8253 Two memory accesses could involve parts of the same array,
8254 and that can't be reversed.
8255 If the biv is used only for counting, than we don't need to worry
8256 about all these things. */
8262 && reversible_mem_store
8267 {
8268 rtx tem;
8270 /* Loop can be reversed. */
8274 /* Now check other conditions:
8276 The increment must be a constant, as must the initial value,
8277 and the comparison code must be LT.
8279 This test can probably be improved since +/- 1 in the constant
8280 can be obtained by changing LT to LE and vice versa; this is
8281 confusing. */
8284 /* for constants, LE gets turned into LT */
8288 {
8299 comparison_const_width
8301 else
8302 comparison_const_width
8306 comparison_sign_mask
8309 /* If the comparison value is not a loop invariant, then we
8310 can not reverse this loop.
8312 ??? If the insns which initialize the comparison value as
8313 a whole compute an invariant result, then we could move
8314 them out of the loop and proceed with loop reversal. */
8322 /* Normalize the initial value if it is an integer and
8323 has no other use except as a counter. This will allow
8324 a few more loops to be reversed. */
8328 {
8330 /* The code below requires comparison_val to be a multiple
8331 of add_val in order to do the loop reversal, so
8332 round up comparison_val to a multiple of add_val.
8333 Since comparison_value is constant, we know that the
8334 current comparison code is LT. */
8336 comparison_val
8338 /* We postpone overflow checks for COMPARISON_VAL here;
8339 even if there is an overflow, we might still be able to
8340 reverse the loop, if converting the loop exit test to
8341 NE is possible. */
8343 }
8345 /* First check if we can do a vanilla loop reversal. */
8347 /* If we have a decrement_and_branch_on_count,
8348 prefer the NE test, since this will allow that
8349 instruction to be generated. Note that we must
8350 use a vanilla loop reversal if the biv is used to
8351 calculate a giv or has a non-counting use. */
8352 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8353 && defined (HAVE_decrement_and_branch_on_count)
8357 #endif
8359 /* Now do postponed overflow checks on COMPARISON_VAL. */
8362 {
8363 /* Register will always be nonnegative, with value
8364 0 on last iteration */
8368 }
8372 {
8375 }
8376 else
8382 /* If the initial value is not zero, or if the comparison
8383 value is not an exact multiple of the increment, then we
8384 can not reverse this loop. */
8387 {
8390 }
8391 else
8392 {
8395 }
8399 /* Reset these in case we normalized the initial value
8400 and comparison value above. */
8403 {
8405 final_value
8407 }
8410 /* Save some info needed to produce the new insns. */
8415 /* Set start_value; if this is not a CONST_INT, we need
8416 to generate a SUB.
8417 Initialize biv to start_value before loop start.
8418 The old initializing insn will be deleted as a
8419 dead store by flow.c. */
8422 {
8425 }
8427 {
8435 start_value
8441 }
8443 {
8446 initial_value);
8450 start_value
8453 }
8454 else
8455 /* We could handle the other cases too, but it'll be
8456 better to have a testcase first. */
8459 /* We may not have a single insn which can increment a reg, so
8460 create a sequence to hold all the insns from expand_inc. */
8469 /* Update biv info to reflect its new status. */
8474 /* Update loop info. */
8483 /* Inc LABEL_NUSES so that delete_insn will
8484 not delete the label. */
8487 /* Emit an insn after the end of the loop to set the biv's
8488 proper exit value if it is used anywhere outside the loop. */
8494 /* Delete compare/branch at end of loop. */
8499 /* Add new compare/branch insn at end of loop. */
8511 ;
8517 {
8519 {
8520 /* Increment of LABEL_NUSES done above. */
8521 /* Register is now always nonnegative,
8522 so add REG_NONNEG note to the branch. */
8525 }
8527 }
8529 /* No insn may reference both the reversed and another biv or it
8530 will fail (see comment near the top of the loop reversal
8531 code).
8532 Earlier on, we have verified that the biv has no use except
8533 counting, or it is the only biv in this function.
8534 However, the code that computes no_use_except_counting does
8535 not verify reg notes. It's possible to have an insn that
8536 references another biv, and has a REG_EQUAL note with an
8537 expression based on the reversed biv. To avoid this case,
8538 remove all REG_EQUAL notes based on the reversed biv
8539 here. */
8542 {
8545 /* If this is a set of a GIV based on the reversed biv, any
8546 REG_EQUAL notes should still be correct. */
8553 {
8558 else
8560 }
8561 }
8563 /* Mark that this biv has been reversed. Each giv which depends
8564 on this biv, and which is also live past the end of the loop
8565 will have to be fixed up. */
8570 {
8574 else
8576 }
8579 }
8580 }
8581 }
8584 }
8585 \f
8586 /* Verify whether the biv BL appears to be eliminable,
8587 based on the insns in the loop that refer to it.
8589 If ELIMINATE_P is non-zero, actually do the elimination.
8591 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8592 determine whether invariant insns should be placed inside or at the
8593 start of the loop. */
8595 static int
8601 {
8604 rtx p;
8606 /* Scan all insns in the loop, stopping if we find one that uses the
8607 biv in a way that we cannot eliminate. */
8610 {
8615 /* If this is a libcall that sets a giv, skip ahead to its end. */
8617 {
8621 {
8626 {
8633 }
8634 }
8635 }
8640 {
8646 }
8647 }
8650 {
8655 }
8658 }
8659 \f
8660 /* INSN and REFERENCE are instructions in the same insn chain.
8661 Return non-zero if INSN is first. */
8663 int
8666 {
8670 {
8671 /* Start with test for not first so that INSN == REFERENCE yields not
8672 first. */
8678 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8679 previous insn, hence the <= comparison below does not work if
8680 P is a note. */
8691 }
8692 }
8694 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8695 the offset that we have to take into account due to auto-increment /
8696 div derivation is zero. */
8697 static int
8700 rtx insn;
8701 {
8702 /* If the giv V had the auto-inc address optimization applied
8703 to it, and INSN occurs between the giv insn and the biv
8704 insn, then we'd have to adjust the value used here.
8705 This is rare, so we don't bother to make this possible. */
8714 }
8716 /* If BL appears in X (part of the pattern of INSN), see if we can
8717 eliminate its use. If so, return 1. If not, return 0.
8719 If BIV does not appear in X, return 1.
8721 If ELIMINATE_P is non-zero, actually do the elimination.
8722 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8723 Depending on how many items have been moved out of the loop, it
8724 will either be before INSN (when WHERE_INSN is non-zero) or at the
8725 start of the loop (when WHERE_INSN is zero). */
8727 static int
8733 basic_block where_bb;
8734 rtx where_insn;
8735 {
8741 #ifdef HAVE_cc0
8743 #endif
8749 {
8751 /* If we haven't already been able to do something with this BIV,
8752 we can't eliminate it. */
8758 /* If this sets the BIV, it is not a problem. */
8762 /* If this is an insn that defines a giv, it is also ok because
8763 it will go away when the giv is reduced. */
8768 #ifdef HAVE_cc0
8770 {
8771 /* Can replace with any giv that was reduced and
8772 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8773 Require a constant for MULT_VAL, so we know it's nonzero.
8774 ??? We disable this optimization to avoid potential
8775 overflows. */
8783 {
8790 /* If the giv has the opposite direction of change,
8791 then reverse the comparison. */
8795 else
8798 /* We can probably test that giv's reduced reg. */
8801 }
8803 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8804 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8805 Require a constant for MULT_VAL, so we know it's nonzero.
8806 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8807 overflow problem. */
8819 {
8826 /* If the giv has the opposite direction of change,
8827 then reverse the comparison. */
8831 else
8835 /* Replace biv with the giv's reduced register. */
8840 /* Insn doesn't support that constant or invariant. Copy it
8841 into a register (it will be a loop invariant.) */
8848 /* Substitute the new register for its invariant value in
8849 the compare expression. */
8853 }
8854 }
8855 #endif
8862 /* See if either argument is the biv. */
8867 else
8871 {
8872 /* First try to replace with any giv that has constant positive
8873 mult_val and constant add_val. We might be able to support
8874 negative mult_val, but it seems complex to do it in general. */
8886 {
8890 /* Don't eliminate if the linear combination that makes up
8891 the giv overflows when it is applied to ARG. */
8893 {
8894 rtx add_val;
8898 else
8904 }
8909 /* Replace biv with the giv's reduced reg. */
8912 /* If all constants are actually constant integers and
8913 the derived constant can be directly placed in the COMPARE,
8914 do so. */
8917 {
8920 }
8921 else
8922 {
8923 /* Otherwise, load it into a register. */
8928 }
8934 }
8936 /* Look for giv with positive constant mult_val and nonconst add_val.
8937 Insert insns to calculate new compare value.
8938 ??? Turn this off due to possible overflow. */
8946 {
8947 rtx tem;
8957 /* Replace biv with giv's reduced register. */
8961 /* Compute value to compare against. */
8965 /* Use it in this insn. */
8969 }
8970 }
8972 {
8974 {
8975 /* Look for giv with constant positive mult_val and nonconst
8976 add_val. Insert insns to compute new compare value.
8977 ??? Turn this off due to possible overflow. */
8984 {
8985 rtx tem;
8995 /* Replace biv with giv's reduced register. */
8999 /* Compute value to compare against. */
9006 }
9007 }
9009 /* This code has problems. Basically, you can't know when
9010 seeing if we will eliminate BL, whether a particular giv
9011 of ARG will be reduced. If it isn't going to be reduced,
9012 we can't eliminate BL. We can try forcing it to be reduced,
9013 but that can generate poor code.
9015 The problem is that the benefit of reducing TV, below should
9016 be increased if BL can actually be eliminated, but this means
9017 we might have to do a topological sort of the order in which
9018 we try to process biv. It doesn't seem worthwhile to do
9019 this sort of thing now. */
9021 #if 0
9022 /* Otherwise the reg compared with had better be a biv. */
9027 /* Look for a pair of givs, one for each biv,
9028 with identical coefficients. */
9030 {
9042 {
9049 /* Replace biv with its giv's reduced reg. */
9051 /* Replace other operand with the other giv's
9052 reduced reg. */
9055 }
9056 }
9057 #endif
9058 }
9060 /* If we get here, the biv can't be eliminated. */
9064 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9065 biv is used in it, since it will be replaced. */
9073 }
9075 /* See if any subexpression fails elimination. */
9078 {
9080 {
9093 }
9094 }
9097 }
9098 \f
9099 /* Return nonzero if the last use of REG
9100 is in an insn following INSN in the same basic block. */
9102 static int
9104 rtx reg;
9105 rtx insn;
9106 {
9107 rtx n;
9111 {
9114 }
9116 }
9117 \f
9118 /* Called via `note_stores' to record the initial value of a biv. Here we
9119 just record the location of the set and process it later. */
9121 static void
9123 rtx dest;
9124 rtx set;
9126 {
9137 /* If this is the first set found, record it. */
9139 {
9142 }
9143 }
9144 \f
9145 /* If any of the registers in X are "old" and currently have a last use earlier
9146 than INSN, update them to have a last use of INSN. Their actual last use
9147 will be the previous insn but it will not have a valid uid_luid so we can't
9148 use it. X must be a source expression only. */
9150 static void
9152 rtx x;
9153 rtx insn;
9154 {
9155 /* Check for the case where INSN does not have a valid luid. In this case,
9156 there is no need to modify the regno_last_uid, as this can only happen
9157 when code is inserted after the loop_end to set a pseudo's final value,
9158 and hence this insn will never be the last use of x.
9159 ???? This comment is not correct. See for example loop_givs_reduce.
9160 This may insert an insn before another new insn. */
9164 {
9166 }
9167 else
9168 {
9172 {
9178 }
9179 }
9180 }
9181 \f
9182 /* Given an insn INSN and condition COND, return the condition in a
9183 canonical form to simplify testing by callers. Specifically:
9185 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9186 (2) Both operands will be machine operands; (cc0) will have been replaced.
9187 (3) If an operand is a constant, it will be the second operand.
9188 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9189 for GE, GEU, and LEU.
9191 If the condition cannot be understood, or is an inequality floating-point
9192 comparison which needs to be reversed, 0 will be returned.
9194 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9196 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9197 insn used in locating the condition was found. If a replacement test
9198 of the condition is desired, it should be placed in front of that
9199 insn and we will be sure that the inputs are still valid.
9201 If WANT_REG is non-zero, we wish the condition to be relative to that
9202 register, if possible. Therefore, do not canonicalize the condition
9203 further. */
9205 rtx
9207 rtx insn;
9208 rtx cond;
9211 rtx want_reg;
9212 {
9215 rtx set;
9216 rtx tem;
9234 /* If we are comparing a register with zero, see if the register is set
9235 in the previous insn to a COMPARE or a comparison operation. Perform
9236 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9237 in cse.c */
9242 {
9243 /* Set non-zero when we find something of interest. */
9246 #ifdef HAVE_cc0
9247 /* If comparison with cc0, import actual comparison from compare
9248 insn. */
9250 {
9261 }
9262 #endif
9264 /* If this is a COMPARE, pick up the two things being compared. */
9266 {
9270 }
9274 /* Go back to the previous insn. Stop if it is not an INSN. We also
9275 stop if it isn't a single set or if it has a REG_INC note because
9276 we don't want to bother dealing with it. */
9290 /* If this is setting OP0, get what it sets it to if it looks
9291 relevant. */
9293 {
9296 /* ??? We may not combine comparisons done in a CCmode with
9297 comparisons not done in a CCmode. This is to aid targets
9298 like Alpha that have an IEEE compliant EQ instruction, and
9299 a non-IEEE compliant BEQ instruction. The use of CCmode is
9300 actually artificial, simply to prevent the combination, but
9301 should not affect other platforms.
9303 However, we must allow VOIDmode comparisons to match either
9304 CCmode or non-CCmode comparison, because some ports have
9305 modeless comparisons inside branch patterns.
9307 ??? This mode check should perhaps look more like the mode check
9308 in simplify_comparison in combine. */
9316 && (STORE_FLAG_VALUE
9319 #ifdef FLOAT_STORE_FLAG_VALUE
9322 && (REAL_VALUE_NEGATIVE
9324 #endif
9325 ))
9336 && (STORE_FLAG_VALUE
9339 #ifdef FLOAT_STORE_FLAG_VALUE
9342 && (REAL_VALUE_NEGATIVE
9344 #endif
9345 ))
9351 {
9354 }
9355 else
9357 }
9360 /* If this sets OP0, but not directly, we have to give up. */
9364 {
9368 {
9373 }
9378 }
9379 }
9381 /* If constant is first, put it last. */
9385 /* If OP0 is the result of a comparison, we weren't able to find what
9386 was really being compared, so fail. */
9390 /* Canonicalize any ordered comparison with integers involving equality
9391 if we can do computations in the relevant mode and we do not
9392 overflow. */
9397 {
9400 unsigned HOST_WIDE_INT max_val
9404 {
9410 /* When cross-compiling, const_val might be sign-extended from
9411 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9431 }
9432 }
9434 #ifdef HAVE_cc0
9435 /* Never return CC0; return zero instead. */
9438 #endif
9441 }
9443 /* Given a jump insn JUMP, return the condition that will cause it to branch
9444 to its JUMP_LABEL. If the condition cannot be understood, or is an
9445 inequality floating-point comparison which needs to be reversed, 0 will
9446 be returned.
9448 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9449 insn used in locating the condition was found. If a replacement test
9450 of the condition is desired, it should be placed in front of that
9451 insn and we will be sure that the inputs are still valid. */
9453 rtx
9455 rtx jump;
9457 {
9458 rtx cond;
9460 rtx set;
9462 /* If this is not a standard conditional jump, we can't parse it. */
9470 /* If this branches to JUMP_LABEL when the condition is false, reverse
9471 the condition. */
9472 reverse
9477 }
9479 /* Similar to above routine, except that we also put an invariant last
9480 unless both operands are invariants. */
9482 rtx
9485 rtx x;
9486 {
9496 }
9498 /* Scan the function and determine whether it has indirect (computed) jumps.
9500 This is taken mostly from flow.c; similar code exists elsewhere
9501 in the compiler. It may be useful to put this into rtlanal.c. */
9502 static int
9504 rtx start;
9505 {
9506 rtx insn;
9513 }
9515 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9516 documentation for LOOP_MEMS for the definition of `appropriate'.
9517 This function is called from prescan_loop via for_each_rtx. */
9519 static int
9523 {
9532 {
9537 /* We're not interested in MEMs that are only clobbered. */
9541 /* We're not interested in the MEM associated with a
9542 CONST_DOUBLE, so there's no need to traverse into this. */
9546 /* We're not interested in any MEMs that only appear in notes. */
9550 /* This is not a MEM. */
9552 }
9554 /* See if we've already seen this MEM. */
9557 {
9559 /* The modes of the two memory accesses are different. If
9560 this happens, something tricky is going on, and we just
9561 don't optimize accesses to this MEM. */
9565 }
9567 /* Resize the array, if necessary. */
9569 {
9572 else
9578 }
9580 /* Actually insert the MEM. */
9582 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9583 because we can't put it in a register. We still store it in the
9584 table, though, so that if we see the same address later, but in a
9585 non-BLK mode, we'll not think we can optimize it at that point. */
9591 }
9594 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9596 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9597 register that is modified by an insn between FROM and TO. If the
9598 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9599 more, stop incrementing it, to avoid overflow.
9601 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9602 register I is used, if it is only used once. Otherwise, it is set
9603 to 0 (for no uses) or const0_rtx for more than one use. This
9604 parameter may be zero, in which case this processing is not done.
9606 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9607 optimize register I. */
9609 static void
9613 {
9616 /* last_set[n] is nonzero iff reg n has been set in the current
9617 basic block. In that case, it is the insn that last set reg n. */
9619 rtx insn;
9625 /* Grow the regs array if not allocated or too small. */
9627 {
9633 /* Zero the new elements. */
9636 }
9638 /* Clear previously scanned fields but do not clear n_times_set. */
9640 {
9644 }
9648 /* Scan the loop, recording register usage. */
9651 {
9653 {
9654 /* Record registers that have exactly one use. */
9657 /* Include uses in REG_EQUAL notes. */
9665 {
9669 last_set);
9670 }
9671 }
9675 }
9677 /* Invalidate all hard registers clobbered by calls. With one exception:
9678 a call-clobbered PIC register is still function-invariant for our
9679 purposes, since we can hoist any PIC calculations out of the loop.
9680 Thus the call to rtx_varies_p. */
9685 {
9688 }
9690 #ifdef AVOID_CCMODE_COPIES
9691 /* Don't try to move insns which set CC registers if we should not
9692 create CCmode register copies. */
9696 #endif
9698 /* Set regs->array[I].n_times_set for the new registers. */
9703 }
9705 /* Returns the number of real INSNs in the LOOP. */
9707 static int
9710 {
9712 rtx insn;
9720 }
9722 /* Move MEMs into registers for the duration of the loop. */
9724 static void
9727 {
9734 rtx end_label;
9735 /* Nonzero if the next instruction may never be executed. */
9742 /* We cannot use next_label here because it skips over normal insns. */
9747 /* Check to see if it's possible that some instructions in the loop are
9748 never executed. Also check if there is a goto out of the loop other
9749 than right after the end of the loop. */
9753 {
9757 /* If we enter the loop in the middle, and scan
9758 around to the beginning, don't set maybe_never
9759 for that. This must be an unconditional jump,
9760 otherwise the code at the top of the loop might
9761 never be executed. Unconditional jumps are
9762 followed a by barrier then loop end. */
9767 {
9768 /* If this is a jump outside of the loop but not right
9769 after the end of the loop, we would have to emit new fixup
9770 sequences for each such label. */
9772 JUMP_INSN is executed, we must be conservative. */
9781 /* Something complicated. */
9783 else
9784 /* If there are any more instructions in the loop, they
9785 might not be reached. */
9787 }
9790 }
9792 /* Find start of the extended basic block that enters the loop. */
9796 ;
9801 /* Build table of mems that get set to constant values before the
9802 loop. */
9806 /* Actually move the MEMs. */
9808 {
9809 regset_head load_copies;
9810 regset_head store_copies;
9812 rtx reg;
9814 rtx mem_list_entry;
9818 /* There's no telling whether or not MEM is modified. */
9821 /* Go through the MEMs written to in the loop to see if this
9822 one is aliased by one of them. */
9825 {
9830 {
9831 /* MEM is indeed aliased by this store. */
9834 }
9836 }
9842 /* If this MEM is written to, we must be sure that there
9843 are no reads from another MEM that aliases this one. */
9845 {
9849 {
9853 VOIDmode,
9855 rtx_varies_p))
9856 {
9857 /* It's not safe to hoist loop_info->mems[i] out of
9858 the loop because writes to it might not be
9859 seen by reads from loop_info->mems[j]. */
9862 }
9863 }
9864 }
9867 /* We can't access the MEM outside the loop; it might
9868 cause a trap that wouldn't have happened otherwise. */
9872 /* We thought we were going to lift this MEM out of the
9873 loop, but later discovered that we could not. */
9879 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9880 order to keep scan_loop from moving stores to this MEM
9881 out of the loop just because this REG is neither a
9882 user-variable nor used in the loop test. */
9887 /* Now, replace all references to the MEM with the
9888 corresponding pseudos. */
9893 {
9895 {
9896 rtx set;
9900 /* See if this copies the mem into a register that isn't
9901 modified afterwards. We'll try to do copy propagation
9902 a little further on. */
9904 /* @@@ This test is _way_ too conservative. */
9905 && ! maybe_never
9913 /* See if this copies the mem from a register that isn't
9914 modified afterwards. We'll try to remove the
9915 redundant copy later on by doing a little register
9916 renaming and copy propagation. This will help
9917 to untangle things for the BIV detection code. */
9919 && ! maybe_never
9927 /* If this is a call which uses / clobbers this memory
9928 location, we must not change the interface here. */
9932 {
9936 }
9937 else
9938 /* Replace the memory reference with the shadow register. */
9941 }
9946 }
9951 /* We couldn't replace all occurrences of the MEM. */
9953 else
9954 {
9955 /* Load the memory immediately before LOOP->START, which is
9956 the NOTE_LOOP_BEG. */
9958 rtx set;
9964 {
9968 {
9972 /* Extending hard register lifetimes causes crash
9973 on SRC targets. Doing so on non-SRC is
9974 probably also not good idea, since we most
9975 probably have pseudoregister equivalence as
9976 well. */
9979 }
9980 /* Use the constant equivalence if that is cheap enough. */
9986 {
9989 }
9991 /* If best_equiv is nonzero, we know that MEM is set to a
9992 constant or register before the loop. We will use this
9993 knowledge to initialize the shadow register with that
9994 constant or reg rather than by loading from MEM. */
9997 }
10002 {
10005 {
10008 }
10009 }
10015 {
10017 {
10020 }
10022 /* Store the memory immediately after END, which is
10023 the NOTE_LOOP_END. */
10026 }
10029 {
10034 }
10036 /* Attempt a bit of copy propagation. This helps untangle the
10037 data flow, and enables {basic,general}_induction_var to find
10038 more bivs/givs. */
10039 EXECUTE_IF_SET_IN_REG_SET
10041 {
10043 });
10046 EXECUTE_IF_SET_IN_REG_SET
10048 {
10050 });
10052 }
10053 }
10056 {
10057 /* Now, we need to replace all references to the previous exit
10058 label with the new one. */
10059 rtx_pair rr;
10064 {
10067 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10068 field. This is not handled by for_each_rtx because it doesn't
10069 handle unprinted ('0') fields. We need to update JUMP_LABEL
10070 because the immediately following unroll pass will use it.
10071 replace_label would not work anyways, because that only handles
10072 LABEL_REFs. */
10075 }
10076 }
10079 }
10081 /* For communication between note_reg_stored and its caller. */
10082 struct note_reg_stored_arg
10083 {
10085 rtx reg;
10086 };
10088 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10089 is equal to ARG. */
10090 static void
10094 {
10098 }
10100 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10101 There must be exactly one insn that sets this pseudo; it will be
10102 deleted if all replacements succeed and we can prove that the register
10103 is not used after the loop. */
10105 static void
10108 rtx replacement;
10110 {
10111 /* This is the reg that we are copying from. */
10114 rtx insn;
10115 /* These help keep track of whether we replaced all uses of the reg. */
10122 {
10123 rtx set;
10125 /* Only substitute within one extended basic block from the initializing
10126 insn. */
10133 /* Is this the initializing insn? */
10138 {
10145 }
10147 /* Only substitute after seeing the initializing insn. */
10149 {
10156 /* Stop replacing when REPLACEMENT is modified. */
10161 {
10164 /* It is possible that we've turned previously valid REG_EQUAL to
10165 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10166 REPLACEMENT is modified, we get different meaning. */
10170 }
10171 }
10172 }
10176 {
10180 {
10181 rtx first;
10182 rtx retval_note;
10184 /* Assume we're just deleting INIT_INSN. */
10186 /* Look for REG_RETVAL note. If we're deleting the end of
10187 the libcall sequence, the whole sequence can go. */
10189 /* If we found a REG_RETVAL note, find the first instruction
10190 in the sequence. */
10194 /* Delete the instructions. */
10196 }
10199 }
10200 }
10202 /* Replace all the instructions from FIRST up to and including LAST
10203 with NOTE_INSN_DELETED notes. */
10205 static void
10207 rtx first;
10208 rtx last;
10209 {
10211 {
10217 /* If this was the LAST instructions we're supposed to delete,
10218 we're done. */
10223 }
10224 }
10226 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10227 loop LOOP if the order of the sets of these registers can be
10228 swapped. There must be exactly one insn within the loop that sets
10229 this pseudo followed immediately by a move insn that sets
10230 REPLACEMENT with REGNO. */
10231 static void
10234 rtx replacement;
10236 {
10237 rtx insn;
10246 {
10247 /* Search for the insn that copies REGNO to NEW_REGNO? */
10255 }
10258 {
10259 rtx prev_insn;
10260 rtx prev_set;
10262 /* Some DEF-USE info would come in handy here to make this
10263 function more general. For now, just check the previous insn
10264 which is the most likely candidate for setting REGNO. */
10272 {
10273 /* We have:
10274 (set (reg regno) (expr))
10275 (set (reg new_regno) (reg regno))
10277 so try converting this to:
10278 (set (reg new_regno) (expr))
10279 (set (reg regno) (reg new_regno))
10281 The former construct is often generated when a global
10282 variable used for an induction variable is shadowed by a
10283 register (NEW_REGNO). The latter construct improves the
10284 chances of GIV replacement and BIV elimination. */
10294 {
10301 /* Update first use of REGNO. */
10305 /* Now perform copy propagation to hopefully
10306 remove all uses of REGNO within the loop. */
10308 }
10309 }
10310 }
10311 }
10313 /* Replace MEM with its associated pseudo register. This function is
10314 called from load_mems via for_each_rtx. DATA is actually a pointer
10315 to a structure describing the instruction currently being scanned
10316 and the MEM we are currently replacing. */
10318 static int
10322 {
10330 {
10335 /* We're not interested in the MEM associated with a
10336 CONST_DOUBLE, so there's no need to traverse into one. */
10340 /* This is not a MEM. */
10342 }
10345 /* This is not the MEM we are currently replacing. */
10348 /* Actually replace the MEM. */
10352 }
10354 static void
10356 rtx insn;
10357 rtx mem;
10358 rtx reg;
10359 {
10360 loop_replace_args args;
10367 }
10369 /* Replace one register with another. Called through for_each_rtx; PX points
10370 to the rtx being scanned. DATA is actually a pointer to
10371 a structure of arguments. */
10373 static int
10377 {
10388 }
10390 static void
10392 rtx insn;
10393 rtx reg;
10394 rtx replacement;
10395 {
10396 loop_replace_args args;
10403 }
10405 /* Replace occurrences of the old exit label for the loop with the new
10406 one. DATA is an rtx_pair containing the old and new labels,
10407 respectively. */
10409 static int
10413 {
10432 }
10433 \f
10434 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10435 (ignored in the interim). */
10437 static rtx
10440 basic_block where_bb ATTRIBUTE_UNUSED;
10441 rtx where_insn;
10442 rtx pattern;
10443 {
10445 }
10448 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10449 in basic block WHERE_BB (ignored in the interim) within the loop
10450 otherwise hoist PATTERN into the loop pre-header. */
10452 rtx
10455 basic_block where_bb ATTRIBUTE_UNUSED;
10456 rtx where_insn;
10457 rtx pattern;
10458 {
10462 }
10465 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10466 WHERE_BB (ignored in the interim) within the loop. */
10468 static rtx
10471 basic_block where_bb ATTRIBUTE_UNUSED;
10472 rtx where_insn;
10473 rtx pattern;
10474 {
10476 }
10479 /* Hoist insn for PATTERN into the loop pre-header. */
10481 rtx
10484 rtx pattern;
10485 {
10487 }
10490 /* Hoist call insn for PATTERN into the loop pre-header. */
10492 static rtx
10495 rtx pattern;
10496 {
10498 }
10501 /* Sink insn for PATTERN after the loop end. */
10503 rtx
10506 rtx pattern;
10507 {
10509 }
10511 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10512 and constant. Emit sequence of intructions to load it into REG */
10513 static rtx
10516 {
10517 rtx seq;
10525 }
10527 /* If the loop has multiple exits, emit insn for PATTERN before the
10528 loop to ensure that it will always be executed no matter how the
10529 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10530 since this is slightly more efficient. */
10532 static rtx
10535 rtx pattern;
10536 {
10539 else
10541 }
10542 \f
10543 static void
10548 {
10556 iv_num++;
10561 {
10564 }
10565 }
10568 static void
10573 {
10575 rtx incr;
10586 {
10589 }
10591 {
10594 }
10598 {
10602 }
10605 {
10609 }
10611 /* List the increments. */
10613 {
10617 }
10619 /* List the givs. */
10621 {
10626 else
10629 }
10630 }
10633 static void
10638 {
10649 {
10653 }
10656 }
10659 static void
10664 {
10671 else
10687 {
10689 {
10701 }
10702 }
10713 {
10717 }
10720 }
10723 void
10726 {
10728 }
10731 void
10734 {
10736 }
10739 void
10742 {
10744 }
10747 void
10750 {
10752 }
10755 #define LOOP_BLOCK_NUM_1(INSN) \
10756 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10758 /* The notes do not have an assigned block, so look at the next insn. */
10759 #define LOOP_BLOCK_NUM(INSN) \
10760 ((INSN) ? (GET_CODE (INSN) == NOTE \
10761 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10762 : LOOP_BLOCK_NUM_1 (INSN)) \
10763 : -1)
10765 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10767 static void
10772 {
10773 rtx label;
10778 /* Print diagnostics to compare our concept of a loop with
10779 what the loop notes say. */
10794 {
10814 {
10817 {
10820 }
10821 }
10824 /* This can happen when a marked loop appears as two nested loops,
10825 say from while (a || b) {}. The inner loop won't match
10826 the loop markers but the outer one will. */
10829 }
10830 }
10832 /* Call this function from the debugger to dump LOOP. */
10834 void
10837 {
10839 }
10841 /* Call this function from the debugger to dump LOOPS. */
10843 void
10846 {
10848 }