gcc/ira.h

   1 /* Communication between the Integrated Register Allocator (IRA) and
   2    the rest of the compiler.
   3    Copyright (C) 2006, 2007, 2008, 2009, 2010, 2012
   4    Free Software Foundation, Inc.
   5    Contributed by Vladimir Makarov <vmakarov@redhat.com>.
   6
   7 This file is part of GCC.
   8
   9 GCC is free software; you can redistribute it and/or modify it under
  10 the terms of the GNU General Public License as published by the Free
  11 Software Foundation; either version 3, or (at your option) any later
  12 version.
  13
  14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17 for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with GCC; see the file COPYING3.  If not see
  21 <http://www.gnu.org/licenses/>.  */
  22
  23 /* True when we use LRA instead of reload pass for the current
  24    function.  */
  25 extern bool ira_use_lra_p;
  26
  27 /* True if we have allocno conflicts.  It is false for non-optimized
  28    mode or when the conflict table is too big.  */
  29 extern bool ira_conflicts_p;
  30
  31 struct target_ira
  32 {
  33   /* Map: hard register number -> allocno class it belongs to.  If the
  34      corresponding class is NO_REGS, the hard register is not available
  35      for allocation.  */
  36   enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
  37
  38   /* Number of allocno classes.  Allocno classes are register classes
  39      which can be used for allocations of allocnos.  */
  40   int x_ira_allocno_classes_num;
  41
  42   /* The array containing allocno classes.  Only first
  43      IRA_ALLOCNO_CLASSES_NUM elements are used for this.  */
  44   enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
  45
  46   /* Map of all register classes to corresponding allocno classes
  47      containing the given class.  If given class is not a subset of an
  48      allocno class, we translate it into the cheapest allocno class.  */
  49   enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
  50
  51   /* Number of pressure classes.  Pressure classes are register
  52      classes for which we calculate register pressure.  */
  53   int x_ira_pressure_classes_num;
  54
  55   /* The array containing pressure classes.  Only first
  56      IRA_PRESSURE_CLASSES_NUM elements are used for this.  */
  57   enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
  58
  59   /* Map of all register classes to corresponding pressure classes
  60      containing the given class.  If given class is not a subset of an
  61      pressure class, we translate it into the cheapest pressure
  62      class.  */
  63   enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
  64
  65   /* Bigest pressure register class containing stack registers.
  66      NO_REGS if there are no stack registers.  */
  67   enum reg_class x_ira_stack_reg_pressure_class;
  68
  69   /* Maps: register class x machine mode -> maximal/minimal number of
  70      hard registers of given class needed to store value of given
  71      mode.  */
  72   unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
  73   unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
  74
  75   /* Array analogous to target hook TARGET_MEMORY_MOVE_COST.  */
  76   short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
  77
  78   /* Array of number of hard registers of given class which are
  79      available for the allocation.  The order is defined by the
  80      allocation order.  */
  81   short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
  82
  83   /* The number of elements of the above array for given register
  84      class.  */
  85   int x_ira_class_hard_regs_num[N_REG_CLASSES];
  86
  87   /* Register class subset relation: TRUE if the first class is a subset
  88      of the second one considering only hard registers available for the
  89      allocation.  */
  90   int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
  91
  92   /* The biggest class inside of intersection of the two classes (that
  93      is calculated taking only hard registers available for allocation
  94      into account.  If the both classes contain no hard registers
  95      available for allocation, the value is calculated with taking all
  96      hard-registers including fixed ones into account.  */
  97   enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
  98
  99   /* True if the two classes (that is calculated taking only hard
 100      registers available for allocation into account; are
 101      intersected.  */
 102   bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
 103
 104   /* If class CL has a single allocatable register of mode M,
 105      index [CL][M] gives the number of that register, otherwise it is -1.  */
 106   short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE];
 107
 108   /* Function specific hard registers can not be used for the register
 109      allocation.  */
 110   HARD_REG_SET x_ira_no_alloc_regs;
 111 };
 112
 113 extern struct target_ira default_target_ira;
 114 #if SWITCHABLE_TARGET
 115 extern struct target_ira *this_target_ira;
 116 #else
 117 #define this_target_ira (&default_target_ira)
 118 #endif
 119
 120 #define ira_hard_regno_allocno_class \
 121   (this_target_ira->x_ira_hard_regno_allocno_class)
 122 #define ira_allocno_classes_num \
 123   (this_target_ira->x_ira_allocno_classes_num)
 124 #define ira_allocno_classes \
 125   (this_target_ira->x_ira_allocno_classes)
 126 #define ira_allocno_class_translate \
 127   (this_target_ira->x_ira_allocno_class_translate)
 128 #define ira_pressure_classes_num \
 129   (this_target_ira->x_ira_pressure_classes_num)
 130 #define ira_pressure_classes \
 131   (this_target_ira->x_ira_pressure_classes)
 132 #define ira_pressure_class_translate \
 133   (this_target_ira->x_ira_pressure_class_translate)
 134 #define ira_stack_reg_pressure_class \
 135   (this_target_ira->x_ira_stack_reg_pressure_class)
 136 #define ira_reg_class_max_nregs \
 137   (this_target_ira->x_ira_reg_class_max_nregs)
 138 #define ira_reg_class_min_nregs \
 139   (this_target_ira->x_ira_reg_class_min_nregs)
 140 #define ira_memory_move_cost \
 141   (this_target_ira->x_ira_memory_move_cost)
 142 #define ira_class_hard_regs \
 143   (this_target_ira->x_ira_class_hard_regs)
 144 #define ira_class_hard_regs_num \
 145   (this_target_ira->x_ira_class_hard_regs_num)
 146 #define ira_class_subset_p \
 147   (this_target_ira->x_ira_class_subset_p)
 148 #define ira_reg_class_subset \
 149   (this_target_ira->x_ira_reg_class_subset)
 150 #define ira_reg_classes_intersect_p \
 151   (this_target_ira->x_ira_reg_classes_intersect_p)
 152 #define ira_class_singleton \
 153   (this_target_ira->x_ira_class_singleton)
 154 #define ira_no_alloc_regs \
 155   (this_target_ira->x_ira_no_alloc_regs)
 156
 157 /* Major structure describing equivalence info for a pseudo.  */
 158 struct ira_reg_equiv
 159 {
 160   /* True if we can use this equivalence.  */
 161   bool defined_p;
 162   /* True if the usage of the equivalence is profitable.  */
 163   bool profitable_p;
 164   /* Equiv. memory, constant, invariant, and initializing insns of
 165      given pseudo-register or NULL_RTX.  */
 166   rtx memory;
 167   rtx constant;
 168   rtx invariant;
 169   /* Always NULL_RTX if defined_p is false.  */
 170   rtx init_insns;
 171 };
 172
 173 /* The length of the following array.  */
 174 extern int ira_reg_equiv_len;
 175
 176 /* Info about equiv. info for each register.  */
 177 extern struct ira_reg_equiv *ira_reg_equiv;
 178
 179 extern void ira_init_once (void);
 180 extern void ira_init (void);
 181 extern void ira_finish_once (void);
 182 extern void ira_setup_eliminable_regset (bool);
 183 extern rtx ira_eliminate_regs (rtx, enum machine_mode);
 184 extern void ira_set_pseudo_classes (bool, FILE *);
 185 extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *);
 186 extern void ira_expand_reg_equiv (void);
 187 extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx);
 188
 189 extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *);
 190 extern void ira_mark_allocation_change (int);
 191 extern void ira_mark_memory_move_deletion (int, int);
 192 extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
 193                                   HARD_REG_SET *, bitmap);
 194 extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int);
 195 extern void ira_mark_new_stack_slot (rtx, int, unsigned int);
 196 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx);
 197 extern bool ira_bad_reload_regno (int, rtx, rtx);
 198
 199 extern void ira_adjust_equiv_reg_cost (unsigned, int);