1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
86 #include "double-int.h"
93 #include "stor-layout.h"
97 #include "hard-reg-set.h"
100 #include "dominance.h"
103 #include "cfgcleanup.h"
104 #include "basic-block.h"
105 #include "insn-config.h"
106 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 #include "statistics.h"
110 #include "fixed-value.h"
115 #include "emit-rtl.h"
119 #include "insn-attr.h"
121 #include "diagnostic-core.h"
123 #include "insn-codes.h"
125 #include "rtlhooks-def.h"
127 #include "tree-pass.h"
129 #include "valtrack.h"
130 #include "hash-map.h"
132 #include "plugin-api.h"
136 #include "rtl-iter.h"
138 /* Number of attempts to combine instructions in this function. */
140 static int combine_attempts
;
142 /* Number of attempts that got as far as substitution in this function. */
144 static int combine_merges
;
146 /* Number of instructions combined with added SETs in this function. */
148 static int combine_extras
;
150 /* Number of instructions combined in this function. */
152 static int combine_successes
;
154 /* Totals over entire compilation. */
156 static int total_attempts
, total_merges
, total_extras
, total_successes
;
158 /* combine_instructions may try to replace the right hand side of the
159 second instruction with the value of an associated REG_EQUAL note
160 before throwing it at try_combine. That is problematic when there
161 is a REG_DEAD note for a register used in the old right hand side
162 and can cause distribute_notes to do wrong things. This is the
163 second instruction if it has been so modified, null otherwise. */
165 static rtx_insn
*i2mod
;
167 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
169 static rtx i2mod_old_rhs
;
171 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
173 static rtx i2mod_new_rhs
;
175 typedef struct reg_stat_struct
{
176 /* Record last point of death of (hard or pseudo) register n. */
177 rtx_insn
*last_death
;
179 /* Record last point of modification of (hard or pseudo) register n. */
182 /* The next group of fields allows the recording of the last value assigned
183 to (hard or pseudo) register n. We use this information to see if an
184 operation being processed is redundant given a prior operation performed
185 on the register. For example, an `and' with a constant is redundant if
186 all the zero bits are already known to be turned off.
188 We use an approach similar to that used by cse, but change it in the
191 (1) We do not want to reinitialize at each label.
192 (2) It is useful, but not critical, to know the actual value assigned
193 to a register. Often just its form is helpful.
195 Therefore, we maintain the following fields:
197 last_set_value the last value assigned
198 last_set_label records the value of label_tick when the
199 register was assigned
200 last_set_table_tick records the value of label_tick when a
201 value using the register is assigned
202 last_set_invalid set to nonzero when it is not valid
203 to use the value of this register in some
206 To understand the usage of these tables, it is important to understand
207 the distinction between the value in last_set_value being valid and
208 the register being validly contained in some other expression in the
211 (The next two parameters are out of date).
213 reg_stat[i].last_set_value is valid if it is nonzero, and either
214 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
216 Register I may validly appear in any expression returned for the value
217 of another register if reg_n_sets[i] is 1. It may also appear in the
218 value for register J if reg_stat[j].last_set_invalid is zero, or
219 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
221 If an expression is found in the table containing a register which may
222 not validly appear in an expression, the register is replaced by
223 something that won't match, (clobber (const_int 0)). */
225 /* Record last value assigned to (hard or pseudo) register n. */
229 /* Record the value of label_tick when an expression involving register n
230 is placed in last_set_value. */
232 int last_set_table_tick
;
234 /* Record the value of label_tick when the value for register n is placed in
239 /* These fields are maintained in parallel with last_set_value and are
240 used to store the mode in which the register was last set, the bits
241 that were known to be zero when it was last set, and the number of
242 sign bits copies it was known to have when it was last set. */
244 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
245 char last_set_sign_bit_copies
;
246 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
248 /* Set nonzero if references to register n in expressions should not be
249 used. last_set_invalid is set nonzero when this register is being
250 assigned to and last_set_table_tick == label_tick. */
252 char last_set_invalid
;
254 /* Some registers that are set more than once and used in more than one
255 basic block are nevertheless always set in similar ways. For example,
256 a QImode register may be loaded from memory in two places on a machine
257 where byte loads zero extend.
259 We record in the following fields if a register has some leading bits
260 that are always equal to the sign bit, and what we know about the
261 nonzero bits of a register, specifically which bits are known to be
264 If an entry is zero, it means that we don't know anything special. */
266 unsigned char sign_bit_copies
;
268 unsigned HOST_WIDE_INT nonzero_bits
;
270 /* Record the value of the label_tick when the last truncation
271 happened. The field truncated_to_mode is only valid if
272 truncation_label == label_tick. */
274 int truncation_label
;
276 /* Record the last truncation seen for this register. If truncation
277 is not a nop to this mode we might be able to save an explicit
278 truncation if we know that value already contains a truncated
281 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
285 static vec
<reg_stat_type
> reg_stat
;
287 /* One plus the highest pseudo for which we track REG_N_SETS.
288 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
289 but during combine_split_insns new pseudos can be created. As we don't have
290 updated DF information in that case, it is hard to initialize the array
291 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
292 so instead of growing the arrays, just assume all newly created pseudos
293 during combine might be set multiple times. */
295 static unsigned int reg_n_sets_max
;
297 /* Record the luid of the last insn that invalidated memory
298 (anything that writes memory, and subroutine calls, but not pushes). */
300 static int mem_last_set
;
302 /* Record the luid of the last CALL_INSN
303 so we can tell whether a potential combination crosses any calls. */
305 static int last_call_luid
;
307 /* When `subst' is called, this is the insn that is being modified
308 (by combining in a previous insn). The PATTERN of this insn
309 is still the old pattern partially modified and it should not be
310 looked at, but this may be used to examine the successors of the insn
311 to judge whether a simplification is valid. */
313 static rtx_insn
*subst_insn
;
315 /* This is the lowest LUID that `subst' is currently dealing with.
316 get_last_value will not return a value if the register was set at or
317 after this LUID. If not for this mechanism, we could get confused if
318 I2 or I1 in try_combine were an insn that used the old value of a register
319 to obtain a new value. In that case, we might erroneously get the
320 new value of the register when we wanted the old one. */
322 static int subst_low_luid
;
324 /* This contains any hard registers that are used in newpat; reg_dead_at_p
325 must consider all these registers to be always live. */
327 static HARD_REG_SET newpat_used_regs
;
329 /* This is an insn to which a LOG_LINKS entry has been added. If this
330 insn is the earlier than I2 or I3, combine should rescan starting at
333 static rtx_insn
*added_links_insn
;
335 /* Basic block in which we are performing combines. */
336 static basic_block this_basic_block
;
337 static bool optimize_this_for_speed_p
;
340 /* Length of the currently allocated uid_insn_cost array. */
342 static int max_uid_known
;
344 /* The following array records the insn_rtx_cost for every insn
345 in the instruction stream. */
347 static int *uid_insn_cost
;
349 /* The following array records the LOG_LINKS for every insn in the
350 instruction stream as struct insn_link pointers. */
355 struct insn_link
*next
;
358 static struct insn_link
**uid_log_links
;
360 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
361 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
363 #define FOR_EACH_LOG_LINK(L, INSN) \
364 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
366 /* Links for LOG_LINKS are allocated from this obstack. */
368 static struct obstack insn_link_obstack
;
370 /* Allocate a link. */
372 static inline struct insn_link
*
373 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
376 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
377 sizeof (struct insn_link
));
384 /* Incremented for each basic block. */
386 static int label_tick
;
388 /* Reset to label_tick for each extended basic block in scanning order. */
390 static int label_tick_ebb_start
;
392 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
393 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
395 static machine_mode nonzero_bits_mode
;
397 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
398 be safely used. It is zero while computing them and after combine has
399 completed. This former test prevents propagating values based on
400 previously set values, which can be incorrect if a variable is modified
403 static int nonzero_sign_valid
;
406 /* Record one modification to rtl structure
407 to be undone by storing old_contents into *where. */
409 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
415 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
416 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
419 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
420 num_undo says how many are currently recorded.
422 other_insn is nonzero if we have modified some other insn in the process
423 of working on subst_insn. It must be verified too. */
429 rtx_insn
*other_insn
;
432 static struct undobuf undobuf
;
434 /* Number of times the pseudo being substituted for
435 was found and replaced. */
437 static int n_occurrences
;
439 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
441 unsigned HOST_WIDE_INT
,
442 unsigned HOST_WIDE_INT
*);
443 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
445 unsigned int, unsigned int *);
446 static void do_SUBST (rtx
*, rtx
);
447 static void do_SUBST_INT (int *, int);
448 static void init_reg_last (void);
449 static void setup_incoming_promotions (rtx_insn
*);
450 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
451 static int cant_combine_insn_p (rtx_insn
*);
452 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
453 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
454 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
455 static int contains_muldiv (rtx
);
456 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
458 static void undo_all (void);
459 static void undo_commit (void);
460 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
461 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
462 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
463 static rtx
simplify_if_then_else (rtx
);
464 static rtx
simplify_set (rtx
);
465 static rtx
simplify_logical (rtx
);
466 static rtx
expand_compound_operation (rtx
);
467 static const_rtx
expand_field_assignment (const_rtx
);
468 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
469 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
470 static rtx
extract_left_shift (rtx
, int);
471 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
472 unsigned HOST_WIDE_INT
*);
473 static rtx
canon_reg_for_combine (rtx
, rtx
);
474 static rtx
force_to_mode (rtx
, machine_mode
,
475 unsigned HOST_WIDE_INT
, int);
476 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
477 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
478 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
479 static rtx
make_field_assignment (rtx
);
480 static rtx
apply_distributive_law (rtx
);
481 static rtx
distribute_and_simplify_rtx (rtx
, int);
482 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
483 unsigned HOST_WIDE_INT
);
484 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
485 unsigned HOST_WIDE_INT
);
486 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
487 HOST_WIDE_INT
, machine_mode
, int *);
488 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
489 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
491 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
492 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
493 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
495 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
496 static void update_table_tick (rtx
);
497 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
498 static void check_promoted_subreg (rtx_insn
*, rtx
);
499 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
500 static void record_dead_and_set_regs (rtx_insn
*);
501 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
502 static rtx
get_last_value (const_rtx
);
503 static int use_crosses_set_p (const_rtx
, int);
504 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
505 static int reg_dead_at_p (rtx
, rtx_insn
*);
506 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
507 static int reg_bitfield_target_p (rtx
, rtx
);
508 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
509 static void distribute_links (struct insn_link
*);
510 static void mark_used_regs_combine (rtx
);
511 static void record_promoted_value (rtx_insn
*, rtx
);
512 static bool unmentioned_reg_p (rtx
, rtx
);
513 static void record_truncated_values (rtx
*, void *);
514 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
515 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
518 /* It is not safe to use ordinary gen_lowpart in combine.
519 See comments in gen_lowpart_for_combine. */
520 #undef RTL_HOOKS_GEN_LOWPART
521 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
523 /* Our implementation of gen_lowpart never emits a new pseudo. */
524 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
525 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
527 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
528 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
530 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
531 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
533 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
534 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
536 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
539 /* Convenience wrapper for the canonicalize_comparison target hook.
540 Target hooks cannot use enum rtx_code. */
542 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
543 bool op0_preserve_value
)
545 int code_int
= (int)*code
;
546 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
547 *code
= (enum rtx_code
)code_int
;
550 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
551 PATTERN can not be split. Otherwise, it returns an insn sequence.
552 This is a wrapper around split_insns which ensures that the
553 reg_stat vector is made larger if the splitter creates a new
557 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
562 ret
= safe_as_a
<rtx_insn
*> (split_insns (pattern
, insn
));
563 nregs
= max_reg_num ();
564 if (nregs
> reg_stat
.length ())
565 reg_stat
.safe_grow_cleared (nregs
);
569 /* This is used by find_single_use to locate an rtx in LOC that
570 contains exactly one use of DEST, which is typically either a REG
571 or CC0. It returns a pointer to the innermost rtx expression
572 containing DEST. Appearances of DEST that are being used to
573 totally replace it are not counted. */
576 find_single_use_1 (rtx dest
, rtx
*loc
)
579 enum rtx_code code
= GET_CODE (x
);
595 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
596 of a REG that occupies all of the REG, the insn uses DEST if
597 it is mentioned in the destination or the source. Otherwise, we
598 need just check the source. */
599 if (GET_CODE (SET_DEST (x
)) != CC0
600 && GET_CODE (SET_DEST (x
)) != PC
601 && !REG_P (SET_DEST (x
))
602 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
603 && REG_P (SUBREG_REG (SET_DEST (x
)))
604 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
605 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
606 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
607 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
610 return find_single_use_1 (dest
, &SET_SRC (x
));
614 return find_single_use_1 (dest
, &XEXP (x
, 0));
620 /* If it wasn't one of the common cases above, check each expression and
621 vector of this code. Look for a unique usage of DEST. */
623 fmt
= GET_RTX_FORMAT (code
);
624 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
628 if (dest
== XEXP (x
, i
)
629 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
630 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
633 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
636 result
= this_result
;
637 else if (this_result
)
638 /* Duplicate usage. */
641 else if (fmt
[i
] == 'E')
645 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
647 if (XVECEXP (x
, i
, j
) == dest
649 && REG_P (XVECEXP (x
, i
, j
))
650 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
653 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
656 result
= this_result
;
657 else if (this_result
)
667 /* See if DEST, produced in INSN, is used only a single time in the
668 sequel. If so, return a pointer to the innermost rtx expression in which
671 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
673 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
674 care about REG_DEAD notes or LOG_LINKS.
676 Otherwise, we find the single use by finding an insn that has a
677 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
678 only referenced once in that insn, we know that it must be the first
679 and last insn referencing DEST. */
682 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
687 struct insn_link
*link
;
691 next
= NEXT_INSN (insn
);
693 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
696 result
= find_single_use_1 (dest
, &PATTERN (next
));
705 bb
= BLOCK_FOR_INSN (insn
);
706 for (next
= NEXT_INSN (insn
);
707 next
&& BLOCK_FOR_INSN (next
) == bb
;
708 next
= NEXT_INSN (next
))
709 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
711 FOR_EACH_LOG_LINK (link
, next
)
712 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
717 result
= find_single_use_1 (dest
, &PATTERN (next
));
727 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
728 insn. The substitution can be undone by undo_all. If INTO is already
729 set to NEWVAL, do not record this change. Because computing NEWVAL might
730 also call SUBST, we have to compute it before we put anything into
734 do_SUBST (rtx
*into
, rtx newval
)
739 if (oldval
== newval
)
742 /* We'd like to catch as many invalid transformations here as
743 possible. Unfortunately, there are way too many mode changes
744 that are perfectly valid, so we'd waste too much effort for
745 little gain doing the checks here. Focus on catching invalid
746 transformations involving integer constants. */
747 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
748 && CONST_INT_P (newval
))
750 /* Sanity check that we're replacing oldval with a CONST_INT
751 that is a valid sign-extension for the original mode. */
752 gcc_assert (INTVAL (newval
)
753 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
755 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
756 CONST_INT is not valid, because after the replacement, the
757 original mode would be gone. Unfortunately, we can't tell
758 when do_SUBST is called to replace the operand thereof, so we
759 perform this test on oldval instead, checking whether an
760 invalid replacement took place before we got here. */
761 gcc_assert (!(GET_CODE (oldval
) == SUBREG
762 && CONST_INT_P (SUBREG_REG (oldval
))));
763 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
764 && CONST_INT_P (XEXP (oldval
, 0))));
768 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
770 buf
= XNEW (struct undo
);
772 buf
->kind
= UNDO_RTX
;
774 buf
->old_contents
.r
= oldval
;
777 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
780 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
782 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
783 for the value of a HOST_WIDE_INT value (including CONST_INT) is
787 do_SUBST_INT (int *into
, int newval
)
792 if (oldval
== newval
)
796 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
798 buf
= XNEW (struct undo
);
800 buf
->kind
= UNDO_INT
;
802 buf
->old_contents
.i
= oldval
;
805 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
808 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
810 /* Similar to SUBST, but just substitute the mode. This is used when
811 changing the mode of a pseudo-register, so that any other
812 references to the entry in the regno_reg_rtx array will change as
816 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
819 machine_mode oldval
= GET_MODE (*into
);
821 if (oldval
== newval
)
825 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
827 buf
= XNEW (struct undo
);
829 buf
->kind
= UNDO_MODE
;
831 buf
->old_contents
.m
= oldval
;
832 adjust_reg_mode (*into
, newval
);
834 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
837 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
840 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
843 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
846 struct insn_link
* oldval
= *into
;
848 if (oldval
== newval
)
852 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
854 buf
= XNEW (struct undo
);
856 buf
->kind
= UNDO_LINKS
;
858 buf
->old_contents
.l
= oldval
;
861 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
864 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
867 /* Subroutine of try_combine. Determine whether the replacement patterns
868 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
869 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
870 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
871 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
872 of all the instructions can be estimated and the replacements are more
873 expensive than the original sequence. */
876 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
877 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
879 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
880 int new_i2_cost
, new_i3_cost
;
881 int old_cost
, new_cost
;
883 /* Lookup the original insn_rtx_costs. */
884 i2_cost
= INSN_COST (i2
);
885 i3_cost
= INSN_COST (i3
);
889 i1_cost
= INSN_COST (i1
);
892 i0_cost
= INSN_COST (i0
);
893 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
894 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
898 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
899 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
905 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
906 i1_cost
= i0_cost
= 0;
909 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
911 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
915 /* Calculate the replacement insn_rtx_costs. */
916 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
919 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
920 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
921 ? new_i2_cost
+ new_i3_cost
: 0;
925 new_cost
= new_i3_cost
;
929 if (undobuf
.other_insn
)
931 int old_other_cost
, new_other_cost
;
933 old_other_cost
= INSN_COST (undobuf
.other_insn
);
934 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
935 if (old_other_cost
> 0 && new_other_cost
> 0)
937 old_cost
+= old_other_cost
;
938 new_cost
+= new_other_cost
;
944 /* Disallow this combination if both new_cost and old_cost are greater than
945 zero, and new_cost is greater than old cost. */
946 int reject
= old_cost
> 0 && new_cost
> old_cost
;
950 fprintf (dump_file
, "%s combination of insns ",
951 reject
? "rejecting" : "allowing");
953 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
954 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
955 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
956 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
958 fprintf (dump_file
, "original costs ");
960 fprintf (dump_file
, "%d + ", i0_cost
);
961 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
962 fprintf (dump_file
, "%d + ", i1_cost
);
963 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
966 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
967 new_i2_cost
, new_i3_cost
, new_cost
);
969 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
975 /* Update the uid_insn_cost array with the replacement costs. */
976 INSN_COST (i2
) = new_i2_cost
;
977 INSN_COST (i3
) = new_i3_cost
;
989 /* Delete any insns that copy a register to itself. */
992 delete_noop_moves (void)
994 rtx_insn
*insn
, *next
;
997 FOR_EACH_BB_FN (bb
, cfun
)
999 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
1001 next
= NEXT_INSN (insn
);
1002 if (INSN_P (insn
) && noop_move_p (insn
))
1005 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
1007 delete_insn_and_edges (insn
);
1014 /* Return false if we do not want to (or cannot) combine DEF. */
1016 can_combine_def_p (df_ref def
)
1018 /* Do not consider if it is pre/post modification in MEM. */
1019 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1022 unsigned int regno
= DF_REF_REGNO (def
);
1024 /* Do not combine frame pointer adjustments. */
1025 if ((regno
== FRAME_POINTER_REGNUM
1026 && (!reload_completed
|| frame_pointer_needed
))
1027 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1028 || (regno
== HARD_FRAME_POINTER_REGNUM
1029 && (!reload_completed
|| frame_pointer_needed
))
1031 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1032 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1038 /* Return false if we do not want to (or cannot) combine USE. */
1040 can_combine_use_p (df_ref use
)
1042 /* Do not consider the usage of the stack pointer by function call. */
1043 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1049 /* Fill in log links field for all insns. */
1052 create_log_links (void)
1055 rtx_insn
**next_use
;
1059 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1061 /* Pass through each block from the end, recording the uses of each
1062 register and establishing log links when def is encountered.
1063 Note that we do not clear next_use array in order to save time,
1064 so we have to test whether the use is in the same basic block as def.
1066 There are a few cases below when we do not consider the definition or
1067 usage -- these are taken from original flow.c did. Don't ask me why it is
1068 done this way; I don't know and if it works, I don't want to know. */
1070 FOR_EACH_BB_FN (bb
, cfun
)
1072 FOR_BB_INSNS_REVERSE (bb
, insn
)
1074 if (!NONDEBUG_INSN_P (insn
))
1077 /* Log links are created only once. */
1078 gcc_assert (!LOG_LINKS (insn
));
1080 FOR_EACH_INSN_DEF (def
, insn
)
1082 unsigned int regno
= DF_REF_REGNO (def
);
1085 if (!next_use
[regno
])
1088 if (!can_combine_def_p (def
))
1091 use_insn
= next_use
[regno
];
1092 next_use
[regno
] = NULL
;
1094 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1099 We don't build a LOG_LINK for hard registers contained
1100 in ASM_OPERANDs. If these registers get replaced,
1101 we might wind up changing the semantics of the insn,
1102 even if reload can make what appear to be valid
1103 assignments later. */
1104 if (regno
< FIRST_PSEUDO_REGISTER
1105 && asm_noperands (PATTERN (use_insn
)) >= 0)
1108 /* Don't add duplicate links between instructions. */
1109 struct insn_link
*links
;
1110 FOR_EACH_LOG_LINK (links
, use_insn
)
1111 if (insn
== links
->insn
&& regno
== links
->regno
)
1115 LOG_LINKS (use_insn
)
1116 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1119 FOR_EACH_INSN_USE (use
, insn
)
1120 if (can_combine_use_p (use
))
1121 next_use
[DF_REF_REGNO (use
)] = insn
;
1128 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1129 true if we found a LOG_LINK that proves that A feeds B. This only works
1130 if there are no instructions between A and B which could have a link
1131 depending on A, since in that case we would not record a link for B.
1132 We also check the implicit dependency created by a cc0 setter/user
1136 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1138 struct insn_link
*links
;
1139 FOR_EACH_LOG_LINK (links
, b
)
1140 if (links
->insn
== a
)
1142 if (HAVE_cc0
&& sets_cc0_p (a
))
1147 /* Main entry point for combiner. F is the first insn of the function.
1148 NREGS is the first unused pseudo-reg number.
1150 Return nonzero if the combiner has turned an indirect jump
1151 instruction into a direct jump. */
1153 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1155 rtx_insn
*insn
, *next
;
1159 struct insn_link
*links
, *nextlinks
;
1161 basic_block last_bb
;
1163 int new_direct_jump_p
= 0;
1165 for (first
= f
; first
&& !INSN_P (first
); )
1166 first
= NEXT_INSN (first
);
1170 combine_attempts
= 0;
1173 combine_successes
= 0;
1175 rtl_hooks
= combine_rtl_hooks
;
1177 reg_stat
.safe_grow_cleared (nregs
);
1179 init_recog_no_volatile ();
1181 /* Allocate array for insn info. */
1182 max_uid_known
= get_max_uid ();
1183 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1184 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1185 gcc_obstack_init (&insn_link_obstack
);
1187 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1189 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1190 problems when, for example, we have j <<= 1 in a loop. */
1192 nonzero_sign_valid
= 0;
1193 label_tick
= label_tick_ebb_start
= 1;
1195 /* Scan all SETs and see if we can deduce anything about what
1196 bits are known to be zero for some registers and how many copies
1197 of the sign bit are known to exist for those registers.
1199 Also set any known values so that we can use it while searching
1200 for what bits are known to be set. */
1202 setup_incoming_promotions (first
);
1203 /* Allow the entry block and the first block to fall into the same EBB.
1204 Conceptually the incoming promotions are assigned to the entry block. */
1205 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1207 create_log_links ();
1208 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1210 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1215 if (!single_pred_p (this_basic_block
)
1216 || single_pred (this_basic_block
) != last_bb
)
1217 label_tick_ebb_start
= label_tick
;
1218 last_bb
= this_basic_block
;
1220 FOR_BB_INSNS (this_basic_block
, insn
)
1221 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1227 subst_low_luid
= DF_INSN_LUID (insn
);
1230 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1232 record_dead_and_set_regs (insn
);
1235 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1236 if (REG_NOTE_KIND (links
) == REG_INC
)
1237 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1241 /* Record the current insn_rtx_cost of this instruction. */
1242 if (NONJUMP_INSN_P (insn
))
1243 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1244 optimize_this_for_speed_p
);
1246 fprintf (dump_file
, "insn_cost %d: %d\n",
1247 INSN_UID (insn
), INSN_COST (insn
));
1251 nonzero_sign_valid
= 1;
1253 /* Now scan all the insns in forward order. */
1254 label_tick
= label_tick_ebb_start
= 1;
1256 setup_incoming_promotions (first
);
1257 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1258 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1260 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1262 rtx_insn
*last_combined_insn
= NULL
;
1263 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1268 if (!single_pred_p (this_basic_block
)
1269 || single_pred (this_basic_block
) != last_bb
)
1270 label_tick_ebb_start
= label_tick
;
1271 last_bb
= this_basic_block
;
1273 rtl_profile_for_bb (this_basic_block
);
1274 for (insn
= BB_HEAD (this_basic_block
);
1275 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1276 insn
= next
? next
: NEXT_INSN (insn
))
1279 if (!NONDEBUG_INSN_P (insn
))
1282 while (last_combined_insn
1283 && last_combined_insn
->deleted ())
1284 last_combined_insn
= PREV_INSN (last_combined_insn
);
1285 if (last_combined_insn
== NULL_RTX
1286 || BARRIER_P (last_combined_insn
)
1287 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1288 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1289 last_combined_insn
= insn
;
1291 /* See if we know about function return values before this
1292 insn based upon SUBREG flags. */
1293 check_promoted_subreg (insn
, PATTERN (insn
));
1295 /* See if we can find hardregs and subreg of pseudos in
1296 narrower modes. This could help turning TRUNCATEs
1298 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1300 /* Try this insn with each insn it links back to. */
1302 FOR_EACH_LOG_LINK (links
, insn
)
1303 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1304 NULL
, &new_direct_jump_p
,
1305 last_combined_insn
)) != 0)
1307 statistics_counter_event (cfun
, "two-insn combine", 1);
1311 /* Try each sequence of three linked insns ending with this one. */
1313 if (max_combine
>= 3)
1314 FOR_EACH_LOG_LINK (links
, insn
)
1316 rtx_insn
*link
= links
->insn
;
1318 /* If the linked insn has been replaced by a note, then there
1319 is no point in pursuing this chain any further. */
1323 FOR_EACH_LOG_LINK (nextlinks
, link
)
1324 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1325 NULL
, &new_direct_jump_p
,
1326 last_combined_insn
)) != 0)
1328 statistics_counter_event (cfun
, "three-insn combine", 1);
1334 /* Try to combine a jump insn that uses CC0
1335 with a preceding insn that sets CC0, and maybe with its
1336 logical predecessor as well.
1337 This is how we make decrement-and-branch insns.
1338 We need this special code because data flow connections
1339 via CC0 do not get entered in LOG_LINKS. */
1342 && (prev
= prev_nonnote_insn (insn
)) != 0
1343 && NONJUMP_INSN_P (prev
)
1344 && sets_cc0_p (PATTERN (prev
)))
1346 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1348 last_combined_insn
)) != 0)
1351 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1352 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1353 NULL
, &new_direct_jump_p
,
1354 last_combined_insn
)) != 0)
1358 /* Do the same for an insn that explicitly references CC0. */
1359 if (NONJUMP_INSN_P (insn
)
1360 && (prev
= prev_nonnote_insn (insn
)) != 0
1361 && NONJUMP_INSN_P (prev
)
1362 && sets_cc0_p (PATTERN (prev
))
1363 && GET_CODE (PATTERN (insn
)) == SET
1364 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1366 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1368 last_combined_insn
)) != 0)
1371 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1372 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1373 NULL
, &new_direct_jump_p
,
1374 last_combined_insn
)) != 0)
1378 /* Finally, see if any of the insns that this insn links to
1379 explicitly references CC0. If so, try this insn, that insn,
1380 and its predecessor if it sets CC0. */
1381 FOR_EACH_LOG_LINK (links
, insn
)
1382 if (NONJUMP_INSN_P (links
->insn
)
1383 && GET_CODE (PATTERN (links
->insn
)) == SET
1384 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1385 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1386 && NONJUMP_INSN_P (prev
)
1387 && sets_cc0_p (PATTERN (prev
))
1388 && (next
= try_combine (insn
, links
->insn
,
1389 prev
, NULL
, &new_direct_jump_p
,
1390 last_combined_insn
)) != 0)
1394 /* Try combining an insn with two different insns whose results it
1396 if (max_combine
>= 3)
1397 FOR_EACH_LOG_LINK (links
, insn
)
1398 for (nextlinks
= links
->next
; nextlinks
;
1399 nextlinks
= nextlinks
->next
)
1400 if ((next
= try_combine (insn
, links
->insn
,
1401 nextlinks
->insn
, NULL
,
1403 last_combined_insn
)) != 0)
1406 statistics_counter_event (cfun
, "three-insn combine", 1);
1410 /* Try four-instruction combinations. */
1411 if (max_combine
>= 4)
1412 FOR_EACH_LOG_LINK (links
, insn
)
1414 struct insn_link
*next1
;
1415 rtx_insn
*link
= links
->insn
;
1417 /* If the linked insn has been replaced by a note, then there
1418 is no point in pursuing this chain any further. */
1422 FOR_EACH_LOG_LINK (next1
, link
)
1424 rtx_insn
*link1
= next1
->insn
;
1427 /* I0 -> I1 -> I2 -> I3. */
1428 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1429 if ((next
= try_combine (insn
, link
, link1
,
1432 last_combined_insn
)) != 0)
1434 statistics_counter_event (cfun
, "four-insn combine", 1);
1437 /* I0, I1 -> I2, I2 -> I3. */
1438 for (nextlinks
= next1
->next
; nextlinks
;
1439 nextlinks
= nextlinks
->next
)
1440 if ((next
= try_combine (insn
, link
, link1
,
1443 last_combined_insn
)) != 0)
1445 statistics_counter_event (cfun
, "four-insn combine", 1);
1450 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1452 rtx_insn
*link1
= next1
->insn
;
1455 /* I0 -> I2; I1, I2 -> I3. */
1456 FOR_EACH_LOG_LINK (nextlinks
, link
)
1457 if ((next
= try_combine (insn
, link
, link1
,
1460 last_combined_insn
)) != 0)
1462 statistics_counter_event (cfun
, "four-insn combine", 1);
1465 /* I0 -> I1; I1, I2 -> I3. */
1466 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1467 if ((next
= try_combine (insn
, link
, link1
,
1470 last_combined_insn
)) != 0)
1472 statistics_counter_event (cfun
, "four-insn combine", 1);
1478 /* Try this insn with each REG_EQUAL note it links back to. */
1479 FOR_EACH_LOG_LINK (links
, insn
)
1482 rtx_insn
*temp
= links
->insn
;
1483 if ((set
= single_set (temp
)) != 0
1484 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1485 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1486 /* Avoid using a register that may already been marked
1487 dead by an earlier instruction. */
1488 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1489 && (GET_MODE (note
) == VOIDmode
1490 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1491 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1493 /* Temporarily replace the set's source with the
1494 contents of the REG_EQUAL note. The insn will
1495 be deleted or recognized by try_combine. */
1496 rtx orig
= SET_SRC (set
);
1497 SET_SRC (set
) = note
;
1499 i2mod_old_rhs
= copy_rtx (orig
);
1500 i2mod_new_rhs
= copy_rtx (note
);
1501 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1503 last_combined_insn
);
1507 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1510 SET_SRC (set
) = orig
;
1515 record_dead_and_set_regs (insn
);
1522 default_rtl_profile ();
1524 new_direct_jump_p
|= purge_all_dead_edges ();
1525 delete_noop_moves ();
1528 obstack_free (&insn_link_obstack
, NULL
);
1529 free (uid_log_links
);
1530 free (uid_insn_cost
);
1531 reg_stat
.release ();
1534 struct undo
*undo
, *next
;
1535 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1543 total_attempts
+= combine_attempts
;
1544 total_merges
+= combine_merges
;
1545 total_extras
+= combine_extras
;
1546 total_successes
+= combine_successes
;
1548 nonzero_sign_valid
= 0;
1549 rtl_hooks
= general_rtl_hooks
;
1551 /* Make recognizer allow volatile MEMs again. */
1554 return new_direct_jump_p
;
1557 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1560 init_reg_last (void)
1565 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1566 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1569 /* Set up any promoted values for incoming argument registers. */
1572 setup_incoming_promotions (rtx_insn
*first
)
1575 bool strictly_local
= false;
1577 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1578 arg
= DECL_CHAIN (arg
))
1580 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1582 machine_mode mode1
, mode2
, mode3
, mode4
;
1584 /* Only continue if the incoming argument is in a register. */
1588 /* Determine, if possible, whether all call sites of the current
1589 function lie within the current compilation unit. (This does
1590 take into account the exporting of a function via taking its
1591 address, and so forth.) */
1592 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1594 /* The mode and signedness of the argument before any promotions happen
1595 (equal to the mode of the pseudo holding it at that stage). */
1596 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1597 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1599 /* The mode and signedness of the argument after any source language and
1600 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1601 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1602 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1604 /* The mode and signedness of the argument as it is actually passed,
1605 see assign_parm_setup_reg in function.c. */
1606 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1607 TREE_TYPE (cfun
->decl
), 0);
1609 /* The mode of the register in which the argument is being passed. */
1610 mode4
= GET_MODE (reg
);
1612 /* Eliminate sign extensions in the callee when:
1613 (a) A mode promotion has occurred; */
1616 /* (b) The mode of the register is the same as the mode of
1617 the argument as it is passed; */
1620 /* (c) There's no language level extension; */
1623 /* (c.1) All callers are from the current compilation unit. If that's
1624 the case we don't have to rely on an ABI, we only have to know
1625 what we're generating right now, and we know that we will do the
1626 mode1 to mode2 promotion with the given sign. */
1627 else if (!strictly_local
)
1629 /* (c.2) The combination of the two promotions is useful. This is
1630 true when the signs match, or if the first promotion is unsigned.
1631 In the later case, (sign_extend (zero_extend x)) is the same as
1632 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1638 /* Record that the value was promoted from mode1 to mode3,
1639 so that any sign extension at the head of the current
1640 function may be eliminated. */
1641 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1642 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1643 record_value_for_reg (reg
, first
, x
);
1647 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1648 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1649 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1650 because some machines (maybe most) will actually do the sign-extension and
1651 this is the conservative approach.
1653 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1657 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1659 if (GET_MODE_PRECISION (mode
) < prec
1660 && CONST_INT_P (src
)
1662 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1663 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1669 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1673 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1676 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1677 unsigned HOST_WIDE_INT bits
= 0;
1678 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1679 unsigned int num
= 0;
1682 reg_equal
= XEXP (reg_equal_note
, 0);
1684 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1685 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1687 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1690 /* Don't call nonzero_bits if it cannot change anything. */
1691 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1693 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1694 if (reg_equal
&& bits
)
1695 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1696 rsp
->nonzero_bits
|= bits
;
1699 /* Don't call num_sign_bit_copies if it cannot change anything. */
1700 if (rsp
->sign_bit_copies
!= 1)
1702 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1703 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1705 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1706 if (num
== 0 || numeq
> num
)
1709 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1710 rsp
->sign_bit_copies
= num
;
1714 /* Called via note_stores. If X is a pseudo that is narrower than
1715 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1717 If we are setting only a portion of X and we can't figure out what
1718 portion, assume all bits will be used since we don't know what will
1721 Similarly, set how many bits of X are known to be copies of the sign bit
1722 at all locations in the function. This is the smallest number implied
1726 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1728 rtx_insn
*insn
= (rtx_insn
*) data
;
1731 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1732 /* If this register is undefined at the start of the file, we can't
1733 say what its contents were. */
1734 && ! REGNO_REG_SET_P
1735 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1736 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1738 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1740 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1742 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1743 rsp
->sign_bit_copies
= 1;
1747 /* If this register is being initialized using itself, and the
1748 register is uninitialized in this basic block, and there are
1749 no LOG_LINKS which set the register, then part of the
1750 register is uninitialized. In that case we can't assume
1751 anything about the number of nonzero bits.
1753 ??? We could do better if we checked this in
1754 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1755 could avoid making assumptions about the insn which initially
1756 sets the register, while still using the information in other
1757 insns. We would have to be careful to check every insn
1758 involved in the combination. */
1761 && reg_referenced_p (x
, PATTERN (insn
))
1762 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1765 struct insn_link
*link
;
1767 FOR_EACH_LOG_LINK (link
, insn
)
1768 if (dead_or_set_p (link
->insn
, x
))
1772 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1773 rsp
->sign_bit_copies
= 1;
1778 /* If this is a complex assignment, see if we can convert it into a
1779 simple assignment. */
1780 set
= expand_field_assignment (set
);
1782 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1783 set what we know about X. */
1785 if (SET_DEST (set
) == x
1786 || (paradoxical_subreg_p (SET_DEST (set
))
1787 && SUBREG_REG (SET_DEST (set
)) == x
))
1788 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1791 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1792 rsp
->sign_bit_copies
= 1;
1797 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1798 optionally insns that were previously combined into I3 or that will be
1799 combined into the merger of INSN and I3. The order is PRED, PRED2,
1800 INSN, SUCC, SUCC2, I3.
1802 Return 0 if the combination is not allowed for any reason.
1804 If the combination is allowed, *PDEST will be set to the single
1805 destination of INSN and *PSRC to the single source, and this function
1809 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1810 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1811 rtx
*pdest
, rtx
*psrc
)
1820 bool all_adjacent
= true;
1821 int (*is_volatile_p
) (const_rtx
);
1827 if (next_active_insn (succ2
) != i3
)
1828 all_adjacent
= false;
1829 if (next_active_insn (succ
) != succ2
)
1830 all_adjacent
= false;
1832 else if (next_active_insn (succ
) != i3
)
1833 all_adjacent
= false;
1834 if (next_active_insn (insn
) != succ
)
1835 all_adjacent
= false;
1837 else if (next_active_insn (insn
) != i3
)
1838 all_adjacent
= false;
1840 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1841 or a PARALLEL consisting of such a SET and CLOBBERs.
1843 If INSN has CLOBBER parallel parts, ignore them for our processing.
1844 By definition, these happen during the execution of the insn. When it
1845 is merged with another insn, all bets are off. If they are, in fact,
1846 needed and aren't also supplied in I3, they may be added by
1847 recog_for_combine. Otherwise, it won't match.
1849 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1852 Get the source and destination of INSN. If more than one, can't
1855 if (GET_CODE (PATTERN (insn
)) == SET
)
1856 set
= PATTERN (insn
);
1857 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1858 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1860 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1862 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1864 switch (GET_CODE (elt
))
1866 /* This is important to combine floating point insns
1867 for the SH4 port. */
1869 /* Combining an isolated USE doesn't make sense.
1870 We depend here on combinable_i3pat to reject them. */
1871 /* The code below this loop only verifies that the inputs of
1872 the SET in INSN do not change. We call reg_set_between_p
1873 to verify that the REG in the USE does not change between
1875 If the USE in INSN was for a pseudo register, the matching
1876 insn pattern will likely match any register; combining this
1877 with any other USE would only be safe if we knew that the
1878 used registers have identical values, or if there was
1879 something to tell them apart, e.g. different modes. For
1880 now, we forgo such complicated tests and simply disallow
1881 combining of USES of pseudo registers with any other USE. */
1882 if (REG_P (XEXP (elt
, 0))
1883 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1885 rtx i3pat
= PATTERN (i3
);
1886 int i
= XVECLEN (i3pat
, 0) - 1;
1887 unsigned int regno
= REGNO (XEXP (elt
, 0));
1891 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1893 if (GET_CODE (i3elt
) == USE
1894 && REG_P (XEXP (i3elt
, 0))
1895 && (REGNO (XEXP (i3elt
, 0)) == regno
1896 ? reg_set_between_p (XEXP (elt
, 0),
1897 PREV_INSN (insn
), i3
)
1898 : regno
>= FIRST_PSEUDO_REGISTER
))
1905 /* We can ignore CLOBBERs. */
1910 /* Ignore SETs whose result isn't used but not those that
1911 have side-effects. */
1912 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1913 && insn_nothrow_p (insn
)
1914 && !side_effects_p (elt
))
1917 /* If we have already found a SET, this is a second one and
1918 so we cannot combine with this insn. */
1926 /* Anything else means we can't combine. */
1932 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1933 so don't do anything with it. */
1934 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1943 /* The simplification in expand_field_assignment may call back to
1944 get_last_value, so set safe guard here. */
1945 subst_low_luid
= DF_INSN_LUID (insn
);
1947 set
= expand_field_assignment (set
);
1948 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1950 /* Do not eliminate user-specified register if it is in an
1951 asm input because we may break the register asm usage defined
1952 in GCC manual if allow to do so.
1953 Be aware that this may cover more cases than we expect but this
1954 should be harmless. */
1955 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1956 && extract_asm_operands (PATTERN (i3
)))
1959 /* Don't eliminate a store in the stack pointer. */
1960 if (dest
== stack_pointer_rtx
1961 /* Don't combine with an insn that sets a register to itself if it has
1962 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1963 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1964 /* Can't merge an ASM_OPERANDS. */
1965 || GET_CODE (src
) == ASM_OPERANDS
1966 /* Can't merge a function call. */
1967 || GET_CODE (src
) == CALL
1968 /* Don't eliminate a function call argument. */
1970 && (find_reg_fusage (i3
, USE
, dest
)
1972 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1973 && global_regs
[REGNO (dest
)])))
1974 /* Don't substitute into an incremented register. */
1975 || FIND_REG_INC_NOTE (i3
, dest
)
1976 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1977 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1978 /* Don't substitute into a non-local goto, this confuses CFG. */
1979 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1980 /* Make sure that DEST is not used after SUCC but before I3. */
1983 && (reg_used_between_p (dest
, succ2
, i3
)
1984 || reg_used_between_p (dest
, succ
, succ2
)))
1985 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1986 /* Make sure that the value that is to be substituted for the register
1987 does not use any registers whose values alter in between. However,
1988 If the insns are adjacent, a use can't cross a set even though we
1989 think it might (this can happen for a sequence of insns each setting
1990 the same destination; last_set of that register might point to
1991 a NOTE). If INSN has a REG_EQUIV note, the register is always
1992 equivalent to the memory so the substitution is valid even if there
1993 are intervening stores. Also, don't move a volatile asm or
1994 UNSPEC_VOLATILE across any other insns. */
1997 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1998 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1999 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
2000 || GET_CODE (src
) == UNSPEC_VOLATILE
))
2001 /* Don't combine across a CALL_INSN, because that would possibly
2002 change whether the life span of some REGs crosses calls or not,
2003 and it is a pain to update that information.
2004 Exception: if source is a constant, moving it later can't hurt.
2005 Accept that as a special case. */
2006 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
2009 /* DEST must either be a REG or CC0. */
2012 /* If register alignment is being enforced for multi-word items in all
2013 cases except for parameters, it is possible to have a register copy
2014 insn referencing a hard register that is not allowed to contain the
2015 mode being copied and which would not be valid as an operand of most
2016 insns. Eliminate this problem by not combining with such an insn.
2018 Also, on some machines we don't want to extend the life of a hard
2022 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
2023 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
2024 /* Don't extend the life of a hard register unless it is
2025 user variable (if we have few registers) or it can't
2026 fit into the desired register (meaning something special
2028 Also avoid substituting a return register into I3, because
2029 reload can't handle a conflict with constraints of other
2031 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2032 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2035 else if (GET_CODE (dest
) != CC0
)
2039 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2040 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2041 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2043 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2045 /* If the clobber represents an earlyclobber operand, we must not
2046 substitute an expression containing the clobbered register.
2047 As we do not analyze the constraint strings here, we have to
2048 make the conservative assumption. However, if the register is
2049 a fixed hard reg, the clobber cannot represent any operand;
2050 we leave it up to the machine description to either accept or
2051 reject use-and-clobber patterns. */
2053 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2054 || !fixed_regs
[REGNO (reg
)])
2055 if (reg_overlap_mentioned_p (reg
, src
))
2059 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2060 or not), reject, unless nothing volatile comes between it and I3 */
2062 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2064 /* Make sure neither succ nor succ2 contains a volatile reference. */
2065 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2067 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2069 /* We'll check insns between INSN and I3 below. */
2072 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2073 to be an explicit register variable, and was chosen for a reason. */
2075 if (GET_CODE (src
) == ASM_OPERANDS
2076 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2079 /* If INSN contains volatile references (specifically volatile MEMs),
2080 we cannot combine across any other volatile references.
2081 Even if INSN doesn't contain volatile references, any intervening
2082 volatile insn might affect machine state. */
2084 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2088 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2089 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2092 /* If INSN contains an autoincrement or autodecrement, make sure that
2093 register is not used between there and I3, and not already used in
2094 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2095 Also insist that I3 not be a jump; if it were one
2096 and the incremented register were spilled, we would lose. */
2099 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2100 if (REG_NOTE_KIND (link
) == REG_INC
2102 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2103 || (pred
!= NULL_RTX
2104 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2105 || (pred2
!= NULL_RTX
2106 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2107 || (succ
!= NULL_RTX
2108 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2109 || (succ2
!= NULL_RTX
2110 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2111 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2115 /* Don't combine an insn that follows a CC0-setting insn.
2116 An insn that uses CC0 must not be separated from the one that sets it.
2117 We do, however, allow I2 to follow a CC0-setting insn if that insn
2118 is passed as I1; in that case it will be deleted also.
2119 We also allow combining in this case if all the insns are adjacent
2120 because that would leave the two CC0 insns adjacent as well.
2121 It would be more logical to test whether CC0 occurs inside I1 or I2,
2122 but that would be much slower, and this ought to be equivalent. */
2126 p
= prev_nonnote_insn (insn
);
2127 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2132 /* If we get here, we have passed all the tests and the combination is
2141 /* LOC is the location within I3 that contains its pattern or the component
2142 of a PARALLEL of the pattern. We validate that it is valid for combining.
2144 One problem is if I3 modifies its output, as opposed to replacing it
2145 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2146 doing so would produce an insn that is not equivalent to the original insns.
2150 (set (reg:DI 101) (reg:DI 100))
2151 (set (subreg:SI (reg:DI 101) 0) <foo>)
2153 This is NOT equivalent to:
2155 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2156 (set (reg:DI 101) (reg:DI 100))])
2158 Not only does this modify 100 (in which case it might still be valid
2159 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2161 We can also run into a problem if I2 sets a register that I1
2162 uses and I1 gets directly substituted into I3 (not via I2). In that
2163 case, we would be getting the wrong value of I2DEST into I3, so we
2164 must reject the combination. This case occurs when I2 and I1 both
2165 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2166 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2167 of a SET must prevent combination from occurring. The same situation
2168 can occur for I0, in which case I0_NOT_IN_SRC is set.
2170 Before doing the above check, we first try to expand a field assignment
2171 into a set of logical operations.
2173 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2174 we place a register that is both set and used within I3. If more than one
2175 such register is detected, we fail.
2177 Return 1 if the combination is valid, zero otherwise. */
2180 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2181 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2185 if (GET_CODE (x
) == SET
)
2188 rtx dest
= SET_DEST (set
);
2189 rtx src
= SET_SRC (set
);
2190 rtx inner_dest
= dest
;
2193 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2194 || GET_CODE (inner_dest
) == SUBREG
2195 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2196 inner_dest
= XEXP (inner_dest
, 0);
2198 /* Check for the case where I3 modifies its output, as discussed
2199 above. We don't want to prevent pseudos from being combined
2200 into the address of a MEM, so only prevent the combination if
2201 i1 or i2 set the same MEM. */
2202 if ((inner_dest
!= dest
&&
2203 (!MEM_P (inner_dest
)
2204 || rtx_equal_p (i2dest
, inner_dest
)
2205 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2206 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2207 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2208 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2209 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2211 /* This is the same test done in can_combine_p except we can't test
2212 all_adjacent; we don't have to, since this instruction will stay
2213 in place, thus we are not considering increasing the lifetime of
2216 Also, if this insn sets a function argument, combining it with
2217 something that might need a spill could clobber a previous
2218 function argument; the all_adjacent test in can_combine_p also
2219 checks this; here, we do a more specific test for this case. */
2221 || (REG_P (inner_dest
)
2222 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2223 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2224 GET_MODE (inner_dest
))))
2225 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2226 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2229 /* If DEST is used in I3, it is being killed in this insn, so
2230 record that for later. We have to consider paradoxical
2231 subregs here, since they kill the whole register, but we
2232 ignore partial subregs, STRICT_LOW_PART, etc.
2233 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2234 STACK_POINTER_REGNUM, since these are always considered to be
2235 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2237 if (GET_CODE (subdest
) == SUBREG
2238 && (GET_MODE_SIZE (GET_MODE (subdest
))
2239 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2240 subdest
= SUBREG_REG (subdest
);
2243 && reg_referenced_p (subdest
, PATTERN (i3
))
2244 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2245 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2246 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2248 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2249 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2250 || ! fixed_regs
[REGNO (subdest
)]))
2251 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2253 if (*pi3dest_killed
)
2256 *pi3dest_killed
= subdest
;
2260 else if (GET_CODE (x
) == PARALLEL
)
2264 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2265 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2266 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2273 /* Return 1 if X is an arithmetic expression that contains a multiplication
2274 and division. We don't count multiplications by powers of two here. */
2277 contains_muldiv (rtx x
)
2279 switch (GET_CODE (x
))
2281 case MOD
: case DIV
: case UMOD
: case UDIV
:
2285 return ! (CONST_INT_P (XEXP (x
, 1))
2286 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2289 return contains_muldiv (XEXP (x
, 0))
2290 || contains_muldiv (XEXP (x
, 1));
2293 return contains_muldiv (XEXP (x
, 0));
2299 /* Determine whether INSN can be used in a combination. Return nonzero if
2300 not. This is used in try_combine to detect early some cases where we
2301 can't perform combinations. */
2304 cant_combine_insn_p (rtx_insn
*insn
)
2309 /* If this isn't really an insn, we can't do anything.
2310 This can occur when flow deletes an insn that it has merged into an
2311 auto-increment address. */
2312 if (! INSN_P (insn
))
2315 /* Never combine loads and stores involving hard regs that are likely
2316 to be spilled. The register allocator can usually handle such
2317 reg-reg moves by tying. If we allow the combiner to make
2318 substitutions of likely-spilled regs, reload might die.
2319 As an exception, we allow combinations involving fixed regs; these are
2320 not available to the register allocator so there's no risk involved. */
2322 set
= single_set (insn
);
2325 src
= SET_SRC (set
);
2326 dest
= SET_DEST (set
);
2327 if (GET_CODE (src
) == SUBREG
)
2328 src
= SUBREG_REG (src
);
2329 if (GET_CODE (dest
) == SUBREG
)
2330 dest
= SUBREG_REG (dest
);
2331 if (REG_P (src
) && REG_P (dest
)
2332 && ((HARD_REGISTER_P (src
)
2333 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2334 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2335 || (HARD_REGISTER_P (dest
)
2336 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2337 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2343 struct likely_spilled_retval_info
2345 unsigned regno
, nregs
;
2349 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2350 hard registers that are known to be written to / clobbered in full. */
2352 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2354 struct likely_spilled_retval_info
*const info
=
2355 (struct likely_spilled_retval_info
*) data
;
2356 unsigned regno
, nregs
;
2359 if (!REG_P (XEXP (set
, 0)))
2362 if (regno
>= info
->regno
+ info
->nregs
)
2364 nregs
= REG_NREGS (x
);
2365 if (regno
+ nregs
<= info
->regno
)
2367 new_mask
= (2U << (nregs
- 1)) - 1;
2368 if (regno
< info
->regno
)
2369 new_mask
>>= info
->regno
- regno
;
2371 new_mask
<<= regno
- info
->regno
;
2372 info
->mask
&= ~new_mask
;
2375 /* Return nonzero iff part of the return value is live during INSN, and
2376 it is likely spilled. This can happen when more than one insn is needed
2377 to copy the return value, e.g. when we consider to combine into the
2378 second copy insn for a complex value. */
2381 likely_spilled_retval_p (rtx_insn
*insn
)
2383 rtx_insn
*use
= BB_END (this_basic_block
);
2386 unsigned regno
, nregs
;
2387 /* We assume here that no machine mode needs more than
2388 32 hard registers when the value overlaps with a register
2389 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2391 struct likely_spilled_retval_info info
;
2393 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2395 reg
= XEXP (PATTERN (use
), 0);
2396 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2398 regno
= REGNO (reg
);
2399 nregs
= REG_NREGS (reg
);
2402 mask
= (2U << (nregs
- 1)) - 1;
2404 /* Disregard parts of the return value that are set later. */
2408 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2410 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2413 /* Check if any of the (probably) live return value registers is
2418 if ((mask
& 1 << nregs
)
2419 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2425 /* Adjust INSN after we made a change to its destination.
2427 Changing the destination can invalidate notes that say something about
2428 the results of the insn and a LOG_LINK pointing to the insn. */
2431 adjust_for_new_dest (rtx_insn
*insn
)
2433 /* For notes, be conservative and simply remove them. */
2434 remove_reg_equal_equiv_notes (insn
);
2436 /* The new insn will have a destination that was previously the destination
2437 of an insn just above it. Call distribute_links to make a LOG_LINK from
2438 the next use of that destination. */
2440 rtx set
= single_set (insn
);
2443 rtx reg
= SET_DEST (set
);
2445 while (GET_CODE (reg
) == ZERO_EXTRACT
2446 || GET_CODE (reg
) == STRICT_LOW_PART
2447 || GET_CODE (reg
) == SUBREG
)
2448 reg
= XEXP (reg
, 0);
2449 gcc_assert (REG_P (reg
));
2451 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2453 df_insn_rescan (insn
);
2456 /* Return TRUE if combine can reuse reg X in mode MODE.
2457 ADDED_SETS is nonzero if the original set is still required. */
2459 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2467 /* Allow hard registers if the new mode is legal, and occupies no more
2468 registers than the old mode. */
2469 if (regno
< FIRST_PSEUDO_REGISTER
)
2470 return (HARD_REGNO_MODE_OK (regno
, mode
)
2471 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2473 /* Or a pseudo that is only used once. */
2474 return (regno
< reg_n_sets_max
2475 && REG_N_SETS (regno
) == 1
2477 && !REG_USERVAR_P (x
));
2481 /* Check whether X, the destination of a set, refers to part of
2482 the register specified by REG. */
2485 reg_subword_p (rtx x
, rtx reg
)
2487 /* Check that reg is an integer mode register. */
2488 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2491 if (GET_CODE (x
) == STRICT_LOW_PART
2492 || GET_CODE (x
) == ZERO_EXTRACT
)
2495 return GET_CODE (x
) == SUBREG
2496 && SUBREG_REG (x
) == reg
2497 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2500 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2501 Note that the INSN should be deleted *after* removing dead edges, so
2502 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2503 but not for a (set (pc) (label_ref FOO)). */
2506 update_cfg_for_uncondjump (rtx_insn
*insn
)
2508 basic_block bb
= BLOCK_FOR_INSN (insn
);
2509 gcc_assert (BB_END (bb
) == insn
);
2511 purge_dead_edges (bb
);
2514 if (EDGE_COUNT (bb
->succs
) == 1)
2518 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2520 /* Remove barriers from the footer if there are any. */
2521 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2522 if (BARRIER_P (insn
))
2524 if (PREV_INSN (insn
))
2525 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2527 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2528 if (NEXT_INSN (insn
))
2529 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2531 else if (LABEL_P (insn
))
2536 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2537 by an arbitrary number of CLOBBERs. */
2539 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2541 if (GET_CODE (pat
) != PARALLEL
)
2544 int len
= XVECLEN (pat
, 0);
2549 for (i
= 0; i
< n
; i
++)
2550 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2551 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2553 for ( ; i
< len
; i
++)
2554 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
2561 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2562 CLOBBERs), can be split into individual SETs in that order, without
2563 changing semantics. */
2565 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2567 if (!insn_nothrow_p (insn
))
2570 rtx pat
= PATTERN (insn
);
2573 for (i
= 0; i
< n
; i
++)
2575 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2578 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2580 for (j
= i
+ 1; j
< n
; j
++)
2581 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2589 /* Try to combine the insns I0, I1 and I2 into I3.
2590 Here I0, I1 and I2 appear earlier than I3.
2591 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2594 If we are combining more than two insns and the resulting insn is not
2595 recognized, try splitting it into two insns. If that happens, I2 and I3
2596 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2597 Otherwise, I0, I1 and I2 are pseudo-deleted.
2599 Return 0 if the combination does not work. Then nothing is changed.
2600 If we did the combination, return the insn at which combine should
2603 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2604 new direct jump instruction.
2606 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2607 been I3 passed to an earlier try_combine within the same basic
2611 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2612 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2614 /* New patterns for I3 and I2, respectively. */
2615 rtx newpat
, newi2pat
= 0;
2616 rtvec newpat_vec_with_clobbers
= 0;
2617 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2618 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2620 int added_sets_0
, added_sets_1
, added_sets_2
;
2621 /* Total number of SETs to put into I3. */
2623 /* Nonzero if I2's or I1's body now appears in I3. */
2624 int i2_is_used
= 0, i1_is_used
= 0;
2625 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2626 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2627 /* Contains I3 if the destination of I3 is used in its source, which means
2628 that the old life of I3 is being killed. If that usage is placed into
2629 I2 and not in I3, a REG_DEAD note must be made. */
2630 rtx i3dest_killed
= 0;
2631 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2632 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2633 /* Copy of SET_SRC of I1 and I0, if needed. */
2634 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2635 /* Set if I2DEST was reused as a scratch register. */
2636 bool i2scratch
= false;
2637 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2638 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2639 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2640 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2641 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2642 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2643 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2644 /* Notes that must be added to REG_NOTES in I3 and I2. */
2645 rtx new_i3_notes
, new_i2_notes
;
2646 /* Notes that we substituted I3 into I2 instead of the normal case. */
2647 int i3_subst_into_i2
= 0;
2648 /* Notes that I1, I2 or I3 is a MULT operation. */
2651 int changed_i3_dest
= 0;
2654 rtx_insn
*temp_insn
;
2656 struct insn_link
*link
;
2658 rtx new_other_notes
;
2661 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2663 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2666 /* Only try four-insn combinations when there's high likelihood of
2667 success. Look for simple insns, such as loads of constants or
2668 binary operations involving a constant. */
2676 if (!flag_expensive_optimizations
)
2679 for (i
= 0; i
< 4; i
++)
2681 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2682 rtx set
= single_set (insn
);
2686 src
= SET_SRC (set
);
2687 if (CONSTANT_P (src
))
2692 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2694 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2695 || GET_CODE (src
) == LSHIFTRT
)
2699 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2700 are likely manipulating its value. Ideally we'll be able to combine
2701 all four insns into a bitfield insertion of some kind.
2703 Note the source in I0 might be inside a sign/zero extension and the
2704 memory modes in I0 and I3 might be different. So extract the address
2705 from the destination of I3 and search for it in the source of I0.
2707 In the event that there's a match but the source/dest do not actually
2708 refer to the same memory, the worst that happens is we try some
2709 combinations that we wouldn't have otherwise. */
2710 if ((set0
= single_set (i0
))
2711 /* Ensure the source of SET0 is a MEM, possibly buried inside
2713 && (GET_CODE (SET_SRC (set0
)) == MEM
2714 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2715 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2716 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2717 && (set3
= single_set (i3
))
2718 /* Ensure the destination of SET3 is a MEM. */
2719 && GET_CODE (SET_DEST (set3
)) == MEM
2720 /* Would it be better to extract the base address for the MEM
2721 in SET3 and look for that? I don't have cases where it matters
2722 but I could envision such cases. */
2723 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2726 if (ngood
< 2 && nshift
< 2)
2730 /* Exit early if one of the insns involved can't be used for
2733 || (i1
&& CALL_P (i1
))
2734 || (i0
&& CALL_P (i0
))
2735 || cant_combine_insn_p (i3
)
2736 || cant_combine_insn_p (i2
)
2737 || (i1
&& cant_combine_insn_p (i1
))
2738 || (i0
&& cant_combine_insn_p (i0
))
2739 || likely_spilled_retval_p (i3
))
2743 undobuf
.other_insn
= 0;
2745 /* Reset the hard register usage information. */
2746 CLEAR_HARD_REG_SET (newpat_used_regs
);
2748 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2751 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2752 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2754 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2755 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2757 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2758 INSN_UID (i2
), INSN_UID (i3
));
2761 /* If multiple insns feed into one of I2 or I3, they can be in any
2762 order. To simplify the code below, reorder them in sequence. */
2763 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2764 temp_insn
= i2
, i2
= i0
, i0
= temp_insn
;
2765 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2766 temp_insn
= i1
, i1
= i0
, i0
= temp_insn
;
2767 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2768 temp_insn
= i1
, i1
= i2
, i2
= temp_insn
;
2770 added_links_insn
= 0;
2772 /* First check for one important special case that the code below will
2773 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2774 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2775 we may be able to replace that destination with the destination of I3.
2776 This occurs in the common code where we compute both a quotient and
2777 remainder into a structure, in which case we want to do the computation
2778 directly into the structure to avoid register-register copies.
2780 Note that this case handles both multiple sets in I2 and also cases
2781 where I2 has a number of CLOBBERs inside the PARALLEL.
2783 We make very conservative checks below and only try to handle the
2784 most common cases of this. For example, we only handle the case
2785 where I2 and I3 are adjacent to avoid making difficult register
2788 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2789 && REG_P (SET_SRC (PATTERN (i3
)))
2790 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2791 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2792 && GET_CODE (PATTERN (i2
)) == PARALLEL
2793 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2794 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2795 below would need to check what is inside (and reg_overlap_mentioned_p
2796 doesn't support those codes anyway). Don't allow those destinations;
2797 the resulting insn isn't likely to be recognized anyway. */
2798 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2799 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2800 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2801 SET_DEST (PATTERN (i3
)))
2802 && next_active_insn (i2
) == i3
)
2804 rtx p2
= PATTERN (i2
);
2806 /* Make sure that the destination of I3,
2807 which we are going to substitute into one output of I2,
2808 is not used within another output of I2. We must avoid making this:
2809 (parallel [(set (mem (reg 69)) ...)
2810 (set (reg 69) ...)])
2811 which is not well-defined as to order of actions.
2812 (Besides, reload can't handle output reloads for this.)
2814 The problem can also happen if the dest of I3 is a memory ref,
2815 if another dest in I2 is an indirect memory ref. */
2816 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2817 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2818 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2819 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2820 SET_DEST (XVECEXP (p2
, 0, i
))))
2823 /* Make sure this PARALLEL is not an asm. We do not allow combining
2824 that usually (see can_combine_p), so do not here either. */
2825 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2826 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2827 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2830 if (i
== XVECLEN (p2
, 0))
2831 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2832 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2833 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2838 subst_low_luid
= DF_INSN_LUID (i2
);
2840 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2841 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2842 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2843 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2845 /* Replace the dest in I2 with our dest and make the resulting
2846 insn the new pattern for I3. Then skip to where we validate
2847 the pattern. Everything was set up above. */
2848 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2850 i3_subst_into_i2
= 1;
2851 goto validate_replacement
;
2855 /* If I2 is setting a pseudo to a constant and I3 is setting some
2856 sub-part of it to another constant, merge them by making a new
2859 && (temp_expr
= single_set (i2
)) != 0
2860 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2861 && GET_CODE (PATTERN (i3
)) == SET
2862 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2863 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2865 rtx dest
= SET_DEST (PATTERN (i3
));
2869 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2871 if (CONST_INT_P (XEXP (dest
, 1))
2872 && CONST_INT_P (XEXP (dest
, 2)))
2874 width
= INTVAL (XEXP (dest
, 1));
2875 offset
= INTVAL (XEXP (dest
, 2));
2876 dest
= XEXP (dest
, 0);
2877 if (BITS_BIG_ENDIAN
)
2878 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2883 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2884 dest
= XEXP (dest
, 0);
2885 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2891 /* If this is the low part, we're done. */
2892 if (subreg_lowpart_p (dest
))
2894 /* Handle the case where inner is twice the size of outer. */
2895 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2896 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2897 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2898 /* Otherwise give up for now. */
2905 rtx inner
= SET_SRC (PATTERN (i3
));
2906 rtx outer
= SET_SRC (temp_expr
);
2909 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2910 std::make_pair (inner
, GET_MODE (dest
)),
2915 subst_low_luid
= DF_INSN_LUID (i2
);
2916 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2917 i2dest
= SET_DEST (temp_expr
);
2918 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2920 /* Replace the source in I2 with the new constant and make the
2921 resulting insn the new pattern for I3. Then skip to where we
2922 validate the pattern. Everything was set up above. */
2923 SUBST (SET_SRC (temp_expr
),
2924 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2926 newpat
= PATTERN (i2
);
2928 /* The dest of I3 has been replaced with the dest of I2. */
2929 changed_i3_dest
= 1;
2930 goto validate_replacement
;
2935 /* If we have no I1 and I2 looks like:
2936 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2938 make up a dummy I1 that is
2941 (set (reg:CC X) (compare:CC Y (const_int 0)))
2943 (We can ignore any trailing CLOBBERs.)
2945 This undoes a previous combination and allows us to match a branch-and-
2949 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2950 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2952 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2953 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2954 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2955 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2956 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2957 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2959 /* We make I1 with the same INSN_UID as I2. This gives it
2960 the same DF_INSN_LUID for value tracking. Our fake I1 will
2961 never appear in the insn stream so giving it the same INSN_UID
2962 as I2 will not cause a problem. */
2964 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2965 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2967 INSN_UID (i1
) = INSN_UID (i2
);
2969 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2970 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2971 SET_DEST (PATTERN (i1
)));
2972 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2973 SUBST_LINK (LOG_LINKS (i2
),
2974 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2977 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2978 make those two SETs separate I1 and I2 insns, and make an I0 that is
2981 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2982 && can_split_parallel_of_n_reg_sets (i2
, 2)
2983 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2984 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2986 /* If there is no I1, there is no I0 either. */
2989 /* We make I1 with the same INSN_UID as I2. This gives it
2990 the same DF_INSN_LUID for value tracking. Our fake I1 will
2991 never appear in the insn stream so giving it the same INSN_UID
2992 as I2 will not cause a problem. */
2994 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2995 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2997 INSN_UID (i1
) = INSN_UID (i2
);
2999 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
3003 /* Verify that I2 and I1 are valid for combining. */
3004 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
3005 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
3007 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
3014 /* Record whether I2DEST is used in I2SRC and similarly for the other
3015 cases. Knowing this will help in register status updating below. */
3016 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
3017 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
3018 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
3019 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
3020 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
3021 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
3022 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
3023 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
3024 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3026 /* For the earlier insns, determine which of the subsequent ones they
3028 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3029 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3030 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3031 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3032 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3034 /* Ensure that I3's pattern can be the destination of combines. */
3035 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3036 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3037 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3038 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3045 /* See if any of the insns is a MULT operation. Unless one is, we will
3046 reject a combination that is, since it must be slower. Be conservative
3048 if (GET_CODE (i2src
) == MULT
3049 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3050 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3051 || (GET_CODE (PATTERN (i3
)) == SET
3052 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3055 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3056 We used to do this EXCEPT in one case: I3 has a post-inc in an
3057 output operand. However, that exception can give rise to insns like
3059 which is a famous insn on the PDP-11 where the value of r3 used as the
3060 source was model-dependent. Avoid this sort of thing. */
3063 if (!(GET_CODE (PATTERN (i3
)) == SET
3064 && REG_P (SET_SRC (PATTERN (i3
)))
3065 && MEM_P (SET_DEST (PATTERN (i3
)))
3066 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3067 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3068 /* It's not the exception. */
3073 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3074 if (REG_NOTE_KIND (link
) == REG_INC
3075 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3077 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3085 /* See if the SETs in I1 or I2 need to be kept around in the merged
3086 instruction: whenever the value set there is still needed past I3.
3087 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3089 For the SET in I1, we have two cases: if I1 and I2 independently feed
3090 into I3, the set in I1 needs to be kept around unless I1DEST dies
3091 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3092 in I1 needs to be kept around unless I1DEST dies or is set in either
3093 I2 or I3. The same considerations apply to I0. */
3095 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3098 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3099 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3104 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3105 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3106 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3107 && dead_or_set_p (i2
, i0dest
)));
3111 /* We are about to copy insns for the case where they need to be kept
3112 around. Check that they can be copied in the merged instruction. */
3114 if (targetm
.cannot_copy_insn_p
3115 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3116 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3117 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3123 /* If the set in I2 needs to be kept around, we must make a copy of
3124 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3125 PATTERN (I2), we are only substituting for the original I1DEST, not into
3126 an already-substituted copy. This also prevents making self-referential
3127 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3132 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3133 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3135 i2pat
= copy_rtx (PATTERN (i2
));
3140 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3141 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3143 i1pat
= copy_rtx (PATTERN (i1
));
3148 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3149 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3151 i0pat
= copy_rtx (PATTERN (i0
));
3156 /* Substitute in the latest insn for the regs set by the earlier ones. */
3158 maxreg
= max_reg_num ();
3162 /* Many machines that don't use CC0 have insns that can both perform an
3163 arithmetic operation and set the condition code. These operations will
3164 be represented as a PARALLEL with the first element of the vector
3165 being a COMPARE of an arithmetic operation with the constant zero.
3166 The second element of the vector will set some pseudo to the result
3167 of the same arithmetic operation. If we simplify the COMPARE, we won't
3168 match such a pattern and so will generate an extra insn. Here we test
3169 for this case, where both the comparison and the operation result are
3170 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3171 I2SRC. Later we will make the PARALLEL that contains I2. */
3173 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3174 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3175 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3176 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3179 rtx
*cc_use_loc
= NULL
;
3180 rtx_insn
*cc_use_insn
= NULL
;
3181 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3182 machine_mode compare_mode
, orig_compare_mode
;
3183 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3185 newpat
= PATTERN (i3
);
3186 newpat_dest
= SET_DEST (newpat
);
3187 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3189 if (undobuf
.other_insn
== 0
3190 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3193 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3194 compare_code
= simplify_compare_const (compare_code
,
3195 GET_MODE (i2dest
), op0
, &op1
);
3196 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3199 /* Do the rest only if op1 is const0_rtx, which may be the
3200 result of simplification. */
3201 if (op1
== const0_rtx
)
3203 /* If a single use of the CC is found, prepare to modify it
3204 when SELECT_CC_MODE returns a new CC-class mode, or when
3205 the above simplify_compare_const() returned a new comparison
3206 operator. undobuf.other_insn is assigned the CC use insn
3207 when modifying it. */
3210 #ifdef SELECT_CC_MODE
3211 machine_mode new_mode
3212 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3213 if (new_mode
!= orig_compare_mode
3214 && can_change_dest_mode (SET_DEST (newpat
),
3215 added_sets_2
, new_mode
))
3217 unsigned int regno
= REGNO (newpat_dest
);
3218 compare_mode
= new_mode
;
3219 if (regno
< FIRST_PSEUDO_REGISTER
)
3220 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3223 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3224 newpat_dest
= regno_reg_rtx
[regno
];
3228 /* Cases for modifying the CC-using comparison. */
3229 if (compare_code
!= orig_compare_code
3230 /* ??? Do we need to verify the zero rtx? */
3231 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3233 /* Replace cc_use_loc with entire new RTX. */
3235 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3236 newpat_dest
, const0_rtx
));
3237 undobuf
.other_insn
= cc_use_insn
;
3239 else if (compare_mode
!= orig_compare_mode
)
3241 /* Just replace the CC reg with a new mode. */
3242 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3243 undobuf
.other_insn
= cc_use_insn
;
3247 /* Now we modify the current newpat:
3248 First, SET_DEST(newpat) is updated if the CC mode has been
3249 altered. For targets without SELECT_CC_MODE, this should be
3251 if (compare_mode
!= orig_compare_mode
)
3252 SUBST (SET_DEST (newpat
), newpat_dest
);
3253 /* This is always done to propagate i2src into newpat. */
3254 SUBST (SET_SRC (newpat
),
3255 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3256 /* Create new version of i2pat if needed; the below PARALLEL
3257 creation needs this to work correctly. */
3258 if (! rtx_equal_p (i2src
, op0
))
3259 i2pat
= gen_rtx_SET (i2dest
, op0
);
3264 if (i2_is_used
== 0)
3266 /* It is possible that the source of I2 or I1 may be performing
3267 an unneeded operation, such as a ZERO_EXTEND of something
3268 that is known to have the high part zero. Handle that case
3269 by letting subst look at the inner insns.
3271 Another way to do this would be to have a function that tries
3272 to simplify a single insn instead of merging two or more
3273 insns. We don't do this because of the potential of infinite
3274 loops and because of the potential extra memory required.
3275 However, doing it the way we are is a bit of a kludge and
3276 doesn't catch all cases.
3278 But only do this if -fexpensive-optimizations since it slows
3279 things down and doesn't usually win.
3281 This is not done in the COMPARE case above because the
3282 unmodified I2PAT is used in the PARALLEL and so a pattern
3283 with a modified I2SRC would not match. */
3285 if (flag_expensive_optimizations
)
3287 /* Pass pc_rtx so no substitutions are done, just
3291 subst_low_luid
= DF_INSN_LUID (i1
);
3292 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3295 subst_low_luid
= DF_INSN_LUID (i2
);
3296 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3299 n_occurrences
= 0; /* `subst' counts here */
3300 subst_low_luid
= DF_INSN_LUID (i2
);
3302 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3303 copy of I2SRC each time we substitute it, in order to avoid creating
3304 self-referential RTL when we will be substituting I1SRC for I1DEST
3305 later. Likewise if I0 feeds into I2, either directly or indirectly
3306 through I1, and I0DEST is in I0SRC. */
3307 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3308 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3309 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3310 && i0dest_in_i0src
));
3313 /* Record whether I2's body now appears within I3's body. */
3314 i2_is_used
= n_occurrences
;
3317 /* If we already got a failure, don't try to do more. Otherwise, try to
3318 substitute I1 if we have it. */
3320 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3322 /* Check that an autoincrement side-effect on I1 has not been lost.
3323 This happens if I1DEST is mentioned in I2 and dies there, and
3324 has disappeared from the new pattern. */
3325 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3327 && dead_or_set_p (i2
, i1dest
)
3328 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3329 /* Before we can do this substitution, we must redo the test done
3330 above (see detailed comments there) that ensures I1DEST isn't
3331 mentioned in any SETs in NEWPAT that are field assignments. */
3332 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3340 subst_low_luid
= DF_INSN_LUID (i1
);
3342 /* If the following substitution will modify I1SRC, make a copy of it
3343 for the case where it is substituted for I1DEST in I2PAT later. */
3344 if (added_sets_2
&& i1_feeds_i2_n
)
3345 i1src_copy
= copy_rtx (i1src
);
3347 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3348 copy of I1SRC each time we substitute it, in order to avoid creating
3349 self-referential RTL when we will be substituting I0SRC for I0DEST
3351 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3352 i0_feeds_i1_n
&& i0dest_in_i0src
);
3355 /* Record whether I1's body now appears within I3's body. */
3356 i1_is_used
= n_occurrences
;
3359 /* Likewise for I0 if we have it. */
3361 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3363 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3364 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3365 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3366 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3367 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3374 /* If the following substitution will modify I0SRC, make a copy of it
3375 for the case where it is substituted for I0DEST in I1PAT later. */
3376 if (added_sets_1
&& i0_feeds_i1_n
)
3377 i0src_copy
= copy_rtx (i0src
);
3378 /* And a copy for I0DEST in I2PAT substitution. */
3379 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3380 || (i0_feeds_i2_n
)))
3381 i0src_copy2
= copy_rtx (i0src
);
3384 subst_low_luid
= DF_INSN_LUID (i0
);
3385 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3389 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3390 to count all the ways that I2SRC and I1SRC can be used. */
3391 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3392 && i2_is_used
+ added_sets_2
> 1)
3393 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3394 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3396 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3397 && (n_occurrences
+ added_sets_0
3398 + (added_sets_1
&& i0_feeds_i1_n
)
3399 + (added_sets_2
&& i0_feeds_i2_n
)
3401 /* Fail if we tried to make a new register. */
3402 || max_reg_num () != maxreg
3403 /* Fail if we couldn't do something and have a CLOBBER. */
3404 || GET_CODE (newpat
) == CLOBBER
3405 /* Fail if this new pattern is a MULT and we didn't have one before
3406 at the outer level. */
3407 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3414 /* If the actions of the earlier insns must be kept
3415 in addition to substituting them into the latest one,
3416 we must make a new PARALLEL for the latest insn
3417 to hold additional the SETs. */
3419 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3421 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3424 if (GET_CODE (newpat
) == PARALLEL
)
3426 rtvec old
= XVEC (newpat
, 0);
3427 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3428 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3429 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3430 sizeof (old
->elem
[0]) * old
->num_elem
);
3435 total_sets
= 1 + extra_sets
;
3436 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3437 XVECEXP (newpat
, 0, 0) = old
;
3441 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3447 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3449 XVECEXP (newpat
, 0, --total_sets
) = t
;
3455 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3456 i0_feeds_i1_n
&& i0dest_in_i0src
);
3457 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3458 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3460 XVECEXP (newpat
, 0, --total_sets
) = t
;
3464 validate_replacement
:
3466 /* Note which hard regs this insn has as inputs. */
3467 mark_used_regs_combine (newpat
);
3469 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3470 consider splitting this pattern, we might need these clobbers. */
3471 if (i1
&& GET_CODE (newpat
) == PARALLEL
3472 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3474 int len
= XVECLEN (newpat
, 0);
3476 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3477 for (i
= 0; i
< len
; i
++)
3478 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3481 /* We have recognized nothing yet. */
3482 insn_code_number
= -1;
3484 /* See if this is a PARALLEL of two SETs where one SET's destination is
3485 a register that is unused and this isn't marked as an instruction that
3486 might trap in an EH region. In that case, we just need the other SET.
3487 We prefer this over the PARALLEL.
3489 This can occur when simplifying a divmod insn. We *must* test for this
3490 case here because the code below that splits two independent SETs doesn't
3491 handle this case correctly when it updates the register status.
3493 It's pointless doing this if we originally had two sets, one from
3494 i3, and one from i2. Combining then splitting the parallel results
3495 in the original i2 again plus an invalid insn (which we delete).
3496 The net effect is only to move instructions around, which makes
3497 debug info less accurate. */
3499 if (!(added_sets_2
&& i1
== 0)
3500 && is_parallel_of_n_reg_sets (newpat
, 2)
3501 && asm_noperands (newpat
) < 0)
3503 rtx set0
= XVECEXP (newpat
, 0, 0);
3504 rtx set1
= XVECEXP (newpat
, 0, 1);
3505 rtx oldpat
= newpat
;
3507 if (((REG_P (SET_DEST (set1
))
3508 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3509 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3510 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3511 && insn_nothrow_p (i3
)
3512 && !side_effects_p (SET_SRC (set1
)))
3515 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3518 else if (((REG_P (SET_DEST (set0
))
3519 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3520 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3521 && find_reg_note (i3
, REG_UNUSED
,
3522 SUBREG_REG (SET_DEST (set0
)))))
3523 && insn_nothrow_p (i3
)
3524 && !side_effects_p (SET_SRC (set0
)))
3527 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3529 if (insn_code_number
>= 0)
3530 changed_i3_dest
= 1;
3533 if (insn_code_number
< 0)
3537 /* Is the result of combination a valid instruction? */
3538 if (insn_code_number
< 0)
3539 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3541 /* If we were combining three insns and the result is a simple SET
3542 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3543 insns. There are two ways to do this. It can be split using a
3544 machine-specific method (like when you have an addition of a large
3545 constant) or by combine in the function find_split_point. */
3547 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3548 && asm_noperands (newpat
) < 0)
3550 rtx parallel
, *split
;
3551 rtx_insn
*m_split_insn
;
3553 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3554 use I2DEST as a scratch register will help. In the latter case,
3555 convert I2DEST to the mode of the source of NEWPAT if we can. */
3557 m_split_insn
= combine_split_insns (newpat
, i3
);
3559 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3560 inputs of NEWPAT. */
3562 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3563 possible to try that as a scratch reg. This would require adding
3564 more code to make it work though. */
3566 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3568 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3570 /* First try to split using the original register as a
3571 scratch register. */
3572 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3573 gen_rtvec (2, newpat
,
3574 gen_rtx_CLOBBER (VOIDmode
,
3576 m_split_insn
= combine_split_insns (parallel
, i3
);
3578 /* If that didn't work, try changing the mode of I2DEST if
3580 if (m_split_insn
== 0
3581 && new_mode
!= GET_MODE (i2dest
)
3582 && new_mode
!= VOIDmode
3583 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3585 machine_mode old_mode
= GET_MODE (i2dest
);
3588 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3589 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3592 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3593 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3596 parallel
= (gen_rtx_PARALLEL
3598 gen_rtvec (2, newpat
,
3599 gen_rtx_CLOBBER (VOIDmode
,
3601 m_split_insn
= combine_split_insns (parallel
, i3
);
3603 if (m_split_insn
== 0
3604 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3608 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3609 buf
= undobuf
.undos
;
3610 undobuf
.undos
= buf
->next
;
3611 buf
->next
= undobuf
.frees
;
3612 undobuf
.frees
= buf
;
3616 i2scratch
= m_split_insn
!= 0;
3619 /* If recog_for_combine has discarded clobbers, try to use them
3620 again for the split. */
3621 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3623 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3624 m_split_insn
= combine_split_insns (parallel
, i3
);
3627 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3629 rtx m_split_pat
= PATTERN (m_split_insn
);
3630 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3631 if (insn_code_number
>= 0)
3632 newpat
= m_split_pat
;
3634 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3635 && (next_nonnote_nondebug_insn (i2
) == i3
3636 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3639 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3640 newi2pat
= PATTERN (m_split_insn
);
3642 i3set
= single_set (NEXT_INSN (m_split_insn
));
3643 i2set
= single_set (m_split_insn
);
3645 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3647 /* If I2 or I3 has multiple SETs, we won't know how to track
3648 register status, so don't use these insns. If I2's destination
3649 is used between I2 and I3, we also can't use these insns. */
3651 if (i2_code_number
>= 0 && i2set
&& i3set
3652 && (next_nonnote_nondebug_insn (i2
) == i3
3653 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3654 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3656 if (insn_code_number
>= 0)
3659 /* It is possible that both insns now set the destination of I3.
3660 If so, we must show an extra use of it. */
3662 if (insn_code_number
>= 0)
3664 rtx new_i3_dest
= SET_DEST (i3set
);
3665 rtx new_i2_dest
= SET_DEST (i2set
);
3667 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3668 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3669 || GET_CODE (new_i3_dest
) == SUBREG
)
3670 new_i3_dest
= XEXP (new_i3_dest
, 0);
3672 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3673 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3674 || GET_CODE (new_i2_dest
) == SUBREG
)
3675 new_i2_dest
= XEXP (new_i2_dest
, 0);
3677 if (REG_P (new_i3_dest
)
3678 && REG_P (new_i2_dest
)
3679 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3680 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3681 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3685 /* If we can split it and use I2DEST, go ahead and see if that
3686 helps things be recognized. Verify that none of the registers
3687 are set between I2 and I3. */
3688 if (insn_code_number
< 0
3689 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3690 && (!HAVE_cc0
|| REG_P (i2dest
))
3691 /* We need I2DEST in the proper mode. If it is a hard register
3692 or the only use of a pseudo, we can change its mode.
3693 Make sure we don't change a hard register to have a mode that
3694 isn't valid for it, or change the number of registers. */
3695 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3696 || GET_MODE (*split
) == VOIDmode
3697 || can_change_dest_mode (i2dest
, added_sets_2
,
3699 && (next_nonnote_nondebug_insn (i2
) == i3
3700 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3701 /* We can't overwrite I2DEST if its value is still used by
3703 && ! reg_referenced_p (i2dest
, newpat
))
3705 rtx newdest
= i2dest
;
3706 enum rtx_code split_code
= GET_CODE (*split
);
3707 machine_mode split_mode
= GET_MODE (*split
);
3708 bool subst_done
= false;
3709 newi2pat
= NULL_RTX
;
3713 /* *SPLIT may be part of I2SRC, so make sure we have the
3714 original expression around for later debug processing.
3715 We should not need I2SRC any more in other cases. */
3716 if (MAY_HAVE_DEBUG_INSNS
)
3717 i2src
= copy_rtx (i2src
);
3721 /* Get NEWDEST as a register in the proper mode. We have already
3722 validated that we can do this. */
3723 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3725 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3726 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3729 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3730 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3734 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3735 an ASHIFT. This can occur if it was inside a PLUS and hence
3736 appeared to be a memory address. This is a kludge. */
3737 if (split_code
== MULT
3738 && CONST_INT_P (XEXP (*split
, 1))
3739 && INTVAL (XEXP (*split
, 1)) > 0
3740 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3742 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3743 XEXP (*split
, 0), GEN_INT (i
)));
3744 /* Update split_code because we may not have a multiply
3746 split_code
= GET_CODE (*split
);
3749 /* Similarly for (plus (mult FOO (const_int pow2))). */
3750 if (split_code
== PLUS
3751 && GET_CODE (XEXP (*split
, 0)) == MULT
3752 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3753 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3754 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3756 rtx nsplit
= XEXP (*split
, 0);
3757 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3758 XEXP (nsplit
, 0), GEN_INT (i
)));
3759 /* Update split_code because we may not have a multiply
3761 split_code
= GET_CODE (*split
);
3764 #ifdef INSN_SCHEDULING
3765 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3766 be written as a ZERO_EXTEND. */
3767 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3769 #ifdef LOAD_EXTEND_OP
3770 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3771 what it really is. */
3772 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3774 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3775 SUBREG_REG (*split
)));
3778 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3779 SUBREG_REG (*split
)));
3783 /* Attempt to split binary operators using arithmetic identities. */
3784 if (BINARY_P (SET_SRC (newpat
))
3785 && split_mode
== GET_MODE (SET_SRC (newpat
))
3786 && ! side_effects_p (SET_SRC (newpat
)))
3788 rtx setsrc
= SET_SRC (newpat
);
3789 machine_mode mode
= GET_MODE (setsrc
);
3790 enum rtx_code code
= GET_CODE (setsrc
);
3791 rtx src_op0
= XEXP (setsrc
, 0);
3792 rtx src_op1
= XEXP (setsrc
, 1);
3794 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3795 if (rtx_equal_p (src_op0
, src_op1
))
3797 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3798 SUBST (XEXP (setsrc
, 0), newdest
);
3799 SUBST (XEXP (setsrc
, 1), newdest
);
3802 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3803 else if ((code
== PLUS
|| code
== MULT
)
3804 && GET_CODE (src_op0
) == code
3805 && GET_CODE (XEXP (src_op0
, 0)) == code
3806 && (INTEGRAL_MODE_P (mode
)
3807 || (FLOAT_MODE_P (mode
)
3808 && flag_unsafe_math_optimizations
)))
3810 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3811 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3812 rtx r
= XEXP (src_op0
, 1);
3815 /* Split both "((X op Y) op X) op Y" and
3816 "((X op Y) op Y) op X" as "T op T" where T is
3818 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3819 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3821 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3822 SUBST (XEXP (setsrc
, 0), newdest
);
3823 SUBST (XEXP (setsrc
, 1), newdest
);
3826 /* Split "((X op X) op Y) op Y)" as "T op T" where
3828 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3830 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3831 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3832 SUBST (XEXP (setsrc
, 0), newdest
);
3833 SUBST (XEXP (setsrc
, 1), newdest
);
3841 newi2pat
= gen_rtx_SET (newdest
, *split
);
3842 SUBST (*split
, newdest
);
3845 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3847 /* recog_for_combine might have added CLOBBERs to newi2pat.
3848 Make sure NEWPAT does not depend on the clobbered regs. */
3849 if (GET_CODE (newi2pat
) == PARALLEL
)
3850 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3851 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3853 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3854 if (reg_overlap_mentioned_p (reg
, newpat
))
3861 /* If the split point was a MULT and we didn't have one before,
3862 don't use one now. */
3863 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3864 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3868 /* Check for a case where we loaded from memory in a narrow mode and
3869 then sign extended it, but we need both registers. In that case,
3870 we have a PARALLEL with both loads from the same memory location.
3871 We can split this into a load from memory followed by a register-register
3872 copy. This saves at least one insn, more if register allocation can
3875 We cannot do this if the destination of the first assignment is a
3876 condition code register or cc0. We eliminate this case by making sure
3877 the SET_DEST and SET_SRC have the same mode.
3879 We cannot do this if the destination of the second assignment is
3880 a register that we have already assumed is zero-extended. Similarly
3881 for a SUBREG of such a register. */
3883 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3884 && GET_CODE (newpat
) == PARALLEL
3885 && XVECLEN (newpat
, 0) == 2
3886 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3887 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3888 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3889 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3890 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3891 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3892 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3893 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3895 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3896 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3897 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3899 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3900 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3901 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3902 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3903 != GET_MODE_MASK (word_mode
))))
3904 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3905 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3907 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3908 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3909 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3910 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3911 != GET_MODE_MASK (word_mode
)))))
3912 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3913 SET_SRC (XVECEXP (newpat
, 0, 1)))
3914 && ! find_reg_note (i3
, REG_UNUSED
,
3915 SET_DEST (XVECEXP (newpat
, 0, 0))))
3919 newi2pat
= XVECEXP (newpat
, 0, 0);
3920 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3921 newpat
= XVECEXP (newpat
, 0, 1);
3922 SUBST (SET_SRC (newpat
),
3923 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3924 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3926 if (i2_code_number
>= 0)
3927 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3929 if (insn_code_number
>= 0)
3933 /* Similarly, check for a case where we have a PARALLEL of two independent
3934 SETs but we started with three insns. In this case, we can do the sets
3935 as two separate insns. This case occurs when some SET allows two
3936 other insns to combine, but the destination of that SET is still live.
3938 Also do this if we started with two insns and (at least) one of the
3939 resulting sets is a noop; this noop will be deleted later. */
3941 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3942 && GET_CODE (newpat
) == PARALLEL
3943 && XVECLEN (newpat
, 0) == 2
3944 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3945 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3946 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3947 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3948 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3949 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3950 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3951 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3952 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3953 XVECEXP (newpat
, 0, 0))
3954 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3955 XVECEXP (newpat
, 0, 1))
3956 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3957 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3959 rtx set0
= XVECEXP (newpat
, 0, 0);
3960 rtx set1
= XVECEXP (newpat
, 0, 1);
3962 /* Normally, it doesn't matter which of the two is done first,
3963 but the one that references cc0 can't be the second, and
3964 one which uses any regs/memory set in between i2 and i3 can't
3965 be first. The PARALLEL might also have been pre-existing in i3,
3966 so we need to make sure that we won't wrongly hoist a SET to i2
3967 that would conflict with a death note present in there. */
3968 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3969 && !(REG_P (SET_DEST (set1
))
3970 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3971 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3972 && find_reg_note (i2
, REG_DEAD
,
3973 SUBREG_REG (SET_DEST (set1
))))
3974 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3975 /* If I3 is a jump, ensure that set0 is a jump so that
3976 we do not create invalid RTL. */
3977 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3983 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3984 && !(REG_P (SET_DEST (set0
))
3985 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3986 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3987 && find_reg_note (i2
, REG_DEAD
,
3988 SUBREG_REG (SET_DEST (set0
))))
3989 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3990 /* If I3 is a jump, ensure that set1 is a jump so that
3991 we do not create invalid RTL. */
3992 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4004 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4006 if (i2_code_number
>= 0)
4008 /* recog_for_combine might have added CLOBBERs to newi2pat.
4009 Make sure NEWPAT does not depend on the clobbered regs. */
4010 if (GET_CODE (newi2pat
) == PARALLEL
)
4012 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4013 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4015 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4016 if (reg_overlap_mentioned_p (reg
, newpat
))
4024 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4028 /* If it still isn't recognized, fail and change things back the way they
4030 if ((insn_code_number
< 0
4031 /* Is the result a reasonable ASM_OPERANDS? */
4032 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4038 /* If we had to change another insn, make sure it is valid also. */
4039 if (undobuf
.other_insn
)
4041 CLEAR_HARD_REG_SET (newpat_used_regs
);
4043 other_pat
= PATTERN (undobuf
.other_insn
);
4044 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4047 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4054 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4055 they are adjacent to each other or not. */
4058 rtx_insn
*p
= prev_nonnote_insn (i3
);
4059 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4060 && sets_cc0_p (newi2pat
))
4067 /* Only allow this combination if insn_rtx_costs reports that the
4068 replacement instructions are cheaper than the originals. */
4069 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4075 if (MAY_HAVE_DEBUG_INSNS
)
4079 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4080 if (undo
->kind
== UNDO_MODE
)
4082 rtx reg
= *undo
->where
.r
;
4083 machine_mode new_mode
= GET_MODE (reg
);
4084 machine_mode old_mode
= undo
->old_contents
.m
;
4086 /* Temporarily revert mode back. */
4087 adjust_reg_mode (reg
, old_mode
);
4089 if (reg
== i2dest
&& i2scratch
)
4091 /* If we used i2dest as a scratch register with a
4092 different mode, substitute it for the original
4093 i2src while its original mode is temporarily
4094 restored, and then clear i2scratch so that we don't
4095 do it again later. */
4096 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4099 /* Put back the new mode. */
4100 adjust_reg_mode (reg
, new_mode
);
4104 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4105 rtx_insn
*first
, *last
;
4110 last
= last_combined_insn
;
4115 last
= undobuf
.other_insn
;
4117 if (DF_INSN_LUID (last
)
4118 < DF_INSN_LUID (last_combined_insn
))
4119 last
= last_combined_insn
;
4122 /* We're dealing with a reg that changed mode but not
4123 meaning, so we want to turn it into a subreg for
4124 the new mode. However, because of REG sharing and
4125 because its mode had already changed, we have to do
4126 it in two steps. First, replace any debug uses of
4127 reg, with its original mode temporarily restored,
4128 with this copy we have created; then, replace the
4129 copy with the SUBREG of the original shared reg,
4130 once again changed to the new mode. */
4131 propagate_for_debug (first
, last
, reg
, tempreg
,
4133 adjust_reg_mode (reg
, new_mode
);
4134 propagate_for_debug (first
, last
, tempreg
,
4135 lowpart_subreg (old_mode
, reg
, new_mode
),
4141 /* If we will be able to accept this, we have made a
4142 change to the destination of I3. This requires us to
4143 do a few adjustments. */
4145 if (changed_i3_dest
)
4147 PATTERN (i3
) = newpat
;
4148 adjust_for_new_dest (i3
);
4151 /* We now know that we can do this combination. Merge the insns and
4152 update the status of registers and LOG_LINKS. */
4154 if (undobuf
.other_insn
)
4158 PATTERN (undobuf
.other_insn
) = other_pat
;
4160 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4161 ensure that they are still valid. Then add any non-duplicate
4162 notes added by recog_for_combine. */
4163 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4165 next
= XEXP (note
, 1);
4167 if ((REG_NOTE_KIND (note
) == REG_DEAD
4168 && !reg_referenced_p (XEXP (note
, 0),
4169 PATTERN (undobuf
.other_insn
)))
4170 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4171 && !reg_set_p (XEXP (note
, 0),
4172 PATTERN (undobuf
.other_insn
))))
4173 remove_note (undobuf
.other_insn
, note
);
4176 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4177 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4184 struct insn_link
*link
;
4187 /* I3 now uses what used to be its destination and which is now
4188 I2's destination. This requires us to do a few adjustments. */
4189 PATTERN (i3
) = newpat
;
4190 adjust_for_new_dest (i3
);
4192 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4195 However, some later insn might be using I2's dest and have
4196 a LOG_LINK pointing at I3. We must remove this link.
4197 The simplest way to remove the link is to point it at I1,
4198 which we know will be a NOTE. */
4200 /* newi2pat is usually a SET here; however, recog_for_combine might
4201 have added some clobbers. */
4202 if (GET_CODE (newi2pat
) == PARALLEL
)
4203 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4205 ni2dest
= SET_DEST (newi2pat
);
4207 for (insn
= NEXT_INSN (i3
);
4208 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4209 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4210 insn
= NEXT_INSN (insn
))
4212 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4214 FOR_EACH_LOG_LINK (link
, insn
)
4215 if (link
->insn
== i3
)
4224 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4225 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4228 /* Compute which registers we expect to eliminate. newi2pat may be setting
4229 either i3dest or i2dest, so we must check it. */
4230 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4231 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4234 /* For i1, we need to compute both local elimination and global
4235 elimination information with respect to newi2pat because i1dest
4236 may be the same as i3dest, in which case newi2pat may be setting
4237 i1dest. Global information is used when distributing REG_DEAD
4238 note for i2 and i3, in which case it does matter if newi2pat sets
4241 Local information is used when distributing REG_DEAD note for i1,
4242 in which case it doesn't matter if newi2pat sets i1dest or not.
4243 See PR62151, if we have four insns combination:
4245 i1: r1 <- i1src (using r0)
4247 i2: r0 <- i2src (using r1)
4248 i3: r3 <- i3src (using r0)
4250 From i1's point of view, r0 is eliminated, no matter if it is set
4251 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4252 should be discarded.
4254 Note local information only affects cases in forms like "I1->I2->I3",
4255 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4256 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4258 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4261 rtx elim_i1
= (local_elim_i1
== 0
4262 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4264 /* Same case as i1. */
4265 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4267 rtx elim_i0
= (local_elim_i0
== 0
4268 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4271 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4273 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4274 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4276 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4278 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4280 /* Ensure that we do not have something that should not be shared but
4281 occurs multiple times in the new insns. Check this by first
4282 resetting all the `used' flags and then copying anything is shared. */
4284 reset_used_flags (i3notes
);
4285 reset_used_flags (i2notes
);
4286 reset_used_flags (i1notes
);
4287 reset_used_flags (i0notes
);
4288 reset_used_flags (newpat
);
4289 reset_used_flags (newi2pat
);
4290 if (undobuf
.other_insn
)
4291 reset_used_flags (PATTERN (undobuf
.other_insn
));
4293 i3notes
= copy_rtx_if_shared (i3notes
);
4294 i2notes
= copy_rtx_if_shared (i2notes
);
4295 i1notes
= copy_rtx_if_shared (i1notes
);
4296 i0notes
= copy_rtx_if_shared (i0notes
);
4297 newpat
= copy_rtx_if_shared (newpat
);
4298 newi2pat
= copy_rtx_if_shared (newi2pat
);
4299 if (undobuf
.other_insn
)
4300 reset_used_flags (PATTERN (undobuf
.other_insn
));
4302 INSN_CODE (i3
) = insn_code_number
;
4303 PATTERN (i3
) = newpat
;
4305 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4307 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4309 reset_used_flags (call_usage
);
4310 call_usage
= copy_rtx (call_usage
);
4314 /* I2SRC must still be meaningful at this point. Some splitting
4315 operations can invalidate I2SRC, but those operations do not
4318 replace_rtx (call_usage
, i2dest
, i2src
);
4322 replace_rtx (call_usage
, i1dest
, i1src
);
4324 replace_rtx (call_usage
, i0dest
, i0src
);
4326 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4329 if (undobuf
.other_insn
)
4330 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4332 /* We had one special case above where I2 had more than one set and
4333 we replaced a destination of one of those sets with the destination
4334 of I3. In that case, we have to update LOG_LINKS of insns later
4335 in this basic block. Note that this (expensive) case is rare.
4337 Also, in this case, we must pretend that all REG_NOTEs for I2
4338 actually came from I3, so that REG_UNUSED notes from I2 will be
4339 properly handled. */
4341 if (i3_subst_into_i2
)
4343 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4344 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4345 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4346 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4347 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4348 && ! find_reg_note (i2
, REG_UNUSED
,
4349 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4350 for (temp_insn
= NEXT_INSN (i2
);
4352 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4353 || BB_HEAD (this_basic_block
) != temp_insn
);
4354 temp_insn
= NEXT_INSN (temp_insn
))
4355 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4356 FOR_EACH_LOG_LINK (link
, temp_insn
)
4357 if (link
->insn
== i2
)
4363 while (XEXP (link
, 1))
4364 link
= XEXP (link
, 1);
4365 XEXP (link
, 1) = i2notes
;
4372 LOG_LINKS (i3
) = NULL
;
4374 LOG_LINKS (i2
) = NULL
;
4379 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4380 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4382 INSN_CODE (i2
) = i2_code_number
;
4383 PATTERN (i2
) = newi2pat
;
4387 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4388 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4390 SET_INSN_DELETED (i2
);
4395 LOG_LINKS (i1
) = NULL
;
4397 if (MAY_HAVE_DEBUG_INSNS
)
4398 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4400 SET_INSN_DELETED (i1
);
4405 LOG_LINKS (i0
) = NULL
;
4407 if (MAY_HAVE_DEBUG_INSNS
)
4408 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4410 SET_INSN_DELETED (i0
);
4413 /* Get death notes for everything that is now used in either I3 or
4414 I2 and used to die in a previous insn. If we built two new
4415 patterns, move from I1 to I2 then I2 to I3 so that we get the
4416 proper movement on registers that I2 modifies. */
4419 from_luid
= DF_INSN_LUID (i0
);
4421 from_luid
= DF_INSN_LUID (i1
);
4423 from_luid
= DF_INSN_LUID (i2
);
4425 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4426 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4428 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4430 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4431 elim_i2
, elim_i1
, elim_i0
);
4433 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4434 elim_i2
, elim_i1
, elim_i0
);
4436 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4437 elim_i2
, local_elim_i1
, local_elim_i0
);
4439 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4440 elim_i2
, elim_i1
, local_elim_i0
);
4442 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4443 elim_i2
, elim_i1
, elim_i0
);
4445 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4446 know these are REG_UNUSED and want them to go to the desired insn,
4447 so we always pass it as i3. */
4449 if (newi2pat
&& new_i2_notes
)
4450 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4454 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4457 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4458 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4459 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4460 in that case, it might delete I2. Similarly for I2 and I1.
4461 Show an additional death due to the REG_DEAD note we make here. If
4462 we discard it in distribute_notes, we will decrement it again. */
4466 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4467 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4468 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4471 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4472 elim_i2
, elim_i1
, elim_i0
);
4475 if (i2dest_in_i2src
)
4477 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4478 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4479 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4480 NULL_RTX
, NULL_RTX
);
4482 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4483 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4486 if (i1dest_in_i1src
)
4488 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4489 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4490 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4491 NULL_RTX
, NULL_RTX
);
4493 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4494 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4497 if (i0dest_in_i0src
)
4499 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4500 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4501 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4502 NULL_RTX
, NULL_RTX
);
4504 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4505 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4508 distribute_links (i3links
);
4509 distribute_links (i2links
);
4510 distribute_links (i1links
);
4511 distribute_links (i0links
);
4515 struct insn_link
*link
;
4516 rtx_insn
*i2_insn
= 0;
4517 rtx i2_val
= 0, set
;
4519 /* The insn that used to set this register doesn't exist, and
4520 this life of the register may not exist either. See if one of
4521 I3's links points to an insn that sets I2DEST. If it does,
4522 that is now the last known value for I2DEST. If we don't update
4523 this and I2 set the register to a value that depended on its old
4524 contents, we will get confused. If this insn is used, thing
4525 will be set correctly in combine_instructions. */
4526 FOR_EACH_LOG_LINK (link
, i3
)
4527 if ((set
= single_set (link
->insn
)) != 0
4528 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4529 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4531 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4533 /* If the reg formerly set in I2 died only once and that was in I3,
4534 zero its use count so it won't make `reload' do any work. */
4536 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4537 && ! i2dest_in_i2src
4538 && REGNO (i2dest
) < reg_n_sets_max
)
4539 INC_REG_N_SETS (REGNO (i2dest
), -1);
4542 if (i1
&& REG_P (i1dest
))
4544 struct insn_link
*link
;
4545 rtx_insn
*i1_insn
= 0;
4546 rtx i1_val
= 0, set
;
4548 FOR_EACH_LOG_LINK (link
, i3
)
4549 if ((set
= single_set (link
->insn
)) != 0
4550 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4551 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4553 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4556 && ! i1dest_in_i1src
4557 && REGNO (i1dest
) < reg_n_sets_max
)
4558 INC_REG_N_SETS (REGNO (i1dest
), -1);
4561 if (i0
&& REG_P (i0dest
))
4563 struct insn_link
*link
;
4564 rtx_insn
*i0_insn
= 0;
4565 rtx i0_val
= 0, set
;
4567 FOR_EACH_LOG_LINK (link
, i3
)
4568 if ((set
= single_set (link
->insn
)) != 0
4569 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4570 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4572 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4575 && ! i0dest_in_i0src
4576 && REGNO (i0dest
) < reg_n_sets_max
)
4577 INC_REG_N_SETS (REGNO (i0dest
), -1);
4580 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4581 been made to this insn. The order is important, because newi2pat
4582 can affect nonzero_bits of newpat. */
4584 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4585 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4588 if (undobuf
.other_insn
!= NULL_RTX
)
4592 fprintf (dump_file
, "modifying other_insn ");
4593 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4595 df_insn_rescan (undobuf
.other_insn
);
4598 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4602 fprintf (dump_file
, "modifying insn i0 ");
4603 dump_insn_slim (dump_file
, i0
);
4605 df_insn_rescan (i0
);
4608 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4612 fprintf (dump_file
, "modifying insn i1 ");
4613 dump_insn_slim (dump_file
, i1
);
4615 df_insn_rescan (i1
);
4618 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4622 fprintf (dump_file
, "modifying insn i2 ");
4623 dump_insn_slim (dump_file
, i2
);
4625 df_insn_rescan (i2
);
4628 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4632 fprintf (dump_file
, "modifying insn i3 ");
4633 dump_insn_slim (dump_file
, i3
);
4635 df_insn_rescan (i3
);
4638 /* Set new_direct_jump_p if a new return or simple jump instruction
4639 has been created. Adjust the CFG accordingly. */
4640 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4642 *new_direct_jump_p
= 1;
4643 mark_jump_label (PATTERN (i3
), i3
, 0);
4644 update_cfg_for_uncondjump (i3
);
4647 if (undobuf
.other_insn
!= NULL_RTX
4648 && (returnjump_p (undobuf
.other_insn
)
4649 || any_uncondjump_p (undobuf
.other_insn
)))
4651 *new_direct_jump_p
= 1;
4652 update_cfg_for_uncondjump (undobuf
.other_insn
);
4655 /* A noop might also need cleaning up of CFG, if it comes from the
4656 simplification of a jump. */
4658 && GET_CODE (newpat
) == SET
4659 && SET_SRC (newpat
) == pc_rtx
4660 && SET_DEST (newpat
) == pc_rtx
)
4662 *new_direct_jump_p
= 1;
4663 update_cfg_for_uncondjump (i3
);
4666 if (undobuf
.other_insn
!= NULL_RTX
4667 && JUMP_P (undobuf
.other_insn
)
4668 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4669 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4670 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4672 *new_direct_jump_p
= 1;
4673 update_cfg_for_uncondjump (undobuf
.other_insn
);
4676 combine_successes
++;
4679 if (added_links_insn
4680 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4681 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4682 return added_links_insn
;
4684 return newi2pat
? i2
: i3
;
4687 /* Get a marker for undoing to the current state. */
4690 get_undo_marker (void)
4692 return undobuf
.undos
;
4695 /* Undo the modifications up to the marker. */
4698 undo_to_marker (void *marker
)
4700 struct undo
*undo
, *next
;
4702 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4710 *undo
->where
.r
= undo
->old_contents
.r
;
4713 *undo
->where
.i
= undo
->old_contents
.i
;
4716 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4719 *undo
->where
.l
= undo
->old_contents
.l
;
4725 undo
->next
= undobuf
.frees
;
4726 undobuf
.frees
= undo
;
4729 undobuf
.undos
= (struct undo
*) marker
;
4732 /* Undo all the modifications recorded in undobuf. */
4740 /* We've committed to accepting the changes we made. Move all
4741 of the undos to the free list. */
4746 struct undo
*undo
, *next
;
4748 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4751 undo
->next
= undobuf
.frees
;
4752 undobuf
.frees
= undo
;
4757 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4758 where we have an arithmetic expression and return that point. LOC will
4761 try_combine will call this function to see if an insn can be split into
4765 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4768 enum rtx_code code
= GET_CODE (x
);
4770 unsigned HOST_WIDE_INT len
= 0;
4771 HOST_WIDE_INT pos
= 0;
4773 rtx inner
= NULL_RTX
;
4775 /* First special-case some codes. */
4779 #ifdef INSN_SCHEDULING
4780 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4782 if (MEM_P (SUBREG_REG (x
)))
4785 return find_split_point (&SUBREG_REG (x
), insn
, false);
4788 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4789 using LO_SUM and HIGH. */
4790 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4791 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4793 machine_mode address_mode
= get_address_mode (x
);
4796 gen_rtx_LO_SUM (address_mode
,
4797 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4799 return &XEXP (XEXP (x
, 0), 0);
4802 /* If we have a PLUS whose second operand is a constant and the
4803 address is not valid, perhaps will can split it up using
4804 the machine-specific way to split large constants. We use
4805 the first pseudo-reg (one of the virtual regs) as a placeholder;
4806 it will not remain in the result. */
4807 if (GET_CODE (XEXP (x
, 0)) == PLUS
4808 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4809 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4810 MEM_ADDR_SPACE (x
)))
4812 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4813 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4816 /* This should have produced two insns, each of which sets our
4817 placeholder. If the source of the second is a valid address,
4818 we can make put both sources together and make a split point
4822 && NEXT_INSN (seq
) != NULL_RTX
4823 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4824 && NONJUMP_INSN_P (seq
)
4825 && GET_CODE (PATTERN (seq
)) == SET
4826 && SET_DEST (PATTERN (seq
)) == reg
4827 && ! reg_mentioned_p (reg
,
4828 SET_SRC (PATTERN (seq
)))
4829 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4830 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4831 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4832 && memory_address_addr_space_p
4833 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4834 MEM_ADDR_SPACE (x
)))
4836 rtx src1
= SET_SRC (PATTERN (seq
));
4837 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4839 /* Replace the placeholder in SRC2 with SRC1. If we can
4840 find where in SRC2 it was placed, that can become our
4841 split point and we can replace this address with SRC2.
4842 Just try two obvious places. */
4844 src2
= replace_rtx (src2
, reg
, src1
);
4846 if (XEXP (src2
, 0) == src1
)
4847 split
= &XEXP (src2
, 0);
4848 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4849 && XEXP (XEXP (src2
, 0), 0) == src1
)
4850 split
= &XEXP (XEXP (src2
, 0), 0);
4854 SUBST (XEXP (x
, 0), src2
);
4859 /* If that didn't work, perhaps the first operand is complex and
4860 needs to be computed separately, so make a split point there.
4861 This will occur on machines that just support REG + CONST
4862 and have a constant moved through some previous computation. */
4864 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4865 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4866 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4867 return &XEXP (XEXP (x
, 0), 0);
4870 /* If we have a PLUS whose first operand is complex, try computing it
4871 separately by making a split there. */
4872 if (GET_CODE (XEXP (x
, 0)) == PLUS
4873 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4875 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4876 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4877 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4878 return &XEXP (XEXP (x
, 0), 0);
4882 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4883 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4884 we need to put the operand into a register. So split at that
4887 if (SET_DEST (x
) == cc0_rtx
4888 && GET_CODE (SET_SRC (x
)) != COMPARE
4889 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4890 && !OBJECT_P (SET_SRC (x
))
4891 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4892 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4893 return &SET_SRC (x
);
4895 /* See if we can split SET_SRC as it stands. */
4896 split
= find_split_point (&SET_SRC (x
), insn
, true);
4897 if (split
&& split
!= &SET_SRC (x
))
4900 /* See if we can split SET_DEST as it stands. */
4901 split
= find_split_point (&SET_DEST (x
), insn
, false);
4902 if (split
&& split
!= &SET_DEST (x
))
4905 /* See if this is a bitfield assignment with everything constant. If
4906 so, this is an IOR of an AND, so split it into that. */
4907 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4908 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4909 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4910 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4911 && CONST_INT_P (SET_SRC (x
))
4912 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4913 + INTVAL (XEXP (SET_DEST (x
), 2)))
4914 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4915 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4917 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4918 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4919 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4920 rtx dest
= XEXP (SET_DEST (x
), 0);
4921 machine_mode mode
= GET_MODE (dest
);
4922 unsigned HOST_WIDE_INT mask
4923 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4926 if (BITS_BIG_ENDIAN
)
4927 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4929 or_mask
= gen_int_mode (src
<< pos
, mode
);
4932 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4935 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4937 simplify_gen_binary (IOR
, mode
,
4938 simplify_gen_binary (AND
, mode
,
4943 SUBST (SET_DEST (x
), dest
);
4945 split
= find_split_point (&SET_SRC (x
), insn
, true);
4946 if (split
&& split
!= &SET_SRC (x
))
4950 /* Otherwise, see if this is an operation that we can split into two.
4951 If so, try to split that. */
4952 code
= GET_CODE (SET_SRC (x
));
4957 /* If we are AND'ing with a large constant that is only a single
4958 bit and the result is only being used in a context where we
4959 need to know if it is zero or nonzero, replace it with a bit
4960 extraction. This will avoid the large constant, which might
4961 have taken more than one insn to make. If the constant were
4962 not a valid argument to the AND but took only one insn to make,
4963 this is no worse, but if it took more than one insn, it will
4966 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4967 && REG_P (XEXP (SET_SRC (x
), 0))
4968 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4969 && REG_P (SET_DEST (x
))
4970 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4971 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4972 && XEXP (*split
, 0) == SET_DEST (x
)
4973 && XEXP (*split
, 1) == const0_rtx
)
4975 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4976 XEXP (SET_SRC (x
), 0),
4977 pos
, NULL_RTX
, 1, 1, 0, 0);
4978 if (extraction
!= 0)
4980 SUBST (SET_SRC (x
), extraction
);
4981 return find_split_point (loc
, insn
, false);
4987 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4988 is known to be on, this can be converted into a NEG of a shift. */
4989 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4990 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4991 && 1 <= (pos
= exact_log2
4992 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4993 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4995 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4999 gen_rtx_LSHIFTRT (mode
,
5000 XEXP (SET_SRC (x
), 0),
5003 split
= find_split_point (&SET_SRC (x
), insn
, true);
5004 if (split
&& split
!= &SET_SRC (x
))
5010 inner
= XEXP (SET_SRC (x
), 0);
5012 /* We can't optimize if either mode is a partial integer
5013 mode as we don't know how many bits are significant
5015 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
5016 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5020 len
= GET_MODE_PRECISION (GET_MODE (inner
));
5026 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5027 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5029 inner
= XEXP (SET_SRC (x
), 0);
5030 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5031 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5033 if (BITS_BIG_ENDIAN
)
5034 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
5035 unsignedp
= (code
== ZERO_EXTRACT
);
5044 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5046 machine_mode mode
= GET_MODE (SET_SRC (x
));
5048 /* For unsigned, we have a choice of a shift followed by an
5049 AND or two shifts. Use two shifts for field sizes where the
5050 constant might be too large. We assume here that we can
5051 always at least get 8-bit constants in an AND insn, which is
5052 true for every current RISC. */
5054 if (unsignedp
&& len
<= 8)
5056 unsigned HOST_WIDE_INT mask
5057 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
5061 (mode
, gen_lowpart (mode
, inner
),
5063 gen_int_mode (mask
, mode
)));
5065 split
= find_split_point (&SET_SRC (x
), insn
, true);
5066 if (split
&& split
!= &SET_SRC (x
))
5073 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5074 gen_rtx_ASHIFT (mode
,
5075 gen_lowpart (mode
, inner
),
5076 GEN_INT (GET_MODE_PRECISION (mode
)
5078 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5080 split
= find_split_point (&SET_SRC (x
), insn
, true);
5081 if (split
&& split
!= &SET_SRC (x
))
5086 /* See if this is a simple operation with a constant as the second
5087 operand. It might be that this constant is out of range and hence
5088 could be used as a split point. */
5089 if (BINARY_P (SET_SRC (x
))
5090 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5091 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5092 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5093 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5094 return &XEXP (SET_SRC (x
), 1);
5096 /* Finally, see if this is a simple operation with its first operand
5097 not in a register. The operation might require this operand in a
5098 register, so return it as a split point. We can always do this
5099 because if the first operand were another operation, we would have
5100 already found it as a split point. */
5101 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5102 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5103 return &XEXP (SET_SRC (x
), 0);
5109 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5110 it is better to write this as (not (ior A B)) so we can split it.
5111 Similarly for IOR. */
5112 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5115 gen_rtx_NOT (GET_MODE (x
),
5116 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5118 XEXP (XEXP (x
, 0), 0),
5119 XEXP (XEXP (x
, 1), 0))));
5120 return find_split_point (loc
, insn
, set_src
);
5123 /* Many RISC machines have a large set of logical insns. If the
5124 second operand is a NOT, put it first so we will try to split the
5125 other operand first. */
5126 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5128 rtx tem
= XEXP (x
, 0);
5129 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5130 SUBST (XEXP (x
, 1), tem
);
5136 /* Canonicalization can produce (minus A (mult B C)), where C is a
5137 constant. It may be better to try splitting (plus (mult B -C) A)
5138 instead if this isn't a multiply by a power of two. */
5139 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5140 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5141 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
5143 machine_mode mode
= GET_MODE (x
);
5144 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5145 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5146 SUBST (*loc
, gen_rtx_PLUS (mode
,
5148 XEXP (XEXP (x
, 1), 0),
5149 gen_int_mode (other_int
,
5152 return find_split_point (loc
, insn
, set_src
);
5155 /* Split at a multiply-accumulate instruction. However if this is
5156 the SET_SRC, we likely do not have such an instruction and it's
5157 worthless to try this split. */
5159 && (GET_CODE (XEXP (x
, 0)) == MULT
5160 || GET_CODE (XEXP (x
, 0)) == ASHIFT
))
5167 /* Otherwise, select our actions depending on our rtx class. */
5168 switch (GET_RTX_CLASS (code
))
5170 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5172 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5175 /* ... fall through ... */
5177 case RTX_COMM_ARITH
:
5179 case RTX_COMM_COMPARE
:
5180 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5183 /* ... fall through ... */
5185 /* Some machines have (and (shift ...) ...) insns. If X is not
5186 an AND, but XEXP (X, 0) is, use it as our split point. */
5187 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5188 return &XEXP (x
, 0);
5190 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5196 /* Otherwise, we don't have a split point. */
5201 /* Throughout X, replace FROM with TO, and return the result.
5202 The result is TO if X is FROM;
5203 otherwise the result is X, but its contents may have been modified.
5204 If they were modified, a record was made in undobuf so that
5205 undo_all will (among other things) return X to its original state.
5207 If the number of changes necessary is too much to record to undo,
5208 the excess changes are not made, so the result is invalid.
5209 The changes already made can still be undone.
5210 undobuf.num_undo is incremented for such changes, so by testing that
5211 the caller can tell whether the result is valid.
5213 `n_occurrences' is incremented each time FROM is replaced.
5215 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5217 IN_COND is nonzero if we are at the top level of a condition.
5219 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5220 by copying if `n_occurrences' is nonzero. */
5223 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5225 enum rtx_code code
= GET_CODE (x
);
5226 machine_mode op0_mode
= VOIDmode
;
5231 /* Two expressions are equal if they are identical copies of a shared
5232 RTX or if they are both registers with the same register number
5235 #define COMBINE_RTX_EQUAL_P(X,Y) \
5237 || (REG_P (X) && REG_P (Y) \
5238 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5240 /* Do not substitute into clobbers of regs -- this will never result in
5242 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5245 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5248 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5251 /* If X and FROM are the same register but different modes, they
5252 will not have been seen as equal above. However, the log links code
5253 will make a LOG_LINKS entry for that case. If we do nothing, we
5254 will try to rerecognize our original insn and, when it succeeds,
5255 we will delete the feeding insn, which is incorrect.
5257 So force this insn not to match in this (rare) case. */
5258 if (! in_dest
&& code
== REG
&& REG_P (from
)
5259 && reg_overlap_mentioned_p (x
, from
))
5260 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5262 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5263 of which may contain things that can be combined. */
5264 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5267 /* It is possible to have a subexpression appear twice in the insn.
5268 Suppose that FROM is a register that appears within TO.
5269 Then, after that subexpression has been scanned once by `subst',
5270 the second time it is scanned, TO may be found. If we were
5271 to scan TO here, we would find FROM within it and create a
5272 self-referent rtl structure which is completely wrong. */
5273 if (COMBINE_RTX_EQUAL_P (x
, to
))
5276 /* Parallel asm_operands need special attention because all of the
5277 inputs are shared across the arms. Furthermore, unsharing the
5278 rtl results in recognition failures. Failure to handle this case
5279 specially can result in circular rtl.
5281 Solve this by doing a normal pass across the first entry of the
5282 parallel, and only processing the SET_DESTs of the subsequent
5285 if (code
== PARALLEL
5286 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5287 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5289 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5291 /* If this substitution failed, this whole thing fails. */
5292 if (GET_CODE (new_rtx
) == CLOBBER
5293 && XEXP (new_rtx
, 0) == const0_rtx
)
5296 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5298 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5300 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5303 && GET_CODE (dest
) != CC0
5304 && GET_CODE (dest
) != PC
)
5306 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5308 /* If this substitution failed, this whole thing fails. */
5309 if (GET_CODE (new_rtx
) == CLOBBER
5310 && XEXP (new_rtx
, 0) == const0_rtx
)
5313 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5319 len
= GET_RTX_LENGTH (code
);
5320 fmt
= GET_RTX_FORMAT (code
);
5322 /* We don't need to process a SET_DEST that is a register, CC0,
5323 or PC, so set up to skip this common case. All other cases
5324 where we want to suppress replacing something inside a
5325 SET_SRC are handled via the IN_DEST operand. */
5327 && (REG_P (SET_DEST (x
))
5328 || GET_CODE (SET_DEST (x
)) == CC0
5329 || GET_CODE (SET_DEST (x
)) == PC
))
5332 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5335 op0_mode
= GET_MODE (XEXP (x
, 0));
5337 for (i
= 0; i
< len
; i
++)
5342 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5344 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5346 new_rtx
= (unique_copy
&& n_occurrences
5347 ? copy_rtx (to
) : to
);
5352 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5355 /* If this substitution failed, this whole thing
5357 if (GET_CODE (new_rtx
) == CLOBBER
5358 && XEXP (new_rtx
, 0) == const0_rtx
)
5362 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5365 else if (fmt
[i
] == 'e')
5367 /* If this is a register being set, ignore it. */
5368 new_rtx
= XEXP (x
, i
);
5371 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5373 || code
== STRICT_LOW_PART
))
5376 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5378 /* In general, don't install a subreg involving two
5379 modes not tieable. It can worsen register
5380 allocation, and can even make invalid reload
5381 insns, since the reg inside may need to be copied
5382 from in the outside mode, and that may be invalid
5383 if it is an fp reg copied in integer mode.
5385 We allow two exceptions to this: It is valid if
5386 it is inside another SUBREG and the mode of that
5387 SUBREG and the mode of the inside of TO is
5388 tieable and it is valid if X is a SET that copies
5391 if (GET_CODE (to
) == SUBREG
5392 && ! MODES_TIEABLE_P (GET_MODE (to
),
5393 GET_MODE (SUBREG_REG (to
)))
5394 && ! (code
== SUBREG
5395 && MODES_TIEABLE_P (GET_MODE (x
),
5396 GET_MODE (SUBREG_REG (to
))))
5398 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5401 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5405 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5406 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5409 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5411 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5415 /* If we are in a SET_DEST, suppress most cases unless we
5416 have gone inside a MEM, in which case we want to
5417 simplify the address. We assume here that things that
5418 are actually part of the destination have their inner
5419 parts in the first expression. This is true for SUBREG,
5420 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5421 things aside from REG and MEM that should appear in a
5423 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5425 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5426 || code
== ZERO_EXTRACT
))
5429 code
== IF_THEN_ELSE
&& i
== 0,
5432 /* If we found that we will have to reject this combination,
5433 indicate that by returning the CLOBBER ourselves, rather than
5434 an expression containing it. This will speed things up as
5435 well as prevent accidents where two CLOBBERs are considered
5436 to be equal, thus producing an incorrect simplification. */
5438 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5441 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5443 machine_mode mode
= GET_MODE (x
);
5445 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5446 GET_MODE (SUBREG_REG (x
)),
5449 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5451 else if (CONST_SCALAR_INT_P (new_rtx
)
5452 && GET_CODE (x
) == ZERO_EXTEND
)
5454 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5455 new_rtx
, GET_MODE (XEXP (x
, 0)));
5459 SUBST (XEXP (x
, i
), new_rtx
);
5464 /* Check if we are loading something from the constant pool via float
5465 extension; in this case we would undo compress_float_constant
5466 optimization and degenerate constant load to an immediate value. */
5467 if (GET_CODE (x
) == FLOAT_EXTEND
5468 && MEM_P (XEXP (x
, 0))
5469 && MEM_READONLY_P (XEXP (x
, 0)))
5471 rtx tmp
= avoid_constant_pool_reference (x
);
5476 /* Try to simplify X. If the simplification changed the code, it is likely
5477 that further simplification will help, so loop, but limit the number
5478 of repetitions that will be performed. */
5480 for (i
= 0; i
< 4; i
++)
5482 /* If X is sufficiently simple, don't bother trying to do anything
5484 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5485 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5487 if (GET_CODE (x
) == code
)
5490 code
= GET_CODE (x
);
5492 /* We no longer know the original mode of operand 0 since we
5493 have changed the form of X) */
5494 op0_mode
= VOIDmode
;
5500 /* Simplify X, a piece of RTL. We just operate on the expression at the
5501 outer level; call `subst' to simplify recursively. Return the new
5504 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5505 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5509 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5512 enum rtx_code code
= GET_CODE (x
);
5513 machine_mode mode
= GET_MODE (x
);
5517 /* If this is a commutative operation, put a constant last and a complex
5518 expression first. We don't need to do this for comparisons here. */
5519 if (COMMUTATIVE_ARITH_P (x
)
5520 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5523 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5524 SUBST (XEXP (x
, 1), temp
);
5527 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5528 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5529 things. Check for cases where both arms are testing the same
5532 Don't do anything if all operands are very simple. */
5535 && ((!OBJECT_P (XEXP (x
, 0))
5536 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5537 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5538 || (!OBJECT_P (XEXP (x
, 1))
5539 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5540 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5542 && (!OBJECT_P (XEXP (x
, 0))
5543 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5544 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5546 rtx cond
, true_rtx
, false_rtx
;
5548 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5550 /* If everything is a comparison, what we have is highly unlikely
5551 to be simpler, so don't use it. */
5552 && ! (COMPARISON_P (x
)
5553 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5555 rtx cop1
= const0_rtx
;
5556 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5558 if (cond_code
== NE
&& COMPARISON_P (cond
))
5561 /* Simplify the alternative arms; this may collapse the true and
5562 false arms to store-flag values. Be careful to use copy_rtx
5563 here since true_rtx or false_rtx might share RTL with x as a
5564 result of the if_then_else_cond call above. */
5565 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5566 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5568 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5569 is unlikely to be simpler. */
5570 if (general_operand (true_rtx
, VOIDmode
)
5571 && general_operand (false_rtx
, VOIDmode
))
5573 enum rtx_code reversed
;
5575 /* Restarting if we generate a store-flag expression will cause
5576 us to loop. Just drop through in this case. */
5578 /* If the result values are STORE_FLAG_VALUE and zero, we can
5579 just make the comparison operation. */
5580 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5581 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5583 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5584 && ((reversed
= reversed_comparison_code_parts
5585 (cond_code
, cond
, cop1
, NULL
))
5587 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5590 /* Likewise, we can make the negate of a comparison operation
5591 if the result values are - STORE_FLAG_VALUE and zero. */
5592 else if (CONST_INT_P (true_rtx
)
5593 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5594 && false_rtx
== const0_rtx
)
5595 x
= simplify_gen_unary (NEG
, mode
,
5596 simplify_gen_relational (cond_code
,
5600 else if (CONST_INT_P (false_rtx
)
5601 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5602 && true_rtx
== const0_rtx
5603 && ((reversed
= reversed_comparison_code_parts
5604 (cond_code
, cond
, cop1
, NULL
))
5606 x
= simplify_gen_unary (NEG
, mode
,
5607 simplify_gen_relational (reversed
,
5612 return gen_rtx_IF_THEN_ELSE (mode
,
5613 simplify_gen_relational (cond_code
,
5618 true_rtx
, false_rtx
);
5620 code
= GET_CODE (x
);
5621 op0_mode
= VOIDmode
;
5626 /* Try to fold this expression in case we have constants that weren't
5629 switch (GET_RTX_CLASS (code
))
5632 if (op0_mode
== VOIDmode
)
5633 op0_mode
= GET_MODE (XEXP (x
, 0));
5634 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5637 case RTX_COMM_COMPARE
:
5639 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5640 if (cmp_mode
== VOIDmode
)
5642 cmp_mode
= GET_MODE (XEXP (x
, 1));
5643 if (cmp_mode
== VOIDmode
)
5644 cmp_mode
= op0_mode
;
5646 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5647 XEXP (x
, 0), XEXP (x
, 1));
5650 case RTX_COMM_ARITH
:
5652 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5654 case RTX_BITFIELD_OPS
:
5656 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5657 XEXP (x
, 1), XEXP (x
, 2));
5666 code
= GET_CODE (temp
);
5667 op0_mode
= VOIDmode
;
5668 mode
= GET_MODE (temp
);
5671 /* First see if we can apply the inverse distributive law. */
5672 if (code
== PLUS
|| code
== MINUS
5673 || code
== AND
|| code
== IOR
|| code
== XOR
)
5675 x
= apply_distributive_law (x
);
5676 code
= GET_CODE (x
);
5677 op0_mode
= VOIDmode
;
5680 /* If CODE is an associative operation not otherwise handled, see if we
5681 can associate some operands. This can win if they are constants or
5682 if they are logically related (i.e. (a & b) & a). */
5683 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5684 || code
== AND
|| code
== IOR
|| code
== XOR
5685 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5686 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5687 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5689 if (GET_CODE (XEXP (x
, 0)) == code
)
5691 rtx other
= XEXP (XEXP (x
, 0), 0);
5692 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5693 rtx inner_op1
= XEXP (x
, 1);
5696 /* Make sure we pass the constant operand if any as the second
5697 one if this is a commutative operation. */
5698 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5700 rtx tem
= inner_op0
;
5701 inner_op0
= inner_op1
;
5704 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5705 : code
== DIV
? MULT
5707 mode
, inner_op0
, inner_op1
);
5709 /* For commutative operations, try the other pair if that one
5711 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5713 other
= XEXP (XEXP (x
, 0), 1);
5714 inner
= simplify_binary_operation (code
, mode
,
5715 XEXP (XEXP (x
, 0), 0),
5720 return simplify_gen_binary (code
, mode
, other
, inner
);
5724 /* A little bit of algebraic simplification here. */
5728 /* Ensure that our address has any ASHIFTs converted to MULT in case
5729 address-recognizing predicates are called later. */
5730 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5731 SUBST (XEXP (x
, 0), temp
);
5735 if (op0_mode
== VOIDmode
)
5736 op0_mode
= GET_MODE (SUBREG_REG (x
));
5738 /* See if this can be moved to simplify_subreg. */
5739 if (CONSTANT_P (SUBREG_REG (x
))
5740 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5741 /* Don't call gen_lowpart if the inner mode
5742 is VOIDmode and we cannot simplify it, as SUBREG without
5743 inner mode is invalid. */
5744 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5745 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5746 return gen_lowpart (mode
, SUBREG_REG (x
));
5748 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5752 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5757 /* If op is known to have all lower bits zero, the result is zero. */
5759 && SCALAR_INT_MODE_P (mode
)
5760 && SCALAR_INT_MODE_P (op0_mode
)
5761 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5762 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5763 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5764 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5765 & GET_MODE_MASK (mode
)) == 0)
5766 return CONST0_RTX (mode
);
5769 /* Don't change the mode of the MEM if that would change the meaning
5771 if (MEM_P (SUBREG_REG (x
))
5772 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5773 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5774 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5775 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5777 /* Note that we cannot do any narrowing for non-constants since
5778 we might have been counting on using the fact that some bits were
5779 zero. We now do this in the SET. */
5784 temp
= expand_compound_operation (XEXP (x
, 0));
5786 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5787 replaced by (lshiftrt X C). This will convert
5788 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5790 if (GET_CODE (temp
) == ASHIFTRT
5791 && CONST_INT_P (XEXP (temp
, 1))
5792 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5793 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5794 INTVAL (XEXP (temp
, 1)));
5796 /* If X has only a single bit that might be nonzero, say, bit I, convert
5797 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5798 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5799 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5800 or a SUBREG of one since we'd be making the expression more
5801 complex if it was just a register. */
5804 && ! (GET_CODE (temp
) == SUBREG
5805 && REG_P (SUBREG_REG (temp
)))
5806 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5808 rtx temp1
= simplify_shift_const
5809 (NULL_RTX
, ASHIFTRT
, mode
,
5810 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5811 GET_MODE_PRECISION (mode
) - 1 - i
),
5812 GET_MODE_PRECISION (mode
) - 1 - i
);
5814 /* If all we did was surround TEMP with the two shifts, we
5815 haven't improved anything, so don't use it. Otherwise,
5816 we are better off with TEMP1. */
5817 if (GET_CODE (temp1
) != ASHIFTRT
5818 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5819 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5825 /* We can't handle truncation to a partial integer mode here
5826 because we don't know the real bitsize of the partial
5828 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5831 if (HWI_COMPUTABLE_MODE_P (mode
))
5833 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5834 GET_MODE_MASK (mode
), 0));
5836 /* We can truncate a constant value and return it. */
5837 if (CONST_INT_P (XEXP (x
, 0)))
5838 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5840 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5841 whose value is a comparison can be replaced with a subreg if
5842 STORE_FLAG_VALUE permits. */
5843 if (HWI_COMPUTABLE_MODE_P (mode
)
5844 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5845 && (temp
= get_last_value (XEXP (x
, 0)))
5846 && COMPARISON_P (temp
))
5847 return gen_lowpart (mode
, XEXP (x
, 0));
5851 /* (const (const X)) can become (const X). Do it this way rather than
5852 returning the inner CONST since CONST can be shared with a
5854 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5855 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5859 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5860 can add in an offset. find_split_point will split this address up
5861 again if it doesn't match. */
5862 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5863 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5868 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5869 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5870 bit-field and can be replaced by either a sign_extend or a
5871 sign_extract. The `and' may be a zero_extend and the two
5872 <c>, -<c> constants may be reversed. */
5873 if (GET_CODE (XEXP (x
, 0)) == XOR
5874 && CONST_INT_P (XEXP (x
, 1))
5875 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5876 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5877 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5878 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5879 && HWI_COMPUTABLE_MODE_P (mode
)
5880 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5881 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5882 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5883 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5884 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5885 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5886 == (unsigned int) i
+ 1))))
5887 return simplify_shift_const
5888 (NULL_RTX
, ASHIFTRT
, mode
,
5889 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5890 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5891 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5892 GET_MODE_PRECISION (mode
) - (i
+ 1));
5894 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5895 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5896 the bitsize of the mode - 1. This allows simplification of
5897 "a = (b & 8) == 0;" */
5898 if (XEXP (x
, 1) == constm1_rtx
5899 && !REG_P (XEXP (x
, 0))
5900 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5901 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5902 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5903 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5904 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5905 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5906 GET_MODE_PRECISION (mode
) - 1),
5907 GET_MODE_PRECISION (mode
) - 1);
5909 /* If we are adding two things that have no bits in common, convert
5910 the addition into an IOR. This will often be further simplified,
5911 for example in cases like ((a & 1) + (a & 2)), which can
5914 if (HWI_COMPUTABLE_MODE_P (mode
)
5915 && (nonzero_bits (XEXP (x
, 0), mode
)
5916 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5918 /* Try to simplify the expression further. */
5919 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5920 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5922 /* If we could, great. If not, do not go ahead with the IOR
5923 replacement, since PLUS appears in many special purpose
5924 address arithmetic instructions. */
5925 if (GET_CODE (temp
) != CLOBBER
5926 && (GET_CODE (temp
) != IOR
5927 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5928 || XEXP (temp
, 1) != XEXP (x
, 1))
5929 && (XEXP (temp
, 0) != XEXP (x
, 1)
5930 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5936 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5937 (and <foo> (const_int pow2-1)) */
5938 if (GET_CODE (XEXP (x
, 1)) == AND
5939 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5940 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5941 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5942 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5943 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5947 /* If we have (mult (plus A B) C), apply the distributive law and then
5948 the inverse distributive law to see if things simplify. This
5949 occurs mostly in addresses, often when unrolling loops. */
5951 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5953 rtx result
= distribute_and_simplify_rtx (x
, 0);
5958 /* Try simplify a*(b/c) as (a*b)/c. */
5959 if (FLOAT_MODE_P (mode
) && flag_associative_math
5960 && GET_CODE (XEXP (x
, 0)) == DIV
)
5962 rtx tem
= simplify_binary_operation (MULT
, mode
,
5963 XEXP (XEXP (x
, 0), 0),
5966 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5971 /* If this is a divide by a power of two, treat it as a shift if
5972 its first operand is a shift. */
5973 if (CONST_INT_P (XEXP (x
, 1))
5974 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5975 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5976 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5977 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5978 || GET_CODE (XEXP (x
, 0)) == ROTATE
5979 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5980 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5984 case GT
: case GTU
: case GE
: case GEU
:
5985 case LT
: case LTU
: case LE
: case LEU
:
5986 case UNEQ
: case LTGT
:
5987 case UNGT
: case UNGE
:
5988 case UNLT
: case UNLE
:
5989 case UNORDERED
: case ORDERED
:
5990 /* If the first operand is a condition code, we can't do anything
5992 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5993 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5994 && ! CC0_P (XEXP (x
, 0))))
5996 rtx op0
= XEXP (x
, 0);
5997 rtx op1
= XEXP (x
, 1);
5998 enum rtx_code new_code
;
6000 if (GET_CODE (op0
) == COMPARE
)
6001 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6003 /* Simplify our comparison, if possible. */
6004 new_code
= simplify_comparison (code
, &op0
, &op1
);
6006 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6007 if only the low-order bit is possibly nonzero in X (such as when
6008 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6009 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6010 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6013 Remove any ZERO_EXTRACT we made when thinking this was a
6014 comparison. It may now be simpler to use, e.g., an AND. If a
6015 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6016 the call to make_compound_operation in the SET case.
6018 Don't apply these optimizations if the caller would
6019 prefer a comparison rather than a value.
6020 E.g., for the condition in an IF_THEN_ELSE most targets need
6021 an explicit comparison. */
6026 else if (STORE_FLAG_VALUE
== 1
6027 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6028 && op1
== const0_rtx
6029 && mode
== GET_MODE (op0
)
6030 && nonzero_bits (op0
, mode
) == 1)
6031 return gen_lowpart (mode
,
6032 expand_compound_operation (op0
));
6034 else if (STORE_FLAG_VALUE
== 1
6035 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6036 && op1
== const0_rtx
6037 && mode
== GET_MODE (op0
)
6038 && (num_sign_bit_copies (op0
, mode
)
6039 == GET_MODE_PRECISION (mode
)))
6041 op0
= expand_compound_operation (op0
);
6042 return simplify_gen_unary (NEG
, mode
,
6043 gen_lowpart (mode
, op0
),
6047 else if (STORE_FLAG_VALUE
== 1
6048 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6049 && op1
== const0_rtx
6050 && mode
== GET_MODE (op0
)
6051 && nonzero_bits (op0
, mode
) == 1)
6053 op0
= expand_compound_operation (op0
);
6054 return simplify_gen_binary (XOR
, mode
,
6055 gen_lowpart (mode
, op0
),
6059 else if (STORE_FLAG_VALUE
== 1
6060 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6061 && op1
== const0_rtx
6062 && mode
== GET_MODE (op0
)
6063 && (num_sign_bit_copies (op0
, mode
)
6064 == GET_MODE_PRECISION (mode
)))
6066 op0
= expand_compound_operation (op0
);
6067 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6070 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6075 else if (STORE_FLAG_VALUE
== -1
6076 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6077 && op1
== const0_rtx
6078 && mode
== GET_MODE (op0
)
6079 && (num_sign_bit_copies (op0
, mode
)
6080 == GET_MODE_PRECISION (mode
)))
6081 return gen_lowpart (mode
,
6082 expand_compound_operation (op0
));
6084 else if (STORE_FLAG_VALUE
== -1
6085 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6086 && op1
== const0_rtx
6087 && mode
== GET_MODE (op0
)
6088 && nonzero_bits (op0
, mode
) == 1)
6090 op0
= expand_compound_operation (op0
);
6091 return simplify_gen_unary (NEG
, mode
,
6092 gen_lowpart (mode
, op0
),
6096 else if (STORE_FLAG_VALUE
== -1
6097 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6098 && op1
== const0_rtx
6099 && mode
== GET_MODE (op0
)
6100 && (num_sign_bit_copies (op0
, mode
)
6101 == GET_MODE_PRECISION (mode
)))
6103 op0
= expand_compound_operation (op0
);
6104 return simplify_gen_unary (NOT
, mode
,
6105 gen_lowpart (mode
, op0
),
6109 /* If X is 0/1, (eq X 0) is X-1. */
6110 else if (STORE_FLAG_VALUE
== -1
6111 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6112 && op1
== const0_rtx
6113 && mode
== GET_MODE (op0
)
6114 && nonzero_bits (op0
, mode
) == 1)
6116 op0
= expand_compound_operation (op0
);
6117 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6120 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6121 one bit that might be nonzero, we can convert (ne x 0) to
6122 (ashift x c) where C puts the bit in the sign bit. Remove any
6123 AND with STORE_FLAG_VALUE when we are done, since we are only
6124 going to test the sign bit. */
6125 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6126 && HWI_COMPUTABLE_MODE_P (mode
)
6127 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6128 && op1
== const0_rtx
6129 && mode
== GET_MODE (op0
)
6130 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6132 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6133 expand_compound_operation (op0
),
6134 GET_MODE_PRECISION (mode
) - 1 - i
);
6135 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6141 /* If the code changed, return a whole new comparison.
6142 We also need to avoid using SUBST in cases where
6143 simplify_comparison has widened a comparison with a CONST_INT,
6144 since in that case the wider CONST_INT may fail the sanity
6145 checks in do_SUBST. */
6146 if (new_code
!= code
6147 || (CONST_INT_P (op1
)
6148 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6149 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6150 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6152 /* Otherwise, keep this operation, but maybe change its operands.
6153 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6154 SUBST (XEXP (x
, 0), op0
);
6155 SUBST (XEXP (x
, 1), op1
);
6160 return simplify_if_then_else (x
);
6166 /* If we are processing SET_DEST, we are done. */
6170 return expand_compound_operation (x
);
6173 return simplify_set (x
);
6177 return simplify_logical (x
);
6184 /* If this is a shift by a constant amount, simplify it. */
6185 if (CONST_INT_P (XEXP (x
, 1)))
6186 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6187 INTVAL (XEXP (x
, 1)));
6189 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6191 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6192 ((unsigned HOST_WIDE_INT
) 1
6193 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6205 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6208 simplify_if_then_else (rtx x
)
6210 machine_mode mode
= GET_MODE (x
);
6211 rtx cond
= XEXP (x
, 0);
6212 rtx true_rtx
= XEXP (x
, 1);
6213 rtx false_rtx
= XEXP (x
, 2);
6214 enum rtx_code true_code
= GET_CODE (cond
);
6215 int comparison_p
= COMPARISON_P (cond
);
6218 enum rtx_code false_code
;
6221 /* Simplify storing of the truth value. */
6222 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6223 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6224 XEXP (cond
, 0), XEXP (cond
, 1));
6226 /* Also when the truth value has to be reversed. */
6228 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6229 && (reversed
= reversed_comparison (cond
, mode
)))
6232 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6233 in it is being compared against certain values. Get the true and false
6234 comparisons and see if that says anything about the value of each arm. */
6237 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6239 && REG_P (XEXP (cond
, 0)))
6242 rtx from
= XEXP (cond
, 0);
6243 rtx true_val
= XEXP (cond
, 1);
6244 rtx false_val
= true_val
;
6247 /* If FALSE_CODE is EQ, swap the codes and arms. */
6249 if (false_code
== EQ
)
6251 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6252 std::swap (true_rtx
, false_rtx
);
6255 /* If we are comparing against zero and the expression being tested has
6256 only a single bit that might be nonzero, that is its value when it is
6257 not equal to zero. Similarly if it is known to be -1 or 0. */
6259 if (true_code
== EQ
&& true_val
== const0_rtx
6260 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6263 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6265 else if (true_code
== EQ
&& true_val
== const0_rtx
6266 && (num_sign_bit_copies (from
, GET_MODE (from
))
6267 == GET_MODE_PRECISION (GET_MODE (from
))))
6270 false_val
= constm1_rtx
;
6273 /* Now simplify an arm if we know the value of the register in the
6274 branch and it is used in the arm. Be careful due to the potential
6275 of locally-shared RTL. */
6277 if (reg_mentioned_p (from
, true_rtx
))
6278 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6280 pc_rtx
, pc_rtx
, 0, 0, 0);
6281 if (reg_mentioned_p (from
, false_rtx
))
6282 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6284 pc_rtx
, pc_rtx
, 0, 0, 0);
6286 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6287 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6289 true_rtx
= XEXP (x
, 1);
6290 false_rtx
= XEXP (x
, 2);
6291 true_code
= GET_CODE (cond
);
6294 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6295 reversed, do so to avoid needing two sets of patterns for
6296 subtract-and-branch insns. Similarly if we have a constant in the true
6297 arm, the false arm is the same as the first operand of the comparison, or
6298 the false arm is more complicated than the true arm. */
6301 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6302 && (true_rtx
== pc_rtx
6303 || (CONSTANT_P (true_rtx
)
6304 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6305 || true_rtx
== const0_rtx
6306 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6307 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6308 && !OBJECT_P (false_rtx
))
6309 || reg_mentioned_p (true_rtx
, false_rtx
)
6310 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6312 true_code
= reversed_comparison_code (cond
, NULL
);
6313 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6314 SUBST (XEXP (x
, 1), false_rtx
);
6315 SUBST (XEXP (x
, 2), true_rtx
);
6317 std::swap (true_rtx
, false_rtx
);
6320 /* It is possible that the conditional has been simplified out. */
6321 true_code
= GET_CODE (cond
);
6322 comparison_p
= COMPARISON_P (cond
);
6325 /* If the two arms are identical, we don't need the comparison. */
6327 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6330 /* Convert a == b ? b : a to "a". */
6331 if (true_code
== EQ
&& ! side_effects_p (cond
)
6332 && !HONOR_NANS (mode
)
6333 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6334 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6336 else if (true_code
== NE
&& ! side_effects_p (cond
)
6337 && !HONOR_NANS (mode
)
6338 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6339 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6342 /* Look for cases where we have (abs x) or (neg (abs X)). */
6344 if (GET_MODE_CLASS (mode
) == MODE_INT
6346 && XEXP (cond
, 1) == const0_rtx
6347 && GET_CODE (false_rtx
) == NEG
6348 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6349 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6350 && ! side_effects_p (true_rtx
))
6355 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6359 simplify_gen_unary (NEG
, mode
,
6360 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6366 /* Look for MIN or MAX. */
6368 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6370 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6371 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6372 && ! side_effects_p (cond
))
6377 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6380 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6383 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6386 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6391 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6392 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6393 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6394 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6395 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6396 neither 1 or -1, but it isn't worth checking for. */
6398 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6400 && GET_MODE_CLASS (mode
) == MODE_INT
6401 && ! side_effects_p (x
))
6403 rtx t
= make_compound_operation (true_rtx
, SET
);
6404 rtx f
= make_compound_operation (false_rtx
, SET
);
6405 rtx cond_op0
= XEXP (cond
, 0);
6406 rtx cond_op1
= XEXP (cond
, 1);
6407 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6408 machine_mode m
= mode
;
6409 rtx z
= 0, c1
= NULL_RTX
;
6411 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6412 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6413 || GET_CODE (t
) == ASHIFT
6414 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6415 && rtx_equal_p (XEXP (t
, 0), f
))
6416 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6418 /* If an identity-zero op is commutative, check whether there
6419 would be a match if we swapped the operands. */
6420 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6421 || GET_CODE (t
) == XOR
)
6422 && rtx_equal_p (XEXP (t
, 1), f
))
6423 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6424 else if (GET_CODE (t
) == SIGN_EXTEND
6425 && (GET_CODE (XEXP (t
, 0)) == PLUS
6426 || GET_CODE (XEXP (t
, 0)) == MINUS
6427 || GET_CODE (XEXP (t
, 0)) == IOR
6428 || GET_CODE (XEXP (t
, 0)) == XOR
6429 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6430 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6431 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6432 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6433 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6434 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6435 && (num_sign_bit_copies (f
, GET_MODE (f
))
6437 (GET_MODE_PRECISION (mode
)
6438 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6440 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6441 extend_op
= SIGN_EXTEND
;
6442 m
= GET_MODE (XEXP (t
, 0));
6444 else if (GET_CODE (t
) == SIGN_EXTEND
6445 && (GET_CODE (XEXP (t
, 0)) == PLUS
6446 || GET_CODE (XEXP (t
, 0)) == IOR
6447 || GET_CODE (XEXP (t
, 0)) == XOR
)
6448 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6449 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6450 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6451 && (num_sign_bit_copies (f
, GET_MODE (f
))
6453 (GET_MODE_PRECISION (mode
)
6454 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6456 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6457 extend_op
= SIGN_EXTEND
;
6458 m
= GET_MODE (XEXP (t
, 0));
6460 else if (GET_CODE (t
) == ZERO_EXTEND
6461 && (GET_CODE (XEXP (t
, 0)) == PLUS
6462 || GET_CODE (XEXP (t
, 0)) == MINUS
6463 || GET_CODE (XEXP (t
, 0)) == IOR
6464 || GET_CODE (XEXP (t
, 0)) == XOR
6465 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6466 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6467 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6468 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6469 && HWI_COMPUTABLE_MODE_P (mode
)
6470 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6471 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6472 && ((nonzero_bits (f
, GET_MODE (f
))
6473 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6476 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6477 extend_op
= ZERO_EXTEND
;
6478 m
= GET_MODE (XEXP (t
, 0));
6480 else if (GET_CODE (t
) == ZERO_EXTEND
6481 && (GET_CODE (XEXP (t
, 0)) == PLUS
6482 || GET_CODE (XEXP (t
, 0)) == IOR
6483 || GET_CODE (XEXP (t
, 0)) == XOR
)
6484 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6485 && HWI_COMPUTABLE_MODE_P (mode
)
6486 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6487 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6488 && ((nonzero_bits (f
, GET_MODE (f
))
6489 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6492 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6493 extend_op
= ZERO_EXTEND
;
6494 m
= GET_MODE (XEXP (t
, 0));
6499 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6500 cond_op0
, cond_op1
),
6501 pc_rtx
, pc_rtx
, 0, 0, 0);
6502 temp
= simplify_gen_binary (MULT
, m
, temp
,
6503 simplify_gen_binary (MULT
, m
, c1
,
6505 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6506 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6508 if (extend_op
!= UNKNOWN
)
6509 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6515 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6516 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6517 negation of a single bit, we can convert this operation to a shift. We
6518 can actually do this more generally, but it doesn't seem worth it. */
6520 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6521 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6522 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6523 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6524 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6525 == GET_MODE_PRECISION (mode
))
6526 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6528 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6529 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6531 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6532 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6533 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6534 && GET_MODE (XEXP (cond
, 0)) == mode
6535 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6536 == nonzero_bits (XEXP (cond
, 0), mode
)
6537 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6538 return XEXP (cond
, 0);
6543 /* Simplify X, a SET expression. Return the new expression. */
6546 simplify_set (rtx x
)
6548 rtx src
= SET_SRC (x
);
6549 rtx dest
= SET_DEST (x
);
6551 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6552 rtx_insn
*other_insn
;
6555 /* (set (pc) (return)) gets written as (return). */
6556 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6559 /* Now that we know for sure which bits of SRC we are using, see if we can
6560 simplify the expression for the object knowing that we only need the
6563 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6565 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6566 SUBST (SET_SRC (x
), src
);
6569 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6570 the comparison result and try to simplify it unless we already have used
6571 undobuf.other_insn. */
6572 if ((GET_MODE_CLASS (mode
) == MODE_CC
6573 || GET_CODE (src
) == COMPARE
6575 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6576 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6577 && COMPARISON_P (*cc_use
)
6578 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6580 enum rtx_code old_code
= GET_CODE (*cc_use
);
6581 enum rtx_code new_code
;
6583 int other_changed
= 0;
6584 rtx inner_compare
= NULL_RTX
;
6585 machine_mode compare_mode
= GET_MODE (dest
);
6587 if (GET_CODE (src
) == COMPARE
)
6589 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6590 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6592 inner_compare
= op0
;
6593 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6597 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6599 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6602 new_code
= old_code
;
6603 else if (!CONSTANT_P (tmp
))
6605 new_code
= GET_CODE (tmp
);
6606 op0
= XEXP (tmp
, 0);
6607 op1
= XEXP (tmp
, 1);
6611 rtx pat
= PATTERN (other_insn
);
6612 undobuf
.other_insn
= other_insn
;
6613 SUBST (*cc_use
, tmp
);
6615 /* Attempt to simplify CC user. */
6616 if (GET_CODE (pat
) == SET
)
6618 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6619 if (new_rtx
!= NULL_RTX
)
6620 SUBST (SET_SRC (pat
), new_rtx
);
6623 /* Convert X into a no-op move. */
6624 SUBST (SET_DEST (x
), pc_rtx
);
6625 SUBST (SET_SRC (x
), pc_rtx
);
6629 /* Simplify our comparison, if possible. */
6630 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6632 #ifdef SELECT_CC_MODE
6633 /* If this machine has CC modes other than CCmode, check to see if we
6634 need to use a different CC mode here. */
6635 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6636 compare_mode
= GET_MODE (op0
);
6637 else if (inner_compare
6638 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6639 && new_code
== old_code
6640 && op0
== XEXP (inner_compare
, 0)
6641 && op1
== XEXP (inner_compare
, 1))
6642 compare_mode
= GET_MODE (inner_compare
);
6644 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6646 /* If the mode changed, we have to change SET_DEST, the mode in the
6647 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6648 a hard register, just build new versions with the proper mode. If it
6649 is a pseudo, we lose unless it is only time we set the pseudo, in
6650 which case we can safely change its mode. */
6651 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6653 if (can_change_dest_mode (dest
, 0, compare_mode
))
6655 unsigned int regno
= REGNO (dest
);
6658 if (regno
< FIRST_PSEUDO_REGISTER
)
6659 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6662 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6663 new_dest
= regno_reg_rtx
[regno
];
6666 SUBST (SET_DEST (x
), new_dest
);
6667 SUBST (XEXP (*cc_use
, 0), new_dest
);
6673 #endif /* SELECT_CC_MODE */
6675 /* If the code changed, we have to build a new comparison in
6676 undobuf.other_insn. */
6677 if (new_code
!= old_code
)
6679 int other_changed_previously
= other_changed
;
6680 unsigned HOST_WIDE_INT mask
;
6681 rtx old_cc_use
= *cc_use
;
6683 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6687 /* If the only change we made was to change an EQ into an NE or
6688 vice versa, OP0 has only one bit that might be nonzero, and OP1
6689 is zero, check if changing the user of the condition code will
6690 produce a valid insn. If it won't, we can keep the original code
6691 in that insn by surrounding our operation with an XOR. */
6693 if (((old_code
== NE
&& new_code
== EQ
)
6694 || (old_code
== EQ
&& new_code
== NE
))
6695 && ! other_changed_previously
&& op1
== const0_rtx
6696 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6697 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6699 rtx pat
= PATTERN (other_insn
), note
= 0;
6701 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6702 && ! check_asm_operands (pat
)))
6704 *cc_use
= old_cc_use
;
6707 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6715 undobuf
.other_insn
= other_insn
;
6717 /* Don't generate a compare of a CC with 0, just use that CC. */
6718 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6720 SUBST (SET_SRC (x
), op0
);
6723 /* Otherwise, if we didn't previously have the same COMPARE we
6724 want, create it from scratch. */
6725 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6726 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6728 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6734 /* Get SET_SRC in a form where we have placed back any
6735 compound expressions. Then do the checks below. */
6736 src
= make_compound_operation (src
, SET
);
6737 SUBST (SET_SRC (x
), src
);
6740 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6741 and X being a REG or (subreg (reg)), we may be able to convert this to
6742 (set (subreg:m2 x) (op)).
6744 We can always do this if M1 is narrower than M2 because that means that
6745 we only care about the low bits of the result.
6747 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6748 perform a narrower operation than requested since the high-order bits will
6749 be undefined. On machine where it is defined, this transformation is safe
6750 as long as M1 and M2 have the same number of words. */
6752 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6753 && !OBJECT_P (SUBREG_REG (src
))
6754 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6756 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6757 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6758 #ifndef WORD_REGISTER_OPERATIONS
6759 && (GET_MODE_SIZE (GET_MODE (src
))
6760 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6762 #ifdef CANNOT_CHANGE_MODE_CLASS
6763 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6764 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6765 GET_MODE (SUBREG_REG (src
)),
6769 || (GET_CODE (dest
) == SUBREG
6770 && REG_P (SUBREG_REG (dest
)))))
6772 SUBST (SET_DEST (x
),
6773 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6775 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6777 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6780 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6783 && GET_CODE (src
) == SUBREG
6784 && subreg_lowpart_p (src
)
6785 && (GET_MODE_PRECISION (GET_MODE (src
))
6786 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6788 rtx inner
= SUBREG_REG (src
);
6789 machine_mode inner_mode
= GET_MODE (inner
);
6791 /* Here we make sure that we don't have a sign bit on. */
6792 if (val_signbit_known_clear_p (GET_MODE (src
),
6793 nonzero_bits (inner
, inner_mode
)))
6795 SUBST (SET_SRC (x
), inner
);
6800 #ifdef LOAD_EXTEND_OP
6801 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6802 would require a paradoxical subreg. Replace the subreg with a
6803 zero_extend to avoid the reload that would otherwise be required. */
6805 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6806 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6807 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6808 && SUBREG_BYTE (src
) == 0
6809 && paradoxical_subreg_p (src
)
6810 && MEM_P (SUBREG_REG (src
)))
6813 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6814 GET_MODE (src
), SUBREG_REG (src
)));
6820 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6821 are comparing an item known to be 0 or -1 against 0, use a logical
6822 operation instead. Check for one of the arms being an IOR of the other
6823 arm with some value. We compute three terms to be IOR'ed together. In
6824 practice, at most two will be nonzero. Then we do the IOR's. */
6826 if (GET_CODE (dest
) != PC
6827 && GET_CODE (src
) == IF_THEN_ELSE
6828 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6829 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6830 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6831 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6832 && (!HAVE_conditional_move
6833 || ! can_conditionally_move_p (GET_MODE (src
)))
6834 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6835 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6836 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6837 && ! side_effects_p (src
))
6839 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6840 ? XEXP (src
, 1) : XEXP (src
, 2));
6841 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6842 ? XEXP (src
, 2) : XEXP (src
, 1));
6843 rtx term1
= const0_rtx
, term2
, term3
;
6845 if (GET_CODE (true_rtx
) == IOR
6846 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6847 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6848 else if (GET_CODE (true_rtx
) == IOR
6849 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6850 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6851 else if (GET_CODE (false_rtx
) == IOR
6852 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6853 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6854 else if (GET_CODE (false_rtx
) == IOR
6855 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6856 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6858 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6859 XEXP (XEXP (src
, 0), 0), true_rtx
);
6860 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6861 simplify_gen_unary (NOT
, GET_MODE (src
),
6862 XEXP (XEXP (src
, 0), 0),
6867 simplify_gen_binary (IOR
, GET_MODE (src
),
6868 simplify_gen_binary (IOR
, GET_MODE (src
),
6875 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6876 whole thing fail. */
6877 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6879 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6882 /* Convert this into a field assignment operation, if possible. */
6883 return make_field_assignment (x
);
6886 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6890 simplify_logical (rtx x
)
6892 machine_mode mode
= GET_MODE (x
);
6893 rtx op0
= XEXP (x
, 0);
6894 rtx op1
= XEXP (x
, 1);
6896 switch (GET_CODE (x
))
6899 /* We can call simplify_and_const_int only if we don't lose
6900 any (sign) bits when converting INTVAL (op1) to
6901 "unsigned HOST_WIDE_INT". */
6902 if (CONST_INT_P (op1
)
6903 && (HWI_COMPUTABLE_MODE_P (mode
)
6904 || INTVAL (op1
) > 0))
6906 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6907 if (GET_CODE (x
) != AND
)
6914 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6915 apply the distributive law and then the inverse distributive
6916 law to see if things simplify. */
6917 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6919 rtx result
= distribute_and_simplify_rtx (x
, 0);
6923 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6925 rtx result
= distribute_and_simplify_rtx (x
, 1);
6932 /* If we have (ior (and A B) C), apply the distributive law and then
6933 the inverse distributive law to see if things simplify. */
6935 if (GET_CODE (op0
) == AND
)
6937 rtx result
= distribute_and_simplify_rtx (x
, 0);
6942 if (GET_CODE (op1
) == AND
)
6944 rtx result
= distribute_and_simplify_rtx (x
, 1);
6957 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6958 operations" because they can be replaced with two more basic operations.
6959 ZERO_EXTEND is also considered "compound" because it can be replaced with
6960 an AND operation, which is simpler, though only one operation.
6962 The function expand_compound_operation is called with an rtx expression
6963 and will convert it to the appropriate shifts and AND operations,
6964 simplifying at each stage.
6966 The function make_compound_operation is called to convert an expression
6967 consisting of shifts and ANDs into the equivalent compound expression.
6968 It is the inverse of this function, loosely speaking. */
6971 expand_compound_operation (rtx x
)
6973 unsigned HOST_WIDE_INT pos
= 0, len
;
6975 unsigned int modewidth
;
6978 switch (GET_CODE (x
))
6983 /* We can't necessarily use a const_int for a multiword mode;
6984 it depends on implicitly extending the value.
6985 Since we don't know the right way to extend it,
6986 we can't tell whether the implicit way is right.
6988 Even for a mode that is no wider than a const_int,
6989 we can't win, because we need to sign extend one of its bits through
6990 the rest of it, and we don't know which bit. */
6991 if (CONST_INT_P (XEXP (x
, 0)))
6994 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6995 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6996 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6997 reloaded. If not for that, MEM's would very rarely be safe.
6999 Reject MODEs bigger than a word, because we might not be able
7000 to reference a two-register group starting with an arbitrary register
7001 (and currently gen_lowpart might crash for a SUBREG). */
7003 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
7006 /* Reject MODEs that aren't scalar integers because turning vector
7007 or complex modes into shifts causes problems. */
7009 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7012 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
7013 /* If the inner object has VOIDmode (the only way this can happen
7014 is if it is an ASM_OPERANDS), we can't do anything since we don't
7015 know how much masking to do. */
7024 /* ... fall through ... */
7027 /* If the operand is a CLOBBER, just return it. */
7028 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7031 if (!CONST_INT_P (XEXP (x
, 1))
7032 || !CONST_INT_P (XEXP (x
, 2))
7033 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7036 /* Reject MODEs that aren't scalar integers because turning vector
7037 or complex modes into shifts causes problems. */
7039 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7042 len
= INTVAL (XEXP (x
, 1));
7043 pos
= INTVAL (XEXP (x
, 2));
7045 /* This should stay within the object being extracted, fail otherwise. */
7046 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7049 if (BITS_BIG_ENDIAN
)
7050 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7057 /* Convert sign extension to zero extension, if we know that the high
7058 bit is not set, as this is easier to optimize. It will be converted
7059 back to cheaper alternative in make_extraction. */
7060 if (GET_CODE (x
) == SIGN_EXTEND
7061 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7062 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7063 & ~(((unsigned HOST_WIDE_INT
)
7064 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7068 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
7069 rtx temp2
= expand_compound_operation (temp
);
7071 /* Make sure this is a profitable operation. */
7072 if (set_src_cost (x
, optimize_this_for_speed_p
)
7073 > set_src_cost (temp2
, optimize_this_for_speed_p
))
7075 else if (set_src_cost (x
, optimize_this_for_speed_p
)
7076 > set_src_cost (temp
, optimize_this_for_speed_p
))
7082 /* We can optimize some special cases of ZERO_EXTEND. */
7083 if (GET_CODE (x
) == ZERO_EXTEND
)
7085 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7086 know that the last value didn't have any inappropriate bits
7088 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7089 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7090 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7091 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7092 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7093 return XEXP (XEXP (x
, 0), 0);
7095 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7096 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7097 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7098 && subreg_lowpart_p (XEXP (x
, 0))
7099 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7100 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7101 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7102 return SUBREG_REG (XEXP (x
, 0));
7104 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7105 is a comparison and STORE_FLAG_VALUE permits. This is like
7106 the first case, but it works even when GET_MODE (x) is larger
7107 than HOST_WIDE_INT. */
7108 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7109 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7110 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7111 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7112 <= HOST_BITS_PER_WIDE_INT
)
7113 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7114 return XEXP (XEXP (x
, 0), 0);
7116 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7117 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7118 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7119 && subreg_lowpart_p (XEXP (x
, 0))
7120 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7121 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7122 <= HOST_BITS_PER_WIDE_INT
)
7123 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7124 return SUBREG_REG (XEXP (x
, 0));
7128 /* If we reach here, we want to return a pair of shifts. The inner
7129 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7130 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7131 logical depending on the value of UNSIGNEDP.
7133 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7134 converted into an AND of a shift.
7136 We must check for the case where the left shift would have a negative
7137 count. This can happen in a case like (x >> 31) & 255 on machines
7138 that can't shift by a constant. On those machines, we would first
7139 combine the shift with the AND to produce a variable-position
7140 extraction. Then the constant of 31 would be substituted in
7141 to produce such a position. */
7143 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7144 if (modewidth
>= pos
+ len
)
7146 machine_mode mode
= GET_MODE (x
);
7147 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7148 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7150 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7151 tem
, modewidth
- pos
- len
);
7152 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7153 mode
, tem
, modewidth
- len
);
7155 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7156 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7157 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7160 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7162 /* Any other cases we can't handle. */
7165 /* If we couldn't do this for some reason, return the original
7167 if (GET_CODE (tem
) == CLOBBER
)
7173 /* X is a SET which contains an assignment of one object into
7174 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7175 or certain SUBREGS). If possible, convert it into a series of
7178 We half-heartedly support variable positions, but do not at all
7179 support variable lengths. */
7182 expand_field_assignment (const_rtx x
)
7185 rtx pos
; /* Always counts from low bit. */
7187 rtx mask
, cleared
, masked
;
7188 machine_mode compute_mode
;
7190 /* Loop until we find something we can't simplify. */
7193 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7194 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7196 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7197 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7198 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7200 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7201 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7203 inner
= XEXP (SET_DEST (x
), 0);
7204 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7205 pos
= XEXP (SET_DEST (x
), 2);
7207 /* A constant position should stay within the width of INNER. */
7208 if (CONST_INT_P (pos
)
7209 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7212 if (BITS_BIG_ENDIAN
)
7214 if (CONST_INT_P (pos
))
7215 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7217 else if (GET_CODE (pos
) == MINUS
7218 && CONST_INT_P (XEXP (pos
, 1))
7219 && (INTVAL (XEXP (pos
, 1))
7220 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7221 /* If position is ADJUST - X, new position is X. */
7222 pos
= XEXP (pos
, 0);
7225 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7226 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7227 gen_int_mode (prec
- len
,
7234 /* A SUBREG between two modes that occupy the same numbers of words
7235 can be done by moving the SUBREG to the source. */
7236 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7237 /* We need SUBREGs to compute nonzero_bits properly. */
7238 && nonzero_sign_valid
7239 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7240 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7241 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7242 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7244 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7246 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7253 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7254 inner
= SUBREG_REG (inner
);
7256 compute_mode
= GET_MODE (inner
);
7258 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7259 if (! SCALAR_INT_MODE_P (compute_mode
))
7263 /* Don't do anything for vector or complex integral types. */
7264 if (! FLOAT_MODE_P (compute_mode
))
7267 /* Try to find an integral mode to pun with. */
7268 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7269 if (imode
== BLKmode
)
7272 compute_mode
= imode
;
7273 inner
= gen_lowpart (imode
, inner
);
7276 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7277 if (len
>= HOST_BITS_PER_WIDE_INT
)
7280 /* Now compute the equivalent expression. Make a copy of INNER
7281 for the SET_DEST in case it is a MEM into which we will substitute;
7282 we don't want shared RTL in that case. */
7283 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7285 cleared
= simplify_gen_binary (AND
, compute_mode
,
7286 simplify_gen_unary (NOT
, compute_mode
,
7287 simplify_gen_binary (ASHIFT
,
7292 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7293 simplify_gen_binary (
7295 gen_lowpart (compute_mode
, SET_SRC (x
)),
7299 x
= gen_rtx_SET (copy_rtx (inner
),
7300 simplify_gen_binary (IOR
, compute_mode
,
7307 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7308 it is an RTX that represents the (variable) starting position; otherwise,
7309 POS is the (constant) starting bit position. Both are counted from the LSB.
7311 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7313 IN_DEST is nonzero if this is a reference in the destination of a SET.
7314 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7315 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7318 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7319 ZERO_EXTRACT should be built even for bits starting at bit 0.
7321 MODE is the desired mode of the result (if IN_DEST == 0).
7323 The result is an RTX for the extraction or NULL_RTX if the target
7327 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7328 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7329 int in_dest
, int in_compare
)
7331 /* This mode describes the size of the storage area
7332 to fetch the overall value from. Within that, we
7333 ignore the POS lowest bits, etc. */
7334 machine_mode is_mode
= GET_MODE (inner
);
7335 machine_mode inner_mode
;
7336 machine_mode wanted_inner_mode
;
7337 machine_mode wanted_inner_reg_mode
= word_mode
;
7338 machine_mode pos_mode
= word_mode
;
7339 machine_mode extraction_mode
= word_mode
;
7340 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7342 rtx orig_pos_rtx
= pos_rtx
;
7343 HOST_WIDE_INT orig_pos
;
7345 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7346 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7348 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7350 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7351 consider just the QI as the memory to extract from.
7352 The subreg adds or removes high bits; its mode is
7353 irrelevant to the meaning of this extraction,
7354 since POS and LEN count from the lsb. */
7355 if (MEM_P (SUBREG_REG (inner
)))
7356 is_mode
= GET_MODE (SUBREG_REG (inner
));
7357 inner
= SUBREG_REG (inner
);
7359 else if (GET_CODE (inner
) == ASHIFT
7360 && CONST_INT_P (XEXP (inner
, 1))
7361 && pos_rtx
== 0 && pos
== 0
7362 && len
> UINTVAL (XEXP (inner
, 1)))
7364 /* We're extracting the least significant bits of an rtx
7365 (ashift X (const_int C)), where LEN > C. Extract the
7366 least significant (LEN - C) bits of X, giving an rtx
7367 whose mode is MODE, then shift it left C times. */
7368 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7369 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7370 unsignedp
, in_dest
, in_compare
);
7372 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7374 else if (GET_CODE (inner
) == TRUNCATE
)
7375 inner
= XEXP (inner
, 0);
7377 inner_mode
= GET_MODE (inner
);
7379 /* See if this can be done without an extraction. We never can if the
7380 width of the field is not the same as that of some integer mode. For
7381 registers, we can only avoid the extraction if the position is at the
7382 low-order bit and this is either not in the destination or we have the
7383 appropriate STRICT_LOW_PART operation available.
7385 For MEM, we can avoid an extract if the field starts on an appropriate
7386 boundary and we can change the mode of the memory reference. */
7388 if (tmode
!= BLKmode
7389 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7391 && (inner_mode
== tmode
7393 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7394 || reg_truncated_to_mode (tmode
, inner
))
7397 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7398 || (MEM_P (inner
) && pos_rtx
== 0
7400 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7401 : BITS_PER_UNIT
)) == 0
7402 /* We can't do this if we are widening INNER_MODE (it
7403 may not be aligned, for one thing). */
7404 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7405 && (inner_mode
== tmode
7406 || (! mode_dependent_address_p (XEXP (inner
, 0),
7407 MEM_ADDR_SPACE (inner
))
7408 && ! MEM_VOLATILE_P (inner
))))))
7410 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7411 field. If the original and current mode are the same, we need not
7412 adjust the offset. Otherwise, we do if bytes big endian.
7414 If INNER is not a MEM, get a piece consisting of just the field
7415 of interest (in this case POS % BITS_PER_WORD must be 0). */
7419 HOST_WIDE_INT offset
;
7421 /* POS counts from lsb, but make OFFSET count in memory order. */
7422 if (BYTES_BIG_ENDIAN
)
7423 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7425 offset
= pos
/ BITS_PER_UNIT
;
7427 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7429 else if (REG_P (inner
))
7431 if (tmode
!= inner_mode
)
7433 /* We can't call gen_lowpart in a DEST since we
7434 always want a SUBREG (see below) and it would sometimes
7435 return a new hard register. */
7438 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7440 if (WORDS_BIG_ENDIAN
7441 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7442 final_word
= ((GET_MODE_SIZE (inner_mode
)
7443 - GET_MODE_SIZE (tmode
))
7444 / UNITS_PER_WORD
) - final_word
;
7446 final_word
*= UNITS_PER_WORD
;
7447 if (BYTES_BIG_ENDIAN
&&
7448 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7449 final_word
+= (GET_MODE_SIZE (inner_mode
)
7450 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7452 /* Avoid creating invalid subregs, for example when
7453 simplifying (x>>32)&255. */
7454 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7457 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7460 new_rtx
= gen_lowpart (tmode
, inner
);
7466 new_rtx
= force_to_mode (inner
, tmode
,
7467 len
>= HOST_BITS_PER_WIDE_INT
7468 ? ~(unsigned HOST_WIDE_INT
) 0
7469 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7472 /* If this extraction is going into the destination of a SET,
7473 make a STRICT_LOW_PART unless we made a MEM. */
7476 return (MEM_P (new_rtx
) ? new_rtx
7477 : (GET_CODE (new_rtx
) != SUBREG
7478 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7479 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7484 if (CONST_SCALAR_INT_P (new_rtx
))
7485 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7486 mode
, new_rtx
, tmode
);
7488 /* If we know that no extraneous bits are set, and that the high
7489 bit is not set, convert the extraction to the cheaper of
7490 sign and zero extension, that are equivalent in these cases. */
7491 if (flag_expensive_optimizations
7492 && (HWI_COMPUTABLE_MODE_P (tmode
)
7493 && ((nonzero_bits (new_rtx
, tmode
)
7494 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7497 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7498 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7500 /* Prefer ZERO_EXTENSION, since it gives more information to
7502 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7503 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7508 /* Otherwise, sign- or zero-extend unless we already are in the
7511 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7515 /* Unless this is a COMPARE or we have a funny memory reference,
7516 don't do anything with zero-extending field extracts starting at
7517 the low-order bit since they are simple AND operations. */
7518 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7519 && ! in_compare
&& unsignedp
)
7522 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7523 if the position is not a constant and the length is not 1. In all
7524 other cases, we would only be going outside our object in cases when
7525 an original shift would have been undefined. */
7527 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7528 || (pos_rtx
!= 0 && len
!= 1)))
7531 enum extraction_pattern pattern
= (in_dest
? EP_insv
7532 : unsignedp
? EP_extzv
: EP_extv
);
7534 /* If INNER is not from memory, we want it to have the mode of a register
7535 extraction pattern's structure operand, or word_mode if there is no
7536 such pattern. The same applies to extraction_mode and pos_mode
7537 and their respective operands.
7539 For memory, assume that the desired extraction_mode and pos_mode
7540 are the same as for a register operation, since at present we don't
7541 have named patterns for aligned memory structures. */
7542 struct extraction_insn insn
;
7543 if (get_best_reg_extraction_insn (&insn
, pattern
,
7544 GET_MODE_BITSIZE (inner_mode
), mode
))
7546 wanted_inner_reg_mode
= insn
.struct_mode
;
7547 pos_mode
= insn
.pos_mode
;
7548 extraction_mode
= insn
.field_mode
;
7551 /* Never narrow an object, since that might not be safe. */
7553 if (mode
!= VOIDmode
7554 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7555 extraction_mode
= mode
;
7558 wanted_inner_mode
= wanted_inner_reg_mode
;
7561 /* Be careful not to go beyond the extracted object and maintain the
7562 natural alignment of the memory. */
7563 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7564 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7565 > GET_MODE_BITSIZE (wanted_inner_mode
))
7567 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7568 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7574 if (BITS_BIG_ENDIAN
)
7576 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7577 BITS_BIG_ENDIAN style. If position is constant, compute new
7578 position. Otherwise, build subtraction.
7579 Note that POS is relative to the mode of the original argument.
7580 If it's a MEM we need to recompute POS relative to that.
7581 However, if we're extracting from (or inserting into) a register,
7582 we want to recompute POS relative to wanted_inner_mode. */
7583 int width
= (MEM_P (inner
)
7584 ? GET_MODE_BITSIZE (is_mode
)
7585 : GET_MODE_BITSIZE (wanted_inner_mode
));
7588 pos
= width
- len
- pos
;
7591 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7592 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7594 /* POS may be less than 0 now, but we check for that below.
7595 Note that it can only be less than 0 if !MEM_P (inner). */
7598 /* If INNER has a wider mode, and this is a constant extraction, try to
7599 make it smaller and adjust the byte to point to the byte containing
7601 if (wanted_inner_mode
!= VOIDmode
7602 && inner_mode
!= wanted_inner_mode
7604 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7606 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7607 && ! MEM_VOLATILE_P (inner
))
7611 /* The computations below will be correct if the machine is big
7612 endian in both bits and bytes or little endian in bits and bytes.
7613 If it is mixed, we must adjust. */
7615 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7616 adjust OFFSET to compensate. */
7617 if (BYTES_BIG_ENDIAN
7618 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7619 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7621 /* We can now move to the desired byte. */
7622 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7623 * GET_MODE_SIZE (wanted_inner_mode
);
7624 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7626 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7627 && is_mode
!= wanted_inner_mode
)
7628 offset
= (GET_MODE_SIZE (is_mode
)
7629 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7631 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7634 /* If INNER is not memory, get it into the proper mode. If we are changing
7635 its mode, POS must be a constant and smaller than the size of the new
7637 else if (!MEM_P (inner
))
7639 /* On the LHS, don't create paradoxical subregs implicitely truncating
7640 the register unless TRULY_NOOP_TRUNCATION. */
7642 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7646 if (GET_MODE (inner
) != wanted_inner_mode
7648 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7654 inner
= force_to_mode (inner
, wanted_inner_mode
,
7656 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7657 ? ~(unsigned HOST_WIDE_INT
) 0
7658 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7663 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7664 have to zero extend. Otherwise, we can just use a SUBREG. */
7666 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7668 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7669 GET_MODE (pos_rtx
));
7671 /* If we know that no extraneous bits are set, and that the high
7672 bit is not set, convert extraction to cheaper one - either
7673 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7675 if (flag_expensive_optimizations
7676 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7677 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7678 & ~(((unsigned HOST_WIDE_INT
)
7679 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7683 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7684 GET_MODE (pos_rtx
));
7686 /* Prefer ZERO_EXTENSION, since it gives more information to
7688 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7689 < set_src_cost (temp
, optimize_this_for_speed_p
))
7695 /* Make POS_RTX unless we already have it and it is correct. If we don't
7696 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7698 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7699 pos_rtx
= orig_pos_rtx
;
7701 else if (pos_rtx
== 0)
7702 pos_rtx
= GEN_INT (pos
);
7704 /* Make the required operation. See if we can use existing rtx. */
7705 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7706 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7708 new_rtx
= gen_lowpart (mode
, new_rtx
);
7713 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7714 with any other operations in X. Return X without that shift if so. */
7717 extract_left_shift (rtx x
, int count
)
7719 enum rtx_code code
= GET_CODE (x
);
7720 machine_mode mode
= GET_MODE (x
);
7726 /* This is the shift itself. If it is wide enough, we will return
7727 either the value being shifted if the shift count is equal to
7728 COUNT or a shift for the difference. */
7729 if (CONST_INT_P (XEXP (x
, 1))
7730 && INTVAL (XEXP (x
, 1)) >= count
)
7731 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7732 INTVAL (XEXP (x
, 1)) - count
);
7736 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7737 return simplify_gen_unary (code
, mode
, tem
, mode
);
7741 case PLUS
: case IOR
: case XOR
: case AND
:
7742 /* If we can safely shift this constant and we find the inner shift,
7743 make a new operation. */
7744 if (CONST_INT_P (XEXP (x
, 1))
7745 && (UINTVAL (XEXP (x
, 1))
7746 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7747 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7749 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7750 return simplify_gen_binary (code
, mode
, tem
,
7751 gen_int_mode (val
, mode
));
7762 /* Look at the expression rooted at X. Look for expressions
7763 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7764 Form these expressions.
7766 Return the new rtx, usually just X.
7768 Also, for machines like the VAX that don't have logical shift insns,
7769 try to convert logical to arithmetic shift operations in cases where
7770 they are equivalent. This undoes the canonicalizations to logical
7771 shifts done elsewhere.
7773 We try, as much as possible, to re-use rtl expressions to save memory.
7775 IN_CODE says what kind of expression we are processing. Normally, it is
7776 SET. In a memory address it is MEM. When processing the arguments of
7777 a comparison or a COMPARE against zero, it is COMPARE. */
7780 make_compound_operation (rtx x
, enum rtx_code in_code
)
7782 enum rtx_code code
= GET_CODE (x
);
7783 machine_mode mode
= GET_MODE (x
);
7784 int mode_width
= GET_MODE_PRECISION (mode
);
7786 enum rtx_code next_code
;
7792 /* Select the code to be used in recursive calls. Once we are inside an
7793 address, we stay there. If we have a comparison, set to COMPARE,
7794 but once inside, go back to our default of SET. */
7796 next_code
= (code
== MEM
? MEM
7797 : ((code
== COMPARE
|| COMPARISON_P (x
))
7798 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7799 : in_code
== COMPARE
? SET
: in_code
);
7801 /* Process depending on the code of this operation. If NEW is set
7802 nonzero, it will be returned. */
7807 /* Convert shifts by constants into multiplications if inside
7809 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7810 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7811 && INTVAL (XEXP (x
, 1)) >= 0
7812 && SCALAR_INT_MODE_P (mode
))
7814 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7815 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7817 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7818 if (GET_CODE (new_rtx
) == NEG
)
7820 new_rtx
= XEXP (new_rtx
, 0);
7823 multval
= trunc_int_for_mode (multval
, mode
);
7824 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7831 lhs
= make_compound_operation (lhs
, next_code
);
7832 rhs
= make_compound_operation (rhs
, next_code
);
7833 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7834 && SCALAR_INT_MODE_P (mode
))
7836 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7838 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7840 else if (GET_CODE (lhs
) == MULT
7841 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7843 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7844 simplify_gen_unary (NEG
, mode
,
7847 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7851 SUBST (XEXP (x
, 0), lhs
);
7852 SUBST (XEXP (x
, 1), rhs
);
7855 x
= gen_lowpart (mode
, new_rtx
);
7861 lhs
= make_compound_operation (lhs
, next_code
);
7862 rhs
= make_compound_operation (rhs
, next_code
);
7863 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7864 && SCALAR_INT_MODE_P (mode
))
7866 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7868 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7870 else if (GET_CODE (rhs
) == MULT
7871 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7873 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7874 simplify_gen_unary (NEG
, mode
,
7877 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7881 SUBST (XEXP (x
, 0), lhs
);
7882 SUBST (XEXP (x
, 1), rhs
);
7885 return gen_lowpart (mode
, new_rtx
);
7888 /* If the second operand is not a constant, we can't do anything
7890 if (!CONST_INT_P (XEXP (x
, 1)))
7893 /* If the constant is a power of two minus one and the first operand
7894 is a logical right shift, make an extraction. */
7895 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7896 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7898 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7899 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7900 0, in_code
== COMPARE
);
7903 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7904 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7905 && subreg_lowpart_p (XEXP (x
, 0))
7906 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7907 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7909 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7911 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7912 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7913 0, in_code
== COMPARE
);
7915 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7916 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7917 || GET_CODE (XEXP (x
, 0)) == IOR
)
7918 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7919 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7920 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7922 /* Apply the distributive law, and then try to make extractions. */
7923 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7924 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7926 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7928 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7931 /* If we are have (and (rotate X C) M) and C is larger than the number
7932 of bits in M, this is an extraction. */
7934 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7935 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7936 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7937 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7939 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7940 new_rtx
= make_extraction (mode
, new_rtx
,
7941 (GET_MODE_PRECISION (mode
)
7942 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7943 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7946 /* On machines without logical shifts, if the operand of the AND is
7947 a logical shift and our mask turns off all the propagated sign
7948 bits, we can replace the logical shift with an arithmetic shift. */
7949 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7950 && !have_insn_for (LSHIFTRT
, mode
)
7951 && have_insn_for (ASHIFTRT
, mode
)
7952 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7953 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7954 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7955 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7957 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7959 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7960 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7962 gen_rtx_ASHIFTRT (mode
,
7963 make_compound_operation
7964 (XEXP (XEXP (x
, 0), 0), next_code
),
7965 XEXP (XEXP (x
, 0), 1)));
7968 /* If the constant is one less than a power of two, this might be
7969 representable by an extraction even if no shift is present.
7970 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7971 we are in a COMPARE. */
7972 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7973 new_rtx
= make_extraction (mode
,
7974 make_compound_operation (XEXP (x
, 0),
7976 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7978 /* If we are in a comparison and this is an AND with a power of two,
7979 convert this into the appropriate bit extract. */
7980 else if (in_code
== COMPARE
7981 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7982 new_rtx
= make_extraction (mode
,
7983 make_compound_operation (XEXP (x
, 0),
7985 i
, NULL_RTX
, 1, 1, 0, 1);
7990 /* If the sign bit is known to be zero, replace this with an
7991 arithmetic shift. */
7992 if (have_insn_for (ASHIFTRT
, mode
)
7993 && ! have_insn_for (LSHIFTRT
, mode
)
7994 && mode_width
<= HOST_BITS_PER_WIDE_INT
7995 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7997 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7998 make_compound_operation (XEXP (x
, 0),
8004 /* ... fall through ... */
8010 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8011 this is a SIGN_EXTRACT. */
8012 if (CONST_INT_P (rhs
)
8013 && GET_CODE (lhs
) == ASHIFT
8014 && CONST_INT_P (XEXP (lhs
, 1))
8015 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8016 && INTVAL (XEXP (lhs
, 1)) >= 0
8017 && INTVAL (rhs
) < mode_width
)
8019 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8020 new_rtx
= make_extraction (mode
, new_rtx
,
8021 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8022 NULL_RTX
, mode_width
- INTVAL (rhs
),
8023 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8027 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8028 If so, try to merge the shifts into a SIGN_EXTEND. We could
8029 also do this for some cases of SIGN_EXTRACT, but it doesn't
8030 seem worth the effort; the case checked for occurs on Alpha. */
8033 && ! (GET_CODE (lhs
) == SUBREG
8034 && (OBJECT_P (SUBREG_REG (lhs
))))
8035 && CONST_INT_P (rhs
)
8036 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8037 && INTVAL (rhs
) < mode_width
8038 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8039 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8040 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8041 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8046 /* Call ourselves recursively on the inner expression. If we are
8047 narrowing the object and it has a different RTL code from
8048 what it originally did, do this SUBREG as a force_to_mode. */
8050 rtx inner
= SUBREG_REG (x
), simplified
;
8051 enum rtx_code subreg_code
= in_code
;
8053 /* If in_code is COMPARE, it isn't always safe to pass it through
8054 to the recursive make_compound_operation call. */
8055 if (subreg_code
== COMPARE
8056 && (!subreg_lowpart_p (x
)
8057 || GET_CODE (inner
) == SUBREG
8058 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8059 is (const_int 0), rather than
8060 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8061 || (GET_CODE (inner
) == AND
8062 && CONST_INT_P (XEXP (inner
, 1))
8063 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8064 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8065 >= GET_MODE_BITSIZE (mode
))))
8068 tem
= make_compound_operation (inner
, subreg_code
);
8071 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8075 if (GET_CODE (tem
) != GET_CODE (inner
)
8076 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8077 && subreg_lowpart_p (x
))
8080 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
8082 /* If we have something other than a SUBREG, we might have
8083 done an expansion, so rerun ourselves. */
8084 if (GET_CODE (newer
) != SUBREG
)
8085 newer
= make_compound_operation (newer
, in_code
);
8087 /* force_to_mode can expand compounds. If it just re-expanded the
8088 compound, use gen_lowpart to convert to the desired mode. */
8089 if (rtx_equal_p (newer
, x
)
8090 /* Likewise if it re-expanded the compound only partially.
8091 This happens for SUBREG of ZERO_EXTRACT if they extract
8092 the same number of bits. */
8093 || (GET_CODE (newer
) == SUBREG
8094 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8095 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8096 && GET_CODE (inner
) == AND
8097 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8098 return gen_lowpart (GET_MODE (x
), tem
);
8114 x
= gen_lowpart (mode
, new_rtx
);
8115 code
= GET_CODE (x
);
8118 /* Now recursively process each operand of this operation. We need to
8119 handle ZERO_EXTEND specially so that we don't lose track of the
8121 if (GET_CODE (x
) == ZERO_EXTEND
)
8123 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8124 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8125 new_rtx
, GET_MODE (XEXP (x
, 0)));
8128 SUBST (XEXP (x
, 0), new_rtx
);
8132 fmt
= GET_RTX_FORMAT (code
);
8133 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8136 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8137 SUBST (XEXP (x
, i
), new_rtx
);
8139 else if (fmt
[i
] == 'E')
8140 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8142 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8143 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8147 /* If this is a commutative operation, the changes to the operands
8148 may have made it noncanonical. */
8149 if (COMMUTATIVE_ARITH_P (x
)
8150 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
8153 SUBST (XEXP (x
, 0), XEXP (x
, 1));
8154 SUBST (XEXP (x
, 1), tem
);
8160 /* Given M see if it is a value that would select a field of bits
8161 within an item, but not the entire word. Return -1 if not.
8162 Otherwise, return the starting position of the field, where 0 is the
8165 *PLEN is set to the length of the field. */
8168 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8170 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8171 int pos
= m
? ctz_hwi (m
) : -1;
8175 /* Now shift off the low-order zero bits and see if we have a
8176 power of two minus 1. */
8177 len
= exact_log2 ((m
>> pos
) + 1);
8186 /* If X refers to a register that equals REG in value, replace these
8187 references with REG. */
8189 canon_reg_for_combine (rtx x
, rtx reg
)
8196 enum rtx_code code
= GET_CODE (x
);
8197 switch (GET_RTX_CLASS (code
))
8200 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8201 if (op0
!= XEXP (x
, 0))
8202 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8207 case RTX_COMM_ARITH
:
8208 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8209 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8210 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8211 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8215 case RTX_COMM_COMPARE
:
8216 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8217 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8218 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8219 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8220 GET_MODE (op0
), op0
, op1
);
8224 case RTX_BITFIELD_OPS
:
8225 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8226 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8227 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8228 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8229 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8230 GET_MODE (op0
), op0
, op1
, op2
);
8235 if (rtx_equal_p (get_last_value (reg
), x
)
8236 || rtx_equal_p (reg
, get_last_value (x
)))
8245 fmt
= GET_RTX_FORMAT (code
);
8247 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8250 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8251 if (op
!= XEXP (x
, i
))
8261 else if (fmt
[i
] == 'E')
8264 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8266 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8267 if (op
!= XVECEXP (x
, i
, j
))
8274 XVECEXP (x
, i
, j
) = op
;
8285 /* Return X converted to MODE. If the value is already truncated to
8286 MODE we can just return a subreg even though in the general case we
8287 would need an explicit truncation. */
8290 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8292 if (!CONST_INT_P (x
)
8293 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8294 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8295 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8297 /* Bit-cast X into an integer mode. */
8298 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8299 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8300 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8304 return gen_lowpart (mode
, x
);
8307 /* See if X can be simplified knowing that we will only refer to it in
8308 MODE and will only refer to those bits that are nonzero in MASK.
8309 If other bits are being computed or if masking operations are done
8310 that select a superset of the bits in MASK, they can sometimes be
8313 Return a possibly simplified expression, but always convert X to
8314 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8316 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8317 are all off in X. This is used when X will be complemented, by either
8318 NOT, NEG, or XOR. */
8321 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8324 enum rtx_code code
= GET_CODE (x
);
8325 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8326 machine_mode op_mode
;
8327 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8330 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8331 code below will do the wrong thing since the mode of such an
8332 expression is VOIDmode.
8334 Also do nothing if X is a CLOBBER; this can happen if X was
8335 the return value from a call to gen_lowpart. */
8336 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8339 /* We want to perform the operation in its present mode unless we know
8340 that the operation is valid in MODE, in which case we do the operation
8342 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8343 && have_insn_for (code
, mode
))
8344 ? mode
: GET_MODE (x
));
8346 /* It is not valid to do a right-shift in a narrower mode
8347 than the one it came in with. */
8348 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8349 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8350 op_mode
= GET_MODE (x
);
8352 /* Truncate MASK to fit OP_MODE. */
8354 mask
&= GET_MODE_MASK (op_mode
);
8356 /* When we have an arithmetic operation, or a shift whose count we
8357 do not know, we need to assume that all bits up to the highest-order
8358 bit in MASK will be needed. This is how we form such a mask. */
8359 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8360 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8362 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8365 /* Determine what bits of X are guaranteed to be (non)zero. */
8366 nonzero
= nonzero_bits (x
, mode
);
8368 /* If none of the bits in X are needed, return a zero. */
8369 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8372 /* If X is a CONST_INT, return a new one. Do this here since the
8373 test below will fail. */
8374 if (CONST_INT_P (x
))
8376 if (SCALAR_INT_MODE_P (mode
))
8377 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8380 x
= GEN_INT (INTVAL (x
) & mask
);
8381 return gen_lowpart_common (mode
, x
);
8385 /* If X is narrower than MODE and we want all the bits in X's mode, just
8386 get X in the proper mode. */
8387 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8388 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8389 return gen_lowpart (mode
, x
);
8391 /* We can ignore the effect of a SUBREG if it narrows the mode or
8392 if the constant masks to zero all the bits the mode doesn't have. */
8393 if (GET_CODE (x
) == SUBREG
8394 && subreg_lowpart_p (x
)
8395 && ((GET_MODE_SIZE (GET_MODE (x
))
8396 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8398 & GET_MODE_MASK (GET_MODE (x
))
8399 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8400 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8402 /* The arithmetic simplifications here only work for scalar integer modes. */
8403 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8404 return gen_lowpart_or_truncate (mode
, x
);
8409 /* If X is a (clobber (const_int)), return it since we know we are
8410 generating something that won't match. */
8417 x
= expand_compound_operation (x
);
8418 if (GET_CODE (x
) != code
)
8419 return force_to_mode (x
, mode
, mask
, next_select
);
8423 /* Similarly for a truncate. */
8424 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8427 /* If this is an AND with a constant, convert it into an AND
8428 whose constant is the AND of that constant with MASK. If it
8429 remains an AND of MASK, delete it since it is redundant. */
8431 if (CONST_INT_P (XEXP (x
, 1)))
8433 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8434 mask
& INTVAL (XEXP (x
, 1)));
8436 /* If X is still an AND, see if it is an AND with a mask that
8437 is just some low-order bits. If so, and it is MASK, we don't
8440 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8441 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8445 /* If it remains an AND, try making another AND with the bits
8446 in the mode mask that aren't in MASK turned on. If the
8447 constant in the AND is wide enough, this might make a
8448 cheaper constant. */
8450 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8451 && GET_MODE_MASK (GET_MODE (x
)) != mask
8452 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8454 unsigned HOST_WIDE_INT cval
8455 = UINTVAL (XEXP (x
, 1))
8456 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8459 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8460 gen_int_mode (cval
, GET_MODE (x
)));
8461 if (set_src_cost (y
, optimize_this_for_speed_p
)
8462 < set_src_cost (x
, optimize_this_for_speed_p
))
8472 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8473 low-order bits (as in an alignment operation) and FOO is already
8474 aligned to that boundary, mask C1 to that boundary as well.
8475 This may eliminate that PLUS and, later, the AND. */
8478 unsigned int width
= GET_MODE_PRECISION (mode
);
8479 unsigned HOST_WIDE_INT smask
= mask
;
8481 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8482 number, sign extend it. */
8484 if (width
< HOST_BITS_PER_WIDE_INT
8485 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8486 smask
|= HOST_WIDE_INT_M1U
<< width
;
8488 if (CONST_INT_P (XEXP (x
, 1))
8489 && exact_log2 (- smask
) >= 0
8490 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8491 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8492 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8493 (INTVAL (XEXP (x
, 1)) & smask
)),
8494 mode
, smask
, next_select
);
8497 /* ... fall through ... */
8500 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8501 most significant bit in MASK since carries from those bits will
8502 affect the bits we are interested in. */
8507 /* If X is (minus C Y) where C's least set bit is larger than any bit
8508 in the mask, then we may replace with (neg Y). */
8509 if (CONST_INT_P (XEXP (x
, 0))
8510 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8512 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8514 return force_to_mode (x
, mode
, mask
, next_select
);
8517 /* Similarly, if C contains every bit in the fuller_mask, then we may
8518 replace with (not Y). */
8519 if (CONST_INT_P (XEXP (x
, 0))
8520 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8522 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8523 XEXP (x
, 1), GET_MODE (x
));
8524 return force_to_mode (x
, mode
, mask
, next_select
);
8532 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8533 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8534 operation which may be a bitfield extraction. Ensure that the
8535 constant we form is not wider than the mode of X. */
8537 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8538 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8539 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8540 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8541 && CONST_INT_P (XEXP (x
, 1))
8542 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8543 + floor_log2 (INTVAL (XEXP (x
, 1))))
8544 < GET_MODE_PRECISION (GET_MODE (x
)))
8545 && (UINTVAL (XEXP (x
, 1))
8546 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8548 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8549 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8551 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8552 XEXP (XEXP (x
, 0), 0), temp
);
8553 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8554 XEXP (XEXP (x
, 0), 1));
8555 return force_to_mode (x
, mode
, mask
, next_select
);
8559 /* For most binary operations, just propagate into the operation and
8560 change the mode if we have an operation of that mode. */
8562 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8563 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8565 /* If we ended up truncating both operands, truncate the result of the
8566 operation instead. */
8567 if (GET_CODE (op0
) == TRUNCATE
8568 && GET_CODE (op1
) == TRUNCATE
)
8570 op0
= XEXP (op0
, 0);
8571 op1
= XEXP (op1
, 0);
8574 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8575 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8577 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8578 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8582 /* For left shifts, do the same, but just for the first operand.
8583 However, we cannot do anything with shifts where we cannot
8584 guarantee that the counts are smaller than the size of the mode
8585 because such a count will have a different meaning in a
8588 if (! (CONST_INT_P (XEXP (x
, 1))
8589 && INTVAL (XEXP (x
, 1)) >= 0
8590 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8591 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8592 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8593 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8596 /* If the shift count is a constant and we can do arithmetic in
8597 the mode of the shift, refine which bits we need. Otherwise, use the
8598 conservative form of the mask. */
8599 if (CONST_INT_P (XEXP (x
, 1))
8600 && INTVAL (XEXP (x
, 1)) >= 0
8601 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8602 && HWI_COMPUTABLE_MODE_P (op_mode
))
8603 mask
>>= INTVAL (XEXP (x
, 1));
8607 op0
= gen_lowpart_or_truncate (op_mode
,
8608 force_to_mode (XEXP (x
, 0), op_mode
,
8609 mask
, next_select
));
8611 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8612 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8616 /* Here we can only do something if the shift count is a constant,
8617 this shift constant is valid for the host, and we can do arithmetic
8620 if (CONST_INT_P (XEXP (x
, 1))
8621 && INTVAL (XEXP (x
, 1)) >= 0
8622 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8623 && HWI_COMPUTABLE_MODE_P (op_mode
))
8625 rtx inner
= XEXP (x
, 0);
8626 unsigned HOST_WIDE_INT inner_mask
;
8628 /* Select the mask of the bits we need for the shift operand. */
8629 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8631 /* We can only change the mode of the shift if we can do arithmetic
8632 in the mode of the shift and INNER_MASK is no wider than the
8633 width of X's mode. */
8634 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8635 op_mode
= GET_MODE (x
);
8637 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8639 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8640 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8643 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8644 shift and AND produces only copies of the sign bit (C2 is one less
8645 than a power of two), we can do this with just a shift. */
8647 if (GET_CODE (x
) == LSHIFTRT
8648 && CONST_INT_P (XEXP (x
, 1))
8649 /* The shift puts one of the sign bit copies in the least significant
8651 && ((INTVAL (XEXP (x
, 1))
8652 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8653 >= GET_MODE_PRECISION (GET_MODE (x
)))
8654 && exact_log2 (mask
+ 1) >= 0
8655 /* Number of bits left after the shift must be more than the mask
8657 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8658 <= GET_MODE_PRECISION (GET_MODE (x
)))
8659 /* Must be more sign bit copies than the mask needs. */
8660 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8661 >= exact_log2 (mask
+ 1)))
8662 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8663 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8664 - exact_log2 (mask
+ 1)));
8669 /* If we are just looking for the sign bit, we don't need this shift at
8670 all, even if it has a variable count. */
8671 if (val_signbit_p (GET_MODE (x
), mask
))
8672 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8674 /* If this is a shift by a constant, get a mask that contains those bits
8675 that are not copies of the sign bit. We then have two cases: If
8676 MASK only includes those bits, this can be a logical shift, which may
8677 allow simplifications. If MASK is a single-bit field not within
8678 those bits, we are requesting a copy of the sign bit and hence can
8679 shift the sign bit to the appropriate location. */
8681 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8682 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8686 /* If the considered data is wider than HOST_WIDE_INT, we can't
8687 represent a mask for all its bits in a single scalar.
8688 But we only care about the lower bits, so calculate these. */
8690 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8692 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8694 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8695 is the number of bits a full-width mask would have set.
8696 We need only shift if these are fewer than nonzero can
8697 hold. If not, we must keep all bits set in nonzero. */
8699 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8700 < HOST_BITS_PER_WIDE_INT
)
8701 nonzero
>>= INTVAL (XEXP (x
, 1))
8702 + HOST_BITS_PER_WIDE_INT
8703 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8707 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8708 nonzero
>>= INTVAL (XEXP (x
, 1));
8711 if ((mask
& ~nonzero
) == 0)
8713 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8714 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8715 if (GET_CODE (x
) != ASHIFTRT
)
8716 return force_to_mode (x
, mode
, mask
, next_select
);
8719 else if ((i
= exact_log2 (mask
)) >= 0)
8721 x
= simplify_shift_const
8722 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8723 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8725 if (GET_CODE (x
) != ASHIFTRT
)
8726 return force_to_mode (x
, mode
, mask
, next_select
);
8730 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8731 even if the shift count isn't a constant. */
8733 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8734 XEXP (x
, 0), XEXP (x
, 1));
8738 /* If this is a zero- or sign-extension operation that just affects bits
8739 we don't care about, remove it. Be sure the call above returned
8740 something that is still a shift. */
8742 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8743 && CONST_INT_P (XEXP (x
, 1))
8744 && INTVAL (XEXP (x
, 1)) >= 0
8745 && (INTVAL (XEXP (x
, 1))
8746 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8747 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8748 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8749 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8756 /* If the shift count is constant and we can do computations
8757 in the mode of X, compute where the bits we care about are.
8758 Otherwise, we can't do anything. Don't change the mode of
8759 the shift or propagate MODE into the shift, though. */
8760 if (CONST_INT_P (XEXP (x
, 1))
8761 && INTVAL (XEXP (x
, 1)) >= 0)
8763 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8765 gen_int_mode (mask
, GET_MODE (x
)),
8767 if (temp
&& CONST_INT_P (temp
))
8768 x
= simplify_gen_binary (code
, GET_MODE (x
),
8769 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8770 INTVAL (temp
), next_select
),
8776 /* If we just want the low-order bit, the NEG isn't needed since it
8777 won't change the low-order bit. */
8779 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8781 /* We need any bits less significant than the most significant bit in
8782 MASK since carries from those bits will affect the bits we are
8788 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8789 same as the XOR case above. Ensure that the constant we form is not
8790 wider than the mode of X. */
8792 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8793 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8794 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8795 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8796 < GET_MODE_PRECISION (GET_MODE (x
)))
8797 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8799 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8801 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8802 XEXP (XEXP (x
, 0), 0), temp
);
8803 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8804 temp
, XEXP (XEXP (x
, 0), 1));
8806 return force_to_mode (x
, mode
, mask
, next_select
);
8809 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8810 use the full mask inside the NOT. */
8814 op0
= gen_lowpart_or_truncate (op_mode
,
8815 force_to_mode (XEXP (x
, 0), mode
, mask
,
8817 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8818 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8822 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8823 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8824 which is equal to STORE_FLAG_VALUE. */
8825 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8826 && XEXP (x
, 1) == const0_rtx
8827 && GET_MODE (XEXP (x
, 0)) == mode
8828 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8829 && (nonzero_bits (XEXP (x
, 0), mode
)
8830 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8831 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8836 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8837 written in a narrower mode. We play it safe and do not do so. */
8839 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8840 force_to_mode (XEXP (x
, 1), mode
,
8841 mask
, next_select
));
8842 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8843 force_to_mode (XEXP (x
, 2), mode
,
8844 mask
, next_select
));
8845 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8846 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8847 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8855 /* Ensure we return a value of the proper mode. */
8856 return gen_lowpart_or_truncate (mode
, x
);
8859 /* Return nonzero if X is an expression that has one of two values depending on
8860 whether some other value is zero or nonzero. In that case, we return the
8861 value that is being tested, *PTRUE is set to the value if the rtx being
8862 returned has a nonzero value, and *PFALSE is set to the other alternative.
8864 If we return zero, we set *PTRUE and *PFALSE to X. */
8867 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8869 machine_mode mode
= GET_MODE (x
);
8870 enum rtx_code code
= GET_CODE (x
);
8871 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8872 unsigned HOST_WIDE_INT nz
;
8874 /* If we are comparing a value against zero, we are done. */
8875 if ((code
== NE
|| code
== EQ
)
8876 && XEXP (x
, 1) == const0_rtx
)
8878 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8879 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8883 /* If this is a unary operation whose operand has one of two values, apply
8884 our opcode to compute those values. */
8885 else if (UNARY_P (x
)
8886 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8888 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8889 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8890 GET_MODE (XEXP (x
, 0)));
8894 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8895 make can't possibly match and would suppress other optimizations. */
8896 else if (code
== COMPARE
)
8899 /* If this is a binary operation, see if either side has only one of two
8900 values. If either one does or if both do and they are conditional on
8901 the same value, compute the new true and false values. */
8902 else if (BINARY_P (x
))
8904 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8905 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8907 if ((cond0
!= 0 || cond1
!= 0)
8908 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8910 /* If if_then_else_cond returned zero, then true/false are the
8911 same rtl. We must copy one of them to prevent invalid rtl
8914 true0
= copy_rtx (true0
);
8915 else if (cond1
== 0)
8916 true1
= copy_rtx (true1
);
8918 if (COMPARISON_P (x
))
8920 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8922 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8927 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8928 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8931 return cond0
? cond0
: cond1
;
8934 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8935 operands is zero when the other is nonzero, and vice-versa,
8936 and STORE_FLAG_VALUE is 1 or -1. */
8938 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8939 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8941 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8943 rtx op0
= XEXP (XEXP (x
, 0), 1);
8944 rtx op1
= XEXP (XEXP (x
, 1), 1);
8946 cond0
= XEXP (XEXP (x
, 0), 0);
8947 cond1
= XEXP (XEXP (x
, 1), 0);
8949 if (COMPARISON_P (cond0
)
8950 && COMPARISON_P (cond1
)
8951 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8952 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8953 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8954 || ((swap_condition (GET_CODE (cond0
))
8955 == reversed_comparison_code (cond1
, NULL
))
8956 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8957 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8958 && ! side_effects_p (x
))
8960 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8961 *pfalse
= simplify_gen_binary (MULT
, mode
,
8963 ? simplify_gen_unary (NEG
, mode
,
8971 /* Similarly for MULT, AND and UMIN, except that for these the result
8973 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8974 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8975 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8977 cond0
= XEXP (XEXP (x
, 0), 0);
8978 cond1
= XEXP (XEXP (x
, 1), 0);
8980 if (COMPARISON_P (cond0
)
8981 && COMPARISON_P (cond1
)
8982 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8983 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8984 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8985 || ((swap_condition (GET_CODE (cond0
))
8986 == reversed_comparison_code (cond1
, NULL
))
8987 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8988 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8989 && ! side_effects_p (x
))
8991 *ptrue
= *pfalse
= const0_rtx
;
8997 else if (code
== IF_THEN_ELSE
)
8999 /* If we have IF_THEN_ELSE already, extract the condition and
9000 canonicalize it if it is NE or EQ. */
9001 cond0
= XEXP (x
, 0);
9002 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9003 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9004 return XEXP (cond0
, 0);
9005 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9007 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9008 return XEXP (cond0
, 0);
9014 /* If X is a SUBREG, we can narrow both the true and false values
9015 if the inner expression, if there is a condition. */
9016 else if (code
== SUBREG
9017 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9020 true0
= simplify_gen_subreg (mode
, true0
,
9021 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9022 false0
= simplify_gen_subreg (mode
, false0
,
9023 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9024 if (true0
&& false0
)
9032 /* If X is a constant, this isn't special and will cause confusions
9033 if we treat it as such. Likewise if it is equivalent to a constant. */
9034 else if (CONSTANT_P (x
)
9035 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9038 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9039 will be least confusing to the rest of the compiler. */
9040 else if (mode
== BImode
)
9042 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9046 /* If X is known to be either 0 or -1, those are the true and
9047 false values when testing X. */
9048 else if (x
== constm1_rtx
|| x
== const0_rtx
9049 || (mode
!= VOIDmode
9050 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9052 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9056 /* Likewise for 0 or a single bit. */
9057 else if (HWI_COMPUTABLE_MODE_P (mode
)
9058 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
9060 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9064 /* Otherwise fail; show no condition with true and false values the same. */
9065 *ptrue
= *pfalse
= x
;
9069 /* Return the value of expression X given the fact that condition COND
9070 is known to be true when applied to REG as its first operand and VAL
9071 as its second. X is known to not be shared and so can be modified in
9074 We only handle the simplest cases, and specifically those cases that
9075 arise with IF_THEN_ELSE expressions. */
9078 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9080 enum rtx_code code
= GET_CODE (x
);
9084 if (side_effects_p (x
))
9087 /* If either operand of the condition is a floating point value,
9088 then we have to avoid collapsing an EQ comparison. */
9090 && rtx_equal_p (x
, reg
)
9091 && ! FLOAT_MODE_P (GET_MODE (x
))
9092 && ! FLOAT_MODE_P (GET_MODE (val
)))
9095 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9098 /* If X is (abs REG) and we know something about REG's relationship
9099 with zero, we may be able to simplify this. */
9101 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9104 case GE
: case GT
: case EQ
:
9107 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9109 GET_MODE (XEXP (x
, 0)));
9114 /* The only other cases we handle are MIN, MAX, and comparisons if the
9115 operands are the same as REG and VAL. */
9117 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9119 if (rtx_equal_p (XEXP (x
, 0), val
))
9121 std::swap (val
, reg
);
9122 cond
= swap_condition (cond
);
9125 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9127 if (COMPARISON_P (x
))
9129 if (comparison_dominates_p (cond
, code
))
9130 return const_true_rtx
;
9132 code
= reversed_comparison_code (x
, NULL
);
9134 && comparison_dominates_p (cond
, code
))
9139 else if (code
== SMAX
|| code
== SMIN
9140 || code
== UMIN
|| code
== UMAX
)
9142 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9144 /* Do not reverse the condition when it is NE or EQ.
9145 This is because we cannot conclude anything about
9146 the value of 'SMAX (x, y)' when x is not equal to y,
9147 but we can when x equals y. */
9148 if ((code
== SMAX
|| code
== UMAX
)
9149 && ! (cond
== EQ
|| cond
== NE
))
9150 cond
= reverse_condition (cond
);
9155 return unsignedp
? x
: XEXP (x
, 1);
9157 return unsignedp
? x
: XEXP (x
, 0);
9159 return unsignedp
? XEXP (x
, 1) : x
;
9161 return unsignedp
? XEXP (x
, 0) : x
;
9168 else if (code
== SUBREG
)
9170 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9171 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9173 if (SUBREG_REG (x
) != r
)
9175 /* We must simplify subreg here, before we lose track of the
9176 original inner_mode. */
9177 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9178 inner_mode
, SUBREG_BYTE (x
));
9182 SUBST (SUBREG_REG (x
), r
);
9187 /* We don't have to handle SIGN_EXTEND here, because even in the
9188 case of replacing something with a modeless CONST_INT, a
9189 CONST_INT is already (supposed to be) a valid sign extension for
9190 its narrower mode, which implies it's already properly
9191 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9192 story is different. */
9193 else if (code
== ZERO_EXTEND
)
9195 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9196 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9198 if (XEXP (x
, 0) != r
)
9200 /* We must simplify the zero_extend here, before we lose
9201 track of the original inner_mode. */
9202 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9207 SUBST (XEXP (x
, 0), r
);
9213 fmt
= GET_RTX_FORMAT (code
);
9214 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9217 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9218 else if (fmt
[i
] == 'E')
9219 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9220 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9227 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9228 assignment as a field assignment. */
9231 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9233 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9235 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9237 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9239 /* For big endian, adjust the memory offset. */
9240 if (BYTES_BIG_ENDIAN
)
9241 x
= adjust_address_nv (x
, GET_MODE (y
),
9242 -subreg_lowpart_offset (GET_MODE (x
),
9245 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9248 if (x
== y
|| rtx_equal_p (x
, y
))
9251 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9254 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9255 Note that all SUBREGs of MEM are paradoxical; otherwise they
9256 would have been rewritten. */
9257 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9258 && MEM_P (SUBREG_REG (y
))
9259 && rtx_equal_p (SUBREG_REG (y
),
9260 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9263 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9264 && MEM_P (SUBREG_REG (x
))
9265 && rtx_equal_p (SUBREG_REG (x
),
9266 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9269 /* We used to see if get_last_value of X and Y were the same but that's
9270 not correct. In one direction, we'll cause the assignment to have
9271 the wrong destination and in the case, we'll import a register into this
9272 insn that might have already have been dead. So fail if none of the
9273 above cases are true. */
9277 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9278 Return that assignment if so.
9280 We only handle the most common cases. */
9283 make_field_assignment (rtx x
)
9285 rtx dest
= SET_DEST (x
);
9286 rtx src
= SET_SRC (x
);
9291 unsigned HOST_WIDE_INT len
;
9295 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9296 a clear of a one-bit field. We will have changed it to
9297 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9300 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9301 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9302 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9303 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9305 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9308 return gen_rtx_SET (assign
, const0_rtx
);
9312 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9313 && subreg_lowpart_p (XEXP (src
, 0))
9314 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9315 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9316 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9317 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9318 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9319 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9321 assign
= make_extraction (VOIDmode
, dest
, 0,
9322 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9325 return gen_rtx_SET (assign
, const0_rtx
);
9329 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9331 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9332 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9333 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9335 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9338 return gen_rtx_SET (assign
, const1_rtx
);
9342 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9343 SRC is an AND with all bits of that field set, then we can discard
9345 if (GET_CODE (dest
) == ZERO_EXTRACT
9346 && CONST_INT_P (XEXP (dest
, 1))
9347 && GET_CODE (src
) == AND
9348 && CONST_INT_P (XEXP (src
, 1)))
9350 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9351 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9352 unsigned HOST_WIDE_INT ze_mask
;
9354 if (width
>= HOST_BITS_PER_WIDE_INT
)
9357 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9359 /* Complete overlap. We can remove the source AND. */
9360 if ((and_mask
& ze_mask
) == ze_mask
)
9361 return gen_rtx_SET (dest
, XEXP (src
, 0));
9363 /* Partial overlap. We can reduce the source AND. */
9364 if ((and_mask
& ze_mask
) != and_mask
)
9366 mode
= GET_MODE (src
);
9367 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9368 gen_int_mode (and_mask
& ze_mask
, mode
));
9369 return gen_rtx_SET (dest
, src
);
9373 /* The other case we handle is assignments into a constant-position
9374 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9375 a mask that has all one bits except for a group of zero bits and
9376 OTHER is known to have zeros where C1 has ones, this is such an
9377 assignment. Compute the position and length from C1. Shift OTHER
9378 to the appropriate position, force it to the required mode, and
9379 make the extraction. Check for the AND in both operands. */
9381 /* One or more SUBREGs might obscure the constant-position field
9382 assignment. The first one we are likely to encounter is an outer
9383 narrowing SUBREG, which we can just strip for the purposes of
9384 identifying the constant-field assignment. */
9385 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9386 src
= SUBREG_REG (src
);
9388 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9391 rhs
= expand_compound_operation (XEXP (src
, 0));
9392 lhs
= expand_compound_operation (XEXP (src
, 1));
9394 if (GET_CODE (rhs
) == AND
9395 && CONST_INT_P (XEXP (rhs
, 1))
9396 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9397 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9398 /* The second SUBREG that might get in the way is a paradoxical
9399 SUBREG around the first operand of the AND. We want to
9400 pretend the operand is as wide as the destination here. We
9401 do this by adjusting the MEM to wider mode for the sole
9402 purpose of the call to rtx_equal_for_field_assignment_p. Also
9403 note this trick only works for MEMs. */
9404 else if (GET_CODE (rhs
) == AND
9405 && paradoxical_subreg_p (XEXP (rhs
, 0))
9406 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9407 && CONST_INT_P (XEXP (rhs
, 1))
9408 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9410 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9411 else if (GET_CODE (lhs
) == AND
9412 && CONST_INT_P (XEXP (lhs
, 1))
9413 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9414 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9415 /* The second SUBREG that might get in the way is a paradoxical
9416 SUBREG around the first operand of the AND. We want to
9417 pretend the operand is as wide as the destination here. We
9418 do this by adjusting the MEM to wider mode for the sole
9419 purpose of the call to rtx_equal_for_field_assignment_p. Also
9420 note this trick only works for MEMs. */
9421 else if (GET_CODE (lhs
) == AND
9422 && paradoxical_subreg_p (XEXP (lhs
, 0))
9423 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9424 && CONST_INT_P (XEXP (lhs
, 1))
9425 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9427 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9431 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9432 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9433 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9434 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9437 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9441 /* The mode to use for the source is the mode of the assignment, or of
9442 what is inside a possible STRICT_LOW_PART. */
9443 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9444 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9446 /* Shift OTHER right POS places and make it the source, restricting it
9447 to the proper length and mode. */
9449 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9453 src
= force_to_mode (src
, mode
,
9454 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9455 ? ~(unsigned HOST_WIDE_INT
) 0
9456 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9459 /* If SRC is masked by an AND that does not make a difference in
9460 the value being stored, strip it. */
9461 if (GET_CODE (assign
) == ZERO_EXTRACT
9462 && CONST_INT_P (XEXP (assign
, 1))
9463 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9464 && GET_CODE (src
) == AND
9465 && CONST_INT_P (XEXP (src
, 1))
9466 && UINTVAL (XEXP (src
, 1))
9467 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9468 src
= XEXP (src
, 0);
9470 return gen_rtx_SET (assign
, src
);
9473 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9477 apply_distributive_law (rtx x
)
9479 enum rtx_code code
= GET_CODE (x
);
9480 enum rtx_code inner_code
;
9481 rtx lhs
, rhs
, other
;
9484 /* Distributivity is not true for floating point as it can change the
9485 value. So we don't do it unless -funsafe-math-optimizations. */
9486 if (FLOAT_MODE_P (GET_MODE (x
))
9487 && ! flag_unsafe_math_optimizations
)
9490 /* The outer operation can only be one of the following: */
9491 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9492 && code
!= PLUS
&& code
!= MINUS
)
9498 /* If either operand is a primitive we can't do anything, so get out
9500 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9503 lhs
= expand_compound_operation (lhs
);
9504 rhs
= expand_compound_operation (rhs
);
9505 inner_code
= GET_CODE (lhs
);
9506 if (inner_code
!= GET_CODE (rhs
))
9509 /* See if the inner and outer operations distribute. */
9516 /* These all distribute except over PLUS. */
9517 if (code
== PLUS
|| code
== MINUS
)
9522 if (code
!= PLUS
&& code
!= MINUS
)
9527 /* This is also a multiply, so it distributes over everything. */
9530 /* This used to handle SUBREG, but this turned out to be counter-
9531 productive, since (subreg (op ...)) usually is not handled by
9532 insn patterns, and this "optimization" therefore transformed
9533 recognizable patterns into unrecognizable ones. Therefore the
9534 SUBREG case was removed from here.
9536 It is possible that distributing SUBREG over arithmetic operations
9537 leads to an intermediate result than can then be optimized further,
9538 e.g. by moving the outer SUBREG to the other side of a SET as done
9539 in simplify_set. This seems to have been the original intent of
9540 handling SUBREGs here.
9542 However, with current GCC this does not appear to actually happen,
9543 at least on major platforms. If some case is found where removing
9544 the SUBREG case here prevents follow-on optimizations, distributing
9545 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9551 /* Set LHS and RHS to the inner operands (A and B in the example
9552 above) and set OTHER to the common operand (C in the example).
9553 There is only one way to do this unless the inner operation is
9555 if (COMMUTATIVE_ARITH_P (lhs
)
9556 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9557 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9558 else if (COMMUTATIVE_ARITH_P (lhs
)
9559 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9560 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9561 else if (COMMUTATIVE_ARITH_P (lhs
)
9562 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9563 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9564 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9565 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9569 /* Form the new inner operation, seeing if it simplifies first. */
9570 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9572 /* There is one exception to the general way of distributing:
9573 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9574 if (code
== XOR
&& inner_code
== IOR
)
9577 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9580 /* We may be able to continuing distributing the result, so call
9581 ourselves recursively on the inner operation before forming the
9582 outer operation, which we return. */
9583 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9584 apply_distributive_law (tem
), other
);
9587 /* See if X is of the form (* (+ A B) C), and if so convert to
9588 (+ (* A C) (* B C)) and try to simplify.
9590 Most of the time, this results in no change. However, if some of
9591 the operands are the same or inverses of each other, simplifications
9594 For example, (and (ior A B) (not B)) can occur as the result of
9595 expanding a bit field assignment. When we apply the distributive
9596 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9597 which then simplifies to (and (A (not B))).
9599 Note that no checks happen on the validity of applying the inverse
9600 distributive law. This is pointless since we can do it in the
9601 few places where this routine is called.
9603 N is the index of the term that is decomposed (the arithmetic operation,
9604 i.e. (+ A B) in the first example above). !N is the index of the term that
9605 is distributed, i.e. of C in the first example above. */
9607 distribute_and_simplify_rtx (rtx x
, int n
)
9610 enum rtx_code outer_code
, inner_code
;
9611 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9613 /* Distributivity is not true for floating point as it can change the
9614 value. So we don't do it unless -funsafe-math-optimizations. */
9615 if (FLOAT_MODE_P (GET_MODE (x
))
9616 && ! flag_unsafe_math_optimizations
)
9619 decomposed
= XEXP (x
, n
);
9620 if (!ARITHMETIC_P (decomposed
))
9623 mode
= GET_MODE (x
);
9624 outer_code
= GET_CODE (x
);
9625 distributed
= XEXP (x
, !n
);
9627 inner_code
= GET_CODE (decomposed
);
9628 inner_op0
= XEXP (decomposed
, 0);
9629 inner_op1
= XEXP (decomposed
, 1);
9631 /* Special case (and (xor B C) (not A)), which is equivalent to
9632 (xor (ior A B) (ior A C)) */
9633 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9635 distributed
= XEXP (distributed
, 0);
9641 /* Distribute the second term. */
9642 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9643 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9647 /* Distribute the first term. */
9648 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9649 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9652 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9654 if (GET_CODE (tmp
) != outer_code
9655 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9656 < set_src_cost (x
, optimize_this_for_speed_p
)))
9662 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9663 in MODE. Return an equivalent form, if different from (and VAROP
9664 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9667 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9668 unsigned HOST_WIDE_INT constop
)
9670 unsigned HOST_WIDE_INT nonzero
;
9671 unsigned HOST_WIDE_INT orig_constop
;
9676 orig_constop
= constop
;
9677 if (GET_CODE (varop
) == CLOBBER
)
9680 /* Simplify VAROP knowing that we will be only looking at some of the
9683 Note by passing in CONSTOP, we guarantee that the bits not set in
9684 CONSTOP are not significant and will never be examined. We must
9685 ensure that is the case by explicitly masking out those bits
9686 before returning. */
9687 varop
= force_to_mode (varop
, mode
, constop
, 0);
9689 /* If VAROP is a CLOBBER, we will fail so return it. */
9690 if (GET_CODE (varop
) == CLOBBER
)
9693 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9694 to VAROP and return the new constant. */
9695 if (CONST_INT_P (varop
))
9696 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9698 /* See what bits may be nonzero in VAROP. Unlike the general case of
9699 a call to nonzero_bits, here we don't care about bits outside
9702 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9704 /* Turn off all bits in the constant that are known to already be zero.
9705 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9706 which is tested below. */
9710 /* If we don't have any bits left, return zero. */
9714 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9715 a power of two, we can replace this with an ASHIFT. */
9716 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9717 && (i
= exact_log2 (constop
)) >= 0)
9718 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9720 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9721 or XOR, then try to apply the distributive law. This may eliminate
9722 operations if either branch can be simplified because of the AND.
9723 It may also make some cases more complex, but those cases probably
9724 won't match a pattern either with or without this. */
9726 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9730 apply_distributive_law
9731 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9732 simplify_and_const_int (NULL_RTX
,
9736 simplify_and_const_int (NULL_RTX
,
9741 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9742 the AND and see if one of the operands simplifies to zero. If so, we
9743 may eliminate it. */
9745 if (GET_CODE (varop
) == PLUS
9746 && exact_log2 (constop
+ 1) >= 0)
9750 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9751 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9752 if (o0
== const0_rtx
)
9754 if (o1
== const0_rtx
)
9758 /* Make a SUBREG if necessary. If we can't make it, fail. */
9759 varop
= gen_lowpart (mode
, varop
);
9760 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9763 /* If we are only masking insignificant bits, return VAROP. */
9764 if (constop
== nonzero
)
9767 if (varop
== orig_varop
&& constop
== orig_constop
)
9770 /* Otherwise, return an AND. */
9771 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9775 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9778 Return an equivalent form, if different from X. Otherwise, return X. If
9779 X is zero, we are to always construct the equivalent form. */
9782 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9783 unsigned HOST_WIDE_INT constop
)
9785 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9790 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9791 gen_int_mode (constop
, mode
));
9792 if (GET_MODE (x
) != mode
)
9793 x
= gen_lowpart (mode
, x
);
9797 /* Given a REG, X, compute which bits in X can be nonzero.
9798 We don't care about bits outside of those defined in MODE.
9800 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9801 a shift, AND, or zero_extract, we can do better. */
9804 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9805 const_rtx known_x ATTRIBUTE_UNUSED
,
9806 machine_mode known_mode ATTRIBUTE_UNUSED
,
9807 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9808 unsigned HOST_WIDE_INT
*nonzero
)
9813 /* If X is a register whose nonzero bits value is current, use it.
9814 Otherwise, if X is a register whose value we can find, use that
9815 value. Otherwise, use the previously-computed global nonzero bits
9816 for this register. */
9818 rsp
= ®_stat
[REGNO (x
)];
9819 if (rsp
->last_set_value
!= 0
9820 && (rsp
->last_set_mode
== mode
9821 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9822 && GET_MODE_CLASS (mode
) == MODE_INT
))
9823 && ((rsp
->last_set_label
>= label_tick_ebb_start
9824 && rsp
->last_set_label
< label_tick
)
9825 || (rsp
->last_set_label
== label_tick
9826 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9827 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9828 && REGNO (x
) < reg_n_sets_max
9829 && REG_N_SETS (REGNO (x
)) == 1
9831 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9834 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9836 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9837 /* We don't know anything about the upper bits. */
9838 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9844 tem
= get_last_value (x
);
9848 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9849 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
9850 GET_MODE_PRECISION (mode
));
9854 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9856 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9858 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9859 /* We don't know anything about the upper bits. */
9860 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9868 /* Return the number of bits at the high-order end of X that are known to
9869 be equal to the sign bit. X will be used in mode MODE; if MODE is
9870 VOIDmode, X will be used in its own mode. The returned value will always
9871 be between 1 and the number of bits in MODE. */
9874 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9875 const_rtx known_x ATTRIBUTE_UNUSED
,
9876 machine_mode known_mode
9878 unsigned int known_ret ATTRIBUTE_UNUSED
,
9879 unsigned int *result
)
9884 rsp
= ®_stat
[REGNO (x
)];
9885 if (rsp
->last_set_value
!= 0
9886 && rsp
->last_set_mode
== mode
9887 && ((rsp
->last_set_label
>= label_tick_ebb_start
9888 && rsp
->last_set_label
< label_tick
)
9889 || (rsp
->last_set_label
== label_tick
9890 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9891 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9892 && REGNO (x
) < reg_n_sets_max
9893 && REG_N_SETS (REGNO (x
)) == 1
9895 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9898 *result
= rsp
->last_set_sign_bit_copies
;
9902 tem
= get_last_value (x
);
9906 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9907 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9908 *result
= rsp
->sign_bit_copies
;
9913 /* Return the number of "extended" bits there are in X, when interpreted
9914 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9915 unsigned quantities, this is the number of high-order zero bits.
9916 For signed quantities, this is the number of copies of the sign bit
9917 minus 1. In both case, this function returns the number of "spare"
9918 bits. For example, if two quantities for which this function returns
9919 at least 1 are added, the addition is known not to overflow.
9921 This function will always return 0 unless called during combine, which
9922 implies that it must be called from a define_split. */
9925 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9927 if (nonzero_sign_valid
== 0)
9931 ? (HWI_COMPUTABLE_MODE_P (mode
)
9932 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9933 - floor_log2 (nonzero_bits (x
, mode
)))
9935 : num_sign_bit_copies (x
, mode
) - 1);
9938 /* This function is called from `simplify_shift_const' to merge two
9939 outer operations. Specifically, we have already found that we need
9940 to perform operation *POP0 with constant *PCONST0 at the outermost
9941 position. We would now like to also perform OP1 with constant CONST1
9942 (with *POP0 being done last).
9944 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9945 the resulting operation. *PCOMP_P is set to 1 if we would need to
9946 complement the innermost operand, otherwise it is unchanged.
9948 MODE is the mode in which the operation will be done. No bits outside
9949 the width of this mode matter. It is assumed that the width of this mode
9950 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9952 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9953 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9954 result is simply *PCONST0.
9956 If the resulting operation cannot be expressed as one operation, we
9957 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9960 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
9962 enum rtx_code op0
= *pop0
;
9963 HOST_WIDE_INT const0
= *pconst0
;
9965 const0
&= GET_MODE_MASK (mode
);
9966 const1
&= GET_MODE_MASK (mode
);
9968 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9972 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9975 if (op1
== UNKNOWN
|| op0
== SET
)
9978 else if (op0
== UNKNOWN
)
9979 op0
= op1
, const0
= const1
;
9981 else if (op0
== op1
)
10005 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10006 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10009 /* If the two constants aren't the same, we can't do anything. The
10010 remaining six cases can all be done. */
10011 else if (const0
!= const1
)
10019 /* (a & b) | b == b */
10021 else /* op1 == XOR */
10022 /* (a ^ b) | b == a | b */
10028 /* (a & b) ^ b == (~a) & b */
10029 op0
= AND
, *pcomp_p
= 1;
10030 else /* op1 == IOR */
10031 /* (a | b) ^ b == a & ~b */
10032 op0
= AND
, const0
= ~const0
;
10037 /* (a | b) & b == b */
10039 else /* op1 == XOR */
10040 /* (a ^ b) & b) == (~a) & b */
10047 /* Check for NO-OP cases. */
10048 const0
&= GET_MODE_MASK (mode
);
10050 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10052 else if (const0
== 0 && op0
== AND
)
10054 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10060 /* ??? Slightly redundant with the above mask, but not entirely.
10061 Moving this above means we'd have to sign-extend the mode mask
10062 for the final test. */
10063 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10064 *pconst0
= trunc_int_for_mode (const0
, mode
);
10069 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10070 the shift in. The original shift operation CODE is performed on OP in
10071 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10072 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10073 result of the shift is subject to operation OUTER_CODE with operand
10076 static machine_mode
10077 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10078 machine_mode orig_mode
, machine_mode mode
,
10079 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10081 if (orig_mode
== mode
)
10083 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10085 /* In general we can't perform in wider mode for right shift and rotate. */
10089 /* We can still widen if the bits brought in from the left are identical
10090 to the sign bit of ORIG_MODE. */
10091 if (num_sign_bit_copies (op
, mode
)
10092 > (unsigned) (GET_MODE_PRECISION (mode
)
10093 - GET_MODE_PRECISION (orig_mode
)))
10098 /* Similarly here but with zero bits. */
10099 if (HWI_COMPUTABLE_MODE_P (mode
)
10100 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10103 /* We can also widen if the bits brought in will be masked off. This
10104 operation is performed in ORIG_MODE. */
10105 if (outer_code
== AND
)
10107 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10110 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10119 gcc_unreachable ();
10126 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10127 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10128 if we cannot simplify it. Otherwise, return a simplified value.
10130 The shift is normally computed in the widest mode we find in VAROP, as
10131 long as it isn't a different number of words than RESULT_MODE. Exceptions
10132 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10135 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10136 rtx varop
, int orig_count
)
10138 enum rtx_code orig_code
= code
;
10139 rtx orig_varop
= varop
;
10141 machine_mode mode
= result_mode
;
10142 machine_mode shift_mode
, tmode
;
10143 unsigned int mode_words
10144 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10145 /* We form (outer_op (code varop count) (outer_const)). */
10146 enum rtx_code outer_op
= UNKNOWN
;
10147 HOST_WIDE_INT outer_const
= 0;
10148 int complement_p
= 0;
10151 /* Make sure and truncate the "natural" shift on the way in. We don't
10152 want to do this inside the loop as it makes it more difficult to
10154 if (SHIFT_COUNT_TRUNCATED
)
10155 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
10157 /* If we were given an invalid count, don't do anything except exactly
10158 what was requested. */
10160 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
10163 count
= orig_count
;
10165 /* Unless one of the branches of the `if' in this loop does a `continue',
10166 we will `break' the loop after the `if'. */
10170 /* If we have an operand of (clobber (const_int 0)), fail. */
10171 if (GET_CODE (varop
) == CLOBBER
)
10174 /* Convert ROTATERT to ROTATE. */
10175 if (code
== ROTATERT
)
10177 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
10179 if (VECTOR_MODE_P (result_mode
))
10180 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
10182 count
= bitsize
- count
;
10185 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10186 mode
, outer_op
, outer_const
);
10188 /* Handle cases where the count is greater than the size of the mode
10189 minus 1. For ASHIFT, use the size minus one as the count (this can
10190 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10191 take the count modulo the size. For other shifts, the result is
10194 Since these shifts are being produced by the compiler by combining
10195 multiple operations, each of which are defined, we know what the
10196 result is supposed to be. */
10198 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
10200 if (code
== ASHIFTRT
)
10201 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10202 else if (code
== ROTATE
|| code
== ROTATERT
)
10203 count
%= GET_MODE_PRECISION (shift_mode
);
10206 /* We can't simply return zero because there may be an
10208 varop
= const0_rtx
;
10214 /* If we discovered we had to complement VAROP, leave. Making a NOT
10215 here would cause an infinite loop. */
10219 /* An arithmetic right shift of a quantity known to be -1 or 0
10221 if (code
== ASHIFTRT
10222 && (num_sign_bit_copies (varop
, shift_mode
)
10223 == GET_MODE_PRECISION (shift_mode
)))
10229 /* If we are doing an arithmetic right shift and discarding all but
10230 the sign bit copies, this is equivalent to doing a shift by the
10231 bitsize minus one. Convert it into that shift because it will often
10232 allow other simplifications. */
10234 if (code
== ASHIFTRT
10235 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
10236 >= GET_MODE_PRECISION (shift_mode
)))
10237 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10239 /* We simplify the tests below and elsewhere by converting
10240 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10241 `make_compound_operation' will convert it to an ASHIFTRT for
10242 those machines (such as VAX) that don't have an LSHIFTRT. */
10243 if (code
== ASHIFTRT
10244 && val_signbit_known_clear_p (shift_mode
,
10245 nonzero_bits (varop
, shift_mode
)))
10248 if (((code
== LSHIFTRT
10249 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10250 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10252 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10253 && !((nonzero_bits (varop
, shift_mode
) << count
)
10254 & GET_MODE_MASK (shift_mode
))))
10255 && !side_effects_p (varop
))
10256 varop
= const0_rtx
;
10258 switch (GET_CODE (varop
))
10264 new_rtx
= expand_compound_operation (varop
);
10265 if (new_rtx
!= varop
)
10273 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10274 minus the width of a smaller mode, we can do this with a
10275 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10276 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10277 && ! mode_dependent_address_p (XEXP (varop
, 0),
10278 MEM_ADDR_SPACE (varop
))
10279 && ! MEM_VOLATILE_P (varop
)
10280 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10281 MODE_INT
, 1)) != BLKmode
)
10283 new_rtx
= adjust_address_nv (varop
, tmode
,
10284 BYTES_BIG_ENDIAN
? 0
10285 : count
/ BITS_PER_UNIT
);
10287 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10288 : ZERO_EXTEND
, mode
, new_rtx
);
10295 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10296 the same number of words as what we've seen so far. Then store
10297 the widest mode in MODE. */
10298 if (subreg_lowpart_p (varop
)
10299 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10300 > GET_MODE_SIZE (GET_MODE (varop
)))
10301 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10302 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10304 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10305 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10307 varop
= SUBREG_REG (varop
);
10308 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10309 mode
= GET_MODE (varop
);
10315 /* Some machines use MULT instead of ASHIFT because MULT
10316 is cheaper. But it is still better on those machines to
10317 merge two shifts into one. */
10318 if (CONST_INT_P (XEXP (varop
, 1))
10319 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10322 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10324 GEN_INT (exact_log2 (
10325 UINTVAL (XEXP (varop
, 1)))));
10331 /* Similar, for when divides are cheaper. */
10332 if (CONST_INT_P (XEXP (varop
, 1))
10333 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10336 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10338 GEN_INT (exact_log2 (
10339 UINTVAL (XEXP (varop
, 1)))));
10345 /* If we are extracting just the sign bit of an arithmetic
10346 right shift, that shift is not needed. However, the sign
10347 bit of a wider mode may be different from what would be
10348 interpreted as the sign bit in a narrower mode, so, if
10349 the result is narrower, don't discard the shift. */
10350 if (code
== LSHIFTRT
10351 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10352 && (GET_MODE_BITSIZE (result_mode
)
10353 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10355 varop
= XEXP (varop
, 0);
10359 /* ... fall through ... */
10364 /* Here we have two nested shifts. The result is usually the
10365 AND of a new shift with a mask. We compute the result below. */
10366 if (CONST_INT_P (XEXP (varop
, 1))
10367 && INTVAL (XEXP (varop
, 1)) >= 0
10368 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10369 && HWI_COMPUTABLE_MODE_P (result_mode
)
10370 && HWI_COMPUTABLE_MODE_P (mode
)
10371 && !VECTOR_MODE_P (result_mode
))
10373 enum rtx_code first_code
= GET_CODE (varop
);
10374 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10375 unsigned HOST_WIDE_INT mask
;
10378 /* We have one common special case. We can't do any merging if
10379 the inner code is an ASHIFTRT of a smaller mode. However, if
10380 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10381 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10382 we can convert it to
10383 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10384 This simplifies certain SIGN_EXTEND operations. */
10385 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10386 && count
== (GET_MODE_PRECISION (result_mode
)
10387 - GET_MODE_PRECISION (GET_MODE (varop
))))
10389 /* C3 has the low-order C1 bits zero. */
10391 mask
= GET_MODE_MASK (mode
)
10392 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10394 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10395 XEXP (varop
, 0), mask
);
10396 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10398 count
= first_count
;
10403 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10404 than C1 high-order bits equal to the sign bit, we can convert
10405 this to either an ASHIFT or an ASHIFTRT depending on the
10408 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10410 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10411 && GET_MODE (varop
) == shift_mode
10412 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10415 varop
= XEXP (varop
, 0);
10416 count
-= first_count
;
10426 /* There are some cases we can't do. If CODE is ASHIFTRT,
10427 we can only do this if FIRST_CODE is also ASHIFTRT.
10429 We can't do the case when CODE is ROTATE and FIRST_CODE is
10432 If the mode of this shift is not the mode of the outer shift,
10433 we can't do this if either shift is a right shift or ROTATE.
10435 Finally, we can't do any of these if the mode is too wide
10436 unless the codes are the same.
10438 Handle the case where the shift codes are the same
10441 if (code
== first_code
)
10443 if (GET_MODE (varop
) != result_mode
10444 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10445 || code
== ROTATE
))
10448 count
+= first_count
;
10449 varop
= XEXP (varop
, 0);
10453 if (code
== ASHIFTRT
10454 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10455 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10456 || (GET_MODE (varop
) != result_mode
10457 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10458 || first_code
== ROTATE
10459 || code
== ROTATE
)))
10462 /* To compute the mask to apply after the shift, shift the
10463 nonzero bits of the inner shift the same way the
10464 outer shift will. */
10466 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10470 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10473 /* Give up if we can't compute an outer operation to use. */
10475 || !CONST_INT_P (mask_rtx
)
10476 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10478 result_mode
, &complement_p
))
10481 /* If the shifts are in the same direction, we add the
10482 counts. Otherwise, we subtract them. */
10483 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10484 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10485 count
+= first_count
;
10487 count
-= first_count
;
10489 /* If COUNT is positive, the new shift is usually CODE,
10490 except for the two exceptions below, in which case it is
10491 FIRST_CODE. If the count is negative, FIRST_CODE should
10494 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10495 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10497 else if (count
< 0)
10498 code
= first_code
, count
= -count
;
10500 varop
= XEXP (varop
, 0);
10504 /* If we have (A << B << C) for any shift, we can convert this to
10505 (A << C << B). This wins if A is a constant. Only try this if
10506 B is not a constant. */
10508 else if (GET_CODE (varop
) == code
10509 && CONST_INT_P (XEXP (varop
, 0))
10510 && !CONST_INT_P (XEXP (varop
, 1)))
10512 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10515 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10522 if (VECTOR_MODE_P (mode
))
10525 /* Make this fit the case below. */
10526 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10532 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10533 with C the size of VAROP - 1 and the shift is logical if
10534 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10535 we have an (le X 0) operation. If we have an arithmetic shift
10536 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10537 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10539 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10540 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10541 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10542 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10543 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10544 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10547 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10550 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10551 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10556 /* If we have (shift (logical)), move the logical to the outside
10557 to allow it to possibly combine with another logical and the
10558 shift to combine with another shift. This also canonicalizes to
10559 what a ZERO_EXTRACT looks like. Also, some machines have
10560 (and (shift)) insns. */
10562 if (CONST_INT_P (XEXP (varop
, 1))
10563 /* We can't do this if we have (ashiftrt (xor)) and the
10564 constant has its sign bit set in shift_mode with shift_mode
10565 wider than result_mode. */
10566 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10567 && result_mode
!= shift_mode
10568 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10570 && (new_rtx
= simplify_const_binary_operation
10571 (code
, result_mode
,
10572 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10573 GEN_INT (count
))) != 0
10574 && CONST_INT_P (new_rtx
)
10575 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10576 INTVAL (new_rtx
), result_mode
, &complement_p
))
10578 varop
= XEXP (varop
, 0);
10582 /* If we can't do that, try to simplify the shift in each arm of the
10583 logical expression, make a new logical expression, and apply
10584 the inverse distributive law. This also can't be done for
10585 (ashiftrt (xor)) where we've widened the shift and the constant
10586 changes the sign bit. */
10587 if (CONST_INT_P (XEXP (varop
, 1))
10588 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10589 && result_mode
!= shift_mode
10590 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10593 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10594 XEXP (varop
, 0), count
);
10595 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10596 XEXP (varop
, 1), count
);
10598 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10600 varop
= apply_distributive_law (varop
);
10608 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10609 says that the sign bit can be tested, FOO has mode MODE, C is
10610 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10611 that may be nonzero. */
10612 if (code
== LSHIFTRT
10613 && XEXP (varop
, 1) == const0_rtx
10614 && GET_MODE (XEXP (varop
, 0)) == result_mode
10615 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10616 && HWI_COMPUTABLE_MODE_P (result_mode
)
10617 && STORE_FLAG_VALUE
== -1
10618 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10619 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10622 varop
= XEXP (varop
, 0);
10629 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10630 than the number of bits in the mode is equivalent to A. */
10631 if (code
== LSHIFTRT
10632 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10633 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10635 varop
= XEXP (varop
, 0);
10640 /* NEG commutes with ASHIFT since it is multiplication. Move the
10641 NEG outside to allow shifts to combine. */
10643 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10646 varop
= XEXP (varop
, 0);
10652 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10653 is one less than the number of bits in the mode is
10654 equivalent to (xor A 1). */
10655 if (code
== LSHIFTRT
10656 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10657 && XEXP (varop
, 1) == constm1_rtx
10658 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10659 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10663 varop
= XEXP (varop
, 0);
10667 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10668 that might be nonzero in BAR are those being shifted out and those
10669 bits are known zero in FOO, we can replace the PLUS with FOO.
10670 Similarly in the other operand order. This code occurs when
10671 we are computing the size of a variable-size array. */
10673 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10674 && count
< HOST_BITS_PER_WIDE_INT
10675 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10676 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10677 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10679 varop
= XEXP (varop
, 0);
10682 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10683 && count
< HOST_BITS_PER_WIDE_INT
10684 && HWI_COMPUTABLE_MODE_P (result_mode
)
10685 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10687 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10688 & nonzero_bits (XEXP (varop
, 1),
10691 varop
= XEXP (varop
, 1);
10695 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10697 && CONST_INT_P (XEXP (varop
, 1))
10698 && (new_rtx
= simplify_const_binary_operation
10699 (ASHIFT
, result_mode
,
10700 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10701 GEN_INT (count
))) != 0
10702 && CONST_INT_P (new_rtx
)
10703 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10704 INTVAL (new_rtx
), result_mode
, &complement_p
))
10706 varop
= XEXP (varop
, 0);
10710 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10711 signbit', and attempt to change the PLUS to an XOR and move it to
10712 the outer operation as is done above in the AND/IOR/XOR case
10713 leg for shift(logical). See details in logical handling above
10714 for reasoning in doing so. */
10715 if (code
== LSHIFTRT
10716 && CONST_INT_P (XEXP (varop
, 1))
10717 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10718 && (new_rtx
= simplify_const_binary_operation
10719 (code
, result_mode
,
10720 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10721 GEN_INT (count
))) != 0
10722 && CONST_INT_P (new_rtx
)
10723 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10724 INTVAL (new_rtx
), result_mode
, &complement_p
))
10726 varop
= XEXP (varop
, 0);
10733 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10734 with C the size of VAROP - 1 and the shift is logical if
10735 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10736 we have a (gt X 0) operation. If the shift is arithmetic with
10737 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10738 we have a (neg (gt X 0)) operation. */
10740 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10741 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10742 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10743 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10744 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10745 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10746 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10749 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10752 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10753 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10760 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10761 if the truncate does not affect the value. */
10762 if (code
== LSHIFTRT
10763 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10764 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10765 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10766 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10767 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10769 rtx varop_inner
= XEXP (varop
, 0);
10772 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10773 XEXP (varop_inner
, 0),
10775 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10776 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10789 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10790 outer_op
, outer_const
);
10792 /* We have now finished analyzing the shift. The result should be
10793 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10794 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10795 to the result of the shift. OUTER_CONST is the relevant constant,
10796 but we must turn off all bits turned off in the shift. */
10798 if (outer_op
== UNKNOWN
10799 && orig_code
== code
&& orig_count
== count
10800 && varop
== orig_varop
10801 && shift_mode
== GET_MODE (varop
))
10804 /* Make a SUBREG if necessary. If we can't make it, fail. */
10805 varop
= gen_lowpart (shift_mode
, varop
);
10806 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10809 /* If we have an outer operation and we just made a shift, it is
10810 possible that we could have simplified the shift were it not
10811 for the outer operation. So try to do the simplification
10814 if (outer_op
!= UNKNOWN
)
10815 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10820 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10822 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10823 turn off all the bits that the shift would have turned off. */
10824 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10825 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10826 GET_MODE_MASK (result_mode
) >> orig_count
);
10828 /* Do the remainder of the processing in RESULT_MODE. */
10829 x
= gen_lowpart_or_truncate (result_mode
, x
);
10831 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10834 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10836 if (outer_op
!= UNKNOWN
)
10838 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10839 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10840 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10842 if (outer_op
== AND
)
10843 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10844 else if (outer_op
== SET
)
10846 /* This means that we have determined that the result is
10847 equivalent to a constant. This should be rare. */
10848 if (!side_effects_p (x
))
10849 x
= GEN_INT (outer_const
);
10851 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10852 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10854 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10855 GEN_INT (outer_const
));
10861 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10862 The result of the shift is RESULT_MODE. If we cannot simplify it,
10863 return X or, if it is NULL, synthesize the expression with
10864 simplify_gen_binary. Otherwise, return a simplified value.
10866 The shift is normally computed in the widest mode we find in VAROP, as
10867 long as it isn't a different number of words than RESULT_MODE. Exceptions
10868 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10871 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10872 rtx varop
, int count
)
10874 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10879 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10880 if (GET_MODE (x
) != result_mode
)
10881 x
= gen_lowpart (result_mode
, x
);
10886 /* A subroutine of recog_for_combine. See there for arguments and
10890 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10892 rtx pat
= *pnewpat
;
10893 rtx pat_without_clobbers
;
10894 int insn_code_number
;
10895 int num_clobbers_to_add
= 0;
10897 rtx notes
= NULL_RTX
;
10898 rtx old_notes
, old_pat
;
10901 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10902 we use to indicate that something didn't match. If we find such a
10903 thing, force rejection. */
10904 if (GET_CODE (pat
) == PARALLEL
)
10905 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10906 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10907 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10910 old_pat
= PATTERN (insn
);
10911 old_notes
= REG_NOTES (insn
);
10912 PATTERN (insn
) = pat
;
10913 REG_NOTES (insn
) = NULL_RTX
;
10915 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10916 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10918 if (insn_code_number
< 0)
10919 fputs ("Failed to match this instruction:\n", dump_file
);
10921 fputs ("Successfully matched this instruction:\n", dump_file
);
10922 print_rtl_single (dump_file
, pat
);
10925 /* If it isn't, there is the possibility that we previously had an insn
10926 that clobbered some register as a side effect, but the combined
10927 insn doesn't need to do that. So try once more without the clobbers
10928 unless this represents an ASM insn. */
10930 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10931 && GET_CODE (pat
) == PARALLEL
)
10935 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10936 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10939 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10943 SUBST_INT (XVECLEN (pat
, 0), pos
);
10946 pat
= XVECEXP (pat
, 0, 0);
10948 PATTERN (insn
) = pat
;
10949 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10950 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10952 if (insn_code_number
< 0)
10953 fputs ("Failed to match this instruction:\n", dump_file
);
10955 fputs ("Successfully matched this instruction:\n", dump_file
);
10956 print_rtl_single (dump_file
, pat
);
10960 pat_without_clobbers
= pat
;
10962 PATTERN (insn
) = old_pat
;
10963 REG_NOTES (insn
) = old_notes
;
10965 /* Recognize all noop sets, these will be killed by followup pass. */
10966 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10967 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10969 /* If we had any clobbers to add, make a new pattern than contains
10970 them. Then check to make sure that all of them are dead. */
10971 if (num_clobbers_to_add
)
10973 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10974 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10975 ? (XVECLEN (pat
, 0)
10976 + num_clobbers_to_add
)
10977 : num_clobbers_to_add
+ 1));
10979 if (GET_CODE (pat
) == PARALLEL
)
10980 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10981 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10983 XVECEXP (newpat
, 0, 0) = pat
;
10985 add_clobbers (newpat
, insn_code_number
);
10987 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10988 i
< XVECLEN (newpat
, 0); i
++)
10990 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10991 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10993 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10995 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10996 notes
= alloc_reg_note (REG_UNUSED
,
10997 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11003 if (insn_code_number
>= 0
11004 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11006 old_pat
= PATTERN (insn
);
11007 old_notes
= REG_NOTES (insn
);
11008 old_icode
= INSN_CODE (insn
);
11009 PATTERN (insn
) = pat
;
11010 REG_NOTES (insn
) = notes
;
11012 /* Allow targets to reject combined insn. */
11013 if (!targetm
.legitimate_combined_insn (insn
))
11015 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11016 fputs ("Instruction not appropriate for target.",
11019 /* Callers expect recog_for_combine to strip
11020 clobbers from the pattern on failure. */
11021 pat
= pat_without_clobbers
;
11024 insn_code_number
= -1;
11027 PATTERN (insn
) = old_pat
;
11028 REG_NOTES (insn
) = old_notes
;
11029 INSN_CODE (insn
) = old_icode
;
11035 return insn_code_number
;
11038 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11039 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11040 Return whether anything was so changed. */
11043 change_zero_ext (rtx
*src
)
11045 bool changed
= false;
11047 subrtx_ptr_iterator::array_type array
;
11048 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11051 machine_mode mode
= GET_MODE (x
);
11054 if (GET_CODE (x
) == ZERO_EXTRACT
11055 && CONST_INT_P (XEXP (x
, 1))
11056 && CONST_INT_P (XEXP (x
, 2))
11057 && GET_MODE (XEXP (x
, 0)) == mode
)
11059 size
= INTVAL (XEXP (x
, 1));
11061 int start
= INTVAL (XEXP (x
, 2));
11062 if (BITS_BIG_ENDIAN
)
11063 start
= GET_MODE_PRECISION (mode
) - size
- start
;
11065 x
= gen_rtx_LSHIFTRT (mode
, XEXP (x
, 0), GEN_INT (start
));
11067 else if (GET_CODE (x
) == ZERO_EXTEND
11068 && GET_CODE (XEXP (x
, 0)) == SUBREG
11069 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
11070 && subreg_lowpart_p (XEXP (x
, 0)))
11072 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11073 x
= SUBREG_REG (XEXP (x
, 0));
11078 unsigned HOST_WIDE_INT mask
= 1;
11082 x
= gen_rtx_AND (mode
, x
, GEN_INT (mask
));
11091 /* Like recog, but we receive the address of a pointer to a new pattern.
11092 We try to match the rtx that the pointer points to.
11093 If that fails, we may try to modify or replace the pattern,
11094 storing the replacement into the same pointer object.
11096 Modifications include deletion or addition of CLOBBERs. If the
11097 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11098 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11099 (and undo if that fails).
11101 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11102 the CLOBBERs are placed.
11104 The value is the final insn code from the pattern ultimately matched,
11108 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11110 rtx pat
= PATTERN (insn
);
11111 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11112 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11113 return insn_code_number
;
11115 void *marker
= get_undo_marker ();
11116 bool changed
= false;
11118 if (GET_CODE (pat
) == SET
)
11119 changed
= change_zero_ext (&SET_SRC (pat
));
11120 else if (GET_CODE (pat
) == PARALLEL
)
11123 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11125 rtx set
= XVECEXP (pat
, 0, i
);
11126 if (GET_CODE (set
) == SET
)
11127 changed
|= change_zero_ext (&SET_SRC (set
));
11133 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11135 if (insn_code_number
< 0)
11136 undo_to_marker (marker
);
11139 return insn_code_number
;
11142 /* Like gen_lowpart_general but for use by combine. In combine it
11143 is not possible to create any new pseudoregs. However, it is
11144 safe to create invalid memory addresses, because combine will
11145 try to recognize them and all they will do is make the combine
11148 If for some reason this cannot do its job, an rtx
11149 (clobber (const_int 0)) is returned.
11150 An insn containing that will not be recognized. */
11153 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11155 machine_mode imode
= GET_MODE (x
);
11156 unsigned int osize
= GET_MODE_SIZE (omode
);
11157 unsigned int isize
= GET_MODE_SIZE (imode
);
11160 if (omode
== imode
)
11163 /* We can only support MODE being wider than a word if X is a
11164 constant integer or has a mode the same size. */
11165 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11166 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11169 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11170 won't know what to do. So we will strip off the SUBREG here and
11171 process normally. */
11172 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11174 x
= SUBREG_REG (x
);
11176 /* For use in case we fall down into the address adjustments
11177 further below, we need to adjust the known mode and size of
11178 x; imode and isize, since we just adjusted x. */
11179 imode
= GET_MODE (x
);
11181 if (imode
== omode
)
11184 isize
= GET_MODE_SIZE (imode
);
11187 result
= gen_lowpart_common (omode
, x
);
11196 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11198 if (MEM_VOLATILE_P (x
)
11199 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11202 /* If we want to refer to something bigger than the original memref,
11203 generate a paradoxical subreg instead. That will force a reload
11204 of the original memref X. */
11206 return gen_rtx_SUBREG (omode
, x
, 0);
11208 if (WORDS_BIG_ENDIAN
)
11209 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11211 /* Adjust the address so that the address-after-the-data is
11213 if (BYTES_BIG_ENDIAN
)
11214 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11216 return adjust_address_nv (x
, omode
, offset
);
11219 /* If X is a comparison operator, rewrite it in a new mode. This
11220 probably won't match, but may allow further simplifications. */
11221 else if (COMPARISON_P (x
))
11222 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11224 /* If we couldn't simplify X any other way, just enclose it in a
11225 SUBREG. Normally, this SUBREG won't match, but some patterns may
11226 include an explicit SUBREG or we may simplify it further in combine. */
11232 offset
= subreg_lowpart_offset (omode
, imode
);
11233 if (imode
== VOIDmode
)
11235 imode
= int_mode_for_mode (omode
);
11236 x
= gen_lowpart_common (imode
, x
);
11240 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
11246 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11249 /* Try to simplify a comparison between OP0 and a constant OP1,
11250 where CODE is the comparison code that will be tested, into a
11251 (CODE OP0 const0_rtx) form.
11253 The result is a possibly different comparison code to use.
11254 *POP1 may be updated. */
11256 static enum rtx_code
11257 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11258 rtx op0
, rtx
*pop1
)
11260 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11261 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11263 /* Get the constant we are comparing against and turn off all bits
11264 not on in our mode. */
11265 if (mode
!= VOIDmode
)
11266 const_op
= trunc_int_for_mode (const_op
, mode
);
11268 /* If we are comparing against a constant power of two and the value
11269 being compared can only have that single bit nonzero (e.g., it was
11270 `and'ed with that bit), we can replace this with a comparison
11273 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11274 || code
== LT
|| code
== LTU
)
11275 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11276 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
11277 && (nonzero_bits (op0
, mode
)
11278 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11280 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11284 /* Similarly, if we are comparing a value known to be either -1 or
11285 0 with -1, change it to the opposite comparison against zero. */
11287 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11288 || code
== GEU
|| code
== LTU
)
11289 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11291 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11295 /* Do some canonicalizations based on the comparison code. We prefer
11296 comparisons against zero and then prefer equality comparisons.
11297 If we can reduce the size of a constant, we will do that too. */
11301 /* < C is equivalent to <= (C - 1) */
11306 /* ... fall through to LE case below. */
11312 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11319 /* If we are doing a <= 0 comparison on a value known to have
11320 a zero sign bit, we can replace this with == 0. */
11321 else if (const_op
== 0
11322 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11323 && (nonzero_bits (op0
, mode
)
11324 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11330 /* >= C is equivalent to > (C - 1). */
11335 /* ... fall through to GT below. */
11341 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11348 /* If we are doing a > 0 comparison on a value known to have
11349 a zero sign bit, we can replace this with != 0. */
11350 else if (const_op
== 0
11351 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11352 && (nonzero_bits (op0
, mode
)
11353 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11359 /* < C is equivalent to <= (C - 1). */
11364 /* ... fall through ... */
11366 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11367 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11368 && (unsigned HOST_WIDE_INT
) const_op
11369 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11379 /* unsigned <= 0 is equivalent to == 0 */
11382 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11383 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11384 && (unsigned HOST_WIDE_INT
) const_op
11385 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11393 /* >= C is equivalent to > (C - 1). */
11398 /* ... fall through ... */
11401 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11402 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11403 && (unsigned HOST_WIDE_INT
) const_op
11404 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11414 /* unsigned > 0 is equivalent to != 0 */
11417 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11418 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11419 && (unsigned HOST_WIDE_INT
) const_op
11420 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11431 *pop1
= GEN_INT (const_op
);
11435 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11436 comparison code that will be tested.
11438 The result is a possibly different comparison code to use. *POP0 and
11439 *POP1 may be updated.
11441 It is possible that we might detect that a comparison is either always
11442 true or always false. However, we do not perform general constant
11443 folding in combine, so this knowledge isn't useful. Such tautologies
11444 should have been detected earlier. Hence we ignore all such cases. */
11446 static enum rtx_code
11447 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11453 machine_mode mode
, tmode
;
11455 /* Try a few ways of applying the same transformation to both operands. */
11458 #ifndef WORD_REGISTER_OPERATIONS
11459 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11460 so check specially. */
11461 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11462 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11463 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11464 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11465 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11466 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11467 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11468 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11469 && CONST_INT_P (XEXP (op0
, 1))
11470 && XEXP (op0
, 1) == XEXP (op1
, 1)
11471 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11472 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11473 && (INTVAL (XEXP (op0
, 1))
11474 == (GET_MODE_PRECISION (GET_MODE (op0
))
11475 - (GET_MODE_PRECISION
11476 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11478 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11479 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11483 /* If both operands are the same constant shift, see if we can ignore the
11484 shift. We can if the shift is a rotate or if the bits shifted out of
11485 this shift are known to be zero for both inputs and if the type of
11486 comparison is compatible with the shift. */
11487 if (GET_CODE (op0
) == GET_CODE (op1
)
11488 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11489 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11490 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11491 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11492 || (GET_CODE (op0
) == ASHIFTRT
11493 && (code
!= GTU
&& code
!= LTU
11494 && code
!= GEU
&& code
!= LEU
)))
11495 && CONST_INT_P (XEXP (op0
, 1))
11496 && INTVAL (XEXP (op0
, 1)) >= 0
11497 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11498 && XEXP (op0
, 1) == XEXP (op1
, 1))
11500 machine_mode mode
= GET_MODE (op0
);
11501 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11502 int shift_count
= INTVAL (XEXP (op0
, 1));
11504 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11505 mask
&= (mask
>> shift_count
) << shift_count
;
11506 else if (GET_CODE (op0
) == ASHIFT
)
11507 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11509 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11510 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11511 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11516 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11517 SUBREGs are of the same mode, and, in both cases, the AND would
11518 be redundant if the comparison was done in the narrower mode,
11519 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11520 and the operand's possibly nonzero bits are 0xffffff01; in that case
11521 if we only care about QImode, we don't need the AND). This case
11522 occurs if the output mode of an scc insn is not SImode and
11523 STORE_FLAG_VALUE == 1 (e.g., the 386).
11525 Similarly, check for a case where the AND's are ZERO_EXTEND
11526 operations from some narrower mode even though a SUBREG is not
11529 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11530 && CONST_INT_P (XEXP (op0
, 1))
11531 && CONST_INT_P (XEXP (op1
, 1)))
11533 rtx inner_op0
= XEXP (op0
, 0);
11534 rtx inner_op1
= XEXP (op1
, 0);
11535 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11536 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11539 if (paradoxical_subreg_p (inner_op0
)
11540 && GET_CODE (inner_op1
) == SUBREG
11541 && (GET_MODE (SUBREG_REG (inner_op0
))
11542 == GET_MODE (SUBREG_REG (inner_op1
)))
11543 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11544 <= HOST_BITS_PER_WIDE_INT
)
11545 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11546 GET_MODE (SUBREG_REG (inner_op0
)))))
11547 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11548 GET_MODE (SUBREG_REG (inner_op1
))))))
11550 op0
= SUBREG_REG (inner_op0
);
11551 op1
= SUBREG_REG (inner_op1
);
11553 /* The resulting comparison is always unsigned since we masked
11554 off the original sign bit. */
11555 code
= unsigned_condition (code
);
11561 for (tmode
= GET_CLASS_NARROWEST_MODE
11562 (GET_MODE_CLASS (GET_MODE (op0
)));
11563 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11564 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11566 op0
= gen_lowpart (tmode
, inner_op0
);
11567 op1
= gen_lowpart (tmode
, inner_op1
);
11568 code
= unsigned_condition (code
);
11577 /* If both operands are NOT, we can strip off the outer operation
11578 and adjust the comparison code for swapped operands; similarly for
11579 NEG, except that this must be an equality comparison. */
11580 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11581 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11582 && (code
== EQ
|| code
== NE
)))
11583 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11589 /* If the first operand is a constant, swap the operands and adjust the
11590 comparison code appropriately, but don't do this if the second operand
11591 is already a constant integer. */
11592 if (swap_commutative_operands_p (op0
, op1
))
11594 std::swap (op0
, op1
);
11595 code
= swap_condition (code
);
11598 /* We now enter a loop during which we will try to simplify the comparison.
11599 For the most part, we only are concerned with comparisons with zero,
11600 but some things may really be comparisons with zero but not start
11601 out looking that way. */
11603 while (CONST_INT_P (op1
))
11605 machine_mode mode
= GET_MODE (op0
);
11606 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11607 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11608 int equality_comparison_p
;
11609 int sign_bit_comparison_p
;
11610 int unsigned_comparison_p
;
11611 HOST_WIDE_INT const_op
;
11613 /* We only want to handle integral modes. This catches VOIDmode,
11614 CCmode, and the floating-point modes. An exception is that we
11615 can handle VOIDmode if OP0 is a COMPARE or a comparison
11618 if (GET_MODE_CLASS (mode
) != MODE_INT
11619 && ! (mode
== VOIDmode
11620 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11623 /* Try to simplify the compare to constant, possibly changing the
11624 comparison op, and/or changing op1 to zero. */
11625 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11626 const_op
= INTVAL (op1
);
11628 /* Compute some predicates to simplify code below. */
11630 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11631 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11632 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11635 /* If this is a sign bit comparison and we can do arithmetic in
11636 MODE, say that we will only be needing the sign bit of OP0. */
11637 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11638 op0
= force_to_mode (op0
, mode
,
11639 (unsigned HOST_WIDE_INT
) 1
11640 << (GET_MODE_PRECISION (mode
) - 1),
11643 /* Now try cases based on the opcode of OP0. If none of the cases
11644 does a "continue", we exit this loop immediately after the
11647 switch (GET_CODE (op0
))
11650 /* If we are extracting a single bit from a variable position in
11651 a constant that has only a single bit set and are comparing it
11652 with zero, we can convert this into an equality comparison
11653 between the position and the location of the single bit. */
11654 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11655 have already reduced the shift count modulo the word size. */
11656 if (!SHIFT_COUNT_TRUNCATED
11657 && CONST_INT_P (XEXP (op0
, 0))
11658 && XEXP (op0
, 1) == const1_rtx
11659 && equality_comparison_p
&& const_op
== 0
11660 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11662 if (BITS_BIG_ENDIAN
)
11663 i
= BITS_PER_WORD
- 1 - i
;
11665 op0
= XEXP (op0
, 2);
11669 /* Result is nonzero iff shift count is equal to I. */
11670 code
= reverse_condition (code
);
11674 /* ... fall through ... */
11677 tem
= expand_compound_operation (op0
);
11686 /* If testing for equality, we can take the NOT of the constant. */
11687 if (equality_comparison_p
11688 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11690 op0
= XEXP (op0
, 0);
11695 /* If just looking at the sign bit, reverse the sense of the
11697 if (sign_bit_comparison_p
)
11699 op0
= XEXP (op0
, 0);
11700 code
= (code
== GE
? LT
: GE
);
11706 /* If testing for equality, we can take the NEG of the constant. */
11707 if (equality_comparison_p
11708 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11710 op0
= XEXP (op0
, 0);
11715 /* The remaining cases only apply to comparisons with zero. */
11719 /* When X is ABS or is known positive,
11720 (neg X) is < 0 if and only if X != 0. */
11722 if (sign_bit_comparison_p
11723 && (GET_CODE (XEXP (op0
, 0)) == ABS
11724 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11725 && (nonzero_bits (XEXP (op0
, 0), mode
)
11726 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11729 op0
= XEXP (op0
, 0);
11730 code
= (code
== LT
? NE
: EQ
);
11734 /* If we have NEG of something whose two high-order bits are the
11735 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11736 if (num_sign_bit_copies (op0
, mode
) >= 2)
11738 op0
= XEXP (op0
, 0);
11739 code
= swap_condition (code
);
11745 /* If we are testing equality and our count is a constant, we
11746 can perform the inverse operation on our RHS. */
11747 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11748 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11749 op1
, XEXP (op0
, 1))) != 0)
11751 op0
= XEXP (op0
, 0);
11756 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11757 a particular bit. Convert it to an AND of a constant of that
11758 bit. This will be converted into a ZERO_EXTRACT. */
11759 if (const_op
== 0 && sign_bit_comparison_p
11760 && CONST_INT_P (XEXP (op0
, 1))
11761 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11763 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11764 ((unsigned HOST_WIDE_INT
) 1
11766 - INTVAL (XEXP (op0
, 1)))));
11767 code
= (code
== LT
? NE
: EQ
);
11771 /* Fall through. */
11774 /* ABS is ignorable inside an equality comparison with zero. */
11775 if (const_op
== 0 && equality_comparison_p
)
11777 op0
= XEXP (op0
, 0);
11783 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11784 (compare FOO CONST) if CONST fits in FOO's mode and we
11785 are either testing inequality or have an unsigned
11786 comparison with ZERO_EXTEND or a signed comparison with
11787 SIGN_EXTEND. But don't do it if we don't have a compare
11788 insn of the given mode, since we'd have to revert it
11789 later on, and then we wouldn't know whether to sign- or
11791 mode
= GET_MODE (XEXP (op0
, 0));
11792 if (GET_MODE_CLASS (mode
) == MODE_INT
11793 && ! unsigned_comparison_p
11794 && HWI_COMPUTABLE_MODE_P (mode
)
11795 && trunc_int_for_mode (const_op
, mode
) == const_op
11796 && have_insn_for (COMPARE
, mode
))
11798 op0
= XEXP (op0
, 0);
11804 /* Check for the case where we are comparing A - C1 with C2, that is
11806 (subreg:MODE (plus (A) (-C1))) op (C2)
11808 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11809 comparison in the wider mode. One of the following two conditions
11810 must be true in order for this to be valid:
11812 1. The mode extension results in the same bit pattern being added
11813 on both sides and the comparison is equality or unsigned. As
11814 C2 has been truncated to fit in MODE, the pattern can only be
11817 2. The mode extension results in the sign bit being copied on
11820 The difficulty here is that we have predicates for A but not for
11821 (A - C1) so we need to check that C1 is within proper bounds so
11822 as to perturbate A as little as possible. */
11824 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11825 && subreg_lowpart_p (op0
)
11826 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11827 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11828 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11830 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11831 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11832 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11835 && (unsigned HOST_WIDE_INT
) c1
11836 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11837 && (equality_comparison_p
|| unsigned_comparison_p
)
11838 /* (A - C1) zero-extends if it is positive and sign-extends
11839 if it is negative, C2 both zero- and sign-extends. */
11840 && ((0 == (nonzero_bits (a
, inner_mode
)
11841 & ~GET_MODE_MASK (mode
))
11843 /* (A - C1) sign-extends if it is positive and 1-extends
11844 if it is negative, C2 both sign- and 1-extends. */
11845 || (num_sign_bit_copies (a
, inner_mode
)
11846 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11849 || ((unsigned HOST_WIDE_INT
) c1
11850 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11851 /* (A - C1) always sign-extends, like C2. */
11852 && num_sign_bit_copies (a
, inner_mode
)
11853 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11854 - (mode_width
- 1))))
11856 op0
= SUBREG_REG (op0
);
11861 /* If the inner mode is narrower and we are extracting the low part,
11862 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11863 if (subreg_lowpart_p (op0
)
11864 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11865 /* Fall through */ ;
11869 /* ... fall through ... */
11872 mode
= GET_MODE (XEXP (op0
, 0));
11873 if (GET_MODE_CLASS (mode
) == MODE_INT
11874 && (unsigned_comparison_p
|| equality_comparison_p
)
11875 && HWI_COMPUTABLE_MODE_P (mode
)
11876 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11878 && have_insn_for (COMPARE
, mode
))
11880 op0
= XEXP (op0
, 0);
11886 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11887 this for equality comparisons due to pathological cases involving
11889 if (equality_comparison_p
11890 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11891 op1
, XEXP (op0
, 1))))
11893 op0
= XEXP (op0
, 0);
11898 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11899 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11900 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11902 op0
= XEXP (XEXP (op0
, 0), 0);
11903 code
= (code
== LT
? EQ
: NE
);
11909 /* We used to optimize signed comparisons against zero, but that
11910 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11911 arrive here as equality comparisons, or (GEU, LTU) are
11912 optimized away. No need to special-case them. */
11914 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11915 (eq B (minus A C)), whichever simplifies. We can only do
11916 this for equality comparisons due to pathological cases involving
11918 if (equality_comparison_p
11919 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11920 XEXP (op0
, 1), op1
)))
11922 op0
= XEXP (op0
, 0);
11927 if (equality_comparison_p
11928 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11929 XEXP (op0
, 0), op1
)))
11931 op0
= XEXP (op0
, 1);
11936 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11937 of bits in X minus 1, is one iff X > 0. */
11938 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11939 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11940 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11941 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11943 op0
= XEXP (op0
, 1);
11944 code
= (code
== GE
? LE
: GT
);
11950 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11951 if C is zero or B is a constant. */
11952 if (equality_comparison_p
11953 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11954 XEXP (op0
, 1), op1
)))
11956 op0
= XEXP (op0
, 0);
11963 case UNEQ
: case LTGT
:
11964 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11965 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11966 case UNORDERED
: case ORDERED
:
11967 /* We can't do anything if OP0 is a condition code value, rather
11968 than an actual data value. */
11970 || CC0_P (XEXP (op0
, 0))
11971 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11974 /* Get the two operands being compared. */
11975 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11976 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11978 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11980 /* Check for the cases where we simply want the result of the
11981 earlier test or the opposite of that result. */
11982 if (code
== NE
|| code
== EQ
11983 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11984 && (code
== LT
|| code
== GE
)))
11986 enum rtx_code new_code
;
11987 if (code
== LT
|| code
== NE
)
11988 new_code
= GET_CODE (op0
);
11990 new_code
= reversed_comparison_code (op0
, NULL
);
11992 if (new_code
!= UNKNOWN
)
12003 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12005 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12006 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12007 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12009 op0
= XEXP (op0
, 1);
12010 code
= (code
== GE
? GT
: LE
);
12016 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12017 will be converted to a ZERO_EXTRACT later. */
12018 if (const_op
== 0 && equality_comparison_p
12019 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12020 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12022 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12023 XEXP (XEXP (op0
, 0), 1));
12024 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12028 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12029 zero and X is a comparison and C1 and C2 describe only bits set
12030 in STORE_FLAG_VALUE, we can compare with X. */
12031 if (const_op
== 0 && equality_comparison_p
12032 && mode_width
<= HOST_BITS_PER_WIDE_INT
12033 && CONST_INT_P (XEXP (op0
, 1))
12034 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12035 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12036 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12037 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12039 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12040 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12041 if ((~STORE_FLAG_VALUE
& mask
) == 0
12042 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12043 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12044 && COMPARISON_P (tem
))))
12046 op0
= XEXP (XEXP (op0
, 0), 0);
12051 /* If we are doing an equality comparison of an AND of a bit equal
12052 to the sign bit, replace this with a LT or GE comparison of
12053 the underlying value. */
12054 if (equality_comparison_p
12056 && CONST_INT_P (XEXP (op0
, 1))
12057 && mode_width
<= HOST_BITS_PER_WIDE_INT
12058 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12059 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
12061 op0
= XEXP (op0
, 0);
12062 code
= (code
== EQ
? GE
: LT
);
12066 /* If this AND operation is really a ZERO_EXTEND from a narrower
12067 mode, the constant fits within that mode, and this is either an
12068 equality or unsigned comparison, try to do this comparison in
12073 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12074 -> (ne:DI (reg:SI 4) (const_int 0))
12076 unless TRULY_NOOP_TRUNCATION allows it or the register is
12077 known to hold a value of the required mode the
12078 transformation is invalid. */
12079 if ((equality_comparison_p
|| unsigned_comparison_p
)
12080 && CONST_INT_P (XEXP (op0
, 1))
12081 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12082 & GET_MODE_MASK (mode
))
12084 && const_op
>> i
== 0
12085 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
12086 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
12087 || (REG_P (XEXP (op0
, 0))
12088 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
12090 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
12094 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12095 fits in both M1 and M2 and the SUBREG is either paradoxical
12096 or represents the low part, permute the SUBREG and the AND
12098 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
12100 unsigned HOST_WIDE_INT c1
;
12101 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12102 /* Require an integral mode, to avoid creating something like
12104 if (SCALAR_INT_MODE_P (tmode
)
12105 /* It is unsafe to commute the AND into the SUBREG if the
12106 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12107 not defined. As originally written the upper bits
12108 have a defined value due to the AND operation.
12109 However, if we commute the AND inside the SUBREG then
12110 they no longer have defined values and the meaning of
12111 the code has been changed. */
12113 #ifdef WORD_REGISTER_OPERATIONS
12114 || (mode_width
> GET_MODE_PRECISION (tmode
)
12115 && mode_width
<= BITS_PER_WORD
)
12117 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12118 && subreg_lowpart_p (XEXP (op0
, 0))))
12119 && CONST_INT_P (XEXP (op0
, 1))
12120 && mode_width
<= HOST_BITS_PER_WIDE_INT
12121 && HWI_COMPUTABLE_MODE_P (tmode
)
12122 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
12123 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12125 && c1
!= GET_MODE_MASK (tmode
))
12127 op0
= simplify_gen_binary (AND
, tmode
,
12128 SUBREG_REG (XEXP (op0
, 0)),
12129 gen_int_mode (c1
, tmode
));
12130 op0
= gen_lowpart (mode
, op0
);
12135 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12136 if (const_op
== 0 && equality_comparison_p
12137 && XEXP (op0
, 1) == const1_rtx
12138 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12140 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12141 XEXP (XEXP (op0
, 0), 0), 1);
12142 code
= (code
== NE
? EQ
: NE
);
12146 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12147 (eq (and (lshiftrt X) 1) 0).
12148 Also handle the case where (not X) is expressed using xor. */
12149 if (const_op
== 0 && equality_comparison_p
12150 && XEXP (op0
, 1) == const1_rtx
12151 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12153 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12154 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12156 if (GET_CODE (shift_op
) == NOT
12157 || (GET_CODE (shift_op
) == XOR
12158 && CONST_INT_P (XEXP (shift_op
, 1))
12159 && CONST_INT_P (shift_count
)
12160 && HWI_COMPUTABLE_MODE_P (mode
)
12161 && (UINTVAL (XEXP (shift_op
, 1))
12162 == (unsigned HOST_WIDE_INT
) 1
12163 << INTVAL (shift_count
))))
12166 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12167 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12168 code
= (code
== NE
? EQ
: NE
);
12175 /* If we have (compare (ashift FOO N) (const_int C)) and
12176 the high order N bits of FOO (N+1 if an inequality comparison)
12177 are known to be zero, we can do this by comparing FOO with C
12178 shifted right N bits so long as the low-order N bits of C are
12180 if (CONST_INT_P (XEXP (op0
, 1))
12181 && INTVAL (XEXP (op0
, 1)) >= 0
12182 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12183 < HOST_BITS_PER_WIDE_INT
)
12184 && (((unsigned HOST_WIDE_INT
) const_op
12185 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
12187 && mode_width
<= HOST_BITS_PER_WIDE_INT
12188 && (nonzero_bits (XEXP (op0
, 0), mode
)
12189 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12190 + ! equality_comparison_p
))) == 0)
12192 /* We must perform a logical shift, not an arithmetic one,
12193 as we want the top N bits of C to be zero. */
12194 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12196 temp
>>= INTVAL (XEXP (op0
, 1));
12197 op1
= gen_int_mode (temp
, mode
);
12198 op0
= XEXP (op0
, 0);
12202 /* If we are doing a sign bit comparison, it means we are testing
12203 a particular bit. Convert it to the appropriate AND. */
12204 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12205 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12207 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12208 ((unsigned HOST_WIDE_INT
) 1
12210 - INTVAL (XEXP (op0
, 1)))));
12211 code
= (code
== LT
? NE
: EQ
);
12215 /* If this an equality comparison with zero and we are shifting
12216 the low bit to the sign bit, we can convert this to an AND of the
12218 if (const_op
== 0 && equality_comparison_p
12219 && CONST_INT_P (XEXP (op0
, 1))
12220 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12222 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12228 /* If this is an equality comparison with zero, we can do this
12229 as a logical shift, which might be much simpler. */
12230 if (equality_comparison_p
&& const_op
== 0
12231 && CONST_INT_P (XEXP (op0
, 1)))
12233 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12235 INTVAL (XEXP (op0
, 1)));
12239 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12240 do the comparison in a narrower mode. */
12241 if (! unsigned_comparison_p
12242 && CONST_INT_P (XEXP (op0
, 1))
12243 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12244 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12245 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12246 MODE_INT
, 1)) != BLKmode
12247 && (((unsigned HOST_WIDE_INT
) const_op
12248 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12249 <= GET_MODE_MASK (tmode
)))
12251 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12255 /* Likewise if OP0 is a PLUS of a sign extension with a
12256 constant, which is usually represented with the PLUS
12257 between the shifts. */
12258 if (! unsigned_comparison_p
12259 && CONST_INT_P (XEXP (op0
, 1))
12260 && GET_CODE (XEXP (op0
, 0)) == PLUS
12261 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12262 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12263 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12264 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12265 MODE_INT
, 1)) != BLKmode
12266 && (((unsigned HOST_WIDE_INT
) const_op
12267 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12268 <= GET_MODE_MASK (tmode
)))
12270 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12271 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12272 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12273 add_const
, XEXP (op0
, 1));
12275 op0
= simplify_gen_binary (PLUS
, tmode
,
12276 gen_lowpart (tmode
, inner
),
12281 /* ... fall through ... */
12283 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12284 the low order N bits of FOO are known to be zero, we can do this
12285 by comparing FOO with C shifted left N bits so long as no
12286 overflow occurs. Even if the low order N bits of FOO aren't known
12287 to be zero, if the comparison is >= or < we can use the same
12288 optimization and for > or <= by setting all the low
12289 order N bits in the comparison constant. */
12290 if (CONST_INT_P (XEXP (op0
, 1))
12291 && INTVAL (XEXP (op0
, 1)) > 0
12292 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12293 && mode_width
<= HOST_BITS_PER_WIDE_INT
12294 && (((unsigned HOST_WIDE_INT
) const_op
12295 + (GET_CODE (op0
) != LSHIFTRT
12296 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12299 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12301 unsigned HOST_WIDE_INT low_bits
12302 = (nonzero_bits (XEXP (op0
, 0), mode
)
12303 & (((unsigned HOST_WIDE_INT
) 1
12304 << INTVAL (XEXP (op0
, 1))) - 1));
12305 if (low_bits
== 0 || !equality_comparison_p
)
12307 /* If the shift was logical, then we must make the condition
12309 if (GET_CODE (op0
) == LSHIFTRT
)
12310 code
= unsigned_condition (code
);
12312 const_op
<<= INTVAL (XEXP (op0
, 1));
12314 && (code
== GT
|| code
== GTU
12315 || code
== LE
|| code
== LEU
))
12317 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
12318 op1
= GEN_INT (const_op
);
12319 op0
= XEXP (op0
, 0);
12324 /* If we are using this shift to extract just the sign bit, we
12325 can replace this with an LT or GE comparison. */
12327 && (equality_comparison_p
|| sign_bit_comparison_p
)
12328 && CONST_INT_P (XEXP (op0
, 1))
12329 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12331 op0
= XEXP (op0
, 0);
12332 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12344 /* Now make any compound operations involved in this comparison. Then,
12345 check for an outmost SUBREG on OP0 that is not doing anything or is
12346 paradoxical. The latter transformation must only be performed when
12347 it is known that the "extra" bits will be the same in op0 and op1 or
12348 that they don't matter. There are three cases to consider:
12350 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12351 care bits and we can assume they have any convenient value. So
12352 making the transformation is safe.
12354 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12355 In this case the upper bits of op0 are undefined. We should not make
12356 the simplification in that case as we do not know the contents of
12359 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12360 UNKNOWN. In that case we know those bits are zeros or ones. We must
12361 also be sure that they are the same as the upper bits of op1.
12363 We can never remove a SUBREG for a non-equality comparison because
12364 the sign bit is in a different place in the underlying object. */
12366 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12367 op1
= make_compound_operation (op1
, SET
);
12369 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12370 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12371 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12372 && (code
== NE
|| code
== EQ
))
12374 if (paradoxical_subreg_p (op0
))
12376 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12378 if (REG_P (SUBREG_REG (op0
)))
12380 op0
= SUBREG_REG (op0
);
12381 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12384 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12385 <= HOST_BITS_PER_WIDE_INT
)
12386 && (nonzero_bits (SUBREG_REG (op0
),
12387 GET_MODE (SUBREG_REG (op0
)))
12388 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12390 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12392 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12393 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12394 op0
= SUBREG_REG (op0
), op1
= tem
;
12398 /* We now do the opposite procedure: Some machines don't have compare
12399 insns in all modes. If OP0's mode is an integer mode smaller than a
12400 word and we can't do a compare in that mode, see if there is a larger
12401 mode for which we can do the compare. There are a number of cases in
12402 which we can use the wider mode. */
12404 mode
= GET_MODE (op0
);
12405 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12406 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12407 && ! have_insn_for (COMPARE
, mode
))
12408 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12409 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12410 tmode
= GET_MODE_WIDER_MODE (tmode
))
12411 if (have_insn_for (COMPARE
, tmode
))
12415 /* If this is a test for negative, we can make an explicit
12416 test of the sign bit. Test this first so we can use
12417 a paradoxical subreg to extend OP0. */
12419 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12420 && HWI_COMPUTABLE_MODE_P (mode
))
12422 unsigned HOST_WIDE_INT sign
12423 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12424 op0
= simplify_gen_binary (AND
, tmode
,
12425 gen_lowpart (tmode
, op0
),
12426 gen_int_mode (sign
, tmode
));
12427 code
= (code
== LT
) ? NE
: EQ
;
12431 /* If the only nonzero bits in OP0 and OP1 are those in the
12432 narrower mode and this is an equality or unsigned comparison,
12433 we can use the wider mode. Similarly for sign-extended
12434 values, in which case it is true for all comparisons. */
12435 zero_extended
= ((code
== EQ
|| code
== NE
12436 || code
== GEU
|| code
== GTU
12437 || code
== LEU
|| code
== LTU
)
12438 && (nonzero_bits (op0
, tmode
)
12439 & ~GET_MODE_MASK (mode
)) == 0
12440 && ((CONST_INT_P (op1
)
12441 || (nonzero_bits (op1
, tmode
)
12442 & ~GET_MODE_MASK (mode
)) == 0)));
12445 || ((num_sign_bit_copies (op0
, tmode
)
12446 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12447 - GET_MODE_PRECISION (mode
)))
12448 && (num_sign_bit_copies (op1
, tmode
)
12449 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12450 - GET_MODE_PRECISION (mode
)))))
12452 /* If OP0 is an AND and we don't have an AND in MODE either,
12453 make a new AND in the proper mode. */
12454 if (GET_CODE (op0
) == AND
12455 && !have_insn_for (AND
, mode
))
12456 op0
= simplify_gen_binary (AND
, tmode
,
12457 gen_lowpart (tmode
,
12459 gen_lowpart (tmode
,
12465 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12466 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12470 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12471 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12478 /* We may have changed the comparison operands. Re-canonicalize. */
12479 if (swap_commutative_operands_p (op0
, op1
))
12481 std::swap (op0
, op1
);
12482 code
= swap_condition (code
);
12485 /* If this machine only supports a subset of valid comparisons, see if we
12486 can convert an unsupported one into a supported one. */
12487 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12495 /* Utility function for record_value_for_reg. Count number of
12500 enum rtx_code code
= GET_CODE (x
);
12504 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12505 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12507 rtx x0
= XEXP (x
, 0);
12508 rtx x1
= XEXP (x
, 1);
12511 return 1 + 2 * count_rtxs (x0
);
12513 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12514 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12515 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12516 return 2 + 2 * count_rtxs (x0
)
12517 + count_rtxs (x
== XEXP (x1
, 0)
12518 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12520 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12521 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12522 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12523 return 2 + 2 * count_rtxs (x1
)
12524 + count_rtxs (x
== XEXP (x0
, 0)
12525 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12528 fmt
= GET_RTX_FORMAT (code
);
12529 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12531 ret
+= count_rtxs (XEXP (x
, i
));
12532 else if (fmt
[i
] == 'E')
12533 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12534 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12539 /* Utility function for following routine. Called when X is part of a value
12540 being stored into last_set_value. Sets last_set_table_tick
12541 for each register mentioned. Similar to mention_regs in cse.c */
12544 update_table_tick (rtx x
)
12546 enum rtx_code code
= GET_CODE (x
);
12547 const char *fmt
= GET_RTX_FORMAT (code
);
12552 unsigned int regno
= REGNO (x
);
12553 unsigned int endregno
= END_REGNO (x
);
12556 for (r
= regno
; r
< endregno
; r
++)
12558 reg_stat_type
*rsp
= ®_stat
[r
];
12559 rsp
->last_set_table_tick
= label_tick
;
12565 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12568 /* Check for identical subexpressions. If x contains
12569 identical subexpression we only have to traverse one of
12571 if (i
== 0 && ARITHMETIC_P (x
))
12573 /* Note that at this point x1 has already been
12575 rtx x0
= XEXP (x
, 0);
12576 rtx x1
= XEXP (x
, 1);
12578 /* If x0 and x1 are identical then there is no need to
12583 /* If x0 is identical to a subexpression of x1 then while
12584 processing x1, x0 has already been processed. Thus we
12585 are done with x. */
12586 if (ARITHMETIC_P (x1
)
12587 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12590 /* If x1 is identical to a subexpression of x0 then we
12591 still have to process the rest of x0. */
12592 if (ARITHMETIC_P (x0
)
12593 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12595 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12600 update_table_tick (XEXP (x
, i
));
12602 else if (fmt
[i
] == 'E')
12603 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12604 update_table_tick (XVECEXP (x
, i
, j
));
12607 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12608 are saying that the register is clobbered and we no longer know its
12609 value. If INSN is zero, don't update reg_stat[].last_set; this is
12610 only permitted with VALUE also zero and is used to invalidate the
12614 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12616 unsigned int regno
= REGNO (reg
);
12617 unsigned int endregno
= END_REGNO (reg
);
12619 reg_stat_type
*rsp
;
12621 /* If VALUE contains REG and we have a previous value for REG, substitute
12622 the previous value. */
12623 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12627 /* Set things up so get_last_value is allowed to see anything set up to
12629 subst_low_luid
= DF_INSN_LUID (insn
);
12630 tem
= get_last_value (reg
);
12632 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12633 it isn't going to be useful and will take a lot of time to process,
12634 so just use the CLOBBER. */
12638 if (ARITHMETIC_P (tem
)
12639 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12640 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12641 tem
= XEXP (tem
, 0);
12642 else if (count_occurrences (value
, reg
, 1) >= 2)
12644 /* If there are two or more occurrences of REG in VALUE,
12645 prevent the value from growing too much. */
12646 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12647 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12650 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12654 /* For each register modified, show we don't know its value, that
12655 we don't know about its bitwise content, that its value has been
12656 updated, and that we don't know the location of the death of the
12658 for (i
= regno
; i
< endregno
; i
++)
12660 rsp
= ®_stat
[i
];
12663 rsp
->last_set
= insn
;
12665 rsp
->last_set_value
= 0;
12666 rsp
->last_set_mode
= VOIDmode
;
12667 rsp
->last_set_nonzero_bits
= 0;
12668 rsp
->last_set_sign_bit_copies
= 0;
12669 rsp
->last_death
= 0;
12670 rsp
->truncated_to_mode
= VOIDmode
;
12673 /* Mark registers that are being referenced in this value. */
12675 update_table_tick (value
);
12677 /* Now update the status of each register being set.
12678 If someone is using this register in this block, set this register
12679 to invalid since we will get confused between the two lives in this
12680 basic block. This makes using this register always invalid. In cse, we
12681 scan the table to invalidate all entries using this register, but this
12682 is too much work for us. */
12684 for (i
= regno
; i
< endregno
; i
++)
12686 rsp
= ®_stat
[i
];
12687 rsp
->last_set_label
= label_tick
;
12689 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12690 rsp
->last_set_invalid
= 1;
12692 rsp
->last_set_invalid
= 0;
12695 /* The value being assigned might refer to X (like in "x++;"). In that
12696 case, we must replace it with (clobber (const_int 0)) to prevent
12698 rsp
= ®_stat
[regno
];
12699 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12701 value
= copy_rtx (value
);
12702 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12706 /* For the main register being modified, update the value, the mode, the
12707 nonzero bits, and the number of sign bit copies. */
12709 rsp
->last_set_value
= value
;
12713 machine_mode mode
= GET_MODE (reg
);
12714 subst_low_luid
= DF_INSN_LUID (insn
);
12715 rsp
->last_set_mode
= mode
;
12716 if (GET_MODE_CLASS (mode
) == MODE_INT
12717 && HWI_COMPUTABLE_MODE_P (mode
))
12718 mode
= nonzero_bits_mode
;
12719 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12720 rsp
->last_set_sign_bit_copies
12721 = num_sign_bit_copies (value
, GET_MODE (reg
));
12725 /* Called via note_stores from record_dead_and_set_regs to handle one
12726 SET or CLOBBER in an insn. DATA is the instruction in which the
12727 set is occurring. */
12730 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12732 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12734 if (GET_CODE (dest
) == SUBREG
)
12735 dest
= SUBREG_REG (dest
);
12737 if (!record_dead_insn
)
12740 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12746 /* If we are setting the whole register, we know its value. Otherwise
12747 show that we don't know the value. We can handle SUBREG in
12749 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12750 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12751 else if (GET_CODE (setter
) == SET
12752 && GET_CODE (SET_DEST (setter
)) == SUBREG
12753 && SUBREG_REG (SET_DEST (setter
)) == dest
12754 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12755 && subreg_lowpart_p (SET_DEST (setter
)))
12756 record_value_for_reg (dest
, record_dead_insn
,
12757 gen_lowpart (GET_MODE (dest
),
12758 SET_SRC (setter
)));
12760 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12762 else if (MEM_P (dest
)
12763 /* Ignore pushes, they clobber nothing. */
12764 && ! push_operand (dest
, GET_MODE (dest
)))
12765 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12768 /* Update the records of when each REG was most recently set or killed
12769 for the things done by INSN. This is the last thing done in processing
12770 INSN in the combiner loop.
12772 We update reg_stat[], in particular fields last_set, last_set_value,
12773 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12774 last_death, and also the similar information mem_last_set (which insn
12775 most recently modified memory) and last_call_luid (which insn was the
12776 most recent subroutine call). */
12779 record_dead_and_set_regs (rtx_insn
*insn
)
12784 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12786 if (REG_NOTE_KIND (link
) == REG_DEAD
12787 && REG_P (XEXP (link
, 0)))
12789 unsigned int regno
= REGNO (XEXP (link
, 0));
12790 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12792 for (i
= regno
; i
< endregno
; i
++)
12794 reg_stat_type
*rsp
;
12796 rsp
= ®_stat
[i
];
12797 rsp
->last_death
= insn
;
12800 else if (REG_NOTE_KIND (link
) == REG_INC
)
12801 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12806 hard_reg_set_iterator hrsi
;
12807 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12809 reg_stat_type
*rsp
;
12811 rsp
= ®_stat
[i
];
12812 rsp
->last_set_invalid
= 1;
12813 rsp
->last_set
= insn
;
12814 rsp
->last_set_value
= 0;
12815 rsp
->last_set_mode
= VOIDmode
;
12816 rsp
->last_set_nonzero_bits
= 0;
12817 rsp
->last_set_sign_bit_copies
= 0;
12818 rsp
->last_death
= 0;
12819 rsp
->truncated_to_mode
= VOIDmode
;
12822 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12824 /* We can't combine into a call pattern. Remember, though, that
12825 the return value register is set at this LUID. We could
12826 still replace a register with the return value from the
12827 wrong subroutine call! */
12828 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12831 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12834 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12835 register present in the SUBREG, so for each such SUBREG go back and
12836 adjust nonzero and sign bit information of the registers that are
12837 known to have some zero/sign bits set.
12839 This is needed because when combine blows the SUBREGs away, the
12840 information on zero/sign bits is lost and further combines can be
12841 missed because of that. */
12844 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12846 struct insn_link
*links
;
12848 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12849 machine_mode mode
= GET_MODE (subreg
);
12851 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12854 for (links
= LOG_LINKS (insn
); links
;)
12856 reg_stat_type
*rsp
;
12858 insn
= links
->insn
;
12859 set
= single_set (insn
);
12861 if (! set
|| !REG_P (SET_DEST (set
))
12862 || REGNO (SET_DEST (set
)) != regno
12863 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12865 links
= links
->next
;
12869 rsp
= ®_stat
[regno
];
12870 if (rsp
->last_set
== insn
)
12872 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12873 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12876 if (REG_P (SET_SRC (set
)))
12878 regno
= REGNO (SET_SRC (set
));
12879 links
= LOG_LINKS (insn
);
12886 /* Check if X, a register, is known to contain a value already
12887 truncated to MODE. In this case we can use a subreg to refer to
12888 the truncated value even though in the generic case we would need
12889 an explicit truncation. */
12892 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12894 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12895 machine_mode truncated
= rsp
->truncated_to_mode
;
12898 || rsp
->truncation_label
< label_tick_ebb_start
)
12900 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12902 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12907 /* If X is a hard reg or a subreg record the mode that the register is
12908 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12909 to turn a truncate into a subreg using this information. Return true
12910 if traversing X is complete. */
12913 record_truncated_value (rtx x
)
12915 machine_mode truncated_mode
;
12916 reg_stat_type
*rsp
;
12918 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12920 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12921 truncated_mode
= GET_MODE (x
);
12923 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12926 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12929 x
= SUBREG_REG (x
);
12931 /* ??? For hard-regs we now record everything. We might be able to
12932 optimize this using last_set_mode. */
12933 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12934 truncated_mode
= GET_MODE (x
);
12938 rsp
= ®_stat
[REGNO (x
)];
12939 if (rsp
->truncated_to_mode
== 0
12940 || rsp
->truncation_label
< label_tick_ebb_start
12941 || (GET_MODE_SIZE (truncated_mode
)
12942 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12944 rsp
->truncated_to_mode
= truncated_mode
;
12945 rsp
->truncation_label
= label_tick
;
12951 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12952 the modes they are used in. This can help truning TRUNCATEs into
12956 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12958 subrtx_var_iterator::array_type array
;
12959 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12960 if (record_truncated_value (*iter
))
12961 iter
.skip_subrtxes ();
12964 /* Scan X for promoted SUBREGs. For each one found,
12965 note what it implies to the registers used in it. */
12968 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12970 if (GET_CODE (x
) == SUBREG
12971 && SUBREG_PROMOTED_VAR_P (x
)
12972 && REG_P (SUBREG_REG (x
)))
12973 record_promoted_value (insn
, x
);
12976 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12979 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12983 check_promoted_subreg (insn
, XEXP (x
, i
));
12987 if (XVEC (x
, i
) != 0)
12988 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12989 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12995 /* Verify that all the registers and memory references mentioned in *LOC are
12996 still valid. *LOC was part of a value set in INSN when label_tick was
12997 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12998 the invalid references with (clobber (const_int 0)) and return 1. This
12999 replacement is useful because we often can get useful information about
13000 the form of a value (e.g., if it was produced by a shift that always
13001 produces -1 or 0) even though we don't know exactly what registers it
13002 was produced from. */
13005 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13008 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13009 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13014 unsigned int regno
= REGNO (x
);
13015 unsigned int endregno
= END_REGNO (x
);
13018 for (j
= regno
; j
< endregno
; j
++)
13020 reg_stat_type
*rsp
= ®_stat
[j
];
13021 if (rsp
->last_set_invalid
13022 /* If this is a pseudo-register that was only set once and not
13023 live at the beginning of the function, it is always valid. */
13024 || (! (regno
>= FIRST_PSEUDO_REGISTER
13025 && regno
< reg_n_sets_max
13026 && REG_N_SETS (regno
) == 1
13027 && (!REGNO_REG_SET_P
13028 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13030 && rsp
->last_set_label
> tick
))
13033 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13040 /* If this is a memory reference, make sure that there were no stores after
13041 it that might have clobbered the value. We don't have alias info, so we
13042 assume any store invalidates it. Moreover, we only have local UIDs, so
13043 we also assume that there were stores in the intervening basic blocks. */
13044 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13045 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13048 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13052 for (i
= 0; i
< len
; i
++)
13056 /* Check for identical subexpressions. If x contains
13057 identical subexpression we only have to traverse one of
13059 if (i
== 1 && ARITHMETIC_P (x
))
13061 /* Note that at this point x0 has already been checked
13062 and found valid. */
13063 rtx x0
= XEXP (x
, 0);
13064 rtx x1
= XEXP (x
, 1);
13066 /* If x0 and x1 are identical then x is also valid. */
13070 /* If x1 is identical to a subexpression of x0 then
13071 while checking x0, x1 has already been checked. Thus
13072 it is valid and so as x. */
13073 if (ARITHMETIC_P (x0
)
13074 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13077 /* If x0 is identical to a subexpression of x1 then x is
13078 valid iff the rest of x1 is valid. */
13079 if (ARITHMETIC_P (x1
)
13080 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13082 get_last_value_validate (&XEXP (x1
,
13083 x0
== XEXP (x1
, 0) ? 1 : 0),
13084 insn
, tick
, replace
);
13087 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13091 else if (fmt
[i
] == 'E')
13092 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13093 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13094 insn
, tick
, replace
) == 0)
13098 /* If we haven't found a reason for it to be invalid, it is valid. */
13102 /* Get the last value assigned to X, if known. Some registers
13103 in the value may be replaced with (clobber (const_int 0)) if their value
13104 is known longer known reliably. */
13107 get_last_value (const_rtx x
)
13109 unsigned int regno
;
13111 reg_stat_type
*rsp
;
13113 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13114 then convert it to the desired mode. If this is a paradoxical SUBREG,
13115 we cannot predict what values the "extra" bits might have. */
13116 if (GET_CODE (x
) == SUBREG
13117 && subreg_lowpart_p (x
)
13118 && !paradoxical_subreg_p (x
)
13119 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13120 return gen_lowpart (GET_MODE (x
), value
);
13126 rsp
= ®_stat
[regno
];
13127 value
= rsp
->last_set_value
;
13129 /* If we don't have a value, or if it isn't for this basic block and
13130 it's either a hard register, set more than once, or it's a live
13131 at the beginning of the function, return 0.
13133 Because if it's not live at the beginning of the function then the reg
13134 is always set before being used (is never used without being set).
13135 And, if it's set only once, and it's always set before use, then all
13136 uses must have the same last value, even if it's not from this basic
13140 || (rsp
->last_set_label
< label_tick_ebb_start
13141 && (regno
< FIRST_PSEUDO_REGISTER
13142 || regno
>= reg_n_sets_max
13143 || REG_N_SETS (regno
) != 1
13145 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13148 /* If the value was set in a later insn than the ones we are processing,
13149 we can't use it even if the register was only set once. */
13150 if (rsp
->last_set_label
== label_tick
13151 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13154 /* If the value has all its registers valid, return it. */
13155 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13158 /* Otherwise, make a copy and replace any invalid register with
13159 (clobber (const_int 0)). If that fails for some reason, return 0. */
13161 value
= copy_rtx (value
);
13162 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13168 /* Return nonzero if expression X refers to a REG or to memory
13169 that is set in an instruction more recent than FROM_LUID. */
13172 use_crosses_set_p (const_rtx x
, int from_luid
)
13176 enum rtx_code code
= GET_CODE (x
);
13180 unsigned int regno
= REGNO (x
);
13181 unsigned endreg
= END_REGNO (x
);
13183 #ifdef PUSH_ROUNDING
13184 /* Don't allow uses of the stack pointer to be moved,
13185 because we don't know whether the move crosses a push insn. */
13186 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13189 for (; regno
< endreg
; regno
++)
13191 reg_stat_type
*rsp
= ®_stat
[regno
];
13193 && rsp
->last_set_label
== label_tick
13194 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13200 if (code
== MEM
&& mem_last_set
> from_luid
)
13203 fmt
= GET_RTX_FORMAT (code
);
13205 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13210 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13211 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13214 else if (fmt
[i
] == 'e'
13215 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13221 /* Define three variables used for communication between the following
13224 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13225 static int reg_dead_flag
;
13227 /* Function called via note_stores from reg_dead_at_p.
13229 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13230 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13233 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13235 unsigned int regno
, endregno
;
13240 regno
= REGNO (dest
);
13241 endregno
= END_REGNO (dest
);
13242 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13243 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13246 /* Return nonzero if REG is known to be dead at INSN.
13248 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13249 referencing REG, it is dead. If we hit a SET referencing REG, it is
13250 live. Otherwise, see if it is live or dead at the start of the basic
13251 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13252 must be assumed to be always live. */
13255 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13260 /* Set variables for reg_dead_at_p_1. */
13261 reg_dead_regno
= REGNO (reg
);
13262 reg_dead_endregno
= END_REGNO (reg
);
13266 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13267 we allow the machine description to decide whether use-and-clobber
13268 patterns are OK. */
13269 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13271 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13272 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13276 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13277 beginning of basic block. */
13278 block
= BLOCK_FOR_INSN (insn
);
13283 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13286 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13288 return reg_dead_flag
== 1 ? 1 : 0;
13290 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13294 if (insn
== BB_HEAD (block
))
13297 insn
= PREV_INSN (insn
);
13300 /* Look at live-in sets for the basic block that we were in. */
13301 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13302 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13308 /* Note hard registers in X that are used. */
13311 mark_used_regs_combine (rtx x
)
13313 RTX_CODE code
= GET_CODE (x
);
13314 unsigned int regno
;
13325 case ADDR_DIFF_VEC
:
13327 /* CC0 must die in the insn after it is set, so we don't need to take
13328 special note of it here. */
13333 /* If we are clobbering a MEM, mark any hard registers inside the
13334 address as used. */
13335 if (MEM_P (XEXP (x
, 0)))
13336 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13341 /* A hard reg in a wide mode may really be multiple registers.
13342 If so, mark all of them just like the first. */
13343 if (regno
< FIRST_PSEUDO_REGISTER
)
13345 /* None of this applies to the stack, frame or arg pointers. */
13346 if (regno
== STACK_POINTER_REGNUM
13347 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13348 || regno
== HARD_FRAME_POINTER_REGNUM
13350 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13351 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13352 || regno
== FRAME_POINTER_REGNUM
)
13355 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13361 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13363 rtx testreg
= SET_DEST (x
);
13365 while (GET_CODE (testreg
) == SUBREG
13366 || GET_CODE (testreg
) == ZERO_EXTRACT
13367 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13368 testreg
= XEXP (testreg
, 0);
13370 if (MEM_P (testreg
))
13371 mark_used_regs_combine (XEXP (testreg
, 0));
13373 mark_used_regs_combine (SET_SRC (x
));
13381 /* Recursively scan the operands of this expression. */
13384 const char *fmt
= GET_RTX_FORMAT (code
);
13386 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13389 mark_used_regs_combine (XEXP (x
, i
));
13390 else if (fmt
[i
] == 'E')
13394 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13395 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13401 /* Remove register number REGNO from the dead registers list of INSN.
13403 Return the note used to record the death, if there was one. */
13406 remove_death (unsigned int regno
, rtx_insn
*insn
)
13408 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13411 remove_note (insn
, note
);
13416 /* For each register (hardware or pseudo) used within expression X, if its
13417 death is in an instruction with luid between FROM_LUID (inclusive) and
13418 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13419 list headed by PNOTES.
13421 That said, don't move registers killed by maybe_kill_insn.
13423 This is done when X is being merged by combination into TO_INSN. These
13424 notes will then be distributed as needed. */
13427 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13432 enum rtx_code code
= GET_CODE (x
);
13436 unsigned int regno
= REGNO (x
);
13437 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13439 /* Don't move the register if it gets killed in between from and to. */
13440 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13441 && ! reg_referenced_p (x
, maybe_kill_insn
))
13445 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13446 && DF_INSN_LUID (where_dead
) >= from_luid
13447 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13449 rtx note
= remove_death (regno
, where_dead
);
13451 /* It is possible for the call above to return 0. This can occur
13452 when last_death points to I2 or I1 that we combined with.
13453 In that case make a new note.
13455 We must also check for the case where X is a hard register
13456 and NOTE is a death note for a range of hard registers
13457 including X. In that case, we must put REG_DEAD notes for
13458 the remaining registers in place of NOTE. */
13460 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13461 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13462 > GET_MODE_SIZE (GET_MODE (x
))))
13464 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13465 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13466 unsigned int ourend
= END_REGNO (x
);
13469 for (i
= deadregno
; i
< deadend
; i
++)
13470 if (i
< regno
|| i
>= ourend
)
13471 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13474 /* If we didn't find any note, or if we found a REG_DEAD note that
13475 covers only part of the given reg, and we have a multi-reg hard
13476 register, then to be safe we must check for REG_DEAD notes
13477 for each register other than the first. They could have
13478 their own REG_DEAD notes lying around. */
13479 else if ((note
== 0
13481 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13482 < GET_MODE_SIZE (GET_MODE (x
)))))
13483 && regno
< FIRST_PSEUDO_REGISTER
13484 && REG_NREGS (x
) > 1)
13486 unsigned int ourend
= END_REGNO (x
);
13487 unsigned int i
, offset
;
13491 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13495 for (i
= regno
+ offset
; i
< ourend
; i
++)
13496 move_deaths (regno_reg_rtx
[i
],
13497 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13500 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13502 XEXP (note
, 1) = *pnotes
;
13506 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13512 else if (GET_CODE (x
) == SET
)
13514 rtx dest
= SET_DEST (x
);
13516 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13518 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13519 that accesses one word of a multi-word item, some
13520 piece of everything register in the expression is used by
13521 this insn, so remove any old death. */
13522 /* ??? So why do we test for equality of the sizes? */
13524 if (GET_CODE (dest
) == ZERO_EXTRACT
13525 || GET_CODE (dest
) == STRICT_LOW_PART
13526 || (GET_CODE (dest
) == SUBREG
13527 && (((GET_MODE_SIZE (GET_MODE (dest
))
13528 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13529 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13530 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13532 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13536 /* If this is some other SUBREG, we know it replaces the entire
13537 value, so use that as the destination. */
13538 if (GET_CODE (dest
) == SUBREG
)
13539 dest
= SUBREG_REG (dest
);
13541 /* If this is a MEM, adjust deaths of anything used in the address.
13542 For a REG (the only other possibility), the entire value is
13543 being replaced so the old value is not used in this insn. */
13546 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13551 else if (GET_CODE (x
) == CLOBBER
)
13554 len
= GET_RTX_LENGTH (code
);
13555 fmt
= GET_RTX_FORMAT (code
);
13557 for (i
= 0; i
< len
; i
++)
13562 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13563 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13566 else if (fmt
[i
] == 'e')
13567 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13571 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13572 pattern of an insn. X must be a REG. */
13575 reg_bitfield_target_p (rtx x
, rtx body
)
13579 if (GET_CODE (body
) == SET
)
13581 rtx dest
= SET_DEST (body
);
13583 unsigned int regno
, tregno
, endregno
, endtregno
;
13585 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13586 target
= XEXP (dest
, 0);
13587 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13588 target
= SUBREG_REG (XEXP (dest
, 0));
13592 if (GET_CODE (target
) == SUBREG
)
13593 target
= SUBREG_REG (target
);
13595 if (!REG_P (target
))
13598 tregno
= REGNO (target
), regno
= REGNO (x
);
13599 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13600 return target
== x
;
13602 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13603 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13605 return endregno
> tregno
&& regno
< endtregno
;
13608 else if (GET_CODE (body
) == PARALLEL
)
13609 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13610 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13616 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13617 as appropriate. I3 and I2 are the insns resulting from the combination
13618 insns including FROM (I2 may be zero).
13620 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13621 not need REG_DEAD notes because they are being substituted for. This
13622 saves searching in the most common cases.
13624 Each note in the list is either ignored or placed on some insns, depending
13625 on the type of note. */
13628 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13629 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13631 rtx note
, next_note
;
13633 rtx_insn
*tem_insn
;
13635 for (note
= notes
; note
; note
= next_note
)
13637 rtx_insn
*place
= 0, *place2
= 0;
13639 next_note
= XEXP (note
, 1);
13640 switch (REG_NOTE_KIND (note
))
13644 /* Doesn't matter much where we put this, as long as it's somewhere.
13645 It is preferable to keep these notes on branches, which is most
13646 likely to be i3. */
13650 case REG_NON_LOCAL_GOTO
:
13655 gcc_assert (i2
&& JUMP_P (i2
));
13660 case REG_EH_REGION
:
13661 /* These notes must remain with the call or trapping instruction. */
13664 else if (i2
&& CALL_P (i2
))
13668 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13669 if (may_trap_p (i3
))
13671 else if (i2
&& may_trap_p (i2
))
13673 /* ??? Otherwise assume we've combined things such that we
13674 can now prove that the instructions can't trap. Drop the
13675 note in this case. */
13679 case REG_ARGS_SIZE
:
13680 /* ??? How to distribute between i3-i1. Assume i3 contains the
13681 entire adjustment. Assert i3 contains at least some adjust. */
13682 if (!noop_move_p (i3
))
13684 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13685 /* fixup_args_size_notes looks at REG_NORETURN note,
13686 so ensure the note is placed there first. */
13690 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13691 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13695 XEXP (n
, 1) = REG_NOTES (i3
);
13696 REG_NOTES (i3
) = n
;
13700 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13701 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13702 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13703 gcc_assert (old_size
!= args_size
13705 && !ACCUMULATE_OUTGOING_ARGS
13706 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13713 case REG_CALL_DECL
:
13714 /* These notes must remain with the call. It should not be
13715 possible for both I2 and I3 to be a call. */
13720 gcc_assert (i2
&& CALL_P (i2
));
13726 /* Any clobbers for i3 may still exist, and so we must process
13727 REG_UNUSED notes from that insn.
13729 Any clobbers from i2 or i1 can only exist if they were added by
13730 recog_for_combine. In that case, recog_for_combine created the
13731 necessary REG_UNUSED notes. Trying to keep any original
13732 REG_UNUSED notes from these insns can cause incorrect output
13733 if it is for the same register as the original i3 dest.
13734 In that case, we will notice that the register is set in i3,
13735 and then add a REG_UNUSED note for the destination of i3, which
13736 is wrong. However, it is possible to have REG_UNUSED notes from
13737 i2 or i1 for register which were both used and clobbered, so
13738 we keep notes from i2 or i1 if they will turn into REG_DEAD
13741 /* If this register is set or clobbered in I3, put the note there
13742 unless there is one already. */
13743 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13745 if (from_insn
!= i3
)
13748 if (! (REG_P (XEXP (note
, 0))
13749 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13750 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13753 /* Otherwise, if this register is used by I3, then this register
13754 now dies here, so we must put a REG_DEAD note here unless there
13756 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13757 && ! (REG_P (XEXP (note
, 0))
13758 ? find_regno_note (i3
, REG_DEAD
,
13759 REGNO (XEXP (note
, 0)))
13760 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13762 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13770 /* These notes say something about results of an insn. We can
13771 only support them if they used to be on I3 in which case they
13772 remain on I3. Otherwise they are ignored.
13774 If the note refers to an expression that is not a constant, we
13775 must also ignore the note since we cannot tell whether the
13776 equivalence is still true. It might be possible to do
13777 slightly better than this (we only have a problem if I2DEST
13778 or I1DEST is present in the expression), but it doesn't
13779 seem worth the trouble. */
13781 if (from_insn
== i3
13782 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13787 /* These notes say something about how a register is used. They must
13788 be present on any use of the register in I2 or I3. */
13789 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13792 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13801 case REG_LABEL_TARGET
:
13802 case REG_LABEL_OPERAND
:
13803 /* This can show up in several ways -- either directly in the
13804 pattern, or hidden off in the constant pool with (or without?)
13805 a REG_EQUAL note. */
13806 /* ??? Ignore the without-reg_equal-note problem for now. */
13807 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13808 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13809 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13810 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13814 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13815 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13816 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13817 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13825 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13826 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13828 if (place
&& JUMP_P (place
)
13829 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13830 && (JUMP_LABEL (place
) == NULL
13831 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13833 rtx label
= JUMP_LABEL (place
);
13836 JUMP_LABEL (place
) = XEXP (note
, 0);
13837 else if (LABEL_P (label
))
13838 LABEL_NUSES (label
)--;
13841 if (place2
&& JUMP_P (place2
)
13842 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13843 && (JUMP_LABEL (place2
) == NULL
13844 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13846 rtx label
= JUMP_LABEL (place2
);
13849 JUMP_LABEL (place2
) = XEXP (note
, 0);
13850 else if (LABEL_P (label
))
13851 LABEL_NUSES (label
)--;
13857 /* This note says something about the value of a register prior
13858 to the execution of an insn. It is too much trouble to see
13859 if the note is still correct in all situations. It is better
13860 to simply delete it. */
13864 /* If we replaced the right hand side of FROM_INSN with a
13865 REG_EQUAL note, the original use of the dying register
13866 will not have been combined into I3 and I2. In such cases,
13867 FROM_INSN is guaranteed to be the first of the combined
13868 instructions, so we simply need to search back before
13869 FROM_INSN for the previous use or set of this register,
13870 then alter the notes there appropriately.
13872 If the register is used as an input in I3, it dies there.
13873 Similarly for I2, if it is nonzero and adjacent to I3.
13875 If the register is not used as an input in either I3 or I2
13876 and it is not one of the registers we were supposed to eliminate,
13877 there are two possibilities. We might have a non-adjacent I2
13878 or we might have somehow eliminated an additional register
13879 from a computation. For example, we might have had A & B where
13880 we discover that B will always be zero. In this case we will
13881 eliminate the reference to A.
13883 In both cases, we must search to see if we can find a previous
13884 use of A and put the death note there. */
13887 && from_insn
== i2mod
13888 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13889 tem_insn
= from_insn
;
13893 && CALL_P (from_insn
)
13894 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13896 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13898 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13899 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13901 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13903 && reg_overlap_mentioned_p (XEXP (note
, 0),
13905 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13906 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13909 /* If the new I2 sets the same register that is marked dead
13910 in the note, the note now should not be put on I2, as the
13911 note refers to a previous incarnation of the reg. */
13912 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
13918 basic_block bb
= this_basic_block
;
13920 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13922 if (!NONDEBUG_INSN_P (tem_insn
))
13924 if (tem_insn
== BB_HEAD (bb
))
13929 /* If the register is being set at TEM_INSN, see if that is all
13930 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13931 into a REG_UNUSED note instead. Don't delete sets to
13932 global register vars. */
13933 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13934 || !global_regs
[REGNO (XEXP (note
, 0))])
13935 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13937 rtx set
= single_set (tem_insn
);
13938 rtx inner_dest
= 0;
13939 rtx_insn
*cc0_setter
= NULL
;
13942 for (inner_dest
= SET_DEST (set
);
13943 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13944 || GET_CODE (inner_dest
) == SUBREG
13945 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13946 inner_dest
= XEXP (inner_dest
, 0))
13949 /* Verify that it was the set, and not a clobber that
13950 modified the register.
13952 CC0 targets must be careful to maintain setter/user
13953 pairs. If we cannot delete the setter due to side
13954 effects, mark the user with an UNUSED note instead
13957 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13958 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13960 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13961 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13962 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13966 /* Move the notes and links of TEM_INSN elsewhere.
13967 This might delete other dead insns recursively.
13968 First set the pattern to something that won't use
13970 rtx old_notes
= REG_NOTES (tem_insn
);
13972 PATTERN (tem_insn
) = pc_rtx
;
13973 REG_NOTES (tem_insn
) = NULL
;
13975 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13976 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13977 distribute_links (LOG_LINKS (tem_insn
));
13979 SET_INSN_DELETED (tem_insn
);
13980 if (tem_insn
== i2
)
13983 /* Delete the setter too. */
13986 PATTERN (cc0_setter
) = pc_rtx
;
13987 old_notes
= REG_NOTES (cc0_setter
);
13988 REG_NOTES (cc0_setter
) = NULL
;
13990 distribute_notes (old_notes
, cc0_setter
,
13992 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13993 distribute_links (LOG_LINKS (cc0_setter
));
13995 SET_INSN_DELETED (cc0_setter
);
13996 if (cc0_setter
== i2
)
14002 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14004 /* If there isn't already a REG_UNUSED note, put one
14005 here. Do not place a REG_DEAD note, even if
14006 the register is also used here; that would not
14007 match the algorithm used in lifetime analysis
14008 and can cause the consistency check in the
14009 scheduler to fail. */
14010 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14011 REGNO (XEXP (note
, 0))))
14016 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14017 || (CALL_P (tem_insn
)
14018 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14022 /* If we are doing a 3->2 combination, and we have a
14023 register which formerly died in i3 and was not used
14024 by i2, which now no longer dies in i3 and is used in
14025 i2 but does not die in i2, and place is between i2
14026 and i3, then we may need to move a link from place to
14028 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14030 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14031 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14033 struct insn_link
*links
= LOG_LINKS (place
);
14034 LOG_LINKS (place
) = NULL
;
14035 distribute_links (links
);
14040 if (tem_insn
== BB_HEAD (bb
))
14046 /* If the register is set or already dead at PLACE, we needn't do
14047 anything with this note if it is still a REG_DEAD note.
14048 We check here if it is set at all, not if is it totally replaced,
14049 which is what `dead_or_set_p' checks, so also check for it being
14052 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14054 unsigned int regno
= REGNO (XEXP (note
, 0));
14055 reg_stat_type
*rsp
= ®_stat
[regno
];
14057 if (dead_or_set_p (place
, XEXP (note
, 0))
14058 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14060 /* Unless the register previously died in PLACE, clear
14061 last_death. [I no longer understand why this is
14063 if (rsp
->last_death
!= place
)
14064 rsp
->last_death
= 0;
14068 rsp
->last_death
= place
;
14070 /* If this is a death note for a hard reg that is occupying
14071 multiple registers, ensure that we are still using all
14072 parts of the object. If we find a piece of the object
14073 that is unused, we must arrange for an appropriate REG_DEAD
14074 note to be added for it. However, we can't just emit a USE
14075 and tag the note to it, since the register might actually
14076 be dead; so we recourse, and the recursive call then finds
14077 the previous insn that used this register. */
14079 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14081 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14082 bool all_used
= true;
14085 for (i
= regno
; i
< endregno
; i
++)
14086 if ((! refers_to_regno_p (i
, PATTERN (place
))
14087 && ! find_regno_fusage (place
, USE
, i
))
14088 || dead_or_set_regno_p (place
, i
))
14096 /* Put only REG_DEAD notes for pieces that are
14097 not already dead or set. */
14099 for (i
= regno
; i
< endregno
;
14100 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14102 rtx piece
= regno_reg_rtx
[i
];
14103 basic_block bb
= this_basic_block
;
14105 if (! dead_or_set_p (place
, piece
)
14106 && ! reg_bitfield_target_p (piece
,
14109 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14112 distribute_notes (new_note
, place
, place
,
14113 NULL
, NULL_RTX
, NULL_RTX
,
14116 else if (! refers_to_regno_p (i
, PATTERN (place
))
14117 && ! find_regno_fusage (place
, USE
, i
))
14118 for (tem_insn
= PREV_INSN (place
); ;
14119 tem_insn
= PREV_INSN (tem_insn
))
14121 if (!NONDEBUG_INSN_P (tem_insn
))
14123 if (tem_insn
== BB_HEAD (bb
))
14127 if (dead_or_set_p (tem_insn
, piece
)
14128 || reg_bitfield_target_p (piece
,
14129 PATTERN (tem_insn
)))
14131 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14144 /* Any other notes should not be present at this point in the
14146 gcc_unreachable ();
14151 XEXP (note
, 1) = REG_NOTES (place
);
14152 REG_NOTES (place
) = note
;
14156 add_shallow_copy_of_reg_note (place2
, note
);
14160 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14161 I3, I2, and I1 to new locations. This is also called to add a link
14162 pointing at I3 when I3's destination is changed. */
14165 distribute_links (struct insn_link
*links
)
14167 struct insn_link
*link
, *next_link
;
14169 for (link
= links
; link
; link
= next_link
)
14171 rtx_insn
*place
= 0;
14175 next_link
= link
->next
;
14177 /* If the insn that this link points to is a NOTE, ignore it. */
14178 if (NOTE_P (link
->insn
))
14182 rtx pat
= PATTERN (link
->insn
);
14183 if (GET_CODE (pat
) == SET
)
14185 else if (GET_CODE (pat
) == PARALLEL
)
14188 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14190 set
= XVECEXP (pat
, 0, i
);
14191 if (GET_CODE (set
) != SET
)
14194 reg
= SET_DEST (set
);
14195 while (GET_CODE (reg
) == ZERO_EXTRACT
14196 || GET_CODE (reg
) == STRICT_LOW_PART
14197 || GET_CODE (reg
) == SUBREG
)
14198 reg
= XEXP (reg
, 0);
14203 if (REGNO (reg
) == link
->regno
)
14206 if (i
== XVECLEN (pat
, 0))
14212 reg
= SET_DEST (set
);
14214 while (GET_CODE (reg
) == ZERO_EXTRACT
14215 || GET_CODE (reg
) == STRICT_LOW_PART
14216 || GET_CODE (reg
) == SUBREG
)
14217 reg
= XEXP (reg
, 0);
14219 /* A LOG_LINK is defined as being placed on the first insn that uses
14220 a register and points to the insn that sets the register. Start
14221 searching at the next insn after the target of the link and stop
14222 when we reach a set of the register or the end of the basic block.
14224 Note that this correctly handles the link that used to point from
14225 I3 to I2. Also note that not much searching is typically done here
14226 since most links don't point very far away. */
14228 for (insn
= NEXT_INSN (link
->insn
);
14229 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14230 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14231 insn
= NEXT_INSN (insn
))
14232 if (DEBUG_INSN_P (insn
))
14234 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14236 if (reg_referenced_p (reg
, PATTERN (insn
)))
14240 else if (CALL_P (insn
)
14241 && find_reg_fusage (insn
, USE
, reg
))
14246 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14249 /* If we found a place to put the link, place it there unless there
14250 is already a link to the same insn as LINK at that point. */
14254 struct insn_link
*link2
;
14256 FOR_EACH_LOG_LINK (link2
, place
)
14257 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14262 link
->next
= LOG_LINKS (place
);
14263 LOG_LINKS (place
) = link
;
14265 /* Set added_links_insn to the earliest insn we added a
14267 if (added_links_insn
== 0
14268 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14269 added_links_insn
= place
;
14275 /* Check for any register or memory mentioned in EQUIV that is not
14276 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14277 of EXPR where some registers may have been replaced by constants. */
14280 unmentioned_reg_p (rtx equiv
, rtx expr
)
14282 subrtx_iterator::array_type array
;
14283 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14285 const_rtx x
= *iter
;
14286 if ((REG_P (x
) || MEM_P (x
))
14287 && !reg_mentioned_p (x
, expr
))
14293 DEBUG_FUNCTION
void
14294 dump_combine_stats (FILE *file
)
14298 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14299 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14303 dump_combine_total_stats (FILE *file
)
14307 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14308 total_attempts
, total_merges
, total_extras
, total_successes
);
14311 /* Try combining insns through substitution. */
14312 static unsigned int
14313 rest_of_handle_combine (void)
14315 int rebuild_jump_labels_after_combine
;
14317 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14318 df_note_add_problem ();
14321 regstat_init_n_sets_and_refs ();
14322 reg_n_sets_max
= max_reg_num ();
14324 rebuild_jump_labels_after_combine
14325 = combine_instructions (get_insns (), max_reg_num ());
14327 /* Combining insns may have turned an indirect jump into a
14328 direct jump. Rebuild the JUMP_LABEL fields of jumping
14330 if (rebuild_jump_labels_after_combine
)
14332 timevar_push (TV_JUMP
);
14333 rebuild_jump_labels (get_insns ());
14335 timevar_pop (TV_JUMP
);
14338 regstat_free_n_sets_and_refs ();
14344 const pass_data pass_data_combine
=
14346 RTL_PASS
, /* type */
14347 "combine", /* name */
14348 OPTGROUP_NONE
, /* optinfo_flags */
14349 TV_COMBINE
, /* tv_id */
14350 PROP_cfglayout
, /* properties_required */
14351 0, /* properties_provided */
14352 0, /* properties_destroyed */
14353 0, /* todo_flags_start */
14354 TODO_df_finish
, /* todo_flags_finish */
14357 class pass_combine
: public rtl_opt_pass
14360 pass_combine (gcc::context
*ctxt
)
14361 : rtl_opt_pass (pass_data_combine
, ctxt
)
14364 /* opt_pass methods: */
14365 virtual bool gate (function
*) { return (optimize
> 0); }
14366 virtual unsigned int execute (function
*)
14368 return rest_of_handle_combine ();
14371 }; // class pass_combine
14373 } // anon namespace
14376 make_pass_combine (gcc::context
*ctxt
)
14378 return new pass_combine (ctxt
);