1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
35 #include "rtl-error.h"
37 #include "addresses.h"
45 /* This file contains the reload pass of the compiler, which is
46 run after register allocation has been done. It checks that
47 each insn is valid (operands required to be in registers really
48 are in registers of the proper class) and fixes up invalid ones
49 by copying values temporarily into registers for the insns
52 The results of register allocation are described by the vector
53 reg_renumber; the insns still contain pseudo regs, but reg_renumber
54 can be used to find which hard reg, if any, a pseudo reg is in.
56 The technique we always use is to free up a few hard regs that are
57 called ``reload regs'', and for each place where a pseudo reg
58 must be in a hard reg, copy it temporarily into one of the reload regs.
60 Reload regs are allocated locally for every instruction that needs
61 reloads. When there are pseudos which are allocated to a register that
62 has been chosen as a reload reg, such pseudos must be ``spilled''.
63 This means that they go to other hard regs, or to stack slots if no other
64 available hard regs can be found. Spilling can invalidate more
65 insns, requiring additional need for reloads, so we must keep checking
66 until the process stabilizes.
68 For machines with different classes of registers, we must keep track
69 of the register class needed for each reload, and make sure that
70 we allocate enough reload registers of each class.
72 The file reload.c contains the code that checks one insn for
73 validity and reports the reloads that it needs. This file
74 is in charge of scanning the entire rtl code, accumulating the
75 reload needs, spilling, assigning reload registers to use for
76 fixing up each insn, and generating the new insns to copy values
77 into the reload registers. */
79 struct target_reload default_target_reload
;
81 struct target_reload
*this_target_reload
= &default_target_reload
;
84 #define spill_indirect_levels \
85 (this_target_reload->x_spill_indirect_levels)
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx
*reg_last_reload_reg
;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static regset_head reg_has_output_reload
;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload
;
99 /* Widest width in which each pseudo reg is referred to (via subreg). */
100 static unsigned int *reg_max_ref_width
;
102 /* Vector to remember old contents of reg_renumber before spilling. */
103 static short *reg_old_renumber
;
105 /* During reload_as_needed, element N contains the last pseudo regno reloaded
106 into hard register N. If that pseudo reg occupied more than one register,
107 reg_reloaded_contents points to that pseudo for each spill register in
108 use; all of these must remain set for an inheritance to occur. */
109 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
111 /* During reload_as_needed, element N contains the insn for which
112 hard register N was last used. Its contents are significant only
113 when reg_reloaded_valid is set for this register. */
114 static rtx_insn
*reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
116 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
117 static HARD_REG_SET reg_reloaded_valid
;
118 /* Indicate if the register was dead at the end of the reload.
119 This is only valid if reg_reloaded_contents is set and valid. */
120 static HARD_REG_SET reg_reloaded_dead
;
122 /* Indicate whether the register's current value is one that is not
123 safe to retain across a call, even for registers that are normally
124 call-saved. This is only meaningful for members of reg_reloaded_valid. */
125 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
127 /* Number of spill-regs so far; number of valid elements of spill_regs. */
130 /* In parallel with spill_regs, contains REG rtx's for those regs.
131 Holds the last rtx used for any given reg, or 0 if it has never
132 been used for spilling yet. This rtx is reused, provided it has
134 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
136 /* In parallel with spill_regs, contains nonzero for a spill reg
137 that was stored after the last time it was used.
138 The precise value is the insn generated to do the store. */
139 static rtx_insn
*spill_reg_store
[FIRST_PSEUDO_REGISTER
];
141 /* This is the register that was stored with spill_reg_store. This is a
142 copy of reload_out / reload_out_reg when the value was stored; if
143 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
144 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
146 /* This table is the inverse mapping of spill_regs:
147 indexed by hard reg number,
148 it contains the position of that reg in spill_regs,
149 or -1 for something that is not in spill_regs.
151 ?!? This is no longer accurate. */
152 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
154 /* This reg set indicates registers that can't be used as spill registers for
155 the currently processed insn. These are the hard registers which are live
156 during the insn, but not allocated to pseudos, as well as fixed
158 static HARD_REG_SET bad_spill_regs
;
160 /* These are the hard registers that can't be used as spill register for any
161 insn. This includes registers used for user variables and registers that
162 we can't eliminate. A register that appears in this set also can't be used
163 to retry register allocation. */
164 static HARD_REG_SET bad_spill_regs_global
;
166 /* Describes order of use of registers for reloading
167 of spilled pseudo-registers. `n_spills' is the number of
168 elements that are actually valid; new ones are added at the end.
170 Both spill_regs and spill_reg_order are used on two occasions:
171 once during find_reload_regs, where they keep track of the spill registers
172 for a single insn, but also during reload_as_needed where they show all
173 the registers ever used by reload. For the latter case, the information
174 is calculated during finish_spills. */
175 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
177 /* This vector of reg sets indicates, for each pseudo, which hard registers
178 may not be used for retrying global allocation because the register was
179 formerly spilled from one of them. If we allowed reallocating a pseudo to
180 a register that it was already allocated to, reload might not
182 static HARD_REG_SET
*pseudo_previous_regs
;
184 /* This vector of reg sets indicates, for each pseudo, which hard
185 registers may not be used for retrying global allocation because they
186 are used as spill registers during one of the insns in which the
188 static HARD_REG_SET
*pseudo_forbidden_regs
;
190 /* All hard regs that have been used as spill registers for any insn are
191 marked in this set. */
192 static HARD_REG_SET used_spill_regs
;
194 /* Index of last register assigned as a spill register. We allocate in
195 a round-robin fashion. */
196 static int last_spill_reg
;
198 /* Record the stack slot for each spilled hard register. */
199 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
201 /* Width allocated so far for that stack slot. */
202 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
204 /* Record which pseudos needed to be spilled. */
205 static regset_head spilled_pseudos
;
207 /* Record which pseudos changed their allocation in finish_spills. */
208 static regset_head changed_allocation_pseudos
;
210 /* Used for communication between order_regs_for_reload and count_pseudo.
211 Used to avoid counting one pseudo twice. */
212 static regset_head pseudos_counted
;
214 /* First uid used by insns created by reload in this function.
215 Used in find_equiv_reg. */
216 int reload_first_uid
;
218 /* Flag set by local-alloc or global-alloc if anything is live in
219 a call-clobbered reg across calls. */
220 int caller_save_needed
;
222 /* Set to 1 while reload_as_needed is operating.
223 Required by some machines to handle any generated moves differently. */
224 int reload_in_progress
= 0;
226 /* This obstack is used for allocation of rtl during register elimination.
227 The allocated storage can be freed once find_reloads has processed the
229 static struct obstack reload_obstack
;
231 /* Points to the beginning of the reload_obstack. All insn_chain structures
232 are allocated first. */
233 static char *reload_startobj
;
235 /* The point after all insn_chain structures. Used to quickly deallocate
236 memory allocated in copy_reloads during calculate_needs_all_insns. */
237 static char *reload_firstobj
;
239 /* This points before all local rtl generated by register elimination.
240 Used to quickly free all memory after processing one insn. */
241 static char *reload_insn_firstobj
;
243 /* List of insn_chain instructions, one for every insn that reload needs to
245 struct insn_chain
*reload_insn_chain
;
247 /* TRUE if we potentially left dead insns in the insn stream and want to
248 run DCE immediately after reload, FALSE otherwise. */
249 static bool need_dce
;
251 /* List of all insns needing reloads. */
252 static struct insn_chain
*insns_need_reload
;
254 /* This structure is used to record information about register eliminations.
255 Each array entry describes one possible way of eliminating a register
256 in favor of another. If there is more than one way of eliminating a
257 particular register, the most preferred should be specified first. */
261 int from
; /* Register number to be eliminated. */
262 int to
; /* Register number used as replacement. */
263 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
264 int can_eliminate
; /* Nonzero if this elimination can be done. */
265 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
266 target hook in previous scan over insns
268 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
269 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
270 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
271 rtx from_rtx
; /* REG rtx for the register to be eliminated.
272 We cannot simply compare the number since
273 we might then spuriously replace a hard
274 register corresponding to a pseudo
275 assigned to the reg to be eliminated. */
276 rtx to_rtx
; /* REG rtx for the replacement. */
279 static struct elim_table
*reg_eliminate
= 0;
281 /* This is an intermediate structure to initialize the table. It has
282 exactly the members provided by ELIMINABLE_REGS. */
283 static const struct elim_table_1
287 } reg_eliminate_1
[] =
289 /* If a set of eliminable registers was specified, define the table from it.
290 Otherwise, default to the normal case of the frame pointer being
291 replaced by the stack pointer. */
293 #ifdef ELIMINABLE_REGS
296 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
299 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
301 /* Record the number of pending eliminations that have an offset not equal
302 to their initial offset. If nonzero, we use a new copy of each
303 replacement result in any insns encountered. */
304 int num_not_at_initial_offset
;
306 /* Count the number of registers that we may be able to eliminate. */
307 static int num_eliminable
;
308 /* And the number of registers that are equivalent to a constant that
309 can be eliminated to frame_pointer / arg_pointer + constant. */
310 static int num_eliminable_invariants
;
312 /* For each label, we record the offset of each elimination. If we reach
313 a label by more than one path and an offset differs, we cannot do the
314 elimination. This information is indexed by the difference of the
315 number of the label and the first label number. We can't offset the
316 pointer itself as this can cause problems on machines with segmented
317 memory. The first table is an array of flags that records whether we
318 have yet encountered a label and the second table is an array of arrays,
319 one entry in the latter array for each elimination. */
321 static int first_label_num
;
322 static char *offsets_known_at
;
323 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
325 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
327 /* Stack of addresses where an rtx has been changed. We can undo the
328 changes by popping items off the stack and restoring the original
329 value at each location.
331 We use this simplistic undo capability rather than copy_rtx as copy_rtx
332 will not make a deep copy of a normally sharable rtx, such as
333 (const (plus (symbol_ref) (const_int))). If such an expression appears
334 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
335 rtx expression would be changed. See PR 42431. */
338 static vec
<rtx_p
> substitute_stack
;
340 /* Number of labels in the current function. */
342 static int num_labels
;
344 static void replace_pseudos_in (rtx
*, machine_mode
, rtx
);
345 static void maybe_fix_stack_asms (void);
346 static void copy_reloads (struct insn_chain
*);
347 static void calculate_needs_all_insns (int);
348 static int find_reg (struct insn_chain
*, int);
349 static void find_reload_regs (struct insn_chain
*);
350 static void select_reload_regs (void);
351 static void delete_caller_save_insns (void);
353 static void spill_failure (rtx_insn
*, enum reg_class
);
354 static void count_spilled_pseudo (int, int, int);
355 static void delete_dead_insn (rtx_insn
*);
356 static void alter_reg (int, int, bool);
357 static void set_label_offsets (rtx
, rtx_insn
*, int);
358 static void check_eliminable_occurrences (rtx
);
359 static void elimination_effects (rtx
, machine_mode
);
360 static rtx
eliminate_regs_1 (rtx
, machine_mode
, rtx
, bool, bool);
361 static int eliminate_regs_in_insn (rtx_insn
*, int);
362 static void update_eliminable_offsets (void);
363 static void mark_not_eliminable (rtx
, const_rtx
, void *);
364 static void set_initial_elim_offsets (void);
365 static bool verify_initial_elim_offsets (void);
366 static void set_initial_label_offsets (void);
367 static void set_offsets_for_label (rtx_insn
*);
368 static void init_eliminable_invariants (rtx_insn
*, bool);
369 static void init_elim_table (void);
370 static void free_reg_equiv (void);
371 static void update_eliminables (HARD_REG_SET
*);
372 static bool update_eliminables_and_spill (void);
373 static void elimination_costs_in_insn (rtx_insn
*);
374 static void spill_hard_reg (unsigned int, int);
375 static int finish_spills (int);
376 static void scan_paradoxical_subregs (rtx
);
377 static void count_pseudo (int);
378 static void order_regs_for_reload (struct insn_chain
*);
379 static void reload_as_needed (int);
380 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
381 static void forget_marked_reloads (regset
);
382 static int reload_reg_class_lower (const void *, const void *);
383 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
385 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
387 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
388 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
390 static int free_for_value_p (int, machine_mode
, int, enum reload_type
,
392 static int allocate_reload_reg (struct insn_chain
*, int, int);
393 static int conflicts_with_override (rtx
);
394 static void failed_reload (rtx_insn
*, int);
395 static int set_reload_reg (int, int);
396 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
397 static void choose_reload_regs (struct insn_chain
*);
398 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
400 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
402 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
403 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
404 static void emit_reload_insns (struct insn_chain
*);
405 static void delete_output_reload (rtx_insn
*, int, int, rtx
);
406 static void delete_address_reloads (rtx_insn
*, rtx_insn
*);
407 static void delete_address_reloads_1 (rtx_insn
*, rtx
, rtx_insn
*);
408 static void inc_for_reload (rtx
, rtx
, rtx
, int);
409 static void add_auto_inc_notes (rtx_insn
*, rtx
);
410 static void substitute (rtx
*, const_rtx
, rtx
);
411 static bool gen_reload_chain_without_interm_reg_p (int, int);
412 static int reloads_conflict (int, int);
413 static rtx_insn
*gen_reload (rtx
, rtx
, int, enum reload_type
);
414 static rtx_insn
*emit_insn_if_valid_for_reload (rtx
);
416 /* Initialize the reload pass. This is called at the beginning of compilation
417 and may be called again if the target is reinitialized. */
424 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
425 Set spill_indirect_levels to the number of levels such addressing is
426 permitted, zero if it is not permitted at all. */
429 = gen_rtx_MEM (Pmode
,
432 LAST_VIRTUAL_REGISTER
+ 1),
433 gen_int_mode (4, Pmode
)));
434 spill_indirect_levels
= 0;
436 while (memory_address_p (QImode
, tem
))
438 spill_indirect_levels
++;
439 tem
= gen_rtx_MEM (Pmode
, tem
);
442 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
444 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
445 indirect_symref_ok
= memory_address_p (QImode
, tem
);
447 /* See if reg+reg is a valid (and offsettable) address. */
449 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
451 tem
= gen_rtx_PLUS (Pmode
,
452 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
453 gen_rtx_REG (Pmode
, i
));
455 /* This way, we make sure that reg+reg is an offsettable address. */
456 tem
= plus_constant (Pmode
, tem
, 4);
458 if (memory_address_p (QImode
, tem
))
460 double_reg_address_ok
= 1;
465 /* Initialize obstack for our rtl allocation. */
466 if (reload_startobj
== NULL
)
468 gcc_obstack_init (&reload_obstack
);
469 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
472 INIT_REG_SET (&spilled_pseudos
);
473 INIT_REG_SET (&changed_allocation_pseudos
);
474 INIT_REG_SET (&pseudos_counted
);
477 /* List of insn chains that are currently unused. */
478 static struct insn_chain
*unused_insn_chains
= 0;
480 /* Allocate an empty insn_chain structure. */
482 new_insn_chain (void)
484 struct insn_chain
*c
;
486 if (unused_insn_chains
== 0)
488 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
489 INIT_REG_SET (&c
->live_throughout
);
490 INIT_REG_SET (&c
->dead_or_set
);
494 c
= unused_insn_chains
;
495 unused_insn_chains
= c
->next
;
497 c
->is_caller_save_insn
= 0;
498 c
->need_operand_change
= 0;
504 /* Small utility function to set all regs in hard reg set TO which are
505 allocated to pseudos in regset FROM. */
508 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
511 reg_set_iterator rsi
;
513 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
515 int r
= reg_renumber
[regno
];
519 /* reload_combine uses the information from DF_LIVE_IN,
520 which might still contain registers that have not
521 actually been allocated since they have an
523 gcc_assert (ira_conflicts_p
|| reload_completed
);
526 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
530 /* Replace all pseudos found in LOC with their corresponding
534 replace_pseudos_in (rtx
*loc
, machine_mode mem_mode
, rtx usage
)
547 unsigned int regno
= REGNO (x
);
549 if (regno
< FIRST_PSEUDO_REGISTER
)
552 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
556 replace_pseudos_in (loc
, mem_mode
, usage
);
560 if (reg_equiv_constant (regno
))
561 *loc
= reg_equiv_constant (regno
);
562 else if (reg_equiv_invariant (regno
))
563 *loc
= reg_equiv_invariant (regno
);
564 else if (reg_equiv_mem (regno
))
565 *loc
= reg_equiv_mem (regno
);
566 else if (reg_equiv_address (regno
))
567 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
570 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
571 || REGNO (regno_reg_rtx
[regno
]) != regno
);
572 *loc
= regno_reg_rtx
[regno
];
577 else if (code
== MEM
)
579 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
583 /* Process each of our operands recursively. */
584 fmt
= GET_RTX_FORMAT (code
);
585 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
587 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
588 else if (*fmt
== 'E')
589 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
590 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
593 /* Determine if the current function has an exception receiver block
594 that reaches the exit block via non-exceptional edges */
597 has_nonexceptional_receiver (void)
601 basic_block
*tos
, *worklist
, bb
;
603 /* If we're not optimizing, then just err on the safe side. */
607 /* First determine which blocks can reach exit via normal paths. */
608 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
610 FOR_EACH_BB_FN (bb
, cfun
)
611 bb
->flags
&= ~BB_REACHABLE
;
613 /* Place the exit block on our worklist. */
614 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
615 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
617 /* Iterate: find everything reachable from what we've already seen. */
618 while (tos
!= worklist
)
622 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
623 if (!(e
->flags
& EDGE_ABNORMAL
))
625 basic_block src
= e
->src
;
627 if (!(src
->flags
& BB_REACHABLE
))
629 src
->flags
|= BB_REACHABLE
;
636 /* Now see if there's a reachable block with an exceptional incoming
638 FOR_EACH_BB_FN (bb
, cfun
)
639 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
642 /* No exceptional block reached exit unexceptionally. */
646 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
647 zero elements) to MAX_REG_NUM elements.
649 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
651 grow_reg_equivs (void)
653 int old_size
= vec_safe_length (reg_equivs
);
654 int max_regno
= max_reg_num ();
658 memset (&ze
, 0, sizeof (reg_equivs_t
));
659 vec_safe_reserve (reg_equivs
, max_regno
);
660 for (i
= old_size
; i
< max_regno
; i
++)
661 reg_equivs
->quick_insert (i
, ze
);
665 /* Global variables used by reload and its subroutines. */
667 /* The current basic block while in calculate_elim_costs_all_insns. */
668 static basic_block elim_bb
;
670 /* Set during calculate_needs if an insn needs register elimination. */
671 static int something_needs_elimination
;
672 /* Set during calculate_needs if an insn needs an operand changed. */
673 static int something_needs_operands_changed
;
674 /* Set by alter_regs if we spilled a register to the stack. */
675 static bool something_was_spilled
;
677 /* Nonzero means we couldn't get enough spill regs. */
680 /* Temporary array of pseudo-register number. */
681 static int *temp_pseudo_reg_arr
;
683 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
684 If that insn didn't set the register (i.e., it copied the register to
685 memory), just delete that insn instead of the equivalencing insn plus
686 anything now dead. If we call delete_dead_insn on that insn, we may
687 delete the insn that actually sets the register if the register dies
688 there and that is incorrect. */
692 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
694 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
697 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
699 rtx_insn
*equiv_insn
= as_a
<rtx_insn
*> (XEXP (list
, 0));
701 /* If we already deleted the insn or if it may trap, we can't
702 delete it. The latter case shouldn't happen, but can
703 if an insn has a variable address, gets a REG_EH_REGION
704 note added to it, and then gets converted into a load
705 from a constant address. */
706 if (NOTE_P (equiv_insn
)
707 || can_throw_internal (equiv_insn
))
709 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
710 delete_dead_insn (equiv_insn
);
712 SET_INSN_DELETED (equiv_insn
);
718 /* Return true if remove_init_insns will delete INSN. */
720 will_delete_init_insn_p (rtx_insn
*insn
)
722 rtx set
= single_set (insn
);
723 if (!set
|| !REG_P (SET_DEST (set
)))
725 unsigned regno
= REGNO (SET_DEST (set
));
727 if (can_throw_internal (insn
))
730 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
733 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
735 rtx equiv_insn
= XEXP (list
, 0);
736 if (equiv_insn
== insn
)
742 /* Main entry point for the reload pass.
744 FIRST is the first insn of the function being compiled.
746 GLOBAL nonzero means we were called from global_alloc
747 and should attempt to reallocate any pseudoregs that we
748 displace from hard regs we will use for reloads.
749 If GLOBAL is zero, we do not have enough information to do that,
750 so any pseudo reg that is spilled must go to the stack.
752 Return value is TRUE if reload likely left dead insns in the
753 stream and a DCE pass should be run to elimiante them. Else the
754 return value is FALSE. */
757 reload (rtx_insn
*first
, int global
)
761 struct elim_table
*ep
;
765 /* Make sure even insns with volatile mem refs are recognizable. */
770 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
772 /* Make sure that the last insn in the chain
773 is not something that needs reloading. */
774 emit_note (NOTE_INSN_DELETED
);
776 /* Enable find_equiv_reg to distinguish insns made by reload. */
777 reload_first_uid
= get_max_uid ();
779 #ifdef SECONDARY_MEMORY_NEEDED
780 /* Initialize the secondary memory table. */
781 clear_secondary_mem ();
784 /* We don't have a stack slot for any spill reg yet. */
785 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
786 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
788 /* Initialize the save area information for caller-save, in case some
792 /* Compute which hard registers are now in use
793 as homes for pseudo registers.
794 This is done here rather than (eg) in global_alloc
795 because this point is reached even if not optimizing. */
796 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
799 /* A function that has a nonlocal label that can reach the exit
800 block via non-exceptional paths must save all call-saved
802 if (cfun
->has_nonlocal_label
803 && has_nonexceptional_receiver ())
804 crtl
->saves_all_registers
= 1;
806 if (crtl
->saves_all_registers
)
807 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
808 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
809 df_set_regs_ever_live (i
, true);
811 /* Find all the pseudo registers that didn't get hard regs
812 but do have known equivalent constants or memory slots.
813 These include parameters (known equivalent to parameter slots)
814 and cse'd or loop-moved constant memory addresses.
816 Record constant equivalents in reg_equiv_constant
817 so they will be substituted by find_reloads.
818 Record memory equivalents in reg_mem_equiv so they can
819 be substituted eventually by altering the REG-rtx's. */
822 reg_old_renumber
= XCNEWVEC (short, max_regno
);
823 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
824 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
825 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
827 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
829 init_eliminable_invariants (first
, true);
832 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
833 stack slots to the pseudos that lack hard regs or equivalents.
834 Do not touch virtual registers. */
836 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
837 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
838 temp_pseudo_reg_arr
[n
++] = i
;
841 /* Ask IRA to order pseudo-registers for better stack slot
843 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
845 for (i
= 0; i
< n
; i
++)
846 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
848 /* If we have some registers we think can be eliminated, scan all insns to
849 see if there is an insn that sets one of these registers to something
850 other than itself plus a constant. If so, the register cannot be
851 eliminated. Doing this scan here eliminates an extra pass through the
852 main reload loop in the most common case where register elimination
854 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
856 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
858 maybe_fix_stack_asms ();
860 insns_need_reload
= 0;
861 something_needs_elimination
= 0;
863 /* Initialize to -1, which means take the first spill register. */
866 /* Spill any hard regs that we know we can't eliminate. */
867 CLEAR_HARD_REG_SET (used_spill_regs
);
868 /* There can be multiple ways to eliminate a register;
869 they should be listed adjacently.
870 Elimination for any register fails only if all possible ways fail. */
871 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
874 int can_eliminate
= 0;
877 can_eliminate
|= ep
->can_eliminate
;
880 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
882 spill_hard_reg (from
, 1);
885 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
)
886 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
888 finish_spills (global
);
890 /* From now on, we may need to generate moves differently. We may also
891 allow modifications of insns which cause them to not be recognized.
892 Any such modifications will be cleaned up during reload itself. */
893 reload_in_progress
= 1;
895 /* This loop scans the entire function each go-round
896 and repeats until one repetition spills no additional hard regs. */
899 int something_changed
;
901 HOST_WIDE_INT starting_frame_size
;
903 starting_frame_size
= get_frame_size ();
904 something_was_spilled
= false;
906 set_initial_elim_offsets ();
907 set_initial_label_offsets ();
909 /* For each pseudo register that has an equivalent location defined,
910 try to eliminate any eliminable registers (such as the frame pointer)
911 assuming initial offsets for the replacement register, which
914 If the resulting location is directly addressable, substitute
915 the MEM we just got directly for the old REG.
917 If it is not addressable but is a constant or the sum of a hard reg
918 and constant, it is probably not addressable because the constant is
919 out of range, in that case record the address; we will generate
920 hairy code to compute the address in a register each time it is
921 needed. Similarly if it is a hard register, but one that is not
922 valid as an address register.
924 If the location is not addressable, but does not have one of the
925 above forms, assign a stack slot. We have to do this to avoid the
926 potential of producing lots of reloads if, e.g., a location involves
927 a pseudo that didn't get a hard register and has an equivalent memory
928 location that also involves a pseudo that didn't get a hard register.
930 Perhaps at some point we will improve reload_when_needed handling
931 so this problem goes away. But that's very hairy. */
933 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
934 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
936 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
939 if (strict_memory_address_addr_space_p
940 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
942 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
943 else if (CONSTANT_P (XEXP (x
, 0))
944 || (REG_P (XEXP (x
, 0))
945 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
946 || (GET_CODE (XEXP (x
, 0)) == PLUS
947 && REG_P (XEXP (XEXP (x
, 0), 0))
948 && (REGNO (XEXP (XEXP (x
, 0), 0))
949 < FIRST_PSEUDO_REGISTER
)
950 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
951 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
954 /* Make a new stack slot. Then indicate that something
955 changed so we go back and recompute offsets for
956 eliminable registers because the allocation of memory
957 below might change some offset. reg_equiv_{mem,address}
958 will be set up for this pseudo on the next pass around
960 reg_equiv_memory_loc (i
) = 0;
961 reg_equiv_init (i
) = 0;
962 alter_reg (i
, -1, true);
966 if (caller_save_needed
)
969 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
971 /* If we have a stack frame, we must align it now. The
972 stack size may be a part of the offset computation for
973 register elimination. So if this changes the stack size,
974 then repeat the elimination bookkeeping. We don't
975 realign when there is no stack, as that will cause a
976 stack frame when none is needed should
977 STARTING_FRAME_OFFSET not be already aligned to
979 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
981 /* If we allocated another stack slot, redo elimination bookkeeping. */
982 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
984 if (update_eliminables_and_spill ())
985 finish_spills (global
);
989 if (caller_save_needed
)
991 save_call_clobbered_regs ();
992 /* That might have allocated new insn_chain structures. */
993 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
996 calculate_needs_all_insns (global
);
998 if (! ira_conflicts_p
)
999 /* Don't do it for IRA. We need this info because we don't
1000 change live_throughout and dead_or_set for chains when IRA
1002 CLEAR_REG_SET (&spilled_pseudos
);
1006 something_changed
= 0;
1008 /* If we allocated any new memory locations, make another pass
1009 since it might have changed elimination offsets. */
1010 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
1011 something_changed
= 1;
1013 /* Even if the frame size remained the same, we might still have
1014 changed elimination offsets, e.g. if find_reloads called
1015 force_const_mem requiring the back end to allocate a constant
1016 pool base register that needs to be saved on the stack. */
1017 else if (!verify_initial_elim_offsets ())
1018 something_changed
= 1;
1020 if (update_eliminables_and_spill ())
1023 something_changed
= 1;
1027 select_reload_regs ();
1032 if (insns_need_reload
!= 0 || did_spill
)
1033 something_changed
|= finish_spills (global
);
1035 if (! something_changed
)
1038 if (caller_save_needed
)
1039 delete_caller_save_insns ();
1041 obstack_free (&reload_obstack
, reload_firstobj
);
1044 /* If global-alloc was run, notify it of any register eliminations we have
1047 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1048 if (ep
->can_eliminate
)
1049 mark_elimination (ep
->from
, ep
->to
);
1051 remove_init_insns ();
1053 /* Use the reload registers where necessary
1054 by generating move instructions to move the must-be-register
1055 values into or out of the reload registers. */
1057 if (insns_need_reload
!= 0 || something_needs_elimination
1058 || something_needs_operands_changed
)
1060 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1062 reload_as_needed (global
);
1064 gcc_assert (old_frame_size
== get_frame_size ());
1066 gcc_assert (verify_initial_elim_offsets ());
1069 /* If we were able to eliminate the frame pointer, show that it is no
1070 longer live at the start of any basic block. If it ls live by
1071 virtue of being in a pseudo, that pseudo will be marked live
1072 and hence the frame pointer will be known to be live via that
1075 if (! frame_pointer_needed
)
1076 FOR_EACH_BB_FN (bb
, cfun
)
1077 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1079 /* Come here (with failure set nonzero) if we can't get enough spill
1083 CLEAR_REG_SET (&changed_allocation_pseudos
);
1084 CLEAR_REG_SET (&spilled_pseudos
);
1085 reload_in_progress
= 0;
1087 /* Now eliminate all pseudo regs by modifying them into
1088 their equivalent memory references.
1089 The REG-rtx's for the pseudos are modified in place,
1090 so all insns that used to refer to them now refer to memory.
1092 For a reg that has a reg_equiv_address, all those insns
1093 were changed by reloading so that no insns refer to it any longer;
1094 but the DECL_RTL of a variable decl may refer to it,
1095 and if so this causes the debugging info to mention the variable. */
1097 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1101 if (reg_equiv_mem (i
))
1102 addr
= XEXP (reg_equiv_mem (i
), 0);
1104 if (reg_equiv_address (i
))
1105 addr
= reg_equiv_address (i
);
1109 if (reg_renumber
[i
] < 0)
1111 rtx reg
= regno_reg_rtx
[i
];
1113 REG_USERVAR_P (reg
) = 0;
1114 PUT_CODE (reg
, MEM
);
1115 XEXP (reg
, 0) = addr
;
1116 if (reg_equiv_memory_loc (i
))
1117 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1119 MEM_ATTRS (reg
) = 0;
1120 MEM_NOTRAP_P (reg
) = 1;
1122 else if (reg_equiv_mem (i
))
1123 XEXP (reg_equiv_mem (i
), 0) = addr
;
1126 /* We don't want complex addressing modes in debug insns
1127 if simpler ones will do, so delegitimize equivalences
1129 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1131 rtx reg
= regno_reg_rtx
[i
];
1135 if (reg_equiv_constant (i
))
1136 equiv
= reg_equiv_constant (i
);
1137 else if (reg_equiv_invariant (i
))
1138 equiv
= reg_equiv_invariant (i
);
1139 else if (reg
&& MEM_P (reg
))
1140 equiv
= targetm
.delegitimize_address (reg
);
1141 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1147 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1149 insn
= DF_REF_INSN (use
);
1151 /* Make sure the next ref is for a different instruction,
1152 so that we're not affected by the rescan. */
1153 next
= DF_REF_NEXT_REG (use
);
1154 while (next
&& DF_REF_INSN (next
) == insn
)
1155 next
= DF_REF_NEXT_REG (next
);
1157 if (DEBUG_INSN_P (insn
))
1161 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1162 df_insn_rescan_debug_internal (insn
);
1165 INSN_VAR_LOCATION_LOC (insn
)
1166 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1173 /* We must set reload_completed now since the cleanup_subreg_operands call
1174 below will re-recognize each insn and reload may have generated insns
1175 which are only valid during and after reload. */
1176 reload_completed
= 1;
1178 /* Make a pass over all the insns and delete all USEs which we inserted
1179 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1180 notes. Delete all CLOBBER insns, except those that refer to the return
1181 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1182 from misarranging variable-array code, and simplify (subreg (reg))
1183 operands. Strip and regenerate REG_INC notes that may have been moved
1186 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1192 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1193 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1195 if ((GET_CODE (PATTERN (insn
)) == USE
1196 /* We mark with QImode USEs introduced by reload itself. */
1197 && (GET_MODE (insn
) == QImode
1198 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1199 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1200 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1201 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1202 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1203 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1204 != stack_pointer_rtx
))
1205 && (!REG_P (XEXP (PATTERN (insn
), 0))
1206 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1212 /* Some CLOBBERs may survive until here and still reference unassigned
1213 pseudos with const equivalent, which may in turn cause ICE in later
1214 passes if the reference remains in place. */
1215 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1216 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1217 VOIDmode
, PATTERN (insn
));
1219 /* Discard obvious no-ops, even without -O. This optimization
1220 is fast and doesn't interfere with debugging. */
1221 if (NONJUMP_INSN_P (insn
)
1222 && GET_CODE (PATTERN (insn
)) == SET
1223 && REG_P (SET_SRC (PATTERN (insn
)))
1224 && REG_P (SET_DEST (PATTERN (insn
)))
1225 && (REGNO (SET_SRC (PATTERN (insn
)))
1226 == REGNO (SET_DEST (PATTERN (insn
)))))
1232 pnote
= ®_NOTES (insn
);
1235 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1236 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1237 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1238 *pnote
= XEXP (*pnote
, 1);
1240 pnote
= &XEXP (*pnote
, 1);
1244 add_auto_inc_notes (insn
, PATTERN (insn
));
1246 /* Simplify (subreg (reg)) if it appears as an operand. */
1247 cleanup_subreg_operands (insn
);
1249 /* Clean up invalid ASMs so that they don't confuse later passes.
1251 if (asm_noperands (PATTERN (insn
)) >= 0)
1253 extract_insn (insn
);
1254 if (!constrain_operands (1, get_enabled_alternatives (insn
)))
1256 error_for_asm (insn
,
1257 "%<asm%> operand has impossible constraints");
1264 free (temp_pseudo_reg_arr
);
1266 /* Indicate that we no longer have known memory locations or constants. */
1269 free (reg_max_ref_width
);
1270 free (reg_old_renumber
);
1271 free (pseudo_previous_regs
);
1272 free (pseudo_forbidden_regs
);
1274 CLEAR_HARD_REG_SET (used_spill_regs
);
1275 for (i
= 0; i
< n_spills
; i
++)
1276 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1278 /* Free all the insn_chain structures at once. */
1279 obstack_free (&reload_obstack
, reload_startobj
);
1280 unused_insn_chains
= 0;
1282 inserted
= fixup_abnormal_edges ();
1284 /* We've possibly turned single trapping insn into multiple ones. */
1285 if (cfun
->can_throw_non_call_exceptions
)
1288 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
1289 bitmap_ones (blocks
);
1290 find_many_sub_basic_blocks (blocks
);
1291 sbitmap_free (blocks
);
1295 commit_edge_insertions ();
1297 /* Replacing pseudos with their memory equivalents might have
1298 created shared rtx. Subsequent passes would get confused
1299 by this, so unshare everything here. */
1300 unshare_all_rtl_again (first
);
1302 #ifdef STACK_BOUNDARY
1303 /* init_emit has set the alignment of the hard frame pointer
1304 to STACK_BOUNDARY. It is very likely no longer valid if
1305 the hard frame pointer was used for register allocation. */
1306 if (!frame_pointer_needed
)
1307 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1310 substitute_stack
.release ();
1312 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1314 reload_completed
= !failure
;
1319 /* Yet another special case. Unfortunately, reg-stack forces people to
1320 write incorrect clobbers in asm statements. These clobbers must not
1321 cause the register to appear in bad_spill_regs, otherwise we'll call
1322 fatal_insn later. We clear the corresponding regnos in the live
1323 register sets to avoid this.
1324 The whole thing is rather sick, I'm afraid. */
1327 maybe_fix_stack_asms (void)
1330 const char *constraints
[MAX_RECOG_OPERANDS
];
1331 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1332 struct insn_chain
*chain
;
1334 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1337 HARD_REG_SET clobbered
, allowed
;
1340 if (! INSN_P (chain
->insn
)
1341 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1343 pat
= PATTERN (chain
->insn
);
1344 if (GET_CODE (pat
) != PARALLEL
)
1347 CLEAR_HARD_REG_SET (clobbered
);
1348 CLEAR_HARD_REG_SET (allowed
);
1350 /* First, make a mask of all stack regs that are clobbered. */
1351 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1353 rtx t
= XVECEXP (pat
, 0, i
);
1354 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1355 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1358 /* Get the operand values and constraints out of the insn. */
1359 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1360 constraints
, operand_mode
, NULL
);
1362 /* For every operand, see what registers are allowed. */
1363 for (i
= 0; i
< noperands
; i
++)
1365 const char *p
= constraints
[i
];
1366 /* For every alternative, we compute the class of registers allowed
1367 for reloading in CLS, and merge its contents into the reg set
1369 int cls
= (int) NO_REGS
;
1375 if (c
== '\0' || c
== ',' || c
== '#')
1377 /* End of one alternative - mark the regs in the current
1378 class, and reset the class. */
1379 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1385 } while (c
!= '\0' && c
!= ',');
1394 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1398 enum constraint_num cn
= lookup_constraint (p
);
1399 if (insn_extra_address_constraint (cn
))
1400 cls
= (int) reg_class_subunion
[cls
]
1401 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1404 cls
= (int) reg_class_subunion
[cls
]
1405 [reg_class_for_constraint (cn
)];
1408 p
+= CONSTRAINT_LEN (c
, p
);
1411 /* Those of the registers which are clobbered, but allowed by the
1412 constraints, must be usable as reload registers. So clear them
1413 out of the life information. */
1414 AND_HARD_REG_SET (allowed
, clobbered
);
1415 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1416 if (TEST_HARD_REG_BIT (allowed
, i
))
1418 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1419 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1426 /* Copy the global variables n_reloads and rld into the corresponding elts
1429 copy_reloads (struct insn_chain
*chain
)
1431 chain
->n_reloads
= n_reloads
;
1432 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1433 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1434 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1437 /* Walk the chain of insns, and determine for each whether it needs reloads
1438 and/or eliminations. Build the corresponding insns_need_reload list, and
1439 set something_needs_elimination as appropriate. */
1441 calculate_needs_all_insns (int global
)
1443 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1444 struct insn_chain
*chain
, *next
= 0;
1446 something_needs_elimination
= 0;
1448 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1449 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1451 rtx_insn
*insn
= chain
->insn
;
1455 /* Clear out the shortcuts. */
1456 chain
->n_reloads
= 0;
1457 chain
->need_elim
= 0;
1458 chain
->need_reload
= 0;
1459 chain
->need_operand_change
= 0;
1461 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1462 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1463 what effects this has on the known offsets at labels. */
1465 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1466 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1467 set_label_offsets (insn
, insn
, 0);
1471 rtx old_body
= PATTERN (insn
);
1472 int old_code
= INSN_CODE (insn
);
1473 rtx old_notes
= REG_NOTES (insn
);
1474 int did_elimination
= 0;
1475 int operands_changed
= 0;
1477 /* Skip insns that only set an equivalence. */
1478 if (will_delete_init_insn_p (insn
))
1481 /* If needed, eliminate any eliminable registers. */
1482 if (num_eliminable
|| num_eliminable_invariants
)
1483 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1485 /* Analyze the instruction. */
1486 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1487 global
, spill_reg_order
);
1489 /* If a no-op set needs more than one reload, this is likely
1490 to be something that needs input address reloads. We
1491 can't get rid of this cleanly later, and it is of no use
1492 anyway, so discard it now.
1493 We only do this when expensive_optimizations is enabled,
1494 since this complements reload inheritance / output
1495 reload deletion, and it can make debugging harder. */
1496 if (flag_expensive_optimizations
&& n_reloads
> 1)
1498 rtx set
= single_set (insn
);
1501 ((SET_SRC (set
) == SET_DEST (set
)
1502 && REG_P (SET_SRC (set
))
1503 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1504 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1505 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1506 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1507 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1508 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1509 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1510 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1512 if (ira_conflicts_p
)
1513 /* Inform IRA about the insn deletion. */
1514 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1515 REGNO (SET_SRC (set
)));
1517 /* Delete it from the reload chain. */
1519 chain
->prev
->next
= next
;
1521 reload_insn_chain
= next
;
1523 next
->prev
= chain
->prev
;
1524 chain
->next
= unused_insn_chains
;
1525 unused_insn_chains
= chain
;
1530 update_eliminable_offsets ();
1532 /* Remember for later shortcuts which insns had any reloads or
1533 register eliminations. */
1534 chain
->need_elim
= did_elimination
;
1535 chain
->need_reload
= n_reloads
> 0;
1536 chain
->need_operand_change
= operands_changed
;
1538 /* Discard any register replacements done. */
1539 if (did_elimination
)
1541 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1542 PATTERN (insn
) = old_body
;
1543 INSN_CODE (insn
) = old_code
;
1544 REG_NOTES (insn
) = old_notes
;
1545 something_needs_elimination
= 1;
1548 something_needs_operands_changed
|= operands_changed
;
1552 copy_reloads (chain
);
1553 *pprev_reload
= chain
;
1554 pprev_reload
= &chain
->next_need_reload
;
1561 /* This function is called from the register allocator to set up estimates
1562 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1563 an invariant. The structure is similar to calculate_needs_all_insns. */
1566 calculate_elim_costs_all_insns (void)
1568 int *reg_equiv_init_cost
;
1572 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1574 init_eliminable_invariants (get_insns (), false);
1576 set_initial_elim_offsets ();
1577 set_initial_label_offsets ();
1579 FOR_EACH_BB_FN (bb
, cfun
)
1584 FOR_BB_INSNS (bb
, insn
)
1586 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1587 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1588 what effects this has on the known offsets at labels. */
1590 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1591 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1592 set_label_offsets (insn
, insn
, 0);
1596 rtx set
= single_set (insn
);
1598 /* Skip insns that only set an equivalence. */
1599 if (set
&& REG_P (SET_DEST (set
))
1600 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1601 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1602 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1604 unsigned regno
= REGNO (SET_DEST (set
));
1605 rtx_insn_list
*init
= reg_equiv_init (regno
);
1608 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1610 machine_mode mode
= GET_MODE (SET_DEST (set
));
1611 int cost
= set_src_cost (t
, mode
,
1612 optimize_bb_for_speed_p (bb
));
1613 int freq
= REG_FREQ_FROM_BB (bb
);
1615 reg_equiv_init_cost
[regno
] = cost
* freq
;
1619 /* If needed, eliminate any eliminable registers. */
1620 if (num_eliminable
|| num_eliminable_invariants
)
1621 elimination_costs_in_insn (insn
);
1624 update_eliminable_offsets ();
1628 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1630 if (reg_equiv_invariant (i
))
1632 if (reg_equiv_init (i
))
1634 int cost
= reg_equiv_init_cost
[i
];
1637 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1639 ira_adjust_equiv_reg_cost (i
, cost
);
1645 "Reg %d had equivalence, but can't be eliminated\n",
1647 ira_adjust_equiv_reg_cost (i
, 0);
1652 free (reg_equiv_init_cost
);
1653 free (offsets_known_at
);
1656 offsets_known_at
= NULL
;
1659 /* Comparison function for qsort to decide which of two reloads
1660 should be handled first. *P1 and *P2 are the reload numbers. */
1663 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1665 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1668 /* Consider required reloads before optional ones. */
1669 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1673 /* Count all solitary classes before non-solitary ones. */
1674 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1675 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1679 /* Aside from solitaires, consider all multi-reg groups first. */
1680 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1684 /* Consider reloads in order of increasing reg-class number. */
1685 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1689 /* If reloads are equally urgent, sort by reload number,
1690 so that the results of qsort leave nothing to chance. */
1694 /* The cost of spilling each hard reg. */
1695 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1697 /* When spilling multiple hard registers, we use SPILL_COST for the first
1698 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1699 only the first hard reg for a multi-reg pseudo. */
1700 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1702 /* Map of hard regno to pseudo regno currently occupying the hard
1704 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1706 /* Update the spill cost arrays, considering that pseudo REG is live. */
1709 count_pseudo (int reg
)
1711 int freq
= REG_FREQ (reg
);
1712 int r
= reg_renumber
[reg
];
1715 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1716 if (ira_conflicts_p
&& r
< 0)
1719 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1720 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1723 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1725 gcc_assert (r
>= 0);
1727 spill_add_cost
[r
] += freq
;
1728 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1731 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1732 spill_cost
[r
+ nregs
] += freq
;
1736 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1737 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1740 order_regs_for_reload (struct insn_chain
*chain
)
1743 HARD_REG_SET used_by_pseudos
;
1744 HARD_REG_SET used_by_pseudos2
;
1745 reg_set_iterator rsi
;
1747 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1749 memset (spill_cost
, 0, sizeof spill_cost
);
1750 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1751 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1752 hard_regno_to_pseudo_regno
[i
] = -1;
1754 /* Count number of uses of each hard reg by pseudo regs allocated to it
1755 and then order them by decreasing use. First exclude hard registers
1756 that are live in or across this insn. */
1758 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1759 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1760 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1761 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1763 /* Now find out which pseudos are allocated to it, and update
1765 CLEAR_REG_SET (&pseudos_counted
);
1767 EXECUTE_IF_SET_IN_REG_SET
1768 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1772 EXECUTE_IF_SET_IN_REG_SET
1773 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1777 CLEAR_REG_SET (&pseudos_counted
);
1780 /* Vector of reload-numbers showing the order in which the reloads should
1782 static short reload_order
[MAX_RELOADS
];
1784 /* This is used to keep track of the spill regs used in one insn. */
1785 static HARD_REG_SET used_spill_regs_local
;
1787 /* We decided to spill hard register SPILLED, which has a size of
1788 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1789 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1790 update SPILL_COST/SPILL_ADD_COST. */
1793 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1795 int freq
= REG_FREQ (reg
);
1796 int r
= reg_renumber
[reg
];
1799 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1800 if (ira_conflicts_p
&& r
< 0)
1803 gcc_assert (r
>= 0);
1805 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1807 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1808 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1811 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1813 spill_add_cost
[r
] -= freq
;
1816 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1817 spill_cost
[r
+ nregs
] -= freq
;
1821 /* Find reload register to use for reload number ORDER. */
1824 find_reg (struct insn_chain
*chain
, int order
)
1826 int rnum
= reload_order
[order
];
1827 struct reload
*rl
= rld
+ rnum
;
1828 int best_cost
= INT_MAX
;
1830 unsigned int i
, j
, n
;
1832 HARD_REG_SET not_usable
;
1833 HARD_REG_SET used_by_other_reload
;
1834 reg_set_iterator rsi
;
1835 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1836 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1838 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1839 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1840 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1842 CLEAR_HARD_REG_SET (used_by_other_reload
);
1843 for (k
= 0; k
< order
; k
++)
1845 int other
= reload_order
[k
];
1847 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1848 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1849 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1852 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1854 #ifdef REG_ALLOC_ORDER
1855 unsigned int regno
= reg_alloc_order
[i
];
1857 unsigned int regno
= i
;
1860 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1861 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1862 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1864 int this_cost
= spill_cost
[regno
];
1866 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1868 for (j
= 1; j
< this_nregs
; j
++)
1870 this_cost
+= spill_add_cost
[regno
+ j
];
1871 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1872 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1878 if (ira_conflicts_p
)
1880 /* Ask IRA to find a better pseudo-register for
1882 for (n
= j
= 0; j
< this_nregs
; j
++)
1884 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1888 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1889 regno_pseudo_regs
[n
++] = r
;
1891 regno_pseudo_regs
[n
++] = -1;
1893 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1894 best_regno_pseudo_regs
,
1901 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1902 if (regno_pseudo_regs
[j
] < 0)
1909 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1911 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1913 if (this_cost
< best_cost
1914 /* Among registers with equal cost, prefer caller-saved ones, or
1915 use REG_ALLOC_ORDER if it is defined. */
1916 || (this_cost
== best_cost
1917 #ifdef REG_ALLOC_ORDER
1918 && (inv_reg_alloc_order
[regno
]
1919 < inv_reg_alloc_order
[best_reg
])
1921 && call_used_regs
[regno
]
1922 && ! call_used_regs
[best_reg
]
1927 best_cost
= this_cost
;
1935 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1937 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1938 rl
->regno
= best_reg
;
1940 EXECUTE_IF_SET_IN_REG_SET
1941 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1943 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1946 EXECUTE_IF_SET_IN_REG_SET
1947 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1949 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1952 for (i
= 0; i
< rl
->nregs
; i
++)
1954 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1955 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1956 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1957 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1962 /* Find more reload regs to satisfy the remaining need of an insn, which
1964 Do it by ascending class number, since otherwise a reg
1965 might be spilled for a big class and might fail to count
1966 for a smaller class even though it belongs to that class. */
1969 find_reload_regs (struct insn_chain
*chain
)
1973 /* In order to be certain of getting the registers we need,
1974 we must sort the reloads into order of increasing register class.
1975 Then our grabbing of reload registers will parallel the process
1976 that provided the reload registers. */
1977 for (i
= 0; i
< chain
->n_reloads
; i
++)
1979 /* Show whether this reload already has a hard reg. */
1980 if (chain
->rld
[i
].reg_rtx
)
1982 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1983 chain
->rld
[i
].regno
= regno
;
1985 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1988 chain
->rld
[i
].regno
= -1;
1989 reload_order
[i
] = i
;
1992 n_reloads
= chain
->n_reloads
;
1993 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1995 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1998 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2000 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2002 /* Compute the order of preference for hard registers to spill. */
2004 order_regs_for_reload (chain
);
2006 for (i
= 0; i
< n_reloads
; i
++)
2008 int r
= reload_order
[i
];
2010 /* Ignore reloads that got marked inoperative. */
2011 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2012 && ! rld
[r
].optional
2013 && rld
[r
].regno
== -1)
2014 if (! find_reg (chain
, i
))
2017 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2018 spill_failure (chain
->insn
, rld
[r
].rclass
);
2024 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2025 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2027 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2031 select_reload_regs (void)
2033 struct insn_chain
*chain
;
2035 /* Try to satisfy the needs for each insn. */
2036 for (chain
= insns_need_reload
; chain
!= 0;
2037 chain
= chain
->next_need_reload
)
2038 find_reload_regs (chain
);
2041 /* Delete all insns that were inserted by emit_caller_save_insns during
2044 delete_caller_save_insns (void)
2046 struct insn_chain
*c
= reload_insn_chain
;
2050 while (c
!= 0 && c
->is_caller_save_insn
)
2052 struct insn_chain
*next
= c
->next
;
2053 rtx_insn
*insn
= c
->insn
;
2055 if (c
== reload_insn_chain
)
2056 reload_insn_chain
= next
;
2060 next
->prev
= c
->prev
;
2062 c
->prev
->next
= next
;
2063 c
->next
= unused_insn_chains
;
2064 unused_insn_chains
= c
;
2072 /* Handle the failure to find a register to spill.
2073 INSN should be one of the insns which needed this particular spill reg. */
2076 spill_failure (rtx_insn
*insn
, enum reg_class rclass
)
2078 if (asm_noperands (PATTERN (insn
)) >= 0)
2079 error_for_asm (insn
, "can%'t find a register in class %qs while "
2080 "reloading %<asm%>",
2081 reg_class_names
[rclass
]);
2084 error ("unable to find a register to spill in class %qs",
2085 reg_class_names
[rclass
]);
2089 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2090 debug_reload_to_stream (dump_file
);
2092 fatal_insn ("this is the insn:", insn
);
2096 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2097 data that is dead in INSN. */
2100 delete_dead_insn (rtx_insn
*insn
)
2102 rtx_insn
*prev
= prev_active_insn (insn
);
2105 /* If the previous insn sets a register that dies in our insn make
2106 a note that we want to run DCE immediately after reload.
2108 We used to delete the previous insn & recurse, but that's wrong for
2109 block local equivalences. Instead of trying to figure out the exact
2110 circumstances where we can delete the potentially dead insns, just
2111 let DCE do the job. */
2112 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2113 && GET_CODE (PATTERN (prev
)) == SET
2114 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2115 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2116 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2117 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2120 SET_INSN_DELETED (insn
);
2123 /* Modify the home of pseudo-reg I.
2124 The new home is present in reg_renumber[I].
2126 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2127 or it may be -1, meaning there is none or it is not relevant.
2128 This is used so that all pseudos spilled from a given hard reg
2129 can share one stack slot. */
2132 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2134 /* When outputting an inline function, this can happen
2135 for a reg that isn't actually used. */
2136 if (regno_reg_rtx
[i
] == 0)
2139 /* If the reg got changed to a MEM at rtl-generation time,
2141 if (!REG_P (regno_reg_rtx
[i
]))
2144 /* Modify the reg-rtx to contain the new hard reg
2145 number or else to contain its pseudo reg number. */
2146 SET_REGNO (regno_reg_rtx
[i
],
2147 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2149 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2150 allocate a stack slot for it. */
2152 if (reg_renumber
[i
] < 0
2153 && REG_N_REFS (i
) > 0
2154 && reg_equiv_constant (i
) == 0
2155 && (reg_equiv_invariant (i
) == 0
2156 || reg_equiv_init (i
) == 0)
2157 && reg_equiv_memory_loc (i
) == 0)
2160 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2161 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2162 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2163 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2164 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2167 something_was_spilled
= true;
2169 if (ira_conflicts_p
)
2171 /* Mark the spill for IRA. */
2172 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2174 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2180 /* Each pseudo reg has an inherent size which comes from its own mode,
2181 and a total size which provides room for paradoxical subregs
2182 which refer to the pseudo reg in wider modes.
2184 We can use a slot already allocated if it provides both
2185 enough inherent space and enough total space.
2186 Otherwise, we allocate a new slot, making sure that it has no less
2187 inherent space, and no less total space, then the previous slot. */
2188 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2192 /* No known place to spill from => no slot to reuse. */
2193 x
= assign_stack_local (mode
, total_size
,
2194 min_align
> inherent_align
2195 || total_size
> inherent_size
? -1 : 0);
2199 /* Cancel the big-endian correction done in assign_stack_local.
2200 Get the address of the beginning of the slot. This is so we
2201 can do a big-endian correction unconditionally below. */
2202 if (BYTES_BIG_ENDIAN
)
2204 adjust
= inherent_size
- total_size
;
2207 = adjust_address_nv (x
, mode_for_size (total_size
2213 if (! dont_share_p
&& ira_conflicts_p
)
2214 /* Inform IRA about allocation a new stack slot. */
2215 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2218 /* Reuse a stack slot if possible. */
2219 else if (spill_stack_slot
[from_reg
] != 0
2220 && spill_stack_slot_width
[from_reg
] >= total_size
2221 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2223 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2224 x
= spill_stack_slot
[from_reg
];
2226 /* Allocate a bigger slot. */
2229 /* Compute maximum size needed, both for inherent size
2230 and for total size. */
2233 if (spill_stack_slot
[from_reg
])
2235 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2237 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2238 if (spill_stack_slot_width
[from_reg
] > total_size
)
2239 total_size
= spill_stack_slot_width
[from_reg
];
2240 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2241 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2244 /* Make a slot with that size. */
2245 x
= assign_stack_local (mode
, total_size
,
2246 min_align
> inherent_align
2247 || total_size
> inherent_size
? -1 : 0);
2250 /* Cancel the big-endian correction done in assign_stack_local.
2251 Get the address of the beginning of the slot. This is so we
2252 can do a big-endian correction unconditionally below. */
2253 if (BYTES_BIG_ENDIAN
)
2255 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2258 = adjust_address_nv (x
, mode_for_size (total_size
2264 spill_stack_slot
[from_reg
] = stack_slot
;
2265 spill_stack_slot_width
[from_reg
] = total_size
;
2268 /* On a big endian machine, the "address" of the slot
2269 is the address of the low part that fits its inherent mode. */
2270 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2271 adjust
+= (total_size
- inherent_size
);
2273 /* If we have any adjustment to make, or if the stack slot is the
2274 wrong mode, make a new stack slot. */
2275 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2277 /* Set all of the memory attributes as appropriate for a spill. */
2278 set_mem_attrs_for_spill (x
);
2280 /* Save the stack slot for later. */
2281 reg_equiv_memory_loc (i
) = x
;
2285 /* Mark the slots in regs_ever_live for the hard regs used by
2286 pseudo-reg number REGNO, accessed in MODE. */
2289 mark_home_live_1 (int regno
, machine_mode mode
)
2293 i
= reg_renumber
[regno
];
2296 lim
= end_hard_regno (mode
, i
);
2298 df_set_regs_ever_live (i
++, true);
2301 /* Mark the slots in regs_ever_live for the hard regs
2302 used by pseudo-reg number REGNO. */
2305 mark_home_live (int regno
)
2307 if (reg_renumber
[regno
] >= 0)
2308 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2311 /* This function handles the tracking of elimination offsets around branches.
2313 X is a piece of RTL being scanned.
2315 INSN is the insn that it came from, if any.
2317 INITIAL_P is nonzero if we are to set the offset to be the initial
2318 offset and zero if we are setting the offset of the label to be the
2322 set_label_offsets (rtx x
, rtx_insn
*insn
, int initial_p
)
2324 enum rtx_code code
= GET_CODE (x
);
2327 struct elim_table
*p
;
2332 if (LABEL_REF_NONLOCAL_P (x
))
2335 x
= LABEL_REF_LABEL (x
);
2337 /* ... fall through ... */
2340 /* If we know nothing about this label, set the desired offsets. Note
2341 that this sets the offset at a label to be the offset before a label
2342 if we don't know anything about the label. This is not correct for
2343 the label after a BARRIER, but is the best guess we can make. If
2344 we guessed wrong, we will suppress an elimination that might have
2345 been possible had we been able to guess correctly. */
2347 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2349 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2350 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2351 = (initial_p
? reg_eliminate
[i
].initial_offset
2352 : reg_eliminate
[i
].offset
);
2353 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2356 /* Otherwise, if this is the definition of a label and it is
2357 preceded by a BARRIER, set our offsets to the known offset of
2361 && (tem
= prev_nonnote_insn (insn
)) != 0
2363 set_offsets_for_label (insn
);
2365 /* If neither of the above cases is true, compare each offset
2366 with those previously recorded and suppress any eliminations
2367 where the offsets disagree. */
2369 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2370 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2371 != (initial_p
? reg_eliminate
[i
].initial_offset
2372 : reg_eliminate
[i
].offset
))
2373 reg_eliminate
[i
].can_eliminate
= 0;
2377 case JUMP_TABLE_DATA
:
2378 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2382 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2384 /* ... fall through ... */
2388 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2389 to indirectly and hence must have all eliminations at their
2391 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2392 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2393 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2399 /* Each of the labels in the parallel or address vector must be
2400 at their initial offsets. We want the first field for PARALLEL
2401 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2403 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2404 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2409 /* We only care about setting PC. If the source is not RETURN,
2410 IF_THEN_ELSE, or a label, disable any eliminations not at
2411 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2412 isn't one of those possibilities. For branches to a label,
2413 call ourselves recursively.
2415 Note that this can disable elimination unnecessarily when we have
2416 a non-local goto since it will look like a non-constant jump to
2417 someplace in the current function. This isn't a significant
2418 problem since such jumps will normally be when all elimination
2419 pairs are back to their initial offsets. */
2421 if (SET_DEST (x
) != pc_rtx
)
2424 switch (GET_CODE (SET_SRC (x
)))
2431 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2435 tem
= XEXP (SET_SRC (x
), 1);
2436 if (GET_CODE (tem
) == LABEL_REF
)
2437 set_label_offsets (LABEL_REF_LABEL (tem
), insn
, initial_p
);
2438 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2441 tem
= XEXP (SET_SRC (x
), 2);
2442 if (GET_CODE (tem
) == LABEL_REF
)
2443 set_label_offsets (LABEL_REF_LABEL (tem
), insn
, initial_p
);
2444 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2452 /* If we reach here, all eliminations must be at their initial
2453 offset because we are doing a jump to a variable address. */
2454 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2455 if (p
->offset
!= p
->initial_offset
)
2456 p
->can_eliminate
= 0;
2464 /* This function examines every reg that occurs in X and adjusts the
2465 costs for its elimination which are gathered by IRA. INSN is the
2466 insn in which X occurs. We do not recurse into MEM expressions. */
2469 note_reg_elim_costly (const_rtx x
, rtx insn
)
2471 subrtx_iterator::array_type array
;
2472 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2474 const_rtx x
= *iter
;
2476 iter
.skip_subrtxes ();
2478 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2479 && reg_equiv_init (REGNO (x
))
2480 && reg_equiv_invariant (REGNO (x
)))
2482 rtx t
= reg_equiv_invariant (REGNO (x
));
2483 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2484 int cost
= set_src_cost (new_rtx
, Pmode
,
2485 optimize_bb_for_speed_p (elim_bb
));
2486 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2489 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2494 /* Scan X and replace any eliminable registers (such as fp) with a
2495 replacement (such as sp), plus an offset.
2497 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2498 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2499 MEM, we are allowed to replace a sum of a register and the constant zero
2500 with the register, which we cannot do outside a MEM. In addition, we need
2501 to record the fact that a register is referenced outside a MEM.
2503 If INSN is an insn, it is the insn containing X. If we replace a REG
2504 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2505 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2506 the REG is being modified.
2508 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2509 That's used when we eliminate in expressions stored in notes.
2510 This means, do not set ref_outside_mem even if the reference
2513 If FOR_COSTS is true, we are being called before reload in order to
2514 estimate the costs of keeping registers with an equivalence unallocated.
2516 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2517 replacements done assuming all offsets are at their initial values. If
2518 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2519 encounter, return the actual location so that find_reloads will do
2520 the proper thing. */
2523 eliminate_regs_1 (rtx x
, machine_mode mem_mode
, rtx insn
,
2524 bool may_use_invariant
, bool for_costs
)
2526 enum rtx_code code
= GET_CODE (x
);
2527 struct elim_table
*ep
;
2534 if (! current_function_decl
)
2554 /* First handle the case where we encounter a bare register that
2555 is eliminable. Replace it with a PLUS. */
2556 if (regno
< FIRST_PSEUDO_REGISTER
)
2558 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2560 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2561 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2564 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2566 && reg_equiv_invariant (regno
))
2568 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2569 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2570 mem_mode
, insn
, true, for_costs
);
2571 /* There exists at least one use of REGNO that cannot be
2572 eliminated. Prevent the defining insn from being deleted. */
2573 reg_equiv_init (regno
) = NULL
;
2575 alter_reg (regno
, -1, true);
2579 /* You might think handling MINUS in a manner similar to PLUS is a
2580 good idea. It is not. It has been tried multiple times and every
2581 time the change has had to have been reverted.
2583 Other parts of reload know a PLUS is special (gen_reload for example)
2584 and require special code to handle code a reloaded PLUS operand.
2586 Also consider backends where the flags register is clobbered by a
2587 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2588 lea instruction comes to mind). If we try to reload a MINUS, we
2589 may kill the flags register that was holding a useful value.
2591 So, please before trying to handle MINUS, consider reload as a
2592 whole instead of this little section as well as the backend issues. */
2594 /* If this is the sum of an eliminable register and a constant, rework
2596 if (REG_P (XEXP (x
, 0))
2597 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2598 && CONSTANT_P (XEXP (x
, 1)))
2600 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2602 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2604 /* The only time we want to replace a PLUS with a REG (this
2605 occurs when the constant operand of the PLUS is the negative
2606 of the offset) is when we are inside a MEM. We won't want
2607 to do so at other times because that would change the
2608 structure of the insn in a way that reload can't handle.
2609 We special-case the commonest situation in
2610 eliminate_regs_in_insn, so just replace a PLUS with a
2611 PLUS here, unless inside a MEM. */
2612 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2613 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2616 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2617 plus_constant (Pmode
, XEXP (x
, 1),
2618 ep
->previous_offset
));
2621 /* If the register is not eliminable, we are done since the other
2622 operand is a constant. */
2626 /* If this is part of an address, we want to bring any constant to the
2627 outermost PLUS. We will do this by doing register replacement in
2628 our operands and seeing if a constant shows up in one of them.
2630 Note that there is no risk of modifying the structure of the insn,
2631 since we only get called for its operands, thus we are either
2632 modifying the address inside a MEM, or something like an address
2633 operand of a load-address insn. */
2636 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2638 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2641 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2643 /* If one side is a PLUS and the other side is a pseudo that
2644 didn't get a hard register but has a reg_equiv_constant,
2645 we must replace the constant here since it may no longer
2646 be in the position of any operand. */
2647 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2648 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2649 && reg_renumber
[REGNO (new1
)] < 0
2651 && reg_equiv_constant (REGNO (new1
)) != 0)
2652 new1
= reg_equiv_constant (REGNO (new1
));
2653 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2654 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2655 && reg_renumber
[REGNO (new0
)] < 0
2656 && reg_equiv_constant (REGNO (new0
)) != 0)
2657 new0
= reg_equiv_constant (REGNO (new0
));
2659 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2661 /* As above, if we are not inside a MEM we do not want to
2662 turn a PLUS into something else. We might try to do so here
2663 for an addition of 0 if we aren't optimizing. */
2664 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2665 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2673 /* If this is the product of an eliminable register and a
2674 constant, apply the distribute law and move the constant out
2675 so that we have (plus (mult ..) ..). This is needed in order
2676 to keep load-address insns valid. This case is pathological.
2677 We ignore the possibility of overflow here. */
2678 if (REG_P (XEXP (x
, 0))
2679 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2680 && CONST_INT_P (XEXP (x
, 1)))
2681 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2683 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2686 /* Refs inside notes or in DEBUG_INSNs don't count for
2688 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2689 || GET_CODE (insn
) == INSN_LIST
2690 || DEBUG_INSN_P (insn
))))
2691 ep
->ref_outside_mem
= 1;
2694 plus_constant (Pmode
,
2695 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2696 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2699 /* ... fall through ... */
2703 /* See comments before PLUS about handling MINUS. */
2705 case DIV
: case UDIV
:
2706 case MOD
: case UMOD
:
2707 case AND
: case IOR
: case XOR
:
2708 case ROTATERT
: case ROTATE
:
2709 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2711 case GE
: case GT
: case GEU
: case GTU
:
2712 case LE
: case LT
: case LEU
: case LTU
:
2714 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2716 rtx new1
= XEXP (x
, 1)
2717 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2720 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2721 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2726 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2729 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2731 if (new_rtx
!= XEXP (x
, 0))
2733 /* If this is a REG_DEAD note, it is not valid anymore.
2734 Using the eliminated version could result in creating a
2735 REG_DEAD note for the stack or frame pointer. */
2736 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2738 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2742 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2746 /* ... fall through ... */
2750 /* Now do eliminations in the rest of the chain. If this was
2751 an EXPR_LIST, this might result in allocating more memory than is
2752 strictly needed, but it simplifies the code. */
2755 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2757 if (new_rtx
!= XEXP (x
, 1))
2759 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2767 /* We do not support elimination of a register that is modified.
2768 elimination_effects has already make sure that this does not
2774 /* We do not support elimination of a register that is modified.
2775 elimination_effects has already make sure that this does not
2776 happen. The only remaining case we need to consider here is
2777 that the increment value may be an eliminable register. */
2778 if (GET_CODE (XEXP (x
, 1)) == PLUS
2779 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2781 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2782 insn
, true, for_costs
);
2784 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2785 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2786 gen_rtx_PLUS (GET_MODE (x
),
2787 XEXP (x
, 0), new_rtx
));
2791 case STRICT_LOW_PART
:
2793 case SIGN_EXTEND
: case ZERO_EXTEND
:
2794 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2795 case FLOAT
: case FIX
:
2796 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2805 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2807 if (new_rtx
!= XEXP (x
, 0))
2808 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2812 /* Similar to above processing, but preserve SUBREG_BYTE.
2813 Convert (subreg (mem)) to (mem) if not paradoxical.
2814 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2815 pseudo didn't get a hard reg, we must replace this with the
2816 eliminated version of the memory location because push_reload
2817 may do the replacement in certain circumstances. */
2818 if (REG_P (SUBREG_REG (x
))
2819 && !paradoxical_subreg_p (x
)
2821 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2823 new_rtx
= SUBREG_REG (x
);
2826 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2828 if (new_rtx
!= SUBREG_REG (x
))
2830 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2831 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2834 && ((x_size
< new_size
2835 #if WORD_REGISTER_OPERATIONS
2836 /* On these machines, combine can create rtl of the form
2837 (set (subreg:m1 (reg:m2 R) 0) ...)
2838 where m1 < m2, and expects something interesting to
2839 happen to the entire word. Moreover, it will use the
2840 (reg:m2 R) later, expecting all bits to be preserved.
2841 So if the number of words is the same, preserve the
2842 subreg so that push_reload can see it. */
2843 && ! ((x_size
- 1) / UNITS_PER_WORD
2844 == (new_size
-1 ) / UNITS_PER_WORD
)
2847 || x_size
== new_size
)
2849 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2851 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2857 /* Our only special processing is to pass the mode of the MEM to our
2858 recursive call and copy the flags. While we are here, handle this
2859 case more efficiently. */
2861 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2864 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2865 && !memory_address_p (GET_MODE (x
), new_rtx
))
2866 note_reg_elim_costly (XEXP (x
, 0), insn
);
2868 return replace_equiv_address_nv (x
, new_rtx
);
2871 /* Handle insn_list USE that a call to a pure function may generate. */
2872 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2874 if (new_rtx
!= XEXP (x
, 0))
2875 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2880 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2890 /* Process each of our operands recursively. If any have changed, make a
2892 fmt
= GET_RTX_FORMAT (code
);
2893 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2897 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2899 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2901 x
= shallow_copy_rtx (x
);
2904 XEXP (x
, i
) = new_rtx
;
2906 else if (*fmt
== 'E')
2909 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2911 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2913 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2915 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2919 x
= shallow_copy_rtx (x
);
2922 XVEC (x
, i
) = new_v
;
2925 XVECEXP (x
, i
, j
) = new_rtx
;
2934 eliminate_regs (rtx x
, machine_mode mem_mode
, rtx insn
)
2936 if (reg_eliminate
== NULL
)
2938 gcc_assert (targetm
.no_register_allocation
);
2941 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2944 /* Scan rtx X for modifications of elimination target registers. Update
2945 the table of eliminables to reflect the changed state. MEM_MODE is
2946 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2949 elimination_effects (rtx x
, machine_mode mem_mode
)
2951 enum rtx_code code
= GET_CODE (x
);
2952 struct elim_table
*ep
;
2974 /* First handle the case where we encounter a bare register that
2975 is eliminable. Replace it with a PLUS. */
2976 if (regno
< FIRST_PSEUDO_REGISTER
)
2978 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2980 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2983 ep
->ref_outside_mem
= 1;
2988 else if (reg_renumber
[regno
] < 0
2990 && reg_equiv_constant (regno
)
2991 && ! function_invariant_p (reg_equiv_constant (regno
)))
2992 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3001 /* If we modify the source of an elimination rule, disable it. */
3002 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3003 if (ep
->from_rtx
== XEXP (x
, 0))
3004 ep
->can_eliminate
= 0;
3006 /* If we modify the target of an elimination rule by adding a constant,
3007 update its offset. If we modify the target in any other way, we'll
3008 have to disable the rule as well. */
3009 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3010 if (ep
->to_rtx
== XEXP (x
, 0))
3012 int size
= GET_MODE_SIZE (mem_mode
);
3014 /* If more bytes than MEM_MODE are pushed, account for them. */
3015 #ifdef PUSH_ROUNDING
3016 if (ep
->to_rtx
== stack_pointer_rtx
)
3017 size
= PUSH_ROUNDING (size
);
3019 if (code
== PRE_DEC
|| code
== POST_DEC
)
3021 else if (code
== PRE_INC
|| code
== POST_INC
)
3023 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3025 if (GET_CODE (XEXP (x
, 1)) == PLUS
3026 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3027 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3028 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3030 ep
->can_eliminate
= 0;
3034 /* These two aren't unary operators. */
3035 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3038 /* Fall through to generic unary operation case. */
3039 case STRICT_LOW_PART
:
3041 case SIGN_EXTEND
: case ZERO_EXTEND
:
3042 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3043 case FLOAT
: case FIX
:
3044 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3053 elimination_effects (XEXP (x
, 0), mem_mode
);
3057 if (REG_P (SUBREG_REG (x
))
3058 && (GET_MODE_SIZE (GET_MODE (x
))
3059 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3061 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3064 elimination_effects (SUBREG_REG (x
), mem_mode
);
3068 /* If using a register that is the source of an eliminate we still
3069 think can be performed, note it cannot be performed since we don't
3070 know how this register is used. */
3071 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3072 if (ep
->from_rtx
== XEXP (x
, 0))
3073 ep
->can_eliminate
= 0;
3075 elimination_effects (XEXP (x
, 0), mem_mode
);
3079 /* If clobbering a register that is the replacement register for an
3080 elimination we still think can be performed, note that it cannot
3081 be performed. Otherwise, we need not be concerned about it. */
3082 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3083 if (ep
->to_rtx
== XEXP (x
, 0))
3084 ep
->can_eliminate
= 0;
3086 elimination_effects (XEXP (x
, 0), mem_mode
);
3090 /* Check for setting a register that we know about. */
3091 if (REG_P (SET_DEST (x
)))
3093 /* See if this is setting the replacement register for an
3096 If DEST is the hard frame pointer, we do nothing because we
3097 assume that all assignments to the frame pointer are for
3098 non-local gotos and are being done at a time when they are valid
3099 and do not disturb anything else. Some machines want to
3100 eliminate a fake argument pointer (or even a fake frame pointer)
3101 with either the real frame or the stack pointer. Assignments to
3102 the hard frame pointer must not prevent this elimination. */
3104 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3106 if (ep
->to_rtx
== SET_DEST (x
)
3107 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3109 /* If it is being incremented, adjust the offset. Otherwise,
3110 this elimination can't be done. */
3111 rtx src
= SET_SRC (x
);
3113 if (GET_CODE (src
) == PLUS
3114 && XEXP (src
, 0) == SET_DEST (x
)
3115 && CONST_INT_P (XEXP (src
, 1)))
3116 ep
->offset
-= INTVAL (XEXP (src
, 1));
3118 ep
->can_eliminate
= 0;
3122 elimination_effects (SET_DEST (x
), VOIDmode
);
3123 elimination_effects (SET_SRC (x
), VOIDmode
);
3127 /* Our only special processing is to pass the mode of the MEM to our
3129 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3136 fmt
= GET_RTX_FORMAT (code
);
3137 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3140 elimination_effects (XEXP (x
, i
), mem_mode
);
3141 else if (*fmt
== 'E')
3142 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3143 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3147 /* Descend through rtx X and verify that no references to eliminable registers
3148 remain. If any do remain, mark the involved register as not
3152 check_eliminable_occurrences (rtx x
)
3161 code
= GET_CODE (x
);
3163 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3165 struct elim_table
*ep
;
3167 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3168 if (ep
->from_rtx
== x
)
3169 ep
->can_eliminate
= 0;
3173 fmt
= GET_RTX_FORMAT (code
);
3174 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3177 check_eliminable_occurrences (XEXP (x
, i
));
3178 else if (*fmt
== 'E')
3181 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3182 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3187 /* Scan INSN and eliminate all eliminable registers in it.
3189 If REPLACE is nonzero, do the replacement destructively. Also
3190 delete the insn as dead it if it is setting an eliminable register.
3192 If REPLACE is zero, do all our allocations in reload_obstack.
3194 If no eliminations were done and this insn doesn't require any elimination
3195 processing (these are not identical conditions: it might be updating sp,
3196 but not referencing fp; this needs to be seen during reload_as_needed so
3197 that the offset between fp and sp can be taken into consideration), zero
3198 is returned. Otherwise, 1 is returned. */
3201 eliminate_regs_in_insn (rtx_insn
*insn
, int replace
)
3203 int icode
= recog_memoized (insn
);
3204 rtx old_body
= PATTERN (insn
);
3205 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3206 rtx old_set
= single_set (insn
);
3210 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3211 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3212 struct elim_table
*ep
;
3213 rtx plus_src
, plus_cst_src
;
3215 if (! insn_is_asm
&& icode
< 0)
3217 gcc_assert (DEBUG_INSN_P (insn
)
3218 || GET_CODE (PATTERN (insn
)) == USE
3219 || GET_CODE (PATTERN (insn
)) == CLOBBER
3220 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3221 if (DEBUG_INSN_P (insn
))
3222 INSN_VAR_LOCATION_LOC (insn
)
3223 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3227 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3228 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3230 /* Check for setting an eliminable register. */
3231 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3232 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3234 /* If this is setting the frame pointer register to the
3235 hardware frame pointer register and this is an elimination
3236 that will be done (tested above), this insn is really
3237 adjusting the frame pointer downward to compensate for
3238 the adjustment done before a nonlocal goto. */
3239 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3240 && ep
->from
== FRAME_POINTER_REGNUM
3241 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3243 rtx base
= SET_SRC (old_set
);
3244 rtx_insn
*base_insn
= insn
;
3245 HOST_WIDE_INT offset
= 0;
3247 while (base
!= ep
->to_rtx
)
3249 rtx_insn
*prev_insn
;
3252 if (GET_CODE (base
) == PLUS
3253 && CONST_INT_P (XEXP (base
, 1)))
3255 offset
+= INTVAL (XEXP (base
, 1));
3256 base
= XEXP (base
, 0);
3258 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3259 && (prev_set
= single_set (prev_insn
)) != 0
3260 && rtx_equal_p (SET_DEST (prev_set
), base
))
3262 base
= SET_SRC (prev_set
);
3263 base_insn
= prev_insn
;
3269 if (base
== ep
->to_rtx
)
3271 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3272 offset
- ep
->offset
);
3274 new_body
= old_body
;
3277 new_body
= copy_insn (old_body
);
3278 if (REG_NOTES (insn
))
3279 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3281 PATTERN (insn
) = new_body
;
3282 old_set
= single_set (insn
);
3284 /* First see if this insn remains valid when we
3285 make the change. If not, keep the INSN_CODE
3286 the same and let reload fit it up. */
3287 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3288 validate_change (insn
, &SET_DEST (old_set
),
3290 if (! apply_change_group ())
3292 SET_SRC (old_set
) = src
;
3293 SET_DEST (old_set
) = ep
->to_rtx
;
3301 /* In this case this insn isn't serving a useful purpose. We
3302 will delete it in reload_as_needed once we know that this
3303 elimination is, in fact, being done.
3305 If REPLACE isn't set, we can't delete this insn, but needn't
3306 process it since it won't be used unless something changes. */
3309 delete_dead_insn (insn
);
3317 /* We allow one special case which happens to work on all machines we
3318 currently support: a single set with the source or a REG_EQUAL
3319 note being a PLUS of an eliminable register and a constant. */
3320 plus_src
= plus_cst_src
= 0;
3321 if (old_set
&& REG_P (SET_DEST (old_set
)))
3323 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3324 plus_src
= SET_SRC (old_set
);
3325 /* First see if the source is of the form (plus (...) CST). */
3327 && CONST_INT_P (XEXP (plus_src
, 1)))
3328 plus_cst_src
= plus_src
;
3329 else if (REG_P (SET_SRC (old_set
))
3332 /* Otherwise, see if we have a REG_EQUAL note of the form
3333 (plus (...) CST). */
3335 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3337 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3338 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3339 && GET_CODE (XEXP (links
, 0)) == PLUS
3340 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3342 plus_cst_src
= XEXP (links
, 0);
3348 /* Check that the first operand of the PLUS is a hard reg or
3349 the lowpart subreg of one. */
3352 rtx reg
= XEXP (plus_cst_src
, 0);
3353 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3354 reg
= SUBREG_REG (reg
);
3356 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3362 rtx reg
= XEXP (plus_cst_src
, 0);
3363 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3365 if (GET_CODE (reg
) == SUBREG
)
3366 reg
= SUBREG_REG (reg
);
3368 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3369 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3371 rtx to_rtx
= ep
->to_rtx
;
3372 offset
+= ep
->offset
;
3373 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3375 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3376 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3378 /* If we have a nonzero offset, and the source is already
3379 a simple REG, the following transformation would
3380 increase the cost of the insn by replacing a simple REG
3381 with (plus (reg sp) CST). So try only when we already
3382 had a PLUS before. */
3383 if (offset
== 0 || plus_src
)
3385 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3388 new_body
= old_body
;
3391 new_body
= copy_insn (old_body
);
3392 if (REG_NOTES (insn
))
3393 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3395 PATTERN (insn
) = new_body
;
3396 old_set
= single_set (insn
);
3398 /* First see if this insn remains valid when we make the
3399 change. If not, try to replace the whole pattern with
3400 a simple set (this may help if the original insn was a
3401 PARALLEL that was only recognized as single_set due to
3402 REG_UNUSED notes). If this isn't valid either, keep
3403 the INSN_CODE the same and let reload fix it up. */
3404 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3406 rtx new_pat
= gen_rtx_SET (SET_DEST (old_set
), new_src
);
3408 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3409 SET_SRC (old_set
) = new_src
;
3416 /* This can't have an effect on elimination offsets, so skip right
3422 /* Determine the effects of this insn on elimination offsets. */
3423 elimination_effects (old_body
, VOIDmode
);
3425 /* Eliminate all eliminable registers occurring in operands that
3426 can be handled by reload. */
3427 extract_insn (insn
);
3428 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3430 orig_operand
[i
] = recog_data
.operand
[i
];
3431 substed_operand
[i
] = recog_data
.operand
[i
];
3433 /* For an asm statement, every operand is eliminable. */
3434 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3436 bool is_set_src
, in_plus
;
3438 /* Check for setting a register that we know about. */
3439 if (recog_data
.operand_type
[i
] != OP_IN
3440 && REG_P (orig_operand
[i
]))
3442 /* If we are assigning to a register that can be eliminated, it
3443 must be as part of a PARALLEL, since the code above handles
3444 single SETs. We must indicate that we can no longer
3445 eliminate this reg. */
3446 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3448 if (ep
->from_rtx
== orig_operand
[i
])
3449 ep
->can_eliminate
= 0;
3452 /* Companion to the above plus substitution, we can allow
3453 invariants as the source of a plain move. */
3456 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3460 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3461 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3465 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3466 replace
? insn
: NULL_RTX
,
3467 is_set_src
|| in_plus
, false);
3468 if (substed_operand
[i
] != orig_operand
[i
])
3470 /* Terminate the search in check_eliminable_occurrences at
3472 *recog_data
.operand_loc
[i
] = 0;
3474 /* If an output operand changed from a REG to a MEM and INSN is an
3475 insn, write a CLOBBER insn. */
3476 if (recog_data
.operand_type
[i
] != OP_IN
3477 && REG_P (orig_operand
[i
])
3478 && MEM_P (substed_operand
[i
])
3480 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3484 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3485 *recog_data
.dup_loc
[i
]
3486 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3488 /* If any eliminable remain, they aren't eliminable anymore. */
3489 check_eliminable_occurrences (old_body
);
3491 /* Substitute the operands; the new values are in the substed_operand
3493 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3494 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3495 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3496 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3498 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3499 re-recognize the insn. We do this in case we had a simple addition
3500 but now can do this as a load-address. This saves an insn in this
3502 If re-recognition fails, the old insn code number will still be used,
3503 and some register operands may have changed into PLUS expressions.
3504 These will be handled by find_reloads by loading them into a register
3509 /* If we aren't replacing things permanently and we changed something,
3510 make another copy to ensure that all the RTL is new. Otherwise
3511 things can go wrong if find_reload swaps commutative operands
3512 and one is inside RTL that has been copied while the other is not. */
3513 new_body
= old_body
;
3516 new_body
= copy_insn (old_body
);
3517 if (REG_NOTES (insn
))
3518 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3520 PATTERN (insn
) = new_body
;
3522 /* If we had a move insn but now we don't, rerecognize it. This will
3523 cause spurious re-recognition if the old move had a PARALLEL since
3524 the new one still will, but we can't call single_set without
3525 having put NEW_BODY into the insn and the re-recognition won't
3526 hurt in this rare case. */
3527 /* ??? Why this huge if statement - why don't we just rerecognize the
3531 && ((REG_P (SET_SRC (old_set
))
3532 && (GET_CODE (new_body
) != SET
3533 || !REG_P (SET_SRC (new_body
))))
3534 /* If this was a load from or store to memory, compare
3535 the MEM in recog_data.operand to the one in the insn.
3536 If they are not equal, then rerecognize the insn. */
3538 && ((MEM_P (SET_SRC (old_set
))
3539 && SET_SRC (old_set
) != recog_data
.operand
[1])
3540 || (MEM_P (SET_DEST (old_set
))
3541 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3542 /* If this was an add insn before, rerecognize. */
3543 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3545 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3547 INSN_CODE (insn
) = new_icode
;
3551 /* Restore the old body. If there were any changes to it, we made a copy
3552 of it while the changes were still in place, so we'll correctly return
3553 a modified insn below. */
3556 /* Restore the old body. */
3557 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3558 /* Restoring a top-level match_parallel would clobber the new_body
3559 we installed in the insn. */
3560 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3561 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3562 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3563 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3566 /* Update all elimination pairs to reflect the status after the current
3567 insn. The changes we make were determined by the earlier call to
3568 elimination_effects.
3570 We also detect cases where register elimination cannot be done,
3571 namely, if a register would be both changed and referenced outside a MEM
3572 in the resulting insn since such an insn is often undefined and, even if
3573 not, we cannot know what meaning will be given to it. Note that it is
3574 valid to have a register used in an address in an insn that changes it
3575 (presumably with a pre- or post-increment or decrement).
3577 If anything changes, return nonzero. */
3579 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3581 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3582 ep
->can_eliminate
= 0;
3584 ep
->ref_outside_mem
= 0;
3586 if (ep
->previous_offset
!= ep
->offset
)
3591 /* If we changed something, perform elimination in REG_NOTES. This is
3592 needed even when REPLACE is zero because a REG_DEAD note might refer
3593 to a register that we eliminate and could cause a different number
3594 of spill registers to be needed in the final reload pass than in
3596 if (val
&& REG_NOTES (insn
) != 0)
3598 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3604 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3605 register allocator. INSN is the instruction we need to examine, we perform
3606 eliminations in its operands and record cases where eliminating a reg with
3607 an invariant equivalence would add extra cost. */
3609 #pragma GCC diagnostic push
3610 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3612 elimination_costs_in_insn (rtx_insn
*insn
)
3614 int icode
= recog_memoized (insn
);
3615 rtx old_body
= PATTERN (insn
);
3616 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3617 rtx old_set
= single_set (insn
);
3619 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3620 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3621 struct elim_table
*ep
;
3622 rtx plus_src
, plus_cst_src
;
3625 if (! insn_is_asm
&& icode
< 0)
3627 gcc_assert (DEBUG_INSN_P (insn
)
3628 || GET_CODE (PATTERN (insn
)) == USE
3629 || GET_CODE (PATTERN (insn
)) == CLOBBER
3630 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3634 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3635 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3637 /* Check for setting an eliminable register. */
3638 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3639 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3643 /* We allow one special case which happens to work on all machines we
3644 currently support: a single set with the source or a REG_EQUAL
3645 note being a PLUS of an eliminable register and a constant. */
3646 plus_src
= plus_cst_src
= 0;
3648 if (old_set
&& REG_P (SET_DEST (old_set
)))
3651 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3652 plus_src
= SET_SRC (old_set
);
3653 /* First see if the source is of the form (plus (...) CST). */
3655 && CONST_INT_P (XEXP (plus_src
, 1)))
3656 plus_cst_src
= plus_src
;
3657 else if (REG_P (SET_SRC (old_set
))
3660 /* Otherwise, see if we have a REG_EQUAL note of the form
3661 (plus (...) CST). */
3663 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3665 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3666 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3667 && GET_CODE (XEXP (links
, 0)) == PLUS
3668 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3670 plus_cst_src
= XEXP (links
, 0);
3677 /* Determine the effects of this insn on elimination offsets. */
3678 elimination_effects (old_body
, VOIDmode
);
3680 /* Eliminate all eliminable registers occurring in operands that
3681 can be handled by reload. */
3682 extract_insn (insn
);
3683 int n_dups
= recog_data
.n_dups
;
3684 for (i
= 0; i
< n_dups
; i
++)
3685 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3687 int n_operands
= recog_data
.n_operands
;
3688 for (i
= 0; i
< n_operands
; i
++)
3690 orig_operand
[i
] = recog_data
.operand
[i
];
3692 /* For an asm statement, every operand is eliminable. */
3693 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3695 bool is_set_src
, in_plus
;
3697 /* Check for setting a register that we know about. */
3698 if (recog_data
.operand_type
[i
] != OP_IN
3699 && REG_P (orig_operand
[i
]))
3701 /* If we are assigning to a register that can be eliminated, it
3702 must be as part of a PARALLEL, since the code above handles
3703 single SETs. We must indicate that we can no longer
3704 eliminate this reg. */
3705 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3707 if (ep
->from_rtx
== orig_operand
[i
])
3708 ep
->can_eliminate
= 0;
3711 /* Companion to the above plus substitution, we can allow
3712 invariants as the source of a plain move. */
3714 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3716 if (is_set_src
&& !sets_reg_p
)
3717 note_reg_elim_costly (SET_SRC (old_set
), insn
);
3719 if (plus_src
&& sets_reg_p
3720 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3721 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3724 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3726 is_set_src
|| in_plus
, true);
3727 /* Terminate the search in check_eliminable_occurrences at
3729 *recog_data
.operand_loc
[i
] = 0;
3733 for (i
= 0; i
< n_dups
; i
++)
3734 *recog_data
.dup_loc
[i
]
3735 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3737 /* If any eliminable remain, they aren't eliminable anymore. */
3738 check_eliminable_occurrences (old_body
);
3740 /* Restore the old body. */
3741 for (i
= 0; i
< n_operands
; i
++)
3742 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3743 for (i
= 0; i
< n_dups
; i
++)
3744 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3746 /* Update all elimination pairs to reflect the status after the current
3747 insn. The changes we make were determined by the earlier call to
3748 elimination_effects. */
3750 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3752 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3753 ep
->can_eliminate
= 0;
3755 ep
->ref_outside_mem
= 0;
3760 #pragma GCC diagnostic pop
3762 /* Loop through all elimination pairs.
3763 Recalculate the number not at initial offset.
3765 Compute the maximum offset (minimum offset if the stack does not
3766 grow downward) for each elimination pair. */
3769 update_eliminable_offsets (void)
3771 struct elim_table
*ep
;
3773 num_not_at_initial_offset
= 0;
3774 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3776 ep
->previous_offset
= ep
->offset
;
3777 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3778 num_not_at_initial_offset
++;
3782 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3783 replacement we currently believe is valid, mark it as not eliminable if X
3784 modifies DEST in any way other than by adding a constant integer to it.
3786 If DEST is the frame pointer, we do nothing because we assume that
3787 all assignments to the hard frame pointer are nonlocal gotos and are being
3788 done at a time when they are valid and do not disturb anything else.
3789 Some machines want to eliminate a fake argument pointer with either the
3790 frame or stack pointer. Assignments to the hard frame pointer must not
3791 prevent this elimination.
3793 Called via note_stores from reload before starting its passes to scan
3794 the insns of the function. */
3797 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3801 /* A SUBREG of a hard register here is just changing its mode. We should
3802 not see a SUBREG of an eliminable hard register, but check just in
3804 if (GET_CODE (dest
) == SUBREG
)
3805 dest
= SUBREG_REG (dest
);
3807 if (dest
== hard_frame_pointer_rtx
)
3810 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3811 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3812 && (GET_CODE (x
) != SET
3813 || GET_CODE (SET_SRC (x
)) != PLUS
3814 || XEXP (SET_SRC (x
), 0) != dest
3815 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3817 reg_eliminate
[i
].can_eliminate_previous
3818 = reg_eliminate
[i
].can_eliminate
= 0;
3823 /* Verify that the initial elimination offsets did not change since the
3824 last call to set_initial_elim_offsets. This is used to catch cases
3825 where something illegal happened during reload_as_needed that could
3826 cause incorrect code to be generated if we did not check for it. */
3829 verify_initial_elim_offsets (void)
3833 if (!num_eliminable
)
3836 #ifdef ELIMINABLE_REGS
3838 struct elim_table
*ep
;
3840 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3842 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3843 if (t
!= ep
->initial_offset
)
3848 INITIAL_FRAME_POINTER_OFFSET (t
);
3849 if (t
!= reg_eliminate
[0].initial_offset
)
3856 /* Reset all offsets on eliminable registers to their initial values. */
3859 set_initial_elim_offsets (void)
3861 struct elim_table
*ep
= reg_eliminate
;
3863 #ifdef ELIMINABLE_REGS
3864 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3866 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3867 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3870 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3871 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3874 num_not_at_initial_offset
= 0;
3877 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3880 set_initial_eh_label_offset (rtx label
)
3882 set_label_offsets (label
, NULL
, 1);
3885 /* Initialize the known label offsets.
3886 Set a known offset for each forced label to be at the initial offset
3887 of each elimination. We do this because we assume that all
3888 computed jumps occur from a location where each elimination is
3889 at its initial offset.
3890 For all other labels, show that we don't know the offsets. */
3893 set_initial_label_offsets (void)
3895 memset (offsets_known_at
, 0, num_labels
);
3897 for (rtx_insn_list
*x
= forced_labels
; x
; x
= x
->next ())
3899 set_label_offsets (x
->insn (), NULL
, 1);
3901 for (rtx_insn_list
*x
= nonlocal_goto_handler_labels
; x
; x
= x
->next ())
3903 set_label_offsets (x
->insn (), NULL
, 1);
3905 for_each_eh_label (set_initial_eh_label_offset
);
3908 /* Set all elimination offsets to the known values for the code label given
3912 set_offsets_for_label (rtx_insn
*insn
)
3915 int label_nr
= CODE_LABEL_NUMBER (insn
);
3916 struct elim_table
*ep
;
3918 num_not_at_initial_offset
= 0;
3919 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3921 ep
->offset
= ep
->previous_offset
3922 = offsets_at
[label_nr
- first_label_num
][i
];
3923 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3924 num_not_at_initial_offset
++;
3928 /* See if anything that happened changes which eliminations are valid.
3929 For example, on the SPARC, whether or not the frame pointer can
3930 be eliminated can depend on what registers have been used. We need
3931 not check some conditions again (such as flag_omit_frame_pointer)
3932 since they can't have changed. */
3935 update_eliminables (HARD_REG_SET
*pset
)
3937 int previous_frame_pointer_needed
= frame_pointer_needed
;
3938 struct elim_table
*ep
;
3940 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3941 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3942 && targetm
.frame_pointer_required ())
3943 #ifdef ELIMINABLE_REGS
3944 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3947 ep
->can_eliminate
= 0;
3949 /* Look for the case where we have discovered that we can't replace
3950 register A with register B and that means that we will now be
3951 trying to replace register A with register C. This means we can
3952 no longer replace register C with register B and we need to disable
3953 such an elimination, if it exists. This occurs often with A == ap,
3954 B == sp, and C == fp. */
3956 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3958 struct elim_table
*op
;
3961 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3963 /* Find the current elimination for ep->from, if there is a
3965 for (op
= reg_eliminate
;
3966 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3967 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3973 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3975 for (op
= reg_eliminate
;
3976 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3977 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3978 op
->can_eliminate
= 0;
3982 /* See if any registers that we thought we could eliminate the previous
3983 time are no longer eliminable. If so, something has changed and we
3984 must spill the register. Also, recompute the number of eliminable
3985 registers and see if the frame pointer is needed; it is if there is
3986 no elimination of the frame pointer that we can perform. */
3988 frame_pointer_needed
= 1;
3989 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3991 if (ep
->can_eliminate
3992 && ep
->from
== FRAME_POINTER_REGNUM
3993 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3994 && (! SUPPORTS_STACK_ALIGNMENT
3995 || ! crtl
->stack_realign_needed
))
3996 frame_pointer_needed
= 0;
3998 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4000 ep
->can_eliminate_previous
= 0;
4001 SET_HARD_REG_BIT (*pset
, ep
->from
);
4006 /* If we didn't need a frame pointer last time, but we do now, spill
4007 the hard frame pointer. */
4008 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4009 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4012 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4013 Return true iff a register was spilled. */
4016 update_eliminables_and_spill (void)
4019 bool did_spill
= false;
4020 HARD_REG_SET to_spill
;
4021 CLEAR_HARD_REG_SET (to_spill
);
4022 update_eliminables (&to_spill
);
4023 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
4025 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4026 if (TEST_HARD_REG_BIT (to_spill
, i
))
4028 spill_hard_reg (i
, 1);
4031 /* Regardless of the state of spills, if we previously had
4032 a register that we thought we could eliminate, but now can
4033 not eliminate, we must run another pass.
4035 Consider pseudos which have an entry in reg_equiv_* which
4036 reference an eliminable register. We must make another pass
4037 to update reg_equiv_* so that we do not substitute in the
4038 old value from when we thought the elimination could be
4044 /* Return true if X is used as the target register of an elimination. */
4047 elimination_target_reg_p (rtx x
)
4049 struct elim_table
*ep
;
4051 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4052 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4058 /* Initialize the table of registers to eliminate.
4059 Pre-condition: global flag frame_pointer_needed has been set before
4060 calling this function. */
4063 init_elim_table (void)
4065 struct elim_table
*ep
;
4066 #ifdef ELIMINABLE_REGS
4067 const struct elim_table_1
*ep1
;
4071 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4075 #ifdef ELIMINABLE_REGS
4076 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4077 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4079 ep
->from
= ep1
->from
;
4081 ep
->can_eliminate
= ep
->can_eliminate_previous
4082 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4083 && ! (ep
->to
== STACK_POINTER_REGNUM
4084 && frame_pointer_needed
4085 && (! SUPPORTS_STACK_ALIGNMENT
4086 || ! stack_realign_fp
)));
4089 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4090 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4091 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4092 = ! frame_pointer_needed
;
4095 /* Count the number of eliminable registers and build the FROM and TO
4096 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4097 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4098 We depend on this. */
4099 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4101 num_eliminable
+= ep
->can_eliminate
;
4102 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4103 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4107 /* Find all the pseudo registers that didn't get hard regs
4108 but do have known equivalent constants or memory slots.
4109 These include parameters (known equivalent to parameter slots)
4110 and cse'd or loop-moved constant memory addresses.
4112 Record constant equivalents in reg_equiv_constant
4113 so they will be substituted by find_reloads.
4114 Record memory equivalents in reg_mem_equiv so they can
4115 be substituted eventually by altering the REG-rtx's. */
4118 init_eliminable_invariants (rtx_insn
*first
, bool do_subregs
)
4125 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4127 reg_max_ref_width
= NULL
;
4129 num_eliminable_invariants
= 0;
4131 first_label_num
= get_first_label_num ();
4132 num_labels
= max_label_num () - first_label_num
;
4134 /* Allocate the tables used to store offset information at labels. */
4135 offsets_known_at
= XNEWVEC (char, num_labels
);
4136 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4138 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4139 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4140 find largest such for each pseudo. FIRST is the head of the insn
4143 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4145 rtx set
= single_set (insn
);
4147 /* We may introduce USEs that we want to remove at the end, so
4148 we'll mark them with QImode. Make sure there are no
4149 previously-marked insns left by say regmove. */
4150 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4151 && GET_MODE (insn
) != VOIDmode
)
4152 PUT_MODE (insn
, VOIDmode
);
4154 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4155 scan_paradoxical_subregs (PATTERN (insn
));
4157 if (set
!= 0 && REG_P (SET_DEST (set
)))
4159 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4165 i
= REGNO (SET_DEST (set
));
4168 if (i
<= LAST_VIRTUAL_REGISTER
)
4171 /* If flag_pic and we have constant, verify it's legitimate. */
4173 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4175 /* It can happen that a REG_EQUIV note contains a MEM
4176 that is not a legitimate memory operand. As later
4177 stages of reload assume that all addresses found
4178 in the reg_equiv_* arrays were originally legitimate,
4179 we ignore such REG_EQUIV notes. */
4180 if (memory_operand (x
, VOIDmode
))
4182 /* Always unshare the equivalence, so we can
4183 substitute into this insn without touching the
4185 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4187 else if (function_invariant_p (x
))
4191 mode
= GET_MODE (SET_DEST (set
));
4192 if (GET_CODE (x
) == PLUS
)
4194 /* This is PLUS of frame pointer and a constant,
4195 and might be shared. Unshare it. */
4196 reg_equiv_invariant (i
) = copy_rtx (x
);
4197 num_eliminable_invariants
++;
4199 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4201 reg_equiv_invariant (i
) = x
;
4202 num_eliminable_invariants
++;
4204 else if (targetm
.legitimate_constant_p (mode
, x
))
4205 reg_equiv_constant (i
) = x
;
4208 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4209 if (! reg_equiv_memory_loc (i
))
4210 reg_equiv_init (i
) = NULL
;
4215 reg_equiv_init (i
) = NULL
;
4220 reg_equiv_init (i
) = NULL
;
4225 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4226 if (reg_equiv_init (i
))
4228 fprintf (dump_file
, "init_insns for %u: ", i
);
4229 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4230 fprintf (dump_file
, "\n");
4234 /* Indicate that we no longer have known memory locations or constants.
4235 Free all data involved in tracking these. */
4238 free_reg_equiv (void)
4242 free (offsets_known_at
);
4245 offsets_known_at
= 0;
4247 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4248 if (reg_equiv_alt_mem_list (i
))
4249 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4250 vec_free (reg_equivs
);
4253 /* Kick all pseudos out of hard register REGNO.
4255 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4256 because we found we can't eliminate some register. In the case, no pseudos
4257 are allowed to be in the register, even if they are only in a block that
4258 doesn't require spill registers, unlike the case when we are spilling this
4259 hard reg to produce another spill register.
4261 Return nonzero if any pseudos needed to be kicked out. */
4264 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4270 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4271 df_set_regs_ever_live (regno
, true);
4274 /* Spill every pseudo reg that was allocated to this reg
4275 or to something that overlaps this reg. */
4277 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4278 if (reg_renumber
[i
] >= 0
4279 && (unsigned int) reg_renumber
[i
] <= regno
4280 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4281 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4284 /* After find_reload_regs has been run for all insn that need reloads,
4285 and/or spill_hard_regs was called, this function is used to actually
4286 spill pseudo registers and try to reallocate them. It also sets up the
4287 spill_regs array for use by choose_reload_regs. */
4290 finish_spills (int global
)
4292 struct insn_chain
*chain
;
4293 int something_changed
= 0;
4295 reg_set_iterator rsi
;
4297 /* Build the spill_regs array for the function. */
4298 /* If there are some registers still to eliminate and one of the spill regs
4299 wasn't ever used before, additional stack space may have to be
4300 allocated to store this register. Thus, we may have changed the offset
4301 between the stack and frame pointers, so mark that something has changed.
4303 One might think that we need only set VAL to 1 if this is a call-used
4304 register. However, the set of registers that must be saved by the
4305 prologue is not identical to the call-used set. For example, the
4306 register used by the call insn for the return PC is a call-used register,
4307 but must be saved by the prologue. */
4310 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4311 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4313 spill_reg_order
[i
] = n_spills
;
4314 spill_regs
[n_spills
++] = i
;
4315 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4316 something_changed
= 1;
4317 df_set_regs_ever_live (i
, true);
4320 spill_reg_order
[i
] = -1;
4322 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4323 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4325 /* Record the current hard register the pseudo is allocated to
4326 in pseudo_previous_regs so we avoid reallocating it to the
4327 same hard reg in a later pass. */
4328 gcc_assert (reg_renumber
[i
] >= 0);
4330 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4331 /* Mark it as no longer having a hard register home. */
4332 reg_renumber
[i
] = -1;
4333 if (ira_conflicts_p
)
4334 /* Inform IRA about the change. */
4335 ira_mark_allocation_change (i
);
4336 /* We will need to scan everything again. */
4337 something_changed
= 1;
4340 /* Retry global register allocation if possible. */
4341 if (global
&& ira_conflicts_p
)
4345 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4346 /* For every insn that needs reloads, set the registers used as spill
4347 regs in pseudo_forbidden_regs for every pseudo live across the
4349 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4351 EXECUTE_IF_SET_IN_REG_SET
4352 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4354 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4355 chain
->used_spill_regs
);
4357 EXECUTE_IF_SET_IN_REG_SET
4358 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4360 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4361 chain
->used_spill_regs
);
4365 /* Retry allocating the pseudos spilled in IRA and the
4366 reload. For each reg, merge the various reg sets that
4367 indicate which hard regs can't be used, and call
4368 ira_reassign_pseudos. */
4369 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4370 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4372 if (reg_renumber
[i
] < 0)
4373 temp_pseudo_reg_arr
[n
++] = i
;
4375 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4377 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4378 bad_spill_regs_global
,
4379 pseudo_forbidden_regs
, pseudo_previous_regs
,
4381 something_changed
= 1;
4383 /* Fix up the register information in the insn chain.
4384 This involves deleting those of the spilled pseudos which did not get
4385 a new hard register home from the live_{before,after} sets. */
4386 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4388 HARD_REG_SET used_by_pseudos
;
4389 HARD_REG_SET used_by_pseudos2
;
4391 if (! ira_conflicts_p
)
4393 /* Don't do it for IRA because IRA and the reload still can
4394 assign hard registers to the spilled pseudos on next
4395 reload iterations. */
4396 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4397 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4399 /* Mark any unallocated hard regs as available for spills. That
4400 makes inheritance work somewhat better. */
4401 if (chain
->need_reload
)
4403 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4404 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4405 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4407 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4408 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4409 /* Value of chain->used_spill_regs from previous iteration
4410 may be not included in the value calculated here because
4411 of possible removing caller-saves insns (see function
4412 delete_caller_save_insns. */
4413 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4414 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4418 CLEAR_REG_SET (&changed_allocation_pseudos
);
4419 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4420 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4422 int regno
= reg_renumber
[i
];
4423 if (reg_old_renumber
[i
] == regno
)
4426 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4428 alter_reg (i
, reg_old_renumber
[i
], false);
4429 reg_old_renumber
[i
] = regno
;
4433 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4435 fprintf (dump_file
, " Register %d now in %d.\n\n",
4436 i
, reg_renumber
[i
]);
4440 return something_changed
;
4443 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4446 scan_paradoxical_subregs (rtx x
)
4450 enum rtx_code code
= GET_CODE (x
);
4466 if (REG_P (SUBREG_REG (x
))
4467 && (GET_MODE_SIZE (GET_MODE (x
))
4468 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4470 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4471 = GET_MODE_SIZE (GET_MODE (x
));
4472 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4480 fmt
= GET_RTX_FORMAT (code
);
4481 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4484 scan_paradoxical_subregs (XEXP (x
, i
));
4485 else if (fmt
[i
] == 'E')
4488 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4489 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4494 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4495 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4496 and apply the corresponding narrowing subreg to *OTHER_PTR.
4497 Return true if the operands were changed, false otherwise. */
4500 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4502 rtx op
, inner
, other
, tem
;
4505 if (!paradoxical_subreg_p (op
))
4507 inner
= SUBREG_REG (op
);
4510 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4514 /* If the lowpart operation turned a hard register into a subreg,
4515 rather than simplifying it to another hard register, then the
4516 mode change cannot be properly represented. For example, OTHER
4517 might be valid in its current mode, but not in the new one. */
4518 if (GET_CODE (tem
) == SUBREG
4520 && HARD_REGISTER_P (other
))
4528 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4529 examine all of the reload insns between PREV and NEXT exclusive, and
4530 annotate all that may trap. */
4533 fixup_eh_region_note (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4535 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4538 if (!insn_could_throw_p (insn
))
4539 remove_note (insn
, note
);
4540 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4543 /* Reload pseudo-registers into hard regs around each insn as needed.
4544 Additional register load insns are output before the insn that needs it
4545 and perhaps store insns after insns that modify the reloaded pseudo reg.
4547 reg_last_reload_reg and reg_reloaded_contents keep track of
4548 which registers are already available in reload registers.
4549 We update these for the reloads that we perform,
4550 as the insns are scanned. */
4553 reload_as_needed (int live_known
)
4555 struct insn_chain
*chain
;
4561 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4562 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4563 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4564 INIT_REG_SET (®_has_output_reload
);
4565 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4566 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4568 set_initial_elim_offsets ();
4570 /* Generate a marker insn that we will move around. */
4571 marker
= emit_note (NOTE_INSN_DELETED
);
4572 unlink_insn_chain (marker
, marker
);
4574 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4577 rtx_insn
*insn
= chain
->insn
;
4578 rtx_insn
*old_next
= NEXT_INSN (insn
);
4580 rtx_insn
*old_prev
= PREV_INSN (insn
);
4583 if (will_delete_init_insn_p (insn
))
4586 /* If we pass a label, copy the offsets from the label information
4587 into the current offsets of each elimination. */
4589 set_offsets_for_label (insn
);
4591 else if (INSN_P (insn
))
4593 regset_head regs_to_forget
;
4594 INIT_REG_SET (®s_to_forget
);
4595 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4597 /* If this is a USE and CLOBBER of a MEM, ensure that any
4598 references to eliminable registers have been removed. */
4600 if ((GET_CODE (PATTERN (insn
)) == USE
4601 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4602 && MEM_P (XEXP (PATTERN (insn
), 0)))
4603 XEXP (XEXP (PATTERN (insn
), 0), 0)
4604 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4605 GET_MODE (XEXP (PATTERN (insn
), 0)),
4608 /* If we need to do register elimination processing, do so.
4609 This might delete the insn, in which case we are done. */
4610 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4612 eliminate_regs_in_insn (insn
, 1);
4615 update_eliminable_offsets ();
4616 CLEAR_REG_SET (®s_to_forget
);
4621 /* If need_elim is nonzero but need_reload is zero, one might think
4622 that we could simply set n_reloads to 0. However, find_reloads
4623 could have done some manipulation of the insn (such as swapping
4624 commutative operands), and these manipulations are lost during
4625 the first pass for every insn that needs register elimination.
4626 So the actions of find_reloads must be redone here. */
4628 if (! chain
->need_elim
&& ! chain
->need_reload
4629 && ! chain
->need_operand_change
)
4631 /* First find the pseudo regs that must be reloaded for this insn.
4632 This info is returned in the tables reload_... (see reload.h).
4633 Also modify the body of INSN by substituting RELOAD
4634 rtx's for those pseudo regs. */
4637 CLEAR_REG_SET (®_has_output_reload
);
4638 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4640 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4646 rtx_insn
*next
= NEXT_INSN (insn
);
4648 /* ??? PREV can get deleted by reload inheritance.
4649 Work around this by emitting a marker note. */
4650 prev
= PREV_INSN (insn
);
4651 reorder_insns_nobb (marker
, marker
, prev
);
4653 /* Now compute which reload regs to reload them into. Perhaps
4654 reusing reload regs from previous insns, or else output
4655 load insns to reload them. Maybe output store insns too.
4656 Record the choices of reload reg in reload_reg_rtx. */
4657 choose_reload_regs (chain
);
4659 /* Generate the insns to reload operands into or out of
4660 their reload regs. */
4661 emit_reload_insns (chain
);
4663 /* Substitute the chosen reload regs from reload_reg_rtx
4664 into the insn's body (or perhaps into the bodies of other
4665 load and store insn that we just made for reloading
4666 and that we moved the structure into). */
4667 subst_reloads (insn
);
4669 prev
= PREV_INSN (marker
);
4670 unlink_insn_chain (marker
, marker
);
4672 /* Adjust the exception region notes for loads and stores. */
4673 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4674 fixup_eh_region_note (insn
, prev
, next
);
4676 /* Adjust the location of REG_ARGS_SIZE. */
4677 rtx p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4680 remove_note (insn
, p
);
4681 fixup_args_size_notes (prev
, PREV_INSN (next
),
4682 INTVAL (XEXP (p
, 0)));
4685 /* If this was an ASM, make sure that all the reload insns
4686 we have generated are valid. If not, give an error
4688 if (asm_noperands (PATTERN (insn
)) >= 0)
4689 for (rtx_insn
*p
= NEXT_INSN (prev
);
4692 if (p
!= insn
&& INSN_P (p
)
4693 && GET_CODE (PATTERN (p
)) != USE
4694 && (recog_memoized (p
) < 0
4695 || (extract_insn (p
),
4696 !(constrain_operands (1,
4697 get_enabled_alternatives (p
))))))
4699 error_for_asm (insn
,
4700 "%<asm%> operand requires "
4701 "impossible reload");
4706 if (num_eliminable
&& chain
->need_elim
)
4707 update_eliminable_offsets ();
4709 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4710 is no longer validly lying around to save a future reload.
4711 Note that this does not detect pseudos that were reloaded
4712 for this insn in order to be stored in
4713 (obeying register constraints). That is correct; such reload
4714 registers ARE still valid. */
4715 forget_marked_reloads (®s_to_forget
);
4716 CLEAR_REG_SET (®s_to_forget
);
4718 /* There may have been CLOBBER insns placed after INSN. So scan
4719 between INSN and NEXT and use them to forget old reloads. */
4720 for (rtx_insn
*x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4721 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4722 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4725 /* Likewise for regs altered by auto-increment in this insn.
4726 REG_INC notes have been changed by reloading:
4727 find_reloads_address_1 records substitutions for them,
4728 which have been performed by subst_reloads above. */
4729 for (i
= n_reloads
- 1; i
>= 0; i
--)
4731 rtx in_reg
= rld
[i
].in_reg
;
4734 enum rtx_code code
= GET_CODE (in_reg
);
4735 /* PRE_INC / PRE_DEC will have the reload register ending up
4736 with the same value as the stack slot, but that doesn't
4737 hold true for POST_INC / POST_DEC. Either we have to
4738 convert the memory access to a true POST_INC / POST_DEC,
4739 or we can't use the reload register for inheritance. */
4740 if ((code
== POST_INC
|| code
== POST_DEC
)
4741 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4742 REGNO (rld
[i
].reg_rtx
))
4743 /* Make sure it is the inc/dec pseudo, and not
4744 some other (e.g. output operand) pseudo. */
4745 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4746 == REGNO (XEXP (in_reg
, 0))))
4749 rtx reload_reg
= rld
[i
].reg_rtx
;
4750 machine_mode mode
= GET_MODE (reload_reg
);
4754 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4756 /* We really want to ignore REG_INC notes here, so
4757 use PATTERN (p) as argument to reg_set_p . */
4758 if (reg_set_p (reload_reg
, PATTERN (p
)))
4760 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4766 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4768 validate_replace_rtx_group (reload_reg
,
4770 n
= verify_changes (0);
4772 /* We must also verify that the constraints
4773 are met after the replacement. Make sure
4774 extract_insn is only called for an insn
4775 where the replacements were found to be
4780 n
= constrain_operands (1,
4781 get_enabled_alternatives (p
));
4784 /* If the constraints were not met, then
4785 undo the replacement, else confirm it. */
4789 confirm_change_group ();
4795 add_reg_note (p
, REG_INC
, reload_reg
);
4796 /* Mark this as having an output reload so that the
4797 REG_INC processing code below won't invalidate
4798 the reload for inheritance. */
4799 SET_HARD_REG_BIT (reg_is_output_reload
,
4800 REGNO (reload_reg
));
4801 SET_REGNO_REG_SET (®_has_output_reload
,
4802 REGNO (XEXP (in_reg
, 0)));
4805 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4808 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4809 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4810 REGNO (rld
[i
].reg_rtx
))
4811 /* Make sure it is the inc/dec pseudo, and not
4812 some other (e.g. output operand) pseudo. */
4813 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4814 == REGNO (XEXP (in_reg
, 0))))
4816 SET_HARD_REG_BIT (reg_is_output_reload
,
4817 REGNO (rld
[i
].reg_rtx
));
4818 SET_REGNO_REG_SET (®_has_output_reload
,
4819 REGNO (XEXP (in_reg
, 0)));
4821 else if (code
== PRE_INC
|| code
== PRE_DEC
4822 || code
== POST_INC
|| code
== POST_DEC
)
4824 int in_regno
= REGNO (XEXP (in_reg
, 0));
4826 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4829 bool forget_p
= true;
4831 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4832 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4835 for (rtx_insn
*x
= (old_prev
?
4836 NEXT_INSN (old_prev
) : insn
);
4839 if (x
== reg_reloaded_insn
[in_hard_regno
])
4845 /* If for some reasons, we didn't set up
4846 reg_last_reload_reg in this insn,
4847 invalidate inheritance from previous
4848 insns for the incremented/decremented
4849 register. Such registers will be not in
4850 reg_has_output_reload. Invalidate it
4851 also if the corresponding element in
4852 reg_reloaded_insn is also
4855 forget_old_reloads_1 (XEXP (in_reg
, 0),
4861 /* If a pseudo that got a hard register is auto-incremented,
4862 we must purge records of copying it into pseudos without
4864 for (rtx x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4865 if (REG_NOTE_KIND (x
) == REG_INC
)
4867 /* See if this pseudo reg was reloaded in this insn.
4868 If so, its last-reload info is still valid
4869 because it is based on this insn's reload. */
4870 for (i
= 0; i
< n_reloads
; i
++)
4871 if (rld
[i
].out
== XEXP (x
, 0))
4875 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4879 /* A reload reg's contents are unknown after a label. */
4881 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4883 /* Don't assume a reload reg is still good after a call insn
4884 if it is a call-used reg, or if it contains a value that will
4885 be partially clobbered by the call. */
4886 else if (CALL_P (insn
))
4888 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4889 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4891 /* If this is a call to a setjmp-type function, we must not
4892 reuse any reload reg contents across the call; that will
4893 just be clobbered by other uses of the register in later
4894 code, before the longjmp. */
4895 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4896 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4901 free (reg_last_reload_reg
);
4902 CLEAR_REG_SET (®_has_output_reload
);
4905 /* Discard all record of any value reloaded from X,
4906 or reloaded in X from someplace else;
4907 unless X is an output reload reg of the current insn.
4909 X may be a hard reg (the reload reg)
4910 or it may be a pseudo reg that was reloaded from.
4912 When DATA is non-NULL just mark the registers in regset
4913 to be forgotten later. */
4916 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4921 regset regs
= (regset
) data
;
4923 /* note_stores does give us subregs of hard regs,
4924 subreg_regno_offset requires a hard reg. */
4925 while (GET_CODE (x
) == SUBREG
)
4927 /* We ignore the subreg offset when calculating the regno,
4928 because we are using the entire underlying hard register
4938 if (regno
>= FIRST_PSEUDO_REGISTER
)
4944 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4945 /* Storing into a spilled-reg invalidates its contents.
4946 This can happen if a block-local pseudo is allocated to that reg
4947 and it wasn't spilled because this block's total need is 0.
4948 Then some insn might have an optional reload and use this reg. */
4950 for (i
= 0; i
< nr
; i
++)
4951 /* But don't do this if the reg actually serves as an output
4952 reload reg in the current instruction. */
4954 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4956 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4957 spill_reg_store
[regno
+ i
] = 0;
4963 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4966 /* Since value of X has changed,
4967 forget any value previously copied from it. */
4970 /* But don't forget a copy if this is the output reload
4971 that establishes the copy's validity. */
4973 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4974 reg_last_reload_reg
[regno
+ nr
] = 0;
4978 /* Forget the reloads marked in regset by previous function. */
4980 forget_marked_reloads (regset regs
)
4983 reg_set_iterator rsi
;
4984 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4986 if (reg
< FIRST_PSEUDO_REGISTER
4987 /* But don't do this if the reg actually serves as an output
4988 reload reg in the current instruction. */
4990 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4992 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4993 spill_reg_store
[reg
] = 0;
4996 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4997 reg_last_reload_reg
[reg
] = 0;
5001 /* The following HARD_REG_SETs indicate when each hard register is
5002 used for a reload of various parts of the current insn. */
5004 /* If reg is unavailable for all reloads. */
5005 static HARD_REG_SET reload_reg_unavailable
;
5006 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5007 static HARD_REG_SET reload_reg_used
;
5008 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5009 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5010 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5011 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5012 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5013 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5014 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5015 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5016 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5017 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5018 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5019 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5020 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5021 static HARD_REG_SET reload_reg_used_in_op_addr
;
5022 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5023 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5024 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5025 static HARD_REG_SET reload_reg_used_in_insn
;
5026 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5027 static HARD_REG_SET reload_reg_used_in_other_addr
;
5029 /* If reg is in use as a reload reg for any sort of reload. */
5030 static HARD_REG_SET reload_reg_used_at_all
;
5032 /* If reg is use as an inherited reload. We just mark the first register
5034 static HARD_REG_SET reload_reg_used_for_inherit
;
5036 /* Records which hard regs are used in any way, either as explicit use or
5037 by being allocated to a pseudo during any point of the current insn. */
5038 static HARD_REG_SET reg_used_in_insn
;
5040 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5041 TYPE. MODE is used to indicate how many consecutive regs are
5045 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5051 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5054 case RELOAD_FOR_INPUT_ADDRESS
:
5055 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5058 case RELOAD_FOR_INPADDR_ADDRESS
:
5059 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5062 case RELOAD_FOR_OUTPUT_ADDRESS
:
5063 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5066 case RELOAD_FOR_OUTADDR_ADDRESS
:
5067 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5070 case RELOAD_FOR_OPERAND_ADDRESS
:
5071 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5074 case RELOAD_FOR_OPADDR_ADDR
:
5075 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5078 case RELOAD_FOR_OTHER_ADDRESS
:
5079 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5082 case RELOAD_FOR_INPUT
:
5083 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5086 case RELOAD_FOR_OUTPUT
:
5087 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5090 case RELOAD_FOR_INSN
:
5091 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5095 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5098 /* Similarly, but show REGNO is no longer in use for a reload. */
5101 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5102 enum reload_type type
, machine_mode mode
)
5104 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5105 unsigned int start_regno
, end_regno
, r
;
5107 /* A complication is that for some reload types, inheritance might
5108 allow multiple reloads of the same types to share a reload register.
5109 We set check_opnum if we have to check only reloads with the same
5110 operand number, and check_any if we have to check all reloads. */
5111 int check_opnum
= 0;
5113 HARD_REG_SET
*used_in_set
;
5118 used_in_set
= &reload_reg_used
;
5121 case RELOAD_FOR_INPUT_ADDRESS
:
5122 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5125 case RELOAD_FOR_INPADDR_ADDRESS
:
5127 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5130 case RELOAD_FOR_OUTPUT_ADDRESS
:
5131 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5134 case RELOAD_FOR_OUTADDR_ADDRESS
:
5136 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5139 case RELOAD_FOR_OPERAND_ADDRESS
:
5140 used_in_set
= &reload_reg_used_in_op_addr
;
5143 case RELOAD_FOR_OPADDR_ADDR
:
5145 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5148 case RELOAD_FOR_OTHER_ADDRESS
:
5149 used_in_set
= &reload_reg_used_in_other_addr
;
5153 case RELOAD_FOR_INPUT
:
5154 used_in_set
= &reload_reg_used_in_input
[opnum
];
5157 case RELOAD_FOR_OUTPUT
:
5158 used_in_set
= &reload_reg_used_in_output
[opnum
];
5161 case RELOAD_FOR_INSN
:
5162 used_in_set
= &reload_reg_used_in_insn
;
5167 /* We resolve conflicts with remaining reloads of the same type by
5168 excluding the intervals of reload registers by them from the
5169 interval of freed reload registers. Since we only keep track of
5170 one set of interval bounds, we might have to exclude somewhat
5171 more than what would be necessary if we used a HARD_REG_SET here.
5172 But this should only happen very infrequently, so there should
5173 be no reason to worry about it. */
5175 start_regno
= regno
;
5176 end_regno
= regno
+ nregs
;
5177 if (check_opnum
|| check_any
)
5179 for (i
= n_reloads
- 1; i
>= 0; i
--)
5181 if (rld
[i
].when_needed
== type
5182 && (check_any
|| rld
[i
].opnum
== opnum
)
5185 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5186 unsigned int conflict_end
5187 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5189 /* If there is an overlap with the first to-be-freed register,
5190 adjust the interval start. */
5191 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5192 start_regno
= conflict_end
;
5193 /* Otherwise, if there is a conflict with one of the other
5194 to-be-freed registers, adjust the interval end. */
5195 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5196 end_regno
= conflict_start
;
5201 for (r
= start_regno
; r
< end_regno
; r
++)
5202 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5205 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5206 specified by OPNUM and TYPE. */
5209 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5213 /* In use for a RELOAD_OTHER means it's not available for anything. */
5214 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5215 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5221 /* In use for anything means we can't use it for RELOAD_OTHER. */
5222 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5223 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5224 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5225 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5228 for (i
= 0; i
< reload_n_operands
; i
++)
5229 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5230 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5231 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5232 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5233 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5234 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5239 case RELOAD_FOR_INPUT
:
5240 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5241 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5244 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5247 /* If it is used for some other input, can't use it. */
5248 for (i
= 0; i
< reload_n_operands
; i
++)
5249 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5252 /* If it is used in a later operand's address, can't use it. */
5253 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5254 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5255 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5260 case RELOAD_FOR_INPUT_ADDRESS
:
5261 /* Can't use a register if it is used for an input address for this
5262 operand or used as an input in an earlier one. */
5263 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5264 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5267 for (i
= 0; i
< opnum
; i
++)
5268 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5273 case RELOAD_FOR_INPADDR_ADDRESS
:
5274 /* Can't use a register if it is used for an input address
5275 for this operand or used as an input in an earlier
5277 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5280 for (i
= 0; i
< opnum
; i
++)
5281 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5286 case RELOAD_FOR_OUTPUT_ADDRESS
:
5287 /* Can't use a register if it is used for an output address for this
5288 operand or used as an output in this or a later operand. Note
5289 that multiple output operands are emitted in reverse order, so
5290 the conflicting ones are those with lower indices. */
5291 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5294 for (i
= 0; i
<= opnum
; i
++)
5295 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5300 case RELOAD_FOR_OUTADDR_ADDRESS
:
5301 /* Can't use a register if it is used for an output address
5302 for this operand or used as an output in this or a
5303 later operand. Note that multiple output operands are
5304 emitted in reverse order, so the conflicting ones are
5305 those with lower indices. */
5306 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5309 for (i
= 0; i
<= opnum
; i
++)
5310 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5315 case RELOAD_FOR_OPERAND_ADDRESS
:
5316 for (i
= 0; i
< reload_n_operands
; i
++)
5317 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5320 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5321 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5323 case RELOAD_FOR_OPADDR_ADDR
:
5324 for (i
= 0; i
< reload_n_operands
; i
++)
5325 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5328 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5330 case RELOAD_FOR_OUTPUT
:
5331 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5332 outputs, or an operand address for this or an earlier output.
5333 Note that multiple output operands are emitted in reverse order,
5334 so the conflicting ones are those with higher indices. */
5335 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5338 for (i
= 0; i
< reload_n_operands
; i
++)
5339 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5342 for (i
= opnum
; i
< reload_n_operands
; i
++)
5343 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5344 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5349 case RELOAD_FOR_INSN
:
5350 for (i
= 0; i
< reload_n_operands
; i
++)
5351 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5352 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5355 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5356 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5358 case RELOAD_FOR_OTHER_ADDRESS
:
5359 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5366 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5367 the number RELOADNUM, is still available in REGNO at the end of the insn.
5369 We can assume that the reload reg was already tested for availability
5370 at the time it is needed, and we should not check this again,
5371 in case the reg has already been marked in use. */
5374 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5376 int opnum
= rld
[reloadnum
].opnum
;
5377 enum reload_type type
= rld
[reloadnum
].when_needed
;
5380 /* See if there is a reload with the same type for this operand, using
5381 the same register. This case is not handled by the code below. */
5382 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5387 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5389 reg
= rld
[i
].reg_rtx
;
5390 if (reg
== NULL_RTX
)
5392 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5393 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5400 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5401 its value must reach the end. */
5404 /* If this use is for part of the insn,
5405 its value reaches if no subsequent part uses the same register.
5406 Just like the above function, don't try to do this with lots
5409 case RELOAD_FOR_OTHER_ADDRESS
:
5410 /* Here we check for everything else, since these don't conflict
5411 with anything else and everything comes later. */
5413 for (i
= 0; i
< reload_n_operands
; i
++)
5414 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5415 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5416 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5417 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5418 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5419 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5422 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5423 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5424 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5425 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5427 case RELOAD_FOR_INPUT_ADDRESS
:
5428 case RELOAD_FOR_INPADDR_ADDRESS
:
5429 /* Similar, except that we check only for this and subsequent inputs
5430 and the address of only subsequent inputs and we do not need
5431 to check for RELOAD_OTHER objects since they are known not to
5434 for (i
= opnum
; i
< reload_n_operands
; i
++)
5435 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5438 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5439 could be killed if the register is also used by reload with type
5440 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5441 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5442 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5445 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5446 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5447 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5450 for (i
= 0; i
< reload_n_operands
; i
++)
5451 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5452 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5453 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5456 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5459 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5460 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5461 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5463 case RELOAD_FOR_INPUT
:
5464 /* Similar to input address, except we start at the next operand for
5465 both input and input address and we do not check for
5466 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5469 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5470 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5471 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5472 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5475 /* ... fall through ... */
5477 case RELOAD_FOR_OPERAND_ADDRESS
:
5478 /* Check outputs and their addresses. */
5480 for (i
= 0; i
< reload_n_operands
; i
++)
5481 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5482 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5483 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5486 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5488 case RELOAD_FOR_OPADDR_ADDR
:
5489 for (i
= 0; i
< reload_n_operands
; i
++)
5490 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5491 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5492 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5495 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5496 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5497 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5499 case RELOAD_FOR_INSN
:
5500 /* These conflict with other outputs with RELOAD_OTHER. So
5501 we need only check for output addresses. */
5503 opnum
= reload_n_operands
;
5505 /* ... fall through ... */
5507 case RELOAD_FOR_OUTPUT
:
5508 case RELOAD_FOR_OUTPUT_ADDRESS
:
5509 case RELOAD_FOR_OUTADDR_ADDRESS
:
5510 /* We already know these can't conflict with a later output. So the
5511 only thing to check are later output addresses.
5512 Note that multiple output operands are emitted in reverse order,
5513 so the conflicting ones are those with lower indices. */
5514 for (i
= 0; i
< opnum
; i
++)
5515 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5516 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5519 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5520 could be killed if the register is also used by reload with type
5521 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5522 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5523 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5533 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5534 every register in REG. */
5537 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5541 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5542 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5548 /* Returns whether R1 and R2 are uniquely chained: the value of one
5549 is used by the other, and that value is not used by any other
5550 reload for this insn. This is used to partially undo the decision
5551 made in find_reloads when in the case of multiple
5552 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5553 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5554 reloads. This code tries to avoid the conflict created by that
5555 change. It might be cleaner to explicitly keep track of which
5556 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5557 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5558 this after the fact. */
5560 reloads_unique_chain_p (int r1
, int r2
)
5564 /* We only check input reloads. */
5565 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5568 /* Avoid anything with output reloads. */
5569 if (rld
[r1
].out
|| rld
[r2
].out
)
5572 /* "chained" means one reload is a component of the other reload,
5573 not the same as the other reload. */
5574 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5575 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5576 || rld
[r1
].optional
|| rld
[r2
].optional
5577 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5578 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5581 /* The following loop assumes that r1 is the reload that feeds r2. */
5585 for (i
= 0; i
< n_reloads
; i
++)
5586 /* Look for input reloads that aren't our two */
5587 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5589 /* If our reload is mentioned at all, it isn't a simple chain. */
5590 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5596 /* The recursive function change all occurrences of WHAT in *WHERE
5599 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5608 if (*where
== what
|| rtx_equal_p (*where
, what
))
5610 /* Record the location of the changed rtx. */
5611 substitute_stack
.safe_push (where
);
5616 code
= GET_CODE (*where
);
5617 fmt
= GET_RTX_FORMAT (code
);
5618 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5624 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5625 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5627 else if (fmt
[i
] == 'e')
5628 substitute (&XEXP (*where
, i
), what
, repl
);
5632 /* The function returns TRUE if chain of reload R1 and R2 (in any
5633 order) can be evaluated without usage of intermediate register for
5634 the reload containing another reload. It is important to see
5635 gen_reload to understand what the function is trying to do. As an
5636 example, let us have reload chain
5639 r1: <something> + const
5641 and reload R2 got reload reg HR. The function returns true if
5642 there is a correct insn HR = HR + <something>. Otherwise,
5643 gen_reload will use intermediate register (and this is the reload
5644 reg for R1) to reload <something>.
5646 We need this function to find a conflict for chain reloads. In our
5647 example, if HR = HR + <something> is incorrect insn, then we cannot
5648 use HR as a reload register for R2. If we do use it then we get a
5657 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5659 /* Assume other cases in gen_reload are not possible for
5660 chain reloads or do need an intermediate hard registers. */
5665 rtx_insn
*last
= get_last_insn ();
5667 /* Make r2 a component of r1. */
5668 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5671 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5672 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5673 gcc_assert (regno
>= 0);
5674 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5676 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5678 /* If IN is a paradoxical SUBREG, remove it and try to put the
5679 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5680 strip_paradoxical_subreg (&in
, &out
);
5682 if (GET_CODE (in
) == PLUS
5683 && (REG_P (XEXP (in
, 0))
5684 || GET_CODE (XEXP (in
, 0)) == SUBREG
5685 || MEM_P (XEXP (in
, 0)))
5686 && (REG_P (XEXP (in
, 1))
5687 || GET_CODE (XEXP (in
, 1)) == SUBREG
5688 || CONSTANT_P (XEXP (in
, 1))
5689 || MEM_P (XEXP (in
, 1))))
5691 insn
= emit_insn (gen_rtx_SET (out
, in
));
5692 code
= recog_memoized (insn
);
5697 extract_insn (insn
);
5698 /* We want constrain operands to treat this insn strictly in
5699 its validity determination, i.e., the way it would after
5700 reload has completed. */
5701 result
= constrain_operands (1, get_enabled_alternatives (insn
));
5704 delete_insns_since (last
);
5707 /* Restore the original value at each changed address within R1. */
5708 while (!substitute_stack
.is_empty ())
5710 rtx
*where
= substitute_stack
.pop ();
5711 *where
= rld
[r2
].in
;
5717 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5720 This function uses the same algorithm as reload_reg_free_p above. */
5723 reloads_conflict (int r1
, int r2
)
5725 enum reload_type r1_type
= rld
[r1
].when_needed
;
5726 enum reload_type r2_type
= rld
[r2
].when_needed
;
5727 int r1_opnum
= rld
[r1
].opnum
;
5728 int r2_opnum
= rld
[r2
].opnum
;
5730 /* RELOAD_OTHER conflicts with everything. */
5731 if (r2_type
== RELOAD_OTHER
)
5734 /* Otherwise, check conflicts differently for each type. */
5738 case RELOAD_FOR_INPUT
:
5739 return (r2_type
== RELOAD_FOR_INSN
5740 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5741 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5742 || r2_type
== RELOAD_FOR_INPUT
5743 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5744 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5745 && r2_opnum
> r1_opnum
));
5747 case RELOAD_FOR_INPUT_ADDRESS
:
5748 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5749 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5751 case RELOAD_FOR_INPADDR_ADDRESS
:
5752 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5753 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5755 case RELOAD_FOR_OUTPUT_ADDRESS
:
5756 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5757 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5759 case RELOAD_FOR_OUTADDR_ADDRESS
:
5760 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5761 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5763 case RELOAD_FOR_OPERAND_ADDRESS
:
5764 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5765 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5766 && (!reloads_unique_chain_p (r1
, r2
)
5767 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5769 case RELOAD_FOR_OPADDR_ADDR
:
5770 return (r2_type
== RELOAD_FOR_INPUT
5771 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5773 case RELOAD_FOR_OUTPUT
:
5774 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5775 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5776 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5777 && r2_opnum
>= r1_opnum
));
5779 case RELOAD_FOR_INSN
:
5780 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5781 || r2_type
== RELOAD_FOR_INSN
5782 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5784 case RELOAD_FOR_OTHER_ADDRESS
:
5785 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5795 /* Indexed by reload number, 1 if incoming value
5796 inherited from previous insns. */
5797 static char reload_inherited
[MAX_RELOADS
];
5799 /* For an inherited reload, this is the insn the reload was inherited from,
5800 if we know it. Otherwise, this is 0. */
5801 static rtx_insn
*reload_inheritance_insn
[MAX_RELOADS
];
5803 /* If nonzero, this is a place to get the value of the reload,
5804 rather than using reload_in. */
5805 static rtx reload_override_in
[MAX_RELOADS
];
5807 /* For each reload, the hard register number of the register used,
5808 or -1 if we did not need a register for this reload. */
5809 static int reload_spill_index
[MAX_RELOADS
];
5811 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5812 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5814 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5815 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5817 /* Subroutine of free_for_value_p, used to check a single register.
5818 START_REGNO is the starting regno of the full reload register
5819 (possibly comprising multiple hard registers) that we are considering. */
5822 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5823 enum reload_type type
, rtx value
, rtx out
,
5824 int reloadnum
, int ignore_address_reloads
)
5827 /* Set if we see an input reload that must not share its reload register
5828 with any new earlyclobber, but might otherwise share the reload
5829 register with an output or input-output reload. */
5830 int check_earlyclobber
= 0;
5834 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5837 if (out
== const0_rtx
)
5843 /* We use some pseudo 'time' value to check if the lifetimes of the
5844 new register use would overlap with the one of a previous reload
5845 that is not read-only or uses a different value.
5846 The 'time' used doesn't have to be linear in any shape or form, just
5848 Some reload types use different 'buckets' for each operand.
5849 So there are MAX_RECOG_OPERANDS different time values for each
5851 We compute TIME1 as the time when the register for the prospective
5852 new reload ceases to be live, and TIME2 for each existing
5853 reload as the time when that the reload register of that reload
5855 Where there is little to be gained by exact lifetime calculations,
5856 we just make conservative assumptions, i.e. a longer lifetime;
5857 this is done in the 'default:' cases. */
5860 case RELOAD_FOR_OTHER_ADDRESS
:
5861 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5862 time1
= copy
? 0 : 1;
5865 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5867 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5868 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5869 respectively, to the time values for these, we get distinct time
5870 values. To get distinct time values for each operand, we have to
5871 multiply opnum by at least three. We round that up to four because
5872 multiply by four is often cheaper. */
5873 case RELOAD_FOR_INPADDR_ADDRESS
:
5874 time1
= opnum
* 4 + 2;
5876 case RELOAD_FOR_INPUT_ADDRESS
:
5877 time1
= opnum
* 4 + 3;
5879 case RELOAD_FOR_INPUT
:
5880 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5881 executes (inclusive). */
5882 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5884 case RELOAD_FOR_OPADDR_ADDR
:
5886 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5887 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5889 case RELOAD_FOR_OPERAND_ADDRESS
:
5890 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5892 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5894 case RELOAD_FOR_OUTADDR_ADDRESS
:
5895 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5897 case RELOAD_FOR_OUTPUT_ADDRESS
:
5898 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5901 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5904 for (i
= 0; i
< n_reloads
; i
++)
5906 rtx reg
= rld
[i
].reg_rtx
;
5907 if (reg
&& REG_P (reg
)
5908 && ((unsigned) regno
- true_regnum (reg
)
5909 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5912 rtx other_input
= rld
[i
].in
;
5914 /* If the other reload loads the same input value, that
5915 will not cause a conflict only if it's loading it into
5916 the same register. */
5917 if (true_regnum (reg
) != start_regno
)
5918 other_input
= NULL_RTX
;
5919 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5920 || rld
[i
].out
|| out
)
5923 switch (rld
[i
].when_needed
)
5925 case RELOAD_FOR_OTHER_ADDRESS
:
5928 case RELOAD_FOR_INPADDR_ADDRESS
:
5929 /* find_reloads makes sure that a
5930 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5931 by at most one - the first -
5932 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5933 address reload is inherited, the address address reload
5934 goes away, so we can ignore this conflict. */
5935 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5936 && ignore_address_reloads
5937 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5938 Then the address address is still needed to store
5939 back the new address. */
5940 && ! rld
[reloadnum
].out
)
5942 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5943 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5945 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5946 && ignore_address_reloads
5947 /* Unless we are reloading an auto_inc expression. */
5948 && ! rld
[reloadnum
].out
)
5950 time2
= rld
[i
].opnum
* 4 + 2;
5952 case RELOAD_FOR_INPUT_ADDRESS
:
5953 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5954 && ignore_address_reloads
5955 && ! rld
[reloadnum
].out
)
5957 time2
= rld
[i
].opnum
* 4 + 3;
5959 case RELOAD_FOR_INPUT
:
5960 time2
= rld
[i
].opnum
* 4 + 4;
5961 check_earlyclobber
= 1;
5963 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5964 == MAX_RECOG_OPERAND * 4 */
5965 case RELOAD_FOR_OPADDR_ADDR
:
5966 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5967 && ignore_address_reloads
5968 && ! rld
[reloadnum
].out
)
5970 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5972 case RELOAD_FOR_OPERAND_ADDRESS
:
5973 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5974 check_earlyclobber
= 1;
5976 case RELOAD_FOR_INSN
:
5977 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5979 case RELOAD_FOR_OUTPUT
:
5980 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5981 instruction is executed. */
5982 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5984 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5985 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5987 case RELOAD_FOR_OUTADDR_ADDRESS
:
5988 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5989 && ignore_address_reloads
5990 && ! rld
[reloadnum
].out
)
5992 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5994 case RELOAD_FOR_OUTPUT_ADDRESS
:
5995 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5998 /* If there is no conflict in the input part, handle this
5999 like an output reload. */
6000 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
6002 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6003 /* Earlyclobbered outputs must conflict with inputs. */
6004 if (earlyclobber_operand_p (rld
[i
].out
))
6005 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6010 /* RELOAD_OTHER might be live beyond instruction execution,
6011 but this is not obvious when we set time2 = 1. So check
6012 here if there might be a problem with the new reload
6013 clobbering the register used by the RELOAD_OTHER. */
6021 && (! rld
[i
].in
|| rld
[i
].out
6022 || ! rtx_equal_p (other_input
, value
)))
6023 || (out
&& rld
[reloadnum
].out_reg
6024 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6030 /* Earlyclobbered outputs must conflict with inputs. */
6031 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6037 /* Return 1 if the value in reload reg REGNO, as used by a reload
6038 needed for the part of the insn specified by OPNUM and TYPE,
6039 may be used to load VALUE into it.
6041 MODE is the mode in which the register is used, this is needed to
6042 determine how many hard regs to test.
6044 Other read-only reloads with the same value do not conflict
6045 unless OUT is nonzero and these other reloads have to live while
6046 output reloads live.
6047 If OUT is CONST0_RTX, this is a special case: it means that the
6048 test should not be for using register REGNO as reload register, but
6049 for copying from register REGNO into the reload register.
6051 RELOADNUM is the number of the reload we want to load this value for;
6052 a reload does not conflict with itself.
6054 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6055 reloads that load an address for the very reload we are considering.
6057 The caller has to make sure that there is no conflict with the return
6061 free_for_value_p (int regno
, machine_mode mode
, int opnum
,
6062 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6063 int ignore_address_reloads
)
6065 int nregs
= hard_regno_nregs
[regno
][mode
];
6067 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6068 value
, out
, reloadnum
,
6069 ignore_address_reloads
))
6074 /* Return nonzero if the rtx X is invariant over the current function. */
6075 /* ??? Actually, the places where we use this expect exactly what is
6076 tested here, and not everything that is function invariant. In
6077 particular, the frame pointer and arg pointer are special cased;
6078 pic_offset_table_rtx is not, and we must not spill these things to
6082 function_invariant_p (const_rtx x
)
6086 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6088 if (GET_CODE (x
) == PLUS
6089 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6090 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6095 /* Determine whether the reload reg X overlaps any rtx'es used for
6096 overriding inheritance. Return nonzero if so. */
6099 conflicts_with_override (rtx x
)
6102 for (i
= 0; i
< n_reloads
; i
++)
6103 if (reload_override_in
[i
]
6104 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6109 /* Give an error message saying we failed to find a reload for INSN,
6110 and clear out reload R. */
6112 failed_reload (rtx_insn
*insn
, int r
)
6114 if (asm_noperands (PATTERN (insn
)) < 0)
6115 /* It's the compiler's fault. */
6116 fatal_insn ("could not find a spill register", insn
);
6118 /* It's the user's fault; the operand's mode and constraint
6119 don't match. Disable this reload so we don't crash in final. */
6120 error_for_asm (insn
,
6121 "%<asm%> operand constraint incompatible with operand size");
6125 rld
[r
].optional
= 1;
6126 rld
[r
].secondary_p
= 1;
6129 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6130 for reload R. If it's valid, get an rtx for it. Return nonzero if
6133 set_reload_reg (int i
, int r
)
6135 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6137 int regno ATTRIBUTE_UNUSED
;
6138 rtx reg
= spill_reg_rtx
[i
];
6140 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6141 spill_reg_rtx
[i
] = reg
6142 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6144 regno
= true_regnum (reg
);
6146 /* Detect when the reload reg can't hold the reload mode.
6147 This used to be one `if', but Sequent compiler can't handle that. */
6148 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6150 machine_mode test_mode
= VOIDmode
;
6152 test_mode
= GET_MODE (rld
[r
].in
);
6153 /* If rld[r].in has VOIDmode, it means we will load it
6154 in whatever mode the reload reg has: to wit, rld[r].mode.
6155 We have already tested that for validity. */
6156 /* Aside from that, we need to test that the expressions
6157 to reload from or into have modes which are valid for this
6158 reload register. Otherwise the reload insns would be invalid. */
6159 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6160 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6161 if (! (rld
[r
].out
!= 0
6162 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6164 /* The reg is OK. */
6167 /* Mark as in use for this insn the reload regs we use
6169 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6170 rld
[r
].when_needed
, rld
[r
].mode
);
6172 rld
[r
].reg_rtx
= reg
;
6173 reload_spill_index
[r
] = spill_regs
[i
];
6180 /* Find a spill register to use as a reload register for reload R.
6181 LAST_RELOAD is nonzero if this is the last reload for the insn being
6184 Set rld[R].reg_rtx to the register allocated.
6186 We return 1 if successful, or 0 if we couldn't find a spill reg and
6187 we didn't change anything. */
6190 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6195 /* If we put this reload ahead, thinking it is a group,
6196 then insist on finding a group. Otherwise we can grab a
6197 reg that some other reload needs.
6198 (That can happen when we have a 68000 DATA_OR_FP_REG
6199 which is a group of data regs or one fp reg.)
6200 We need not be so restrictive if there are no more reloads
6203 ??? Really it would be nicer to have smarter handling
6204 for that kind of reg class, where a problem like this is normal.
6205 Perhaps those classes should be avoided for reloading
6206 by use of more alternatives. */
6208 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6210 /* If we want a single register and haven't yet found one,
6211 take any reg in the right class and not in use.
6212 If we want a consecutive group, here is where we look for it.
6214 We use three passes so we can first look for reload regs to
6215 reuse, which are already in use for other reloads in this insn,
6216 and only then use additional registers which are not "bad", then
6217 finally any register.
6219 I think that maximizing reuse is needed to make sure we don't
6220 run out of reload regs. Suppose we have three reloads, and
6221 reloads A and B can share regs. These need two regs.
6222 Suppose A and B are given different regs.
6223 That leaves none for C. */
6224 for (pass
= 0; pass
< 3; pass
++)
6226 /* I is the index in spill_regs.
6227 We advance it round-robin between insns to use all spill regs
6228 equally, so that inherited reloads have a chance
6229 of leapfrogging each other. */
6233 for (count
= 0; count
< n_spills
; count
++)
6235 int rclass
= (int) rld
[r
].rclass
;
6241 regnum
= spill_regs
[i
];
6243 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6246 /* We check reload_reg_used to make sure we
6247 don't clobber the return register. */
6248 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6249 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6250 rld
[r
].when_needed
, rld
[r
].in
,
6252 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6253 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6254 /* Look first for regs to share, then for unshared. But
6255 don't share regs used for inherited reloads; they are
6256 the ones we want to preserve. */
6258 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6260 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6263 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6265 /* During the second pass we want to avoid reload registers
6266 which are "bad" for this reload. */
6268 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6271 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6272 (on 68000) got us two FP regs. If NR is 1,
6273 we would reject both of them. */
6276 /* If we need only one reg, we have already won. */
6279 /* But reject a single reg if we demand a group. */
6284 /* Otherwise check that as many consecutive regs as we need
6285 are available here. */
6288 int regno
= regnum
+ nr
- 1;
6289 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6290 && spill_reg_order
[regno
] >= 0
6291 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6292 rld
[r
].when_needed
)))
6301 /* If we found something on the current pass, omit later passes. */
6302 if (count
< n_spills
)
6306 /* We should have found a spill register by now. */
6307 if (count
>= n_spills
)
6310 /* I is the index in SPILL_REG_RTX of the reload register we are to
6311 allocate. Get an rtx for it and find its register number. */
6313 return set_reload_reg (i
, r
);
6316 /* Initialize all the tables needed to allocate reload registers.
6317 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6318 is the array we use to restore the reg_rtx field for every reload. */
6321 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6325 for (i
= 0; i
< n_reloads
; i
++)
6326 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6328 memset (reload_inherited
, 0, MAX_RELOADS
);
6329 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6330 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6332 CLEAR_HARD_REG_SET (reload_reg_used
);
6333 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6334 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6335 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6336 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6337 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6339 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6342 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6343 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6344 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6345 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6346 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6347 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6350 for (i
= 0; i
< reload_n_operands
; i
++)
6352 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6353 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6354 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6355 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6356 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6357 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6360 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6362 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6364 for (i
= 0; i
< n_reloads
; i
++)
6365 /* If we have already decided to use a certain register,
6366 don't use it in another way. */
6368 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6369 rld
[i
].when_needed
, rld
[i
].mode
);
6372 #ifdef SECONDARY_MEMORY_NEEDED
6373 /* If X is not a subreg, return it unmodified. If it is a subreg,
6374 look up whether we made a replacement for the SUBREG_REG. Return
6375 either the replacement or the SUBREG_REG. */
6378 replaced_subreg (rtx x
)
6380 if (GET_CODE (x
) == SUBREG
)
6381 return find_replacement (&SUBREG_REG (x
));
6386 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6387 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6388 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6389 otherwise it is NULL. */
6392 compute_reload_subreg_offset (machine_mode outermode
,
6394 machine_mode innermode
)
6397 machine_mode middlemode
;
6400 return subreg_lowpart_offset (outermode
, innermode
);
6402 outer_offset
= SUBREG_BYTE (subreg
);
6403 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6405 /* If SUBREG is paradoxical then return the normal lowpart offset
6406 for OUTERMODE and INNERMODE. Our caller has already checked
6407 that OUTERMODE fits in INNERMODE. */
6408 if (outer_offset
== 0
6409 && GET_MODE_SIZE (outermode
) > GET_MODE_SIZE (middlemode
))
6410 return subreg_lowpart_offset (outermode
, innermode
);
6412 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6413 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6414 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6417 /* Assign hard reg targets for the pseudo-registers we must reload
6418 into hard regs for this insn.
6419 Also output the instructions to copy them in and out of the hard regs.
6421 For machines with register classes, we are responsible for
6422 finding a reload reg in the proper class. */
6425 choose_reload_regs (struct insn_chain
*chain
)
6427 rtx_insn
*insn
= chain
->insn
;
6429 unsigned int max_group_size
= 1;
6430 enum reg_class group_class
= NO_REGS
;
6431 int pass
, win
, inheritance
;
6433 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6435 /* In order to be certain of getting the registers we need,
6436 we must sort the reloads into order of increasing register class.
6437 Then our grabbing of reload registers will parallel the process
6438 that provided the reload registers.
6440 Also note whether any of the reloads wants a consecutive group of regs.
6441 If so, record the maximum size of the group desired and what
6442 register class contains all the groups needed by this insn. */
6444 for (j
= 0; j
< n_reloads
; j
++)
6446 reload_order
[j
] = j
;
6447 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6449 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6450 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6451 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6454 reload_spill_index
[j
] = -1;
6456 if (rld
[j
].nregs
> 1)
6458 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6460 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6463 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6467 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6469 /* If -O, try first with inheritance, then turning it off.
6470 If not -O, don't do inheritance.
6471 Using inheritance when not optimizing leads to paradoxes
6472 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6473 because one side of the comparison might be inherited. */
6475 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6477 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6479 /* Process the reloads in order of preference just found.
6480 Beyond this point, subregs can be found in reload_reg_rtx.
6482 This used to look for an existing reloaded home for all of the
6483 reloads, and only then perform any new reloads. But that could lose
6484 if the reloads were done out of reg-class order because a later
6485 reload with a looser constraint might have an old home in a register
6486 needed by an earlier reload with a tighter constraint.
6488 To solve this, we make two passes over the reloads, in the order
6489 described above. In the first pass we try to inherit a reload
6490 from a previous insn. If there is a later reload that needs a
6491 class that is a proper subset of the class being processed, we must
6492 also allocate a spill register during the first pass.
6494 Then make a second pass over the reloads to allocate any reloads
6495 that haven't been given registers yet. */
6497 for (j
= 0; j
< n_reloads
; j
++)
6499 int r
= reload_order
[j
];
6500 rtx search_equiv
= NULL_RTX
;
6502 /* Ignore reloads that got marked inoperative. */
6503 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6504 && ! rld
[r
].secondary_p
)
6507 /* If find_reloads chose to use reload_in or reload_out as a reload
6508 register, we don't need to chose one. Otherwise, try even if it
6509 found one since we might save an insn if we find the value lying
6511 Try also when reload_in is a pseudo without a hard reg. */
6512 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6513 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6514 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6515 && !MEM_P (rld
[r
].in
)
6516 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6519 #if 0 /* No longer needed for correct operation.
6520 It might give better code, or might not; worth an experiment? */
6521 /* If this is an optional reload, we can't inherit from earlier insns
6522 until we are sure that any non-optional reloads have been allocated.
6523 The following code takes advantage of the fact that optional reloads
6524 are at the end of reload_order. */
6525 if (rld
[r
].optional
!= 0)
6526 for (i
= 0; i
< j
; i
++)
6527 if ((rld
[reload_order
[i
]].out
!= 0
6528 || rld
[reload_order
[i
]].in
!= 0
6529 || rld
[reload_order
[i
]].secondary_p
)
6530 && ! rld
[reload_order
[i
]].optional
6531 && rld
[reload_order
[i
]].reg_rtx
== 0)
6532 allocate_reload_reg (chain
, reload_order
[i
], 0);
6535 /* First see if this pseudo is already available as reloaded
6536 for a previous insn. We cannot try to inherit for reloads
6537 that are smaller than the maximum number of registers needed
6538 for groups unless the register we would allocate cannot be used
6541 We could check here to see if this is a secondary reload for
6542 an object that is already in a register of the desired class.
6543 This would avoid the need for the secondary reload register.
6544 But this is complex because we can't easily determine what
6545 objects might want to be loaded via this reload. So let a
6546 register be allocated here. In `emit_reload_insns' we suppress
6547 one of the loads in the case described above. */
6553 machine_mode mode
= VOIDmode
;
6554 rtx subreg
= NULL_RTX
;
6558 else if (REG_P (rld
[r
].in
))
6560 regno
= REGNO (rld
[r
].in
);
6561 mode
= GET_MODE (rld
[r
].in
);
6563 else if (REG_P (rld
[r
].in_reg
))
6565 regno
= REGNO (rld
[r
].in_reg
);
6566 mode
= GET_MODE (rld
[r
].in_reg
);
6568 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6569 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6571 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6572 if (regno
< FIRST_PSEUDO_REGISTER
)
6573 regno
= subreg_regno (rld
[r
].in_reg
);
6576 subreg
= rld
[r
].in_reg
;
6577 byte
= SUBREG_BYTE (subreg
);
6579 mode
= GET_MODE (rld
[r
].in_reg
);
6582 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6583 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6585 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6586 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6587 rld
[r
].out
= rld
[r
].in
;
6591 /* This won't work, since REGNO can be a pseudo reg number.
6592 Also, it takes much more hair to keep track of all the things
6593 that can invalidate an inherited reload of part of a pseudoreg. */
6594 else if (GET_CODE (rld
[r
].in
) == SUBREG
6595 && REG_P (SUBREG_REG (rld
[r
].in
)))
6596 regno
= subreg_regno (rld
[r
].in
);
6600 && reg_last_reload_reg
[regno
] != 0
6601 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6602 >= GET_MODE_SIZE (mode
) + byte
)
6603 #ifdef CANNOT_CHANGE_MODE_CLASS
6604 /* Verify that the register it's in can be used in
6606 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6607 GET_MODE (reg_last_reload_reg
[regno
]),
6612 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6613 rtx last_reg
= reg_last_reload_reg
[regno
];
6615 i
= REGNO (last_reg
);
6616 byte
= compute_reload_subreg_offset (mode
,
6618 GET_MODE (last_reg
));
6619 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6620 last_class
= REGNO_REG_CLASS (i
);
6622 if (reg_reloaded_contents
[i
] == regno
6623 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6624 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6625 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6626 /* Even if we can't use this register as a reload
6627 register, we might use it for reload_override_in,
6628 if copying it to the desired class is cheap
6630 || ((register_move_cost (mode
, last_class
, rclass
)
6631 < memory_move_cost (mode
, rclass
, true))
6632 && (secondary_reload_class (1, rclass
, mode
,
6635 #ifdef SECONDARY_MEMORY_NEEDED
6636 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6641 && (rld
[r
].nregs
== max_group_size
6642 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6644 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6645 rld
[r
].when_needed
, rld
[r
].in
,
6648 /* If a group is needed, verify that all the subsequent
6649 registers still have their values intact. */
6650 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6653 for (k
= 1; k
< nr
; k
++)
6654 if (reg_reloaded_contents
[i
+ k
] != regno
6655 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6663 last_reg
= (GET_MODE (last_reg
) == mode
6664 ? last_reg
: gen_rtx_REG (mode
, i
));
6667 for (k
= 0; k
< nr
; k
++)
6668 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6671 /* We found a register that contains the
6672 value we need. If this register is the
6673 same as an `earlyclobber' operand of the
6674 current insn, just mark it as a place to
6675 reload from since we can't use it as the
6676 reload register itself. */
6678 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6679 if (reg_overlap_mentioned_for_reload_p
6680 (reg_last_reload_reg
[regno
],
6681 reload_earlyclobbers
[i1
]))
6684 if (i1
!= n_earlyclobbers
6685 || ! (free_for_value_p (i
, rld
[r
].mode
,
6687 rld
[r
].when_needed
, rld
[r
].in
,
6689 /* Don't use it if we'd clobber a pseudo reg. */
6690 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6692 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6693 /* Don't clobber the frame pointer. */
6694 || (i
== HARD_FRAME_POINTER_REGNUM
6695 && frame_pointer_needed
6697 /* Don't really use the inherited spill reg
6698 if we need it wider than we've got it. */
6699 || (GET_MODE_SIZE (rld
[r
].mode
)
6700 > GET_MODE_SIZE (mode
))
6703 /* If find_reloads chose reload_out as reload
6704 register, stay with it - that leaves the
6705 inherited register for subsequent reloads. */
6706 || (rld
[r
].out
&& rld
[r
].reg_rtx
6707 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6709 if (! rld
[r
].optional
)
6711 reload_override_in
[r
] = last_reg
;
6712 reload_inheritance_insn
[r
]
6713 = reg_reloaded_insn
[i
];
6719 /* We can use this as a reload reg. */
6720 /* Mark the register as in use for this part of
6722 mark_reload_reg_in_use (i
,
6726 rld
[r
].reg_rtx
= last_reg
;
6727 reload_inherited
[r
] = 1;
6728 reload_inheritance_insn
[r
]
6729 = reg_reloaded_insn
[i
];
6730 reload_spill_index
[r
] = i
;
6731 for (k
= 0; k
< nr
; k
++)
6732 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6740 /* Here's another way to see if the value is already lying around. */
6743 && ! reload_inherited
[r
]
6745 && (CONSTANT_P (rld
[r
].in
)
6746 || GET_CODE (rld
[r
].in
) == PLUS
6747 || REG_P (rld
[r
].in
)
6748 || MEM_P (rld
[r
].in
))
6749 && (rld
[r
].nregs
== max_group_size
6750 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6751 search_equiv
= rld
[r
].in
;
6756 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6757 -1, NULL
, 0, rld
[r
].mode
);
6763 regno
= REGNO (equiv
);
6766 /* This must be a SUBREG of a hard register.
6767 Make a new REG since this might be used in an
6768 address and not all machines support SUBREGs
6770 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6771 regno
= subreg_regno (equiv
);
6772 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6773 /* If we choose EQUIV as the reload register, but the
6774 loop below decides to cancel the inheritance, we'll
6775 end up reloading EQUIV in rld[r].mode, not the mode
6776 it had originally. That isn't safe when EQUIV isn't
6777 available as a spill register since its value might
6778 still be live at this point. */
6779 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6780 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6785 /* If we found a spill reg, reject it unless it is free
6786 and of the desired class. */
6790 int bad_for_class
= 0;
6791 int max_regno
= regno
+ rld
[r
].nregs
;
6793 for (i
= regno
; i
< max_regno
; i
++)
6795 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6797 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6802 && ! free_for_value_p (regno
, rld
[r
].mode
,
6803 rld
[r
].opnum
, rld
[r
].when_needed
,
6804 rld
[r
].in
, rld
[r
].out
, r
, 1))
6809 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6812 /* We found a register that contains the value we need.
6813 If this register is the same as an `earlyclobber' operand
6814 of the current insn, just mark it as a place to reload from
6815 since we can't use it as the reload register itself. */
6818 for (i
= 0; i
< n_earlyclobbers
; i
++)
6819 if (reg_overlap_mentioned_for_reload_p (equiv
,
6820 reload_earlyclobbers
[i
]))
6822 if (! rld
[r
].optional
)
6823 reload_override_in
[r
] = equiv
;
6828 /* If the equiv register we have found is explicitly clobbered
6829 in the current insn, it depends on the reload type if we
6830 can use it, use it for reload_override_in, or not at all.
6831 In particular, we then can't use EQUIV for a
6832 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6836 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6837 switch (rld
[r
].when_needed
)
6839 case RELOAD_FOR_OTHER_ADDRESS
:
6840 case RELOAD_FOR_INPADDR_ADDRESS
:
6841 case RELOAD_FOR_INPUT_ADDRESS
:
6842 case RELOAD_FOR_OPADDR_ADDR
:
6845 case RELOAD_FOR_INPUT
:
6846 case RELOAD_FOR_OPERAND_ADDRESS
:
6847 if (! rld
[r
].optional
)
6848 reload_override_in
[r
] = equiv
;
6854 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6855 switch (rld
[r
].when_needed
)
6857 case RELOAD_FOR_OTHER_ADDRESS
:
6858 case RELOAD_FOR_INPADDR_ADDRESS
:
6859 case RELOAD_FOR_INPUT_ADDRESS
:
6860 case RELOAD_FOR_OPADDR_ADDR
:
6861 case RELOAD_FOR_OPERAND_ADDRESS
:
6862 case RELOAD_FOR_INPUT
:
6865 if (! rld
[r
].optional
)
6866 reload_override_in
[r
] = equiv
;
6874 /* If we found an equivalent reg, say no code need be generated
6875 to load it, and use it as our reload reg. */
6877 && (regno
!= HARD_FRAME_POINTER_REGNUM
6878 || !frame_pointer_needed
))
6880 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6882 rld
[r
].reg_rtx
= equiv
;
6883 reload_spill_index
[r
] = regno
;
6884 reload_inherited
[r
] = 1;
6886 /* If reg_reloaded_valid is not set for this register,
6887 there might be a stale spill_reg_store lying around.
6888 We must clear it, since otherwise emit_reload_insns
6889 might delete the store. */
6890 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6891 spill_reg_store
[regno
] = NULL
;
6892 /* If any of the hard registers in EQUIV are spill
6893 registers, mark them as in use for this insn. */
6894 for (k
= 0; k
< nr
; k
++)
6896 i
= spill_reg_order
[regno
+ k
];
6899 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6902 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6909 /* If we found a register to use already, or if this is an optional
6910 reload, we are done. */
6911 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6915 /* No longer needed for correct operation. Might or might
6916 not give better code on the average. Want to experiment? */
6918 /* See if there is a later reload that has a class different from our
6919 class that intersects our class or that requires less register
6920 than our reload. If so, we must allocate a register to this
6921 reload now, since that reload might inherit a previous reload
6922 and take the only available register in our class. Don't do this
6923 for optional reloads since they will force all previous reloads
6924 to be allocated. Also don't do this for reloads that have been
6927 for (i
= j
+ 1; i
< n_reloads
; i
++)
6929 int s
= reload_order
[i
];
6931 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6932 && ! rld
[s
].secondary_p
)
6936 if ((rld
[s
].rclass
!= rld
[r
].rclass
6937 && reg_classes_intersect_p (rld
[r
].rclass
,
6939 || rld
[s
].nregs
< rld
[r
].nregs
)
6946 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6950 /* Now allocate reload registers for anything non-optional that
6951 didn't get one yet. */
6952 for (j
= 0; j
< n_reloads
; j
++)
6954 int r
= reload_order
[j
];
6956 /* Ignore reloads that got marked inoperative. */
6957 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6960 /* Skip reloads that already have a register allocated or are
6962 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6965 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6969 /* If that loop got all the way, we have won. */
6976 /* Loop around and try without any inheritance. */
6981 /* First undo everything done by the failed attempt
6982 to allocate with inheritance. */
6983 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6985 /* Some sanity tests to verify that the reloads found in the first
6986 pass are identical to the ones we have now. */
6987 gcc_assert (chain
->n_reloads
== n_reloads
);
6989 for (i
= 0; i
< n_reloads
; i
++)
6991 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6993 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6994 for (j
= 0; j
< n_spills
; j
++)
6995 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6996 if (! set_reload_reg (j
, i
))
6997 failed_reload (chain
->insn
, i
);
7001 /* If we thought we could inherit a reload, because it seemed that
7002 nothing else wanted the same reload register earlier in the insn,
7003 verify that assumption, now that all reloads have been assigned.
7004 Likewise for reloads where reload_override_in has been set. */
7006 /* If doing expensive optimizations, do one preliminary pass that doesn't
7007 cancel any inheritance, but removes reloads that have been needed only
7008 for reloads that we know can be inherited. */
7009 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
7011 for (j
= 0; j
< n_reloads
; j
++)
7013 int r
= reload_order
[j
];
7015 #ifdef SECONDARY_MEMORY_NEEDED
7018 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
7019 check_reg
= rld
[r
].reg_rtx
;
7020 else if (reload_override_in
[r
]
7021 && (REG_P (reload_override_in
[r
])
7022 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
7023 check_reg
= reload_override_in
[r
];
7026 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
7027 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
7028 (reload_inherited
[r
]
7029 ? rld
[r
].out
: const0_rtx
),
7034 reload_inherited
[r
] = 0;
7035 reload_override_in
[r
] = 0;
7037 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7038 reload_override_in, then we do not need its related
7039 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7040 likewise for other reload types.
7041 We handle this by removing a reload when its only replacement
7042 is mentioned in reload_in of the reload we are going to inherit.
7043 A special case are auto_inc expressions; even if the input is
7044 inherited, we still need the address for the output. We can
7045 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7046 If we succeeded removing some reload and we are doing a preliminary
7047 pass just to remove such reloads, make another pass, since the
7048 removal of one reload might allow us to inherit another one. */
7050 && rld
[r
].out
!= rld
[r
].in
7051 && remove_address_replacements (rld
[r
].in
))
7056 #ifdef SECONDARY_MEMORY_NEEDED
7057 /* If we needed a memory location for the reload, we also have to
7058 remove its related reloads. */
7060 && rld
[r
].out
!= rld
[r
].in
7061 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7062 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7063 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7064 rld
[r
].rclass
, rld
[r
].inmode
)
7065 && remove_address_replacements
7066 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7067 rld
[r
].when_needed
)))
7076 /* Now that reload_override_in is known valid,
7077 actually override reload_in. */
7078 for (j
= 0; j
< n_reloads
; j
++)
7079 if (reload_override_in
[j
])
7080 rld
[j
].in
= reload_override_in
[j
];
7082 /* If this reload won't be done because it has been canceled or is
7083 optional and not inherited, clear reload_reg_rtx so other
7084 routines (such as subst_reloads) don't get confused. */
7085 for (j
= 0; j
< n_reloads
; j
++)
7086 if (rld
[j
].reg_rtx
!= 0
7087 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7088 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7089 && ! rld
[j
].secondary_p
)))
7091 int regno
= true_regnum (rld
[j
].reg_rtx
);
7093 if (spill_reg_order
[regno
] >= 0)
7094 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7095 rld
[j
].when_needed
, rld
[j
].mode
);
7097 reload_spill_index
[j
] = -1;
7100 /* Record which pseudos and which spill regs have output reloads. */
7101 for (j
= 0; j
< n_reloads
; j
++)
7103 int r
= reload_order
[j
];
7105 i
= reload_spill_index
[r
];
7107 /* I is nonneg if this reload uses a register.
7108 If rld[r].reg_rtx is 0, this is an optional reload
7109 that we opted to ignore. */
7110 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7111 && rld
[r
].reg_rtx
!= 0)
7113 int nregno
= REGNO (rld
[r
].out_reg
);
7116 if (nregno
< FIRST_PSEUDO_REGISTER
)
7117 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7120 SET_REGNO_REG_SET (®_has_output_reload
,
7124 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7126 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7127 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7128 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7133 /* Deallocate the reload register for reload R. This is called from
7134 remove_address_replacements. */
7137 deallocate_reload_reg (int r
)
7141 if (! rld
[r
].reg_rtx
)
7143 regno
= true_regnum (rld
[r
].reg_rtx
);
7145 if (spill_reg_order
[regno
] >= 0)
7146 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7148 reload_spill_index
[r
] = -1;
7151 /* These arrays are filled by emit_reload_insns and its subroutines. */
7152 static rtx_insn
*input_reload_insns
[MAX_RECOG_OPERANDS
];
7153 static rtx_insn
*other_input_address_reload_insns
= 0;
7154 static rtx_insn
*other_input_reload_insns
= 0;
7155 static rtx_insn
*input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7156 static rtx_insn
*inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7157 static rtx_insn
*output_reload_insns
[MAX_RECOG_OPERANDS
];
7158 static rtx_insn
*output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7159 static rtx_insn
*outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7160 static rtx_insn
*operand_reload_insns
= 0;
7161 static rtx_insn
*other_operand_reload_insns
= 0;
7162 static rtx_insn
*other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7164 /* Values to be put in spill_reg_store are put here first. Instructions
7165 must only be placed here if the associated reload register reaches
7166 the end of the instruction's reload sequence. */
7167 static rtx_insn
*new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7168 static HARD_REG_SET reg_reloaded_died
;
7170 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7171 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7172 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7173 adjusted register, and return true. Otherwise, return false. */
7175 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7176 enum reg_class new_class
,
7177 machine_mode new_mode
)
7182 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7184 unsigned regno
= REGNO (reg
);
7186 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7188 if (GET_MODE (reg
) != new_mode
)
7190 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7192 if (hard_regno_nregs
[regno
][new_mode
]
7193 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7195 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7203 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7204 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7205 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7206 adjusted register, and return true. Otherwise, return false. */
7208 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7209 enum insn_code icode
)
7212 enum reg_class new_class
= scratch_reload_class (icode
);
7213 machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7215 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7216 new_class
, new_mode
);
7219 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7220 has the number J. OLD contains the value to be used as input. */
7223 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7226 rtx_insn
*insn
= chain
->insn
;
7228 rtx oldequiv_reg
= 0;
7234 /* delete_output_reload is only invoked properly if old contains
7235 the original pseudo register. Since this is replaced with a
7236 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7237 find the pseudo in RELOAD_IN_REG. This is also used to
7238 determine whether a secondary reload is needed. */
7239 if (reload_override_in
[j
]
7240 && (REG_P (rl
->in_reg
)
7241 || (GET_CODE (rl
->in_reg
) == SUBREG
7242 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7249 else if (REG_P (oldequiv
))
7250 oldequiv_reg
= oldequiv
;
7251 else if (GET_CODE (oldequiv
) == SUBREG
)
7252 oldequiv_reg
= SUBREG_REG (oldequiv
);
7254 reloadreg
= reload_reg_rtx_for_input
[j
];
7255 mode
= GET_MODE (reloadreg
);
7257 /* If we are reloading from a register that was recently stored in
7258 with an output-reload, see if we can prove there was
7259 actually no need to store the old value in it. */
7261 if (optimize
&& REG_P (oldequiv
)
7262 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7263 && spill_reg_store
[REGNO (oldequiv
)]
7265 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7266 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7268 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7270 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7273 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7274 oldequiv
= SUBREG_REG (oldequiv
);
7275 if (GET_MODE (oldequiv
) != VOIDmode
7276 && mode
!= GET_MODE (oldequiv
))
7277 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7279 /* Switch to the right place to emit the reload insns. */
7280 switch (rl
->when_needed
)
7283 where
= &other_input_reload_insns
;
7285 case RELOAD_FOR_INPUT
:
7286 where
= &input_reload_insns
[rl
->opnum
];
7288 case RELOAD_FOR_INPUT_ADDRESS
:
7289 where
= &input_address_reload_insns
[rl
->opnum
];
7291 case RELOAD_FOR_INPADDR_ADDRESS
:
7292 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7294 case RELOAD_FOR_OUTPUT_ADDRESS
:
7295 where
= &output_address_reload_insns
[rl
->opnum
];
7297 case RELOAD_FOR_OUTADDR_ADDRESS
:
7298 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7300 case RELOAD_FOR_OPERAND_ADDRESS
:
7301 where
= &operand_reload_insns
;
7303 case RELOAD_FOR_OPADDR_ADDR
:
7304 where
= &other_operand_reload_insns
;
7306 case RELOAD_FOR_OTHER_ADDRESS
:
7307 where
= &other_input_address_reload_insns
;
7313 push_to_sequence (*where
);
7315 /* Auto-increment addresses must be reloaded in a special way. */
7316 if (rl
->out
&& ! rl
->out_reg
)
7318 /* We are not going to bother supporting the case where a
7319 incremented register can't be copied directly from
7320 OLDEQUIV since this seems highly unlikely. */
7321 gcc_assert (rl
->secondary_in_reload
< 0);
7323 if (reload_inherited
[j
])
7324 oldequiv
= reloadreg
;
7326 old
= XEXP (rl
->in_reg
, 0);
7328 /* Prevent normal processing of this reload. */
7330 /* Output a special code sequence for this case. */
7331 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7334 /* If we are reloading a pseudo-register that was set by the previous
7335 insn, see if we can get rid of that pseudo-register entirely
7336 by redirecting the previous insn into our reload register. */
7338 else if (optimize
&& REG_P (old
)
7339 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7340 && dead_or_set_p (insn
, old
)
7341 /* This is unsafe if some other reload
7342 uses the same reg first. */
7343 && ! conflicts_with_override (reloadreg
)
7344 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7345 rl
->when_needed
, old
, rl
->out
, j
, 0))
7347 rtx_insn
*temp
= PREV_INSN (insn
);
7348 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7349 temp
= PREV_INSN (temp
);
7351 && NONJUMP_INSN_P (temp
)
7352 && GET_CODE (PATTERN (temp
)) == SET
7353 && SET_DEST (PATTERN (temp
)) == old
7354 /* Make sure we can access insn_operand_constraint. */
7355 && asm_noperands (PATTERN (temp
)) < 0
7356 /* This is unsafe if operand occurs more than once in current
7357 insn. Perhaps some occurrences aren't reloaded. */
7358 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7360 rtx old
= SET_DEST (PATTERN (temp
));
7361 /* Store into the reload register instead of the pseudo. */
7362 SET_DEST (PATTERN (temp
)) = reloadreg
;
7364 /* Verify that resulting insn is valid.
7366 Note that we have replaced the destination of TEMP with
7367 RELOADREG. If TEMP references RELOADREG within an
7368 autoincrement addressing mode, then the resulting insn
7369 is ill-formed and we must reject this optimization. */
7370 extract_insn (temp
);
7371 if (constrain_operands (1, get_enabled_alternatives (temp
))
7372 && (!AUTO_INC_DEC
|| ! find_reg_note (temp
, REG_INC
, reloadreg
)))
7374 /* If the previous insn is an output reload, the source is
7375 a reload register, and its spill_reg_store entry will
7376 contain the previous destination. This is now
7378 if (REG_P (SET_SRC (PATTERN (temp
)))
7379 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7381 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7382 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7385 /* If these are the only uses of the pseudo reg,
7386 pretend for GDB it lives in the reload reg we used. */
7387 if (REG_N_DEATHS (REGNO (old
)) == 1
7388 && REG_N_SETS (REGNO (old
)) == 1)
7390 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7391 if (ira_conflicts_p
)
7392 /* Inform IRA about the change. */
7393 ira_mark_allocation_change (REGNO (old
));
7394 alter_reg (REGNO (old
), -1, false);
7398 /* Adjust any debug insns between temp and insn. */
7399 while ((temp
= NEXT_INSN (temp
)) != insn
)
7400 if (DEBUG_INSN_P (temp
))
7401 INSN_VAR_LOCATION_LOC (temp
)
7402 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp
),
7405 gcc_assert (NOTE_P (temp
));
7409 SET_DEST (PATTERN (temp
)) = old
;
7414 /* We can't do that, so output an insn to load RELOADREG. */
7416 /* If we have a secondary reload, pick up the secondary register
7417 and icode, if any. If OLDEQUIV and OLD are different or
7418 if this is an in-out reload, recompute whether or not we
7419 still need a secondary register and what the icode should
7420 be. If we still need a secondary register and the class or
7421 icode is different, go back to reloading from OLD if using
7422 OLDEQUIV means that we got the wrong type of register. We
7423 cannot have different class or icode due to an in-out reload
7424 because we don't make such reloads when both the input and
7425 output need secondary reload registers. */
7427 if (! special
&& rl
->secondary_in_reload
>= 0)
7429 rtx second_reload_reg
= 0;
7430 rtx third_reload_reg
= 0;
7431 int secondary_reload
= rl
->secondary_in_reload
;
7432 rtx real_oldequiv
= oldequiv
;
7435 enum insn_code icode
;
7436 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7438 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7439 and similarly for OLD.
7440 See comments in get_secondary_reload in reload.c. */
7441 /* If it is a pseudo that cannot be replaced with its
7442 equivalent MEM, we must fall back to reload_in, which
7443 will have all the necessary substitutions registered.
7444 Likewise for a pseudo that can't be replaced with its
7445 equivalent constant.
7447 Take extra care for subregs of such pseudos. Note that
7448 we cannot use reg_equiv_mem in this case because it is
7449 not in the right mode. */
7452 if (GET_CODE (tmp
) == SUBREG
)
7453 tmp
= SUBREG_REG (tmp
);
7455 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7456 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7457 || reg_equiv_constant (REGNO (tmp
)) != 0))
7459 if (! reg_equiv_mem (REGNO (tmp
))
7460 || num_not_at_initial_offset
7461 || GET_CODE (oldequiv
) == SUBREG
)
7462 real_oldequiv
= rl
->in
;
7464 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7468 if (GET_CODE (tmp
) == SUBREG
)
7469 tmp
= SUBREG_REG (tmp
);
7471 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7472 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7473 || reg_equiv_constant (REGNO (tmp
)) != 0))
7475 if (! reg_equiv_mem (REGNO (tmp
))
7476 || num_not_at_initial_offset
7477 || GET_CODE (old
) == SUBREG
)
7480 real_old
= reg_equiv_mem (REGNO (tmp
));
7483 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7484 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7486 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7488 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7489 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7490 /* We'd have to add more code for quartary reloads. */
7491 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7493 icode
= rl
->secondary_in_icode
;
7495 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7496 || (rl
->in
!= 0 && rl
->out
!= 0))
7498 secondary_reload_info sri
, sri2
;
7499 enum reg_class new_class
, new_t_class
;
7501 sri
.icode
= CODE_FOR_nothing
;
7502 sri
.prev_sri
= NULL
;
7504 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7508 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7509 second_reload_reg
= 0;
7510 else if (new_class
== NO_REGS
)
7512 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7514 (enum insn_code
) sri
.icode
))
7516 icode
= (enum insn_code
) sri
.icode
;
7517 third_reload_reg
= 0;
7522 real_oldequiv
= real_old
;
7525 else if (sri
.icode
!= CODE_FOR_nothing
)
7526 /* We currently lack a way to express this in reloads. */
7530 sri2
.icode
= CODE_FOR_nothing
;
7531 sri2
.prev_sri
= &sri
;
7533 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7536 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7538 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7542 third_reload_reg
= 0;
7543 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7548 real_oldequiv
= real_old
;
7551 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7553 rtx intermediate
= second_reload_reg
;
7555 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7557 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7561 second_reload_reg
= intermediate
;
7562 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7567 real_oldequiv
= real_old
;
7570 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7572 rtx intermediate
= second_reload_reg
;
7574 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7576 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7579 second_reload_reg
= intermediate
;
7580 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7585 real_oldequiv
= real_old
;
7590 /* This could be handled more intelligently too. */
7592 real_oldequiv
= real_old
;
7597 /* If we still need a secondary reload register, check
7598 to see if it is being used as a scratch or intermediate
7599 register and generate code appropriately. If we need
7600 a scratch register, use REAL_OLDEQUIV since the form of
7601 the insn may depend on the actual address if it is
7604 if (second_reload_reg
)
7606 if (icode
!= CODE_FOR_nothing
)
7608 /* We'd have to add extra code to handle this case. */
7609 gcc_assert (!third_reload_reg
);
7611 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7612 second_reload_reg
));
7617 /* See if we need a scratch register to load the
7618 intermediate register (a tertiary reload). */
7619 if (tertiary_icode
!= CODE_FOR_nothing
)
7621 emit_insn ((GEN_FCN (tertiary_icode
)
7622 (second_reload_reg
, real_oldequiv
,
7623 third_reload_reg
)));
7625 else if (third_reload_reg
)
7627 gen_reload (third_reload_reg
, real_oldequiv
,
7630 gen_reload (second_reload_reg
, third_reload_reg
,
7635 gen_reload (second_reload_reg
, real_oldequiv
,
7639 oldequiv
= second_reload_reg
;
7644 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7646 rtx real_oldequiv
= oldequiv
;
7648 if ((REG_P (oldequiv
)
7649 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7650 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7651 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7652 || (GET_CODE (oldequiv
) == SUBREG
7653 && REG_P (SUBREG_REG (oldequiv
))
7654 && (REGNO (SUBREG_REG (oldequiv
))
7655 >= FIRST_PSEUDO_REGISTER
)
7656 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7657 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7658 || (CONSTANT_P (oldequiv
)
7659 && (targetm
.preferred_reload_class (oldequiv
,
7660 REGNO_REG_CLASS (REGNO (reloadreg
)))
7662 real_oldequiv
= rl
->in
;
7663 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7667 if (cfun
->can_throw_non_call_exceptions
)
7668 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7670 /* End this sequence. */
7671 *where
= get_insns ();
7674 /* Update reload_override_in so that delete_address_reloads_1
7675 can see the actual register usage. */
7677 reload_override_in
[j
] = oldequiv
;
7680 /* Generate insns to for the output reload RL, which is for the insn described
7681 by CHAIN and has the number J. */
7683 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7687 rtx_insn
*insn
= chain
->insn
;
7694 if (rl
->when_needed
== RELOAD_OTHER
)
7697 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7699 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7700 mode
= GET_MODE (rl_reg_rtx
);
7702 reloadreg
= rl_reg_rtx
;
7704 /* If we need two reload regs, set RELOADREG to the intermediate
7705 one, since it will be stored into OLD. We might need a secondary
7706 register only for an input reload, so check again here. */
7708 if (rl
->secondary_out_reload
>= 0)
7711 int secondary_reload
= rl
->secondary_out_reload
;
7712 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7714 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7715 && reg_equiv_mem (REGNO (old
)) != 0)
7716 real_old
= reg_equiv_mem (REGNO (old
));
7718 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7720 rtx second_reloadreg
= reloadreg
;
7721 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7723 /* See if RELOADREG is to be used as a scratch register
7724 or as an intermediate register. */
7725 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7727 /* We'd have to add extra code to handle this case. */
7728 gcc_assert (tertiary_reload
< 0);
7730 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7731 (real_old
, second_reloadreg
, reloadreg
)));
7736 /* See if we need both a scratch and intermediate reload
7739 enum insn_code tertiary_icode
7740 = rld
[secondary_reload
].secondary_out_icode
;
7742 /* We'd have to add more code for quartary reloads. */
7743 gcc_assert (tertiary_reload
< 0
7744 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7746 if (GET_MODE (reloadreg
) != mode
)
7747 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7749 if (tertiary_icode
!= CODE_FOR_nothing
)
7751 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7753 /* Copy primary reload reg to secondary reload reg.
7754 (Note that these have been swapped above, then
7755 secondary reload reg to OLD using our insn.) */
7757 /* If REAL_OLD is a paradoxical SUBREG, remove it
7758 and try to put the opposite SUBREG on
7760 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7762 gen_reload (reloadreg
, second_reloadreg
,
7763 rl
->opnum
, rl
->when_needed
);
7764 emit_insn ((GEN_FCN (tertiary_icode
)
7765 (real_old
, reloadreg
, third_reloadreg
)));
7771 /* Copy between the reload regs here and then to
7774 gen_reload (reloadreg
, second_reloadreg
,
7775 rl
->opnum
, rl
->when_needed
);
7776 if (tertiary_reload
>= 0)
7778 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7780 gen_reload (third_reloadreg
, reloadreg
,
7781 rl
->opnum
, rl
->when_needed
);
7782 reloadreg
= third_reloadreg
;
7789 /* Output the last reload insn. */
7794 /* Don't output the last reload if OLD is not the dest of
7795 INSN and is in the src and is clobbered by INSN. */
7796 if (! flag_expensive_optimizations
7798 || !(set
= single_set (insn
))
7799 || rtx_equal_p (old
, SET_DEST (set
))
7800 || !reg_mentioned_p (old
, SET_SRC (set
))
7801 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7802 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7803 gen_reload (old
, reloadreg
, rl
->opnum
,
7807 /* Look at all insns we emitted, just to be safe. */
7808 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7811 rtx pat
= PATTERN (p
);
7813 /* If this output reload doesn't come from a spill reg,
7814 clear any memory of reloaded copies of the pseudo reg.
7815 If this output reload comes from a spill reg,
7816 reg_has_output_reload will make this do nothing. */
7817 note_stores (pat
, forget_old_reloads_1
, NULL
);
7819 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7821 rtx set
= single_set (insn
);
7822 if (reload_spill_index
[j
] < 0
7824 && SET_SRC (set
) == rl_reg_rtx
)
7826 int src
= REGNO (SET_SRC (set
));
7828 reload_spill_index
[j
] = src
;
7829 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7830 if (find_regno_note (insn
, REG_DEAD
, src
))
7831 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7833 if (HARD_REGISTER_P (rl_reg_rtx
))
7835 int s
= rl
->secondary_out_reload
;
7836 set
= single_set (p
);
7837 /* If this reload copies only to the secondary reload
7838 register, the secondary reload does the actual
7840 if (s
>= 0 && set
== NULL_RTX
)
7841 /* We can't tell what function the secondary reload
7842 has and where the actual store to the pseudo is
7843 made; leave new_spill_reg_store alone. */
7846 && SET_SRC (set
) == rl_reg_rtx
7847 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7849 /* Usually the next instruction will be the
7850 secondary reload insn; if we can confirm
7851 that it is, setting new_spill_reg_store to
7852 that insn will allow an extra optimization. */
7853 rtx s_reg
= rld
[s
].reg_rtx
;
7854 rtx_insn
*next
= NEXT_INSN (p
);
7855 rld
[s
].out
= rl
->out
;
7856 rld
[s
].out_reg
= rl
->out_reg
;
7857 set
= single_set (next
);
7858 if (set
&& SET_SRC (set
) == s_reg
7859 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7861 SET_HARD_REG_BIT (reg_is_output_reload
,
7863 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7866 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7867 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7872 if (rl
->when_needed
== RELOAD_OTHER
)
7874 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7875 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7878 output_reload_insns
[rl
->opnum
] = get_insns ();
7880 if (cfun
->can_throw_non_call_exceptions
)
7881 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7886 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7887 and has the number J. */
7889 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7891 rtx_insn
*insn
= chain
->insn
;
7892 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7893 ? rl
->in_reg
: rl
->in
);
7894 rtx reg_rtx
= rl
->reg_rtx
;
7900 /* Determine the mode to reload in.
7901 This is very tricky because we have three to choose from.
7902 There is the mode the insn operand wants (rl->inmode).
7903 There is the mode of the reload register RELOADREG.
7904 There is the intrinsic mode of the operand, which we could find
7905 by stripping some SUBREGs.
7906 It turns out that RELOADREG's mode is irrelevant:
7907 we can change that arbitrarily.
7909 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7910 then the reload reg may not support QImode moves, so use SImode.
7911 If foo is in memory due to spilling a pseudo reg, this is safe,
7912 because the QImode value is in the least significant part of a
7913 slot big enough for a SImode. If foo is some other sort of
7914 memory reference, then it is impossible to reload this case,
7915 so previous passes had better make sure this never happens.
7917 Then consider a one-word union which has SImode and one of its
7918 members is a float, being fetched as (SUBREG:SF union:SI).
7919 We must fetch that as SFmode because we could be loading into
7920 a float-only register. In this case OLD's mode is correct.
7922 Consider an immediate integer: it has VOIDmode. Here we need
7923 to get a mode from something else.
7925 In some cases, there is a fourth mode, the operand's
7926 containing mode. If the insn specifies a containing mode for
7927 this operand, it overrides all others.
7929 I am not sure whether the algorithm here is always right,
7930 but it does the right things in those cases. */
7932 mode
= GET_MODE (old
);
7933 if (mode
== VOIDmode
)
7936 /* We cannot use gen_lowpart_common since it can do the wrong thing
7937 when REG_RTX has a multi-word mode. Note that REG_RTX must
7938 always be a REG here. */
7939 if (GET_MODE (reg_rtx
) != mode
)
7940 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7942 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7945 /* AUTO_INC reloads need to be handled even if inherited. We got an
7946 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7947 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7948 && ! rtx_equal_p (reg_rtx
, old
)
7950 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7952 /* When inheriting a wider reload, we have a MEM in rl->in,
7953 e.g. inheriting a SImode output reload for
7954 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7955 if (optimize
&& reload_inherited
[j
] && rl
->in
7957 && MEM_P (rl
->in_reg
)
7958 && reload_spill_index
[j
] >= 0
7959 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7960 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7962 /* If we are reloading a register that was recently stored in with an
7963 output-reload, see if we can prove there was
7964 actually no need to store the old value in it. */
7967 && (reload_inherited
[j
] || reload_override_in
[j
])
7970 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7972 /* There doesn't seem to be any reason to restrict this to pseudos
7973 and doing so loses in the case where we are copying from a
7974 register of the wrong class. */
7975 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7977 /* The insn might have already some references to stackslots
7978 replaced by MEMs, while reload_out_reg still names the
7980 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7981 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7982 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7985 /* Do output reloading for reload RL, which is for the insn described by
7986 CHAIN and has the number J.
7987 ??? At some point we need to support handling output reloads of
7988 JUMP_INSNs or insns that set cc0. */
7990 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7993 rtx_insn
*insn
= chain
->insn
;
7994 /* If this is an output reload that stores something that is
7995 not loaded in this same reload, see if we can eliminate a previous
7997 rtx pseudo
= rl
->out_reg
;
7998 rtx reg_rtx
= rl
->reg_rtx
;
8000 if (rl
->out
&& reg_rtx
)
8004 /* Determine the mode to reload in.
8005 See comments above (for input reloading). */
8006 mode
= GET_MODE (rl
->out
);
8007 if (mode
== VOIDmode
)
8009 /* VOIDmode should never happen for an output. */
8010 if (asm_noperands (PATTERN (insn
)) < 0)
8011 /* It's the compiler's fault. */
8012 fatal_insn ("VOIDmode on an output", insn
);
8013 error_for_asm (insn
, "output operand is constant in %<asm%>");
8014 /* Prevent crash--use something we know is valid. */
8016 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
8018 if (GET_MODE (reg_rtx
) != mode
)
8019 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
8021 reload_reg_rtx_for_output
[j
] = reg_rtx
;
8026 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
8027 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
8028 && reg_last_reload_reg
[REGNO (pseudo
)])
8030 int pseudo_no
= REGNO (pseudo
);
8031 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
8033 /* We don't need to test full validity of last_regno for
8034 inherit here; we only want to know if the store actually
8035 matches the pseudo. */
8036 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
8037 && reg_reloaded_contents
[last_regno
] == pseudo_no
8038 && spill_reg_store
[last_regno
]
8039 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
8040 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
8046 || rtx_equal_p (old
, reg_rtx
))
8049 /* An output operand that dies right away does need a reload,
8050 but need not be copied from it. Show the new location in the
8052 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
8053 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
8055 XEXP (note
, 0) = reg_rtx
;
8058 /* Likewise for a SUBREG of an operand that dies. */
8059 else if (GET_CODE (old
) == SUBREG
8060 && REG_P (SUBREG_REG (old
))
8061 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
8064 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
8067 else if (GET_CODE (old
) == SCRATCH
)
8068 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8069 but we don't want to make an output reload. */
8072 /* If is a JUMP_INSN, we can't support output reloads yet. */
8073 gcc_assert (NONJUMP_INSN_P (insn
));
8075 emit_output_reload_insns (chain
, rld
+ j
, j
);
8078 /* A reload copies values of MODE from register SRC to register DEST.
8079 Return true if it can be treated for inheritance purposes like a
8080 group of reloads, each one reloading a single hard register. The
8081 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8082 occupy the same number of hard registers. */
8085 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8086 int src ATTRIBUTE_UNUSED
,
8087 machine_mode mode ATTRIBUTE_UNUSED
)
8089 #ifdef CANNOT_CHANGE_MODE_CLASS
8090 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8091 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8097 /* Output insns to reload values in and out of the chosen reload regs. */
8100 emit_reload_insns (struct insn_chain
*chain
)
8102 rtx_insn
*insn
= chain
->insn
;
8106 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8108 for (j
= 0; j
< reload_n_operands
; j
++)
8109 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8110 = inpaddr_address_reload_insns
[j
]
8111 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8112 = outaddr_address_reload_insns
[j
]
8113 = other_output_reload_insns
[j
] = 0;
8114 other_input_address_reload_insns
= 0;
8115 other_input_reload_insns
= 0;
8116 operand_reload_insns
= 0;
8117 other_operand_reload_insns
= 0;
8119 /* Dump reloads into the dump file. */
8122 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8123 debug_reload_to_stream (dump_file
);
8126 for (j
= 0; j
< n_reloads
; j
++)
8127 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8131 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8132 new_spill_reg_store
[i
] = 0;
8135 /* Now output the instructions to copy the data into and out of the
8136 reload registers. Do these in the order that the reloads were reported,
8137 since reloads of base and index registers precede reloads of operands
8138 and the operands may need the base and index registers reloaded. */
8140 for (j
= 0; j
< n_reloads
; j
++)
8142 do_input_reload (chain
, rld
+ j
, j
);
8143 do_output_reload (chain
, rld
+ j
, j
);
8146 /* Now write all the insns we made for reloads in the order expected by
8147 the allocation functions. Prior to the insn being reloaded, we write
8148 the following reloads:
8150 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8152 RELOAD_OTHER reloads.
8154 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8155 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8156 RELOAD_FOR_INPUT reload for the operand.
8158 RELOAD_FOR_OPADDR_ADDRS reloads.
8160 RELOAD_FOR_OPERAND_ADDRESS reloads.
8162 After the insn being reloaded, we write the following:
8164 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8165 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8166 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8167 reloads for the operand. The RELOAD_OTHER output reloads are
8168 output in descending order by reload number. */
8170 emit_insn_before (other_input_address_reload_insns
, insn
);
8171 emit_insn_before (other_input_reload_insns
, insn
);
8173 for (j
= 0; j
< reload_n_operands
; j
++)
8175 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8176 emit_insn_before (input_address_reload_insns
[j
], insn
);
8177 emit_insn_before (input_reload_insns
[j
], insn
);
8180 emit_insn_before (other_operand_reload_insns
, insn
);
8181 emit_insn_before (operand_reload_insns
, insn
);
8183 for (j
= 0; j
< reload_n_operands
; j
++)
8185 rtx_insn
*x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8186 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8187 x
= emit_insn_after (output_reload_insns
[j
], x
);
8188 emit_insn_after (other_output_reload_insns
[j
], x
);
8191 /* For all the spill regs newly reloaded in this instruction,
8192 record what they were reloaded from, so subsequent instructions
8193 can inherit the reloads.
8195 Update spill_reg_store for the reloads of this insn.
8196 Copy the elements that were updated in the loop above. */
8198 for (j
= 0; j
< n_reloads
; j
++)
8200 int r
= reload_order
[j
];
8201 int i
= reload_spill_index
[r
];
8203 /* If this is a non-inherited input reload from a pseudo, we must
8204 clear any memory of a previous store to the same pseudo. Only do
8205 something if there will not be an output reload for the pseudo
8207 if (rld
[r
].in_reg
!= 0
8208 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8210 rtx reg
= rld
[r
].in_reg
;
8212 if (GET_CODE (reg
) == SUBREG
)
8213 reg
= SUBREG_REG (reg
);
8216 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8217 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8219 int nregno
= REGNO (reg
);
8221 if (reg_last_reload_reg
[nregno
])
8223 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8225 if (reg_reloaded_contents
[last_regno
] == nregno
)
8226 spill_reg_store
[last_regno
] = 0;
8231 /* I is nonneg if this reload used a register.
8232 If rld[r].reg_rtx is 0, this is an optional reload
8233 that we opted to ignore. */
8235 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8237 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8240 /* For a multi register reload, we need to check if all or part
8241 of the value lives to the end. */
8242 for (k
= 0; k
< nr
; k
++)
8243 if (reload_reg_reaches_end_p (i
+ k
, r
))
8244 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8246 /* Maybe the spill reg contains a copy of reload_out. */
8248 && (REG_P (rld
[r
].out
)
8250 ? REG_P (rld
[r
].out_reg
)
8251 /* The reload value is an auto-modification of
8252 some kind. For PRE_INC, POST_INC, PRE_DEC
8253 and POST_DEC, we record an equivalence
8254 between the reload register and the operand
8255 on the optimistic assumption that we can make
8256 the equivalence hold. reload_as_needed must
8257 then either make it hold or invalidate the
8260 PRE_MODIFY and POST_MODIFY addresses are reloaded
8261 somewhat differently, and allowing them here leads
8263 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8264 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8268 reg
= reload_reg_rtx_for_output
[r
];
8269 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8271 machine_mode mode
= GET_MODE (reg
);
8272 int regno
= REGNO (reg
);
8273 int nregs
= hard_regno_nregs
[regno
][mode
];
8274 rtx out
= (REG_P (rld
[r
].out
)
8278 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8279 int out_regno
= REGNO (out
);
8280 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8281 : hard_regno_nregs
[out_regno
][mode
]);
8284 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8285 spill_reg_stored_to
[regno
] = out
;
8286 reg_last_reload_reg
[out_regno
] = reg
;
8288 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8289 && nregs
== out_nregs
8290 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8292 /* If OUT_REGNO is a hard register, it may occupy more than
8293 one register. If it does, say what is in the
8294 rest of the registers assuming that both registers
8295 agree on how many words the object takes. If not,
8296 invalidate the subsequent registers. */
8298 if (HARD_REGISTER_NUM_P (out_regno
))
8299 for (k
= 1; k
< out_nregs
; k
++)
8300 reg_last_reload_reg
[out_regno
+ k
]
8301 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8303 /* Now do the inverse operation. */
8304 for (k
= 0; k
< nregs
; k
++)
8306 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8307 reg_reloaded_contents
[regno
+ k
]
8308 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8311 reg_reloaded_insn
[regno
+ k
] = insn
;
8312 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8313 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8314 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8317 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8322 /* Maybe the spill reg contains a copy of reload_in. Only do
8323 something if there will not be an output reload for
8324 the register being reloaded. */
8325 else if (rld
[r
].out_reg
== 0
8327 && ((REG_P (rld
[r
].in
)
8328 && !HARD_REGISTER_P (rld
[r
].in
)
8329 && !REGNO_REG_SET_P (®_has_output_reload
,
8331 || (REG_P (rld
[r
].in_reg
)
8332 && !REGNO_REG_SET_P (®_has_output_reload
,
8333 REGNO (rld
[r
].in_reg
))))
8334 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8338 reg
= reload_reg_rtx_for_input
[r
];
8339 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8349 mode
= GET_MODE (reg
);
8350 regno
= REGNO (reg
);
8351 nregs
= hard_regno_nregs
[regno
][mode
];
8352 if (REG_P (rld
[r
].in
)
8353 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8355 else if (REG_P (rld
[r
].in_reg
))
8358 in
= XEXP (rld
[r
].in_reg
, 0);
8359 in_regno
= REGNO (in
);
8361 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8362 : hard_regno_nregs
[in_regno
][mode
]);
8364 reg_last_reload_reg
[in_regno
] = reg
;
8366 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8367 && nregs
== in_nregs
8368 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8370 if (HARD_REGISTER_NUM_P (in_regno
))
8371 for (k
= 1; k
< in_nregs
; k
++)
8372 reg_last_reload_reg
[in_regno
+ k
]
8373 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8375 /* Unless we inherited this reload, show we haven't
8376 recently done a store.
8377 Previous stores of inherited auto_inc expressions
8378 also have to be discarded. */
8379 if (! reload_inherited
[r
]
8380 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8381 spill_reg_store
[regno
] = 0;
8383 for (k
= 0; k
< nregs
; k
++)
8385 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8386 reg_reloaded_contents
[regno
+ k
]
8387 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8390 reg_reloaded_insn
[regno
+ k
] = insn
;
8391 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8392 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8393 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8396 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8403 /* The following if-statement was #if 0'd in 1.34 (or before...).
8404 It's reenabled in 1.35 because supposedly nothing else
8405 deals with this problem. */
8407 /* If a register gets output-reloaded from a non-spill register,
8408 that invalidates any previous reloaded copy of it.
8409 But forget_old_reloads_1 won't get to see it, because
8410 it thinks only about the original insn. So invalidate it here.
8411 Also do the same thing for RELOAD_OTHER constraints where the
8412 output is discarded. */
8414 && ((rld
[r
].out
!= 0
8415 && (REG_P (rld
[r
].out
)
8416 || (MEM_P (rld
[r
].out
)
8417 && REG_P (rld
[r
].out_reg
))))
8418 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8419 && REG_P (rld
[r
].out_reg
))))
8421 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8422 ? rld
[r
].out
: rld
[r
].out_reg
);
8423 int out_regno
= REGNO (out
);
8424 machine_mode mode
= GET_MODE (out
);
8426 /* REG_RTX is now set or clobbered by the main instruction.
8427 As the comment above explains, forget_old_reloads_1 only
8428 sees the original instruction, and there is no guarantee
8429 that the original instruction also clobbered REG_RTX.
8430 For example, if find_reloads sees that the input side of
8431 a matched operand pair dies in this instruction, it may
8432 use the input register as the reload register.
8434 Calling forget_old_reloads_1 is a waste of effort if
8435 REG_RTX is also the output register.
8437 If we know that REG_RTX holds the value of a pseudo
8438 register, the code after the call will record that fact. */
8439 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8440 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8442 if (!HARD_REGISTER_NUM_P (out_regno
))
8445 rtx_insn
*store_insn
= NULL
;
8447 reg_last_reload_reg
[out_regno
] = 0;
8449 /* If we can find a hard register that is stored, record
8450 the storing insn so that we may delete this insn with
8451 delete_output_reload. */
8452 src_reg
= reload_reg_rtx_for_output
[r
];
8456 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8457 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8463 /* If this is an optional reload, try to find the
8464 source reg from an input reload. */
8465 rtx set
= single_set (insn
);
8466 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8470 src_reg
= SET_SRC (set
);
8472 for (k
= 0; k
< n_reloads
; k
++)
8474 if (rld
[k
].in
== src_reg
)
8476 src_reg
= reload_reg_rtx_for_input
[k
];
8482 if (src_reg
&& REG_P (src_reg
)
8483 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8485 int src_regno
, src_nregs
, k
;
8488 gcc_assert (GET_MODE (src_reg
) == mode
);
8489 src_regno
= REGNO (src_reg
);
8490 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8491 /* The place where to find a death note varies with
8492 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8493 necessarily checked exactly in the code that moves
8494 notes, so just check both locations. */
8495 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8496 if (! note
&& store_insn
)
8497 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8498 for (k
= 0; k
< src_nregs
; k
++)
8500 spill_reg_store
[src_regno
+ k
] = store_insn
;
8501 spill_reg_stored_to
[src_regno
+ k
] = out
;
8502 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8503 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8504 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8505 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8506 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8508 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8511 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8513 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8515 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8517 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8519 reg_last_reload_reg
[out_regno
] = src_reg
;
8520 /* We have to set reg_has_output_reload here, or else
8521 forget_old_reloads_1 will clear reg_last_reload_reg
8523 SET_REGNO_REG_SET (®_has_output_reload
,
8529 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8531 for (k
= 0; k
< out_nregs
; k
++)
8532 reg_last_reload_reg
[out_regno
+ k
] = 0;
8536 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8539 /* Go through the motions to emit INSN and test if it is strictly valid.
8540 Return the emitted insn if valid, else return NULL. */
8543 emit_insn_if_valid_for_reload (rtx pat
)
8545 rtx_insn
*last
= get_last_insn ();
8548 rtx_insn
*insn
= emit_insn (pat
);
8549 code
= recog_memoized (insn
);
8553 extract_insn (insn
);
8554 /* We want constrain operands to treat this insn strictly in its
8555 validity determination, i.e., the way it would after reload has
8557 if (constrain_operands (1, get_enabled_alternatives (insn
)))
8561 delete_insns_since (last
);
8565 /* Emit code to perform a reload from IN (which may be a reload register) to
8566 OUT (which may also be a reload register). IN or OUT is from operand
8567 OPNUM with reload type TYPE.
8569 Returns first insn emitted. */
8572 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8574 rtx_insn
*last
= get_last_insn ();
8576 #ifdef SECONDARY_MEMORY_NEEDED
8580 /* If IN is a paradoxical SUBREG, remove it and try to put the
8581 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8582 if (!strip_paradoxical_subreg (&in
, &out
))
8583 strip_paradoxical_subreg (&out
, &in
);
8585 /* How to do this reload can get quite tricky. Normally, we are being
8586 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8587 register that didn't get a hard register. In that case we can just
8588 call emit_move_insn.
8590 We can also be asked to reload a PLUS that adds a register or a MEM to
8591 another register, constant or MEM. This can occur during frame pointer
8592 elimination and while reloading addresses. This case is handled by
8593 trying to emit a single insn to perform the add. If it is not valid,
8594 we use a two insn sequence.
8596 Or we can be asked to reload an unary operand that was a fragment of
8597 an addressing mode, into a register. If it isn't recognized as-is,
8598 we try making the unop operand and the reload-register the same:
8599 (set reg:X (unop:X expr:Y))
8600 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8602 Finally, we could be called to handle an 'o' constraint by putting
8603 an address into a register. In that case, we first try to do this
8604 with a named pattern of "reload_load_address". If no such pattern
8605 exists, we just emit a SET insn and hope for the best (it will normally
8606 be valid on machines that use 'o').
8608 This entire process is made complex because reload will never
8609 process the insns we generate here and so we must ensure that
8610 they will fit their constraints and also by the fact that parts of
8611 IN might be being reloaded separately and replaced with spill registers.
8612 Because of this, we are, in some sense, just guessing the right approach
8613 here. The one listed above seems to work.
8615 ??? At some point, this whole thing needs to be rethought. */
8617 if (GET_CODE (in
) == PLUS
8618 && (REG_P (XEXP (in
, 0))
8619 || GET_CODE (XEXP (in
, 0)) == SUBREG
8620 || MEM_P (XEXP (in
, 0)))
8621 && (REG_P (XEXP (in
, 1))
8622 || GET_CODE (XEXP (in
, 1)) == SUBREG
8623 || CONSTANT_P (XEXP (in
, 1))
8624 || MEM_P (XEXP (in
, 1))))
8626 /* We need to compute the sum of a register or a MEM and another
8627 register, constant, or MEM, and put it into the reload
8628 register. The best possible way of doing this is if the machine
8629 has a three-operand ADD insn that accepts the required operands.
8631 The simplest approach is to try to generate such an insn and see if it
8632 is recognized and matches its constraints. If so, it can be used.
8634 It might be better not to actually emit the insn unless it is valid,
8635 but we need to pass the insn as an operand to `recog' and
8636 `extract_insn' and it is simpler to emit and then delete the insn if
8637 not valid than to dummy things up. */
8641 enum insn_code code
;
8643 op0
= find_replacement (&XEXP (in
, 0));
8644 op1
= find_replacement (&XEXP (in
, 1));
8646 /* Since constraint checking is strict, commutativity won't be
8647 checked, so we need to do that here to avoid spurious failure
8648 if the add instruction is two-address and the second operand
8649 of the add is the same as the reload reg, which is frequently
8650 the case. If the insn would be A = B + A, rearrange it so
8651 it will be A = A + B as constrain_operands expects. */
8653 if (REG_P (XEXP (in
, 1))
8654 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8655 tem
= op0
, op0
= op1
, op1
= tem
;
8657 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8658 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8660 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8664 /* If that failed, we must use a conservative two-insn sequence.
8666 Use a move to copy one operand into the reload register. Prefer
8667 to reload a constant, MEM or pseudo since the move patterns can
8668 handle an arbitrary operand. If OP1 is not a constant, MEM or
8669 pseudo and OP1 is not a valid operand for an add instruction, then
8672 After reloading one of the operands into the reload register, add
8673 the reload register to the output register.
8675 If there is another way to do this for a specific machine, a
8676 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8679 code
= optab_handler (add_optab
, GET_MODE (out
));
8681 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8683 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8684 || (code
!= CODE_FOR_nothing
8685 && !insn_operand_matches (code
, 2, op1
)))
8686 tem
= op0
, op0
= op1
, op1
= tem
;
8688 gen_reload (out
, op0
, opnum
, type
);
8690 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8691 This fixes a problem on the 32K where the stack pointer cannot
8692 be used as an operand of an add insn. */
8694 if (rtx_equal_p (op0
, op1
))
8697 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8700 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8701 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8705 /* If that failed, copy the address register to the reload register.
8706 Then add the constant to the reload register. */
8708 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8709 gen_reload (out
, op1
, opnum
, type
);
8710 insn
= emit_insn (gen_add2_insn (out
, op0
));
8711 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8714 #ifdef SECONDARY_MEMORY_NEEDED
8715 /* If we need a memory location to do the move, do it that way. */
8716 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8717 (REG_P (tem1
) && REG_P (tem2
)))
8718 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8719 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8720 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8721 REGNO_REG_CLASS (REGNO (tem2
)),
8724 /* Get the memory to use and rewrite both registers to its mode. */
8725 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8727 if (GET_MODE (loc
) != GET_MODE (out
))
8728 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8730 if (GET_MODE (loc
) != GET_MODE (in
))
8731 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8733 gen_reload (loc
, in
, opnum
, type
);
8734 gen_reload (out
, loc
, opnum
, type
);
8737 else if (REG_P (out
) && UNARY_P (in
))
8744 op1
= find_replacement (&XEXP (in
, 0));
8745 if (op1
!= XEXP (in
, 0))
8746 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8748 /* First, try a plain SET. */
8749 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8753 /* If that failed, move the inner operand to the reload
8754 register, and try the same unop with the inner expression
8755 replaced with the reload register. */
8757 if (GET_MODE (op1
) != GET_MODE (out
))
8758 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8762 gen_reload (out_moded
, op1
, opnum
, type
);
8764 insn
= gen_rtx_SET (out
, gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8766 insn
= emit_insn_if_valid_for_reload (insn
);
8769 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8770 return as_a
<rtx_insn
*> (insn
);
8773 fatal_insn ("failure trying to reload:", set
);
8775 /* If IN is a simple operand, use gen_move_insn. */
8776 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8778 tem
= emit_insn (gen_move_insn (out
, in
));
8779 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8780 mark_jump_label (in
, tem
, 0);
8783 else if (targetm
.have_reload_load_address ())
8784 emit_insn (targetm
.gen_reload_load_address (out
, in
));
8786 /* Otherwise, just write (set OUT IN) and hope for the best. */
8788 emit_insn (gen_rtx_SET (out
, in
));
8790 /* Return the first insn emitted.
8791 We can not just return get_last_insn, because there may have
8792 been multiple instructions emitted. Also note that gen_move_insn may
8793 emit more than one insn itself, so we can not assume that there is one
8794 insn emitted per emit_insn_before call. */
8796 return last
? NEXT_INSN (last
) : get_insns ();
8799 /* Delete a previously made output-reload whose result we now believe
8800 is not needed. First we double-check.
8802 INSN is the insn now being processed.
8803 LAST_RELOAD_REG is the hard register number for which we want to delete
8804 the last output reload.
8805 J is the reload-number that originally used REG. The caller has made
8806 certain that reload J doesn't use REG any longer for input.
8807 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8810 delete_output_reload (rtx_insn
*insn
, int j
, int last_reload_reg
,
8813 rtx_insn
*output_reload_insn
= spill_reg_store
[last_reload_reg
];
8814 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8817 int n_inherited
= 0;
8822 /* It is possible that this reload has been only used to set another reload
8823 we eliminated earlier and thus deleted this instruction too. */
8824 if (output_reload_insn
->deleted ())
8827 /* Get the raw pseudo-register referred to. */
8829 while (GET_CODE (reg
) == SUBREG
)
8830 reg
= SUBREG_REG (reg
);
8831 substed
= reg_equiv_memory_loc (REGNO (reg
));
8833 /* This is unsafe if the operand occurs more often in the current
8834 insn than it is inherited. */
8835 for (k
= n_reloads
- 1; k
>= 0; k
--)
8837 rtx reg2
= rld
[k
].in
;
8840 if (MEM_P (reg2
) || reload_override_in
[k
])
8841 reg2
= rld
[k
].in_reg
;
8843 if (AUTO_INC_DEC
&& rld
[k
].out
&& ! rld
[k
].out_reg
)
8844 reg2
= XEXP (rld
[k
].in_reg
, 0);
8846 while (GET_CODE (reg2
) == SUBREG
)
8847 reg2
= SUBREG_REG (reg2
);
8848 if (rtx_equal_p (reg2
, reg
))
8850 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8856 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8857 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8858 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8861 n_occurrences
+= count_occurrences (PATTERN (insn
),
8862 eliminate_regs (substed
, VOIDmode
,
8864 for (rtx i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8866 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8867 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8869 if (n_occurrences
> n_inherited
)
8872 regno
= REGNO (reg
);
8873 if (regno
>= FIRST_PSEUDO_REGISTER
)
8876 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8878 /* If the pseudo-reg we are reloading is no longer referenced
8879 anywhere between the store into it and here,
8880 and we're within the same basic block, then the value can only
8881 pass through the reload reg and end up here.
8882 Otherwise, give up--return. */
8883 for (rtx_insn
*i1
= NEXT_INSN (output_reload_insn
);
8884 i1
!= insn
; i1
= NEXT_INSN (i1
))
8886 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8888 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8889 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8891 /* If this is USE in front of INSN, we only have to check that
8892 there are no more references than accounted for by inheritance. */
8893 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8895 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8896 i1
= NEXT_INSN (i1
);
8898 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8904 /* We will be deleting the insn. Remove the spill reg information. */
8905 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8907 spill_reg_store
[last_reload_reg
+ k
] = 0;
8908 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8911 /* The caller has already checked that REG dies or is set in INSN.
8912 It has also checked that we are optimizing, and thus some
8913 inaccuracies in the debugging information are acceptable.
8914 So we could just delete output_reload_insn. But in some cases
8915 we can improve the debugging information without sacrificing
8916 optimization - maybe even improving the code: See if the pseudo
8917 reg has been completely replaced with reload regs. If so, delete
8918 the store insn and forget we had a stack slot for the pseudo. */
8919 if (rld
[j
].out
!= rld
[j
].in
8920 && REG_N_DEATHS (REGNO (reg
)) == 1
8921 && REG_N_SETS (REGNO (reg
)) == 1
8922 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8923 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8927 /* We know that it was used only between here and the beginning of
8928 the current basic block. (We also know that the last use before
8929 INSN was the output reload we are thinking of deleting, but never
8930 mind that.) Search that range; see if any ref remains. */
8931 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8933 rtx set
= single_set (i2
);
8935 /* Uses which just store in the pseudo don't count,
8936 since if they are the only uses, they are dead. */
8937 if (set
!= 0 && SET_DEST (set
) == reg
)
8939 if (LABEL_P (i2
) || JUMP_P (i2
))
8941 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8942 && reg_mentioned_p (reg
, PATTERN (i2
)))
8944 /* Some other ref remains; just delete the output reload we
8946 delete_address_reloads (output_reload_insn
, insn
);
8947 delete_insn (output_reload_insn
);
8952 /* Delete the now-dead stores into this pseudo. Note that this
8953 loop also takes care of deleting output_reload_insn. */
8954 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8956 rtx set
= single_set (i2
);
8958 if (set
!= 0 && SET_DEST (set
) == reg
)
8960 delete_address_reloads (i2
, insn
);
8963 if (LABEL_P (i2
) || JUMP_P (i2
))
8967 /* For the debugging info, say the pseudo lives in this reload reg. */
8968 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8969 if (ira_conflicts_p
)
8970 /* Inform IRA about the change. */
8971 ira_mark_allocation_change (REGNO (reg
));
8972 alter_reg (REGNO (reg
), -1, false);
8976 delete_address_reloads (output_reload_insn
, insn
);
8977 delete_insn (output_reload_insn
);
8981 /* We are going to delete DEAD_INSN. Recursively delete loads of
8982 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8983 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8985 delete_address_reloads (rtx_insn
*dead_insn
, rtx_insn
*current_insn
)
8987 rtx set
= single_set (dead_insn
);
8989 rtx_insn
*prev
, *next
;
8992 rtx dst
= SET_DEST (set
);
8994 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8996 /* If we deleted the store from a reloaded post_{in,de}c expression,
8997 we can delete the matching adds. */
8998 prev
= PREV_INSN (dead_insn
);
8999 next
= NEXT_INSN (dead_insn
);
9000 if (! prev
|| ! next
)
9002 set
= single_set (next
);
9003 set2
= single_set (prev
);
9005 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
9006 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
9007 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
9009 dst
= SET_DEST (set
);
9010 if (! rtx_equal_p (dst
, SET_DEST (set2
))
9011 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
9012 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
9013 || (INTVAL (XEXP (SET_SRC (set
), 1))
9014 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
9016 delete_related_insns (prev
);
9017 delete_related_insns (next
);
9020 /* Subfunction of delete_address_reloads: process registers found in X. */
9022 delete_address_reloads_1 (rtx_insn
*dead_insn
, rtx x
, rtx_insn
*current_insn
)
9024 rtx_insn
*prev
, *i2
;
9027 enum rtx_code code
= GET_CODE (x
);
9031 const char *fmt
= GET_RTX_FORMAT (code
);
9032 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9035 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
9036 else if (fmt
[i
] == 'E')
9038 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9039 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
9046 if (spill_reg_order
[REGNO (x
)] < 0)
9049 /* Scan backwards for the insn that sets x. This might be a way back due
9051 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
9053 code
= GET_CODE (prev
);
9054 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
9058 if (reg_set_p (x
, PATTERN (prev
)))
9060 if (reg_referenced_p (x
, PATTERN (prev
)))
9063 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
9065 /* Check that PREV only sets the reload register. */
9066 set
= single_set (prev
);
9069 dst
= SET_DEST (set
);
9071 || ! rtx_equal_p (dst
, x
))
9073 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9075 /* Check if DST was used in a later insn -
9076 it might have been inherited. */
9077 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9083 if (reg_referenced_p (dst
, PATTERN (i2
)))
9085 /* If there is a reference to the register in the current insn,
9086 it might be loaded in a non-inherited reload. If no other
9087 reload uses it, that means the register is set before
9089 if (i2
== current_insn
)
9091 for (j
= n_reloads
- 1; j
>= 0; j
--)
9092 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9093 || reload_override_in
[j
] == dst
)
9095 for (j
= n_reloads
- 1; j
>= 0; j
--)
9096 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9105 /* If DST is still live at CURRENT_INSN, check if it is used for
9106 any reload. Note that even if CURRENT_INSN sets DST, we still
9107 have to check the reloads. */
9108 if (i2
== current_insn
)
9110 for (j
= n_reloads
- 1; j
>= 0; j
--)
9111 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9112 || reload_override_in
[j
] == dst
)
9114 /* ??? We can't finish the loop here, because dst might be
9115 allocated to a pseudo in this block if no reload in this
9116 block needs any of the classes containing DST - see
9117 spill_hard_reg. There is no easy way to tell this, so we
9118 have to scan till the end of the basic block. */
9120 if (reg_set_p (dst
, PATTERN (i2
)))
9124 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9125 reg_reloaded_contents
[REGNO (dst
)] = -1;
9129 /* Output reload-insns to reload VALUE into RELOADREG.
9130 VALUE is an autoincrement or autodecrement RTX whose operand
9131 is a register or memory location;
9132 so reloading involves incrementing that location.
9133 IN is either identical to VALUE, or some cheaper place to reload from.
9135 INC_AMOUNT is the number to increment or decrement by (always positive).
9136 This cannot be deduced from VALUE. */
9139 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9141 /* REG or MEM to be copied and incremented. */
9142 rtx incloc
= find_replacement (&XEXP (value
, 0));
9143 /* Nonzero if increment after copying. */
9144 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9145 || GET_CODE (value
) == POST_MODIFY
);
9150 rtx real_in
= in
== value
? incloc
: in
;
9152 /* No hard register is equivalent to this register after
9153 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9154 we could inc/dec that register as well (maybe even using it for
9155 the source), but I'm not sure it's worth worrying about. */
9157 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9159 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9161 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9162 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9166 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9167 inc_amount
= -inc_amount
;
9169 inc
= GEN_INT (inc_amount
);
9172 /* If this is post-increment, first copy the location to the reload reg. */
9173 if (post
&& real_in
!= reloadreg
)
9174 emit_insn (gen_move_insn (reloadreg
, real_in
));
9178 /* See if we can directly increment INCLOC. Use a method similar to
9179 that in gen_reload. */
9181 last
= get_last_insn ();
9182 add_insn
= emit_insn (gen_rtx_SET (incloc
,
9183 gen_rtx_PLUS (GET_MODE (incloc
),
9186 code
= recog_memoized (add_insn
);
9189 extract_insn (add_insn
);
9190 if (constrain_operands (1, get_enabled_alternatives (add_insn
)))
9192 /* If this is a pre-increment and we have incremented the value
9193 where it lives, copy the incremented value to RELOADREG to
9194 be used as an address. */
9197 emit_insn (gen_move_insn (reloadreg
, incloc
));
9201 delete_insns_since (last
);
9204 /* If couldn't do the increment directly, must increment in RELOADREG.
9205 The way we do this depends on whether this is pre- or post-increment.
9206 For pre-increment, copy INCLOC to the reload register, increment it
9207 there, then save back. */
9211 if (in
!= reloadreg
)
9212 emit_insn (gen_move_insn (reloadreg
, real_in
));
9213 emit_insn (gen_add2_insn (reloadreg
, inc
));
9214 emit_insn (gen_move_insn (incloc
, reloadreg
));
9219 Because this might be a jump insn or a compare, and because RELOADREG
9220 may not be available after the insn in an input reload, we must do
9221 the incrementation before the insn being reloaded for.
9223 We have already copied IN to RELOADREG. Increment the copy in
9224 RELOADREG, save that back, then decrement RELOADREG so it has
9225 the original value. */
9227 emit_insn (gen_add2_insn (reloadreg
, inc
));
9228 emit_insn (gen_move_insn (incloc
, reloadreg
));
9229 if (CONST_INT_P (inc
))
9230 emit_insn (gen_add2_insn (reloadreg
,
9231 gen_int_mode (-INTVAL (inc
),
9232 GET_MODE (reloadreg
))));
9234 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9239 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
9241 enum rtx_code code
= GET_CODE (x
);
9245 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9247 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9251 /* Scan all the operand sub-expressions. */
9252 fmt
= GET_RTX_FORMAT (code
);
9253 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9256 add_auto_inc_notes (insn
, XEXP (x
, i
));
9257 else if (fmt
[i
] == 'E')
9258 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9259 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));