1 ;; e500 SPE description
2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011, 2012
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
35 (E500_CR_IOR_COMPARE 1018)
38 ;; Modes using a 64-bit register.
39 (define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI])
41 ;; Likewise, but allow TFmode (two registers) as well.
42 (define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
45 (define_mode_iterator DITI [DI TI])
47 (define_insn "*negsf2_gpr"
48 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
49 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
50 "TARGET_HARD_FLOAT && !TARGET_FPRS"
52 [(set_attr "type" "fpsimple")])
54 (define_insn "*abssf2_gpr"
55 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
56 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
57 "TARGET_HARD_FLOAT && !TARGET_FPRS"
59 [(set_attr "type" "fpsimple")])
61 (define_insn "*nabssf2_gpr"
62 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
63 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
64 "TARGET_HARD_FLOAT && !TARGET_FPRS"
66 [(set_attr "type" "fpsimple")])
68 (define_insn "*addsf3_gpr"
69 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
70 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
71 (match_operand:SF 2 "gpc_reg_operand" "r")))]
72 "TARGET_HARD_FLOAT && !TARGET_FPRS"
74 [(set_attr "type" "fp")])
76 (define_insn "*subsf3_gpr"
77 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
78 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
79 (match_operand:SF 2 "gpc_reg_operand" "r")))]
80 "TARGET_HARD_FLOAT && !TARGET_FPRS"
82 [(set_attr "type" "fp")])
84 (define_insn "*mulsf3_gpr"
85 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
86 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
87 (match_operand:SF 2 "gpc_reg_operand" "r")))]
88 "TARGET_HARD_FLOAT && !TARGET_FPRS"
90 [(set_attr "type" "fp")])
92 (define_insn "*divsf3_gpr"
93 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
94 (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
95 (match_operand:SF 2 "gpc_reg_operand" "r")))]
96 "TARGET_HARD_FLOAT && !TARGET_FPRS"
98 [(set_attr "type" "vecfdiv")])
100 ;; Floating point conversion instructions.
102 (define_insn "spe_fixuns_truncdfsi2"
103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
104 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
105 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
107 [(set_attr "type" "fp")])
109 (define_insn "spe_extendsfdf2"
110 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
111 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
112 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
114 [(set_attr "type" "fp")])
116 (define_insn "spe_fixuns_truncsfsi2"
117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
118 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
119 "TARGET_HARD_FLOAT && !TARGET_FPRS"
121 [(set_attr "type" "fp")])
123 (define_insn "spe_fix_truncsfsi2"
124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
125 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
126 "TARGET_HARD_FLOAT && !TARGET_FPRS"
128 [(set_attr "type" "fp")])
130 (define_insn "spe_fix_truncdfsi2"
131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
132 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
133 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
135 [(set_attr "type" "fp")])
137 (define_insn "spe_floatunssisf2"
138 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
139 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
140 "TARGET_HARD_FLOAT && !TARGET_FPRS"
142 [(set_attr "type" "fp")])
144 (define_insn "spe_floatunssidf2"
145 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
146 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
147 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
149 [(set_attr "type" "fp")])
151 (define_insn "spe_floatsisf2"
152 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
153 (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
154 "TARGET_HARD_FLOAT && !TARGET_FPRS"
156 [(set_attr "type" "fp")])
158 (define_insn "spe_floatsidf2"
159 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
160 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
161 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
163 [(set_attr "type" "fp")])
165 ;; SPE SIMD instructions
167 (define_insn "absv2si2"
168 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
169 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
172 [(set_attr "type" "vecsimple")
173 (set_attr "length" "4")])
175 (define_insn "spe_evandc"
176 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
177 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
178 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
181 [(set_attr "type" "vecsimple")
182 (set_attr "length" "4")])
184 (define_insn "andv2si3"
185 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
186 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
187 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
190 [(set_attr "type" "vecsimple")
191 (set_attr "length" "4")])
193 ;; Vector compare instructions
195 (define_insn "spe_evcmpeq"
196 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
197 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
198 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
201 [(set_attr "type" "veccmp")
202 (set_attr "length" "4")])
204 (define_insn "spe_evcmpgts"
205 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
206 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
207 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
210 [(set_attr "type" "veccmp")
211 (set_attr "length" "4")])
213 (define_insn "spe_evcmpgtu"
214 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
215 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
216 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
219 [(set_attr "type" "veccmp")
220 (set_attr "length" "4")])
222 (define_insn "spe_evcmplts"
223 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
224 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
225 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
228 [(set_attr "type" "veccmp")
229 (set_attr "length" "4")])
231 (define_insn "spe_evcmpltu"
232 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
233 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
234 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
237 [(set_attr "type" "veccmp")
238 (set_attr "length" "4")])
240 ;; Floating point vector compare instructions
242 (define_insn "spe_evfscmpeq"
243 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
244 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
245 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
246 (clobber (reg:SI SPEFSCR_REGNO))]
249 [(set_attr "type" "veccmp")
250 (set_attr "length" "4")])
252 (define_insn "spe_evfscmpgt"
253 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
254 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
255 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
256 (clobber (reg:SI SPEFSCR_REGNO))]
259 [(set_attr "type" "veccmp")
260 (set_attr "length" "4")])
262 (define_insn "spe_evfscmplt"
263 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
264 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
265 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
266 (clobber (reg:SI SPEFSCR_REGNO))]
269 [(set_attr "type" "veccmp")
270 (set_attr "length" "4")])
272 (define_insn "spe_evfststeq"
273 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
274 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
275 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
278 [(set_attr "type" "veccmp")
279 (set_attr "length" "4")])
281 (define_insn "spe_evfststgt"
282 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
283 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
284 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
287 [(set_attr "type" "veccmp")
288 (set_attr "length" "4")])
290 (define_insn "spe_evfststlt"
291 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
292 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
293 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
296 [(set_attr "type" "veccmp")
297 (set_attr "length" "4")])
299 ;; End of vector compare instructions
301 (define_insn "spe_evcntlsw"
302 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
303 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
306 [(set_attr "type" "vecsimple")
307 (set_attr "length" "4")])
309 (define_insn "spe_evcntlzw"
310 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
311 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
314 [(set_attr "type" "vecsimple")
315 (set_attr "length" "4")])
317 (define_insn "spe_eveqv"
318 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
319 (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
320 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
323 [(set_attr "type" "vecsimple")
324 (set_attr "length" "4")])
326 (define_insn "spe_evextsb"
327 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
328 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
331 [(set_attr "type" "vecsimple")
332 (set_attr "length" "4")])
334 (define_insn "spe_evextsh"
335 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
336 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
339 [(set_attr "type" "vecsimple")
340 (set_attr "length" "4")])
342 (define_insn "spe_evlhhesplat"
343 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
344 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
345 (match_operand:QI 2 "immediate_operand" "i"))))
346 (unspec [(const_int 0)] 509)]
347 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
348 "evlhhesplat %0,%2*2(%1)"
349 [(set_attr "type" "vecload")
350 (set_attr "length" "4")])
352 (define_insn "spe_evlhhesplatx"
353 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
354 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
355 (match_operand:SI 2 "gpc_reg_operand" "r"))))
356 (unspec [(const_int 0)] 510)]
358 "evlhhesplatx %0,%1,%2"
359 [(set_attr "type" "vecload")
360 (set_attr "length" "4")])
362 (define_insn "spe_evlhhossplat"
363 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
364 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
365 (match_operand:QI 2 "immediate_operand" "i"))))
366 (unspec [(const_int 0)] 511)]
367 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
368 "evlhhossplat %0,%2*2(%1)"
369 [(set_attr "type" "vecload")
370 (set_attr "length" "4")])
372 (define_insn "spe_evlhhossplatx"
373 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
374 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
375 (match_operand:SI 2 "gpc_reg_operand" "r"))))
376 (unspec [(const_int 0)] 512)]
378 "evlhhossplatx %0,%1,%2"
379 [(set_attr "type" "vecload")
380 (set_attr "length" "4")])
382 (define_insn "spe_evlhhousplat"
383 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
384 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
385 (match_operand:QI 2 "immediate_operand" "i"))))
386 (unspec [(const_int 0)] 513)]
387 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
388 "evlhhousplat %0,%2*2(%1)"
389 [(set_attr "type" "vecload")
390 (set_attr "length" "4")])
392 (define_insn "spe_evlhhousplatx"
393 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
394 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
395 (match_operand:SI 2 "gpc_reg_operand" "r"))))
396 (unspec [(const_int 0)] 514)]
398 "evlhhousplatx %0,%1,%2"
399 [(set_attr "type" "vecload")
400 (set_attr "length" "4")])
402 (define_insn "spe_evlwhsplat"
403 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
404 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
405 (match_operand:QI 2 "immediate_operand" "i"))))
406 (unspec [(const_int 0)] 515)]
407 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
408 "evlwhsplat %0,%2*4(%1)"
409 [(set_attr "type" "vecload")
410 (set_attr "length" "4")])
412 (define_insn "spe_evlwhsplatx"
413 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
414 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
415 (match_operand:SI 2 "gpc_reg_operand" "r"))))
416 (unspec [(const_int 0)] 516)]
418 "evlwhsplatx %0,%1,%2"
419 [(set_attr "type" "vecload")
420 (set_attr "length" "4")])
422 (define_insn "spe_evlwwsplat"
423 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
424 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
425 (match_operand:QI 2 "immediate_operand" "i"))))
426 (unspec [(const_int 0)] 517)]
427 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
428 "evlwwsplat %0,%2*4(%1)"
429 [(set_attr "type" "vecload")
430 (set_attr "length" "4")])
432 (define_insn "spe_evlwwsplatx"
433 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
434 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
435 (match_operand:SI 2 "gpc_reg_operand" "r"))))
436 (unspec [(const_int 0)] 518)]
438 "evlwwsplatx %0,%1,%2"
439 [(set_attr "type" "vecload")
440 (set_attr "length" "4")])
442 (define_insn "spe_evmergehi"
443 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
446 (match_operand:V2SI 1 "gpc_reg_operand" "r")
447 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
448 (parallel [(const_int 0) (const_int 2)])))]
451 [(set_attr "type" "vecsimple")
452 (set_attr "length" "4")])
454 (define_insn "spe_evmergehilo"
455 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
458 (match_operand:V2SI 1 "gpc_reg_operand" "r")
459 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
460 (parallel [(const_int 0) (const_int 3)])))]
462 "evmergehilo %0,%1,%2"
463 [(set_attr "type" "vecsimple")
464 (set_attr "length" "4")])
466 (define_insn "spe_evmergelo"
467 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
470 (match_operand:V2SI 1 "gpc_reg_operand" "r")
471 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
472 (parallel [(const_int 1) (const_int 3)])))]
475 [(set_attr "type" "vecsimple")
476 (set_attr "length" "4")])
478 (define_insn "spe_evmergelohi"
479 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
482 (match_operand:V2SI 1 "gpc_reg_operand" "r")
483 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
484 (parallel [(const_int 1) (const_int 2)])))]
486 "evmergelohi %0,%1,%2"
487 [(set_attr "type" "vecsimple")
488 (set_attr "length" "4")])
490 (define_expand "vec_perm_constv2si"
491 [(match_operand:V2SI 0 "gpc_reg_operand" "")
492 (match_operand:V2SI 1 "gpc_reg_operand" "")
493 (match_operand:V2SI 2 "gpc_reg_operand" "")
494 (match_operand:V2SI 3 "" "")]
497 if (rs6000_expand_vec_perm_const (operands))
503 (define_insn "spe_evnand"
504 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
505 (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
506 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
509 [(set_attr "type" "vecsimple")
510 (set_attr "length" "4")])
512 (define_insn "negv2si2"
513 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
514 (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
517 [(set_attr "type" "vecsimple")
518 (set_attr "length" "4")])
520 (define_insn "spe_evnor"
521 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
522 (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
523 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
526 [(set_attr "type" "vecsimple")
527 (set_attr "length" "4")])
529 (define_insn "spe_evorc"
530 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
531 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
532 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
535 [(set_attr "type" "vecsimple")
536 (set_attr "length" "4")])
538 (define_insn "spe_evor"
539 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
540 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
541 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
544 [(set_attr "type" "vecsimple")
545 (set_attr "length" "4")])
547 (define_insn "spe_evrlwi"
548 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
549 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
550 (match_operand:QI 2 "immediate_operand" "i")] 519))]
553 [(set_attr "type" "vecsimple")
554 (set_attr "length" "4")])
556 (define_insn "spe_evrlw"
557 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
558 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
559 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
562 [(set_attr "type" "veccomplex")
563 (set_attr "length" "4")])
565 (define_insn "spe_evrndw"
566 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
567 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
570 [(set_attr "type" "vecsimple")
571 (set_attr "length" "4")])
573 (define_insn "spe_evsel"
574 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
575 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
576 (match_operand:V2SI 2 "gpc_reg_operand" "r")
577 (match_operand:CC 3 "cc_reg_operand" "y")] 522))]
580 [(set_attr "type" "veccmp")
581 (set_attr "length" "4")])
583 (define_insn "spe_evsel_fs"
584 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
585 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
586 (match_operand:V2SF 2 "gpc_reg_operand" "r")
587 (match_operand:CC 3 "cc_reg_operand" "y")] 725))]
590 [(set_attr "type" "veccmp")
591 (set_attr "length" "4")])
593 (define_insn "spe_evslwi"
594 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
595 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
596 (match_operand:QI 2 "immediate_operand" "i")]
600 [(set_attr "type" "vecsimple")
601 (set_attr "length" "4")])
603 (define_insn "spe_evslw"
604 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
605 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
606 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
609 [(set_attr "type" "vecsimple")
610 (set_attr "length" "4")])
612 (define_insn "spe_evsrwis"
613 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
614 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
615 (match_operand:QI 2 "immediate_operand" "i")]
619 [(set_attr "type" "vecsimple")
620 (set_attr "length" "4")])
622 (define_insn "spe_evsrwiu"
623 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
624 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
625 (match_operand:QI 2 "immediate_operand" "i")]
629 [(set_attr "type" "vecsimple")
630 (set_attr "length" "4")])
632 (define_insn "spe_evsrws"
633 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
634 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
635 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
638 [(set_attr "type" "vecsimple")
639 (set_attr "length" "4")])
641 (define_insn "spe_evsrwu"
642 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
643 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
644 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
647 [(set_attr "type" "vecsimple")
648 (set_attr "length" "4")])
652 (define_insn "xorv2si3"
653 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
654 (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
655 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
658 [(set_attr "type" "vecsimple")
659 (set_attr "length" "4")])
661 (define_insn "xorv4hi3"
662 [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
663 (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
664 (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
667 [(set_attr "type" "vecsimple")
668 (set_attr "length" "4")])
670 (define_insn "xorv1di3"
671 [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
672 (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
673 (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
676 [(set_attr "type" "vecsimple")
677 (set_attr "length" "4")])
679 ;; end of vector xors
681 (define_insn "spe_evfsabs"
682 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
683 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
686 [(set_attr "type" "vecsimple")
687 (set_attr "length" "4")])
689 (define_insn "spe_evfsadd"
690 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
691 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
692 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
693 (clobber (reg:SI SPEFSCR_REGNO))]
696 [(set_attr "type" "vecfloat")
697 (set_attr "length" "4")])
699 (define_insn "spe_evfscfsf"
700 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
701 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
704 [(set_attr "type" "vecfloat")
705 (set_attr "length" "4")])
707 (define_insn "spe_evfscfsi"
708 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
709 (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
712 [(set_attr "type" "vecfloat")
713 (set_attr "length" "4")])
715 (define_insn "spe_evfscfuf"
716 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
717 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
720 [(set_attr "type" "vecfloat")
721 (set_attr "length" "4")])
723 (define_insn "spe_evfscfui"
724 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
725 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
728 [(set_attr "type" "vecfloat")
729 (set_attr "length" "4")])
731 (define_insn "spe_evfsctsf"
732 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
733 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
736 [(set_attr "type" "vecfloat")
737 (set_attr "length" "4")])
739 (define_insn "spe_evfsctsi"
740 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
741 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
744 [(set_attr "type" "vecfloat")
745 (set_attr "length" "4")])
747 (define_insn "spe_evfsctsiz"
748 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
749 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
752 [(set_attr "type" "vecfloat")
753 (set_attr "length" "4")])
755 (define_insn "spe_evfsctuf"
756 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
757 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
760 [(set_attr "type" "vecfloat")
761 (set_attr "length" "4")])
763 (define_insn "spe_evfsctui"
764 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
765 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
768 [(set_attr "type" "vecfloat")
769 (set_attr "length" "4")])
771 (define_insn "spe_evfsctuiz"
772 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
773 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
776 [(set_attr "type" "vecfloat")
777 (set_attr "length" "4")])
779 (define_insn "spe_evfsdiv"
780 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
781 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
782 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
783 (clobber (reg:SI SPEFSCR_REGNO))]
786 [(set_attr "type" "vecfdiv")
787 (set_attr "length" "4")])
789 (define_insn "spe_evfsmul"
790 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
791 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
792 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
793 (clobber (reg:SI SPEFSCR_REGNO))]
796 [(set_attr "type" "vecfloat")
797 (set_attr "length" "4")])
799 (define_insn "spe_evfsnabs"
800 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
801 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
804 [(set_attr "type" "vecsimple")
805 (set_attr "length" "4")])
807 (define_insn "spe_evfsneg"
808 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
809 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
812 [(set_attr "type" "vecsimple")
813 (set_attr "length" "4")])
815 (define_insn "spe_evfssub"
816 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
817 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
818 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
819 (clobber (reg:SI SPEFSCR_REGNO))]
822 [(set_attr "type" "vecfloat")
823 (set_attr "length" "4")])
825 ;; SPE SIMD load instructions.
827 ;; Only the hardware engineer who designed the SPE understands the
828 ;; plethora of load and store instructions ;-). We have no way of
829 ;; differentiating between them with RTL so use an unspec of const_int 0
830 ;; to avoid identical RTL.
832 (define_insn "spe_evldd"
833 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
834 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
835 (match_operand:QI 2 "immediate_operand" "i"))))
836 (unspec [(const_int 0)] 544)]
837 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
839 [(set_attr "type" "vecload")
840 (set_attr "length" "4")])
842 (define_insn "spe_evlddx"
843 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
844 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
845 (match_operand:SI 2 "gpc_reg_operand" "r"))))
846 (unspec [(const_int 0)] 545)]
849 [(set_attr "type" "vecload")
850 (set_attr "length" "4")])
852 (define_insn "spe_evldh"
853 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
854 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
855 (match_operand:QI 2 "immediate_operand" "i"))))
856 (unspec [(const_int 0)] 546)]
857 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
859 [(set_attr "type" "vecload")
860 (set_attr "length" "4")])
862 (define_insn "spe_evldhx"
863 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
864 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
865 (match_operand:SI 2 "gpc_reg_operand" "r"))))
866 (unspec [(const_int 0)] 547)]
869 [(set_attr "type" "vecload")
870 (set_attr "length" "4")])
872 (define_insn "spe_evldw"
873 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
874 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
875 (match_operand:QI 2 "immediate_operand" "i"))))
876 (unspec [(const_int 0)] 548)]
877 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
879 [(set_attr "type" "vecload")
880 (set_attr "length" "4")])
882 (define_insn "spe_evldwx"
883 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
884 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
885 (match_operand:SI 2 "gpc_reg_operand" "r"))))
886 (unspec [(const_int 0)] 549)]
889 [(set_attr "type" "vecload")
890 (set_attr "length" "4")])
892 (define_insn "spe_evlwhe"
893 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
894 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
895 (match_operand:QI 2 "immediate_operand" "i"))))
896 (unspec [(const_int 0)] 550)]
897 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
899 [(set_attr "type" "vecload")
900 (set_attr "length" "4")])
902 (define_insn "spe_evlwhex"
903 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
904 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
905 (match_operand:SI 2 "gpc_reg_operand" "r"))))
906 (unspec [(const_int 0)] 551)]
909 [(set_attr "type" "vecload")
910 (set_attr "length" "4")])
912 (define_insn "spe_evlwhos"
913 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
914 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
915 (match_operand:QI 2 "immediate_operand" "i"))))
916 (unspec [(const_int 0)] 552)]
917 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
918 "evlwhos %0,%2*4(%1)"
919 [(set_attr "type" "vecload")
920 (set_attr "length" "4")])
922 (define_insn "spe_evlwhosx"
923 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
924 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
925 (match_operand:SI 2 "gpc_reg_operand" "r"))))
926 (unspec [(const_int 0)] 553)]
929 [(set_attr "type" "vecload")
930 (set_attr "length" "4")])
932 (define_insn "spe_evlwhou"
933 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
934 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
935 (match_operand:QI 2 "immediate_operand" "i"))))
936 (unspec [(const_int 0)] 554)]
937 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
938 "evlwhou %0,%2*4(%1)"
939 [(set_attr "type" "vecload")
940 (set_attr "length" "4")])
942 (define_insn "spe_evlwhoux"
943 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
944 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
945 (match_operand:SI 2 "gpc_reg_operand" "r"))))
946 (unspec [(const_int 0)] 555)]
949 [(set_attr "type" "vecload")
950 (set_attr "length" "4")])
952 (define_insn "spe_brinc"
953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
954 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
955 (match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
958 [(set_attr "type" "brinc")
959 (set_attr "length" "4")])
961 (define_insn "spe_evmhegsmfaa"
962 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
963 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
964 (match_operand:V2SI 2 "gpc_reg_operand" "r")
965 (reg:V2SI SPE_ACC_REGNO)] 557))
966 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
968 "evmhegsmfaa %0,%1,%2"
969 [(set_attr "type" "veccomplex")
970 (set_attr "length" "4")])
972 (define_insn "spe_evmhegsmfan"
973 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
974 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
975 (match_operand:V2SI 2 "gpc_reg_operand" "r")
976 (reg:V2SI SPE_ACC_REGNO)] 558))
977 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
979 "evmhegsmfan %0,%1,%2"
980 [(set_attr "type" "veccomplex")
981 (set_attr "length" "4")])
983 (define_insn "spe_evmhegsmiaa"
984 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
985 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
986 (match_operand:V2SI 2 "gpc_reg_operand" "r")
987 (reg:V2SI SPE_ACC_REGNO)] 559))
988 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
990 "evmhegsmiaa %0,%1,%2"
991 [(set_attr "type" "veccomplex")
992 (set_attr "length" "4")])
994 (define_insn "spe_evmhegsmian"
995 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
996 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
997 (match_operand:V2SI 2 "gpc_reg_operand" "r")
998 (reg:V2SI SPE_ACC_REGNO)] 560))
999 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1001 "evmhegsmian %0,%1,%2"
1002 [(set_attr "type" "veccomplex")
1003 (set_attr "length" "4")])
1005 (define_insn "spe_evmhegumiaa"
1006 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1007 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1008 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1009 (reg:V2SI SPE_ACC_REGNO)] 561))
1010 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1012 "evmhegumiaa %0,%1,%2"
1013 [(set_attr "type" "veccomplex")
1014 (set_attr "length" "4")])
1016 (define_insn "spe_evmhegumian"
1017 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1018 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1019 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1020 (reg:V2SI SPE_ACC_REGNO)] 562))
1021 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1023 "evmhegumian %0,%1,%2"
1024 [(set_attr "type" "veccomplex")
1025 (set_attr "length" "4")])
1027 (define_insn "spe_evmhesmfaaw"
1028 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1029 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1030 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1031 (reg:V2SI SPE_ACC_REGNO)] 563))
1032 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1034 "evmhesmfaaw %0,%1,%2"
1035 [(set_attr "type" "veccomplex")
1036 (set_attr "length" "4")])
1038 (define_insn "spe_evmhesmfanw"
1039 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1040 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1041 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1042 (reg:V2SI SPE_ACC_REGNO)] 564))
1043 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1045 "evmhesmfanw %0,%1,%2"
1046 [(set_attr "type" "veccomplex")
1047 (set_attr "length" "4")])
1049 (define_insn "spe_evmhesmfa"
1050 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1051 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1052 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
1053 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1055 "evmhesmfa %0,%1,%2"
1056 [(set_attr "type" "veccomplex")
1057 (set_attr "length" "4")])
1059 (define_insn "spe_evmhesmf"
1060 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1061 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1062 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
1065 [(set_attr "type" "veccomplex")
1066 (set_attr "length" "4")])
1068 (define_insn "spe_evmhesmiaaw"
1069 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1070 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1071 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1072 (reg:V2SI SPE_ACC_REGNO)] 567))
1073 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1075 "evmhesmiaaw %0,%1,%2"
1076 [(set_attr "type" "veccomplex")
1077 (set_attr "length" "4")])
1079 (define_insn "spe_evmhesmianw"
1080 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1081 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1082 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1083 (reg:V2SI SPE_ACC_REGNO)] 568))
1084 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1086 "evmhesmianw %0,%1,%2"
1087 [(set_attr "type" "veccomplex")
1088 (set_attr "length" "4")])
1090 (define_insn "spe_evmhesmia"
1091 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1092 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1093 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
1094 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1096 "evmhesmia %0,%1,%2"
1097 [(set_attr "type" "veccomplex")
1098 (set_attr "length" "4")])
1100 (define_insn "spe_evmhesmi"
1101 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1102 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1103 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
1106 [(set_attr "type" "veccomplex")
1107 (set_attr "length" "4")])
1109 (define_insn "spe_evmhessfaaw"
1110 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1111 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1112 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1113 (reg:V2SI SPE_ACC_REGNO)] 571))
1114 (clobber (reg:SI SPEFSCR_REGNO))
1115 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1117 "evmhessfaaw %0,%1,%2"
1118 [(set_attr "type" "veccomplex")
1119 (set_attr "length" "4")])
1121 (define_insn "spe_evmhessfanw"
1122 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1123 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1124 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1125 (reg:V2SI SPE_ACC_REGNO)] 572))
1126 (clobber (reg:SI SPEFSCR_REGNO))
1127 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1129 "evmhessfanw %0,%1,%2"
1130 [(set_attr "type" "veccomplex")
1131 (set_attr "length" "4")])
1133 (define_insn "spe_evmhessfa"
1134 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1135 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1136 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
1137 (clobber (reg:SI SPEFSCR_REGNO))
1138 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1140 "evmhessfa %0,%1,%2"
1141 [(set_attr "type" "veccomplex")
1142 (set_attr "length" "4")])
1144 (define_insn "spe_evmhessf"
1145 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1146 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1147 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
1148 (clobber (reg:SI SPEFSCR_REGNO))]
1151 [(set_attr "type" "veccomplex")
1152 (set_attr "length" "4")])
1154 (define_insn "spe_evmhessiaaw"
1155 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1156 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1157 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1158 (reg:V2SI SPE_ACC_REGNO)] 575))
1159 (clobber (reg:SI SPEFSCR_REGNO))
1160 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1162 "evmhessiaaw %0,%1,%2"
1163 [(set_attr "type" "veccomplex")
1164 (set_attr "length" "4")])
1166 (define_insn "spe_evmhessianw"
1167 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1168 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1169 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1170 (reg:V2SI SPE_ACC_REGNO)] 576))
1171 (clobber (reg:SI SPEFSCR_REGNO))
1172 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1174 "evmhessianw %0,%1,%2"
1175 [(set_attr "type" "veccomplex")
1176 (set_attr "length" "4")])
1178 (define_insn "spe_evmheumiaaw"
1179 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1180 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1181 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1182 (reg:V2SI SPE_ACC_REGNO)] 577))
1183 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1185 "evmheumiaaw %0,%1,%2"
1186 [(set_attr "type" "veccomplex")
1187 (set_attr "length" "4")])
1189 (define_insn "spe_evmheumianw"
1190 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1191 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1192 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1193 (reg:V2SI SPE_ACC_REGNO)] 578))
1194 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1196 "evmheumianw %0,%1,%2"
1197 [(set_attr "type" "veccomplex")
1198 (set_attr "length" "4")])
1200 (define_insn "spe_evmheumia"
1201 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1202 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1203 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
1204 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1206 "evmheumia %0,%1,%2"
1207 [(set_attr "type" "veccomplex")
1208 (set_attr "length" "4")])
1210 (define_insn "spe_evmheumi"
1211 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1212 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1213 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
1216 [(set_attr "type" "veccomplex")
1217 (set_attr "length" "4")])
1219 (define_insn "spe_evmheusiaaw"
1220 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1221 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1222 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1223 (reg:V2SI SPE_ACC_REGNO)] 581))
1224 (clobber (reg:SI SPEFSCR_REGNO))
1225 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1227 "evmheusiaaw %0,%1,%2"
1228 [(set_attr "type" "veccomplex")
1229 (set_attr "length" "4")])
1231 (define_insn "spe_evmheusianw"
1232 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1233 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1234 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1235 (reg:V2SI SPE_ACC_REGNO)] 582))
1236 (clobber (reg:SI SPEFSCR_REGNO))
1237 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1239 "evmheusianw %0,%1,%2"
1240 [(set_attr "type" "veccomplex")
1241 (set_attr "length" "4")])
1243 (define_insn "spe_evmhogsmfaa"
1244 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1245 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1246 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1247 (reg:V2SI SPE_ACC_REGNO)] 583))
1248 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1250 "evmhogsmfaa %0,%1,%2"
1251 [(set_attr "type" "veccomplex")
1252 (set_attr "length" "4")])
1254 (define_insn "spe_evmhogsmfan"
1255 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1256 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1257 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1258 (reg:V2SI SPE_ACC_REGNO)] 584))
1259 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1261 "evmhogsmfan %0,%1,%2"
1262 [(set_attr "type" "veccomplex")
1263 (set_attr "length" "4")])
1265 (define_insn "spe_evmhogsmiaa"
1266 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1267 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1268 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1269 (reg:V2SI SPE_ACC_REGNO)] 585))
1270 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1272 "evmhogsmiaa %0,%1,%2"
1273 [(set_attr "type" "veccomplex")
1274 (set_attr "length" "4")])
1276 (define_insn "spe_evmhogsmian"
1277 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1278 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1279 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1280 (reg:V2SI SPE_ACC_REGNO)] 586))
1281 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1283 "evmhogsmian %0,%1,%2"
1284 [(set_attr "type" "veccomplex")
1285 (set_attr "length" "4")])
1287 (define_insn "spe_evmhogumiaa"
1288 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1289 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1290 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1291 (reg:V2SI SPE_ACC_REGNO)] 587))
1292 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1294 "evmhogumiaa %0,%1,%2"
1295 [(set_attr "type" "veccomplex")
1296 (set_attr "length" "4")])
1298 (define_insn "spe_evmhogumian"
1299 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1300 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1301 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1302 (reg:V2SI SPE_ACC_REGNO)] 588))
1303 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1305 "evmhogumian %0,%1,%2"
1306 [(set_attr "type" "veccomplex")
1307 (set_attr "length" "4")])
1309 (define_insn "spe_evmhosmfaaw"
1310 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1311 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1312 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1313 (reg:V2SI SPE_ACC_REGNO)] 589))
1314 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1316 "evmhosmfaaw %0,%1,%2"
1317 [(set_attr "type" "veccomplex")
1318 (set_attr "length" "4")])
1320 (define_insn "spe_evmhosmfanw"
1321 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1322 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1323 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1324 (reg:V2SI SPE_ACC_REGNO)] 590))
1325 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1327 "evmhosmfanw %0,%1,%2"
1328 [(set_attr "type" "veccomplex")
1329 (set_attr "length" "4")])
1331 (define_insn "spe_evmhosmfa"
1332 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1333 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1334 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
1336 "evmhosmfa %0,%1,%2"
1337 [(set_attr "type" "veccomplex")
1338 (set_attr "length" "4")])
1340 (define_insn "spe_evmhosmf"
1341 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1342 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1343 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
1344 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1347 [(set_attr "type" "veccomplex")
1348 (set_attr "length" "4")])
1350 (define_insn "spe_evmhosmiaaw"
1351 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1352 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1353 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1354 (reg:V2SI SPE_ACC_REGNO)] 593))
1355 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1357 "evmhosmiaaw %0,%1,%2"
1358 [(set_attr "type" "veccomplex")
1359 (set_attr "length" "4")])
1361 (define_insn "spe_evmhosmianw"
1362 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1363 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1364 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1365 (reg:V2SI SPE_ACC_REGNO)] 594))
1366 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1368 "evmhosmianw %0,%1,%2"
1369 [(set_attr "type" "veccomplex")
1370 (set_attr "length" "4")])
1372 (define_insn "spe_evmhosmia"
1373 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1374 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1375 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
1376 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1378 "evmhosmia %0,%1,%2"
1379 [(set_attr "type" "veccomplex")
1380 (set_attr "length" "4")])
1382 (define_insn "spe_evmhosmi"
1383 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1384 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1385 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
1388 [(set_attr "type" "veccomplex")
1389 (set_attr "length" "4")])
1391 (define_insn "spe_evmhossfaaw"
1392 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1393 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1394 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1395 (reg:V2SI SPE_ACC_REGNO)] 597))
1396 (clobber (reg:SI SPEFSCR_REGNO))
1397 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1399 "evmhossfaaw %0,%1,%2"
1400 [(set_attr "type" "veccomplex")
1401 (set_attr "length" "4")])
1403 (define_insn "spe_evmhossfanw"
1404 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1405 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1406 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1407 (reg:V2SI SPE_ACC_REGNO)] 598))
1408 (clobber (reg:SI SPEFSCR_REGNO))
1409 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1411 "evmhossfanw %0,%1,%2"
1412 [(set_attr "type" "veccomplex")
1413 (set_attr "length" "4")])
1415 (define_insn "spe_evmhossfa"
1416 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1417 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1418 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1419 (reg:V2SI SPE_ACC_REGNO)] 599))
1420 (clobber (reg:SI SPEFSCR_REGNO))
1421 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1423 "evmhossfa %0,%1,%2"
1424 [(set_attr "type" "veccomplex")
1425 (set_attr "length" "4")])
1427 (define_insn "spe_evmhossf"
1428 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1429 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1430 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
1431 (clobber (reg:SI SPEFSCR_REGNO))]
1434 [(set_attr "type" "veccomplex")
1435 (set_attr "length" "4")])
1437 (define_insn "spe_evmhossiaaw"
1438 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1439 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1440 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1441 (reg:V2SI SPE_ACC_REGNO)] 601))
1442 (clobber (reg:SI SPEFSCR_REGNO))
1443 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1445 "evmhossiaaw %0,%1,%2"
1446 [(set_attr "type" "veccomplex")
1447 (set_attr "length" "4")])
1449 (define_insn "spe_evmhossianw"
1450 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1451 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1452 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1453 (reg:V2SI SPE_ACC_REGNO)] 602))
1454 (clobber (reg:SI SPEFSCR_REGNO))
1455 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1457 "evmhossianw %0,%1,%2"
1458 [(set_attr "type" "veccomplex")
1459 (set_attr "length" "4")])
1461 (define_insn "spe_evmhoumiaaw"
1462 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1463 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1464 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1465 (reg:V2SI SPE_ACC_REGNO)] 603))
1466 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1468 "evmhoumiaaw %0,%1,%2"
1469 [(set_attr "type" "veccomplex")
1470 (set_attr "length" "4")])
1472 (define_insn "spe_evmhoumianw"
1473 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1474 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1475 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1476 (reg:V2SI SPE_ACC_REGNO)] 604))
1477 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1479 "evmhoumianw %0,%1,%2"
1480 [(set_attr "type" "veccomplex")
1481 (set_attr "length" "4")])
1483 (define_insn "spe_evmhoumia"
1484 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1485 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1486 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
1487 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1489 "evmhoumia %0,%1,%2"
1490 [(set_attr "type" "veccomplex")
1491 (set_attr "length" "4")])
1493 (define_insn "spe_evmhoumi"
1494 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1495 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1496 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
1499 [(set_attr "type" "veccomplex")
1500 (set_attr "length" "4")])
1502 (define_insn "spe_evmhousiaaw"
1503 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1504 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1505 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1506 (reg:V2SI SPE_ACC_REGNO)] 607))
1507 (clobber (reg:SI SPEFSCR_REGNO))
1508 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1510 "evmhousiaaw %0,%1,%2"
1511 [(set_attr "type" "veccomplex")
1512 (set_attr "length" "4")])
1514 (define_insn "spe_evmhousianw"
1515 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1516 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1517 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1518 (reg:V2SI SPE_ACC_REGNO)] 608))
1519 (clobber (reg:SI SPEFSCR_REGNO))
1520 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1522 "evmhousianw %0,%1,%2"
1523 [(set_attr "type" "veccomplex")
1524 (set_attr "length" "4")])
1526 (define_insn "spe_evmmlssfa"
1527 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1528 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1529 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
1531 "evmmlssfa %0,%1,%2"
1532 [(set_attr "type" "veccomplex")
1533 (set_attr "length" "4")])
1535 (define_insn "spe_evmmlssf"
1536 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1537 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1538 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
1541 [(set_attr "type" "veccomplex")
1542 (set_attr "length" "4")])
1544 (define_insn "spe_evmwhsmfa"
1545 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1546 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1547 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
1548 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1550 "evmwhsmfa %0,%1,%2"
1551 [(set_attr "type" "veccomplex")
1552 (set_attr "length" "4")])
1554 (define_insn "spe_evmwhsmf"
1555 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1556 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1557 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
1560 [(set_attr "type" "veccomplex")
1561 (set_attr "length" "4")])
1563 (define_insn "spe_evmwhsmia"
1564 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1565 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1566 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
1567 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1569 "evmwhsmia %0,%1,%2"
1570 [(set_attr "type" "veccomplex")
1571 (set_attr "length" "4")])
1573 (define_insn "spe_evmwhsmi"
1574 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1575 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1576 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
1579 [(set_attr "type" "veccomplex")
1580 (set_attr "length" "4")])
1582 (define_insn "spe_evmwhssfa"
1583 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1584 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1585 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
1586 (clobber (reg:SI SPEFSCR_REGNO))
1587 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1589 "evmwhssfa %0,%1,%2"
1590 [(set_attr "type" "veccomplex")
1591 (set_attr "length" "4")])
1593 (define_insn "spe_evmwhusian"
1594 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1595 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1596 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
1598 "evmwhusian %0,%1,%2"
1599 [(set_attr "type" "veccomplex")
1600 (set_attr "length" "4")])
1602 (define_insn "spe_evmwhssf"
1603 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1604 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1605 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
1606 (clobber (reg:SI SPEFSCR_REGNO))]
1609 [(set_attr "type" "veccomplex")
1610 (set_attr "length" "4")])
1612 (define_insn "spe_evmwhumia"
1613 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1614 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1615 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
1616 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1618 "evmwhumia %0,%1,%2"
1619 [(set_attr "type" "veccomplex")
1620 (set_attr "length" "4")])
1622 (define_insn "spe_evmwhumi"
1623 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1624 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1625 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
1628 [(set_attr "type" "veccomplex")
1629 (set_attr "length" "4")])
1631 (define_insn "spe_evmwlsmiaaw"
1632 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1633 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1634 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1635 (reg:V2SI SPE_ACC_REGNO)] 635))
1636 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1638 "evmwlsmiaaw %0,%1,%2"
1639 [(set_attr "type" "veccomplex")
1640 (set_attr "length" "4")])
1642 (define_insn "spe_evmwlsmianw"
1643 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1644 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1645 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1646 (reg:V2SI SPE_ACC_REGNO)] 636))
1647 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1649 "evmwlsmianw %0,%1,%2"
1650 [(set_attr "type" "veccomplex")
1651 (set_attr "length" "4")])
1653 (define_insn "spe_evmwlssiaaw"
1654 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1655 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1656 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1657 (reg:V2SI SPE_ACC_REGNO)] 641))
1658 (clobber (reg:SI SPEFSCR_REGNO))
1659 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1661 "evmwlssiaaw %0,%1,%2"
1662 [(set_attr "type" "veccomplex")
1663 (set_attr "length" "4")])
1665 (define_insn "spe_evmwlssianw"
1666 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1667 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1668 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1669 (reg:V2SI SPE_ACC_REGNO)] 642))
1670 (clobber (reg:SI SPEFSCR_REGNO))
1671 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1673 "evmwlssianw %0,%1,%2"
1674 [(set_attr "type" "veccomplex")
1675 (set_attr "length" "4")])
1677 (define_insn "spe_evmwlumiaaw"
1678 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1679 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1680 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1681 (reg:V2SI SPE_ACC_REGNO)] 643))
1682 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1684 "evmwlumiaaw %0,%1,%2"
1685 [(set_attr "type" "veccomplex")
1686 (set_attr "length" "4")])
1688 (define_insn "spe_evmwlumianw"
1689 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1690 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1691 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1692 (reg:V2SI SPE_ACC_REGNO)] 644))
1693 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1695 "evmwlumianw %0,%1,%2"
1696 [(set_attr "type" "veccomplex")
1697 (set_attr "length" "4")])
1699 (define_insn "spe_evmwlumia"
1700 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1701 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1702 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
1703 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1705 "evmwlumia %0,%1,%2"
1706 [(set_attr "type" "veccomplex")
1707 (set_attr "length" "4")])
1709 (define_insn "spe_evmwlumi"
1710 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1711 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1712 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
1715 [(set_attr "type" "veccomplex")
1716 (set_attr "length" "4")])
1718 (define_insn "spe_evmwlusiaaw"
1719 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1720 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1721 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1722 (reg:V2SI SPE_ACC_REGNO)] 647))
1723 (clobber (reg:SI SPEFSCR_REGNO))
1724 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1726 "evmwlusiaaw %0,%1,%2"
1727 [(set_attr "type" "veccomplex")
1728 (set_attr "length" "4")])
1730 (define_insn "spe_evmwlusianw"
1731 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1732 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1733 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1734 (reg:V2SI SPE_ACC_REGNO)] 648))
1735 (clobber (reg:SI SPEFSCR_REGNO))
1736 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1738 "evmwlusianw %0,%1,%2"
1739 [(set_attr "type" "veccomplex")
1740 (set_attr "length" "4")])
1742 (define_insn "spe_evmwsmfaa"
1743 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1744 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1745 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1746 (reg:V2SI SPE_ACC_REGNO)] 649))
1747 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1749 "evmwsmfaa %0,%1,%2"
1750 [(set_attr "type" "veccomplex")
1751 (set_attr "length" "4")])
1753 (define_insn "spe_evmwsmfan"
1754 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1755 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1756 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1757 (reg:V2SI SPE_ACC_REGNO)] 650))
1758 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1760 "evmwsmfan %0,%1,%2"
1761 [(set_attr "type" "veccomplex")
1762 (set_attr "length" "4")])
1764 (define_insn "spe_evmwsmfa"
1765 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1766 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1767 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
1768 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1771 [(set_attr "type" "veccomplex")
1772 (set_attr "length" "4")])
1774 (define_insn "spe_evmwsmf"
1775 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1776 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1777 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
1780 [(set_attr "type" "veccomplex")
1781 (set_attr "length" "4")])
1783 (define_insn "spe_evmwsmiaa"
1784 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1785 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1786 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1787 (reg:V2SI SPE_ACC_REGNO)] 653))
1788 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1790 "evmwsmiaa %0,%1,%2"
1791 [(set_attr "type" "veccomplex")
1792 (set_attr "length" "4")])
1794 (define_insn "spe_evmwsmian"
1795 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1796 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1797 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1798 (reg:V2SI SPE_ACC_REGNO)] 654))
1799 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1801 "evmwsmian %0,%1,%2"
1802 [(set_attr "type" "veccomplex")
1803 (set_attr "length" "4")])
1805 (define_insn "spe_evmwsmia"
1806 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1807 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1808 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
1809 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1812 [(set_attr "type" "veccomplex")
1813 (set_attr "length" "4")])
1815 (define_insn "spe_evmwsmi"
1816 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1817 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1818 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
1821 [(set_attr "type" "veccomplex")
1822 (set_attr "length" "4")])
1824 (define_insn "spe_evmwssfaa"
1825 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1826 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1827 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1828 (reg:V2SI SPE_ACC_REGNO)] 657))
1829 (clobber (reg:SI SPEFSCR_REGNO))
1830 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1832 "evmwssfaa %0,%1,%2"
1833 [(set_attr "type" "veccomplex")
1834 (set_attr "length" "4")])
1836 (define_insn "spe_evmwssfan"
1837 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1838 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1839 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1840 (reg:V2SI SPE_ACC_REGNO)] 658))
1841 (clobber (reg:SI SPEFSCR_REGNO))
1842 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1844 "evmwssfan %0,%1,%2"
1845 [(set_attr "type" "veccomplex")
1846 (set_attr "length" "4")])
1848 (define_insn "spe_evmwssfa"
1849 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1850 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1851 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
1852 (clobber (reg:SI SPEFSCR_REGNO))
1853 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1856 [(set_attr "type" "veccomplex")
1857 (set_attr "length" "4")])
1859 (define_insn "spe_evmwssf"
1860 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1861 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1862 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
1863 (clobber (reg:SI SPEFSCR_REGNO))]
1866 [(set_attr "type" "veccomplex")
1867 (set_attr "length" "4")])
1869 (define_insn "spe_evmwumiaa"
1870 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1871 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1872 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1873 (reg:V2SI SPE_ACC_REGNO)] 661))
1874 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1876 "evmwumiaa %0,%1,%2"
1877 [(set_attr "type" "veccomplex")
1878 (set_attr "length" "4")])
1880 (define_insn "spe_evmwumian"
1881 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1882 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1883 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1884 (reg:V2SI SPE_ACC_REGNO)] 662))
1885 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1887 "evmwumian %0,%1,%2"
1888 [(set_attr "type" "veccomplex")
1889 (set_attr "length" "4")])
1891 (define_insn "spe_evmwumia"
1892 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1893 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1894 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
1895 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1898 [(set_attr "type" "veccomplex")
1899 (set_attr "length" "4")])
1901 (define_insn "spe_evmwumi"
1902 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1903 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1904 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
1907 [(set_attr "type" "veccomplex")
1908 (set_attr "length" "4")])
1910 (define_insn "addv2si3"
1911 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1912 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1913 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1916 [(set_attr "type" "vecsimple")
1917 (set_attr "length" "4")])
1919 (define_insn "spe_evaddusiaaw"
1920 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1921 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1922 (reg:V2SI SPE_ACC_REGNO)] 673))
1923 (clobber (reg:SI SPEFSCR_REGNO))
1924 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1927 [(set_attr "type" "veccomplex")
1928 (set_attr "length" "4")])
1930 (define_insn "spe_evaddumiaaw"
1931 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1932 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1933 (reg:V2SI SPE_ACC_REGNO)] 674))
1934 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1937 [(set_attr "type" "veccomplex")
1938 (set_attr "length" "4")])
1940 (define_insn "spe_evaddssiaaw"
1941 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1942 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1943 (reg:V2SI SPE_ACC_REGNO)] 675))
1944 (clobber (reg:SI SPEFSCR_REGNO))
1945 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1948 [(set_attr "type" "veccomplex")
1949 (set_attr "length" "4")])
1951 (define_insn "spe_evaddsmiaaw"
1952 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1953 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1954 (reg:V2SI SPE_ACC_REGNO)] 676))
1955 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1958 [(set_attr "type" "veccomplex")
1959 (set_attr "length" "4")])
1961 (define_insn "spe_evaddiw"
1962 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1963 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1964 (match_operand:QI 2 "immediate_operand" "i")] 677))]
1967 [(set_attr "type" "vecsimple")
1968 (set_attr "length" "4")])
1970 (define_insn "spe_evsubifw"
1971 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1972 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1973 (match_operand:QI 2 "immediate_operand" "i")] 678))]
1976 [(set_attr "type" "veccomplex")
1977 (set_attr "length" "4")])
1979 (define_insn "subv2si3"
1980 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1981 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1982 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1985 [(set_attr "type" "veccomplex")
1986 (set_attr "length" "4")])
1988 (define_insn "spe_evsubfusiaaw"
1989 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1990 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1991 (reg:V2SI SPE_ACC_REGNO)] 679))
1992 (clobber (reg:SI SPEFSCR_REGNO))
1993 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1995 "evsubfusiaaw %0,%1"
1996 [(set_attr "type" "veccomplex")
1997 (set_attr "length" "4")])
1999 (define_insn "spe_evsubfumiaaw"
2000 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2001 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2002 (reg:V2SI SPE_ACC_REGNO)] 680))
2003 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2005 "evsubfumiaaw %0,%1"
2006 [(set_attr "type" "veccomplex")
2007 (set_attr "length" "4")])
2009 (define_insn "spe_evsubfssiaaw"
2010 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2011 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2012 (reg:V2SI SPE_ACC_REGNO)] 681))
2013 (clobber (reg:SI SPEFSCR_REGNO))
2014 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2016 "evsubfssiaaw %0,%1"
2017 [(set_attr "type" "veccomplex")
2018 (set_attr "length" "4")])
2020 (define_insn "spe_evsubfsmiaaw"
2021 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2022 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2023 (reg:V2SI SPE_ACC_REGNO)] 682))
2024 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2026 "evsubfsmiaaw %0,%1"
2027 [(set_attr "type" "veccomplex")
2028 (set_attr "length" "4")])
2030 (define_insn "spe_evmra"
2031 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2032 (match_operand:V2SI 1 "gpc_reg_operand" "r"))
2033 (set (reg:V2SI SPE_ACC_REGNO)
2034 (unspec:V2SI [(match_dup 1)] 726))]
2037 [(set_attr "type" "veccomplex")
2038 (set_attr "length" "4")])
2040 (define_insn "divv2si3"
2041 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2042 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2043 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2044 (clobber (reg:SI SPEFSCR_REGNO))]
2047 [(set_attr "type" "vecdiv")
2048 (set_attr "length" "4")])
2050 (define_insn "spe_evdivwu"
2051 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2052 (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2053 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2054 (clobber (reg:SI SPEFSCR_REGNO))]
2057 [(set_attr "type" "vecdiv")
2058 (set_attr "length" "4")])
2060 (define_insn "spe_evsplatfi"
2061 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2062 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
2065 [(set_attr "type" "vecperm")
2066 (set_attr "length" "4")])
2068 (define_insn "spe_evsplati"
2069 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2070 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
2073 [(set_attr "type" "vecperm")
2074 (set_attr "length" "4")])
2076 (define_insn "spe_evstdd"
2077 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2078 (match_operand:QI 1 "immediate_operand" "i")))
2079 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2080 (unspec [(const_int 0)] 686)]
2081 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2082 "evstdd %2,%1*8(%0)"
2083 [(set_attr "type" "vecstore")
2084 (set_attr "length" "4")])
2086 (define_insn "spe_evstddx"
2087 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2088 (match_operand:SI 1 "gpc_reg_operand" "r")))
2089 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2090 (unspec [(const_int 0)] 687)]
2093 [(set_attr "type" "vecstore")
2094 (set_attr "length" "4")])
2096 (define_insn "spe_evstdh"
2097 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2098 (match_operand:QI 1 "immediate_operand" "i")))
2099 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2100 (unspec [(const_int 0)] 688)]
2101 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2102 "evstdh %2,%1*8(%0)"
2103 [(set_attr "type" "vecstore")
2104 (set_attr "length" "4")])
2106 (define_insn "spe_evstdhx"
2107 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2108 (match_operand:SI 1 "gpc_reg_operand" "r")))
2109 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2110 (unspec [(const_int 0)] 689)]
2113 [(set_attr "type" "vecstore")
2114 (set_attr "length" "4")])
2116 (define_insn "spe_evstdw"
2117 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2118 (match_operand:QI 1 "immediate_operand" "i")))
2119 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2120 (unspec [(const_int 0)] 690)]
2121 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2122 "evstdw %2,%1*8(%0)"
2123 [(set_attr "type" "vecstore")
2124 (set_attr "length" "4")])
2126 (define_insn "spe_evstdwx"
2127 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2128 (match_operand:SI 1 "gpc_reg_operand" "r")))
2129 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2130 (unspec [(const_int 0)] 691)]
2133 [(set_attr "type" "vecstore")
2134 (set_attr "length" "4")])
2136 (define_insn "spe_evstwhe"
2137 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2138 (match_operand:QI 1 "immediate_operand" "i")))
2139 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2140 (unspec [(const_int 0)] 692)]
2141 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2142 "evstwhe %2,%1*4(%0)"
2143 [(set_attr "type" "vecstore")
2144 (set_attr "length" "4")])
2146 (define_insn "spe_evstwhex"
2147 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2148 (match_operand:SI 1 "gpc_reg_operand" "r")))
2149 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2150 (unspec [(const_int 0)] 693)]
2153 [(set_attr "type" "vecstore")
2154 (set_attr "length" "4")])
2156 (define_insn "spe_evstwho"
2157 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2158 (match_operand:QI 1 "immediate_operand" "i")))
2159 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2160 (unspec [(const_int 0)] 694)]
2161 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2162 "evstwho %2,%1*4(%0)"
2163 [(set_attr "type" "vecstore")
2164 (set_attr "length" "4")])
2166 (define_insn "spe_evstwhox"
2167 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2168 (match_operand:SI 1 "gpc_reg_operand" "r")))
2169 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2170 (unspec [(const_int 0)] 695)]
2173 [(set_attr "type" "vecstore")
2174 (set_attr "length" "4")])
2176 (define_insn "spe_evstwwe"
2177 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2178 (match_operand:QI 1 "immediate_operand" "i")))
2179 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2180 (unspec [(const_int 0)] 696)]
2181 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2182 "evstwwe %2,%1*4(%0)"
2183 [(set_attr "type" "vecstore")
2184 (set_attr "length" "4")])
2186 (define_insn "spe_evstwwex"
2187 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2188 (match_operand:SI 1 "gpc_reg_operand" "r")))
2189 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2190 (unspec [(const_int 0)] 697)]
2193 [(set_attr "type" "vecstore")
2194 (set_attr "length" "4")])
2196 (define_insn "spe_evstwwo"
2197 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2198 (match_operand:QI 1 "immediate_operand" "i")))
2199 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2200 (unspec [(const_int 0)] 698)]
2201 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2202 "evstwwo %2,%1*4(%0)"
2203 [(set_attr "type" "vecstore")
2204 (set_attr "length" "4")])
2206 (define_insn "spe_evstwwox"
2207 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2208 (match_operand:SI 1 "gpc_reg_operand" "r")))
2209 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2210 (unspec [(const_int 0)] 699)]
2213 [(set_attr "type" "vecstore")
2214 (set_attr "length" "4")])
2216 ;; Double-precision floating point instructions.
2218 ;; FIXME: Add o=r option.
2219 (define_insn "*frob_<SPE64:mode>_<DITI:mode>"
2220 [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r")
2221 (subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))]
2222 "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
2223 || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
2228 (define_insn "*frob_tf_ti"
2229 [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
2230 (subreg:TF (match_operand:TI 1 "gpc_reg_operand" "r") 0))]
2231 "TARGET_E500_DOUBLE"
2232 "evmergelo %0,%1,%L1\;evmergelo %L0,%Y1,%Z1"
2233 [(set_attr "length" "8")])
2235 (define_insn "*frob_<mode>_di_2"
2236 [(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0)
2237 (match_operand:DI 1 "input_operand" "r,m"))]
2238 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2239 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2244 (define_insn "*frob_tf_di_8_2"
2245 [(set (subreg:DI (match_operand:TF 0 "nonimmediate_operand" "+&r,r") 8)
2246 (match_operand:DI 1 "input_operand" "r,m"))]
2247 "TARGET_E500_DOUBLE"
2249 evmergelo %L0,%1,%L1
2252 (define_insn "*frob_di_<mode>"
2253 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
2254 (subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))]
2255 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2256 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2257 "evmergehi %0,%1,%1\;mr %L0,%1"
2258 [(set_attr "length" "8")])
2260 (define_insn "*frob_ti_tf"
2261 [(set (match_operand:TI 0 "nonimmediate_operand" "=&r")
2262 (subreg:TI (match_operand:TF 1 "input_operand" "r") 0))]
2263 "TARGET_E500_DOUBLE"
2264 "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"
2265 [(set_attr "length" "16")])
2267 (define_insn "*frob_<DITI:mode>_<SPE64:mode>_2"
2268 [(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0)
2269 (match_operand:SPE64 1 "input_operand" "r,m"))]
2270 "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
2271 || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
2274 switch (which_alternative)
2279 return \"evmergehi %0,%1,%1\;mr %L0,%1\";
2281 /* If the address is not offsettable we need to load the whole
2282 doubleword into a 64-bit register and then copy the high word
2283 to form the correct output layout. */
2284 if (!offsettable_nonstrict_memref_p (operands[1]))
2285 return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
2286 /* If the low-address word is used in the address, we must load
2287 it last. Otherwise, load it first. Note that we cannot have
2288 auto-increment in that case since the address register is
2289 known to be dead. */
2290 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2292 return \"lwz %L0,%L1\;lwz %0,%1\";
2294 return \"lwz%U1%X1 %0,%1\;lwz %L0,%L1\";
2297 [(set_attr "length" "8,8")])
2299 ; As the above, but TImode at offset 8.
2300 (define_insn "*frob_ti_<mode>_8_2"
2301 [(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8)
2302 (match_operand:SPE64 1 "input_operand" "r,m"))]
2303 "(TARGET_E500_DOUBLE && <MODE>mode == DFmode)
2304 || (TARGET_SPE && <MODE>mode != DFmode)"
2307 switch (which_alternative)
2312 return \"evmergehi %Y0,%1,%1\;mr %Z0,%1\";
2314 if (!offsettable_nonstrict_memref_p (operands[1]))
2315 return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\";
2316 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2318 return \"lwz %Z0,%L1\;lwz %Y0,%1\";
2320 return \"lwz%U1%X1 %Y0,%1\;lwz %Z0,%L1\";
2323 [(set_attr "length" "8,8")])
2325 (define_insn "*frob_ti_tf_2"
2326 [(set (subreg:TF (match_operand:TI 0 "gpc_reg_operand" "=&r") 0)
2327 (match_operand:TF 1 "input_operand" "r"))]
2328 "TARGET_E500_DOUBLE"
2329 "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"
2330 [(set_attr "length" "16")])
2332 (define_insn "mov_si<mode>_e500_subreg0"
2333 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0)
2334 (match_operand:SI 1 "input_operand" "r,m"))]
2335 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2336 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2339 evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
2340 [(set_attr "length" "4,12")])
2342 (define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low"
2343 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0)
2344 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2345 (match_operand 2 "" "")))]
2346 "((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2347 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
2348 && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()"
2353 rtx tmp = gen_reg_rtx (SImode);
2354 emit_insn (gen_elf_low (tmp, operands[1], operands[2]));
2355 emit_insn (gen_mov_si<mode>_e500_subreg0 (operands[0], tmp));
2358 [(set_attr "length" "8")])
2360 ;; ??? Could use evstwwe for memory stores in some cases, depending on
2362 (define_insn "*mov_si<mode>_e500_subreg0_2"
2363 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2364 (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
2365 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2366 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2369 evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
2370 [(set_attr "length" "4,8")])
2372 (define_insn "*mov_si<mode>_e500_subreg4"
2373 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4)
2374 (match_operand:SI 1 "input_operand" "r,m"))]
2375 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2376 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2381 (define_insn "*mov_si<mode>_e500_subreg4_elf_low"
2382 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
2383 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2384 (match_operand 2 "" "")))]
2385 "((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2386 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
2387 && TARGET_ELF && !TARGET_64BIT"
2390 (define_insn "*mov_si<mode>_e500_subreg4_2"
2391 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2392 (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
2393 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2394 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
2399 (define_insn "*mov_sitf_e500_subreg8"
2400 [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8)
2401 (match_operand:SI 1 "input_operand" "r,m"))]
2402 "TARGET_E500_DOUBLE"
2404 evmergelo %L0,%1,%L0
2405 evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0"
2406 [(set_attr "length" "4,12")])
2408 (define_insn "*mov_sitf_e500_subreg8_2"
2409 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2410 (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))]
2411 "TARGET_E500_DOUBLE"
2414 evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
2415 [(set_attr "length" "4,8")])
2417 (define_insn "*mov_sitf_e500_subreg12"
2418 [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 12)
2419 (match_operand:SI 1 "input_operand" "r,m"))]
2420 "TARGET_E500_DOUBLE"
2425 (define_insn "*mov_sitf_e500_subreg12_2"
2426 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2427 (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))]
2428 "TARGET_E500_DOUBLE"
2433 ;; FIXME: Allow r=CONST0.
2434 (define_insn "*movdf_e500_double"
2435 [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
2436 (match_operand:DF 1 "input_operand" "r,m,r"))]
2437 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
2438 && (gpc_reg_operand (operands[0], DFmode)
2439 || gpc_reg_operand (operands[1], DFmode))"
2442 switch (which_alternative)
2445 return \"evor %0,%1,%1\";
2447 return \"evldd%X1 %0,%y1\";
2449 return \"evstdd%X0 %1,%y0\";
2454 [(set_attr "type" "*,vecload,vecstore")
2455 (set_attr "length" "*,*,*")])
2457 (define_insn "spe_truncdfsf2"
2458 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2459 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2460 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2463 (define_insn "spe_absdf2"
2464 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2465 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2466 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2469 (define_insn "spe_nabsdf2"
2470 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2471 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
2472 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2475 (define_insn "spe_negdf2"
2476 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2477 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2478 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2481 (define_insn "spe_adddf3"
2482 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2483 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2484 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2485 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2488 (define_insn "spe_subdf3"
2489 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2490 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2491 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2492 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2495 (define_insn "spe_muldf3"
2496 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2497 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2498 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2499 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2502 (define_insn "spe_divdf3"
2503 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2504 (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2505 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2506 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2509 ;; Double-precision floating point instructions for IBM long double.
2511 (define_insn_and_split "spe_trunctfdf2_internal1"
2512 [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r")
2513 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))]
2515 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2519 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
2522 emit_note (NOTE_INSN_DELETED);
2526 (define_insn_and_split "spe_trunctfsf2"
2527 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2528 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r")))
2529 (clobber (match_scratch:DF 2 "=r"))]
2531 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2533 "&& reload_completed"
2535 (float_truncate:DF (match_dup 1)))
2537 (float_truncate:SF (match_dup 2)))]
2540 (define_insn "spe_extenddftf2"
2541 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o")
2542 (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r")))
2543 (clobber (match_scratch:DF 2 "=X,X,X,&r"))]
2545 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2548 evor %0,%1,%1\;evxor %L0,%L0,%L0
2549 evldd%X1 %0,%y1\;evxor %L0,%L0,%L0
2550 evstdd%X0 %1,%y0\;evxor %2,%2,%2\;evstdd %2,%Y0"
2551 [(set_attr "length" "4,8,8,12")])
2553 (define_expand "spe_fix_trunctfsi2"
2554 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2555 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
2556 (clobber (match_dup 2))
2557 (clobber (match_dup 3))
2558 (clobber (match_dup 4))])]
2560 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2562 operands[2] = gen_reg_rtx (DFmode);
2563 operands[3] = gen_reg_rtx (SImode);
2564 operands[4] = gen_reg_rtx (SImode);
2567 ; Like fix_trunc_helper, add with rounding towards 0.
2568 (define_insn "spe_fix_trunctfsi2_internal"
2569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2570 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "r")))
2571 (clobber (match_operand:DF 2 "gpc_reg_operand" "=r"))
2572 (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r"))
2573 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))]
2575 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2576 "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2"
2577 [(set_attr "length" "24")])
2579 (define_insn "spe_negtf2_internal"
2580 [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
2581 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))]
2583 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2586 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2587 return \"efdneg %L0,%L1\;efdneg %0,%1\";
2589 return \"efdneg %0,%1\;efdneg %L0,%L1\";
2591 [(set_attr "length" "8")])
2593 (define_expand "spe_abstf2_cmp"
2594 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
2595 (match_operand:TF 1 "gpc_reg_operand" "f"))
2596 (set (match_dup 3) (match_dup 5))
2597 (set (match_dup 5) (abs:DF (match_dup 5)))
2598 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2599 (match_dup 5))] CMPDFEQ_GPR))
2600 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
2601 (label_ref (match_operand 2 "" ""))
2603 (set (match_dup 6) (neg:DF (match_dup 6)))]
2605 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2608 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
2609 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
2610 operands[3] = gen_reg_rtx (DFmode);
2611 operands[4] = gen_reg_rtx (CCFPmode);
2612 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
2613 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
2616 (define_expand "spe_abstf2_tst"
2617 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
2618 (match_operand:TF 1 "gpc_reg_operand" "f"))
2619 (set (match_dup 3) (match_dup 5))
2620 (set (match_dup 5) (abs:DF (match_dup 5)))
2621 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2622 (match_dup 5))] TSTDFEQ_GPR))
2623 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
2624 (label_ref (match_operand 2 "" ""))
2626 (set (match_dup 6) (neg:DF (match_dup 6)))]
2628 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2631 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
2632 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
2633 operands[3] = gen_reg_rtx (DFmode);
2634 operands[4] = gen_reg_rtx (CCFPmode);
2635 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
2636 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
2639 ;; Vector move instructions.
2641 (define_expand "movv2si"
2642 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
2643 (match_operand:V2SI 1 "any_operand" ""))]
2645 "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
2647 (define_insn "*movv2si_internal"
2648 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
2649 (match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
2651 && (gpc_reg_operand (operands[0], V2SImode)
2652 || gpc_reg_operand (operands[1], V2SImode))"
2655 switch (which_alternative)
2657 case 0: return \"evstdd%X0 %1,%y0\";
2658 case 1: return \"evldd%X1 %0,%y1\";
2659 case 2: return \"evor %0,%1,%1\";
2660 case 3: return output_vec_const_move (operands);
2661 default: gcc_unreachable ();
2664 [(set_attr "type" "vecload,vecstore,*,*")
2665 (set_attr "length" "*,*,*,12")])
2668 [(set (match_operand:V2SI 0 "register_operand" "")
2669 (match_operand:V2SI 1 "zero_constant" ""))]
2670 "TARGET_SPE && reload_completed"
2672 (xor:V2SI (match_dup 0) (match_dup 0)))]
2675 (define_expand "movv1di"
2676 [(set (match_operand:V1DI 0 "nonimmediate_operand" "")
2677 (match_operand:V1DI 1 "any_operand" ""))]
2679 "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
2681 (define_insn "*movv1di_internal"
2682 [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
2683 (match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
2685 && (gpc_reg_operand (operands[0], V1DImode)
2686 || gpc_reg_operand (operands[1], V1DImode))"
2692 [(set_attr "type" "vecload,vecstore,*,*")
2693 (set_attr "length" "*,*,*,*")])
2695 (define_expand "movv4hi"
2696 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
2697 (match_operand:V4HI 1 "any_operand" ""))]
2699 "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
2701 (define_insn "*movv4hi_internal"
2702 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r")
2703 (match_operand:V4HI 1 "input_operand" "r,m,r,W"))]
2705 && (gpc_reg_operand (operands[0], V4HImode)
2706 || gpc_reg_operand (operands[1], V4HImode))"
2712 [(set_attr "type" "vecload")])
2714 (define_expand "movv2sf"
2715 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
2716 (match_operand:V2SF 1 "any_operand" ""))]
2717 "TARGET_SPE || TARGET_PAIRED_FLOAT"
2718 "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
2720 (define_insn "*movv2sf_internal"
2721 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
2722 (match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
2724 && (gpc_reg_operand (operands[0], V2SFmode)
2725 || gpc_reg_operand (operands[1], V2SFmode))"
2731 [(set_attr "type" "vecload,vecstore,*,*")
2732 (set_attr "length" "*,*,*,*")])
2734 ;; End of vector move instructions.
2736 (define_insn "spe_evmwhssfaa"
2737 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2738 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2739 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
2740 (clobber (reg:SI SPEFSCR_REGNO))
2741 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2743 "evmwhssfaa %0,%1,%2"
2744 [(set_attr "type" "veccomplex")
2745 (set_attr "length" "4")])
2747 (define_insn "spe_evmwhssmaa"
2748 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2749 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2750 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
2751 (clobber (reg:SI SPEFSCR_REGNO))
2752 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2754 "evmwhssmaa %0,%1,%2"
2755 [(set_attr "type" "veccomplex")
2756 (set_attr "length" "4")])
2758 (define_insn "spe_evmwhsmfaa"
2759 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2760 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2761 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
2762 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2764 "evmwhsmfaa %0,%1,%2"
2765 [(set_attr "type" "veccomplex")
2766 (set_attr "length" "4")])
2768 (define_insn "spe_evmwhsmiaa"
2769 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2770 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2771 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
2772 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2774 "evmwhsmiaa %0,%1,%2"
2775 [(set_attr "type" "veccomplex")
2776 (set_attr "length" "4")])
2778 (define_insn "spe_evmwhusiaa"
2779 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2780 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2781 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
2782 (clobber (reg:SI SPEFSCR_REGNO))
2783 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2785 "evmwhusiaa %0,%1,%2"
2786 [(set_attr "type" "veccomplex")
2787 (set_attr "length" "4")])
2789 (define_insn "spe_evmwhumiaa"
2790 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2791 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2792 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
2793 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2795 "evmwhumiaa %0,%1,%2"
2796 [(set_attr "type" "veccomplex")
2797 (set_attr "length" "4")])
2799 (define_insn "spe_evmwhssfan"
2800 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2801 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2802 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
2803 (clobber (reg:SI SPEFSCR_REGNO))
2804 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2806 "evmwhssfan %0,%1,%2"
2807 [(set_attr "type" "veccomplex")
2808 (set_attr "length" "4")])
2810 (define_insn "spe_evmwhssian"
2811 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2812 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2813 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
2814 (clobber (reg:SI SPEFSCR_REGNO))
2815 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2817 "evmwhssian %0,%1,%2"
2818 [(set_attr "type" "veccomplex")
2819 (set_attr "length" "4")])
2821 (define_insn "spe_evmwhsmfan"
2822 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2823 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2824 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
2825 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2827 "evmwhsmfan %0,%1,%2"
2828 [(set_attr "type" "veccomplex")
2829 (set_attr "length" "4")])
2831 (define_insn "spe_evmwhsmian"
2832 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2833 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2834 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
2835 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2837 "evmwhsmian %0,%1,%2"
2838 [(set_attr "type" "veccomplex")
2839 (set_attr "length" "4")])
2841 (define_insn "spe_evmwhumian"
2842 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2843 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2844 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
2845 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2847 "evmwhumian %0,%1,%2"
2848 [(set_attr "type" "veccomplex")
2849 (set_attr "length" "4")])
2851 (define_insn "spe_evmwhgssfaa"
2852 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2853 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2854 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
2855 (clobber (reg:SI SPEFSCR_REGNO))
2856 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2858 "evmwhgssfaa %0,%1,%2"
2859 [(set_attr "type" "veccomplex")
2860 (set_attr "length" "4")])
2862 (define_insn "spe_evmwhgsmfaa"
2863 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2864 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2865 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
2866 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2868 "evmwhgsmfaa %0,%1,%2"
2869 [(set_attr "type" "veccomplex")
2870 (set_attr "length" "4")])
2872 (define_insn "spe_evmwhgsmiaa"
2873 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2874 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2875 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
2876 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2878 "evmwhgsmiaa %0,%1,%2"
2879 [(set_attr "type" "veccomplex")
2880 (set_attr "length" "4")])
2882 (define_insn "spe_evmwhgumiaa"
2883 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2884 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2885 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
2886 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2888 "evmwhgumiaa %0,%1,%2"
2889 [(set_attr "type" "veccomplex")
2890 (set_attr "length" "4")])
2892 (define_insn "spe_evmwhgssfan"
2893 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2894 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2895 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
2896 (clobber (reg:SI SPEFSCR_REGNO))
2897 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2899 "evmwhgssfan %0,%1,%2"
2900 [(set_attr "type" "veccomplex")
2901 (set_attr "length" "4")])
2903 (define_insn "spe_evmwhgsmfan"
2904 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2905 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2906 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
2907 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2909 "evmwhgsmfan %0,%1,%2"
2910 [(set_attr "type" "veccomplex")
2911 (set_attr "length" "4")])
2913 (define_insn "spe_evmwhgsmian"
2914 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2915 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2916 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
2917 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2919 "evmwhgsmian %0,%1,%2"
2920 [(set_attr "type" "veccomplex")
2921 (set_attr "length" "4")])
2923 (define_insn "spe_evmwhgumian"
2924 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2925 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2926 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
2927 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2929 "evmwhgumian %0,%1,%2"
2930 [(set_attr "type" "veccomplex")
2931 (set_attr "length" "4")])
2933 (define_insn "spe_mtspefscr"
2934 [(set (reg:SI SPEFSCR_REGNO)
2935 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2939 [(set_attr "type" "vecsimple")])
2941 (define_insn "spe_mfspefscr"
2942 [(set (match_operand:SI 0 "register_operand" "=r")
2943 (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
2946 [(set_attr "type" "vecsimple")])
2949 (define_insn "e500_flip_gt_bit"
2950 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2952 [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
2953 "!TARGET_FPRS && TARGET_HARD_FLOAT"
2956 return output_e500_flip_gt_bit (operands[0], operands[1]);
2958 [(set_attr "type" "cr_logical")])
2960 ;; MPC8540 single-precision FP instructions on GPRs.
2961 ;; We have 2 variants for each. One for IEEE compliant math and one
2962 ;; for non IEEE compliant math.
2964 (define_insn "cmpsfeq_gpr"
2965 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2967 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2968 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2970 "TARGET_HARD_FLOAT && !TARGET_FPRS
2971 && !(flag_finite_math_only && !flag_trapping_math)"
2973 [(set_attr "type" "veccmp")])
2975 (define_insn "tstsfeq_gpr"
2976 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2978 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2979 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2981 "TARGET_HARD_FLOAT && !TARGET_FPRS
2982 && flag_finite_math_only && !flag_trapping_math"
2984 [(set_attr "type" "veccmpsimple")])
2986 (define_insn "cmpsfgt_gpr"
2987 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2989 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2990 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2992 "TARGET_HARD_FLOAT && !TARGET_FPRS
2993 && !(flag_finite_math_only && !flag_trapping_math)"
2995 [(set_attr "type" "veccmp")])
2997 (define_insn "tstsfgt_gpr"
2998 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3000 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
3001 (match_operand:SF 2 "gpc_reg_operand" "r"))]
3003 "TARGET_HARD_FLOAT && !TARGET_FPRS
3004 && flag_finite_math_only && !flag_trapping_math"
3006 [(set_attr "type" "veccmpsimple")])
3008 (define_insn "cmpsflt_gpr"
3009 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3011 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
3012 (match_operand:SF 2 "gpc_reg_operand" "r"))]
3014 "TARGET_HARD_FLOAT && !TARGET_FPRS
3015 && !(flag_finite_math_only && !flag_trapping_math)"
3017 [(set_attr "type" "veccmp")])
3019 (define_insn "tstsflt_gpr"
3020 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3022 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
3023 (match_operand:SF 2 "gpc_reg_operand" "r"))]
3025 "TARGET_HARD_FLOAT && !TARGET_FPRS
3026 && flag_finite_math_only && !flag_trapping_math"
3028 [(set_attr "type" "veccmpsimple")])
3030 ;; Same thing, but for double-precision.
3032 (define_insn "cmpdfeq_gpr"
3033 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3035 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3036 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3038 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3039 && !(flag_finite_math_only && !flag_trapping_math)"
3041 [(set_attr "type" "veccmp")])
3043 (define_insn "tstdfeq_gpr"
3044 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3046 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3047 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3049 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3050 && flag_finite_math_only && !flag_trapping_math"
3052 [(set_attr "type" "veccmpsimple")])
3054 (define_insn "cmpdfgt_gpr"
3055 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3057 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3058 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3060 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3061 && !(flag_finite_math_only && !flag_trapping_math)"
3063 [(set_attr "type" "veccmp")])
3065 (define_insn "tstdfgt_gpr"
3066 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3068 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3069 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3071 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3072 && flag_finite_math_only && !flag_trapping_math"
3074 [(set_attr "type" "veccmpsimple")])
3076 (define_insn "cmpdflt_gpr"
3077 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3079 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3080 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3082 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3083 && !(flag_finite_math_only && !flag_trapping_math)"
3085 [(set_attr "type" "veccmp")])
3087 (define_insn "tstdflt_gpr"
3088 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3090 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3091 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3093 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3094 && flag_finite_math_only && !flag_trapping_math"
3096 [(set_attr "type" "veccmpsimple")])
3098 ;; Same thing, but for IBM long double.
3100 (define_insn "cmptfeq_gpr"
3101 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3103 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3104 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3107 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3108 && !(flag_finite_math_only && !flag_trapping_math)"
3109 "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2"
3110 [(set_attr "type" "veccmp")
3111 (set_attr "length" "12")])
3113 (define_insn "tsttfeq_gpr"
3114 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3116 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3117 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3120 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3121 && flag_finite_math_only && !flag_trapping_math"
3122 "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2"
3123 [(set_attr "type" "veccmpsimple")
3124 (set_attr "length" "12")])
3126 (define_insn "cmptfgt_gpr"
3127 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3129 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3130 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3133 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3134 && !(flag_finite_math_only && !flag_trapping_math)"
3135 "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2"
3136 [(set_attr "type" "veccmp")
3137 (set_attr "length" "20")])
3139 (define_insn "tsttfgt_gpr"
3140 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3142 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3143 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3146 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3147 && flag_finite_math_only && !flag_trapping_math"
3148 "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2"
3149 [(set_attr "type" "veccmpsimple")
3150 (set_attr "length" "20")])
3152 (define_insn "cmptflt_gpr"
3153 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3155 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3156 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3159 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3160 && !(flag_finite_math_only && !flag_trapping_math)"
3161 "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2"
3162 [(set_attr "type" "veccmp")
3163 (set_attr "length" "20")])
3165 (define_insn "tsttflt_gpr"
3166 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3168 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3169 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3172 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3173 && flag_finite_math_only && !flag_trapping_math"
3174 "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2"
3175 [(set_attr "type" "veccmpsimple")
3176 (set_attr "length" "20")])
3178 ;; Like cceq_ior_compare, but compare the GT bits.
3179 (define_insn "e500_cr_ior_compare"
3180 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3181 (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
3182 (match_operand 2 "cc_reg_operand" "y")]
3183 E500_CR_IOR_COMPARE))]
3184 "TARGET_HARD_FLOAT && !TARGET_FPRS"
3185 "cror 4*%0+gt,4*%1+gt,4*%2+gt"
3186 [(set_attr "type" "cr_logical")])
3188 ;; Out-of-line prologues and epilogues.
3189 (define_insn "*save_gpregs_spe"
3190 [(match_parallel 0 "any_parallel_operand"
3191 [(clobber (reg:P 65))
3192 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3194 (set (match_operand:V2SI 2 "memory_operand" "=m")
3195 (match_operand:V2SI 3 "gpc_reg_operand" "r"))])]
3198 [(set_attr "type" "branch")
3199 (set_attr "length" "4")])
3201 (define_insn "*restore_gpregs_spe"
3202 [(match_parallel 0 "any_parallel_operand"
3203 [(clobber (reg:P 65))
3204 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3206 (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
3207 (match_operand:V2SI 3 "memory_operand" "m"))])]
3210 [(set_attr "type" "branch")
3211 (set_attr "length" "4")])
3213 (define_insn "*return_and_restore_gpregs_spe"
3214 [(match_parallel 0 "any_parallel_operand"
3216 (clobber (reg:P 65))
3217 (use (match_operand:P 1 "symbol_ref_operand" "s"))
3219 (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
3220 (match_operand:V2SI 3 "memory_operand" "m"))])]
3223 [(set_attr "type" "branch")
3224 (set_attr "length" "4")])