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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
70 #ifndef CHECK_STACK_LIMIT
71 #define CHECK_STACK_LIMIT (-1)
72 #endif
74 /* Return index of given mode in mult and division cost tables. */
75 #define MODE_INDEX(mode) \
76 ((mode) == QImode ? 0 \
77 : (mode) == HImode ? 1 \
78 : (mode) == SImode ? 2 \
79 : (mode) == DImode ? 3 \
80 : 4)
82 /* Processor costs (relative to an add) */
83 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
84 #define COSTS_N_BYTES(N) ((N) * 2)
86 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
88 const
111 in QImode, HImode and SImode.
112 Relative to reg-reg move (2). */
116 in SFmode, DFmode and XFmode */
118 in SFmode, DFmode and XFmode */
121 in SImode and DImode */
123 in SImode and DImode */
126 in SImode, DImode and TImode */
128 in SImode, DImode and TImode */
156 };
158 /* Processor costs (relative to an add) */
159 static const
182 in QImode, HImode and SImode.
183 Relative to reg-reg move (2). */
187 in SFmode, DFmode and XFmode */
189 in SFmode, DFmode and XFmode */
192 in SImode and DImode */
194 in SImode and DImode */
197 in SImode, DImode and TImode */
199 in SImode, DImode and TImode */
213 DUMMY_STRINGOP_ALGS},
215 DUMMY_STRINGOP_ALGS},
227 };
229 static const
252 in QImode, HImode and SImode.
253 Relative to reg-reg move (2). */
257 in SFmode, DFmode and XFmode */
259 in SFmode, DFmode and XFmode */
262 in SImode and DImode */
264 in SImode and DImode */
267 in SImode, DImode and TImode */
269 in SImode, DImode and TImode */
272 shared for code and data, so 4kB is
273 not really precise. */
285 DUMMY_STRINGOP_ALGS},
287 DUMMY_STRINGOP_ALGS},
299 };
301 static const
324 in QImode, HImode and SImode.
325 Relative to reg-reg move (2). */
329 in SFmode, DFmode and XFmode */
331 in SFmode, DFmode and XFmode */
334 in SImode and DImode */
336 in SImode and DImode */
339 in SImode, DImode and TImode */
341 in SImode, DImode and TImode */
355 DUMMY_STRINGOP_ALGS},
357 DUMMY_STRINGOP_ALGS},
369 };
371 static const
394 in QImode, HImode and SImode.
395 Relative to reg-reg move (2). */
399 in SFmode, DFmode and XFmode */
401 in SFmode, DFmode and XFmode */
404 in SImode and DImode */
406 in SImode and DImode */
409 in SImode, DImode and TImode */
411 in SImode, DImode and TImode */
424 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
425 (we ensure the alignment). For small blocks inline loop is still a
426 noticeable win, for bigger blocks either rep movsl or rep movsb is
427 way to go. Rep movsb has apparently more expensive startup time in CPU,
428 but after 4K the difference is down in the noise. */
431 DUMMY_STRINGOP_ALGS},
434 DUMMY_STRINGOP_ALGS},
446 };
448 static const
471 in QImode, HImode and SImode.
472 Relative to reg-reg move (2). */
476 in SFmode, DFmode and XFmode */
478 in SFmode, DFmode and XFmode */
482 in SImode and DImode */
484 in SImode and DImode */
487 in SImode, DImode and TImode */
489 in SImode, DImode and TImode */
503 DUMMY_STRINGOP_ALGS},
505 DUMMY_STRINGOP_ALGS},
517 };
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
563 have integrated l2 cache, but
564 optimizing for k6 is not important
565 enough to worry about that. */
576 DUMMY_STRINGOP_ALGS},
578 DUMMY_STRINGOP_ALGS},
590 };
592 static const
615 in QImode, HImode and SImode.
616 Relative to reg-reg move (2). */
620 in SFmode, DFmode and XFmode */
622 in SFmode, DFmode and XFmode */
625 in SImode and DImode */
627 in SImode and DImode */
630 in SImode, DImode and TImode */
632 in SImode, DImode and TImode */
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
649 DUMMY_STRINGOP_ALGS},
651 DUMMY_STRINGOP_ALGS},
663 };
665 static const
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
693 in SFmode, DFmode and XFmode */
695 in SFmode, DFmode and XFmode */
698 in SImode and DImode */
700 in SImode and DImode */
703 in SImode, DImode and TImode */
705 in SImode, DImode and TImode */
710 /* New AMD processors never drop prefetches; if they cannot be performed
711 immediately, they are queued. We set number of simultaneous prefetches
712 to a large constant to reflect this (it probably is not a good idea not
713 to limit number of prefetches at all, as their execution also takes some
714 time). */
723 /* K8 has optimized REP instruction for medium sized blocks, but for very
724 small blocks it is better to use loop. For large blocks, libcall can
725 do nontemporary accesses and beat inline considerably. */
742 };
766 in QImode, HImode and SImode.
767 Relative to reg-reg move (2). */
771 in SFmode, DFmode and XFmode */
773 in SFmode, DFmode and XFmode */
776 in SImode and DImode */
778 in SImode and DImode */
781 in SImode, DImode and TImode */
783 in SImode, DImode and TImode */
785 /* On K8:
786 MOVD reg64, xmmreg Double FSTORE 4
787 MOVD reg32, xmmreg Double FSTORE 4
788 On AMDFAM10:
789 MOVD reg64, xmmreg Double FADD 3
790 1/1 1/1
791 MOVD reg32, xmmreg Double FADD 3
792 1/1 1/1 */
796 /* New AMD processors never drop prefetches; if they cannot be performed
797 immediately, they are queued. We set number of simultaneous prefetches
798 to a large constant to reflect this (it probably is not a good idea not
799 to limit number of prefetches at all, as their execution also takes some
800 time). */
810 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
811 very small blocks it is better to use loop. For large blocks, libcall can
812 do nontemporary accesses and beat inline considerably. */
829 };
853 in QImode, HImode and SImode.
854 Relative to reg-reg move (2). */
858 in SFmode, DFmode and XFmode */
860 in SFmode, DFmode and XFmode */
863 in SImode and DImode */
865 in SImode and DImode */
868 in SImode, DImode and TImode */
870 in SImode, DImode and TImode */
872 /* On K8:
873 MOVD reg64, xmmreg Double FSTORE 4
874 MOVD reg32, xmmreg Double FSTORE 4
875 On AMDFAM10:
876 MOVD reg64, xmmreg Double FADD 3
877 1/1 1/1
878 MOVD reg32, xmmreg Double FADD 3
879 1/1 1/1 */
883 /* New AMD processors never drop prefetches; if they cannot be performed
884 immediately, they are queued. We set number of simultaneous prefetches
885 to a large constant to reflect this (it probably is not a good idea not
886 to limit number of prefetches at all, as their execution also takes some
887 time). */
897 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
898 very small blocks it is better to use loop. For large blocks, libcall
899 can do nontemporary accesses and beat inline considerably. */
916 };
940 in QImode, HImode and SImode.
941 Relative to reg-reg move (2). */
945 in SFmode, DFmode and XFmode */
947 in SFmode, DFmode and XFmode */
950 in SImode and DImode */
952 in SImode and DImode */
955 in SImode, DImode and TImode */
957 in SImode, DImode and TImode */
959 /* On K8:
960 MOVD reg64, xmmreg Double FSTORE 4
961 MOVD reg32, xmmreg Double FSTORE 4
962 On AMDFAM10:
963 MOVD reg64, xmmreg Double FADD 3
964 1/1 1/1
965 MOVD reg32, xmmreg Double FADD 3
966 1/1 1/1 */
970 /* New AMD processors never drop prefetches; if they cannot be performed
971 immediately, they are queued. We set number of simultaneous prefetches
972 to a large constant to reflect this (it probably is not a good idea not
973 to limit number of prefetches at all, as their execution also takes some
974 time). */
984 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
985 very small blocks it is better to use loop. For large blocks, libcall
986 can do nontemporary accesses and beat inline considerably. */
1003 };
1027 in QImode, HImode and SImode.
1028 Relative to reg-reg move (2). */
1032 in SFmode, DFmode and XFmode */
1034 in SFmode, DFmode and XFmode */
1037 in SImode and DImode */
1039 in SImode and DImode */
1042 in SImode, DImode and TImode */
1044 in SImode, DImode and TImode */
1046 /* On K8:
1047 MOVD reg64, xmmreg Double FSTORE 4
1048 MOVD reg32, xmmreg Double FSTORE 4
1049 On AMDFAM10:
1050 MOVD reg64, xmmreg Double FADD 3
1051 1/1 1/1
1052 MOVD reg32, xmmreg Double FADD 3
1053 1/1 1/1 */
1066 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1067 very small blocks it is better to use loop. For large blocks, libcall can
1068 do nontemporary accesses and beat inline considerably. */
1085 };
1109 in QImode, HImode and SImode.
1110 Relative to reg-reg move (2). */
1114 in SFmode, DFmode and XFmode */
1116 in SFmode, DFmode and XFmode */
1119 in SImode and DImode */
1121 in SImode and DImode */
1124 in SImode, DImode and TImode */
1126 in SImode, DImode and TImode */
1128 /* On K8:
1129 MOVD reg64, xmmreg Double FSTORE 4
1130 MOVD reg32, xmmreg Double FSTORE 4
1131 On AMDFAM10:
1132 MOVD reg64, xmmreg Double FADD 3
1133 1/1 1/1
1134 MOVD reg32, xmmreg Double FADD 3
1135 1/1 1/1 */
1164 };
1166 static const
1189 in QImode, HImode and SImode.
1190 Relative to reg-reg move (2). */
1194 in SFmode, DFmode and XFmode */
1196 in SFmode, DFmode and XFmode */
1199 in SImode and DImode */
1201 in SImode and DImode */
1204 in SImode, DImode and TImode */
1206 in SImode, DImode and TImode */
1220 DUMMY_STRINGOP_ALGS},
1223 DUMMY_STRINGOP_ALGS},
1235 };
1237 static const
1260 in QImode, HImode and SImode.
1261 Relative to reg-reg move (2). */
1265 in SFmode, DFmode and XFmode */
1267 in SFmode, DFmode and XFmode */
1270 in SImode and DImode */
1272 in SImode and DImode */
1275 in SImode, DImode and TImode */
1277 in SImode, DImode and TImode */
1308 };
1310 static const
1333 in QImode, HImode and SImode.
1334 Relative to reg-reg move (2). */
1338 in SFmode, DFmode and XFmode */
1340 in SFmode, DFmode and XFmode */
1343 in SImode and DImode */
1345 in SImode and DImode */
1348 in SImode, DImode and TImode */
1350 in SImode, DImode and TImode */
1381 };
1383 /* Generic64 should produce code tuned for Nocona and K8. */
1384 static const
1387 /* On all chips taken into consideration lea is 2 cycles and more. With
1388 this cost however our current implementation of synth_mult results in
1389 use of unnecessary temporary registers causing regression on several
1390 SPECfp benchmarks. */
1411 in QImode, HImode and SImode.
1412 Relative to reg-reg move (2). */
1416 in SFmode, DFmode and XFmode */
1418 in SFmode, DFmode and XFmode */
1421 in SImode and DImode */
1423 in SImode and DImode */
1426 in SImode, DImode and TImode */
1428 in SImode, DImode and TImode */
1434 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1435 value is increased to perhaps more appropriate value of 5. */
1458 };
1460 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1461 Athlon and K8. */
1462 static const
1485 in QImode, HImode and SImode.
1486 Relative to reg-reg move (2). */
1490 in SFmode, DFmode and XFmode */
1492 in SFmode, DFmode and XFmode */
1495 in SImode and DImode */
1497 in SImode and DImode */
1500 in SImode, DImode and TImode */
1502 in SImode, DImode and TImode */
1516 DUMMY_STRINGOP_ALGS},
1518 DUMMY_STRINGOP_ALGS},
1530 };
1532 /* Set by -mtune. */
1535 /* Set by -mtune or -Os. */
1538 /* Processor feature/optimization bitmasks. */
1539 #define m_386 (1<<PROCESSOR_I386)
1540 #define m_486 (1<<PROCESSOR_I486)
1541 #define m_PENT (1<<PROCESSOR_PENTIUM)
1542 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1543 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1544 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1545 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1546 #define m_CORE2_32 (1<<PROCESSOR_CORE2_32)
1547 #define m_CORE2_64 (1<<PROCESSOR_CORE2_64)
1548 #define m_COREI7_32 (1<<PROCESSOR_COREI7_32)
1549 #define m_COREI7_64 (1<<PROCESSOR_COREI7_64)
1550 #define m_COREI7 (m_COREI7_32 | m_COREI7_64)
1551 #define m_CORE2I7_32 (m_CORE2_32 | m_COREI7_32)
1552 #define m_CORE2I7_64 (m_CORE2_64 | m_COREI7_64)
1553 #define m_CORE2I7 (m_CORE2I7_32 | m_CORE2I7_64)
1554 #define m_ATOM (1<<PROCESSOR_ATOM)
1556 #define m_GEODE (1<<PROCESSOR_GEODE)
1557 #define m_K6 (1<<PROCESSOR_K6)
1558 #define m_K6_GEODE (m_K6 | m_GEODE)
1559 #define m_K8 (1<<PROCESSOR_K8)
1560 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1561 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1562 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1563 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1564 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1565 #define m_BDVER (m_BDVER1 | m_BDVER2)
1566 #define m_BTVER (m_BTVER1 | m_BTVER2)
1567 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1568 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1569 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1571 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1572 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1574 /* Generic instruction choice should be common subset of supported CPUs
1575 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1576 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1578 /* Feature tests against the various tunings. */
1581 /* Feature tests against the various tunings used to create ix86_tune_features
1582 based on the processor mask. */
1584 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1585 negatively, so enabling for Generic64 seems like good code size
1586 tradeoff. We can't enable it for 32bit generic because it does not
1587 work well with PPro base chips. */
1590 /* X86_TUNE_PUSH_MEMORY */
1593 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1596 /* X86_TUNE_UNROLL_STRLEN */
1599 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1600 on simulation result. But after P4 was made, no performance benefit
1601 was observed with branch hints. It also increases the code size.
1602 As a result, icc never generates branch hints. */
1605 /* X86_TUNE_DOUBLE_WITH_ADD */
1608 /* X86_TUNE_USE_SAHF */
1609 m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1611 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1612 partial dependencies. */
1615 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1616 register stalls on Generic32 compilation setting as well. However
1617 in current implementation the partial register stalls are not eliminated
1618 very well - they can be introduced via subregs synthesized by combine
1619 and can happen in caller/callee saving sequences. Because this option
1620 pays back little on PPro based chips and is in conflict with partial reg
1621 dependencies used by Athlon/P4 based chips, it is better to leave it off
1622 for generic32 for now. */
1623 m_PPRO,
1625 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1628 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1629 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1632 /* X86_TUNE_USE_HIMODE_FIOP */
1635 /* X86_TUNE_USE_SIMODE_FIOP */
1638 /* X86_TUNE_USE_MOV0 */
1639 m_K6,
1641 /* X86_TUNE_USE_CLTD */
1644 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1645 m_PENT4,
1647 /* X86_TUNE_SPLIT_LONG_MOVES */
1648 m_PPRO,
1650 /* X86_TUNE_READ_MODIFY_WRITE */
1653 /* X86_TUNE_READ_MODIFY */
1656 /* X86_TUNE_PROMOTE_QIMODE */
1659 /* X86_TUNE_FAST_PREFIX */
1662 /* X86_TUNE_SINGLE_STRINGOP */
1665 /* X86_TUNE_QIMODE_MATH */
1668 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1669 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1670 might be considered for Generic32 if our scheme for avoiding partial
1671 stalls was more effective. */
1674 /* X86_TUNE_PROMOTE_QI_REGS */
1677 /* X86_TUNE_PROMOTE_HI_REGS */
1678 m_PPRO,
1680 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1681 over esp addition. */
1684 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1685 over esp addition. */
1686 m_PENT,
1688 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1689 over esp subtraction. */
1692 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1693 over esp subtraction. */
1696 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1697 for DFmode copies */
1700 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1703 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1704 conflict here in between PPro/Pentium4 based chips that thread 128bit
1705 SSE registers as single units versus K8 based chips that divide SSE
1706 registers to two 64bit halves. This knob promotes all store destinations
1707 to be 128bit to allow register renaming on 128bit SSE units, but usually
1708 results in one extra microop on 64bit SSE units. Experimental results
1709 shows that disabling this option on P4 brings over 20% SPECfp regression,
1710 while enabling it on K8 brings roughly 2.4% regression that can be partly
1711 masked by careful scheduling of moves. */
1714 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1717 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1720 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1721 m_BDVER ,
1723 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1724 are resolved on SSE register parts instead of whole registers, so we may
1725 maintain just lower part of scalar values in proper format leaving the
1726 upper part undefined. */
1727 m_ATHLON_K8,
1729 /* X86_TUNE_SSE_TYPELESS_STORES */
1730 m_AMD_MULTIPLE,
1732 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1735 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1738 /* X86_TUNE_PROLOGUE_USING_MOVE */
1741 /* X86_TUNE_EPILOGUE_USING_MOVE */
1744 /* X86_TUNE_SHIFT1 */
1747 /* X86_TUNE_USE_FFREEP */
1748 m_AMD_MULTIPLE,
1750 /* X86_TUNE_INTER_UNIT_MOVES */
1753 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1756 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1757 than 4 branch instructions in the 16 byte window. */
1760 /* X86_TUNE_SCHEDULE */
1763 /* X86_TUNE_USE_BT */
1766 /* X86_TUNE_USE_INCDEC */
1769 /* X86_TUNE_PAD_RETURNS */
1772 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1773 m_ATOM,
1775 /* X86_TUNE_EXT_80387_CONSTANTS */
1778 /* X86_TUNE_SHORTEN_X87_SSE */
1781 /* X86_TUNE_AVOID_VECTOR_DECODE */
1784 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1785 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1788 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1789 vector path on AMD machines. */
1792 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1793 machines. */
1796 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1797 than a MOV. */
1798 m_PENT,
1800 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1801 but one byte longer. */
1802 m_PENT,
1804 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1805 operand that cannot be represented using a modRM byte. The XOR
1806 replacement is long decoded, so this split helps here as well. */
1807 m_K6,
1809 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1810 from FP to FP. */
1813 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1814 from integer to FP. */
1815 m_AMDFAM10,
1817 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1818 with a subsequent conditional jump instruction into a single
1819 compare-and-branch uop. */
1820 m_BDVER,
1822 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1823 will impact LEA instruction selection. */
1824 m_ATOM,
1826 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
1827 instructions. */
1830 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
1831 at -O3. For the moment, the prefetching seems badly tuned for Intel
1832 chips. */
1835 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
1836 the auto-vectorizer. */
1837 m_BDVER,
1839 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
1840 during reassociation of integer computation. */
1841 m_ATOM,
1843 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
1844 during reassociation of fp computation. */
1845 m_ATOM,
1847 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
1848 regs instead of memory. */
1849 m_COREI7 | m_CORE2I7
1850 };
1852 /* Feature tests against the various architecture variations. */
1855 /* Feature tests against the various architecture variations, used to create
1856 ix86_arch_features based on the processor mask. */
1858 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
1861 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1864 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1867 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1870 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1872 };
1874 static const unsigned int x86_accumulate_outgoing_args
1877 static const unsigned int x86_arch_always_fancy_math_387
1880 static const unsigned int x86_avx256_split_unaligned_load
1883 static const unsigned int x86_avx256_split_unaligned_store
1886 /* In case the average insn count for single function invocation is
1887 lower than this constant, emit fast (but longer) prologue and
1888 epilogue code. */
1889 #define FAST_PROLOGUE_INSN_COUNT 20
1891 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1896 /* Array of the smallest class containing reg number REGNO, indexed by
1897 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1900 {
1901 /* ax, dx, cx, bx */
1903 /* si, di, bp, sp */
1905 /* FP registers */
1908 /* arg pointer */
1909 NON_Q_REGS,
1910 /* flags, fpsr, fpcr, frame */
1912 /* SSE registers */
1915 /* MMX registers */
1918 /* REX registers */
1921 /* SSE REX registers */
1924 };
1926 /* The "default" register map used in 32bit mode. */
1929 {
1937 };
1939 /* The "default" register map used in 64bit mode. */
1942 {
1950 };
1952 /* Define the register numbers to be used in Dwarf debugging information.
1953 The SVR4 reference port C compiler uses the following register numbers
1954 in its Dwarf output code:
1955 0 for %eax (gcc regno = 0)
1956 1 for %ecx (gcc regno = 2)
1957 2 for %edx (gcc regno = 1)
1958 3 for %ebx (gcc regno = 3)
1959 4 for %esp (gcc regno = 7)
1960 5 for %ebp (gcc regno = 6)
1961 6 for %esi (gcc regno = 4)
1962 7 for %edi (gcc regno = 5)
1963 The following three DWARF register numbers are never generated by
1964 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1965 believes these numbers have these meanings.
1966 8 for %eip (no gcc equivalent)
1967 9 for %eflags (gcc regno = 17)
1968 10 for %trapno (no gcc equivalent)
1969 It is not at all clear how we should number the FP stack registers
1970 for the x86 architecture. If the version of SDB on x86/svr4 were
1971 a bit less brain dead with respect to floating-point then we would
1972 have a precedent to follow with respect to DWARF register numbers
1973 for x86 FP registers, but the SDB on x86/svr4 is so completely
1974 broken with respect to FP registers that it is hardly worth thinking
1975 of it as something to strive for compatibility with.
1976 The version of x86/svr4 SDB I have at the moment does (partially)
1977 seem to believe that DWARF register number 11 is associated with
1978 the x86 register %st(0), but that's about all. Higher DWARF
1979 register numbers don't seem to be associated with anything in
1980 particular, and even for DWARF regno 11, SDB only seems to under-
1981 stand that it should say that a variable lives in %st(0) (when
1982 asked via an `=' command) if we said it was in DWARF regno 11,
1983 but SDB still prints garbage when asked for the value of the
1984 variable in question (via a `/' command).
1985 (Also note that the labels SDB prints for various FP stack regs
1986 when doing an `x' command are all wrong.)
1987 Note that these problems generally don't affect the native SVR4
1988 C compiler because it doesn't allow the use of -O with -g and
1989 because when it is *not* optimizing, it allocates a memory
1990 location for each floating-point variable, and the memory
1991 location is what gets described in the DWARF AT_location
1992 attribute for the variable in question.
1993 Regardless of the severe mental illness of the x86/svr4 SDB, we
1994 do something sensible here and we use the following DWARF
1995 register numbers. Note that these are all stack-top-relative
1996 numbers.
1997 11 for %st(0) (gcc regno = 8)
1998 12 for %st(1) (gcc regno = 9)
1999 13 for %st(2) (gcc regno = 10)
2000 14 for %st(3) (gcc regno = 11)
2001 15 for %st(4) (gcc regno = 12)
2002 16 for %st(5) (gcc regno = 13)
2003 17 for %st(6) (gcc regno = 14)
2004 18 for %st(7) (gcc regno = 15)
2005 */
2007 {
2015 };
2017 /* Define parameter passing and return registers. */
2020 {
2022 };
2025 {
2027 };
2030 {
2032 };
2034 /* Define the structure for the machine field in struct function. */
2039 rtx rtl;
2041 };
2043 /* Structure describing stack frame layout.
2044 Stack grows downward:
2046 [arguments]
2047 <- ARG_POINTER
2048 saved pc
2050 saved static chain if ix86_static_chain_on_stack
2052 saved frame pointer if frame_pointer_needed
2053 <- HARD_FRAME_POINTER
2054 [saved regs]
2055 <- regs_save_offset
2056 [padding0]
2058 [saved SSE regs]
2059 <- sse_regs_save_offset
2060 [padding1] |
2061 | <- FRAME_POINTER
2062 [va_arg registers] |
2063 |
2064 [frame] |
2065 |
2066 [padding2] | = to_allocate
2067 <- STACK_POINTER
2068 */
2069 struct ix86_frame
2070 {
2077 /* The offsets relative to ARG_POINTER. */
2078 HOST_WIDE_INT frame_pointer_offset;
2079 HOST_WIDE_INT hard_frame_pointer_offset;
2080 HOST_WIDE_INT stack_pointer_offset;
2081 HOST_WIDE_INT hfp_save_offset;
2082 HOST_WIDE_INT reg_save_offset;
2083 HOST_WIDE_INT sse_reg_save_offset;
2085 /* When save_regs_using_mov is set, emit prologue using
2086 move instead of push instructions. */
2088 };
2090 /* Which cpu are we scheduling for. */
2093 /* Which cpu are we optimizing for. */
2096 /* Which instruction set architecture to use. */
2099 /* True if processor has SSE prefetch instruction. */
2102 /* -mstackrealign option */
2119 /* Preferred alignment for stack boundary in bits. */
2122 /* Alignment for incoming stack boundary in bits specified at
2123 command line. */
2126 /* Default alignment for incoming stack boundary in bits. */
2129 /* Alignment for incoming stack boundary in bits. */
2132 /* Calling abi specific va_list type nodes. */
2136 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2140 /* Fence to use after loop using movnt. */
2141 tree x86_mfence;
2143 /* Register class used for passing given 64bit part of the argument.
2144 These represent classes as documented by the PS ABI, with the exception
2145 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2146 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2148 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2149 whenever possible (upper half does contain padding). */
2150 enum x86_64_reg_class
2151 {
2152 X86_64_NO_CLASS,
2153 X86_64_INTEGER_CLASS,
2154 X86_64_INTEGERSI_CLASS,
2155 X86_64_SSE_CLASS,
2156 X86_64_SSESF_CLASS,
2157 X86_64_SSEDF_CLASS,
2158 X86_64_SSEUP_CLASS,
2159 X86_64_X87_CLASS,
2160 X86_64_X87UP_CLASS,
2161 X86_64_COMPLEX_X87_CLASS,
2162 X86_64_MEMORY_CLASS
2163 };
2165 #define MAX_CLASSES 4
2167 /* Table of constants used by fldpi, fldln2, etc.... */
2171 \f
2176 const_tree);
2188 enum ix86_function_specific_strings
2189 {
2190 IX86_FUNCTION_SPECIFIC_ARCH,
2191 IX86_FUNCTION_SPECIFIC_TUNE,
2192 IX86_FUNCTION_SPECIFIC_MAX
2193 };
2211 \f
2212 #ifndef SUBTARGET32_DEFAULT_CPU
2214 #endif
2216 /* The svr4 ABI for the i386 says that records and unions are returned
2217 in memory. */
2218 #ifndef DEFAULT_PCC_STRUCT_RETURN
2219 #define DEFAULT_PCC_STRUCT_RETURN 1
2220 #endif
2222 /* Whether -mtune= or -march= were specified */
2226 /* Vectorization library interface and handlers. */
2232 /* Processor target table, indexed by processor number */
2233 struct ptt
2234 {
2241 };
2244 {
2255 /* Core 2 32-bit. */
2257 /* Core 2 64-bit. */
2259 /* Core i7 32-bit. */
2261 /* Core i7 64-bit. */
2271 };
2274 {
2301 "btver2"
2302 };
2303 \f
2304 /* Return true if a red-zone is in use. */
2308 {
2310 }
2311 \f
2312 /* Return a string that documents the current -m options. The caller is
2313 responsible for freeing the string. */
2319 {
2320 struct ix86_target_opts
2321 {
2324 };
2326 /* This table is ordered so that options like -msse4.2 that imply
2327 preceding options while match those first. */
2329 {
2365 };
2367 /* Flag options. */
2369 {
2397 };
2414 /* Add -march= option. */
2416 {
2419 }
2421 /* Add -mtune= option. */
2423 {
2426 }
2428 /* Add -m32/-m64/-mx32. */
2430 {
2433 else
2435 isa &= ~ (OPTION_MASK_ISA_64BIT
2436 | OPTION_MASK_ABI_64
2438 }
2439 else
2443 /* Pick out the options in isa options. */
2445 {
2447 {
2450 }
2451 }
2454 {
2457 isa);
2458 }
2460 /* Add flag options. */
2462 {
2464 {
2467 }
2468 }
2471 {
2474 }
2476 /* Add -fpmath= option. */
2478 {
2481 {
2496 }
2497 }
2499 /* Any options? */
2505 /* Size the string. */
2509 {
2514 }
2516 /* Build the string. */
2521 {
2528 {
2530 line_len++;
2533 {
2537 }
2538 }
2542 {
2546 }
2547 }
2553 }
2555 /* Return true, if profiling code should be emitted before
2556 prologue. Otherwise it returns false.
2557 Note: For x86 with "hotfix" it is sorried. */
2558 static bool
2560 {
2562 }
2564 /* Function that is callable from the debugger to print the current
2565 options. */
2566 void
2568 {
2574 {
2577 }
2578 else
2582 }
2583 \f
2584 /* Override various settings based on options. If MAIN_ARGS_P, the
2585 options are from the command line, otherwise they are from
2586 attributes. */
2588 static void
2590 {
2598 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2599 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2600 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2601 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2602 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2603 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2604 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2605 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2606 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2607 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2608 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2609 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2610 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2611 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2612 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2613 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2614 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2615 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2616 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2617 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2618 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2619 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2620 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2621 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2622 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2623 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2624 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2625 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2626 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2627 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2628 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2629 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2630 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2631 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2632 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2633 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2634 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2635 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2636 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2637 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2639 /* if this reaches 64, need to widen struct pta flags below */
2641 static struct pta
2642 {
2647 }
2649 {
2773 PTA_64BIT
2775 };
2777 /* -mrecip options. */
2778 static struct
2779 {
2782 }
2784 {
2791 };
2795 /* Set up prefix/suffix so the error messages refer to either the command
2796 line argument, or the attribute(target). */
2798 {
2802 }
2803 else
2804 {
2808 }
2810 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
2811 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
2814 #ifdef TARGET_BI_ARCH
2815 else
2816 {
2817 #if TARGET_BI_ARCH == 1
2818 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
2819 is on and OPTION_MASK_ABI_X32 is off. We turn off
2820 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
2821 -mx32. */
2824 #else
2825 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
2826 on and OPTION_MASK_ABI_64 is off. We turn off
2827 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
2828 -m64. */
2831 #endif
2832 }
2833 #endif
2836 {
2837 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
2838 OPTION_MASK_ABI_64 for TARGET_X32. */
2841 }
2843 {
2844 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
2845 OPTION_MASK_ABI_X32 for TARGET_LP64. */
2848 }
2850 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2851 SUBTARGET_OVERRIDE_OPTIONS;
2852 #endif
2854 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2855 SUBSUBTARGET_OVERRIDE_OPTIONS;
2856 #endif
2858 /* -fPIC is the default for x86_64. */
2862 /* Need to check -mtune=generic first. */
2864 {
2867 /* As special support for cross compilers we read -mtune=native
2868 as -mtune=generic. With native compilers we won't see the
2869 -mtune=native, as it was changed by the driver. */
2871 {
2874 else
2876 }
2877 /* If this call is for setting the option attribute, allow the
2878 generic32/generic64 that was previously set. */
2882 ;
2890 }
2891 else
2892 {
2896 {
2899 }
2901 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2902 need to use a sensible tune option. */
2906 {
2909 else
2911 }
2912 }
2915 {
2916 /* rep; movq isn't available in 32-bit code. */
2919 }
2923 else
2927 {
2933 }
2934 else
2941 {
2943 {
2987 {
2990 }
2998 }
2999 }
3000 else
3001 {
3002 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3003 use of rip-relative addressing. This eliminates fixups that
3004 would otherwise be needed if this object is to be placed in a
3005 DLL, and is essentially just as efficient as direct addressing. */
3010 else
3012 }
3014 {
3017 }
3024 {
3027 /* Default cpu tuning to the architecture. */
3152 }
3167 {
3171 {
3173 {
3175 {
3183 }
3184 else
3187 }
3188 }
3189 else
3190 {
3191 /* Adjust tuning when compiling for 32-bit ABI. */
3193 {
3209 }
3210 }
3211 /* Intel CPUs have always interpreted SSE prefetch instructions as
3212 NOPs; so, we can enable SSE prefetch instructions even when
3213 -mtune (rather than -march) points us to a processor that has them.
3214 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3215 higher processors. */
3220 }
3230 #ifndef USE_IX86_FRAME_POINTER
3231 #define USE_IX86_FRAME_POINTER 0
3232 #endif
3234 #ifndef USE_X86_64_FRAME_POINTER
3235 #define USE_X86_64_FRAME_POINTER 0
3236 #endif
3238 /* Set the default values for switches whose default depends on TARGET_64BIT
3239 in case they weren't overwritten by command line options. */
3241 {
3248 }
3249 else
3250 {
3257 }
3262 else
3265 /* Arrange to set up i386_stack_locals for all functions. */
3268 /* Validate -mregparm= value. */
3270 {
3274 {
3278 }
3279 }
3283 /* Default align_* from the processor table. */
3285 {
3288 }
3290 {
3293 }
3295 {
3297 }
3299 /* Provide default for -mbranch-cost= value. */
3304 {
3307 /* Enable by default the SSE and MMX builtins. Do allow the user to
3308 explicitly disable any of these. In particular, disabling SSE and
3309 MMX for kernel code is extremely useful. */
3311 ix86_isa_flags
3317 }
3318 else
3319 {
3323 ix86_isa_flags
3326 /* i386 ABI does not specify red zone. It still makes sense to use it
3327 when programmer takes care to stack from being destroyed. */
3330 }
3332 /* Keep nonleaf frame pointers. */
3338 /* If we're doing fast math, we don't care about comparison order
3339 wrt NaNs. This lets us use a shorter comparison sequence. */
3343 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3344 since the insns won't need emulation. */
3348 /* Likewise, if the target doesn't have a 387, or we've specified
3349 software floating point, don't use 387 inline intrinsics. */
3353 /* Turn on MMX builtins for -msse. */
3357 /* Enable SSE prefetch. */
3361 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3365 /* Turn on lzcnt instruction for -mabm. */
3369 /* Validate -mpreferred-stack-boundary= value or default it to
3370 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3373 {
3379 {
3383 else
3386 }
3387 else
3388 ix86_preferred_stack_boundary
3390 }
3392 /* Set the default value for -mstackrealign. */
3398 /* Validate -mincoming-stack-boundary= value or default it to
3399 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3402 {
3407 else
3408 {
3409 ix86_user_incoming_stack_boundary
3411 ix86_incoming_stack_boundary
3413 }
3414 }
3416 /* Accept -msseregparm only if at least SSE support is enabled. */
3422 {
3424 {
3426 {
3429 }
3431 {
3434 }
3435 }
3436 }
3437 else
3440 /* If the i387 is disabled, then do not return values in it. */
3444 /* Use external vectorized library in vectorizing intrinsics. */
3447 {
3458 }
3466 /* ??? Unwind info is not correct around the CFG unless either a frame
3467 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3468 unwind info generation to be aware of the CFG and propagating states
3469 around edges. */
3472 && flag_omit_frame_pointer
3474 {
3480 }
3482 /* If stack probes are required, the space used for large function
3483 arguments on the stack must also be probed, so enable
3484 -maccumulate-outgoing-args so this happens in the prologue. */
3487 {
3492 }
3494 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3495 {
3501 }
3503 /* When scheduling description is not available, disable scheduler pass
3504 so it won't slow down the compilation and make x87 code slower. */
3525 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3527 && HAVE_prefetch
3532 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3533 can be optimized to ap = __builtin_next_arg (0). */
3538 {
3541 {
3544 ix86_gen_tls_local_dynamic_base_64
3546 }
3547 else
3548 {
3551 ix86_gen_tls_local_dynamic_base_64
3553 }
3554 }
3555 else
3556 {
3559 }
3562 {
3571 }
3572 else
3573 {
3582 }
3584 #ifdef USE_IX86_CLD
3585 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3588 #endif
3591 {
3596 }
3598 {
3602 }
3604 {
3605 #if defined(PROFILE_BEFORE_PROLOGUE)
3607 #else
3609 #endif
3610 }
3613 {
3614 /* When not optimize for size, enable vzeroupper optimization for
3615 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3616 AVX unaligned load/store. */
3618 {
3628 /* Enable 128-bit AVX instruction generation
3629 for the auto-vectorizer. */
3633 }
3634 }
3635 else
3636 {
3637 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3639 }
3642 {
3649 {
3652 {
3654 q++;
3655 }
3656 else
3661 else
3662 {
3665 {
3668 }
3671 {
3675 }
3676 }
3681 else
3683 }
3684 }
3691 /* Default long double to 64-bit for Bionic. */
3696 /* Save the initial options in case the user does function specific
3697 options. */
3699 target_option_default_node = target_option_current_node
3701 }
3703 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3705 static void
3707 {
3709 }
3711 /* Update register usage after having seen the compiler flags. */
3713 static void
3715 {
3719 /* The PIC register, if it exists, is fixed. */
3724 /* For 32-bit targets, squash the REX registers. */
3726 {
3731 }
3733 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3741 {
3742 /* Set/reset conditionally defined registers from
3743 CALL_USED_REGISTERS initializer. */
3747 /* Calculate registers of CLOBBERED_REGS register set
3748 as call used registers from GENERAL_REGS register set. */
3752 }
3754 /* If MMX is disabled, squash the registers. */
3760 /* If SSE is disabled, squash the registers. */
3766 /* If the FPU is disabled, squash the registers. */
3771 }
3773 \f
3774 /* Save the current options */
3776 static void
3778 {
3789 /* The fields are char but the variables are not; make sure the
3790 values fit in the fields. */
3795 }
3797 /* Restore the current options */
3799 static void
3801 {
3817 /* Recreate the arch feature tests if the arch changed */
3819 {
3824 }
3826 /* Recreate the tune optimization tests */
3828 {
3833 }
3834 }
3836 /* Print the current options */
3838 static void
3841 {
3863 {
3866 }
3867 }
3869 \f
3870 /* Inner function to process the attribute((target(...))), take an argument and
3871 set the current options from the argument. If we have a list, recursively go
3872 over the list. */
3874 static bool
3877 {
3881 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3882 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3883 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
3884 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3885 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3887 enum ix86_opt_type
3888 {
3889 ix86_opt_unknown,
3890 ix86_opt_yes,
3891 ix86_opt_no,
3892 ix86_opt_str,
3893 ix86_opt_enum,
3894 ix86_opt_isa
3895 };
3897 static const struct
3898 {
3905 /* isa options */
3942 /* enum options */
3945 /* string options */
3949 /* flag options */
3951 OPT_mcld,
3952 MASK_CLD),
3955 OPT_mfancy_math_387,
3956 MASK_NO_FANCY_MATH_387),
3959 OPT_mieee_fp,
3960 MASK_IEEE_FP),
3963 OPT_minline_all_stringops,
3964 MASK_INLINE_ALL_STRINGOPS),
3967 OPT_minline_stringops_dynamically,
3968 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3971 OPT_mno_align_stringops,
3972 MASK_NO_ALIGN_STRINGOPS),
3975 OPT_mrecip,
3976 MASK_RECIP),
3978 };
3980 /* If this is a list, recurse to get the options. */
3982 {
3992 }
3997 /* Handle multiple arguments separated by commas. */
4001 {
4015 {
4019 }
4020 else
4021 {
4024 }
4026 /* Recognize no-xxx. */
4028 {
4032 }
4033 else
4036 /* Find the option. */
4040 {
4048 {
4053 }
4054 }
4056 /* Process the option. */
4058 {
4061 }
4064 {
4070 }
4073 {
4079 else
4081 }
4084 {
4086 {
4089 }
4090 else
4092 }
4095 {
4103 global_dc);
4104 else
4105 {
4108 }
4109 }
4111 else
4113 }
4116 }
4118 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4120 tree
4122 {
4137 /* Process each of the options on the chain. */
4142 /* If the changed options are different from the default, rerun
4143 ix86_option_override_internal, and then save the options away.
4144 The string options are are attribute options, and will be undone
4145 when we copy the save structure. */
4151 {
4152 /* If we are using the default tune= or arch=, undo the string assigned,
4153 and use the default. */
4164 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4168 {
4171 }
4173 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4176 /* Add any builtin functions with the new isa if any. */
4179 /* Save the current options unless we are validating options for
4180 #pragma. */
4187 /* Free up memory allocated to hold the strings */
4190 }
4193 }
4195 /* Hook to validate attribute((target("string"))). */
4197 static bool
4200 tree args,
4202 {
4209 /* If the function changed the optimization levels as well as setting target
4210 options, start with the optimizations specified. */
4215 /* The target attributes may also change some optimization flags, so update
4216 the optimization options if necessary. */
4225 {
4230 }
4239 }
4241 \f
4242 /* Hook to determine if one function can safely inline another. */
4244 static bool
4246 {
4251 /* If callee has no option attributes, then it is ok to inline. */
4255 /* If caller has no option attributes, but callee does then it is not ok to
4256 inline. */
4260 else
4261 {
4265 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4266 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4267 function. */
4272 /* See if we have the same non-isa options. */
4276 /* See if arch, tune, etc. are the same. */
4289 else
4291 }
4294 }
4296 \f
4297 /* Remember the last target of ix86_set_current_function. */
4300 /* Establish appropriate back-end context for processing the function
4301 FNDECL. The argument might be NULL to indicate processing at top
4302 level, outside of any function scope. */
4303 static void
4305 {
4306 /* Only change the context if the function changes. This hook is called
4307 several times in the course of compiling a function, and we don't want to
4308 slow things down too much or call target_reinit when it isn't safe. */
4310 {
4311 tree old_tree = (ix86_previous_fndecl
4315 tree new_tree = (fndecl
4321 ;
4324 {
4328 }
4331 {
4337 }
4338 }
4339 }
4341 \f
4342 /* Return true if this goes in large data/bss. */
4344 static bool
4346 {
4350 /* Functions are never large data. */
4355 {
4361 }
4362 else
4363 {
4366 /* If this is an incomplete type with size 0, then we can't put it
4367 in data because it might be too big when completed. */
4370 }
4373 }
4375 /* Switch to the appropriate section for output of DECL.
4376 DECL is either a `VAR_DECL' node or a constant of some sort.
4377 RELOC indicates whether forming the initial value of DECL requires
4378 link-time relocations. */
4381 ATTRIBUTE_UNUSED;
4386 {
4389 {
4393 {
4427 /* We don't split these for medium model. Place them into
4428 default sections and hope for best. */
4430 }
4432 {
4433 /* We might get called with string constants, but get_named_section
4434 doesn't like them as they are not DECLs. Also, we need to set
4435 flags in that case. */
4439 }
4440 }
4442 }
4444 /* Build up a unique section name, expressed as a
4445 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4446 RELOC indicates whether the initial value of EXP requires
4447 link-time relocations. */
4449 static void ATTRIBUTE_UNUSED
4451 {
4454 {
4456 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4460 {
4484 /* We don't split these for medium model. Place them into
4485 default sections and hope for best. */
4487 }
4489 {
4496 /* If we're using one_only, then there needs to be a .gnu.linkonce
4497 prefix to the section name. */
4504 }
4505 }
4507 }
4509 #ifdef COMMON_ASM_OP
4510 /* This says how to output assembler code to declare an
4511 uninitialized external linkage data object.
4513 For medium model x86-64 we need to use .largecomm opcode for
4514 large objects. */
4515 void
4519 {
4523 else
4528 }
4529 #endif
4531 /* Utility function for targets to use in implementing
4532 ASM_OUTPUT_ALIGNED_BSS. */
4534 void
4538 {
4542 else
4545 #ifdef ASM_DECLARE_OBJECT_NAME
4548 #else
4549 /* Standard thing is just output label for the object. */
4553 }
4554 \f
4555 /* Decide whether we must probe the stack before any space allocation
4556 on this target. It's essentially TARGET_STACK_PROBE except when
4557 -fstack-check causes the stack to be already probed differently. */
4559 bool
4561 {
4562 /* Do not probe the stack twice if static stack checking is enabled. */
4567 }
4568 \f
4569 /* Decide whether we can make a sibling call to a function. DECL is the
4570 declaration of the function being targeted by the call and EXP is the
4571 CALL_EXPR representing the call. */
4573 static bool
4575 {
4579 /* If we are generating position-independent code, we cannot sibcall
4580 optimize any indirect call, or a direct call to a global function,
4581 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4583 && !TARGET_64BIT
4584 && flag_pic
4588 /* If we need to align the outgoing stack, then sibcalling would
4589 unalign the stack, which may break the called function. */
4595 {
4598 }
4599 else
4600 {
4601 /* We're looking at the CALL_EXPR, we need the type of the function. */
4606 }
4608 /* Check that the return value locations are the same. Like
4609 if we are returning floats on the 80387 register stack, we cannot
4610 make a sibcall from a function that doesn't return a float to a
4611 function that does or, conversely, from a function that does return
4612 a float to a function that doesn't; the necessary stack adjustment
4613 would not be executed. This is also the place we notice
4614 differences in the return value ABI. Note that it is ok for one
4615 of the functions to have void return type as long as the return
4616 value of the other is passed in a register. */
4621 {
4624 }
4626 ;
4631 {
4632 /* The SYSV ABI has more call-clobbered registers;
4633 disallow sibcalls from MS to SYSV. */
4637 }
4638 else
4639 {
4640 /* If this call is indirect, we'll need to be able to use a
4641 call-clobbered register for the address of the target function.
4642 Make sure that all such registers are not used for passing
4643 parameters. Note that DLLIMPORT functions are indirect. */
4646 {
4648 {
4649 /* ??? Need to count the actual number of registers to be used,
4650 not the possible number of registers. Fix later. */
4652 }
4653 }
4654 }
4656 /* Otherwise okay. That also includes certain types of indirect calls. */
4658 }
4660 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4661 and "sseregparm" calling convention attributes;
4662 arguments as in struct attribute_spec.handler. */
4664 static tree
4666 tree args,
4669 {
4674 {
4676 name);
4679 }
4681 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4683 {
4684 tree cst;
4687 {
4689 }
4692 {
4694 }
4698 {
4701 name);
4703 }
4705 {
4709 }
4712 }
4715 {
4716 /* Do not warn when emulating the MS ABI. */
4721 name);
4724 }
4726 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4728 {
4730 {
4732 }
4734 {
4736 }
4738 {
4740 }
4742 {
4744 }
4745 }
4747 /* Can combine stdcall with fastcall (redundant), regparm and
4748 sseregparm. */
4750 {
4752 {
4754 }
4756 {
4758 }
4760 {
4762 }
4763 }
4765 /* Can combine cdecl with regparm and sseregparm. */
4767 {
4769 {
4771 }
4773 {
4775 }
4777 {
4779 }
4780 }
4782 {
4785 name);
4787 {
4789 }
4791 {
4793 }
4795 {
4797 }
4798 }
4800 /* Can combine sseregparm with all attributes. */
4803 }
4805 /* The transactional memory builtins are implicitly regparm or fastcall
4806 depending on the ABI. Override the generic do-nothing attribute that
4807 these builtins were declared with, and replace it with one of the two
4808 attributes that we expect elsewhere. */
4810 static tree
4812 tree args ATTRIBUTE_UNUSED,
4815 {
4816 tree alt;
4818 /* In no case do we want to add the placeholder attribute. */
4821 /* The 64-bit ABI is unchanged for transactional memory. */
4825 /* ??? Is there a better way to validate 32-bit windows? We have
4826 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
4829 else
4830 {
4833 }
4837 }
4839 /* This function determines from TYPE the calling-convention. */
4841 unsigned int
4843 {
4846 tree attrs;
4853 {
4863 /* Regparam isn't allowed for thiscall and fastcall. */
4865 {
4870 }
4874 }
4881 || is_stdarg
4887 }
4889 /* Return 0 if the attributes for two types are incompatible, 1 if they
4890 are compatible, and 2 if they are nearly compatible (which causes a
4891 warning to be generated). */
4893 static int
4895 {
4911 }
4912 \f
4913 /* Return the regparm value for a function with the indicated TYPE and DECL.
4914 DECL may be NULL when calling function indirectly
4915 or considering a libcall. */
4917 static int
4919 {
4920 tree attr;
4931 {
4934 {
4937 }
4938 }
4944 /* Use register calling convention for local functions when possible. */
4947 && optimize
4949 {
4950 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4953 {
4956 /* Make sure no regparm register is taken by a
4957 fixed register variable. */
4962 /* We don't want to use regparm(3) for nested functions as
4963 these use a static chain pointer in the third argument. */
4967 /* In 32-bit mode save a register for the split stack. */
4971 /* Each fixed register usage increases register pressure,
4972 so less registers should be used for argument passing.
4973 This functionality can be overriden by an explicit
4974 regparm value. */
4977 globals++;
4979 local_regparm
4984 }
4985 }
4988 }
4990 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4991 DFmode (2) arguments in SSE registers for a function with the
4992 indicated TYPE and DECL. DECL may be NULL when calling function
4993 indirectly or considering a libcall. Otherwise return 0. */
4995 static int
4997 {
5000 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5001 by the sseregparm attribute. */
5004 {
5006 {
5008 {
5012 else
5015 }
5017 }
5020 }
5022 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5023 (and DFmode for SSE2) arguments in SSE registers. */
5026 {
5027 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5031 }
5034 }
5036 /* Return true if EAX is live at the start of the function. Used by
5037 ix86_expand_prologue to determine if we need special help before
5038 calling allocate_stack_worker. */
5040 static bool
5042 {
5043 /* Cheat. Don't bother working forward from ix86_function_regparm
5044 to the function type to whether an actual argument is located in
5045 eax. Instead just look at cfg info, which is still close enough
5046 to correct at this point. This gives false positives for broken
5047 functions that might use uninitialized data that happens to be
5048 allocated in eax, but who cares? */
5050 }
5052 static bool
5054 {
5055 tree attr;
5058 {
5064 /* For 32-bit MS-ABI the default is to keep aggregate
5065 return pointer. */
5068 }
5070 }
5072 /* Value is the number of bytes of arguments automatically
5073 popped when returning from a subroutine call.
5074 FUNDECL is the declaration node of the function (as a tree),
5075 FUNTYPE is the data type of the function (as a tree),
5076 or for a library call it is an identifier node for the subroutine name.
5077 SIZE is the number of bytes of arguments passed on the stack.
5079 On the 80386, the RTD insn may be used to pop them if the number
5080 of args is fixed, but if the number is variable then the caller
5081 must pop them all. RTD can't be used for library calls now
5082 because the library is compiled with the Unix compiler.
5083 Use of RTD is a selectable option, since it is incompatible with
5084 standard Unix calling sequences. If the option is not selected,
5085 the caller must always pop the args.
5087 The attribute stdcall is equivalent to RTD on a per module basis. */
5089 static int
5091 {
5094 /* None of the 64-bit ABIs pop arguments. */
5105 /* Lose any fake structure return argument if it is passed on the stack. */
5108 {
5112 }
5115 }
5117 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5119 static bool
5121 {
5122 /* Check operand constraints in case hard registers were propagated
5123 into insn pattern. This check prevents combine pass from
5124 generating insn patterns with invalid hard register operands.
5125 These invalid insns can eventually confuse reload to error out
5126 with a spill failure. See also PRs 46829 and 46843. */
5128 {
5135 {
5143 /* A unary operator may be accepted by the predicate, but it
5144 is irrelevant for matching constraints. */
5149 {
5157 }
5164 /* Operand has no constraints, anything is OK. */
5168 {
5171 && operands_match_p
5175 {
5178 }
5179 }
5183 }
5184 }
5187 }
5188 \f
5189 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5191 static unsigned HOST_WIDE_INT
5193 {
5195 }
5196 \f
5197 /* Argument support functions. */
5199 /* Return true when register may be used to pass function parameters. */
5200 bool
5202 {
5207 {
5211 else
5217 }
5220 {
5223 }
5224 else
5225 {
5229 }
5231 /* TODO: The function should depend on current function ABI but
5232 builtins.c would need updating then. Therefore we use the
5233 default ABI. */
5235 /* RAX is used as hidden argument to va_arg functions. */
5241 else
5248 }
5250 /* Return if we do not know how to pass TYPE solely in registers. */
5252 static bool
5254 {
5258 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5259 The layout_type routine is crafty and tries to trick us into passing
5260 currently unsupported vector types on the stack by using TImode. */
5263 }
5265 /* It returns the size, in bytes, of the area reserved for arguments passed
5266 in registers for the function represented by fndecl dependent to the used
5267 abi format. */
5268 int
5270 {
5274 else
5279 }
5281 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5282 call abi used. */
5283 enum calling_abi
5285 {
5287 {
5290 {
5293 }
5297 }
5299 }
5301 static bool
5303 {
5305 {
5309 else
5311 }
5313 }
5315 static enum calling_abi
5317 {
5321 }
5323 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5324 call abi used. */
5325 enum calling_abi
5327 {
5331 }
5333 /* Write the extra assembler code needed to declare a function properly. */
5335 void
5337 tree decl)
5338 {
5342 {
5348 }
5350 #ifdef SUBTARGET_ASM_UNWIND_INIT
5352 #endif
5356 /* Output magic byte marker, if hot-patch attribute is set. */
5358 {
5360 {
5361 /* leaq [%rsp + 0], %rsp */
5364 }
5365 else
5366 {
5367 /* movl.s %edi, %edi
5368 push %ebp
5369 movl.s %esp, %ebp */
5372 }
5373 }
5374 }
5376 /* regclass.c */
5379 /* Implementation of call abi switching target hook. Specific to FNDECL
5380 the specific call register sets are set. See also
5381 ix86_conditional_register_usage for more details. */
5382 void
5384 {
5387 else
5389 }
5391 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5392 expensive re-initialization of init_regs each time we switch function context
5393 since this is needed only during RTL expansion. */
5394 static void
5396 {
5400 }
5402 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5403 for a call to a function whose data type is FNTYPE.
5404 For a library call, FNTYPE is 0. */
5406 void
5410 tree fndecl,
5412 {
5418 {
5421 }
5422 else
5423 {
5426 }
5430 /* Set up the number of registers to use for passing arguments. */
5437 {
5439 ? X86_64_REGPARM_MAX
5441 }
5443 {
5446 {
5448 ? X86_64_SSE_REGPARM_MAX
5450 }
5451 }
5458 /* Because type might mismatch in between caller and callee, we need to
5459 use actual type of function for local calls.
5460 FIXME: cgraph_analyze can be told to actually record if function uses
5461 va_start so for local functions maybe_vaarg can be made aggressive
5462 helping K&R code.
5463 FIXME: once typesytem is fixed, we won't need this code anymore. */
5471 {
5472 /* If there are variable arguments, then we won't pass anything
5473 in registers in 32-bit mode. */
5475 {
5483 }
5485 /* Use ecx and edx registers if function has fastcall attribute,
5486 else look for regparm information. */
5488 {
5491 {
5494 }
5496 {
5499 }
5500 else
5502 }
5504 /* Set up the number of SSE registers used for passing SFmode
5505 and DFmode arguments. Warn for mismatching ABI. */
5507 }
5508 }
5510 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5511 But in the case of vector types, it is some vector mode.
5513 When we have only some of our vector isa extensions enabled, then there
5514 are some modes for which vector_mode_supported_p is false. For these
5515 modes, the generic vector support in gcc will choose some non-vector mode
5516 in order to implement the type. By computing the natural mode, we'll
5517 select the proper ABI location for the operand and not depend on whatever
5518 the middle-end decides to do with these vector types.
5520 The midde-end can't deal with the vector types > 16 bytes. In this
5521 case, we return the original mode and warn ABI change if CUM isn't
5522 NULL. */
5524 static enum machine_mode
5526 {
5530 {
5533 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5535 {
5540 else
5543 /* Get the mode which has this inner mode and number of units. */
5547 {
5549 {
5553 && !warnedavx
5555 {
5559 }
5561 }
5563 {
5567 && !warnedsse
5569 {
5573 }
5575 }
5576 else
5578 }
5581 }
5582 }
5585 }
5587 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5588 this may not agree with the mode that the type system has chosen for the
5589 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5590 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5592 static rtx
5595 {
5596 rtx tmp;
5600 else
5601 {
5605 }
5608 }
5610 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5611 of this code is to classify each 8bytes of incoming argument by the register
5612 class and assign registers accordingly. */
5614 /* Return the union class of CLASS1 and CLASS2.
5615 See the x86-64 PS ABI for details. */
5617 static enum x86_64_reg_class
5619 {
5620 /* Rule #1: If both classes are equal, this is the resulting class. */
5624 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5625 the other class. */
5631 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5635 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5643 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5644 MEMORY is used. */
5653 /* Rule #6: Otherwise class SSE is used. */
5655 }
5657 /* Classify the argument of type TYPE and mode MODE.
5658 CLASSES will be filled by the register class used to pass each word
5659 of the operand. The number of words is returned. In case the parameter
5660 should be passed in memory, 0 is returned. As a special case for zero
5661 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5663 BIT_OFFSET is used internally for handling records and specifies offset
5664 of the offset in bits modulo 256 to avoid overflow cases.
5666 See the x86-64 PS ABI for details.
5667 */
5669 static int
5672 {
5673 HOST_WIDE_INT bytes =
5675 int words
5678 /* Variable sized entities are always passed/returned in memory. */
5687 {
5689 tree field;
5692 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5699 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5700 signalize memory class, so handle it as special case. */
5702 {
5705 }
5707 /* Classify each field of record and merge classes. */
5709 {
5711 /* And now merge the fields of structure. */
5713 {
5715 {
5721 /* Bitfields are always classified as integer. Handle them
5722 early, since later code would consider them to be
5723 misaligned integers. */
5725 {
5734 }
5735 else
5736 {
5741 /* Flexible array member is ignored. */
5748 {
5752 {
5755 "the ABI of passing struct with"
5756 " a flexible array member has"
5758 }
5760 }
5762 subclasses,
5772 }
5773 }
5774 }
5778 /* Arrays are handled as small records. */
5779 {
5786 /* The partial classes are now full classes. */
5797 }
5800 /* Unions are similar to RECORD_TYPE but offset is always 0.
5801 */
5803 {
5805 {
5813 bit_offset);
5818 }
5819 }
5824 }
5827 {
5828 /* When size > 16 bytes, if the first one isn't
5829 X86_64_SSE_CLASS or any other ones aren't
5830 X86_64_SSEUP_CLASS, everything should be passed in
5831 memory. */
5838 }
5840 /* Final merger cleanup. */
5842 {
5843 /* If one class is MEMORY, everything should be passed in
5844 memory. */
5848 /* The X86_64_SSEUP_CLASS should be always preceded by
5849 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5853 {
5854 /* The first one should never be X86_64_SSEUP_CLASS. */
5857 }
5859 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5860 everything should be passed in memory. */
5863 {
5866 /* The first one should never be X86_64_X87UP_CLASS. */
5869 {
5872 "the ABI of passing union with long double"
5874 }
5876 }
5877 }
5879 }
5881 /* Compute alignment needed. We align all types to natural boundaries with
5882 exception of XFmode that is aligned to 64bits. */
5884 {
5893 /* Misaligned fields are always returned in memory. */
5896 }
5898 /* for V1xx modes, just use the base mode */
5903 /* Classification of atomic types. */
5905 {
5921 {
5925 {
5928 }
5930 {
5933 }
5935 {
5939 }
5941 {
5944 }
5945 else
5947 }
5954 /* OImode shouldn't be used directly. */
5961 else
5979 else
5980 {
5984 {
5987 "the ABI of passing structure with complex float"
5989 }
5992 }
6001 /* This modes is larger than 16 bytes. */
6044 else
6048 }
6049 }
6051 /* Examine the argument and return set number of register required in each
6052 class. Return 0 iff parameter should be passed in memory. */
6053 static int
6056 {
6066 {
6088 }
6090 }
6092 /* Construct container for the argument used by GCC interface. See
6093 FUNCTION_ARG for the detailed description. */
6095 static rtx
6099 {
6100 /* The following variables hold the static issued_error state. */
6114 rtx ret;
6125 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6126 some less clueful developer tries to use floating-point anyway. */
6128 {
6130 {
6132 {
6135 }
6136 }
6138 {
6141 }
6143 }
6145 /* Likewise, error if the ABI requires us to return values in the
6146 x87 registers and the user specified -mno-80387. */
6152 {
6154 {
6157 }
6159 }
6161 /* First construct simple cases. Avoid SCmode, since we want to use
6162 single register to pass this type. */
6165 {
6180 /* Zero sized array, struct or class. */
6184 }
6211 /* Otherwise figure out the entries of the PARALLEL. */
6213 {
6217 {
6222 /* Merge TImodes on aligned occasions here too. */
6224 tmpmode
6228 else
6230 /* We've requested 24 bytes we
6231 don't have mode for. Use DImode. */
6238 intreg++;
6246 sse_regno++;
6254 sse_regno++;
6259 {
6265 {
6267 i++;
6268 }
6269 else
6282 }
6288 sse_regno++;
6292 }
6293 }
6295 /* Empty aligned struct, union or class. */
6303 }
6305 /* Update the data in CUM to advance over an argument of mode MODE
6306 and data type TYPE. (TYPE is null for libcalls where that information
6307 may not be available.) */
6309 static void
6312 HOST_WIDE_INT words)
6313 {
6315 {
6322 /* FALLTHRU */
6333 {
6336 }
6340 /* OImode shouldn't be used directly. */
6349 /* FALLTHRU */
6365 {
6370 {
6373 }
6374 }
6384 {
6389 {
6392 }
6393 }
6395 }
6396 }
6398 static void
6401 {
6404 /* Unnamed 256bit vector mode parameters are passed on stack. */
6410 {
6415 }
6416 else
6417 {
6421 }
6422 }
6424 static void
6426 HOST_WIDE_INT words)
6427 {
6428 /* Otherwise, this should be passed indirect. */
6433 {
6436 }
6437 }
6439 /* Update the data in CUM to advance over an argument of mode MODE and
6440 data type TYPE. (TYPE is null for libcalls where that information
6441 may not be available.) */
6443 static void
6446 {
6452 else
6463 else
6465 }
6467 /* Define where to put the arguments to a function.
6468 Value is zero to push the argument on the stack,
6469 or a hard register in which to store the argument.
6471 MODE is the argument's machine mode.
6472 TYPE is the data type of the argument (as a tree).
6473 This is null for libcalls where that information may
6474 not be available.
6475 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6476 the preceding args and about the function being called.
6477 NAMED is nonzero if this argument is a named parameter
6478 (otherwise it is an extra parameter matching an ellipsis). */
6480 static rtx
6484 {
6487 /* Avoid the AL settings for the Unix64 ABI. */
6492 {
6499 /* FALLTHRU */
6505 {
6508 /* Fastcall allocates the first two DWORD (SImode) or
6509 smaller arguments to ECX and EDX if it isn't an
6510 aggregate type . */
6512 {
6518 /* ECX not EAX is the first allocated register. */
6521 }
6523 }
6532 /* FALLTHRU */
6534 /* In 32bit, we pass TImode in xmm registers. */
6542 {
6544 {
6548 }
6552 }
6556 /* OImode shouldn't be used directly. */
6566 {
6570 }
6580 {
6582 {
6586 }
6590 }
6592 }
6595 }
6597 static rtx
6600 {
6601 /* Handle a hidden AL argument containing number of registers
6602 for varargs x86-64 functions. */
6606 ? X86_64_SSE_REGPARM_MAX
6611 {
6621 /* Unnamed 256bit vector mode parameters are passed on stack. */
6625 }
6631 }
6633 static rtx
6636 HOST_WIDE_INT bytes)
6637 {
6640 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6641 We use value of -2 to specify that current function call is MSABI. */
6645 /* If we've run out of registers, it goes on the stack. */
6651 /* Only floating point modes are passed in anything but integer regs. */
6653 {
6656 else
6657 {
6660 /* Unnamed floating parameters are passed in both the
6661 SSE and integer registers. */
6667 }
6668 }
6669 /* Handle aggregated types passed in register. */
6671 {
6676 }
6679 }
6681 /* Return where to put the arguments to a function.
6682 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6684 MODE is the argument's machine mode. TYPE is the data type of the
6685 argument. It is null for libcalls where that information may not be
6686 available. CUM gives information about the preceding args and about
6687 the function being called. NAMED is nonzero if this argument is a
6688 named parameter (otherwise it is an extra parameter matching an
6689 ellipsis). */
6691 static rtx
6694 {
6698 rtx arg;
6702 else
6706 /* To simplify the code below, represent vector types with a vector mode
6707 even if MMX/SSE are not active. */
6715 else
6719 }
6721 /* A C expression that indicates when an argument must be passed by
6722 reference. If nonzero for an argument, a copy of that argument is
6723 made in memory and a pointer to the argument is passed instead of
6724 the argument itself. The pointer is passed in whatever way is
6725 appropriate for passing a pointer to that type. */
6727 static bool
6731 {
6734 /* See Windows x64 Software Convention. */
6736 {
6739 {
6740 /* Arrays are passed by reference. */
6745 {
6746 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6747 are passed by reference. */
6749 }
6750 }
6752 /* __m128 is passed by reference. */
6758 }
6759 }
6764 }
6766 /* Return true when TYPE should be 128bit aligned for 32bit argument
6767 passing ABI. XXX: This function is obsolete and is only used for
6768 checking psABI compatibility with previous versions of GCC. */
6770 static bool
6772 {
6784 {
6785 /* Walk the aggregates recursively. */
6787 {
6791 {
6792 tree field;
6794 /* Walk all the structure fields. */
6796 {
6800 }
6802 }
6805 /* Just for use if some languages passes arrays by value. */
6812 }
6813 }
6815 }
6817 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
6818 XXX: This function is obsolete and is only used for checking psABI
6819 compatibility with previous versions of GCC. */
6821 static unsigned int
6824 {
6825 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6826 natural boundaries. */
6828 {
6829 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6830 make an exception for SSE modes since these require 128bit
6831 alignment.
6833 The handling here differs from field_alignment. ICC aligns MMX
6834 arguments to 4 byte boundaries, while structure fields are aligned
6835 to 8 byte boundaries. */
6837 {
6840 }
6841 else
6842 {
6845 }
6846 }
6850 }
6852 /* Return true when TYPE should be 128bit aligned for 32bit argument
6853 passing ABI. */
6855 static bool
6857 {
6867 {
6868 /* Walk the aggregates recursively. */
6870 {
6874 {
6875 tree field;
6877 /* Walk all the structure fields. */
6879 field;
6881 {
6885 }
6887 }
6890 /* Just for use if some languages passes arrays by value. */
6897 }
6898 }
6899 else
6903 }
6905 /* Gives the alignment boundary, in bits, of an argument with the
6906 specified mode and type. */
6908 static unsigned int
6910 {
6913 {
6914 /* Since the main variant type is used for call, we convert it to
6915 the main variant type. */
6918 }
6919 else
6923 else
6924 {
6929 {
6930 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
6932 {
6935 }
6941 }
6944 && !warned
6946 saved_align))
6947 {
6950 "The ABI for passing parameters with %d-byte"
6953 }
6954 }
6957 }
6959 /* Return true if N is a possible register number of function value. */
6961 static bool
6963 {
6965 {
6970 /* TODO: The function should depend on current function ABI but
6971 builtins.c would need updating then. Therefore we use the
6972 default ABI. */
6984 }
6987 }
6989 /* Define how to find the value returned by a function.
6990 VALTYPE is the data type of the value (as a tree).
6991 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6992 otherwise, FUNC is 0. */
6994 static rtx
6997 {
7000 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7001 we normally prevent this case when mmx is not available. However
7002 some ABIs may require the result to be returned like DImode. */
7006 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7007 we prevent this case when sse is not available. However some ABIs
7008 may require the result to be returned like integer TImode. */
7013 /* 32-byte vector modes in %ymm0. */
7017 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7020 else
7021 /* Most things go in %eax. */
7024 /* Override FP return register with %xmm0 for local functions when
7025 SSE math is enabled or for functions with sseregparm attribute. */
7027 {
7032 }
7034 /* OImode shouldn't be used directly. */
7038 }
7040 static rtx
7042 const_tree valtype)
7043 {
7044 rtx ret;
7046 /* Handle libcalls, which don't provide a type node. */
7048 {
7052 {
7071 }
7074 }
7076 {
7077 /* Pointers are always returned in word_mode. */
7079 }
7085 /* For zero sized structures, construct_container returns NULL, but we
7086 need to keep rest of compiler happy by returning meaningful value. */
7091 }
7093 static rtx
7095 {
7099 {
7101 {
7114 }
7115 }
7117 }
7119 static rtx
7122 {
7134 else
7136 }
7138 static rtx
7141 {
7147 }
7149 /* Pointer function arguments and return values are promoted to
7150 word_mode. */
7152 static enum machine_mode
7156 {
7158 {
7161 }
7163 for_return);
7164 }
7166 /* Return true if a structure, union or array with MODE containing FIELD
7167 should be accessed using BLKmode. */
7169 static bool
7171 {
7172 /* Union with XFmode must be in BLKmode. */
7176 }
7178 rtx
7180 {
7182 }
7184 /* Return true iff type is returned in memory. */
7186 static bool ATTRIBUTE_UNUSED
7188 {
7189 HOST_WIDE_INT size;
7200 {
7201 /* User-created vectors small enough to fit in EAX. */
7205 /* MMX/3dNow values are returned in MM0,
7206 except when it doesn't exits or the ABI prescribes otherwise. */
7210 /* SSE values are returned in XMM0, except when it doesn't exist. */
7214 /* AVX values are returned in YMM0, except when it doesn't exist. */
7217 }
7225 /* OImode shouldn't be used directly. */
7229 }
7231 static bool ATTRIBUTE_UNUSED
7233 {
7236 }
7238 static bool ATTRIBUTE_UNUSED
7240 {
7243 /* __m128 is returned in xmm0. */
7248 /* Otherwise, the size must be exactly in [1248]. */
7250 }
7252 static bool
7254 {
7255 #ifdef SUBTARGET_RETURN_IN_MEMORY
7257 #else
7261 {
7264 else
7266 }
7267 else
7269 #endif
7270 }
7272 /* When returning SSE vector types, we have a choice of either
7273 (1) being abi incompatible with a -march switch, or
7274 (2) generating an error.
7275 Given no good solution, I think the safest thing is one warning.
7276 The user won't be able to use -Werror, but....
7278 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7279 called in response to actually generating a caller or callee that
7280 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7281 via aggregate_value_p for general type probing from tree-ssa. */
7283 static rtx
7285 {
7289 {
7290 /* Look at the return type of the function, not the function type. */
7294 {
7297 {
7301 }
7302 }
7305 {
7307 {
7311 }
7312 }
7313 }
7316 }
7318 \f
7319 /* Create the va_list data type. */
7321 /* Returns the calling convention specific va_list date type.
7322 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7324 static tree
7326 {
7329 /* For i386 we use plain pointer to argument area. */
7339 unsigned_type_node);
7342 unsigned_type_node);
7345 ptr_type_node);
7348 ptr_type_node);
7367 /* The correct type is an array type of one element. */
7369 }
7371 /* Setup the builtin va_list data type and for 64-bit the additional
7372 calling convention specific va_list data types. */
7374 static tree
7376 {
7379 /* Initialize abi specific va_list builtin types. */
7381 {
7382 tree t;
7384 {
7389 }
7390 else
7391 {
7396 }
7398 {
7403 }
7404 else
7405 {
7410 }
7411 }
7414 }
7416 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7418 static void
7420 {
7422 alias_set_type set;
7425 /* GPR size of varargs save area. */
7428 else
7431 /* FPR size of varargs save area. We don't need it if we don't pass
7432 anything in SSE registers. */
7435 else
7449 {
7457 }
7460 {
7464 /* Now emit code to save SSE registers. The AX parameter contains number
7465 of SSE parameter registers used to call this function, though all we
7466 actually check here is the zero/non-zero status. */
7471 label));
7473 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7474 we used movdqa (i.e. TImode) instead? Perhaps even better would
7475 be if we could determine the real mode of the data, via a hook
7476 into pass_stdarg. Ignore all that for now. */
7486 {
7495 }
7498 }
7499 }
7501 static void
7503 {
7507 /* Reset to zero, as there might be a sysv vaarg used
7508 before. */
7513 {
7524 }
7525 }
7527 static void
7531 {
7533 CUMULATIVE_ARGS next_cum;
7534 tree fntype;
7536 /* This argument doesn't appear to be used anymore. Which is good,
7537 because the old code here didn't suppress rtl generation. */
7545 /* For varargs, we do not want to skip the dummy va_dcl argument.
7546 For stdargs, we do want to skip the last named argument. */
7554 else
7556 }
7558 /* Checks if TYPE is of kind va_list char *. */
7560 static bool
7562 {
7563 tree canonic;
7565 /* For 32-bit it is always true. */
7571 }
7573 /* Implement va_start. */
7575 static void
7577 {
7581 tree type;
7582 rtx ovf_rtx;
7586 {
7589 /* When we are splitting the stack, we can't refer to the stack
7590 arguments using internal_arg_pointer, because they may be on
7591 the old stack. The split stack prologue will arrange to
7592 leave a pointer to the old stack arguments in a scratch
7593 register, which we here copy to a pseudo-register. The split
7594 stack prologue can't set the pseudo-register directly because
7595 it (the prologue) runs before any registers have been saved. */
7599 {
7613 }
7614 }
7616 /* Only 64bit target needs something special. */
7618 {
7621 else
7622 {
7631 }
7633 }
7642 /* The following should be folded into the MEM_REF offset. */
7652 /* Count number of gp and fp argument registers used. */
7658 {
7664 }
7667 {
7673 }
7675 /* Find the overflow area. */
7679 else
7689 {
7690 /* Find the register save area.
7691 Prologue of the function save it right above stack frame. */
7699 }
7700 }
7702 /* Implement va_arg. */
7704 static tree
7707 {
7714 rtx container;
7716 tree ptrtype;
7720 /* Only 64bit target needs something special. */
7744 {
7751 /* Unnamed 256bit vector mode parameters are passed on stack. */
7753 {
7756 }
7764 }
7766 /* Pull the value out of the saved registers. */
7771 {
7785 /* In case we are passing structure, verify that it is consecutive block
7786 on the register save area. If not we need to do moves. */
7788 {
7789 /* Verify that all registers are strictly consecutive */
7791 {
7795 {
7800 }
7801 }
7802 else
7803 {
7807 {
7812 }
7813 }
7814 }
7816 {
7819 }
7820 else
7821 {
7824 }
7826 /* First ensure that we fit completely in registers. */
7828 {
7835 }
7837 {
7845 }
7847 /* Compute index to start of area used for integer regs. */
7849 {
7850 /* int_addr = gpr + sav; */
7853 }
7855 {
7856 /* sse_addr = fpr + sav; */
7859 }
7861 {
7865 /* addr = &temp; */
7870 {
7874 tree piece_type;
7875 tree addr_type;
7876 tree daddr_type;
7885 {
7890 }
7894 else
7901 {
7904 }
7905 else
7906 {
7909 }
7916 {
7921 }
7922 else
7923 {
7924 tree copy
7929 }
7931 }
7932 }
7935 {
7939 }
7942 {
7946 }
7951 }
7953 /* ... otherwise out of the overflow area. */
7955 /* When we align parameter on stack for caller, if the parameter
7956 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7957 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7958 here with caller. */
7963 /* Care for on-stack alignment if needed. */
7966 else
7967 {
7972 }
7989 }
7990 \f
7991 /* Return true if OPNUM's MEM should be matched
7992 in movabs* patterns. */
7994 bool
7996 {
8008 }
8009 \f
8010 /* Initialize the table of extra 80387 mathematical constants. */
8012 static void
8014 {
8016 {
8022 };
8026 {
8028 /* Ensure each constant is rounded to XFmode precision. */
8031 }
8034 }
8036 /* Return non-zero if the constant is something that
8037 can be loaded with a special instruction. */
8039 int
8041 {
8044 REAL_VALUE_TYPE r;
8056 /* For XFmode constants, try to find a special 80387 instruction when
8057 optimizing for size or on those CPUs that benefit from them. */
8060 {
8069 }
8071 /* Load of the constant -0.0 or -1.0 will be split as
8072 fldz;fchs or fld1;fchs sequence. */
8079 }
8081 /* Return the opcode of the special instruction to be used to load
8082 the constant X. */
8086 {
8088 {
8108 }
8109 }
8111 /* Return the CONST_DOUBLE representing the 80387 constant that is
8112 loaded by the specified special instruction. The argument IDX
8113 matches the return value from standard_80387_constant_p. */
8115 rtx
8117 {
8124 {
8135 }
8138 XFmode);
8139 }
8141 /* Return 1 if X is all 0s and 2 if x is all 1s
8142 in supported SSE/AVX vector mode. */
8144 int
8146 {
8153 {
8168 }
8171 }
8173 /* Return the opcode of the special instruction to be used to load
8174 the constant X. */
8178 {
8180 {
8183 {
8200 }
8205 else
8210 }
8212 }
8214 /* Returns true if OP contains a symbol reference */
8216 bool
8218 {
8227 {
8229 {
8235 }
8239 }
8242 }
8244 /* Return true if it is appropriate to emit `ret' instructions in the
8245 body of a function. Do this only if the epilogue is simple, needing a
8246 couple of insns. Prior to reloading, we can't tell how many registers
8247 must be saved, so return false then. Return false if there is no frame
8248 marker to de-allocate. */
8250 bool
8252 {
8258 /* Don't allow more than 32k pop, since that's all we can do
8259 with one instruction. */
8266 }
8267 \f
8268 /* Value should be nonzero if functions must have frame pointers.
8269 Zero means the frame pointer need not be set up (and parms may
8270 be accessed via the stack pointer) in functions that seem suitable. */
8272 static bool
8274 {
8275 /* If we accessed previous frames, then the generated code expects
8276 to be able to access the saved ebp value in our frame. */
8280 /* Several x86 os'es need a frame pointer for other reasons,
8281 usually pertaining to setjmp. */
8285 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8289 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8290 allocation is 4GB. */
8294 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8295 turns off the frame pointer by default. Turn it back on now if
8296 we've not got a leaf function. */
8306 }
8308 /* Record that the current function accesses previous call frames. */
8310 void
8312 {
8314 }
8315 \f
8316 #ifndef USE_HIDDEN_LINKONCE
8317 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8318 # define USE_HIDDEN_LINKONCE 1
8319 # else
8320 # define USE_HIDDEN_LINKONCE 0
8321 # endif
8322 #endif
8326 /* Fills in the label name that should be used for a pc thunk for
8327 the given register. */
8329 static void
8331 {
8336 else
8338 }
8341 /* This function generates code for -fpic that loads %ebx with
8342 the return address of the caller and then returns. */
8344 static void
8346 {
8351 {
8353 tree decl;
8369 #if TARGET_MACHO
8371 {
8380 }
8381 else
8382 #endif
8384 {
8395 }
8396 else
8397 {
8400 }
8406 /* Make sure unwind info is emitted for the thunk if needed. */
8409 /* Pad stack IP move with 4 instructions (two NOPs count
8410 as one instruction). */
8412 {
8417 }
8428 }
8432 }
8434 /* Emit code for the SET_GOT patterns. */
8438 {
8444 {
8445 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8450 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8451 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8452 an unadorned address. */
8457 }
8462 {
8467 #if TARGET_MACHO
8468 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8469 is what will be referenced by the Mach-O PIC subsystem. */
8472 #endif
8476 }
8477 else
8478 {
8486 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8487 is what will be referenced by the Mach-O PIC subsystem. */
8488 #if TARGET_MACHO
8491 else
8494 #endif
8495 }
8501 }
8503 /* Generate an "push" pattern for input ARG. */
8505 static rtx
8507 {
8520 stack_pointer_rtx)),
8521 arg);
8522 }
8524 /* Generate an "pop" pattern for input ARG. */
8526 static rtx
8528 {
8533 arg,
8536 stack_pointer_rtx)));
8537 }
8539 /* Return >= 0 if there is an unused call-clobbered register available
8540 for the entire function. */
8542 static unsigned int
8544 {
8548 {
8550 /* Can't use the same register for both PIC and DRAP. */
8553 else
8558 }
8561 }
8563 /* Return TRUE if we need to save REGNO. */
8565 static bool
8567 {
8577 {
8580 {
8586 }
8587 }
8596 }
8598 /* Return number of saved general prupose registers. */
8600 static int
8602 {
8608 nregs ++;
8610 }
8612 /* Return number of saved SSE registrers. */
8614 static int
8616 {
8624 nregs ++;
8626 }
8628 /* Given FROM and TO register numbers, say whether this elimination is
8629 allowed. If stack alignment is needed, we can only replace argument
8630 pointer with hard frame pointer, or replace frame pointer with stack
8631 pointer. Otherwise, frame pointer elimination is automatically
8632 handled and all other eliminations are valid. */
8634 static bool
8636 {
8642 else
8644 }
8646 /* Return the offset between two registers, one to be eliminated, and the other
8647 its replacement, at the start of a routine. */
8649 HOST_WIDE_INT
8651 {
8660 else
8661 {
8669 }
8670 }
8672 /* In a dynamically-aligned function, we can't know the offset from
8673 stack pointer to frame pointer, so we must ensure that setjmp
8674 eliminates fp against the hard fp (%ebp) rather than trying to
8675 index from %esp up to the top of the frame across a gap that is
8676 of unknown (at compile-time) size. */
8677 static rtx
8679 {
8681 }
8683 /* When using -fsplit-stack, the allocation routines set a field in
8684 the TCB to the bottom of the stack plus this much space, measured
8685 in bytes. */
8687 #define SPLIT_STACK_AVAILABLE 256
8689 /* Fill structure ix86_frame about frame of currently computed function. */
8691 static void
8693 {
8695 HOST_WIDE_INT offset;
8698 HOST_WIDE_INT to_allocate;
8706 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8707 function prologues and leaf. */
8711 {
8716 }
8722 /* For SEH we have to limit the amount of code movement into the prologue.
8723 At present we do this via a BLOCKAGE, at which point there's very little
8724 scheduling that can be done, which means that there's very little point
8725 in doing anything except PUSHs. */
8729 /* During reload iteration the amount of registers saved can change.
8730 Recompute the value as needed. Do not recompute when amount of registers
8731 didn't change as reload does multiple calls to the function and does not
8732 expect the decision to change within single iteration. */
8735 {
8741 /* The fast prologue uses move instead of push to save registers. This
8742 is significantly longer, but also executes faster as modern hardware
8743 can execute the moves in parallel, but can't do that for push/pop.
8745 Be careful about choosing what prologue to emit: When function takes
8746 many instructions to execute we may use slow version as well as in
8747 case function is known to be outside hot spot (this is known with
8748 feedback only). Weight the size of function by number of registers
8749 to save as it is cheap to use one or two push instructions but very
8750 slow to use many of them. */
8754 || (flag_branch_probabilities
8757 else
8760 }
8762 frame->save_regs_using_mov
8764 /* If static stack checking is enabled and done with probes,
8765 the registers need to be saved before allocating the frame. */
8768 /* Skip return address. */
8771 /* Skip pushed static chain. */
8775 /* Skip saved base pointer. */
8780 /* The traditional frame pointer location is at the top of the frame. */
8783 /* Register save area */
8787 /* On SEH target, registers are pushed just before the frame pointer
8788 location. */
8792 /* Align and set SSE register save area. */
8794 {
8795 /* The only ABI that has saved SSE registers (Win64) also has a
8796 16-byte aligned default stack, and thus we don't need to be
8797 within the re-aligned local stack frame to save them. */
8801 }
8804 /* The re-aligned stack starts here. Values before this point are not
8805 directly comparable with values below this point. In order to make
8806 sure that no value happens to be the same before and after, force
8807 the alignment computation below to add a non-zero value. */
8811 /* Va-arg area */
8815 /* Align start of frame for local function. */
8824 /* Frame pointer points here. */
8829 /* Add outgoing arguments area. Can be skipped if we eliminated
8830 all the function calls as dead code.
8831 Skipping is however impossible when function calls alloca. Alloca
8832 expander assumes that last crtl->outgoing_args_size
8833 of stack frame are unused. */
8837 {
8840 }
8841 else
8844 /* Align stack boundary. Only needed if we're calling another function
8845 or using alloca. */
8850 /* We've reached end of stack frame. */
8853 /* Size prologue needs to allocate. */
8864 {
8870 }
8871 else
8875 /* The SEH frame pointer location is near the bottom of the frame.
8876 This is enforced by the fact that the difference between the
8877 stack pointer and the frame pointer is limited to 240 bytes in
8878 the unwind data structure. */
8880 {
8881 HOST_WIDE_INT diff;
8883 /* If we can leave the frame pointer where it is, do so. Also, returns
8884 the establisher frame for __builtin_frame_address (0). */
8889 {
8890 /* Ideally we'd determine what portion of the local stack frame
8891 (within the constraint of the lowest 240) is most heavily used.
8892 But without that complication, simply bias the frame pointer
8893 by 128 bytes so as to maximize the amount of the local stack
8894 frame that is addressable with 8-bit offsets. */
8896 }
8897 }
8898 }
8900 /* This is semi-inlined memory_address_length, but simplified
8901 since we know that we're always dealing with reg+offset, and
8902 to avoid having to create and discard all that rtl. */
8906 {
8910 {
8911 /* EBP and R13 cannot be encoded without an offset. */
8913 }
8917 /* ESP and R12 must be encoded with a SIB byte. */
8919 len++;
8922 }
8924 /* Return an RTX that points to CFA_OFFSET within the stack frame.
8925 The valid base registers are taken from CFUN->MACHINE->FS. */
8927 static rtx
8929 {
8935 {
8936 /* Choose the base register most likely to allow the most scheduling
8937 opportunities. Generally FP is valid throughout the function,
8938 while DRAP must be reloaded within the epilogue. But choose either
8939 over the SP due to increased encoding size. */
8942 {
8945 }
8947 {
8950 }
8952 {
8955 }
8956 }
8957 else
8958 {
8959 HOST_WIDE_INT toffset;
8962 /* Choose the base register with the smallest address encoding.
8963 With a tie, choose FP > DRAP > SP. */
8965 {
8969 }
8971 {
8975 {
8979 }
8980 }
8982 {
8986 {
8990 }
8991 }
8992 }
8996 }
8998 /* Emit code to save registers in the prologue. */
9000 static void
9002 {
9004 rtx insn;
9008 {
9011 }
9012 }
9014 /* Emit a single register save at CFA - CFA_OFFSET. */
9016 static void
9018 HOST_WIDE_INT cfa_offset)
9019 {
9027 /* For SSE saves, we need to indicate the 128-bit alignment. */
9038 /* When saving registers into a re-aligned local stack frame, avoid
9039 any tricky guessing by dwarf2out. */
9041 {
9045 {
9046 /* A bit of a hack. We force the DRAP register to be saved in
9047 the re-aligned stack frame, which provides us with a copy
9048 of the CFA that will last past the prologue. Install it. */
9054 }
9055 else
9056 {
9057 /* The frame pointer is a stable reference within the
9058 aligned frame. Use it. */
9065 }
9066 }
9068 /* The memory may not be relative to the current CFA register,
9069 which means that we may need to generate a new pattern for
9070 use by the unwind info. */
9072 {
9077 }
9078 }
9080 /* Emit code to save registers using MOV insns.
9081 First register is stored at CFA - CFA_OFFSET. */
9082 static void
9084 {
9089 {
9092 }
9093 }
9095 /* Emit code to save SSE registers using MOV insns.
9096 First register is stored at CFA - CFA_OFFSET. */
9097 static void
9099 {
9104 {
9107 }
9108 }
9112 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9113 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9114 Don't add the note if the previously saved value will be left untouched
9115 within stack red-zone till return, as unwinders can find the same value
9116 in the register and on the stack. */
9118 static void
9120 {
9126 {
9129 }
9130 else
9131 queued_cfa_restores
9133 }
9135 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9137 static void
9139 {
9140 rtx last;
9144 ;
9149 }
9151 /* Expand prologue or epilogue stack adjustment.
9152 The pattern exist to put a dependency on all ebp-based memory accesses.
9153 STYLE should be negative if instructions should be marked as frame related,
9154 zero if %r11 register is live and cannot be freely used and positive
9155 otherwise. */
9157 static void
9160 {
9162 rtx insn;
9169 else
9170 {
9171 rtx tmp;
9172 /* r11 is used by indirect sibcall return as well, set before the
9173 epilogue and used after the epilogue. */
9176 else
9177 {
9181 }
9187 }
9194 {
9195 rtx r;
9205 }
9207 {
9210 {
9214 }
9215 }
9218 {
9223 {
9226 }
9228 {
9231 }
9232 else
9233 {
9234 /* Else there are two possibilities: SP itself, which we set
9235 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9236 taken care of this by hand along the eh_return path. */
9239 }
9243 }
9244 }
9246 /* Find an available register to be used as dynamic realign argument
9247 pointer regsiter. Such a register will be written in prologue and
9248 used in begin of body, so it must not be
9249 1. parameter passing register.
9250 2. GOT pointer.
9251 We reuse static-chain register if it is available. Otherwise, we
9252 use DI for i386 and R13 for x86-64. We chose R13 since it has
9253 shorter encoding.
9255 Return: the regno of chosen register. */
9257 static unsigned int
9259 {
9263 {
9264 /* Use R13 for nested function or function need static chain.
9265 Since function with tail call may use any caller-saved
9266 registers in epilogue, DRAP must not use caller-saved
9267 register in such case. */
9272 }
9273 else
9274 {
9275 /* Use DI for nested function or function need static chain.
9276 Since function with tail call may use any caller-saved
9277 registers in epilogue, DRAP must not use caller-saved
9278 register in such case. */
9282 /* Reuse static chain register if it isn't used for parameter
9283 passing. */
9285 {
9289 }
9291 }
9292 }
9294 /* Return minimum incoming stack alignment. */
9296 static unsigned int
9298 {
9301 /* Prefer the one specified at command line. */
9304 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9305 if -mstackrealign is used, it isn't used for sibcall check and
9306 estimated stack alignment is 128bit. */
9308 && !TARGET_64BIT
9309 && ix86_force_align_arg_pointer
9312 else
9315 /* Incoming stack alignment can be changed on individual functions
9316 via force_align_arg_pointer attribute. We use the smallest
9317 incoming stack boundary. */
9323 /* The incoming stack frame has to be aligned at least at
9324 parm_stack_boundary. */
9328 /* Stack at entrance of main is aligned by runtime. We use the
9329 smallest incoming stack boundary. */
9337 }
9339 /* Update incoming stack boundary and estimated stack alignment. */
9341 static void
9343 {
9344 ix86_incoming_stack_boundary
9347 /* x86_64 vararg needs 16byte stack alignment for register save
9348 area. */
9353 }
9355 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9356 needed or an rtx for DRAP otherwise. */
9358 static rtx
9360 {
9365 {
9366 /* Assign DRAP to vDRAP and returns vDRAP */
9368 rtx drap_vreg;
9369 rtx arg_ptr;
9382 {
9385 }
9387 }
9388 else
9390 }
9392 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9394 static rtx
9396 {
9398 }
9401 rtx reg;
9403 };
9405 /* Return a short-lived scratch register for use on function entry.
9406 In 32-bit mode, it is valid only after the registers are saved
9407 in the prologue. This register must be released by means of
9408 release_scratch_register_on_entry once it is dead. */
9410 static void
9412 {
9418 {
9419 /* We always use R11 in 64-bit mode. */
9421 }
9422 else
9423 {
9425 bool fastcall_p
9429 int drap_regno
9432 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9433 for the static chain register. */
9439 /* ecx is the static chain register. */
9445 /* esi is the static chain register. */
9451 else
9452 {
9455 }
9456 }
9460 {
9463 }
9464 }
9466 /* Release a scratch register obtained from the preceding function. */
9468 static void
9470 {
9472 {
9476 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9482 }
9483 }
9485 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9487 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9489 static void
9491 {
9492 /* We skip the probe for the first interval + a small dope of 4 words and
9493 probe that many bytes past the specified size to maintain a protection
9494 area at the botton of the stack. */
9498 /* See if we have a constant small number of probes to generate. If so,
9499 that's the easy case. The run-time loop is made up of 11 insns in the
9500 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9501 for n # of intervals. */
9503 {
9507 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9508 values of N from 1 until it exceeds SIZE. If only one probe is
9509 needed, this will not generate any code. Then adjust and probe
9510 to PROBE_INTERVAL + SIZE. */
9512 {
9514 {
9517 }
9518 else
9525 }
9529 else
9537 /* Adjust back to account for the additional first interval. */
9541 }
9543 /* Otherwise, do the same as above, but in a loop. Note that we must be
9544 extra careful with variables wrapping around because we might be at
9545 the very top (or the very bottom) of the address space and we have
9546 to be able to handle this case properly; in particular, we use an
9547 equality test for the loop condition. */
9548 else
9549 {
9550 HOST_WIDE_INT rounded_size;
9556 /* Step 1: round SIZE to the previous multiple of the interval. */
9561 /* Step 2: compute initial and final value of the loop counter. */
9563 /* SP = SP_0 + PROBE_INTERVAL. */
9568 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9572 stack_pointer_rtx)));
9575 /* Step 3: the loop
9577 while (SP != LAST_ADDR)
9578 {
9579 SP = SP + PROBE_INTERVAL
9580 probe at SP
9581 }
9583 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9584 values of N from 1 until it is equal to ROUNDED_SIZE. */
9589 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9590 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9593 {
9598 }
9600 /* Adjust back to account for the additional first interval. */
9606 }
9610 /* Even if the stack pointer isn't the CFA register, we need to correctly
9611 describe the adjustments made to it, in particular differentiate the
9612 frame-related ones from the frame-unrelated ones. */
9614 {
9627 }
9629 /* Make sure nothing is scheduled before we are done. */
9631 }
9633 /* Adjust the stack pointer up to REG while probing it. */
9637 {
9647 /* Jump to END_LAB if SP == LAST_ADDR. */
9655 /* SP = SP + PROBE_INTERVAL. */
9659 /* Probe at SP. */
9670 }
9672 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9673 inclusive. These are offsets from the current stack pointer. */
9675 static void
9677 {
9678 /* See if we have a constant small number of probes to generate. If so,
9679 that's the easy case. The run-time loop is made up of 7 insns in the
9680 generic case while the compile-time loop is made up of n insns for n #
9681 of intervals. */
9683 {
9684 HOST_WIDE_INT i;
9686 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9687 it exceeds SIZE. If only one probe is needed, this will not
9688 generate any code. Then probe at FIRST + SIZE. */
9695 }
9697 /* Otherwise, do the same as above, but in a loop. Note that we must be
9698 extra careful with variables wrapping around because we might be at
9699 the very top (or the very bottom) of the address space and we have
9700 to be able to handle this case properly; in particular, we use an
9701 equality test for the loop condition. */
9702 else
9703 {
9710 /* Step 1: round SIZE to the previous multiple of the interval. */
9715 /* Step 2: compute initial and final value of the loop counter. */
9717 /* TEST_OFFSET = FIRST. */
9720 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9724 /* Step 3: the loop
9726 while (TEST_ADDR != LAST_ADDR)
9727 {
9728 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9729 probe at TEST_ADDR
9730 }
9732 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
9733 until it is equal to ROUNDED_SIZE. */
9738 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
9739 that SIZE is equal to ROUNDED_SIZE. */
9744 stack_pointer_rtx,
9749 }
9751 /* Make sure nothing is scheduled before we are done. */
9753 }
9755 /* Probe a range of stack addresses from REG to END, inclusive. These are
9756 offsets from the current stack pointer. */
9760 {
9770 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
9778 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
9782 /* Probe at TEST_ADDR. */
9795 }
9797 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
9798 to be generated in correct form. */
9799 static void
9801 {
9802 /* Check if stack realign is really needed after reload, and
9803 stores result in cfun */
9804 unsigned int incoming_stack_boundary
9813 {
9814 /* After stack_realign_needed is finalized, we can't no longer
9815 change it. */
9818 }
9820 /* If the only reason for frame_pointer_needed is that we conservatively
9821 assumed stack realignment might be needed, but in the end nothing that
9822 needed the stack alignment had been spilled, clear frame_pointer_needed
9823 and say we don't need stack realignment. */
9826 && frame_pointer_needed
9828 && flag_omit_frame_pointer
9830 && !ix86_current_function_calls_tls_descriptor
9839 {
9841 basic_block bb;
9848 HARD_FRAME_POINTER_REGNUM);
9850 {
9851 rtx insn;
9855 set_up_by_prologue))
9856 {
9860 }
9861 }
9875 }
9879 }
9881 /* Expand the prologue into a bunch of separate insns. */
9883 void
9885 {
9890 HOST_WIDE_INT allocate;
9896 /* DRAP should not coexist with stack_realign_fp */
9901 /* Initialize CFA state for before the prologue. */
9905 /* Track SP offset to the CFA. We continue tracking this after we've
9906 swapped the CFA register away from SP. In the case of re-alignment
9907 this is fudged; we're interested to offsets within the local frame. */
9914 {
9915 /* We should have already generated an error for any use of
9916 ms_hook on a nested function. */
9919 /* Check if profiling is active and we shall use profiling before
9920 prologue variant. If so sorry. */
9925 /* In ix86_asm_output_function_label we emitted:
9926 8b ff movl.s %edi,%edi
9927 55 push %ebp
9928 8b ec movl.s %esp,%ebp
9930 This matches the hookable function prologue in Win32 API
9931 functions in Microsoft Windows XP Service Pack 2 and newer.
9932 Wine uses this to enable Windows apps to hook the Win32 API
9933 functions provided by Wine.
9935 What that means is that we've already set up the frame pointer. */
9939 {
9942 /* We've decided to use the frame pointer already set up.
9943 Describe this to the unwinder by pretending that both
9944 push and mov insns happen right here.
9946 Putting the unwind info here at the end of the ms_hook
9947 is done so that we can make absolutely certain we get
9948 the required byte sequence at the start of the function,
9949 rather than relying on an assembler that can produce
9950 the exact encoding required.
9952 However it does mean (in the unpatched case) that we have
9953 a 1 insn window where the asynchronous unwind info is
9954 incorrect. However, if we placed the unwind info at
9955 its correct location we would have incorrect unwind info
9956 in the patched case. Which is probably all moot since
9957 I don't expect Wine generates dwarf2 unwind info for the
9958 system libraries that use this feature. */
9964 stack_pointer_rtx);
9972 /* Note that gen_push incremented m->fs.cfa_offset, even
9973 though we didn't emit the push insn here. */
9977 }
9978 else
9979 {
9980 /* The frame pointer is not needed so pop %ebp again.
9981 This leaves us with a pristine state. */
9983 }
9984 }
9986 /* The first insn of a function that accepts its static chain on the
9987 stack is to push the register that would be filled in by a direct
9988 call. This insn will be skipped by the trampoline. */
9990 {
9994 /* We don't want to interpret this push insn as a register save,
9995 only as a stack adjustment. The real copy of the register as
9996 a save will be done later, if needed. */
10001 }
10003 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10004 of DRAP is needed and stack realignment is really needed after reload */
10006 {
10009 /* Only need to push parameter pointer reg if it is caller saved. */
10011 {
10012 /* Push arg pointer reg */
10015 }
10017 /* Grab the argument pointer. */
10024 /* Align the stack. */
10026 stack_pointer_rtx,
10030 /* Replicate the return address on the stack so that return
10031 address can be reached via (argp - 1) slot. This is needed
10032 to implement macro RETURN_ADDR_RTX and intrinsic function
10033 expand_builtin_return_addr etc. */
10039 /* For the purposes of frame and register save area addressing,
10040 we've started over with a new frame. */
10043 }
10049 {
10050 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10051 slower on all targets. Also sdb doesn't like it. */
10055 /* Push registers now, before setting the frame pointer
10056 on SEH target. */
10058 && TARGET_SEH
10060 {
10064 }
10067 {
10075 }
10076 }
10079 {
10080 /* If saving registers via PUSH, do so now. */
10082 {
10086 }
10088 /* When using red zone we may start register saving before allocating
10089 the stack frame saving one cycle of the prologue. However, avoid
10090 doing this if we have to probe the stack; at least on x86_64 the
10091 stack probe can turn into a call that clobbers a red zone location. */
10093 && (! TARGET_STACK_PROBE
10095 {
10098 }
10099 }
10102 {
10106 /* The computation of the size of the re-aligned stack frame means
10107 that we must allocate the size of the register save area before
10108 performing the actual alignment. Otherwise we cannot guarantee
10109 that there's enough storage above the realignment point. */
10116 /* Align the stack. */
10118 stack_pointer_rtx,
10121 /* For the purposes of register save area addressing, the stack
10122 pointer is no longer valid. As for the value of sp_offset,
10123 see ix86_compute_frame_layout, which we need to match in order
10124 to pass verification of stack_pointer_offset at the end. */
10127 }
10132 {
10133 /* We start to count from ARG_POINTER. */
10136 /* If it was realigned, take into account the fake frame. */
10138 {
10145 /* This over-estimates by 1 minimal-stack-alignment-unit but
10146 mitigates that by counting in the new return address slot. */
10147 current_function_dynamic_stack_size
10149 }
10152 }
10154 /* On SEH target with very large frame size, allocate an area to save
10155 SSE registers (as the very large allocation won't be described). */
10159 {
10160 HOST_WIDE_INT sse_size =
10165 /* No need to do stack checking as the area will be immediately
10166 written. */
10173 }
10175 /* The stack has already been decremented by the instruction calling us
10176 so probe if the size is non-negative to preserve the protection area. */
10178 {
10179 /* We expect the registers to be saved when probes are used. */
10183 {
10186 }
10187 else
10188 {
10196 else
10198 }
10199 }
10202 ;
10205 {
10209 }
10210 else
10211 {
10224 /* Note that SEH directives need to continue tracking the stack
10225 pointer even after the frame pointer has been set up. */
10227 {
10231 {
10235 }
10236 }
10239 {
10244 {
10248 }
10249 }
10254 /* Use the fact that AX still contains ALLOCATE. */
10256 ? gen_pro_epilogue_adjust_stack_di_sub
10263 {
10271 }
10275 {
10282 }
10284 {
10289 }
10290 }
10293 /* If we havn't already set up the frame pointer, do so now. */
10295 {
10307 }
10318 {
10325 }
10328 {
10330 {
10332 {
10342 label));
10346 }
10347 else
10349 }
10350 else
10351 {
10355 }
10356 }
10358 /* In the pic_reg_used case, make sure that the got load isn't deleted
10359 when mcount needs it. Blockage to avoid call movement across mcount
10360 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10361 note. */
10366 {
10367 /* vDRAP is setup but after reload it turns out stack realign
10368 isn't necessary, here we will emit prologue to setup DRAP
10369 without stack realign adjustment */
10372 }
10374 /* Prevent instructions from being scheduled into register save push
10375 sequence when access to the redzone area is done through frame pointer.
10376 The offset between the frame pointer and the stack pointer is calculated
10377 relative to the value of the stack pointer at the end of the function
10378 prologue, and moving instructions that access redzone area via frame
10379 pointer inside push sequence violates this assumption. */
10383 /* Emit cld instruction if stringops are used in the function. */
10387 /* SEH requires that the prologue end within 256 bytes of the start of
10388 the function. Prevent instruction schedules that would extend that.
10389 Further, prevent alloca modifications to the stack pointer from being
10390 combined with prologue modifications. */
10393 }
10395 /* Emit code to restore REG using a POP insn. */
10397 static void
10399 {
10408 {
10409 /* Previously we'd represented the CFA as an expression
10410 like *(%ebp - 8). We've just popped that value from
10411 the stack, which means we need to reset the CFA to
10412 the drap register. This will remain until we restore
10413 the stack pointer. */
10417 /* This means that the DRAP register is valid for addressing too. */
10420 }
10423 {
10430 }
10432 /* When the frame pointer is the CFA, and we pop it, we are
10433 swapping back to the stack pointer as the CFA. This happens
10434 for stack frames that don't allocate other data, so we assume
10435 the stack pointer is now pointing at the return address, i.e.
10436 the function entry state, which makes the offset be 1 word. */
10438 {
10441 {
10449 }
10450 }
10451 }
10453 /* Emit code to restore saved registers using POP insns. */
10455 static void
10457 {
10463 }
10465 /* Emit code and notes for the LEAVE instruction. */
10467 static void
10469 {
10481 {
10489 }
10492 }
10494 /* Emit code to restore saved registers using MOV insns.
10495 First register is restored from CFA - CFA_OFFSET. */
10496 static void
10499 {
10505 {
10514 {
10515 /* Previously we'd represented the CFA as an expression
10516 like *(%ebp - 8). We've just popped that value from
10517 the stack, which means we need to reset the CFA to
10518 the drap register. This will remain until we restore
10519 the stack pointer. */
10523 /* This means that the DRAP register is valid for addressing. */
10525 }
10526 else
10530 }
10531 }
10533 /* Emit code to restore saved registers using MOV insns.
10534 First register is restored from CFA - CFA_OFFSET. */
10535 static void
10538 {
10543 {
10545 rtx mem;
10555 }
10556 }
10558 /* Restore function stack, frame, and registers. */
10560 void
10562 {
10578 /* The FP must be valid if the frame pointer is present. */
10583 /* We must have *some* valid pointer to the stack frame. */
10586 /* The DRAP is never valid at this point. */
10589 /* See the comment about red zone and frame
10590 pointer usage in ix86_expand_prologue. */
10597 /* Determine the CFA offset of the end of the red-zone. */
10600 {
10601 /* The red-zone begins below the return address. */
10604 /* When the register save area is in the aligned portion of
10605 the stack, determine the maximum runtime displacement that
10606 matches up with the aligned frame. */
10610 }
10612 /* Special care must be taken for the normal return case of a function
10613 using eh_return: the eax and edx registers are marked as saved, but
10614 not restored along this path. Adjust the save location to match. */
10618 /* EH_RETURN requires the use of moves to function properly. */
10621 /* SEH requires the use of pops to identify the epilogue. */
10624 /* If we're only restoring one register and sp is not valid then
10625 using a move instruction to restore the register since it's
10626 less work than reloading sp and popping the register. */
10639 && TARGET_USE_LEAVE
10643 else
10647 {
10648 /* Ensure that the entire register save area is addressable via
10649 the stack pointer, if we will restore via sp. */
10654 {
10658 style,
10660 }
10661 }
10663 /* If there are any SSE registers to restore, then we have to do it
10664 via moves, since there's obviously no pop for SSE regs. */
10670 {
10671 rtx t;
10676 /* eh_return epilogues need %ecx added to the stack pointer. */
10678 {
10681 /* Stack align doesn't work with eh_return. */
10683 /* Neither does regparm nested functions. */
10687 {
10695 /* Note that we use SA as a temporary CFA, as the return
10696 address is at the proper place relative to it. We
10697 pretend this happens at the FP restore insn because
10698 prior to this insn the FP would be stored at the wrong
10699 offset relative to SA, and after this insn we have no
10700 other reasonable register to use for the CFA. We don't
10701 bother resetting the CFA to the SP for the duration of
10702 the return insn. */
10715 }
10716 else
10717 {
10725 {
10729 UNITS_PER_WORD));
10731 }
10732 }
10735 }
10736 }
10737 else
10738 {
10739 /* SEH requires that the function end with (1) a stack adjustment
10740 if necessary, (2) a sequence of pops, and (3) a return or
10741 jump instruction. Prevent insns from the function body from
10742 being scheduled into this sequence. */
10744 {
10745 /* Prevent a catch region from being adjacent to the standard
10746 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
10747 several other flags that would be interesting to test are
10748 not yet set up. */
10751 else
10753 }
10755 /* First step is to deallocate the stack frame so that we can
10756 pop the registers. Also do it on SEH target for very large
10757 frame as the emitted instructions aren't allowed by the ABI in
10758 epilogues. */
10760 || (TARGET_SEH
10763 {
10768 }
10770 {
10774 style,
10776 }
10779 }
10781 /* If we used a stack pointer and haven't already got rid of it,
10782 then do so now. */
10784 {
10785 /* If the stack pointer is valid and pointing at the frame
10786 pointer store address, then we only need a pop. */
10789 /* Leave results in shorter dependency chains on CPUs that are
10790 able to grok it fast. */
10795 else
10796 {
10798 hard_frame_pointer_rtx,
10801 }
10802 }
10805 {
10807 rtx insn;
10833 }
10835 /* At this point the stack pointer must be valid, and we must have
10836 restored all of the registers. We may not have deallocated the
10837 entire stack frame. We've delayed this until now because it may
10838 be possible to merge the local stack deallocation with the
10839 deallocation forced by ix86_static_chain_on_stack. */
10844 {
10848 }
10849 else
10852 /* Sibcall epilogues don't want a return instruction. */
10854 {
10857 }
10860 {
10863 /* i386 can only pop 64K bytes. If asked to pop more, pop return
10864 address, do explicit add, and jump indirectly to the caller. */
10867 {
10869 rtx insn;
10871 /* There is no "pascal" calling convention in any 64bit ABI. */
10887 }
10888 else
10890 }
10891 else
10894 /* Restore the state back to the state from the prologue,
10895 so that it's correct for the next epilogue. */
10897 }
10899 /* Reset from the function's potential modifications. */
10901 static void
10903 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10904 {
10907 #if TARGET_MACHO
10908 /* Mach-O doesn't support labels at the end of objects, so if
10909 it looks like we might want one, insert a NOP. */
10910 {
10916 {
10917 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
10918 notes only, instead set their CODE_LABEL_NUMBER to -1,
10919 otherwise there would be code generation differences
10920 in between -g and -g0. */
10924 }
10934 }
10935 #endif
10937 }
10939 /* Return a scratch register to use in the split stack prologue. The
10940 split stack prologue is used for -fsplit-stack. It is the first
10941 instructions in the function, even before the regular prologue.
10942 The scratch register can be any caller-saved register which is not
10943 used for parameters or for the static chain. */
10945 static unsigned int
10947 {
10950 else
10951 {
10961 {
10963 {
10967 }
10969 }
10971 {
10974 else
10975 {
10977 {
10981 }
10983 }
10984 }
10985 else
10986 {
10987 /* FIXME: We could make this work by pushing a register
10988 around the addition and comparison. */
10991 }
10992 }
10993 }
10995 /* A SYMBOL_REF for the function which allocates new stackspace for
10996 -fsplit-stack. */
11000 /* A SYMBOL_REF for the more stack function when using the large
11001 model. */
11005 /* Handle -fsplit-stack. These are the first instructions in the
11006 function, even before the regular prologue. */
11008 void
11010 {
11012 HOST_WIDE_INT allocate;
11017 rtx fn;
11025 /* This is the label we will branch to if we have enough stack
11026 space. We expect the basic block reordering pass to reverse this
11027 branch if optimizing, so that we branch in the unlikely case. */
11030 /* We need to compare the stack pointer minus the frame size with
11031 the stack boundary in the TCB. The stack boundary always gives
11032 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11033 can compare directly. Otherwise we need to do an addition. */
11036 UNSPEC_STACK_CHECK);
11041 else
11042 {
11044 rtx offset;
11046 /* We need a scratch register to hold the stack pointer minus
11047 the required frame size. Since this is the very start of the
11048 function, the scratch register can be any caller-saved
11049 register which is not used for parameters. */
11056 {
11057 /* We don't use ix86_gen_add3 in this case because it will
11058 want to split to lea, but when not optimizing the insn
11059 will not be split after this point. */
11062 offset)));
11063 }
11064 else
11065 {
11068 stack_pointer_rtx));
11069 }
11071 }
11077 /* Mark the jump as very likely to be taken. */
11085 /* Get more stack space. We pass in the desired stack space and the
11086 size of the arguments to copy to the new stack. In 32-bit mode
11087 we push the parameters; __morestack will return on a new stack
11088 anyhow. In 64-bit mode we pass the parameters in r10 and
11089 r11. */
11094 {
11100 /* If this function uses a static chain, it will be in %r10.
11101 Preserve it across the call to __morestack. */
11103 {
11104 rtx rax;
11109 }
11112 {
11113 HOST_WIDE_INT argval;
11116 /* When using the large model we need to load the address
11117 into a register, and we've run out of registers. So we
11118 switch to a different calling convention, and we call a
11119 different function: __morestack_large. We pass the
11120 argument size in the upper 32 bits of r10 and pass the
11121 frame size in the lower 32 bits. */
11126 split_stack_fn_large =
11130 {
11140 UNSPEC_GOT);
11146 }
11147 else
11154 }
11155 else
11156 {
11160 }
11163 }
11164 else
11165 {
11168 }
11174 /* In order to make call/return prediction work right, we now need
11175 to execute a return instruction. See
11176 libgcc/config/i386/morestack.S for the details on how this works.
11178 For flow purposes gcc must not see this as a return
11179 instruction--we need control flow to continue at the subsequent
11180 label. Therefore, we use an unspec. */
11184 /* If we are in 64-bit mode and this function uses a static chain,
11185 we saved %r10 in %rax before calling _morestack. */
11190 /* If this function calls va_start, we need to store a pointer to
11191 the arguments on the old stack, because they may not have been
11192 all copied to the new stack. At this point the old stack can be
11193 found at the frame pointer value used by __morestack, because
11194 __morestack has set that up before calling back to us. Here we
11195 store that pointer in a scratch register, and in
11196 ix86_expand_prologue we store the scratch register in a stack
11197 slot. */
11199 {
11201 rtx frame_reg;
11208 /* 64-bit:
11209 fp -> old fp value
11210 return address within this function
11211 return address of caller of this function
11212 stack arguments
11213 So we add three words to get to the stack arguments.
11215 32-bit:
11216 fp -> old fp value
11217 return address within this function
11218 first argument to __morestack
11219 second argument to __morestack
11220 return address of caller of this function
11221 stack arguments
11222 So we add five words to get to the stack arguments.
11223 */
11234 }
11239 /* If this function calls va_start, we now have to set the scratch
11240 register for the case where we do not call __morestack. In this
11241 case we need to set it based on the stack pointer. */
11243 {
11250 }
11251 }
11253 /* We may have to tell the dataflow pass that the split stack prologue
11254 is initializing a scratch register. */
11256 static void
11258 {
11260 {
11263 }
11264 }
11265 \f
11266 /* Determine if op is suitable SUBREG RTX for address. */
11268 static bool
11270 {
11281 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11282 failures when the register is one word out of a two word structure. */
11286 /* Allow only SUBREGs of non-eliminable hard registers. */
11288 }
11290 /* Extract the parts of an RTL expression that is a valid memory address
11291 for an instruction. Return 0 if the structure of the address is
11292 grossly off. Return -1 if the address contains ASHIFT, so it is not
11293 strictly valid, but still used for computing length of lea instruction. */
11295 int
11297 {
11302 rtx tmp;
11306 /* Allow zero-extended SImode addresses,
11307 they will be emitted with addr32 prefix. */
11309 {
11312 {
11316 }
11319 {
11326 }
11327 }
11329 /* Allow SImode subregs of DImode addresses,
11330 they will be emitted with addr32 prefix. */
11332 {
11335 {
11339 }
11340 }
11345 {
11348 else
11350 }
11352 {
11357 do
11358 {
11363 }
11370 {
11373 {
11398 /* FALLTHRU */
11402 && TARGET_TLS_DIRECT_SEG_REFS
11405 else
11412 /* FALLTHRU */
11419 else
11434 }
11435 }
11436 }
11438 {
11441 }
11443 {
11444 /* We're called for lea too, which implements ashift on occasion. */
11454 }
11456 {
11460 /* Constant addresses are sign extended to 64bit, we have to
11461 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11467 }
11468 else
11472 {
11474 ;
11477 ;
11478 else
11480 }
11482 /* Address override works only on the (%reg) part of %fs:(%reg). */
11488 /* Extract the integral value of scale. */
11490 {
11494 }
11499 /* Avoid useless 0 displacement. */
11503 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11508 {
11509 rtx tmp;
11512 }
11514 /* Special case: %ebp cannot be encoded as a base without a displacement.
11515 Similarly %r13. */
11517 && base_reg
11526 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11527 Avoid this by transforming to [%esi+0].
11528 Reload calls address legitimization without cfun defined, so we need
11529 to test cfun for being non-NULL. */
11535 /* Special case: encode reg+reg instead of reg*2. */
11539 /* Special case: scaling cannot be encoded without base or displacement. */
11550 }
11551 \f
11552 /* Return cost of the memory address x.
11553 For i386, it is better to use a complex address than let gcc copy
11554 the address into a reg and make a new pseudo. But not if the address
11555 requires to two regs - that would mean more pseudos with longer
11556 lifetimes. */
11557 static int
11559 addr_space_t as ATTRIBUTE_UNUSED,
11561 {
11573 /* Attempt to minimize number of registers in the address. */
11579 cost++;
11586 cost++;
11588 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11589 since it's predecode logic can't detect the length of instructions
11590 and it degenerates to vector decoded. Increase cost of such
11591 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11592 to split such addresses or even refuse such addresses at all.
11594 Following addressing modes are affected:
11595 [base+scale*index]
11596 [scale*index+disp]
11597 [base+index]
11599 The first and last case may be avoidable by explicitly coding the zero in
11600 memory address, but I don't have AMD-K6 machine handy to check this
11601 theory. */
11610 }
11611 \f
11612 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11613 this is used for to form addresses to local data when -fPIC is in
11614 use. */
11616 static bool
11618 {
11621 }
11623 /* Determine if a given RTX is a valid constant. We already know this
11624 satisfies CONSTANT_P. */
11626 static bool
11628 {
11630 {
11635 {
11639 }
11644 /* Only some unspecs are valid as "constants". */
11647 {
11663 }
11665 /* We must have drilled down to a symbol. */
11670 /* FALLTHRU */
11673 /* TLS symbols are never valid. */
11677 /* DLLIMPORT symbols are never valid. */
11682 #if TARGET_MACHO
11683 /* mdynamic-no-pic */
11686 #endif
11702 }
11704 /* Otherwise we handle everything else in the move patterns. */
11706 }
11708 /* Determine if it's legal to put X into the constant pool. This
11709 is not possible for the address of thread-local symbols, which
11710 is checked above. */
11712 static bool
11714 {
11715 /* We can always put integral constants and vectors in memory. */
11717 {
11725 }
11727 }
11730 /* Nonzero if the constant value X is a legitimate general operand
11731 when generating PIC code. It is given that flag_pic is on and
11732 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11734 bool
11736 {
11737 rtx inner;
11740 {
11747 /* Only some unspecs are valid as "constants". */
11750 {
11763 }
11764 /* FALLTHRU */
11772 }
11773 }
11775 /* Determine if a given CONST RTX is a valid memory displacement
11776 in PIC mode. */
11778 bool
11780 {
11783 /* In 64bit mode we can allow direct addresses of symbols and labels
11784 when they are not dynamic symbols. */
11786 {
11790 {
11814 /* FALLTHRU */
11817 /* TLS references should always be enclosed in UNSPEC. */
11827 }
11828 }
11834 {
11835 /* We are unsafe to allow PLUS expressions. This limit allowed distance
11836 of GOT tables. We should not need these anyway. */
11848 }
11852 {
11857 }
11866 {
11870 /* We need to check for both symbols and labels because VxWorks loads
11871 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
11872 details. */
11876 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
11877 While ABI specify also 32bit relocation but we don't produce it in
11878 small PIC model at all. */
11900 }
11903 }
11905 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
11906 replace the input X, or the original X if no replacement is called for.
11907 The output parameter *WIN is 1 if the calling macro should goto WIN,
11908 0 if it should not. */
11910 bool
11915 {
11916 /* Reload can generate:
11918 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
11919 (reg:DI 97))
11920 (reg:DI 2 cx))
11922 This RTX is rejected from ix86_legitimate_address_p due to
11923 non-strictness of base register 97. Following this rejection,
11924 reload pushes all three components into separate registers,
11925 creating invalid memory address RTX.
11927 Following code reloads only the invalid part of the
11928 memory address RTX. */
11934 {
11940 {
11945 }
11949 {
11954 }
11958 }
11961 }
11963 /* Recognizes RTL expressions that are valid memory addresses for an
11964 instruction. The MODE argument is the machine mode for the MEM
11965 expression that wants to use this address.
11967 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
11968 convert common non-canonical forms to canonical form so that they will
11969 be recognized. */
11971 static bool
11974 {
11977 HOST_WIDE_INT scale;
11980 /* Decomposition failed. */
11988 /* Validate base register. */
11990 {
11991 rtx reg;
11997 else
11998 /* Base is not a register. */
12006 /* Base is not valid. */
12008 }
12010 /* Validate index register. */
12012 {
12013 rtx reg;
12019 else
12020 /* Index is not a register. */
12028 /* Index is not valid. */
12030 }
12032 /* Index and base should have the same mode. */
12037 /* Validate scale factor. */
12039 {
12041 /* Scale without index. */
12045 /* Scale is not a valid multiplier. */
12047 }
12049 /* Validate displacement. */
12051 {
12056 {
12057 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12058 used. While ABI specify also 32bit relocations, we don't produce
12059 them at all and use IP relative instead. */
12066 /* 64bit address unspec. */
12086 /* Invalid address unspec. */
12088 }
12091 && (flag_pic
12092 || (TARGET_MACHO
12093 #if TARGET_MACHO
12094 && MACHOPIC_INDIRECT
12096 #endif
12097 )))
12098 {
12100 is_legitimate_pic:
12102 {
12103 /* foo@dtpoff(%rX) is ok. */
12110 /* Non-constant pic memory reference. */
12112 }
12115 /* Displacement is an invalid pic construct. */
12117 #if TARGET_MACHO
12120 /* displacment must be referenced via non_lazy_pointer */
12122 #endif
12124 /* This code used to verify that a symbolic pic displacement
12125 includes the pic_offset_table_rtx register.
12127 While this is good idea, unfortunately these constructs may
12128 be created by "adds using lea" optimization for incorrect
12129 code like:
12131 int a;
12132 int foo(int i)
12133 {
12134 return *(&a+i);
12135 }
12137 This code is nonsensical, but results in addressing
12138 GOT table with pic_offset_table_rtx base. We can't
12139 just refuse it easily, since it gets matched by
12140 "addsi3" pattern, that later gets split to lea in the
12141 case output register differs from input. While this
12142 can be handled by separate addsi pattern for this case
12143 that never results in lea, this seems to be easier and
12144 correct fix for crash to disable this test. */
12145 }
12152 /* Displacement is not constant. */
12156 /* Displacement is out of range. */
12158 }
12160 /* Everything looks valid. */
12162 }
12164 /* Determine if a given RTX is a valid constant address. */
12166 bool
12168 {
12170 }
12171 \f
12172 /* Return a unique alias set for the GOT. */
12174 static alias_set_type
12176 {
12181 }
12183 /* Return a legitimate reference for ORIG (an address) using the
12184 register REG. If REG is 0, a new pseudo is generated.
12186 There are two types of references that must be handled:
12188 1. Global data references must load the address from the GOT, via
12189 the PIC reg. An insn is emitted to do this load, and the reg is
12190 returned.
12192 2. Static data references, constant pool addresses, and code labels
12193 compute the address as an offset from the GOT, whose base is in
12194 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12195 differentiate them from global data objects. The returned
12196 address is the PIC reg + an unspec constant.
12198 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12199 reg also appears in the address. */
12201 static rtx
12203 {
12206 rtx base;
12208 #if TARGET_MACHO
12210 {
12213 /* Use the generic Mach-O PIC machinery. */
12215 }
12216 #endif
12223 {
12224 rtx tmpreg;
12225 /* This symbol may be referenced via a displacement from the PIC
12226 base address (@GOTOFF). */
12233 {
12235 UNSPEC_GOTOFF);
12237 }
12238 else
12243 else
12248 {
12252 }
12254 }
12256 {
12257 /* This symbol may be referenced via a displacement from the PIC
12258 base address (@GOTOFF). */
12265 {
12267 UNSPEC_GOTOFF);
12269 }
12270 else
12276 {
12279 }
12280 }
12282 /* We can't use @GOTOFF for text labels on VxWorks;
12283 see gotoff_operand. */
12285 {
12287 {
12293 {
12296 }
12297 }
12299 /* For x64 PE-COFF there is no GOT table. So we use address
12300 directly. */
12302 {
12310 }
12312 {
12320 /* Use directly gen_movsi, otherwise the address is loaded
12321 into register for CSE. We don't want to CSE this addresses,
12322 instead we CSE addresses from the GOT table, so skip this. */
12325 }
12326 else
12327 {
12328 /* This symbol must be referenced via a load from the
12329 Global Offset Table (@GOT). */
12345 }
12346 }
12347 else
12348 {
12351 {
12353 {
12356 }
12357 else
12359 }
12361 {
12364 /* We must match stuff we generate before. Assume the only
12365 unspecs that can get here are ours. Not that we could do
12366 anything with them anyway.... */
12372 }
12374 {
12377 /* Check first to see if this is a constant offset from a @GOTOFF
12378 symbol reference. */
12381 {
12383 {
12387 UNSPEC_GOTOFF);
12393 {
12396 }
12397 }
12398 else
12399 {
12402 {
12406 }
12407 }
12408 }
12409 else
12410 {
12417 else
12418 {
12420 {
12423 }
12425 }
12426 }
12427 }
12428 }
12430 }
12431 \f
12432 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12434 static rtx
12436 {
12440 {
12445 }
12451 }
12453 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12457 static rtx
12459 {
12461 {
12467 }
12470 }
12472 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12476 rtx
12478 {
12480 {
12481 ix86_tls_module_base_symbol
12486 }
12489 }
12491 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12492 false if we expect this to be used for a memory address and true if
12493 we expect to load the address into a register. */
12495 static rtx
12497 {
12504 {
12509 {
12512 else
12513 {
12516 }
12517 }
12520 {
12523 else
12530 }
12531 else
12532 {
12536 {
12541 caddr));
12547 }
12548 else
12550 }
12557 {
12560 else
12561 {
12564 }
12565 }
12568 {
12573 else
12579 }
12580 else
12581 {
12585 {
12590 caddr));
12594 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12595 share the LD_BASE result with other LD model accesses. */
12597 UNSPEC_TLS_LD_BASE);
12601 }
12602 else
12604 }
12612 {
12616 }
12621 {
12623 {
12624 /* The Sun linker took the AMD64 TLS spec literally
12625 and can only handle %rax as destination of the
12626 initial executable code sequence. */
12631 }
12633 /* Generate DImode references to avoid %fs:(%reg32)
12634 problems and linker IE->LE relaxation bug. */
12638 }
12640 {
12645 }
12647 {
12651 }
12652 else
12653 {
12656 }
12666 {
12671 }
12672 else
12673 {
12677 }
12687 {
12691 }
12692 else
12693 {
12697 }
12702 }
12705 }
12707 /* Create or return the unique __imp_DECL dllimport symbol corresponding
12708 to symbol DECL. */
12711 htab_t dllimport_map;
12713 static tree
12715 {
12722 tree to;
12723 rtx rtl;
12767 }
12769 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
12770 true if we require the result be a register. */
12772 static rtx
12774 {
12775 tree imp_decl;
12776 rtx x;
12785 }
12787 /* Try machine-dependent ways of modifying an illegitimate address
12788 to be legitimate. If we find one, return the new, valid address.
12789 This macro is used in only one place: `memory_address' in explow.c.
12791 OLDX is the address as it was before break_out_memory_refs was called.
12792 In some cases it is useful to look at this to decide what needs to be done.
12794 It is always safe for this macro to do nothing. It exists to recognize
12795 opportunities to optimize the output.
12797 For the 80386, we handle X+REG by loading X into a register R and
12798 using R+REG. R will go in a general reg and indexing will be used.
12799 However, if REG is a broken-out memory address or multiplication,
12800 nothing needs to be done because REG can certainly go in a general reg.
12802 When -fpic is used, special handling is needed for symbolic references.
12803 See comments by legitimize_pic_address in i386.c for details. */
12805 static rtx
12808 {
12819 {
12823 }
12826 {
12833 {
12836 }
12837 }
12842 #if TARGET_MACHO
12845 #endif
12847 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
12851 {
12856 }
12859 {
12860 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
12865 {
12871 }
12876 {
12882 }
12884 /* Put multiply first if it isn't already. */
12886 {
12891 }
12893 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
12894 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
12895 created by virtual register instantiation, register elimination, and
12896 similar optimizations. */
12898 {
12904 }
12906 /* Canonicalize
12907 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
12908 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
12913 {
12914 rtx constant;
12918 {
12921 }
12923 {
12926 }
12927 else
12931 {
12938 }
12939 }
12945 {
12948 }
12951 {
12954 }
12962 {
12965 }
12971 {
12975 {
12979 }
12983 }
12986 {
12990 {
12994 }
12998 }
12999 }
13002 }
13003 \f
13004 /* Print an integer constant expression in assembler syntax. Addition
13005 and subtraction are the only arithmetic that may appear in these
13006 expressions. FILE is the stdio stream to write to, X is the rtx, and
13007 CODE is the operand print code from the output string. */
13009 static void
13011 {
13015 {
13024 else
13025 {
13028 /* Mark the decl as referenced so that cgraph will
13029 output the function. */
13033 #if TARGET_MACHO
13037 #endif
13039 }
13047 /* FALLTHRU */
13058 /* This used to output parentheses around the expression,
13059 but that does not work on the 386 (either ATT or BSD assembler). */
13065 {
13066 /* We can use %d if the number is <32 bits and positive. */
13071 else
13073 }
13074 else
13075 /* We can't handle floating point constants;
13076 TARGET_PRINT_OPERAND must handle them. */
13081 /* Some assemblers need integer constants to appear first. */
13083 {
13087 }
13088 else
13089 {
13094 }
13109 {
13113 }
13118 {
13137 /* FIXME: This might be @TPOFF in Sun ld too. */
13146 else
13156 else
13162 #if TARGET_MACHO
13167 #endif
13171 }
13176 }
13177 }
13179 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13180 We need to emit DTP-relative relocations. */
13182 static void ATTRIBUTE_UNUSED
13184 {
13189 {
13197 }
13198 }
13200 /* Return true if X is a representation of the PIC register. This copes
13201 with calls from ix86_find_base_term, where the register might have
13202 been replaced by a cselib value. */
13204 static bool
13206 {
13210 else
13212 }
13214 /* Helper function for ix86_delegitimize_address.
13215 Attempt to delegitimize TLS local-exec accesses. */
13217 static rtx
13219 {
13244 {
13249 }
13255 }
13257 /* In the name of slightly smaller debug output, and to cater to
13258 general assembler lossage, recognize PIC+GOTOFF and turn it back
13259 into a direct symbol reference.
13261 On Darwin, this is necessary to avoid a crash, because Darwin
13262 has a different PIC label for each routine but the DWARF debugging
13263 information is not associated with any particular routine, so it's
13264 necessary to remove references to the PIC label from RTL stored by
13265 the DWARF output code. */
13267 static rtx
13269 {
13271 /* addend is NULL or some rtx if x is something+GOTOFF where
13272 something doesn't include the PIC register. */
13274 /* reg_addend is NULL or a multiple of some register. */
13276 /* const_addend is NULL or a const_int. */
13278 /* This is the result, or NULL. */
13287 {
13294 {
13300 }
13309 {
13314 }
13316 }
13323 /* %ebx + GOT/GOTOFF */
13324 ;
13326 {
13327 /* %ebx + %reg * scale + GOT/GOTOFF */
13333 else
13334 {
13337 }
13338 }
13339 else
13345 {
13348 }
13367 {
13368 /* If the rest of original X doesn't involve the PIC register, add
13369 addend and subtract pic_offset_table_rtx. This can happen e.g.
13370 for code like:
13371 leal (%ebx, %ecx, 4), %ecx
13372 ...
13373 movl foo@GOTOFF(%ecx), %edx
13374 in which case we return (%ecx - %ebx) + foo. */
13377 pic_offset_table_rtx),
13378 result);
13379 else
13381 }
13383 {
13387 }
13389 }
13391 /* If X is a machine specific address (i.e. a symbol or label being
13392 referenced as a displacement from the GOT implemented using an
13393 UNSPEC), then return the base term. Otherwise return X. */
13395 rtx
13397 {
13398 rtx term;
13401 {
13415 }
13418 }
13419 \f
13420 static void
13423 {
13427 {
13430 }
13435 {
13438 {
13457 }
13461 {
13480 }
13487 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13488 Those same assemblers have the same but opposite lossage on cmov. */
13493 else
13498 {
13511 }
13519 {
13532 }
13535 /* ??? As above. */
13544 /* ??? As above. */
13549 else
13560 }
13562 }
13564 /* Print the name of register X to FILE based on its machine mode and number.
13565 If CODE is 'w', pretend the mode is HImode.
13566 If CODE is 'b', pretend the mode is QImode.
13567 If CODE is 'k', pretend the mode is SImode.
13568 If CODE is 'q', pretend the mode is DImode.
13569 If CODE is 'x', pretend the mode is V4SFmode.
13570 If CODE is 't', pretend the mode is V8SFmode.
13571 If CODE is 'h', pretend the reg is the 'high' byte register.
13572 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13573 If CODE is 'd', duplicate the operand for AVX instruction.
13574 */
13576 void
13578 {
13587 {
13591 }
13616 else
13619 /* Irritatingly, AMD extended registers use different naming convention
13620 from the normal registers: "r%d[bwd]" */
13622 {
13627 {
13641 /* no suffix */
13646 }
13648 }
13652 {
13655 {
13658 }
13659 /* FALLTHRU */
13665 /* FALLTHRU */
13668 normal:
13683 {
13688 }
13692 }
13696 {
13699 else
13701 }
13702 }
13704 /* Locate some local-dynamic symbol still in use by this function
13705 so that we can print its name in some tls_local_dynamic_base
13706 pattern. */
13708 static int
13710 {
13715 {
13718 }
13721 }
13725 {
13726 rtx insn;
13737 }
13739 /* Meaning of CODE:
13740 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
13741 C -- print opcode suffix for set/cmov insn.
13742 c -- like C, but print reversed condition
13743 F,f -- likewise, but for floating-point.
13744 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
13745 otherwise nothing
13746 R -- print the prefix for register names.
13747 z -- print the opcode suffix for the size of the current operand.
13748 Z -- likewise, with special suffixes for x87 instructions.
13749 * -- print a star (in certain assembler syntax)
13750 A -- print an absolute memory reference.
13751 E -- print address with DImode register names if TARGET_64BIT.
13752 w -- print the operand as if it's a "word" (HImode) even if it isn't.
13753 s -- print a shift double count, followed by the assemblers argument
13754 delimiter.
13755 b -- print the QImode name of the register for the indicated operand.
13756 %b0 would print %al if operands[0] is reg 0.
13757 w -- likewise, print the HImode name of the register.
13758 k -- likewise, print the SImode name of the register.
13759 q -- likewise, print the DImode name of the register.
13760 x -- likewise, print the V4SFmode name of the register.
13761 t -- likewise, print the V8SFmode name of the register.
13762 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
13763 y -- print "st(0)" instead of "st" as a register.
13764 d -- print duplicated register operand for AVX instruction.
13765 D -- print condition for SSE cmp instruction.
13766 P -- if PIC, print an @PLT suffix.
13767 p -- print raw symbol name.
13768 X -- don't print any sort of PIC '@' suffix for a symbol.
13769 & -- print some in-use local-dynamic symbol name.
13770 H -- print a memory address offset by 8; used for sse high-parts
13771 Y -- print condition for XOP pcom* instruction.
13772 + -- print a branch hint as 'cs' or 'ds' prefix
13773 ; -- print a semicolon (after prefixes due to bug in older gas).
13774 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
13775 @ -- print a segment register of thread base pointer load
13776 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
13777 */
13779 void
13781 {
13783 {
13785 {
13788 {
13794 /* Intel syntax. For absolute addresses, registers should not
13795 be surrounded by braces. */
13797 {
13802 }
13807 }
13813 /* Wrap address in an UNSPEC to declare special handling. */
13851 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
13856 {
13870 output_operand_lossage
13873 }
13876 #endif
13881 {
13882 /* Opcodes don't get size suffixes if using Intel opcodes. */
13887 {
13905 output_operand_lossage
13908 }
13909 }
13912 warning
13914 /* FALLTHRU */
13917 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
13922 {
13924 {
13926 #ifdef HAVE_AS_IX86_FILDS
13928 #endif
13936 #ifdef HAVE_AS_IX86_FILDQ
13938 #else
13940 #endif
13945 }
13946 }
13948 {
13949 /* 387 opcodes don't get size suffixes
13950 if the operands are registers. */
13955 {
13971 }
13972 }
13973 else
13974 {
13975 output_operand_lossage
13978 }
13980 output_operand_lossage
14000 {
14003 }
14008 {
14059 }
14063 /* Little bit of braindamage here. The SSE compare instructions
14064 does use completely different names for the comparisons that the
14065 fp conditional moves. */
14067 {
14070 {
14073 }
14079 {
14082 }
14088 {
14091 }
14100 {
14103 }
14109 {
14112 }
14118 {
14121 }
14132 }
14137 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14140 #endif
14145 {
14149 }
14153 file);
14158 {
14162 }
14163 /* It doesn't actually matter what mode we use here, as we're
14164 only going to use this for printing. */
14172 #ifdef HAVE_AS_IX86_HLE
14174 #else
14176 #endif
14178 #ifdef HAVE_AS_IX86_HLE
14180 #else
14182 #endif
14183 /* We do not want to print value of the operand. */
14192 {
14197 else
14200 }
14203 {
14204 rtx x;
14213 {
14218 {
14220 bool cputaken
14223 /* Emit hints only in the case default branch prediction
14224 heuristics would fail. */
14226 {
14227 /* We use 3e (DS) prefix for taken branches and
14228 2e (CS) prefix for not taken branches. */
14231 else
14233 }
14234 }
14235 }
14237 }
14240 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14242 #endif
14249 /* The kernel uses a different segment register for performance
14250 reasons; a system call would not have to trash the userspace
14251 segment register, which would be expensive. */
14254 else
14269 }
14270 }
14276 {
14277 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14280 {
14283 {
14292 else
14298 }
14300 /* Check for explicit size override (codes 'b', 'w', 'k',
14301 'q' and 'x') */
14315 }
14318 /* Avoid (%rip) for call operands. */
14324 else
14326 }
14329 {
14330 REAL_VALUE_TYPE r;
14338 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14341 else
14343 }
14346 {
14347 REAL_VALUE_TYPE r;
14356 }
14358 /* These float cases don't actually occur as immediate operands. */
14360 {
14365 }
14367 else
14368 {
14369 /* We have patterns that allow zero sets of memory, for instance.
14370 In 64-bit mode, we should probably support all 8-byte vectors,
14371 since we can in fact encode that into an immediate. */
14373 {
14376 }
14379 {
14381 {
14384 }
14387 {
14390 else
14392 }
14393 }
14398 else
14400 }
14401 }
14403 static bool
14405 {
14408 }
14409 \f
14410 /* Print a memory operand whose address is ADDR. */
14412 static void
14414 {
14423 {
14430 }
14432 {
14436 }
14437 else
14448 {
14459 }
14461 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14463 {
14475 }
14477 {
14478 /* Displacement only requires special attention. */
14481 {
14485 }
14488 else
14490 }
14491 else
14492 {
14493 /* Print SImode register names to force addr32 prefix. */
14495 {
14496 #ifdef ENABLE_CHECKING
14499 {
14510 }
14511 #endif
14514 }
14517 {
14519 {
14524 else
14526 }
14532 {
14537 }
14539 }
14540 else
14541 {
14545 {
14546 /* Pull out the offset of a symbol; print any symbol itself. */
14550 {
14554 }
14562 else
14564 }
14568 {
14571 {
14575 }
14576 }
14579 else
14583 {
14588 }
14590 }
14591 }
14592 }
14594 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14596 static bool
14598 {
14599 rtx op;
14606 {
14609 /* FIXME: This might be @TPOFF in Sun ld. */
14620 else
14632 else
14639 #if TARGET_MACHO
14645 #endif
14648 {
14653 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14655 #else
14657 #endif
14660 }
14665 }
14668 }
14669 \f
14670 /* Split one or more double-mode RTL references into pairs of half-mode
14671 references. The RTL can be REG, offsettable MEM, integer constant, or
14672 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14673 split and "num" is its length. lo_half and hi_half are output arrays
14674 that parallel "operands". */
14676 void
14679 {
14684 {
14693 }
14698 {
14701 /* simplify_subreg refuse to split volatile memory addresses,
14702 but we still have to handle it. */
14704 {
14707 }
14708 else
14709 {
14716 }
14717 }
14718 }
14719 \f
14720 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
14721 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
14722 is the expression of the binary operation. The output may either be
14723 emitted here, or returned to the caller, like all output_* functions.
14725 There is no guarantee that the operands are the same mode, as they
14726 might be within FLOAT or FLOAT_EXTEND expressions. */
14728 #ifndef SYSV386_COMPAT
14729 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
14730 wants to fix the assemblers because that causes incompatibility
14731 with gcc. No-one wants to fix gcc because that causes
14732 incompatibility with assemblers... You can use the option of
14733 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
14734 #define SYSV386_COMPAT 1
14735 #endif
14739 {
14745 #ifdef ENABLE_CHECKING
14746 /* Even if we do not want to check the inputs, this documents input
14747 constraints. Which helps in understanding the following code. */
14757 else
14759 #endif
14762 {
14767 else
14776 else
14785 else
14794 else
14801 }
14804 {
14806 {
14810 else
14812 }
14813 else
14814 {
14818 else
14820 }
14822 }
14826 {
14830 {
14834 }
14836 /* know operands[0] == operands[1]. */
14839 {
14842 }
14845 {
14847 /* How is it that we are storing to a dead operand[2]?
14848 Well, presumably operands[1] is dead too. We can't
14849 store the result to st(0) as st(0) gets popped on this
14850 instruction. Instead store to operands[2] (which I
14851 think has to be st(1)). st(1) will be popped later.
14852 gcc <= 2.8.1 didn't have this check and generated
14853 assembly code that the Unixware assembler rejected. */
14855 else
14858 }
14862 else
14869 {
14872 }
14875 {
14878 }
14881 {
14882 #if SYSV386_COMPAT
14883 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
14884 derived assemblers, confusingly reverse the direction of
14885 the operation for fsub{r} and fdiv{r} when the
14886 destination register is not st(0). The Intel assembler
14887 doesn't have this brain damage. Read !SYSV386_COMPAT to
14888 figure out what the hardware really does. */
14891 else
14893 #else
14895 /* As above for fmul/fadd, we can't store to st(0). */
14897 else
14899 #endif
14901 }
14904 {
14905 #if SYSV386_COMPAT
14908 else
14910 #else
14913 else
14915 #endif
14917 }
14920 {
14923 else
14926 }
14928 {
14929 #if SYSV386_COMPAT
14931 #else
14933 #endif
14934 }
14935 else
14936 {
14937 #if SYSV386_COMPAT
14939 #else
14941 #endif
14942 }
14947 }
14951 }
14953 /* Check if a 256bit AVX register is referenced in stores. */
14955 static void
14957 {
14963 {
14966 }
14967 }
14969 /* Return needed mode for entity in optimize_mode_switching pass. */
14971 static int
14973 {
14977 {
14978 rtx link;
14980 /* Needed mode is set to AVX_U128_CLEAN if there are
14981 no 256bit modes used in function arguments. */
14983 link;
14985 {
14987 {
14993 }
14994 }
14997 }
14999 /* Check if a 256bit AVX register is referenced in stores. */
15006 }
15008 /* Return mode that i387 must be switched into
15009 prior to the execution of insn. */
15011 static int
15013 {
15016 /* The mode UNINITIALIZED is used to store control word after a
15017 function call or ASM pattern. The mode ANY specify that function
15018 has no requirements on the control word and make no changes in the
15019 bits we are interested in. */
15033 {
15056 }
15059 }
15061 /* Return mode that entity must be switched into
15062 prior to the execution of insn. */
15064 int
15066 {
15068 {
15078 }
15080 }
15082 /* Calculate mode of upper 128bit AVX registers after the insn. */
15084 static int
15086 {
15094 /* Check if a 256bit AVX register is referenced in stores. */
15099 /* We know that state is clean after CALL insn if there are no
15100 256bit modes used in the function return register. */
15105 }
15107 /* Return the mode that an insn results in. */
15109 int
15111 {
15113 {
15123 }
15124 }
15126 static int
15128 {
15129 tree arg;
15131 /* Entry mode is set to AVX_U128_DIRTY if there are
15132 256bit modes used in function arguments. */
15135 {
15141 }
15144 }
15146 /* Return a mode that ENTITY is assumed to be
15147 switched to at function entry. */
15149 int
15151 {
15153 {
15163 }
15164 }
15166 static int
15168 {
15171 /* Exit mode is set to AVX_U128_DIRTY if there are
15172 256bit modes used in the function return register. */
15177 }
15179 /* Return a mode that ENTITY is assumed to be
15180 switched to at function exit. */
15182 int
15184 {
15186 {
15196 }
15197 }
15199 /* Output code to initialize control word copies used by trunc?f?i and
15200 rounding patterns. CURRENT_MODE is set to current control word,
15201 while NEW_MODE is set to new control word. */
15203 static void
15205 {
15207 rtx new_mode;
15218 {
15220 {
15222 /* round toward zero (truncate) */
15228 /* round down toward -oo */
15235 /* round up toward +oo */
15242 /* mask precision exception for nearbyint() */
15249 }
15250 }
15251 else
15252 {
15254 {
15256 /* round toward zero (truncate) */
15262 /* round down toward -oo */
15268 /* round up toward +oo */
15274 /* mask precision exception for nearbyint() */
15281 }
15282 }
15288 }
15290 /* Generate one or more insns to set ENTITY to MODE. */
15292 void
15294 {
15296 {
15311 }
15312 }
15314 /* Output code for INSN to convert a float to a signed int. OPERANDS
15315 are the insn operands. The output may be [HSD]Imode and the input
15316 operand may be [SDX]Fmode. */
15320 {
15325 /* Jump through a hoop or two for DImode, since the hardware has no
15326 non-popping instruction. We used to do this a different way, but
15327 that was somewhat fragile and broke with post-reload splitters. */
15337 else
15338 {
15343 else
15347 }
15350 }
15352 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15353 have the values zero or one, indicates the ffreep insn's operand
15354 from the OPERANDS array. */
15358 {
15360 #ifdef HAVE_AS_IX86_FFREEP
15362 #else
15363 {
15373 }
15374 #endif
15377 }
15380 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15381 should be used. UNORDERED_P is true when fucom should be used. */
15385 {
15391 {
15394 }
15395 else
15396 {
15399 }
15402 {
15406 else
15408 else
15411 else
15413 }
15420 {
15422 {
15425 }
15426 else
15428 }
15431 && stack_top_dies
15434 {
15435 /* If both the top of the 387 stack dies, and the other operand
15436 is also a stack register that dies, then this must be a
15437 `fcompp' float compare */
15440 {
15441 /* There is no double popping fcomi variant. Fortunately,
15442 eflags is immune from the fstp's cc clobbering. */
15445 else
15448 }
15449 else
15450 {
15453 else
15455 }
15456 }
15457 else
15458 {
15459 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15462 {
15470 NULL,
15471 NULL,
15478 NULL,
15479 NULL,
15480 NULL,
15481 NULL
15482 };
15497 }
15498 }
15500 void
15502 {
15505 #ifdef ASM_QUAD
15508 #else
15510 #endif
15513 }
15515 void
15517 {
15520 #ifdef ASM_QUAD
15523 #else
15525 #endif
15526 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15532 #if TARGET_MACHO
15534 {
15538 }
15539 #endif
15540 else
15543 }
15544 \f
15545 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15546 for the target. */
15548 void
15550 {
15551 rtx tmp;
15553 /* We play register width games, which are only valid after reload. */
15556 /* Avoid HImode and its attendant prefix byte. */
15561 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15563 {
15566 }
15569 }
15571 /* X is an unchanging MEM. If it is a constant pool reference, return
15572 the constant pool rtx, else NULL. */
15574 rtx
15576 {
15583 }
15585 void
15587 {
15595 {
15598 {
15605 }
15609 }
15613 {
15626 {
15634 }
15635 }
15639 {
15641 {
15642 #if TARGET_MACHO
15643 /* dynamic-no-pic */
15645 {
15646 rtx temp = ((reload_in_progress
15654 }
15656 {
15660 }
15663 else
15664 {
15672 }
15673 /* dynamic-no-pic */
15674 #endif
15675 }
15676 else
15677 {
15681 {
15688 }
15689 }
15690 }
15691 else
15692 {
15703 /* Force large constants in 64bit compilation into register
15704 to get them CSEed. */
15716 {
15717 /* If we are loading a floating point constant to a register,
15718 force the value to memory now, since we'll get better code
15719 out the back end. */
15723 {
15728 }
15729 }
15730 }
15733 }
15735 void
15737 {
15741 /* Force constants other than zero into memory. We do not know how
15742 the instructions used to build constants modify the upper 64 bits
15743 of the register, once we have that information we may be able
15744 to handle some of them more efficiently. */
15753 /* We need to check memory alignment for SSE mode since attribute
15754 can make operands unaligned. */
15759 {
15762 /* ix86_expand_vector_move_misalign() does not like constants ... */
15768 /* ... nor both arguments in memory. */
15776 }
15778 /* Make operand1 a register if it isn't already. */
15782 {
15785 }
15788 }
15790 /* Split 32-byte AVX unaligned load and store if needed. */
15792 static void
15794 {
15795 rtx m;
15802 {
15823 }
15826 {
15828 {
15835 }
15836 else
15838 }
15840 {
15842 {
15847 }
15848 else
15850 }
15851 else
15853 }
15855 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
15856 straight to ix86_expand_vector_move. */
15857 /* Code generation for scalar reg-reg moves of single and double precision data:
15858 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
15859 movaps reg, reg
15860 else
15861 movss reg, reg
15862 if (x86_sse_partial_reg_dependency == true)
15863 movapd reg, reg
15864 else
15865 movsd reg, reg
15867 Code generation for scalar loads of double precision data:
15868 if (x86_sse_split_regs == true)
15869 movlpd mem, reg (gas syntax)
15870 else
15871 movsd mem, reg
15873 Code generation for unaligned packed loads of single precision data
15874 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
15875 if (x86_sse_unaligned_move_optimal)
15876 movups mem, reg
15878 if (x86_sse_partial_reg_dependency == true)
15879 {
15880 xorps reg, reg
15881 movlps mem, reg
15882 movhps mem+8, reg
15883 }
15884 else
15885 {
15886 movlps mem, reg
15887 movhps mem+8, reg
15888 }
15890 Code generation for unaligned packed loads of double precision data
15891 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
15892 if (x86_sse_unaligned_move_optimal)
15893 movupd mem, reg
15895 if (x86_sse_split_regs == true)
15896 {
15897 movlpd mem, reg
15898 movhpd mem+8, reg
15899 }
15900 else
15901 {
15902 movsd mem, reg
15903 movhpd mem+8, reg
15904 }
15905 */
15907 void
15909 {
15917 {
15919 {
15924 /* FALLTHRU */
15932 }
15935 }
15938 {
15939 /* ??? If we have typed data, then it would appear that using
15940 movdqu is the only way to get unaligned data loaded with
15941 integer type. */
15943 {
15946 /* We will eventually emit movups based on insn attributes. */
15948 }
15950 {
15951 rtx zero;
15954 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
15955 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
15957 {
15958 /* We will eventually emit movups based on insn attributes. */
15961 }
15963 /* When SSE registers are split into halves, we can avoid
15964 writing to the top half twice. */
15966 {
15969 }
15970 else
15971 {
15972 /* ??? Not sure about the best option for the Intel chips.
15973 The following would seem to satisfy; the register is
15974 entirely cleared, breaking the dependency chain. We
15975 then store to the upper half, with a dependency depth
15976 of one. A rumor has it that Intel recommends two movsd
15977 followed by an unpacklpd, but this is unconfirmed. And
15978 given that the dependency depth of the unpacklpd would
15979 still be one, I'm not sure why this would be better. */
15981 }
15987 }
15988 else
15989 {
15991 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
15992 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
15994 {
15999 }
16003 else
16013 }
16014 }
16016 {
16018 {
16021 /* We will eventually emit movups based on insn attributes. */
16023 }
16025 {
16027 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16028 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16030 /* We will eventually emit movups based on insn attributes. */
16032 else
16033 {
16038 }
16039 }
16040 else
16041 {
16046 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16047 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16049 {
16052 }
16053 else
16054 {
16059 }
16060 }
16061 }
16062 else
16064 }
16066 /* Expand a push in MODE. This is some mode for which we do not support
16067 proper push instructions, at least from the registers that we expect
16068 the value to live in. */
16070 void
16072 {
16073 rtx tmp;
16083 /* When we push an operand onto stack, it has to be aligned at least
16084 at the function argument boundary. However since we don't have
16085 the argument type, we can't determine the actual argument
16086 boundary. */
16088 }
16090 /* Helper function of ix86_fixup_binary_operands to canonicalize
16091 operand order. Returns true if the operands should be swapped. */
16093 static bool
16095 rtx operands[])
16096 {
16101 /* If the operation is not commutative, we can't do anything. */
16105 /* Highest priority is that src1 should match dst. */
16111 /* Next highest priority is that immediate constants come second. */
16117 /* Lowest priority is that memory references should come second. */
16124 }
16127 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16128 destination to use for the operation. If different from the true
16129 destination in operands[0], a copy operation will be required. */
16131 rtx
16133 rtx operands[])
16134 {
16139 /* Canonicalize operand order. */
16141 {
16142 rtx temp;
16144 /* It is invalid to swap operands of different modes. */
16150 }
16152 /* Both source operands cannot be in memory. */
16154 {
16155 /* Optimization: Only read from memory once. */
16157 {
16160 }
16161 else
16163 }
16165 /* If the destination is memory, and we do not have matching source
16166 operands, do things in registers. */
16170 /* Source 1 cannot be a constant. */
16174 /* Source 1 cannot be a non-matching memory. */
16178 /* Improve address combine. */
16187 }
16189 /* Similarly, but assume that the destination has already been
16190 set up properly. */
16192 void
16195 {
16198 }
16200 /* Attempt to expand a binary operator. Make the expansion closer to the
16201 actual machine, then just general_operand, which will allow 3 separate
16202 memory references (one output, two input) in a single insn. */
16204 void
16206 rtx operands[])
16207 {
16214 /* Emit the instruction. */
16218 {
16219 /* Reload doesn't know about the flags register, and doesn't know that
16220 it doesn't want to clobber it. We can only do this with PLUS. */
16223 }
16227 {
16228 /* This is going to be an LEA; avoid splitting it later. */
16230 }
16231 else
16232 {
16235 }
16237 /* Fix up the destination if needed. */
16240 }
16242 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16243 the given OPERANDS. */
16245 void
16247 rtx operands[])
16248 {
16251 {
16254 }
16256 {
16259 }
16260 /* Optimize (__m128i) d | (__m128i) e and similar code
16261 when d and e are float vectors into float vector logical
16262 insn. In C/C++ without using intrinsics there is no other way
16263 to express vector logical operation on float vectors than
16264 to cast them temporarily to integer vectors. */
16266 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16275 {
16276 rtx dst;
16278 {
16285 {
16288 }
16289 else
16290 {
16295 }
16306 }
16307 }
16316 }
16318 /* Return TRUE or FALSE depending on whether the binary operator meets the
16319 appropriate constraints. */
16321 bool
16324 {
16329 /* Both source operands cannot be in memory. */
16333 /* Canonicalize operand order for commutative operators. */
16335 {
16339 }
16341 /* If the destination is memory, we must have a matching source operand. */
16345 /* Source 1 cannot be a constant. */
16349 /* Source 1 cannot be a non-matching memory. */
16351 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16359 }
16361 /* Attempt to expand a unary operator. Make the expansion closer to the
16362 actual machine, then just general_operand, which will allow 2 separate
16363 memory references (one output, one input) in a single insn. */
16365 void
16367 rtx operands[])
16368 {
16375 /* If the destination is memory, and we do not have matching source
16376 operands, do things in registers. */
16379 {
16382 else
16384 }
16386 /* When source operand is memory, destination must match. */
16390 /* Emit the instruction. */
16394 {
16395 /* Reload doesn't know about the flags register, and doesn't know that
16396 it doesn't want to clobber it. */
16399 }
16400 else
16401 {
16404 }
16406 /* Fix up the destination if needed. */
16409 }
16411 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16412 divisor are within the range [0-255]. */
16414 void
16417 {
16426 {
16439 }
16446 /* Use 8bit unsigned divimod if dividend and divisor are within
16447 the range [0-255]. */
16456 pc_rtx);
16461 /* Generate original signed/unsigned divimod. */
16466 /* Branch to the end. */
16470 /* Generate 8bit unsigned divide. */
16472 /* Don't use operands[0] for result of 8bit divide since not all
16473 registers support QImode ZERO_EXTRACT. */
16480 {
16483 }
16484 else
16485 {
16488 }
16490 /* Extract remainder from AH. */
16494 else
16495 {
16496 /* Need a new scratch register since the old one has result
16497 of 8bit divide. */
16501 }
16504 /* Zero extend quotient from AL. */
16510 }
16512 #define LEA_MAX_STALL (3)
16513 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16515 /* Increase given DISTANCE in half-cycles according to
16516 dependencies between PREV and NEXT instructions.
16517 Add 1 half-cycle if there is no dependency and
16518 go to next cycle if there is some dependecy. */
16520 static unsigned int
16522 {
16539 }
16541 /* Function checks if instruction INSN defines register number
16542 REGNO1 or REGNO2. */
16544 static bool
16546 rtx insn)
16547 {
16555 {
16557 }
16560 }
16562 /* Function checks if instruction INSN uses register number
16563 REGNO as a part of address expression. */
16565 static bool
16567 {
16575 }
16577 /* Search backward for non-agu definition of register number REGNO1
16578 or register number REGNO2 in basic block starting from instruction
16579 START up to head of basic block or instruction INSN.
16581 Function puts true value into *FOUND var if definition was found
16582 and false otherwise.
16584 Distance in half-cycles between START and found instruction or head
16585 of BB is added to DISTANCE and returned. */
16587 static int
16591 {
16601 {
16603 {
16606 {
16609 {
16612 }
16613 }
16616 }
16621 }
16624 }
16626 /* Search backward for non-agu definition of register number REGNO1
16627 or register number REGNO2 in INSN's basic block until
16628 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16629 2. Reach neighbour BBs boundary, or
16630 3. Reach agu definition.
16631 Returns the distance between the non-agu definition point and INSN.
16632 If no definition point, returns -1. */
16634 static int
16636 rtx insn)
16637 {
16648 {
16649 edge e;
16650 edge_iterator ei;
16655 {
16658 }
16664 else
16665 {
16670 {
16671 int bb_dist
16677 {
16684 }
16685 }
16688 }
16689 }
16691 /* get_attr_type may modify recog data. We want to make sure
16692 that recog data is valid for instruction INSN, on which
16693 distance_non_agu_define is called. INSN is unchanged here. */
16700 }
16702 /* Return the distance in half-cycles between INSN and the next
16703 insn that uses register number REGNO in memory address added
16704 to DISTANCE. Return -1 if REGNO0 is set.
16706 Put true value into *FOUND if register usage was found and
16707 false otherwise.
16708 Put true value into *REDEFINED if register redefinition was
16709 found and false otherwise. */
16711 static int
16715 {
16726 {
16728 {
16731 {
16732 /* Return DISTANCE if OP0 is used in memory
16733 address in NEXT. */
16736 }
16739 {
16740 /* Return -1 if OP0 is set in NEXT. */
16743 }
16746 }
16752 }
16755 }
16757 /* Return the distance between INSN and the next insn that uses
16758 register number REGNO0 in memory address. Return -1 if no such
16759 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
16761 static int
16763 {
16775 {
16776 edge e;
16777 edge_iterator ei;
16782 {
16785 }
16791 else
16792 {
16798 {
16799 int bb_dist
16804 {
16811 }
16812 }
16815 }
16816 }
16822 }
16824 /* Define this macro to tune LEA priority vs ADD, it take effect when
16825 there is a dilemma of choicing LEA or ADD
16826 Negative value: ADD is more preferred than LEA
16827 Zero: Netrual
16828 Positive value: LEA is more preferred than ADD*/
16829 #define IX86_LEA_PRIORITY 0
16831 /* Return true if usage of lea INSN has performance advantage
16832 over a sequence of instructions. Instructions sequence has
16833 SPLIT_COST cycles higher latency than lea latency. */
16835 static bool
16838 {
16845 {
16846 /* If there is no non AGU operand definition, no AGU
16847 operand usage and split cost is 0 then both lea
16848 and non lea variants have same priority. Currently
16849 we prefer lea for 64 bit code and non lea on 32 bit
16850 code. */
16853 else
16855 }
16857 /* With longer definitions distance lea is more preferable.
16858 Here we change it to take into account splitting cost and
16859 lea priority. */
16862 /* If there is no use in memory addess then we just check
16863 that split cost exceeds AGU stall. */
16867 /* If this insn has both backward non-agu dependence and forward
16868 agu dependence, the one with short distance takes effect. */
16870 }
16872 /* Return true if it is legal to clobber flags by INSN and
16873 false otherwise. */
16875 static bool
16877 {
16880 bitmap live;
16883 {
16885 {
16892 }
16898 }
16902 }
16904 /* Return true if we need to split op0 = op1 + op2 into a sequence of
16905 move and add to avoid AGU stalls. */
16907 bool
16909 {
16912 /* Check if we need to optimize. */
16916 /* Check it is correct to split here. */
16924 /* We need to split only adds with non destructive
16925 destination operand. */
16928 else
16930 }
16932 /* Return true if we should emit lea instruction instead of mov
16933 instruction. */
16935 bool
16937 {
16940 /* Check if we need to optimize. */
16944 /* Use lea for reg to reg moves only. */
16952 }
16954 /* Return true if we need to split lea into a sequence of
16955 instructions to avoid AGU stalls. */
16957 bool
16959 {
16965 /* Check we need to optimize. */
16969 /* Check it is correct to split here. */
16976 /* There should be at least two components in the address. */
16981 /* We should not split into add if non legitimate pic
16982 operand is used as displacement. */
16997 /* Compute how many cycles we will add to execution time
16998 if split lea into a sequence of instructions. */
17000 {
17001 /* Have to use mov instruction if non desctructive
17002 destination form is used. */
17006 /* Have to add index to base if both exist. */
17010 /* Have to use shift and adds if scale is 2 or greater. */
17012 {
17017 else
17019 }
17021 /* Have to use add instruction with immediate if
17022 disp is non zero. */
17026 /* Subtract the price of lea. */
17028 }
17031 }
17033 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17034 matches destination. RTX includes clobber of FLAGS_REG. */
17036 static void
17039 {
17046 }
17048 /* Return true if regno1 def is nearest to the insn. */
17050 static bool
17052 {
17059 {
17061 {
17064 }
17070 }
17072 /* None of the regs is defined in the bb. */
17074 }
17076 /* Split lea instructions into a sequence of instructions
17077 which are executed on ALU to avoid AGU stalls.
17078 It is assumed that it is allowed to clobber flags register
17079 at lea position. */
17081 void
17083 {
17099 {
17102 }
17105 {
17108 }
17114 {
17115 /* Case r1 = r1 + ... */
17117 {
17118 /* If we have a case r1 = r1 + C * r1 then we
17119 should use multiplication which is very
17120 expensive. Assume cost model is wrong if we
17121 have such case here. */
17126 }
17127 else
17128 {
17129 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17133 /* Use shift for scaling. */
17142 }
17143 }
17145 {
17148 }
17149 else
17150 {
17152 {
17155 }
17157 {
17160 }
17161 else
17162 {
17167 else
17168 {
17169 rtx tmp1;
17171 /* Find better operand for SET instruction, depending
17172 on which definition is farther from the insn. */
17175 else
17185 }
17188 }
17192 }
17193 }
17195 /* Return true if it is ok to optimize an ADD operation to LEA
17196 operation to avoid flag register consumation. For most processors,
17197 ADD is faster than LEA. For the processors like ATOM, if the
17198 destination register of LEA holds an actual address which will be
17199 used soon, LEA is better and otherwise ADD is better. */
17201 bool
17203 {
17208 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17216 }
17218 /* Return true if destination reg of SET_BODY is shift count of
17219 USE_BODY. */
17221 static bool
17223 {
17224 rtx set_dest;
17225 rtx shift_rtx;
17228 /* Retrieve destination of SET_BODY. */
17230 {
17239 use_body))
17244 }
17246 /* Retrieve shift count of USE_BODY. */
17248 {
17260 }
17268 {
17271 /* Return true if shift count is dest of SET_BODY. */
17273 {
17274 /* Add check since it can be invoked before register
17275 allocation in pre-reload schedule. */
17281 }
17282 }
17285 }
17287 /* Return true if destination reg of SET_INSN is shift count of
17288 USE_INSN. */
17290 bool
17292 {
17295 }
17297 /* Return TRUE or FALSE depending on whether the unary operator meets the
17298 appropriate constraints. */
17300 bool
17304 {
17305 /* If one of operands is memory, source and destination must match. */
17311 }
17313 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17314 are ok, keeping in mind the possible movddup alternative. */
17316 bool
17318 {
17324 }
17326 /* Post-reload splitter for converting an SF or DFmode value in an
17327 SSE register into an unsigned SImode. */
17329 void
17331 {
17342 /* Load up the value into the low element. We must ensure that the other
17343 elements are valid floats -- zero is the easiest such value. */
17345 {
17348 else
17350 }
17351 else
17352 {
17357 else
17359 }
17379 else
17384 }
17386 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17387 Expects the 64-bit DImode to be supplied in a pair of integral
17388 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17389 -mfpmath=sse, !optimize_size only. */
17391 void
17393 {
17397 rtx x;
17403 {
17406 }
17407 else
17408 {
17412 }
17420 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17423 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17424 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17425 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17426 (0x1.0p84 + double(fp_value_hi_xmm)).
17427 Note these exponents differ by 32. */
17431 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17432 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17441 /* Add the upper and lower DFmode values together. */
17444 else
17445 {
17449 }
17452 }
17454 /* Not used, but eases macroization of patterns. */
17455 void
17457 rtx input ATTRIBUTE_UNUSED)
17458 {
17460 }
17462 /* Convert an unsigned SImode value into a DFmode. Only currently used
17463 for SSE, but applicable anywhere. */
17465 void
17467 {
17468 REAL_VALUE_TYPE TWO31r;
17483 }
17485 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17486 32-bit mode; otherwise we have a direct convert instruction. */
17488 void
17490 {
17491 REAL_VALUE_TYPE TWO32r;
17509 }
17511 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17512 For x86_32, -mfpmath=sse, !optimize_size only. */
17513 void
17515 {
17516 REAL_VALUE_TYPE ONE16r;
17535 }
17537 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17538 a vector of unsigned ints VAL to vector of floats TARGET. */
17540 void
17542 {
17544 REAL_VALUE_TYPE TWO16r;
17551 else
17556 OPTAB_DIRECT);
17567 OPTAB_DIRECT);
17569 OPTAB_DIRECT);
17572 }
17574 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17575 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17576 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17577 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17579 rtx
17581 {
17582 REAL_VALUE_TYPE TWO31r;
17597 {
17603 }
17612 OPTAB_DIRECT);
17613 else
17614 {
17620 OPTAB_DIRECT);
17621 }
17624 }
17626 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17627 then replicate the value for all elements of the vector
17628 register. */
17630 rtx
17632 {
17634 rtvec v;
17638 {
17665 }
17666 }
17668 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
17669 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
17670 for an SSE register. If VECT is true, then replicate the mask for
17671 all elements of the vector register. If INVERT is true, then create
17672 a mask excluding the sign bit. */
17674 rtx
17676 {
17680 rtx v;
17681 rtx mask;
17683 /* Find the sign bit, sign extended to 2*HWI. */
17685 {
17705 else
17713 {
17716 }
17717 else
17718 {
17719 rtvec vec;
17725 {
17728 }
17729 else
17739 }
17744 }
17749 /* Force this value into the low part of a fp vector constant. */
17758 }
17760 /* Generate code for floating point ABS or NEG. */
17762 void
17764 rtx operands[])
17765 {
17776 {
17782 }
17784 /* NEG and ABS performed with SSE use bitwise mask operations.
17785 Create the appropriate mask now. */
17788 else
17798 {
17800 rtvec par;
17805 else
17806 {
17809 }
17811 }
17812 else
17814 }
17816 /* Expand a copysign operation. Special case operand 0 being a constant. */
17818 void
17820 {
17834 else
17838 {
17845 {
17848 else
17849 {
17853 }
17854 }
17864 else
17868 }
17869 else
17870 {
17880 else
17884 }
17885 }
17887 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
17888 be a constant, and so has already been expanded into a vector constant. */
17890 void
17892 {
17908 {
17911 }
17912 }
17914 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
17915 so we have to do two masks. */
17917 void
17919 {
17934 {
17935 /* Shouldn't happen often (it's useless, obviously), but when it does
17936 we'd generate incorrect code if we continue below. */
17939 }
17942 {
17953 }
17954 else
17955 {
17957 {
17959 }
17961 {
17965 }
17969 {
17972 }
17974 {
17979 }
17981 }
17985 }
17987 /* Return TRUE or FALSE depending on whether the first SET in INSN
17988 has source and destination with matching CC modes, and that the
17989 CC mode is at least as constrained as REQ_MODE. */
17991 bool
17993 {
17994 rtx set;
18005 {
18015 /* FALLTHRU */
18019 /* FALLTHRU */
18023 /* FALLTHRU */
18037 }
18040 }
18042 /* Generate insn patterns to do an integer compare of OPERANDS. */
18044 static rtx
18046 {
18053 /* This is very simple, but making the interface the same as in the
18054 FP case makes the rest of the code easier. */
18058 /* Return the test that should be put into the flags user, i.e.
18059 the bcc, scc, or cmov instruction. */
18061 }
18063 /* Figure out whether to use ordered or unordered fp comparisons.
18064 Return the appropriate mode to use. */
18066 enum machine_mode
18068 {
18069 /* ??? In order to make all comparisons reversible, we do all comparisons
18070 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18071 all forms trapping and nontrapping comparisons, we can make inequality
18072 comparisons trapping again, since it results in better code when using
18073 FCOM based compares. */
18075 }
18077 enum machine_mode
18079 {
18083 {
18086 }
18089 {
18090 /* Only zero flag is needed. */
18094 /* Codes needing carry flag. */
18097 /* Detect overflow checks. They need just the carry flag. */
18101 else
18105 /* Detect overflow checks. They need just the carry flag. */
18109 else
18111 /* Codes possibly doable only with sign flag when
18112 comparing against zero. */
18117 else
18118 /* For other cases Carry flag is not required. */
18120 /* Codes doable only with sign flag when comparing
18121 against zero, but we miss jump instruction for it
18122 so we need to use relational tests against overflow
18123 that thus needs to be zero. */
18128 else
18130 /* strcmp pattern do (use flags) and combine may ask us for proper
18131 mode. */
18136 }
18137 }
18139 /* Return the fixed registers used for condition codes. */
18141 static bool
18143 {
18147 }
18149 /* If two condition code modes are compatible, return a condition code
18150 mode which is compatible with both. Otherwise, return
18151 VOIDmode. */
18153 static enum machine_mode
18155 {
18172 {
18186 {
18200 }
18204 /* These are only compatible with themselves, which we already
18205 checked above. */
18207 }
18208 }
18211 /* Return a comparison we can do and that it is equivalent to
18212 swap_condition (code) apart possibly from orderedness.
18213 But, never change orderedness if TARGET_IEEE_FP, returning
18214 UNKNOWN in that case if necessary. */
18216 static enum rtx_code
18218 {
18220 {
18231 }
18232 }
18234 /* Return cost of comparison CODE using the best strategy for performance.
18235 All following functions do use number of instructions as a cost metrics.
18236 In future this should be tweaked to compute bytes for optimize_size and
18237 take into account performance of various instructions on various CPUs. */
18239 static int
18241 {
18244 /* The cost of code using bit-twiddling on %ah. */
18246 {
18269 }
18272 {
18279 }
18280 }
18282 /* Return strategy to use for floating-point. We assume that fcomi is always
18283 preferrable where available, since that is also true when looking at size
18284 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18286 enum ix86_fpcmp_strategy
18288 {
18289 /* Do fcomi/sahf based test when profitable. */
18298 }
18300 /* Swap, force into registers, or otherwise massage the two operands
18301 to a fp comparison. The operands are updated in place; the new
18302 comparison code is returned. */
18304 static enum rtx_code
18306 {
18312 /* All of the unordered compare instructions only work on registers.
18313 The same is true of the fcomi compare instructions. The XFmode
18314 compare instructions require registers except when comparing
18315 against zero or when converting operand 1 from fixed point to
18316 floating point. */
18325 {
18328 }
18329 else
18330 {
18331 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18332 things around if they appear profitable, otherwise force op0
18333 into a register. */
18339 {
18342 {
18343 rtx tmp;
18346 }
18347 }
18353 {
18358 {
18361 }
18362 else
18364 }
18365 }
18367 /* Try to rearrange the comparison to make it cheaper. */
18371 {
18372 rtx tmp;
18377 }
18382 }
18384 /* Convert comparison codes we use to represent FP comparison to integer
18385 code that will result in proper branch. Return UNKNOWN if no such code
18386 is available. */
18388 enum rtx_code
18390 {
18392 {
18415 }
18416 }
18418 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18420 static rtx
18422 {
18429 /* Do fcomi/sahf based test when profitable. */
18431 {
18436 tmp);
18444 tmp);
18453 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18460 /* In the unordered case, we have to check C2 for NaN's, which
18461 doesn't happen to work out to anything nice combination-wise.
18462 So do some bit twiddling on the value we've got in AH to come
18463 up with an appropriate set of condition codes. */
18467 {
18471 {
18474 }
18475 else
18476 {
18482 }
18487 {
18492 }
18493 else
18494 {
18497 }
18502 {
18505 }
18506 else
18507 {
18511 }
18516 {
18522 }
18523 else
18524 {
18527 }
18532 {
18537 }
18538 else
18539 {
18542 }
18547 {
18552 }
18553 else
18554 {
18557 }
18571 }
18576 }
18578 /* Return the test that should be put into the flags user, i.e.
18579 the bcc, scc, or cmov instruction. */
18582 const0_rtx);
18583 }
18585 static rtx
18587 {
18588 rtx ret;
18594 {
18597 }
18598 else
18602 }
18604 void
18606 {
18608 rtx tmp;
18611 {
18618 simple:
18622 pc_rtx);
18630 /* Expand DImode branch into multiple compare+branch. */
18631 {
18637 {
18640 }
18647 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18648 avoid two branches. This costs one extra insn, so disable when
18649 optimizing for size. */
18654 {
18672 }
18674 /* Otherwise, if we are doing less-than or greater-or-equal-than,
18675 op1 is a constant and the low word is zero, then we can just
18676 examine the high word. Similarly for low word -1 and
18677 less-or-equal-than or greater-than. */
18681 {
18684 {
18687 }
18691 {
18694 }
18698 }
18700 /* Otherwise, we need two or three jumps. */
18709 {
18723 }
18725 /*
18726 * a < b =>
18727 * if (hi(a) < hi(b)) goto true;
18728 * if (hi(a) > hi(b)) goto false;
18729 * if (lo(a) < lo(b)) goto true;
18730 * false:
18731 */
18743 }
18748 }
18749 }
18751 /* Split branch based on floating point condition. */
18752 void
18755 {
18756 rtx condition;
18757 rtx i;
18760 {
18765 }
18768 tmp);
18770 /* Remove pushed operand from stack. */
18780 }
18782 void
18784 {
18785 rtx ret;
18792 }
18794 /* Expand comparison setting or clearing carry flag. Return true when
18795 successful and set pop for the operation. */
18796 static bool
18798 {
18802 /* Do not handle double-mode compares that go through special path. */
18807 {
18812 /* Shortcut: following common codes never translate
18813 into carry flag compares. */
18818 /* These comparisons require zero flag; swap operands so they won't. */
18821 {
18826 }
18828 /* Try to expand the comparison and verify that we end up with
18829 carry flag based comparison. This fails to be true only when
18830 we decide to expand comparison using arithmetic that is not
18831 too common scenario. */
18840 else
18849 }
18855 {
18860 /* Convert a==0 into (unsigned)a<1. */
18869 /* Convert a>b into b<a or a>=b-1. */
18873 {
18875 /* Bail out on overflow. We still can swap operands but that
18876 would force loading of the constant into register. */
18881 }
18882 else
18883 {
18888 }
18891 /* Convert a>=0 into (unsigned)a<0x80000000. */
18909 }
18910 /* Swapping operands may cause constant to appear as first operand. */
18912 {
18916 }
18920 }
18922 bool
18924 {
18948 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
18949 HImode insns, we'd be swallowed in word prefix ops. */
18955 {
18959 HOST_WIDE_INT diff;
18962 /* Sign bit compares are better done using shifts than we do by using
18963 sbb. */
18966 {
18967 /* Detect overlap between destination and compare sources. */
18971 {
18972 rtx flags;
18981 {
18983 compare_code
18985 }
18987 /* To simplify rest of code, restrict to the GEU case. */
18989 {
18995 }
18996 else
18997 {
19000 reverse_condition_maybe_unordered
19002 else
19005 }
19014 else
19017 }
19018 else
19019 {
19022 else
19023 {
19028 }
19030 }
19033 {
19034 /*
19035 * cmpl op0,op1
19036 * sbbl dest,dest
19037 * [addl dest, ct]
19038 *
19039 * Size 5 - 8.
19040 */
19045 }
19047 {
19048 /*
19049 * cmpl op0,op1
19050 * sbbl dest,dest
19051 * orl $ct, dest
19052 *
19053 * Size 8.
19054 */
19058 }
19060 {
19061 /*
19062 * cmpl op0,op1
19063 * sbbl dest,dest
19064 * notl dest
19065 * [addl dest, cf]
19066 *
19067 * Size 8 - 11.
19068 */
19074 }
19075 else
19076 {
19077 /*
19078 * cmpl op0,op1
19079 * sbbl dest,dest
19080 * [notl dest]
19081 * andl cf - ct, dest
19082 * [addl dest, ct]
19083 *
19084 * Size 8 - 11.
19085 */
19088 {
19092 }
19102 }
19108 }
19111 {
19114 HOST_WIDE_INT tmp;
19119 {
19122 /* We may be reversing unordered compare to normal compare, that
19123 is not valid in general (we may convert non-trapping condition
19124 to trapping one), however on i386 we currently emit all
19125 comparisons unordered. */
19128 }
19129 else
19130 {
19133 }
19134 }
19139 {
19144 {
19149 }
19150 }
19152 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19156 {
19157 /* If lea code below could be used, only optimize
19158 if it results in a 2 insn sequence. */
19164 {
19165 /*
19166 * notl op1 (if necessary)
19167 * sarl $31, op1
19168 * orl cf, op1
19169 */
19171 {
19175 }
19186 }
19187 }
19195 {
19196 /*
19197 * xorl dest,dest
19198 * cmpl op1,op2
19199 * setcc dest
19200 * lea cf(dest*(ct-cf)),dest
19201 *
19202 * Size 14.
19203 *
19204 * This also catches the degenerate setcc-only case.
19205 */
19207 rtx tmp;
19213 /* On x86_64 the lea instruction operates on Pmode, so we need
19214 to get arithmetics done in proper mode to match. */
19217 else
19218 {
19219 rtx out1;
19222 nops++;
19224 {
19226 nops++;
19227 }
19228 }
19230 {
19232 nops++;
19233 }
19235 {
19238 else
19240 }
19245 }
19247 /*
19248 * General case: Jumpful:
19249 * xorl dest,dest cmpl op1, op2
19250 * cmpl op1, op2 movl ct, dest
19251 * setcc dest jcc 1f
19252 * decl dest movl cf, dest
19253 * andl (cf-ct),dest 1:
19254 * addl ct,dest
19255 *
19256 * Size 20. Size 14.
19257 *
19258 * This is reasonably steep, but branch mispredict costs are
19259 * high on modern cpus, so consider failing only if optimizing
19260 * for space.
19261 */
19266 {
19268 {
19275 {
19278 /* We may be reversing unordered compare to normal compare,
19279 that is not valid in general (we may convert non-trapping
19280 condition to trapping one), however on i386 we currently
19281 emit all comparisons unordered. */
19283 }
19284 else
19285 {
19289 }
19290 }
19293 {
19294 /* notl op1 (if needed)
19295 sarl $31, op1
19296 andl (cf-ct), op1
19297 addl ct, op1
19299 For x < 0 (resp. x <= -1) there will be no notl,
19300 so if possible swap the constants to get rid of the
19301 complement.
19302 True/false will be -1/0 while code below (store flag
19303 followed by decrement) is 0/-1, so the constants need
19304 to be exchanged once more. */
19307 {
19310 }
19311 else
19312 {
19316 }
19319 }
19320 else
19321 {
19325 constm1_rtx,
19327 }
19339 }
19340 }
19343 {
19344 /* Try a few things more with specific constants and a variable. */
19346 optab op;
19352 /* If one of the two operands is an interesting constant, load a
19353 constant with the above and mask it in with a logical operation. */
19356 {
19362 else
19364 }
19366 {
19372 else
19374 }
19375 else
19382 /* Recurse to get the constant loaded. */
19386 /* Mask in the interesting variable. */
19388 OPTAB_WIDEN);
19393 }
19395 /*
19396 * For comparison with above,
19397 *
19398 * movl cf,dest
19399 * movl ct,tmp
19400 * cmpl op1,op2
19401 * cmovcc tmp,dest
19402 *
19403 * Size 15.
19404 */
19426 }
19428 /* Swap, force into registers, or otherwise massage the two operands
19429 to an sse comparison with a mask result. Thus we differ a bit from
19430 ix86_prepare_fp_compare_args which expects to produce a flags result.
19432 The DEST operand exists to help determine whether to commute commutative
19433 operators. The POP0/POP1 operands are updated in place. The new
19434 comparison code is returned, or UNKNOWN if not implementable. */
19436 static enum rtx_code
19439 {
19440 rtx tmp;
19443 {
19446 /* AVX supports all the needed comparisons. */
19449 /* We have no LTGT as an operator. We could implement it with
19450 NE & ORDERED, but this requires an extra temporary. It's
19451 not clear that it's worth it. */
19458 /* These are supported directly. */
19465 /* AVX has 3 operand comparisons, no need to swap anything. */
19468 /* For commutative operators, try to canonicalize the destination
19469 operand to be first in the comparison - this helps reload to
19470 avoid extra moves. */
19473 /* FALLTHRU */
19479 /* These are not supported directly before AVX, and furthermore
19480 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19481 comparison operands to transform into something that is
19482 supported. */
19491 }
19494 }
19496 /* Detect conditional moves that exactly match min/max operational
19497 semantics. Note that this is IEEE safe, as long as we don't
19498 interchange the operands.
19500 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19501 and TRUE if the operation is successful and instructions are emitted. */
19503 static bool
19506 {
19509 rtx tmp;
19512 ;
19514 {
19518 }
19519 else
19526 else
19531 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19532 but MODE may be a vector mode and thus not appropriate. */
19534 {
19536 rtvec v;
19541 }
19542 else
19543 {
19546 }
19550 }
19552 /* Expand an sse vector comparison. Return the register with the result. */
19554 static rtx
19557 {
19560 rtx x;
19573 {
19576 }
19577 else
19581 }
19583 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19584 operations. This is used for both scalar and vector conditional moves. */
19586 static void
19588 {
19594 {
19596 }
19598 {
19602 }
19604 {
19609 }
19611 {
19615 }
19617 {
19625 op_true,
19626 op_false)));
19627 }
19628 else
19629 {
19638 {
19652 {
19658 }
19673 {
19679 }
19683 }
19687 else
19688 {
19694 else
19706 }
19707 }
19708 }
19710 /* Expand a floating-point conditional move. Return true if successful. */
19712 bool
19714 {
19722 {
19725 /* Since we've no cmove for sse registers, don't force bad register
19726 allocation just to gain access to it. Deny movcc when the
19727 comparison mode doesn't match the move mode. */
19746 }
19748 /* The floating point conditional move instructions don't directly
19749 support conditions resulting from a signed integer comparison. */
19753 {
19758 }
19765 }
19767 /* Expand a floating-point vector conditional move; a vcond operation
19768 rather than a movcc operation. */
19770 bool
19772 {
19774 rtx cmp;
19779 {
19780 rtx temp;
19782 {
19799 }
19801 OPTAB_DIRECT);
19804 }
19814 }
19816 /* Expand a signed/unsigned integral vector conditional move. */
19818 bool
19820 {
19830 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
19831 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
19840 {
19844 {
19850 }
19853 {
19859 }
19860 }
19869 /* XOP supports all of the comparisons on all 128-bit vector int types. */
19873 ;
19874 else
19875 {
19876 /* Canonicalize the comparison to EQ, GT, GTU. */
19878 {
19895 /* FALLTHRU */
19905 }
19907 /* Only SSE4.1/SSE4.2 supports V2DImode. */
19909 {
19911 {
19913 /* SSE4.1 supports EQ. */
19920 /* SSE4.2 supports GT/GTU. */
19927 }
19928 }
19930 /* Unsigned parallel compare is not supported by the hardware.
19931 Play some tricks to turn this into a signed comparison
19932 against 0. */
19934 {
19938 {
19943 {
19948 {
19955 }
19956 /* Subtract (-(INT MAX) - 1) from both operands to make
19957 them signed. */
19968 }
19975 /* Perform a parallel unsigned saturating subtraction. */
19988 }
19989 }
19990 }
19992 /* Allow the comparison to be done in one mode, but the movcc to
19993 happen in another mode. */
19995 {
19998 }
19999 else
20000 {
20006 }
20011 }
20013 /* Expand a variable vector permutation. */
20015 void
20017 {
20028 /* Number of elements in the vector. */
20034 {
20036 {
20037 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20038 an constant shuffle operand. With a tiny bit of effort we can
20039 use VPERMD instead. A re-interpretation stall for V4DFmode is
20040 unfortunate but there's no avoiding it.
20041 Similarly for V16HImode we don't have instructions for variable
20042 shuffling, while for V32QImode we can use after preparing suitable
20043 masks vpshufb; vpshufb; vpermq; vpor. */
20046 {
20050 }
20051 else
20052 {
20056 }
20059 /* Replicate the low bits of the V4DImode mask into V8SImode:
20060 mask = { A B C D }
20061 t1 = { A A B B C C D D }. */
20069 else
20072 /* Multiply the shuffle indicies by two. */
20074 OPTAB_DIRECT);
20076 /* Add one to the odd shuffle indicies:
20077 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20079 {
20082 }
20086 OPTAB_DIRECT);
20088 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20093 }
20096 {
20098 /* The VPERMD and VPERMPS instructions already properly ignore
20099 the high bits of the shuffle elements. No need for us to
20100 perform an AND ourselves. */
20103 else
20104 {
20110 }
20117 else
20118 {
20124 }
20128 /* By combining the two 128-bit input vectors into one 256-bit
20129 input vector, we can use VPERMD and VPERMPS for the full
20130 two-operand shuffle. */
20162 /* From mask create two adjusted masks, which contain the same
20163 bits as mask in the low 7 bits of each vector element.
20164 The first mask will have the most significant bit clear
20165 if it requests element from the same 128-bit lane
20166 and MSB set if it requests element from the other 128-bit lane.
20167 The second mask will have the opposite values of the MSB,
20168 and additionally will have its 128-bit lanes swapped.
20169 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20170 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20171 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20172 stands for other 12 bytes. */
20173 /* The bit whether element is from the same lane or the other
20174 lane is bit 4, so shift it up by 3 to the MSB position. */
20178 /* Clear MSB bits from the mask just in case it had them set. */
20180 /* After this t1 will have MSB set for elements from other lane. */
20182 /* Clear bits other than MSB. */
20184 /* Or in the lower bits from mask into t3. */
20186 /* And invert MSB bits in t1, so MSB is set for elements from the same
20187 lane. */
20189 /* Swap 128-bit lanes in t3. */
20194 /* And or in the lower bits from mask into t1. */
20197 {
20198 /* Each of these shuffles will put 0s in places where
20199 element from the other 128-bit lane is needed, otherwise
20200 will shuffle in the requested value. */
20203 /* For t3 the 128-bit lanes are swapped again. */
20208 /* And oring both together leads to the result. */
20211 }
20214 /* Similarly to the above one_operand_shuffle code,
20215 just for repeated twice for each operand. merge_two:
20216 code will merge the two results together. */
20238 }
20239 }
20242 {
20243 /* The XOP VPPERM insn supports three inputs. By ignoring the
20244 one_operand_shuffle special case, we avoid creating another
20245 set of constant vectors in memory. */
20248 /* mask = mask & {2*w-1, ...} */
20250 }
20251 else
20252 {
20253 /* mask = mask & {w-1, ...} */
20255 }
20263 /* For non-QImode operations, convert the word permutation control
20264 into a byte permutation control. */
20266 {
20271 /* Convert mask to vector of chars. */
20274 /* Replicate each of the input bytes into byte positions:
20275 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20276 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20277 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20284 else
20287 /* Convert it into the byte positions by doing
20288 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20294 }
20296 /* The actual shuffle operations all operate on V16QImode. */
20302 {
20304 }
20306 {
20308 }
20309 else
20310 {
20314 /* Shuffle the two input vectors independently. */
20320 merge_two:
20321 /* Then merge them together. The key is whether any given control
20322 element contained a bit set that indicates the second word. */
20326 {
20327 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20328 more shuffle to convert the V2DI input mask into a V4SI
20329 input mask. At which point the masking that expand_int_vcond
20330 will work as desired. */
20338 }
20355 }
20356 }
20358 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20359 true if we should do zero extension, else sign extension. HIGH_P is
20360 true if we want the N/2 high elements, else the low elements. */
20362 void
20364 {
20366 rtx tmp;
20369 {
20375 {
20379 else
20382 extract
20388 else
20391 extract
20397 else
20400 extract
20406 else
20412 else
20418 else
20423 }
20426 {
20429 }
20431 {
20432 /* Shift higher 8 bytes to lower 8 bytes. */
20437 }
20438 else
20442 }
20443 else
20444 {
20448 {
20452 else
20458 else
20464 else
20469 }
20473 else
20478 }
20479 }
20481 /* Expand conditional increment or decrement using adb/sbb instructions.
20482 The default case using setcc followed by the conditional move can be
20483 done by generic code. */
20484 bool
20486 {
20488 rtx flags;
20490 rtx compare_op;
20508 {
20511 }
20514 {
20518 reverse_condition_maybe_unordered
20520 else
20522 }
20526 /* Construct either adc or sbb insn. */
20528 {
20530 {
20545 }
20546 }
20547 else
20548 {
20550 {
20565 }
20566 }
20570 }
20573 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20574 but works for floating pointer parameters and nonoffsetable memories.
20575 For pushes, it returns just stack offsets; the values will be saved
20576 in the right order. Maximally three parts are generated. */
20578 static int
20580 {
20585 else
20591 /* Optimize constant pool reference to immediates. This is used by fp
20592 moves, that force all constants to memory to allow combining. */
20594 {
20598 }
20601 {
20602 /* The only non-offsetable memories we handle are pushes. */
20611 }
20614 {
20616 /* Caution: if we looked through a constant pool memory above,
20617 the operand may actually have a different mode now. That's
20618 ok, since we want to pun this all the way back to an integer. */
20622 }
20625 {
20628 else
20629 {
20633 {
20637 }
20639 {
20644 }
20646 {
20647 REAL_VALUE_TYPE r;
20652 {
20659 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
20660 long double may not be 80-bit. */
20669 }
20672 }
20673 else
20675 }
20676 }
20677 else
20678 {
20682 {
20685 {
20689 }
20691 {
20695 }
20697 {
20698 REAL_VALUE_TYPE r;
20704 /* Do not use shift by 32 to avoid warning on 32bit systems. */
20707 = gen_int_mode
20710 DImode);
20711 else
20718 = gen_int_mode
20721 DImode);
20722 else
20724 }
20725 else
20727 }
20728 }
20731 }
20733 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
20734 Return false when normal moves are needed; true when all required
20735 insns have been emitted. Operands 2-4 contain the input values
20736 int the correct order; operands 5-7 contain the output values. */
20738 void
20740 {
20748 /* The DFmode expanders may ask us to move double.
20749 For 64bit target this is single move. By hiding the fact
20750 here we simplify i386.md splitters. */
20752 {
20753 /* Optimize constant pool reference to immediates. This is used by
20754 fp moves, that force all constants to memory to allow combining. */
20761 {
20764 }
20765 else
20770 }
20772 /* The only non-offsettable memory we handle is push. */
20775 else
20782 /* When emitting push, take care for source operands on the stack. */
20785 {
20788 /* Compensate for the stack decrement by 4. */
20793 /* src_base refers to the stack pointer and is
20794 automatically decreased by emitted push. */
20798 }
20800 /* We need to do copy in the right order in case an address register
20801 of the source overlaps the destination. */
20803 {
20804 rtx tmp;
20807 {
20811 collisions++;
20812 }
20814 /* Collision in the middle part can be handled by reordering. */
20816 {
20819 }
20823 {
20825 {
20828 }
20829 else
20830 {
20833 }
20834 }
20836 /* If there are more collisions, we can't handle it by reordering.
20837 Do an lea to the last part and use only one colliding move. */
20839 {
20840 rtx base;
20846 /* Handle the case when the last part isn't valid for lea.
20847 Happens in 64-bit mode storing the 12-byte XFmode. */
20854 {
20857 }
20858 }
20859 }
20862 {
20864 {
20866 {
20871 }
20873 {
20876 }
20877 }
20878 else
20879 {
20880 /* In 64bit mode we don't have 32bit push available. In case this is
20881 register, it is OK - we will just use larger counterpart. We also
20882 retype memory - these comes from attempt to avoid REX prefix on
20883 moving of second half of TFmode value. */
20885 {
20887 {
20898 }
20902 }
20903 }
20907 }
20909 /* Choose correct order to not overwrite the source before it is copied. */
20919 {
20921 {
20924 }
20925 }
20926 else
20927 {
20929 {
20932 }
20933 }
20935 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
20937 {
20946 }
20952 }
20954 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
20955 left shift by a constant, either using a single shift or
20956 a sequence of add instructions. */
20958 static void
20960 {
20966 {
20970 }
20971 else
20972 {
20975 }
20976 }
20978 void
20980 {
20989 {
20994 {
21000 }
21001 else
21002 {
21010 }
21012 }
21019 {
21020 /* Assuming we've chosen a QImode capable registers, then 1 << N
21021 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21023 {
21039 }
21041 /* Otherwise, we can get the same results by manually performing
21042 a bit extract operation on bit 5/6, and then performing the two
21043 shifts. The two methods of getting 0/1 into low/high are exactly
21044 the same size. Avoiding the shift in the bit extract case helps
21045 pentium4 a bit; no one else seems to care much either way. */
21046 else
21047 {
21052 HOST_WIDE_INT bits;
21053 rtx x;
21056 {
21062 }
21063 else
21064 {
21070 }
21074 else
21082 }
21087 }
21090 {
21091 /* For -1 << N, we can avoid the shld instruction, because we
21092 know that we're shifting 0...31/63 ones into a -1. */
21096 else
21098 }
21099 else
21100 {
21108 }
21113 {
21119 }
21120 else
21121 {
21126 }
21127 }
21129 void
21131 {
21141 {
21146 {
21152 }
21154 {
21163 }
21164 else
21165 {
21173 }
21174 }
21175 else
21176 {
21188 {
21196 scratch));
21197 }
21198 else
21199 {
21204 }
21205 }
21206 }
21208 void
21210 {
21220 {
21225 {
21232 }
21233 else
21234 {
21242 }
21243 }
21244 else
21245 {
21257 {
21263 scratch));
21264 }
21265 else
21266 {
21271 }
21272 }
21273 }
21275 /* Predict just emitted jump instruction to be taken with probability PROB. */
21276 static void
21278 {
21282 }
21284 /* Helper function for the string operations below. Dest VARIABLE whether
21285 it is aligned to VALUE bytes. If true, jump to the label. */
21286 static rtx
21288 {
21293 else
21299 else
21302 }
21304 /* Adjust COUNTER by the VALUE. */
21305 static void
21307 {
21312 }
21314 /* Zero extend possibly SImode EXP to Pmode register. */
21315 rtx
21317 {
21321 }
21323 /* Divide COUNTREG by SCALE. */
21324 static rtx
21326 {
21327 rtx sc;
21339 }
21341 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21342 DImode for constant loop counts. */
21344 static enum machine_mode
21346 {
21354 }
21356 /* When SRCPTR is non-NULL, output simple loop to move memory
21357 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21358 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21359 equivalent loop to set memory by VALUE (supposed to be in MODE).
21361 The size is rounded down to whole number of chunk size moved at once.
21362 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21365 static void
21370 {
21375 rtx size;
21376 rtx x_addr;
21377 rtx y_addr;
21386 /* Those two should combine. */
21388 {
21392 }
21402 {
21406 /* When unrolling for chips that reorder memory reads and writes,
21407 we can save registers by using single temporary.
21408 Also using 4 temporaries is overkill in 32bit mode. */
21410 {
21412 {
21414 {
21415 destmem =
21417 srcmem =
21419 }
21421 }
21422 }
21423 else
21424 {
21428 {
21431 {
21432 srcmem =
21434 }
21436 }
21438 {
21440 {
21441 destmem =
21443 }
21445 }
21446 }
21447 }
21448 else
21450 {
21452 destmem =
21455 }
21465 {
21471 else
21473 }
21474 else
21482 {
21487 }
21489 }
21491 /* Output "rep; mov" instruction.
21492 Arguments have same meaning as for previous function */
21493 static void
21496 rtx count,
21498 {
21499 rtx destexp;
21500 rtx srcexp;
21501 rtx countreg;
21502 HOST_WIDE_INT rounded_count;
21504 /* If the size is known, it is shorter to use rep movs. */
21515 {
21522 }
21523 else
21524 {
21527 }
21529 {
21536 }
21537 else
21538 {
21543 }
21546 }
21548 /* Output "rep; stos" instruction.
21549 Arguments have same meaning as for previous function */
21550 static void
21553 rtx orig_value)
21554 {
21555 rtx destexp;
21556 rtx countreg;
21557 HOST_WIDE_INT rounded_count;
21564 {
21568 }
21569 else
21572 {
21577 }
21581 }
21583 static void
21586 {
21590 }
21592 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21593 static void
21596 {
21599 {
21604 {
21606 {
21609 }
21610 else
21613 }
21615 {
21618 else
21619 {
21622 }
21624 }
21626 {
21629 }
21631 {
21634 }
21636 {
21639 }
21641 }
21643 {
21649 }
21651 /* When there are stringops, we can cheaply increase dest and src pointers.
21652 Otherwise we save code size by maintaining offset (zero is readily
21653 available from preceding rep operation) and using x86 addressing modes.
21654 */
21656 {
21658 {
21665 }
21667 {
21674 }
21676 {
21683 }
21684 }
21685 else
21686 {
21688 rtx tmp;
21691 {
21702 }
21704 {
21717 }
21719 {
21728 }
21729 }
21730 }
21732 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
21733 static void
21736 {
21737 count =
21743 }
21745 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
21746 static void
21748 {
21749 rtx dest;
21752 {
21757 {
21759 {
21764 }
21765 else
21768 }
21770 {
21772 {
21775 }
21776 else
21777 {
21782 }
21784 }
21786 {
21790 }
21792 {
21796 }
21798 {
21802 }
21804 }
21806 {
21809 }
21811 {
21814 {
21818 }
21819 else
21820 {
21826 }
21829 }
21831 {
21834 {
21837 }
21838 else
21839 {
21843 }
21846 }
21848 {
21854 }
21856 {
21862 }
21864 {
21870 }
21871 }
21873 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
21874 DESIRED_ALIGNMENT. */
21875 static void
21879 {
21881 {
21889 }
21891 {
21899 }
21901 {
21909 }
21911 }
21913 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
21914 ALIGN_BYTES is how many bytes need to be copied. */
21915 static rtx
21918 {
21927 {
21932 }
21934 {
21945 }
21947 {
21953 {
21961 }
21964 }
21970 {
21982 }
21989 }
21991 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
21992 DESIRED_ALIGNMENT. */
21993 static void
21996 {
21998 {
22005 }
22007 {
22014 }
22016 {
22023 }
22025 }
22027 /* Set enough from DST to align DST known to by aligned by ALIGN to
22028 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22029 static rtx
22032 {
22036 {
22041 }
22043 {
22050 }
22052 {
22059 }
22066 }
22068 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22069 static enum stringop_alg
22072 {
22075 /* Algorithms using the rep prefix want at least edi and ecx;
22076 additionally, memset wants eax and memcpy wants esi. Don't
22077 consider such algorithms if the user has appropriated those
22078 registers for their own purposes. */
22080 || (memset
22083 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22084 || (alg != rep_prefix_1_byte \
22085 && alg != rep_prefix_4_byte \
22086 && alg != rep_prefix_8_byte))
22089 /* Even if the string operation call is cold, we still might spend a lot
22090 of time processing large blocks. */
22095 else
22103 else
22107 /* rep; movq or rep; movl is the smallest variant. */
22109 {
22112 else
22114 }
22115 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22116 */
22120 {
22124 {
22125 /* We get here if the algorithms that were not libcall-based
22126 were rep-prefix based and we are unable to use rep prefixes
22127 based on global register usage. Break out of the loop and
22128 use the heuristic below. */
22132 {
22137 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22138 last non-libcall inline algorithm. */
22140 {
22141 /* When the current size is best to be copied by a libcall,
22142 but we are still forced to inline, run the heuristic below
22143 that will pick code for medium sized blocks. */
22147 }
22150 }
22151 }
22153 }
22154 /* When asked to inline the call anyway, try to pick meaningful choice.
22155 We look for maximal size of block that is faster to copy by hand and
22156 take blocks of at most of that size guessing that average size will
22157 be roughly half of the block.
22159 If this turns out to be bad, we might simply specify the preferred
22160 choice in ix86_costs. */
22163 {
22170 {
22177 }
22178 /* If there aren't any usable algorithms, then recursing on
22179 smaller sizes isn't going to find anything. Just return the
22180 simple byte-at-a-time copy loop. */
22182 {
22183 /* Pick something reasonable. */
22187 }
22196 }
22198 #undef ALG_USABLE_P
22199 }
22201 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22202 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22203 static int
22207 {
22210 {
22221 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22222 copying whole cacheline at once. */
22225 else
22229 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22230 copying whole cacheline at once. */
22233 else
22241 }
22250 }
22252 /* Return the smallest power of 2 greater than VAL. */
22253 static int
22255 {
22260 }
22262 /* Expand string move (memcpy) operation. Use i386 string operations
22263 when profitable. expand_setmem contains similar code. The code
22264 depends upon architecture, block size and alignment, but always has
22265 the same overall structure:
22267 1) Prologue guard: Conditional that jumps up to epilogues for small
22268 blocks that can be handled by epilogue alone. This is faster
22269 but also needed for correctness, since prologue assume the block
22270 is larger than the desired alignment.
22272 Optional dynamic check for size and libcall for large
22273 blocks is emitted here too, with -minline-stringops-dynamically.
22275 2) Prologue: copy first few bytes in order to get destination
22276 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22277 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22278 copied. We emit either a jump tree on power of two sized
22279 blocks, or a byte loop.
22281 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22282 with specified algorithm.
22284 4) Epilogue: code copying tail of the block that is too small to be
22285 handled by main body (or up to size guarded by prologue guard). */
22287 bool
22290 {
22291 rtx destreg;
22292 rtx srcreg;
22294 rtx tmp;
22307 /* i386 can do misaligned access on reasonably increased cost. */
22311 /* ALIGN is the minimum of destination and source alignment, but we care here
22312 just about destination alignment. */
22321 /* Make sure we don't need to care about overflow later on. */
22325 /* Step 0: Decide on preferred algorithm, desired alignment and
22326 size of chunks to be copied by main loop. */
22342 {
22367 }
22371 /* Step 1: Prologue guard. */
22373 /* Alignment code needs count to be in register. */
22375 {
22378 {
22379 align_bytes
22383 else
22385 }
22388 }
22391 /* Ensure that alignment prologue won't copy past end of block. */
22393 {
22395 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22396 Make sure it is power of 2. */
22400 {
22402 {
22403 /* If main algorithm works on QImode, no epilogue is needed.
22404 For small sizes just don't align anything. */
22407 else
22409 }
22410 }
22411 else
22412 {
22419 else
22421 }
22422 }
22424 /* Emit code to decide on runtime whether library call or inline should be
22425 used. */
22427 {
22429 {
22431 {
22435 }
22436 }
22437 else
22438 {
22447 }
22448 }
22450 /* Step 2: Alignment prologue. */
22453 {
22455 {
22456 /* Except for the first move in epilogue, we no longer know
22457 constant offset in aliasing info. It don't seems to worth
22458 the pain to maintain it for the first move, so throw away
22459 the info early. */
22463 desired_align);
22464 }
22465 else
22466 {
22467 /* If we know how many bytes need to be stored before dst is
22468 sufficiently aligned, maintain aliasing info accurately. */
22474 }
22480 {
22481 /* It is possible that we copied enough so the main loop will not
22482 execute. */
22492 else
22494 }
22495 }
22497 {
22502 }
22506 /* Step 3: Main loop. */
22509 {
22522 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22523 registers for 4 temporaries anyway. */
22526 expected_size);
22530 DImode);
22534 SImode);
22538 QImode);
22540 }
22541 /* Adjust properly the offset of src and dest memory for aliasing. */
22543 {
22548 }
22549 else
22550 {
22553 }
22555 /* Step 4: Epilogue to copy the remaining bytes. */
22556 epilogue:
22558 {
22559 /* When the main loop is done, COUNT_EXP might hold original count,
22560 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22561 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22562 bytes. Compensate if needed. */
22565 {
22566 tmp =
22569 OPTAB_DIRECT);
22572 }
22575 }
22579 epilogue_size_needed);
22583 }
22585 /* Helper function for memcpy. For QImode value 0xXY produce
22586 0xXYXYXYXY of wide specified by MODE. This is essentially
22587 a * 0x10101010, but we can do slightly better than
22588 synth_mult by unwinding the sequence by hand on CPUs with
22589 slow multiply. */
22590 static rtx
22592 {
22594 rtx tmp;
22601 {
22609 }
22618 nops--;
22623 {
22627 OPTAB_DIRECT);
22628 }
22629 else
22630 {
22636 else
22638 else
22639 {
22642 reg =
22644 }
22654 }
22655 }
22657 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
22658 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
22659 alignment from ALIGN to DESIRED_ALIGN. */
22660 static rtx
22662 {
22663 rtx promoted_val;
22672 else
22676 }
22678 /* Expand string clear operation (bzero). Use i386 string operations when
22679 profitable. See expand_movmem comment for explanation of individual
22680 steps performed. */
22681 bool
22684 {
22685 rtx destreg;
22687 rtx tmp;
22702 /* i386 can do misaligned access on reasonably increased cost. */
22711 /* Make sure we don't need to care about overflow later on. */
22715 /* Step 0: Decide on preferred algorithm, desired alignment and
22716 size of chunks to be copied by main loop. */
22731 {
22756 }
22759 /* Step 1: Prologue guard. */
22761 /* Alignment code needs count to be in register. */
22763 {
22766 {
22767 align_bytes
22771 else
22773 }
22775 {
22780 }
22781 }
22782 /* Do the cheap promotion to allow better CSE across the
22783 main loop and epilogue (ie one load of the big constant in the
22784 front of all code. */
22788 /* Ensure that alignment prologue won't copy past end of block. */
22790 {
22792 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
22793 Make sure it is power of 2. */
22796 /* To improve performance of small blocks, we jump around the VAL
22797 promoting mode. This mean that if the promoted VAL is not constant,
22798 we might not use it in the epilogue and have to use byte
22799 loop variant. */
22803 {
22805 {
22806 /* If main algorithm works on QImode, no epilogue is needed.
22807 For small sizes just don't align anything. */
22810 else
22812 }
22813 }
22814 else
22815 {
22822 else
22824 }
22825 }
22827 {
22836 }
22838 /* Step 2: Alignment prologue. */
22840 /* Do the expensive promotion once we branched off the small blocks. */
22847 {
22849 {
22850 /* Except for the first move in epilogue, we no longer know
22851 constant offset in aliasing info. It don't seems to worth
22852 the pain to maintain it for the first move, so throw away
22853 the info early. */
22856 desired_align);
22857 }
22858 else
22859 {
22860 /* If we know how many bytes need to be stored before dst is
22861 sufficiently aligned, maintain aliasing info accurately. */
22867 }
22873 {
22874 /* It is possible that we copied enough so the main loop will not
22875 execute. */
22885 else
22887 }
22888 }
22890 {
22896 }
22900 /* Step 3: Main loop. */
22903 {
22931 }
22932 /* Adjust properly the offset of src and dest memory for aliasing. */
22936 else
22939 /* Step 4: Epilogue to copy the remaining bytes. */
22942 {
22943 /* When the main loop is done, COUNT_EXP might hold original count,
22944 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22945 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22946 bytes. Compensate if needed. */
22949 {
22950 tmp =
22953 OPTAB_DIRECT);
22956 }
22959 }
22960 epilogue:
22962 {
22965 epilogue_size_needed);
22966 else
22968 epilogue_size_needed);
22969 }
22973 }
22975 /* Expand the appropriate insns for doing strlen if not just doing
22976 repnz; scasb
22978 out = result, initialized with the start address
22979 align_rtx = alignment of the address.
22980 scratch = scratch register, initialized with the startaddress when
22981 not aligned, otherwise undefined
22983 This is just the body. It needs the initializations mentioned above and
22984 some address computing at the end. These things are done in i386.md. */
22986 static void
22988 {
22990 rtx tmp;
22995 rtx mem;
22998 rtx cmp;
23004 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23006 /* Is there a known alignment and is it less than 4? */
23008 {
23011 /* Is there a known alignment and is it not 2? */
23013 {
23017 /* Leave just the 3 lower bits. */
23027 }
23028 else
23029 {
23030 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23031 check if is aligned to 4 - byte. */
23038 }
23042 /* Now compare the bytes. */
23044 /* Compare the first n unaligned byte on a byte per byte basis. */
23048 /* Increment the address. */
23051 /* Not needed with an alignment of 2 */
23053 {
23057 end_0_label);
23062 }
23065 end_0_label);
23068 }
23070 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23071 align this loop. It gives only huge programs, but does not help to
23072 speed up. */
23079 /* This formula yields a nonzero result iff one of the bytes is zero.
23080 This saves three branches inside loop and many cycles. */
23088 align_4_label);
23091 {
23097 /* If zero is not in the first two bytes, move two bytes forward. */
23103 reg,
23104 tmpreg)));
23105 /* Emit lea manually to avoid clobbering of flags. */
23113 reg2,
23114 out)));
23115 }
23116 else
23117 {
23119 /* Is zero in the first two bytes? */
23126 pc_rtx);
23130 /* Not in the first two. Move two bytes forward. */
23136 }
23138 /* Avoid branch in fixing the byte. */
23146 }
23148 /* Expand strlen. */
23150 bool
23152 {
23155 /* The generic case of strlen expander is long. Avoid it's
23156 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23159 && !TARGET_INLINE_ALL_STRINGOPS
23169 {
23170 /* Well it seems that some optimizer does not combine a call like
23171 foo(strlen(bar), strlen(bar));
23172 when the move and the subtraction is done here. It does calculate
23173 the length just once when these instructions are done inside of
23174 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23175 often used and I use one fewer register for the lifetime of
23176 output_strlen_unroll() this is better. */
23182 /* strlensi_unroll_1 returns the address of the zero at the end of
23183 the string, like memchr(), so compute the length by subtracting
23184 the start address. */
23186 }
23187 else
23188 {
23189 rtx unspec;
23191 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23204 /* If .md starts supporting :P, this can be done in .md. */
23210 }
23212 }
23214 /* For given symbol (function) construct code to compute address of it's PLT
23215 entry in large x86-64 PIC model. */
23216 static rtx
23218 {
23231 }
23233 rtx
23235 rtx callarg2,
23237 {
23238 /* We need to represent that SI and DI registers are clobbered
23239 by SYSV calls. */
23245 };
23255 {
23256 #if TARGET_MACHO
23259 #endif
23260 }
23261 else
23262 {
23263 /* Static functions and indirect calls don't need the pic register. */
23268 }
23271 {
23275 }
23285 {
23290 }
23299 {
23303 }
23307 {
23311 UNSPEC_MS_TO_SYSV_CALL);
23320 }
23329 }
23331 /* Output the assembly for a call instruction. */
23335 {
23341 {
23344 /* SEH epilogue detection requires the indirect branch case
23345 to include REX.W. */
23348 else
23353 }
23355 /* SEH unwinding can require an extra nop to be emitted in several
23356 circumstances. Determine if we have one of those. */
23358 {
23359 rtx i;
23362 {
23363 /* If we get to another real insn, we don't need the nop. */
23367 /* If we get to the epilogue note, prevent a catch region from
23368 being adjacent to the standard epilogue sequence. If non-
23369 call-exceptions, we'll have done this during epilogue emission. */
23371 && !flag_non_call_exceptions
23373 {
23376 }
23377 }
23379 /* If we didn't find a real insn following the call, prevent the
23380 unwinder from looking into the next function. */
23383 }
23387 else
23396 }
23397 \f
23398 /* Clear stack slot assignments remembered from previous functions.
23399 This is called from INIT_EXPANDERS once before RTL is emitted for each
23400 function. */
23404 {
23413 }
23415 /* Return a MEM corresponding to a stack slot with mode MODE.
23416 Allocate a new slot if necessary.
23418 The RTL for a function can have several slots available: N is
23419 which slot to use. */
23421 rtx
23423 {
23440 }
23442 static void
23444 {
23450 }
23451 \f
23452 /* Calculate the length of the memory address in the instruction encoding.
23453 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23454 or other prefixes. We never generate addr32 prefix for LEA insn. */
23456 int
23458 {
23475 /* If this is not LEA instruction, add the length of addr32 prefix. */
23480 len++;
23494 /* Rule of thumb:
23495 - esp as the base always wants an index,
23496 - ebp as the base always wants a displacement,
23497 - r12 as the base always wants an index,
23498 - r13 as the base always wants a displacement. */
23500 /* Register Indirect. */
23502 {
23503 /* esp (for its index) and ebp (for its displacement) need
23504 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23505 code. */
23512 len++;
23513 }
23515 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23516 is not disp32, but disp32(%rip), so for disp32
23517 SIB byte is needed, unless print_operand_address
23518 optimizes it into disp32(%rip) or (%rip) is implied
23519 by UNSPEC. */
23521 {
23524 {
23540 len++;
23541 }
23542 }
23543 else
23544 {
23545 /* Find the length of the displacement constant. */
23547 {
23550 else
23552 }
23553 /* ebp always wants a displacement. Similarly r13. */
23555 len++;
23557 /* An index requires the two-byte modrm form.... */
23559 /* ...like esp (or r12), which always wants an index. */
23563 len++;
23564 }
23567 }
23569 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23570 is set, expect that insn have 8bit immediate alternative. */
23571 int
23573 {
23579 {
23584 {
23587 {
23599 }
23601 {
23604 }
23605 }
23607 {
23617 /* Immediates for DImode instructions are encoded
23618 as 32bit sign extended values. */
23624 }
23625 }
23627 }
23629 /* Compute default value for "length_address" attribute. */
23630 int
23632 {
23636 {
23647 }
23652 {
23655 {
23660 constraints++;
23663 ;
23664 /* Skip ignored operands. */
23667 }
23669 }
23671 }
23673 /* Compute default value for "length_vex" attribute. It includes
23674 2 or 3 byte VEX prefix and 1 opcode byte. */
23676 int
23678 {
23681 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
23682 byte VEX prefix. */
23686 /* We can always use 2 byte VEX prefix in 32bit. */
23694 {
23695 /* REX.W bit uses 3 byte VEX prefix. */
23699 }
23700 else
23701 {
23702 /* REX.X or REX.B bits use 3 byte VEX prefix. */
23706 }
23709 }
23710 \f
23711 /* Return the maximum number of instructions a cpu can issue. */
23713 static int
23715 {
23717 {
23743 }
23744 }
23746 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
23747 by DEP_INSN and nothing set by DEP_INSN. */
23749 static bool
23751 {
23754 /* Simplify the test for uninteresting insns. */
23762 {
23765 }
23770 {
23773 }
23774 else
23780 /* This test is true if the dependent insn reads the flags but
23781 not any other potentially set register. */
23789 }
23791 /* Return true iff USE_INSN has a memory address with operands set by
23792 SET_INSN. */
23794 bool
23796 {
23801 {
23804 }
23806 }
23808 static int
23810 {
23816 /* Anti and output dependencies have zero cost on all CPUs. */
23822 /* If we can't recognize the insns, we can't really do anything. */
23830 {
23832 /* Address Generation Interlock adds a cycle of latency. */
23834 {
23845 }
23849 /* ??? Compares pair with jump/setcc. */
23853 /* Floating point stores require value to be ready one cycle earlier. */
23863 /* INT->FP conversion is expensive. */
23867 /* There is one cycle extra latency between an FP op and a store. */
23875 /* Show ability of reorder buffer to hide latency of load by executing
23876 in parallel with previous instruction in case
23877 previous instruction is not needed to compute the address. */
23880 {
23881 /* Claim moves to take one cycle, as core can issue one load
23882 at time and the next load can start cycle later. */
23887 cost--;
23888 }
23894 /* The esp dependency is resolved before the instruction is really
23895 finished. */
23900 /* INT->FP conversion is expensive. */
23904 /* Show ability of reorder buffer to hide latency of load by executing
23905 in parallel with previous instruction in case
23906 previous instruction is not needed to compute the address. */
23909 {
23910 /* Claim moves to take one cycle, as core can issue one load
23911 at time and the next load can start cycle later. */
23917 else
23919 }
23934 /* Show ability of reorder buffer to hide latency of load by executing
23935 in parallel with previous instruction in case
23936 previous instruction is not needed to compute the address. */
23939 {
23943 /* Because of the difference between the length of integer and
23944 floating unit pipeline preparation stages, the memory operands
23945 for floating point are cheaper.
23947 ??? For Athlon it the difference is most probably 2. */
23950 else
23955 else
23957 }
23961 }
23964 }
23966 /* How many alternative schedules to try. This should be as wide as the
23967 scheduling freedom in the DFA, but no wider. Making this value too
23968 large results extra work for the scheduler. */
23970 static int
23972 {
23974 {
23987 /* Generally, we want haifa-sched:max_issue() to look ahead as far
23988 as many instructions can be executed on a cycle, i.e.,
23989 issue_rate. I wonder why tuning for many CPUs does not do this. */
23992 /* Don't use lookahead for pre-reload schedule to save compile time. */
23997 }
23998 }
24000 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24001 execution. It is applied if
24002 (1) IMUL instruction is on the top of list;
24003 (2) There exists the only producer of independent IMUL instruction in
24004 ready list;
24005 (3) Put found producer on the top of ready list.
24006 Returns issue rate. */
24008 static int
24011 {
24016 sd_iterator_def sd_it;
24017 dep_t dep;
24020 /* Set up issue rate. */
24023 /* Do reodering for Atom only. */
24026 /* Do not perform ready list reodering for pre-reload schedule pass. */
24029 /* Nothing to do if ready list contains only 1 instruction. */
24033 /* Check that IMUL instruction is on the top of ready list. */
24046 /* Search for producer of independent IMUL instruction. */
24048 {
24052 /* Skip IMUL instruction. */
24062 {
24063 rtx con;
24074 {
24075 sd_iterator_def sd_it1;
24076 dep_t dep1;
24077 /* Check if there is no other dependee for IMUL. */
24080 {
24081 rtx pro;
24087 }
24090 }
24091 }
24094 }
24102 /* Put IMUL producer (ready[index]) at the top of ready list. */
24109 }
24111 static bool
24114 /* Returns true if lhs of insn is HW function argument register and set up
24115 is_spilled to true if it is likely spilled HW register. */
24116 static bool
24118 {
24119 rtx dst;
24123 /* Call instructions are not movable, ignore it. */
24134 {
24135 /* Is it likely spilled HW register? */
24140 }
24142 }
24144 /* Add output dependencies for chain of function adjacent arguments if only
24145 there is a move to likely spilled HW register. Return first argument
24146 if at least one dependence was added or NULL otherwise. */
24147 static rtx
24149 {
24150 rtx insn;
24157 /* Find nearest to call argument passing instruction. */
24159 {
24168 }
24172 {
24179 {
24182 }
24184 {
24185 /* Add output depdendence between two function arguments if chain
24186 of output arguments contains likely spilled HW registers. */
24190 }
24191 else
24193 }
24197 }
24199 /* Add output or anti dependency from insn to first_arg to restrict its code
24200 motion. */
24201 static void
24203 {
24204 rtx set;
24205 rtx tmp;
24212 {
24213 /* Add output dependency to the first function argument. */
24216 }
24217 /* Add anti dependency. */
24219 }
24221 /* Avoid cross block motion of function argument through adding dependency
24222 from the first non-jump instruction in bb. */
24223 static void
24225 {
24229 {
24231 {
24234 {
24237 }
24238 }
24242 }
24243 }
24245 /* Hook for pre-reload schedule - avoid motion of function arguments
24246 passed in likely spilled HW registers. */
24247 static void
24249 {
24250 rtx insn;
24258 {
24261 {
24262 /* Add dependee for first argument to predecessors if only
24263 region contains more than one block. */
24267 /* Skip trivial regions and region head blocks that can have
24268 predecessors outside of region. */
24270 {
24271 edge e;
24272 edge_iterator ei;
24273 /* Assume that region is SCC, i.e. all immediate predecessors
24274 of non-head block are in the same region. */
24276 {
24277 /* Avoid creating of loop-carried dependencies through
24278 using topological odering in region. */
24281 }
24282 }
24286 }
24287 }
24290 }
24292 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24293 HW registers to maximum, to schedule them at soon as possible. These are
24294 moves from function argument registers at the top of the function entry
24295 and moves from function return value registers after call. */
24296 static int
24298 {
24299 rtx set;
24309 {
24316 }
24319 }
24321 /* Model decoder of Core 2/i7.
24322 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24323 track the instruction fetch block boundaries and make sure that long
24324 (9+ bytes) instructions are assigned to D0. */
24326 /* Maximum length of an insn that can be handled by
24327 a secondary decoder unit. '8' for Core 2/i7. */
24330 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24331 '16' for Core 2/i7. */
24334 /* Maximum number of instructions decoder can handle per cycle.
24335 '6' for Core 2/i7. */
24339 ix86_first_cycle_multipass_data_t;
24341 const_ix86_first_cycle_multipass_data_t;
24343 /* A variable to store target state across calls to max_issue within
24344 one cycle. */
24348 /* Initialize DATA. */
24349 static void
24351 {
24352 ix86_first_cycle_multipass_data_t data
24359 }
24361 /* Advancing the cycle; reset ifetch block counts. */
24362 static void
24364 {
24371 }
24375 /* Filter out insns from ready_try that the core will not be able to issue
24376 on current cycle due to decoder. */
24377 static void
24378 core2i7_first_cycle_multipass_filter_ready_try
24381 {
24383 {
24384 rtx insn;
24394 (!first_cycle_insn_p
24396 /* ... or it would not fit into the ifetch block ... */
24398 /* ... or the decoder is full already ... */
24400 /* ... mask the insn out. */
24401 {
24406 }
24407 }
24408 }
24410 /* Prepare for a new round of multipass lookahead scheduling. */
24411 static void
24414 {
24415 ix86_first_cycle_multipass_data_t data
24417 const_ix86_first_cycle_multipass_data_t prev_data
24420 /* Restore the state from the end of the previous round. */
24424 /* Filter instructions that cannot be issued on current cycle due to
24425 decoder restrictions. */
24427 first_cycle_insn_p);
24428 }
24430 /* INSN is being issued in current solution. Account for its impact on
24431 the decoder model. */
24432 static void
24435 {
24436 ix86_first_cycle_multipass_data_t data
24438 const_ix86_first_cycle_multipass_data_t prev_data
24448 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24450 {
24453 }
24455 {
24459 }
24462 /* Filter out insns from ready_try that the core will not be able to issue
24463 on current cycle due to decoder. */
24466 }
24468 /* Revert the effect on ready_try. */
24469 static void
24473 {
24474 const_ix86_first_cycle_multipass_data_t data
24477 sbitmap_iterator sbi;
24481 {
24483 }
24484 }
24486 /* Save the result of multipass lookahead scheduling for the next round. */
24487 static void
24489 {
24490 const_ix86_first_cycle_multipass_data_t data
24492 ix86_first_cycle_multipass_data_t next_data
24496 {
24499 }
24500 }
24502 /* Deallocate target data. */
24503 static void
24505 {
24506 ix86_first_cycle_multipass_data_t data
24510 {
24514 }
24515 }
24517 /* Prepare for scheduling pass. */
24518 static void
24522 {
24523 /* Install scheduling hooks for current CPU. Some of these hooks are used
24524 in time-critical parts of the scheduler, so we only set them up when
24525 they are actually used. */
24527 {
24532 /* Do not perform multipass scheduling for pre-reload schedule
24533 to save compile time. */
24535 {
24551 /* Set decoder parameters. */
24556 }
24557 /* ... Fall through ... */
24567 }
24568 }
24570 \f
24571 /* Compute the alignment given to a constant that is being placed in memory.
24572 EXP is the constant and ALIGN is the alignment that the object would
24573 ordinarily have.
24574 The value of this function is used instead of that alignment to align
24575 the object. */
24577 int
24579 {
24582 {
24587 }
24593 }
24595 /* Compute the alignment for a static variable.
24596 TYPE is the data type, and ALIGN is the alignment that
24597 the object would ordinarily have. The value of this function is used
24598 instead of that alignment to align the object. */
24600 int
24602 {
24613 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24614 to 16byte boundary. */
24616 {
24623 }
24626 {
24631 }
24633 {
24640 }
24645 {
24650 }
24653 {
24658 }
24661 }
24663 /* Compute the alignment for a local variable or a stack slot. EXP is
24664 the data type or decl itself, MODE is the widest mode available and
24665 ALIGN is the alignment that the object would ordinarily have. The
24666 value of this macro is used instead of that alignment to align the
24667 object. */
24669 unsigned int
24672 {
24676 {
24679 }
24680 else
24681 {
24684 }
24686 /* Don't do dynamic stack realignment for long long objects with
24687 -mpreferred-stack-boundary=2. */
24696 /* If TYPE is NULL, we are allocating a stack slot for caller-save
24697 register in MODE. We will return the largest alignment of XF
24698 and DF. */
24700 {
24704 }
24706 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24707 to 16byte boundary. Exact wording is:
24709 An array uses the same alignment as its elements, except that a local or
24710 global array variable of length at least 16 bytes or
24711 a C99 variable-length array variable always has alignment of at least 16 bytes.
24713 This was added to allow use of aligned SSE instructions at arrays. This
24714 rule is meant for static storage (where compiler can not do the analysis
24715 by itself). We follow it for automatic variables only when convenient.
24716 We fully control everything in the function compiled and functions from
24717 other unit can not rely on the alignment.
24719 Exclude va_list type. It is the common case of local array where
24720 we can not benefit from the alignment. */
24723 {
24733 }
24735 {
24740 }
24742 {
24748 }
24753 {
24758 }
24761 {
24767 }
24769 }
24771 /* Compute the minimum required alignment for dynamic stack realignment
24772 purposes for a local variable, parameter or a stack slot. EXP is
24773 the data type or decl itself, MODE is its mode and ALIGN is the
24774 alignment that the object would ordinarily have. */
24776 unsigned int
24779 {
24783 {
24786 }
24787 else
24788 {
24791 }
24796 /* Don't do dynamic stack realignment for long long objects with
24797 -mpreferred-stack-boundary=2. */
24804 }
24805 \f
24806 /* Find a location for the static chain incoming to a nested function.
24807 This is a register, unless all free registers are used by arguments. */
24809 static rtx
24811 {
24818 {
24819 /* We always use R10 in 64-bit mode. */
24821 }
24822 else
24823 {
24824 tree fntype;
24827 /* By default in 32-bit mode we use ECX to pass the static chain. */
24833 {
24834 /* Fastcall functions use ecx/edx for arguments, which leaves
24835 us with EAX for the static chain.
24836 Thiscall functions use ecx for arguments, which also
24837 leaves us with EAX for the static chain. */
24839 }
24841 {
24842 /* For regparm 3, we have no free call-clobbered registers in
24843 which to store the static chain. In order to implement this,
24844 we have the trampoline push the static chain to the stack.
24845 However, we can't push a value below the return address when
24846 we call the nested function directly, so we have to use an
24847 alternate entry point. For this we use ESI, and have the
24848 alternate entry point push ESI, so that things appear the
24849 same once we're executing the nested function. */
24851 {
24857 }
24859 }
24860 }
24863 }
24865 /* Emit RTL insns to initialize the variable parts of a trampoline.
24866 FNDECL is the decl of the target address; M_TRAMP is a MEM for
24867 the trampoline, and CHAIN_VALUE is an RTX for the static chain
24868 to be passed to the target function. */
24870 static void
24872 {
24880 {
24883 /* Load the function address to r11. Try to load address using
24884 the shorter movl instead of movabs. We may want to support
24885 movq for kernel mode, but kernel does not use trampolines at
24886 the moment. FNADDR is a 32bit address and may not be in
24887 DImode when ptr_mode == SImode. Always use movl in this
24888 case. */
24891 {
24900 }
24901 else
24902 {
24909 }
24911 /* Load static chain using movabs to r10. Use the shorter movl
24912 instead of movabs when ptr_mode == SImode. */
24914 {
24917 }
24918 else
24919 {
24922 }
24931 /* Jump to r11; the last (unused) byte is a nop, only there to
24932 pad the write out to a single 32-bit store. */
24936 }
24937 else
24938 {
24941 /* Depending on the static chain location, either load a register
24942 with a constant, or push the constant to the stack. All of the
24943 instructions are the same size. */
24946 {
24948 {
24955 }
24956 }
24957 else
24972 /* Compute offset from the end of the jmp to the target function.
24973 In the case in which the trampoline stores the static chain on
24974 the stack, we need to skip the first insn which pushes the
24975 (call-saved) register static chain; this push is 1 byte. */
24982 }
24986 #ifdef HAVE_ENABLE_EXECUTE_STACK
24987 #ifdef CHECK_EXECUTE_STACK_ENABLED
24989 #endif
24992 #endif
24993 }
24994 \f
24995 /* The following file contains several enumerations and data structures
24996 built from the definitions in i386-builtin-types.def. */
25000 /* Table for the ix86 builtin non-function types. */
25003 /* Retrieve an element from the above table, building some of
25004 the types lazily. */
25006 static tree
25008 {
25020 {
25028 }
25029 else
25030 {
25036 else
25044 }
25048 }
25050 /* Table for the ix86 builtin function types. */
25053 /* Retrieve an element from the above table, building some of
25054 the types lazily. */
25056 static tree
25058 {
25059 tree type;
25068 {
25076 {
25079 }
25082 }
25083 else
25084 {
25090 }
25094 }
25097 /* Codes for all the SSE/MMX builtins. */
25098 enum ix86_builtins
25099 {
25100 IX86_BUILTIN_ADDPS,
25101 IX86_BUILTIN_ADDSS,
25102 IX86_BUILTIN_DIVPS,
25103 IX86_BUILTIN_DIVSS,
25104 IX86_BUILTIN_MULPS,
25105 IX86_BUILTIN_MULSS,
25106 IX86_BUILTIN_SUBPS,
25107 IX86_BUILTIN_SUBSS,
25109 IX86_BUILTIN_CMPEQPS,
25110 IX86_BUILTIN_CMPLTPS,
25111 IX86_BUILTIN_CMPLEPS,
25112 IX86_BUILTIN_CMPGTPS,
25113 IX86_BUILTIN_CMPGEPS,
25114 IX86_BUILTIN_CMPNEQPS,
25115 IX86_BUILTIN_CMPNLTPS,
25116 IX86_BUILTIN_CMPNLEPS,
25117 IX86_BUILTIN_CMPNGTPS,
25118 IX86_BUILTIN_CMPNGEPS,
25119 IX86_BUILTIN_CMPORDPS,
25120 IX86_BUILTIN_CMPUNORDPS,
25121 IX86_BUILTIN_CMPEQSS,
25122 IX86_BUILTIN_CMPLTSS,
25123 IX86_BUILTIN_CMPLESS,
25124 IX86_BUILTIN_CMPNEQSS,
25125 IX86_BUILTIN_CMPNLTSS,
25126 IX86_BUILTIN_CMPNLESS,
25127 IX86_BUILTIN_CMPNGTSS,
25128 IX86_BUILTIN_CMPNGESS,
25129 IX86_BUILTIN_CMPORDSS,
25130 IX86_BUILTIN_CMPUNORDSS,
25132 IX86_BUILTIN_COMIEQSS,
25133 IX86_BUILTIN_COMILTSS,
25134 IX86_BUILTIN_COMILESS,
25135 IX86_BUILTIN_COMIGTSS,
25136 IX86_BUILTIN_COMIGESS,
25137 IX86_BUILTIN_COMINEQSS,
25138 IX86_BUILTIN_UCOMIEQSS,
25139 IX86_BUILTIN_UCOMILTSS,
25140 IX86_BUILTIN_UCOMILESS,
25141 IX86_BUILTIN_UCOMIGTSS,
25142 IX86_BUILTIN_UCOMIGESS,
25143 IX86_BUILTIN_UCOMINEQSS,
25145 IX86_BUILTIN_CVTPI2PS,
25146 IX86_BUILTIN_CVTPS2PI,
25147 IX86_BUILTIN_CVTSI2SS,
25148 IX86_BUILTIN_CVTSI642SS,
25149 IX86_BUILTIN_CVTSS2SI,
25150 IX86_BUILTIN_CVTSS2SI64,
25151 IX86_BUILTIN_CVTTPS2PI,
25152 IX86_BUILTIN_CVTTSS2SI,
25153 IX86_BUILTIN_CVTTSS2SI64,
25155 IX86_BUILTIN_MAXPS,
25156 IX86_BUILTIN_MAXSS,
25157 IX86_BUILTIN_MINPS,
25158 IX86_BUILTIN_MINSS,
25160 IX86_BUILTIN_LOADUPS,
25161 IX86_BUILTIN_STOREUPS,
25162 IX86_BUILTIN_MOVSS,
25164 IX86_BUILTIN_MOVHLPS,
25165 IX86_BUILTIN_MOVLHPS,
25166 IX86_BUILTIN_LOADHPS,
25167 IX86_BUILTIN_LOADLPS,
25168 IX86_BUILTIN_STOREHPS,
25169 IX86_BUILTIN_STORELPS,
25171 IX86_BUILTIN_MASKMOVQ,
25172 IX86_BUILTIN_MOVMSKPS,
25173 IX86_BUILTIN_PMOVMSKB,
25175 IX86_BUILTIN_MOVNTPS,
25176 IX86_BUILTIN_MOVNTQ,
25178 IX86_BUILTIN_LOADDQU,
25179 IX86_BUILTIN_STOREDQU,
25181 IX86_BUILTIN_PACKSSWB,
25182 IX86_BUILTIN_PACKSSDW,
25183 IX86_BUILTIN_PACKUSWB,
25185 IX86_BUILTIN_PADDB,
25186 IX86_BUILTIN_PADDW,
25187 IX86_BUILTIN_PADDD,
25188 IX86_BUILTIN_PADDQ,
25189 IX86_BUILTIN_PADDSB,
25190 IX86_BUILTIN_PADDSW,
25191 IX86_BUILTIN_PADDUSB,
25192 IX86_BUILTIN_PADDUSW,
25193 IX86_BUILTIN_PSUBB,
25194 IX86_BUILTIN_PSUBW,
25195 IX86_BUILTIN_PSUBD,
25196 IX86_BUILTIN_PSUBQ,
25197 IX86_BUILTIN_PSUBSB,
25198 IX86_BUILTIN_PSUBSW,
25199 IX86_BUILTIN_PSUBUSB,
25200 IX86_BUILTIN_PSUBUSW,
25202 IX86_BUILTIN_PAND,
25203 IX86_BUILTIN_PANDN,
25204 IX86_BUILTIN_POR,
25205 IX86_BUILTIN_PXOR,
25207 IX86_BUILTIN_PAVGB,
25208 IX86_BUILTIN_PAVGW,
25210 IX86_BUILTIN_PCMPEQB,
25211 IX86_BUILTIN_PCMPEQW,
25212 IX86_BUILTIN_PCMPEQD,
25213 IX86_BUILTIN_PCMPGTB,
25214 IX86_BUILTIN_PCMPGTW,
25215 IX86_BUILTIN_PCMPGTD,
25217 IX86_BUILTIN_PMADDWD,
25219 IX86_BUILTIN_PMAXSW,
25220 IX86_BUILTIN_PMAXUB,
25221 IX86_BUILTIN_PMINSW,
25222 IX86_BUILTIN_PMINUB,
25224 IX86_BUILTIN_PMULHUW,
25225 IX86_BUILTIN_PMULHW,
25226 IX86_BUILTIN_PMULLW,
25228 IX86_BUILTIN_PSADBW,
25229 IX86_BUILTIN_PSHUFW,
25231 IX86_BUILTIN_PSLLW,
25232 IX86_BUILTIN_PSLLD,
25233 IX86_BUILTIN_PSLLQ,
25234 IX86_BUILTIN_PSRAW,
25235 IX86_BUILTIN_PSRAD,
25236 IX86_BUILTIN_PSRLW,
25237 IX86_BUILTIN_PSRLD,
25238 IX86_BUILTIN_PSRLQ,
25239 IX86_BUILTIN_PSLLWI,
25240 IX86_BUILTIN_PSLLDI,
25241 IX86_BUILTIN_PSLLQI,
25242 IX86_BUILTIN_PSRAWI,
25243 IX86_BUILTIN_PSRADI,
25244 IX86_BUILTIN_PSRLWI,
25245 IX86_BUILTIN_PSRLDI,
25246 IX86_BUILTIN_PSRLQI,
25248 IX86_BUILTIN_PUNPCKHBW,
25249 IX86_BUILTIN_PUNPCKHWD,
25250 IX86_BUILTIN_PUNPCKHDQ,
25251 IX86_BUILTIN_PUNPCKLBW,
25252 IX86_BUILTIN_PUNPCKLWD,
25253 IX86_BUILTIN_PUNPCKLDQ,
25255 IX86_BUILTIN_SHUFPS,
25257 IX86_BUILTIN_RCPPS,
25258 IX86_BUILTIN_RCPSS,
25259 IX86_BUILTIN_RSQRTPS,
25260 IX86_BUILTIN_RSQRTPS_NR,
25261 IX86_BUILTIN_RSQRTSS,
25262 IX86_BUILTIN_RSQRTF,
25263 IX86_BUILTIN_SQRTPS,
25264 IX86_BUILTIN_SQRTPS_NR,
25265 IX86_BUILTIN_SQRTSS,
25267 IX86_BUILTIN_UNPCKHPS,
25268 IX86_BUILTIN_UNPCKLPS,
25270 IX86_BUILTIN_ANDPS,
25271 IX86_BUILTIN_ANDNPS,
25272 IX86_BUILTIN_ORPS,
25273 IX86_BUILTIN_XORPS,
25275 IX86_BUILTIN_EMMS,
25276 IX86_BUILTIN_LDMXCSR,
25277 IX86_BUILTIN_STMXCSR,
25278 IX86_BUILTIN_SFENCE,
25280 IX86_BUILTIN_FXSAVE,
25281 IX86_BUILTIN_FXRSTOR,
25282 IX86_BUILTIN_FXSAVE64,
25283 IX86_BUILTIN_FXRSTOR64,
25285 IX86_BUILTIN_XSAVE,
25286 IX86_BUILTIN_XRSTOR,
25287 IX86_BUILTIN_XSAVE64,
25288 IX86_BUILTIN_XRSTOR64,
25290 IX86_BUILTIN_XSAVEOPT,
25291 IX86_BUILTIN_XSAVEOPT64,
25293 /* 3DNow! Original */
25294 IX86_BUILTIN_FEMMS,
25295 IX86_BUILTIN_PAVGUSB,
25296 IX86_BUILTIN_PF2ID,
25297 IX86_BUILTIN_PFACC,
25298 IX86_BUILTIN_PFADD,
25299 IX86_BUILTIN_PFCMPEQ,
25300 IX86_BUILTIN_PFCMPGE,
25301 IX86_BUILTIN_PFCMPGT,
25302 IX86_BUILTIN_PFMAX,
25303 IX86_BUILTIN_PFMIN,
25304 IX86_BUILTIN_PFMUL,
25305 IX86_BUILTIN_PFRCP,
25306 IX86_BUILTIN_PFRCPIT1,
25307 IX86_BUILTIN_PFRCPIT2,
25308 IX86_BUILTIN_PFRSQIT1,
25309 IX86_BUILTIN_PFRSQRT,
25310 IX86_BUILTIN_PFSUB,
25311 IX86_BUILTIN_PFSUBR,
25312 IX86_BUILTIN_PI2FD,
25313 IX86_BUILTIN_PMULHRW,
25315 /* 3DNow! Athlon Extensions */
25316 IX86_BUILTIN_PF2IW,
25317 IX86_BUILTIN_PFNACC,
25318 IX86_BUILTIN_PFPNACC,
25319 IX86_BUILTIN_PI2FW,
25320 IX86_BUILTIN_PSWAPDSI,
25321 IX86_BUILTIN_PSWAPDSF,
25323 /* SSE2 */
25324 IX86_BUILTIN_ADDPD,
25325 IX86_BUILTIN_ADDSD,
25326 IX86_BUILTIN_DIVPD,
25327 IX86_BUILTIN_DIVSD,
25328 IX86_BUILTIN_MULPD,
25329 IX86_BUILTIN_MULSD,
25330 IX86_BUILTIN_SUBPD,
25331 IX86_BUILTIN_SUBSD,
25333 IX86_BUILTIN_CMPEQPD,
25334 IX86_BUILTIN_CMPLTPD,
25335 IX86_BUILTIN_CMPLEPD,
25336 IX86_BUILTIN_CMPGTPD,
25337 IX86_BUILTIN_CMPGEPD,
25338 IX86_BUILTIN_CMPNEQPD,
25339 IX86_BUILTIN_CMPNLTPD,
25340 IX86_BUILTIN_CMPNLEPD,
25341 IX86_BUILTIN_CMPNGTPD,
25342 IX86_BUILTIN_CMPNGEPD,
25343 IX86_BUILTIN_CMPORDPD,
25344 IX86_BUILTIN_CMPUNORDPD,
25345 IX86_BUILTIN_CMPEQSD,
25346 IX86_BUILTIN_CMPLTSD,
25347 IX86_BUILTIN_CMPLESD,
25348 IX86_BUILTIN_CMPNEQSD,
25349 IX86_BUILTIN_CMPNLTSD,
25350 IX86_BUILTIN_CMPNLESD,
25351 IX86_BUILTIN_CMPORDSD,
25352 IX86_BUILTIN_CMPUNORDSD,
25354 IX86_BUILTIN_COMIEQSD,
25355 IX86_BUILTIN_COMILTSD,
25356 IX86_BUILTIN_COMILESD,
25357 IX86_BUILTIN_COMIGTSD,
25358 IX86_BUILTIN_COMIGESD,
25359 IX86_BUILTIN_COMINEQSD,
25360 IX86_BUILTIN_UCOMIEQSD,
25361 IX86_BUILTIN_UCOMILTSD,
25362 IX86_BUILTIN_UCOMILESD,
25363 IX86_BUILTIN_UCOMIGTSD,
25364 IX86_BUILTIN_UCOMIGESD,
25365 IX86_BUILTIN_UCOMINEQSD,
25367 IX86_BUILTIN_MAXPD,
25368 IX86_BUILTIN_MAXSD,
25369 IX86_BUILTIN_MINPD,
25370 IX86_BUILTIN_MINSD,
25372 IX86_BUILTIN_ANDPD,
25373 IX86_BUILTIN_ANDNPD,
25374 IX86_BUILTIN_ORPD,
25375 IX86_BUILTIN_XORPD,
25377 IX86_BUILTIN_SQRTPD,
25378 IX86_BUILTIN_SQRTSD,
25380 IX86_BUILTIN_UNPCKHPD,
25381 IX86_BUILTIN_UNPCKLPD,
25383 IX86_BUILTIN_SHUFPD,
25385 IX86_BUILTIN_LOADUPD,
25386 IX86_BUILTIN_STOREUPD,
25387 IX86_BUILTIN_MOVSD,
25389 IX86_BUILTIN_LOADHPD,
25390 IX86_BUILTIN_LOADLPD,
25392 IX86_BUILTIN_CVTDQ2PD,
25393 IX86_BUILTIN_CVTDQ2PS,
25395 IX86_BUILTIN_CVTPD2DQ,
25396 IX86_BUILTIN_CVTPD2PI,
25397 IX86_BUILTIN_CVTPD2PS,
25398 IX86_BUILTIN_CVTTPD2DQ,
25399 IX86_BUILTIN_CVTTPD2PI,
25401 IX86_BUILTIN_CVTPI2PD,
25402 IX86_BUILTIN_CVTSI2SD,
25403 IX86_BUILTIN_CVTSI642SD,
25405 IX86_BUILTIN_CVTSD2SI,
25406 IX86_BUILTIN_CVTSD2SI64,
25407 IX86_BUILTIN_CVTSD2SS,
25408 IX86_BUILTIN_CVTSS2SD,
25409 IX86_BUILTIN_CVTTSD2SI,
25410 IX86_BUILTIN_CVTTSD2SI64,
25412 IX86_BUILTIN_CVTPS2DQ,
25413 IX86_BUILTIN_CVTPS2PD,
25414 IX86_BUILTIN_CVTTPS2DQ,
25416 IX86_BUILTIN_MOVNTI,
25417 IX86_BUILTIN_MOVNTI64,
25418 IX86_BUILTIN_MOVNTPD,
25419 IX86_BUILTIN_MOVNTDQ,
25421 IX86_BUILTIN_MOVQ128,
25423 /* SSE2 MMX */
25424 IX86_BUILTIN_MASKMOVDQU,
25425 IX86_BUILTIN_MOVMSKPD,
25426 IX86_BUILTIN_PMOVMSKB128,
25428 IX86_BUILTIN_PACKSSWB128,
25429 IX86_BUILTIN_PACKSSDW128,
25430 IX86_BUILTIN_PACKUSWB128,
25432 IX86_BUILTIN_PADDB128,
25433 IX86_BUILTIN_PADDW128,
25434 IX86_BUILTIN_PADDD128,
25435 IX86_BUILTIN_PADDQ128,
25436 IX86_BUILTIN_PADDSB128,
25437 IX86_BUILTIN_PADDSW128,
25438 IX86_BUILTIN_PADDUSB128,
25439 IX86_BUILTIN_PADDUSW128,
25440 IX86_BUILTIN_PSUBB128,
25441 IX86_BUILTIN_PSUBW128,
25442 IX86_BUILTIN_PSUBD128,
25443 IX86_BUILTIN_PSUBQ128,
25444 IX86_BUILTIN_PSUBSB128,
25445 IX86_BUILTIN_PSUBSW128,
25446 IX86_BUILTIN_PSUBUSB128,
25447 IX86_BUILTIN_PSUBUSW128,
25449 IX86_BUILTIN_PAND128,
25450 IX86_BUILTIN_PANDN128,
25451 IX86_BUILTIN_POR128,
25452 IX86_BUILTIN_PXOR128,
25454 IX86_BUILTIN_PAVGB128,
25455 IX86_BUILTIN_PAVGW128,
25457 IX86_BUILTIN_PCMPEQB128,
25458 IX86_BUILTIN_PCMPEQW128,
25459 IX86_BUILTIN_PCMPEQD128,
25460 IX86_BUILTIN_PCMPGTB128,
25461 IX86_BUILTIN_PCMPGTW128,
25462 IX86_BUILTIN_PCMPGTD128,
25464 IX86_BUILTIN_PMADDWD128,
25466 IX86_BUILTIN_PMAXSW128,
25467 IX86_BUILTIN_PMAXUB128,
25468 IX86_BUILTIN_PMINSW128,
25469 IX86_BUILTIN_PMINUB128,
25471 IX86_BUILTIN_PMULUDQ,
25472 IX86_BUILTIN_PMULUDQ128,
25473 IX86_BUILTIN_PMULHUW128,
25474 IX86_BUILTIN_PMULHW128,
25475 IX86_BUILTIN_PMULLW128,
25477 IX86_BUILTIN_PSADBW128,
25478 IX86_BUILTIN_PSHUFHW,
25479 IX86_BUILTIN_PSHUFLW,
25480 IX86_BUILTIN_PSHUFD,
25482 IX86_BUILTIN_PSLLDQI128,
25483 IX86_BUILTIN_PSLLWI128,
25484 IX86_BUILTIN_PSLLDI128,
25485 IX86_BUILTIN_PSLLQI128,
25486 IX86_BUILTIN_PSRAWI128,
25487 IX86_BUILTIN_PSRADI128,
25488 IX86_BUILTIN_PSRLDQI128,
25489 IX86_BUILTIN_PSRLWI128,
25490 IX86_BUILTIN_PSRLDI128,
25491 IX86_BUILTIN_PSRLQI128,
25493 IX86_BUILTIN_PSLLDQ128,
25494 IX86_BUILTIN_PSLLW128,
25495 IX86_BUILTIN_PSLLD128,
25496 IX86_BUILTIN_PSLLQ128,
25497 IX86_BUILTIN_PSRAW128,
25498 IX86_BUILTIN_PSRAD128,
25499 IX86_BUILTIN_PSRLW128,
25500 IX86_BUILTIN_PSRLD128,
25501 IX86_BUILTIN_PSRLQ128,
25503 IX86_BUILTIN_PUNPCKHBW128,
25504 IX86_BUILTIN_PUNPCKHWD128,
25505 IX86_BUILTIN_PUNPCKHDQ128,
25506 IX86_BUILTIN_PUNPCKHQDQ128,
25507 IX86_BUILTIN_PUNPCKLBW128,
25508 IX86_BUILTIN_PUNPCKLWD128,
25509 IX86_BUILTIN_PUNPCKLDQ128,
25510 IX86_BUILTIN_PUNPCKLQDQ128,
25512 IX86_BUILTIN_CLFLUSH,
25513 IX86_BUILTIN_MFENCE,
25514 IX86_BUILTIN_LFENCE,
25515 IX86_BUILTIN_PAUSE,
25517 IX86_BUILTIN_BSRSI,
25518 IX86_BUILTIN_BSRDI,
25519 IX86_BUILTIN_RDPMC,
25520 IX86_BUILTIN_RDTSC,
25521 IX86_BUILTIN_RDTSCP,
25522 IX86_BUILTIN_ROLQI,
25523 IX86_BUILTIN_ROLHI,
25524 IX86_BUILTIN_RORQI,
25525 IX86_BUILTIN_RORHI,
25527 /* SSE3. */
25528 IX86_BUILTIN_ADDSUBPS,
25529 IX86_BUILTIN_HADDPS,
25530 IX86_BUILTIN_HSUBPS,
25531 IX86_BUILTIN_MOVSHDUP,
25532 IX86_BUILTIN_MOVSLDUP,
25533 IX86_BUILTIN_ADDSUBPD,
25534 IX86_BUILTIN_HADDPD,
25535 IX86_BUILTIN_HSUBPD,
25536 IX86_BUILTIN_LDDQU,
25538 IX86_BUILTIN_MONITOR,
25539 IX86_BUILTIN_MWAIT,
25541 /* SSSE3. */
25542 IX86_BUILTIN_PHADDW,
25543 IX86_BUILTIN_PHADDD,
25544 IX86_BUILTIN_PHADDSW,
25545 IX86_BUILTIN_PHSUBW,
25546 IX86_BUILTIN_PHSUBD,
25547 IX86_BUILTIN_PHSUBSW,
25548 IX86_BUILTIN_PMADDUBSW,
25549 IX86_BUILTIN_PMULHRSW,
25550 IX86_BUILTIN_PSHUFB,
25551 IX86_BUILTIN_PSIGNB,
25552 IX86_BUILTIN_PSIGNW,
25553 IX86_BUILTIN_PSIGND,
25554 IX86_BUILTIN_PALIGNR,
25555 IX86_BUILTIN_PABSB,
25556 IX86_BUILTIN_PABSW,
25557 IX86_BUILTIN_PABSD,
25559 IX86_BUILTIN_PHADDW128,
25560 IX86_BUILTIN_PHADDD128,
25561 IX86_BUILTIN_PHADDSW128,
25562 IX86_BUILTIN_PHSUBW128,
25563 IX86_BUILTIN_PHSUBD128,
25564 IX86_BUILTIN_PHSUBSW128,
25565 IX86_BUILTIN_PMADDUBSW128,
25566 IX86_BUILTIN_PMULHRSW128,
25567 IX86_BUILTIN_PSHUFB128,
25568 IX86_BUILTIN_PSIGNB128,
25569 IX86_BUILTIN_PSIGNW128,
25570 IX86_BUILTIN_PSIGND128,
25571 IX86_BUILTIN_PALIGNR128,
25572 IX86_BUILTIN_PABSB128,
25573 IX86_BUILTIN_PABSW128,
25574 IX86_BUILTIN_PABSD128,
25576 /* AMDFAM10 - SSE4A New Instructions. */
25577 IX86_BUILTIN_MOVNTSD,
25578 IX86_BUILTIN_MOVNTSS,
25579 IX86_BUILTIN_EXTRQI,
25580 IX86_BUILTIN_EXTRQ,
25581 IX86_BUILTIN_INSERTQI,
25582 IX86_BUILTIN_INSERTQ,
25584 /* SSE4.1. */
25585 IX86_BUILTIN_BLENDPD,
25586 IX86_BUILTIN_BLENDPS,
25587 IX86_BUILTIN_BLENDVPD,
25588 IX86_BUILTIN_BLENDVPS,
25589 IX86_BUILTIN_PBLENDVB128,
25590 IX86_BUILTIN_PBLENDW128,
25592 IX86_BUILTIN_DPPD,
25593 IX86_BUILTIN_DPPS,
25595 IX86_BUILTIN_INSERTPS128,
25597 IX86_BUILTIN_MOVNTDQA,
25598 IX86_BUILTIN_MPSADBW128,
25599 IX86_BUILTIN_PACKUSDW128,
25600 IX86_BUILTIN_PCMPEQQ,
25601 IX86_BUILTIN_PHMINPOSUW128,
25603 IX86_BUILTIN_PMAXSB128,
25604 IX86_BUILTIN_PMAXSD128,
25605 IX86_BUILTIN_PMAXUD128,
25606 IX86_BUILTIN_PMAXUW128,
25608 IX86_BUILTIN_PMINSB128,
25609 IX86_BUILTIN_PMINSD128,
25610 IX86_BUILTIN_PMINUD128,
25611 IX86_BUILTIN_PMINUW128,
25613 IX86_BUILTIN_PMOVSXBW128,
25614 IX86_BUILTIN_PMOVSXBD128,
25615 IX86_BUILTIN_PMOVSXBQ128,
25616 IX86_BUILTIN_PMOVSXWD128,
25617 IX86_BUILTIN_PMOVSXWQ128,
25618 IX86_BUILTIN_PMOVSXDQ128,
25620 IX86_BUILTIN_PMOVZXBW128,
25621 IX86_BUILTIN_PMOVZXBD128,
25622 IX86_BUILTIN_PMOVZXBQ128,
25623 IX86_BUILTIN_PMOVZXWD128,
25624 IX86_BUILTIN_PMOVZXWQ128,
25625 IX86_BUILTIN_PMOVZXDQ128,
25627 IX86_BUILTIN_PMULDQ128,
25628 IX86_BUILTIN_PMULLD128,
25630 IX86_BUILTIN_ROUNDSD,
25631 IX86_BUILTIN_ROUNDSS,
25633 IX86_BUILTIN_ROUNDPD,
25634 IX86_BUILTIN_ROUNDPS,
25636 IX86_BUILTIN_FLOORPD,
25637 IX86_BUILTIN_CEILPD,
25638 IX86_BUILTIN_TRUNCPD,
25639 IX86_BUILTIN_RINTPD,
25640 IX86_BUILTIN_ROUNDPD_AZ,
25642 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
25643 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
25644 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
25646 IX86_BUILTIN_FLOORPS,
25647 IX86_BUILTIN_CEILPS,
25648 IX86_BUILTIN_TRUNCPS,
25649 IX86_BUILTIN_RINTPS,
25650 IX86_BUILTIN_ROUNDPS_AZ,
25652 IX86_BUILTIN_FLOORPS_SFIX,
25653 IX86_BUILTIN_CEILPS_SFIX,
25654 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
25656 IX86_BUILTIN_PTESTZ,
25657 IX86_BUILTIN_PTESTC,
25658 IX86_BUILTIN_PTESTNZC,
25660 IX86_BUILTIN_VEC_INIT_V2SI,
25661 IX86_BUILTIN_VEC_INIT_V4HI,
25662 IX86_BUILTIN_VEC_INIT_V8QI,
25663 IX86_BUILTIN_VEC_EXT_V2DF,
25664 IX86_BUILTIN_VEC_EXT_V2DI,
25665 IX86_BUILTIN_VEC_EXT_V4SF,
25666 IX86_BUILTIN_VEC_EXT_V4SI,
25667 IX86_BUILTIN_VEC_EXT_V8HI,
25668 IX86_BUILTIN_VEC_EXT_V2SI,
25669 IX86_BUILTIN_VEC_EXT_V4HI,
25670 IX86_BUILTIN_VEC_EXT_V16QI,
25671 IX86_BUILTIN_VEC_SET_V2DI,
25672 IX86_BUILTIN_VEC_SET_V4SF,
25673 IX86_BUILTIN_VEC_SET_V4SI,
25674 IX86_BUILTIN_VEC_SET_V8HI,
25675 IX86_BUILTIN_VEC_SET_V4HI,
25676 IX86_BUILTIN_VEC_SET_V16QI,
25678 IX86_BUILTIN_VEC_PACK_SFIX,
25679 IX86_BUILTIN_VEC_PACK_SFIX256,
25681 /* SSE4.2. */
25682 IX86_BUILTIN_CRC32QI,
25683 IX86_BUILTIN_CRC32HI,
25684 IX86_BUILTIN_CRC32SI,
25685 IX86_BUILTIN_CRC32DI,
25687 IX86_BUILTIN_PCMPESTRI128,
25688 IX86_BUILTIN_PCMPESTRM128,
25689 IX86_BUILTIN_PCMPESTRA128,
25690 IX86_BUILTIN_PCMPESTRC128,
25691 IX86_BUILTIN_PCMPESTRO128,
25692 IX86_BUILTIN_PCMPESTRS128,
25693 IX86_BUILTIN_PCMPESTRZ128,
25694 IX86_BUILTIN_PCMPISTRI128,
25695 IX86_BUILTIN_PCMPISTRM128,
25696 IX86_BUILTIN_PCMPISTRA128,
25697 IX86_BUILTIN_PCMPISTRC128,
25698 IX86_BUILTIN_PCMPISTRO128,
25699 IX86_BUILTIN_PCMPISTRS128,
25700 IX86_BUILTIN_PCMPISTRZ128,
25702 IX86_BUILTIN_PCMPGTQ,
25704 /* AES instructions */
25705 IX86_BUILTIN_AESENC128,
25706 IX86_BUILTIN_AESENCLAST128,
25707 IX86_BUILTIN_AESDEC128,
25708 IX86_BUILTIN_AESDECLAST128,
25709 IX86_BUILTIN_AESIMC128,
25710 IX86_BUILTIN_AESKEYGENASSIST128,
25712 /* PCLMUL instruction */
25713 IX86_BUILTIN_PCLMULQDQ128,
25715 /* AVX */
25716 IX86_BUILTIN_ADDPD256,
25717 IX86_BUILTIN_ADDPS256,
25718 IX86_BUILTIN_ADDSUBPD256,
25719 IX86_BUILTIN_ADDSUBPS256,
25720 IX86_BUILTIN_ANDPD256,
25721 IX86_BUILTIN_ANDPS256,
25722 IX86_BUILTIN_ANDNPD256,
25723 IX86_BUILTIN_ANDNPS256,
25724 IX86_BUILTIN_BLENDPD256,
25725 IX86_BUILTIN_BLENDPS256,
25726 IX86_BUILTIN_BLENDVPD256,
25727 IX86_BUILTIN_BLENDVPS256,
25728 IX86_BUILTIN_DIVPD256,
25729 IX86_BUILTIN_DIVPS256,
25730 IX86_BUILTIN_DPPS256,
25731 IX86_BUILTIN_HADDPD256,
25732 IX86_BUILTIN_HADDPS256,
25733 IX86_BUILTIN_HSUBPD256,
25734 IX86_BUILTIN_HSUBPS256,
25735 IX86_BUILTIN_MAXPD256,
25736 IX86_BUILTIN_MAXPS256,
25737 IX86_BUILTIN_MINPD256,
25738 IX86_BUILTIN_MINPS256,
25739 IX86_BUILTIN_MULPD256,
25740 IX86_BUILTIN_MULPS256,
25741 IX86_BUILTIN_ORPD256,
25742 IX86_BUILTIN_ORPS256,
25743 IX86_BUILTIN_SHUFPD256,
25744 IX86_BUILTIN_SHUFPS256,
25745 IX86_BUILTIN_SUBPD256,
25746 IX86_BUILTIN_SUBPS256,
25747 IX86_BUILTIN_XORPD256,
25748 IX86_BUILTIN_XORPS256,
25749 IX86_BUILTIN_CMPSD,
25750 IX86_BUILTIN_CMPSS,
25751 IX86_BUILTIN_CMPPD,
25752 IX86_BUILTIN_CMPPS,
25753 IX86_BUILTIN_CMPPD256,
25754 IX86_BUILTIN_CMPPS256,
25755 IX86_BUILTIN_CVTDQ2PD256,
25756 IX86_BUILTIN_CVTDQ2PS256,
25757 IX86_BUILTIN_CVTPD2PS256,
25758 IX86_BUILTIN_CVTPS2DQ256,
25759 IX86_BUILTIN_CVTPS2PD256,
25760 IX86_BUILTIN_CVTTPD2DQ256,
25761 IX86_BUILTIN_CVTPD2DQ256,
25762 IX86_BUILTIN_CVTTPS2DQ256,
25763 IX86_BUILTIN_EXTRACTF128PD256,
25764 IX86_BUILTIN_EXTRACTF128PS256,
25765 IX86_BUILTIN_EXTRACTF128SI256,
25766 IX86_BUILTIN_VZEROALL,
25767 IX86_BUILTIN_VZEROUPPER,
25768 IX86_BUILTIN_VPERMILVARPD,
25769 IX86_BUILTIN_VPERMILVARPS,
25770 IX86_BUILTIN_VPERMILVARPD256,
25771 IX86_BUILTIN_VPERMILVARPS256,
25772 IX86_BUILTIN_VPERMILPD,
25773 IX86_BUILTIN_VPERMILPS,
25774 IX86_BUILTIN_VPERMILPD256,
25775 IX86_BUILTIN_VPERMILPS256,
25776 IX86_BUILTIN_VPERMIL2PD,
25777 IX86_BUILTIN_VPERMIL2PS,
25778 IX86_BUILTIN_VPERMIL2PD256,
25779 IX86_BUILTIN_VPERMIL2PS256,
25780 IX86_BUILTIN_VPERM2F128PD256,
25781 IX86_BUILTIN_VPERM2F128PS256,
25782 IX86_BUILTIN_VPERM2F128SI256,
25783 IX86_BUILTIN_VBROADCASTSS,
25784 IX86_BUILTIN_VBROADCASTSD256,
25785 IX86_BUILTIN_VBROADCASTSS256,
25786 IX86_BUILTIN_VBROADCASTPD256,
25787 IX86_BUILTIN_VBROADCASTPS256,
25788 IX86_BUILTIN_VINSERTF128PD256,
25789 IX86_BUILTIN_VINSERTF128PS256,
25790 IX86_BUILTIN_VINSERTF128SI256,
25791 IX86_BUILTIN_LOADUPD256,
25792 IX86_BUILTIN_LOADUPS256,
25793 IX86_BUILTIN_STOREUPD256,
25794 IX86_BUILTIN_STOREUPS256,
25795 IX86_BUILTIN_LDDQU256,
25796 IX86_BUILTIN_MOVNTDQ256,
25797 IX86_BUILTIN_MOVNTPD256,
25798 IX86_BUILTIN_MOVNTPS256,
25799 IX86_BUILTIN_LOADDQU256,
25800 IX86_BUILTIN_STOREDQU256,
25801 IX86_BUILTIN_MASKLOADPD,
25802 IX86_BUILTIN_MASKLOADPS,
25803 IX86_BUILTIN_MASKSTOREPD,
25804 IX86_BUILTIN_MASKSTOREPS,
25805 IX86_BUILTIN_MASKLOADPD256,
25806 IX86_BUILTIN_MASKLOADPS256,
25807 IX86_BUILTIN_MASKSTOREPD256,
25808 IX86_BUILTIN_MASKSTOREPS256,
25809 IX86_BUILTIN_MOVSHDUP256,
25810 IX86_BUILTIN_MOVSLDUP256,
25811 IX86_BUILTIN_MOVDDUP256,
25813 IX86_BUILTIN_SQRTPD256,
25814 IX86_BUILTIN_SQRTPS256,
25815 IX86_BUILTIN_SQRTPS_NR256,
25816 IX86_BUILTIN_RSQRTPS256,
25817 IX86_BUILTIN_RSQRTPS_NR256,
25819 IX86_BUILTIN_RCPPS256,
25821 IX86_BUILTIN_ROUNDPD256,
25822 IX86_BUILTIN_ROUNDPS256,
25824 IX86_BUILTIN_FLOORPD256,
25825 IX86_BUILTIN_CEILPD256,
25826 IX86_BUILTIN_TRUNCPD256,
25827 IX86_BUILTIN_RINTPD256,
25828 IX86_BUILTIN_ROUNDPD_AZ256,
25830 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
25831 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
25832 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
25834 IX86_BUILTIN_FLOORPS256,
25835 IX86_BUILTIN_CEILPS256,
25836 IX86_BUILTIN_TRUNCPS256,
25837 IX86_BUILTIN_RINTPS256,
25838 IX86_BUILTIN_ROUNDPS_AZ256,
25840 IX86_BUILTIN_FLOORPS_SFIX256,
25841 IX86_BUILTIN_CEILPS_SFIX256,
25842 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
25844 IX86_BUILTIN_UNPCKHPD256,
25845 IX86_BUILTIN_UNPCKLPD256,
25846 IX86_BUILTIN_UNPCKHPS256,
25847 IX86_BUILTIN_UNPCKLPS256,
25849 IX86_BUILTIN_SI256_SI,
25850 IX86_BUILTIN_PS256_PS,
25851 IX86_BUILTIN_PD256_PD,
25852 IX86_BUILTIN_SI_SI256,
25853 IX86_BUILTIN_PS_PS256,
25854 IX86_BUILTIN_PD_PD256,
25856 IX86_BUILTIN_VTESTZPD,
25857 IX86_BUILTIN_VTESTCPD,
25858 IX86_BUILTIN_VTESTNZCPD,
25859 IX86_BUILTIN_VTESTZPS,
25860 IX86_BUILTIN_VTESTCPS,
25861 IX86_BUILTIN_VTESTNZCPS,
25862 IX86_BUILTIN_VTESTZPD256,
25863 IX86_BUILTIN_VTESTCPD256,
25864 IX86_BUILTIN_VTESTNZCPD256,
25865 IX86_BUILTIN_VTESTZPS256,
25866 IX86_BUILTIN_VTESTCPS256,
25867 IX86_BUILTIN_VTESTNZCPS256,
25868 IX86_BUILTIN_PTESTZ256,
25869 IX86_BUILTIN_PTESTC256,
25870 IX86_BUILTIN_PTESTNZC256,
25872 IX86_BUILTIN_MOVMSKPD256,
25873 IX86_BUILTIN_MOVMSKPS256,
25875 /* AVX2 */
25876 IX86_BUILTIN_MPSADBW256,
25877 IX86_BUILTIN_PABSB256,
25878 IX86_BUILTIN_PABSW256,
25879 IX86_BUILTIN_PABSD256,
25880 IX86_BUILTIN_PACKSSDW256,
25881 IX86_BUILTIN_PACKSSWB256,
25882 IX86_BUILTIN_PACKUSDW256,
25883 IX86_BUILTIN_PACKUSWB256,
25884 IX86_BUILTIN_PADDB256,
25885 IX86_BUILTIN_PADDW256,
25886 IX86_BUILTIN_PADDD256,
25887 IX86_BUILTIN_PADDQ256,
25888 IX86_BUILTIN_PADDSB256,
25889 IX86_BUILTIN_PADDSW256,
25890 IX86_BUILTIN_PADDUSB256,
25891 IX86_BUILTIN_PADDUSW256,
25892 IX86_BUILTIN_PALIGNR256,
25893 IX86_BUILTIN_AND256I,
25894 IX86_BUILTIN_ANDNOT256I,
25895 IX86_BUILTIN_PAVGB256,
25896 IX86_BUILTIN_PAVGW256,
25897 IX86_BUILTIN_PBLENDVB256,
25898 IX86_BUILTIN_PBLENDVW256,
25899 IX86_BUILTIN_PCMPEQB256,
25900 IX86_BUILTIN_PCMPEQW256,
25901 IX86_BUILTIN_PCMPEQD256,
25902 IX86_BUILTIN_PCMPEQQ256,
25903 IX86_BUILTIN_PCMPGTB256,
25904 IX86_BUILTIN_PCMPGTW256,
25905 IX86_BUILTIN_PCMPGTD256,
25906 IX86_BUILTIN_PCMPGTQ256,
25907 IX86_BUILTIN_PHADDW256,
25908 IX86_BUILTIN_PHADDD256,
25909 IX86_BUILTIN_PHADDSW256,
25910 IX86_BUILTIN_PHSUBW256,
25911 IX86_BUILTIN_PHSUBD256,
25912 IX86_BUILTIN_PHSUBSW256,
25913 IX86_BUILTIN_PMADDUBSW256,
25914 IX86_BUILTIN_PMADDWD256,
25915 IX86_BUILTIN_PMAXSB256,
25916 IX86_BUILTIN_PMAXSW256,
25917 IX86_BUILTIN_PMAXSD256,
25918 IX86_BUILTIN_PMAXUB256,
25919 IX86_BUILTIN_PMAXUW256,
25920 IX86_BUILTIN_PMAXUD256,
25921 IX86_BUILTIN_PMINSB256,
25922 IX86_BUILTIN_PMINSW256,
25923 IX86_BUILTIN_PMINSD256,
25924 IX86_BUILTIN_PMINUB256,
25925 IX86_BUILTIN_PMINUW256,
25926 IX86_BUILTIN_PMINUD256,
25927 IX86_BUILTIN_PMOVMSKB256,
25928 IX86_BUILTIN_PMOVSXBW256,
25929 IX86_BUILTIN_PMOVSXBD256,
25930 IX86_BUILTIN_PMOVSXBQ256,
25931 IX86_BUILTIN_PMOVSXWD256,
25932 IX86_BUILTIN_PMOVSXWQ256,
25933 IX86_BUILTIN_PMOVSXDQ256,
25934 IX86_BUILTIN_PMOVZXBW256,
25935 IX86_BUILTIN_PMOVZXBD256,
25936 IX86_BUILTIN_PMOVZXBQ256,
25937 IX86_BUILTIN_PMOVZXWD256,
25938 IX86_BUILTIN_PMOVZXWQ256,
25939 IX86_BUILTIN_PMOVZXDQ256,
25940 IX86_BUILTIN_PMULDQ256,
25941 IX86_BUILTIN_PMULHRSW256,
25942 IX86_BUILTIN_PMULHUW256,
25943 IX86_BUILTIN_PMULHW256,
25944 IX86_BUILTIN_PMULLW256,
25945 IX86_BUILTIN_PMULLD256,
25946 IX86_BUILTIN_PMULUDQ256,
25947 IX86_BUILTIN_POR256,
25948 IX86_BUILTIN_PSADBW256,
25949 IX86_BUILTIN_PSHUFB256,
25950 IX86_BUILTIN_PSHUFD256,
25951 IX86_BUILTIN_PSHUFHW256,
25952 IX86_BUILTIN_PSHUFLW256,
25953 IX86_BUILTIN_PSIGNB256,
25954 IX86_BUILTIN_PSIGNW256,
25955 IX86_BUILTIN_PSIGND256,
25956 IX86_BUILTIN_PSLLDQI256,
25957 IX86_BUILTIN_PSLLWI256,
25958 IX86_BUILTIN_PSLLW256,
25959 IX86_BUILTIN_PSLLDI256,
25960 IX86_BUILTIN_PSLLD256,
25961 IX86_BUILTIN_PSLLQI256,
25962 IX86_BUILTIN_PSLLQ256,
25963 IX86_BUILTIN_PSRAWI256,
25964 IX86_BUILTIN_PSRAW256,
25965 IX86_BUILTIN_PSRADI256,
25966 IX86_BUILTIN_PSRAD256,
25967 IX86_BUILTIN_PSRLDQI256,
25968 IX86_BUILTIN_PSRLWI256,
25969 IX86_BUILTIN_PSRLW256,
25970 IX86_BUILTIN_PSRLDI256,
25971 IX86_BUILTIN_PSRLD256,
25972 IX86_BUILTIN_PSRLQI256,
25973 IX86_BUILTIN_PSRLQ256,
25974 IX86_BUILTIN_PSUBB256,
25975 IX86_BUILTIN_PSUBW256,
25976 IX86_BUILTIN_PSUBD256,
25977 IX86_BUILTIN_PSUBQ256,
25978 IX86_BUILTIN_PSUBSB256,
25979 IX86_BUILTIN_PSUBSW256,
25980 IX86_BUILTIN_PSUBUSB256,
25981 IX86_BUILTIN_PSUBUSW256,
25982 IX86_BUILTIN_PUNPCKHBW256,
25983 IX86_BUILTIN_PUNPCKHWD256,
25984 IX86_BUILTIN_PUNPCKHDQ256,
25985 IX86_BUILTIN_PUNPCKHQDQ256,
25986 IX86_BUILTIN_PUNPCKLBW256,
25987 IX86_BUILTIN_PUNPCKLWD256,
25988 IX86_BUILTIN_PUNPCKLDQ256,
25989 IX86_BUILTIN_PUNPCKLQDQ256,
25990 IX86_BUILTIN_PXOR256,
25991 IX86_BUILTIN_MOVNTDQA256,
25992 IX86_BUILTIN_VBROADCASTSS_PS,
25993 IX86_BUILTIN_VBROADCASTSS_PS256,
25994 IX86_BUILTIN_VBROADCASTSD_PD256,
25995 IX86_BUILTIN_VBROADCASTSI256,
25996 IX86_BUILTIN_PBLENDD256,
25997 IX86_BUILTIN_PBLENDD128,
25998 IX86_BUILTIN_PBROADCASTB256,
25999 IX86_BUILTIN_PBROADCASTW256,
26000 IX86_BUILTIN_PBROADCASTD256,
26001 IX86_BUILTIN_PBROADCASTQ256,
26002 IX86_BUILTIN_PBROADCASTB128,
26003 IX86_BUILTIN_PBROADCASTW128,
26004 IX86_BUILTIN_PBROADCASTD128,
26005 IX86_BUILTIN_PBROADCASTQ128,
26006 IX86_BUILTIN_VPERMVARSI256,
26007 IX86_BUILTIN_VPERMDF256,
26008 IX86_BUILTIN_VPERMVARSF256,
26009 IX86_BUILTIN_VPERMDI256,
26010 IX86_BUILTIN_VPERMTI256,
26011 IX86_BUILTIN_VEXTRACT128I256,
26012 IX86_BUILTIN_VINSERT128I256,
26013 IX86_BUILTIN_MASKLOADD,
26014 IX86_BUILTIN_MASKLOADQ,
26015 IX86_BUILTIN_MASKLOADD256,
26016 IX86_BUILTIN_MASKLOADQ256,
26017 IX86_BUILTIN_MASKSTORED,
26018 IX86_BUILTIN_MASKSTOREQ,
26019 IX86_BUILTIN_MASKSTORED256,
26020 IX86_BUILTIN_MASKSTOREQ256,
26021 IX86_BUILTIN_PSLLVV4DI,
26022 IX86_BUILTIN_PSLLVV2DI,
26023 IX86_BUILTIN_PSLLVV8SI,
26024 IX86_BUILTIN_PSLLVV4SI,
26025 IX86_BUILTIN_PSRAVV8SI,
26026 IX86_BUILTIN_PSRAVV4SI,
26027 IX86_BUILTIN_PSRLVV4DI,
26028 IX86_BUILTIN_PSRLVV2DI,
26029 IX86_BUILTIN_PSRLVV8SI,
26030 IX86_BUILTIN_PSRLVV4SI,
26032 IX86_BUILTIN_GATHERSIV2DF,
26033 IX86_BUILTIN_GATHERSIV4DF,
26034 IX86_BUILTIN_GATHERDIV2DF,
26035 IX86_BUILTIN_GATHERDIV4DF,
26036 IX86_BUILTIN_GATHERSIV4SF,
26037 IX86_BUILTIN_GATHERSIV8SF,
26038 IX86_BUILTIN_GATHERDIV4SF,
26039 IX86_BUILTIN_GATHERDIV8SF,
26040 IX86_BUILTIN_GATHERSIV2DI,
26041 IX86_BUILTIN_GATHERSIV4DI,
26042 IX86_BUILTIN_GATHERDIV2DI,
26043 IX86_BUILTIN_GATHERDIV4DI,
26044 IX86_BUILTIN_GATHERSIV4SI,
26045 IX86_BUILTIN_GATHERSIV8SI,
26046 IX86_BUILTIN_GATHERDIV4SI,
26047 IX86_BUILTIN_GATHERDIV8SI,
26049 /* Alternate 4 element gather for the vectorizer where
26050 all operands are 32-byte wide. */
26051 IX86_BUILTIN_GATHERALTSIV4DF,
26052 IX86_BUILTIN_GATHERALTDIV8SF,
26053 IX86_BUILTIN_GATHERALTSIV4DI,
26054 IX86_BUILTIN_GATHERALTDIV8SI,
26056 /* TFmode support builtins. */
26057 IX86_BUILTIN_INFQ,
26058 IX86_BUILTIN_HUGE_VALQ,
26059 IX86_BUILTIN_FABSQ,
26060 IX86_BUILTIN_COPYSIGNQ,
26062 /* Vectorizer support builtins. */
26063 IX86_BUILTIN_CPYSGNPS,
26064 IX86_BUILTIN_CPYSGNPD,
26065 IX86_BUILTIN_CPYSGNPS256,
26066 IX86_BUILTIN_CPYSGNPD256,
26068 /* FMA4 instructions. */
26069 IX86_BUILTIN_VFMADDSS,
26070 IX86_BUILTIN_VFMADDSD,
26071 IX86_BUILTIN_VFMADDPS,
26072 IX86_BUILTIN_VFMADDPD,
26073 IX86_BUILTIN_VFMADDPS256,
26074 IX86_BUILTIN_VFMADDPD256,
26075 IX86_BUILTIN_VFMADDSUBPS,
26076 IX86_BUILTIN_VFMADDSUBPD,
26077 IX86_BUILTIN_VFMADDSUBPS256,
26078 IX86_BUILTIN_VFMADDSUBPD256,
26080 /* FMA3 instructions. */
26081 IX86_BUILTIN_VFMADDSS3,
26082 IX86_BUILTIN_VFMADDSD3,
26084 /* XOP instructions. */
26085 IX86_BUILTIN_VPCMOV,
26086 IX86_BUILTIN_VPCMOV_V2DI,
26087 IX86_BUILTIN_VPCMOV_V4SI,
26088 IX86_BUILTIN_VPCMOV_V8HI,
26089 IX86_BUILTIN_VPCMOV_V16QI,
26090 IX86_BUILTIN_VPCMOV_V4SF,
26091 IX86_BUILTIN_VPCMOV_V2DF,
26092 IX86_BUILTIN_VPCMOV256,
26093 IX86_BUILTIN_VPCMOV_V4DI256,
26094 IX86_BUILTIN_VPCMOV_V8SI256,
26095 IX86_BUILTIN_VPCMOV_V16HI256,
26096 IX86_BUILTIN_VPCMOV_V32QI256,
26097 IX86_BUILTIN_VPCMOV_V8SF256,
26098 IX86_BUILTIN_VPCMOV_V4DF256,
26100 IX86_BUILTIN_VPPERM,
26102 IX86_BUILTIN_VPMACSSWW,
26103 IX86_BUILTIN_VPMACSWW,
26104 IX86_BUILTIN_VPMACSSWD,
26105 IX86_BUILTIN_VPMACSWD,
26106 IX86_BUILTIN_VPMACSSDD,
26107 IX86_BUILTIN_VPMACSDD,
26108 IX86_BUILTIN_VPMACSSDQL,
26109 IX86_BUILTIN_VPMACSSDQH,
26110 IX86_BUILTIN_VPMACSDQL,
26111 IX86_BUILTIN_VPMACSDQH,
26112 IX86_BUILTIN_VPMADCSSWD,
26113 IX86_BUILTIN_VPMADCSWD,
26115 IX86_BUILTIN_VPHADDBW,
26116 IX86_BUILTIN_VPHADDBD,
26117 IX86_BUILTIN_VPHADDBQ,
26118 IX86_BUILTIN_VPHADDWD,
26119 IX86_BUILTIN_VPHADDWQ,
26120 IX86_BUILTIN_VPHADDDQ,
26121 IX86_BUILTIN_VPHADDUBW,
26122 IX86_BUILTIN_VPHADDUBD,
26123 IX86_BUILTIN_VPHADDUBQ,
26124 IX86_BUILTIN_VPHADDUWD,
26125 IX86_BUILTIN_VPHADDUWQ,
26126 IX86_BUILTIN_VPHADDUDQ,
26127 IX86_BUILTIN_VPHSUBBW,
26128 IX86_BUILTIN_VPHSUBWD,
26129 IX86_BUILTIN_VPHSUBDQ,
26131 IX86_BUILTIN_VPROTB,
26132 IX86_BUILTIN_VPROTW,
26133 IX86_BUILTIN_VPROTD,
26134 IX86_BUILTIN_VPROTQ,
26135 IX86_BUILTIN_VPROTB_IMM,
26136 IX86_BUILTIN_VPROTW_IMM,
26137 IX86_BUILTIN_VPROTD_IMM,
26138 IX86_BUILTIN_VPROTQ_IMM,
26140 IX86_BUILTIN_VPSHLB,
26141 IX86_BUILTIN_VPSHLW,
26142 IX86_BUILTIN_VPSHLD,
26143 IX86_BUILTIN_VPSHLQ,
26144 IX86_BUILTIN_VPSHAB,
26145 IX86_BUILTIN_VPSHAW,
26146 IX86_BUILTIN_VPSHAD,
26147 IX86_BUILTIN_VPSHAQ,
26149 IX86_BUILTIN_VFRCZSS,
26150 IX86_BUILTIN_VFRCZSD,
26151 IX86_BUILTIN_VFRCZPS,
26152 IX86_BUILTIN_VFRCZPD,
26153 IX86_BUILTIN_VFRCZPS256,
26154 IX86_BUILTIN_VFRCZPD256,
26156 IX86_BUILTIN_VPCOMEQUB,
26157 IX86_BUILTIN_VPCOMNEUB,
26158 IX86_BUILTIN_VPCOMLTUB,
26159 IX86_BUILTIN_VPCOMLEUB,
26160 IX86_BUILTIN_VPCOMGTUB,
26161 IX86_BUILTIN_VPCOMGEUB,
26162 IX86_BUILTIN_VPCOMFALSEUB,
26163 IX86_BUILTIN_VPCOMTRUEUB,
26165 IX86_BUILTIN_VPCOMEQUW,
26166 IX86_BUILTIN_VPCOMNEUW,
26167 IX86_BUILTIN_VPCOMLTUW,
26168 IX86_BUILTIN_VPCOMLEUW,
26169 IX86_BUILTIN_VPCOMGTUW,
26170 IX86_BUILTIN_VPCOMGEUW,
26171 IX86_BUILTIN_VPCOMFALSEUW,
26172 IX86_BUILTIN_VPCOMTRUEUW,
26174 IX86_BUILTIN_VPCOMEQUD,
26175 IX86_BUILTIN_VPCOMNEUD,
26176 IX86_BUILTIN_VPCOMLTUD,
26177 IX86_BUILTIN_VPCOMLEUD,
26178 IX86_BUILTIN_VPCOMGTUD,
26179 IX86_BUILTIN_VPCOMGEUD,
26180 IX86_BUILTIN_VPCOMFALSEUD,
26181 IX86_BUILTIN_VPCOMTRUEUD,
26183 IX86_BUILTIN_VPCOMEQUQ,
26184 IX86_BUILTIN_VPCOMNEUQ,
26185 IX86_BUILTIN_VPCOMLTUQ,
26186 IX86_BUILTIN_VPCOMLEUQ,
26187 IX86_BUILTIN_VPCOMGTUQ,
26188 IX86_BUILTIN_VPCOMGEUQ,
26189 IX86_BUILTIN_VPCOMFALSEUQ,
26190 IX86_BUILTIN_VPCOMTRUEUQ,
26192 IX86_BUILTIN_VPCOMEQB,
26193 IX86_BUILTIN_VPCOMNEB,
26194 IX86_BUILTIN_VPCOMLTB,
26195 IX86_BUILTIN_VPCOMLEB,
26196 IX86_BUILTIN_VPCOMGTB,
26197 IX86_BUILTIN_VPCOMGEB,
26198 IX86_BUILTIN_VPCOMFALSEB,
26199 IX86_BUILTIN_VPCOMTRUEB,
26201 IX86_BUILTIN_VPCOMEQW,
26202 IX86_BUILTIN_VPCOMNEW,
26203 IX86_BUILTIN_VPCOMLTW,
26204 IX86_BUILTIN_VPCOMLEW,
26205 IX86_BUILTIN_VPCOMGTW,
26206 IX86_BUILTIN_VPCOMGEW,
26207 IX86_BUILTIN_VPCOMFALSEW,
26208 IX86_BUILTIN_VPCOMTRUEW,
26210 IX86_BUILTIN_VPCOMEQD,
26211 IX86_BUILTIN_VPCOMNED,
26212 IX86_BUILTIN_VPCOMLTD,
26213 IX86_BUILTIN_VPCOMLED,
26214 IX86_BUILTIN_VPCOMGTD,
26215 IX86_BUILTIN_VPCOMGED,
26216 IX86_BUILTIN_VPCOMFALSED,
26217 IX86_BUILTIN_VPCOMTRUED,
26219 IX86_BUILTIN_VPCOMEQQ,
26220 IX86_BUILTIN_VPCOMNEQ,
26221 IX86_BUILTIN_VPCOMLTQ,
26222 IX86_BUILTIN_VPCOMLEQ,
26223 IX86_BUILTIN_VPCOMGTQ,
26224 IX86_BUILTIN_VPCOMGEQ,
26225 IX86_BUILTIN_VPCOMFALSEQ,
26226 IX86_BUILTIN_VPCOMTRUEQ,
26228 /* LWP instructions. */
26229 IX86_BUILTIN_LLWPCB,
26230 IX86_BUILTIN_SLWPCB,
26231 IX86_BUILTIN_LWPVAL32,
26232 IX86_BUILTIN_LWPVAL64,
26233 IX86_BUILTIN_LWPINS32,
26234 IX86_BUILTIN_LWPINS64,
26236 IX86_BUILTIN_CLZS,
26238 /* RTM */
26239 IX86_BUILTIN_XBEGIN,
26240 IX86_BUILTIN_XEND,
26241 IX86_BUILTIN_XABORT,
26242 IX86_BUILTIN_XTEST,
26244 /* BMI instructions. */
26245 IX86_BUILTIN_BEXTR32,
26246 IX86_BUILTIN_BEXTR64,
26247 IX86_BUILTIN_CTZS,
26249 /* TBM instructions. */
26250 IX86_BUILTIN_BEXTRI32,
26251 IX86_BUILTIN_BEXTRI64,
26253 /* BMI2 instructions. */
26254 IX86_BUILTIN_BZHI32,
26255 IX86_BUILTIN_BZHI64,
26256 IX86_BUILTIN_PDEP32,
26257 IX86_BUILTIN_PDEP64,
26258 IX86_BUILTIN_PEXT32,
26259 IX86_BUILTIN_PEXT64,
26261 /* ADX instructions. */
26262 IX86_BUILTIN_ADDCARRYX32,
26263 IX86_BUILTIN_ADDCARRYX64,
26265 /* FSGSBASE instructions. */
26266 IX86_BUILTIN_RDFSBASE32,
26267 IX86_BUILTIN_RDFSBASE64,
26268 IX86_BUILTIN_RDGSBASE32,
26269 IX86_BUILTIN_RDGSBASE64,
26270 IX86_BUILTIN_WRFSBASE32,
26271 IX86_BUILTIN_WRFSBASE64,
26272 IX86_BUILTIN_WRGSBASE32,
26273 IX86_BUILTIN_WRGSBASE64,
26275 /* RDRND instructions. */
26276 IX86_BUILTIN_RDRAND16_STEP,
26277 IX86_BUILTIN_RDRAND32_STEP,
26278 IX86_BUILTIN_RDRAND64_STEP,
26280 /* RDSEED instructions. */
26281 IX86_BUILTIN_RDSEED16_STEP,
26282 IX86_BUILTIN_RDSEED32_STEP,
26283 IX86_BUILTIN_RDSEED64_STEP,
26285 /* F16C instructions. */
26286 IX86_BUILTIN_CVTPH2PS,
26287 IX86_BUILTIN_CVTPH2PS256,
26288 IX86_BUILTIN_CVTPS2PH,
26289 IX86_BUILTIN_CVTPS2PH256,
26291 /* CFString built-in for darwin */
26292 IX86_BUILTIN_CFSTRING,
26294 /* Builtins to get CPU type and supported features. */
26295 IX86_BUILTIN_CPU_INIT,
26296 IX86_BUILTIN_CPU_IS,
26297 IX86_BUILTIN_CPU_SUPPORTS,
26299 IX86_BUILTIN_MAX
26300 };
26302 /* Table for the ix86 builtin decls. */
26305 /* Table of all of the builtin functions that are possible with different ISA's
26306 but are waiting to be built until a function is declared to use that
26307 ISA. */
26314 };
26319 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26320 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26321 function decl in the ix86_builtins array. Returns the function decl or
26322 NULL_TREE, if the builtin was not added.
26324 If the front end has a special hook for builtin functions, delay adding
26325 builtin functions that aren't in the current ISA until the ISA is changed
26326 with function specific optimization. Doing so, can save about 300K for the
26327 default compiler. When the builtin is expanded, check at that time whether
26328 it is valid.
26330 If the front end doesn't have a special hook, record all builtins, even if
26331 it isn't an instruction set in the current ISA in case the user uses
26332 function specific options for a different ISA, so that we don't get scope
26333 errors if a builtin is added in the middle of a function scope. */
26339 {
26343 {
26352 {
26358 }
26359 else
26360 {
26366 }
26367 }
26370 }
26372 /* Like def_builtin, but also marks the function decl "const". */
26377 {
26381 else
26385 }
26387 /* Add any new builtin functions for a given ISA that may not have been
26388 declared. This saves a bit of space compared to adding all of the
26389 declarations to the tree, even if we didn't use them. */
26391 static void
26393 {
26397 {
26400 {
26403 /* Don't define the builtin again. */
26409 NULL_TREE);
26414 }
26415 }
26416 }
26418 /* Bits for builtin_description.flag. */
26420 /* Set when we don't support the comparison natively, and should
26421 swap_comparison in order to support it. */
26422 #define BUILTIN_DESC_SWAP_OPERANDS 1
26424 struct builtin_description
26425 {
26432 };
26435 {
26436 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26439 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26440 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26441 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26442 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26443 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26444 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26445 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26446 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26447 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26449 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26456 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26460 };
26463 {
26464 /* SSE4.2 */
26465 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26466 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26467 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26468 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26469 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26470 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26471 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26472 };
26475 {
26476 /* SSE4.2 */
26477 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26478 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26479 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26480 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26481 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26482 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26483 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26484 };
26486 /* Special builtins with variable number of arguments. */
26488 {
26489 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26490 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26491 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26493 /* MMX */
26494 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26496 /* 3DNow! */
26497 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26499 /* FXSR, XSAVE and XSAVEOPT */
26500 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26501 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26502 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26503 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26504 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26506 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26507 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26508 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26509 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26510 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26512 /* SSE */
26513 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26514 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26515 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26517 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26518 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26519 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26520 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26522 /* SSE or 3DNow!A */
26523 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26524 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26526 /* SSE2 */
26527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26532 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26534 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26541 /* SSE3 */
26542 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26544 /* SSE4.1 */
26545 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26547 /* SSE4A */
26548 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26549 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26551 /* AVX */
26552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26555 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26556 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26557 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26582 /* AVX2 */
26583 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26584 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26585 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26586 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26587 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26588 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26589 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26590 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26591 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26593 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26594 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26595 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26596 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26597 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26598 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26600 /* FSGSBASE */
26601 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26602 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26603 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26604 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26605 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26606 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26607 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26608 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26610 /* RTM */
26611 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26612 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26613 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26614 };
26616 /* Builtins with variable number of arguments. */
26618 {
26619 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26620 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26621 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26622 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26623 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26624 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26625 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26627 /* MMX */
26628 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26629 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26630 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26631 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26632 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26633 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26635 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26636 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26637 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26638 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26639 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26640 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26641 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26642 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26644 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26645 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26647 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26648 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26649 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26650 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26652 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26653 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26654 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26655 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26656 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26657 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26659 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26660 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26661 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26662 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26663 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
26664 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
26666 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
26667 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
26668 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
26670 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
26672 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
26673 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
26674 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
26675 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
26676 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
26677 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
26679 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
26680 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
26681 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
26682 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
26683 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
26684 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
26686 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
26687 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
26688 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
26689 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
26691 /* 3DNow! */
26692 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
26693 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
26694 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
26695 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
26697 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26698 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26699 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26700 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
26701 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
26702 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
26703 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26704 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26705 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26706 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26707 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26708 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26709 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26710 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26711 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26713 /* 3DNow!A */
26714 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
26715 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
26716 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
26717 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
26718 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26719 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
26721 /* SSE */
26722 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
26723 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26724 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26725 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26726 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26727 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26728 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
26729 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
26730 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
26731 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
26732 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
26733 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
26735 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
26737 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26738 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26739 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26740 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26741 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26742 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26744 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26746 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
26747 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
26748 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
26749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26750 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
26752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
26753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
26754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
26755 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26756 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
26757 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
26758 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
26759 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
26760 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
26761 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
26762 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
26763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
26764 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
26765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
26767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
26769 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26770 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26774 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26775 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26776 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26777 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26779 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26781 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26782 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26783 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26784 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26785 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26787 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
26788 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
26789 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
26791 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
26793 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
26794 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
26795 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
26797 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
26798 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
26800 /* SSE MMX or 3Dnow!A */
26801 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26802 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26803 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26805 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26806 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26807 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26808 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26810 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
26811 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
26813 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
26815 /* SSE2 */
26816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
26818 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
26819 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
26820 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
26821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
26822 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
26824 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
26825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
26826 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
26827 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
26828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
26830 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
26832 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
26833 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
26834 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
26835 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
26837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
26838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
26839 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
26841 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26842 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26843 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26844 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
26851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
26852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
26853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
26854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
26855 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
26856 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
26857 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
26858 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
26859 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
26860 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
26861 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
26862 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
26863 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
26864 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
26865 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
26866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
26867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
26868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
26869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
26871 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26872 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26876 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26878 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26879 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26881 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26884 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26885 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26887 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
26889 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26890 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26891 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26892 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26893 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26894 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26895 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26896 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26898 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26899 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26901 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26902 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26903 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26907 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26908 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
26910 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26911 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26912 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26913 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26915 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26916 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26920 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26921 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26922 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26925 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26926 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26927 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26928 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26930 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26931 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26932 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26933 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26934 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
26935 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26936 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
26937 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
26939 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
26940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
26941 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
26943 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
26944 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
26946 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
26947 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
26949 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
26951 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
26952 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
26953 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
26954 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
26956 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
26957 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
26958 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
26959 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
26960 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
26961 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
26962 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
26964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
26965 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
26966 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
26967 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
26968 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
26969 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
26970 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
26972 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
26973 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
26974 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
26975 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
26977 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
26978 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
26979 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
26981 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
26983 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
26985 /* SSE2 MMX */
26986 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
26987 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
26989 /* SSE3 */
26990 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
26991 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
26993 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26994 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26995 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26996 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
26997 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
26998 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27000 /* SSSE3 */
27001 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27002 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27003 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27004 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27005 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27006 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27008 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27009 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27010 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27011 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27012 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27013 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27014 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27015 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27016 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27017 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27018 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27019 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27020 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27021 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27022 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27023 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27024 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27025 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27026 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27027 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27028 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27029 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27030 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27031 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27033 /* SSSE3. */
27034 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27035 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27037 /* SSE4.1 */
27038 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27039 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27040 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27041 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27042 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27043 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27044 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27045 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27046 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27047 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27049 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27050 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27051 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27052 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27053 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27054 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27055 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27056 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27057 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27058 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27059 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27060 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27061 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27063 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27064 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27065 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27066 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27067 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27068 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27069 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27070 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27071 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27072 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27073 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27074 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27076 /* SSE4.1 */
27077 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27078 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27079 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27080 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27082 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27083 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27084 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27085 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27087 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27088 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27090 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27091 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27093 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27094 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27095 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27096 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27098 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27099 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27101 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27102 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27104 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27105 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27106 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27108 /* SSE4.2 */
27109 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27110 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27111 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27112 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27113 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27115 /* SSE4A */
27116 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27117 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27118 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27119 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27121 /* AES */
27122 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27123 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27125 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27126 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27127 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27128 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27130 /* PCLMUL */
27131 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27133 /* AVX */
27134 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27135 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27138 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27139 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27140 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27141 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27142 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27143 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27144 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27145 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27146 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27147 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27148 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27149 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27150 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27151 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27152 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27153 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27154 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27155 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27156 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27157 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27158 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27159 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27161 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27162 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27163 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27164 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27166 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27167 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27168 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27169 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27170 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27171 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27172 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27173 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27174 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27175 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27176 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27177 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27178 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27179 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27180 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27182 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27183 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27184 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27185 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27186 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27187 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27188 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27189 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27190 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27191 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27192 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27193 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27194 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27195 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27196 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27197 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27198 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27199 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27202 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27203 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27205 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27207 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27208 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27209 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27211 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27213 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27214 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27216 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27217 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27218 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27219 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27221 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27222 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27224 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27225 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27227 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27228 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27229 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27230 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27232 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27233 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27235 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27236 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27238 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27239 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27240 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27241 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27243 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27244 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27245 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27246 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27247 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27248 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27250 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27251 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27252 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27253 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27254 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27255 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27256 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27257 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27258 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27259 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27260 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27261 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27262 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27263 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27264 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27266 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27267 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27269 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27270 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27272 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27274 /* AVX2 */
27275 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27276 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27277 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27278 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27279 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27280 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27281 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27282 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27283 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27284 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27285 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27286 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27287 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27288 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27289 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27290 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27291 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27292 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27293 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27294 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27295 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27296 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27297 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27298 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27299 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27300 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27301 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27302 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27303 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27304 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27305 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27306 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27307 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27308 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27309 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27310 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27311 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27312 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27313 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27314 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27315 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27316 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27317 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27318 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27319 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27320 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27321 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27322 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27323 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27324 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27325 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27326 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27327 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27328 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27329 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27330 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27331 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27332 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27333 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27334 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27335 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27336 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27337 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27338 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27339 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27340 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27341 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27342 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27343 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27344 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27345 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27346 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27347 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27348 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27349 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27350 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27351 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27352 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27353 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27354 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27355 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27356 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27357 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27358 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27359 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27360 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27361 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27362 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27363 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27364 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27365 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27366 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27367 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27368 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27369 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27370 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27371 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27372 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27373 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27374 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27375 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27376 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27377 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27378 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27379 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27380 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27381 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27382 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27383 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27384 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27385 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27386 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27387 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27388 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27389 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27390 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27391 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27392 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27393 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27394 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27395 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27396 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27397 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27398 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27399 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27400 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27401 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27402 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27403 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27404 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27405 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27406 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27407 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27408 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27409 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27410 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27411 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27412 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27413 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27414 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27415 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27416 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27417 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27418 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27419 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27420 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27422 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27424 /* BMI */
27425 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27426 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27427 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27429 /* TBM */
27430 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27431 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27433 /* F16C */
27434 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27435 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27436 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27437 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27439 /* BMI2 */
27440 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27441 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27442 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27443 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27444 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27445 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27446 };
27448 /* FMA4 and XOP. */
27449 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27450 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27451 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27452 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27453 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27454 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27455 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27456 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27457 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27458 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27459 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27460 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27461 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27462 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27463 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27464 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27465 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27466 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27467 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27468 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27469 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27470 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27471 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27472 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27473 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27474 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27475 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27476 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27477 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27478 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27479 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27480 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27481 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27482 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27483 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27484 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27485 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27486 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27487 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27488 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27489 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27490 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27491 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27492 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27493 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27494 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27495 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27496 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27497 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27498 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27499 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27500 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27503 {
27544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
27593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27617 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27620 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27621 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27625 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27626 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
27628 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
27629 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
27631 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
27632 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27633 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27634 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
27635 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
27636 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
27637 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
27639 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27640 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27641 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
27642 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
27643 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
27644 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
27645 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
27647 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
27648 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
27649 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
27650 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
27651 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
27652 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
27653 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
27655 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
27656 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
27657 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
27658 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
27659 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
27660 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
27661 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
27663 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
27664 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
27665 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
27666 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
27667 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
27668 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
27669 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
27671 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
27672 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
27673 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
27674 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
27675 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
27676 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
27677 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
27679 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
27680 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
27681 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
27682 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
27683 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
27684 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
27685 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
27686 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
27688 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
27689 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
27690 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
27691 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
27692 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
27693 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
27694 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
27695 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
27697 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
27698 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
27699 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
27700 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
27702 };
27703 \f
27704 /* TM vector builtins. */
27706 /* Reuse the existing x86-specific `struct builtin_description' cause
27707 we're lazy. Add casts to make them fit. */
27709 {
27710 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
27711 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
27712 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
27713 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
27714 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
27715 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
27716 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
27718 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
27719 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
27720 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
27721 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
27722 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
27723 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
27724 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
27726 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
27727 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
27728 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
27729 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
27730 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
27731 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
27732 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
27734 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
27735 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
27736 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
27737 };
27739 /* TM callbacks. */
27741 /* Return the builtin decl needed to load a vector of TYPE. */
27743 static tree
27745 {
27747 {
27749 {
27756 }
27757 }
27759 }
27761 /* Return the builtin decl needed to store a vector of TYPE. */
27763 static tree
27765 {
27767 {
27769 {
27776 }
27777 }
27779 }
27780 \f
27781 /* Initialize the transactional memory vector load/store builtins. */
27783 static void
27785 {
27789 tree decl;
27796 /* If there are no builtins defined, we must be compiling in a
27797 language without trans-mem support. */
27801 /* Use whatever attributes a normal TM load has. */
27805 /* Use whatever attributes a normal TM store has. */
27809 /* Use whatever attributes a normal TM log has. */
27817 {
27821 {
27829 {
27832 }
27834 {
27837 }
27838 else
27839 {
27842 }
27844 /* The builtin without the prefix for
27845 calling it directly. */
27847 attrs);
27848 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
27849 set the TYPE_ATTRIBUTES. */
27853 }
27854 }
27855 }
27857 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
27858 in the current target ISA to allow the user to compile particular modules
27859 with different target specific options that differ from the command line
27860 options. */
27861 static void
27863 {
27868 /* Add all special builtins with variable number of operands. */
27872 {
27878 }
27880 /* Add all builtins with variable number of operands. */
27884 {
27890 }
27892 /* pcmpestr[im] insns. */
27896 {
27899 else
27902 }
27904 /* pcmpistr[im] insns. */
27908 {
27911 else
27914 }
27916 /* comi/ucomi insns. */
27918 {
27921 else
27924 }
27926 /* SSE */
27932 /* SSE or 3DNow!A */
27935 IX86_BUILTIN_MASKMOVQ);
27937 /* SSE2 */
27946 /* SSE3. */
27952 /* AES */
27966 /* PCLMUL */
27970 /* RDRND */
27977 IX86_BUILTIN_RDRAND64_STEP);
27979 /* AVX2 */
27981 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
27982 IX86_BUILTIN_GATHERSIV2DF);
27985 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
27986 IX86_BUILTIN_GATHERSIV4DF);
27989 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
27990 IX86_BUILTIN_GATHERDIV2DF);
27993 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
27994 IX86_BUILTIN_GATHERDIV4DF);
27997 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
27998 IX86_BUILTIN_GATHERSIV4SF);
28001 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28002 IX86_BUILTIN_GATHERSIV8SF);
28005 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28006 IX86_BUILTIN_GATHERDIV4SF);
28009 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28010 IX86_BUILTIN_GATHERDIV8SF);
28013 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28014 IX86_BUILTIN_GATHERSIV2DI);
28017 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28018 IX86_BUILTIN_GATHERSIV4DI);
28021 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28022 IX86_BUILTIN_GATHERDIV2DI);
28025 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28026 IX86_BUILTIN_GATHERDIV4DI);
28029 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28030 IX86_BUILTIN_GATHERSIV4SI);
28033 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28034 IX86_BUILTIN_GATHERSIV8SI);
28037 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28038 IX86_BUILTIN_GATHERDIV4SI);
28041 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28042 IX86_BUILTIN_GATHERDIV8SI);
28045 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28046 IX86_BUILTIN_GATHERALTSIV4DF);
28049 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28050 IX86_BUILTIN_GATHERALTDIV8SF);
28053 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28054 IX86_BUILTIN_GATHERALTSIV4DI);
28057 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28058 IX86_BUILTIN_GATHERALTDIV8SI);
28060 /* RTM. */
28064 /* MMX access to the vec_init patterns. */
28069 V4HI_FTYPE_HI_HI_HI_HI,
28070 IX86_BUILTIN_VEC_INIT_V4HI);
28073 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28074 IX86_BUILTIN_VEC_INIT_V8QI);
28076 /* Access to the vec_extract patterns. */
28098 /* Access to the vec_set patterns. */
28119 /* RDSEED */
28128 /* ADCX */
28133 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28134 IX86_BUILTIN_ADDCARRYX64);
28136 /* Add FMA4 multi-arg argument instructions */
28138 {
28144 }
28145 }
28147 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28148 to return a pointer to VERSION_DECL if the outcome of the expression
28149 formed by PREDICATE_CHAIN is true. This function will be called during
28150 version dispatch to decide which function version to execute. It returns
28151 the basic block at the end, to which more conditions can be added. */
28153 static basic_block
28156 {
28157 gimple return_stmt;
28159 gimple convert_stmt;
28160 gimple call_cond_stmt;
28161 gimple if_else_stmt;
28167 gimple_seq gseq;
28184 {
28192 }
28195 {
28210 else
28211 {
28212 gimple assign_stmt;
28213 /* Use MIN_EXPR to check if any integer is zero?.
28214 and_expr_var = min_expr <cond_var, and_expr_var> */
28222 }
28223 }
28226 integer_zero_node,
28256 }
28258 /* This parses the attribute arguments to target in DECL and determines
28259 the right builtin to use to match the platform specification.
28260 It returns the priority value for this version decl. If PREDICATE_LIST
28261 is not NULL, it stores the list of cpu features that need to be checked
28262 before dispatching this function. */
28264 static unsigned int
28266 {
28267 tree attrs;
28269 tree target_node;
28276 /* Priority of i386 features, greater value is higher priority. This is
28277 used to decide the order in which function dispatch must happen. For
28278 instance, a version specialized for SSE4.2 should be checked for dispatch
28279 before a version for SSE3, as SSE4.2 implies SSE3. */
28280 enum feature_priority
28281 {
28283 P_MMX,
28284 P_SSE,
28285 P_SSE2,
28286 P_SSE3,
28287 P_SSSE3,
28288 P_PROC_SSSE3,
28289 P_SSE4_a,
28290 P_PROC_SSE4_a,
28291 P_SSE4_1,
28292 P_SSE4_2,
28293 P_PROC_SSE4_2,
28294 P_POPCNT,
28295 P_AVX,
28296 P_AVX2,
28297 P_FMA,
28298 P_PROC_FMA
28299 };
28303 /* These are the target attribute strings for which a dispatcher is
28304 available, from fold_builtin_cpu. */
28306 static struct _feature_list
28307 {
28310 }
28312 {
28323 };
28326 static unsigned int NUM_FEATURES
28343 /* Handle arch= if specified. For priority, set it to be 1 more than
28344 the best instruction set the processor can handle. For instance, if
28345 there is a version for atom and a version for ssse3 (the highest ISA
28346 priority for atom), the atom version must be checked for dispatch
28347 before the ssse3 version. */
28349 {
28358 {
28360 {
28387 }
28388 }
28393 {
28397 }
28400 {
28402 /* For a C string literal the length includes the trailing NULL. */
28405 predicate_chain);
28406 }
28407 }
28409 /* Process feature name. */
28416 {
28417 /* Do not process "arch=" */
28419 {
28422 }
28424 {
28426 {
28428 {
28433 predicate_chain);
28434 }
28435 /* Find the maximum priority feature. */
28440 }
28441 }
28443 {
28447 }
28449 }
28453 {
28456 attrs_str);
28458 }
28460 {
28463 }
28466 }
28468 /* This compares the priority of target features in function DECL1
28469 and DECL2. It returns positive value if DECL1 is higher priority,
28470 negative value if DECL2 is higher priority and 0 if they are the
28471 same. */
28473 static int
28475 {
28486 }
28488 /* V1 and V2 point to function versions with different priorities
28489 based on the target ISA. This function compares their priorities. */
28491 static int
28493 {
28495 {
28496 tree version_decl;
28497 tree predicate_chain;
28504 }
28506 /* This function generates the dispatch function for
28507 multi-versioned functions. DISPATCH_DECL is the function which will
28508 contain the dispatch logic. FNDECLS are the function choices for
28509 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28510 in DISPATCH_DECL in which the dispatch code is generated. */
28512 static int
28516 {
28517 tree default_decl;
28518 gimple ifunc_cpu_init_stmt;
28519 gimple_seq gseq;
28521 tree ele;
28527 struct _function_version_info
28528 {
28529 tree version_decl;
28530 tree predicate_chain;
28538 /*fndecls_p is actually a vector. */
28541 /* At least one more version other than the default. */
28548 /* The first version in the vector is the default decl. */
28554 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28555 constructors, so explicity call __builtin_cpu_init here. */
28566 {
28570 /* Get attribute string, parse it and find the right predicate decl.
28571 The predicate function could be a lengthy combination of many
28572 features, like arch-type and various isa-variants. */
28579 actual_versions++;
28583 }
28585 /* Sort the versions according to descending order of dispatch priority. The
28586 priority is based on the ISA. This is not a perfect solution. There
28587 could still be ambiguity. If more than one function version is suitable
28588 to execute, which one should be dispatched? In future, allow the user
28589 to specify a dispatch priority next to the version. */
28599 /* dispatch default version at the end. */
28605 }
28607 /* This function returns true if FN1 and FN2 are versions of the same function,
28608 that is, the targets of the function decls are different. This assumes
28609 that FN1 and FN2 have the same signature. */
28611 static bool
28613 {
28624 /* Atleast one function decl should have target attribute specified. */
28636 /* target1 and target2 must be different in some way. */
28646 }
28648 /* Comparator function to be used in qsort routine to sort attribute
28649 specification strings to "target". */
28651 static int
28653 {
28657 }
28659 /* STR is the argument to target attribute. This function tokenizes
28660 the comma separated arguments, sorts them and returns a string which
28661 is a unique identifier for the comma separated arguments. It also
28662 replaces non-identifier characters "=,-" with "_". */
28666 {
28675 argnum++;
28680 /* Replace "=,-" with "_". */
28693 {
28695 i++;
28697 }
28704 {
28707 }
28712 }
28714 /* This function changes the assembler name for functions that are
28715 versions. If DECL is a function version and has a "target"
28716 attribute, it appends the attribute string to its assembler name. */
28718 static tree
28720 {
28721 tree version_attr;
28729 "Function versions cannot be marked as gnu_inline,"
28739 /* target attribute string is NULL for default functions. */
28744 version_string
28753 /* Allow assembler name to be modified if already set. */
28758 }
28760 static tree
28762 {
28763 /* For function version, add the target suffix to the assembler name. */
28769 }
28771 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
28772 is true, append the full path name of the source file. */
28776 {
28784 /* Get a unique name that can be used globally without any chances
28785 of collision at link time. */
28795 /* Use '.' to concatenate names as it is demangler friendly. */
28799 else
28803 }
28805 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
28807 /* Make a dispatcher declaration for the multi-versioned function DECL.
28808 Calls to DECL function will be replaced with calls to the dispatcher
28809 by the front-end. Return the decl created. */
28811 static tree
28813 {
28814 tree func_decl;
28835 /* Mark this func as external, the resolver will flip it again if
28836 it gets generated. */
28838 /* This will be of type IFUNCs have to be externally visible. */
28842 }
28844 #endif
28846 /* Returns true if decl is multi-versioned and DECL is the default function,
28847 that is it is not tagged with target specific optimization. */
28849 static bool
28851 {
28855 }
28857 /* Make a dispatcher declaration for the multi-versioned function DECL.
28858 Calls to DECL function will be replaced with calls to the dispatcher
28859 by the front-end. Returns the decl of the dispatcher function. */
28861 static tree
28863 {
28888 /* Find the default version and make it the first node. */
28890 /* Go to the beginnig of the chain. */
28895 {
28900 }
28902 /* If there is no default node, just return NULL. */
28906 /* Make default info the first node. */
28908 {
28915 }
28919 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
28920 /* Right now, the dispatching is done via ifunc. */
28922 #else
28924 "Multiversioning needs ifunc which is not supported "
28926 #endif
28931 dispatcher_version_info
28936 /* Set the dispatcher for all the versions. */
28939 {
28942 }
28945 }
28947 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
28948 it to CHAIN. */
28950 static tree
28952 {
28953 tree attr_name;
28954 tree attr_arg_name;
28955 tree attr_args;
28956 tree attr;
28963 }
28965 /* Make the resolver function decl to dispatch the versions of
28966 a multi-versioned function, DEFAULT_DECL. Create an
28967 empty basic block in the resolver and store the pointer in
28968 EMPTY_BB. Return the decl of the resolver function. */
28970 static tree
28974 {
28979 /* IFUNC's have to be globally visible. So, if the default_decl is
28980 not, then the name of the IFUNC should be made unique. */
28984 /* Append the filename to the resolver function if the versions are
28985 not externally visible. This is because the resolver function has
28986 to be externally visible for the loader to find it. So, appending
28987 the filename will prevent conflicts with a resolver function from
28988 another module which is based on the same version name. */
28991 /* The resolver function should return a (void *). */
29002 /* IFUNC resolvers have to be externally visible. */
29006 /* Resolver is not external, body is generated. */
29016 {
29017 /* In this case, each translation unit with a call to this
29018 versioned function will put out a resolver. Ensure it
29019 is comdat to keep just one copy. */
29022 }
29023 /* Build result decl and add to function_decl. */
29039 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29043 /* Create the alias for dispatch to resolver here. */
29044 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29047 }
29049 /* Generate the dispatching code body to dispatch multi-versioned function
29050 DECL. The target hook is called to process the "target" attributes and
29051 provide the code to dispatch the right function at run-time. NODE points
29052 to the dispatcher decl whose body will be created. */
29054 static tree
29056 {
29057 tree resolver_decl;
29058 basic_block empty_bb;
29060 tree default_ver_decl;
29076 /* The first version in the chain corresponds to the default version. */
29079 /* node is going to be an alias, so remove the finalized bit. */
29093 {
29095 /* Check for virtual functions here again, as by this time it should
29096 have been determined if this function needs a vtable index or
29097 not. This happens for methods in derived classes that override
29098 virtual methods in base classes but are not explicitly marked as
29099 virtual. */
29104 }
29111 }
29112 /* This builds the processor_model struct type defined in
29113 libgcc/config/i386/cpuinfo.c */
29115 static tree
29117 {
29124 /* The first 3 fields are unsigned int. */
29126 {
29132 }
29134 /* The last field is an array of unsigned integers of size one. */
29145 }
29147 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29149 static tree
29151 {
29152 tree new_decl;
29155 VAR_DECL,
29157 type);
29170 }
29172 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29173 into an integer defined in libgcc/config/i386/cpuinfo.c */
29175 static tree
29177 {
29183 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29184 enum processor_features
29185 {
29187 F_MMX,
29188 F_POPCNT,
29189 F_SSE,
29190 F_SSE2,
29191 F_SSE3,
29192 F_SSSE3,
29193 F_SSE4_1,
29194 F_SSE4_2,
29195 F_AVX,
29196 F_AVX2,
29197 F_MAX
29198 };
29200 /* These are the values for vendor types and cpu types and subtypes
29201 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29202 the corresponding start value. */
29203 enum processor_model
29204 {
29206 M_AMD,
29207 M_CPU_TYPE_START,
29208 M_INTEL_ATOM,
29209 M_INTEL_CORE2,
29210 M_INTEL_COREI7,
29211 M_AMDFAM10H,
29212 M_AMDFAM15H,
29213 M_CPU_SUBTYPE_START,
29214 M_INTEL_COREI7_NEHALEM,
29215 M_INTEL_COREI7_WESTMERE,
29216 M_INTEL_COREI7_SANDYBRIDGE,
29217 M_AMDFAM10H_BARCELONA,
29218 M_AMDFAM10H_SHANGHAI,
29219 M_AMDFAM10H_ISTANBUL,
29220 M_AMDFAM15H_BDVER1,
29221 M_AMDFAM15H_BDVER2
29222 };
29224 static struct _arch_names_table
29225 {
29228 }
29230 {
29246 };
29248 static struct _isa_names_table
29249 {
29252 }
29254 {
29266 };
29283 {
29284 /* *args must be a expr that can contain other EXPRS leading to a
29285 STRING_CST. */
29287 {
29290 }
29292 }
29297 {
29298 tree ref;
29299 tree field;
29300 tree final;
29303 unsigned int NUM_ARCH_NAMES
29312 {
29316 }
29321 /* CPU types are stored in the next field. */
29324 {
29327 }
29329 /* CPU subtypes are stored in the next field. */
29331 {
29334 }
29336 /* Get the appropriate field in __cpu_model. */
29340 /* Check the value. */
29344 }
29346 {
29347 tree ref;
29348 tree array_elt;
29349 tree field;
29350 tree final;
29353 unsigned int NUM_ISA_NAMES
29362 {
29366 }
29369 /* Get the last field, which is __cpu_features. */
29373 /* Get the appropriate field: __cpu_model.__cpu_features */
29377 /* Access the 0th element of __cpu_features array. */
29382 /* Return __cpu_model.__cpu_features[0] & field_val */
29386 }
29388 }
29390 static tree
29393 {
29395 {
29400 {
29403 }
29404 }
29406 #ifdef SUBTARGET_FOLD_BUILTIN
29408 #endif
29411 }
29413 /* Make builtins to detect cpu type and features supported. NAME is
29414 the builtin name, CODE is the builtin code, and FTYPE is the function
29415 type of the builtin. */
29417 static void
29420 {
29421 tree decl;
29422 tree type;
29430 }
29432 /* Make builtins to get CPU type and features supported. The created
29433 builtins are :
29435 __builtin_cpu_init (), to detect cpu type and features,
29436 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29437 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29438 */
29440 static void
29442 {
29449 }
29451 /* Internal method for ix86_init_builtins. */
29453 static void
29455 {
29467 sysv_va_ref =
29470 fnvoid_va_end_ms =
29472 fnvoid_va_start_ms =
29474 fnvoid_va_end_sysv =
29476 fnvoid_va_start_sysv =
29478 NULL_TREE);
29479 fnvoid_va_copy_ms =
29481 NULL_TREE);
29482 fnvoid_va_copy_sysv =
29498 }
29500 static void
29502 {
29505 /* The __float80 type. */
29508 {
29509 /* The __float80 type. */
29514 }
29517 /* The __float128 type. */
29523 /* This macro is built by i386-builtin-types.awk. */
29524 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29525 }
29527 static void
29529 {
29530 tree t;
29534 /* Builtins to get CPU type and features. */
29537 /* TFmode support builtins. */
29543 /* We will expand them to normal call if SSE isn't available since
29544 they are used by libgcc. */
29563 #ifdef SUBTARGET_INIT_BUILTINS
29564 SUBTARGET_INIT_BUILTINS;
29565 #endif
29566 }
29568 /* Return the ix86 builtin for CODE. */
29570 static tree
29572 {
29577 }
29579 /* Errors in the source file can cause expand_expr to return const0_rtx
29580 where we expect a vector. To avoid crashing, use one of the vector
29581 clear instructions. */
29582 static rtx
29584 {
29588 }
29590 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
29592 static rtx
29594 {
29595 rtx pat;
29615 {
29619 }
29633 }
29635 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
29637 static rtx
29641 {
29642 rtx pat;
29650 rtx op;
29657 {
29737 }
29747 {
29754 {
29756 {
29759 {
29777 xop_rotl:
29779 {
29782 gcc_checking_assert
29784 }
29785 else
29786 {
29787 gcc_checking_assert
29798 }
29802 }
29803 }
29804 }
29805 else
29806 {
29807 non_constant:
29811 /* If we aren't optimizing, only allow one memory operand to be
29812 generated. */
29814 num_memory++;
29822 }
29826 }
29829 {
29840 else
29841 {
29847 }
29860 }
29867 }
29869 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
29870 insns with vec_merge. */
29872 static rtx
29874 rtx target)
29875 {
29876 rtx pat;
29903 }
29905 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
29907 static rtx
29910 {
29911 rtx pat;
29916 rtx op2;
29927 /* Swap operands if we have a comparison that isn't available in
29928 hardware. */
29930 {
29935 }
29955 }
29957 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
29959 static rtx
29961 rtx target)
29962 {
29963 rtx pat;
29977 /* Swap operands if we have a comparison that isn't available in
29978 hardware. */
29980 {
29984 }
30005 const0_rtx)));
30008 }
30010 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30012 static rtx
30014 rtx target)
30015 {
30016 rtx pat;
30041 }
30043 static rtx
30046 {
30047 rtx pat;
30052 rtx op2;
30079 }
30081 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30083 static rtx
30085 rtx target)
30086 {
30087 rtx pat;
30120 const0_rtx)));
30123 }
30125 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30127 static rtx
30130 {
30131 rtx pat;
30169 {
30172 }
30175 {
30184 }
30186 {
30195 }
30196 else
30197 {
30204 }
30212 {
30217 emit_insn
30221 FLAGS_REG),
30222 const0_rtx)));
30224 }
30225 else
30227 }
30230 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30232 static rtx
30235 {
30236 rtx pat;
30264 {
30267 }
30270 {
30279 }
30281 {
30290 }
30291 else
30292 {
30299 }
30307 {
30312 emit_insn
30316 FLAGS_REG),
30317 const0_rtx)));
30319 }
30320 else
30322 }
30324 /* Subroutine of ix86_expand_builtin to take care of insns with
30325 variable number of operands. */
30327 static rtx
30330 {
30335 struct
30336 {
30337 rtx op;
30349 {
30628 }
30633 {
30636 }
30639 {
30646 }
30647 else
30648 {
30651 }
30654 {
30661 {
30662 /* SIMD shift insns take either an 8-bit immediate or
30663 register as count. But builtin functions take int as
30664 count. If count doesn't match, we put it in register. */
30666 {
30670 }
30671 }
30673 {
30676 {
30730 {
30733 {
30736 }
30742 }
30744 }
30745 }
30746 else
30747 {
30751 /* If we aren't optimizing, only allow one memory operand to
30752 be generated. */
30754 num_memory++;
30757 {
30760 }
30761 else
30762 {
30765 }
30766 }
30770 }
30773 {
30790 }
30797 }
30799 /* Subroutine of ix86_expand_builtin to take care of special insns
30800 with variable number of operands. */
30802 static rtx
30805 {
30806 tree arg;
30809 struct
30810 {
30811 rtx op;
30821 {
30869 /* Reserve memory operand for target. */
30900 /* Reserve memory operand for target. */
30914 }
30919 {
30924 {
30928 }
30929 else
30932 }
30933 else
30934 {
30941 }
30944 {
30953 {
30955 {
30961 else
30964 }
30965 }
30966 else
30967 {
30969 {
30970 /* This must be the memory operand. */
30976 }
30977 else
30978 {
30979 /* This must be register. */
30986 }
30987 }
30991 }
30994 {
31009 }
31015 }
31017 /* Return the integer constant in ARG. Constrain it to be in the range
31018 of the subparts of VEC_TYPE; issue an error if not. */
31020 static int
31022 {
31027 {
31030 }
31033 }
31035 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31036 ix86_expand_vector_init. We DO have language-level syntax for this, in
31037 the form of (type){ init-list }. Except that since we can't place emms
31038 instructions from inside the compiler, we can't allow the use of MMX
31039 registers unless the user explicitly asks for it. So we do *not* define
31040 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31041 we have builtins invoked by mmintrin.h that gives us license to emit
31042 these sorts of instructions. */
31044 static rtx
31046 {
31056 {
31059 }
31066 }
31068 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31069 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31070 had a language-level syntax for referencing vector elements. */
31072 static rtx
31074 {
31078 rtx op0;
31098 }
31100 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31101 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31102 a language-level syntax for referencing vector elements. */
31104 static rtx
31106 {
31130 /* OP0 is the source of these builtin functions and shouldn't be
31131 modified. Create a copy, use it and return it as target. */
31137 }
31139 /* Expand an expression EXP that calls a built-in function,
31140 with result going to TARGET if that's convenient
31141 (and in mode MODE if that's convenient).
31142 SUBTARGET may be used as the target for computing one of EXP's operands.
31143 IGNORE is nonzero if the value is to be ignored. */
31145 static rtx
31149 {
31159 /* For CPU builtins that can be folded, fold first and expand the fold. */
31161 {
31163 {
31164 /* Make it call __cpu_indicator_init in libgcc. */
31170 }
31173 {
31178 }
31179 }
31181 /* Determine whether the builtin function is available under the current ISA.
31182 Originally the builtin was not created if it wasn't applicable to the
31183 current ISA based on the command line switches. With function specific
31184 options, we need to check in the context of the function making the call
31185 whether it is supported. */
31188 {
31194 else
31195 {
31199 }
31201 }
31204 {
31208 ? CODE_FOR_mmx_maskmovq
31210 /* Note the arg order is different from the operand order. */
31254 {
31258 }
31271 {
31275 }
31320 {
31321 REAL_VALUE_TYPE inf;
31322 rtx tmp;
31334 }
31344 {
31350 insn = (TARGET_64BIT
31354 }
31356 {
31357 insn = (TARGET_64BIT
31361 }
31362 else
31363 {
31366 insn = (TARGET_64BIT
31374 {
31377 }
31379 }
31385 {
31390 }
31400 {
31415 }
31421 {
31424 }
31444 {
31447 }
31453 {
31457 {
31478 }
31483 }
31484 else
31485 {
31487 {
31499 }
31501 }
31512 {
31516 }
31535 ? CODE_FOR_tbm_bextri_si
31538 {
31541 }
31542 else
31543 {
31552 }
31568 rdrand_step:
31575 {
31578 }
31584 /* Emit SImode conditional move. */
31586 {
31589 }
31592 else
31599 const0_rtx);
31618 rdseed_step:
31625 {
31628 }
31634 const0_rtx);
31652 addcarryx:
31660 /* Generate CF from input operand. */
31667 /* Gen ADCX instruction to compute X+Y+CF. */
31682 /* Store the result. */
31685 {
31688 }
31691 /* Return current CF value. */
31760 gather_gen:
31771 /* Note the arg order is different from the operand order. */
31780 else
31785 {
31791 }
31794 {
31799 else
31809 }
31811 /* Force memory operand only with base register here. But we
31812 don't want to do it on memory operand for other builtin
31813 functions. */
31827 {
31830 }
31832 /* Optimize. If mask is known to have all high bits set,
31833 replace op0 with pc_rtx to signal that the instruction
31834 overwrites the whole destination and doesn't use its
31835 previous contents. */
31837 {
31839 {
31842 {
31846 negative++;
31849 negative++;
31850 }
31853 }
31855 {
31856 /* Recognize also when mask is like:
31857 __v2df src = _mm_setzero_pd ();
31858 __v2df mask = _mm_cmpeq_pd (src, src);
31859 or
31860 __v8sf src = _mm256_setzero_ps ();
31861 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
31862 as that is a cheaper way to load all ones into
31863 a register than having to load a constant from
31864 memory. */
31867 {
31872 {
31879 /* FALLTHRU */
31889 }
31890 }
31891 }
31892 }
31901 {
31908 else
31910 }
31911 else
31922 {
31925 }
31931 }
31944 {
31948 /* Emit a normal call if SSE isn't available. */
31952 }
31977 }
31979 /* Returns a function decl for a vectorized version of the builtin function
31980 with builtin function code FN and the result vector type TYPE, or NULL_TREE
31981 if it is not available. */
31983 static tree
31985 tree type_in)
31986 {
32002 {
32005 {
32010 }
32015 {
32020 }
32026 /* The round insn does not trap on denormals. */
32031 {
32036 }
32042 /* The round insn does not trap on denormals. */
32047 {
32052 }
32058 /* The round insn does not trap on denormals. */
32063 {
32068 }
32074 /* The round insn does not trap on denormals. */
32079 {
32084 }
32091 {
32096 }
32103 {
32108 }
32114 /* The round insn does not trap on denormals. */
32119 {
32124 }
32130 /* The round insn does not trap on denormals. */
32135 {
32140 }
32145 {
32150 }
32155 {
32160 }
32164 /* The round insn does not trap on denormals. */
32169 {
32174 }
32178 /* The round insn does not trap on denormals. */
32183 {
32188 }
32192 /* The round insn does not trap on denormals. */
32197 {
32202 }
32206 /* The round insn does not trap on denormals. */
32211 {
32216 }
32220 /* The round insn does not trap on denormals. */
32225 {
32230 }
32234 /* The round insn does not trap on denormals. */
32239 {
32244 }
32248 /* The round insn does not trap on denormals. */
32253 {
32258 }
32262 /* The round insn does not trap on denormals. */
32267 {
32272 }
32276 /* The round insn does not trap on denormals. */
32281 {
32286 }
32290 /* The round insn does not trap on denormals. */
32295 {
32300 }
32305 {
32310 }
32315 {
32320 }
32325 }
32327 /* Dispatch to a handler for a vectorization library. */
32330 type_in);
32333 }
32335 /* Handler for an SVML-style interface to
32336 a library with vectorized intrinsics. */
32338 static tree
32340 {
32348 /* The SVML is suitable for unsafe math only. */
32361 {
32408 }
32417 {
32420 }
32421 else
32424 /* Convert to uppercase. */
32429 args;
32431 arity++;
32435 else
32438 /* Build a function declaration for the vectorized function. */
32447 }
32449 /* Handler for an ACML-style interface to
32450 a library with vectorized intrinsics. */
32452 static tree
32454 {
32462 /* The ACML is 64bits only and suitable for unsafe math only as
32463 it does not correctly support parts of IEEE with the required
32464 precision such as denormals. */
32478 {
32508 }
32515 args;
32517 arity++;
32521 else
32524 /* Build a function declaration for the vectorized function. */
32533 }
32535 /* Returns a decl of a function that implements gather load with
32536 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
32537 Return NULL_TREE if it is not available. */
32539 static tree
32542 {
32558 /* v*gather* insn sign extends index to pointer mode. */
32570 {
32597 }
32600 }
32602 /* Returns a code for a target-specific builtin that implements
32603 reciprocal of the function, or NULL_TREE if not available. */
32605 static tree
32608 {
32615 /* Machine dependent builtins. */
32617 {
32618 /* Vectorized version of sqrt to rsqrt conversion. */
32627 }
32628 else
32629 /* Normal builtins. */
32631 {
32632 /* Sqrt to rsqrt conversion. */
32638 }
32639 }
32640 \f
32641 /* Helper for avx_vpermilps256_operand et al. This is also used by
32642 the expansion functions to turn the parallel back into a mask.
32643 The return value is 0 for no match and the imm8+1 for a match. */
32645 int
32647 {
32655 /* Validate that all of the elements are constants, and not totally
32656 out of range. Copy the data into an integral array to make the
32657 subsequent checks easier. */
32659 {
32669 }
32672 {
32674 /* In the 256-bit DFmode case, we can only move elements within
32675 a 128-bit lane. */
32677 {
32681 }
32683 {
32687 }
32691 /* In the 256-bit SFmode case, we have full freedom of movement
32692 within the low 128-bit lane, but the high 128-bit lane must
32693 mirror the exact same pattern. */
32698 /* FALLTHRU */
32702 /* In the 128-bit case, we've full freedom in the placement of
32703 the elements from the source operand. */
32710 }
32712 /* Make sure success has a non-zero value by adding one. */
32714 }
32716 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
32717 the expansion functions to turn the parallel back into a mask.
32718 The return value is 0 for no match and the imm8+1 for a match. */
32720 int
32722 {
32730 /* Validate that all of the elements are constants, and not totally
32731 out of range. Copy the data into an integral array to make the
32732 subsequent checks easier. */
32734 {
32744 }
32746 /* Validate that the halves of the permute are halves. */
32754 /* Reconstruct the mask. */
32756 {
32762 }
32764 /* Make sure success has a non-zero value by adding one. */
32766 }
32767 \f
32768 /* Store OPERAND to the memory after reload is completed. This means
32769 that we can't easily use assign_stack_local. */
32770 rtx
32772 {
32773 rtx result;
32777 {
32780 stack_pointer_rtx,
32783 }
32785 {
32787 {
32791 /* FALLTHRU */
32797 stack_pointer_rtx)),
32798 operand));
32802 }
32804 }
32805 else
32806 {
32808 {
32810 {
32817 stack_pointer_rtx)),
32823 stack_pointer_rtx)),
32825 }
32828 /* Store HImodes as SImodes. */
32830 /* FALLTHRU */
32836 stack_pointer_rtx)),
32837 operand));
32841 }
32843 }
32845 }
32847 /* Free operand from the memory. */
32848 void
32850 {
32852 {
32857 else
32859 /* Use LEA to deallocate stack space. In peephole2 it will be converted
32860 to pop or add instruction if registers are available. */
32864 }
32865 }
32867 /* Return true if we use LRA instead of reload pass. */
32868 static bool
32870 {
32872 }
32874 /* Return a register priority for hard reg REGNO. */
32875 static int
32877 {
32878 /* ebp and r13 as the base always wants a displacement, r12 as the
32879 base always wants an index. So discourage their usage in an
32880 address. */
32885 /* New x86-64 int registers result in bigger code size. Discourage
32886 them. */
32889 /* New x86-64 SSE registers result in bigger code size. Discourage
32890 them. */
32893 /* Usage of AX register results in smaller code. Prefer it. */
32897 }
32899 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
32901 Put float CONST_DOUBLE in the constant pool instead of fp regs.
32902 QImode must go into class Q_REGS.
32903 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
32904 movdf to do mem-to-mem moves through integer regs. */
32906 static reg_class_t
32908 {
32911 /* We're only allowed to return a subclass of CLASS. Many of the
32912 following checks fail for NO_REGS, so eliminate that early. */
32916 /* All classes can load zeros. */
32920 /* Force constants into memory if we are loading a (nonzero) constant into
32921 an MMX or SSE register. This is because there are no MMX/SSE instructions
32922 to load from a constant. */
32927 /* Prefer SSE regs only, if we can use them for math. */
32931 /* Floating-point constants need more complex checks. */
32933 {
32934 /* General regs can load everything. */
32938 /* Floats can load 0 and 1 plus some others. Note that we eliminated
32939 zero above. We only want to wind up preferring 80387 registers if
32940 we plan on doing computation with them. */
32943 {
32944 /* Limit class to non-sse. */
32953 }
32956 }
32958 /* Generally when we see PLUS here, it's the function invariant
32959 (plus soft-fp const_int). Which can only be computed into general
32960 regs. */
32964 /* QImode constants are easy to load, but non-constant QImode data
32965 must go into Q_REGS. */
32967 {
32973 }
32976 }
32978 /* Discourage putting floating-point values in SSE registers unless
32979 SSE math is being used, and likewise for the 387 registers. */
32980 static reg_class_t
32982 {
32985 /* Restrict the output reload class to the register bank that we are doing
32986 math on. If we would like not to return a subset of CLASS, reject this
32987 alternative: if reload cannot do this, it will still use its choice. */
32993 {
32998 else
33000 }
33003 }
33005 static reg_class_t
33008 {
33009 /* Double-word spills from general registers to non-offsettable memory
33010 references (zero-extended addresses) require special handling. */
33016 {
33018 ? CODE_FOR_reload_noff_load
33020 /* Add the cost of moving address to a temporary. */
33024 }
33026 /* QImode spills from non-QI registers require
33027 intermediate register on 32bit targets. */
33036 {
33041 else
33047 /* Return Q_REGS if the operand is in memory. */
33050 }
33052 /* This condition handles corner case where an expression involving
33053 pointers gets vectorized. We're trying to use the address of a
33054 stack slot as a vector initializer.
33056 (set (reg:V2DI 74 [ vect_cst_.2 ])
33057 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33059 Eventually frame gets turned into sp+offset like this:
33061 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33062 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33063 (const_int 392 [0x188]))))
33065 That later gets turned into:
33067 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33068 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33069 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33071 We'll have the following reload recorded:
33073 Reload 0: reload_in (DI) =
33074 (plus:DI (reg/f:DI 7 sp)
33075 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33076 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33077 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33078 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33079 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33080 reload_reg_rtx: (reg:V2DI 22 xmm1)
33082 Which isn't going to work since SSE instructions can't handle scalar
33083 additions. Returning GENERAL_REGS forces the addition into integer
33084 register and reload can handle subsequent reloads without problems. */
33092 }
33094 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33096 static bool
33098 {
33100 {
33115 }
33118 }
33120 /* If we are copying between general and FP registers, we need a memory
33121 location. The same is true for SSE and MMX registers.
33123 To optimize register_move_cost performance, allow inline variant.
33125 The macro can't work reliably when one of the CLASSES is class containing
33126 registers from multiple units (SSE, MMX, integer). We avoid this by never
33127 combining those units in single alternative in the machine description.
33128 Ensure that this constraint holds to avoid unexpected surprises.
33130 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33131 enforce these sanity checks. */
33136 {
33143 {
33146 }
33151 /* ??? This is a lie. We do have moves between mmx/general, and for
33152 mmx/sse2. But by saying we need secondary memory we discourage the
33153 register allocator from using the mmx registers unless needed. */
33158 {
33159 /* SSE1 doesn't have any direct moves from other classes. */
33163 /* If the target says that inter-unit moves are more expensive
33164 than moving through memory, then don't generate them. */
33168 /* Between SSE and general, we have moves no larger than word size. */
33171 }
33174 }
33176 bool
33179 {
33181 }
33183 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33185 On the 80386, this is the size of MODE in words,
33186 except in the FP regs, where a single reg is always enough. */
33188 static unsigned char
33190 {
33192 {
33197 else
33199 }
33200 else
33201 {
33204 else
33206 }
33207 }
33209 /* Return true if the registers in CLASS cannot represent the change from
33210 modes FROM to TO. */
33212 bool
33215 {
33219 /* x87 registers can't do subreg at all, as all values are reformatted
33220 to extended precision. */
33225 {
33226 /* Vector registers do not support QI or HImode loads. If we don't
33227 disallow a change to these modes, reload will assume it's ok to
33228 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33229 the vec_dupv4hi pattern. */
33233 /* Vector registers do not support subreg with nonzero offsets, which
33234 are otherwise valid for integer registers. Since we can't see
33235 whether we have a nonzero offset from here, prohibit all
33236 nonparadoxical subregs changing size. */
33239 }
33242 }
33244 /* Return the cost of moving data of mode M between a
33245 register and memory. A value of 2 is the default; this cost is
33246 relative to those in `REGISTER_MOVE_COST'.
33248 This function is used extensively by register_move_cost that is used to
33249 build tables at startup. Make it inline in this case.
33250 When IN is 2, return maximum of in and out move cost.
33252 If moving between registers and memory is more expensive than
33253 between two registers, you should define this macro to express the
33254 relative cost.
33256 Model also increased moving costs of QImode registers in non
33257 Q_REGS classes.
33258 */
33262 {
33265 {
33268 {
33280 }
33284 }
33286 {
33289 {
33301 }
33305 }
33307 {
33310 {
33319 }
33323 }
33325 {
33328 {
33334 else
33339 }
33340 else
33341 {
33346 else
33348 }
33355 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33362 else
33366 }
33367 }
33369 static int
33372 {
33374 }
33377 /* Return the cost of moving data from a register in class CLASS1 to
33378 one in class CLASS2.
33380 It is not required that the cost always equal 2 when FROM is the same as TO;
33381 on some machines it is expensive to move between registers if they are not
33382 general registers. */
33384 static int
33386 reg_class_t class2_i)
33387 {
33391 /* In case we require secondary memory, compute cost of the store followed
33392 by load. In order to avoid bad register allocation choices, we need
33393 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33396 {
33402 /* In case of copying from general_purpose_register we may emit multiple
33403 stores followed by single load causing memory size mismatch stall.
33404 Count this as arbitrarily high cost of 20. */
33409 /* In the case of FP/MMX moves, the registers actually overlap, and we
33410 have to switch modes in order to treat them differently. */
33416 }
33418 /* Moves between SSE/MMX and integer unit are expensive. */
33422 /* ??? By keeping returned value relatively high, we limit the number
33423 of moves between integer and MMX/SSE registers for all targets.
33424 Additionally, high value prevents problem with x86_modes_tieable_p(),
33425 where integer modes in MMX/SSE registers are not tieable
33426 because of missing QImode and HImode moves to, from or between
33427 MMX/SSE registers. */
33437 }
33439 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33440 MODE. */
33442 bool
33444 {
33445 /* Flags and only flags can only hold CCmode values. */
33455 {
33456 /* We implement the move patterns for all vector modes into and
33457 out of SSE registers, even when no operation instructions
33458 are available. OImode move is available only when AVX is
33459 enabled. */
33466 }
33468 {
33469 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33470 so if the register is available at all, then we can move data of
33471 the given mode into or out of it. */
33474 }
33477 {
33478 /* Take care for QImode values - they can be in non-QI regs,
33479 but then they do cause partial register stalls. */
33485 }
33486 /* We handle both integer and floats in the general purpose registers. */
33493 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33494 on to use that value in smaller contexts, this can easily force a
33495 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33496 supporting DImode, allow it. */
33501 }
33503 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33504 tieable integer mode. */
33506 static bool
33508 {
33510 {
33523 }
33524 }
33526 /* Return true if MODE1 is accessible in a register that can hold MODE2
33527 without copying. That is, all register classes that can hold MODE2
33528 can also hold MODE1. */
33530 bool
33532 {
33540 /* MODE2 being XFmode implies fp stack or general regs, which means we
33541 can tie any smaller floating point modes to it. Note that we do not
33542 tie this with TFmode. */
33546 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
33547 that we can tie it with SFmode. */
33551 /* If MODE2 is only appropriate for an SSE register, then tie with
33552 any other mode acceptable to SSE registers. */
33562 /* If MODE2 is appropriate for an MMX register, then tie
33563 with any other mode acceptable to MMX registers. */
33570 }
33572 /* Return the cost of moving between two registers of mode MODE. */
33574 static int
33576 {
33580 {
33611 }
33613 /* Return the cost of moving between two registers of mode MODE,
33614 assuming that the move will be in pieces of at most UNITS bytes. */
33616 }
33618 /* Compute a (partial) cost for rtx X. Return true if the complete
33619 cost has been computed, and false if subexpressions should be
33620 scanned. In either case, *TOTAL contains the cost result. */
33622 static bool
33625 {
33632 {
33636 {
33639 }
33651 && (!TARGET_64BIT
33656 else
33662 {
33665 }
33667 {
33677 }
33679 {
33682 {
33691 }
33692 }
33693 /* Fall back to (MEM (SYMBOL_REF)), since that's where
33694 it'll probably end up. Add a penalty for size. */
33701 /* The zero extensions is often completely free on x86_64, so make
33702 it as cheap as possible. */
33708 else
33720 {
33723 {
33726 }
33729 {
33732 }
33733 }
33734 /* FALLTHRU */
33741 {
33742 /* ??? Should be SSE vector operation cost. */
33743 /* At least for published AMD latencies, this really is the same
33744 as the latency for a simple fpu operation like fabs. */
33745 /* V*QImode is emulated with 1-11 insns. */
33747 {
33750 {
33751 /* For XOP we use vpshab, which requires a broadcast of the
33752 value to the variable shift insn. For constants this
33753 means a V16Q const in mem; even when we can perform the
33754 shift with one insn set the cost to prefer paddb. */
33756 {
33761 }
33763 }
33767 }
33768 else
33770 }
33772 {
33774 {
33777 else
33779 }
33780 else
33781 {
33784 else
33786 }
33787 }
33788 else
33789 {
33792 else
33794 }
33798 {
33799 rtx sub;
33804 /* ??? SSE scalar/vector cost should be used here. */
33805 /* ??? Bald assumption that fma has the same cost as fmul. */
33809 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
33820 }
33824 {
33825 /* ??? SSE scalar cost should be used here. */
33828 }
33830 {
33833 }
33835 {
33836 /* ??? SSE vector cost should be used here. */
33839 }
33841 {
33842 /* V*QImode is emulated with 7-13 insns. */
33844 {
33851 }
33852 /* V*DImode is emulated with 5-8 insns. */
33854 {
33857 else
33859 }
33860 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
33861 insns, including two PMULUDQ. */
33864 else
33867 }
33868 else
33869 {
33874 {
33877 nbits++;
33878 }
33879 else
33880 /* This is arbitrary. */
33883 /* Compute costs correctly for widening multiplication. */
33887 {
33894 {
33898 else
33900 }
33904 }
33912 }
33919 /* ??? SSE cost should be used here. */
33924 /* ??? SSE vector cost should be used here. */
33926 else
33933 {
33938 {
33941 {
33949 }
33950 }
33953 {
33956 {
33962 }
33963 }
33965 {
33973 }
33974 }
33975 /* FALLTHRU */
33979 {
33980 /* ??? SSE cost should be used here. */
33983 }
33985 {
33988 }
33990 {
33991 /* ??? SSE vector cost should be used here. */
33994 }
33995 /* FALLTHRU */
34002 {
34009 }
34010 /* FALLTHRU */
34014 {
34015 /* ??? SSE cost should be used here. */
34018 }
34020 {
34023 }
34025 {
34026 /* ??? SSE vector cost should be used here. */
34029 }
34030 /* FALLTHRU */
34034 {
34035 /* ??? Should be SSE vector operation cost. */
34036 /* At least for published AMD latencies, this really is the same
34037 as the latency for a simple fpu operation like fabs. */
34039 }
34042 else
34051 {
34052 /* This kind of construct is implemented using test[bwl].
34053 Treat it as if we had an AND. */
34058 }
34068 /* ??? SSE cost should be used here. */
34073 /* ??? SSE vector cost should be used here. */
34079 /* ??? SSE cost should be used here. */
34084 /* ??? SSE vector cost should be used here. */
34097 /* ??? Assume all of these vector manipulation patterns are
34098 recognizable. In which case they all pretty much have the
34099 same cost. */
34105 }
34106 }
34108 #if TARGET_MACHO
34112 /* Given a symbol name and its associated stub, write out the
34113 definition of the stub. */
34115 void
34117 {
34122 /* For 64-bit we shouldn't get here. */
34125 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34142 else
34149 {
34151 }
34153 {
34154 /* PIC stub. */
34155 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34161 }
34162 else
34165 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34166 it needs no stub-binding-helper. */
34173 {
34176 }
34177 else
34182 /* N.B. Keep the correspondence of these
34183 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34184 old-pic/new-pic/non-pic stubs; altering this will break
34185 compatibility with existing dylibs. */
34187 {
34188 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34190 }
34191 else
34192 /* 16-byte -mdynamic-no-pic stub. */
34198 }
34201 /* Order the registers for register allocator. */
34203 void
34205 {
34209 /* First allocate the local general purpose registers. */
34214 /* Global general purpose registers. */
34219 /* x87 registers come first in case we are doing FP math
34220 using them. */
34225 /* SSE registers. */
34231 /* x87 registers. */
34239 /* Initialize the rest of array as we do not allocate some registers
34240 at all. */
34243 }
34245 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34246 in struct attribute_spec handler. */
34247 static tree
34249 tree args,
34252 {
34257 {
34259 name);
34262 }
34264 {
34266 name);
34269 }
34271 {
34272 tree cst;
34276 {
34279 name);
34281 }
34284 {
34287 name);
34289 }
34292 }
34295 }
34297 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34298 struct attribute_spec.handler. */
34299 static tree
34301 tree args ATTRIBUTE_UNUSED,
34303 {
34308 {
34310 name);
34313 }
34315 /* Can combine regparm with all attributes but fastcall. */
34317 {
34319 {
34321 }
34324 }
34326 {
34328 {
34330 }
34333 }
34336 }
34338 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34339 struct attribute_spec.handler. */
34340 static tree
34342 tree args ATTRIBUTE_UNUSED,
34344 {
34347 {
34350 }
34351 else
34355 {
34357 name);
34359 }
34365 {
34367 name);
34369 }
34372 }
34374 static tree
34376 tree args ATTRIBUTE_UNUSED,
34378 {
34380 {
34382 name);
34384 }
34386 }
34388 static bool
34390 {
34394 }
34396 /* Returns an expression indicating where the this parameter is
34397 located on entry to the FUNCTION. */
34399 static rtx
34401 {
34407 {
34412 else
34415 }
34420 {
34427 {
34432 }
34433 else
34434 {
34437 {
34443 }
34444 }
34446 }
34450 }
34452 /* Determine whether x86_output_mi_thunk can succeed. */
34454 static bool
34456 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34458 {
34459 /* 64-bit can handle anything. */
34463 /* For 32-bit, everything's fine if we have one free register. */
34467 /* Need a free register for vcall_offset. */
34471 /* Need a free register for GOT references. */
34475 /* Otherwise ok. */
34477 }
34479 /* Output the assembler code for a thunk function. THUNK_DECL is the
34480 declaration for the thunk function itself, FUNCTION is the decl for
34481 the target function. DELTA is an immediate constant offset to be
34482 added to THIS. If VCALL_OFFSET is nonzero, the word at
34483 *(*this + vcall_offset) should be added to THIS. */
34485 static void
34489 {
34496 else
34497 {
34501 else
34503 }
34507 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34508 pull it in now and let DELTA benefit. */
34512 {
34513 /* Put the this parameter into %eax. */
34516 }
34517 else
34520 /* Adjust the this parameter by a fixed constant. */
34522 {
34527 {
34529 {
34533 }
34534 }
34537 }
34539 /* Adjust the this parameter by a value stored in the vtable. */
34541 {
34551 /* Adjust the this parameter. */
34555 {
34559 }
34566 vcall_mem));
34567 else
34569 }
34571 /* If necessary, drop THIS back to its stack slot. */
34577 {
34580 ;
34581 else
34582 {
34586 }
34587 }
34588 else
34589 {
34591 ;
34592 #if TARGET_MACHO
34594 {
34597 }
34599 else
34600 {
34607 }
34608 }
34610 /* Our sibling call patterns do not allow memories, because we have no
34611 predicate that can distinguish between frame and non-frame memory.
34612 For our purposes here, we can get away with (ab)using a jump pattern,
34613 because we're going to do no optimization. */
34616 else
34617 {
34623 {
34629 }
34635 }
34638 /* Emit just enough of rest_of_compilation to get the insns emitted.
34639 Note that use_thunk calls assemble_start_function et al. */
34645 }
34647 static void
34649 {
34651 #if TARGET_MACHO
34653 #endif
34660 }
34662 int
34664 {
34676 }
34678 /* Output assembler code to FILE to increment profiler label # LABELNO
34679 for profiling a function entry. */
34680 void
34682 {
34687 {
34688 #ifndef NO_PROFILE_COUNTERS
34690 #endif
34694 else
34696 }
34698 {
34699 #ifndef NO_PROFILE_COUNTERS
34702 #endif
34704 }
34705 else
34706 {
34707 #ifndef NO_PROFILE_COUNTERS
34710 #endif
34712 }
34713 }
34715 /* We don't have exact information about the insn sizes, but we may assume
34716 quite safely that we are informed about all 1 byte insns and memory
34717 address sizes. This is enough to eliminate unnecessary padding in
34718 99% of cases. */
34720 static int
34722 {
34728 /* Discard alignments we've emit and jump instructions. */
34735 /* Important case - calls are always 5 bytes.
34736 It is common to have many calls in the row. */
34745 /* For normal instructions we rely on get_attr_length being exact,
34746 with a few exceptions. */
34748 {
34752 {
34762 /* Otherwise trust get_attr_length. */
34764 }
34769 }
34772 else
34774 }
34776 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
34778 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
34779 window. */
34781 static void
34783 {
34788 /* Look for all minimal intervals of instructions containing 4 jumps.
34789 The intervals are bounded by START and INSN. NBYTES is the total
34790 size of instructions in the interval including INSN and not including
34791 START. When the NBYTES is smaller than 16 bytes, it is possible
34792 that the end of START and INSN ends up in the same 16byte page.
34794 The smallest offset in the page INSN can start is the case where START
34795 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
34796 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
34797 */
34799 {
34803 {
34809 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
34810 already in the current 16 byte page, because otherwise
34811 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
34812 bytes to reach 16 byte boundary. */
34820 {
34822 {
34829 else
34832 }
34833 }
34835 }
34846 njumps++;
34847 else
34851 {
34858 else
34861 }
34868 {
34875 }
34876 }
34877 }
34878 #endif
34880 /* AMD Athlon works faster
34881 when RET is not destination of conditional jump or directly preceded
34882 by other jump instruction. We avoid the penalty by inserting NOP just
34883 before the RET instructions in such cases. */
34884 static void
34886 {
34887 edge e;
34888 edge_iterator ei;
34891 {
34894 rtx prev;
34904 {
34905 edge e;
34906 edge_iterator ei;
34912 }
34914 {
34920 /* Empty functions get branch mispredict even when
34921 the jump destination is not visible to us. */
34924 }
34926 {
34929 }
34930 }
34931 }
34933 /* Count the minimum number of instructions in BB. Return 4 if the
34934 number of instructions >= 4. */
34936 static int
34938 {
34939 rtx insn;
34942 /* Count number of instructions in this block. Return 4 if the number
34943 of instructions >= 4. */
34945 {
34946 /* Only happen in exit blocks. */
34954 {
34955 insn_count++;
34958 }
34959 }
34962 }
34965 /* Count the minimum number of instructions in code path in BB.
34966 Return 4 if the number of instructions >= 4. */
34968 static int
34970 {
34971 edge e;
34972 edge_iterator ei;
34975 /* Only bother counting instructions along paths with no
34976 more than 2 basic blocks between entry and exit. Given
34977 that BB has an edge to exit, determine if a predecessor
34978 of BB has an edge from entry. If so, compute the number
34979 of instructions in the predecessor block. If there
34980 happen to be multiple such blocks, compute the minimum. */
34983 {
34984 edge prev_e;
34985 edge_iterator prev_ei;
34988 {
34991 }
34993 {
34995 {
35000 }
35001 }
35002 }
35008 }
35010 /* Pad short function to 4 instructions. */
35012 static void
35014 {
35015 edge e;
35016 edge_iterator ei;
35019 {
35022 {
35025 /* Pad short function. */
35027 {
35030 /* Find epilogue. */
35039 /* Two NOPs count as one instruction. */
35042 }
35043 }
35044 }
35045 }
35047 /* Implement machine specific optimizations. We implement padding of returns
35048 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35049 static void
35051 {
35052 /* We are freeing block_for_insn in the toplev to keep compatibility
35053 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35057 {
35062 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35065 #endif
35066 }
35067 }
35069 /* Return nonzero when QImode register that must be represented via REX prefix
35070 is used. */
35071 bool
35073 {
35081 }
35083 /* Return nonzero when P points to register encoded via REX prefix.
35084 Called via for_each_rtx. */
35085 static int
35087 {
35093 }
35095 /* Return true when INSN mentions register that must be encoded using REX
35096 prefix. */
35097 bool
35099 {
35102 }
35104 /* If profitable, negate (without causing overflow) integer constant
35105 of mode MODE at location LOC. Return true in this case. */
35106 bool
35108 {
35109 HOST_WIDE_INT val;
35115 {
35117 /* DImode x86_64 constants must fit in 32 bits. */
35130 }
35132 /* Avoid overflows. */
35138 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35139 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35142 {
35145 }
35148 }
35150 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35151 optabs would emit if we didn't have TFmode patterns. */
35153 void
35155 {
35189 }
35190 \f
35191 /* AVX2 does support 32-byte integer vector operations,
35192 thus the longest vector we are faced with is V32QImode. */
35193 #define MAX_VECT_LEN 32
35195 struct expand_vec_perm_d
35196 {
35203 };
35209 /* Get a vector mode of the same size as the original but with elements
35210 twice as wide. This is only guaranteed to apply to integral vectors. */
35214 {
35215 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35220 }
35222 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35223 with all elements equal to VAR. Return true if successful. */
35225 static bool
35228 {
35232 {
35237 /* FALLTHRU */
35247 {
35250 /* First attempt to recognize VAL as-is. */
35254 {
35255 rtx seq;
35256 /* If that fails, force VAL into a register. */
35267 }
35268 }
35275 {
35276 rtx x;
35283 }
35293 {
35297 permute:
35305 /* Extend to SImode using a paradoxical SUBREG. */
35309 /* Insert the SImode value as low element of a V4SImode vector. */
35317 }
35325 widen:
35326 /* Replicate the value once into the next wider mode and recurse. */
35327 {
35329 rtx x;
35345 }
35349 {
35358 }
35363 }
35364 }
35366 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35367 whose ONE_VAR element is VAR, and other elements are zero. Return true
35368 if successful. */
35370 static bool
35373 {
35375 rtx new_target;
35380 {
35382 /* For SSE4.1, we normally use vector set. But if the second
35383 element is zero and inter-unit moves are OK, we use movq
35384 instead. */
35385 use_vector_set = (TARGET_64BIT
35386 && TARGET_SSE4_1
35387 && !(TARGET_INTER_UNIT_MOVES
35409 /* Use ix86_expand_vector_set in 64bit mode only. */
35414 }
35417 {
35422 }
35425 {
35430 /* FALLTHRU */
35445 else
35452 {
35453 /* We need to shuffle the value to the correct position, so
35454 create a new pseudo to store the intermediate result. */
35456 /* With SSE2, we can use the integer shuffle insns. */
35458 {
35460 const1_rtx,
35467 }
35469 /* Otherwise convert the intermediate result to V4SFmode and
35470 use the SSE1 shuffle instructions. */
35472 {
35475 }
35476 else
35480 const1_rtx,
35489 }
35504 widen:
35508 /* Zero extend the variable element to SImode and recurse. */
35521 }
35522 }
35524 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35525 consisting of the values in VALS. It is known that all elements
35526 except ONE_VAR are constants. Return true if successful. */
35528 static bool
35531 {
35541 {
35546 /* For the two element vectors, it's just as easy to use
35547 the general case. */
35551 /* Use ix86_expand_vector_set in 64bit mode only. */
35573 widen:
35574 /* There's no way to set one QImode entry easily. Combine
35575 the variable value with its adjacent constant value, and
35576 promote to an HImode set. */
35579 {
35584 }
35585 else
35586 {
35589 }
35603 }
35608 }
35610 /* A subroutine of ix86_expand_vector_init_general. Use vector
35611 concatenate to handle the most general case: all values variable,
35612 and none identical. */
35614 static void
35617 {
35620 rtvec v;
35624 {
35627 {
35660 }
35673 {
35688 }
35693 {
35704 }
35707 half:
35708 /* FIXME: We process inputs backward to help RA. PR 36222. */
35712 {
35717 }
35721 {
35724 {
35728 }
35731 }
35732 else
35738 }
35739 }
35741 /* A subroutine of ix86_expand_vector_init_general. Use vector
35742 interleave to handle the most general case: all values variable,
35743 and none identical. */
35745 static void
35748 {
35757 {
35778 }
35781 {
35782 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
35786 /* Insert the SImode value as low element of V4SImode vector. */
35790 op0),
35792 const1_rtx);
35795 /* Cast the V4SImode vector back to a vector in orignal mode. */
35799 /* Load even elements into the second positon. */
35803 const1_rtx));
35805 /* Cast vector to FIRST_IMODE vector. */
35808 }
35810 /* Interleave low FIRST_IMODE vectors. */
35812 {
35816 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
35819 }
35821 /* Interleave low SECOND_IMODE vectors. */
35823 {
35826 {
35831 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
35832 vector. */
35835 }
35838 /* FALLTHRU */
35845 /* Cast the SECOND_IMODE vector back to a vector on original
35846 mode. */
35853 }
35854 }
35856 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
35857 all values variable, and none identical. */
35859 static void
35862 {
35868 {
35873 /* FALLTHRU */
35897 half:
35914 /* FALLTHRU */
35920 /* Don't use ix86_expand_vector_init_interleave if we can't
35921 move from GPR to SSE register directly. */
35937 }
35939 {
35951 {
35955 {
35961 else
35962 {
35967 }
35968 }
35971 }
35976 {
35982 }
35984 {
35990 }
35991 else
35993 }
35994 }
35996 /* Initialize vector TARGET via VALS. Suppress the use of MMX
35997 instructions unless MMX_OK is true. */
35999 void
36001 {
36008 rtx x;
36011 {
36021 }
36023 /* Constants are best loaded from the constant pool. */
36025 {
36028 }
36030 /* If all values are identical, broadcast the value. */
36036 /* Values where only one field is non-constant are best loaded from
36037 the pool and overwritten via move later. */
36039 {
36043 one_var))
36048 }
36051 }
36053 void
36055 {
36060 rtx tmp;
36062 = {
36069 };
36071 = {
36078 };
36082 {
36086 {
36091 else
36095 }
36107 else
36113 {
36116 /* For the two element vectors, we implement a VEC_CONCAT with
36117 the extraction of the other element. */
36124 else
36129 }
36138 {
36144 /* tmp = target = A B C D */
36146 /* target = A A B B */
36148 /* target = X A B B */
36150 /* target = A X C D */
36157 /* tmp = target = A B C D */
36159 /* tmp = X B C D */
36161 /* target = A B X D */
36168 /* tmp = target = A B C D */
36170 /* tmp = X B C D */
36172 /* target = A B X D */
36180 }
36188 /* Element 0 handled by vec_merge below. */
36190 {
36193 }
36196 {
36197 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36198 store into element 0, then shuffle them back. */
36215 }
36216 else
36217 {
36218 /* For SSE1, we have to reuse the V4SF code. */
36221 }
36274 half:
36275 /* Compute offset. */
36281 /* Extract the half. */
36285 /* Put val in tmp at elt. */
36288 /* Put it back. */
36294 }
36297 {
36301 }
36302 else
36303 {
36312 }
36313 }
36315 void
36317 {
36321 rtx tmp;
36324 {
36329 /* FALLTHRU */
36342 {
36362 }
36374 {
36376 {
36396 }
36400 }
36401 else
36402 {
36403 /* For SSE1, we have to reuse the V4SF code. */
36407 }
36423 {
36427 else
36431 }
36436 {
36440 else
36444 }
36449 {
36453 else
36457 }
36462 {
36466 else
36470 }
36475 {
36479 else
36483 }
36488 {
36492 else
36496 }
36500 /* ??? Could extract the appropriate HImode element and shift. */
36503 }
36506 {
36510 /* Let the rtl optimizers know about the zero extension performed. */
36512 {
36515 }
36518 }
36519 else
36520 {
36527 }
36528 }
36530 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
36531 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
36532 The upper bits of DEST are undefined, though they shouldn't cause
36533 exceptions (some bits from src or all zeros are ok). */
36535 static void
36537 {
36538 rtx tem;
36540 {
36544 else
36562 else
36569 else
36580 const1_rtx);
36581 else
36588 }
36590 }
36592 /* Expand a vector reduction. FN is the binary pattern to reduce;
36593 DEST is the destination; IN is the input vector. */
36595 void
36597 {
36602 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
36606 {
36609 }
36614 {
36619 else
36623 }
36624 }
36625 \f
36626 /* Target hook for scalar_mode_supported_p. */
36627 static bool
36629 {
36634 else
36636 }
36638 /* Implements target hook vector_mode_supported_p. */
36639 static bool
36641 {
36653 }
36655 /* Target hook for c_mode_for_suffix. */
36656 static enum machine_mode
36658 {
36665 }
36667 /* Worker function for TARGET_MD_ASM_CLOBBERS.
36669 We do this in the new i386 backend to maintain source compatibility
36670 with the old cc0-based compiler. */
36672 static tree
36674 tree inputs ATTRIBUTE_UNUSED,
36675 tree clobbers)
36676 {
36678 clobbers);
36680 clobbers);
36682 }
36684 /* Implements target vector targetm.asm.encode_section_info. */
36686 static void ATTRIBUTE_UNUSED
36688 {
36695 }
36697 /* Worker function for REVERSE_CONDITION. */
36699 enum rtx_code
36701 {
36705 }
36707 /* Output code to perform an x87 FP register move, from OPERANDS[1]
36708 to OPERANDS[0]. */
36712 {
36714 {
36717 {
36721 }
36725 }
36727 {
36731 else
36732 {
36733 /* There is no non-popping store to memory for XFmode.
36734 So if we need one, follow the store with a load. */
36737 else
36739 }
36740 }
36741 else
36743 }
36745 /* Output code to perform a conditional jump to LABEL, if C2 flag in
36746 FP status register is set. */
36748 void
36750 {
36752 rtx temp;
36757 {
36762 }
36763 else
36764 {
36769 }
36773 pc_rtx);
36778 }
36780 /* Output code to perform a log1p XFmode calculation. */
36783 {
36789 rtx test;
36795 XFmode));
36809 }
36811 /* Emit code for round calculation. */
36813 {
36820 rtx insn;
36825 {
36837 }
36840 {
36861 }
36869 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
36871 /* scratch = fxam(op1) */
36874 UNSPEC_FXAM)));
36875 /* e1 = fabs(op1) */
36878 /* e2 = e1 + 0.5 */
36883 /* res = floor(e2) */
36885 {
36890 }
36891 else
36895 {
36898 {
36905 UNSPEC_TRUNC_NOOP)));
36906 }
36922 }
36924 /* flags = signbit(a) */
36927 /* if (flags) then res = -res */
36931 pc_rtx);
36942 }
36944 /* Output code to perform a Newton-Rhapson approximation of a single precision
36945 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
36948 {
36956 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
36960 /* x0 = rcp(b) estimate */
36963 UNSPEC_RCP)));
36964 /* e0 = x0 * b */
36968 /* e0 = x0 * e0 */
36972 /* e1 = x0 + x0 */
36976 /* x1 = e1 - e0 */
36980 /* res = a * x1 */
36983 }
36985 /* Output code to perform a Newton-Rhapson approximation of a
36986 single precision floating point [reciprocal] square root. */
36990 {
36992 REAL_VALUE_TYPE r;
37007 {
37010 }
37012 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37013 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37017 /* x0 = rsqrt(a) estimate */
37020 UNSPEC_RSQRT)));
37022 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37024 {
37036 }
37038 /* e0 = x0 * a */
37041 /* e1 = e0 * x0 */
37045 /* e2 = e1 - 3. */
37052 /* e3 = -.5 * x0 */
37055 else
37056 /* e3 = -.5 * e0 */
37059 /* ret = e2 * e3 */
37062 }
37064 #ifdef TARGET_SOLARIS
37065 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37067 static void
37069 tree decl)
37070 {
37071 /* With Binutils 2.15, the "@unwind" marker must be specified on
37072 every occurrence of the ".eh_frame" section, not just the first
37073 one. */
37076 {
37080 }
37082 #ifndef USE_GAS
37084 {
37087 }
37088 #endif
37091 }
37094 /* Return the mangling of TYPE if it is an extended fundamental type. */
37098 {
37106 {
37108 /* __float128 is "g". */
37111 /* "long double" or __float80 is "e". */
37115 }
37116 }
37118 /* For 32-bit code we can save PIC register setup by using
37119 __stack_chk_fail_local hidden function instead of calling
37120 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37121 register, so it is better to call __stack_chk_fail directly. */
37123 static tree ATTRIBUTE_UNUSED
37125 {
37126 return TARGET_64BIT
37129 }
37131 /* Select a format to encode pointers in exception handling data. CODE
37132 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37133 true if the symbol may be affected by dynamic relocations.
37135 ??? All x86 object file formats are capable of representing this.
37136 After all, the relocation needed is the same as for the call insn.
37137 Whether or not a particular assembler allows us to enter such, I
37138 guess we'll have to see. */
37139 int
37141 {
37143 {
37150 }
37155 }
37156 \f
37157 /* Expand copysign from SIGN to the positive value ABS_VALUE
37158 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37159 the sign-bit. */
37160 static void
37162 {
37166 {
37173 else
37178 {
37179 /* We need to generate a scalar mode mask in this case. */
37184 }
37185 }
37186 else
37192 }
37194 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37195 mask for masking out the sign-bit is stored in *SMASK, if that is
37196 non-null. */
37197 static rtx
37199 {
37208 else
37212 {
37213 /* We need to generate a scalar mode mask in this case. */
37218 }
37226 }
37228 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37229 swapping the operands if SWAP_OPERANDS is true. The expanded
37230 code is a forward jump to a newly created label in case the
37231 comparison is true. The generated label rtx is returned. */
37232 static rtx
37235 {
37239 {
37243 }
37256 }
37258 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37259 using comparison code CODE. Operands are swapped for the comparison if
37260 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37261 static rtx
37264 {
37270 {
37274 }
37281 }
37283 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37284 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37285 static rtx
37287 {
37288 REAL_VALUE_TYPE TWO52r;
37289 rtx TWO52;
37296 }
37298 /* Expand SSE sequence for computing lround from OP1 storing
37299 into OP0. */
37300 void
37302 {
37303 /* C code for the stuff we're doing below:
37304 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37305 return (long)tmp;
37306 */
37310 rtx adj;
37312 /* load nextafter (0.5, 0.0) */
37317 /* adj = copysign (0.5, op1) */
37321 /* adj = op1 + adj */
37324 /* op0 = (imode)adj */
37326 }
37328 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37329 into OPERAND0. */
37330 void
37332 {
37333 /* C code for the stuff we're doing below (for do_floor):
37334 xi = (long)op1;
37335 xi -= (double)xi > op1 ? 1 : 0;
37336 return xi;
37337 */
37342 /* reg = (long)op1 */
37346 /* freg = (double)reg */
37350 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37361 }
37363 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37364 result in OPERAND0. */
37365 void
37367 {
37368 /* C code for the stuff we're doing below:
37369 xa = fabs (operand1);
37370 if (!isless (xa, 2**52))
37371 return operand1;
37372 xa = xa + 2**52 - 2**52;
37373 return copysign (xa, operand1);
37374 */
37381 /* xa = abs (operand1) */
37384 /* if (!isless (xa, TWO52)) goto label; */
37397 }
37399 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37400 into OPERAND0. */
37401 void
37403 {
37404 /* C code for the stuff we expand below.
37405 double xa = fabs (x), x2;
37406 if (!isless (xa, TWO52))
37407 return x;
37408 xa = xa + TWO52 - TWO52;
37409 x2 = copysign (xa, x);
37410 Compensate. Floor:
37411 if (x2 > x)
37412 x2 -= 1;
37413 Compensate. Ceil:
37414 if (x2 < x)
37415 x2 -= -1;
37416 return x2;
37417 */
37423 /* Temporary for holding the result, initialized to the input
37424 operand to ease control flow. */
37428 /* xa = abs (operand1) */
37431 /* if (!isless (xa, TWO52)) goto label; */
37434 /* xa = xa + TWO52 - TWO52; */
37438 /* xa = copysign (xa, operand1) */
37441 /* generate 1.0 or -1.0 */
37446 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37450 /* We always need to subtract here to preserve signed zero. */
37459 }
37461 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37462 into OPERAND0. */
37463 void
37465 {
37466 /* C code for the stuff we expand below.
37467 double xa = fabs (x), x2;
37468 if (!isless (xa, TWO52))
37469 return x;
37470 x2 = (double)(long)x;
37471 Compensate. Floor:
37472 if (x2 > x)
37473 x2 -= 1;
37474 Compensate. Ceil:
37475 if (x2 < x)
37476 x2 += 1;
37477 if (HONOR_SIGNED_ZEROS (mode))
37478 return copysign (x2, x);
37479 return x2;
37480 */
37486 /* Temporary for holding the result, initialized to the input
37487 operand to ease control flow. */
37491 /* xa = abs (operand1) */
37494 /* if (!isless (xa, TWO52)) goto label; */
37497 /* xa = (double)(long)x */
37502 /* generate 1.0 */
37505 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37520 }
37522 /* Expand SSE sequence for computing round from OPERAND1 storing
37523 into OPERAND0. Sequence that works without relying on DImode truncation
37524 via cvttsd2siq that is only available on 64bit targets. */
37525 void
37527 {
37528 /* C code for the stuff we expand below.
37529 double xa = fabs (x), xa2, x2;
37530 if (!isless (xa, TWO52))
37531 return x;
37532 Using the absolute value and copying back sign makes
37533 -0.0 -> -0.0 correct.
37534 xa2 = xa + TWO52 - TWO52;
37535 Compensate.
37536 dxa = xa2 - xa;
37537 if (dxa <= -0.5)
37538 xa2 += 1;
37539 else if (dxa > 0.5)
37540 xa2 -= 1;
37541 x2 = copysign (xa2, x);
37542 return x2;
37543 */
37549 /* Temporary for holding the result, initialized to the input
37550 operand to ease control flow. */
37554 /* xa = abs (operand1) */
37557 /* if (!isless (xa, TWO52)) goto label; */
37560 /* xa2 = xa + TWO52 - TWO52; */
37564 /* dxa = xa2 - xa; */
37567 /* generate 0.5, 1.0 and -0.5 */
37573 /* Compensate. */
37575 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
37580 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
37586 /* res = copysign (xa2, operand1) */
37593 }
37595 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37596 into OPERAND0. */
37597 void
37599 {
37600 /* C code for SSE variant we expand below.
37601 double xa = fabs (x), x2;
37602 if (!isless (xa, TWO52))
37603 return x;
37604 x2 = (double)(long)x;
37605 if (HONOR_SIGNED_ZEROS (mode))
37606 return copysign (x2, x);
37607 return x2;
37608 */
37614 /* Temporary for holding the result, initialized to the input
37615 operand to ease control flow. */
37619 /* xa = abs (operand1) */
37622 /* if (!isless (xa, TWO52)) goto label; */
37625 /* x = (double)(long)x */
37637 }
37639 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37640 into OPERAND0. */
37641 void
37643 {
37647 /* C code for SSE variant we expand below.
37648 double xa = fabs (x), x2;
37649 if (!isless (xa, TWO52))
37650 return x;
37651 xa2 = xa + TWO52 - TWO52;
37652 Compensate:
37653 if (xa2 > xa)
37654 xa2 -= 1.0;
37655 x2 = copysign (xa2, x);
37656 return x2;
37657 */
37661 /* Temporary for holding the result, initialized to the input
37662 operand to ease control flow. */
37666 /* xa = abs (operand1) */
37669 /* if (!isless (xa, TWO52)) goto label; */
37672 /* res = xa + TWO52 - TWO52; */
37677 /* generate 1.0 */
37680 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
37688 /* res = copysign (res, operand1) */
37695 }
37697 /* Expand SSE sequence for computing round from OPERAND1 storing
37698 into OPERAND0. */
37699 void
37701 {
37702 /* C code for the stuff we're doing below:
37703 double xa = fabs (x);
37704 if (!isless (xa, TWO52))
37705 return x;
37706 xa = (double)(long)(xa + nextafter (0.5, 0.0));
37707 return copysign (xa, x);
37708 */
37714 /* Temporary for holding the result, initialized to the input
37715 operand to ease control flow. */
37723 /* load nextafter (0.5, 0.0) */
37728 /* xa = xa + 0.5 */
37732 /* xa = (double)(int64_t)xa */
37737 /* res = copysign (xa, operand1) */
37744 }
37746 /* Expand SSE sequence for computing round
37747 from OP1 storing into OP0 using sse4 round insn. */
37748 void
37750 {
37759 {
37770 }
37772 /* round (a) = trunc (a + copysign (0.5, a)) */
37774 /* load nextafter (0.5, 0.0) */
37780 /* e1 = copysign (0.5, op1) */
37784 /* e2 = op1 + e1 */
37787 /* res = trunc (e2) */
37792 }
37793 \f
37795 /* Table of valid machine attributes. */
37797 {
37798 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
37799 affects_type_identity } */
37800 /* Stdcall attribute says callee is responsible for popping arguments
37801 if they are not variable. */
37804 /* Fastcall attribute says callee is responsible for popping arguments
37805 if they are not variable. */
37808 /* Thiscall attribute says callee is responsible for popping arguments
37809 if they are not variable. */
37812 /* Cdecl attribute says the callee is a normal C declaration */
37815 /* Regparm attribute specifies how many integer arguments are to be
37816 passed in registers. */
37819 /* Sseregparm attribute says we are using x86_64 calling conventions
37820 for FP arguments. */
37823 /* The transactional memory builtins are implicitly regparm or fastcall
37824 depending on the ABI. Override the generic do-nothing attribute that
37825 these builtins were declared with. */
37828 /* force_align_arg_pointer says this function realigns the stack at entry. */
37831 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
37836 #endif
37841 #ifdef SUBTARGET_ATTRIBUTE_TABLE
37842 SUBTARGET_ATTRIBUTE_TABLE,
37843 #endif
37844 /* ms_abi and sysv_abi calling convention function attributes. */
37851 /* End element. */
37853 };
37855 /* Implement targetm.vectorize.builtin_vectorization_cost. */
37856 static int
37858 tree vectype,
37860 {
37864 {
37909 }
37910 }
37912 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
37913 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
37914 insn every time. */
37918 /* Initialize vselect_insn. */
37920 static void
37922 {
37924 rtx x;
37935 }
37937 /* Construct (set target (vec_select op0 (parallel perm))) and
37938 return true if that's a valid instruction in the active ISA. */
37940 static bool
37943 {
37969 }
37971 /* Similar, but generate a vec_concat from op0 and op1 as well. */
37973 static bool
37977 {
37979 rtx x;
37994 }
37996 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
37997 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
37999 static bool
38001 {
38010 ;
38012 ;
38014 ;
38015 else
38018 /* This is a blend, not a permute. Elements must stay in their
38019 respective lanes. */
38021 {
38025 }
38030 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38031 decision should be extracted elsewhere, so that we only try that
38032 sequence once all budget==3 options have been tried. */
38039 {
38063 /* See if bytes move in pairs so we can use pblendw with
38064 an immediate argument, rather than pblendvb with a vector
38065 argument. */
38068 {
38069 use_pblendvb:
38073 finish_pblendvb:
38079 else
38082 }
38087 /* FALLTHRU */
38089 do_subreg:
38096 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38100 /* See if bytes move in quadruplets. If yes, vpblendd
38101 with immediate can be used. */
38106 {
38107 /* See if bytes move the same in both lanes. If yes,
38108 vpblendw with immediate can be used. */
38113 /* Use vpblendw. */
38118 }
38120 /* Use vpblendd. */
38127 /* See if words move in pairs. If yes, vpblendd can be used. */
38132 {
38133 /* See if words move the same in both lanes. If not,
38134 vpblendvb must be used. */
38137 {
38138 /* Use vpblendvb. */
38148 }
38150 /* Use vpblendw. */
38154 }
38156 /* Use vpblendd. */
38163 /* Use vpblendd. */
38171 }
38173 /* This matches five different patterns with the different modes. */
38179 }
38181 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38182 in terms of the variable form of vpermilps.
38184 Note that we will have already failed the immediate input vpermilps,
38185 which requires that the high and low part shuffle be identical; the
38186 variable form doesn't require that. */
38188 static bool
38190 {
38197 /* We can only permute within the 128-bit lane. */
38199 {
38203 }
38209 {
38212 /* Within each 128-bit lane, the elements of op0 are numbered
38213 from 0 and the elements of op1 are numbered from 4. */
38220 }
38227 }
38229 /* Return true if permutation D can be performed as VMODE permutation
38230 instead. */
38232 static bool
38234 {
38249 else
38255 }
38257 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38258 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38260 static bool
38262 {
38271 {
38273 {
38276 {
38280 /* Use vperm2i128 insn. The pattern uses
38281 V4DImode instead of V2TImode. */
38290 }
38292 }
38293 }
38294 else
38295 {
38297 {
38300 }
38302 {
38306 /* V4DImode should be already handled through
38307 expand_vselect by vpermq instruction. */
38314 {
38315 /* First see if vpermq can be used for
38316 V8SImode/V16HImode/V32QImode. */
38318 {
38326 }
38328 /* Next see if vpermd can be used. */
38331 }
38332 /* Or if vpermps can be used. */
38337 {
38338 /* vpshufb only works intra lanes, it is not
38339 possible to shuffle bytes in between the lanes. */
38343 }
38344 }
38345 else
38347 }
38355 else
38356 {
38362 else
38366 {
38370 }
38371 }
38380 {
38387 else
38389 }
38390 else
38391 {
38394 }
38397 }
38399 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38400 in a single instruction. */
38402 static bool
38404 {
38408 /* Check plain VEC_SELECT first, because AVX has instructions that could
38409 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38410 input where SEL+CONCAT may not. */
38412 {
38418 {
38424 }
38427 {
38431 }
38433 {
38434 /* Use vpbroadcast{b,w,d}. */
38437 {
38456 /* For other modes prefer other shuffles this function creates. */
38458 }
38460 {
38464 }
38465 }
38470 /* There are plenty of patterns in sse.md that are written for
38471 SEL+CONCAT and are not replicated for a single op. Perhaps
38472 that should be changed, to avoid the nastiness here. */
38474 /* Recognize interleave style patterns, which means incrementing
38475 every other permutation operand. */
38477 {
38480 }
38485 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38487 {
38489 {
38494 }
38499 }
38500 }
38502 /* Finally, try the fully general two operand permute. */
38507 /* Recognize interleave style patterns with reversed operands. */
38509 {
38511 {
38515 else
38518 }
38523 }
38525 /* Try the SSE4.1 blend variable merge instructions. */
38529 /* Try one of the AVX vpermil variable permutations. */
38533 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
38534 vpshufb, vpermd, vpermps or vpermq variable permutation. */
38539 }
38541 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38542 in terms of a pair of pshuflw + pshufhw instructions. */
38544 static bool
38546 {
38554 /* The two permutations only operate in 64-bit lanes. */
38565 /* Emit the pshuflw. */
38572 /* Emit the pshufhw. */
38580 }
38582 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38583 the permutation using the SSSE3 palignr instruction. This succeeds
38584 when all of the elements in PERM fit within one vector and we merely
38585 need to shift them down so that a single vector permutation has a
38586 chance to succeed. */
38588 static bool
38590 {
38594 rtx shift;
38596 /* Even with AVX, palignr only operates on 128-bit vectors. */
38602 {
38608 }
38612 /* Given that we have SSSE3, we know we'll be able to implement the
38613 single operand permutation after the palignr with pshufb. */
38627 {
38632 }
38634 /* Test for the degenerate case where the alignment by itself
38635 produces the desired permutation. */
38643 }
38647 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38648 a two vector permutation into a single vector permutation by using
38649 an interleave operation to merge the vectors. */
38651 static bool
38653 {
38658 rtx seq;
38662 {
38665 }
38667 {
38670 /* For 32-byte modes allow even d->one_operand_p.
38671 The lack of cross-lane shuffling in some instructions
38672 might prevent a single insn shuffle. */
38675 /* If expand_vec_perm_interleave3 can expand this into
38676 a 3 insn sequence, give up and let it be expanded as
38677 3 insn sequence. While that is one insn longer,
38678 it doesn't need a memory operand and in the common
38679 case that both interleave low and high permutations
38680 with the same operands are adjacent needs 4 insns
38681 for both after CSE. */
38684 }
38685 else
38688 /* Examine from whence the elements come. */
38697 {
38700 /* Split the two input vectors into 4 halves. */
38706 /* If the elements from the low halves use interleave low, and similarly
38707 for interleave high. If the elements are from mis-matched halves, we
38708 can use shufps for V4SF/V4SI or do a DImode shuffle. */
38710 {
38711 /* punpckl* */
38713 {
38718 }
38721 }
38723 {
38724 /* punpckh* */
38726 {
38731 }
38734 }
38736 {
38737 /* shufps */
38739 {
38744 }
38746 {
38747 /* shufpd */
38752 }
38753 }
38755 {
38756 /* shufps */
38758 {
38763 }
38765 {
38766 /* shufpd */
38771 }
38772 }
38773 else
38775 }
38776 else
38777 {
38782 /* Split the two input vectors into 8 quarters. */
38788 {
38791 }
38794 {
38798 }
38800 {
38803 }
38806 {
38808 {
38809 /* Attempt to increase the likelihood that dfinal
38810 shuffle will be intra-lane. */
38814 }
38816 /* vperm2f128 or vperm2i128. */
38818 {
38823 }
38828 {
38832 {
38835 }
38836 }
38837 }
38842 {
38843 /* vpunpckl* */
38845 {
38854 }
38855 }
38858 {
38859 /* vpunpckh* */
38861 {
38870 }
38871 }
38872 else
38874 }
38876 /* Use the remapping array set up above to move the elements from their
38877 swizzled locations into their final destinations. */
38880 {
38883 /* If same_halves is true, both halves of the remapped vector are the
38884 same. Avoid cross-lane accesses if possible. */
38886 {
38889 }
38890 else
38892 }
38898 /* Test if the final remap can be done with a single insn. For V4SFmode or
38899 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
38912 {
38916 }
38923 }
38925 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38926 a single vector cross-lane permutation into vpermq followed
38927 by any of the single insn permutations. */
38929 static bool
38931 {
38945 {
38948 }
38951 {
38956 }
38969 {
38976 }
38983 {
38988 ;
38991 else
38993 }
39002 }
39004 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39005 a vector permutation using two instructions, vperm2f128 resp.
39006 vperm2i128 followed by any single in-lane permutation. */
39008 static bool
39010 {
39024 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39025 immediate. For perm < 16 the second permutation uses
39026 d->op0 as first operand, for perm >= 16 it uses d->op1
39027 as first operand. The second operand is the result of
39028 vperm2[fi]128. */
39030 {
39031 /* Ignore permutations which do not move anything cross-lane. */
39033 {
39034 /* The second shuffle for e.g. V4DFmode has
39035 0123 and ABCD operands.
39036 Ignore AB23, as 23 is already in the second lane
39037 of the first operand. */
39039 /* And 01CD, as 01 is in the first lane of the first
39040 operand. */
39042 /* And 4567, as then the vperm2[fi]128 doesn't change
39043 anything on the original 4567 second operand. */
39045 }
39046 else
39047 {
39048 /* The second shuffle for e.g. V4DFmode has
39049 4567 and ABCD operands.
39050 Ignore AB67, as 67 is already in the second lane
39051 of the first operand. */
39053 /* And 45CD, as 45 is in the first lane of the first
39054 operand. */
39056 /* And 0123, as then the vperm2[fi]128 doesn't change
39057 anything on the original 0123 first operand. */
39059 }
39062 {
39068 else
39070 }
39073 {
39077 }
39078 else
39082 {
39086 /* Found a usable second shuffle. dfirst will be
39087 vperm2f128 on d->op0 and d->op1. */
39098 /* And dsecond is some single insn shuffle, taking
39099 d->op0 and result of vperm2f128 (if perm < 16) or
39100 d->op1 and result of vperm2f128 (otherwise). */
39109 }
39111 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39114 }
39117 }
39119 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39120 a two vector permutation using 2 intra-lane interleave insns
39121 and cross-lane shuffle for 32-byte vectors. */
39123 static bool
39125 {
39132 ;
39134 ;
39135 else
39150 {
39154 else
39160 else
39166 else
39172 else
39178 else
39184 else
39189 }
39193 }
39195 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39196 a single vector permutation using a single intra-lane vector
39197 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39198 the non-swapped and swapped vectors together. */
39200 static bool
39202 {
39205 rtx seq;
39210 || TARGET_AVX2
39219 {
39226 }
39261 }
39263 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39264 permutation using two vperm2f128, followed by a vshufpd insn blending
39265 the two vectors together. */
39267 static bool
39269 {
39312 }
39314 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39315 permutation with two pshufb insns and an ior. We should have already
39316 failed all two instruction sequences. */
39318 static bool
39320 {
39331 /* Generate two permutation masks. If the required element is within
39332 the given vector it is shuffled into the proper lane. If the required
39333 element is in the other vector, force a zero into the lane by setting
39334 bit 7 in the permutation mask. */
39337 {
39344 {
39347 }
39348 }
39368 }
39370 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39371 with two vpshufb insns, vpermq and vpor. We should have already failed
39372 all two or three instruction sequences. */
39374 static bool
39376 {
39391 /* Generate two permutation masks. If the required element is within
39392 the same lane, it is shuffled in. If the required element from the
39393 other lane, force a zero by setting bit 7 in the permutation mask.
39394 In the other mask the mask has non-negative elements if element
39395 is requested from the other lane, but also moved to the other lane,
39396 so that the result of vpshufb can have the two V2TImode halves
39397 swapped. */
39400 {
39405 {
39408 }
39409 }
39418 /* Swap the 128-byte lanes of h into hp. */
39422 const1_rtx));
39435 }
39437 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39438 and extract-odd permutations of two V32QImode and V16QImode operand
39439 with two vpshufb insns, vpor and vpermq. We should have already
39440 failed all two or three instruction sequences. */
39442 static bool
39444 {
39463 /* Generate two permutation masks. In the first permutation mask
39464 the first quarter will contain indexes for the first half
39465 of the op0, the second quarter will contain bit 7 set, third quarter
39466 will contain indexes for the second half of the op0 and the
39467 last quarter bit 7 set. In the second permutation mask
39468 the first quarter will contain bit 7 set, the second quarter
39469 indexes for the first half of the op1, the third quarter bit 7 set
39470 and last quarter indexes for the second half of the op1.
39471 I.e. the first mask e.g. for V32QImode extract even will be:
39472 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39473 (all values masked with 0xf except for -128) and second mask
39474 for extract even will be
39475 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39478 {
39484 {
39487 }
39488 }
39507 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
39514 }
39516 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
39517 and extract-odd permutations. */
39519 static bool
39521 {
39525 {
39530 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39534 /* Now an unpck[lh]pd will produce the result required. */
39537 else
39543 {
39550 /* Shuffle within the 128-bit lanes to produce:
39551 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
39555 /* Shuffle the lanes around to produce:
39556 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
39560 /* Shuffle within the 128-bit lanes to produce:
39561 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
39564 /* Shuffle within the 128-bit lanes to produce:
39565 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
39568 /* Shuffle the lanes around to produce:
39569 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
39572 }
39579 /* These are always directly implementable by expand_vec_perm_1. */
39585 else
39586 {
39587 /* We need 2*log2(N)-1 operations to achieve odd/even
39588 with interleave. */
39597 else
39600 }
39606 else
39607 {
39619 else
39622 }
39631 {
39638 }
39643 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39647 /* Now an vpunpck[lh]qdq will produce the result required. */
39650 else
39657 {
39664 }
39669 /* Shuffle the lanes around into
39670 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
39680 /* Swap the 2nd and 3rd position in each lane into
39681 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
39687 /* Now an vpunpck[lh]qdq will produce
39688 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
39693 else
39702 }
39705 }
39707 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
39708 extract-even and extract-odd permutations. */
39710 static bool
39712 {
39724 }
39726 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
39727 permutations. We assume that expand_vec_perm_1 has already failed. */
39729 static bool
39731 {
39739 {
39742 /* These are special-cased in sse.md so that we can optionally
39743 use the vbroadcast instruction. They expand to two insns
39744 if the input happens to be in a register. */
39751 /* These are always implementable using standard shuffle patterns. */
39756 /* These can be implemented via interleave. We save one insn by
39757 stopping once we have promoted to V4SImode and then use pshufd. */
39758 do
39759 {
39760 rtx dest;
39766 {
39770 }
39777 }
39790 /* For AVX2 broadcasts of the first element vpbroadcast* or
39791 vpermq should be used by expand_vec_perm_1. */
39797 }
39798 }
39800 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
39801 broadcast permutations. */
39803 static bool
39805 {
39817 }
39819 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
39820 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
39821 all the shorter instruction sequences. */
39823 static bool
39825 {
39841 /* Generate 4 permutation masks. If the required element is within
39842 the same lane, it is shuffled in. If the required element from the
39843 other lane, force a zero by setting bit 7 in the permutation mask.
39844 In the other mask the mask has non-negative elements if element
39845 is requested from the other lane, but also moved to the other lane,
39846 so that the result of vpshufb can have the two V2TImode halves
39847 swapped. */
39850 {
39855 }
39861 {
39869 }
39872 {
39874 {
39877 }
39884 }
39886 /* Swap the 128-byte lanes of h[X]. */
39888 {
39894 const1_rtx));
39896 }
39899 {
39901 {
39904 }
39910 }
39913 {
39915 {
39919 }
39922 }
39928 }
39930 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
39931 With all of the interface bits taken care of, perform the expansion
39932 in D and return true on success. */
39934 static bool
39936 {
39937 /* Try a single instruction expansion. */
39941 /* Try sequences of two instructions. */
39961 /* Try sequences of three instructions. */
39975 /* Try sequences of four instructions. */
39983 /* ??? Look for narrow permutations whose element orderings would
39984 allow the promotion to a wider mode. */
39986 /* ??? Look for sequences of interleave or a wider permute that place
39987 the data into the correct lanes for a half-vector shuffle like
39988 pshuf[lh]w or vpermilps. */
39990 /* ??? Look for sequences of interleave that produce the desired results.
39991 The combinatorics of punpck[lh] get pretty ugly... */
39996 /* Even longer sequences. */
40001 }
40003 /* If a permutation only uses one operand, make it clear. Returns true
40004 if the permutation references both operands. */
40006 static bool
40008 {
40016 {
40022 {
40025 }
40026 /* The elements of PERM do not suggest that only the first operand
40027 is used, but both operands are identical. Allow easier matching
40028 of the permutation by folding the permutation into the single
40029 input vector. */
40030 /* FALLTHRU */
40041 }
40044 }
40046 bool
40048 {
40053 rtx sel;
40070 {
40075 }
40082 /* If the selector says both arguments are needed, but the operands are the
40083 same, the above tried to expand with one_operand_p and flattened selector.
40084 If that didn't work, retry without one_operand_p; we succeeded with that
40085 during testing. */
40087 {
40091 }
40094 }
40096 /* Implement targetm.vectorize.vec_perm_const_ok. */
40098 static bool
40101 {
40110 /* Given sufficient ISA support we can just return true here
40111 for selected vector modes. */
40113 {
40114 /* All implementable with a single vpperm insn. */
40117 /* All implementable with 2 pshufb + 1 ior. */
40120 /* All implementable with shufpd or unpck[lh]pd. */
40123 }
40125 /* Extract the values from the vector CST into the permutation
40126 array in D. */
40129 {
40133 }
40135 /* For all elements from second vector, fold the elements to first. */
40140 /* Check whether the mask can be applied to the vector type. */
40143 /* Implementable with shufps or pshufd. */
40147 /* Otherwise we have to go through the motions and see if we can
40148 figure out how to generate the requested permutation. */
40159 }
40161 void
40163 {
40178 /* We'll either be able to implement the permutation directly... */
40182 /* ... or we use the special-case patterns. */
40184 }
40186 static void
40188 {
40203 {
40206 }
40208 /* Note that for AVX this isn't one instruction. */
40211 }
40214 /* Expand a vector operation CODE for a V*QImode in terms of the
40215 same operation on V*HImode. */
40217 void
40219 {
40231 {
40244 }
40248 {
40250 /* Unpack data such that we've got a source byte in each low byte of
40251 each word. We don't care what goes into the high byte of each word.
40252 Rather than trying to get zero in there, most convenient is to let
40253 it be a copy of the low byte. */
40258 /* FALLTHRU */
40270 /* FALLTHRU */
40280 }
40282 /* Perform the operation. */
40289 /* Merge the data back into the right place. */
40299 {
40300 /* For SSE2, we used an full interleave, so the desired
40301 results are in the even elements. */
40304 }
40305 else
40306 {
40307 /* For AVX, the interleave used above was not cross-lane. So the
40308 extraction is evens but with the second and third quarter swapped.
40309 Happily, that is even one insn shorter than even extraction. */
40312 }
40319 }
40321 void
40324 {
40327 rtx x;
40329 /* We only play even/odd games with vectors of SImode. */
40332 /* If we're looking for the odd results, shift those members down to
40333 the even slots. For some cpus this is faster than a PSHUFD. */
40335 {
40337 {
40341 }
40350 }
40353 {
40356 else
40358 }
40363 else
40364 {
40367 /* The easiest way to implement this without PMULDQ is to go through
40368 the motions as if we are performing a full 64-bit multiply. With
40369 the exception that we need to do less shuffling of the elements. */
40371 /* Compute the sign-extension, aka highparts, of the two operands. */
40377 /* Multiply LO(A) * HI(B), and vice-versa. */
40383 /* Multiply LO(A) * LO(B). */
40387 /* Combine and shift the highparts into place. */
40392 /* Combine high and low parts. */
40395 }
40397 }
40399 void
40402 {
40408 {
40413 {
40414 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40415 shuffle the elements once so that all elements are in the right
40416 place for immediate use: { A C B D }. */
40421 }
40422 else
40423 {
40424 /* Put the elements into place for the multiply. */
40428 }
40433 /* Shuffle the elements between the lanes. After this we
40434 have { A B E F | C D G H } for each operand. */
40444 /* Shuffle the elements within the lanes. After this we
40445 have { A A B B | C C D D } or { E E F F | G G H H }. */
40481 }
40482 }
40484 void
40486 {
40496 /* Move the results in element 2 down to element 1; we don't care
40497 what goes in elements 2 and 3. Then we can merge the parts
40498 back together with an interleave.
40500 Note that two other sequences were tried:
40501 (1) Use interleaves at the start instead of psrldq, which allows
40502 us to use a single shufps to merge things back at the end.
40503 (2) Use shufps here to combine the two vectors, then pshufd to
40504 put the elements in the correct order.
40505 In both cases the cost of the reformatting stall was too high
40506 and the overall sequence slower. */
40515 }
40517 void
40519 {
40524 {
40525 /* op1: A,B,C,D, op2: E,F,G,H */
40534 /* t1: B,A,D,C */
40541 /* t2: (B*E),(A*F),(D*G),(C*H) */
40544 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
40547 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
40550 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
40552 }
40553 else
40554 {
40559 {
40562 }
40564 {
40567 }
40568 else
40572 /* Multiply low parts. */
40576 /* Shift input vectors right 32 bits so we can multiply high parts. */
40581 /* Multiply high parts by low parts. */
40587 /* Combine and shift the highparts back. */
40591 /* Combine high and low parts. */
40593 }
40597 }
40599 /* Expand an insert into a vector register through pinsr insn.
40600 Return true if successful. */
40602 bool
40604 {
40612 {
40615 }
40621 {
40626 {
40633 {
40665 }
40674 }
40678 }
40679 }
40680 \f
40681 /* This function returns the calling abi specific va_list type node.
40682 It returns the FNDECL specific va_list type. */
40684 static tree
40686 {
40693 else
40695 }
40697 /* Returns the canonical va_list type specified by TYPE. If there
40698 is no valid TYPE provided, it return NULL_TREE. */
40700 static tree
40702 {
40705 /* Resolve references and pointers to va_list type. */
40714 {
40719 {
40720 /* If va_list is an array type, the argument may have decayed
40721 to a pointer type, e.g. by being passed to another function.
40722 In that case, unwrap both types so that we can compare the
40723 underlying records. */
40726 {
40729 }
40730 }
40737 {
40738 /* If va_list is an array type, the argument may have decayed
40739 to a pointer type, e.g. by being passed to another function.
40740 In that case, unwrap both types so that we can compare the
40741 underlying records. */
40744 {
40747 }
40748 }
40755 {
40756 /* If va_list is an array type, the argument may have decayed
40757 to a pointer type, e.g. by being passed to another function.
40758 In that case, unwrap both types so that we can compare the
40759 underlying records. */
40762 {
40765 }
40766 }
40770 }
40772 }
40774 /* Iterate through the target-specific builtin types for va_list.
40775 IDX denotes the iterator, *PTREE is set to the result type of
40776 the va_list builtin, and *PNAME to its internal type.
40777 Returns zero if there is no element for this index, otherwise
40778 IDX should be increased upon the next call.
40779 Note, do not iterate a base builtin's name like __builtin_va_list.
40780 Used from c_common_nodes_and_builtins. */
40782 static int
40784 {
40786 {
40788 {
40801 }
40802 }
40805 }
40807 #undef TARGET_SCHED_DISPATCH
40808 #define TARGET_SCHED_DISPATCH has_dispatch
40809 #undef TARGET_SCHED_DISPATCH_DO
40810 #define TARGET_SCHED_DISPATCH_DO do_dispatch
40811 #undef TARGET_SCHED_REASSOCIATION_WIDTH
40812 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
40813 #undef TARGET_SCHED_REORDER
40814 #define TARGET_SCHED_REORDER ix86_sched_reorder
40815 #undef TARGET_SCHED_ADJUST_PRIORITY
40816 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
40817 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
40818 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
40820 /* The size of the dispatch window is the total number of bytes of
40821 object code allowed in a window. */
40822 #define DISPATCH_WINDOW_SIZE 16
40824 /* Number of dispatch windows considered for scheduling. */
40825 #define MAX_DISPATCH_WINDOWS 3
40827 /* Maximum number of instructions in a window. */
40828 #define MAX_INSN 4
40830 /* Maximum number of immediate operands in a window. */
40831 #define MAX_IMM 4
40833 /* Maximum number of immediate bits allowed in a window. */
40834 #define MAX_IMM_SIZE 128
40836 /* Maximum number of 32 bit immediates allowed in a window. */
40837 #define MAX_IMM_32 4
40839 /* Maximum number of 64 bit immediates allowed in a window. */
40840 #define MAX_IMM_64 2
40842 /* Maximum total of loads or prefetches allowed in a window. */
40843 #define MAX_LOAD 2
40845 /* Maximum total of stores allowed in a window. */
40846 #define MAX_STORE 1
40848 #undef BIG
40849 #define BIG 100
40852 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
40855 disp_load,
40856 disp_store,
40857 disp_load_store,
40858 disp_prefetch,
40859 disp_imm,
40860 disp_imm_32,
40861 disp_imm_64,
40862 disp_branch,
40863 disp_cmp,
40864 disp_jcc,
40865 disp_last
40866 };
40868 /* Number of allowable groups in a dispatch window. It is an array
40869 indexed by dispatch_group enum. 100 is used as a big number,
40870 because the number of these kind of operations does not have any
40871 effect in dispatch window, but we need them for other reasons in
40872 the table. */
40875 };
40881 };
40883 /* Instruction path. */
40889 last_path
40890 };
40892 /* sched_insn_info defines a window to the instructions scheduled in
40893 the basic block. It contains a pointer to the insn_info table and
40894 the instruction scheduled.
40896 Windows are allocated for each basic block and are linked
40897 together. */
40899 rtx insn;
40906 /* Linked list of dispatch windows. This is a two way list of
40907 dispatch windows of a basic block. It contains information about
40908 the number of uops in the window and the total number of
40909 instructions and of bytes in the object code for this dispatch
40910 window. */
40928 /* Immediate valuse used in an insn. */
40930 {
40939 /* Get dispatch group of insn. */
40941 static enum dispatch_group
40943 {
40959 }
40961 /* Return true if insn is a compare instruction. */
40963 static bool
40965 {
40973 }
40975 /* Return true if a dispatch violation encountered. */
40977 static bool
40979 {
40983 }
40985 /* Return true if insn is a branch instruction. */
40987 static bool
40989 {
40991 }
40993 /* Return true if insn is a prefetch instruction. */
40995 static bool
40997 {
40999 }
41001 /* This function initializes a dispatch window and the list container holding a
41002 pointer to the window. */
41004 static void
41006 {
41012 else
41030 {
41036 }
41038 }
41040 /* This function allocates and initializes a dispatch window and the
41041 list container holding a pointer to the window. */
41045 {
41050 }
41052 /* This routine initializes the dispatch scheduling information. It
41053 initiates building dispatch scheduler tables and constructs the
41054 first dispatch window. */
41056 static void
41058 {
41059 /* Allocate a dispatch list and a window. */
41064 }
41066 /* This function returns true if a branch is detected. End of a basic block
41067 does not have to be a branch, but here we assume only branches end a
41068 window. */
41070 static bool
41072 {
41074 }
41076 /* This function is called when the end of a window processing is reached. */
41078 static void
41080 {
41083 {
41088 }
41090 }
41092 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41093 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41094 for 48 bytes of instructions. Note that these windows are not dispatch
41095 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41099 {
41101 {
41106 }
41112 }
41114 /* Increment the number of immediate operands of an instruction. */
41116 static int
41118 {
41123 {
41130 else
41141 {
41144 }
41149 }
41152 }
41154 /* Compute number of immediate operands of an instruction. */
41156 static void
41158 {
41161 }
41163 /* Return total size of immediate operands of an instruction along with number
41164 of corresponding immediate-operands. It initializes its parameters to zero
41165 befor calling FIND_CONSTANT.
41166 INSN is the input instruction. IMM is the total of immediates.
41167 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41168 bit immediates. */
41170 static int
41172 {
41180 }
41182 /* This function indicates if an operand of an instruction is an
41183 immediate. */
41185 static bool
41187 {
41196 }
41198 /* Return single or double path for instructions. */
41200 static enum insn_path
41202 {
41212 }
41214 /* Return insn dispatch group. */
41216 static enum dispatch_group
41218 {
41236 }
41238 /* Count number of GROUP restricted instructions in a dispatch
41239 window WINDOW_LIST. */
41241 static int
41243 {
41254 {
41273 }
41286 }
41288 /* This function returns true if insn satisfies dispatch rules on the
41289 last window scheduled. */
41291 static bool
41293 {
41301 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41302 instructions should be given the lowest priority in the
41303 scheduling process in Haifa scheduler to make sure they will be
41304 scheduled in the same dispatch window as the reference to them. */
41308 /* Check nonrestricted. */
41312 /* Get last dispatch window. */
41317 {
41322 /* Window 1 is full. Go for next window. */
41324 }
41331 /* See if it fits in the first window. */
41333 {
41334 /* The first widow should have only single and double path
41335 uops. */
41341 }
41343 }
41345 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41346 dispatch window WINDOW_LIST. */
41348 static void
41350 {
41368 /* Initialize window with new instruction. */
41389 {
41392 }
41393 }
41395 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41396 If the total bytes of instructions or the number of instructions in
41397 the window exceed allowable, it allocates a new window. */
41399 static void
41401 {
41424 /* Get the last dispatch window. */
41432 else
41435 /* If current window is full, get a new window.
41436 Window number zero is full, if MAX_INSN uops are scheduled in it.
41437 Window number one is full, if window zero's bytes plus window
41438 one's bytes is 32, or if the bytes of the new instruction added
41439 to the total makes it greater than 48, or it has already MAX_INSN
41440 instructions in it. */
41449 {
41452 }
41455 {
41459 {
41462 }
41463 }
41465 {
41470 {
41473 }
41476 }
41477 else
41481 {
41482 /* End of basic block is reached do end-basic-block process. */
41485 }
41486 }
41488 /* Print the dispatch window, WINDOW_NUM, to FILE. */
41490 DEBUG_FUNCTION static void
41492 {
41498 else
41512 {
41515 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
41521 }
41522 }
41524 /* Print to stdout a dispatch window. */
41526 DEBUG_FUNCTION void
41528 {
41530 }
41532 /* Print INSN dispatch information to FILE. */
41534 DEBUG_FUNCTION static void
41536 {
41559 }
41561 /* Print to STDERR the status of the ready list with respect to
41562 dispatch windows. */
41564 DEBUG_FUNCTION void
41566 {
41574 }
41576 /* This routine is the driver of the dispatch scheduler. */
41578 static void
41580 {
41585 }
41587 /* Return TRUE if Dispatch Scheduling is supported. */
41589 static bool
41591 {
41595 {
41611 }
41614 }
41616 /* Implementation of reassociation_width target hook used by
41617 reassoc phase to identify parallelism level in reassociated
41618 tree. Statements tree_code is passed in OPC. Arguments type
41619 is passed in MODE.
41621 Currently parallel reassociation is enabled for Atom
41622 processors only and we set reassociation width to be 2
41623 because Atom may issue up to 2 instructions per cycle.
41625 Return value should be fixed if parallel reassociation is
41626 enabled for other processors. */
41628 static int
41631 {
41640 }
41642 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
41643 place emms and femms instructions. */
41645 static enum machine_mode
41647 {
41652 {
41665 else
41675 /* FALLTHRU */
41679 }
41680 }
41682 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
41683 vectors. */
41685 static unsigned int
41687 {
41689 }
41691 \f
41693 /* Return class of registers which could be used for pseudo of MODE
41694 and of class RCLASS for spilling instead of memory. Return NO_REGS
41695 if it is not possible or non-profitable. */
41696 static reg_class_t
41698 {
41705 }
41707 /* Implement targetm.vectorize.init_cost. */
41711 {
41715 }
41717 /* Implement targetm.vectorize.add_stmt_cost. */
41719 static unsigned
41723 {
41728 {
41732 /* Statements in an inner loop relative to the loop being
41733 vectorized are weighted more heavily. The value here is
41734 arbitrary and could potentially be improved with analysis. */
41740 }
41743 }
41745 /* Implement targetm.vectorize.finish_cost. */
41747 static void
41750 {
41755 }
41757 /* Implement targetm.vectorize.destroy_cost_data. */
41759 static void
41761 {
41763 }
41765 /* Validate target specific memory model bits in VAL. */
41767 static unsigned HOST_WIDE_INT
41769 {
41776 {
41780 }
41783 {
41787 }
41789 {
41793 }
41795 }
41797 /* Initialize the GCC target structure. */
41798 #undef TARGET_RETURN_IN_MEMORY
41799 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
41801 #undef TARGET_LEGITIMIZE_ADDRESS
41802 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
41804 #undef TARGET_ATTRIBUTE_TABLE
41805 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
41806 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
41807 # undef TARGET_MERGE_DECL_ATTRIBUTES
41808 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
41809 #endif
41811 #undef TARGET_COMP_TYPE_ATTRIBUTES
41812 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
41814 #undef TARGET_INIT_BUILTINS
41815 #define TARGET_INIT_BUILTINS ix86_init_builtins
41816 #undef TARGET_BUILTIN_DECL
41817 #define TARGET_BUILTIN_DECL ix86_builtin_decl
41818 #undef TARGET_EXPAND_BUILTIN
41819 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
41821 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
41822 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
41823 ix86_builtin_vectorized_function
41825 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
41826 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
41828 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
41829 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
41831 #undef TARGET_VECTORIZE_BUILTIN_GATHER
41832 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
41834 #undef TARGET_BUILTIN_RECIPROCAL
41835 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
41837 #undef TARGET_ASM_FUNCTION_EPILOGUE
41838 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
41840 #undef TARGET_ENCODE_SECTION_INFO
41841 #ifndef SUBTARGET_ENCODE_SECTION_INFO
41842 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
41843 #else
41844 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
41845 #endif
41847 #undef TARGET_ASM_OPEN_PAREN
41849 #undef TARGET_ASM_CLOSE_PAREN
41852 #undef TARGET_ASM_BYTE_OP
41853 #define TARGET_ASM_BYTE_OP ASM_BYTE
41855 #undef TARGET_ASM_ALIGNED_HI_OP
41856 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
41857 #undef TARGET_ASM_ALIGNED_SI_OP
41858 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
41859 #ifdef ASM_QUAD
41860 #undef TARGET_ASM_ALIGNED_DI_OP
41861 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
41862 #endif
41864 #undef TARGET_PROFILE_BEFORE_PROLOGUE
41865 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
41867 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
41868 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
41870 #undef TARGET_ASM_UNALIGNED_HI_OP
41871 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
41872 #undef TARGET_ASM_UNALIGNED_SI_OP
41873 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
41874 #undef TARGET_ASM_UNALIGNED_DI_OP
41875 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
41877 #undef TARGET_PRINT_OPERAND
41878 #define TARGET_PRINT_OPERAND ix86_print_operand
41879 #undef TARGET_PRINT_OPERAND_ADDRESS
41880 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
41881 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
41882 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
41883 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
41884 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
41886 #undef TARGET_SCHED_INIT_GLOBAL
41887 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
41888 #undef TARGET_SCHED_ADJUST_COST
41889 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
41890 #undef TARGET_SCHED_ISSUE_RATE
41891 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
41892 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
41893 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
41894 ia32_multipass_dfa_lookahead
41896 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
41897 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
41899 #undef TARGET_MEMMODEL_CHECK
41900 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
41902 #ifdef HAVE_AS_TLS
41903 #undef TARGET_HAVE_TLS
41904 #define TARGET_HAVE_TLS true
41905 #endif
41906 #undef TARGET_CANNOT_FORCE_CONST_MEM
41907 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
41908 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
41909 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
41911 #undef TARGET_DELEGITIMIZE_ADDRESS
41912 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
41914 #undef TARGET_MS_BITFIELD_LAYOUT_P
41915 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
41917 #if TARGET_MACHO
41918 #undef TARGET_BINDS_LOCAL_P
41919 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
41920 #endif
41921 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
41922 #undef TARGET_BINDS_LOCAL_P
41923 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
41924 #endif
41926 #undef TARGET_ASM_OUTPUT_MI_THUNK
41927 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
41928 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
41929 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
41931 #undef TARGET_ASM_FILE_START
41932 #define TARGET_ASM_FILE_START x86_file_start
41934 #undef TARGET_OPTION_OVERRIDE
41935 #define TARGET_OPTION_OVERRIDE ix86_option_override
41937 #undef TARGET_REGISTER_MOVE_COST
41938 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
41939 #undef TARGET_MEMORY_MOVE_COST
41940 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
41941 #undef TARGET_RTX_COSTS
41942 #define TARGET_RTX_COSTS ix86_rtx_costs
41943 #undef TARGET_ADDRESS_COST
41944 #define TARGET_ADDRESS_COST ix86_address_cost
41946 #undef TARGET_FIXED_CONDITION_CODE_REGS
41947 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
41948 #undef TARGET_CC_MODES_COMPATIBLE
41949 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
41951 #undef TARGET_MACHINE_DEPENDENT_REORG
41952 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
41954 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
41955 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
41957 #undef TARGET_BUILD_BUILTIN_VA_LIST
41958 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
41960 #undef TARGET_FOLD_BUILTIN
41961 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
41963 #undef TARGET_COMPARE_VERSION_PRIORITY
41964 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
41966 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
41967 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
41968 ix86_generate_version_dispatcher_body
41970 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
41971 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
41972 ix86_get_function_versions_dispatcher
41974 #undef TARGET_ENUM_VA_LIST_P
41975 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
41977 #undef TARGET_FN_ABI_VA_LIST
41978 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
41980 #undef TARGET_CANONICAL_VA_LIST_TYPE
41981 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
41983 #undef TARGET_EXPAND_BUILTIN_VA_START
41984 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
41986 #undef TARGET_MD_ASM_CLOBBERS
41987 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
41989 #undef TARGET_PROMOTE_PROTOTYPES
41990 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
41991 #undef TARGET_STRUCT_VALUE_RTX
41992 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
41993 #undef TARGET_SETUP_INCOMING_VARARGS
41994 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
41995 #undef TARGET_MUST_PASS_IN_STACK
41996 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
41997 #undef TARGET_FUNCTION_ARG_ADVANCE
41998 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
41999 #undef TARGET_FUNCTION_ARG
42000 #define TARGET_FUNCTION_ARG ix86_function_arg
42001 #undef TARGET_FUNCTION_ARG_BOUNDARY
42002 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42003 #undef TARGET_PASS_BY_REFERENCE
42004 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42005 #undef TARGET_INTERNAL_ARG_POINTER
42006 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42007 #undef TARGET_UPDATE_STACK_BOUNDARY
42008 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42009 #undef TARGET_GET_DRAP_RTX
42010 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42011 #undef TARGET_STRICT_ARGUMENT_NAMING
42012 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42013 #undef TARGET_STATIC_CHAIN
42014 #define TARGET_STATIC_CHAIN ix86_static_chain
42015 #undef TARGET_TRAMPOLINE_INIT
42016 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42017 #undef TARGET_RETURN_POPS_ARGS
42018 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42020 #undef TARGET_LEGITIMATE_COMBINED_INSN
42021 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42023 #undef TARGET_ASAN_SHADOW_OFFSET
42024 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42026 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42027 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42029 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42030 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42032 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42033 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42035 #undef TARGET_C_MODE_FOR_SUFFIX
42036 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42038 #ifdef HAVE_AS_TLS
42039 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42040 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42041 #endif
42043 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42044 #undef TARGET_INSERT_ATTRIBUTES
42045 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42046 #endif
42048 #undef TARGET_MANGLE_TYPE
42049 #define TARGET_MANGLE_TYPE ix86_mangle_type
42051 #if !TARGET_MACHO
42052 #undef TARGET_STACK_PROTECT_FAIL
42053 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42054 #endif
42056 #undef TARGET_FUNCTION_VALUE
42057 #define TARGET_FUNCTION_VALUE ix86_function_value
42059 #undef TARGET_FUNCTION_VALUE_REGNO_P
42060 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42062 #undef TARGET_PROMOTE_FUNCTION_MODE
42063 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42065 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42066 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42068 #undef TARGET_INSTANTIATE_DECLS
42069 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42071 #undef TARGET_SECONDARY_RELOAD
42072 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42074 #undef TARGET_CLASS_MAX_NREGS
42075 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42077 #undef TARGET_PREFERRED_RELOAD_CLASS
42078 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42079 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42080 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42081 #undef TARGET_CLASS_LIKELY_SPILLED_P
42082 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42084 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42085 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42086 ix86_builtin_vectorization_cost
42087 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42088 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42089 ix86_vectorize_vec_perm_const_ok
42090 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42091 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42092 ix86_preferred_simd_mode
42093 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42094 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42095 ix86_autovectorize_vector_sizes
42096 #undef TARGET_VECTORIZE_INIT_COST
42097 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42098 #undef TARGET_VECTORIZE_ADD_STMT_COST
42099 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42100 #undef TARGET_VECTORIZE_FINISH_COST
42101 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42102 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42103 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42105 #undef TARGET_SET_CURRENT_FUNCTION
42106 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42108 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42109 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42111 #undef TARGET_OPTION_SAVE
42112 #define TARGET_OPTION_SAVE ix86_function_specific_save
42114 #undef TARGET_OPTION_RESTORE
42115 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42117 #undef TARGET_OPTION_PRINT
42118 #define TARGET_OPTION_PRINT ix86_function_specific_print
42120 #undef TARGET_OPTION_FUNCTION_VERSIONS
42121 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42123 #undef TARGET_CAN_INLINE_P
42124 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42126 #undef TARGET_EXPAND_TO_RTL_HOOK
42127 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42129 #undef TARGET_LEGITIMATE_ADDRESS_P
42130 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42132 #undef TARGET_LRA_P
42133 #define TARGET_LRA_P ix86_lra_p
42135 #undef TARGET_REGISTER_PRIORITY
42136 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42138 #undef TARGET_LEGITIMATE_CONSTANT_P
42139 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42141 #undef TARGET_FRAME_POINTER_REQUIRED
42142 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42144 #undef TARGET_CAN_ELIMINATE
42145 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42147 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42148 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42150 #undef TARGET_ASM_CODE_END
42151 #define TARGET_ASM_CODE_END ix86_code_end
42153 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42154 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42156 #if TARGET_MACHO
42157 #undef TARGET_INIT_LIBFUNCS
42158 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42159 #endif
42161 #undef TARGET_SPILL_CLASS
42162 #define TARGET_SPILL_CLASS ix86_spill_class
42165 \f