| blob | 62df8b04e661ed4fa459a7d7617fb129dde6a89c |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 88, 89, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
55 /* Information about the loop being processed used to compute
56 the number of loop iterations for loop unrolling and doloop
57 optimization. */
60 /* Vector mapping INSN_UIDs to luids.
61 The luids are like uids but increase monotonically always.
62 We use them to see whether a jump comes from outside a given loop. */
66 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
67 number the insn is contained in. */
71 /* 1 + largest uid of any insn. */
75 /* 1 + luid of last insn. */
79 /* Number of loops detected in current function. Used as index to the
80 next few tables. */
84 /* Indexed by loop number, contains the first and last insn of each loop. */
88 /* Likewise for the continue insn */
91 /* The first code_label that is reached in every loop iteration.
92 0 when not computed yet, initially const0_rtx if a jump couldn't be
93 followed.
94 Also set to 0 when there is no such label before the NOTE_INSN_LOOP_CONT
95 of this loop, or in verify_dominator, if a jump couldn't be followed. */
98 /* For each loop, gives the containing loop number, -1 if none. */
102 #ifdef HAVE_decrement_and_branch_on_count
103 /* Records whether resource in use by inner loop. */
108 /* Indexed by loop number, contains a nonzero value if the "loop" isn't
109 really a loop (an insn outside the loop branches into it). */
113 /* Indexed by loop number, links together all LABEL_REFs which refer to
114 code labels outside the loop. Used by routines that need to know all
115 loop exits, such as final_biv_value and final_giv_value.
117 This does not include loop exits due to return instructions. This is
118 because all bivs and givs are pseudos, and hence must be dead after a
119 return, so the presense of a return does not affect any of the
120 optimizations that use this info. It is simpler to just not include return
121 instructions on this list. */
125 /* Indexed by loop number, counts the number of LABEL_REFs on
126 loop_number_exit_labels for this loop and all loops nested inside it. */
130 /* Indexed by register number, contains the number of times the reg
131 is set during the loop being scanned.
132 During code motion, a negative value indicates a reg that has been
133 made a candidate; in particular -2 means that it is an candidate that
134 we know is equal to a constant and -1 means that it is an candidate
135 not known equal to a constant.
136 After code motion, regs moved have 0 (which is accurate now)
137 while the failed candidates have the original number of times set.
139 Therefore, at all times, == 0 indicates an invariant register;
140 < 0 a conditionally invariant one. */
144 /* Original value of set_in_loop; same except that this value
145 is not set negative for a reg whose sets have been made candidates
146 and not set to 0 for a reg that is moved. */
150 /* Index by register number, 1 indicates that the register
151 cannot be moved or strength reduced. */
155 /* Contains the insn in which a register was used if it was used
156 exactly once; contains const0_rtx if it was used more than once. */
160 /* Nonzero means reg N has already been moved out of one loop.
161 This reduces the desire to move it out of another. */
165 /* List of MEMs that are stored in this loop. */
169 /* The insn where the first of these was found. */
178 /* Array of MEMs that are used (read or written) in this loop, but
179 cannot be aliased by anything in this loop, except perhaps
180 themselves. In other words, if loop_mems[i] is altered during the
181 loop, it is altered by an expression that is rtx_equal_p to it. */
185 /* The index of the next available slot in LOOP_MEMS. */
189 /* The number of elements allocated in LOOP_MEMs. */
193 /* Nonzero if we don't know what MEMs were changed in the current
194 loop. This happens if the loop contains a call (in which case
195 `loop_info->has_call' will also be set) or if we store into more
196 than NUM_STORES MEMs. */
200 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
203 /* Count of memory write instructions discovered in the loop. */
206 /* Bound on pseudo register number before loop optimization.
207 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
210 /* This obstack is used in product_cheap_p to allocate its rtl. It
211 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
212 If we used the same obstack that it did, we would be deallocating
213 that array. */
217 /* This is where the pointer to the obstack being used for RTL is stored. */
221 #define obstack_chunk_alloc xmalloc
222 #define obstack_chunk_free free
223 \f
224 /* During the analysis of a loop, a chain of `struct movable's
225 is made to record all the movable insns found.
226 Then the entire chain can be scanned to decide which to move. */
228 struct movable
229 {
234 of any registers used within the LIBCALL. */
236 that must be moved with this one. */
239 may be adjusted when matching movables
240 that load the same value are found. */
242 including other movables that force this
243 or match this one. */
247 /* If PARTIAL is 1, GLOBAL means something different:
248 that the reg is live outside the range from where it is set
249 to the following label. */
253 In particular, moving it does not make it
254 invariant. */
256 load SRC, rather than copying INSN. */
258 first insn of a consecutive sets group. */
261 that we should avoid changing when clearing
262 the rest of the reg. */
266 };
272 /* Forward declarations. */
289 #if 0
291 #endif
310 static void record_giv PROTO((struct induction *, rtx, rtx, rtx, rtx, rtx, int, enum g_types, int, int, rtx *, rtx, rtx));
338 rtx r;
343 rtx r1;
344 rtx r2;
347 /* Nonzero iff INSN is between START and END, inclusive. */
348 #define INSN_IN_RANGE_P(INSN, START, END) \
349 (INSN_UID (INSN) < max_uid_for_loop \
350 && INSN_LUID (INSN) >= INSN_LUID (START) \
351 && INSN_LUID (INSN) <= INSN_LUID (END))
353 #ifdef HAVE_decrement_and_branch_on_count
354 /* Test whether BCT applicable and safe. */
357 /* Auxiliary function that inserts the BCT pattern into the loop. */
361 /* Indirect_jump_in_function is computed once per function. */
369 \f
370 /* Relative gain of eliminating various kinds of operations. */
372 #if 0
375 #endif
377 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
378 copy the value of the strength reduced giv to its original register. */
381 /* Cost of using a register, to normalize the benefits of a giv. */
385 void
387 {
393 #ifdef ADDRESS_COST
395 #else
397 #endif
399 /* We multiply by 2 to reconcile the difference in scale between
400 these two ways of computing costs. Otherwise the cost of a copy
401 will be far less than the cost of an add. */
405 /* Free the objects we just allocated. */
408 /* Initialize the obstack used for rtl in product_cheap_p. */
410 }
411 \f
412 /* Compute the mapping from uids to luids.
413 LUIDs are numbers assigned to insns, like uids,
414 except that luids increase monotonically through the code.
415 Start at insn START and stop just before END. Assign LUIDs
416 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
417 static int
421 {
423 rtx insn;
426 {
429 /* Don't assign luids to line-number NOTEs, so that the distance in
430 luids between two insns is not affected by -g. */
434 else
435 /* Give a line number note the same luid as preceding insn. */
437 }
439 }
440 \f
441 /* Entry point of this file. Perform loop optimization
442 on the current function. F is the first insn of the function
443 and DUMPFILE is a stream for output of a trace of actions taken
444 (or 0 if none should be output). */
446 void
448 /* f is the first instruction of a chain of insns for one function */
449 rtx f;
452 {
467 /* Count the number of loops. */
471 {
474 max_loop_num++;
475 }
477 /* Don't waste time if no loops. */
481 /* Get size to use for tables indexed by uids.
482 Leave some space for labels allocated by find_and_verify_loops. */
491 /* Allocate tables for recording each loop. We set each entry, so they need
492 not be zeroed. */
502 #ifdef HAVE_decrement_and_branch_on_count
503 /* Allocate for BCT optimization */
508 /* Find and process each loop.
509 First, find them, and record them in order of their beginnings. */
512 /* Now find all register lifetimes. This must be done after
513 find_and_verify_loops, because it might reorder the insns in the
514 function. */
517 /* This must occur after reg_scan so that registers created by gcse
518 will have entries in the register tables.
520 We could have added a call to reg_scan after gcse_main in toplev.c,
521 but moving this call to init_alias_analysis is more efficient. */
524 /* See if we went too far. Note that get_max_uid already returns
525 one more that the maximum uid of all insn. */
528 /* Now reset it to the actual size we need. See above. */
531 /* find_and_verify_loops has already called compute_luids, but it might
532 have rearranged code afterwards, so we need to recompute the luids now. */
535 /* Don't leave gaps in uid_luid for insns that have been
536 deleted. It is possible that the first or last insn
537 using some register has been deleted by cross-jumping.
538 Make sure that uid_luid for that former insn's uid
539 points to the general area where that insn used to be. */
541 {
545 }
550 /* Create a mapping from loops to BLOCK tree nodes. */
554 /* Determine if the function has indirect jump. On some systems
555 this prevents low overhead loop instructions from being used. */
558 /* Now scan the loops, last ones first, since this means inner ones are done
559 before outer ones. */
565 /* If debugging and unrolling loops, we must replicate the tree nodes
566 corresponding to the blocks inside the loop, so that the original one
567 to one mapping will remain. */
572 }
573 \f
574 /* Returns the next insn, in execution order, after INSN. START and
575 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
576 respectively. LOOP_TOP, if non-NULL, is the top of the loop in the
577 insn-stream; it is used with loops that are entered near the
578 bottom. */
580 static rtx
582 rtx insn;
583 rtx start;
584 rtx end;
585 rtx loop_top;
586 {
590 {
592 /* Go to the top of the loop, and continue there. */
594 else
595 /* We're done. */
597 }
600 /* We're done. */
604 }
606 /* Optimize one loop whose start is LOOP_START and end is END.
607 LOOP_START is the NOTE_INSN_LOOP_BEG and END is the matching
608 NOTE_INSN_LOOP_END.
609 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
611 /* ??? Could also move memory writes out of loops if the destination address
612 is invariant, the source is invariant, the memory write is not volatile,
613 and if we can prove that no read inside the loop can read this address
614 before the write occurs. If there is a read of this address after the
615 write, then we can also mark the memory read as invariant. */
617 static void
621 {
623 rtx p;
624 /* 1 if we are scanning insns that could be executed zero times. */
626 /* 1 if we are scanning insns that might never be executed
627 due to a subroutine call which might exit before they are reached. */
629 /* For a rotated loop that is entered near the bottom,
630 this is the label at the top. Otherwise it is zero. */
632 /* Jump insn that enters the loop, or 0 if control drops in. */
634 /* Place in the loop where control enters. */
635 rtx scan_start;
636 /* Number of insns in the loop. */
640 rtx temp;
641 /* The SET from an insn, if it is the only SET in the insn. */
643 /* Chain describing insns movable in current loop. */
645 /* Last element in `movables' -- so we can add elements at the end. */
647 /* Ratio of extra register life span we can justify
648 for saving an instruction. More if loop doesn't call subroutines
649 since in that case saving an insn makes more difference
650 and more registers are available. */
652 /* Nonzero if we are scanning instructions in a sub-loop. */
657 /* Determine whether this loop starts with a jump down to a test at
658 the end. This will occur for a small number of loops with a test
659 that is too complex to duplicate in front of the loop.
661 We search for the first insn or label in the loop, skipping NOTEs.
662 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
663 (because we might have a loop executed only once that contains a
664 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
665 (in case we have a degenerate loop).
667 Note that if we mistakenly think that a loop is entered at the top
668 when, in fact, it is entered at the exit test, the only effect will be
669 slightly poorer optimization. Making the opposite error can generate
670 incorrect code. Since very few loops now start with a jump to the
671 exit test, the code here to detect that case is very conservative. */
674 p != end
680 ;
684 /* Set up variables describing this loop. */
688 /* If loop has a jump before the first label,
689 the true entry is the target of that jump.
690 Start scan from there.
691 But record in LOOP_TOP the place where the end-test jumps
692 back to so we can scan that after the end of the loop. */
694 {
697 /* Loop entry must be unconditional jump (and not a RETURN) */
700 /* Check to see whether the jump actually
701 jumps out of the loop (meaning it's no loop).
702 This case can happen for things like
703 do {..} while (0). If this label was generated previously
704 by loop, we can't tell anything about it and have to reject
705 the loop. */
707 {
710 }
711 }
713 /* If SCAN_START was an insn created by loop, we don't know its luid
714 as required by loop_reg_used_before_p. So skip such loops. (This
715 test may never be true, but it's best to play it safe.)
717 Also, skip loops where we do not start scanning at a label. This
718 test also rejects loops starting with a JUMP_INSN that failed the
719 test above. */
723 {
728 }
730 /* Count number of times each reg is set during this loop.
731 Set VARRAY_CHAR (may_not_optimize, I) if it is not safe to move out
732 the setting of register I. Set VARRAY_RTX (reg_single_usage, I). */
734 /* Allocate extra space for REGS that might be created by
735 load_mems. We allocate a little extra slop as well, in the hopes
736 that even after the moving of movables creates some new registers
737 we won't have to reallocate these arrays. However, we do grow
738 the arrays, if necessary, in load_mems_recount_loop_regs_set. */
749 {
752 }
754 #ifdef AVOID_CCMODE_COPIES
755 /* Don't try to move insns which set CC registers if we should not
756 create CCmode register copies. */
760 #endif
766 {
772 }
774 /* Scan through the loop finding insns that are safe to move.
775 Set set_in_loop negative for the reg being set, so that
776 this reg will be considered invariant for subsequent insns.
777 We consider whether subsequent insns use the reg
778 in deciding whether it is worth actually moving.
780 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
781 and therefore it is possible that the insns we are scanning
782 would never be executed. At such times, we must make sure
783 that it is safe to execute the insn once instead of zero times.
784 When MAYBE_NEVER is 0, all insns will be executed at least once
785 so that is not a problem. */
790 {
802 {
809 /* Figure out what to use as a source of this insn. If a REG_EQUIV
810 note is given or if a REG_EQUAL note with a constant operand is
811 specified, use it as the source and mark that we should move
812 this insn by calling emit_move_insn rather that duplicating the
813 insn.
815 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
816 is present. */
820 else
821 {
826 {
828 /* A libcall block can use regs that don't appear in
829 the equivalent expression. To move the libcall,
830 we must move those regs too. */
832 }
833 }
835 /* Don't try to optimize a register that was made
836 by loop-optimization for an inner loop.
837 We don't know its life-span, so we can't compute the benefit. */
839 ;
841 than the one where it is set (meaning that
842 something after this point in the loop might
843 depend on its value before the set). */
845 /* And the set is not guaranteed to be executed one
846 the loop starts, or the value before the set is
847 needed before the set occurs...
849 ??? Note we have quadratic behaviour here, mitigated
850 by the fact that the previous test will often fail for
851 large loops. Rather than re-scanning the entire loop
852 each time for register usage, we should build tables
853 of the register usage and use them here instead. */
854 && (maybe_never
857 /* It is unsafe to move the set.
859 This code used to consider it OK to move a set of a variable
860 which was not created by the user and not used in an exit test.
861 That behavior is incorrect and was removed. */
862 ;
868 || (tem1
869 = consec_sets_invariant_p
872 p)))
873 /* If the insn can cause a trap (such as divide by zero),
874 can't move it unless it's guaranteed to be executed
875 once loop is entered. Even a function call might
876 prevent the trap insn from being reached
877 (since it might exit!) */
880 {
884 /* A potential lossage is where we have a case where two insns
885 can be combined as long as they are both in the loop, but
886 we move one of them outside the loop. For large loops,
887 this can lose. The most common case of this is the address
888 of a function being called.
890 Therefore, if this register is marked as being used exactly
891 once if we are in a loop with calls (a "large loop"), see if
892 we can replace the usage of this register with the source
893 of this SET. If we can, delete this insn.
895 Don't do this if P has a REG_RETVAL note or if we have
896 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
907 && (! SMALL_REGISTER_CLASSES
910 /* This test is not redundant; SET_SRC (set) might be
911 a call-clobbered register and the life of REGNO
912 might span a call. */
914 VARRAY_RTX
918 VARRAY_RTX
920 {
921 /* Replace any usage in a REG_EQUAL note. Must copy the
922 new source, so that we don't get rtx sharing between the
923 SET_SOURCE and REG_NOTES of insn p. */
934 }
953 /* Set M->cond if either invariant_p or consec_sets_invariant_p
954 returned 2 (only conditionally invariant). */
965 /* Add M to the end of the chain MOVABLES. */
968 else
973 {
974 /* It is possible for the first instruction to have a
975 REG_EQUAL note but a non-invariant SET_SRC, so we must
976 remember the status of the first instruction in case
977 the last instruction doesn't have a REG_EQUAL note. */
980 /* Skip this insn, not checking REG_LIBCALL notes. */
982 /* Skip the consecutive insns, if there are any. */
984 /* Back up to the last insn of the consecutive group. */
987 /* We must now reset m->move_insn, m->is_equiv, and possibly
988 m->set_src to correspond to the effects of all the
989 insns. */
993 else
994 {
998 else
1001 }
1003 }
1004 }
1005 /* If this register is always set within a STRICT_LOW_PART
1006 or set to zero, then its high bytes are constant.
1007 So clear them outside the loop and within the loop
1008 just load the low bytes.
1009 We must check that the machine has an instruction to do so.
1010 Also, if the value loaded into the register
1011 depends on the same register, this cannot be done. */
1021 {
1024 {
1038 /* If the insn may not be executed on some cycles,
1039 we can't clear the whole reg; clear just high part.
1040 Not even if the reg is used only within this loop.
1041 Consider this:
1042 while (1)
1043 while (s != t) {
1044 if (foo ()) x = *s;
1045 use (x);
1046 }
1047 Clearing x before the inner loop could clobber a value
1048 being saved from the last time around the outer loop.
1049 However, if the reg is not used outside this loop
1050 and all uses of the register are in the same
1051 basic block as the store, there is no problem.
1053 If this insn was made by loop, we don't know its
1054 INSN_LUID and hence must make a conservative
1055 assumption. */
1061 || (labels_in_range_p
1065 else
1074 /* Add M to the end of the chain MOVABLES. */
1077 else
1080 }
1081 }
1082 }
1083 /* Past a call insn, we get to insns which might not be executed
1084 because the call might exit. This matters for insns that trap.
1085 Call insns inside a REG_LIBCALL/REG_RETVAL block always return,
1086 so they don't count. */
1089 /* Past a label or a jump, we get to insns for which we
1090 can't count on whether or how many times they will be
1091 executed during each iteration. Therefore, we can
1092 only move out sets of trivial variables
1093 (those not used after the loop). */
1094 /* Similar code appears twice in strength_reduce. */
1096 /* If we enter the loop in the middle, and scan around to the
1097 beginning, don't set maybe_never for that. This must be an
1098 unconditional jump, otherwise the code at the top of the
1099 loop might never be executed. Unconditional jumps are
1100 followed a by barrier then loop end. */
1106 {
1107 /* At the virtual top of a converted loop, insns are again known to
1108 be executed: logically, the loop begins here even though the exit
1109 code has been duplicated. */
1113 loop_depth++;
1115 loop_depth--;
1116 }
1117 }
1119 /* If one movable subsumes another, ignore that other. */
1123 /* For each movable insn, see if the reg that it loads
1124 leads when it dies right into another conditionally movable insn.
1125 If so, record that the second insn "forces" the first one,
1126 since the second can be moved only if the first is. */
1130 /* See if there are multiple movable insns that load the same value.
1131 If there are, make all but the first point at the first one
1132 through the `match' field, and add the priorities of them
1133 all together as the priority of the first. */
1137 /* Now consider each movable insn to decide whether it is worth moving.
1138 Store 0 in set_in_loop for each reg that is moved.
1140 Generally this increases code size, so do not move moveables when
1141 optimizing for code size. */
1147 /* Now candidates that still are negative are those not moved.
1148 Change set_in_loop to indicate that those are not actually invariant. */
1153 /* Now that we've moved some things out of the loop, we might be able to
1154 hoist even more memory references. */
1159 {
1164 }
1170 }
1171 \f
1172 /* Add elements to *OUTPUT to record all the pseudo-regs
1173 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1175 void
1179 {
1187 {
1205 }
1209 {
1213 {
1222 }
1223 }
1224 }
1225 \f
1226 /* Check what regs are referred to in the libcall block ending with INSN,
1227 aside from those mentioned in the equivalent value.
1228 If there are none, return 0.
1229 If there are one or more, return an EXPR_LIST containing all of them. */
1231 rtx
1234 {
1239 /* First, find all the regs used in the libcall block
1240 that are not mentioned as inputs to the result. */
1243 {
1248 }
1251 }
1252 \f
1253 /* Return 1 if all uses of REG
1254 are between INSN and the end of the basic block. */
1256 static int
1259 {
1261 rtx p;
1266 /* Search this basic block for the already recorded last use of the reg. */
1268 {
1270 {
1276 /* Ordinary insn: if this is the last use, we win. */
1282 /* Jump insn: if this is the last use, we win. */
1285 /* Otherwise, it's the end of the basic block, so we lose. */
1290 /* It's the end of the basic block, so we lose. */
1295 }
1296 }
1298 /* The "last use" doesn't follow the "first use"?? */
1300 }
1301 \f
1302 /* Compute the benefit of eliminating the insns in the block whose
1303 last insn is LAST. This may be a group of insns used to compute a
1304 value directly or can contain a library call. */
1306 static int
1308 rtx last;
1309 {
1310 rtx insn;
1315 {
1318 routine. */
1322 benefit++;
1323 }
1326 }
1327 \f
1328 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1330 static rtx
1332 rtx insn;
1334 {
1336 {
1337 rtx temp;
1339 /* If first insn of libcall sequence, skip to end. */
1340 /* Do this at start of loop, since INSN is guaranteed to
1341 be an insn here. */
1348 }
1351 }
1353 /* Ignore any movable whose insn falls within a libcall
1354 which is part of another movable.
1355 We make use of the fact that the movable for the libcall value
1356 was made later and so appears later on the chain. */
1358 static void
1361 {
1365 {
1366 /* Is this a movable for the value of a libcall? */
1369 {
1370 rtx insn;
1371 /* Check for earlier movables inside that range,
1372 and mark them invalid. We cannot use LUIDs here because
1373 insns created by loop.c for prior loops don't have LUIDs.
1374 Rather than reject all such insns from movables, we just
1375 explicitly check each insn in the libcall (since invariant
1376 libcalls aren't that common). */
1381 }
1382 }
1383 }
1385 /* For each movable insn, see if the reg that it loads
1386 leads when it dies right into another conditionally movable insn.
1387 If so, record that the second insn "forces" the first one,
1388 since the second can be moved only if the first is. */
1390 static void
1393 {
1396 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1398 {
1401 /* ??? Could this be a bug? What if CSE caused the
1402 register of M1 to be used after this insn?
1403 Since CSE does not update regno_last_uid,
1404 this insn M->insn might not be where it dies.
1405 But very likely this doesn't matter; what matters is
1406 that M's reg is computed from M1's reg. */
1411 /* If m->consec, m->set_src isn't valid. */
1415 /* Increase the priority of the moving the first insn
1416 since it permits the second to be moved as well. */
1418 {
1422 }
1423 }
1424 }
1425 \f
1426 /* Find invariant expressions that are equal and can be combined into
1427 one register. */
1429 static void
1433 {
1438 /* Regs that are set more than once are not allowed to match
1439 or be matched. I'm no longer sure why not. */
1440 /* Perhaps testing m->consec_sets would be more appropriate here? */
1444 {
1451 /* We want later insns to match the first one. Don't make the first
1452 one match any later ones. So start this loop at m->next. */
1455 /* A reg used outside the loop mustn't be eliminated. */
1457 /* A reg used for zero-extending mustn't be eliminated. */
1460 ||
1461 (
1462 /* Can combine regs with different modes loaded from the
1463 same constant only if the modes are the same or
1464 if both are integer modes with M wider or the same
1465 width as M1. The check for integer is redundant, but
1466 safe, since the only case of differing destination
1467 modes with equal sources is when both sources are
1468 VOIDmode, i.e., CONST_INT. */
1474 /* See if the source of M1 says it matches M. */
1478 movables))))
1481 {
1487 }
1488 }
1490 /* Now combine the regs used for zero-extension.
1491 This can be done for those not marked `global'
1492 provided their lives don't overlap. */
1496 {
1499 /* Combine all the registers for extension from mode MODE.
1500 Don't combine any that are used outside this loop. */
1504 {
1510 {
1511 /* First one: don't check for overlap, just record it. */
1514 }
1516 /* Make sure they extend to the same mode.
1517 (Almost always true.) */
1521 /* We already have one: check for overlap with those
1522 already combined together. */
1529 /* No overlap: we can combine this with the others. */
1535 overlap: ;
1536 }
1537 }
1538 }
1539 \f
1540 /* Return 1 if regs X and Y will become the same if moved. */
1542 static int
1546 {
1563 }
1565 /* Return 1 if X and Y are identical-looking rtx's.
1566 This is the Lisp function EQUAL for rtx arguments.
1568 If two registers are matching movables or a movable register and an
1569 equivalent constant, consider them equal. */
1571 static int
1575 {
1589 /* If we have a register and a constant, they may sometimes be
1590 equal. */
1593 {
1598 }
1601 {
1606 }
1608 /* Otherwise, rtx's of different codes cannot be equal. */
1612 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1613 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1618 /* These three types of rtx's can be compared nonrecursively. */
1627 /* Compare the elements. If any pair of corresponding elements
1628 fail to match, return 0 for the whole things. */
1632 {
1634 {
1646 /* Two vectors must have the same length. */
1650 /* And the corresponding elements must match. */
1667 /* These are just backpointers, so they don't matter. */
1673 /* It is believed that rtx's at this level will never
1674 contain anything but integers and other rtx's,
1675 except for within LABEL_REFs and SYMBOL_REFs. */
1678 }
1679 }
1681 }
1682 \f
1683 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1684 insns in INSNS which use the reference. */
1686 static void
1688 rtx x;
1689 rtx insns;
1690 {
1694 rtx insn;
1697 {
1698 /* This code used to ignore labels that referred to dispatch tables to
1699 avoid flow generating (slighly) worse code.
1701 We no longer ignore such label references (see LABEL_REF handling in
1702 mark_jump_label for additional information). */
1707 }
1711 {
1717 }
1718 }
1719 \f
1720 /* Scan MOVABLES, and move the insns that deserve to be moved.
1721 If two matching movables are combined, replace one reg with the
1722 other throughout. */
1724 static void
1729 rtx loop_start;
1730 rtx end;
1732 {
1736 /* Map of pseudo-register replacements to handle combining
1737 when we move several insns that load the same value
1738 into different pseudo-registers. */
1748 {
1749 /* Describe this movable insn. */
1752 {
1773 }
1775 /* Count movables. Value used in heuristics in strength_reduce. */
1776 num_movables++;
1778 /* Ignore the insn if it's already done (it matched something else).
1779 Otherwise, see if it is now safe to move. */
1791 {
1796 /* We have an insn that is safe to move.
1797 Compute its desirability. */
1808 /* An insn MUST be moved if we already moved something else
1809 which is safe only if this one is moved too: that is,
1810 if already_moved[REGNO] is nonzero. */
1812 /* An insn is desirable to move if the new lifetime of the
1813 register is no more than THRESHOLD times the old lifetime.
1814 If it's not desirable, it means the loop is so big
1815 that moving won't speed things up much,
1816 and it is liable to make register usage worse. */
1818 /* It is also desirable to move if it can be moved at no
1819 extra cost because something else was already moved. */
1822 || flag_move_all_movables
1827 {
1832 /* Now move the insns that set the reg. */
1835 {
1838 /* Find the end of this chain of matching regs.
1839 Thus, we load each reg in the chain from that one reg.
1840 And that reg is loaded with 0 directly,
1841 since it has ->match == 0. */
1847 /* Mark the moved, invariant reg as being allowed to
1848 share a hard reg with the other matching invariant. */
1852 regs_may_share
1855 regs_may_share));
1863 }
1864 /* If we are to re-generate the item being moved with a
1865 new move insn, first delete what we have and then emit
1866 the move insn before the loop. */
1868 {
1872 {
1873 /* If this is the first insn of a library call sequence,
1874 skip to the end. */
1879 /* If this is the last insn of a libcall sequence, then
1880 delete every insn in the sequence except the last.
1881 The last insn is handled in the normal manner. */
1884 {
1888 }
1893 /* simplify_giv_expr expects that it can walk the insns
1894 at m->insn forwards and see this old sequence we are
1895 tossing here. delete_insn does preserve the next
1896 pointers, but when we skip over a NOTE we must fix
1897 it up. Otherwise that code walks into the non-deleted
1898 insn stream. */
1901 }
1919 /* The more regs we move, the less we like moving them. */
1921 }
1922 else
1923 {
1925 {
1928 /* If first insn of libcall sequence, skip to end. */
1929 /* Do this at start of loop, since p is guaranteed to
1930 be an insn here. */
1935 /* If last insn of libcall sequence, move all
1936 insns except the last before the loop. The last
1937 insn is handled in the normal manner. */
1940 {
1948 {
1949 rtx body;
1950 rtx n;
1951 rtx next;
1958 /* Find the next insn after TEMP,
1959 not counting USE or NOTE insns. */
1967 /* If that is the call, this may be the insn
1968 that loads the function address.
1970 Extract the function address from the insn
1971 that loads it into a register.
1972 If this insn was cse'd, we get incorrect code.
1974 So emit a new move insn that copies the
1975 function address into the register that the
1976 call insn will use. flow.c will delete any
1977 redundant stores that we have created. */
1982 NULL_RTX)))
1983 {
1989 }
1990 /* We have the call insn.
1991 If it uses the register we suspect it might,
1992 load it with the correct address directly. */
1997 fn_address),
1998 fn_address_insn);
2001 {
2003 /* Because the USAGE information potentially
2004 contains objects other than hard registers
2005 we need to copy it. */
2009 }
2010 else
2018 }
2021 }
2023 {
2024 /* P sets REG to zero; but we should clear only
2025 the bits that are not covered by the mode
2026 m->savemode. */
2028 rtx sequence;
2029 rtx tem;
2032 tem = expand_binop
2045 }
2047 {
2049 /* Because the USAGE information potentially
2050 contains objects other than hard registers
2051 we need to copy it. */
2055 }
2057 {
2058 /* The SET_SRC might not be invariant, so we must
2059 use the REG_EQUAL note. */
2073 }
2074 else
2078 {
2081 /* If there is a REG_EQUAL note present whose value
2082 is not loop invariant, then delete it, since it
2083 may cause problems with later optimization passes.
2084 It is possible for cse to create such notes
2085 like this as a result of record_jump_cond. */
2090 }
2099 /* If library call, now fix the REG_NOTES that contain
2100 insn pointers, namely REG_LIBCALL on FIRST
2101 and REG_RETVAL on I1. */
2103 {
2107 }
2113 /* simplify_giv_expr expects that it can walk the insns
2114 at m->insn forwards and see this old sequence we are
2115 tossing here. delete_insn does preserve the next
2116 pointers, but when we skip over a NOTE we must fix
2117 it up. Otherwise that code walks into the non-deleted
2118 insn stream. */
2121 }
2123 /* The more regs we move, the less we like moving them. */
2125 }
2127 /* Any other movable that loads the same register
2128 MUST be moved. */
2131 /* This reg has been moved out of one loop. */
2134 /* The reg set here is now invariant. */
2140 /* Change the length-of-life info for the register
2141 to say it lives at least the full length of this loop.
2142 This will help guide optimizations in outer loops. */
2145 /* This is the old insn before all the moved insns.
2146 We can't use the moved insn because it is out of range
2147 in uid_luid. Only the old insns have luids. */
2152 /* Combine with this moved insn any other matching movables. */
2157 {
2158 rtx temp;
2160 /* Schedule the reg loaded by M1
2161 for replacement so that shares the reg of M.
2162 If the modes differ (only possible in restricted
2163 circumstances, make a SUBREG.
2165 Note this assumes that the target dependent files
2166 treat REG and SUBREG equally, including within
2167 GO_IF_LEGITIMATE_ADDRESS and in all the
2168 predicates since we never verify that replacing the
2169 original register with a SUBREG results in a
2170 recognizable insn. */
2173 else
2178 /* Get rid of the matching insn
2179 and prevent further processing of it. */
2182 /* if library call, delete all insn except last, which
2183 is deleted below */
2185 NULL_RTX)))
2186 {
2190 }
2193 /* Any other movable that loads the same register
2194 MUST be moved. */
2197 /* The reg merged here is now invariant,
2198 if the reg it matches is invariant. */
2201 }
2202 }
2205 }
2211 }
2216 /* Go through all the instructions in the loop, making
2217 all the register substitutions scheduled in REG_MAP. */
2221 {
2225 }
2226 }
2227 \f
2228 #if 0
2229 /* Scan X and replace the address of any MEM in it with ADDR.
2230 REG is the address that MEM should have before the replacement. */
2232 static void
2235 {
2244 {
2256 /* Short cut for very common case. */
2261 /* Short cut for very common case. */
2266 /* If this MEM uses a reg other than the one we expected,
2267 something is wrong. */
2275 }
2279 {
2283 {
2287 }
2288 }
2289 }
2290 #endif
2291 \f
2292 /* Return the number of memory refs to addresses that vary
2293 in the rtx X. */
2295 static int
2297 rtx x;
2298 {
2309 {
2326 }
2331 {
2335 {
2339 }
2340 }
2342 }
2344 \f
2345 #if 0
2346 /* P is an instruction that sets a register to the result of a ZERO_EXTEND.
2347 Replace it with an instruction to load just the low bytes
2348 if the machine supports such an instruction,
2349 and insert above LOOP_START an instruction to clear the register. */
2351 static void
2354 {
2358 /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...)))
2359 to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */
2361 new
2362 = gen_rtx_SET
2364 gen_rtx_STRICT_LOW_PART
2373 {
2376 /* Clear destination register before the loop. */
2379 loop_start);
2381 /* Inside the loop, just load the low part. */
2383 }
2384 }
2385 #endif
2386 \f
2387 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2388 `has_call', `has_volatile', and `has_tablejump' within LOOP_INFO.
2389 Set the global variables `unknown_address_altered' and
2390 `num_mem_sets'. Also, fill in the array `loop_mems' and the list
2391 `loop_store_mems'. */
2393 static void
2397 {
2399 rtx insn;
2400 /* The label after END. Jumping here is just like falling off the
2401 end of the loop. We use next_nonnote_insn instead of next_label
2402 as a hedge against the (pathological) case where some actual insn
2403 might end up between the two. */
2424 {
2426 {
2428 {
2430 /* Count number of loops contained in this one. */
2432 }
2434 {
2437 {
2440 }
2441 }
2443 {
2446 }
2448 {
2449 /* If there is a NOTE_INSN_LOOP_VTOP, then this is a for
2450 or while style loop, with a loop exit test at the
2451 start. Thus, we can assume that the loop condition
2452 was true when the loop was entered. */
2455 }
2456 }
2458 {
2462 }
2464 {
2484 {
2486 {
2489 }
2490 else
2491 {
2493 }
2497 {
2499 {
2500 /* Something tricky. */
2503 }
2506 {
2507 /* A jump outside the current loop. */
2510 }
2511 }
2516 }
2517 }
2520 }
2522 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2524 !unknown_address_altered
2525 /* An exception thrown by a called function might land us
2526 anywhere. */
2528 /* We don't want loads for MEMs moved to a location before the
2529 one at which their stack memory becomes allocated. (Note
2530 that this is not a problem for malloc, etc., since those
2531 require actual function calls. */
2532 && !current_function_calls_alloca
2533 /* There are ways to leave the loop other than falling off the
2534 end. */
2539 }
2540 \f
2541 /* LOOP_NUMBER_CONT_DOMINATOR is now the last label between the loop start
2542 and the continue note that is a the destination of a (cond)jump after
2543 the continue note. If there is any (cond)jump between the loop start
2544 and what we have so far as LOOP_NUMBER_CONT_DOMINATOR that has a
2545 target between LOOP_DOMINATOR and the continue note, move
2546 LOOP_NUMBER_CONT_DOMINATOR forward to that label; if a jump's
2547 destination cannot be determined, clear LOOP_NUMBER_CONT_DOMINATOR. */
2549 static void
2552 {
2553 rtx insn;
2556 /* This can happen for an empty loop, e.g. in
2557 gcc.c-torture/compile/920410-2.c */
2560 {
2563 }
2567 {
2570 {
2574 /* If it is not a jump we can easily understand or for
2575 which we do not have jump target information in the JUMP_LABEL
2576 field (consider ADDR_VEC and ADDR_DIFF_VEC insns), then clear
2577 LOOP_NUMBER_CONT_DOMINATOR. */
2581 {
2584 }
2588 && (label_luid
2591 }
2592 }
2593 }
2595 /* Scan the function looking for loops. Record the start and end of each loop.
2596 Also mark as invalid loops any loops that contain a setjmp or are branched
2597 to from outside the loop. */
2599 static void
2601 rtx f;
2602 {
2610 /* If there are jumps to undefined labels,
2611 treat them as jumps out of any/all loops.
2612 This also avoids writing past end of tables when there are no loops. */
2615 /* Find boundaries of loops, mark which loops are contained within
2616 loops, and invalidate loops that have setjmp. */
2619 {
2622 {
2636 /* In this case, we must invalidate our current loop and any
2637 enclosing loop. */
2639 {
2645 }
2662 }
2663 /* If for any loop, this is a jump insn between the NOTE_INSN_LOOP_CONT
2664 and NOTE_INSN_LOOP_END notes, update loop_number_loop_dominator. */
2668 {
2676 do
2677 {
2678 /* First see if we care about this loop. */
2681 {
2682 /* If the jump destination is not known, invalidate
2683 loop_number_const_dominator. */
2686 else
2687 /* Check if the destination is between loop start and
2688 cont. */
2693 /* And if there is no later destination already
2694 recorded. */
2700 }
2702 }
2704 }
2706 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2707 enclosing loop, but this doesn't matter. */
2709 }
2711 /* Any loop containing a label used in an initializer must be invalidated,
2712 because it can be jumped into from anywhere. */
2715 {
2722 }
2724 /* Any loop containing a label used for an exception handler must be
2725 invalidated, because it can be jumped into from anywhere. */
2728 {
2735 }
2737 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2738 loop that it is not contained within, that loop is marked invalid.
2739 If any INSN or CALL_INSN uses a label's address, then the loop containing
2740 that label is marked invalid, because it could be jumped into from
2741 anywhere.
2743 Also look for blocks of code ending in an unconditional branch that
2744 exits the loop. If such a block is surrounded by a conditional
2745 branch around the block, move the block elsewhere (see below) and
2746 invert the jump to point to the code block. This may eliminate a
2747 label in our loop and will simplify processing by both us and a
2748 possible second cse pass. */
2752 {
2756 {
2759 {
2766 }
2767 }
2774 /* See if this is an unconditional branch outside the loop. */
2781 {
2782 rtx p;
2788 /* Go backwards until we reach the start of the loop, a label,
2789 or a JUMP_INSN. */
2796 ;
2798 /* Check for the case where we have a jump to an inner nested
2799 loop, and do not perform the optimization in that case. */
2802 {
2805 {
2810 }
2811 }
2813 /* Make sure that the target of P is within the current loop. */
2819 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2820 we have a block of code to try to move.
2822 We look backward and then forward from the target of INSN
2823 to find a BARRIER at the same loop depth as the target.
2824 If we find such a BARRIER, we make a new label for the start
2825 of the block, invert the jump in P and point it to that label,
2826 and move the block of code to the spot we found. */
2831 /* Just ignore jumps to labels that were never emitted.
2832 These always indicate compilation errors. */
2837 /* If it's not safe to move the sequence, then we
2838 mustn't try. */
2841 {
2842 rtx target
2849 /* Don't move things inside a tablejump. */
2862 /* Don't move things inside a tablejump. */
2873 {
2877 /* Ensure our label doesn't go away. */
2880 /* Verify that uid_loop_num is large enough and that
2881 we can invert P. */
2883 {
2886 /* If no suitable BARRIER was found, create a suitable
2887 one before TARGET. Since TARGET is a fall through
2888 path, we'll need to insert an jump around our block
2889 and a add a BARRIER before TARGET.
2891 This creates an extra unconditional jump outside
2892 the loop. However, the benefits of removing rarely
2893 executed instructions from inside the loop usually
2894 outweighs the cost of the extra unconditional jump
2895 outside the loop. */
2897 {
2898 rtx temp;
2905 }
2907 /* Include the BARRIER after INSN and copy the
2908 block after LOC. */
2910 last_insn_to_move);
2913 /* All those insns are now in TARGET_LOOP_NUM. */
2919 /* The label jumped to by INSN is no longer a loop exit.
2920 Unless INSN does not have a label (e.g., it is a
2921 RETURN insn), search loop_number_exit_labels to find
2922 its label_ref, and remove it. Also turn off
2923 LABEL_OUTSIDE_LOOP_P bit. */
2925 {
2932 {
2936 else
2940 }
2947 /* If we didn't find it, then something is wrong. */
2950 }
2952 /* P is now a jump outside the loop, so it must be put
2953 in loop_number_exit_labels, and marked as such.
2954 The easiest way to do this is to just call
2955 mark_loop_jump again for P. */
2958 /* If INSN now jumps to the insn after it,
2959 delete INSN. */
2964 }
2966 /* Continue the loop after where the conditional
2967 branch used to jump, since the only branch insn
2968 in the block (if it still remains) is an inter-loop
2969 branch and hence needs no processing. */
2975 /* This loop will be continued with NEXT_INSN (insn). */
2977 }
2978 }
2979 }
2980 }
2981 }
2983 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2984 loops it is contained in, mark the target loop invalid.
2986 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2988 static void
2990 rtx x;
2992 {
2998 {
3010 /* There could be a label reference in here. */
3022 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3034 /* Link together all labels that branch outside the loop. This
3035 is used by final_[bg]iv_value and the loop unrolling code. Also
3036 mark this LABEL_REF so we know that this branch should predict
3037 false. */
3039 /* A check to make sure the label is not in an inner nested loop,
3040 since this does not count as a loop exit. */
3042 {
3047 }
3048 else
3052 {
3061 }
3063 /* If this is inside a loop, but not in the current loop or one enclosed
3064 by it, it invalidates at least one loop. */
3069 /* We must invalidate every nested loop containing the target of this
3070 label, except those that also contain the jump insn. */
3073 {
3074 /* Stop when we reach a loop that also contains the jump insn. */
3080 /* If we get here, we know we need to invalidate a loop. */
3087 }
3091 /* If this is not setting pc, ignore. */
3113 /* Strictly speaking this is not a jump into the loop, only a possible
3114 jump out of the loop. However, we have no way to link the destination
3115 of this jump onto the list of exit labels. To be safe we mark this
3116 loop and any containing loops as invalid. */
3118 {
3121 {
3127 }
3128 }
3130 }
3131 }
3132 \f
3133 /* Return nonzero if there is a label in the range from
3134 insn INSN to and including the insn whose luid is END
3135 INSN must have an assigned luid (i.e., it must not have
3136 been previously created by loop.c). */
3138 static int
3140 rtx insn;
3142 {
3144 {
3148 }
3151 }
3153 /* Record that a memory reference X is being set. */
3155 static void
3157 rtx x;
3158 rtx y ATTRIBUTE_UNUSED;
3160 {
3164 /* Count number of memory writes.
3165 This affects heuristics in strength_reduce. */
3166 num_mem_sets++;
3168 /* BLKmode MEM means all memory is clobbered. */
3176 }
3178 /* X is a value modified by an INSN that references a biv inside a loop
3179 exit test (ie, X is somehow related to the value of the biv). If X
3180 is a pseudo that is used more than once, then the biv is (effectively)
3181 used more than once. DATA is really an `int *', and is set if the
3182 biv is used more than once. */
3184 static void
3186 rtx x;
3187 rtx y ATTRIBUTE_UNUSED;
3189 {
3202 /* If we do not have usage information, or if we know the register
3203 is used more than once, note that fact for check_dbra_loop. */
3208 }
3209 \f
3210 /* Return nonzero if the rtx X is invariant over the current loop.
3212 The value is 2 if we refer to something only conditionally invariant.
3214 If `unknown_address_altered' is nonzero, no memory ref is invariant.
3215 Otherwise, a memory ref is invariant if it does not conflict with
3216 anything stored in `loop_store_mems'. */
3218 int
3221 {
3226 rtx mem_list_entry;
3232 {
3240 /* A LABEL_REF is normally invariant, however, if we are unrolling
3241 loops, and this label is inside the loop, then it isn't invariant.
3242 This is because each unrolled copy of the loop body will have
3243 a copy of this label. If this was invariant, then an insn loading
3244 the address of this label into a register might get moved outside
3245 the loop, and then each loop body would end up using the same label.
3247 We don't know the loop bounds here though, so just fail for all
3248 labels. */
3251 else
3260 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3261 since the reg might be set by initialization within the loop. */
3278 /* Volatile memory references must be rejected. Do this before
3279 checking for read-only items, so that volatile read-only items
3280 will be rejected also. */
3284 /* Read-only items (such as constants in a constant pool) are
3285 invariant if their address is. */
3289 /* If we had a subroutine call, any location in memory could have been
3290 clobbered. */
3294 /* See if there is any dependence between a store and this load. */
3297 {
3302 }
3304 /* It's not invalidated by a store in memory
3305 but we must still verify the address is invariant. */
3309 /* Don't mess with insns declared volatile. */
3316 }
3320 {
3322 {
3328 }
3330 {
3333 {
3339 }
3341 }
3342 }
3345 }
3347 \f
3348 /* Return nonzero if all the insns in the loop that set REG
3349 are INSN and the immediately following insns,
3350 and if each of those insns sets REG in an invariant way
3351 (not counting uses of REG in them).
3353 The value is 2 if some of these insns are only conditionally invariant.
3355 We assume that INSN itself is the first set of REG
3356 and that its source is invariant. */
3358 static int
3362 {
3365 rtx temp;
3366 /* Number of sets we have to insist on finding after INSN. */
3372 /* If N_SETS hit the limit, we can't rely on its value. */
3379 {
3381 rtx set;
3386 /* If library call, skip to end of it. */
3395 {
3400 {
3401 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3402 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3403 notes are OK. */
3409 }
3410 }
3412 count--;
3414 {
3417 }
3418 }
3421 /* If invariant_p ever returned 2, we return 2. */
3423 }
3425 #if 0
3426 /* I don't think this condition is sufficient to allow INSN
3427 to be moved, so we no longer test it. */
3429 /* Return 1 if all insns in the basic block of INSN and following INSN
3430 that set REG are invariant according to TABLE. */
3432 static int
3436 {
3441 {
3450 {
3453 }
3454 }
3455 }
3457 \f
3458 /* Look at all uses (not sets) of registers in X. For each, if it is
3459 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3460 a different insn, set USAGE[REGNO] to const0_rtx. */
3462 static void
3464 rtx insn;
3465 rtx x;
3466 varray_type usage;
3467 {
3479 {
3480 /* Don't count SET_DEST if it is a REG; otherwise count things
3481 in SET_DEST because if a register is partially modified, it won't
3482 show up as a potential movable so we don't care how USAGE is set
3483 for it. */
3487 }
3488 else
3490 {
3496 }
3497 }
3498 \f
3499 /* Count and record any set in X which is contained in INSN. Update
3500 MAY_NOT_MOVE and LAST_SET for any register set in X. */
3502 static void
3505 varray_type may_not_move;
3507 {
3509 /* Don't move a reg that has an explicit clobber.
3510 It's not worth the pain to try to do it correctly. */
3514 {
3522 {
3524 /* If this is the first setting of this reg
3525 in current basic block, and it was set before,
3526 it must be set in two basic blocks, so it cannot
3527 be moved out of the loop. */
3531 /* If this is not first setting in current basic block,
3532 see if reg was used in between previous one and this.
3533 If so, neither one can be moved. */
3540 }
3541 }
3542 }
3544 /* Increment SET_IN_LOOP at the index of each register
3545 that is modified by an insn between FROM and TO.
3546 If the value of an element of SET_IN_LOOP becomes 127 or more,
3547 stop incrementing it, to avoid overflow.
3549 Store in SINGLE_USAGE[I] the single insn in which register I is
3550 used, if it is only used once. Otherwise, it is set to 0 (for no
3551 uses) or const0_rtx for more than one use. This parameter may be zero,
3552 in which case this processing is not done.
3554 Store in *COUNT_PTR the number of actual instruction
3555 in the loop. We use this to decide what is worth moving out. */
3557 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3558 In that case, it is the insn that last set reg n. */
3560 static void
3563 varray_type may_not_move;
3564 varray_type single_usage;
3567 {
3574 {
3576 {
3579 /* Record registers that have exactly one use. */
3582 /* Include uses in REG_EQUAL notes. */
3590 {
3595 }
3596 }
3600 }
3602 }
3603 \f
3604 /* Given a loop that is bounded by LOOP_START and LOOP_END
3605 and that is entered at SCAN_START,
3606 return 1 if the register set in SET contained in insn INSN is used by
3607 any insn that precedes INSN in cyclic order starting
3608 from the loop entry point.
3610 We don't want to use INSN_LUID here because if we restrict INSN to those
3611 that have a valid INSN_LUID, it means we cannot move an invariant out
3612 from an inner loop past two loops. */
3614 static int
3617 {
3619 rtx p;
3621 /* Scan forward checking for register usage. If we hit INSN, we
3622 are done. Otherwise, if we hit LOOP_END, wrap around to LOOP_START. */
3624 {
3631 }
3634 }
3635 \f
3636 /* A "basic induction variable" or biv is a pseudo reg that is set
3637 (within this loop) only by incrementing or decrementing it. */
3638 /* A "general induction variable" or giv is a pseudo reg whose
3639 value is a linear function of a biv. */
3641 /* Bivs are recognized by `basic_induction_var';
3642 Givs by `general_induction_var'. */
3644 /* Indexed by register number, indicates whether or not register is an
3645 induction variable, and if so what type. */
3647 varray_type reg_iv_type;
3649 /* Indexed by register number, contains pointer to `struct induction'
3650 if register is an induction variable. This holds general info for
3651 all induction variables. */
3653 varray_type reg_iv_info;
3655 /* Indexed by register number, contains pointer to `struct iv_class'
3656 if register is a basic induction variable. This holds info describing
3657 the class (a related group) of induction variables that the biv belongs
3658 to. */
3662 /* The head of a list which links together (via the next field)
3663 every iv class for the current loop. */
3667 /* Givs made from biv increments are always splittable for loop unrolling.
3668 Since there is no regscan info for them, we have to keep track of them
3669 separately. */
3672 /* Communication with routines called via `note_stores'. */
3676 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3680 /* ??? Unfinished optimizations, and possible future optimizations,
3681 for the strength reduction code. */
3683 /* ??? The interaction of biv elimination, and recognition of 'constant'
3684 bivs, may cause problems. */
3686 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3687 performance problems.
3689 Perhaps don't eliminate things that can be combined with an addressing
3690 mode. Find all givs that have the same biv, mult_val, and add_val;
3691 then for each giv, check to see if its only use dies in a following
3692 memory address. If so, generate a new memory address and check to see
3693 if it is valid. If it is valid, then store the modified memory address,
3694 otherwise, mark the giv as not done so that it will get its own iv. */
3696 /* ??? Could try to optimize branches when it is known that a biv is always
3697 positive. */
3699 /* ??? When replace a biv in a compare insn, we should replace with closest
3700 giv so that an optimized branch can still be recognized by the combiner,
3701 e.g. the VAX acb insn. */
3703 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3704 was rerun in loop_optimize whenever a register was added or moved.
3705 Also, some of the optimizations could be a little less conservative. */
3706 \f
3707 /* Perform strength reduction and induction variable elimination.
3709 Pseudo registers created during this function will be beyond the last
3710 valid index in several tables including n_times_set and regno_last_uid.
3711 This does not cause a problem here, because the added registers cannot be
3712 givs outside of their loop, and hence will never be reconsidered.
3713 But scan_loop must check regnos to make sure they are in bounds.
3715 SCAN_START is the first instruction in the loop, as the loop would
3716 actually be executed. END is the NOTE_INSN_LOOP_END. LOOP_TOP is
3717 the first instruction in the loop, as it is layed out in the
3718 instruction stream. LOOP_START is the NOTE_INSN_LOOP_BEG.
3719 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
3721 static void
3724 rtx scan_start;
3725 rtx end;
3726 rtx loop_top;
3728 rtx loop_start;
3729 rtx loop_end;
3731 rtx loop_cont;
3733 {
3734 rtx p;
3735 rtx set;
3736 rtx inc_val;
3737 rtx mult_val;
3738 rtx dest_reg;
3740 /* This is 1 if current insn is not executed at least once for every loop
3741 iteration. */
3743 /* This is 1 if current insn may be executed more than once for every
3744 loop iteration. */
3746 /* This is 1 if we have past a branch back to the top of the loop
3747 (aka a loop latch). */
3749 /* Temporary list pointers for traversing loop_iv_list. */
3751 /* Ratio of extra register life span we can justify
3752 for saving an instruction. More if loop doesn't call subroutines
3753 since in that case saving an insn makes more difference
3754 and more registers are available. */
3755 /* ??? could set this to last value of threshold in move_movables */
3757 /* Map of pseudo-register replacements. */
3761 rtx test;
3762 rtx end_insert_before;
3767 /* If scan_start points to the loop exit test, we have to be wary of
3768 subversive use of gotos inside expression statements. */
3782 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3783 must be put before this insn, so that they will appear in the right
3784 order (i.e. loop order).
3786 If loop_end is the end of the current function, then emit a
3787 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3788 dummy note insn. */
3791 else
3794 /* Scan through loop to find all possible bivs. */
3799 {
3803 {
3808 {
3812 {
3813 /* It is a possible basic induction variable.
3814 Create and initialize an induction structure for it. */
3822 }
3825 }
3826 }
3828 /* Past CODE_LABEL, we get to insns that may be executed multiple
3829 times. The only way we can be sure that they can't is if every
3830 jump insn between here and the end of the loop either
3831 returns, exits the loop, is a jump to a location that is still
3832 behind the label, or is a jump to the loop start. */
3835 {
3841 {
3846 {
3849 else
3853 }
3861 {
3864 }
3865 }
3866 }
3868 /* Past a jump, we get to insns for which we can't count
3869 on whether they will be executed during each iteration. */
3870 /* This code appears twice in strength_reduce. There is also similar
3871 code in scan_loop. */
3873 /* If we enter the loop in the middle, and scan around to the
3874 beginning, don't set not_every_iteration for that.
3875 This can be any kind of jump, since we want to know if insns
3876 will be executed if the loop is executed. */
3880 {
3883 /* If this is a jump outside the loop, then it also doesn't
3884 matter. Check to see if the target of this branch is on the
3885 loop_number_exits_labels list. */
3888 label;
3895 }
3898 {
3899 /* At the virtual top of a converted loop, insns are again known to
3900 be executed each iteration: logically, the loop begins here
3901 even though the exit code has been duplicated.
3903 Insns are also again known to be executed each iteration at
3904 the LOOP_CONT note. */
3910 loop_depth++;
3912 loop_depth--;
3913 }
3915 /* Note if we pass a loop latch. If we do, then we can not clear
3916 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3917 a loop since a jump before the last CODE_LABEL may have started
3918 a new loop iteration.
3920 Note that LOOP_TOP is only set for rotated loops and we need
3921 this check for all loops, so compare against the CODE_LABEL
3922 which immediately follows LOOP_START. */
3926 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3927 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3928 or not an insn is known to be executed each iteration of the
3929 loop, whether or not any iterations are known to occur.
3931 Therefore, if we have just passed a label and have no more labels
3932 between here and the test insn of the loop, and we have not passed
3933 a jump to the top of the loop, then we know these insns will be
3934 executed each iteration. */
3937 && ! past_loop_latch
3942 }
3944 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3945 Make a sanity check against n_times_set. */
3947 {
3949 /* Above happens if register modified by subreg, etc. */
3950 /* Make sure it is not recognized as a basic induction var: */
3952 /* If never incremented, it is invariant that we decided not to
3953 move. So leave it alone. */
3955 {
3966 }
3967 else
3968 {
3973 }
3974 }
3976 /* Exit if there are no bivs. */
3978 {
3979 /* Can still unroll the loop anyways, but indicate that there is no
3980 strength reduction info available. */
3986 }
3988 /* Find initial value for each biv by searching backwards from loop_start,
3989 halting at first label. Also record any test condition. */
3993 {
4003 /* Record any test of a biv that branches around the loop if no store
4004 between it and the start of loop. We only care about tests with
4005 constants and registers and only certain of those. */
4015 {
4016 /* If an NE test, we have an initial value! */
4018 {
4022 }
4023 else
4025 }
4026 }
4028 /* Look at the each biv and see if we can say anything better about its
4029 initial value from any initializing insns set up above. (This is done
4030 in two passes to avoid missing SETs in a PARALLEL.) */
4032 {
4033 rtx src;
4034 rtx note;
4039 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4040 is a constant, use the value of that. */
4046 else
4057 {
4061 {
4063 {
4066 }
4067 else
4068 {
4071 }
4072 }
4073 }
4074 else
4075 {
4079 /* Biv initial value is not a simple move. If it is the sum of
4080 another biv and a constant, check if both bivs are incremented
4081 in lockstep. Then we are actually looking at a giv.
4082 For simplicity, we only handle the case where there is but a
4083 single increment, and the register is not used elsewhere. */
4092 {
4098 }
4100 /* Now, can we transform this biv into a giv? */
4105 /* init_insn is only set to insns that are before loop_start
4106 without any intervening labels. */
4109 /* The register from BL2 must be set before the register from
4110 BL is set, or we must be able to move the latter set after
4111 the former set. Currently there can't be any labels
4112 in-between when biv_total_increment returns nonzero both times
4113 but we test it here in case some day some real cfg analysis
4114 gets used to set always_computable. */
4123 {
4132 /* Let this giv be discovered by the generic code. */
4135 /* We can get better optimization if we can move the giv setting
4136 before the first giv use. */
4140 dominator)
4143 {
4144 rtx p;
4145 rtx next;
4148 {
4154 #ifdef HAVE_cc0
4157 #endif
4159 }
4163 /* Avoid problems with luids by actually moving the insn
4164 and adjusting all luids in the range. */
4169 /* If the only purpose of the init insn is to initialize
4170 this giv, delete it. */
4174 }
4176 {
4183 }
4184 /* Remove this biv from the chain. */
4186 {
4187 /* We move the following giv from *bl->next into *bl.
4188 We have to update reg_biv_class for that moved biv
4189 to point to its new address. */
4192 }
4193 else
4194 {
4197 }
4198 }
4200 /* If we can't make it a giv,
4201 let biv keep initial value of "itself". */
4204 }
4205 }
4207 /* If a biv is unconditionally incremented several times in a row, convert
4208 all but the last increment into a giv. */
4210 /* Get an upper bound for the number of registers
4211 we might have after all bivs have been processed. */
4216 /* If the loop contains volatile memory references do not allow any
4217 replacements to take place, since this could loose the volatile markers. */
4219 {
4222 /* Reallocate reg_iv_type and reg_iv_info. */
4227 {
4231 /* The biv increments lists are in reverse order. Fix this first. */
4233 {
4237 }
4239 /* We must guard against the case that an early exit between v->insn
4240 and next->insn leaves the biv live after the loop, since that
4241 would mean that we'd be missing an increment for the final
4242 value. The following test to set biv_dead_after_loop is like
4243 the first part of the test to set bl->eliminable.
4244 We don't check here if we can calculate the final value, since
4245 this can't succeed if we already know that there is a jump
4246 between v->insn and next->insn, yet next->always_executed is
4247 set and next->maybe_multiple is cleared. Such a combination
4248 implies that the jump destination is outside the loop.
4249 If we want to make this check more sophisticated, we should
4250 check each branch between v->insn and next->insn individually
4251 to see if the biv is dead at its destination. */
4258 #ifdef HAVE_decrement_and_branch_until_zero
4260 #endif
4265 {
4266 HOST_WIDE_INT offset;
4278 || ! (biv_dead_after_loop
4280 {
4283 }
4290 /* Unlike reg_iv_type / reg_iv_info, the other three arrays
4291 have been allocated with some slop space, so we may not
4292 actually need to reallocate them. If we do, the following
4293 if statement will be executed just once in this loop. */
4295 {
4296 /* Grow all the remaining arrays. */
4301 }
4304 {
4307 }
4309 /* Here we can try to eliminate the increment by combining
4310 it into the uses. */
4312 /* Set last_use_insn so that we can check against it. */
4317 {
4321 {
4323 }
4324 }
4326 /* If we can't get the LUIDs for the insns, we can't
4327 calculate the lifetime. This is likely from unrolling
4328 of an inner loop, so there is little point in making this
4329 a DEST_REG giv anyways. */
4333 {
4334 /* Change the increment at NEXT back to what it was. */
4340 }
4374 /* If next_insn has a REG_EQUAL note that mentiones OLD_REG,
4375 it must be replaced. */
4380 /* Remove the increment from the list of biv increments,
4381 and record it as a giv. */
4390 /* Now replace the biv with DEST_REG in all insns between
4391 the replaced increment and the next increment, and
4392 remember the last insn that needed a replacement. */
4396 {
4397 rtx note;
4402 {
4406 }
4408 {
4412 }
4413 }
4417 /* If the lifetime is zero, it means that this register is really
4418 a dead store. So mark this as a giv that can be ignored.
4419 This will not prevent the biv from being eliminated. */
4427 }
4428 }
4429 }
4432 /* Search the loop for general induction variables. */
4434 /* A register is a giv if: it is only set once, it is a function of a
4435 biv and a constant (or invariant), and it is not a biv. */
4442 {
4444 /* At end of a straight-in loop, we are done.
4445 At end of a loop entered at the bottom, scan the top. */
4449 {
4452 else
4456 }
4458 /* Look for a general induction variable in a register. */
4463 {
4464 rtx src_reg;
4465 rtx add_val;
4466 rtx mult_val;
4469 rtx last_consec_insn;
4478 /* Equivalent expression is a giv. */
4483 /* Don't try to handle any regs made by loop optimization.
4484 We have nothing on them in regno_first_uid, etc. */
4486 /* Don't recognize a BASIC_INDUCT_VAR here. */
4488 /* This must be the only place where the register is set. */
4490 /* or all sets must be consecutive and make a giv. */
4495 {
4499 /* If this is a library call, increase benefit. */
4503 /* Skip the consecutive insns, if there are any. */
4511 }
4512 }
4514 #ifndef DONT_REDUCE_ADDR
4515 /* Look for givs which are memory addresses. */
4516 /* This resulted in worse code on a VAX 8600. I wonder if it
4517 still does. */
4521 #endif
4523 /* Update the status of whether giv can derive other givs. This can
4524 change when we pass a label or an insn that updates a biv. */
4529 /* Past CODE_LABEL, we get to insns that may be executed multiple
4530 times. The only way we can be sure that they can't is if every
4531 every jump insn between here and the end of the loop either
4532 returns, exits the loop, is a forward jump, or is a jump
4533 to the loop start. */
4536 {
4542 {
4547 {
4550 else
4554 }
4565 {
4568 }
4569 }
4570 }
4572 /* Past a jump, we get to insns for which we can't count
4573 on whether they will be executed during each iteration. */
4574 /* This code appears twice in strength_reduce. There is also similar
4575 code in scan_loop. */
4577 /* If we enter the loop in the middle, and scan around to the
4578 beginning, don't set not_every_iteration for that.
4579 This can be any kind of jump, since we want to know if insns
4580 will be executed if the loop is executed. */
4584 {
4587 /* If this is a jump outside the loop, then it also doesn't
4588 matter. Check to see if the target of this branch is on the
4589 loop_number_exits_labels list. */
4592 label;
4599 }
4602 {
4603 /* At the virtual top of a converted loop, insns are again known to
4604 be executed each iteration: logically, the loop begins here
4605 even though the exit code has been duplicated.
4607 Insns are also again known to be executed each iteration at
4608 the LOOP_CONT note. */
4614 loop_depth++;
4616 loop_depth--;
4617 }
4619 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4620 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4621 or not an insn is known to be executed each iteration of the
4622 loop, whether or not any iterations are known to occur.
4624 Therefore, if we have just passed a label and have no more labels
4625 between here and the test insn of the loop, we know these insns
4626 will be executed each iteration. */
4632 }
4634 /* Try to calculate and save the number of loop iterations. This is
4635 set to zero if the actual number can not be calculated. This must
4636 be called after all giv's have been identified, since otherwise it may
4637 fail if the iteration variable is a giv. */
4641 /* Now for each giv for which we still don't know whether or not it is
4642 replaceable, check to see if it is replaceable because its final value
4643 can be calculated. This must be done after loop_iterations is called,
4644 so that final_giv_value will work correctly. */
4647 {
4653 }
4655 /* Try to prove that the loop counter variable (if any) is always
4656 nonnegative; if so, record that fact with a REG_NONNEG note
4657 so that "decrement and branch until zero" insn can be used. */
4660 /* Create reg_map to hold substitutions for replaceable giv regs.
4661 Some givs might have been made from biv increments, so look at
4662 reg_iv_type for a suitable size. */
4667 /* Examine each iv class for feasibility of strength reduction/induction
4668 variable elimination. */
4671 {
4678 /* Test whether it will be possible to eliminate this biv
4679 provided all givs are reduced. This is possible if either
4680 the reg is not used outside the loop, or we can compute
4681 what its final value will be.
4683 For architectures with a decrement_and_branch_until_zero insn,
4684 don't do this if we put a REG_NONNEG note on the endtest for
4685 this biv. */
4687 /* Compare against bl->init_insn rather than loop_start.
4688 We aren't concerned with any uses of the biv between
4689 init_insn and loop_start since these won't be affected
4690 by the value of the biv elsewhere in the function, so
4691 long as init_insn doesn't use the biv itself.
4692 March 14, 1989 -- self@bayes.arc.nasa.gov */
4698 #ifdef HAVE_decrement_and_branch_until_zero
4700 #endif
4704 #ifdef HAVE_decrement_and_branch_until_zero
4706 #endif
4707 ))
4710 else
4711 {
4713 {
4721 }
4722 }
4724 /* Combine all giv's for this iv_class. */
4727 /* This will be true at the end, if all givs which depend on this
4728 biv have been strength reduced.
4729 We can't (currently) eliminate the biv unless this is so. */
4732 /* Check each giv in this class to see if we will benefit by reducing
4733 it. Skip giv's combined with others. */
4735 {
4743 /* Reduce benefit if not replaceable, since we will insert
4744 a move-insn to replace the insn that calculates this giv.
4745 Don't do this unless the giv is a user variable, since it
4746 will often be marked non-replaceable because of the duplication
4747 of the exit code outside the loop. In such a case, the copies
4748 we insert are dead and will be deleted. So they don't have
4749 a cost. Similar situations exist. */
4750 /* ??? The new final_[bg]iv_value code does a much better job
4751 of finding replaceable giv's, and hence this code may no longer
4752 be necessary. */
4757 /* Decrease the benefit to count the add-insns that we will
4758 insert to increment the reduced reg for the giv. */
4761 /* Decide whether to strength-reduce this giv or to leave the code
4762 unchanged (recompute it from the biv each time it is used).
4763 This decision can be made independently for each giv. */
4765 #ifdef AUTO_INC_DEC
4766 /* Attempt to guess whether autoincrement will handle some of the
4767 new add insns; if so, increase BENEFIT (undo the subtraction of
4768 add_cost that was done above). */
4771 {
4784 }
4785 #endif
4787 /* If an insn is not to be strength reduced, then set its ignore
4788 flag, and clear all_reduced. */
4790 /* A giv that depends on a reversed biv must be reduced if it is
4791 used after the loop exit, otherwise, it would have the wrong
4792 value after the loop exit. To make it simple, just reduce all
4793 of such giv's whether or not we know they are used after the loop
4794 exit. */
4798 {
4806 }
4807 else
4808 {
4809 /* Check that we can increment the reduced giv without a
4810 multiply insn. If not, reject it. */
4815 {
4823 }
4824 }
4825 }
4827 /* Check for givs whose first use is their definition and whose
4828 last use is the definition of another giv. If so, it is likely
4829 dead and should not be used to derive another giv nor to
4830 eliminate a biv. */
4832 {
4838 {
4844 }
4847 {
4853 }
4854 }
4856 /* Now that we know which givs will be reduced, try to rearrange the
4857 combinations to reduce register pressure.
4858 recombine_givs calls find_life_end, which needs reg_iv_type and
4859 reg_iv_info to be valid for all pseudos. We do the necessary
4860 reallocation here since it allows to check if there are still
4861 more bivs to process. */
4864 {
4865 /* If there are still more bivs to process, allocate some slack
4866 space so that we're not constantly reallocating these arrays. */
4869 /* Reallocate reg_iv_type and reg_iv_info. */
4872 }
4875 /* Reduce each giv that we decided to reduce. */
4878 {
4881 {
4884 /* If the code for derived givs immediately below has already
4885 allocated a new_reg, we must keep it. */
4890 {
4893 /* In case d->dest_reg is not replaceable, we have
4894 to replace it in v->insn now. */
4901 /* For each place where the biv is incremented, add an
4902 insn to set the new, reduced reg for the giv.
4903 We used to do this only for biv_count != 1, but
4904 this fails when there is a giv after a single biv
4905 increment, e.g. when the last giv was expressed as
4906 pre-decrement. */
4908 {
4909 /* We always emit reduced giv increments before the
4910 biv increment when bl->biv_count != 1. So by
4911 emitting the add insns for derived givs after the
4912 biv increment, they pick up the updated value of
4913 the reduced giv.
4914 If the reduced giv is processed with
4915 auto_inc_opt == 1, then it is incremented earlier
4916 than the biv, hence we'll still pick up the right
4917 value.
4918 If it's processed with auto_inc_opt == -1,
4919 that implies that the biv increment is before the
4920 first reduced giv's use. The derived giv's lifetime
4921 is after the reduced giv's lifetime, hence in this
4922 case, the biv increment doesn't matter. */
4924 }
4926 }
4928 #ifdef AUTO_INC_DEC
4929 /* If the target has auto-increment addressing modes, and
4930 this is an address giv, then try to put the increment
4931 immediately after its use, so that flow can create an
4932 auto-increment addressing mode. */
4935 /* We don't handle reversed biv's because bl->biv->insn
4936 does not have a valid INSN_LUID. */
4940 {
4941 /* If other giv's have been combined with this one, then
4942 this will work only if all uses of the other giv's occur
4943 before this giv's insn. This is difficult to check.
4945 We simplify this by looking for the common case where
4946 there is one DEST_REG giv, and this giv's insn is the
4947 last use of the dest_reg of that DEST_REG giv. If the
4948 increment occurs after the address giv, then we can
4949 perform the optimization. (Otherwise, the increment
4950 would have to go before other_giv, and we would not be
4951 able to combine it with the address giv to get an
4952 auto-inc address.) */
4954 {
4959 {
4962 else
4964 }
4971 }
4972 /* Check for case where increment is before the address
4973 giv. Do this test in "loop order". */
4982 else
4985 #ifdef HAVE_cc0
4986 {
4987 rtx prev;
4989 /* We can't put an insn immediately after one setting
4990 cc0, or immediately before one using cc0. */
4997 }
4998 #endif
5002 }
5003 #endif
5005 /* For each place where the biv is incremented, add an insn
5006 to increment the new, reduced reg for the giv. */
5008 {
5009 rtx insert_before;
5015 else
5022 /* A multiply is acceptable here
5023 since this is presumed to be seldom executed. */
5026 }
5028 /* Add code at loop start to initialize giv's reduced reg. */
5032 }
5033 }
5035 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5036 as not reduced.
5038 For each giv register that can be reduced now: if replaceable,
5039 substitute reduced reg wherever the old giv occurs;
5040 else add new move insn "giv_reg = reduced_reg". */
5043 {
5050 /* Update expression if this was combined, in case other giv was
5051 replaced. */
5057 /* Store reduced reg as the address in the memref where we found
5058 this giv. */
5061 {
5064 #if 0
5065 /* I can no longer duplicate the original problem. Perhaps
5066 this is unnecessary now? */
5068 /* Replaceable; it isn't strictly necessary to delete the old
5069 insn and emit a new one, because v->dest_reg is now dead.
5071 However, especially when unrolling loops, the special
5072 handling for (set REG0 REG1) in the second cse pass may
5073 make v->dest_reg live again. To avoid this problem, emit
5074 an insn to set the original giv reg from the reduced giv.
5075 We can not delete the original insn, since it may be part
5076 of a LIBCALL, and the code in flow that eliminates dead
5077 libcalls will fail if it is deleted. */
5080 #endif
5081 }
5082 else
5083 {
5084 /* Not replaceable; emit an insn to set the original giv reg from
5085 the reduced giv, same as above. */
5088 }
5090 /* When a loop is reversed, givs which depend on the reversed
5091 biv, and which are live outside the loop, must be set to their
5092 correct final value. This insn is only needed if the giv is
5093 not replaceable. The correct final value is the same as the
5094 value that the giv starts the reversed loop with. */
5099 {
5100 rtx insert_before;
5102 /* If the loop has multiple exits, emit the insn before the
5103 loop to ensure that it will always be executed no matter
5104 how the loop exits. Otherwise, emit the insn after the loop,
5105 since this is slightly more efficient. */
5108 else
5111 insert_before);
5113 #if 0
5114 /* If the insn to set the final value of the giv was emitted
5115 before the loop, then we must delete the insn inside the loop
5116 that sets it. If this is a LIBCALL, then we must delete
5117 every insn in the libcall. Note, however, that
5118 final_giv_value will only succeed when there are multiple
5119 exits if the giv is dead at each exit, hence it does not
5120 matter that the original insn remains because it is dead
5121 anyways. */
5122 /* Delete the insn inside the loop that sets the giv since
5123 the giv is now set before (or after) the loop. */
5125 #endif
5126 }
5129 {
5134 }
5135 }
5137 /* All the givs based on the biv bl have been reduced if they
5138 merit it. */
5140 /* For each giv not marked as maybe dead that has been combined with a
5141 second giv, clear any "maybe dead" mark on that second giv.
5142 v->new_reg will either be or refer to the register of the giv it
5143 combined with.
5145 Doing this clearing avoids problems in biv elimination where a
5146 giv's new_reg is a complex value that can't be put in the insn but
5147 the giv combined with (with a reg as new_reg) is marked maybe_dead.
5148 Since the register will be used in either case, we'd prefer it be
5149 used from the simpler giv. */
5155 /* Try to eliminate the biv, if it is a candidate.
5156 This won't work if ! all_reduced,
5157 since the givs we planned to use might not have been reduced.
5159 We have to be careful that we didn't initially think we could eliminate
5160 this biv because of a giv that we now think may be dead and shouldn't
5161 be used as a biv replacement.
5163 Also, there is the possibility that we may have a giv that looks
5164 like it can be used to eliminate a biv, but the resulting insn
5165 isn't valid. This can happen, for example, on the 88k, where a
5166 JUMP_INSN can compare a register only with zero. Attempts to
5167 replace it with a compare with a constant will fail.
5169 Note that in cases where this call fails, we may have replaced some
5170 of the occurrences of the biv with a giv, but no harm was done in
5171 doing so in the rare cases where it can occur. */
5177 {
5178 /* ?? If we created a new test to bypass the loop entirely,
5179 or otherwise drop straight in, based on this test, then
5180 we might want to rewrite it also. This way some later
5181 pass has more hope of removing the initialization of this
5182 biv entirely. */
5184 /* If final_value != 0, then the biv may be used after loop end
5185 and we must emit an insn to set it just in case.
5187 Reversed bivs already have an insn after the loop setting their
5188 value, so we don't need another one. We can't calculate the
5189 proper final value for such a biv here anyways. */
5191 {
5192 rtx insert_before;
5194 /* If the loop has multiple exits, emit the insn before the
5195 loop to ensure that it will always be executed no matter
5196 how the loop exits. Otherwise, emit the insn after the
5197 loop, since this is slightly more efficient. */
5200 else
5204 end_insert_before);
5205 }
5207 #if 0
5208 /* Delete all of the instructions inside the loop which set
5209 the biv, as they are all dead. If is safe to delete them,
5210 because an insn setting a biv will never be part of a libcall. */
5211 /* However, deleting them will invalidate the regno_last_uid info,
5212 so keeping them around is more convenient. Final_biv_value
5213 will only succeed when there are multiple exits if the biv
5214 is dead at each exit, hence it does not matter that the original
5215 insn remains, because it is dead anyways. */
5218 #endif
5223 }
5224 }
5226 /* Go through all the instructions in the loop, making all the
5227 register substitutions scheduled in REG_MAP. */
5232 {
5236 }
5239 {
5240 /* When we completely unroll a loop we will likely not need the increment
5241 of the loop BIV and we will not need the conditional branch at the
5242 end of the loop. */
5245 #ifdef HAVE_cc0
5246 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5247 need the comparison before the conditional branch at the end of the
5248 loop. */
5250 #endif
5252 /* We'll need one copy for each loop iteration. */
5255 /* A little slop to account for the ability to remove initialization
5256 code, better CSE, and other secondary benefits of completely
5257 unrolling some loops. */
5260 /* Clamp the value. */
5263 }
5265 /* Unroll loops from within strength reduction so that we can use the
5266 induction variable information that strength_reduce has already
5267 collected. Always unroll loops that would be as small or smaller
5268 unrolled than when rolled. */
5275 #ifdef HAVE_decrement_and_branch_on_count
5276 /* Instrument the loop with BCT insn. */
5285 egress:
5288 }
5289 \f
5290 /* Return 1 if X is a valid source for an initial value (or as value being
5291 compared against in an initial test).
5293 X must be either a register or constant and must not be clobbered between
5294 the current insn and the start of the loop.
5296 INSN is the insn containing X. */
5298 static int
5300 rtx x;
5301 rtx insn;
5303 rtx loop_start;
5304 {
5308 /* Only consider pseudos we know about initialized in insns whose luids
5309 we know. */
5314 /* Don't use call-clobbered registers across a call which clobbers it. On
5315 some machines, don't use any hard registers at all. */
5317 && (SMALL_REGISTER_CLASSES
5321 /* Don't use registers that have been clobbered before the start of the
5322 loop. */
5327 }
5328 \f
5329 /* Scan X for memory refs and check each memory address
5330 as a possible giv. INSN is the insn whose pattern X comes from.
5331 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5332 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5333 more thanonce in each loop iteration. */
5335 static void
5337 loop_end)
5338 rtx x;
5339 rtx insn;
5342 {
5352 {
5368 {
5369 rtx src_reg;
5370 rtx add_val;
5371 rtx mult_val;
5374 /* This code used to disable creating GIVs with mult_val == 1 and
5375 add_val == 0. However, this leads to lost optimizations when
5376 it comes time to combine a set of related DEST_ADDR GIVs, since
5377 this one would not be seen. */
5381 {
5382 /* Found one; record it. */
5391 }
5392 }
5397 }
5399 /* Recursively scan the subexpressions for other mem refs. */
5410 }
5411 \f
5412 /* Fill in the data about one biv update.
5413 V is the `struct induction' in which we record the biv. (It is
5414 allocated by the caller, with alloca.)
5415 INSN is the insn that sets it.
5416 DEST_REG is the biv's reg.
5418 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5419 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5420 being set to INC_VAL.
5422 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5423 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5424 can be executed more than once per iteration. If MAYBE_MULTIPLE
5425 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5426 executed exactly once per iteration. */
5428 static void
5432 rtx insn;
5433 rtx dest_reg;
5434 rtx inc_val;
5435 rtx mult_val;
5439 {
5453 /* Add this to the reg's iv_class, creating a class
5454 if this is the first incrementation of the reg. */
5458 {
5459 /* Create and initialize new iv_class. */
5469 /* Set initial value to the reg itself. */
5471 /* We haven't seen the initializing insn yet */
5481 /* Add this class to loop_iv_list. */
5485 /* Put it in the array of biv register classes. */
5487 }
5489 /* Update IV_CLASS entry for this biv. */
5497 {
5502 {
5506 }
5507 else
5508 {
5512 }
5513 }
5514 }
5515 \f
5516 /* Fill in the data about one giv.
5517 V is the `struct induction' in which we record the giv. (It is
5518 allocated by the caller, with alloca.)
5519 INSN is the insn that sets it.
5520 BENEFIT estimates the savings from deleting this insn.
5521 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5522 into a register or is used as a memory address.
5524 SRC_REG is the biv reg which the giv is computed from.
5525 DEST_REG is the giv's reg (if the giv is stored in a reg).
5526 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5527 LOCATION points to the place where this giv's value appears in INSN. */
5529 static void
5532 loop_end)
5534 rtx insn;
5535 rtx src_reg;
5536 rtx dest_reg;
5543 {
5572 /* The v->always_computable field is used in update_giv_derive, to
5573 determine whether a giv can be used to derive another giv. For a
5574 DEST_REG giv, INSN computes a new value for the giv, so its value
5575 isn't computable if INSN insn't executed every iteration.
5576 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5577 it does not compute a new value. Hence the value is always computable
5578 regardless of whether INSN is executed each iteration. */
5582 else
5588 {
5591 }
5593 {
5599 /* If the lifetime is zero, it means that this register is
5600 really a dead store. So mark this as a giv that can be
5601 ignored. This will not prevent the biv from being eliminated. */
5607 }
5609 /* Add the giv to the class of givs computed from one biv. */
5613 {
5616 /* Don't count DEST_ADDR. This is supposed to count the number of
5617 insns that calculate givs. */
5621 }
5622 else
5623 /* Fatal error, biv missing for this giv? */
5628 else
5629 {
5630 /* The giv can be replaced outright by the reduced register only if all
5631 of the following conditions are true:
5632 - the insn that sets the giv is always executed on any iteration
5633 on which the giv is used at all
5634 (there are two ways to deduce this:
5635 either the insn is executed on every iteration,
5636 or all uses follow that insn in the same basic block),
5637 - the giv is not used outside the loop
5638 - no assignments to the biv occur during the giv's lifetime. */
5641 /* Previous line always fails if INSN was moved by loop opt. */
5643 && (! not_every_iteration
5645 {
5646 /* Now check that there are no assignments to the biv within the
5647 giv's lifetime. This requires two separate checks. */
5649 /* Check each biv update, and fail if any are between the first
5650 and last use of the giv.
5652 If this loop contains an inner loop that was unrolled, then
5653 the insn modifying the biv may have been emitted by the loop
5654 unrolling code, and hence does not have a valid luid. Just
5655 mark the biv as not replaceable in this case. It is not very
5656 useful as a biv, because it is used in two different loops.
5657 It is very unlikely that we would be able to optimize the giv
5658 using this biv anyways. */
5662 {
5668 {
5672 }
5673 }
5675 /* If there are any backwards branches that go from after the
5676 biv update to before it, then this giv is not replaceable. */
5680 {
5684 }
5685 }
5686 else
5687 {
5688 /* May still be replaceable, we don't have enough info here to
5689 decide. */
5692 }
5693 }
5695 /* Record whether the add_val contains a const_int, for later use by
5696 combine_givs. */
5697 {
5702 ;
5706 {
5708 {
5713 else
5715 }
5718 }
5719 }
5722 {
5726 else
5742 {
5745 }
5746 else
5747 {
5750 }
5753 {
5756 }
5757 else
5758 {
5761 }
5762 }
5767 }
5770 /* All this does is determine whether a giv can be made replaceable because
5771 its final value can be calculated. This code can not be part of record_giv
5772 above, because final_giv_value requires that the number of loop iterations
5773 be known, and that can not be accurately calculated until after all givs
5774 have been identified. */
5776 static void
5781 {
5787 /* DEST_ADDR givs will never reach here, because they are always marked
5788 replaceable above in record_giv. */
5790 /* The giv can be replaced outright by the reduced register only if all
5791 of the following conditions are true:
5792 - the insn that sets the giv is always executed on any iteration
5793 on which the giv is used at all
5794 (there are two ways to deduce this:
5795 either the insn is executed on every iteration,
5796 or all uses follow that insn in the same basic block),
5797 - its final value can be calculated (this condition is different
5798 than the one above in record_giv)
5799 - no assignments to the biv occur during the giv's lifetime. */
5801 #if 0
5802 /* This is only called now when replaceable is known to be false. */
5803 /* Clear replaceable, so that it won't confuse final_giv_value. */
5805 #endif
5809 {
5812 rtx last_giv_use;
5816 /* When trying to determine whether or not a biv increment occurs
5817 during the lifetime of the giv, we can ignore uses of the variable
5818 outside the loop because final_value is true. Hence we can not
5819 use regno_last_uid and regno_first_uid as above in record_giv. */
5821 /* Search the loop to determine whether any assignments to the
5822 biv occur during the giv's lifetime. Start with the insn
5823 that sets the giv, and search around the loop until we come
5824 back to that insn again.
5826 Also fail if there is a jump within the giv's lifetime that jumps
5827 to somewhere outside the lifetime but still within the loop. This
5828 catches spaghetti code where the execution order is not linear, and
5829 hence the above test fails. Here we assume that the giv lifetime
5830 does not extend from one iteration of the loop to the next, so as
5831 to make the test easier. Since the lifetime isn't known yet,
5832 this requires two loops. See also record_giv above. */
5837 {
5846 {
5848 {
5850 {
5854 }
5855 }
5860 }
5861 }
5863 /* Now that the lifetime of the giv is known, check for branches
5864 from within the lifetime to outside the lifetime if it is still
5865 replaceable. */
5868 {
5871 {
5884 {
5893 }
5894 }
5895 }
5897 /* If it is replaceable, then save the final value. */
5900 }
5905 }
5906 \f
5907 /* Update the status of whether a giv can derive other givs.
5909 We need to do something special if there is or may be an update to the biv
5910 between the time the giv is defined and the time it is used to derive
5911 another giv.
5913 In addition, a giv that is only conditionally set is not allowed to
5914 derive another giv once a label has been passed.
5916 The cases we look at are when a label or an update to a biv is passed. */
5918 static void
5920 rtx p;
5921 {
5924 rtx tem;
5927 /* Search all IV classes, then all bivs, and finally all givs.
5929 There are three cases we are concerned with. First we have the situation
5930 of a giv that is only updated conditionally. In that case, it may not
5931 derive any givs after a label is passed.
5933 The second case is when a biv update occurs, or may occur, after the
5934 definition of a giv. For certain biv updates (see below) that are
5935 known to occur between the giv definition and use, we can adjust the
5936 giv definition. For others, or when the biv update is conditional,
5937 we must prevent the giv from deriving any other givs. There are two
5938 sub-cases within this case.
5940 If this is a label, we are concerned with any biv update that is done
5941 conditionally, since it may be done after the giv is defined followed by
5942 a branch here (actually, we need to pass both a jump and a label, but
5943 this extra tracking doesn't seem worth it).
5945 If this is a jump, we are concerned about any biv update that may be
5946 executed multiple times. We are actually only concerned about
5947 backward jumps, but it is probably not worth performing the test
5948 on the jump again here.
5950 If this is a biv update, we must adjust the giv status to show that a
5951 subsequent biv update was performed. If this adjustment cannot be done,
5952 the giv cannot derive further givs. */
5958 {
5960 {
5961 /* If cant_derive is already true, there is no point in
5962 checking all of these conditions again. */
5966 /* If this giv is conditionally set and we have passed a label,
5967 it cannot derive anything. */
5971 /* Skip givs that have mult_val == 0, since
5972 they are really invariants. Also skip those that are
5973 replaceable, since we know their lifetime doesn't contain
5974 any biv update. */
5978 /* The only way we can allow this giv to derive another
5979 is if this is a biv increment and we can form the product
5980 of biv->add_val and giv->mult_val. In this case, we will
5981 be able to compute a compensation. */
5983 {
5993 tem = simplify_giv_expr
5999 else
6001 }
6005 }
6006 }
6007 }
6008 \f
6009 /* Check whether an insn is an increment legitimate for a basic induction var.
6010 X is the source of insn P, or a part of it.
6011 MODE is the mode in which X should be interpreted.
6013 DEST_REG is the putative biv, also the destination of the insn.
6014 We accept patterns of these forms:
6015 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6016 REG = INVARIANT + REG
6018 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6019 store the additive term into *INC_VAL, and store the place where
6020 we found the additive term into *LOCATION.
6022 If X is an assignment of an invariant into DEST_REG, we set
6023 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6025 We also want to detect a BIV when it corresponds to a variable
6026 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6027 of the variable may be a PLUS that adds a SUBREG of that variable to
6028 an invariant and then sign- or zero-extends the result of the PLUS
6029 into the variable.
6031 Most GIVs in such cases will be in the promoted mode, since that is the
6032 probably the natural computation mode (and almost certainly the mode
6033 used for addresses) on the machine. So we view the pseudo-reg containing
6034 the variable as the BIV, as if it were simply incremented.
6036 Note that treating the entire pseudo as a BIV will result in making
6037 simple increments to any GIVs based on it. However, if the variable
6038 overflows in its declared mode but not its promoted mode, the result will
6039 be incorrect. This is acceptable if the variable is signed, since
6040 overflows in such cases are undefined, but not if it is unsigned, since
6041 those overflows are defined. So we only check for SIGN_EXTEND and
6042 not ZERO_EXTEND.
6044 If we cannot find a biv, we return 0. */
6046 static int
6050 rtx p;
6051 rtx dest_reg;
6055 {
6063 {
6069 {
6071 }
6076 {
6078 }
6079 else
6092 /* If this is a SUBREG for a promoted variable, check the inner
6093 value. */
6100 /* If this register is assigned in a previous insn, look at its
6101 source, but don't go outside the loop or past a label. */
6105 {
6131 }
6132 /* ... fall through ... */
6134 /* Can accept constant setting of biv only when inside inner most loop.
6135 Otherwise, a biv of an inner loop may be incorrectly recognized
6136 as a biv of the outer loop,
6137 causing code to be moved INTO the inner loop. */
6144 /* convert_modes aborts if we try to convert to or from CCmode, so just
6145 exclude that case. It is very unlikely that a condition code value
6146 would be a useful iterator anyways. */
6150 {
6151 /* Possible bug here? Perhaps we don't know the mode of X. */
6155 }
6156 else
6164 /* Similar, since this can be a sign extension. */
6169 ;
6182 location);
6187 }
6188 }
6189 \f
6190 /* A general induction variable (giv) is any quantity that is a linear
6191 function of a basic induction variable,
6192 i.e. giv = biv * mult_val + add_val.
6193 The coefficients can be any loop invariant quantity.
6194 A giv need not be computed directly from the biv;
6195 it can be computed by way of other givs. */
6197 /* Determine whether X computes a giv.
6198 If it does, return a nonzero value
6199 which is the benefit from eliminating the computation of X;
6200 set *SRC_REG to the register of the biv that it is computed from;
6201 set *ADD_VAL and *MULT_VAL to the coefficients,
6202 such that the value of X is biv * mult + add; */
6204 static int
6206 rtx x;
6212 {
6216 /* If this is an invariant, forget it, it isn't a giv. */
6220 /* See if the expression could be a giv and get its form.
6221 Mark our place on the obstack in case we don't find a giv. */
6226 {
6229 }
6232 {
6235 /* Since this is now an invariant and wasn't before, it must be a giv
6236 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6237 with. */
6244 /* This is equivalent to a BIV. */
6251 /* Either (plus (biv) (invar)) or
6252 (plus (mult (biv) (invar_1)) (invar_2)). */
6254 {
6257 }
6258 else
6259 {
6262 }
6267 /* ADD_VAL is zero. */
6275 }
6277 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6278 unless they are CONST_INT). */
6285 {
6286 #ifdef ADDRESS_COST
6288 #else
6290 #endif
6291 }
6292 else
6295 /* Always return true if this is a giv so it will be detected as such,
6296 even if the benefit is zero or negative. This allows elimination
6297 of bivs that might otherwise not be eliminated. */
6299 }
6300 \f
6301 /* Given an expression, X, try to form it as a linear function of a biv.
6302 We will canonicalize it to be of the form
6303 (plus (mult (BIV) (invar_1))
6304 (invar_2))
6305 with possible degeneracies.
6307 The invariant expressions must each be of a form that can be used as a
6308 machine operand. We surround then with a USE rtx (a hack, but localized
6309 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6310 routine; it is the caller's responsibility to strip them.
6312 If no such canonicalization is possible (i.e., two biv's are used or an
6313 expression that is neither invariant nor a biv or giv), this routine
6314 returns 0.
6316 For a non-zero return, the result will have a code of CONST_INT, USE,
6317 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6319 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6326 static rtx
6328 rtx x;
6330 {
6333 rtx tem;
6335 /* If this is not an integer mode, or if we cannot do arithmetic in this
6336 mode, this can't be a giv. */
6343 {
6350 /* Put constant last, CONST_INT last if both constant. */
6358 /* Handle addition of zero, then addition of an invariant. */
6363 {
6366 /* Adding two invariants must result in an invariant, so enclose
6367 addition operation inside a USE and return it. */
6377 else
6386 /* biv + invar or mult + invar. Return sum. */
6390 /* (a + invar_1) + invar_2. Associate. */
6391 return
6396 arg1)),
6397 benefit);
6401 }
6403 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6404 MULT to reduce cases. */
6410 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6411 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6412 Recurse to associate the second PLUS. */
6417 return
6422 benefit);
6424 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6436 benefit);
6439 /* Handle "a - b" as "a + b * (-1)". */
6444 constm1_rtx)),
6445 benefit);
6453 /* Put constant last, CONST_INT last if both constant. */
6458 /* If second argument is not now constant, not giv. */
6462 /* Handle multiply by 0 or 1. */
6470 {
6472 /* biv * invar. Done. */
6476 /* Product of two constants. */
6480 /* invar * invar. It is a giv, but very few of these will
6481 actually pay off, so limit to simple registers. */
6491 {
6495 }
6496 else
6501 /* (a * invar_1) * invar_2. Associate. */
6506 arg1)),
6507 benefit);
6510 /* (a + invar_1) * invar_2. Distribute. */
6514 arg1),
6517 arg1)),
6518 benefit);
6522 }
6525 /* Shift by constant is multiply by power of two. */
6529 return
6534 benefit);
6537 /* "-a" is "a * (-1)" */
6539 benefit);
6542 /* "~a" is "-a - 1". Silly, but easy. */
6545 const1_rtx),
6546 benefit);
6549 /* Already in proper form for invariant. */
6553 /* If this is a new register, we can't deal with it. */
6557 /* Check for biv or giv. */
6559 {
6563 {
6566 /* Form expression from giv and add benefit. Ensure this giv
6567 can derive another and subtract any needed adjustment if so. */
6579 }
6582 /* If it isn't an induction variable, and it is invariant, we
6583 may be able to simplify things further by looking through
6584 the bits we just moved outside the loop. */
6586 {
6591 {
6592 /* Ok, we found a match. Substitute and simplify. */
6594 /* If we match another movable, we must use that, as
6595 this one is going away. */
6599 /* If consec is non-zero, this is a member of a group of
6600 instructions that were moved together. We handle this
6601 case only to the point of seeking to the last insn and
6602 looking for a REG_EQUAL. Fail if we don't find one. */
6604 {
6612 }
6613 else
6614 {
6618 }
6621 {
6622 /* What we are most interested in is pointer
6623 arithmetic on invariants -- only take
6624 patterns we may be able to do something with. */
6630 {
6634 }
6639 {
6643 }
6644 }
6646 }
6647 }
6649 }
6651 /* Fall through to general case. */
6653 /* If invariant, return as USE (unless CONST_INT).
6654 Otherwise, not giv. */
6659 {
6668 }
6669 else
6671 }
6672 }
6674 /* This routine folds invariants such that there is only ever one
6675 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6677 static rtx
6680 {
6686 {
6689 }
6692 {
6695 }
6696 else
6697 {
6700 }
6701 }
6703 static rtx
6707 {
6709 {
6713 else
6716 }
6719 else
6722 }
6723 \f
6724 /* Help detect a giv that is calculated by several consecutive insns;
6725 for example,
6726 giv = biv * M
6727 giv = giv + A
6728 The caller has already identified the first insn P as having a giv as dest;
6729 we check that all other insns that set the same register follow
6730 immediately after P, that they alter nothing else,
6731 and that the result of the last is still a giv.
6733 The value is 0 if the reg set in P is not really a giv.
6734 Otherwise, the value is the amount gained by eliminating
6735 all the consecutive insns that compute the value.
6737 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6738 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6740 The coefficients of the ultimate giv value are stored in
6741 *MULT_VAL and *ADD_VAL. */
6743 static int
6747 rtx p;
6748 rtx src_reg;
6749 rtx dest_reg;
6753 {
6757 rtx temp;
6758 rtx set;
6760 /* Indicate that this is a giv so that we can update the value produced in
6761 each insn of the multi-insn sequence.
6763 This induction structure will be used only by the call to
6764 general_induction_var below, so we can allocate it on our stack.
6765 If this is a giv, our caller will replace the induct var entry with
6766 a new induction structure. */
6782 {
6786 /* If libcall, skip to end of call sequence. */
6796 /* Giv created by equivalent expression. */
6801 {
6805 count--;
6809 }
6811 {
6812 /* Allow insns that set something other than this giv to a
6813 constant. Such insns are needed on machines which cannot
6814 include long constants and should not disqualify a giv. */
6823 }
6824 }
6828 }
6829 \f
6830 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6831 represented by G1. If no such expression can be found, or it is clear that
6832 it cannot possibly be a valid address, 0 is returned.
6834 To perform the computation, we note that
6835 G1 = x * v + a and
6836 G2 = y * v + b
6837 where `v' is the biv.
6839 So G2 = (y/b) * G1 + (b - a*y/x).
6841 Note that MULT = y/x.
6843 Update: A and B are now allowed to be additive expressions such that
6844 B contains all variables in A. That is, computing B-A will not require
6845 subtracting variables. */
6847 static rtx
6850 {
6851 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6856 /* If MULT is not 1, we cannot handle A with non-constants, since we
6857 would then be required to subtract multiples of the registers in A.
6858 This is theoretically possible, and may even apply to some Fortran
6859 constructs, but it is a lot of work and we do not attempt it here. */
6864 /* In general these structures are sorted top to bottom (down the PLUS
6865 chain), but not left to right across the PLUS. If B is a higher
6866 order giv than A, we can strip one level and recurse. If A is higher
6867 order, we'll eventually bail out, but won't know that until the end.
6868 If they are the same, we'll strip one level around this loop. */
6871 {
6883 /* We matched: remove one reg completely. */
6886 /* An alternate match. */
6889 /* An alternate match. */
6891 else
6892 {
6893 /* Indicates an extra register in B. Strip one level from B and
6894 recurse, hoping B was the higher order expression. */
6899 }
6900 }
6902 /* Here we are at the last level of A, go through the cases hoping to
6903 get rid of everything but a constant. */
6906 {
6919 }
6921 {
6923 }
6925 {
6930 else
6932 }
6937 }
6939 rtx
6942 {
6945 /* The value that G1 will be multiplied by must be a constant integer. Also,
6946 the only chance we have of getting a valid address is if b*c/a (see above
6947 for notation) is also an integer. */
6950 {
6955 }
6958 else
6959 {
6960 /* ??? Find out if the one is a multiple of the other? */
6962 }
6966 {
6967 /* Failed. If we've got a multiplication factor between G1 and G2,
6968 scale G1's addend and try again. */
6970 {
6974 {
6975 HOST_WIDE_INT m;
6979 }
6980 else
6981 {
6983 mult);
6984 }
6987 }
6988 }
6992 /* Form simplified final result. */
6997 else
7002 else
7003 {
7006 {
7010 }
7013 }
7015 }
7016 \f
7017 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7018 represented by G1. This indicates that G2 should be combined with G1 and
7019 that G2 can use (either directly or via an address expression) a register
7020 used to represent G1. */
7022 static rtx
7025 {
7028 /* If these givs are identical, they can be combined. We use the results
7029 of express_from because the addends are not in a canonical form, so
7030 rtx_equal_p is a weaker test. */
7031 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7032 combination to be the other way round. */
7035 {
7037 }
7039 /* If G2 can be expressed as a function of G1 and that function is valid
7040 as an address and no more expensive than using a register for G2,
7041 the expression of G2 in terms of G1 can be used. */
7045 /* ??? Looses, especially with -fforce-addr, where *g2->location
7046 will always be a register, and so anything more complicated
7047 gets discarded. */
7048 #if 0
7049 #ifdef ADDRESS_COST
7051 #else
7053 #endif
7054 #endif
7055 )
7056 {
7058 }
7061 }
7062 \f
7063 struct combine_givs_stats
7064 {
7067 };
7069 static int
7073 {
7080 /* Stabilize the sort. */
7084 }
7086 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7087 any other. If so, point SAME to the giv combined with and set NEW_REG to
7088 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7089 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7091 static void
7094 {
7095 /* Additional benefit to add for being combined multiple times. */
7103 /* Count givs, because bl->giv_count is incorrect here. */
7107 giv_count++;
7109 giv_array
7123 {
7125 rtx single_use;
7130 /* If a DEST_REG GIV is used only once, do not allow it to combine
7131 with anything, for in doing so we will gain nothing that cannot
7132 be had by simply letting the GIV with which we would have combined
7133 to be reduced on its own. The losage shows up in particular with
7134 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7135 be seen elsewhere as well. */
7142 /* Add an additional weight for zero addends. */
7147 {
7148 rtx this_combine;
7153 {
7156 }
7157 }
7159 }
7161 /* Iterate, combining until we can't. */
7162 restart:
7166 {
7169 {
7175 }
7177 }
7180 {
7186 /* If it has already been combined, skip. */
7191 {
7194 /* If it has already been combined, skip. */
7196 {
7206 /* ??? The new final_[bg]iv_value code does a much better job
7207 of finding replaceable giv's, and hence this code may no
7208 longer be necessary. */
7212 /* To help optimize the next set of combinations, remove
7213 this giv from the benefits of other potential mates. */
7215 {
7219 }
7225 }
7226 }
7228 /* To help optimize the next set of combinations, remove
7229 this giv from the benefits of other potential mates. */
7231 {
7233 {
7237 }
7241 /* We've finished with this giv, and everything it touched.
7242 Restart the combination so that proper weights for the
7243 rest of the givs are properly taken into account. */
7244 /* ??? Ideally we would compact the arrays at this point, so
7245 as to not cover old ground. But sanely compacting
7246 can_combine is tricky. */
7248 }
7249 }
7250 }
7251 \f
7252 struct recombine_givs_stats
7253 {
7256 };
7258 /* Used below as comparison function for qsort. We want a ascending luid
7259 when scanning the array starting at the end, thus the arguments are
7260 used in reverse. */
7261 static int
7265 {
7272 /* Stabilize the sort. */
7276 }
7278 /* Scan X, which is a part of INSN, for the end of life of a giv. Also
7279 look for the start of life of a giv where the start has not been seen
7280 yet to unlock the search for the end of its life.
7281 Only consider givs that belong to BIV.
7282 Return the total number of lifetime ends that have been found. */
7283 static int
7287 {
7295 {
7297 {
7300 {
7308 {
7309 /* If we see a 0 here for end_luid, it means that we have
7310 scanned the entire loop without finding any use at all.
7311 We must not predicate this code on a start_luid match
7312 since that would make the test fail for givs that have
7313 been hoisted out of inner loops. */
7315 {
7318 }
7321 }
7323 }
7325 }
7327 {
7335 {
7340 }
7342 }
7350 }
7354 {
7361 }
7363 }
7365 /* For each giv that has been combined with another, look if
7366 we can combine it with the most recently used one instead.
7367 This tends to shorten giv lifetimes, and helps the next step:
7368 try to derive givs from other givs. */
7369 static void
7374 {
7382 {
7384 giv_count++;
7385 }
7386 giv_array
7390 /* Initialize stats and set up the ix field for each giv in stats to name
7391 the corresponding index into stats. */
7393 {
7394 rtx p;
7400 /* If this giv has been hoisted out of an inner loop, use the luid of
7401 the previous insn. */
7405 i++;
7406 }
7410 /* Set up the ix field for each giv in stats to name
7411 the corresponding index into stats, and
7412 do the actual most-recently-used recombination. */
7414 {
7418 {
7420 rtx new_combine;
7422 /* combine_givs_p actually says if we can make this transformation.
7423 The other tests are here only to avoid keeping a giv alive
7424 that could otherwise be eliminated. */
7430 {
7435 /* No need to update lifetimes / benefits here since we have
7436 already decided what to reduce. */
7439 {
7445 }
7447 }
7449 }
7457 }
7460 /* For each DEST_REG giv, compute lifetime starts, and try to compute
7461 lifetime ends from regscan info. */
7463 {
7468 {
7469 /* Loop unrolling of an inner loop can even create new DEST_REG
7470 givs. */
7471 rtx p;
7477 }
7479 {
7481 {
7484 }
7486 {
7487 rtx p;
7488 /* This insn has been created by loop optimization on an inner
7489 loop. We don't have a proper start_luid that will match
7490 when we see the first set. But we do know that there will
7491 be no use before the set, so we can set end_luid to 0 so that
7492 we'll start looking for the last use right away. */
7497 ends_need_computing++;
7498 }
7499 else
7500 {
7505 /* Find the first insn that sets the giv, so that we can verify
7506 if this giv's lifetime wraps around the loop. We also need
7507 the luid of the first setting insn in order to detect the
7508 last use properly. */
7510 {
7513 count--;
7514 }
7518 {
7520 ends_need_computing++;
7521 }
7522 else
7523 {
7526 {
7528 ends_need_computing++;
7529 }
7530 }
7531 }
7532 }
7533 }
7535 /* If the regscan information was unconclusive for one or more DEST_REG
7536 givs, scan the all insn in the loop to find out lifetime ends. */
7538 {
7542 do
7543 {
7550 }
7552 }
7554 /* Set start_luid back to the last insn that sets the giv. This allows
7555 more combinations. */
7557 {
7563 }
7565 /* Now adjust lifetime ends by taking combined givs into account. */
7567 {
7575 {
7578 /* Use unsigned arithmetic to model loop wrap-around. */
7582 }
7583 }
7587 /* Try to derive DEST_REG givs from previous DEST_REG givs with the
7588 same mult_val and non-overlapping lifetime. This reduces register
7589 pressure.
7590 Once we find a DEST_REG giv that is suitable to derive others from,
7591 we set last_giv to this giv, and try to derive as many other DEST_REG
7592 givs from it without joining overlapping lifetimes. If we then
7593 encounter a DEST_REG giv that we can't derive, we set rescan to the
7594 index for this giv (unless rescan is already set).
7595 When we are finished with the current LAST_GIV (i.e. the inner loop
7596 terminates), we start again with rescan, which then becomes the new
7597 LAST_GIV. */
7599 {
7603 {
7604 rtx sum;
7610 {
7611 /* Don't use a giv that's likely to be dead to derive
7612 others - that would be likely to keep that giv alive. */
7614 {
7618 }
7620 }
7621 /* Use unsigned arithmetic to model loop wrap around. */
7626 /* Check that the giv insn we're about to use for deriving
7627 precedes all uses of that giv. Note that initializing the
7628 derived giv would defeat the purpose of reducing register
7629 pressure.
7630 ??? We could arrange to move the insn. */
7634 /* ??? Could handle libcalls, but would need more logic. */
7636 /* We would really like to know if for any giv that v
7637 is combined with, v->insn or any intervening biv increment
7638 dominates that combined giv. However, we
7639 don't have this detailed control flow information.
7640 N.B. since last_giv will be reduced, it is valid
7641 anywhere in the loop, so we don't need to check the
7642 validity of last_giv.
7643 We rely here on the fact that v->always_executed implies that
7644 there is no jump to someplace else in the loop before the
7645 giv insn, and hence any insn that is executed before the
7646 giv insn in the loop will have a lower luid. */
7649 /* Make sure we don't make the add more expensive. ADD_COST
7650 doesn't take different costs of registers and constants into
7651 account, so compare the cost of the actual SET_SRCs. */
7654 /* ??? unroll can't understand anything but reg + const_int
7655 sums. It would be cleaner to fix unroll. */
7662 {
7667 {
7673 }
7674 }
7677 }
7678 }
7679 }
7680 \f
7681 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
7683 void
7689 rtx insert_before;
7690 {
7691 rtx seq;
7692 rtx result;
7694 /* Prevent unexpected sharing of these rtx. */
7698 /* Increase the lifetime of any invariants moved further in code. */
7712 /* It is entirely possible that the expansion created lots of new
7713 registers. Iterate over the sequence we just created and
7714 record them all. */
7717 {
7720 {
7724 }
7725 }
7729 }
7730 \f
7731 /* Test whether A * B can be computed without
7732 an actual multiply insn. Value is 1 if so. */
7734 static int
7736 rtx a;
7737 rtx b;
7738 {
7740 rtx tmp;
7745 /* If only one is constant, make it B. */
7749 /* If first constant, both constant, so don't need multiply. */
7753 /* If second not constant, neither is constant, so would need multiply. */
7757 /* One operand is constant, so might not need multiply insn. Generate the
7758 code for the multiply and see if a call or multiply, or long sequence
7759 of insns is generated. */
7768 {
7773 else
7775 {
7784 {
7787 }
7788 }
7789 }
7798 /* Free any storage we obtained in generating this multiply and restore rtl
7799 allocation to its normal obstack. */
7804 }
7805 \f
7806 /* Check to see if loop can be terminated by a "decrement and branch until
7807 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7808 Also try reversing an increment loop to a decrement loop
7809 to see if the optimization can be performed.
7810 Value is nonzero if optimization was performed. */
7812 /* This is useful even if the architecture doesn't have such an insn,
7813 because it might change a loops which increments from 0 to n to a loop
7814 which decrements from n to 0. A loop that decrements to zero is usually
7815 faster than one that increments from zero. */
7817 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7818 such as approx_final_value, biv_total_increment, loop_iterations, and
7819 final_[bg]iv_value. */
7821 static int
7823 rtx loop_end;
7825 rtx loop_start;
7827 {
7829 rtx reg;
7830 rtx jump_label;
7831 rtx final_value;
7832 rtx start_value;
7833 rtx new_add_val;
7834 rtx comparison;
7835 rtx before_comparison;
7836 rtx p;
7837 rtx jump;
7838 rtx first_compare;
7841 /* If last insn is a conditional branch, and the insn before tests a
7842 register value, try to optimize it. Otherwise, we can't do anything. */
7849 /* Try to compute whether the compare/branch at the loop end is one or
7850 two instructions. */
7856 else
7859 /* Check all of the bivs to see if the compare uses one of them.
7860 Skip biv's set more than once because we can't guarantee that
7861 it will be zero on the last iteration. Also skip if the biv is
7862 used between its update and the test insn. */
7865 {
7869 first_compare))
7871 }
7876 /* Look for the case where the basic induction variable is always
7877 nonnegative, and equals zero on the last iteration.
7878 In this case, add a reg_note REG_NONNEG, which allows the
7879 m68k DBRA instruction to be used. */
7887 {
7888 /* Initial value must be greater than 0,
7889 init_val % -dec_value == 0 to ensure that it equals zero on
7890 the last iteration */
7896 {
7897 /* register always nonnegative, add REG_NOTE to branch */
7904 }
7906 /* If the decrement is 1 and the value was tested as >= 0 before
7907 the loop, then we can safely optimize. */
7909 {
7922 {
7929 }
7930 }
7931 }
7934 {
7935 /* Try to change inc to dec, so can apply above optimization. */
7936 /* Can do this if:
7937 all registers modified are induction variables or invariant,
7938 all memory references have non-overlapping addresses
7939 (obviously true if only one write)
7940 allow 2 insns for the compare/jump at the end of the loop. */
7941 /* Also, we must avoid any instructions which use both the reversed
7942 biv and another biv. Such instructions will fail if the loop is
7943 reversed. We meet this condition by requiring that either
7944 no_use_except_counting is true, or else that there is only
7945 one biv. */
7947 /* 1 if the iteration var is used only to count iterations. */
7949 /* 1 if the loop has no memory store, or it has a single memory store
7950 which is reversible. */
7955 {
7958 /* If there are no givs for this biv, and the only exit is the
7959 fall through at the end of the loop, then
7960 see if perhaps there are no uses except to count. */
7964 {
7969 /* An insn that sets the biv is okay. */
7970 ;
7974 {
7975 /* If either of these insns uses the biv and sets a pseudo
7976 that has more than one usage, then the biv has uses
7977 other than counting since it's used to derive a value
7978 that is used more than one time. */
7983 {
7986 }
7987 }
7989 {
7992 }
7993 }
7994 }
7999 {
8004 /* If the loop has a single store, and the destination address is
8005 invariant, then we can't reverse the loop, because this address
8006 might then have the wrong value at loop exit.
8007 This would work if the source was invariant also, however, in that
8008 case, the insn should have been moved out of the loop. */
8011 {
8014 reversible_mem_store
8015 = (! unknown_address_altered
8018 /* If the store depends on a register that is set after the
8019 store, it depends on the initial value, and is thus not
8020 reversible. */
8022 {
8028 }
8029 }
8030 }
8031 else
8034 /* This code only acts for innermost loops. Also it simplifies
8035 the memory address check by only reversing loops with
8036 zero or one memory access.
8037 Two memory accesses could involve parts of the same array,
8038 and that can't be reversed.
8039 If the biv is used only for counting, than we don't need to worry
8040 about all these things. */
8045 && reversible_mem_store
8050 {
8051 rtx tem;
8053 /* Loop can be reversed. */
8057 /* Now check other conditions:
8059 The increment must be a constant, as must the initial value,
8060 and the comparison code must be LT.
8062 This test can probably be improved since +/- 1 in the constant
8063 can be obtained by changing LT to LE and vice versa; this is
8064 confusing. */
8067 /* for constants, LE gets turned into LT */
8071 {
8082 comparison_const_width
8084 else
8085 comparison_const_width
8089 comparison_sign_mask
8092 /* If the comparison value is not a loop invariant, then we
8093 can not reverse this loop.
8095 ??? If the insns which initialize the comparison value as
8096 a whole compute an invariant result, then we could move
8097 them out of the loop and proceed with loop reversal. */
8105 /* Normalize the initial value if it is an integer and
8106 has no other use except as a counter. This will allow
8107 a few more loops to be reversed. */
8111 {
8113 /* The code below requires comparison_val to be a multiple
8114 of add_val in order to do the loop reversal, so
8115 round up comparison_val to a multiple of add_val.
8116 Since comparison_value is constant, we know that the
8117 current comparison code is LT. */
8119 comparison_val
8121 /* We postpone overflow checks for COMPARISON_VAL here;
8122 even if there is an overflow, we might still be able to
8123 reverse the loop, if converting the loop exit test to
8124 NE is possible. */
8126 }
8128 /* First check if we can do a vanilla loop reversal. */
8130 /* If we have a decrement_and_branch_on_count,
8131 prefer the NE test, since this will allow that
8132 instruction to be generated. Note that we must
8133 use a vanilla loop reversal if the biv is used to
8134 calculate a giv or has a non-counting use. */
8135 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8136 && defined (HAVE_decrement_and_branch_on_count)
8140 #endif
8142 /* Now do postponed overflow checks on COMPARISON_VAL. */
8145 {
8146 /* Register will always be nonnegative, with value
8147 0 on last iteration */
8151 }
8155 {
8158 }
8159 else
8165 /* If the initial value is not zero, or if the comparison
8166 value is not an exact multiple of the increment, then we
8167 can not reverse this loop. */
8170 {
8173 }
8174 else
8175 {
8178 }
8182 /* Reset these in case we normalized the initial value
8183 and comparison value above. */
8186 {
8188 final_value
8190 }
8193 /* Save some info needed to produce the new insns. */
8200 /* Set start_value; if this is not a CONST_INT, we need
8201 to generate a SUB.
8202 Initialize biv to start_value before loop start.
8203 The old initializing insn will be deleted as a
8204 dead store by flow.c. */
8207 {
8210 loop_start);
8211 }
8213 {
8216 enum insn_code icode
8225 start_value
8229 loop_start);
8233 }
8235 {
8237 enum insn_code icode
8245 start_value
8249 loop_start);
8250 }
8251 else
8252 /* We could handle the other cases too, but it'll be
8253 better to have a testcase first. */
8256 /* We may not have a single insn which can increment a reg, so
8257 create a sequence to hold all the insns from expand_inc. */
8266 /* Update biv info to reflect its new status. */
8271 /* Update loop info. */
8280 /* Inc LABEL_NUSES so that delete_insn will
8281 not delete the label. */
8284 /* Emit an insn after the end of the loop to set the biv's
8285 proper exit value if it is used anywhere outside the loop. */
8290 loop_end);
8292 /* Delete compare/branch at end of loop. */
8297 /* Add new compare/branch insn at end of loop. */
8309 ;
8315 {
8317 {
8318 /* Increment of LABEL_NUSES done above. */
8319 /* Register is now always nonnegative,
8320 so add REG_NONNEG note to the branch. */
8323 }
8325 }
8327 /* No insn may reference both the reversed and another biv or it
8328 will fail (see comment near the top of the loop reversal
8329 code).
8330 Earlier on, we have verified that the biv has no use except
8331 counting, or it is the only biv in this function.
8332 However, the code that computes no_use_except_counting does
8333 not verify reg notes. It's possible to have an insn that
8334 references another biv, and has a REG_EQUAL note with an
8335 expression based on the reversed biv. To avoid this case,
8336 remove all REG_EQUAL notes based on the reversed biv
8337 here. */
8340 {
8343 /* If this is a set of a GIV based on the reversed biv, any
8344 REG_EQUAL notes should still be correct. */
8351 {
8356 else
8358 }
8359 }
8361 /* Mark that this biv has been reversed. Each giv which depends
8362 on this biv, and which is also live past the end of the loop
8363 will have to be fixed up. */
8368 {
8372 else
8374 }
8377 }
8378 }
8379 }
8382 }
8383 \f
8384 /* Verify whether the biv BL appears to be eliminable,
8385 based on the insns in the loop that refer to it.
8386 LOOP_START is the first insn of the loop, and END is the end insn.
8388 If ELIMINATE_P is non-zero, actually do the elimination.
8390 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8391 determine whether invariant insns should be placed inside or at the
8392 start of the loop. */
8394 static int
8397 rtx loop_start;
8398 rtx end;
8401 {
8403 rtx p;
8405 /* Scan all insns in the loop, stopping if we find one that uses the
8406 biv in a way that we cannot eliminate. */
8409 {
8413 /* If this is a libcall that sets a giv, skip ahead to its end. */
8415 {
8419 {
8424 {
8431 }
8432 }
8433 }
8437 {
8443 }
8444 }
8447 {
8452 }
8455 }
8456 \f
8457 /* INSN and REFERENCE are instructions in the same insn chain.
8458 Return non-zero if INSN is first. */
8460 int
8463 {
8467 {
8468 /* Start with test for not first so that INSN == REFERENCE yields not
8469 first. */
8475 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8476 previous insn, hence the <= comparison below does not work if
8477 P is a note. */
8488 }
8489 }
8491 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8492 the offset that we have to take into account due to auto-increment /
8493 div derivation is zero. */
8494 static int
8497 rtx insn;
8498 {
8499 /* If the giv V had the auto-inc address optimization applied
8500 to it, and INSN occurs between the giv insn and the biv
8501 insn, then we'd have to adjust the value used here.
8502 This is rare, so we don't bother to make this possible. */
8510 /* If the giv V was derived from another giv, and INSN does
8511 not occur between the giv insn and the biv insn, then we'd
8512 have to adjust the value used here. This is rare, so we don't
8513 bother to make this possible. */
8527 }
8529 /* If BL appears in X (part of the pattern of INSN), see if we can
8530 eliminate its use. If so, return 1. If not, return 0.
8532 If BIV does not appear in X, return 1.
8534 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
8535 where extra insns should be added. Depending on how many items have been
8536 moved out of the loop, it will either be before INSN or at the start of
8537 the loop. */
8539 static int
8544 rtx where;
8545 {
8551 #ifdef HAVE_cc0
8553 #endif
8559 {
8561 /* If we haven't already been able to do something with this BIV,
8562 we can't eliminate it. */
8568 /* If this sets the BIV, it is not a problem. */
8572 /* If this is an insn that defines a giv, it is also ok because
8573 it will go away when the giv is reduced. */
8578 #ifdef HAVE_cc0
8580 {
8581 /* Can replace with any giv that was reduced and
8582 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8583 Require a constant for MULT_VAL, so we know it's nonzero.
8584 ??? We disable this optimization to avoid potential
8585 overflows. */
8593 {
8600 /* If the giv has the opposite direction of change,
8601 then reverse the comparison. */
8605 else
8608 /* We can probably test that giv's reduced reg. */
8611 }
8613 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8614 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8615 Require a constant for MULT_VAL, so we know it's nonzero.
8616 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8617 overflow problem. */
8628 {
8635 /* If the giv has the opposite direction of change,
8636 then reverse the comparison. */
8640 else
8644 /* Replace biv with the giv's reduced register. */
8649 /* Insn doesn't support that constant or invariant. Copy it
8650 into a register (it will be a loop invariant.) */
8654 where);
8656 /* Substitute the new register for its invariant value in
8657 the compare expression. */
8661 }
8662 }
8663 #endif
8670 /* See if either argument is the biv. */
8675 else
8679 {
8680 /* First try to replace with any giv that has constant positive
8681 mult_val and constant add_val. We might be able to support
8682 negative mult_val, but it seems complex to do it in general. */
8693 {
8700 /* Replace biv with the giv's reduced reg. */
8703 /* If all constants are actually constant integers and
8704 the derived constant can be directly placed in the COMPARE,
8705 do so. */
8715 /* Otherwise, load it into a register. */
8721 /* If that failed, put back the change we made above. */
8723 }
8725 /* Look for giv with positive constant mult_val and nonconst add_val.
8726 Insert insns to calculate new compare value.
8727 ??? Turn this off due to possible overflow. */
8734 {
8735 rtx tem;
8745 /* Replace biv with giv's reduced register. */
8749 /* Compute value to compare against. */
8751 /* Use it in this insn. */
8755 }
8756 }
8758 {
8760 {
8761 /* Look for giv with constant positive mult_val and nonconst
8762 add_val. Insert insns to compute new compare value.
8763 ??? Turn this off due to possible overflow. */
8770 {
8771 rtx tem;
8781 /* Replace biv with giv's reduced register. */
8785 /* Compute value to compare against. */
8791 }
8792 }
8794 /* This code has problems. Basically, you can't know when
8795 seeing if we will eliminate BL, whether a particular giv
8796 of ARG will be reduced. If it isn't going to be reduced,
8797 we can't eliminate BL. We can try forcing it to be reduced,
8798 but that can generate poor code.
8800 The problem is that the benefit of reducing TV, below should
8801 be increased if BL can actually be eliminated, but this means
8802 we might have to do a topological sort of the order in which
8803 we try to process biv. It doesn't seem worthwhile to do
8804 this sort of thing now. */
8806 #if 0
8807 /* Otherwise the reg compared with had better be a biv. */
8812 /* Look for a pair of givs, one for each biv,
8813 with identical coefficients. */
8815 {
8826 {
8833 /* Replace biv with its giv's reduced reg. */
8835 /* Replace other operand with the other giv's
8836 reduced reg. */
8839 }
8840 }
8841 #endif
8842 }
8844 /* If we get here, the biv can't be eliminated. */
8848 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8849 biv is used in it, since it will be replaced. */
8857 }
8859 /* See if any subexpression fails elimination. */
8862 {
8864 {
8877 }
8878 }
8881 }
8882 \f
8883 /* Return nonzero if the last use of REG
8884 is in an insn following INSN in the same basic block. */
8886 static int
8888 rtx reg;
8889 rtx insn;
8890 {
8891 rtx n;
8895 {
8898 }
8900 }
8901 \f
8902 /* Called via `note_stores' to record the initial value of a biv. Here we
8903 just record the location of the set and process it later. */
8905 static void
8907 rtx dest;
8908 rtx set;
8910 {
8920 /* If this is the first set found, record it. */
8922 {
8925 }
8926 }
8927 \f
8928 /* If any of the registers in X are "old" and currently have a last use earlier
8929 than INSN, update them to have a last use of INSN. Their actual last use
8930 will be the previous insn but it will not have a valid uid_luid so we can't
8931 use it. */
8933 static void
8935 rtx x;
8936 rtx insn;
8937 {
8938 /* Check for the case where INSN does not have a valid luid. In this case,
8939 there is no need to modify the regno_last_uid, as this can only happen
8940 when code is inserted after the loop_end to set a pseudo's final value,
8941 and hence this insn will never be the last use of x. */
8946 else
8947 {
8951 {
8957 }
8958 }
8959 }
8960 \f
8961 /* Given a jump insn JUMP, return the condition that will cause it to branch
8962 to its JUMP_LABEL. If the condition cannot be understood, or is an
8963 inequality floating-point comparison which needs to be reversed, 0 will
8964 be returned.
8966 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8967 insn used in locating the condition was found. If a replacement test
8968 of the condition is desired, it should be placed in front of that
8969 insn and we will be sure that the inputs are still valid.
8971 The condition will be returned in a canonical form to simplify testing by
8972 callers. Specifically:
8974 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8975 (2) Both operands will be machine operands; (cc0) will have been replaced.
8976 (3) If an operand is a constant, it will be the second operand.
8977 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8978 for GE, GEU, and LEU. */
8980 rtx
8982 rtx jump;
8984 {
8987 rtx set;
8988 rtx tem;
8994 /* If this is not a standard conditional jump, we can't parse it. */
9007 /* If this branches to JUMP_LABEL when the condition is false, reverse
9008 the condition. */
9013 /* If we are comparing a register with zero, see if the register is set
9014 in the previous insn to a COMPARE or a comparison operation. Perform
9015 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9016 in cse.c */
9019 {
9020 /* Set non-zero when we find something of interest. */
9023 #ifdef HAVE_cc0
9024 /* If comparison with cc0, import actual comparison from compare
9025 insn. */
9027 {
9038 }
9039 #endif
9041 /* If this is a COMPARE, pick up the two things being compared. */
9043 {
9047 }
9051 /* Go back to the previous insn. Stop if it is not an INSN. We also
9052 stop if it isn't a single set or if it has a REG_INC note because
9053 we don't want to bother dealing with it. */
9061 /* If this is setting OP0, get what it sets it to if it looks
9062 relevant. */
9064 {
9067 /* ??? We may not combine comparisons done in a CCmode with
9068 comparisons not done in a CCmode. This is to aid targets
9069 like Alpha that have an IEEE compliant EQ instruction, and
9070 a non-IEEE compliant BEQ instruction. The use of CCmode is
9071 actually artificial, simply to prevent the combination, but
9072 should not affect other platforms.
9074 However, we must allow VOIDmode comparisons to match either
9075 CCmode or non-CCmode comparison, because some ports have
9076 modeless comparisons inside branch patterns.
9078 ??? This mode check should perhaps look more like the mode check
9079 in simplify_comparison in combine. */
9087 && (STORE_FLAG_VALUE
9090 #ifdef FLOAT_STORE_FLAG_VALUE
9094 #endif
9095 ))
9106 && (STORE_FLAG_VALUE
9109 #ifdef FLOAT_STORE_FLAG_VALUE
9113 #endif
9114 ))
9120 {
9121 /* We might have reversed a LT to get a GE here. But this wasn't
9122 actually the comparison of data, so we don't flag that we
9123 have had to reverse the condition. */
9127 }
9128 else
9130 }
9133 /* If this sets OP0, but not directly, we have to give up. */
9137 {
9141 {
9145 }
9150 }
9151 }
9153 /* If constant is first, put it last. */
9157 /* If OP0 is the result of a comparison, we weren't able to find what
9158 was really being compared, so fail. */
9162 /* Canonicalize any ordered comparison with integers involving equality
9163 if we can do computations in the relevant mode and we do not
9164 overflow. */
9169 {
9172 unsigned HOST_WIDE_INT max_val
9176 {
9182 /* When cross-compiling, const_val might be sign-extended from
9183 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9203 }
9204 }
9206 /* If this was floating-point and we reversed anything other than an
9207 EQ or NE, return zero. */
9210 && ! flag_fast_math
9214 #ifdef HAVE_cc0
9215 /* Never return CC0; return zero instead. */
9218 #endif
9221 }
9223 /* Similar to above routine, except that we also put an invariant last
9224 unless both operands are invariants. */
9226 rtx
9228 rtx x;
9229 {
9239 }
9241 #ifdef HAVE_decrement_and_branch_on_count
9242 /* Instrument loop for insertion of bct instruction. We distinguish between
9243 loops with compile-time bounds and those with run-time bounds.
9244 Information from loop_iterations() is used to compute compile-time bounds.
9245 Run-time bounds should use loop preconditioning, but currently ignored.
9246 */
9248 static void
9252 {
9258 /* If the loop condition is <= or >=, the number of iteration
9259 is 1 more than the range of the bounds of the loop. */
9266 /* It's impossible to instrument a competely unrolled loop. */
9270 /* Make sure that the count register is not in use. */
9272 {
9276 loop_num);
9278 }
9280 /* Make sure that the function has no indirect jumps. */
9282 {
9286 loop_num);
9288 }
9290 /* Make sure that the last loop insn is a conditional jump. */
9294 {
9298 loop_num);
9300 }
9302 /* Make sure that the loop does not contain a function call
9303 (the count register might be altered by the called function). */
9305 {
9309 loop_num);
9311 }
9313 /* Make sure that the loop does not jump via a table.
9314 (the count register might be used to perform the branch on table). */
9316 {
9320 loop_num);
9322 }
9324 /* Account for loop unrolling in instrumented iteration count. */
9327 else
9331 {
9332 /* Allow an enclosing outer loop to benefit if possible. */
9336 loop_num);
9338 }
9340 /* Try to instrument the loop. */
9342 /* Handle the simpler case, where the bounds are known at compile time. */
9344 {
9345 /* Mark all enclosing loops that they cannot use count register. */
9350 }
9352 /* Handle the more complex case, that the bounds are NOT known
9353 at compile time. In this case we generate run_time calculation
9354 of the number of iterations. */
9357 {
9361 loop_num);
9363 }
9367 {
9371 loop_num);
9373 }
9375 /* With runtime bounds, if the compare is of the form '!=' we give up */
9377 {
9381 loop_num);
9383 }
9384 /* Use common loop preconditioning code instead. */
9385 #if 0
9386 else
9387 {
9388 /* We rely on the existence of run-time guard to ensure that the
9389 loop executes at least once. */
9390 rtx sequence;
9391 rtx iterations_num_reg;
9393 unsigned HOST_WIDE_INT increment_value_abs
9396 /* make sure that the increment is a power of two, otherwise (an
9397 expensive) divide is needed. */
9399 {
9404 }
9406 /* compute the number of iterations */
9408 {
9409 rtx temp_reg;
9411 /* Again, the number of iterations is calculated by:
9412 ;
9413 ; compare-val - initial-val + (increment -1) + additional-iteration
9414 ; num_iterations = -----------------------------------------------------------------
9415 ; increment
9416 */
9417 /* ??? Do we have to call copy_rtx here before passing rtx to
9418 expand_binop? */
9420 {
9421 /* <, <= :the loop variable is increasing */
9425 }
9426 else
9427 {
9431 }
9441 temp_reg,
9444 else
9446 }
9451 }
9455 }
9457 /* Instrument loop by inserting a bct in it as follows:
9458 1. A new counter register is created.
9459 2. In the head of the loop the new variable is initialized to the value
9460 passed in the loop_num_iterations parameter.
9461 3. At the end of the loop, comparison of the register with 0 is generated.
9462 The created comparison follows the pattern defined for the
9463 decrement_and_branch_on_count insn, so this insn will be generated.
9464 4. The branch on the old variable are deleted. The compare must remain
9465 because it might be used elsewhere. If the loop-variable or condition
9466 register are used elsewhere, they will be eliminated by flow. */
9468 static void
9471 rtx loop_num_iterations;
9472 {
9473 rtx counter_reg;
9474 rtx start_label;
9475 rtx sequence;
9478 {
9480 {
9485 else
9488 }
9490 /* Discard original jump to continue loop. Original compare result
9491 may still be live, so it cannot be discarded explicitly. */
9494 /* Insert the label which will delimit the start of the loop. */
9498 /* Insert initialization of the count register into the loop header. */
9506 /* Insert new comparison on the count register instead of the
9507 old one, generating the needed BCT pattern (that will be
9508 later recognized by assembly generation phase). */
9510 start_label),
9511 loop_end);
9513 }
9515 }
9518 /* Scan the function and determine whether it has indirect (computed) jumps.
9520 This is taken mostly from flow.c; similar code exists elsewhere
9521 in the compiler. It may be useful to put this into rtlanal.c. */
9522 static int
9524 rtx start;
9525 {
9526 rtx insn;
9533 }
9535 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9536 documentation for LOOP_MEMS for the definition of `appropriate'.
9537 This function is called from prescan_loop via for_each_rtx. */
9539 static int
9543 {
9551 {
9556 /* We're not interested in the MEM associated with a
9557 CONST_DOUBLE, so there's no need to traverse into this. */
9561 /* This is not a MEM. */
9563 }
9565 /* See if we've already seen this MEM. */
9568 {
9570 /* The modes of the two memory accesses are different. If
9571 this happens, something tricky is going on, and we just
9572 don't optimize accesses to this MEM. */
9576 }
9578 /* Resize the array, if necessary. */
9580 {
9583 else
9589 }
9591 /* Actually insert the MEM. */
9593 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9594 because we can't put it in a register. We still store it in the
9595 table, though, so that if we see the same address later, but in a
9596 non-BLK mode, we'll not think we can optimize it at that point. */
9602 }
9604 /* Like load_mems, but also ensures that SET_IN_LOOP,
9605 MAY_NOT_OPTIMIZE, REG_SINGLE_USAGE, and INSN_COUNT have the correct
9606 values after load_mems. */
9608 static void
9610 insn_count)
9611 rtx scan_start;
9612 rtx end;
9613 rtx loop_top;
9614 rtx start;
9616 {
9621 /* Recalculate set_in_loop and friends since load_mems may have
9622 created new registers. */
9624 {
9632 {
9633 /* Grow all the arrays. */
9638 }
9639 /* Clear the arrays */
9649 {
9652 }
9654 #ifdef AVOID_CCMODE_COPIES
9655 /* Don't try to move insns which set CC registers if we should not
9656 create CCmode register copies. */
9660 #endif
9662 /* Set n_times_set for the new registers. */
9666 }
9667 }
9669 /* Move MEMs into registers for the duration of the loop. SCAN_START
9670 is the first instruction in the loop (as it is executed). The
9671 other parameters are as for next_insn_in_loop. */
9673 static void
9675 rtx scan_start;
9676 rtx end;
9677 rtx loop_top;
9678 rtx start;
9679 {
9682 rtx p;
9687 {
9688 /* Nonzero if the next instruction may never be executed. */
9691 /* Check to see if it's possible that some instructions in the
9692 loop are never executed. */
9696 {
9700 /* If we enter the loop in the middle, and scan
9701 around to the beginning, don't set maybe_never
9702 for that. This must be an unconditional jump,
9703 otherwise the code at the top of the loop might
9704 never be executed. Unconditional jumps are
9705 followed a by barrier then loop end. */
9710 {
9712 /* Something complicated. */
9714 else
9715 /* If there are any more instructions in the loop, they
9716 might not be reached. */
9718 }
9721 }
9723 /* Actually move the MEMs. */
9725 {
9727 rtx reg;
9729 rtx mem_list_entry;
9733 /* There's no telling whether or not MEM is modified. */
9736 /* Go through the MEMs written to in the loop to see if this
9737 one is aliased by one of them. */
9740 {
9745 {
9746 /* MEM is indeed aliased by this store. */
9749 }
9751 }
9753 /* If this MEM is written to, we must be sure that there
9754 are no reads from another MEM that aliases this one. */
9756 {
9760 {
9764 VOIDmode,
9766 rtx_varies_p))
9767 {
9768 /* It's not safe to hoist loop_mems[i] out of
9769 the loop because writes to it might not be
9770 seen by reads from loop_mems[j]. */
9773 }
9774 }
9775 }
9778 /* We can't access the MEM outside the loop; it might
9779 cause a trap that wouldn't have happened otherwise. */
9783 /* We thought we were going to lift this MEM out of the
9784 loop, but later discovered that we could not. */
9787 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9788 order to keep scan_loop from moving stores to this MEM
9789 out of the loop just because this REG is neither a
9790 user-variable nor used in the loop test. */
9795 /* Now, replace all references to the MEM with the
9796 corresponding pesudos. */
9800 {
9801 rtx_and_int ri;
9805 }
9808 /* We couldn't replace all occurrences of the MEM. */
9810 else
9811 {
9812 rtx set;
9814 /* Load the memory immediately before START, which is
9815 the NOTE_LOOP_BEG. */
9820 {
9822 {
9823 /* We must compute the former
9824 right-after-the-end label before we insert
9825 the new one. */
9829 }
9831 /* Store the memory immediately after END, which is
9832 the NOTE_LOOP_END. */
9835 }
9838 {
9843 }
9844 }
9845 }
9846 }
9849 {
9850 /* Now, we need to replace all references to the previous exit
9851 label with the new one. */
9852 rtx_pair rr;
9857 {
9860 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9861 field. This is not handled by for_each_rtx because it doesn't
9862 handle unprinted ('0') fields. We need to update JUMP_LABEL
9863 because the immediately following unroll pass will use it.
9864 replace_label would not work anyways, because that only handles
9865 LABEL_REFs. */
9868 }
9869 }
9870 }
9872 /* Replace MEM with its associated pseudo register. This function is
9873 called from load_mems via for_each_rtx. DATA is actually an
9874 rtx_and_int * describing the instruction currently being scanned
9875 and the MEM we are currently replacing. */
9877 static int
9881 {
9883 rtx insn;
9891 {
9896 /* We're not interested in the MEM associated with a
9897 CONST_DOUBLE, so there's no need to traverse into one. */
9901 /* This is not a MEM. */
9903 }
9909 /* This is not the MEM we are currently replacing. */
9914 /* Actually replace the MEM. */
9918 }
9920 /* Replace occurrences of the old exit label for the loop with the new
9921 one. DATA is an rtx_pair containing the old and new labels,
9922 respectively. */
9924 static int
9928 {
9947 }