[RS6000] dg-do !compile and scan-assembler
[official-gcc.git] / gcc / testsuite / gcc.target / powerpc / p9-vec-length-full-6.c
blob5d2357aabfa5752847f649edc3ab4808dafd14d7
1 /* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */
2 /* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops" } */
4 /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */
6 /* Test for fully with length, the loop body uses vector access with length,
7 there should not be any epilogues. */
9 #include "p9-vec-length-6.h"
11 /* It can use normal vector load for constant vector load. */
12 /* { dg-final { scan-assembler-times {\mstxvx?\M} 6 } } */
13 /* 64bit/32bit pairs won't use partial vectors. */
14 /* { dg-final { scan-assembler-times {\mlxvl\M} 10 } } */
15 /* { dg-final { scan-assembler-times {\mstxvl\M} 10 } } */