gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 /* combine_instructions may try to replace the right hand side of the
 127    second instruction with the value of an associated REG_EQUAL note
 128    before throwing it at try_combine.  That is problematic when there
 129    is a REG_DEAD note for a register used in the old right hand side
 130    and can cause distribute_notes to do wrong things.  This is the
 131    second instruction if it has been so modified, null otherwise.  */
 132
 133 static rtx i2mod;
 134
 135 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 136
 137 static rtx i2mod_old_rhs;
 138
 139 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 140
 141 static rtx i2mod_new_rhs;
 142 \f
 143 /* Vector mapping INSN_UIDs to cuids.
 144    The cuids are like uids but increase monotonically always.
 145    Combine always uses cuids so that it can compare them.
 146    But actually renumbering the uids, which we used to do,
 147    proves to be a bad idea because it makes it hard to compare
 148    the dumps produced by earlier passes with those from later passes.  */
 149
 150 static int *uid_cuid;
 151 static int max_uid_cuid;
 152
 153 /* Get the cuid of an insn.  */
 154
 155 #define INSN_CUID(INSN) \
 156 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 157
 158 /* Maximum register number, which is the size of the tables below.  */
 159
 160 static unsigned int combine_max_regno;
 161
 162 struct reg_stat {
 163   /* Record last point of death of (hard or pseudo) register n.  */
 164   rtx                           last_death;
 165
 166   /* Record last point of modification of (hard or pseudo) register n.  */
 167   rtx                           last_set;
 168
 169   /* The next group of fields allows the recording of the last value assigned
 170      to (hard or pseudo) register n.  We use this information to see if an
 171      operation being processed is redundant given a prior operation performed
 172      on the register.  For example, an `and' with a constant is redundant if
 173      all the zero bits are already known to be turned off.
 174
 175      We use an approach similar to that used by cse, but change it in the
 176      following ways:
 177
 178      (1) We do not want to reinitialize at each label.
 179      (2) It is useful, but not critical, to know the actual value assigned
 180          to a register.  Often just its form is helpful.
 181
 182      Therefore, we maintain the following fields:
 183
 184      last_set_value             the last value assigned
 185      last_set_label             records the value of label_tick when the
 186                                 register was assigned
 187      last_set_table_tick        records the value of label_tick when a
 188                                 value using the register is assigned
 189      last_set_invalid           set to nonzero when it is not valid
 190                                 to use the value of this register in some
 191                                 register's value
 192
 193      To understand the usage of these tables, it is important to understand
 194      the distinction between the value in last_set_value being valid and
 195      the register being validly contained in some other expression in the
 196      table.
 197
 198      (The next two parameters are out of date).
 199
 200      reg_stat[i].last_set_value is valid if it is nonzero, and either
 201      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 202
 203      Register I may validly appear in any expression returned for the value
 204      of another register if reg_n_sets[i] is 1.  It may also appear in the
 205      value for register J if reg_stat[j].last_set_invalid is zero, or
 206      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 207
 208      If an expression is found in the table containing a register which may
 209      not validly appear in an expression, the register is replaced by
 210      something that won't match, (clobber (const_int 0)).  */
 211
 212   /* Record last value assigned to (hard or pseudo) register n.  */
 213
 214   rtx                           last_set_value;
 215
 216   /* Record the value of label_tick when an expression involving register n
 217      is placed in last_set_value.  */
 218
 219   int                           last_set_table_tick;
 220
 221   /* Record the value of label_tick when the value for register n is placed in
 222      last_set_value.  */
 223
 224   int                           last_set_label;
 225
 226   /* These fields are maintained in parallel with last_set_value and are
 227      used to store the mode in which the register was last set, the bits
 228      that were known to be zero when it was last set, and the number of
 229      sign bits copies it was known to have when it was last set.  */
 230
 231   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 232   char                          last_set_sign_bit_copies;
 233   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 234
 235   /* Set nonzero if references to register n in expressions should not be
 236      used.  last_set_invalid is set nonzero when this register is being
 237      assigned to and last_set_table_tick == label_tick.  */
 238
 239   char                          last_set_invalid;
 240
 241   /* Some registers that are set more than once and used in more than one
 242      basic block are nevertheless always set in similar ways.  For example,
 243      a QImode register may be loaded from memory in two places on a machine
 244      where byte loads zero extend.
 245
 246      We record in the following fields if a register has some leading bits
 247      that are always equal to the sign bit, and what we know about the
 248      nonzero bits of a register, specifically which bits are known to be
 249      zero.
 250
 251      If an entry is zero, it means that we don't know anything special.  */
 252
 253   unsigned char                 sign_bit_copies;
 254
 255   unsigned HOST_WIDE_INT        nonzero_bits;
 256
 257   /* Record the value of the label_tick when the last truncation
 258      happened.  The field truncated_to_mode is only valid if
 259      truncation_label == label_tick.  */
 260
 261   int                           truncation_label;
 262
 263   /* Record the last truncation seen for this register.  If truncation
 264      is not a nop to this mode we might be able to save an explicit
 265      truncation if we know that value already contains a truncated
 266      value.  */
 267
 268   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 269 };
 270
 271 static struct reg_stat *reg_stat;
 272
 273 /* Record the cuid of the last insn that invalidated memory
 274    (anything that writes memory, and subroutine calls, but not pushes).  */
 275
 276 static int mem_last_set;
 277
 278 /* Record the cuid of the last CALL_INSN
 279    so we can tell whether a potential combination crosses any calls.  */
 280
 281 static int last_call_cuid;
 282
 283 /* When `subst' is called, this is the insn that is being modified
 284    (by combining in a previous insn).  The PATTERN of this insn
 285    is still the old pattern partially modified and it should not be
 286    looked at, but this may be used to examine the successors of the insn
 287    to judge whether a simplification is valid.  */
 288
 289 static rtx subst_insn;
 290
 291 /* This is the lowest CUID that `subst' is currently dealing with.
 292    get_last_value will not return a value if the register was set at or
 293    after this CUID.  If not for this mechanism, we could get confused if
 294    I2 or I1 in try_combine were an insn that used the old value of a register
 295    to obtain a new value.  In that case, we might erroneously get the
 296    new value of the register when we wanted the old one.  */
 297
 298 static int subst_low_cuid;
 299
 300 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 301    must consider all these registers to be always live.  */
 302
 303 static HARD_REG_SET newpat_used_regs;
 304
 305 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 306    insn is the earlier than I2 or I3, combine should rescan starting at
 307    that location.  */
 308
 309 static rtx added_links_insn;
 310
 311 /* Basic block in which we are performing combines.  */
 312 static basic_block this_basic_block;
 313
 314 /* A bitmap indicating which blocks had registers go dead at entry.
 315    After combine, we'll need to re-do global life analysis with
 316    those blocks as starting points.  */
 317 static sbitmap refresh_blocks;
 318 \f
 319 /* The following array records the insn_rtx_cost for every insn
 320    in the instruction stream.  */
 321
 322 static int *uid_insn_cost;
 323
 324 /* Length of the currently allocated uid_insn_cost array.  */
 325
 326 static int last_insn_cost;
 327
 328 /* Incremented for each label.  */
 329
 330 static int label_tick;
 331
 332 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 333    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 334
 335 static enum machine_mode nonzero_bits_mode;
 336
 337 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 338    be safely used.  It is zero while computing them and after combine has
 339    completed.  This former test prevents propagating values based on
 340    previously set values, which can be incorrect if a variable is modified
 341    in a loop.  */
 342
 343 static int nonzero_sign_valid;
 344
 345 \f
 346 /* Record one modification to rtl structure
 347    to be undone by storing old_contents into *where.  */
 348
 349 struct undo
 350 {
 351   struct undo *next;
 352   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 353   union { rtx r; int i; enum machine_mode m; } old_contents;
 354   union { rtx *r; int *i; } where;
 355 };
 356
 357 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 358    num_undo says how many are currently recorded.
 359
 360    other_insn is nonzero if we have modified some other insn in the process
 361    of working on subst_insn.  It must be verified too.  */
 362
 363 struct undobuf
 364 {
 365   struct undo *undos;
 366   struct undo *frees;
 367   rtx other_insn;
 368 };
 369
 370 static struct undobuf undobuf;
 371
 372 /* Number of times the pseudo being substituted for
 373    was found and replaced.  */
 374
 375 static int n_occurrences;
 376
 377 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 378                                          enum machine_mode,
 379                                          unsigned HOST_WIDE_INT,
 380                                          unsigned HOST_WIDE_INT *);
 381 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 382                                                 enum machine_mode,
 383                                                 unsigned int, unsigned int *);
 384 static void do_SUBST (rtx *, rtx);
 385 static void do_SUBST_INT (int *, int);
 386 static void init_reg_last (void);
 387 static void setup_incoming_promotions (void);
 388 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 389 static int cant_combine_insn_p (rtx);
 390 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 391 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 392 static int contains_muldiv (rtx);
 393 static rtx try_combine (rtx, rtx, rtx, int *);
 394 static void undo_all (void);
 395 static void undo_commit (void);
 396 static rtx *find_split_point (rtx *, rtx);
 397 static rtx subst (rtx, rtx, rtx, int, int);
 398 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 399 static rtx simplify_if_then_else (rtx);
 400 static rtx simplify_set (rtx);
 401 static rtx simplify_logical (rtx);
 402 static rtx expand_compound_operation (rtx);
 403 static rtx expand_field_assignment (rtx);
 404 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 405                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 406 static rtx extract_left_shift (rtx, int);
 407 static rtx make_compound_operation (rtx, enum rtx_code);
 408 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 409                               unsigned HOST_WIDE_INT *);
 410 static rtx canon_reg_for_combine (rtx, rtx);
 411 static rtx force_to_mode (rtx, enum machine_mode,
 412                           unsigned HOST_WIDE_INT, int);
 413 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 414 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 415 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 416 static rtx make_field_assignment (rtx);
 417 static rtx apply_distributive_law (rtx);
 418 static rtx distribute_and_simplify_rtx (rtx, int);
 419 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 420                                      unsigned HOST_WIDE_INT);
 421 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 422                                    unsigned HOST_WIDE_INT);
 423 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 424                             HOST_WIDE_INT, enum machine_mode, int *);
 425 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 426 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 427                                  int);
 428 static int recog_for_combine (rtx *, rtx, rtx *);
 429 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 430 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 431 static void update_table_tick (rtx);
 432 static void record_value_for_reg (rtx, rtx, rtx);
 433 static void check_conversions (rtx, rtx);
 434 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 435 static void record_dead_and_set_regs (rtx);
 436 static int get_last_value_validate (rtx *, rtx, int, int);
 437 static rtx get_last_value (rtx);
 438 static int use_crosses_set_p (rtx, int);
 439 static void reg_dead_at_p_1 (rtx, rtx, void *);
 440 static int reg_dead_at_p (rtx, rtx);
 441 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 442 static int reg_bitfield_target_p (rtx, rtx);
 443 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 444 static void distribute_links (rtx);
 445 static void mark_used_regs_combine (rtx);
 446 static int insn_cuid (rtx);
 447 static void record_promoted_value (rtx, rtx);
 448 static int unmentioned_reg_p_1 (rtx *, void *);
 449 static bool unmentioned_reg_p (rtx, rtx);
 450 static void record_truncated_value (rtx);
 451 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 452 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 453 \f
 454
 455 /* It is not safe to use ordinary gen_lowpart in combine.
 456    See comments in gen_lowpart_for_combine.  */
 457 #undef RTL_HOOKS_GEN_LOWPART
 458 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 459
 460 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 461 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 462 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 463
 464 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 465 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 466
 467 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 468 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 469
 470 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 471 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 472
 473 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 474
 475 \f
 476 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 477    insn.  The substitution can be undone by undo_all.  If INTO is already
 478    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 479    also call SUBST, we have to compute it before we put anything into
 480    the undo table.  */
 481
 482 static void
 483 do_SUBST (rtx *into, rtx newval)
 484 {
 485   struct undo *buf;
 486   rtx oldval = *into;
 487
 488   if (oldval == newval)
 489     return;
 490
 491   /* We'd like to catch as many invalid transformations here as
 492      possible.  Unfortunately, there are way too many mode changes
 493      that are perfectly valid, so we'd waste too much effort for
 494      little gain doing the checks here.  Focus on catching invalid
 495      transformations involving integer constants.  */
 496   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 497       && GET_CODE (newval) == CONST_INT)
 498     {
 499       /* Sanity check that we're replacing oldval with a CONST_INT
 500          that is a valid sign-extension for the original mode.  */
 501       gcc_assert (INTVAL (newval)
 502                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 503
 504       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 505          CONST_INT is not valid, because after the replacement, the
 506          original mode would be gone.  Unfortunately, we can't tell
 507          when do_SUBST is called to replace the operand thereof, so we
 508          perform this test on oldval instead, checking whether an
 509          invalid replacement took place before we got here.  */
 510       gcc_assert (!(GET_CODE (oldval) == SUBREG
 511                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 512       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 513                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 514     }
 515
 516   if (undobuf.frees)
 517     buf = undobuf.frees, undobuf.frees = buf->next;
 518   else
 519     buf = XNEW (struct undo);
 520
 521   buf->kind = UNDO_RTX;
 522   buf->where.r = into;
 523   buf->old_contents.r = oldval;
 524   *into = newval;
 525
 526   buf->next = undobuf.undos, undobuf.undos = buf;
 527 }
 528
 529 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 530
 531 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 532    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 533    not safe.  */
 534
 535 static void
 536 do_SUBST_INT (int *into, int newval)
 537 {
 538   struct undo *buf;
 539   int oldval = *into;
 540
 541   if (oldval == newval)
 542     return;
 543
 544   if (undobuf.frees)
 545     buf = undobuf.frees, undobuf.frees = buf->next;
 546   else
 547     buf = XNEW (struct undo);
 548
 549   buf->kind = UNDO_INT;
 550   buf->where.i = into;
 551   buf->old_contents.i = oldval;
 552   *into = newval;
 553
 554   buf->next = undobuf.undos, undobuf.undos = buf;
 555 }
 556
 557 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 558
 559 /* Similar to SUBST, but just substitute the mode.  This is used when
 560    changing the mode of a pseudo-register, so that any other
 561    references to the entry in the regno_reg_rtx array will change as
 562    well.  */
 563
 564 static void
 565 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 566 {
 567   struct undo *buf;
 568   enum machine_mode oldval = GET_MODE (*into);
 569
 570   if (oldval == newval)
 571     return;
 572
 573   if (undobuf.frees)
 574     buf = undobuf.frees, undobuf.frees = buf->next;
 575   else
 576     buf = XNEW (struct undo);
 577
 578   buf->kind = UNDO_MODE;
 579   buf->where.r = into;
 580   buf->old_contents.m = oldval;
 581   PUT_MODE (*into, newval);
 582
 583   buf->next = undobuf.undos, undobuf.undos = buf;
 584 }
 585
 586 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 587 \f
 588 /* Subroutine of try_combine.  Determine whether the combine replacement
 589    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 590    that the original instruction sequence I1, I2 and I3.  Note that I1
 591    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 592    costs of all instructions can be estimated, and the replacements are
 593    more expensive than the original sequence.  */
 594
 595 static bool
 596 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 597 {
 598   int i1_cost, i2_cost, i3_cost;
 599   int new_i2_cost, new_i3_cost;
 600   int old_cost, new_cost;
 601
 602   /* Lookup the original insn_rtx_costs.  */
 603   i2_cost = INSN_UID (i2) <= last_insn_cost
 604             ? uid_insn_cost[INSN_UID (i2)] : 0;
 605   i3_cost = INSN_UID (i3) <= last_insn_cost
 606             ? uid_insn_cost[INSN_UID (i3)] : 0;
 607
 608   if (i1)
 609     {
 610       i1_cost = INSN_UID (i1) <= last_insn_cost
 611                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 612       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 613                  ? i1_cost + i2_cost + i3_cost : 0;
 614     }
 615   else
 616     {
 617       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 618       i1_cost = 0;
 619     }
 620
 621   /* Calculate the replacement insn_rtx_costs.  */
 622   new_i3_cost = insn_rtx_cost (newpat);
 623   if (newi2pat)
 624     {
 625       new_i2_cost = insn_rtx_cost (newi2pat);
 626       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 627                  ? new_i2_cost + new_i3_cost : 0;
 628     }
 629   else
 630     {
 631       new_cost = new_i3_cost;
 632       new_i2_cost = 0;
 633     }
 634
 635   if (undobuf.other_insn)
 636     {
 637       int old_other_cost, new_other_cost;
 638
 639       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 640                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 641       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 642       if (old_other_cost > 0 && new_other_cost > 0)
 643         {
 644           old_cost += old_other_cost;
 645           new_cost += new_other_cost;
 646         }
 647       else
 648         old_cost = 0;
 649     }
 650
 651   /* Disallow this recombination if both new_cost and old_cost are
 652      greater than zero, and new_cost is greater than old cost.  */
 653   if (old_cost > 0
 654       && new_cost > old_cost)
 655     {
 656       if (dump_file)
 657         {
 658           if (i1)
 659             {
 660               fprintf (dump_file,
 661                        "rejecting combination of insns %d, %d and %d\n",
 662                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 663               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 664                        i1_cost, i2_cost, i3_cost, old_cost);
 665             }
 666           else
 667             {
 668               fprintf (dump_file,
 669                        "rejecting combination of insns %d and %d\n",
 670                        INSN_UID (i2), INSN_UID (i3));
 671               fprintf (dump_file, "original costs %d + %d = %d\n",
 672                        i2_cost, i3_cost, old_cost);
 673             }
 674
 675           if (newi2pat)
 676             {
 677               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 678                        new_i2_cost, new_i3_cost, new_cost);
 679             }
 680           else
 681             fprintf (dump_file, "replacement cost %d\n", new_cost);
 682         }
 683
 684       return false;
 685     }
 686
 687   /* Update the uid_insn_cost array with the replacement costs.  */
 688   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 689   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 690   if (i1)
 691     uid_insn_cost[INSN_UID (i1)] = 0;
 692
 693   return true;
 694 }
 695 \f
 696 /* Main entry point for combiner.  F is the first insn of the function.
 697    NREGS is the first unused pseudo-reg number.
 698
 699    Return nonzero if the combiner has turned an indirect jump
 700    instruction into a direct jump.  */
 701 static int
 702 combine_instructions (rtx f, unsigned int nregs)
 703 {
 704   rtx insn, next;
 705 #ifdef HAVE_cc0
 706   rtx prev;
 707 #endif
 708   int i;
 709   unsigned int j = 0;
 710   rtx links, nextlinks;
 711   sbitmap_iterator sbi;
 712
 713   int new_direct_jump_p = 0;
 714
 715   combine_attempts = 0;
 716   combine_merges = 0;
 717   combine_extras = 0;
 718   combine_successes = 0;
 719
 720   combine_max_regno = nregs;
 721
 722   rtl_hooks = combine_rtl_hooks;
 723
 724   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 725
 726   init_recog_no_volatile ();
 727
 728   /* Compute maximum uid value so uid_cuid can be allocated.  */
 729
 730   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 731     if (INSN_UID (insn) > i)
 732       i = INSN_UID (insn);
 733
 734   uid_cuid = XNEWVEC (int, i + 1);
 735   max_uid_cuid = i;
 736
 737   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 738
 739   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 740      problems when, for example, we have j <<= 1 in a loop.  */
 741
 742   nonzero_sign_valid = 0;
 743
 744   /* Compute the mapping from uids to cuids.
 745      Cuids are numbers assigned to insns, like uids,
 746      except that cuids increase monotonically through the code.
 747
 748      Scan all SETs and see if we can deduce anything about what
 749      bits are known to be zero for some registers and how many copies
 750      of the sign bit are known to exist for those registers.
 751
 752      Also set any known values so that we can use it while searching
 753      for what bits are known to be set.  */
 754
 755   label_tick = 1;
 756
 757   setup_incoming_promotions ();
 758
 759   refresh_blocks = sbitmap_alloc (last_basic_block);
 760   sbitmap_zero (refresh_blocks);
 761
 762   /* Allocate array of current insn_rtx_costs.  */
 763   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 764   last_insn_cost = max_uid_cuid;
 765
 766   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 767     {
 768       uid_cuid[INSN_UID (insn)] = ++i;
 769       subst_low_cuid = i;
 770       subst_insn = insn;
 771
 772       if (INSN_P (insn))
 773         {
 774           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 775                        NULL);
 776           record_dead_and_set_regs (insn);
 777
 778 #ifdef AUTO_INC_DEC
 779           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 780             if (REG_NOTE_KIND (links) == REG_INC)
 781               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 782                                                 NULL);
 783 #endif
 784
 785           /* Record the current insn_rtx_cost of this instruction.  */
 786           if (NONJUMP_INSN_P (insn))
 787             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 788           if (dump_file)
 789             fprintf(dump_file, "insn_cost %d: %d\n",
 790                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 791         }
 792
 793       if (LABEL_P (insn))
 794         label_tick++;
 795     }
 796
 797   nonzero_sign_valid = 1;
 798
 799   /* Now scan all the insns in forward order.  */
 800
 801   label_tick = 1;
 802   last_call_cuid = 0;
 803   mem_last_set = 0;
 804   init_reg_last ();
 805   setup_incoming_promotions ();
 806
 807   FOR_EACH_BB (this_basic_block)
 808     {
 809       for (insn = BB_HEAD (this_basic_block);
 810            insn != NEXT_INSN (BB_END (this_basic_block));
 811            insn = next ? next : NEXT_INSN (insn))
 812         {
 813           next = 0;
 814
 815           if (LABEL_P (insn))
 816             label_tick++;
 817
 818           else if (INSN_P (insn))
 819             {
 820               /* See if we know about function return values before this
 821                  insn based upon SUBREG flags.  */
 822               check_conversions (insn, PATTERN (insn));
 823
 824               /* Try this insn with each insn it links back to.  */
 825
 826               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 827                 if ((next = try_combine (insn, XEXP (links, 0),
 828                                          NULL_RTX, &new_direct_jump_p)) != 0)
 829                   goto retry;
 830
 831               /* Try each sequence of three linked insns ending with this one.  */
 832
 833               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 834                 {
 835                   rtx link = XEXP (links, 0);
 836
 837                   /* If the linked insn has been replaced by a note, then there
 838                      is no point in pursuing this chain any further.  */
 839                   if (NOTE_P (link))
 840                     continue;
 841
 842                   for (nextlinks = LOG_LINKS (link);
 843                        nextlinks;
 844                        nextlinks = XEXP (nextlinks, 1))
 845                     if ((next = try_combine (insn, link,
 846                                              XEXP (nextlinks, 0),
 847                                              &new_direct_jump_p)) != 0)
 848                       goto retry;
 849                 }
 850
 851 #ifdef HAVE_cc0
 852               /* Try to combine a jump insn that uses CC0
 853                  with a preceding insn that sets CC0, and maybe with its
 854                  logical predecessor as well.
 855                  This is how we make decrement-and-branch insns.
 856                  We need this special code because data flow connections
 857                  via CC0 do not get entered in LOG_LINKS.  */
 858
 859               if (JUMP_P (insn)
 860                   && (prev = prev_nonnote_insn (insn)) != 0
 861                   && NONJUMP_INSN_P (prev)
 862                   && sets_cc0_p (PATTERN (prev)))
 863                 {
 864                   if ((next = try_combine (insn, prev,
 865                                            NULL_RTX, &new_direct_jump_p)) != 0)
 866                     goto retry;
 867
 868                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 869                        nextlinks = XEXP (nextlinks, 1))
 870                     if ((next = try_combine (insn, prev,
 871                                              XEXP (nextlinks, 0),
 872                                              &new_direct_jump_p)) != 0)
 873                       goto retry;
 874                 }
 875
 876               /* Do the same for an insn that explicitly references CC0.  */
 877               if (NONJUMP_INSN_P (insn)
 878                   && (prev = prev_nonnote_insn (insn)) != 0
 879                   && NONJUMP_INSN_P (prev)
 880                   && sets_cc0_p (PATTERN (prev))
 881                   && GET_CODE (PATTERN (insn)) == SET
 882                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 883                 {
 884                   if ((next = try_combine (insn, prev,
 885                                            NULL_RTX, &new_direct_jump_p)) != 0)
 886                     goto retry;
 887
 888                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 889                        nextlinks = XEXP (nextlinks, 1))
 890                     if ((next = try_combine (insn, prev,
 891                                              XEXP (nextlinks, 0),
 892                                              &new_direct_jump_p)) != 0)
 893                       goto retry;
 894                 }
 895
 896               /* Finally, see if any of the insns that this insn links to
 897                  explicitly references CC0.  If so, try this insn, that insn,
 898                  and its predecessor if it sets CC0.  */
 899               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 900                 if (NONJUMP_INSN_P (XEXP (links, 0))
 901                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 902                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 903                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 904                     && NONJUMP_INSN_P (prev)
 905                     && sets_cc0_p (PATTERN (prev))
 906                     && (next = try_combine (insn, XEXP (links, 0),
 907                                             prev, &new_direct_jump_p)) != 0)
 908                   goto retry;
 909 #endif
 910
 911               /* Try combining an insn with two different insns whose results it
 912                  uses.  */
 913               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 914                 for (nextlinks = XEXP (links, 1); nextlinks;
 915                      nextlinks = XEXP (nextlinks, 1))
 916                   if ((next = try_combine (insn, XEXP (links, 0),
 917                                            XEXP (nextlinks, 0),
 918                                            &new_direct_jump_p)) != 0)
 919                     goto retry;
 920
 921               /* Try this insn with each REG_EQUAL note it links back to.  */
 922               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 923                 {
 924                   rtx set, note;
 925                   rtx temp = XEXP (links, 0);
 926                   if ((set = single_set (temp)) != 0
 927                       && (note = find_reg_equal_equiv_note (temp)) != 0
 928                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 929                       /* Avoid using a register that may already been marked
 930                          dead by an earlier instruction.  */
 931                       && ! unmentioned_reg_p (note, SET_SRC (set))
 932                       && (GET_MODE (note) == VOIDmode
 933                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 934                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 935                     {
 936                       /* Temporarily replace the set's source with the
 937                          contents of the REG_EQUAL note.  The insn will
 938                          be deleted or recognized by try_combine.  */
 939                       rtx orig = SET_SRC (set);
 940                       SET_SRC (set) = note;
 941                       i2mod = temp;
 942                       i2mod_old_rhs = copy_rtx (orig);
 943                       i2mod_new_rhs = copy_rtx (note);
 944                       next = try_combine (insn, i2mod, NULL_RTX,
 945                                           &new_direct_jump_p);
 946                       i2mod = NULL_RTX;
 947                       if (next)
 948                         goto retry;
 949                       SET_SRC (set) = orig;
 950                     }
 951                 }
 952
 953               if (!NOTE_P (insn))
 954                 record_dead_and_set_regs (insn);
 955
 956             retry:
 957               ;
 958             }
 959         }
 960     }
 961   clear_bb_flags ();
 962
 963   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 964     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 965   new_direct_jump_p |= purge_all_dead_edges ();
 966   delete_noop_moves ();
 967
 968   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 969                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 970                                     | PROP_KILL_DEAD_CODE);
 971
 972   /* Clean up.  */
 973   sbitmap_free (refresh_blocks);
 974   free (uid_insn_cost);
 975   free (reg_stat);
 976   free (uid_cuid);
 977
 978   {
 979     struct undo *undo, *next;
 980     for (undo = undobuf.frees; undo; undo = next)
 981       {
 982         next = undo->next;
 983         free (undo);
 984       }
 985     undobuf.frees = 0;
 986   }
 987
 988   total_attempts += combine_attempts;
 989   total_merges += combine_merges;
 990   total_extras += combine_extras;
 991   total_successes += combine_successes;
 992
 993   nonzero_sign_valid = 0;
 994   rtl_hooks = general_rtl_hooks;
 995
 996   /* Make recognizer allow volatile MEMs again.  */
 997   init_recog ();
 998
 999   return new_direct_jump_p;
1000 }
1001
1002 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1003
1004 static void
1005 init_reg_last (void)
1006 {
1007   unsigned int i;
1008   for (i = 0; i < combine_max_regno; i++)
1009     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
1010 }
1011 \f
1012 /* Set up any promoted values for incoming argument registers.  */
1013
1014 static void
1015 setup_incoming_promotions (void)
1016 {
1017   unsigned int regno;
1018   rtx reg;
1019   enum machine_mode mode;
1020   int unsignedp;
1021   rtx first = get_insns ();
1022
1023   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1024     {
1025       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1026         /* Check whether this register can hold an incoming pointer
1027            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1028            numbers, so translate if necessary due to register windows.  */
1029         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1030             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1031           {
1032             record_value_for_reg
1033               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1034                                            : SIGN_EXTEND),
1035                                           GET_MODE (reg),
1036                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1037           }
1038     }
1039 }
1040 \f
1041 /* Called via note_stores.  If X is a pseudo that is narrower than
1042    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1043
1044    If we are setting only a portion of X and we can't figure out what
1045    portion, assume all bits will be used since we don't know what will
1046    be happening.
1047
1048    Similarly, set how many bits of X are known to be copies of the sign bit
1049    at all locations in the function.  This is the smallest number implied
1050    by any set of X.  */
1051
1052 static void
1053 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1054                                   void *data ATTRIBUTE_UNUSED)
1055 {
1056   unsigned int num;
1057
1058   if (REG_P (x)
1059       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1060       /* If this register is undefined at the start of the file, we can't
1061          say what its contents were.  */
1062       && ! REGNO_REG_SET_P
1063          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1064       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1065     {
1066       if (set == 0 || GET_CODE (set) == CLOBBER)
1067         {
1068           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1069           reg_stat[REGNO (x)].sign_bit_copies = 1;
1070           return;
1071         }
1072
1073       /* If this is a complex assignment, see if we can convert it into a
1074          simple assignment.  */
1075       set = expand_field_assignment (set);
1076
1077       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1078          set what we know about X.  */
1079
1080       if (SET_DEST (set) == x
1081           || (GET_CODE (SET_DEST (set)) == SUBREG
1082               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1083                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1084               && SUBREG_REG (SET_DEST (set)) == x))
1085         {
1086           rtx src = SET_SRC (set);
1087
1088 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1089           /* If X is narrower than a word and SRC is a non-negative
1090              constant that would appear negative in the mode of X,
1091              sign-extend it for use in reg_stat[].nonzero_bits because some
1092              machines (maybe most) will actually do the sign-extension
1093              and this is the conservative approach.
1094
1095              ??? For 2.5, try to tighten up the MD files in this regard
1096              instead of this kludge.  */
1097
1098           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1099               && GET_CODE (src) == CONST_INT
1100               && INTVAL (src) > 0
1101               && 0 != (INTVAL (src)
1102                        & ((HOST_WIDE_INT) 1
1103                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1104             src = GEN_INT (INTVAL (src)
1105                            | ((HOST_WIDE_INT) (-1)
1106                               << GET_MODE_BITSIZE (GET_MODE (x))));
1107 #endif
1108
1109           /* Don't call nonzero_bits if it cannot change anything.  */
1110           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1111             reg_stat[REGNO (x)].nonzero_bits
1112               |= nonzero_bits (src, nonzero_bits_mode);
1113           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1114           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1115               || reg_stat[REGNO (x)].sign_bit_copies > num)
1116             reg_stat[REGNO (x)].sign_bit_copies = num;
1117         }
1118       else
1119         {
1120           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1121           reg_stat[REGNO (x)].sign_bit_copies = 1;
1122         }
1123     }
1124 }
1125 \f
1126 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1127    insns that were previously combined into I3 or that will be combined
1128    into the merger of INSN and I3.
1129
1130    Return 0 if the combination is not allowed for any reason.
1131
1132    If the combination is allowed, *PDEST will be set to the single
1133    destination of INSN and *PSRC to the single source, and this function
1134    will return 1.  */
1135
1136 static int
1137 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1138                rtx *pdest, rtx *psrc)
1139 {
1140   int i;
1141   rtx set = 0, src, dest;
1142   rtx p;
1143 #ifdef AUTO_INC_DEC
1144   rtx link;
1145 #endif
1146   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1147                               && next_active_insn (succ) == i3)
1148                       : next_active_insn (insn) == i3);
1149
1150   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1151      or a PARALLEL consisting of such a SET and CLOBBERs.
1152
1153      If INSN has CLOBBER parallel parts, ignore them for our processing.
1154      By definition, these happen during the execution of the insn.  When it
1155      is merged with another insn, all bets are off.  If they are, in fact,
1156      needed and aren't also supplied in I3, they may be added by
1157      recog_for_combine.  Otherwise, it won't match.
1158
1159      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1160      note.
1161
1162      Get the source and destination of INSN.  If more than one, can't
1163      combine.  */
1164
1165   if (GET_CODE (PATTERN (insn)) == SET)
1166     set = PATTERN (insn);
1167   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1168            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1169     {
1170       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1171         {
1172           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1173           rtx note;
1174
1175           switch (GET_CODE (elt))
1176             {
1177             /* This is important to combine floating point insns
1178                for the SH4 port.  */
1179             case USE:
1180               /* Combining an isolated USE doesn't make sense.
1181                  We depend here on combinable_i3pat to reject them.  */
1182               /* The code below this loop only verifies that the inputs of
1183                  the SET in INSN do not change.  We call reg_set_between_p
1184                  to verify that the REG in the USE does not change between
1185                  I3 and INSN.
1186                  If the USE in INSN was for a pseudo register, the matching
1187                  insn pattern will likely match any register; combining this
1188                  with any other USE would only be safe if we knew that the
1189                  used registers have identical values, or if there was
1190                  something to tell them apart, e.g. different modes.  For
1191                  now, we forgo such complicated tests and simply disallow
1192                  combining of USES of pseudo registers with any other USE.  */
1193               if (REG_P (XEXP (elt, 0))
1194                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1195                 {
1196                   rtx i3pat = PATTERN (i3);
1197                   int i = XVECLEN (i3pat, 0) - 1;
1198                   unsigned int regno = REGNO (XEXP (elt, 0));
1199
1200                   do
1201                     {
1202                       rtx i3elt = XVECEXP (i3pat, 0, i);
1203
1204                       if (GET_CODE (i3elt) == USE
1205                           && REG_P (XEXP (i3elt, 0))
1206                           && (REGNO (XEXP (i3elt, 0)) == regno
1207                               ? reg_set_between_p (XEXP (elt, 0),
1208                                                    PREV_INSN (insn), i3)
1209                               : regno >= FIRST_PSEUDO_REGISTER))
1210                         return 0;
1211                     }
1212                   while (--i >= 0);
1213                 }
1214               break;
1215
1216               /* We can ignore CLOBBERs.  */
1217             case CLOBBER:
1218               break;
1219
1220             case SET:
1221               /* Ignore SETs whose result isn't used but not those that
1222                  have side-effects.  */
1223               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1224                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1225                       || INTVAL (XEXP (note, 0)) <= 0)
1226                   && ! side_effects_p (elt))
1227                 break;
1228
1229               /* If we have already found a SET, this is a second one and
1230                  so we cannot combine with this insn.  */
1231               if (set)
1232                 return 0;
1233
1234               set = elt;
1235               break;
1236
1237             default:
1238               /* Anything else means we can't combine.  */
1239               return 0;
1240             }
1241         }
1242
1243       if (set == 0
1244           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1245              so don't do anything with it.  */
1246           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1247         return 0;
1248     }
1249   else
1250     return 0;
1251
1252   if (set == 0)
1253     return 0;
1254
1255   set = expand_field_assignment (set);
1256   src = SET_SRC (set), dest = SET_DEST (set);
1257
1258   /* Don't eliminate a store in the stack pointer.  */
1259   if (dest == stack_pointer_rtx
1260       /* Don't combine with an insn that sets a register to itself if it has
1261          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1262       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1263       /* Can't merge an ASM_OPERANDS.  */
1264       || GET_CODE (src) == ASM_OPERANDS
1265       /* Can't merge a function call.  */
1266       || GET_CODE (src) == CALL
1267       /* Don't eliminate a function call argument.  */
1268       || (CALL_P (i3)
1269           && (find_reg_fusage (i3, USE, dest)
1270               || (REG_P (dest)
1271                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1272                   && global_regs[REGNO (dest)])))
1273       /* Don't substitute into an incremented register.  */
1274       || FIND_REG_INC_NOTE (i3, dest)
1275       || (succ && FIND_REG_INC_NOTE (succ, dest))
1276       /* Don't substitute into a non-local goto, this confuses CFG.  */
1277       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1278 #if 0
1279       /* Don't combine the end of a libcall into anything.  */
1280       /* ??? This gives worse code, and appears to be unnecessary, since no
1281          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1282          use REG_RETVAL notes for noconflict blocks, but other code here
1283          makes sure that those insns don't disappear.  */
1284       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1285 #endif
1286       /* Make sure that DEST is not used after SUCC but before I3.  */
1287       || (succ && ! all_adjacent
1288           && reg_used_between_p (dest, succ, i3))
1289       /* Make sure that the value that is to be substituted for the register
1290          does not use any registers whose values alter in between.  However,
1291          If the insns are adjacent, a use can't cross a set even though we
1292          think it might (this can happen for a sequence of insns each setting
1293          the same destination; last_set of that register might point to
1294          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1295          equivalent to the memory so the substitution is valid even if there
1296          are intervening stores.  Also, don't move a volatile asm or
1297          UNSPEC_VOLATILE across any other insns.  */
1298       || (! all_adjacent
1299           && (((!MEM_P (src)
1300                 || ! find_reg_note (insn, REG_EQUIV, src))
1301                && use_crosses_set_p (src, INSN_CUID (insn)))
1302               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1303               || GET_CODE (src) == UNSPEC_VOLATILE))
1304       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1305          better register allocation by not doing the combine.  */
1306       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1307       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1308       /* Don't combine across a CALL_INSN, because that would possibly
1309          change whether the life span of some REGs crosses calls or not,
1310          and it is a pain to update that information.
1311          Exception: if source is a constant, moving it later can't hurt.
1312          Accept that special case, because it helps -fforce-addr a lot.  */
1313       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1314     return 0;
1315
1316   /* DEST must either be a REG or CC0.  */
1317   if (REG_P (dest))
1318     {
1319       /* If register alignment is being enforced for multi-word items in all
1320          cases except for parameters, it is possible to have a register copy
1321          insn referencing a hard register that is not allowed to contain the
1322          mode being copied and which would not be valid as an operand of most
1323          insns.  Eliminate this problem by not combining with such an insn.
1324
1325          Also, on some machines we don't want to extend the life of a hard
1326          register.  */
1327
1328       if (REG_P (src)
1329           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1330                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1331               /* Don't extend the life of a hard register unless it is
1332                  user variable (if we have few registers) or it can't
1333                  fit into the desired register (meaning something special
1334                  is going on).
1335                  Also avoid substituting a return register into I3, because
1336                  reload can't handle a conflict with constraints of other
1337                  inputs.  */
1338               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1339                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1340         return 0;
1341     }
1342   else if (GET_CODE (dest) != CC0)
1343     return 0;
1344
1345
1346   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1347     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1348       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1349         {
1350           /* Don't substitute for a register intended as a clobberable
1351              operand.  */
1352           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1353           if (rtx_equal_p (reg, dest))
1354             return 0;
1355
1356           /* If the clobber represents an earlyclobber operand, we must not
1357              substitute an expression containing the clobbered register.
1358              As we do not analyze the constraint strings here, we have to
1359              make the conservative assumption.  However, if the register is
1360              a fixed hard reg, the clobber cannot represent any operand;
1361              we leave it up to the machine description to either accept or
1362              reject use-and-clobber patterns.  */
1363           if (!REG_P (reg)
1364               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1365               || !fixed_regs[REGNO (reg)])
1366             if (reg_overlap_mentioned_p (reg, src))
1367               return 0;
1368         }
1369
1370   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1371      or not), reject, unless nothing volatile comes between it and I3 */
1372
1373   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1374     {
1375       /* Make sure succ doesn't contain a volatile reference.  */
1376       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1377         return 0;
1378
1379       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1380         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1381           return 0;
1382     }
1383
1384   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1385      to be an explicit register variable, and was chosen for a reason.  */
1386
1387   if (GET_CODE (src) == ASM_OPERANDS
1388       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1389     return 0;
1390
1391   /* If there are any volatile insns between INSN and I3, reject, because
1392      they might affect machine state.  */
1393
1394   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1395     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1396       return 0;
1397
1398   /* If INSN contains an autoincrement or autodecrement, make sure that
1399      register is not used between there and I3, and not already used in
1400      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1401      Also insist that I3 not be a jump; if it were one
1402      and the incremented register were spilled, we would lose.  */
1403
1404 #ifdef AUTO_INC_DEC
1405   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1406     if (REG_NOTE_KIND (link) == REG_INC
1407         && (JUMP_P (i3)
1408             || reg_used_between_p (XEXP (link, 0), insn, i3)
1409             || (pred != NULL_RTX
1410                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1411             || (succ != NULL_RTX
1412                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1413             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1414       return 0;
1415 #endif
1416
1417 #ifdef HAVE_cc0
1418   /* Don't combine an insn that follows a CC0-setting insn.
1419      An insn that uses CC0 must not be separated from the one that sets it.
1420      We do, however, allow I2 to follow a CC0-setting insn if that insn
1421      is passed as I1; in that case it will be deleted also.
1422      We also allow combining in this case if all the insns are adjacent
1423      because that would leave the two CC0 insns adjacent as well.
1424      It would be more logical to test whether CC0 occurs inside I1 or I2,
1425      but that would be much slower, and this ought to be equivalent.  */
1426
1427   p = prev_nonnote_insn (insn);
1428   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1429       && ! all_adjacent)
1430     return 0;
1431 #endif
1432
1433   /* If we get here, we have passed all the tests and the combination is
1434      to be allowed.  */
1435
1436   *pdest = dest;
1437   *psrc = src;
1438
1439   return 1;
1440 }
1441 \f
1442 /* LOC is the location within I3 that contains its pattern or the component
1443    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1444
1445    One problem is if I3 modifies its output, as opposed to replacing it
1446    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1447    so would produce an insn that is not equivalent to the original insns.
1448
1449    Consider:
1450
1451          (set (reg:DI 101) (reg:DI 100))
1452          (set (subreg:SI (reg:DI 101) 0) <foo>)
1453
1454    This is NOT equivalent to:
1455
1456          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1457                     (set (reg:DI 101) (reg:DI 100))])
1458
1459    Not only does this modify 100 (in which case it might still be valid
1460    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1461
1462    We can also run into a problem if I2 sets a register that I1
1463    uses and I1 gets directly substituted into I3 (not via I2).  In that
1464    case, we would be getting the wrong value of I2DEST into I3, so we
1465    must reject the combination.  This case occurs when I2 and I1 both
1466    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1467    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1468    of a SET must prevent combination from occurring.
1469
1470    Before doing the above check, we first try to expand a field assignment
1471    into a set of logical operations.
1472
1473    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1474    we place a register that is both set and used within I3.  If more than one
1475    such register is detected, we fail.
1476
1477    Return 1 if the combination is valid, zero otherwise.  */
1478
1479 static int
1480 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1481                   int i1_not_in_src, rtx *pi3dest_killed)
1482 {
1483   rtx x = *loc;
1484
1485   if (GET_CODE (x) == SET)
1486     {
1487       rtx set = x ;
1488       rtx dest = SET_DEST (set);
1489       rtx src = SET_SRC (set);
1490       rtx inner_dest = dest;
1491       rtx subdest;
1492
1493       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1494              || GET_CODE (inner_dest) == SUBREG
1495              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1496         inner_dest = XEXP (inner_dest, 0);
1497
1498       /* Check for the case where I3 modifies its output, as discussed
1499          above.  We don't want to prevent pseudos from being combined
1500          into the address of a MEM, so only prevent the combination if
1501          i1 or i2 set the same MEM.  */
1502       if ((inner_dest != dest &&
1503            (!MEM_P (inner_dest)
1504             || rtx_equal_p (i2dest, inner_dest)
1505             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1506            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1507                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1508
1509           /* This is the same test done in can_combine_p except we can't test
1510              all_adjacent; we don't have to, since this instruction will stay
1511              in place, thus we are not considering increasing the lifetime of
1512              INNER_DEST.
1513
1514              Also, if this insn sets a function argument, combining it with
1515              something that might need a spill could clobber a previous
1516              function argument; the all_adjacent test in can_combine_p also
1517              checks this; here, we do a more specific test for this case.  */
1518
1519           || (REG_P (inner_dest)
1520               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1521               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1522                                         GET_MODE (inner_dest))))
1523           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1524         return 0;
1525
1526       /* If DEST is used in I3, it is being killed in this insn, so
1527          record that for later.  We have to consider paradoxical
1528          subregs here, since they kill the whole register, but we
1529          ignore partial subregs, STRICT_LOW_PART, etc.
1530          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1531          STACK_POINTER_REGNUM, since these are always considered to be
1532          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1533       subdest = dest;
1534       if (GET_CODE (subdest) == SUBREG
1535           && (GET_MODE_SIZE (GET_MODE (subdest))
1536               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1537         subdest = SUBREG_REG (subdest);
1538       if (pi3dest_killed
1539           && REG_P (subdest)
1540           && reg_referenced_p (subdest, PATTERN (i3))
1541           && REGNO (subdest) != FRAME_POINTER_REGNUM
1542 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1543           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1544 #endif
1545 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1546           && (REGNO (subdest) != ARG_POINTER_REGNUM
1547               || ! fixed_regs [REGNO (subdest)])
1548 #endif
1549           && REGNO (subdest) != STACK_POINTER_REGNUM)
1550         {
1551           if (*pi3dest_killed)
1552             return 0;
1553
1554           *pi3dest_killed = subdest;
1555         }
1556     }
1557
1558   else if (GET_CODE (x) == PARALLEL)
1559     {
1560       int i;
1561
1562       for (i = 0; i < XVECLEN (x, 0); i++)
1563         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1564                                 i1_not_in_src, pi3dest_killed))
1565           return 0;
1566     }
1567
1568   return 1;
1569 }
1570 \f
1571 /* Return 1 if X is an arithmetic expression that contains a multiplication
1572    and division.  We don't count multiplications by powers of two here.  */
1573
1574 static int
1575 contains_muldiv (rtx x)
1576 {
1577   switch (GET_CODE (x))
1578     {
1579     case MOD:  case DIV:  case UMOD:  case UDIV:
1580       return 1;
1581
1582     case MULT:
1583       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1584                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1585     default:
1586       if (BINARY_P (x))
1587         return contains_muldiv (XEXP (x, 0))
1588             || contains_muldiv (XEXP (x, 1));
1589
1590       if (UNARY_P (x))
1591         return contains_muldiv (XEXP (x, 0));
1592
1593       return 0;
1594     }
1595 }
1596 \f
1597 /* Determine whether INSN can be used in a combination.  Return nonzero if
1598    not.  This is used in try_combine to detect early some cases where we
1599    can't perform combinations.  */
1600
1601 static int
1602 cant_combine_insn_p (rtx insn)
1603 {
1604   rtx set;
1605   rtx src, dest;
1606
1607   /* If this isn't really an insn, we can't do anything.
1608      This can occur when flow deletes an insn that it has merged into an
1609      auto-increment address.  */
1610   if (! INSN_P (insn))
1611     return 1;
1612
1613   /* Never combine loads and stores involving hard regs that are likely
1614      to be spilled.  The register allocator can usually handle such
1615      reg-reg moves by tying.  If we allow the combiner to make
1616      substitutions of likely-spilled regs, reload might die.
1617      As an exception, we allow combinations involving fixed regs; these are
1618      not available to the register allocator so there's no risk involved.  */
1619
1620   set = single_set (insn);
1621   if (! set)
1622     return 0;
1623   src = SET_SRC (set);
1624   dest = SET_DEST (set);
1625   if (GET_CODE (src) == SUBREG)
1626     src = SUBREG_REG (src);
1627   if (GET_CODE (dest) == SUBREG)
1628     dest = SUBREG_REG (dest);
1629   if (REG_P (src) && REG_P (dest)
1630       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1631            && ! fixed_regs[REGNO (src)]
1632            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1633           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1634               && ! fixed_regs[REGNO (dest)]
1635               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1636     return 1;
1637
1638   return 0;
1639 }
1640
1641 struct likely_spilled_retval_info
1642 {
1643   unsigned regno, nregs;
1644   unsigned mask;
1645 };
1646
1647 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1648    hard registers that are known to be written to / clobbered in full.  */
1649 static void
1650 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1651 {
1652   struct likely_spilled_retval_info *info = data;
1653   unsigned regno, nregs;
1654   unsigned new_mask;
1655
1656   if (!REG_P (XEXP (set, 0)))
1657     return;
1658   regno = REGNO (x);
1659   if (regno >= info->regno + info->nregs)
1660     return;
1661   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1662   if (regno + nregs <= info->regno)
1663     return;
1664   new_mask = (2U << (nregs - 1)) - 1;
1665   if (regno < info->regno)
1666     new_mask >>= info->regno - regno;
1667   else
1668     new_mask <<= regno - info->regno;
1669   info->mask &= ~new_mask;
1670 }
1671
1672 /* Return nonzero iff part of the return value is live during INSN, and
1673    it is likely spilled.  This can happen when more than one insn is needed
1674    to copy the return value, e.g. when we consider to combine into the
1675    second copy insn for a complex value.  */
1676
1677 static int
1678 likely_spilled_retval_p (rtx insn)
1679 {
1680   rtx use = BB_END (this_basic_block);
1681   rtx reg, p;
1682   unsigned regno, nregs;
1683   /* We assume here that no machine mode needs more than
1684      32 hard registers when the value overlaps with a register
1685      for which FUNCTION_VALUE_REGNO_P is true.  */
1686   unsigned mask;
1687   struct likely_spilled_retval_info info;
1688
1689   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1690     return 0;
1691   reg = XEXP (PATTERN (use), 0);
1692   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1693     return 0;
1694   regno = REGNO (reg);
1695   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1696   if (nregs == 1)
1697     return 0;
1698   mask = (2U << (nregs - 1)) - 1;
1699
1700   /* Disregard parts of the return value that are set later.  */
1701   info.regno = regno;
1702   info.nregs = nregs;
1703   info.mask = mask;
1704   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1705     if (INSN_P (p))
1706       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
1707   mask = info.mask;
1708
1709   /* Check if any of the (probably) live return value registers is
1710      likely spilled.  */
1711   nregs --;
1712   do
1713     {
1714       if ((mask & 1 << nregs)
1715           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1716         return 1;
1717     } while (nregs--);
1718   return 0;
1719 }
1720
1721 /* Adjust INSN after we made a change to its destination.
1722
1723    Changing the destination can invalidate notes that say something about
1724    the results of the insn and a LOG_LINK pointing to the insn.  */
1725
1726 static void
1727 adjust_for_new_dest (rtx insn)
1728 {
1729   rtx *loc;
1730
1731   /* For notes, be conservative and simply remove them.  */
1732   loc = &REG_NOTES (insn);
1733   while (*loc)
1734     {
1735       enum reg_note kind = REG_NOTE_KIND (*loc);
1736       if (kind == REG_EQUAL || kind == REG_EQUIV)
1737         *loc = XEXP (*loc, 1);
1738       else
1739         loc = &XEXP (*loc, 1);
1740     }
1741
1742   /* The new insn will have a destination that was previously the destination
1743      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1744      the next use of that destination.  */
1745   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1746 }
1747
1748 /* Return TRUE if combine can reuse reg X in mode MODE.
1749    ADDED_SETS is nonzero if the original set is still required.  */
1750 static bool
1751 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1752 {
1753   unsigned int regno;
1754
1755   if (!REG_P(x))
1756     return false;
1757
1758   regno = REGNO (x);
1759   /* Allow hard registers if the new mode is legal, and occupies no more
1760      registers than the old mode.  */
1761   if (regno < FIRST_PSEUDO_REGISTER)
1762     return (HARD_REGNO_MODE_OK (regno, mode)
1763             && (hard_regno_nregs[regno][GET_MODE (x)]
1764                 >= hard_regno_nregs[regno][mode]));
1765
1766   /* Or a pseudo that is only used once.  */
1767   return (REG_N_SETS (regno) == 1 && !added_sets
1768           && !REG_USERVAR_P (x));
1769 }
1770
1771
1772 /* Check whether X, the destination of a set, refers to part of
1773    the register specified by REG.  */
1774
1775 static bool
1776 reg_subword_p (rtx x, rtx reg)
1777 {
1778   /* Check that reg is an integer mode register.  */
1779   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1780     return false;
1781
1782   if (GET_CODE (x) == STRICT_LOW_PART
1783       || GET_CODE (x) == ZERO_EXTRACT)
1784     x = XEXP (x, 0);
1785
1786   return GET_CODE (x) == SUBREG
1787          && SUBREG_REG (x) == reg
1788          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1789 }
1790
1791
1792 /* Try to combine the insns I1 and I2 into I3.
1793    Here I1 and I2 appear earlier than I3.
1794    I1 can be zero; then we combine just I2 into I3.
1795
1796    If we are combining three insns and the resulting insn is not recognized,
1797    try splitting it into two insns.  If that happens, I2 and I3 are retained
1798    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1799    are pseudo-deleted.
1800
1801    Return 0 if the combination does not work.  Then nothing is changed.
1802    If we did the combination, return the insn at which combine should
1803    resume scanning.
1804
1805    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1806    new direct jump instruction.  */
1807
1808 static rtx
1809 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1810 {
1811   /* New patterns for I3 and I2, respectively.  */
1812   rtx newpat, newi2pat = 0;
1813   rtvec newpat_vec_with_clobbers = 0;
1814   int substed_i2 = 0, substed_i1 = 0;
1815   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1816   int added_sets_1, added_sets_2;
1817   /* Total number of SETs to put into I3.  */
1818   int total_sets;
1819   /* Nonzero if I2's body now appears in I3.  */
1820   int i2_is_used;
1821   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1822   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1823   /* Contains I3 if the destination of I3 is used in its source, which means
1824      that the old life of I3 is being killed.  If that usage is placed into
1825      I2 and not in I3, a REG_DEAD note must be made.  */
1826   rtx i3dest_killed = 0;
1827   /* SET_DEST and SET_SRC of I2 and I1.  */
1828   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1829   /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases.  */
1830   rtx i1pat = 0, i2pat = 0;
1831   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1832   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1833   int i2dest_killed = 0, i1dest_killed = 0;
1834   int i1_feeds_i3 = 0;
1835   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1836   rtx new_i3_notes, new_i2_notes;
1837   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1838   int i3_subst_into_i2 = 0;
1839   /* Notes that I1, I2 or I3 is a MULT operation.  */
1840   int have_mult = 0;
1841   int swap_i2i3 = 0;
1842
1843   int maxreg;
1844   rtx temp;
1845   rtx link;
1846   int i;
1847
1848   /* Exit early if one of the insns involved can't be used for
1849      combinations.  */
1850   if (cant_combine_insn_p (i3)
1851       || cant_combine_insn_p (i2)
1852       || (i1 && cant_combine_insn_p (i1))
1853       || likely_spilled_retval_p (i3)
1854       /* We also can't do anything if I3 has a
1855          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1856          libcall.  */
1857 #if 0
1858       /* ??? This gives worse code, and appears to be unnecessary, since no
1859          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1860       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1861 #endif
1862       )
1863     return 0;
1864
1865   combine_attempts++;
1866   undobuf.other_insn = 0;
1867
1868   /* Reset the hard register usage information.  */
1869   CLEAR_HARD_REG_SET (newpat_used_regs);
1870
1871   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1872      code below, set I1 to be the earlier of the two insns.  */
1873   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1874     temp = i1, i1 = i2, i2 = temp;
1875
1876   added_links_insn = 0;
1877
1878   /* First check for one important special-case that the code below will
1879      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1880      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1881      we may be able to replace that destination with the destination of I3.
1882      This occurs in the common code where we compute both a quotient and
1883      remainder into a structure, in which case we want to do the computation
1884      directly into the structure to avoid register-register copies.
1885
1886      Note that this case handles both multiple sets in I2 and also
1887      cases where I2 has a number of CLOBBER or PARALLELs.
1888
1889      We make very conservative checks below and only try to handle the
1890      most common cases of this.  For example, we only handle the case
1891      where I2 and I3 are adjacent to avoid making difficult register
1892      usage tests.  */
1893
1894   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1895       && REG_P (SET_SRC (PATTERN (i3)))
1896       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1897       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1898       && GET_CODE (PATTERN (i2)) == PARALLEL
1899       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1900       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1901          below would need to check what is inside (and reg_overlap_mentioned_p
1902          doesn't support those codes anyway).  Don't allow those destinations;
1903          the resulting insn isn't likely to be recognized anyway.  */
1904       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1905       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1906       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1907                                     SET_DEST (PATTERN (i3)))
1908       && next_real_insn (i2) == i3)
1909     {
1910       rtx p2 = PATTERN (i2);
1911
1912       /* Make sure that the destination of I3,
1913          which we are going to substitute into one output of I2,
1914          is not used within another output of I2.  We must avoid making this:
1915          (parallel [(set (mem (reg 69)) ...)
1916                     (set (reg 69) ...)])
1917          which is not well-defined as to order of actions.
1918          (Besides, reload can't handle output reloads for this.)
1919
1920          The problem can also happen if the dest of I3 is a memory ref,
1921          if another dest in I2 is an indirect memory ref.  */
1922       for (i = 0; i < XVECLEN (p2, 0); i++)
1923         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1924              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1925             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1926                                         SET_DEST (XVECEXP (p2, 0, i))))
1927           break;
1928
1929       if (i == XVECLEN (p2, 0))
1930         for (i = 0; i < XVECLEN (p2, 0); i++)
1931           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1932                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1933               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1934             {
1935               combine_merges++;
1936
1937               subst_insn = i3;
1938               subst_low_cuid = INSN_CUID (i2);
1939
1940               added_sets_2 = added_sets_1 = 0;
1941               i2dest = SET_SRC (PATTERN (i3));
1942               i2dest_killed = dead_or_set_p (i2, i2dest);
1943
1944               /* Replace the dest in I2 with our dest and make the resulting
1945                  insn the new pattern for I3.  Then skip to where we
1946                  validate the pattern.  Everything was set up above.  */
1947               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1948                      SET_DEST (PATTERN (i3)));
1949
1950               newpat = p2;
1951               i3_subst_into_i2 = 1;
1952               goto validate_replacement;
1953             }
1954     }
1955
1956   /* If I2 is setting a pseudo to a constant and I3 is setting some
1957      sub-part of it to another constant, merge them by making a new
1958      constant.  */
1959   if (i1 == 0
1960       && (temp = single_set (i2)) != 0
1961       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1962           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1963       && GET_CODE (PATTERN (i3)) == SET
1964       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1965           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1966       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1967     {
1968       rtx dest = SET_DEST (PATTERN (i3));
1969       int offset = -1;
1970       int width = 0;
1971
1972       if (GET_CODE (dest) == ZERO_EXTRACT)
1973         {
1974           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1975               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1976             {
1977               width = INTVAL (XEXP (dest, 1));
1978               offset = INTVAL (XEXP (dest, 2));
1979               dest = XEXP (dest, 0);
1980               if (BITS_BIG_ENDIAN)
1981                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1982             }
1983         }
1984       else
1985         {
1986           if (GET_CODE (dest) == STRICT_LOW_PART)
1987             dest = XEXP (dest, 0);
1988           width = GET_MODE_BITSIZE (GET_MODE (dest));
1989           offset = 0;
1990         }
1991
1992       if (offset >= 0)
1993         {
1994           /* If this is the low part, we're done.  */
1995           if (subreg_lowpart_p (dest))
1996             ;
1997           /* Handle the case where inner is twice the size of outer.  */
1998           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1999                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2000             offset += GET_MODE_BITSIZE (GET_MODE (dest));
2001           /* Otherwise give up for now.  */
2002           else
2003             offset = -1;
2004         }
2005
2006       if (offset >= 0
2007           && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2008               <= HOST_BITS_PER_WIDE_INT * 2))
2009         {
2010           HOST_WIDE_INT mhi, ohi, ihi;
2011           HOST_WIDE_INT mlo, olo, ilo;
2012           rtx inner = SET_SRC (PATTERN (i3));
2013           rtx outer = SET_SRC (temp);
2014
2015           if (GET_CODE (outer) == CONST_INT)
2016             {
2017               olo = INTVAL (outer);
2018               ohi = olo < 0 ? -1 : 0;
2019             }
2020           else
2021             {
2022               olo = CONST_DOUBLE_LOW (outer);
2023               ohi = CONST_DOUBLE_HIGH (outer);
2024             }
2025
2026           if (GET_CODE (inner) == CONST_INT)
2027             {
2028               ilo = INTVAL (inner);
2029               ihi = ilo < 0 ? -1 : 0;
2030             }
2031           else
2032             {
2033               ilo = CONST_DOUBLE_LOW (inner);
2034               ihi = CONST_DOUBLE_HIGH (inner);
2035             }
2036
2037           if (width < HOST_BITS_PER_WIDE_INT)
2038             {
2039               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2040               mhi = 0;
2041             }
2042           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2043             {
2044               mhi = ((unsigned HOST_WIDE_INT) 1
2045                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2046               mlo = -1;
2047             }
2048           else
2049             {
2050               mlo = -1;
2051               mhi = -1;
2052             }
2053
2054           ilo &= mlo;
2055           ihi &= mhi;
2056
2057           if (offset >= HOST_BITS_PER_WIDE_INT)
2058             {
2059               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2060               mlo = 0;
2061               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2062               ilo = 0;
2063             }
2064           else if (offset > 0)
2065             {
2066               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2067                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2068               mlo = mlo << offset;
2069               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2070                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2071               ilo = ilo << offset;
2072             }
2073
2074           olo = (olo & ~mlo) | ilo;
2075           ohi = (ohi & ~mhi) | ihi;
2076
2077           combine_merges++;
2078           subst_insn = i3;
2079           subst_low_cuid = INSN_CUID (i2);
2080           added_sets_2 = added_sets_1 = 0;
2081           i2dest = SET_DEST (temp);
2082           i2dest_killed = dead_or_set_p (i2, i2dest);
2083
2084           SUBST (SET_SRC (temp),
2085                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2086
2087           newpat = PATTERN (i2);
2088           goto validate_replacement;
2089         }
2090     }
2091
2092 #ifndef HAVE_cc0
2093   /* If we have no I1 and I2 looks like:
2094         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2095                    (set Y OP)])
2096      make up a dummy I1 that is
2097         (set Y OP)
2098      and change I2 to be
2099         (set (reg:CC X) (compare:CC Y (const_int 0)))
2100
2101      (We can ignore any trailing CLOBBERs.)
2102
2103      This undoes a previous combination and allows us to match a branch-and-
2104      decrement insn.  */
2105
2106   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2107       && XVECLEN (PATTERN (i2), 0) >= 2
2108       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2109       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2110           == MODE_CC)
2111       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2112       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2113       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2114       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2115       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2116                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2117     {
2118       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2119         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2120           break;
2121
2122       if (i == 1)
2123         {
2124           /* We make I1 with the same INSN_UID as I2.  This gives it
2125              the same INSN_CUID for value tracking.  Our fake I1 will
2126              never appear in the insn stream so giving it the same INSN_UID
2127              as I2 will not cause a problem.  */
2128
2129           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2130                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2131                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2132                              NULL_RTX);
2133
2134           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2135           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2136                  SET_DEST (PATTERN (i1)));
2137         }
2138     }
2139 #endif
2140
2141   /* Verify that I2 and I1 are valid for combining.  */
2142   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2143       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2144     {
2145       undo_all ();
2146       return 0;
2147     }
2148
2149   /* Record whether I2DEST is used in I2SRC and similarly for the other
2150      cases.  Knowing this will help in register status updating below.  */
2151   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2152   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2153   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2154   i2dest_killed = dead_or_set_p (i2, i2dest);
2155   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2156
2157   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2158      in I2SRC.  */
2159   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2160
2161   /* Ensure that I3's pattern can be the destination of combines.  */
2162   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2163                           i1 && i2dest_in_i1src && i1_feeds_i3,
2164                           &i3dest_killed))
2165     {
2166       undo_all ();
2167       return 0;
2168     }
2169
2170   /* See if any of the insns is a MULT operation.  Unless one is, we will
2171      reject a combination that is, since it must be slower.  Be conservative
2172      here.  */
2173   if (GET_CODE (i2src) == MULT
2174       || (i1 != 0 && GET_CODE (i1src) == MULT)
2175       || (GET_CODE (PATTERN (i3)) == SET
2176           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2177     have_mult = 1;
2178
2179   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2180      We used to do this EXCEPT in one case: I3 has a post-inc in an
2181      output operand.  However, that exception can give rise to insns like
2182         mov r3,(r3)+
2183      which is a famous insn on the PDP-11 where the value of r3 used as the
2184      source was model-dependent.  Avoid this sort of thing.  */
2185
2186 #if 0
2187   if (!(GET_CODE (PATTERN (i3)) == SET
2188         && REG_P (SET_SRC (PATTERN (i3)))
2189         && MEM_P (SET_DEST (PATTERN (i3)))
2190         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2191             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2192     /* It's not the exception.  */
2193 #endif
2194 #ifdef AUTO_INC_DEC
2195     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2196       if (REG_NOTE_KIND (link) == REG_INC
2197           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2198               || (i1 != 0
2199                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2200         {
2201           undo_all ();
2202           return 0;
2203         }
2204 #endif
2205
2206   /* See if the SETs in I1 or I2 need to be kept around in the merged
2207      instruction: whenever the value set there is still needed past I3.
2208      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2209
2210      For the SET in I1, we have two cases:  If I1 and I2 independently
2211      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2212      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2213      in I1 needs to be kept around unless I1DEST dies or is set in either
2214      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2215      I1DEST.  If so, we know I1 feeds into I2.  */
2216
2217   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2218
2219   added_sets_1
2220     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2221                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2222
2223   /* If the set in I2 needs to be kept around, we must make a copy of
2224      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2225      PATTERN (I2), we are only substituting for the original I1DEST, not into
2226      an already-substituted copy.  This also prevents making self-referential
2227      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2228      I2DEST.  */
2229
2230   if (added_sets_2)
2231     {
2232       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2233         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2234       else
2235         i2pat = copy_rtx (PATTERN (i2));
2236     }
2237
2238   if (added_sets_1)
2239     {
2240       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2241         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2242       else
2243         i1pat = copy_rtx (PATTERN (i1));
2244     }
2245
2246   combine_merges++;
2247
2248   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2249
2250   maxreg = max_reg_num ();
2251
2252   subst_insn = i3;
2253
2254 #ifndef HAVE_cc0
2255   /* Many machines that don't use CC0 have insns that can both perform an
2256      arithmetic operation and set the condition code.  These operations will
2257      be represented as a PARALLEL with the first element of the vector
2258      being a COMPARE of an arithmetic operation with the constant zero.
2259      The second element of the vector will set some pseudo to the result
2260      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2261      match such a pattern and so will generate an extra insn.   Here we test
2262      for this case, where both the comparison and the operation result are
2263      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2264      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2265
2266   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2267       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2268       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2269       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2270     {
2271 #ifdef SELECT_CC_MODE
2272       rtx *cc_use;
2273       enum machine_mode compare_mode;
2274 #endif
2275
2276       newpat = PATTERN (i3);
2277       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2278
2279       i2_is_used = 1;
2280
2281 #ifdef SELECT_CC_MODE
2282       /* See if a COMPARE with the operand we substituted in should be done
2283          with the mode that is currently being used.  If not, do the same
2284          processing we do in `subst' for a SET; namely, if the destination
2285          is used only once, try to replace it with a register of the proper
2286          mode and also replace the COMPARE.  */
2287       if (undobuf.other_insn == 0
2288           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2289                                         &undobuf.other_insn))
2290           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2291                                               i2src, const0_rtx))
2292               != GET_MODE (SET_DEST (newpat))))
2293         {
2294           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2295                                    compare_mode))
2296             {
2297               unsigned int regno = REGNO (SET_DEST (newpat));
2298               rtx new_dest;
2299
2300               if (regno < FIRST_PSEUDO_REGISTER)
2301                 new_dest = gen_rtx_REG (compare_mode, regno);
2302               else
2303                 {
2304                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2305                   new_dest = regno_reg_rtx[regno];
2306                 }
2307
2308               SUBST (SET_DEST (newpat), new_dest);
2309               SUBST (XEXP (*cc_use, 0), new_dest);
2310               SUBST (SET_SRC (newpat),
2311                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2312             }
2313           else
2314             undobuf.other_insn = 0;
2315         }
2316 #endif
2317     }
2318   else
2319 #endif
2320     {
2321       /* It is possible that the source of I2 or I1 may be performing
2322          an unneeded operation, such as a ZERO_EXTEND of something
2323          that is known to have the high part zero.  Handle that case
2324          by letting subst look at the innermost one of them.
2325
2326          Another way to do this would be to have a function that tries
2327          to simplify a single insn instead of merging two or more
2328          insns.  We don't do this because of the potential of infinite
2329          loops and because of the potential extra memory required.
2330          However, doing it the way we are is a bit of a kludge and
2331          doesn't catch all cases.
2332
2333          But only do this if -fexpensive-optimizations since it slows
2334          things down and doesn't usually win.
2335
2336          This is not done in the COMPARE case above because the
2337          unmodified I2PAT is used in the PARALLEL and so a pattern
2338          with a modified I2SRC would not match.  */
2339
2340       if (flag_expensive_optimizations)
2341         {
2342           /* Pass pc_rtx so no substitutions are done, just
2343              simplifications.  */
2344           if (i1)
2345             {
2346               subst_low_cuid = INSN_CUID (i1);
2347               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2348             }
2349           else
2350             {
2351               subst_low_cuid = INSN_CUID (i2);
2352               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2353             }
2354         }
2355
2356       n_occurrences = 0;                /* `subst' counts here */
2357
2358       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2359          need to make a unique copy of I2SRC each time we substitute it
2360          to avoid self-referential rtl.  */
2361
2362       subst_low_cuid = INSN_CUID (i2);
2363       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2364                       ! i1_feeds_i3 && i1dest_in_i1src);
2365       substed_i2 = 1;
2366
2367       /* Record whether i2's body now appears within i3's body.  */
2368       i2_is_used = n_occurrences;
2369     }
2370
2371   /* If we already got a failure, don't try to do more.  Otherwise,
2372      try to substitute in I1 if we have it.  */
2373
2374   if (i1 && GET_CODE (newpat) != CLOBBER)
2375     {
2376       /* Before we can do this substitution, we must redo the test done
2377          above (see detailed comments there) that ensures  that I1DEST
2378          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2379
2380       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2381                               0, (rtx*) 0))
2382         {
2383           undo_all ();
2384           return 0;
2385         }
2386
2387       n_occurrences = 0;
2388       subst_low_cuid = INSN_CUID (i1);
2389       newpat = subst (newpat, i1dest, i1src, 0, 0);
2390       substed_i1 = 1;
2391     }
2392
2393   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2394      to count all the ways that I2SRC and I1SRC can be used.  */
2395   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2396        && i2_is_used + added_sets_2 > 1)
2397       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2398           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2399               > 1))
2400       /* Fail if we tried to make a new register.  */
2401       || max_reg_num () != maxreg
2402       /* Fail if we couldn't do something and have a CLOBBER.  */
2403       || GET_CODE (newpat) == CLOBBER
2404       /* Fail if this new pattern is a MULT and we didn't have one before
2405          at the outer level.  */
2406       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2407           && ! have_mult))
2408     {
2409       undo_all ();
2410       return 0;
2411     }
2412
2413   /* If the actions of the earlier insns must be kept
2414      in addition to substituting them into the latest one,
2415      we must make a new PARALLEL for the latest insn
2416      to hold additional the SETs.  */
2417
2418   if (added_sets_1 || added_sets_2)
2419     {
2420       combine_extras++;
2421
2422       if (GET_CODE (newpat) == PARALLEL)
2423         {
2424           rtvec old = XVEC (newpat, 0);
2425           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2426           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2427           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2428                   sizeof (old->elem[0]) * old->num_elem);
2429         }
2430       else
2431         {
2432           rtx old = newpat;
2433           total_sets = 1 + added_sets_1 + added_sets_2;
2434           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2435           XVECEXP (newpat, 0, 0) = old;
2436         }
2437
2438       if (added_sets_1)
2439         XVECEXP (newpat, 0, --total_sets) = i1pat;
2440
2441       if (added_sets_2)
2442         {
2443           /* If there is no I1, use I2's body as is.  We used to also not do
2444              the subst call below if I2 was substituted into I3,
2445              but that could lose a simplification.  */
2446           if (i1 == 0)
2447             XVECEXP (newpat, 0, --total_sets) = i2pat;
2448           else
2449             /* See comment where i2pat is assigned.  */
2450             XVECEXP (newpat, 0, --total_sets)
2451               = subst (i2pat, i1dest, i1src, 0, 0);
2452         }
2453     }
2454
2455   /* We come here when we are replacing a destination in I2 with the
2456      destination of I3.  */
2457  validate_replacement:
2458
2459   /* Note which hard regs this insn has as inputs.  */
2460   mark_used_regs_combine (newpat);
2461
2462   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2463      consider splitting this pattern, we might need these clobbers.  */
2464   if (i1 && GET_CODE (newpat) == PARALLEL
2465       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2466     {
2467       int len = XVECLEN (newpat, 0);
2468
2469       newpat_vec_with_clobbers = rtvec_alloc (len);
2470       for (i = 0; i < len; i++)
2471         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2472     }
2473
2474   /* Is the result of combination a valid instruction?  */
2475   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2476
2477   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2478      the second SET's destination is a register that is unused and isn't
2479      marked as an instruction that might trap in an EH region.  In that case,
2480      we just need the first SET.   This can occur when simplifying a divmod
2481      insn.  We *must* test for this case here because the code below that
2482      splits two independent SETs doesn't handle this case correctly when it
2483      updates the register status.
2484
2485      It's pointless doing this if we originally had two sets, one from
2486      i3, and one from i2.  Combining then splitting the parallel results
2487      in the original i2 again plus an invalid insn (which we delete).
2488      The net effect is only to move instructions around, which makes
2489      debug info less accurate.
2490
2491      Also check the case where the first SET's destination is unused.
2492      That would not cause incorrect code, but does cause an unneeded
2493      insn to remain.  */
2494
2495   if (insn_code_number < 0
2496       && !(added_sets_2 && i1 == 0)
2497       && GET_CODE (newpat) == PARALLEL
2498       && XVECLEN (newpat, 0) == 2
2499       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2500       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2501       && asm_noperands (newpat) < 0)
2502     {
2503       rtx set0 = XVECEXP (newpat, 0, 0);
2504       rtx set1 = XVECEXP (newpat, 0, 1);
2505       rtx note;
2506
2507       if (((REG_P (SET_DEST (set1))
2508             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2509            || (GET_CODE (SET_DEST (set1)) == SUBREG
2510                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2511           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2512               || INTVAL (XEXP (note, 0)) <= 0)
2513           && ! side_effects_p (SET_SRC (set1)))
2514         {
2515           newpat = set0;
2516           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2517         }
2518
2519       else if (((REG_P (SET_DEST (set0))
2520                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2521                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2522                     && find_reg_note (i3, REG_UNUSED,
2523                                       SUBREG_REG (SET_DEST (set0)))))
2524                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2525                    || INTVAL (XEXP (note, 0)) <= 0)
2526                && ! side_effects_p (SET_SRC (set0)))
2527         {
2528           newpat = set1;
2529           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2530
2531           if (insn_code_number >= 0)
2532             {
2533               /* If we will be able to accept this, we have made a
2534                  change to the destination of I3.  This requires us to
2535                  do a few adjustments.  */
2536
2537               PATTERN (i3) = newpat;
2538               adjust_for_new_dest (i3);
2539             }
2540         }
2541     }
2542
2543   /* If we were combining three insns and the result is a simple SET
2544      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2545      insns.  There are two ways to do this.  It can be split using a
2546      machine-specific method (like when you have an addition of a large
2547      constant) or by combine in the function find_split_point.  */
2548
2549   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2550       && asm_noperands (newpat) < 0)
2551     {
2552       rtx m_split, *split;
2553
2554       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2555          use I2DEST as a scratch register will help.  In the latter case,
2556          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2557
2558       m_split = split_insns (newpat, i3);
2559
2560       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2561          inputs of NEWPAT.  */
2562
2563       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2564          possible to try that as a scratch reg.  This would require adding
2565          more code to make it work though.  */
2566
2567       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2568         {
2569           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2570
2571           /* First try to split using the original register as a
2572              scratch register.  */
2573           m_split = split_insns (gen_rtx_PARALLEL
2574                                  (VOIDmode,
2575                                   gen_rtvec (2, newpat,
2576                                              gen_rtx_CLOBBER (VOIDmode,
2577                                                               i2dest))),
2578                                  i3);
2579
2580           /* If that didn't work, try changing the mode of I2DEST if
2581              we can.  */
2582           if (m_split == 0
2583               && new_mode != GET_MODE (i2dest)
2584               && new_mode != VOIDmode
2585               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2586             {
2587               enum machine_mode old_mode = GET_MODE (i2dest);
2588               rtx ni2dest;
2589
2590               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2591                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2592               else
2593                 {
2594                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2595                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2596                 }
2597
2598               m_split = split_insns (gen_rtx_PARALLEL
2599                                      (VOIDmode,
2600                                       gen_rtvec (2, newpat,
2601                                                  gen_rtx_CLOBBER (VOIDmode,
2602                                                                   ni2dest))),
2603                                      i3);
2604
2605               if (m_split == 0
2606                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2607                 {
2608                   struct undo *buf;
2609
2610                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2611                   buf = undobuf.undos;
2612                   undobuf.undos = buf->next;
2613                   buf->next = undobuf.frees;
2614                   undobuf.frees = buf;
2615                 }
2616             }
2617         }
2618
2619       /* If recog_for_combine has discarded clobbers, try to use them
2620          again for the split.  */
2621       if (m_split == 0 && newpat_vec_with_clobbers)
2622         m_split
2623           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2624                                            newpat_vec_with_clobbers), i3);
2625
2626       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2627         {
2628           m_split = PATTERN (m_split);
2629           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2630           if (insn_code_number >= 0)
2631             newpat = m_split;
2632         }
2633       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2634                && (next_real_insn (i2) == i3
2635                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2636         {
2637           rtx i2set, i3set;
2638           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2639           newi2pat = PATTERN (m_split);
2640
2641           i3set = single_set (NEXT_INSN (m_split));
2642           i2set = single_set (m_split);
2643
2644           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2645
2646           /* If I2 or I3 has multiple SETs, we won't know how to track
2647              register status, so don't use these insns.  If I2's destination
2648              is used between I2 and I3, we also can't use these insns.  */
2649
2650           if (i2_code_number >= 0 && i2set && i3set
2651               && (next_real_insn (i2) == i3
2652                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2653             insn_code_number = recog_for_combine (&newi3pat, i3,
2654                                                   &new_i3_notes);
2655           if (insn_code_number >= 0)
2656             newpat = newi3pat;
2657
2658           /* It is possible that both insns now set the destination of I3.
2659              If so, we must show an extra use of it.  */
2660
2661           if (insn_code_number >= 0)
2662             {
2663               rtx new_i3_dest = SET_DEST (i3set);
2664               rtx new_i2_dest = SET_DEST (i2set);
2665
2666               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2667                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2668                      || GET_CODE (new_i3_dest) == SUBREG)
2669                 new_i3_dest = XEXP (new_i3_dest, 0);
2670
2671               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2672                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2673                      || GET_CODE (new_i2_dest) == SUBREG)
2674                 new_i2_dest = XEXP (new_i2_dest, 0);
2675
2676               if (REG_P (new_i3_dest)
2677                   && REG_P (new_i2_dest)
2678                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2679                 REG_N_SETS (REGNO (new_i2_dest))++;
2680             }
2681         }
2682
2683       /* If we can split it and use I2DEST, go ahead and see if that
2684          helps things be recognized.  Verify that none of the registers
2685          are set between I2 and I3.  */
2686       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2687 #ifdef HAVE_cc0
2688           && REG_P (i2dest)
2689 #endif
2690           /* We need I2DEST in the proper mode.  If it is a hard register
2691              or the only use of a pseudo, we can change its mode.
2692              Make sure we don't change a hard register to have a mode that
2693              isn't valid for it, or change the number of registers.  */
2694           && (GET_MODE (*split) == GET_MODE (i2dest)
2695               || GET_MODE (*split) == VOIDmode
2696               || can_change_dest_mode (i2dest, added_sets_2,
2697                                        GET_MODE (*split)))
2698           && (next_real_insn (i2) == i3
2699               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2700           /* We can't overwrite I2DEST if its value is still used by
2701              NEWPAT.  */
2702           && ! reg_referenced_p (i2dest, newpat))
2703         {
2704           rtx newdest = i2dest;
2705           enum rtx_code split_code = GET_CODE (*split);
2706           enum machine_mode split_mode = GET_MODE (*split);
2707           bool subst_done = false;
2708           newi2pat = NULL_RTX;
2709
2710           /* Get NEWDEST as a register in the proper mode.  We have already
2711              validated that we can do this.  */
2712           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2713             {
2714               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2715                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2716               else
2717                 {
2718                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2719                   newdest = regno_reg_rtx[REGNO (i2dest)];
2720                 }
2721             }
2722
2723           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2724              an ASHIFT.  This can occur if it was inside a PLUS and hence
2725              appeared to be a memory address.  This is a kludge.  */
2726           if (split_code == MULT
2727               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2728               && INTVAL (XEXP (*split, 1)) > 0
2729               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2730             {
2731               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2732                                              XEXP (*split, 0), GEN_INT (i)));
2733               /* Update split_code because we may not have a multiply
2734                  anymore.  */
2735               split_code = GET_CODE (*split);
2736             }
2737
2738 #ifdef INSN_SCHEDULING
2739           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2740              be written as a ZERO_EXTEND.  */
2741           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2742             {
2743 #ifdef LOAD_EXTEND_OP
2744               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2745                  what it really is.  */
2746               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2747                   == SIGN_EXTEND)
2748                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2749                                                     SUBREG_REG (*split)));
2750               else
2751 #endif
2752                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2753                                                     SUBREG_REG (*split)));
2754             }
2755 #endif
2756
2757           /* Attempt to split binary operators using arithmetic identities.  */
2758           if (BINARY_P (SET_SRC (newpat))
2759               && split_mode == GET_MODE (SET_SRC (newpat))
2760               && ! side_effects_p (SET_SRC (newpat)))
2761             {
2762               rtx setsrc = SET_SRC (newpat);
2763               enum machine_mode mode = GET_MODE (setsrc);
2764               enum rtx_code code = GET_CODE (setsrc);
2765               rtx src_op0 = XEXP (setsrc, 0);
2766               rtx src_op1 = XEXP (setsrc, 1);
2767
2768               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2769               if (rtx_equal_p (src_op0, src_op1))
2770                 {
2771                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2772                   SUBST (XEXP (setsrc, 0), newdest);
2773                   SUBST (XEXP (setsrc, 1), newdest);
2774                   subst_done = true;
2775                 }
2776               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2777               else if ((code == PLUS || code == MULT)
2778                        && GET_CODE (src_op0) == code
2779                        && GET_CODE (XEXP (src_op0, 0)) == code
2780                        && (INTEGRAL_MODE_P (mode)
2781                            || (FLOAT_MODE_P (mode)
2782                                && flag_unsafe_math_optimizations)))
2783                 {
2784                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2785                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2786                   rtx r = XEXP (src_op0, 1);
2787                   rtx s = src_op1;
2788
2789                   /* Split both "((X op Y) op X) op Y" and
2790                      "((X op Y) op Y) op X" as "T op T" where T is
2791                      "X op Y".  */
2792                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2793                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2794                     {
2795                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2796                                               XEXP (src_op0, 0));
2797                       SUBST (XEXP (setsrc, 0), newdest);
2798                       SUBST (XEXP (setsrc, 1), newdest);
2799                       subst_done = true;
2800                     }
2801                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2802                      T is "X op Y".  */
2803                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2804                     {
2805                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2806                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2807                       SUBST (XEXP (setsrc, 0), newdest);
2808                       SUBST (XEXP (setsrc, 1), newdest);
2809                       subst_done = true;
2810                     }
2811                 }
2812             }
2813
2814           if (!subst_done)
2815             {
2816               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2817               SUBST (*split, newdest);
2818             }
2819
2820           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2821
2822           /* recog_for_combine might have added CLOBBERs to newi2pat.
2823              Make sure NEWPAT does not depend on the clobbered regs.  */
2824           if (GET_CODE (newi2pat) == PARALLEL)
2825             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2826               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2827                 {
2828                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2829                   if (reg_overlap_mentioned_p (reg, newpat))
2830                     {
2831                       undo_all ();
2832                       return 0;
2833                     }
2834                 }
2835
2836           /* If the split point was a MULT and we didn't have one before,
2837              don't use one now.  */
2838           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2839             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2840         }
2841     }
2842
2843   /* Check for a case where we loaded from memory in a narrow mode and
2844      then sign extended it, but we need both registers.  In that case,
2845      we have a PARALLEL with both loads from the same memory location.
2846      We can split this into a load from memory followed by a register-register
2847      copy.  This saves at least one insn, more if register allocation can
2848      eliminate the copy.
2849
2850      We cannot do this if the destination of the first assignment is a
2851      condition code register or cc0.  We eliminate this case by making sure
2852      the SET_DEST and SET_SRC have the same mode.
2853
2854      We cannot do this if the destination of the second assignment is
2855      a register that we have already assumed is zero-extended.  Similarly
2856      for a SUBREG of such a register.  */
2857
2858   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2859            && GET_CODE (newpat) == PARALLEL
2860            && XVECLEN (newpat, 0) == 2
2861            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2862            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2863            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2864                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2865            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2866            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2867                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2868            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2869                                    INSN_CUID (i2))
2870            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2871            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2872            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2873                  (REG_P (temp)
2874                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2875                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2876                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2877                   && (reg_stat[REGNO (temp)].nonzero_bits
2878                       != GET_MODE_MASK (word_mode))))
2879            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2880                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2881                      (REG_P (temp)
2882                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2883                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2884                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2885                       && (reg_stat[REGNO (temp)].nonzero_bits
2886                           != GET_MODE_MASK (word_mode)))))
2887            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2888                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2889            && ! find_reg_note (i3, REG_UNUSED,
2890                                SET_DEST (XVECEXP (newpat, 0, 0))))
2891     {
2892       rtx ni2dest;
2893
2894       newi2pat = XVECEXP (newpat, 0, 0);
2895       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2896       newpat = XVECEXP (newpat, 0, 1);
2897       SUBST (SET_SRC (newpat),
2898              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2899       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2900
2901       if (i2_code_number >= 0)
2902         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2903
2904       if (insn_code_number >= 0)
2905         swap_i2i3 = 1;
2906     }
2907
2908   /* Similarly, check for a case where we have a PARALLEL of two independent
2909      SETs but we started with three insns.  In this case, we can do the sets
2910      as two separate insns.  This case occurs when some SET allows two
2911      other insns to combine, but the destination of that SET is still live.  */
2912
2913   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2914            && GET_CODE (newpat) == PARALLEL
2915            && XVECLEN (newpat, 0) == 2
2916            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2917            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2918            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2919            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2920            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2921            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2922            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2923                                    INSN_CUID (i2))
2924            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2925                                   XVECEXP (newpat, 0, 0))
2926            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2927                                   XVECEXP (newpat, 0, 1))
2928            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2929                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
2930 #ifdef HAVE_cc0
2931            /* We cannot split the parallel into two sets if both sets
2932               reference cc0.  */
2933            && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
2934                  && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
2935 #endif
2936            )
2937     {
2938       /* Normally, it doesn't matter which of the two is done first,
2939          but it does if one references cc0.  In that case, it has to
2940          be first.  */
2941 #ifdef HAVE_cc0
2942       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2943         {
2944           newi2pat = XVECEXP (newpat, 0, 0);
2945           newpat = XVECEXP (newpat, 0, 1);
2946         }
2947       else
2948 #endif
2949         {
2950           newi2pat = XVECEXP (newpat, 0, 1);
2951           newpat = XVECEXP (newpat, 0, 0);
2952         }
2953
2954       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2955
2956       if (i2_code_number >= 0)
2957         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2958     }
2959
2960   /* If it still isn't recognized, fail and change things back the way they
2961      were.  */
2962   if ((insn_code_number < 0
2963        /* Is the result a reasonable ASM_OPERANDS?  */
2964        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2965     {
2966       undo_all ();
2967       return 0;
2968     }
2969
2970   /* If we had to change another insn, make sure it is valid also.  */
2971   if (undobuf.other_insn)
2972     {
2973       rtx other_pat = PATTERN (undobuf.other_insn);
2974       rtx new_other_notes;
2975       rtx note, next;
2976
2977       CLEAR_HARD_REG_SET (newpat_used_regs);
2978
2979       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2980                                              &new_other_notes);
2981
2982       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2983         {
2984           undo_all ();
2985           return 0;
2986         }
2987
2988       PATTERN (undobuf.other_insn) = other_pat;
2989
2990       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2991          are still valid.  Then add any non-duplicate notes added by
2992          recog_for_combine.  */
2993       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2994         {
2995           next = XEXP (note, 1);
2996
2997           if (REG_NOTE_KIND (note) == REG_UNUSED
2998               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2999             {
3000               if (REG_P (XEXP (note, 0)))
3001                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
3002
3003               remove_note (undobuf.other_insn, note);
3004             }
3005         }
3006
3007       for (note = new_other_notes; note; note = XEXP (note, 1))
3008         if (REG_P (XEXP (note, 0)))
3009           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
3010
3011       distribute_notes (new_other_notes, undobuf.other_insn,
3012                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3013     }
3014 #ifdef HAVE_cc0
3015   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3016      they are adjacent to each other or not.  */
3017   {
3018     rtx p = prev_nonnote_insn (i3);
3019     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3020         && sets_cc0_p (newi2pat))
3021       {
3022         undo_all ();
3023         return 0;
3024       }
3025   }
3026 #endif
3027
3028   /* Only allow this combination if insn_rtx_costs reports that the
3029      replacement instructions are cheaper than the originals.  */
3030   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3031     {
3032       undo_all ();
3033       return 0;
3034     }
3035
3036   /* We now know that we can do this combination.  Merge the insns and
3037      update the status of registers and LOG_LINKS.  */
3038
3039   if (swap_i2i3)
3040     {
3041       rtx insn;
3042       rtx link;
3043       rtx ni2dest;
3044
3045       /* I3 now uses what used to be its destination and which is now
3046          I2's destination.  This requires us to do a few adjustments.  */
3047       PATTERN (i3) = newpat;
3048       adjust_for_new_dest (i3);
3049
3050       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3051          so we still will.
3052
3053          However, some later insn might be using I2's dest and have
3054          a LOG_LINK pointing at I3.  We must remove this link.
3055          The simplest way to remove the link is to point it at I1,
3056          which we know will be a NOTE.  */
3057
3058       /* newi2pat is usually a SET here; however, recog_for_combine might
3059          have added some clobbers.  */
3060       if (GET_CODE (newi2pat) == PARALLEL)
3061         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3062       else
3063         ni2dest = SET_DEST (newi2pat);
3064
3065       for (insn = NEXT_INSN (i3);
3066            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3067                     || insn != BB_HEAD (this_basic_block->next_bb));
3068            insn = NEXT_INSN (insn))
3069         {
3070           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3071             {
3072               for (link = LOG_LINKS (insn); link;
3073                    link = XEXP (link, 1))
3074                 if (XEXP (link, 0) == i3)
3075                   XEXP (link, 0) = i1;
3076
3077               break;
3078             }
3079         }
3080     }
3081
3082   {
3083     rtx i3notes, i2notes, i1notes = 0;
3084     rtx i3links, i2links, i1links = 0;
3085     rtx midnotes = 0;
3086     unsigned int regno;
3087     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3088        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3089        same as i3dest, in which case newi2pat may be setting i1dest.  */
3090     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3091                    || i2dest_in_i2src || i2dest_in_i1src
3092                    || !i2dest_killed
3093                    ? 0 : i2dest);
3094     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3095                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3096                    || !i1dest_killed
3097                    ? 0 : i1dest);
3098
3099     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3100        clear them.  */
3101     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3102     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3103     if (i1)
3104       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3105
3106     /* Ensure that we do not have something that should not be shared but
3107        occurs multiple times in the new insns.  Check this by first
3108        resetting all the `used' flags and then copying anything is shared.  */
3109
3110     reset_used_flags (i3notes);
3111     reset_used_flags (i2notes);
3112     reset_used_flags (i1notes);
3113     reset_used_flags (newpat);
3114     reset_used_flags (newi2pat);
3115     if (undobuf.other_insn)
3116       reset_used_flags (PATTERN (undobuf.other_insn));
3117
3118     i3notes = copy_rtx_if_shared (i3notes);
3119     i2notes = copy_rtx_if_shared (i2notes);
3120     i1notes = copy_rtx_if_shared (i1notes);
3121     newpat = copy_rtx_if_shared (newpat);
3122     newi2pat = copy_rtx_if_shared (newi2pat);
3123     if (undobuf.other_insn)
3124       reset_used_flags (PATTERN (undobuf.other_insn));
3125
3126     INSN_CODE (i3) = insn_code_number;
3127     PATTERN (i3) = newpat;
3128
3129     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3130       {
3131         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3132
3133         reset_used_flags (call_usage);
3134         call_usage = copy_rtx (call_usage);
3135
3136         if (substed_i2)
3137           replace_rtx (call_usage, i2dest, i2src);
3138
3139         if (substed_i1)
3140           replace_rtx (call_usage, i1dest, i1src);
3141
3142         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3143       }
3144
3145     if (undobuf.other_insn)
3146       INSN_CODE (undobuf.other_insn) = other_code_number;
3147
3148     /* We had one special case above where I2 had more than one set and
3149        we replaced a destination of one of those sets with the destination
3150        of I3.  In that case, we have to update LOG_LINKS of insns later
3151        in this basic block.  Note that this (expensive) case is rare.
3152
3153        Also, in this case, we must pretend that all REG_NOTEs for I2
3154        actually came from I3, so that REG_UNUSED notes from I2 will be
3155        properly handled.  */
3156
3157     if (i3_subst_into_i2)
3158       {
3159         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3160           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3161                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3162               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3163               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3164               && ! find_reg_note (i2, REG_UNUSED,
3165                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3166             for (temp = NEXT_INSN (i2);
3167                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3168                           || BB_HEAD (this_basic_block) != temp);
3169                  temp = NEXT_INSN (temp))
3170               if (temp != i3 && INSN_P (temp))
3171                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3172                   if (XEXP (link, 0) == i2)
3173                     XEXP (link, 0) = i3;
3174
3175         if (i3notes)
3176           {
3177             rtx link = i3notes;
3178             while (XEXP (link, 1))
3179               link = XEXP (link, 1);
3180             XEXP (link, 1) = i2notes;
3181           }
3182         else
3183           i3notes = i2notes;
3184         i2notes = 0;
3185       }
3186
3187     LOG_LINKS (i3) = 0;
3188     REG_NOTES (i3) = 0;
3189     LOG_LINKS (i2) = 0;
3190     REG_NOTES (i2) = 0;
3191
3192     if (newi2pat)
3193       {
3194         INSN_CODE (i2) = i2_code_number;
3195         PATTERN (i2) = newi2pat;
3196       }
3197     else
3198       SET_INSN_DELETED (i2);
3199
3200     if (i1)
3201       {
3202         LOG_LINKS (i1) = 0;
3203         REG_NOTES (i1) = 0;
3204         SET_INSN_DELETED (i1);
3205       }
3206
3207     /* Get death notes for everything that is now used in either I3 or
3208        I2 and used to die in a previous insn.  If we built two new
3209        patterns, move from I1 to I2 then I2 to I3 so that we get the
3210        proper movement on registers that I2 modifies.  */
3211
3212     if (newi2pat)
3213       {
3214         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3215         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3216       }
3217     else
3218       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3219                    i3, &midnotes);
3220
3221     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3222     if (i3notes)
3223       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3224                         elim_i2, elim_i1);
3225     if (i2notes)
3226       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3227                         elim_i2, elim_i1);
3228     if (i1notes)
3229       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3230                         elim_i2, elim_i1);
3231     if (midnotes)
3232       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3233                         elim_i2, elim_i1);
3234
3235     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3236        know these are REG_UNUSED and want them to go to the desired insn,
3237        so we always pass it as i3.  We have not counted the notes in
3238        reg_n_deaths yet, so we need to do so now.  */
3239
3240     if (newi2pat && new_i2_notes)
3241       {
3242         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3243           if (REG_P (XEXP (temp, 0)))
3244             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3245
3246         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3247       }
3248
3249     if (new_i3_notes)
3250       {
3251         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3252           if (REG_P (XEXP (temp, 0)))
3253             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3254
3255         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3256       }
3257
3258     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3259        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3260        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3261        in that case, it might delete I2.  Similarly for I2 and I1.
3262        Show an additional death due to the REG_DEAD note we make here.  If
3263        we discard it in distribute_notes, we will decrement it again.  */
3264
3265     if (i3dest_killed)
3266       {
3267         if (REG_P (i3dest_killed))
3268           REG_N_DEATHS (REGNO (i3dest_killed))++;
3269
3270         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3271           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3272                                                NULL_RTX),
3273                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3274         else
3275           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3276                                                NULL_RTX),
3277                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3278                             elim_i2, elim_i1);
3279       }
3280
3281     if (i2dest_in_i2src)
3282       {
3283         if (REG_P (i2dest))
3284           REG_N_DEATHS (REGNO (i2dest))++;
3285
3286         if (newi2pat && reg_set_p (i2dest, newi2pat))
3287           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3288                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3289         else
3290           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3291                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3292                             NULL_RTX, NULL_RTX);
3293       }
3294
3295     if (i1dest_in_i1src)
3296       {
3297         if (REG_P (i1dest))
3298           REG_N_DEATHS (REGNO (i1dest))++;
3299
3300         if (newi2pat && reg_set_p (i1dest, newi2pat))
3301           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3302                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3303         else
3304           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3305                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3306                             NULL_RTX, NULL_RTX);
3307       }
3308
3309     distribute_links (i3links);
3310     distribute_links (i2links);
3311     distribute_links (i1links);
3312
3313     if (REG_P (i2dest))
3314       {
3315         rtx link;
3316         rtx i2_insn = 0, i2_val = 0, set;
3317
3318         /* The insn that used to set this register doesn't exist, and
3319            this life of the register may not exist either.  See if one of
3320            I3's links points to an insn that sets I2DEST.  If it does,
3321            that is now the last known value for I2DEST. If we don't update
3322            this and I2 set the register to a value that depended on its old
3323            contents, we will get confused.  If this insn is used, thing
3324            will be set correctly in combine_instructions.  */
3325
3326         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3327           if ((set = single_set (XEXP (link, 0))) != 0
3328               && rtx_equal_p (i2dest, SET_DEST (set)))
3329             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3330
3331         record_value_for_reg (i2dest, i2_insn, i2_val);
3332
3333         /* If the reg formerly set in I2 died only once and that was in I3,
3334            zero its use count so it won't make `reload' do any work.  */
3335         if (! added_sets_2
3336             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3337             && ! i2dest_in_i2src)
3338           {
3339             regno = REGNO (i2dest);
3340             REG_N_SETS (regno)--;
3341           }
3342       }
3343
3344     if (i1 && REG_P (i1dest))
3345       {
3346         rtx link;
3347         rtx i1_insn = 0, i1_val = 0, set;
3348
3349         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3350           if ((set = single_set (XEXP (link, 0))) != 0
3351               && rtx_equal_p (i1dest, SET_DEST (set)))
3352             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3353
3354         record_value_for_reg (i1dest, i1_insn, i1_val);
3355
3356         regno = REGNO (i1dest);
3357         if (! added_sets_1 && ! i1dest_in_i1src)
3358           REG_N_SETS (regno)--;
3359       }
3360
3361     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3362        been made to this insn.  The order of
3363        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3364        can affect nonzero_bits of newpat */
3365     if (newi2pat)
3366       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3367     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3368
3369     /* Set new_direct_jump_p if a new return or simple jump instruction
3370        has been created.
3371
3372        If I3 is now an unconditional jump, ensure that it has a
3373        BARRIER following it since it may have initially been a
3374        conditional jump.  It may also be the last nonnote insn.  */
3375
3376     if (returnjump_p (i3) || any_uncondjump_p (i3))
3377       {
3378         *new_direct_jump_p = 1;
3379         mark_jump_label (PATTERN (i3), i3, 0);
3380
3381         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3382             || !BARRIER_P (temp))
3383           emit_barrier_after (i3);
3384       }
3385
3386     if (undobuf.other_insn != NULL_RTX
3387         && (returnjump_p (undobuf.other_insn)
3388             || any_uncondjump_p (undobuf.other_insn)))
3389       {
3390         *new_direct_jump_p = 1;
3391
3392         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3393             || !BARRIER_P (temp))
3394           emit_barrier_after (undobuf.other_insn);
3395       }
3396
3397     /* An NOOP jump does not need barrier, but it does need cleaning up
3398        of CFG.  */
3399     if (GET_CODE (newpat) == SET
3400         && SET_SRC (newpat) == pc_rtx
3401         && SET_DEST (newpat) == pc_rtx)
3402       *new_direct_jump_p = 1;
3403   }
3404
3405   combine_successes++;
3406   undo_commit ();
3407
3408   if (added_links_insn
3409       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3410       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3411     return added_links_insn;
3412   else
3413     return newi2pat ? i2 : i3;
3414 }
3415 \f
3416 /* Undo all the modifications recorded in undobuf.  */
3417
3418 static void
3419 undo_all (void)
3420 {
3421   struct undo *undo, *next;
3422
3423   for (undo = undobuf.undos; undo; undo = next)
3424     {
3425       next = undo->next;
3426       switch (undo->kind)
3427         {
3428         case UNDO_RTX:
3429           *undo->where.r = undo->old_contents.r;
3430           break;
3431         case UNDO_INT:
3432           *undo->where.i = undo->old_contents.i;
3433           break;
3434         case UNDO_MODE:
3435           PUT_MODE (*undo->where.r, undo->old_contents.m);
3436           break;
3437         default:
3438           gcc_unreachable ();
3439         }
3440
3441       undo->next = undobuf.frees;
3442       undobuf.frees = undo;
3443     }
3444
3445   undobuf.undos = 0;
3446 }
3447
3448 /* We've committed to accepting the changes we made.  Move all
3449    of the undos to the free list.  */
3450
3451 static void
3452 undo_commit (void)
3453 {
3454   struct undo *undo, *next;
3455
3456   for (undo = undobuf.undos; undo; undo = next)
3457     {
3458       next = undo->next;
3459       undo->next = undobuf.frees;
3460       undobuf.frees = undo;
3461     }
3462   undobuf.undos = 0;
3463 }
3464 \f
3465 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3466    where we have an arithmetic expression and return that point.  LOC will
3467    be inside INSN.
3468
3469    try_combine will call this function to see if an insn can be split into
3470    two insns.  */
3471
3472 static rtx *
3473 find_split_point (rtx *loc, rtx insn)
3474 {
3475   rtx x = *loc;
3476   enum rtx_code code = GET_CODE (x);
3477   rtx *split;
3478   unsigned HOST_WIDE_INT len = 0;
3479   HOST_WIDE_INT pos = 0;
3480   int unsignedp = 0;
3481   rtx inner = NULL_RTX;
3482
3483   /* First special-case some codes.  */
3484   switch (code)
3485     {
3486     case SUBREG:
3487 #ifdef INSN_SCHEDULING
3488       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3489          point.  */
3490       if (MEM_P (SUBREG_REG (x)))
3491         return loc;
3492 #endif
3493       return find_split_point (&SUBREG_REG (x), insn);
3494
3495     case MEM:
3496 #ifdef HAVE_lo_sum
3497       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3498          using LO_SUM and HIGH.  */
3499       if (GET_CODE (XEXP (x, 0)) == CONST
3500           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3501         {
3502           SUBST (XEXP (x, 0),
3503                  gen_rtx_LO_SUM (Pmode,
3504                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3505                                  XEXP (x, 0)));
3506           return &XEXP (XEXP (x, 0), 0);
3507         }
3508 #endif
3509
3510       /* If we have a PLUS whose second operand is a constant and the
3511          address is not valid, perhaps will can split it up using
3512          the machine-specific way to split large constants.  We use
3513          the first pseudo-reg (one of the virtual regs) as a placeholder;
3514          it will not remain in the result.  */
3515       if (GET_CODE (XEXP (x, 0)) == PLUS
3516           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3517           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3518         {
3519           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3520           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3521                                  subst_insn);
3522
3523           /* This should have produced two insns, each of which sets our
3524              placeholder.  If the source of the second is a valid address,
3525              we can make put both sources together and make a split point
3526              in the middle.  */
3527
3528           if (seq
3529               && NEXT_INSN (seq) != NULL_RTX
3530               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3531               && NONJUMP_INSN_P (seq)
3532               && GET_CODE (PATTERN (seq)) == SET
3533               && SET_DEST (PATTERN (seq)) == reg
3534               && ! reg_mentioned_p (reg,
3535                                     SET_SRC (PATTERN (seq)))
3536               && NONJUMP_INSN_P (NEXT_INSN (seq))
3537               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3538               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3539               && memory_address_p (GET_MODE (x),
3540                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3541             {
3542               rtx src1 = SET_SRC (PATTERN (seq));
3543               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3544
3545               /* Replace the placeholder in SRC2 with SRC1.  If we can
3546                  find where in SRC2 it was placed, that can become our
3547                  split point and we can replace this address with SRC2.
3548                  Just try two obvious places.  */
3549
3550               src2 = replace_rtx (src2, reg, src1);
3551               split = 0;
3552               if (XEXP (src2, 0) == src1)
3553                 split = &XEXP (src2, 0);
3554               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3555                        && XEXP (XEXP (src2, 0), 0) == src1)
3556                 split = &XEXP (XEXP (src2, 0), 0);
3557
3558               if (split)
3559                 {
3560                   SUBST (XEXP (x, 0), src2);
3561                   return split;
3562                 }
3563             }
3564
3565           /* If that didn't work, perhaps the first operand is complex and
3566              needs to be computed separately, so make a split point there.
3567              This will occur on machines that just support REG + CONST
3568              and have a constant moved through some previous computation.  */
3569
3570           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3571                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3572                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3573             return &XEXP (XEXP (x, 0), 0);
3574         }
3575       break;
3576
3577     case SET:
3578 #ifdef HAVE_cc0
3579       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3580          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3581          we need to put the operand into a register.  So split at that
3582          point.  */
3583
3584       if (SET_DEST (x) == cc0_rtx
3585           && GET_CODE (SET_SRC (x)) != COMPARE
3586           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3587           && !OBJECT_P (SET_SRC (x))
3588           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3589                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3590         return &SET_SRC (x);
3591 #endif
3592
3593       /* See if we can split SET_SRC as it stands.  */
3594       split = find_split_point (&SET_SRC (x), insn);
3595       if (split && split != &SET_SRC (x))
3596         return split;
3597
3598       /* See if we can split SET_DEST as it stands.  */
3599       split = find_split_point (&SET_DEST (x), insn);
3600       if (split && split != &SET_DEST (x))
3601         return split;
3602
3603       /* See if this is a bitfield assignment with everything constant.  If
3604          so, this is an IOR of an AND, so split it into that.  */
3605       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3606           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3607               <= HOST_BITS_PER_WIDE_INT)
3608           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3609           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3610           && GET_CODE (SET_SRC (x)) == CONST_INT
3611           && ((INTVAL (XEXP (SET_DEST (x), 1))
3612                + INTVAL (XEXP (SET_DEST (x), 2)))
3613               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3614           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3615         {
3616           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3617           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3618           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3619           rtx dest = XEXP (SET_DEST (x), 0);
3620           enum machine_mode mode = GET_MODE (dest);
3621           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3622           rtx or_mask;
3623
3624           if (BITS_BIG_ENDIAN)
3625             pos = GET_MODE_BITSIZE (mode) - len - pos;
3626
3627           or_mask = gen_int_mode (src << pos, mode);
3628           if (src == mask)
3629             SUBST (SET_SRC (x),
3630                    simplify_gen_binary (IOR, mode, dest, or_mask));
3631           else
3632             {
3633               rtx negmask = gen_int_mode (~(mask << pos), mode);
3634               SUBST (SET_SRC (x),
3635                      simplify_gen_binary (IOR, mode,
3636                                           simplify_gen_binary (AND, mode,
3637                                                                dest, negmask),
3638                                           or_mask));
3639             }
3640
3641           SUBST (SET_DEST (x), dest);
3642
3643           split = find_split_point (&SET_SRC (x), insn);
3644           if (split && split != &SET_SRC (x))
3645             return split;
3646         }
3647
3648       /* Otherwise, see if this is an operation that we can split into two.
3649          If so, try to split that.  */
3650       code = GET_CODE (SET_SRC (x));
3651
3652       switch (code)
3653         {
3654         case AND:
3655           /* If we are AND'ing with a large constant that is only a single
3656              bit and the result is only being used in a context where we
3657              need to know if it is zero or nonzero, replace it with a bit
3658              extraction.  This will avoid the large constant, which might
3659              have taken more than one insn to make.  If the constant were
3660              not a valid argument to the AND but took only one insn to make,
3661              this is no worse, but if it took more than one insn, it will
3662              be better.  */
3663
3664           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3665               && REG_P (XEXP (SET_SRC (x), 0))
3666               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3667               && REG_P (SET_DEST (x))
3668               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3669               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3670               && XEXP (*split, 0) == SET_DEST (x)
3671               && XEXP (*split, 1) == const0_rtx)
3672             {
3673               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3674                                                 XEXP (SET_SRC (x), 0),
3675                                                 pos, NULL_RTX, 1, 1, 0, 0);
3676               if (extraction != 0)
3677                 {
3678                   SUBST (SET_SRC (x), extraction);
3679                   return find_split_point (loc, insn);
3680                 }
3681             }
3682           break;
3683
3684         case NE:
3685           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3686              is known to be on, this can be converted into a NEG of a shift.  */
3687           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3688               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3689               && 1 <= (pos = exact_log2
3690                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3691                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3692             {
3693               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3694
3695               SUBST (SET_SRC (x),
3696                      gen_rtx_NEG (mode,
3697                                   gen_rtx_LSHIFTRT (mode,
3698                                                     XEXP (SET_SRC (x), 0),
3699                                                     GEN_INT (pos))));
3700
3701               split = find_split_point (&SET_SRC (x), insn);
3702               if (split && split != &SET_SRC (x))
3703                 return split;
3704             }
3705           break;
3706
3707         case SIGN_EXTEND:
3708           inner = XEXP (SET_SRC (x), 0);
3709
3710           /* We can't optimize if either mode is a partial integer
3711              mode as we don't know how many bits are significant
3712              in those modes.  */
3713           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3714               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3715             break;
3716
3717           pos = 0;
3718           len = GET_MODE_BITSIZE (GET_MODE (inner));
3719           unsignedp = 0;
3720           break;
3721
3722         case SIGN_EXTRACT:
3723         case ZERO_EXTRACT:
3724           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3725               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3726             {
3727               inner = XEXP (SET_SRC (x), 0);
3728               len = INTVAL (XEXP (SET_SRC (x), 1));
3729               pos = INTVAL (XEXP (SET_SRC (x), 2));
3730
3731               if (BITS_BIG_ENDIAN)
3732                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3733               unsignedp = (code == ZERO_EXTRACT);
3734             }
3735           break;
3736
3737         default:
3738           break;
3739         }
3740
3741       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3742         {
3743           enum machine_mode mode = GET_MODE (SET_SRC (x));
3744
3745           /* For unsigned, we have a choice of a shift followed by an
3746              AND or two shifts.  Use two shifts for field sizes where the
3747              constant might be too large.  We assume here that we can
3748              always at least get 8-bit constants in an AND insn, which is
3749              true for every current RISC.  */
3750
3751           if (unsignedp && len <= 8)
3752             {
3753               SUBST (SET_SRC (x),
3754                      gen_rtx_AND (mode,
3755                                   gen_rtx_LSHIFTRT
3756                                   (mode, gen_lowpart (mode, inner),
3757                                    GEN_INT (pos)),
3758                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3759
3760               split = find_split_point (&SET_SRC (x), insn);
3761               if (split && split != &SET_SRC (x))
3762                 return split;
3763             }
3764           else
3765             {
3766               SUBST (SET_SRC (x),
3767                      gen_rtx_fmt_ee
3768                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3769                       gen_rtx_ASHIFT (mode,
3770                                       gen_lowpart (mode, inner),
3771                                       GEN_INT (GET_MODE_BITSIZE (mode)
3772                                                - len - pos)),
3773                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3774
3775               split = find_split_point (&SET_SRC (x), insn);
3776               if (split && split != &SET_SRC (x))
3777                 return split;
3778             }
3779         }
3780
3781       /* See if this is a simple operation with a constant as the second
3782          operand.  It might be that this constant is out of range and hence
3783          could be used as a split point.  */
3784       if (BINARY_P (SET_SRC (x))
3785           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3786           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3787               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3788                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3789         return &XEXP (SET_SRC (x), 1);
3790
3791       /* Finally, see if this is a simple operation with its first operand
3792          not in a register.  The operation might require this operand in a
3793          register, so return it as a split point.  We can always do this
3794          because if the first operand were another operation, we would have
3795          already found it as a split point.  */
3796       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3797           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3798         return &XEXP (SET_SRC (x), 0);
3799
3800       return 0;
3801
3802     case AND:
3803     case IOR:
3804       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3805          it is better to write this as (not (ior A B)) so we can split it.
3806          Similarly for IOR.  */
3807       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3808         {
3809           SUBST (*loc,
3810                  gen_rtx_NOT (GET_MODE (x),
3811                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3812                                               GET_MODE (x),
3813                                               XEXP (XEXP (x, 0), 0),
3814                                               XEXP (XEXP (x, 1), 0))));
3815           return find_split_point (loc, insn);
3816         }
3817
3818       /* Many RISC machines have a large set of logical insns.  If the
3819          second operand is a NOT, put it first so we will try to split the
3820          other operand first.  */
3821       if (GET_CODE (XEXP (x, 1)) == NOT)
3822         {
3823           rtx tem = XEXP (x, 0);
3824           SUBST (XEXP (x, 0), XEXP (x, 1));
3825           SUBST (XEXP (x, 1), tem);
3826         }
3827       break;
3828
3829     default:
3830       break;
3831     }
3832
3833   /* Otherwise, select our actions depending on our rtx class.  */
3834   switch (GET_RTX_CLASS (code))
3835     {
3836     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3837     case RTX_TERNARY:
3838       split = find_split_point (&XEXP (x, 2), insn);
3839       if (split)
3840         return split;
3841       /* ... fall through ...  */
3842     case RTX_BIN_ARITH:
3843     case RTX_COMM_ARITH:
3844     case RTX_COMPARE:
3845     case RTX_COMM_COMPARE:
3846       split = find_split_point (&XEXP (x, 1), insn);
3847       if (split)
3848         return split;
3849       /* ... fall through ...  */
3850     case RTX_UNARY:
3851       /* Some machines have (and (shift ...) ...) insns.  If X is not
3852          an AND, but XEXP (X, 0) is, use it as our split point.  */
3853       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3854         return &XEXP (x, 0);
3855
3856       split = find_split_point (&XEXP (x, 0), insn);
3857       if (split)
3858         return split;
3859       return loc;
3860
3861     default:
3862       /* Otherwise, we don't have a split point.  */
3863       return 0;
3864     }
3865 }
3866 \f
3867 /* Throughout X, replace FROM with TO, and return the result.
3868    The result is TO if X is FROM;
3869    otherwise the result is X, but its contents may have been modified.
3870    If they were modified, a record was made in undobuf so that
3871    undo_all will (among other things) return X to its original state.
3872
3873    If the number of changes necessary is too much to record to undo,
3874    the excess changes are not made, so the result is invalid.
3875    The changes already made can still be undone.
3876    undobuf.num_undo is incremented for such changes, so by testing that
3877    the caller can tell whether the result is valid.
3878
3879    `n_occurrences' is incremented each time FROM is replaced.
3880
3881    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3882
3883    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3884    by copying if `n_occurrences' is nonzero.  */
3885
3886 static rtx
3887 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3888 {
3889   enum rtx_code code = GET_CODE (x);
3890   enum machine_mode op0_mode = VOIDmode;
3891   const char *fmt;
3892   int len, i;
3893   rtx new;
3894
3895 /* Two expressions are equal if they are identical copies of a shared
3896    RTX or if they are both registers with the same register number
3897    and mode.  */
3898
3899 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3900   ((X) == (Y)                                           \
3901    || (REG_P (X) && REG_P (Y)   \
3902        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3903
3904   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3905     {
3906       n_occurrences++;
3907       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3908     }
3909
3910   /* If X and FROM are the same register but different modes, they will
3911      not have been seen as equal above.  However, flow.c will make a
3912      LOG_LINKS entry for that case.  If we do nothing, we will try to
3913      rerecognize our original insn and, when it succeeds, we will
3914      delete the feeding insn, which is incorrect.
3915
3916      So force this insn not to match in this (rare) case.  */
3917   if (! in_dest && code == REG && REG_P (from)
3918       && REGNO (x) == REGNO (from))
3919     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3920
3921   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3922      of which may contain things that can be combined.  */
3923   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3924     return x;
3925
3926   /* It is possible to have a subexpression appear twice in the insn.
3927      Suppose that FROM is a register that appears within TO.
3928      Then, after that subexpression has been scanned once by `subst',
3929      the second time it is scanned, TO may be found.  If we were
3930      to scan TO here, we would find FROM within it and create a
3931      self-referent rtl structure which is completely wrong.  */
3932   if (COMBINE_RTX_EQUAL_P (x, to))
3933     return to;
3934
3935   /* Parallel asm_operands need special attention because all of the
3936      inputs are shared across the arms.  Furthermore, unsharing the
3937      rtl results in recognition failures.  Failure to handle this case
3938      specially can result in circular rtl.
3939
3940      Solve this by doing a normal pass across the first entry of the
3941      parallel, and only processing the SET_DESTs of the subsequent
3942      entries.  Ug.  */
3943
3944   if (code == PARALLEL
3945       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3946       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3947     {
3948       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3949
3950       /* If this substitution failed, this whole thing fails.  */
3951       if (GET_CODE (new) == CLOBBER
3952           && XEXP (new, 0) == const0_rtx)
3953         return new;
3954
3955       SUBST (XVECEXP (x, 0, 0), new);
3956
3957       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3958         {
3959           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3960
3961           if (!REG_P (dest)
3962               && GET_CODE (dest) != CC0
3963               && GET_CODE (dest) != PC)
3964             {
3965               new = subst (dest, from, to, 0, unique_copy);
3966
3967               /* If this substitution failed, this whole thing fails.  */
3968               if (GET_CODE (new) == CLOBBER
3969                   && XEXP (new, 0) == const0_rtx)
3970                 return new;
3971
3972               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3973             }
3974         }
3975     }
3976   else
3977     {
3978       len = GET_RTX_LENGTH (code);
3979       fmt = GET_RTX_FORMAT (code);
3980
3981       /* We don't need to process a SET_DEST that is a register, CC0,
3982          or PC, so set up to skip this common case.  All other cases
3983          where we want to suppress replacing something inside a
3984          SET_SRC are handled via the IN_DEST operand.  */
3985       if (code == SET
3986           && (REG_P (SET_DEST (x))
3987               || GET_CODE (SET_DEST (x)) == CC0
3988               || GET_CODE (SET_DEST (x)) == PC))
3989         fmt = "ie";
3990
3991       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3992          constant.  */
3993       if (fmt[0] == 'e')
3994         op0_mode = GET_MODE (XEXP (x, 0));
3995
3996       for (i = 0; i < len; i++)
3997         {
3998           if (fmt[i] == 'E')
3999             {
4000               int j;
4001               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4002                 {
4003                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4004                     {
4005                       new = (unique_copy && n_occurrences
4006                              ? copy_rtx (to) : to);
4007                       n_occurrences++;
4008                     }
4009                   else
4010                     {
4011                       new = subst (XVECEXP (x, i, j), from, to, 0,
4012                                    unique_copy);
4013
4014                       /* If this substitution failed, this whole thing
4015                          fails.  */
4016                       if (GET_CODE (new) == CLOBBER
4017                           && XEXP (new, 0) == const0_rtx)
4018                         return new;
4019                     }
4020
4021                   SUBST (XVECEXP (x, i, j), new);
4022                 }
4023             }
4024           else if (fmt[i] == 'e')
4025             {
4026               /* If this is a register being set, ignore it.  */
4027               new = XEXP (x, i);
4028               if (in_dest
4029                   && i == 0
4030                   && (((code == SUBREG || code == ZERO_EXTRACT)
4031                        && REG_P (new))
4032                       || code == STRICT_LOW_PART))
4033                 ;
4034
4035               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4036                 {
4037                   /* In general, don't install a subreg involving two
4038                      modes not tieable.  It can worsen register
4039                      allocation, and can even make invalid reload
4040                      insns, since the reg inside may need to be copied
4041                      from in the outside mode, and that may be invalid
4042                      if it is an fp reg copied in integer mode.
4043
4044                      We allow two exceptions to this: It is valid if
4045                      it is inside another SUBREG and the mode of that
4046                      SUBREG and the mode of the inside of TO is
4047                      tieable and it is valid if X is a SET that copies
4048                      FROM to CC0.  */
4049
4050                   if (GET_CODE (to) == SUBREG
4051                       && ! MODES_TIEABLE_P (GET_MODE (to),
4052                                             GET_MODE (SUBREG_REG (to)))
4053                       && ! (code == SUBREG
4054                             && MODES_TIEABLE_P (GET_MODE (x),
4055                                                 GET_MODE (SUBREG_REG (to))))
4056 #ifdef HAVE_cc0
4057                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4058 #endif
4059                       )
4060                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4061
4062 #ifdef CANNOT_CHANGE_MODE_CLASS
4063                   if (code == SUBREG
4064                       && REG_P (to)
4065                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4066                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4067                                                    GET_MODE (to),
4068                                                    GET_MODE (x)))
4069                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4070 #endif
4071
4072                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4073                   n_occurrences++;
4074                 }
4075               else
4076                 /* If we are in a SET_DEST, suppress most cases unless we
4077                    have gone inside a MEM, in which case we want to
4078                    simplify the address.  We assume here that things that
4079                    are actually part of the destination have their inner
4080                    parts in the first expression.  This is true for SUBREG,
4081                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4082                    things aside from REG and MEM that should appear in a
4083                    SET_DEST.  */
4084                 new = subst (XEXP (x, i), from, to,
4085                              (((in_dest
4086                                 && (code == SUBREG || code == STRICT_LOW_PART
4087                                     || code == ZERO_EXTRACT))
4088                                || code == SET)
4089                               && i == 0), unique_copy);
4090
4091               /* If we found that we will have to reject this combination,
4092                  indicate that by returning the CLOBBER ourselves, rather than
4093                  an expression containing it.  This will speed things up as
4094                  well as prevent accidents where two CLOBBERs are considered
4095                  to be equal, thus producing an incorrect simplification.  */
4096
4097               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4098                 return new;
4099
4100               if (GET_CODE (x) == SUBREG
4101                   && (GET_CODE (new) == CONST_INT
4102                       || GET_CODE (new) == CONST_DOUBLE))
4103                 {
4104                   enum machine_mode mode = GET_MODE (x);
4105
4106                   x = simplify_subreg (GET_MODE (x), new,
4107                                        GET_MODE (SUBREG_REG (x)),
4108                                        SUBREG_BYTE (x));
4109                   if (! x)
4110                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4111                 }
4112               else if (GET_CODE (new) == CONST_INT
4113                        && GET_CODE (x) == ZERO_EXTEND)
4114                 {
4115                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4116                                                 new, GET_MODE (XEXP (x, 0)));
4117                   gcc_assert (x);
4118                 }
4119               else
4120                 SUBST (XEXP (x, i), new);
4121             }
4122         }
4123     }
4124
4125   /* Try to simplify X.  If the simplification changed the code, it is likely
4126      that further simplification will help, so loop, but limit the number
4127      of repetitions that will be performed.  */
4128
4129   for (i = 0; i < 4; i++)
4130     {
4131       /* If X is sufficiently simple, don't bother trying to do anything
4132          with it.  */
4133       if (code != CONST_INT && code != REG && code != CLOBBER)
4134         x = combine_simplify_rtx (x, op0_mode, in_dest);
4135
4136       if (GET_CODE (x) == code)
4137         break;
4138
4139       code = GET_CODE (x);
4140
4141       /* We no longer know the original mode of operand 0 since we
4142          have changed the form of X)  */
4143       op0_mode = VOIDmode;
4144     }
4145
4146   return x;
4147 }
4148 \f
4149 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4150    outer level; call `subst' to simplify recursively.  Return the new
4151    expression.
4152
4153    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4154    if we are inside a SET_DEST.  */
4155
4156 static rtx
4157 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4158 {
4159   enum rtx_code code = GET_CODE (x);
4160   enum machine_mode mode = GET_MODE (x);
4161   rtx temp;
4162   int i;
4163
4164   /* If this is a commutative operation, put a constant last and a complex
4165      expression first.  We don't need to do this for comparisons here.  */
4166   if (COMMUTATIVE_ARITH_P (x)
4167       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4168     {
4169       temp = XEXP (x, 0);
4170       SUBST (XEXP (x, 0), XEXP (x, 1));
4171       SUBST (XEXP (x, 1), temp);
4172     }
4173
4174   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4175      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4176      things.  Check for cases where both arms are testing the same
4177      condition.
4178
4179      Don't do anything if all operands are very simple.  */
4180
4181   if ((BINARY_P (x)
4182        && ((!OBJECT_P (XEXP (x, 0))
4183             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4184                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4185            || (!OBJECT_P (XEXP (x, 1))
4186                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4187                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4188       || (UNARY_P (x)
4189           && (!OBJECT_P (XEXP (x, 0))
4190                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4191                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4192     {
4193       rtx cond, true_rtx, false_rtx;
4194
4195       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4196       if (cond != 0
4197           /* If everything is a comparison, what we have is highly unlikely
4198              to be simpler, so don't use it.  */
4199           && ! (COMPARISON_P (x)
4200                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4201         {
4202           rtx cop1 = const0_rtx;
4203           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4204
4205           if (cond_code == NE && COMPARISON_P (cond))
4206             return x;
4207
4208           /* Simplify the alternative arms; this may collapse the true and
4209              false arms to store-flag values.  Be careful to use copy_rtx
4210              here since true_rtx or false_rtx might share RTL with x as a
4211              result of the if_then_else_cond call above.  */
4212           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4213           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4214
4215           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4216              is unlikely to be simpler.  */
4217           if (general_operand (true_rtx, VOIDmode)
4218               && general_operand (false_rtx, VOIDmode))
4219             {
4220               enum rtx_code reversed;
4221
4222               /* Restarting if we generate a store-flag expression will cause
4223                  us to loop.  Just drop through in this case.  */
4224
4225               /* If the result values are STORE_FLAG_VALUE and zero, we can
4226                  just make the comparison operation.  */
4227               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4228                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4229                                              cond, cop1);
4230               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4231                        && ((reversed = reversed_comparison_code_parts
4232                                         (cond_code, cond, cop1, NULL))
4233                            != UNKNOWN))
4234                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4235                                              cond, cop1);
4236
4237               /* Likewise, we can make the negate of a comparison operation
4238                  if the result values are - STORE_FLAG_VALUE and zero.  */
4239               else if (GET_CODE (true_rtx) == CONST_INT
4240                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4241                        && false_rtx == const0_rtx)
4242                 x = simplify_gen_unary (NEG, mode,
4243                                         simplify_gen_relational (cond_code,
4244                                                                  mode, VOIDmode,
4245                                                                  cond, cop1),
4246                                         mode);
4247               else if (GET_CODE (false_rtx) == CONST_INT
4248                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4249                        && true_rtx == const0_rtx
4250                        && ((reversed = reversed_comparison_code_parts
4251                                         (cond_code, cond, cop1, NULL))
4252                            != UNKNOWN))
4253                 x = simplify_gen_unary (NEG, mode,
4254                                         simplify_gen_relational (reversed,
4255                                                                  mode, VOIDmode,
4256                                                                  cond, cop1),
4257                                         mode);
4258               else
4259                 return gen_rtx_IF_THEN_ELSE (mode,
4260                                              simplify_gen_relational (cond_code,
4261                                                                       mode,
4262                                                                       VOIDmode,
4263                                                                       cond,
4264                                                                       cop1),
4265                                              true_rtx, false_rtx);
4266
4267               code = GET_CODE (x);
4268               op0_mode = VOIDmode;
4269             }
4270         }
4271     }
4272
4273   /* Try to fold this expression in case we have constants that weren't
4274      present before.  */
4275   temp = 0;
4276   switch (GET_RTX_CLASS (code))
4277     {
4278     case RTX_UNARY:
4279       if (op0_mode == VOIDmode)
4280         op0_mode = GET_MODE (XEXP (x, 0));
4281       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4282       break;
4283     case RTX_COMPARE:
4284     case RTX_COMM_COMPARE:
4285       {
4286         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4287         if (cmp_mode == VOIDmode)
4288           {
4289             cmp_mode = GET_MODE (XEXP (x, 1));
4290             if (cmp_mode == VOIDmode)
4291               cmp_mode = op0_mode;
4292           }
4293         temp = simplify_relational_operation (code, mode, cmp_mode,
4294                                               XEXP (x, 0), XEXP (x, 1));
4295       }
4296       break;
4297     case RTX_COMM_ARITH:
4298     case RTX_BIN_ARITH:
4299       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4300       break;
4301     case RTX_BITFIELD_OPS:
4302     case RTX_TERNARY:
4303       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4304                                          XEXP (x, 1), XEXP (x, 2));
4305       break;
4306     default:
4307       break;
4308     }
4309
4310   if (temp)
4311     {
4312       x = temp;
4313       code = GET_CODE (temp);
4314       op0_mode = VOIDmode;
4315       mode = GET_MODE (temp);
4316     }
4317
4318   /* First see if we can apply the inverse distributive law.  */
4319   if (code == PLUS || code == MINUS
4320       || code == AND || code == IOR || code == XOR)
4321     {
4322       x = apply_distributive_law (x);
4323       code = GET_CODE (x);
4324       op0_mode = VOIDmode;
4325     }
4326
4327   /* If CODE is an associative operation not otherwise handled, see if we
4328      can associate some operands.  This can win if they are constants or
4329      if they are logically related (i.e. (a & b) & a).  */
4330   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4331        || code == AND || code == IOR || code == XOR
4332        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4333       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4334           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4335     {
4336       if (GET_CODE (XEXP (x, 0)) == code)
4337         {
4338           rtx other = XEXP (XEXP (x, 0), 0);
4339           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4340           rtx inner_op1 = XEXP (x, 1);
4341           rtx inner;
4342
4343           /* Make sure we pass the constant operand if any as the second
4344              one if this is a commutative operation.  */
4345           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4346             {
4347               rtx tem = inner_op0;
4348               inner_op0 = inner_op1;
4349               inner_op1 = tem;
4350             }
4351           inner = simplify_binary_operation (code == MINUS ? PLUS
4352                                              : code == DIV ? MULT
4353                                              : code,
4354                                              mode, inner_op0, inner_op1);
4355
4356           /* For commutative operations, try the other pair if that one
4357              didn't simplify.  */
4358           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4359             {
4360               other = XEXP (XEXP (x, 0), 1);
4361               inner = simplify_binary_operation (code, mode,
4362                                                  XEXP (XEXP (x, 0), 0),
4363                                                  XEXP (x, 1));
4364             }
4365
4366           if (inner)
4367             return simplify_gen_binary (code, mode, other, inner);
4368         }
4369     }
4370
4371   /* A little bit of algebraic simplification here.  */
4372   switch (code)
4373     {
4374     case MEM:
4375       /* Ensure that our address has any ASHIFTs converted to MULT in case
4376          address-recognizing predicates are called later.  */
4377       temp = make_compound_operation (XEXP (x, 0), MEM);
4378       SUBST (XEXP (x, 0), temp);
4379       break;
4380
4381     case SUBREG:
4382       if (op0_mode == VOIDmode)
4383         op0_mode = GET_MODE (SUBREG_REG (x));
4384
4385       /* See if this can be moved to simplify_subreg.  */
4386       if (CONSTANT_P (SUBREG_REG (x))
4387           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4388              /* Don't call gen_lowpart if the inner mode
4389                 is VOIDmode and we cannot simplify it, as SUBREG without
4390                 inner mode is invalid.  */
4391           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4392               || gen_lowpart_common (mode, SUBREG_REG (x))))
4393         return gen_lowpart (mode, SUBREG_REG (x));
4394
4395       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4396         break;
4397       {
4398         rtx temp;
4399         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4400                                 SUBREG_BYTE (x));
4401         if (temp)
4402           return temp;
4403       }
4404
4405       /* Don't change the mode of the MEM if that would change the meaning
4406          of the address.  */
4407       if (MEM_P (SUBREG_REG (x))
4408           && (MEM_VOLATILE_P (SUBREG_REG (x))
4409               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4410         return gen_rtx_CLOBBER (mode, const0_rtx);
4411
4412       /* Note that we cannot do any narrowing for non-constants since
4413          we might have been counting on using the fact that some bits were
4414          zero.  We now do this in the SET.  */
4415
4416       break;
4417
4418     case NEG:
4419       temp = expand_compound_operation (XEXP (x, 0));
4420
4421       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4422          replaced by (lshiftrt X C).  This will convert
4423          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4424
4425       if (GET_CODE (temp) == ASHIFTRT
4426           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4427           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4428         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4429                                      INTVAL (XEXP (temp, 1)));
4430
4431       /* If X has only a single bit that might be nonzero, say, bit I, convert
4432          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4433          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4434          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4435          or a SUBREG of one since we'd be making the expression more
4436          complex if it was just a register.  */
4437
4438       if (!REG_P (temp)
4439           && ! (GET_CODE (temp) == SUBREG
4440                 && REG_P (SUBREG_REG (temp)))
4441           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4442         {
4443           rtx temp1 = simplify_shift_const
4444             (NULL_RTX, ASHIFTRT, mode,
4445              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4446                                    GET_MODE_BITSIZE (mode) - 1 - i),
4447              GET_MODE_BITSIZE (mode) - 1 - i);
4448
4449           /* If all we did was surround TEMP with the two shifts, we
4450              haven't improved anything, so don't use it.  Otherwise,
4451              we are better off with TEMP1.  */
4452           if (GET_CODE (temp1) != ASHIFTRT
4453               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4454               || XEXP (XEXP (temp1, 0), 0) != temp)
4455             return temp1;
4456         }
4457       break;
4458
4459     case TRUNCATE:
4460       /* We can't handle truncation to a partial integer mode here
4461          because we don't know the real bitsize of the partial
4462          integer mode.  */
4463       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4464         break;
4465
4466       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4467           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4468                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4469         SUBST (XEXP (x, 0),
4470                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4471                               GET_MODE_MASK (mode), 0));
4472
4473       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4474          whose value is a comparison can be replaced with a subreg if
4475          STORE_FLAG_VALUE permits.  */
4476       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4477           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4478           && (temp = get_last_value (XEXP (x, 0)))
4479           && COMPARISON_P (temp))
4480         return gen_lowpart (mode, XEXP (x, 0));
4481       break;
4482
4483 #ifdef HAVE_cc0
4484     case COMPARE:
4485       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4486          using cc0, in which case we want to leave it as a COMPARE
4487          so we can distinguish it from a register-register-copy.  */
4488       if (XEXP (x, 1) == const0_rtx)
4489         return XEXP (x, 0);
4490
4491       /* x - 0 is the same as x unless x's mode has signed zeros and
4492          allows rounding towards -infinity.  Under those conditions,
4493          0 - 0 is -0.  */
4494       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4495             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4496           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4497         return XEXP (x, 0);
4498       break;
4499 #endif
4500
4501     case CONST:
4502       /* (const (const X)) can become (const X).  Do it this way rather than
4503          returning the inner CONST since CONST can be shared with a
4504          REG_EQUAL note.  */
4505       if (GET_CODE (XEXP (x, 0)) == CONST)
4506         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4507       break;
4508
4509 #ifdef HAVE_lo_sum
4510     case LO_SUM:
4511       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4512          can add in an offset.  find_split_point will split this address up
4513          again if it doesn't match.  */
4514       if (GET_CODE (XEXP (x, 0)) == HIGH
4515           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4516         return XEXP (x, 1);
4517       break;
4518 #endif
4519
4520     case PLUS:
4521       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4522          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4523          bit-field and can be replaced by either a sign_extend or a
4524          sign_extract.  The `and' may be a zero_extend and the two
4525          <c>, -<c> constants may be reversed.  */
4526       if (GET_CODE (XEXP (x, 0)) == XOR
4527           && GET_CODE (XEXP (x, 1)) == CONST_INT
4528           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4529           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4530           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4531               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4532           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4533           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4534                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4535                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4536                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4537               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4538                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4539                       == (unsigned int) i + 1))))
4540         return simplify_shift_const
4541           (NULL_RTX, ASHIFTRT, mode,
4542            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4543                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4544                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4545            GET_MODE_BITSIZE (mode) - (i + 1));
4546
4547       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4548          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4549          the bitsize of the mode - 1.  This allows simplification of
4550          "a = (b & 8) == 0;"  */
4551       if (XEXP (x, 1) == constm1_rtx
4552           && !REG_P (XEXP (x, 0))
4553           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4554                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4555           && nonzero_bits (XEXP (x, 0), mode) == 1)
4556         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4557            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4558                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4559                                  GET_MODE_BITSIZE (mode) - 1),
4560            GET_MODE_BITSIZE (mode) - 1);
4561
4562       /* If we are adding two things that have no bits in common, convert
4563          the addition into an IOR.  This will often be further simplified,
4564          for example in cases like ((a & 1) + (a & 2)), which can
4565          become a & 3.  */
4566
4567       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4568           && (nonzero_bits (XEXP (x, 0), mode)
4569               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4570         {
4571           /* Try to simplify the expression further.  */
4572           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4573           temp = combine_simplify_rtx (tor, mode, in_dest);
4574
4575           /* If we could, great.  If not, do not go ahead with the IOR
4576              replacement, since PLUS appears in many special purpose
4577              address arithmetic instructions.  */
4578           if (GET_CODE (temp) != CLOBBER && temp != tor)
4579             return temp;
4580         }
4581       break;
4582
4583     case MINUS:
4584       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4585          (and <foo> (const_int pow2-1))  */
4586       if (GET_CODE (XEXP (x, 1)) == AND
4587           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4588           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4589           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4590         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4591                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4592       break;
4593
4594     case MULT:
4595       /* If we have (mult (plus A B) C), apply the distributive law and then
4596          the inverse distributive law to see if things simplify.  This
4597          occurs mostly in addresses, often when unrolling loops.  */
4598
4599       if (GET_CODE (XEXP (x, 0)) == PLUS)
4600         {
4601           rtx result = distribute_and_simplify_rtx (x, 0);
4602           if (result)
4603             return result;
4604         }
4605
4606       /* Try simplify a*(b/c) as (a*b)/c.  */
4607       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4608           && GET_CODE (XEXP (x, 0)) == DIV)
4609         {
4610           rtx tem = simplify_binary_operation (MULT, mode,
4611                                                XEXP (XEXP (x, 0), 0),
4612                                                XEXP (x, 1));
4613           if (tem)
4614             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4615         }
4616       break;
4617
4618     case UDIV:
4619       /* If this is a divide by a power of two, treat it as a shift if
4620          its first operand is a shift.  */
4621       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4622           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4623           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4624               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4625               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4626               || GET_CODE (XEXP (x, 0)) == ROTATE
4627               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4628         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4629       break;
4630
4631     case EQ:  case NE:
4632     case GT:  case GTU:  case GE:  case GEU:
4633     case LT:  case LTU:  case LE:  case LEU:
4634     case UNEQ:  case LTGT:
4635     case UNGT:  case UNGE:
4636     case UNLT:  case UNLE:
4637     case UNORDERED: case ORDERED:
4638       /* If the first operand is a condition code, we can't do anything
4639          with it.  */
4640       if (GET_CODE (XEXP (x, 0)) == COMPARE
4641           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4642               && ! CC0_P (XEXP (x, 0))))
4643         {
4644           rtx op0 = XEXP (x, 0);
4645           rtx op1 = XEXP (x, 1);
4646           enum rtx_code new_code;
4647
4648           if (GET_CODE (op0) == COMPARE)
4649             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4650
4651           /* Simplify our comparison, if possible.  */
4652           new_code = simplify_comparison (code, &op0, &op1);
4653
4654           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4655              if only the low-order bit is possibly nonzero in X (such as when
4656              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4657              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4658              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4659              (plus X 1).
4660
4661              Remove any ZERO_EXTRACT we made when thinking this was a
4662              comparison.  It may now be simpler to use, e.g., an AND.  If a
4663              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4664              the call to make_compound_operation in the SET case.  */
4665
4666           if (STORE_FLAG_VALUE == 1
4667               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4668               && op1 == const0_rtx
4669               && mode == GET_MODE (op0)
4670               && nonzero_bits (op0, mode) == 1)
4671             return gen_lowpart (mode,
4672                                 expand_compound_operation (op0));
4673
4674           else if (STORE_FLAG_VALUE == 1
4675                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4676                    && op1 == const0_rtx
4677                    && mode == GET_MODE (op0)
4678                    && (num_sign_bit_copies (op0, mode)
4679                        == GET_MODE_BITSIZE (mode)))
4680             {
4681               op0 = expand_compound_operation (op0);
4682               return simplify_gen_unary (NEG, mode,
4683                                          gen_lowpart (mode, op0),
4684                                          mode);
4685             }
4686
4687           else if (STORE_FLAG_VALUE == 1
4688                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4689                    && op1 == const0_rtx
4690                    && mode == GET_MODE (op0)
4691                    && nonzero_bits (op0, mode) == 1)
4692             {
4693               op0 = expand_compound_operation (op0);
4694               return simplify_gen_binary (XOR, mode,
4695                                           gen_lowpart (mode, op0),
4696                                           const1_rtx);
4697             }
4698
4699           else if (STORE_FLAG_VALUE == 1
4700                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4701                    && op1 == const0_rtx
4702                    && mode == GET_MODE (op0)
4703                    && (num_sign_bit_copies (op0, mode)
4704                        == GET_MODE_BITSIZE (mode)))
4705             {
4706               op0 = expand_compound_operation (op0);
4707               return plus_constant (gen_lowpart (mode, op0), 1);
4708             }
4709
4710           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4711              those above.  */
4712           if (STORE_FLAG_VALUE == -1
4713               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4714               && op1 == const0_rtx
4715               && (num_sign_bit_copies (op0, mode)
4716                   == GET_MODE_BITSIZE (mode)))
4717             return gen_lowpart (mode,
4718                                 expand_compound_operation (op0));
4719
4720           else if (STORE_FLAG_VALUE == -1
4721                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4722                    && op1 == const0_rtx
4723                    && mode == GET_MODE (op0)
4724                    && nonzero_bits (op0, mode) == 1)
4725             {
4726               op0 = expand_compound_operation (op0);
4727               return simplify_gen_unary (NEG, mode,
4728                                          gen_lowpart (mode, op0),
4729                                          mode);
4730             }
4731
4732           else if (STORE_FLAG_VALUE == -1
4733                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4734                    && op1 == const0_rtx
4735                    && mode == GET_MODE (op0)
4736                    && (num_sign_bit_copies (op0, mode)
4737                        == GET_MODE_BITSIZE (mode)))
4738             {
4739               op0 = expand_compound_operation (op0);
4740               return simplify_gen_unary (NOT, mode,
4741                                          gen_lowpart (mode, op0),
4742                                          mode);
4743             }
4744
4745           /* If X is 0/1, (eq X 0) is X-1.  */
4746           else if (STORE_FLAG_VALUE == -1
4747                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4748                    && op1 == const0_rtx
4749                    && mode == GET_MODE (op0)
4750                    && nonzero_bits (op0, mode) == 1)
4751             {
4752               op0 = expand_compound_operation (op0);
4753               return plus_constant (gen_lowpart (mode, op0), -1);
4754             }
4755
4756           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4757              one bit that might be nonzero, we can convert (ne x 0) to
4758              (ashift x c) where C puts the bit in the sign bit.  Remove any
4759              AND with STORE_FLAG_VALUE when we are done, since we are only
4760              going to test the sign bit.  */
4761           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4762               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4763               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4764                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4765               && op1 == const0_rtx
4766               && mode == GET_MODE (op0)
4767               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4768             {
4769               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4770                                         expand_compound_operation (op0),
4771                                         GET_MODE_BITSIZE (mode) - 1 - i);
4772               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4773                 return XEXP (x, 0);
4774               else
4775                 return x;
4776             }
4777
4778           /* If the code changed, return a whole new comparison.  */
4779           if (new_code != code)
4780             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4781
4782           /* Otherwise, keep this operation, but maybe change its operands.
4783              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4784           SUBST (XEXP (x, 0), op0);
4785           SUBST (XEXP (x, 1), op1);
4786         }
4787       break;
4788
4789     case IF_THEN_ELSE:
4790       return simplify_if_then_else (x);
4791
4792     case ZERO_EXTRACT:
4793     case SIGN_EXTRACT:
4794     case ZERO_EXTEND:
4795     case SIGN_EXTEND:
4796       /* If we are processing SET_DEST, we are done.  */
4797       if (in_dest)
4798         return x;
4799
4800       return expand_compound_operation (x);
4801
4802     case SET:
4803       return simplify_set (x);
4804
4805     case AND:
4806     case IOR:
4807       return simplify_logical (x);
4808
4809     case ASHIFT:
4810     case LSHIFTRT:
4811     case ASHIFTRT:
4812     case ROTATE:
4813     case ROTATERT:
4814       /* If this is a shift by a constant amount, simplify it.  */
4815       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4816         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4817                                      INTVAL (XEXP (x, 1)));
4818
4819       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4820         SUBST (XEXP (x, 1),
4821                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4822                               ((HOST_WIDE_INT) 1
4823                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4824                               - 1,
4825                               0));
4826       break;
4827
4828     default:
4829       break;
4830     }
4831
4832   return x;
4833 }
4834 \f
4835 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4836
4837 static rtx
4838 simplify_if_then_else (rtx x)
4839 {
4840   enum machine_mode mode = GET_MODE (x);
4841   rtx cond = XEXP (x, 0);
4842   rtx true_rtx = XEXP (x, 1);
4843   rtx false_rtx = XEXP (x, 2);
4844   enum rtx_code true_code = GET_CODE (cond);
4845   int comparison_p = COMPARISON_P (cond);
4846   rtx temp;
4847   int i;
4848   enum rtx_code false_code;
4849   rtx reversed;
4850
4851   /* Simplify storing of the truth value.  */
4852   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4853     return simplify_gen_relational (true_code, mode, VOIDmode,
4854                                     XEXP (cond, 0), XEXP (cond, 1));
4855
4856   /* Also when the truth value has to be reversed.  */
4857   if (comparison_p
4858       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4859       && (reversed = reversed_comparison (cond, mode)))
4860     return reversed;
4861
4862   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4863      in it is being compared against certain values.  Get the true and false
4864      comparisons and see if that says anything about the value of each arm.  */
4865
4866   if (comparison_p
4867       && ((false_code = reversed_comparison_code (cond, NULL))
4868           != UNKNOWN)
4869       && REG_P (XEXP (cond, 0)))
4870     {
4871       HOST_WIDE_INT nzb;
4872       rtx from = XEXP (cond, 0);
4873       rtx true_val = XEXP (cond, 1);
4874       rtx false_val = true_val;
4875       int swapped = 0;
4876
4877       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4878
4879       if (false_code == EQ)
4880         {
4881           swapped = 1, true_code = EQ, false_code = NE;
4882           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4883         }
4884
4885       /* If we are comparing against zero and the expression being tested has
4886          only a single bit that might be nonzero, that is its value when it is
4887          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4888
4889       if (true_code == EQ && true_val == const0_rtx
4890           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4891         false_code = EQ, false_val = GEN_INT (nzb);
4892       else if (true_code == EQ && true_val == const0_rtx
4893                && (num_sign_bit_copies (from, GET_MODE (from))
4894                    == GET_MODE_BITSIZE (GET_MODE (from))))
4895         false_code = EQ, false_val = constm1_rtx;
4896
4897       /* Now simplify an arm if we know the value of the register in the
4898          branch and it is used in the arm.  Be careful due to the potential
4899          of locally-shared RTL.  */
4900
4901       if (reg_mentioned_p (from, true_rtx))
4902         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4903                                       from, true_val),
4904                       pc_rtx, pc_rtx, 0, 0);
4905       if (reg_mentioned_p (from, false_rtx))
4906         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4907                                    from, false_val),
4908                        pc_rtx, pc_rtx, 0, 0);
4909
4910       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4911       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4912
4913       true_rtx = XEXP (x, 1);
4914       false_rtx = XEXP (x, 2);
4915       true_code = GET_CODE (cond);
4916     }
4917
4918   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4919      reversed, do so to avoid needing two sets of patterns for
4920      subtract-and-branch insns.  Similarly if we have a constant in the true
4921      arm, the false arm is the same as the first operand of the comparison, or
4922      the false arm is more complicated than the true arm.  */
4923
4924   if (comparison_p
4925       && reversed_comparison_code (cond, NULL) != UNKNOWN
4926       && (true_rtx == pc_rtx
4927           || (CONSTANT_P (true_rtx)
4928               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4929           || true_rtx == const0_rtx
4930           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4931           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4932               && !OBJECT_P (false_rtx))
4933           || reg_mentioned_p (true_rtx, false_rtx)
4934           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4935     {
4936       true_code = reversed_comparison_code (cond, NULL);
4937       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4938       SUBST (XEXP (x, 1), false_rtx);
4939       SUBST (XEXP (x, 2), true_rtx);
4940
4941       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4942       cond = XEXP (x, 0);
4943
4944       /* It is possible that the conditional has been simplified out.  */
4945       true_code = GET_CODE (cond);
4946       comparison_p = COMPARISON_P (cond);
4947     }
4948
4949   /* If the two arms are identical, we don't need the comparison.  */
4950
4951   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4952     return true_rtx;
4953
4954   /* Convert a == b ? b : a to "a".  */
4955   if (true_code == EQ && ! side_effects_p (cond)
4956       && !HONOR_NANS (mode)
4957       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4958       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4959     return false_rtx;
4960   else if (true_code == NE && ! side_effects_p (cond)
4961            && !HONOR_NANS (mode)
4962            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4963            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4964     return true_rtx;
4965
4966   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4967
4968   if (GET_MODE_CLASS (mode) == MODE_INT
4969       && GET_CODE (false_rtx) == NEG
4970       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4971       && comparison_p
4972       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4973       && ! side_effects_p (true_rtx))
4974     switch (true_code)
4975       {
4976       case GT:
4977       case GE:
4978         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4979       case LT:
4980       case LE:
4981         return
4982           simplify_gen_unary (NEG, mode,
4983                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4984                               mode);
4985       default:
4986         break;
4987       }
4988
4989   /* Look for MIN or MAX.  */
4990
4991   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4992       && comparison_p
4993       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4994       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4995       && ! side_effects_p (cond))
4996     switch (true_code)
4997       {
4998       case GE:
4999       case GT:
5000         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5001       case LE:
5002       case LT:
5003         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5004       case GEU:
5005       case GTU:
5006         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5007       case LEU:
5008       case LTU:
5009         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5010       default:
5011         break;
5012       }
5013
5014   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5015      second operand is zero, this can be done as (OP Z (mult COND C2)) where
5016      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5017      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5018      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5019      neither 1 or -1, but it isn't worth checking for.  */
5020
5021   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5022       && comparison_p
5023       && GET_MODE_CLASS (mode) == MODE_INT
5024       && ! side_effects_p (x))
5025     {
5026       rtx t = make_compound_operation (true_rtx, SET);
5027       rtx f = make_compound_operation (false_rtx, SET);
5028       rtx cond_op0 = XEXP (cond, 0);
5029       rtx cond_op1 = XEXP (cond, 1);
5030       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5031       enum machine_mode m = mode;
5032       rtx z = 0, c1 = NULL_RTX;
5033
5034       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5035            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5036            || GET_CODE (t) == ASHIFT
5037            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5038           && rtx_equal_p (XEXP (t, 0), f))
5039         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5040
5041       /* If an identity-zero op is commutative, check whether there
5042          would be a match if we swapped the operands.  */
5043       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5044                 || GET_CODE (t) == XOR)
5045                && rtx_equal_p (XEXP (t, 1), f))
5046         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5047       else if (GET_CODE (t) == SIGN_EXTEND
5048                && (GET_CODE (XEXP (t, 0)) == PLUS
5049                    || GET_CODE (XEXP (t, 0)) == MINUS
5050                    || GET_CODE (XEXP (t, 0)) == IOR
5051                    || GET_CODE (XEXP (t, 0)) == XOR
5052                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5053                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5054                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5055                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5056                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5057                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5058                && (num_sign_bit_copies (f, GET_MODE (f))
5059                    > (unsigned int)
5060                      (GET_MODE_BITSIZE (mode)
5061                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5062         {
5063           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5064           extend_op = SIGN_EXTEND;
5065           m = GET_MODE (XEXP (t, 0));
5066         }
5067       else if (GET_CODE (t) == SIGN_EXTEND
5068                && (GET_CODE (XEXP (t, 0)) == PLUS
5069                    || GET_CODE (XEXP (t, 0)) == IOR
5070                    || GET_CODE (XEXP (t, 0)) == XOR)
5071                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5072                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5073                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5074                && (num_sign_bit_copies (f, GET_MODE (f))
5075                    > (unsigned int)
5076                      (GET_MODE_BITSIZE (mode)
5077                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5078         {
5079           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5080           extend_op = SIGN_EXTEND;
5081           m = GET_MODE (XEXP (t, 0));
5082         }
5083       else if (GET_CODE (t) == ZERO_EXTEND
5084                && (GET_CODE (XEXP (t, 0)) == PLUS
5085                    || GET_CODE (XEXP (t, 0)) == MINUS
5086                    || GET_CODE (XEXP (t, 0)) == IOR
5087                    || GET_CODE (XEXP (t, 0)) == XOR
5088                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5089                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5090                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5091                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5092                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5093                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5094                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5095                && ((nonzero_bits (f, GET_MODE (f))
5096                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5097                    == 0))
5098         {
5099           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5100           extend_op = ZERO_EXTEND;
5101           m = GET_MODE (XEXP (t, 0));
5102         }
5103       else if (GET_CODE (t) == ZERO_EXTEND
5104                && (GET_CODE (XEXP (t, 0)) == PLUS
5105                    || GET_CODE (XEXP (t, 0)) == IOR
5106                    || GET_CODE (XEXP (t, 0)) == XOR)
5107                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5108                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5109                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5110                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5111                && ((nonzero_bits (f, GET_MODE (f))
5112                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5113                    == 0))
5114         {
5115           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5116           extend_op = ZERO_EXTEND;
5117           m = GET_MODE (XEXP (t, 0));
5118         }
5119
5120       if (z)
5121         {
5122           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5123                                                  cond_op0, cond_op1),
5124                         pc_rtx, pc_rtx, 0, 0);
5125           temp = simplify_gen_binary (MULT, m, temp,
5126                                       simplify_gen_binary (MULT, m, c1,
5127                                                            const_true_rtx));
5128           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5129           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5130
5131           if (extend_op != UNKNOWN)
5132             temp = simplify_gen_unary (extend_op, mode, temp, m);
5133
5134           return temp;
5135         }
5136     }
5137
5138   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5139      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5140      negation of a single bit, we can convert this operation to a shift.  We
5141      can actually do this more generally, but it doesn't seem worth it.  */
5142
5143   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5144       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5145       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5146            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5147           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5148                == GET_MODE_BITSIZE (mode))
5149               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5150     return
5151       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5152                             gen_lowpart (mode, XEXP (cond, 0)), i);
5153
5154   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5155   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5156       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5157       && GET_MODE (XEXP (cond, 0)) == mode
5158       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5159           == nonzero_bits (XEXP (cond, 0), mode)
5160       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5161     return XEXP (cond, 0);
5162
5163   return x;
5164 }
5165 \f
5166 /* Simplify X, a SET expression.  Return the new expression.  */
5167
5168 static rtx
5169 simplify_set (rtx x)
5170 {
5171   rtx src = SET_SRC (x);
5172   rtx dest = SET_DEST (x);
5173   enum machine_mode mode
5174     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5175   rtx other_insn;
5176   rtx *cc_use;
5177
5178   /* (set (pc) (return)) gets written as (return).  */
5179   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5180     return src;
5181
5182   /* Now that we know for sure which bits of SRC we are using, see if we can
5183      simplify the expression for the object knowing that we only need the
5184      low-order bits.  */
5185
5186   if (GET_MODE_CLASS (mode) == MODE_INT
5187       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5188     {
5189       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5190       SUBST (SET_SRC (x), src);
5191     }
5192
5193   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5194      the comparison result and try to simplify it unless we already have used
5195      undobuf.other_insn.  */
5196   if ((GET_MODE_CLASS (mode) == MODE_CC
5197        || GET_CODE (src) == COMPARE
5198        || CC0_P (dest))
5199       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5200       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5201       && COMPARISON_P (*cc_use)
5202       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5203     {
5204       enum rtx_code old_code = GET_CODE (*cc_use);
5205       enum rtx_code new_code;
5206       rtx op0, op1, tmp;
5207       int other_changed = 0;
5208       enum machine_mode compare_mode = GET_MODE (dest);
5209
5210       if (GET_CODE (src) == COMPARE)
5211         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5212       else
5213         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5214
5215       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5216                                            op0, op1);
5217       if (!tmp)
5218         new_code = old_code;
5219       else if (!CONSTANT_P (tmp))
5220         {
5221           new_code = GET_CODE (tmp);
5222           op0 = XEXP (tmp, 0);
5223           op1 = XEXP (tmp, 1);
5224         }
5225       else
5226         {
5227           rtx pat = PATTERN (other_insn);
5228           undobuf.other_insn = other_insn;
5229           SUBST (*cc_use, tmp);
5230
5231           /* Attempt to simplify CC user.  */
5232           if (GET_CODE (pat) == SET)
5233             {
5234               rtx new = simplify_rtx (SET_SRC (pat));
5235               if (new != NULL_RTX)
5236                 SUBST (SET_SRC (pat), new);
5237             }
5238
5239           /* Convert X into a no-op move.  */
5240           SUBST (SET_DEST (x), pc_rtx);
5241           SUBST (SET_SRC (x), pc_rtx);
5242           return x;
5243         }
5244
5245       /* Simplify our comparison, if possible.  */
5246       new_code = simplify_comparison (new_code, &op0, &op1);
5247
5248 #ifdef SELECT_CC_MODE
5249       /* If this machine has CC modes other than CCmode, check to see if we
5250          need to use a different CC mode here.  */
5251       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5252         compare_mode = GET_MODE (op0);
5253       else
5254         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5255
5256 #ifndef HAVE_cc0
5257       /* If the mode changed, we have to change SET_DEST, the mode in the
5258          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5259          a hard register, just build new versions with the proper mode.  If it
5260          is a pseudo, we lose unless it is only time we set the pseudo, in
5261          which case we can safely change its mode.  */
5262       if (compare_mode != GET_MODE (dest))
5263         {
5264           if (can_change_dest_mode (dest, 0, compare_mode))
5265             {
5266               unsigned int regno = REGNO (dest);
5267               rtx new_dest;
5268
5269               if (regno < FIRST_PSEUDO_REGISTER)
5270                 new_dest = gen_rtx_REG (compare_mode, regno);
5271               else
5272                 {
5273                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5274                   new_dest = regno_reg_rtx[regno];
5275                 }
5276
5277               SUBST (SET_DEST (x), new_dest);
5278               SUBST (XEXP (*cc_use, 0), new_dest);
5279               other_changed = 1;
5280
5281               dest = new_dest;
5282             }
5283         }
5284 #endif  /* cc0 */
5285 #endif  /* SELECT_CC_MODE */
5286
5287       /* If the code changed, we have to build a new comparison in
5288          undobuf.other_insn.  */
5289       if (new_code != old_code)
5290         {
5291           int other_changed_previously = other_changed;
5292           unsigned HOST_WIDE_INT mask;
5293
5294           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5295                                           dest, const0_rtx));
5296           other_changed = 1;
5297
5298           /* If the only change we made was to change an EQ into an NE or
5299              vice versa, OP0 has only one bit that might be nonzero, and OP1
5300              is zero, check if changing the user of the condition code will
5301              produce a valid insn.  If it won't, we can keep the original code
5302              in that insn by surrounding our operation with an XOR.  */
5303
5304           if (((old_code == NE && new_code == EQ)
5305                || (old_code == EQ && new_code == NE))
5306               && ! other_changed_previously && op1 == const0_rtx
5307               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5308               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5309             {
5310               rtx pat = PATTERN (other_insn), note = 0;
5311
5312               if ((recog_for_combine (&pat, other_insn, &note) < 0
5313                    && ! check_asm_operands (pat)))
5314                 {
5315                   PUT_CODE (*cc_use, old_code);
5316                   other_changed = 0;
5317
5318                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5319                                              op0, GEN_INT (mask));
5320                 }
5321             }
5322         }
5323
5324       if (other_changed)
5325         undobuf.other_insn = other_insn;
5326
5327 #ifdef HAVE_cc0
5328       /* If we are now comparing against zero, change our source if
5329          needed.  If we do not use cc0, we always have a COMPARE.  */
5330       if (op1 == const0_rtx && dest == cc0_rtx)
5331         {
5332           SUBST (SET_SRC (x), op0);
5333           src = op0;
5334         }
5335       else
5336 #endif
5337
5338       /* Otherwise, if we didn't previously have a COMPARE in the
5339          correct mode, we need one.  */
5340       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5341         {
5342           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5343           src = SET_SRC (x);
5344         }
5345       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5346         {
5347           SUBST(SET_SRC (x), op0);
5348           src = SET_SRC (x);
5349         }
5350       else
5351         {
5352           /* Otherwise, update the COMPARE if needed.  */
5353           SUBST (XEXP (src, 0), op0);
5354           SUBST (XEXP (src, 1), op1);
5355         }
5356     }
5357   else
5358     {
5359       /* Get SET_SRC in a form where we have placed back any
5360          compound expressions.  Then do the checks below.  */
5361       src = make_compound_operation (src, SET);
5362       SUBST (SET_SRC (x), src);
5363     }
5364
5365   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5366      and X being a REG or (subreg (reg)), we may be able to convert this to
5367      (set (subreg:m2 x) (op)).
5368
5369      We can always do this if M1 is narrower than M2 because that means that
5370      we only care about the low bits of the result.
5371
5372      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5373      perform a narrower operation than requested since the high-order bits will
5374      be undefined.  On machine where it is defined, this transformation is safe
5375      as long as M1 and M2 have the same number of words.  */
5376
5377   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5378       && !OBJECT_P (SUBREG_REG (src))
5379       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5380            / UNITS_PER_WORD)
5381           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5382                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5383 #ifndef WORD_REGISTER_OPERATIONS
5384       && (GET_MODE_SIZE (GET_MODE (src))
5385         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5386 #endif
5387 #ifdef CANNOT_CHANGE_MODE_CLASS
5388       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5389             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5390                                          GET_MODE (SUBREG_REG (src)),
5391                                          GET_MODE (src)))
5392 #endif
5393       && (REG_P (dest)
5394           || (GET_CODE (dest) == SUBREG
5395               && REG_P (SUBREG_REG (dest)))))
5396     {
5397       SUBST (SET_DEST (x),
5398              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5399                                       dest));
5400       SUBST (SET_SRC (x), SUBREG_REG (src));
5401
5402       src = SET_SRC (x), dest = SET_DEST (x);
5403     }
5404
5405 #ifdef HAVE_cc0
5406   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5407      in SRC.  */
5408   if (dest == cc0_rtx
5409       && GET_CODE (src) == SUBREG
5410       && subreg_lowpart_p (src)
5411       && (GET_MODE_BITSIZE (GET_MODE (src))
5412           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5413     {
5414       rtx inner = SUBREG_REG (src);
5415       enum machine_mode inner_mode = GET_MODE (inner);
5416
5417       /* Here we make sure that we don't have a sign bit on.  */
5418       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5419           && (nonzero_bits (inner, inner_mode)
5420               < ((unsigned HOST_WIDE_INT) 1
5421                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5422         {
5423           SUBST (SET_SRC (x), inner);
5424           src = SET_SRC (x);
5425         }
5426     }
5427 #endif
5428
5429 #ifdef LOAD_EXTEND_OP
5430   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5431      would require a paradoxical subreg.  Replace the subreg with a
5432      zero_extend to avoid the reload that would otherwise be required.  */
5433
5434   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5435       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5436       && SUBREG_BYTE (src) == 0
5437       && (GET_MODE_SIZE (GET_MODE (src))
5438           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5439       && MEM_P (SUBREG_REG (src)))
5440     {
5441       SUBST (SET_SRC (x),
5442              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5443                             GET_MODE (src), SUBREG_REG (src)));
5444
5445       src = SET_SRC (x);
5446     }
5447 #endif
5448
5449   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5450      are comparing an item known to be 0 or -1 against 0, use a logical
5451      operation instead. Check for one of the arms being an IOR of the other
5452      arm with some value.  We compute three terms to be IOR'ed together.  In
5453      practice, at most two will be nonzero.  Then we do the IOR's.  */
5454
5455   if (GET_CODE (dest) != PC
5456       && GET_CODE (src) == IF_THEN_ELSE
5457       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5458       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5459       && XEXP (XEXP (src, 0), 1) == const0_rtx
5460       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5461 #ifdef HAVE_conditional_move
5462       && ! can_conditionally_move_p (GET_MODE (src))
5463 #endif
5464       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5465                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5466           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5467       && ! side_effects_p (src))
5468     {
5469       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5470                       ? XEXP (src, 1) : XEXP (src, 2));
5471       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5472                    ? XEXP (src, 2) : XEXP (src, 1));
5473       rtx term1 = const0_rtx, term2, term3;
5474
5475       if (GET_CODE (true_rtx) == IOR
5476           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5477         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5478       else if (GET_CODE (true_rtx) == IOR
5479                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5480         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5481       else if (GET_CODE (false_rtx) == IOR
5482                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5483         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5484       else if (GET_CODE (false_rtx) == IOR
5485                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5486         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5487
5488       term2 = simplify_gen_binary (AND, GET_MODE (src),
5489                                    XEXP (XEXP (src, 0), 0), true_rtx);
5490       term3 = simplify_gen_binary (AND, GET_MODE (src),
5491                                    simplify_gen_unary (NOT, GET_MODE (src),
5492                                                        XEXP (XEXP (src, 0), 0),
5493                                                        GET_MODE (src)),
5494                                    false_rtx);
5495
5496       SUBST (SET_SRC (x),
5497              simplify_gen_binary (IOR, GET_MODE (src),
5498                                   simplify_gen_binary (IOR, GET_MODE (src),
5499                                                        term1, term2),
5500                                   term3));
5501
5502       src = SET_SRC (x);
5503     }
5504
5505   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5506      whole thing fail.  */
5507   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5508     return src;
5509   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5510     return dest;
5511   else
5512     /* Convert this into a field assignment operation, if possible.  */
5513     return make_field_assignment (x);
5514 }
5515 \f
5516 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5517    result.  */
5518
5519 static rtx
5520 simplify_logical (rtx x)
5521 {
5522   enum machine_mode mode = GET_MODE (x);
5523   rtx op0 = XEXP (x, 0);
5524   rtx op1 = XEXP (x, 1);
5525
5526   switch (GET_CODE (x))
5527     {
5528     case AND:
5529       /* We can call simplify_and_const_int only if we don't lose
5530          any (sign) bits when converting INTVAL (op1) to
5531          "unsigned HOST_WIDE_INT".  */
5532       if (GET_CODE (op1) == CONST_INT
5533           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5534               || INTVAL (op1) > 0))
5535         {
5536           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5537           if (GET_CODE (x) != AND)
5538             return x;
5539
5540           op0 = XEXP (x, 0);
5541           op1 = XEXP (x, 1);
5542         }
5543
5544       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5545          apply the distributive law and then the inverse distributive
5546          law to see if things simplify.  */
5547       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5548         {
5549           rtx result = distribute_and_simplify_rtx (x, 0);
5550           if (result)
5551             return result;
5552         }
5553       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5554         {
5555           rtx result = distribute_and_simplify_rtx (x, 1);
5556           if (result)
5557             return result;
5558         }
5559       break;
5560
5561     case IOR:
5562       /* If we have (ior (and A B) C), apply the distributive law and then
5563          the inverse distributive law to see if things simplify.  */
5564
5565       if (GET_CODE (op0) == AND)
5566         {
5567           rtx result = distribute_and_simplify_rtx (x, 0);
5568           if (result)
5569             return result;
5570         }
5571
5572       if (GET_CODE (op1) == AND)
5573         {
5574           rtx result = distribute_and_simplify_rtx (x, 1);
5575           if (result)
5576             return result;
5577         }
5578       break;
5579
5580     default:
5581       gcc_unreachable ();
5582     }
5583
5584   return x;
5585 }
5586 \f
5587 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5588    operations" because they can be replaced with two more basic operations.
5589    ZERO_EXTEND is also considered "compound" because it can be replaced with
5590    an AND operation, which is simpler, though only one operation.
5591
5592    The function expand_compound_operation is called with an rtx expression
5593    and will convert it to the appropriate shifts and AND operations,
5594    simplifying at each stage.
5595
5596    The function make_compound_operation is called to convert an expression
5597    consisting of shifts and ANDs into the equivalent compound expression.
5598    It is the inverse of this function, loosely speaking.  */
5599
5600 static rtx
5601 expand_compound_operation (rtx x)
5602 {
5603   unsigned HOST_WIDE_INT pos = 0, len;
5604   int unsignedp = 0;
5605   unsigned int modewidth;
5606   rtx tem;
5607
5608   switch (GET_CODE (x))
5609     {
5610     case ZERO_EXTEND:
5611       unsignedp = 1;
5612     case SIGN_EXTEND:
5613       /* We can't necessarily use a const_int for a multiword mode;
5614          it depends on implicitly extending the value.
5615          Since we don't know the right way to extend it,
5616          we can't tell whether the implicit way is right.
5617
5618          Even for a mode that is no wider than a const_int,
5619          we can't win, because we need to sign extend one of its bits through
5620          the rest of it, and we don't know which bit.  */
5621       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5622         return x;
5623
5624       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5625          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5626          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5627          reloaded. If not for that, MEM's would very rarely be safe.
5628
5629          Reject MODEs bigger than a word, because we might not be able
5630          to reference a two-register group starting with an arbitrary register
5631          (and currently gen_lowpart might crash for a SUBREG).  */
5632
5633       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5634         return x;
5635
5636       /* Reject MODEs that aren't scalar integers because turning vector
5637          or complex modes into shifts causes problems.  */
5638
5639       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5640         return x;
5641
5642       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5643       /* If the inner object has VOIDmode (the only way this can happen
5644          is if it is an ASM_OPERANDS), we can't do anything since we don't
5645          know how much masking to do.  */
5646       if (len == 0)
5647         return x;
5648
5649       break;
5650
5651     case ZERO_EXTRACT:
5652       unsignedp = 1;
5653
5654       /* ... fall through ...  */
5655
5656     case SIGN_EXTRACT:
5657       /* If the operand is a CLOBBER, just return it.  */
5658       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5659         return XEXP (x, 0);
5660
5661       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5662           || GET_CODE (XEXP (x, 2)) != CONST_INT
5663           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5664         return x;
5665
5666       /* Reject MODEs that aren't scalar integers because turning vector
5667          or complex modes into shifts causes problems.  */
5668
5669       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5670         return x;
5671
5672       len = INTVAL (XEXP (x, 1));
5673       pos = INTVAL (XEXP (x, 2));
5674
5675       /* This should stay within the object being extracted, fail otherwise.  */
5676       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5677         return x;
5678
5679       if (BITS_BIG_ENDIAN)
5680         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5681
5682       break;
5683
5684     default:
5685       return x;
5686     }
5687   /* Convert sign extension to zero extension, if we know that the high
5688      bit is not set, as this is easier to optimize.  It will be converted
5689      back to cheaper alternative in make_extraction.  */
5690   if (GET_CODE (x) == SIGN_EXTEND
5691       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5692           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5693                 & ~(((unsigned HOST_WIDE_INT)
5694                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5695                      >> 1))
5696                == 0)))
5697     {
5698       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5699       rtx temp2 = expand_compound_operation (temp);
5700
5701       /* Make sure this is a profitable operation.  */
5702       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5703        return temp2;
5704       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5705        return temp;
5706       else
5707        return x;
5708     }
5709
5710   /* We can optimize some special cases of ZERO_EXTEND.  */
5711   if (GET_CODE (x) == ZERO_EXTEND)
5712     {
5713       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5714          know that the last value didn't have any inappropriate bits
5715          set.  */
5716       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5717           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5718           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5719           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5720               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5721         return XEXP (XEXP (x, 0), 0);
5722
5723       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5724       if (GET_CODE (XEXP (x, 0)) == SUBREG
5725           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5726           && subreg_lowpart_p (XEXP (x, 0))
5727           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5728           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5729               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5730         return SUBREG_REG (XEXP (x, 0));
5731
5732       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5733          is a comparison and STORE_FLAG_VALUE permits.  This is like
5734          the first case, but it works even when GET_MODE (x) is larger
5735          than HOST_WIDE_INT.  */
5736       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5737           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5738           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5739           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5740               <= HOST_BITS_PER_WIDE_INT)
5741           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5742               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5743         return XEXP (XEXP (x, 0), 0);
5744
5745       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5746       if (GET_CODE (XEXP (x, 0)) == SUBREG
5747           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5748           && subreg_lowpart_p (XEXP (x, 0))
5749           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5750           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5751               <= HOST_BITS_PER_WIDE_INT)
5752           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5753               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5754         return SUBREG_REG (XEXP (x, 0));
5755
5756     }
5757
5758   /* If we reach here, we want to return a pair of shifts.  The inner
5759      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5760      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5761      logical depending on the value of UNSIGNEDP.
5762
5763      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5764      converted into an AND of a shift.
5765
5766      We must check for the case where the left shift would have a negative
5767      count.  This can happen in a case like (x >> 31) & 255 on machines
5768      that can't shift by a constant.  On those machines, we would first
5769      combine the shift with the AND to produce a variable-position
5770      extraction.  Then the constant of 31 would be substituted in to produce
5771      a such a position.  */
5772
5773   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5774   if (modewidth + len >= pos)
5775     {
5776       enum machine_mode mode = GET_MODE (x);
5777       tem = gen_lowpart (mode, XEXP (x, 0));
5778       if (!tem || GET_CODE (tem) == CLOBBER)
5779         return x;
5780       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5781                                   tem, modewidth - pos - len);
5782       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5783                                   mode, tem, modewidth - len);
5784     }
5785   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5786     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5787                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5788                                                         GET_MODE (x),
5789                                                         XEXP (x, 0), pos),
5790                                   ((HOST_WIDE_INT) 1 << len) - 1);
5791   else
5792     /* Any other cases we can't handle.  */
5793     return x;
5794
5795   /* If we couldn't do this for some reason, return the original
5796      expression.  */
5797   if (GET_CODE (tem) == CLOBBER)
5798     return x;
5799
5800   return tem;
5801 }
5802 \f
5803 /* X is a SET which contains an assignment of one object into
5804    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5805    or certain SUBREGS). If possible, convert it into a series of
5806    logical operations.
5807
5808    We half-heartedly support variable positions, but do not at all
5809    support variable lengths.  */
5810
5811 static rtx
5812 expand_field_assignment (rtx x)
5813 {
5814   rtx inner;
5815   rtx pos;                      /* Always counts from low bit.  */
5816   int len;
5817   rtx mask, cleared, masked;
5818   enum machine_mode compute_mode;
5819
5820   /* Loop until we find something we can't simplify.  */
5821   while (1)
5822     {
5823       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5824           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5825         {
5826           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5827           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5828           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5829         }
5830       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5831                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5832         {
5833           inner = XEXP (SET_DEST (x), 0);
5834           len = INTVAL (XEXP (SET_DEST (x), 1));
5835           pos = XEXP (SET_DEST (x), 2);
5836
5837           /* A constant position should stay within the width of INNER.  */
5838           if (GET_CODE (pos) == CONST_INT
5839               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5840             break;
5841
5842           if (BITS_BIG_ENDIAN)
5843             {
5844               if (GET_CODE (pos) == CONST_INT)
5845                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5846                                - INTVAL (pos));
5847               else if (GET_CODE (pos) == MINUS
5848                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5849                        && (INTVAL (XEXP (pos, 1))
5850                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5851                 /* If position is ADJUST - X, new position is X.  */
5852                 pos = XEXP (pos, 0);
5853               else
5854                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5855                                            GEN_INT (GET_MODE_BITSIZE (
5856                                                     GET_MODE (inner))
5857                                                     - len),
5858                                            pos);
5859             }
5860         }
5861
5862       /* A SUBREG between two modes that occupy the same numbers of words
5863          can be done by moving the SUBREG to the source.  */
5864       else if (GET_CODE (SET_DEST (x)) == SUBREG
5865                /* We need SUBREGs to compute nonzero_bits properly.  */
5866                && nonzero_sign_valid
5867                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5868                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5869                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5870                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5871         {
5872           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5873                            gen_lowpart
5874                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5875                             SET_SRC (x)));
5876           continue;
5877         }
5878       else
5879         break;
5880
5881       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5882         inner = SUBREG_REG (inner);
5883
5884       compute_mode = GET_MODE (inner);
5885
5886       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5887       if (! SCALAR_INT_MODE_P (compute_mode))
5888         {
5889           enum machine_mode imode;
5890
5891           /* Don't do anything for vector or complex integral types.  */
5892           if (! FLOAT_MODE_P (compute_mode))
5893             break;
5894
5895           /* Try to find an integral mode to pun with.  */
5896           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5897           if (imode == BLKmode)
5898             break;
5899
5900           compute_mode = imode;
5901           inner = gen_lowpart (imode, inner);
5902         }
5903
5904       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5905       if (len >= HOST_BITS_PER_WIDE_INT)
5906         break;
5907
5908       /* Now compute the equivalent expression.  Make a copy of INNER
5909          for the SET_DEST in case it is a MEM into which we will substitute;
5910          we don't want shared RTL in that case.  */
5911       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5912       cleared = simplify_gen_binary (AND, compute_mode,
5913                                      simplify_gen_unary (NOT, compute_mode,
5914                                        simplify_gen_binary (ASHIFT,
5915                                                             compute_mode,
5916                                                             mask, pos),
5917                                        compute_mode),
5918                                      inner);
5919       masked = simplify_gen_binary (ASHIFT, compute_mode,
5920                                     simplify_gen_binary (
5921                                       AND, compute_mode,
5922                                       gen_lowpart (compute_mode, SET_SRC (x)),
5923                                       mask),
5924                                     pos);
5925
5926       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5927                        simplify_gen_binary (IOR, compute_mode,
5928                                             cleared, masked));
5929     }
5930
5931   return x;
5932 }
5933 \f
5934 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5935    it is an RTX that represents a variable starting position; otherwise,
5936    POS is the (constant) starting bit position (counted from the LSB).
5937
5938    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5939    signed reference.
5940
5941    IN_DEST is nonzero if this is a reference in the destination of a
5942    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5943    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5944    be used.
5945
5946    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5947    ZERO_EXTRACT should be built even for bits starting at bit 0.
5948
5949    MODE is the desired mode of the result (if IN_DEST == 0).
5950
5951    The result is an RTX for the extraction or NULL_RTX if the target
5952    can't handle it.  */
5953
5954 static rtx
5955 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5956                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5957                  int in_dest, int in_compare)
5958 {
5959   /* This mode describes the size of the storage area
5960      to fetch the overall value from.  Within that, we
5961      ignore the POS lowest bits, etc.  */
5962   enum machine_mode is_mode = GET_MODE (inner);
5963   enum machine_mode inner_mode;
5964   enum machine_mode wanted_inner_mode;
5965   enum machine_mode wanted_inner_reg_mode = word_mode;
5966   enum machine_mode pos_mode = word_mode;
5967   enum machine_mode extraction_mode = word_mode;
5968   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5969   rtx new = 0;
5970   rtx orig_pos_rtx = pos_rtx;
5971   HOST_WIDE_INT orig_pos;
5972
5973   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5974     {
5975       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5976          consider just the QI as the memory to extract from.
5977          The subreg adds or removes high bits; its mode is
5978          irrelevant to the meaning of this extraction,
5979          since POS and LEN count from the lsb.  */
5980       if (MEM_P (SUBREG_REG (inner)))
5981         is_mode = GET_MODE (SUBREG_REG (inner));
5982       inner = SUBREG_REG (inner);
5983     }
5984   else if (GET_CODE (inner) == ASHIFT
5985            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5986            && pos_rtx == 0 && pos == 0
5987            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5988     {
5989       /* We're extracting the least significant bits of an rtx
5990          (ashift X (const_int C)), where LEN > C.  Extract the
5991          least significant (LEN - C) bits of X, giving an rtx
5992          whose mode is MODE, then shift it left C times.  */
5993       new = make_extraction (mode, XEXP (inner, 0),
5994                              0, 0, len - INTVAL (XEXP (inner, 1)),
5995                              unsignedp, in_dest, in_compare);
5996       if (new != 0)
5997         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5998     }
5999
6000   inner_mode = GET_MODE (inner);
6001
6002   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6003     pos = INTVAL (pos_rtx), pos_rtx = 0;
6004
6005   /* See if this can be done without an extraction.  We never can if the
6006      width of the field is not the same as that of some integer mode. For
6007      registers, we can only avoid the extraction if the position is at the
6008      low-order bit and this is either not in the destination or we have the
6009      appropriate STRICT_LOW_PART operation available.
6010
6011      For MEM, we can avoid an extract if the field starts on an appropriate
6012      boundary and we can change the mode of the memory reference.  */
6013
6014   if (tmode != BLKmode
6015       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6016            && !MEM_P (inner)
6017            && (inner_mode == tmode
6018                || !REG_P (inner)
6019                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6020                                          GET_MODE_BITSIZE (inner_mode))
6021                || reg_truncated_to_mode (tmode, inner))
6022            && (! in_dest
6023                || (REG_P (inner)
6024                    && have_insn_for (STRICT_LOW_PART, tmode))))
6025           || (MEM_P (inner) && pos_rtx == 0
6026               && (pos
6027                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6028                      : BITS_PER_UNIT)) == 0
6029               /* We can't do this if we are widening INNER_MODE (it
6030                  may not be aligned, for one thing).  */
6031               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6032               && (inner_mode == tmode
6033                   || (! mode_dependent_address_p (XEXP (inner, 0))
6034                       && ! MEM_VOLATILE_P (inner))))))
6035     {
6036       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6037          field.  If the original and current mode are the same, we need not
6038          adjust the offset.  Otherwise, we do if bytes big endian.
6039
6040          If INNER is not a MEM, get a piece consisting of just the field
6041          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6042
6043       if (MEM_P (inner))
6044         {
6045           HOST_WIDE_INT offset;
6046
6047           /* POS counts from lsb, but make OFFSET count in memory order.  */
6048           if (BYTES_BIG_ENDIAN)
6049             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6050           else
6051             offset = pos / BITS_PER_UNIT;
6052
6053           new = adjust_address_nv (inner, tmode, offset);
6054         }
6055       else if (REG_P (inner))
6056         {
6057           if (tmode != inner_mode)
6058             {
6059               /* We can't call gen_lowpart in a DEST since we
6060                  always want a SUBREG (see below) and it would sometimes
6061                  return a new hard register.  */
6062               if (pos || in_dest)
6063                 {
6064                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6065
6066                   if (WORDS_BIG_ENDIAN
6067                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6068                     final_word = ((GET_MODE_SIZE (inner_mode)
6069                                    - GET_MODE_SIZE (tmode))
6070                                   / UNITS_PER_WORD) - final_word;
6071
6072                   final_word *= UNITS_PER_WORD;
6073                   if (BYTES_BIG_ENDIAN &&
6074                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6075                     final_word += (GET_MODE_SIZE (inner_mode)
6076                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6077
6078                   /* Avoid creating invalid subregs, for example when
6079                      simplifying (x>>32)&255.  */
6080                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6081                     return NULL_RTX;
6082
6083                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6084                 }
6085               else
6086                 new = gen_lowpart (tmode, inner);
6087             }
6088           else
6089             new = inner;
6090         }
6091       else
6092         new = force_to_mode (inner, tmode,
6093                              len >= HOST_BITS_PER_WIDE_INT
6094                              ? ~(unsigned HOST_WIDE_INT) 0
6095                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6096                              0);
6097
6098       /* If this extraction is going into the destination of a SET,
6099          make a STRICT_LOW_PART unless we made a MEM.  */
6100
6101       if (in_dest)
6102         return (MEM_P (new) ? new
6103                 : (GET_CODE (new) != SUBREG
6104                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6105                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6106
6107       if (mode == tmode)
6108         return new;
6109
6110       if (GET_CODE (new) == CONST_INT)
6111         return gen_int_mode (INTVAL (new), mode);
6112
6113       /* If we know that no extraneous bits are set, and that the high
6114          bit is not set, convert the extraction to the cheaper of
6115          sign and zero extension, that are equivalent in these cases.  */
6116       if (flag_expensive_optimizations
6117           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6118               && ((nonzero_bits (new, tmode)
6119                    & ~(((unsigned HOST_WIDE_INT)
6120                         GET_MODE_MASK (tmode))
6121                        >> 1))
6122                   == 0)))
6123         {
6124           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6125           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6126
6127           /* Prefer ZERO_EXTENSION, since it gives more information to
6128              backends.  */
6129           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6130             return temp;
6131           return temp1;
6132         }
6133
6134       /* Otherwise, sign- or zero-extend unless we already are in the
6135          proper mode.  */
6136
6137       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6138                              mode, new));
6139     }
6140
6141   /* Unless this is a COMPARE or we have a funny memory reference,
6142      don't do anything with zero-extending field extracts starting at
6143      the low-order bit since they are simple AND operations.  */
6144   if (pos_rtx == 0 && pos == 0 && ! in_dest
6145       && ! in_compare && unsignedp)
6146     return 0;
6147
6148   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6149      if the position is not a constant and the length is not 1.  In all
6150      other cases, we would only be going outside our object in cases when
6151      an original shift would have been undefined.  */
6152   if (MEM_P (inner)
6153       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6154           || (pos_rtx != 0 && len != 1)))
6155     return 0;
6156
6157   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6158      and the mode for the result.  */
6159   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6160     {
6161       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6162       pos_mode = mode_for_extraction (EP_insv, 2);
6163       extraction_mode = mode_for_extraction (EP_insv, 3);
6164     }
6165
6166   if (! in_dest && unsignedp
6167       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6168     {
6169       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6170       pos_mode = mode_for_extraction (EP_extzv, 3);
6171       extraction_mode = mode_for_extraction (EP_extzv, 0);
6172     }
6173
6174   if (! in_dest && ! unsignedp
6175       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6176     {
6177       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6178       pos_mode = mode_for_extraction (EP_extv, 3);
6179       extraction_mode = mode_for_extraction (EP_extv, 0);
6180     }
6181
6182   /* Never narrow an object, since that might not be safe.  */
6183
6184   if (mode != VOIDmode
6185       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6186     extraction_mode = mode;
6187
6188   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6189       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6190     pos_mode = GET_MODE (pos_rtx);
6191
6192   /* If this is not from memory, the desired mode is the preferred mode
6193      for an extraction pattern's first input operand, or word_mode if there
6194      is none.  */
6195   if (!MEM_P (inner))
6196     wanted_inner_mode = wanted_inner_reg_mode;
6197   else
6198     {
6199       /* Be careful not to go beyond the extracted object and maintain the
6200          natural alignment of the memory.  */
6201       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6202       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6203              > GET_MODE_BITSIZE (wanted_inner_mode))
6204         {
6205           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6206           gcc_assert (wanted_inner_mode != VOIDmode);
6207         }
6208
6209       /* If we have to change the mode of memory and cannot, the desired mode
6210          is EXTRACTION_MODE.  */
6211       if (inner_mode != wanted_inner_mode
6212           && (mode_dependent_address_p (XEXP (inner, 0))
6213               || MEM_VOLATILE_P (inner)
6214               || pos_rtx))
6215         wanted_inner_mode = extraction_mode;
6216     }
6217
6218   orig_pos = pos;
6219
6220   if (BITS_BIG_ENDIAN)
6221     {
6222       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6223          BITS_BIG_ENDIAN style.  If position is constant, compute new
6224          position.  Otherwise, build subtraction.
6225          Note that POS is relative to the mode of the original argument.
6226          If it's a MEM we need to recompute POS relative to that.
6227          However, if we're extracting from (or inserting into) a register,
6228          we want to recompute POS relative to wanted_inner_mode.  */
6229       int width = (MEM_P (inner)
6230                    ? GET_MODE_BITSIZE (is_mode)
6231                    : GET_MODE_BITSIZE (wanted_inner_mode));
6232
6233       if (pos_rtx == 0)
6234         pos = width - len - pos;
6235       else
6236         pos_rtx
6237           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6238       /* POS may be less than 0 now, but we check for that below.
6239          Note that it can only be less than 0 if !MEM_P (inner).  */
6240     }
6241
6242   /* If INNER has a wider mode, and this is a constant extraction, try to
6243      make it smaller and adjust the byte to point to the byte containing
6244      the value.  */
6245   if (wanted_inner_mode != VOIDmode
6246       && inner_mode != wanted_inner_mode
6247       && ! pos_rtx
6248       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6249       && MEM_P (inner)
6250       && ! mode_dependent_address_p (XEXP (inner, 0))
6251       && ! MEM_VOLATILE_P (inner))
6252     {
6253       int offset = 0;
6254
6255       /* The computations below will be correct if the machine is big
6256          endian in both bits and bytes or little endian in bits and bytes.
6257          If it is mixed, we must adjust.  */
6258
6259       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6260          adjust OFFSET to compensate.  */
6261       if (BYTES_BIG_ENDIAN
6262           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6263         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6264
6265       /* We can now move to the desired byte.  */
6266       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6267                 * GET_MODE_SIZE (wanted_inner_mode);
6268       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6269
6270       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6271           && is_mode != wanted_inner_mode)
6272         offset = (GET_MODE_SIZE (is_mode)
6273                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6274
6275       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6276     }
6277
6278   /* If INNER is not memory, we can always get it into the proper mode.  If we
6279      are changing its mode, POS must be a constant and smaller than the size
6280      of the new mode.  */
6281   else if (!MEM_P (inner))
6282     {
6283       if (GET_MODE (inner) != wanted_inner_mode
6284           && (pos_rtx != 0
6285               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6286         return 0;
6287
6288       if (orig_pos < 0)
6289         return 0;
6290
6291       inner = force_to_mode (inner, wanted_inner_mode,
6292                              pos_rtx
6293                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6294                              ? ~(unsigned HOST_WIDE_INT) 0
6295                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6296                                 << orig_pos),
6297                              0);
6298     }
6299
6300   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6301      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6302   if (pos_rtx != 0
6303       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6304     {
6305       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6306
6307       /* If we know that no extraneous bits are set, and that the high
6308          bit is not set, convert extraction to cheaper one - either
6309          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6310          cases.  */
6311       if (flag_expensive_optimizations
6312           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6313               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6314                    & ~(((unsigned HOST_WIDE_INT)
6315                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6316                        >> 1))
6317                   == 0)))
6318         {
6319           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6320
6321           /* Prefer ZERO_EXTENSION, since it gives more information to
6322              backends.  */
6323           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6324             temp = temp1;
6325         }
6326       pos_rtx = temp;
6327     }
6328   else if (pos_rtx != 0
6329            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6330     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6331
6332   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6333      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6334      be a CONST_INT.  */
6335   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6336     pos_rtx = orig_pos_rtx;
6337
6338   else if (pos_rtx == 0)
6339     pos_rtx = GEN_INT (pos);
6340
6341   /* Make the required operation.  See if we can use existing rtx.  */
6342   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6343                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6344   if (! in_dest)
6345     new = gen_lowpart (mode, new);
6346
6347   return new;
6348 }
6349 \f
6350 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6351    with any other operations in X.  Return X without that shift if so.  */
6352
6353 static rtx
6354 extract_left_shift (rtx x, int count)
6355 {
6356   enum rtx_code code = GET_CODE (x);
6357   enum machine_mode mode = GET_MODE (x);
6358   rtx tem;
6359
6360   switch (code)
6361     {
6362     case ASHIFT:
6363       /* This is the shift itself.  If it is wide enough, we will return
6364          either the value being shifted if the shift count is equal to
6365          COUNT or a shift for the difference.  */
6366       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6367           && INTVAL (XEXP (x, 1)) >= count)
6368         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6369                                      INTVAL (XEXP (x, 1)) - count);
6370       break;
6371
6372     case NEG:  case NOT:
6373       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6374         return simplify_gen_unary (code, mode, tem, mode);
6375
6376       break;
6377
6378     case PLUS:  case IOR:  case XOR:  case AND:
6379       /* If we can safely shift this constant and we find the inner shift,
6380          make a new operation.  */
6381       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6382           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6383           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6384         return simplify_gen_binary (code, mode, tem,
6385                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6386
6387       break;
6388
6389     default:
6390       break;
6391     }
6392
6393   return 0;
6394 }
6395 \f
6396 /* Look at the expression rooted at X.  Look for expressions
6397    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6398    Form these expressions.
6399
6400    Return the new rtx, usually just X.
6401
6402    Also, for machines like the VAX that don't have logical shift insns,
6403    try to convert logical to arithmetic shift operations in cases where
6404    they are equivalent.  This undoes the canonicalizations to logical
6405    shifts done elsewhere.
6406
6407    We try, as much as possible, to re-use rtl expressions to save memory.
6408
6409    IN_CODE says what kind of expression we are processing.  Normally, it is
6410    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6411    being kludges), it is MEM.  When processing the arguments of a comparison
6412    or a COMPARE against zero, it is COMPARE.  */
6413
6414 static rtx
6415 make_compound_operation (rtx x, enum rtx_code in_code)
6416 {
6417   enum rtx_code code = GET_CODE (x);
6418   enum machine_mode mode = GET_MODE (x);
6419   int mode_width = GET_MODE_BITSIZE (mode);
6420   rtx rhs, lhs;
6421   enum rtx_code next_code;
6422   int i;
6423   rtx new = 0;
6424   rtx tem;
6425   const char *fmt;
6426
6427   /* Select the code to be used in recursive calls.  Once we are inside an
6428      address, we stay there.  If we have a comparison, set to COMPARE,
6429      but once inside, go back to our default of SET.  */
6430
6431   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6432                : ((code == COMPARE || COMPARISON_P (x))
6433                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6434                : in_code == COMPARE ? SET : in_code);
6435
6436   /* Process depending on the code of this operation.  If NEW is set
6437      nonzero, it will be returned.  */
6438
6439   switch (code)
6440     {
6441     case ASHIFT:
6442       /* Convert shifts by constants into multiplications if inside
6443          an address.  */
6444       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6445           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6446           && INTVAL (XEXP (x, 1)) >= 0)
6447         {
6448           new = make_compound_operation (XEXP (x, 0), next_code);
6449           new = gen_rtx_MULT (mode, new,
6450                               GEN_INT ((HOST_WIDE_INT) 1
6451                                        << INTVAL (XEXP (x, 1))));
6452         }
6453       break;
6454
6455     case AND:
6456       /* If the second operand is not a constant, we can't do anything
6457          with it.  */
6458       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6459         break;
6460
6461       /* If the constant is a power of two minus one and the first operand
6462          is a logical right shift, make an extraction.  */
6463       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6464           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6465         {
6466           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6467           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6468                                  0, in_code == COMPARE);
6469         }
6470
6471       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6472       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6473                && subreg_lowpart_p (XEXP (x, 0))
6474                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6475                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6476         {
6477           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6478                                          next_code);
6479           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6480                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6481                                  0, in_code == COMPARE);
6482         }
6483       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6484       else if ((GET_CODE (XEXP (x, 0)) == XOR
6485                 || GET_CODE (XEXP (x, 0)) == IOR)
6486                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6487                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6488                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6489         {
6490           /* Apply the distributive law, and then try to make extractions.  */
6491           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6492                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6493                                              XEXP (x, 1)),
6494                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6495                                              XEXP (x, 1)));
6496           new = make_compound_operation (new, in_code);
6497         }
6498
6499       /* If we are have (and (rotate X C) M) and C is larger than the number
6500          of bits in M, this is an extraction.  */
6501
6502       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6503                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6504                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6505                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6506         {
6507           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6508           new = make_extraction (mode, new,
6509                                  (GET_MODE_BITSIZE (mode)
6510                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6511                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6512         }
6513
6514       /* On machines without logical shifts, if the operand of the AND is
6515          a logical shift and our mask turns off all the propagated sign
6516          bits, we can replace the logical shift with an arithmetic shift.  */
6517       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6518                && !have_insn_for (LSHIFTRT, mode)
6519                && have_insn_for (ASHIFTRT, mode)
6520                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6521                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6522                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6523                && mode_width <= HOST_BITS_PER_WIDE_INT)
6524         {
6525           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6526
6527           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6528           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6529             SUBST (XEXP (x, 0),
6530                    gen_rtx_ASHIFTRT (mode,
6531                                      make_compound_operation
6532                                      (XEXP (XEXP (x, 0), 0), next_code),
6533                                      XEXP (XEXP (x, 0), 1)));
6534         }
6535
6536       /* If the constant is one less than a power of two, this might be
6537          representable by an extraction even if no shift is present.
6538          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6539          we are in a COMPARE.  */
6540       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6541         new = make_extraction (mode,
6542                                make_compound_operation (XEXP (x, 0),
6543                                                         next_code),
6544                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6545
6546       /* If we are in a comparison and this is an AND with a power of two,
6547          convert this into the appropriate bit extract.  */
6548       else if (in_code == COMPARE
6549                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6550         new = make_extraction (mode,
6551                                make_compound_operation (XEXP (x, 0),
6552                                                         next_code),
6553                                i, NULL_RTX, 1, 1, 0, 1);
6554
6555       break;
6556
6557     case LSHIFTRT:
6558       /* If the sign bit is known to be zero, replace this with an
6559          arithmetic shift.  */
6560       if (have_insn_for (ASHIFTRT, mode)
6561           && ! have_insn_for (LSHIFTRT, mode)
6562           && mode_width <= HOST_BITS_PER_WIDE_INT
6563           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6564         {
6565           new = gen_rtx_ASHIFTRT (mode,
6566                                   make_compound_operation (XEXP (x, 0),
6567                                                            next_code),
6568                                   XEXP (x, 1));
6569           break;
6570         }
6571
6572       /* ... fall through ...  */
6573
6574     case ASHIFTRT:
6575       lhs = XEXP (x, 0);
6576       rhs = XEXP (x, 1);
6577
6578       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6579          this is a SIGN_EXTRACT.  */
6580       if (GET_CODE (rhs) == CONST_INT
6581           && GET_CODE (lhs) == ASHIFT
6582           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6583           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6584         {
6585           new = make_compound_operation (XEXP (lhs, 0), next_code);
6586           new = make_extraction (mode, new,
6587                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6588                                  NULL_RTX, mode_width - INTVAL (rhs),
6589                                  code == LSHIFTRT, 0, in_code == COMPARE);
6590           break;
6591         }
6592
6593       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6594          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6595          also do this for some cases of SIGN_EXTRACT, but it doesn't
6596          seem worth the effort; the case checked for occurs on Alpha.  */
6597
6598       if (!OBJECT_P (lhs)
6599           && ! (GET_CODE (lhs) == SUBREG
6600                 && (OBJECT_P (SUBREG_REG (lhs))))
6601           && GET_CODE (rhs) == CONST_INT
6602           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6603           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6604         new = make_extraction (mode, make_compound_operation (new, next_code),
6605                                0, NULL_RTX, mode_width - INTVAL (rhs),
6606                                code == LSHIFTRT, 0, in_code == COMPARE);
6607
6608       break;
6609
6610     case SUBREG:
6611       /* Call ourselves recursively on the inner expression.  If we are
6612          narrowing the object and it has a different RTL code from
6613          what it originally did, do this SUBREG as a force_to_mode.  */
6614
6615       tem = make_compound_operation (SUBREG_REG (x), in_code);
6616
6617       {
6618         rtx simplified;
6619         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6620                                       SUBREG_BYTE (x));
6621
6622         if (simplified)
6623           tem = simplified;
6624
6625         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6626             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6627             && subreg_lowpart_p (x))
6628           {
6629             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6630                                        0);
6631
6632             /* If we have something other than a SUBREG, we might have
6633                done an expansion, so rerun ourselves.  */
6634             if (GET_CODE (newer) != SUBREG)
6635               newer = make_compound_operation (newer, in_code);
6636
6637             return newer;
6638           }
6639
6640         if (simplified)
6641           return tem;
6642       }
6643       break;
6644
6645     default:
6646       break;
6647     }
6648
6649   if (new)
6650     {
6651       x = gen_lowpart (mode, new);
6652       code = GET_CODE (x);
6653     }
6654
6655   /* Now recursively process each operand of this operation.  */
6656   fmt = GET_RTX_FORMAT (code);
6657   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6658     if (fmt[i] == 'e')
6659       {
6660         new = make_compound_operation (XEXP (x, i), next_code);
6661         SUBST (XEXP (x, i), new);
6662       }
6663
6664   /* If this is a commutative operation, the changes to the operands
6665      may have made it noncanonical.  */
6666   if (COMMUTATIVE_ARITH_P (x)
6667       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6668     {
6669       tem = XEXP (x, 0);
6670       SUBST (XEXP (x, 0), XEXP (x, 1));
6671       SUBST (XEXP (x, 1), tem);
6672     }
6673
6674   return x;
6675 }
6676 \f
6677 /* Given M see if it is a value that would select a field of bits
6678    within an item, but not the entire word.  Return -1 if not.
6679    Otherwise, return the starting position of the field, where 0 is the
6680    low-order bit.
6681
6682    *PLEN is set to the length of the field.  */
6683
6684 static int
6685 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6686 {
6687   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6688   int pos = exact_log2 (m & -m);
6689   int len = 0;
6690
6691   if (pos >= 0)
6692     /* Now shift off the low-order zero bits and see if we have a
6693        power of two minus 1.  */
6694     len = exact_log2 ((m >> pos) + 1);
6695
6696   if (len <= 0)
6697     pos = -1;
6698
6699   *plen = len;
6700   return pos;
6701 }
6702 \f
6703 /* If X refers to a register that equals REG in value, replace these
6704    references with REG.  */
6705 static rtx
6706 canon_reg_for_combine (rtx x, rtx reg)
6707 {
6708   rtx op0, op1, op2;
6709   const char *fmt;
6710   int i;
6711   bool copied;
6712
6713   enum rtx_code code = GET_CODE (x);
6714   switch (GET_RTX_CLASS (code))
6715     {
6716     case RTX_UNARY:
6717       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6718       if (op0 != XEXP (x, 0))
6719         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6720                                    GET_MODE (reg));
6721       break;
6722
6723     case RTX_BIN_ARITH:
6724     case RTX_COMM_ARITH:
6725       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6726       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6727       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6728         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6729       break;
6730
6731     case RTX_COMPARE:
6732     case RTX_COMM_COMPARE:
6733       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6734       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6735       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6736         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6737                                         GET_MODE (op0), op0, op1);
6738       break;
6739
6740     case RTX_TERNARY:
6741     case RTX_BITFIELD_OPS:
6742       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6743       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6744       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6745       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6746         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6747                                      GET_MODE (op0), op0, op1, op2);
6748
6749     case RTX_OBJ:
6750       if (REG_P (x))
6751         {
6752           if (rtx_equal_p (get_last_value (reg), x)
6753               || rtx_equal_p (reg, get_last_value (x)))
6754             return reg;
6755           else
6756             break;
6757         }
6758
6759       /* fall through */
6760
6761     default:
6762       fmt = GET_RTX_FORMAT (code);
6763       copied = false;
6764       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6765         if (fmt[i] == 'e')
6766           {
6767             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6768             if (op != XEXP (x, i))
6769               {
6770                 if (!copied)
6771                   {
6772                     copied = true;
6773                     x = copy_rtx (x);
6774                   }
6775                 XEXP (x, i) = op;
6776               }
6777           }
6778         else if (fmt[i] == 'E')
6779           {
6780             int j;
6781             for (j = 0; j < XVECLEN (x, i); j++)
6782               {
6783                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6784                 if (op != XVECEXP (x, i, j))
6785                   {
6786                     if (!copied)
6787                       {
6788                         copied = true;
6789                         x = copy_rtx (x);
6790                       }
6791                     XVECEXP (x, i, j) = op;
6792                   }
6793               }
6794           }
6795
6796       break;
6797     }
6798
6799   return x;
6800 }
6801
6802 /* Return X converted to MODE.  If the value is already truncated to
6803    MODE we can just return a subreg even though in the general case we
6804    would need an explicit truncation.  */
6805
6806 static rtx
6807 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6808 {
6809   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6810       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6811                                 GET_MODE_BITSIZE (GET_MODE (x)))
6812       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6813     return gen_lowpart (mode, x);
6814   else
6815     return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6816 }
6817
6818 /* See if X can be simplified knowing that we will only refer to it in
6819    MODE and will only refer to those bits that are nonzero in MASK.
6820    If other bits are being computed or if masking operations are done
6821    that select a superset of the bits in MASK, they can sometimes be
6822    ignored.
6823
6824    Return a possibly simplified expression, but always convert X to
6825    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6826
6827    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6828    are all off in X.  This is used when X will be complemented, by either
6829    NOT, NEG, or XOR.  */
6830
6831 static rtx
6832 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6833                int just_select)
6834 {
6835   enum rtx_code code = GET_CODE (x);
6836   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6837   enum machine_mode op_mode;
6838   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6839   rtx op0, op1, temp;
6840
6841   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6842      code below will do the wrong thing since the mode of such an
6843      expression is VOIDmode.
6844
6845      Also do nothing if X is a CLOBBER; this can happen if X was
6846      the return value from a call to gen_lowpart.  */
6847   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6848     return x;
6849
6850   /* We want to perform the operation is its present mode unless we know
6851      that the operation is valid in MODE, in which case we do the operation
6852      in MODE.  */
6853   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6854               && have_insn_for (code, mode))
6855              ? mode : GET_MODE (x));
6856
6857   /* It is not valid to do a right-shift in a narrower mode
6858      than the one it came in with.  */
6859   if ((code == LSHIFTRT || code == ASHIFTRT)
6860       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6861     op_mode = GET_MODE (x);
6862
6863   /* Truncate MASK to fit OP_MODE.  */
6864   if (op_mode)
6865     mask &= GET_MODE_MASK (op_mode);
6866
6867   /* When we have an arithmetic operation, or a shift whose count we
6868      do not know, we need to assume that all bits up to the highest-order
6869      bit in MASK will be needed.  This is how we form such a mask.  */
6870   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6871     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6872   else
6873     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6874                    - 1);
6875
6876   /* Determine what bits of X are guaranteed to be (non)zero.  */
6877   nonzero = nonzero_bits (x, mode);
6878
6879   /* If none of the bits in X are needed, return a zero.  */
6880   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
6881     x = const0_rtx;
6882
6883   /* If X is a CONST_INT, return a new one.  Do this here since the
6884      test below will fail.  */
6885   if (GET_CODE (x) == CONST_INT)
6886     {
6887       if (SCALAR_INT_MODE_P (mode))
6888         return gen_int_mode (INTVAL (x) & mask, mode);
6889       else
6890         {
6891           x = GEN_INT (INTVAL (x) & mask);
6892           return gen_lowpart_common (mode, x);
6893         }
6894     }
6895
6896   /* If X is narrower than MODE and we want all the bits in X's mode, just
6897      get X in the proper mode.  */
6898   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6899       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6900     return gen_lowpart (mode, x);
6901
6902   switch (code)
6903     {
6904     case CLOBBER:
6905       /* If X is a (clobber (const_int)), return it since we know we are
6906          generating something that won't match.  */
6907       return x;
6908
6909     case SIGN_EXTEND:
6910     case ZERO_EXTEND:
6911     case ZERO_EXTRACT:
6912     case SIGN_EXTRACT:
6913       x = expand_compound_operation (x);
6914       if (GET_CODE (x) != code)
6915         return force_to_mode (x, mode, mask, next_select);
6916       break;
6917
6918     case SUBREG:
6919       if (subreg_lowpart_p (x)
6920           /* We can ignore the effect of this SUBREG if it narrows the mode or
6921              if the constant masks to zero all the bits the mode doesn't
6922              have.  */
6923           && ((GET_MODE_SIZE (GET_MODE (x))
6924                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6925               || (0 == (mask
6926                         & GET_MODE_MASK (GET_MODE (x))
6927                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6928         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6929       break;
6930
6931     case AND:
6932       /* If this is an AND with a constant, convert it into an AND
6933          whose constant is the AND of that constant with MASK.  If it
6934          remains an AND of MASK, delete it since it is redundant.  */
6935
6936       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6937         {
6938           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6939                                       mask & INTVAL (XEXP (x, 1)));
6940
6941           /* If X is still an AND, see if it is an AND with a mask that
6942              is just some low-order bits.  If so, and it is MASK, we don't
6943              need it.  */
6944
6945           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6946               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6947                   == mask))
6948             x = XEXP (x, 0);
6949
6950           /* If it remains an AND, try making another AND with the bits
6951              in the mode mask that aren't in MASK turned on.  If the
6952              constant in the AND is wide enough, this might make a
6953              cheaper constant.  */
6954
6955           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6956               && GET_MODE_MASK (GET_MODE (x)) != mask
6957               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6958             {
6959               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6960                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6961               int width = GET_MODE_BITSIZE (GET_MODE (x));
6962               rtx y;
6963
6964               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6965                  number, sign extend it.  */
6966               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6967                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6968                 cval |= (HOST_WIDE_INT) -1 << width;
6969
6970               y = simplify_gen_binary (AND, GET_MODE (x),
6971                                        XEXP (x, 0), GEN_INT (cval));
6972               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6973                 x = y;
6974             }
6975
6976           break;
6977         }
6978
6979       goto binop;
6980
6981     case PLUS:
6982       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6983          low-order bits (as in an alignment operation) and FOO is already
6984          aligned to that boundary, mask C1 to that boundary as well.
6985          This may eliminate that PLUS and, later, the AND.  */
6986
6987       {
6988         unsigned int width = GET_MODE_BITSIZE (mode);
6989         unsigned HOST_WIDE_INT smask = mask;
6990
6991         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6992            number, sign extend it.  */
6993
6994         if (width < HOST_BITS_PER_WIDE_INT
6995             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6996           smask |= (HOST_WIDE_INT) -1 << width;
6997
6998         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6999             && exact_log2 (- smask) >= 0
7000             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7001             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7002           return force_to_mode (plus_constant (XEXP (x, 0),
7003                                                (INTVAL (XEXP (x, 1)) & smask)),
7004                                 mode, smask, next_select);
7005       }
7006
7007       /* ... fall through ...  */
7008
7009     case MULT:
7010       /* For PLUS, MINUS and MULT, we need any bits less significant than the
7011          most significant bit in MASK since carries from those bits will
7012          affect the bits we are interested in.  */
7013       mask = fuller_mask;
7014       goto binop;
7015
7016     case MINUS:
7017       /* If X is (minus C Y) where C's least set bit is larger than any bit
7018          in the mask, then we may replace with (neg Y).  */
7019       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7020           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7021                                         & -INTVAL (XEXP (x, 0))))
7022               > mask))
7023         {
7024           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7025                                   GET_MODE (x));
7026           return force_to_mode (x, mode, mask, next_select);
7027         }
7028
7029       /* Similarly, if C contains every bit in the fuller_mask, then we may
7030          replace with (not Y).  */
7031       if (GET_CODE (XEXP (x, 0)) == CONST_INT
7032           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7033               == INTVAL (XEXP (x, 0))))
7034         {
7035           x = simplify_gen_unary (NOT, GET_MODE (x),
7036                                   XEXP (x, 1), GET_MODE (x));
7037           return force_to_mode (x, mode, mask, next_select);
7038         }
7039
7040       mask = fuller_mask;
7041       goto binop;
7042
7043     case IOR:
7044     case XOR:
7045       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7046          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7047          operation which may be a bitfield extraction.  Ensure that the
7048          constant we form is not wider than the mode of X.  */
7049
7050       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7051           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7052           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7053           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7054           && GET_CODE (XEXP (x, 1)) == CONST_INT
7055           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7056                + floor_log2 (INTVAL (XEXP (x, 1))))
7057               < GET_MODE_BITSIZE (GET_MODE (x)))
7058           && (INTVAL (XEXP (x, 1))
7059               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7060         {
7061           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7062                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7063           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7064                                       XEXP (XEXP (x, 0), 0), temp);
7065           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7066                                    XEXP (XEXP (x, 0), 1));
7067           return force_to_mode (x, mode, mask, next_select);
7068         }
7069
7070     binop:
7071       /* For most binary operations, just propagate into the operation and
7072          change the mode if we have an operation of that mode.  */
7073
7074       op0 = gen_lowpart_or_truncate (op_mode,
7075                                      force_to_mode (XEXP (x, 0), mode, mask,
7076                                                     next_select));
7077       op1 = gen_lowpart_or_truncate (op_mode,
7078                                      force_to_mode (XEXP (x, 1), mode, mask,
7079                                         next_select));
7080
7081       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7082         x = simplify_gen_binary (code, op_mode, op0, op1);
7083       break;
7084
7085     case ASHIFT:
7086       /* For left shifts, do the same, but just for the first operand.
7087          However, we cannot do anything with shifts where we cannot
7088          guarantee that the counts are smaller than the size of the mode
7089          because such a count will have a different meaning in a
7090          wider mode.  */
7091
7092       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7093              && INTVAL (XEXP (x, 1)) >= 0
7094              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7095           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7096                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7097                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7098         break;
7099
7100       /* If the shift count is a constant and we can do arithmetic in
7101          the mode of the shift, refine which bits we need.  Otherwise, use the
7102          conservative form of the mask.  */
7103       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7104           && INTVAL (XEXP (x, 1)) >= 0
7105           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7106           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7107         mask >>= INTVAL (XEXP (x, 1));
7108       else
7109         mask = fuller_mask;
7110
7111       op0 = gen_lowpart_or_truncate (op_mode,
7112                                      force_to_mode (XEXP (x, 0), op_mode,
7113                                                     mask, next_select));
7114
7115       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7116         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7117       break;
7118
7119     case LSHIFTRT:
7120       /* Here we can only do something if the shift count is a constant,
7121          this shift constant is valid for the host, and we can do arithmetic
7122          in OP_MODE.  */
7123
7124       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7125           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7126           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7127         {
7128           rtx inner = XEXP (x, 0);
7129           unsigned HOST_WIDE_INT inner_mask;
7130
7131           /* Select the mask of the bits we need for the shift operand.  */
7132           inner_mask = mask << INTVAL (XEXP (x, 1));
7133
7134           /* We can only change the mode of the shift if we can do arithmetic
7135              in the mode of the shift and INNER_MASK is no wider than the
7136              width of X's mode.  */
7137           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7138             op_mode = GET_MODE (x);
7139
7140           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7141
7142           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7143             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7144         }
7145
7146       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7147          shift and AND produces only copies of the sign bit (C2 is one less
7148          than a power of two), we can do this with just a shift.  */
7149
7150       if (GET_CODE (x) == LSHIFTRT
7151           && GET_CODE (XEXP (x, 1)) == CONST_INT
7152           /* The shift puts one of the sign bit copies in the least significant
7153              bit.  */
7154           && ((INTVAL (XEXP (x, 1))
7155                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7156               >= GET_MODE_BITSIZE (GET_MODE (x)))
7157           && exact_log2 (mask + 1) >= 0
7158           /* Number of bits left after the shift must be more than the mask
7159              needs.  */
7160           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7161               <= GET_MODE_BITSIZE (GET_MODE (x)))
7162           /* Must be more sign bit copies than the mask needs.  */
7163           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7164               >= exact_log2 (mask + 1)))
7165         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7166                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7167                                           - exact_log2 (mask + 1)));
7168
7169       goto shiftrt;
7170
7171     case ASHIFTRT:
7172       /* If we are just looking for the sign bit, we don't need this shift at
7173          all, even if it has a variable count.  */
7174       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7175           && (mask == ((unsigned HOST_WIDE_INT) 1
7176                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7177         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7178
7179       /* If this is a shift by a constant, get a mask that contains those bits
7180          that are not copies of the sign bit.  We then have two cases:  If
7181          MASK only includes those bits, this can be a logical shift, which may
7182          allow simplifications.  If MASK is a single-bit field not within
7183          those bits, we are requesting a copy of the sign bit and hence can
7184          shift the sign bit to the appropriate location.  */
7185
7186       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7187           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7188         {
7189           int i;
7190
7191           /* If the considered data is wider than HOST_WIDE_INT, we can't
7192              represent a mask for all its bits in a single scalar.
7193              But we only care about the lower bits, so calculate these.  */
7194
7195           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7196             {
7197               nonzero = ~(HOST_WIDE_INT) 0;
7198
7199               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7200                  is the number of bits a full-width mask would have set.
7201                  We need only shift if these are fewer than nonzero can
7202                  hold.  If not, we must keep all bits set in nonzero.  */
7203
7204               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7205                   < HOST_BITS_PER_WIDE_INT)
7206                 nonzero >>= INTVAL (XEXP (x, 1))
7207                             + HOST_BITS_PER_WIDE_INT
7208                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7209             }
7210           else
7211             {
7212               nonzero = GET_MODE_MASK (GET_MODE (x));
7213               nonzero >>= INTVAL (XEXP (x, 1));
7214             }
7215
7216           if ((mask & ~nonzero) == 0)
7217             {
7218               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7219                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7220               if (GET_CODE (x) != ASHIFTRT)
7221                 return force_to_mode (x, mode, mask, next_select);
7222             }
7223
7224           else if ((i = exact_log2 (mask)) >= 0)
7225             {
7226               x = simplify_shift_const
7227                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7228                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7229
7230               if (GET_CODE (x) != ASHIFTRT)
7231                 return force_to_mode (x, mode, mask, next_select);
7232             }
7233         }
7234
7235       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7236          even if the shift count isn't a constant.  */
7237       if (mask == 1)
7238         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7239                                  XEXP (x, 0), XEXP (x, 1));
7240
7241     shiftrt:
7242
7243       /* If this is a zero- or sign-extension operation that just affects bits
7244          we don't care about, remove it.  Be sure the call above returned
7245          something that is still a shift.  */
7246
7247       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7248           && GET_CODE (XEXP (x, 1)) == CONST_INT
7249           && INTVAL (XEXP (x, 1)) >= 0
7250           && (INTVAL (XEXP (x, 1))
7251               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7252           && GET_CODE (XEXP (x, 0)) == ASHIFT
7253           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7254         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7255                               next_select);
7256
7257       break;
7258
7259     case ROTATE:
7260     case ROTATERT:
7261       /* If the shift count is constant and we can do computations
7262          in the mode of X, compute where the bits we care about are.
7263          Otherwise, we can't do anything.  Don't change the mode of
7264          the shift or propagate MODE into the shift, though.  */
7265       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7266           && INTVAL (XEXP (x, 1)) >= 0)
7267         {
7268           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7269                                             GET_MODE (x), GEN_INT (mask),
7270                                             XEXP (x, 1));
7271           if (temp && GET_CODE (temp) == CONST_INT)
7272             SUBST (XEXP (x, 0),
7273                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7274                                   INTVAL (temp), next_select));
7275         }
7276       break;
7277
7278     case NEG:
7279       /* If we just want the low-order bit, the NEG isn't needed since it
7280          won't change the low-order bit.  */
7281       if (mask == 1)
7282         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7283
7284       /* We need any bits less significant than the most significant bit in
7285          MASK since carries from those bits will affect the bits we are
7286          interested in.  */
7287       mask = fuller_mask;
7288       goto unop;
7289
7290     case NOT:
7291       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7292          same as the XOR case above.  Ensure that the constant we form is not
7293          wider than the mode of X.  */
7294
7295       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7296           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7297           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7298           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7299               < GET_MODE_BITSIZE (GET_MODE (x)))
7300           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7301         {
7302           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7303                                GET_MODE (x));
7304           temp = simplify_gen_binary (XOR, GET_MODE (x),
7305                                       XEXP (XEXP (x, 0), 0), temp);
7306           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7307                                    temp, XEXP (XEXP (x, 0), 1));
7308
7309           return force_to_mode (x, mode, mask, next_select);
7310         }
7311
7312       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7313          use the full mask inside the NOT.  */
7314       mask = fuller_mask;
7315
7316     unop:
7317       op0 = gen_lowpart_or_truncate (op_mode,
7318                                      force_to_mode (XEXP (x, 0), mode, mask,
7319                                                     next_select));
7320       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7321         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7322       break;
7323
7324     case NE:
7325       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7326          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7327          which is equal to STORE_FLAG_VALUE.  */
7328       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7329           && GET_MODE (XEXP (x, 0)) == mode
7330           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7331           && (nonzero_bits (XEXP (x, 0), mode)
7332               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7333         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7334
7335       break;
7336
7337     case IF_THEN_ELSE:
7338       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7339          written in a narrower mode.  We play it safe and do not do so.  */
7340
7341       SUBST (XEXP (x, 1),
7342              gen_lowpart_or_truncate (GET_MODE (x),
7343                                       force_to_mode (XEXP (x, 1), mode,
7344                                                      mask, next_select)));
7345       SUBST (XEXP (x, 2),
7346              gen_lowpart_or_truncate (GET_MODE (x),
7347                                       force_to_mode (XEXP (x, 2), mode,
7348                                                      mask, next_select)));
7349       break;
7350
7351     default:
7352       break;
7353     }
7354
7355   /* Ensure we return a value of the proper mode.  */
7356   return gen_lowpart_or_truncate (mode, x);
7357 }
7358 \f
7359 /* Return nonzero if X is an expression that has one of two values depending on
7360    whether some other value is zero or nonzero.  In that case, we return the
7361    value that is being tested, *PTRUE is set to the value if the rtx being
7362    returned has a nonzero value, and *PFALSE is set to the other alternative.
7363
7364    If we return zero, we set *PTRUE and *PFALSE to X.  */
7365
7366 static rtx
7367 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7368 {
7369   enum machine_mode mode = GET_MODE (x);
7370   enum rtx_code code = GET_CODE (x);
7371   rtx cond0, cond1, true0, true1, false0, false1;
7372   unsigned HOST_WIDE_INT nz;
7373
7374   /* If we are comparing a value against zero, we are done.  */
7375   if ((code == NE || code == EQ)
7376       && XEXP (x, 1) == const0_rtx)
7377     {
7378       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7379       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7380       return XEXP (x, 0);
7381     }
7382
7383   /* If this is a unary operation whose operand has one of two values, apply
7384      our opcode to compute those values.  */
7385   else if (UNARY_P (x)
7386            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7387     {
7388       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7389       *pfalse = simplify_gen_unary (code, mode, false0,
7390                                     GET_MODE (XEXP (x, 0)));
7391       return cond0;
7392     }
7393
7394   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7395      make can't possibly match and would suppress other optimizations.  */
7396   else if (code == COMPARE)
7397     ;
7398
7399   /* If this is a binary operation, see if either side has only one of two
7400      values.  If either one does or if both do and they are conditional on
7401      the same value, compute the new true and false values.  */
7402   else if (BINARY_P (x))
7403     {
7404       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7405       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7406
7407       if ((cond0 != 0 || cond1 != 0)
7408           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7409         {
7410           /* If if_then_else_cond returned zero, then true/false are the
7411              same rtl.  We must copy one of them to prevent invalid rtl
7412              sharing.  */
7413           if (cond0 == 0)
7414             true0 = copy_rtx (true0);
7415           else if (cond1 == 0)
7416             true1 = copy_rtx (true1);
7417
7418           if (COMPARISON_P (x))
7419             {
7420               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7421                                                 true0, true1);
7422               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7423                                                  false0, false1);
7424              }
7425           else
7426             {
7427               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7428               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7429             }
7430
7431           return cond0 ? cond0 : cond1;
7432         }
7433
7434       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7435          operands is zero when the other is nonzero, and vice-versa,
7436          and STORE_FLAG_VALUE is 1 or -1.  */
7437
7438       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7439           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7440               || code == UMAX)
7441           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7442         {
7443           rtx op0 = XEXP (XEXP (x, 0), 1);
7444           rtx op1 = XEXP (XEXP (x, 1), 1);
7445
7446           cond0 = XEXP (XEXP (x, 0), 0);
7447           cond1 = XEXP (XEXP (x, 1), 0);
7448
7449           if (COMPARISON_P (cond0)
7450               && COMPARISON_P (cond1)
7451               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7452                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7453                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7454                   || ((swap_condition (GET_CODE (cond0))
7455                        == reversed_comparison_code (cond1, NULL))
7456                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7457                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7458               && ! side_effects_p (x))
7459             {
7460               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7461               *pfalse = simplify_gen_binary (MULT, mode,
7462                                              (code == MINUS
7463                                               ? simplify_gen_unary (NEG, mode,
7464                                                                     op1, mode)
7465                                               : op1),
7466                                               const_true_rtx);
7467               return cond0;
7468             }
7469         }
7470
7471       /* Similarly for MULT, AND and UMIN, except that for these the result
7472          is always zero.  */
7473       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7474           && (code == MULT || code == AND || code == UMIN)
7475           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7476         {
7477           cond0 = XEXP (XEXP (x, 0), 0);
7478           cond1 = XEXP (XEXP (x, 1), 0);
7479
7480           if (COMPARISON_P (cond0)
7481               && COMPARISON_P (cond1)
7482               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7483                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7484                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7485                   || ((swap_condition (GET_CODE (cond0))
7486                        == reversed_comparison_code (cond1, NULL))
7487                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7488                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7489               && ! side_effects_p (x))
7490             {
7491               *ptrue = *pfalse = const0_rtx;
7492               return cond0;
7493             }
7494         }
7495     }
7496
7497   else if (code == IF_THEN_ELSE)
7498     {
7499       /* If we have IF_THEN_ELSE already, extract the condition and
7500          canonicalize it if it is NE or EQ.  */
7501       cond0 = XEXP (x, 0);
7502       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7503       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7504         return XEXP (cond0, 0);
7505       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7506         {
7507           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7508           return XEXP (cond0, 0);
7509         }
7510       else
7511         return cond0;
7512     }
7513
7514   /* If X is a SUBREG, we can narrow both the true and false values
7515      if the inner expression, if there is a condition.  */
7516   else if (code == SUBREG
7517            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7518                                                &true0, &false0)))
7519     {
7520       true0 = simplify_gen_subreg (mode, true0,
7521                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7522       false0 = simplify_gen_subreg (mode, false0,
7523                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7524       if (true0 && false0)
7525         {
7526           *ptrue = true0;
7527           *pfalse = false0;
7528           return cond0;
7529         }
7530     }
7531
7532   /* If X is a constant, this isn't special and will cause confusions
7533      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7534   else if (CONSTANT_P (x)
7535            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7536     ;
7537
7538   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7539      will be least confusing to the rest of the compiler.  */
7540   else if (mode == BImode)
7541     {
7542       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7543       return x;
7544     }
7545
7546   /* If X is known to be either 0 or -1, those are the true and
7547      false values when testing X.  */
7548   else if (x == constm1_rtx || x == const0_rtx
7549            || (mode != VOIDmode
7550                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7551     {
7552       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7553       return x;
7554     }
7555
7556   /* Likewise for 0 or a single bit.  */
7557   else if (SCALAR_INT_MODE_P (mode)
7558            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7559            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7560     {
7561       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7562       return x;
7563     }
7564
7565   /* Otherwise fail; show no condition with true and false values the same.  */
7566   *ptrue = *pfalse = x;
7567   return 0;
7568 }
7569 \f
7570 /* Return the value of expression X given the fact that condition COND
7571    is known to be true when applied to REG as its first operand and VAL
7572    as its second.  X is known to not be shared and so can be modified in
7573    place.
7574
7575    We only handle the simplest cases, and specifically those cases that
7576    arise with IF_THEN_ELSE expressions.  */
7577
7578 static rtx
7579 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7580 {
7581   enum rtx_code code = GET_CODE (x);
7582   rtx temp;
7583   const char *fmt;
7584   int i, j;
7585
7586   if (side_effects_p (x))
7587     return x;
7588
7589   /* If either operand of the condition is a floating point value,
7590      then we have to avoid collapsing an EQ comparison.  */
7591   if (cond == EQ
7592       && rtx_equal_p (x, reg)
7593       && ! FLOAT_MODE_P (GET_MODE (x))
7594       && ! FLOAT_MODE_P (GET_MODE (val)))
7595     return val;
7596
7597   if (cond == UNEQ && rtx_equal_p (x, reg))
7598     return val;
7599
7600   /* If X is (abs REG) and we know something about REG's relationship
7601      with zero, we may be able to simplify this.  */
7602
7603   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7604     switch (cond)
7605       {
7606       case GE:  case GT:  case EQ:
7607         return XEXP (x, 0);
7608       case LT:  case LE:
7609         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7610                                    XEXP (x, 0),
7611                                    GET_MODE (XEXP (x, 0)));
7612       default:
7613         break;
7614       }
7615
7616   /* The only other cases we handle are MIN, MAX, and comparisons if the
7617      operands are the same as REG and VAL.  */
7618
7619   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7620     {
7621       if (rtx_equal_p (XEXP (x, 0), val))
7622         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7623
7624       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7625         {
7626           if (COMPARISON_P (x))
7627             {
7628               if (comparison_dominates_p (cond, code))
7629                 return const_true_rtx;
7630
7631               code = reversed_comparison_code (x, NULL);
7632               if (code != UNKNOWN
7633                   && comparison_dominates_p (cond, code))
7634                 return const0_rtx;
7635               else
7636                 return x;
7637             }
7638           else if (code == SMAX || code == SMIN
7639                    || code == UMIN || code == UMAX)
7640             {
7641               int unsignedp = (code == UMIN || code == UMAX);
7642
7643               /* Do not reverse the condition when it is NE or EQ.
7644                  This is because we cannot conclude anything about
7645                  the value of 'SMAX (x, y)' when x is not equal to y,
7646                  but we can when x equals y.  */
7647               if ((code == SMAX || code == UMAX)
7648                   && ! (cond == EQ || cond == NE))
7649                 cond = reverse_condition (cond);
7650
7651               switch (cond)
7652                 {
7653                 case GE:   case GT:
7654                   return unsignedp ? x : XEXP (x, 1);
7655                 case LE:   case LT:
7656                   return unsignedp ? x : XEXP (x, 0);
7657                 case GEU:  case GTU:
7658                   return unsignedp ? XEXP (x, 1) : x;
7659                 case LEU:  case LTU:
7660                   return unsignedp ? XEXP (x, 0) : x;
7661                 default:
7662                   break;
7663                 }
7664             }
7665         }
7666     }
7667   else if (code == SUBREG)
7668     {
7669       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7670       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7671
7672       if (SUBREG_REG (x) != r)
7673         {
7674           /* We must simplify subreg here, before we lose track of the
7675              original inner_mode.  */
7676           new = simplify_subreg (GET_MODE (x), r,
7677                                  inner_mode, SUBREG_BYTE (x));
7678           if (new)
7679             return new;
7680           else
7681             SUBST (SUBREG_REG (x), r);
7682         }
7683
7684       return x;
7685     }
7686   /* We don't have to handle SIGN_EXTEND here, because even in the
7687      case of replacing something with a modeless CONST_INT, a
7688      CONST_INT is already (supposed to be) a valid sign extension for
7689      its narrower mode, which implies it's already properly
7690      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7691      story is different.  */
7692   else if (code == ZERO_EXTEND)
7693     {
7694       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7695       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7696
7697       if (XEXP (x, 0) != r)
7698         {
7699           /* We must simplify the zero_extend here, before we lose
7700              track of the original inner_mode.  */
7701           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7702                                           r, inner_mode);
7703           if (new)
7704             return new;
7705           else
7706             SUBST (XEXP (x, 0), r);
7707         }
7708
7709       return x;
7710     }
7711
7712   fmt = GET_RTX_FORMAT (code);
7713   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7714     {
7715       if (fmt[i] == 'e')
7716         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7717       else if (fmt[i] == 'E')
7718         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7719           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7720                                                 cond, reg, val));
7721     }
7722
7723   return x;
7724 }
7725 \f
7726 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7727    assignment as a field assignment.  */
7728
7729 static int
7730 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7731 {
7732   if (x == y || rtx_equal_p (x, y))
7733     return 1;
7734
7735   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7736     return 0;
7737
7738   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7739      Note that all SUBREGs of MEM are paradoxical; otherwise they
7740      would have been rewritten.  */
7741   if (MEM_P (x) && GET_CODE (y) == SUBREG
7742       && MEM_P (SUBREG_REG (y))
7743       && rtx_equal_p (SUBREG_REG (y),
7744                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7745     return 1;
7746
7747   if (MEM_P (y) && GET_CODE (x) == SUBREG
7748       && MEM_P (SUBREG_REG (x))
7749       && rtx_equal_p (SUBREG_REG (x),
7750                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7751     return 1;
7752
7753   /* We used to see if get_last_value of X and Y were the same but that's
7754      not correct.  In one direction, we'll cause the assignment to have
7755      the wrong destination and in the case, we'll import a register into this
7756      insn that might have already have been dead.   So fail if none of the
7757      above cases are true.  */
7758   return 0;
7759 }
7760 \f
7761 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7762    Return that assignment if so.
7763
7764    We only handle the most common cases.  */
7765
7766 static rtx
7767 make_field_assignment (rtx x)
7768 {
7769   rtx dest = SET_DEST (x);
7770   rtx src = SET_SRC (x);
7771   rtx assign;
7772   rtx rhs, lhs;
7773   HOST_WIDE_INT c1;
7774   HOST_WIDE_INT pos;
7775   unsigned HOST_WIDE_INT len;
7776   rtx other;
7777   enum machine_mode mode;
7778
7779   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7780      a clear of a one-bit field.  We will have changed it to
7781      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7782      for a SUBREG.  */
7783
7784   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7785       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7786       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7787       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7788     {
7789       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7790                                 1, 1, 1, 0);
7791       if (assign != 0)
7792         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7793       return x;
7794     }
7795
7796   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7797       && subreg_lowpart_p (XEXP (src, 0))
7798       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7799           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7800       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7801       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7802       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7803       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7804     {
7805       assign = make_extraction (VOIDmode, dest, 0,
7806                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7807                                 1, 1, 1, 0);
7808       if (assign != 0)
7809         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7810       return x;
7811     }
7812
7813   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7814      one-bit field.  */
7815   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7816       && XEXP (XEXP (src, 0), 0) == const1_rtx
7817       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7818     {
7819       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7820                                 1, 1, 1, 0);
7821       if (assign != 0)
7822         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7823       return x;
7824     }
7825
7826   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7827      SRC is an AND with all bits of that field set, then we can discard
7828      the AND.  */
7829   if (GET_CODE (dest) == ZERO_EXTRACT
7830       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7831       && GET_CODE (src) == AND
7832       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7833     {
7834       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7835       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7836       unsigned HOST_WIDE_INT ze_mask;
7837
7838       if (width >= HOST_BITS_PER_WIDE_INT)
7839         ze_mask = -1;
7840       else
7841         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7842
7843       /* Complete overlap.  We can remove the source AND.  */
7844       if ((and_mask & ze_mask) == ze_mask)
7845         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7846
7847       /* Partial overlap.  We can reduce the source AND.  */
7848       if ((and_mask & ze_mask) != and_mask)
7849         {
7850           mode = GET_MODE (src);
7851           src = gen_rtx_AND (mode, XEXP (src, 0),
7852                              gen_int_mode (and_mask & ze_mask, mode));
7853           return gen_rtx_SET (VOIDmode, dest, src);
7854         }
7855     }
7856
7857   /* The other case we handle is assignments into a constant-position
7858      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7859      a mask that has all one bits except for a group of zero bits and
7860      OTHER is known to have zeros where C1 has ones, this is such an
7861      assignment.  Compute the position and length from C1.  Shift OTHER
7862      to the appropriate position, force it to the required mode, and
7863      make the extraction.  Check for the AND in both operands.  */
7864
7865   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7866     return x;
7867
7868   rhs = expand_compound_operation (XEXP (src, 0));
7869   lhs = expand_compound_operation (XEXP (src, 1));
7870
7871   if (GET_CODE (rhs) == AND
7872       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7873       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7874     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7875   else if (GET_CODE (lhs) == AND
7876            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7877            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7878     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7879   else
7880     return x;
7881
7882   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7883   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7884       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7885       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7886     return x;
7887
7888   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7889   if (assign == 0)
7890     return x;
7891
7892   /* The mode to use for the source is the mode of the assignment, or of
7893      what is inside a possible STRICT_LOW_PART.  */
7894   mode = (GET_CODE (assign) == STRICT_LOW_PART
7895           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7896
7897   /* Shift OTHER right POS places and make it the source, restricting it
7898      to the proper length and mode.  */
7899
7900   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7901                                                      GET_MODE (src),
7902                                                      other, pos),
7903                                dest);
7904   src = force_to_mode (src, mode,
7905                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7906                        ? ~(unsigned HOST_WIDE_INT) 0
7907                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7908                        0);
7909
7910   /* If SRC is masked by an AND that does not make a difference in
7911      the value being stored, strip it.  */
7912   if (GET_CODE (assign) == ZERO_EXTRACT
7913       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7914       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7915       && GET_CODE (src) == AND
7916       && GET_CODE (XEXP (src, 1)) == CONST_INT
7917       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7918           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7919     src = XEXP (src, 0);
7920
7921   return gen_rtx_SET (VOIDmode, assign, src);
7922 }
7923 \f
7924 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7925    if so.  */
7926
7927 static rtx
7928 apply_distributive_law (rtx x)
7929 {
7930   enum rtx_code code = GET_CODE (x);
7931   enum rtx_code inner_code;
7932   rtx lhs, rhs, other;
7933   rtx tem;
7934
7935   /* Distributivity is not true for floating point as it can change the
7936      value.  So we don't do it unless -funsafe-math-optimizations.  */
7937   if (FLOAT_MODE_P (GET_MODE (x))
7938       && ! flag_unsafe_math_optimizations)
7939     return x;
7940
7941   /* The outer operation can only be one of the following:  */
7942   if (code != IOR && code != AND && code != XOR
7943       && code != PLUS && code != MINUS)
7944     return x;
7945
7946   lhs = XEXP (x, 0);
7947   rhs = XEXP (x, 1);
7948
7949   /* If either operand is a primitive we can't do anything, so get out
7950      fast.  */
7951   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7952     return x;
7953
7954   lhs = expand_compound_operation (lhs);
7955   rhs = expand_compound_operation (rhs);
7956   inner_code = GET_CODE (lhs);
7957   if (inner_code != GET_CODE (rhs))
7958     return x;
7959
7960   /* See if the inner and outer operations distribute.  */
7961   switch (inner_code)
7962     {
7963     case LSHIFTRT:
7964     case ASHIFTRT:
7965     case AND:
7966     case IOR:
7967       /* These all distribute except over PLUS.  */
7968       if (code == PLUS || code == MINUS)
7969         return x;
7970       break;
7971
7972     case MULT:
7973       if (code != PLUS && code != MINUS)
7974         return x;
7975       break;
7976
7977     case ASHIFT:
7978       /* This is also a multiply, so it distributes over everything.  */
7979       break;
7980
7981     case SUBREG:
7982       /* Non-paradoxical SUBREGs distributes over all operations,
7983          provided the inner modes and byte offsets are the same, this
7984          is an extraction of a low-order part, we don't convert an fp
7985          operation to int or vice versa, this is not a vector mode,
7986          and we would not be converting a single-word operation into a
7987          multi-word operation.  The latter test is not required, but
7988          it prevents generating unneeded multi-word operations.  Some
7989          of the previous tests are redundant given the latter test,
7990          but are retained because they are required for correctness.
7991
7992          We produce the result slightly differently in this case.  */
7993
7994       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7995           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7996           || ! subreg_lowpart_p (lhs)
7997           || (GET_MODE_CLASS (GET_MODE (lhs))
7998               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7999           || (GET_MODE_SIZE (GET_MODE (lhs))
8000               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8001           || VECTOR_MODE_P (GET_MODE (lhs))
8002           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8003           /* Result might need to be truncated.  Don't change mode if
8004              explicit truncation is needed.  */
8005           || !TRULY_NOOP_TRUNCATION
8006                (GET_MODE_BITSIZE (GET_MODE (x)),
8007                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8008         return x;
8009
8010       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8011                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
8012       return gen_lowpart (GET_MODE (x), tem);
8013
8014     default:
8015       return x;
8016     }
8017
8018   /* Set LHS and RHS to the inner operands (A and B in the example
8019      above) and set OTHER to the common operand (C in the example).
8020      There is only one way to do this unless the inner operation is
8021      commutative.  */
8022   if (COMMUTATIVE_ARITH_P (lhs)
8023       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8024     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8025   else if (COMMUTATIVE_ARITH_P (lhs)
8026            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8027     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8028   else if (COMMUTATIVE_ARITH_P (lhs)
8029            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8030     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8031   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8032     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8033   else
8034     return x;
8035
8036   /* Form the new inner operation, seeing if it simplifies first.  */
8037   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8038
8039   /* There is one exception to the general way of distributing:
8040      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8041   if (code == XOR && inner_code == IOR)
8042     {
8043       inner_code = AND;
8044       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8045     }
8046
8047   /* We may be able to continuing distributing the result, so call
8048      ourselves recursively on the inner operation before forming the
8049      outer operation, which we return.  */
8050   return simplify_gen_binary (inner_code, GET_MODE (x),
8051                               apply_distributive_law (tem), other);
8052 }
8053
8054 /* See if X is of the form (* (+ A B) C), and if so convert to
8055    (+ (* A C) (* B C)) and try to simplify.
8056
8057    Most of the time, this results in no change.  However, if some of
8058    the operands are the same or inverses of each other, simplifications
8059    will result.
8060
8061    For example, (and (ior A B) (not B)) can occur as the result of
8062    expanding a bit field assignment.  When we apply the distributive
8063    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8064    which then simplifies to (and (A (not B))).
8065
8066    Note that no checks happen on the validity of applying the inverse
8067    distributive law.  This is pointless since we can do it in the
8068    few places where this routine is called.
8069
8070    N is the index of the term that is decomposed (the arithmetic operation,
8071    i.e. (+ A B) in the first example above).  !N is the index of the term that
8072    is distributed, i.e. of C in the first example above.  */
8073 static rtx
8074 distribute_and_simplify_rtx (rtx x, int n)
8075 {
8076   enum machine_mode mode;
8077   enum rtx_code outer_code, inner_code;
8078   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8079
8080   decomposed = XEXP (x, n);
8081   if (!ARITHMETIC_P (decomposed))
8082     return NULL_RTX;
8083
8084   mode = GET_MODE (x);
8085   outer_code = GET_CODE (x);
8086   distributed = XEXP (x, !n);
8087
8088   inner_code = GET_CODE (decomposed);
8089   inner_op0 = XEXP (decomposed, 0);
8090   inner_op1 = XEXP (decomposed, 1);
8091
8092   /* Special case (and (xor B C) (not A)), which is equivalent to
8093      (xor (ior A B) (ior A C))  */
8094   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8095     {
8096       distributed = XEXP (distributed, 0);
8097       outer_code = IOR;
8098     }
8099
8100   if (n == 0)
8101     {
8102       /* Distribute the second term.  */
8103       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8104       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8105     }
8106   else
8107     {
8108       /* Distribute the first term.  */
8109       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8110       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8111     }
8112
8113   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8114                                                      new_op0, new_op1));
8115   if (GET_CODE (tmp) != outer_code
8116       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8117     return tmp;
8118
8119   return NULL_RTX;
8120 }
8121 \f
8122 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8123    in MODE.  Return an equivalent form, if different from (and VAROP
8124    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8125
8126 static rtx
8127 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8128                           unsigned HOST_WIDE_INT constop)
8129 {
8130   unsigned HOST_WIDE_INT nonzero;
8131   unsigned HOST_WIDE_INT orig_constop;
8132   rtx orig_varop;
8133   int i;
8134
8135   orig_varop = varop;
8136   orig_constop = constop;
8137   if (GET_CODE (varop) == CLOBBER)
8138     return NULL_RTX;
8139
8140   /* Simplify VAROP knowing that we will be only looking at some of the
8141      bits in it.
8142
8143      Note by passing in CONSTOP, we guarantee that the bits not set in
8144      CONSTOP are not significant and will never be examined.  We must
8145      ensure that is the case by explicitly masking out those bits
8146      before returning.  */
8147   varop = force_to_mode (varop, mode, constop, 0);
8148
8149   /* If VAROP is a CLOBBER, we will fail so return it.  */
8150   if (GET_CODE (varop) == CLOBBER)
8151     return varop;
8152
8153   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8154      to VAROP and return the new constant.  */
8155   if (GET_CODE (varop) == CONST_INT)
8156     return gen_int_mode (INTVAL (varop) & constop, mode);
8157
8158   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8159      a call to nonzero_bits, here we don't care about bits outside
8160      MODE.  */
8161
8162   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8163
8164   /* Turn off all bits in the constant that are known to already be zero.
8165      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8166      which is tested below.  */
8167
8168   constop &= nonzero;
8169
8170   /* If we don't have any bits left, return zero.  */
8171   if (constop == 0)
8172     return const0_rtx;
8173
8174   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8175      a power of two, we can replace this with an ASHIFT.  */
8176   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8177       && (i = exact_log2 (constop)) >= 0)
8178     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8179
8180   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8181      or XOR, then try to apply the distributive law.  This may eliminate
8182      operations if either branch can be simplified because of the AND.
8183      It may also make some cases more complex, but those cases probably
8184      won't match a pattern either with or without this.  */
8185
8186   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8187     return
8188       gen_lowpart
8189         (mode,
8190          apply_distributive_law
8191          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8192                                simplify_and_const_int (NULL_RTX,
8193                                                        GET_MODE (varop),
8194                                                        XEXP (varop, 0),
8195                                                        constop),
8196                                simplify_and_const_int (NULL_RTX,
8197                                                        GET_MODE (varop),
8198                                                        XEXP (varop, 1),
8199                                                        constop))));
8200
8201   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8202      the AND and see if one of the operands simplifies to zero.  If so, we
8203      may eliminate it.  */
8204
8205   if (GET_CODE (varop) == PLUS
8206       && exact_log2 (constop + 1) >= 0)
8207     {
8208       rtx o0, o1;
8209
8210       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8211       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8212       if (o0 == const0_rtx)
8213         return o1;
8214       if (o1 == const0_rtx)
8215         return o0;
8216     }
8217
8218   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8219   varop = gen_lowpart (mode, varop);
8220   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8221     return NULL_RTX;
8222
8223   /* If we are only masking insignificant bits, return VAROP.  */
8224   if (constop == nonzero)
8225     return varop;
8226
8227   if (varop == orig_varop && constop == orig_constop)
8228     return NULL_RTX;
8229
8230   /* Otherwise, return an AND.  */
8231   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8232 }
8233
8234
8235 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8236    in MODE.
8237
8238    Return an equivalent form, if different from X.  Otherwise, return X.  If
8239    X is zero, we are to always construct the equivalent form.  */
8240
8241 static rtx
8242 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8243                         unsigned HOST_WIDE_INT constop)
8244 {
8245   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8246   if (tem)
8247     return tem;
8248
8249   if (!x)
8250     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8251                              gen_int_mode (constop, mode));
8252   if (GET_MODE (x) != mode)
8253     x = gen_lowpart (mode, x);
8254   return x;
8255 }
8256 \f
8257 /* Given a REG, X, compute which bits in X can be nonzero.
8258    We don't care about bits outside of those defined in MODE.
8259
8260    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8261    a shift, AND, or zero_extract, we can do better.  */
8262
8263 static rtx
8264 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8265                               rtx known_x ATTRIBUTE_UNUSED,
8266                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8267                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8268                               unsigned HOST_WIDE_INT *nonzero)
8269 {
8270   rtx tem;
8271
8272   /* If X is a register whose nonzero bits value is current, use it.
8273      Otherwise, if X is a register whose value we can find, use that
8274      value.  Otherwise, use the previously-computed global nonzero bits
8275      for this register.  */
8276
8277   if (reg_stat[REGNO (x)].last_set_value != 0
8278       && (reg_stat[REGNO (x)].last_set_mode == mode
8279           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8280               && GET_MODE_CLASS (mode) == MODE_INT))
8281       && (reg_stat[REGNO (x)].last_set_label == label_tick
8282           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8283               && REG_N_SETS (REGNO (x)) == 1
8284               && ! REGNO_REG_SET_P
8285                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8286                   REGNO (x))))
8287       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8288     {
8289       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8290       return NULL;
8291     }
8292
8293   tem = get_last_value (x);
8294
8295   if (tem)
8296     {
8297 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8298       /* If X is narrower than MODE and TEM is a non-negative
8299          constant that would appear negative in the mode of X,
8300          sign-extend it for use in reg_nonzero_bits because some
8301          machines (maybe most) will actually do the sign-extension
8302          and this is the conservative approach.
8303
8304          ??? For 2.5, try to tighten up the MD files in this regard
8305          instead of this kludge.  */
8306
8307       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8308           && GET_CODE (tem) == CONST_INT
8309           && INTVAL (tem) > 0
8310           && 0 != (INTVAL (tem)
8311                    & ((HOST_WIDE_INT) 1
8312                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8313         tem = GEN_INT (INTVAL (tem)
8314                        | ((HOST_WIDE_INT) (-1)
8315                           << GET_MODE_BITSIZE (GET_MODE (x))));
8316 #endif
8317       return tem;
8318     }
8319   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8320     {
8321       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8322
8323       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8324         /* We don't know anything about the upper bits.  */
8325         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8326       *nonzero &= mask;
8327     }
8328
8329   return NULL;
8330 }
8331
8332 /* Return the number of bits at the high-order end of X that are known to
8333    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8334    VOIDmode, X will be used in its own mode.  The returned value  will always
8335    be between 1 and the number of bits in MODE.  */
8336
8337 static rtx
8338 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8339                                      rtx known_x ATTRIBUTE_UNUSED,
8340                                      enum machine_mode known_mode
8341                                      ATTRIBUTE_UNUSED,
8342                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8343                                      unsigned int *result)
8344 {
8345   rtx tem;
8346
8347   if (reg_stat[REGNO (x)].last_set_value != 0
8348       && reg_stat[REGNO (x)].last_set_mode == mode
8349       && (reg_stat[REGNO (x)].last_set_label == label_tick
8350           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8351               && REG_N_SETS (REGNO (x)) == 1
8352               && ! REGNO_REG_SET_P
8353                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8354                   REGNO (x))))
8355       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8356     {
8357       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8358       return NULL;
8359     }
8360
8361   tem = get_last_value (x);
8362   if (tem != 0)
8363     return tem;
8364
8365   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8366       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8367     *result = reg_stat[REGNO (x)].sign_bit_copies;
8368
8369   return NULL;
8370 }
8371 \f
8372 /* Return the number of "extended" bits there are in X, when interpreted
8373    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8374    unsigned quantities, this is the number of high-order zero bits.
8375    For signed quantities, this is the number of copies of the sign bit
8376    minus 1.  In both case, this function returns the number of "spare"
8377    bits.  For example, if two quantities for which this function returns
8378    at least 1 are added, the addition is known not to overflow.
8379
8380    This function will always return 0 unless called during combine, which
8381    implies that it must be called from a define_split.  */
8382
8383 unsigned int
8384 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8385 {
8386   if (nonzero_sign_valid == 0)
8387     return 0;
8388
8389   return (unsignedp
8390           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8391              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8392                                - floor_log2 (nonzero_bits (x, mode)))
8393              : 0)
8394           : num_sign_bit_copies (x, mode) - 1);
8395 }
8396 \f
8397 /* This function is called from `simplify_shift_const' to merge two
8398    outer operations.  Specifically, we have already found that we need
8399    to perform operation *POP0 with constant *PCONST0 at the outermost
8400    position.  We would now like to also perform OP1 with constant CONST1
8401    (with *POP0 being done last).
8402
8403    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8404    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8405    complement the innermost operand, otherwise it is unchanged.
8406
8407    MODE is the mode in which the operation will be done.  No bits outside
8408    the width of this mode matter.  It is assumed that the width of this mode
8409    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8410
8411    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8412    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8413    result is simply *PCONST0.
8414
8415    If the resulting operation cannot be expressed as one operation, we
8416    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8417
8418 static int
8419 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8420 {
8421   enum rtx_code op0 = *pop0;
8422   HOST_WIDE_INT const0 = *pconst0;
8423
8424   const0 &= GET_MODE_MASK (mode);
8425   const1 &= GET_MODE_MASK (mode);
8426
8427   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8428   if (op0 == AND)
8429     const1 &= const0;
8430
8431   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8432      if OP0 is SET.  */
8433
8434   if (op1 == UNKNOWN || op0 == SET)
8435     return 1;
8436
8437   else if (op0 == UNKNOWN)
8438     op0 = op1, const0 = const1;
8439
8440   else if (op0 == op1)
8441     {
8442       switch (op0)
8443         {
8444         case AND:
8445           const0 &= const1;
8446           break;
8447         case IOR:
8448           const0 |= const1;
8449           break;
8450         case XOR:
8451           const0 ^= const1;
8452           break;
8453         case PLUS:
8454           const0 += const1;
8455           break;
8456         case NEG:
8457           op0 = UNKNOWN;
8458           break;
8459         default:
8460           break;
8461         }
8462     }
8463
8464   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8465   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8466     return 0;
8467
8468   /* If the two constants aren't the same, we can't do anything.  The
8469      remaining six cases can all be done.  */
8470   else if (const0 != const1)
8471     return 0;
8472
8473   else
8474     switch (op0)
8475       {
8476       case IOR:
8477         if (op1 == AND)
8478           /* (a & b) | b == b */
8479           op0 = SET;
8480         else /* op1 == XOR */
8481           /* (a ^ b) | b == a | b */
8482           {;}
8483         break;
8484
8485       case XOR:
8486         if (op1 == AND)
8487           /* (a & b) ^ b == (~a) & b */
8488           op0 = AND, *pcomp_p = 1;
8489         else /* op1 == IOR */
8490           /* (a | b) ^ b == a & ~b */
8491           op0 = AND, const0 = ~const0;
8492         break;
8493
8494       case AND:
8495         if (op1 == IOR)
8496           /* (a | b) & b == b */
8497         op0 = SET;
8498         else /* op1 == XOR */
8499           /* (a ^ b) & b) == (~a) & b */
8500           *pcomp_p = 1;
8501         break;
8502       default:
8503         break;
8504       }
8505
8506   /* Check for NO-OP cases.  */
8507   const0 &= GET_MODE_MASK (mode);
8508   if (const0 == 0
8509       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8510     op0 = UNKNOWN;
8511   else if (const0 == 0 && op0 == AND)
8512     op0 = SET;
8513   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8514            && op0 == AND)
8515     op0 = UNKNOWN;
8516
8517   /* ??? Slightly redundant with the above mask, but not entirely.
8518      Moving this above means we'd have to sign-extend the mode mask
8519      for the final test.  */
8520   const0 = trunc_int_for_mode (const0, mode);
8521
8522   *pop0 = op0;
8523   *pconst0 = const0;
8524
8525   return 1;
8526 }
8527 \f
8528 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8529    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8530    simplify it.  Otherwise, return a simplified value.
8531
8532    The shift is normally computed in the widest mode we find in VAROP, as
8533    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8534    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8535
8536 static rtx
8537 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8538                         rtx varop, int orig_count)
8539 {
8540   enum rtx_code orig_code = code;
8541   rtx orig_varop = varop;
8542   int count;
8543   enum machine_mode mode = result_mode;
8544   enum machine_mode shift_mode, tmode;
8545   unsigned int mode_words
8546     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8547   /* We form (outer_op (code varop count) (outer_const)).  */
8548   enum rtx_code outer_op = UNKNOWN;
8549   HOST_WIDE_INT outer_const = 0;
8550   int complement_p = 0;
8551   rtx new, x;
8552
8553   /* Make sure and truncate the "natural" shift on the way in.  We don't
8554      want to do this inside the loop as it makes it more difficult to
8555      combine shifts.  */
8556   if (SHIFT_COUNT_TRUNCATED)
8557     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8558
8559   /* If we were given an invalid count, don't do anything except exactly
8560      what was requested.  */
8561
8562   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8563     return NULL_RTX;
8564
8565   count = orig_count;
8566
8567   /* Unless one of the branches of the `if' in this loop does a `continue',
8568      we will `break' the loop after the `if'.  */
8569
8570   while (count != 0)
8571     {
8572       /* If we have an operand of (clobber (const_int 0)), fail.  */
8573       if (GET_CODE (varop) == CLOBBER)
8574         return NULL_RTX;
8575
8576       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8577          here would cause an infinite loop.  */
8578       if (complement_p)
8579         break;
8580
8581       /* Convert ROTATERT to ROTATE.  */
8582       if (code == ROTATERT)
8583         {
8584           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8585           code = ROTATE;
8586           if (VECTOR_MODE_P (result_mode))
8587             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8588           else
8589             count = bitsize - count;
8590         }
8591
8592       /* We need to determine what mode we will do the shift in.  If the
8593          shift is a right shift or a ROTATE, we must always do it in the mode
8594          it was originally done in.  Otherwise, we can do it in MODE, the
8595          widest mode encountered.  */
8596       shift_mode
8597         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8598            ? result_mode : mode);
8599
8600       /* Handle cases where the count is greater than the size of the mode
8601          minus 1.  For ASHIFT, use the size minus one as the count (this can
8602          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8603          take the count modulo the size.  For other shifts, the result is
8604          zero.
8605
8606          Since these shifts are being produced by the compiler by combining
8607          multiple operations, each of which are defined, we know what the
8608          result is supposed to be.  */
8609
8610       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8611         {
8612           if (code == ASHIFTRT)
8613             count = GET_MODE_BITSIZE (shift_mode) - 1;
8614           else if (code == ROTATE || code == ROTATERT)
8615             count %= GET_MODE_BITSIZE (shift_mode);
8616           else
8617             {
8618               /* We can't simply return zero because there may be an
8619                  outer op.  */
8620               varop = const0_rtx;
8621               count = 0;
8622               break;
8623             }
8624         }
8625
8626       /* An arithmetic right shift of a quantity known to be -1 or 0
8627          is a no-op.  */
8628       if (code == ASHIFTRT
8629           && (num_sign_bit_copies (varop, shift_mode)
8630               == GET_MODE_BITSIZE (shift_mode)))
8631         {
8632           count = 0;
8633           break;
8634         }
8635
8636       /* If we are doing an arithmetic right shift and discarding all but
8637          the sign bit copies, this is equivalent to doing a shift by the
8638          bitsize minus one.  Convert it into that shift because it will often
8639          allow other simplifications.  */
8640
8641       if (code == ASHIFTRT
8642           && (count + num_sign_bit_copies (varop, shift_mode)
8643               >= GET_MODE_BITSIZE (shift_mode)))
8644         count = GET_MODE_BITSIZE (shift_mode) - 1;
8645
8646       /* We simplify the tests below and elsewhere by converting
8647          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8648          `make_compound_operation' will convert it to an ASHIFTRT for
8649          those machines (such as VAX) that don't have an LSHIFTRT.  */
8650       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8651           && code == ASHIFTRT
8652           && ((nonzero_bits (varop, shift_mode)
8653                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8654               == 0))
8655         code = LSHIFTRT;
8656
8657       if (((code == LSHIFTRT
8658             && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8659             && !(nonzero_bits (varop, shift_mode) >> count))
8660            || (code == ASHIFT
8661                && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8662                && !((nonzero_bits (varop, shift_mode) << count)
8663                     & GET_MODE_MASK (shift_mode))))
8664           && !side_effects_p (varop))
8665         varop = const0_rtx;
8666
8667       switch (GET_CODE (varop))
8668         {
8669         case SIGN_EXTEND:
8670         case ZERO_EXTEND:
8671         case SIGN_EXTRACT:
8672         case ZERO_EXTRACT:
8673           new = expand_compound_operation (varop);
8674           if (new != varop)
8675             {
8676               varop = new;
8677               continue;
8678             }
8679           break;
8680
8681         case MEM:
8682           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8683              minus the width of a smaller mode, we can do this with a
8684              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8685           if ((code == ASHIFTRT || code == LSHIFTRT)
8686               && ! mode_dependent_address_p (XEXP (varop, 0))
8687               && ! MEM_VOLATILE_P (varop)
8688               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8689                                          MODE_INT, 1)) != BLKmode)
8690             {
8691               new = adjust_address_nv (varop, tmode,
8692                                        BYTES_BIG_ENDIAN ? 0
8693                                        : count / BITS_PER_UNIT);
8694
8695               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8696                                      : ZERO_EXTEND, mode, new);
8697               count = 0;
8698               continue;
8699             }
8700           break;
8701
8702         case SUBREG:
8703           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8704              the same number of words as what we've seen so far.  Then store
8705              the widest mode in MODE.  */
8706           if (subreg_lowpart_p (varop)
8707               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8708                   > GET_MODE_SIZE (GET_MODE (varop)))
8709               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8710                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8711                  == mode_words)
8712             {
8713               varop = SUBREG_REG (varop);
8714               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8715                 mode = GET_MODE (varop);
8716               continue;
8717             }
8718           break;
8719
8720         case MULT:
8721           /* Some machines use MULT instead of ASHIFT because MULT
8722              is cheaper.  But it is still better on those machines to
8723              merge two shifts into one.  */
8724           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8725               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8726             {
8727               varop
8728                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8729                                        XEXP (varop, 0),
8730                                        GEN_INT (exact_log2 (
8731                                                 INTVAL (XEXP (varop, 1)))));
8732               continue;
8733             }
8734           break;
8735
8736         case UDIV:
8737           /* Similar, for when divides are cheaper.  */
8738           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8739               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8740             {
8741               varop
8742                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8743                                        XEXP (varop, 0),
8744                                        GEN_INT (exact_log2 (
8745                                                 INTVAL (XEXP (varop, 1)))));
8746               continue;
8747             }
8748           break;
8749
8750         case ASHIFTRT:
8751           /* If we are extracting just the sign bit of an arithmetic
8752              right shift, that shift is not needed.  However, the sign
8753              bit of a wider mode may be different from what would be
8754              interpreted as the sign bit in a narrower mode, so, if
8755              the result is narrower, don't discard the shift.  */
8756           if (code == LSHIFTRT
8757               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8758               && (GET_MODE_BITSIZE (result_mode)
8759                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8760             {
8761               varop = XEXP (varop, 0);
8762               continue;
8763             }
8764
8765           /* ... fall through ...  */
8766
8767         case LSHIFTRT:
8768         case ASHIFT:
8769         case ROTATE:
8770           /* Here we have two nested shifts.  The result is usually the
8771              AND of a new shift with a mask.  We compute the result below.  */
8772           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8773               && INTVAL (XEXP (varop, 1)) >= 0
8774               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8775               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8776               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8777               && !VECTOR_MODE_P (result_mode))
8778             {
8779               enum rtx_code first_code = GET_CODE (varop);
8780               unsigned int first_count = INTVAL (XEXP (varop, 1));
8781               unsigned HOST_WIDE_INT mask;
8782               rtx mask_rtx;
8783
8784               /* We have one common special case.  We can't do any merging if
8785                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8786                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8787                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8788                  we can convert it to
8789                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8790                  This simplifies certain SIGN_EXTEND operations.  */
8791               if (code == ASHIFT && first_code == ASHIFTRT
8792                   && count == (GET_MODE_BITSIZE (result_mode)
8793                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8794                 {
8795                   /* C3 has the low-order C1 bits zero.  */
8796
8797                   mask = (GET_MODE_MASK (mode)
8798                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8799
8800                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8801                                                   XEXP (varop, 0), mask);
8802                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8803                                                 varop, count);
8804                   count = first_count;
8805                   code = ASHIFTRT;
8806                   continue;
8807                 }
8808
8809               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8810                  than C1 high-order bits equal to the sign bit, we can convert
8811                  this to either an ASHIFT or an ASHIFTRT depending on the
8812                  two counts.
8813
8814                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8815
8816               if (code == ASHIFTRT && first_code == ASHIFT
8817                   && GET_MODE (varop) == shift_mode
8818                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8819                       > first_count))
8820                 {
8821                   varop = XEXP (varop, 0);
8822                   count -= first_count;
8823                   if (count < 0)
8824                     {
8825                       count = -count;
8826                       code = ASHIFT;
8827                     }
8828
8829                   continue;
8830                 }
8831
8832               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8833                  we can only do this if FIRST_CODE is also ASHIFTRT.
8834
8835                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8836                  ASHIFTRT.
8837
8838                  If the mode of this shift is not the mode of the outer shift,
8839                  we can't do this if either shift is a right shift or ROTATE.
8840
8841                  Finally, we can't do any of these if the mode is too wide
8842                  unless the codes are the same.
8843
8844                  Handle the case where the shift codes are the same
8845                  first.  */
8846
8847               if (code == first_code)
8848                 {
8849                   if (GET_MODE (varop) != result_mode
8850                       && (code == ASHIFTRT || code == LSHIFTRT
8851                           || code == ROTATE))
8852                     break;
8853
8854                   count += first_count;
8855                   varop = XEXP (varop, 0);
8856                   continue;
8857                 }
8858
8859               if (code == ASHIFTRT
8860                   || (code == ROTATE && first_code == ASHIFTRT)
8861                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8862                   || (GET_MODE (varop) != result_mode
8863                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8864                           || first_code == ROTATE
8865                           || code == ROTATE)))
8866                 break;
8867
8868               /* To compute the mask to apply after the shift, shift the
8869                  nonzero bits of the inner shift the same way the
8870                  outer shift will.  */
8871
8872               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8873
8874               mask_rtx
8875                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8876                                                    GEN_INT (count));
8877
8878               /* Give up if we can't compute an outer operation to use.  */
8879               if (mask_rtx == 0
8880                   || GET_CODE (mask_rtx) != CONST_INT
8881                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8882                                         INTVAL (mask_rtx),
8883                                         result_mode, &complement_p))
8884                 break;
8885
8886               /* If the shifts are in the same direction, we add the
8887                  counts.  Otherwise, we subtract them.  */
8888               if ((code == ASHIFTRT || code == LSHIFTRT)
8889                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8890                 count += first_count;
8891               else
8892                 count -= first_count;
8893
8894               /* If COUNT is positive, the new shift is usually CODE,
8895                  except for the two exceptions below, in which case it is
8896                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8897                  always be used  */
8898               if (count > 0
8899                   && ((first_code == ROTATE && code == ASHIFT)
8900                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8901                 code = first_code;
8902               else if (count < 0)
8903                 code = first_code, count = -count;
8904
8905               varop = XEXP (varop, 0);
8906               continue;
8907             }
8908
8909           /* If we have (A << B << C) for any shift, we can convert this to
8910              (A << C << B).  This wins if A is a constant.  Only try this if
8911              B is not a constant.  */
8912
8913           else if (GET_CODE (varop) == code
8914                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8915                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8916             {
8917               rtx new = simplify_const_binary_operation (code, mode,
8918                                                          XEXP (varop, 0),
8919                                                          GEN_INT (count));
8920               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8921               count = 0;
8922               continue;
8923             }
8924           break;
8925
8926         case NOT:
8927           /* Make this fit the case below.  */
8928           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8929                                GEN_INT (GET_MODE_MASK (mode)));
8930           continue;
8931
8932         case IOR:
8933         case AND:
8934         case XOR:
8935           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8936              with C the size of VAROP - 1 and the shift is logical if
8937              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8938              we have an (le X 0) operation.   If we have an arithmetic shift
8939              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8940              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8941
8942           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8943               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8944               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8945               && (code == LSHIFTRT || code == ASHIFTRT)
8946               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8947               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8948             {
8949               count = 0;
8950               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8951                                   const0_rtx);
8952
8953               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8954                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8955
8956               continue;
8957             }
8958
8959           /* If we have (shift (logical)), move the logical to the outside
8960              to allow it to possibly combine with another logical and the
8961              shift to combine with another shift.  This also canonicalizes to
8962              what a ZERO_EXTRACT looks like.  Also, some machines have
8963              (and (shift)) insns.  */
8964
8965           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8966               /* We can't do this if we have (ashiftrt (xor))  and the
8967                  constant has its sign bit set in shift_mode.  */
8968               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8969                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8970                                               shift_mode))
8971               && (new = simplify_const_binary_operation (code, result_mode,
8972                                                          XEXP (varop, 1),
8973                                                          GEN_INT (count))) != 0
8974               && GET_CODE (new) == CONST_INT
8975               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8976                                   INTVAL (new), result_mode, &complement_p))
8977             {
8978               varop = XEXP (varop, 0);
8979               continue;
8980             }
8981
8982           /* If we can't do that, try to simplify the shift in each arm of the
8983              logical expression, make a new logical expression, and apply
8984              the inverse distributive law.  This also can't be done
8985              for some (ashiftrt (xor)).  */
8986           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8987              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8988                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8989                                              shift_mode)))
8990             {
8991               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8992                                               XEXP (varop, 0), count);
8993               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8994                                               XEXP (varop, 1), count);
8995
8996               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8997                                            lhs, rhs);
8998               varop = apply_distributive_law (varop);
8999
9000               count = 0;
9001               continue;
9002             }
9003           break;
9004
9005         case EQ:
9006           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9007              says that the sign bit can be tested, FOO has mode MODE, C is
9008              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9009              that may be nonzero.  */
9010           if (code == LSHIFTRT
9011               && XEXP (varop, 1) == const0_rtx
9012               && GET_MODE (XEXP (varop, 0)) == result_mode
9013               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9014               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9015               && STORE_FLAG_VALUE == -1
9016               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9017               && merge_outer_ops (&outer_op, &outer_const, XOR,
9018                                   (HOST_WIDE_INT) 1, result_mode,
9019                                   &complement_p))
9020             {
9021               varop = XEXP (varop, 0);
9022               count = 0;
9023               continue;
9024             }
9025           break;
9026
9027         case NEG:
9028           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9029              than the number of bits in the mode is equivalent to A.  */
9030           if (code == LSHIFTRT
9031               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9032               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9033             {
9034               varop = XEXP (varop, 0);
9035               count = 0;
9036               continue;
9037             }
9038
9039           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9040              NEG outside to allow shifts to combine.  */
9041           if (code == ASHIFT
9042               && merge_outer_ops (&outer_op, &outer_const, NEG,
9043                                   (HOST_WIDE_INT) 0, result_mode,
9044                                   &complement_p))
9045             {
9046               varop = XEXP (varop, 0);
9047               continue;
9048             }
9049           break;
9050
9051         case PLUS:
9052           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9053              is one less than the number of bits in the mode is
9054              equivalent to (xor A 1).  */
9055           if (code == LSHIFTRT
9056               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9057               && XEXP (varop, 1) == constm1_rtx
9058               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9059               && merge_outer_ops (&outer_op, &outer_const, XOR,
9060                                   (HOST_WIDE_INT) 1, result_mode,
9061                                   &complement_p))
9062             {
9063               count = 0;
9064               varop = XEXP (varop, 0);
9065               continue;
9066             }
9067
9068           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9069              that might be nonzero in BAR are those being shifted out and those
9070              bits are known zero in FOO, we can replace the PLUS with FOO.
9071              Similarly in the other operand order.  This code occurs when
9072              we are computing the size of a variable-size array.  */
9073
9074           if ((code == ASHIFTRT || code == LSHIFTRT)
9075               && count < HOST_BITS_PER_WIDE_INT
9076               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9077               && (nonzero_bits (XEXP (varop, 1), result_mode)
9078                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9079             {
9080               varop = XEXP (varop, 0);
9081               continue;
9082             }
9083           else if ((code == ASHIFTRT || code == LSHIFTRT)
9084                    && count < HOST_BITS_PER_WIDE_INT
9085                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9086                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9087                             >> count)
9088                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9089                             & nonzero_bits (XEXP (varop, 1),
9090                                                  result_mode)))
9091             {
9092               varop = XEXP (varop, 1);
9093               continue;
9094             }
9095
9096           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9097           if (code == ASHIFT
9098               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9099               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9100                                                          XEXP (varop, 1),
9101                                                          GEN_INT (count))) != 0
9102               && GET_CODE (new) == CONST_INT
9103               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9104                                   INTVAL (new), result_mode, &complement_p))
9105             {
9106               varop = XEXP (varop, 0);
9107               continue;
9108             }
9109
9110           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9111              signbit', and attempt to change the PLUS to an XOR and move it to
9112              the outer operation as is done above in the AND/IOR/XOR case
9113              leg for shift(logical). See details in logical handling above
9114              for reasoning in doing so.  */
9115           if (code == LSHIFTRT
9116               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9117               && mode_signbit_p (result_mode, XEXP (varop, 1))
9118               && (new = simplify_const_binary_operation (code, result_mode,
9119                                                          XEXP (varop, 1),
9120                                                          GEN_INT (count))) != 0
9121               && GET_CODE (new) == CONST_INT
9122               && merge_outer_ops (&outer_op, &outer_const, XOR,
9123                                   INTVAL (new), result_mode, &complement_p))
9124             {
9125               varop = XEXP (varop, 0);
9126               continue;
9127             }
9128
9129           break;
9130
9131         case MINUS:
9132           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9133              with C the size of VAROP - 1 and the shift is logical if
9134              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9135              we have a (gt X 0) operation.  If the shift is arithmetic with
9136              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9137              we have a (neg (gt X 0)) operation.  */
9138
9139           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9140               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9141               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9142               && (code == LSHIFTRT || code == ASHIFTRT)
9143               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9144               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9145               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9146             {
9147               count = 0;
9148               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9149                                   const0_rtx);
9150
9151               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9152                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9153
9154               continue;
9155             }
9156           break;
9157
9158         case TRUNCATE:
9159           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9160              if the truncate does not affect the value.  */
9161           if (code == LSHIFTRT
9162               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9163               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9164               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9165                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9166                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9167             {
9168               rtx varop_inner = XEXP (varop, 0);
9169
9170               varop_inner
9171                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9172                                     XEXP (varop_inner, 0),
9173                                     GEN_INT
9174                                     (count + INTVAL (XEXP (varop_inner, 1))));
9175               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9176               count = 0;
9177               continue;
9178             }
9179           break;
9180
9181         default:
9182           break;
9183         }
9184
9185       break;
9186     }
9187
9188   /* We need to determine what mode to do the shift in.  If the shift is
9189      a right shift or ROTATE, we must always do it in the mode it was
9190      originally done in.  Otherwise, we can do it in MODE, the widest mode
9191      encountered.  The code we care about is that of the shift that will
9192      actually be done, not the shift that was originally requested.  */
9193   shift_mode
9194     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9195        ? result_mode : mode);
9196
9197   /* We have now finished analyzing the shift.  The result should be
9198      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9199      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9200      to the result of the shift.  OUTER_CONST is the relevant constant,
9201      but we must turn off all bits turned off in the shift.  */
9202
9203   if (outer_op == UNKNOWN
9204       && orig_code == code && orig_count == count
9205       && varop == orig_varop
9206       && shift_mode == GET_MODE (varop))
9207     return NULL_RTX;
9208
9209   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9210   varop = gen_lowpart (shift_mode, varop);
9211   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9212     return NULL_RTX;
9213
9214   /* If we have an outer operation and we just made a shift, it is
9215      possible that we could have simplified the shift were it not
9216      for the outer operation.  So try to do the simplification
9217      recursively.  */
9218
9219   if (outer_op != UNKNOWN)
9220     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9221   else
9222     x = NULL_RTX;
9223
9224   if (x == NULL_RTX)
9225     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9226
9227   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9228      turn off all the bits that the shift would have turned off.  */
9229   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9230     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9231                                 GET_MODE_MASK (result_mode) >> orig_count);
9232
9233   /* Do the remainder of the processing in RESULT_MODE.  */
9234   x = gen_lowpart_or_truncate (result_mode, x);
9235
9236   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9237      operation.  */
9238   if (complement_p)
9239     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9240
9241   if (outer_op != UNKNOWN)
9242     {
9243       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9244         outer_const = trunc_int_for_mode (outer_const, result_mode);
9245
9246       if (outer_op == AND)
9247         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9248       else if (outer_op == SET)
9249         {
9250           /* This means that we have determined that the result is
9251              equivalent to a constant.  This should be rare.  */
9252           if (!side_effects_p (x))
9253             x = GEN_INT (outer_const);
9254         }
9255       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9256         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9257       else
9258         x = simplify_gen_binary (outer_op, result_mode, x,
9259                                  GEN_INT (outer_const));
9260     }
9261
9262   return x;
9263 }
9264
9265 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9266    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9267    return X or, if it is NULL, synthesize the expression with
9268    simplify_gen_binary.  Otherwise, return a simplified value.
9269
9270    The shift is normally computed in the widest mode we find in VAROP, as
9271    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9272    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9273
9274 static rtx
9275 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9276                       rtx varop, int count)
9277 {
9278   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9279   if (tem)
9280     return tem;
9281
9282   if (!x)
9283     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9284   if (GET_MODE (x) != result_mode)
9285     x = gen_lowpart (result_mode, x);
9286   return x;
9287 }
9288
9289 \f
9290 /* Like recog, but we receive the address of a pointer to a new pattern.
9291    We try to match the rtx that the pointer points to.
9292    If that fails, we may try to modify or replace the pattern,
9293    storing the replacement into the same pointer object.
9294
9295    Modifications include deletion or addition of CLOBBERs.
9296
9297    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9298    the CLOBBERs are placed.
9299
9300    The value is the final insn code from the pattern ultimately matched,
9301    or -1.  */
9302
9303 static int
9304 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9305 {
9306   rtx pat = *pnewpat;
9307   int insn_code_number;
9308   int num_clobbers_to_add = 0;
9309   int i;
9310   rtx notes = 0;
9311   rtx old_notes, old_pat;
9312
9313   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9314      we use to indicate that something didn't match.  If we find such a
9315      thing, force rejection.  */
9316   if (GET_CODE (pat) == PARALLEL)
9317     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9318       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9319           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9320         return -1;
9321
9322   old_pat = PATTERN (insn);
9323   old_notes = REG_NOTES (insn);
9324   PATTERN (insn) = pat;
9325   REG_NOTES (insn) = 0;
9326
9327   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9328
9329   /* If it isn't, there is the possibility that we previously had an insn
9330      that clobbered some register as a side effect, but the combined
9331      insn doesn't need to do that.  So try once more without the clobbers
9332      unless this represents an ASM insn.  */
9333
9334   if (insn_code_number < 0 && ! check_asm_operands (pat)
9335       && GET_CODE (pat) == PARALLEL)
9336     {
9337       int pos;
9338
9339       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9340         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9341           {
9342             if (i != pos)
9343               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9344             pos++;
9345           }
9346
9347       SUBST_INT (XVECLEN (pat, 0), pos);
9348
9349       if (pos == 1)
9350         pat = XVECEXP (pat, 0, 0);
9351
9352       PATTERN (insn) = pat;
9353       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9354     }
9355   PATTERN (insn) = old_pat;
9356   REG_NOTES (insn) = old_notes;
9357
9358   /* Recognize all noop sets, these will be killed by followup pass.  */
9359   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9360     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9361
9362   /* If we had any clobbers to add, make a new pattern than contains
9363      them.  Then check to make sure that all of them are dead.  */
9364   if (num_clobbers_to_add)
9365     {
9366       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9367                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9368                                                   ? (XVECLEN (pat, 0)
9369                                                      + num_clobbers_to_add)
9370                                                   : num_clobbers_to_add + 1));
9371
9372       if (GET_CODE (pat) == PARALLEL)
9373         for (i = 0; i < XVECLEN (pat, 0); i++)
9374           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9375       else
9376         XVECEXP (newpat, 0, 0) = pat;
9377
9378       add_clobbers (newpat, insn_code_number);
9379
9380       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9381            i < XVECLEN (newpat, 0); i++)
9382         {
9383           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9384               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9385             return -1;
9386           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9387                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9388         }
9389       pat = newpat;
9390     }
9391
9392   *pnewpat = pat;
9393   *pnotes = notes;
9394
9395   return insn_code_number;
9396 }
9397 \f
9398 /* Like gen_lowpart_general but for use by combine.  In combine it
9399    is not possible to create any new pseudoregs.  However, it is
9400    safe to create invalid memory addresses, because combine will
9401    try to recognize them and all they will do is make the combine
9402    attempt fail.
9403
9404    If for some reason this cannot do its job, an rtx
9405    (clobber (const_int 0)) is returned.
9406    An insn containing that will not be recognized.  */
9407
9408 static rtx
9409 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9410 {
9411   enum machine_mode imode = GET_MODE (x);
9412   unsigned int osize = GET_MODE_SIZE (omode);
9413   unsigned int isize = GET_MODE_SIZE (imode);
9414   rtx result;
9415
9416   if (omode == imode)
9417     return x;
9418
9419   /* Return identity if this is a CONST or symbolic reference.  */
9420   if (omode == Pmode
9421       && (GET_CODE (x) == CONST
9422           || GET_CODE (x) == SYMBOL_REF
9423           || GET_CODE (x) == LABEL_REF))
9424     return x;
9425
9426   /* We can only support MODE being wider than a word if X is a
9427      constant integer or has a mode the same size.  */
9428   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9429       && ! ((imode == VOIDmode
9430              && (GET_CODE (x) == CONST_INT
9431                  || GET_CODE (x) == CONST_DOUBLE))
9432             || isize == osize))
9433     goto fail;
9434
9435   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9436      won't know what to do.  So we will strip off the SUBREG here and
9437      process normally.  */
9438   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9439     {
9440       x = SUBREG_REG (x);
9441
9442       /* For use in case we fall down into the address adjustments
9443          further below, we need to adjust the known mode and size of
9444          x; imode and isize, since we just adjusted x.  */
9445       imode = GET_MODE (x);
9446
9447       if (imode == omode)
9448         return x;
9449
9450       isize = GET_MODE_SIZE (imode);
9451     }
9452
9453   result = gen_lowpart_common (omode, x);
9454
9455 #ifdef CANNOT_CHANGE_MODE_CLASS
9456   if (result != 0 && GET_CODE (result) == SUBREG)
9457     record_subregs_of_mode (result);
9458 #endif
9459
9460   if (result)
9461     return result;
9462
9463   if (MEM_P (x))
9464     {
9465       int offset = 0;
9466
9467       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9468          address.  */
9469       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9470         goto fail;
9471
9472       /* If we want to refer to something bigger than the original memref,
9473          generate a paradoxical subreg instead.  That will force a reload
9474          of the original memref X.  */
9475       if (isize < osize)
9476         return gen_rtx_SUBREG (omode, x, 0);
9477
9478       if (WORDS_BIG_ENDIAN)
9479         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9480
9481       /* Adjust the address so that the address-after-the-data is
9482          unchanged.  */
9483       if (BYTES_BIG_ENDIAN)
9484         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9485
9486       return adjust_address_nv (x, omode, offset);
9487     }
9488
9489   /* If X is a comparison operator, rewrite it in a new mode.  This
9490      probably won't match, but may allow further simplifications.  */
9491   else if (COMPARISON_P (x))
9492     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9493
9494   /* If we couldn't simplify X any other way, just enclose it in a
9495      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9496      include an explicit SUBREG or we may simplify it further in combine.  */
9497   else
9498     {
9499       int offset = 0;
9500       rtx res;
9501
9502       offset = subreg_lowpart_offset (omode, imode);
9503       if (imode == VOIDmode)
9504         {
9505           imode = int_mode_for_mode (omode);
9506           x = gen_lowpart_common (imode, x);
9507           if (x == NULL)
9508             goto fail;
9509         }
9510       res = simplify_gen_subreg (omode, x, imode, offset);
9511       if (res)
9512         return res;
9513     }
9514
9515  fail:
9516   return gen_rtx_CLOBBER (imode, const0_rtx);
9517 }
9518 \f
9519 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9520    comparison code that will be tested.
9521
9522    The result is a possibly different comparison code to use.  *POP0 and
9523    *POP1 may be updated.
9524
9525    It is possible that we might detect that a comparison is either always
9526    true or always false.  However, we do not perform general constant
9527    folding in combine, so this knowledge isn't useful.  Such tautologies
9528    should have been detected earlier.  Hence we ignore all such cases.  */
9529
9530 static enum rtx_code
9531 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9532 {
9533   rtx op0 = *pop0;
9534   rtx op1 = *pop1;
9535   rtx tem, tem1;
9536   int i;
9537   enum machine_mode mode, tmode;
9538
9539   /* Try a few ways of applying the same transformation to both operands.  */
9540   while (1)
9541     {
9542 #ifndef WORD_REGISTER_OPERATIONS
9543       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9544          so check specially.  */
9545       if (code != GTU && code != GEU && code != LTU && code != LEU
9546           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9547           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9548           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9549           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9550           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9551           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9552               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9553           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9554           && XEXP (op0, 1) == XEXP (op1, 1)
9555           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9556           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9557           && (INTVAL (XEXP (op0, 1))
9558               == (GET_MODE_BITSIZE (GET_MODE (op0))
9559                   - (GET_MODE_BITSIZE
9560                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9561         {
9562           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9563           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9564         }
9565 #endif
9566
9567       /* If both operands are the same constant shift, see if we can ignore the
9568          shift.  We can if the shift is a rotate or if the bits shifted out of
9569          this shift are known to be zero for both inputs and if the type of
9570          comparison is compatible with the shift.  */
9571       if (GET_CODE (op0) == GET_CODE (op1)
9572           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9573           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9574               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9575                   && (code != GT && code != LT && code != GE && code != LE))
9576               || (GET_CODE (op0) == ASHIFTRT
9577                   && (code != GTU && code != LTU
9578                       && code != GEU && code != LEU)))
9579           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9580           && INTVAL (XEXP (op0, 1)) >= 0
9581           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9582           && XEXP (op0, 1) == XEXP (op1, 1))
9583         {
9584           enum machine_mode mode = GET_MODE (op0);
9585           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9586           int shift_count = INTVAL (XEXP (op0, 1));
9587
9588           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9589             mask &= (mask >> shift_count) << shift_count;
9590           else if (GET_CODE (op0) == ASHIFT)
9591             mask = (mask & (mask << shift_count)) >> shift_count;
9592
9593           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9594               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9595             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9596           else
9597             break;
9598         }
9599
9600       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9601          SUBREGs are of the same mode, and, in both cases, the AND would
9602          be redundant if the comparison was done in the narrower mode,
9603          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9604          and the operand's possibly nonzero bits are 0xffffff01; in that case
9605          if we only care about QImode, we don't need the AND).  This case
9606          occurs if the output mode of an scc insn is not SImode and
9607          STORE_FLAG_VALUE == 1 (e.g., the 386).
9608
9609          Similarly, check for a case where the AND's are ZERO_EXTEND
9610          operations from some narrower mode even though a SUBREG is not
9611          present.  */
9612
9613       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9614                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9615                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9616         {
9617           rtx inner_op0 = XEXP (op0, 0);
9618           rtx inner_op1 = XEXP (op1, 0);
9619           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9620           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9621           int changed = 0;
9622
9623           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9624               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9625                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9626               && (GET_MODE (SUBREG_REG (inner_op0))
9627                   == GET_MODE (SUBREG_REG (inner_op1)))
9628               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9629                   <= HOST_BITS_PER_WIDE_INT)
9630               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9631                                              GET_MODE (SUBREG_REG (inner_op0)))))
9632               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9633                                              GET_MODE (SUBREG_REG (inner_op1))))))
9634             {
9635               op0 = SUBREG_REG (inner_op0);
9636               op1 = SUBREG_REG (inner_op1);
9637
9638               /* The resulting comparison is always unsigned since we masked
9639                  off the original sign bit.  */
9640               code = unsigned_condition (code);
9641
9642               changed = 1;
9643             }
9644
9645           else if (c0 == c1)
9646             for (tmode = GET_CLASS_NARROWEST_MODE
9647                  (GET_MODE_CLASS (GET_MODE (op0)));
9648                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9649               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9650                 {
9651                   op0 = gen_lowpart (tmode, inner_op0);
9652                   op1 = gen_lowpart (tmode, inner_op1);
9653                   code = unsigned_condition (code);
9654                   changed = 1;
9655                   break;
9656                 }
9657
9658           if (! changed)
9659             break;
9660         }
9661
9662       /* If both operands are NOT, we can strip off the outer operation
9663          and adjust the comparison code for swapped operands; similarly for
9664          NEG, except that this must be an equality comparison.  */
9665       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9666                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9667                    && (code == EQ || code == NE)))
9668         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9669
9670       else
9671         break;
9672     }
9673
9674   /* If the first operand is a constant, swap the operands and adjust the
9675      comparison code appropriately, but don't do this if the second operand
9676      is already a constant integer.  */
9677   if (swap_commutative_operands_p (op0, op1))
9678     {
9679       tem = op0, op0 = op1, op1 = tem;
9680       code = swap_condition (code);
9681     }
9682
9683   /* We now enter a loop during which we will try to simplify the comparison.
9684      For the most part, we only are concerned with comparisons with zero,
9685      but some things may really be comparisons with zero but not start
9686      out looking that way.  */
9687
9688   while (GET_CODE (op1) == CONST_INT)
9689     {
9690       enum machine_mode mode = GET_MODE (op0);
9691       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9692       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9693       int equality_comparison_p;
9694       int sign_bit_comparison_p;
9695       int unsigned_comparison_p;
9696       HOST_WIDE_INT const_op;
9697
9698       /* We only want to handle integral modes.  This catches VOIDmode,
9699          CCmode, and the floating-point modes.  An exception is that we
9700          can handle VOIDmode if OP0 is a COMPARE or a comparison
9701          operation.  */
9702
9703       if (GET_MODE_CLASS (mode) != MODE_INT
9704           && ! (mode == VOIDmode
9705                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9706         break;
9707
9708       /* Get the constant we are comparing against and turn off all bits
9709          not on in our mode.  */
9710       const_op = INTVAL (op1);
9711       if (mode != VOIDmode)
9712         const_op = trunc_int_for_mode (const_op, mode);
9713       op1 = GEN_INT (const_op);
9714
9715       /* If we are comparing against a constant power of two and the value
9716          being compared can only have that single bit nonzero (e.g., it was
9717          `and'ed with that bit), we can replace this with a comparison
9718          with zero.  */
9719       if (const_op
9720           && (code == EQ || code == NE || code == GE || code == GEU
9721               || code == LT || code == LTU)
9722           && mode_width <= HOST_BITS_PER_WIDE_INT
9723           && exact_log2 (const_op) >= 0
9724           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9725         {
9726           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9727           op1 = const0_rtx, const_op = 0;
9728         }
9729
9730       /* Similarly, if we are comparing a value known to be either -1 or
9731          0 with -1, change it to the opposite comparison against zero.  */
9732
9733       if (const_op == -1
9734           && (code == EQ || code == NE || code == GT || code == LE
9735               || code == GEU || code == LTU)
9736           && num_sign_bit_copies (op0, mode) == mode_width)
9737         {
9738           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9739           op1 = const0_rtx, const_op = 0;
9740         }
9741
9742       /* Do some canonicalizations based on the comparison code.  We prefer
9743          comparisons against zero and then prefer equality comparisons.
9744          If we can reduce the size of a constant, we will do that too.  */
9745
9746       switch (code)
9747         {
9748         case LT:
9749           /* < C is equivalent to <= (C - 1) */
9750           if (const_op > 0)
9751             {
9752               const_op -= 1;
9753               op1 = GEN_INT (const_op);
9754               code = LE;
9755               /* ... fall through to LE case below.  */
9756             }
9757           else
9758             break;
9759
9760         case LE:
9761           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9762           if (const_op < 0)
9763             {
9764               const_op += 1;
9765               op1 = GEN_INT (const_op);
9766               code = LT;
9767             }
9768
9769           /* If we are doing a <= 0 comparison on a value known to have
9770              a zero sign bit, we can replace this with == 0.  */
9771           else if (const_op == 0
9772                    && mode_width <= HOST_BITS_PER_WIDE_INT
9773                    && (nonzero_bits (op0, mode)
9774                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9775             code = EQ;
9776           break;
9777
9778         case GE:
9779           /* >= C is equivalent to > (C - 1).  */
9780           if (const_op > 0)
9781             {
9782               const_op -= 1;
9783               op1 = GEN_INT (const_op);
9784               code = GT;
9785               /* ... fall through to GT below.  */
9786             }
9787           else
9788             break;
9789
9790         case GT:
9791           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9792           if (const_op < 0)
9793             {
9794               const_op += 1;
9795               op1 = GEN_INT (const_op);
9796               code = GE;
9797             }
9798
9799           /* If we are doing a > 0 comparison on a value known to have
9800              a zero sign bit, we can replace this with != 0.  */
9801           else if (const_op == 0
9802                    && mode_width <= HOST_BITS_PER_WIDE_INT
9803                    && (nonzero_bits (op0, mode)
9804                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9805             code = NE;
9806           break;
9807
9808         case LTU:
9809           /* < C is equivalent to <= (C - 1).  */
9810           if (const_op > 0)
9811             {
9812               const_op -= 1;
9813               op1 = GEN_INT (const_op);
9814               code = LEU;
9815               /* ... fall through ...  */
9816             }
9817
9818           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9819           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9820                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9821             {
9822               const_op = 0, op1 = const0_rtx;
9823               code = GE;
9824               break;
9825             }
9826           else
9827             break;
9828
9829         case LEU:
9830           /* unsigned <= 0 is equivalent to == 0 */
9831           if (const_op == 0)
9832             code = EQ;
9833
9834           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9835           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9836                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9837             {
9838               const_op = 0, op1 = const0_rtx;
9839               code = GE;
9840             }
9841           break;
9842
9843         case GEU:
9844           /* >= C is equivalent to > (C - 1).  */
9845           if (const_op > 1)
9846             {
9847               const_op -= 1;
9848               op1 = GEN_INT (const_op);
9849               code = GTU;
9850               /* ... fall through ...  */
9851             }
9852
9853           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9854           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9855                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9856             {
9857               const_op = 0, op1 = const0_rtx;
9858               code = LT;
9859               break;
9860             }
9861           else
9862             break;
9863
9864         case GTU:
9865           /* unsigned > 0 is equivalent to != 0 */
9866           if (const_op == 0)
9867             code = NE;
9868
9869           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9870           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9871                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9872             {
9873               const_op = 0, op1 = const0_rtx;
9874               code = LT;
9875             }
9876           break;
9877
9878         default:
9879           break;
9880         }
9881
9882       /* Compute some predicates to simplify code below.  */
9883
9884       equality_comparison_p = (code == EQ || code == NE);
9885       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9886       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9887                                || code == GEU);
9888
9889       /* If this is a sign bit comparison and we can do arithmetic in
9890          MODE, say that we will only be needing the sign bit of OP0.  */
9891       if (sign_bit_comparison_p
9892           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9893         op0 = force_to_mode (op0, mode,
9894                              ((HOST_WIDE_INT) 1
9895                               << (GET_MODE_BITSIZE (mode) - 1)),
9896                              0);
9897
9898       /* Now try cases based on the opcode of OP0.  If none of the cases
9899          does a "continue", we exit this loop immediately after the
9900          switch.  */
9901
9902       switch (GET_CODE (op0))
9903         {
9904         case ZERO_EXTRACT:
9905           /* If we are extracting a single bit from a variable position in
9906              a constant that has only a single bit set and are comparing it
9907              with zero, we can convert this into an equality comparison
9908              between the position and the location of the single bit.  */
9909           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9910              have already reduced the shift count modulo the word size.  */
9911           if (!SHIFT_COUNT_TRUNCATED
9912               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9913               && XEXP (op0, 1) == const1_rtx
9914               && equality_comparison_p && const_op == 0
9915               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9916             {
9917               if (BITS_BIG_ENDIAN)
9918                 {
9919                   enum machine_mode new_mode
9920                     = mode_for_extraction (EP_extzv, 1);
9921                   if (new_mode == MAX_MACHINE_MODE)
9922                     i = BITS_PER_WORD - 1 - i;
9923                   else
9924                     {
9925                       mode = new_mode;
9926                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9927                     }
9928                 }
9929
9930               op0 = XEXP (op0, 2);
9931               op1 = GEN_INT (i);
9932               const_op = i;
9933
9934               /* Result is nonzero iff shift count is equal to I.  */
9935               code = reverse_condition (code);
9936               continue;
9937             }
9938
9939           /* ... fall through ...  */
9940
9941         case SIGN_EXTRACT:
9942           tem = expand_compound_operation (op0);
9943           if (tem != op0)
9944             {
9945               op0 = tem;
9946               continue;
9947             }
9948           break;
9949
9950         case NOT:
9951           /* If testing for equality, we can take the NOT of the constant.  */
9952           if (equality_comparison_p
9953               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9954             {
9955               op0 = XEXP (op0, 0);
9956               op1 = tem;
9957               continue;
9958             }
9959
9960           /* If just looking at the sign bit, reverse the sense of the
9961              comparison.  */
9962           if (sign_bit_comparison_p)
9963             {
9964               op0 = XEXP (op0, 0);
9965               code = (code == GE ? LT : GE);
9966               continue;
9967             }
9968           break;
9969
9970         case NEG:
9971           /* If testing for equality, we can take the NEG of the constant.  */
9972           if (equality_comparison_p
9973               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9974             {
9975               op0 = XEXP (op0, 0);
9976               op1 = tem;
9977               continue;
9978             }
9979
9980           /* The remaining cases only apply to comparisons with zero.  */
9981           if (const_op != 0)
9982             break;
9983
9984           /* When X is ABS or is known positive,
9985              (neg X) is < 0 if and only if X != 0.  */
9986
9987           if (sign_bit_comparison_p
9988               && (GET_CODE (XEXP (op0, 0)) == ABS
9989                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9990                       && (nonzero_bits (XEXP (op0, 0), mode)
9991                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9992             {
9993               op0 = XEXP (op0, 0);
9994               code = (code == LT ? NE : EQ);
9995               continue;
9996             }
9997
9998           /* If we have NEG of something whose two high-order bits are the
9999              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
10000           if (num_sign_bit_copies (op0, mode) >= 2)
10001             {
10002               op0 = XEXP (op0, 0);
10003               code = swap_condition (code);
10004               continue;
10005             }
10006           break;
10007
10008         case ROTATE:
10009           /* If we are testing equality and our count is a constant, we
10010              can perform the inverse operation on our RHS.  */
10011           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10012               && (tem = simplify_binary_operation (ROTATERT, mode,
10013                                                    op1, XEXP (op0, 1))) != 0)
10014             {
10015               op0 = XEXP (op0, 0);
10016               op1 = tem;
10017               continue;
10018             }
10019
10020           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10021              a particular bit.  Convert it to an AND of a constant of that
10022              bit.  This will be converted into a ZERO_EXTRACT.  */
10023           if (const_op == 0 && sign_bit_comparison_p
10024               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10025               && mode_width <= HOST_BITS_PER_WIDE_INT)
10026             {
10027               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10028                                             ((HOST_WIDE_INT) 1
10029                                              << (mode_width - 1
10030                                                  - INTVAL (XEXP (op0, 1)))));
10031               code = (code == LT ? NE : EQ);
10032               continue;
10033             }
10034
10035           /* Fall through.  */
10036
10037         case ABS:
10038           /* ABS is ignorable inside an equality comparison with zero.  */
10039           if (const_op == 0 && equality_comparison_p)
10040             {
10041               op0 = XEXP (op0, 0);
10042               continue;
10043             }
10044           break;
10045
10046         case SIGN_EXTEND:
10047           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10048              (compare FOO CONST) if CONST fits in FOO's mode and we
10049              are either testing inequality or have an unsigned
10050              comparison with ZERO_EXTEND or a signed comparison with
10051              SIGN_EXTEND.  But don't do it if we don't have a compare
10052              insn of the given mode, since we'd have to revert it
10053              later on, and then we wouldn't know whether to sign- or
10054              zero-extend.  */
10055           mode = GET_MODE (XEXP (op0, 0));
10056           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10057               && ! unsigned_comparison_p
10058               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10059               && ((unsigned HOST_WIDE_INT) const_op
10060                   < (((unsigned HOST_WIDE_INT) 1
10061                       << (GET_MODE_BITSIZE (mode) - 1))))
10062               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10063             {
10064               op0 = XEXP (op0, 0);
10065               continue;
10066             }
10067           break;
10068
10069         case SUBREG:
10070           /* Check for the case where we are comparing A - C1 with C2, that is
10071
10072                (subreg:MODE (plus (A) (-C1))) op (C2)
10073
10074              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10075              comparison in the wider mode.  One of the following two conditions
10076              must be true in order for this to be valid:
10077
10078                1. The mode extension results in the same bit pattern being added
10079                   on both sides and the comparison is equality or unsigned.  As
10080                   C2 has been truncated to fit in MODE, the pattern can only be
10081                   all 0s or all 1s.
10082
10083                2. The mode extension results in the sign bit being copied on
10084                   each side.
10085
10086              The difficulty here is that we have predicates for A but not for
10087              (A - C1) so we need to check that C1 is within proper bounds so
10088              as to perturbate A as little as possible.  */
10089
10090           if (mode_width <= HOST_BITS_PER_WIDE_INT
10091               && subreg_lowpart_p (op0)
10092               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10093               && GET_CODE (SUBREG_REG (op0)) == PLUS
10094               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10095             {
10096               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10097               rtx a = XEXP (SUBREG_REG (op0), 0);
10098               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10099
10100               if ((c1 > 0
10101                    && (unsigned HOST_WIDE_INT) c1
10102                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10103                    && (equality_comparison_p || unsigned_comparison_p)
10104                    /* (A - C1) zero-extends if it is positive and sign-extends
10105                       if it is negative, C2 both zero- and sign-extends.  */
10106                    && ((0 == (nonzero_bits (a, inner_mode)
10107                               & ~GET_MODE_MASK (mode))
10108                         && const_op >= 0)
10109                        /* (A - C1) sign-extends if it is positive and 1-extends
10110                           if it is negative, C2 both sign- and 1-extends.  */
10111                        || (num_sign_bit_copies (a, inner_mode)
10112                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10113                                              - mode_width)
10114                            && const_op < 0)))
10115                   || ((unsigned HOST_WIDE_INT) c1
10116                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10117                       /* (A - C1) always sign-extends, like C2.  */
10118                       && num_sign_bit_copies (a, inner_mode)
10119                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10120                                            - (mode_width - 1))))
10121                 {
10122                   op0 = SUBREG_REG (op0);
10123                   continue;
10124                 }
10125             }
10126
10127           /* If the inner mode is narrower and we are extracting the low part,
10128              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10129           if (subreg_lowpart_p (op0)
10130               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10131             /* Fall through */ ;
10132           else
10133             break;
10134
10135           /* ... fall through ...  */
10136
10137         case ZERO_EXTEND:
10138           mode = GET_MODE (XEXP (op0, 0));
10139           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10140               && (unsigned_comparison_p || equality_comparison_p)
10141               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10142               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10143               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10144             {
10145               op0 = XEXP (op0, 0);
10146               continue;
10147             }
10148           break;
10149
10150         case PLUS:
10151           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10152              this for equality comparisons due to pathological cases involving
10153              overflows.  */
10154           if (equality_comparison_p
10155               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10156                                                         op1, XEXP (op0, 1))))
10157             {
10158               op0 = XEXP (op0, 0);
10159               op1 = tem;
10160               continue;
10161             }
10162
10163           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10164           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10165               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10166             {
10167               op0 = XEXP (XEXP (op0, 0), 0);
10168               code = (code == LT ? EQ : NE);
10169               continue;
10170             }
10171           break;
10172
10173         case MINUS:
10174           /* We used to optimize signed comparisons against zero, but that
10175              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10176              arrive here as equality comparisons, or (GEU, LTU) are
10177              optimized away.  No need to special-case them.  */
10178
10179           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10180              (eq B (minus A C)), whichever simplifies.  We can only do
10181              this for equality comparisons due to pathological cases involving
10182              overflows.  */
10183           if (equality_comparison_p
10184               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10185                                                         XEXP (op0, 1), op1)))
10186             {
10187               op0 = XEXP (op0, 0);
10188               op1 = tem;
10189               continue;
10190             }
10191
10192           if (equality_comparison_p
10193               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10194                                                         XEXP (op0, 0), op1)))
10195             {
10196               op0 = XEXP (op0, 1);
10197               op1 = tem;
10198               continue;
10199             }
10200
10201           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10202              of bits in X minus 1, is one iff X > 0.  */
10203           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10204               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10205               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10206                  == mode_width - 1
10207               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10208             {
10209               op0 = XEXP (op0, 1);
10210               code = (code == GE ? LE : GT);
10211               continue;
10212             }
10213           break;
10214
10215         case XOR:
10216           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10217              if C is zero or B is a constant.  */
10218           if (equality_comparison_p
10219               && 0 != (tem = simplify_binary_operation (XOR, mode,
10220                                                         XEXP (op0, 1), op1)))
10221             {
10222               op0 = XEXP (op0, 0);
10223               op1 = tem;
10224               continue;
10225             }
10226           break;
10227
10228         case EQ:  case NE:
10229         case UNEQ:  case LTGT:
10230         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10231         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10232         case UNORDERED: case ORDERED:
10233           /* We can't do anything if OP0 is a condition code value, rather
10234              than an actual data value.  */
10235           if (const_op != 0
10236               || CC0_P (XEXP (op0, 0))
10237               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10238             break;
10239
10240           /* Get the two operands being compared.  */
10241           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10242             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10243           else
10244             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10245
10246           /* Check for the cases where we simply want the result of the
10247              earlier test or the opposite of that result.  */
10248           if (code == NE || code == EQ
10249               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10250                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10251                   && (STORE_FLAG_VALUE
10252                       & (((HOST_WIDE_INT) 1
10253                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10254                   && (code == LT || code == GE)))
10255             {
10256               enum rtx_code new_code;
10257               if (code == LT || code == NE)
10258                 new_code = GET_CODE (op0);
10259               else
10260                 new_code = reversed_comparison_code (op0, NULL);
10261
10262               if (new_code != UNKNOWN)
10263                 {
10264                   code = new_code;
10265                   op0 = tem;
10266                   op1 = tem1;
10267                   continue;
10268                 }
10269             }
10270           break;
10271
10272         case IOR:
10273           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10274              iff X <= 0.  */
10275           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10276               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10277               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10278             {
10279               op0 = XEXP (op0, 1);
10280               code = (code == GE ? GT : LE);
10281               continue;
10282             }
10283           break;
10284
10285         case AND:
10286           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10287              will be converted to a ZERO_EXTRACT later.  */
10288           if (const_op == 0 && equality_comparison_p
10289               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10290               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10291             {
10292               op0 = simplify_and_const_int
10293                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10294                                                    XEXP (op0, 1),
10295                                                    XEXP (XEXP (op0, 0), 1)),
10296                  (HOST_WIDE_INT) 1);
10297               continue;
10298             }
10299
10300           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10301              zero and X is a comparison and C1 and C2 describe only bits set
10302              in STORE_FLAG_VALUE, we can compare with X.  */
10303           if (const_op == 0 && equality_comparison_p
10304               && mode_width <= HOST_BITS_PER_WIDE_INT
10305               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10306               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10307               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10308               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10309               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10310             {
10311               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10312                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10313               if ((~STORE_FLAG_VALUE & mask) == 0
10314                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10315                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10316                           && COMPARISON_P (tem))))
10317                 {
10318                   op0 = XEXP (XEXP (op0, 0), 0);
10319                   continue;
10320                 }
10321             }
10322
10323           /* If we are doing an equality comparison of an AND of a bit equal
10324              to the sign bit, replace this with a LT or GE comparison of
10325              the underlying value.  */
10326           if (equality_comparison_p
10327               && const_op == 0
10328               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10329               && mode_width <= HOST_BITS_PER_WIDE_INT
10330               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10331                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10332             {
10333               op0 = XEXP (op0, 0);
10334               code = (code == EQ ? GE : LT);
10335               continue;
10336             }
10337
10338           /* If this AND operation is really a ZERO_EXTEND from a narrower
10339              mode, the constant fits within that mode, and this is either an
10340              equality or unsigned comparison, try to do this comparison in
10341              the narrower mode.
10342
10343              Note that in:
10344
10345              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10346              -> (ne:DI (reg:SI 4) (const_int 0))
10347
10348              unless TRULY_NOOP_TRUNCATION allows it or the register is
10349              known to hold a value of the required mode the
10350              transformation is invalid.  */
10351           if ((equality_comparison_p || unsigned_comparison_p)
10352               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10353               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10354                                    & GET_MODE_MASK (mode))
10355                                   + 1)) >= 0
10356               && const_op >> i == 0
10357               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10358               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10359                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10360                   || (REG_P (XEXP (op0, 0))
10361                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10362             {
10363               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10364               continue;
10365             }
10366
10367           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10368              fits in both M1 and M2 and the SUBREG is either paradoxical
10369              or represents the low part, permute the SUBREG and the AND
10370              and try again.  */
10371           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10372             {
10373               unsigned HOST_WIDE_INT c1;
10374               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10375               /* Require an integral mode, to avoid creating something like
10376                  (AND:SF ...).  */
10377               if (SCALAR_INT_MODE_P (tmode)
10378                   /* It is unsafe to commute the AND into the SUBREG if the
10379                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10380                      not defined.  As originally written the upper bits
10381                      have a defined value due to the AND operation.
10382                      However, if we commute the AND inside the SUBREG then
10383                      they no longer have defined values and the meaning of
10384                      the code has been changed.  */
10385                   && (0
10386 #ifdef WORD_REGISTER_OPERATIONS
10387                       || (mode_width > GET_MODE_BITSIZE (tmode)
10388                           && mode_width <= BITS_PER_WORD)
10389 #endif
10390                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10391                           && subreg_lowpart_p (XEXP (op0, 0))))
10392                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10393                   && mode_width <= HOST_BITS_PER_WIDE_INT
10394                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10395                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10396                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10397                   && c1 != mask
10398                   && c1 != GET_MODE_MASK (tmode))
10399                 {
10400                   op0 = simplify_gen_binary (AND, tmode,
10401                                              SUBREG_REG (XEXP (op0, 0)),
10402                                              gen_int_mode (c1, tmode));
10403                   op0 = gen_lowpart (mode, op0);
10404                   continue;
10405                 }
10406             }
10407
10408           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10409           if (const_op == 0 && equality_comparison_p
10410               && XEXP (op0, 1) == const1_rtx
10411               && GET_CODE (XEXP (op0, 0)) == NOT)
10412             {
10413               op0 = simplify_and_const_int
10414                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10415               code = (code == NE ? EQ : NE);
10416               continue;
10417             }
10418
10419           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10420              (eq (and (lshiftrt X) 1) 0).
10421              Also handle the case where (not X) is expressed using xor.  */
10422           if (const_op == 0 && equality_comparison_p
10423               && XEXP (op0, 1) == const1_rtx
10424               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10425             {
10426               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10427               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10428
10429               if (GET_CODE (shift_op) == NOT
10430                   || (GET_CODE (shift_op) == XOR
10431                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10432                       && GET_CODE (shift_count) == CONST_INT
10433                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10434                       && (INTVAL (XEXP (shift_op, 1))
10435                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10436                 {
10437                   op0 = simplify_and_const_int
10438                     (NULL_RTX, mode,
10439                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10440                      (HOST_WIDE_INT) 1);
10441                   code = (code == NE ? EQ : NE);
10442                   continue;
10443                 }
10444             }
10445           break;
10446
10447         case ASHIFT:
10448           /* If we have (compare (ashift FOO N) (const_int C)) and
10449              the high order N bits of FOO (N+1 if an inequality comparison)
10450              are known to be zero, we can do this by comparing FOO with C
10451              shifted right N bits so long as the low-order N bits of C are
10452              zero.  */
10453           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10454               && INTVAL (XEXP (op0, 1)) >= 0
10455               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10456                   < HOST_BITS_PER_WIDE_INT)
10457               && ((const_op
10458                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10459               && mode_width <= HOST_BITS_PER_WIDE_INT
10460               && (nonzero_bits (XEXP (op0, 0), mode)
10461                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10462                                + ! equality_comparison_p))) == 0)
10463             {
10464               /* We must perform a logical shift, not an arithmetic one,
10465                  as we want the top N bits of C to be zero.  */
10466               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10467
10468               temp >>= INTVAL (XEXP (op0, 1));
10469               op1 = gen_int_mode (temp, mode);
10470               op0 = XEXP (op0, 0);
10471               continue;
10472             }
10473
10474           /* If we are doing a sign bit comparison, it means we are testing
10475              a particular bit.  Convert it to the appropriate AND.  */
10476           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10477               && mode_width <= HOST_BITS_PER_WIDE_INT)
10478             {
10479               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10480                                             ((HOST_WIDE_INT) 1
10481                                              << (mode_width - 1
10482                                                  - INTVAL (XEXP (op0, 1)))));
10483               code = (code == LT ? NE : EQ);
10484               continue;
10485             }
10486
10487           /* If this an equality comparison with zero and we are shifting
10488              the low bit to the sign bit, we can convert this to an AND of the
10489              low-order bit.  */
10490           if (const_op == 0 && equality_comparison_p
10491               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10492               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10493                  == mode_width - 1)
10494             {
10495               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10496                                             (HOST_WIDE_INT) 1);
10497               continue;
10498             }
10499           break;
10500
10501         case ASHIFTRT:
10502           /* If this is an equality comparison with zero, we can do this
10503              as a logical shift, which might be much simpler.  */
10504           if (equality_comparison_p && const_op == 0
10505               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10506             {
10507               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10508                                           XEXP (op0, 0),
10509                                           INTVAL (XEXP (op0, 1)));
10510               continue;
10511             }
10512
10513           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10514              do the comparison in a narrower mode.  */
10515           if (! unsigned_comparison_p
10516               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10517               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10518               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10519               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10520                                          MODE_INT, 1)) != BLKmode
10521               && (((unsigned HOST_WIDE_INT) const_op
10522                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10523                   <= GET_MODE_MASK (tmode)))
10524             {
10525               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10526               continue;
10527             }
10528
10529           /* Likewise if OP0 is a PLUS of a sign extension with a
10530              constant, which is usually represented with the PLUS
10531              between the shifts.  */
10532           if (! unsigned_comparison_p
10533               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10534               && GET_CODE (XEXP (op0, 0)) == PLUS
10535               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10536               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10537               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10538               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10539                                          MODE_INT, 1)) != BLKmode
10540               && (((unsigned HOST_WIDE_INT) const_op
10541                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10542                   <= GET_MODE_MASK (tmode)))
10543             {
10544               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10545               rtx add_const = XEXP (XEXP (op0, 0), 1);
10546               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10547                                                    add_const, XEXP (op0, 1));
10548
10549               op0 = simplify_gen_binary (PLUS, tmode,
10550                                          gen_lowpart (tmode, inner),
10551                                          new_const);
10552               continue;
10553             }
10554
10555           /* ... fall through ...  */
10556         case LSHIFTRT:
10557           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10558              the low order N bits of FOO are known to be zero, we can do this
10559              by comparing FOO with C shifted left N bits so long as no
10560              overflow occurs.  */
10561           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10562               && INTVAL (XEXP (op0, 1)) >= 0
10563               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10564               && mode_width <= HOST_BITS_PER_WIDE_INT
10565               && (nonzero_bits (XEXP (op0, 0), mode)
10566                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10567               && (((unsigned HOST_WIDE_INT) const_op
10568                    + (GET_CODE (op0) != LSHIFTRT
10569                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10570                          + 1)
10571                       : 0))
10572                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10573             {
10574               /* If the shift was logical, then we must make the condition
10575                  unsigned.  */
10576               if (GET_CODE (op0) == LSHIFTRT)
10577                 code = unsigned_condition (code);
10578
10579               const_op <<= INTVAL (XEXP (op0, 1));
10580               op1 = GEN_INT (const_op);
10581               op0 = XEXP (op0, 0);
10582               continue;
10583             }
10584
10585           /* If we are using this shift to extract just the sign bit, we
10586              can replace this with an LT or GE comparison.  */
10587           if (const_op == 0
10588               && (equality_comparison_p || sign_bit_comparison_p)
10589               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10590               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10591                  == mode_width - 1)
10592             {
10593               op0 = XEXP (op0, 0);
10594               code = (code == NE || code == GT ? LT : GE);
10595               continue;
10596             }
10597           break;
10598
10599         default:
10600           break;
10601         }
10602
10603       break;
10604     }
10605
10606   /* Now make any compound operations involved in this comparison.  Then,
10607      check for an outmost SUBREG on OP0 that is not doing anything or is
10608      paradoxical.  The latter transformation must only be performed when
10609      it is known that the "extra" bits will be the same in op0 and op1 or
10610      that they don't matter.  There are three cases to consider:
10611
10612      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10613      care bits and we can assume they have any convenient value.  So
10614      making the transformation is safe.
10615
10616      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10617      In this case the upper bits of op0 are undefined.  We should not make
10618      the simplification in that case as we do not know the contents of
10619      those bits.
10620
10621      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10622      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10623      also be sure that they are the same as the upper bits of op1.
10624
10625      We can never remove a SUBREG for a non-equality comparison because
10626      the sign bit is in a different place in the underlying object.  */
10627
10628   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10629   op1 = make_compound_operation (op1, SET);
10630
10631   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10632       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10633       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10634       && (code == NE || code == EQ))
10635     {
10636       if (GET_MODE_SIZE (GET_MODE (op0))
10637           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10638         {
10639           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10640              implemented.  */
10641           if (REG_P (SUBREG_REG (op0)))
10642             {
10643               op0 = SUBREG_REG (op0);
10644               op1 = gen_lowpart (GET_MODE (op0), op1);
10645             }
10646         }
10647       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10648                 <= HOST_BITS_PER_WIDE_INT)
10649                && (nonzero_bits (SUBREG_REG (op0),
10650                                  GET_MODE (SUBREG_REG (op0)))
10651                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10652         {
10653           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10654
10655           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10656                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10657             op0 = SUBREG_REG (op0), op1 = tem;
10658         }
10659     }
10660
10661   /* We now do the opposite procedure: Some machines don't have compare
10662      insns in all modes.  If OP0's mode is an integer mode smaller than a
10663      word and we can't do a compare in that mode, see if there is a larger
10664      mode for which we can do the compare.  There are a number of cases in
10665      which we can use the wider mode.  */
10666
10667   mode = GET_MODE (op0);
10668   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10669       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10670       && ! have_insn_for (COMPARE, mode))
10671     for (tmode = GET_MODE_WIDER_MODE (mode);
10672          (tmode != VOIDmode
10673           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10674          tmode = GET_MODE_WIDER_MODE (tmode))
10675       if (have_insn_for (COMPARE, tmode))
10676         {
10677           int zero_extended;
10678
10679           /* If the only nonzero bits in OP0 and OP1 are those in the
10680              narrower mode and this is an equality or unsigned comparison,
10681              we can use the wider mode.  Similarly for sign-extended
10682              values, in which case it is true for all comparisons.  */
10683           zero_extended = ((code == EQ || code == NE
10684                             || code == GEU || code == GTU
10685                             || code == LEU || code == LTU)
10686                            && (nonzero_bits (op0, tmode)
10687                                & ~GET_MODE_MASK (mode)) == 0
10688                            && ((GET_CODE (op1) == CONST_INT
10689                                 || (nonzero_bits (op1, tmode)
10690                                     & ~GET_MODE_MASK (mode)) == 0)));
10691
10692           if (zero_extended
10693               || ((num_sign_bit_copies (op0, tmode)
10694                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10695                                      - GET_MODE_BITSIZE (mode)))
10696                   && (num_sign_bit_copies (op1, tmode)
10697                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10698                                         - GET_MODE_BITSIZE (mode)))))
10699             {
10700               /* If OP0 is an AND and we don't have an AND in MODE either,
10701                  make a new AND in the proper mode.  */
10702               if (GET_CODE (op0) == AND
10703                   && !have_insn_for (AND, mode))
10704                 op0 = simplify_gen_binary (AND, tmode,
10705                                            gen_lowpart (tmode,
10706                                                         XEXP (op0, 0)),
10707                                            gen_lowpart (tmode,
10708                                                         XEXP (op0, 1)));
10709
10710               op0 = gen_lowpart (tmode, op0);
10711               if (zero_extended && GET_CODE (op1) == CONST_INT)
10712                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10713               op1 = gen_lowpart (tmode, op1);
10714               break;
10715             }
10716
10717           /* If this is a test for negative, we can make an explicit
10718              test of the sign bit.  */
10719
10720           if (op1 == const0_rtx && (code == LT || code == GE)
10721               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10722             {
10723               op0 = simplify_gen_binary (AND, tmode,
10724                                          gen_lowpart (tmode, op0),
10725                                          GEN_INT ((HOST_WIDE_INT) 1
10726                                                   << (GET_MODE_BITSIZE (mode)
10727                                                       - 1)));
10728               code = (code == LT) ? NE : EQ;
10729               break;
10730             }
10731         }
10732
10733 #ifdef CANONICALIZE_COMPARISON
10734   /* If this machine only supports a subset of valid comparisons, see if we
10735      can convert an unsupported one into a supported one.  */
10736   CANONICALIZE_COMPARISON (code, op0, op1);
10737 #endif
10738
10739   *pop0 = op0;
10740   *pop1 = op1;
10741
10742   return code;
10743 }
10744 \f
10745 /* Utility function for record_value_for_reg.  Count number of
10746    rtxs in X.  */
10747 static int
10748 count_rtxs (rtx x)
10749 {
10750   enum rtx_code code = GET_CODE (x);
10751   const char *fmt;
10752   int i, ret = 1;
10753
10754   if (GET_RTX_CLASS (code) == '2'
10755       || GET_RTX_CLASS (code) == 'c')
10756     {
10757       rtx x0 = XEXP (x, 0);
10758       rtx x1 = XEXP (x, 1);
10759
10760       if (x0 == x1)
10761         return 1 + 2 * count_rtxs (x0);
10762
10763       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10764            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10765           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10766         return 2 + 2 * count_rtxs (x0)
10767                + count_rtxs (x == XEXP (x1, 0)
10768                              ? XEXP (x1, 1) : XEXP (x1, 0));
10769
10770       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10771            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10772           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10773         return 2 + 2 * count_rtxs (x1)
10774                + count_rtxs (x == XEXP (x0, 0)
10775                              ? XEXP (x0, 1) : XEXP (x0, 0));
10776     }
10777
10778   fmt = GET_RTX_FORMAT (code);
10779   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10780     if (fmt[i] == 'e')
10781       ret += count_rtxs (XEXP (x, i));
10782
10783   return ret;
10784 }
10785 \f
10786 /* Utility function for following routine.  Called when X is part of a value
10787    being stored into last_set_value.  Sets last_set_table_tick
10788    for each register mentioned.  Similar to mention_regs in cse.c  */
10789
10790 static void
10791 update_table_tick (rtx x)
10792 {
10793   enum rtx_code code = GET_CODE (x);
10794   const char *fmt = GET_RTX_FORMAT (code);
10795   int i;
10796
10797   if (code == REG)
10798     {
10799       unsigned int regno = REGNO (x);
10800       unsigned int endregno
10801         = regno + (regno < FIRST_PSEUDO_REGISTER
10802                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10803       unsigned int r;
10804
10805       for (r = regno; r < endregno; r++)
10806         reg_stat[r].last_set_table_tick = label_tick;
10807
10808       return;
10809     }
10810
10811   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10812     /* Note that we can't have an "E" in values stored; see
10813        get_last_value_validate.  */
10814     if (fmt[i] == 'e')
10815       {
10816         /* Check for identical subexpressions.  If x contains
10817            identical subexpression we only have to traverse one of
10818            them.  */
10819         if (i == 0 && ARITHMETIC_P (x))
10820           {
10821             /* Note that at this point x1 has already been
10822                processed.  */
10823             rtx x0 = XEXP (x, 0);
10824             rtx x1 = XEXP (x, 1);
10825
10826             /* If x0 and x1 are identical then there is no need to
10827                process x0.  */
10828             if (x0 == x1)
10829               break;
10830
10831             /* If x0 is identical to a subexpression of x1 then while
10832                processing x1, x0 has already been processed.  Thus we
10833                are done with x.  */
10834             if (ARITHMETIC_P (x1)
10835                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10836               break;
10837
10838             /* If x1 is identical to a subexpression of x0 then we
10839                still have to process the rest of x0.  */
10840             if (ARITHMETIC_P (x0)
10841                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10842               {
10843                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10844                 break;
10845               }
10846           }
10847
10848         update_table_tick (XEXP (x, i));
10849       }
10850 }
10851
10852 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10853    are saying that the register is clobbered and we no longer know its
10854    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10855    only permitted with VALUE also zero and is used to invalidate the
10856    register.  */
10857
10858 static void
10859 record_value_for_reg (rtx reg, rtx insn, rtx value)
10860 {
10861   unsigned int regno = REGNO (reg);
10862   unsigned int endregno
10863     = regno + (regno < FIRST_PSEUDO_REGISTER
10864                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10865   unsigned int i;
10866
10867   /* If VALUE contains REG and we have a previous value for REG, substitute
10868      the previous value.  */
10869   if (value && insn && reg_overlap_mentioned_p (reg, value))
10870     {
10871       rtx tem;
10872
10873       /* Set things up so get_last_value is allowed to see anything set up to
10874          our insn.  */
10875       subst_low_cuid = INSN_CUID (insn);
10876       tem = get_last_value (reg);
10877
10878       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10879          it isn't going to be useful and will take a lot of time to process,
10880          so just use the CLOBBER.  */
10881
10882       if (tem)
10883         {
10884           if (ARITHMETIC_P (tem)
10885               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10886               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10887             tem = XEXP (tem, 0);
10888           else if (count_occurrences (value, reg, 1) >= 2)
10889             {
10890               /* If there are two or more occurrences of REG in VALUE,
10891                  prevent the value from growing too much.  */
10892               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10893                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10894             }
10895
10896           value = replace_rtx (copy_rtx (value), reg, tem);
10897         }
10898     }
10899
10900   /* For each register modified, show we don't know its value, that
10901      we don't know about its bitwise content, that its value has been
10902      updated, and that we don't know the location of the death of the
10903      register.  */
10904   for (i = regno; i < endregno; i++)
10905     {
10906       if (insn)
10907         reg_stat[i].last_set = insn;
10908
10909       reg_stat[i].last_set_value = 0;
10910       reg_stat[i].last_set_mode = 0;
10911       reg_stat[i].last_set_nonzero_bits = 0;
10912       reg_stat[i].last_set_sign_bit_copies = 0;
10913       reg_stat[i].last_death = 0;
10914       reg_stat[i].truncated_to_mode = 0;
10915     }
10916
10917   /* Mark registers that are being referenced in this value.  */
10918   if (value)
10919     update_table_tick (value);
10920
10921   /* Now update the status of each register being set.
10922      If someone is using this register in this block, set this register
10923      to invalid since we will get confused between the two lives in this
10924      basic block.  This makes using this register always invalid.  In cse, we
10925      scan the table to invalidate all entries using this register, but this
10926      is too much work for us.  */
10927
10928   for (i = regno; i < endregno; i++)
10929     {
10930       reg_stat[i].last_set_label = label_tick;
10931       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10932         reg_stat[i].last_set_invalid = 1;
10933       else
10934         reg_stat[i].last_set_invalid = 0;
10935     }
10936
10937   /* The value being assigned might refer to X (like in "x++;").  In that
10938      case, we must replace it with (clobber (const_int 0)) to prevent
10939      infinite loops.  */
10940   if (value && ! get_last_value_validate (&value, insn,
10941                                           reg_stat[regno].last_set_label, 0))
10942     {
10943       value = copy_rtx (value);
10944       if (! get_last_value_validate (&value, insn,
10945                                      reg_stat[regno].last_set_label, 1))
10946         value = 0;
10947     }
10948
10949   /* For the main register being modified, update the value, the mode, the
10950      nonzero bits, and the number of sign bit copies.  */
10951
10952   reg_stat[regno].last_set_value = value;
10953
10954   if (value)
10955     {
10956       enum machine_mode mode = GET_MODE (reg);
10957       subst_low_cuid = INSN_CUID (insn);
10958       reg_stat[regno].last_set_mode = mode;
10959       if (GET_MODE_CLASS (mode) == MODE_INT
10960           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10961         mode = nonzero_bits_mode;
10962       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10963       reg_stat[regno].last_set_sign_bit_copies
10964         = num_sign_bit_copies (value, GET_MODE (reg));
10965     }
10966 }
10967
10968 /* Called via note_stores from record_dead_and_set_regs to handle one
10969    SET or CLOBBER in an insn.  DATA is the instruction in which the
10970    set is occurring.  */
10971
10972 static void
10973 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10974 {
10975   rtx record_dead_insn = (rtx) data;
10976
10977   if (GET_CODE (dest) == SUBREG)
10978     dest = SUBREG_REG (dest);
10979
10980   if (!record_dead_insn)
10981     {
10982       if (REG_P (dest))
10983         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10984       return;
10985     }
10986
10987   if (REG_P (dest))
10988     {
10989       /* If we are setting the whole register, we know its value.  Otherwise
10990          show that we don't know the value.  We can handle SUBREG in
10991          some cases.  */
10992       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10993         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10994       else if (GET_CODE (setter) == SET
10995                && GET_CODE (SET_DEST (setter)) == SUBREG
10996                && SUBREG_REG (SET_DEST (setter)) == dest
10997                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10998                && subreg_lowpart_p (SET_DEST (setter)))
10999         record_value_for_reg (dest, record_dead_insn,
11000                               gen_lowpart (GET_MODE (dest),
11001                                                        SET_SRC (setter)));
11002       else
11003         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11004     }
11005   else if (MEM_P (dest)
11006            /* Ignore pushes, they clobber nothing.  */
11007            && ! push_operand (dest, GET_MODE (dest)))
11008     mem_last_set = INSN_CUID (record_dead_insn);
11009 }
11010
11011 /* Update the records of when each REG was most recently set or killed
11012    for the things done by INSN.  This is the last thing done in processing
11013    INSN in the combiner loop.
11014
11015    We update reg_stat[], in particular fields last_set, last_set_value,
11016    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11017    last_death, and also the similar information mem_last_set (which insn
11018    most recently modified memory) and last_call_cuid (which insn was the
11019    most recent subroutine call).  */
11020
11021 static void
11022 record_dead_and_set_regs (rtx insn)
11023 {
11024   rtx link;
11025   unsigned int i;
11026
11027   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11028     {
11029       if (REG_NOTE_KIND (link) == REG_DEAD
11030           && REG_P (XEXP (link, 0)))
11031         {
11032           unsigned int regno = REGNO (XEXP (link, 0));
11033           unsigned int endregno
11034             = regno + (regno < FIRST_PSEUDO_REGISTER
11035                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11036                        : 1);
11037
11038           for (i = regno; i < endregno; i++)
11039             reg_stat[i].last_death = insn;
11040         }
11041       else if (REG_NOTE_KIND (link) == REG_INC)
11042         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11043     }
11044
11045   if (CALL_P (insn))
11046     {
11047       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11048         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11049           {
11050             reg_stat[i].last_set_value = 0;
11051             reg_stat[i].last_set_mode = 0;
11052             reg_stat[i].last_set_nonzero_bits = 0;
11053             reg_stat[i].last_set_sign_bit_copies = 0;
11054             reg_stat[i].last_death = 0;
11055             reg_stat[i].truncated_to_mode = 0;
11056           }
11057
11058       last_call_cuid = mem_last_set = INSN_CUID (insn);
11059
11060       /* We can't combine into a call pattern.  Remember, though, that
11061          the return value register is set at this CUID.  We could
11062          still replace a register with the return value from the
11063          wrong subroutine call!  */
11064       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11065     }
11066   else
11067     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11068 }
11069
11070 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11071    register present in the SUBREG, so for each such SUBREG go back and
11072    adjust nonzero and sign bit information of the registers that are
11073    known to have some zero/sign bits set.
11074
11075    This is needed because when combine blows the SUBREGs away, the
11076    information on zero/sign bits is lost and further combines can be
11077    missed because of that.  */
11078
11079 static void
11080 record_promoted_value (rtx insn, rtx subreg)
11081 {
11082   rtx links, set;
11083   unsigned int regno = REGNO (SUBREG_REG (subreg));
11084   enum machine_mode mode = GET_MODE (subreg);
11085
11086   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11087     return;
11088
11089   for (links = LOG_LINKS (insn); links;)
11090     {
11091       insn = XEXP (links, 0);
11092       set = single_set (insn);
11093
11094       if (! set || !REG_P (SET_DEST (set))
11095           || REGNO (SET_DEST (set)) != regno
11096           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11097         {
11098           links = XEXP (links, 1);
11099           continue;
11100         }
11101
11102       if (reg_stat[regno].last_set == insn)
11103         {
11104           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11105             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11106         }
11107
11108       if (REG_P (SET_SRC (set)))
11109         {
11110           regno = REGNO (SET_SRC (set));
11111           links = LOG_LINKS (insn);
11112         }
11113       else
11114         break;
11115     }
11116 }
11117
11118 /* Check if X, a register, is known to contain a value already
11119    truncated to MODE.  In this case we can use a subreg to refer to
11120    the truncated value even though in the generic case we would need
11121    an explicit truncation.  */
11122
11123 static bool
11124 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11125 {
11126   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11127
11128   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11129     return false;
11130   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11131     return true;
11132   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11133                              GET_MODE_BITSIZE (truncated)))
11134     return true;
11135   return false;
11136 }
11137
11138 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11139    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11140    a truncate into a subreg using this information.  */
11141
11142 static void
11143 record_truncated_value (rtx x)
11144 {
11145   enum machine_mode truncated_mode;
11146
11147   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11148     {
11149       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11150       truncated_mode = GET_MODE (x);
11151
11152       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11153         return;
11154
11155       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11156                                  GET_MODE_BITSIZE (original_mode)))
11157         return;
11158
11159       x = SUBREG_REG (x);
11160     }
11161   /* ??? For hard-regs we now record everything.  We might be able to
11162      optimize this using last_set_mode.  */
11163   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11164     truncated_mode = GET_MODE (x);
11165   else
11166     return;
11167
11168   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11169       || reg_stat[REGNO (x)].truncation_label < label_tick
11170       || (GET_MODE_SIZE (truncated_mode)
11171           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11172     {
11173       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11174       reg_stat[REGNO (x)].truncation_label = label_tick;
11175     }
11176 }
11177
11178 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11179    found, note what it implies to the registers used in it.  */
11180
11181 static void
11182 check_conversions (rtx insn, rtx x)
11183 {
11184   if (GET_CODE (x) == SUBREG || REG_P (x))
11185     {
11186       if (GET_CODE (x) == SUBREG
11187           && SUBREG_PROMOTED_VAR_P (x)
11188           && REG_P (SUBREG_REG (x)))
11189         record_promoted_value (insn, x);
11190
11191       record_truncated_value (x);
11192     }
11193   else
11194     {
11195       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11196       int i, j;
11197
11198       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11199         switch (format[i])
11200           {
11201           case 'e':
11202             check_conversions (insn, XEXP (x, i));
11203             break;
11204           case 'V':
11205           case 'E':
11206             if (XVEC (x, i) != 0)
11207               for (j = 0; j < XVECLEN (x, i); j++)
11208                 check_conversions (insn, XVECEXP (x, i, j));
11209             break;
11210           }
11211     }
11212 }
11213 \f
11214 /* Utility routine for the following function.  Verify that all the registers
11215    mentioned in *LOC are valid when *LOC was part of a value set when
11216    label_tick == TICK.  Return 0 if some are not.
11217
11218    If REPLACE is nonzero, replace the invalid reference with
11219    (clobber (const_int 0)) and return 1.  This replacement is useful because
11220    we often can get useful information about the form of a value (e.g., if
11221    it was produced by a shift that always produces -1 or 0) even though
11222    we don't know exactly what registers it was produced from.  */
11223
11224 static int
11225 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11226 {
11227   rtx x = *loc;
11228   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11229   int len = GET_RTX_LENGTH (GET_CODE (x));
11230   int i;
11231
11232   if (REG_P (x))
11233     {
11234       unsigned int regno = REGNO (x);
11235       unsigned int endregno
11236         = regno + (regno < FIRST_PSEUDO_REGISTER
11237                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11238       unsigned int j;
11239
11240       for (j = regno; j < endregno; j++)
11241         if (reg_stat[j].last_set_invalid
11242             /* If this is a pseudo-register that was only set once and not
11243                live at the beginning of the function, it is always valid.  */
11244             || (! (regno >= FIRST_PSEUDO_REGISTER
11245                    && REG_N_SETS (regno) == 1
11246                    && (! REGNO_REG_SET_P
11247                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11248                         regno)))
11249                 && reg_stat[j].last_set_label > tick))
11250           {
11251             if (replace)
11252               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11253             return replace;
11254           }
11255
11256       return 1;
11257     }
11258   /* If this is a memory reference, make sure that there were
11259      no stores after it that might have clobbered the value.  We don't
11260      have alias info, so we assume any store invalidates it.  */
11261   else if (MEM_P (x) && !MEM_READONLY_P (x)
11262            && INSN_CUID (insn) <= mem_last_set)
11263     {
11264       if (replace)
11265         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11266       return replace;
11267     }
11268
11269   for (i = 0; i < len; i++)
11270     {
11271       if (fmt[i] == 'e')
11272         {
11273           /* Check for identical subexpressions.  If x contains
11274              identical subexpression we only have to traverse one of
11275              them.  */
11276           if (i == 1 && ARITHMETIC_P (x))
11277             {
11278               /* Note that at this point x0 has already been checked
11279                  and found valid.  */
11280               rtx x0 = XEXP (x, 0);
11281               rtx x1 = XEXP (x, 1);
11282
11283               /* If x0 and x1 are identical then x is also valid.  */
11284               if (x0 == x1)
11285                 return 1;
11286
11287               /* If x1 is identical to a subexpression of x0 then
11288                  while checking x0, x1 has already been checked.  Thus
11289                  it is valid and so as x.  */
11290               if (ARITHMETIC_P (x0)
11291                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11292                 return 1;
11293
11294               /* If x0 is identical to a subexpression of x1 then x is
11295                  valid iff the rest of x1 is valid.  */
11296               if (ARITHMETIC_P (x1)
11297                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11298                 return
11299                   get_last_value_validate (&XEXP (x1,
11300                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11301                                            insn, tick, replace);
11302             }
11303
11304           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11305                                        replace) == 0)
11306             return 0;
11307         }
11308       /* Don't bother with these.  They shouldn't occur anyway.  */
11309       else if (fmt[i] == 'E')
11310         return 0;
11311     }
11312
11313   /* If we haven't found a reason for it to be invalid, it is valid.  */
11314   return 1;
11315 }
11316
11317 /* Get the last value assigned to X, if known.  Some registers
11318    in the value may be replaced with (clobber (const_int 0)) if their value
11319    is known longer known reliably.  */
11320
11321 static rtx
11322 get_last_value (rtx x)
11323 {
11324   unsigned int regno;
11325   rtx value;
11326
11327   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11328      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11329      we cannot predict what values the "extra" bits might have.  */
11330   if (GET_CODE (x) == SUBREG
11331       && subreg_lowpart_p (x)
11332       && (GET_MODE_SIZE (GET_MODE (x))
11333           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11334       && (value = get_last_value (SUBREG_REG (x))) != 0)
11335     return gen_lowpart (GET_MODE (x), value);
11336
11337   if (!REG_P (x))
11338     return 0;
11339
11340   regno = REGNO (x);
11341   value = reg_stat[regno].last_set_value;
11342
11343   /* If we don't have a value, or if it isn't for this basic block and
11344      it's either a hard register, set more than once, or it's a live
11345      at the beginning of the function, return 0.
11346
11347      Because if it's not live at the beginning of the function then the reg
11348      is always set before being used (is never used without being set).
11349      And, if it's set only once, and it's always set before use, then all
11350      uses must have the same last value, even if it's not from this basic
11351      block.  */
11352
11353   if (value == 0
11354       || (reg_stat[regno].last_set_label != label_tick
11355           && (regno < FIRST_PSEUDO_REGISTER
11356               || REG_N_SETS (regno) != 1
11357               || (REGNO_REG_SET_P
11358                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11359                    regno)))))
11360     return 0;
11361
11362   /* If the value was set in a later insn than the ones we are processing,
11363      we can't use it even if the register was only set once.  */
11364   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11365     return 0;
11366
11367   /* If the value has all its registers valid, return it.  */
11368   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11369                                reg_stat[regno].last_set_label, 0))
11370     return value;
11371
11372   /* Otherwise, make a copy and replace any invalid register with
11373      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11374
11375   value = copy_rtx (value);
11376   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11377                                reg_stat[regno].last_set_label, 1))
11378     return value;
11379
11380   return 0;
11381 }
11382 \f
11383 /* Return nonzero if expression X refers to a REG or to memory
11384    that is set in an instruction more recent than FROM_CUID.  */
11385
11386 static int
11387 use_crosses_set_p (rtx x, int from_cuid)
11388 {
11389   const char *fmt;
11390   int i;
11391   enum rtx_code code = GET_CODE (x);
11392
11393   if (code == REG)
11394     {
11395       unsigned int regno = REGNO (x);
11396       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11397                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11398
11399 #ifdef PUSH_ROUNDING
11400       /* Don't allow uses of the stack pointer to be moved,
11401          because we don't know whether the move crosses a push insn.  */
11402       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11403         return 1;
11404 #endif
11405       for (; regno < endreg; regno++)
11406         if (reg_stat[regno].last_set
11407             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11408           return 1;
11409       return 0;
11410     }
11411
11412   if (code == MEM && mem_last_set > from_cuid)
11413     return 1;
11414
11415   fmt = GET_RTX_FORMAT (code);
11416
11417   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11418     {
11419       if (fmt[i] == 'E')
11420         {
11421           int j;
11422           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11423             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11424               return 1;
11425         }
11426       else if (fmt[i] == 'e'
11427                && use_crosses_set_p (XEXP (x, i), from_cuid))
11428         return 1;
11429     }
11430   return 0;
11431 }
11432 \f
11433 /* Define three variables used for communication between the following
11434    routines.  */
11435
11436 static unsigned int reg_dead_regno, reg_dead_endregno;
11437 static int reg_dead_flag;
11438
11439 /* Function called via note_stores from reg_dead_at_p.
11440
11441    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11442    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11443
11444 static void
11445 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11446 {
11447   unsigned int regno, endregno;
11448
11449   if (!REG_P (dest))
11450     return;
11451
11452   regno = REGNO (dest);
11453   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11454                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11455
11456   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11457     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11458 }
11459
11460 /* Return nonzero if REG is known to be dead at INSN.
11461
11462    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11463    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11464    live.  Otherwise, see if it is live or dead at the start of the basic
11465    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11466    must be assumed to be always live.  */
11467
11468 static int
11469 reg_dead_at_p (rtx reg, rtx insn)
11470 {
11471   basic_block block;
11472   unsigned int i;
11473
11474   /* Set variables for reg_dead_at_p_1.  */
11475   reg_dead_regno = REGNO (reg);
11476   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11477                                         ? hard_regno_nregs[reg_dead_regno]
11478                                                           [GET_MODE (reg)]
11479                                         : 1);
11480
11481   reg_dead_flag = 0;
11482
11483   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11484      we allow the machine description to decide whether use-and-clobber
11485      patterns are OK.  */
11486   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11487     {
11488       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11489         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11490           return 0;
11491     }
11492
11493   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11494      beginning of function.  */
11495   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11496        insn = prev_nonnote_insn (insn))
11497     {
11498       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11499       if (reg_dead_flag)
11500         return reg_dead_flag == 1 ? 1 : 0;
11501
11502       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11503         return 1;
11504     }
11505
11506   /* Get the basic block that we were in.  */
11507   if (insn == 0)
11508     block = ENTRY_BLOCK_PTR->next_bb;
11509   else
11510     {
11511       FOR_EACH_BB (block)
11512         if (insn == BB_HEAD (block))
11513           break;
11514
11515       if (block == EXIT_BLOCK_PTR)
11516         return 0;
11517     }
11518
11519   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11520     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11521       return 0;
11522
11523   return 1;
11524 }
11525 \f
11526 /* Note hard registers in X that are used.  This code is similar to
11527    that in flow.c, but much simpler since we don't care about pseudos.  */
11528
11529 static void
11530 mark_used_regs_combine (rtx x)
11531 {
11532   RTX_CODE code = GET_CODE (x);
11533   unsigned int regno;
11534   int i;
11535
11536   switch (code)
11537     {
11538     case LABEL_REF:
11539     case SYMBOL_REF:
11540     case CONST_INT:
11541     case CONST:
11542     case CONST_DOUBLE:
11543     case CONST_VECTOR:
11544     case PC:
11545     case ADDR_VEC:
11546     case ADDR_DIFF_VEC:
11547     case ASM_INPUT:
11548 #ifdef HAVE_cc0
11549     /* CC0 must die in the insn after it is set, so we don't need to take
11550        special note of it here.  */
11551     case CC0:
11552 #endif
11553       return;
11554
11555     case CLOBBER:
11556       /* If we are clobbering a MEM, mark any hard registers inside the
11557          address as used.  */
11558       if (MEM_P (XEXP (x, 0)))
11559         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11560       return;
11561
11562     case REG:
11563       regno = REGNO (x);
11564       /* A hard reg in a wide mode may really be multiple registers.
11565          If so, mark all of them just like the first.  */
11566       if (regno < FIRST_PSEUDO_REGISTER)
11567         {
11568           unsigned int endregno, r;
11569
11570           /* None of this applies to the stack, frame or arg pointers.  */
11571           if (regno == STACK_POINTER_REGNUM
11572 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11573               || regno == HARD_FRAME_POINTER_REGNUM
11574 #endif
11575 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11576               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11577 #endif
11578               || regno == FRAME_POINTER_REGNUM)
11579             return;
11580
11581           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11582           for (r = regno; r < endregno; r++)
11583             SET_HARD_REG_BIT (newpat_used_regs, r);
11584         }
11585       return;
11586
11587     case SET:
11588       {
11589         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11590            the address.  */
11591         rtx testreg = SET_DEST (x);
11592
11593         while (GET_CODE (testreg) == SUBREG
11594                || GET_CODE (testreg) == ZERO_EXTRACT
11595                || GET_CODE (testreg) == STRICT_LOW_PART)
11596           testreg = XEXP (testreg, 0);
11597
11598         if (MEM_P (testreg))
11599           mark_used_regs_combine (XEXP (testreg, 0));
11600
11601         mark_used_regs_combine (SET_SRC (x));
11602       }
11603       return;
11604
11605     default:
11606       break;
11607     }
11608
11609   /* Recursively scan the operands of this expression.  */
11610
11611   {
11612     const char *fmt = GET_RTX_FORMAT (code);
11613
11614     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11615       {
11616         if (fmt[i] == 'e')
11617           mark_used_regs_combine (XEXP (x, i));
11618         else if (fmt[i] == 'E')
11619           {
11620             int j;
11621
11622             for (j = 0; j < XVECLEN (x, i); j++)
11623               mark_used_regs_combine (XVECEXP (x, i, j));
11624           }
11625       }
11626   }
11627 }
11628 \f
11629 /* Remove register number REGNO from the dead registers list of INSN.
11630
11631    Return the note used to record the death, if there was one.  */
11632
11633 rtx
11634 remove_death (unsigned int regno, rtx insn)
11635 {
11636   rtx note = find_regno_note (insn, REG_DEAD, regno);
11637
11638   if (note)
11639     {
11640       REG_N_DEATHS (regno)--;
11641       remove_note (insn, note);
11642     }
11643
11644   return note;
11645 }
11646
11647 /* For each register (hardware or pseudo) used within expression X, if its
11648    death is in an instruction with cuid between FROM_CUID (inclusive) and
11649    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11650    list headed by PNOTES.
11651
11652    That said, don't move registers killed by maybe_kill_insn.
11653
11654    This is done when X is being merged by combination into TO_INSN.  These
11655    notes will then be distributed as needed.  */
11656
11657 static void
11658 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11659              rtx *pnotes)
11660 {
11661   const char *fmt;
11662   int len, i;
11663   enum rtx_code code = GET_CODE (x);
11664
11665   if (code == REG)
11666     {
11667       unsigned int regno = REGNO (x);
11668       rtx where_dead = reg_stat[regno].last_death;
11669       rtx before_dead, after_dead;
11670
11671       /* Don't move the register if it gets killed in between from and to.  */
11672       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11673           && ! reg_referenced_p (x, maybe_kill_insn))
11674         return;
11675
11676       /* WHERE_DEAD could be a USE insn made by combine, so first we
11677          make sure that we have insns with valid INSN_CUID values.  */
11678       before_dead = where_dead;
11679       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11680         before_dead = PREV_INSN (before_dead);
11681
11682       after_dead = where_dead;
11683       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11684         after_dead = NEXT_INSN (after_dead);
11685
11686       if (before_dead && after_dead
11687           && INSN_CUID (before_dead) >= from_cuid
11688           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11689               || (where_dead != after_dead
11690                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11691         {
11692           rtx note = remove_death (regno, where_dead);
11693
11694           /* It is possible for the call above to return 0.  This can occur
11695              when last_death points to I2 or I1 that we combined with.
11696              In that case make a new note.
11697
11698              We must also check for the case where X is a hard register
11699              and NOTE is a death note for a range of hard registers
11700              including X.  In that case, we must put REG_DEAD notes for
11701              the remaining registers in place of NOTE.  */
11702
11703           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11704               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11705                   > GET_MODE_SIZE (GET_MODE (x))))
11706             {
11707               unsigned int deadregno = REGNO (XEXP (note, 0));
11708               unsigned int deadend
11709                 = (deadregno + hard_regno_nregs[deadregno]
11710                                                [GET_MODE (XEXP (note, 0))]);
11711               unsigned int ourend
11712                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11713               unsigned int i;
11714
11715               for (i = deadregno; i < deadend; i++)
11716                 if (i < regno || i >= ourend)
11717                   REG_NOTES (where_dead)
11718                     = gen_rtx_EXPR_LIST (REG_DEAD,
11719                                          regno_reg_rtx[i],
11720                                          REG_NOTES (where_dead));
11721             }
11722
11723           /* If we didn't find any note, or if we found a REG_DEAD note that
11724              covers only part of the given reg, and we have a multi-reg hard
11725              register, then to be safe we must check for REG_DEAD notes
11726              for each register other than the first.  They could have
11727              their own REG_DEAD notes lying around.  */
11728           else if ((note == 0
11729                     || (note != 0
11730                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11731                             < GET_MODE_SIZE (GET_MODE (x)))))
11732                    && regno < FIRST_PSEUDO_REGISTER
11733                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11734             {
11735               unsigned int ourend
11736                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11737               unsigned int i, offset;
11738               rtx oldnotes = 0;
11739
11740               if (note)
11741                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11742               else
11743                 offset = 1;
11744
11745               for (i = regno + offset; i < ourend; i++)
11746                 move_deaths (regno_reg_rtx[i],
11747                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11748             }
11749
11750           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11751             {
11752               XEXP (note, 1) = *pnotes;
11753               *pnotes = note;
11754             }
11755           else
11756             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11757
11758           REG_N_DEATHS (regno)++;
11759         }
11760
11761       return;
11762     }
11763
11764   else if (GET_CODE (x) == SET)
11765     {
11766       rtx dest = SET_DEST (x);
11767
11768       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11769
11770       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11771          that accesses one word of a multi-word item, some
11772          piece of everything register in the expression is used by
11773          this insn, so remove any old death.  */
11774       /* ??? So why do we test for equality of the sizes?  */
11775
11776       if (GET_CODE (dest) == ZERO_EXTRACT
11777           || GET_CODE (dest) == STRICT_LOW_PART
11778           || (GET_CODE (dest) == SUBREG
11779               && (((GET_MODE_SIZE (GET_MODE (dest))
11780                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11781                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11782                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11783         {
11784           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11785           return;
11786         }
11787
11788       /* If this is some other SUBREG, we know it replaces the entire
11789          value, so use that as the destination.  */
11790       if (GET_CODE (dest) == SUBREG)
11791         dest = SUBREG_REG (dest);
11792
11793       /* If this is a MEM, adjust deaths of anything used in the address.
11794          For a REG (the only other possibility), the entire value is
11795          being replaced so the old value is not used in this insn.  */
11796
11797       if (MEM_P (dest))
11798         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11799                      to_insn, pnotes);
11800       return;
11801     }
11802
11803   else if (GET_CODE (x) == CLOBBER)
11804     return;
11805
11806   len = GET_RTX_LENGTH (code);
11807   fmt = GET_RTX_FORMAT (code);
11808
11809   for (i = 0; i < len; i++)
11810     {
11811       if (fmt[i] == 'E')
11812         {
11813           int j;
11814           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11815             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11816                          to_insn, pnotes);
11817         }
11818       else if (fmt[i] == 'e')
11819         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11820     }
11821 }
11822 \f
11823 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11824    pattern of an insn.  X must be a REG.  */
11825
11826 static int
11827 reg_bitfield_target_p (rtx x, rtx body)
11828 {
11829   int i;
11830
11831   if (GET_CODE (body) == SET)
11832     {
11833       rtx dest = SET_DEST (body);
11834       rtx target;
11835       unsigned int regno, tregno, endregno, endtregno;
11836
11837       if (GET_CODE (dest) == ZERO_EXTRACT)
11838         target = XEXP (dest, 0);
11839       else if (GET_CODE (dest) == STRICT_LOW_PART)
11840         target = SUBREG_REG (XEXP (dest, 0));
11841       else
11842         return 0;
11843
11844       if (GET_CODE (target) == SUBREG)
11845         target = SUBREG_REG (target);
11846
11847       if (!REG_P (target))
11848         return 0;
11849
11850       tregno = REGNO (target), regno = REGNO (x);
11851       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11852         return target == x;
11853
11854       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11855       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11856
11857       return endregno > tregno && regno < endtregno;
11858     }
11859
11860   else if (GET_CODE (body) == PARALLEL)
11861     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11862       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11863         return 1;
11864
11865   return 0;
11866 }
11867 \f
11868 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11869    as appropriate.  I3 and I2 are the insns resulting from the combination
11870    insns including FROM (I2 may be zero).
11871
11872    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11873    not need REG_DEAD notes because they are being substituted for.  This
11874    saves searching in the most common cases.
11875
11876    Each note in the list is either ignored or placed on some insns, depending
11877    on the type of note.  */
11878
11879 static void
11880 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11881                   rtx elim_i1)
11882 {
11883   rtx note, next_note;
11884   rtx tem;
11885
11886   for (note = notes; note; note = next_note)
11887     {
11888       rtx place = 0, place2 = 0;
11889
11890       next_note = XEXP (note, 1);
11891       switch (REG_NOTE_KIND (note))
11892         {
11893         case REG_BR_PROB:
11894         case REG_BR_PRED:
11895           /* Doesn't matter much where we put this, as long as it's somewhere.
11896              It is preferable to keep these notes on branches, which is most
11897              likely to be i3.  */
11898           place = i3;
11899           break;
11900
11901         case REG_VALUE_PROFILE:
11902           /* Just get rid of this note, as it is unused later anyway.  */
11903           break;
11904
11905         case REG_NON_LOCAL_GOTO:
11906           if (JUMP_P (i3))
11907             place = i3;
11908           else
11909             {
11910               gcc_assert (i2 && JUMP_P (i2));
11911               place = i2;
11912             }
11913           break;
11914
11915         case REG_EH_REGION:
11916           /* These notes must remain with the call or trapping instruction.  */
11917           if (CALL_P (i3))
11918             place = i3;
11919           else if (i2 && CALL_P (i2))
11920             place = i2;
11921           else
11922             {
11923               gcc_assert (flag_non_call_exceptions);
11924               if (may_trap_p (i3))
11925                 place = i3;
11926               else if (i2 && may_trap_p (i2))
11927                 place = i2;
11928               /* ??? Otherwise assume we've combined things such that we
11929                  can now prove that the instructions can't trap.  Drop the
11930                  note in this case.  */
11931             }
11932           break;
11933
11934         case REG_NORETURN:
11935         case REG_SETJMP:
11936           /* These notes must remain with the call.  It should not be
11937              possible for both I2 and I3 to be a call.  */
11938           if (CALL_P (i3))
11939             place = i3;
11940           else
11941             {
11942               gcc_assert (i2 && CALL_P (i2));
11943               place = i2;
11944             }
11945           break;
11946
11947         case REG_UNUSED:
11948           /* Any clobbers for i3 may still exist, and so we must process
11949              REG_UNUSED notes from that insn.
11950
11951              Any clobbers from i2 or i1 can only exist if they were added by
11952              recog_for_combine.  In that case, recog_for_combine created the
11953              necessary REG_UNUSED notes.  Trying to keep any original
11954              REG_UNUSED notes from these insns can cause incorrect output
11955              if it is for the same register as the original i3 dest.
11956              In that case, we will notice that the register is set in i3,
11957              and then add a REG_UNUSED note for the destination of i3, which
11958              is wrong.  However, it is possible to have REG_UNUSED notes from
11959              i2 or i1 for register which were both used and clobbered, so
11960              we keep notes from i2 or i1 if they will turn into REG_DEAD
11961              notes.  */
11962
11963           /* If this register is set or clobbered in I3, put the note there
11964              unless there is one already.  */
11965           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11966             {
11967               if (from_insn != i3)
11968                 break;
11969
11970               if (! (REG_P (XEXP (note, 0))
11971                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11972                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11973                 place = i3;
11974             }
11975           /* Otherwise, if this register is used by I3, then this register
11976              now dies here, so we must put a REG_DEAD note here unless there
11977              is one already.  */
11978           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11979                    && ! (REG_P (XEXP (note, 0))
11980                          ? find_regno_note (i3, REG_DEAD,
11981                                             REGNO (XEXP (note, 0)))
11982                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11983             {
11984               PUT_REG_NOTE_KIND (note, REG_DEAD);
11985               place = i3;
11986             }
11987           break;
11988
11989         case REG_EQUAL:
11990         case REG_EQUIV:
11991         case REG_NOALIAS:
11992           /* These notes say something about results of an insn.  We can
11993              only support them if they used to be on I3 in which case they
11994              remain on I3.  Otherwise they are ignored.
11995
11996              If the note refers to an expression that is not a constant, we
11997              must also ignore the note since we cannot tell whether the
11998              equivalence is still true.  It might be possible to do
11999              slightly better than this (we only have a problem if I2DEST
12000              or I1DEST is present in the expression), but it doesn't
12001              seem worth the trouble.  */
12002
12003           if (from_insn == i3
12004               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12005             place = i3;
12006           break;
12007
12008         case REG_INC:
12009         case REG_NO_CONFLICT:
12010           /* These notes say something about how a register is used.  They must
12011              be present on any use of the register in I2 or I3.  */
12012           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12013             place = i3;
12014
12015           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12016             {
12017               if (place)
12018                 place2 = i2;
12019               else
12020                 place = i2;
12021             }
12022           break;
12023
12024         case REG_LABEL:
12025           /* This can show up in several ways -- either directly in the
12026              pattern, or hidden off in the constant pool with (or without?)
12027              a REG_EQUAL note.  */
12028           /* ??? Ignore the without-reg_equal-note problem for now.  */
12029           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12030               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12031                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12032                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12033             place = i3;
12034
12035           if (i2
12036               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12037                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12038                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12039                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12040             {
12041               if (place)
12042                 place2 = i2;
12043               else
12044                 place = i2;
12045             }
12046
12047           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12048              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12049           if (place && JUMP_P (place))
12050             {
12051               rtx label = JUMP_LABEL (place);
12052
12053               if (!label)
12054                 JUMP_LABEL (place) = XEXP (note, 0);
12055               else
12056                 {
12057                   gcc_assert (label == XEXP (note, 0));
12058                   if (LABEL_P (label))
12059                     LABEL_NUSES (label)--;
12060                 }
12061               place = 0;
12062             }
12063           if (place2 && JUMP_P (place2))
12064             {
12065               rtx label = JUMP_LABEL (place2);
12066
12067               if (!label)
12068                 JUMP_LABEL (place2) = XEXP (note, 0);
12069               else
12070                 {
12071                   gcc_assert (label == XEXP (note, 0));
12072                   if (LABEL_P (label))
12073                     LABEL_NUSES (label)--;
12074                 }
12075               place2 = 0;
12076             }
12077           break;
12078
12079         case REG_NONNEG:
12080           /* This note says something about the value of a register prior
12081              to the execution of an insn.  It is too much trouble to see
12082              if the note is still correct in all situations.  It is better
12083              to simply delete it.  */
12084           break;
12085
12086         case REG_RETVAL:
12087           /* If the insn previously containing this note still exists,
12088              put it back where it was.  Otherwise move it to the previous
12089              insn.  Adjust the corresponding REG_LIBCALL note.  */
12090           if (!NOTE_P (from_insn))
12091             place = from_insn;
12092           else
12093             {
12094               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12095               place = prev_real_insn (from_insn);
12096               if (tem && place)
12097                 XEXP (tem, 0) = place;
12098               /* If we're deleting the last remaining instruction of a
12099                  libcall sequence, don't add the notes.  */
12100               else if (XEXP (note, 0) == from_insn)
12101                 tem = place = 0;
12102               /* Don't add the dangling REG_RETVAL note.  */
12103               else if (! tem)
12104                 place = 0;
12105             }
12106           break;
12107
12108         case REG_LIBCALL:
12109           /* This is handled similarly to REG_RETVAL.  */
12110           if (!NOTE_P (from_insn))
12111             place = from_insn;
12112           else
12113             {
12114               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12115               place = next_real_insn (from_insn);
12116               if (tem && place)
12117                 XEXP (tem, 0) = place;
12118               /* If we're deleting the last remaining instruction of a
12119                  libcall sequence, don't add the notes.  */
12120               else if (XEXP (note, 0) == from_insn)
12121                 tem = place = 0;
12122               /* Don't add the dangling REG_LIBCALL note.  */
12123               else if (! tem)
12124                 place = 0;
12125             }
12126           break;
12127
12128         case REG_DEAD:
12129           /* If we replaced the right hand side of FROM_INSN with a
12130              REG_EQUAL note, the original use of the dying register
12131              will not have been combined into I3 and I2.  In such cases,
12132              FROM_INSN is guaranteed to be the first of the combined
12133              instructions, so we simply need to search back before
12134              FROM_INSN for the previous use or set of this register,
12135              then alter the notes there appropriately.
12136
12137              If the register is used as an input in I3, it dies there.
12138              Similarly for I2, if it is nonzero and adjacent to I3.
12139
12140              If the register is not used as an input in either I3 or I2
12141              and it is not one of the registers we were supposed to eliminate,
12142              there are two possibilities.  We might have a non-adjacent I2
12143              or we might have somehow eliminated an additional register
12144              from a computation.  For example, we might have had A & B where
12145              we discover that B will always be zero.  In this case we will
12146              eliminate the reference to A.
12147
12148              In both cases, we must search to see if we can find a previous
12149              use of A and put the death note there.  */
12150
12151           if (from_insn
12152               && from_insn == i2mod
12153               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12154             tem = from_insn;
12155           else
12156             {
12157               if (from_insn
12158                   && CALL_P (from_insn)
12159                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12160                 place = from_insn;
12161               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12162                 place = i3;
12163               else if (i2 != 0 && next_nonnote_insn (i2) == i3
12164                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12165                 place = i2;
12166               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12167                         && !(i2mod
12168                              && reg_overlap_mentioned_p (XEXP (note, 0),
12169                                                          i2mod_old_rhs)))
12170                        || rtx_equal_p (XEXP (note, 0), elim_i1))
12171                 break;
12172               tem = i3;
12173             }
12174
12175           if (place == 0)
12176             {
12177               basic_block bb = this_basic_block;
12178
12179               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12180                 {
12181                   if (! INSN_P (tem))
12182                     {
12183                       if (tem == BB_HEAD (bb))
12184                         break;
12185                       continue;
12186                     }
12187
12188                   /* If the register is being set at TEM, see if that is all
12189                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12190                      into a REG_UNUSED note instead. Don't delete sets to
12191                      global register vars.  */
12192                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12193                        || !global_regs[REGNO (XEXP (note, 0))])
12194                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12195                     {
12196                       rtx set = single_set (tem);
12197                       rtx inner_dest = 0;
12198 #ifdef HAVE_cc0
12199                       rtx cc0_setter = NULL_RTX;
12200 #endif
12201
12202                       if (set != 0)
12203                         for (inner_dest = SET_DEST (set);
12204                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12205                               || GET_CODE (inner_dest) == SUBREG
12206                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12207                              inner_dest = XEXP (inner_dest, 0))
12208                           ;
12209
12210                       /* Verify that it was the set, and not a clobber that
12211                          modified the register.
12212
12213                          CC0 targets must be careful to maintain setter/user
12214                          pairs.  If we cannot delete the setter due to side
12215                          effects, mark the user with an UNUSED note instead
12216                          of deleting it.  */
12217
12218                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12219                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12220 #ifdef HAVE_cc0
12221                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12222                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12223                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12224 #endif
12225                           )
12226                         {
12227                           /* Move the notes and links of TEM elsewhere.
12228                              This might delete other dead insns recursively.
12229                              First set the pattern to something that won't use
12230                              any register.  */
12231                           rtx old_notes = REG_NOTES (tem);
12232
12233                           PATTERN (tem) = pc_rtx;
12234                           REG_NOTES (tem) = NULL;
12235
12236                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12237                                             NULL_RTX, NULL_RTX);
12238                           distribute_links (LOG_LINKS (tem));
12239
12240                           SET_INSN_DELETED (tem);
12241
12242 #ifdef HAVE_cc0
12243                           /* Delete the setter too.  */
12244                           if (cc0_setter)
12245                             {
12246                               PATTERN (cc0_setter) = pc_rtx;
12247                               old_notes = REG_NOTES (cc0_setter);
12248                               REG_NOTES (cc0_setter) = NULL;
12249
12250                               distribute_notes (old_notes, cc0_setter,
12251                                                 cc0_setter, NULL_RTX,
12252                                                 NULL_RTX, NULL_RTX);
12253                               distribute_links (LOG_LINKS (cc0_setter));
12254
12255                               SET_INSN_DELETED (cc0_setter);
12256                             }
12257 #endif
12258                         }
12259                       else
12260                         {
12261                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12262
12263                           /*  If there isn't already a REG_UNUSED note, put one
12264                               here.  Do not place a REG_DEAD note, even if
12265                               the register is also used here; that would not
12266                               match the algorithm used in lifetime analysis
12267                               and can cause the consistency check in the
12268                               scheduler to fail.  */
12269                           if (! find_regno_note (tem, REG_UNUSED,
12270                                                  REGNO (XEXP (note, 0))))
12271                             place = tem;
12272                           break;
12273                         }
12274                     }
12275                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12276                            || (CALL_P (tem)
12277                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12278                     {
12279                       place = tem;
12280
12281                       /* If we are doing a 3->2 combination, and we have a
12282                          register which formerly died in i3 and was not used
12283                          by i2, which now no longer dies in i3 and is used in
12284                          i2 but does not die in i2, and place is between i2
12285                          and i3, then we may need to move a link from place to
12286                          i2.  */
12287                       if (i2 && INSN_UID (place) <= max_uid_cuid
12288                           && INSN_CUID (place) > INSN_CUID (i2)
12289                           && from_insn
12290                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12291                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12292                         {
12293                           rtx links = LOG_LINKS (place);
12294                           LOG_LINKS (place) = 0;
12295                           distribute_links (links);
12296                         }
12297                       break;
12298                     }
12299
12300                   if (tem == BB_HEAD (bb))
12301                     break;
12302                 }
12303
12304               /* We haven't found an insn for the death note and it
12305                  is still a REG_DEAD note, but we have hit the beginning
12306                  of the block.  If the existing life info says the reg
12307                  was dead, there's nothing left to do.  Otherwise, we'll
12308                  need to do a global life update after combine.  */
12309               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12310                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12311                                       REGNO (XEXP (note, 0))))
12312                 SET_BIT (refresh_blocks, this_basic_block->index);
12313             }
12314
12315           /* If the register is set or already dead at PLACE, we needn't do
12316              anything with this note if it is still a REG_DEAD note.
12317              We check here if it is set at all, not if is it totally replaced,
12318              which is what `dead_or_set_p' checks, so also check for it being
12319              set partially.  */
12320
12321           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12322             {
12323               unsigned int regno = REGNO (XEXP (note, 0));
12324
12325               /* Similarly, if the instruction on which we want to place
12326                  the note is a noop, we'll need do a global live update
12327                  after we remove them in delete_noop_moves.  */
12328               if (noop_move_p (place))
12329                 SET_BIT (refresh_blocks, this_basic_block->index);
12330
12331               if (dead_or_set_p (place, XEXP (note, 0))
12332                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12333                 {
12334                   /* Unless the register previously died in PLACE, clear
12335                      last_death.  [I no longer understand why this is
12336                      being done.] */
12337                   if (reg_stat[regno].last_death != place)
12338                     reg_stat[regno].last_death = 0;
12339                   place = 0;
12340                 }
12341               else
12342                 reg_stat[regno].last_death = place;
12343
12344               /* If this is a death note for a hard reg that is occupying
12345                  multiple registers, ensure that we are still using all
12346                  parts of the object.  If we find a piece of the object
12347                  that is unused, we must arrange for an appropriate REG_DEAD
12348                  note to be added for it.  However, we can't just emit a USE
12349                  and tag the note to it, since the register might actually
12350                  be dead; so we recourse, and the recursive call then finds
12351                  the previous insn that used this register.  */
12352
12353               if (place && regno < FIRST_PSEUDO_REGISTER
12354                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12355                 {
12356                   unsigned int endregno
12357                     = regno + hard_regno_nregs[regno]
12358                                               [GET_MODE (XEXP (note, 0))];
12359                   int all_used = 1;
12360                   unsigned int i;
12361
12362                   for (i = regno; i < endregno; i++)
12363                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12364                          && ! find_regno_fusage (place, USE, i))
12365                         || dead_or_set_regno_p (place, i))
12366                       all_used = 0;
12367
12368                   if (! all_used)
12369                     {
12370                       /* Put only REG_DEAD notes for pieces that are
12371                          not already dead or set.  */
12372
12373                       for (i = regno; i < endregno;
12374                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12375                         {
12376                           rtx piece = regno_reg_rtx[i];
12377                           basic_block bb = this_basic_block;
12378
12379                           if (! dead_or_set_p (place, piece)
12380                               && ! reg_bitfield_target_p (piece,
12381                                                           PATTERN (place)))
12382                             {
12383                               rtx new_note
12384                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12385
12386                               distribute_notes (new_note, place, place,
12387                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12388                             }
12389                           else if (! refers_to_regno_p (i, i + 1,
12390                                                         PATTERN (place), 0)
12391                                    && ! find_regno_fusage (place, USE, i))
12392                             for (tem = PREV_INSN (place); ;
12393                                  tem = PREV_INSN (tem))
12394                               {
12395                                 if (! INSN_P (tem))
12396                                   {
12397                                     if (tem == BB_HEAD (bb))
12398                                       {
12399                                         SET_BIT (refresh_blocks,
12400                                                  this_basic_block->index);
12401                                         break;
12402                                       }
12403                                     continue;
12404                                   }
12405                                 if (dead_or_set_p (tem, piece)
12406                                     || reg_bitfield_target_p (piece,
12407                                                               PATTERN (tem)))
12408                                   {
12409                                     REG_NOTES (tem)
12410                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12411                                                            REG_NOTES (tem));
12412                                     break;
12413                                   }
12414                               }
12415
12416                         }
12417
12418                       place = 0;
12419                     }
12420                 }
12421             }
12422           break;
12423
12424         default:
12425           /* Any other notes should not be present at this point in the
12426              compilation.  */
12427           gcc_unreachable ();
12428         }
12429
12430       if (place)
12431         {
12432           XEXP (note, 1) = REG_NOTES (place);
12433           REG_NOTES (place) = note;
12434         }
12435       else if ((REG_NOTE_KIND (note) == REG_DEAD
12436                 || REG_NOTE_KIND (note) == REG_UNUSED)
12437                && REG_P (XEXP (note, 0)))
12438         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12439
12440       if (place2)
12441         {
12442           if ((REG_NOTE_KIND (note) == REG_DEAD
12443                || REG_NOTE_KIND (note) == REG_UNUSED)
12444               && REG_P (XEXP (note, 0)))
12445             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12446
12447           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12448                                                REG_NOTE_KIND (note),
12449                                                XEXP (note, 0),
12450                                                REG_NOTES (place2));
12451         }
12452     }
12453 }
12454 \f
12455 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12456    I3, I2, and I1 to new locations.  This is also called to add a link
12457    pointing at I3 when I3's destination is changed.  */
12458
12459 static void
12460 distribute_links (rtx links)
12461 {
12462   rtx link, next_link;
12463
12464   for (link = links; link; link = next_link)
12465     {
12466       rtx place = 0;
12467       rtx insn;
12468       rtx set, reg;
12469
12470       next_link = XEXP (link, 1);
12471
12472       /* If the insn that this link points to is a NOTE or isn't a single
12473          set, ignore it.  In the latter case, it isn't clear what we
12474          can do other than ignore the link, since we can't tell which
12475          register it was for.  Such links wouldn't be used by combine
12476          anyway.
12477
12478          It is not possible for the destination of the target of the link to
12479          have been changed by combine.  The only potential of this is if we
12480          replace I3, I2, and I1 by I3 and I2.  But in that case the
12481          destination of I2 also remains unchanged.  */
12482
12483       if (NOTE_P (XEXP (link, 0))
12484           || (set = single_set (XEXP (link, 0))) == 0)
12485         continue;
12486
12487       reg = SET_DEST (set);
12488       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12489              || GET_CODE (reg) == STRICT_LOW_PART)
12490         reg = XEXP (reg, 0);
12491
12492       /* A LOG_LINK is defined as being placed on the first insn that uses
12493          a register and points to the insn that sets the register.  Start
12494          searching at the next insn after the target of the link and stop
12495          when we reach a set of the register or the end of the basic block.
12496
12497          Note that this correctly handles the link that used to point from
12498          I3 to I2.  Also note that not much searching is typically done here
12499          since most links don't point very far away.  */
12500
12501       for (insn = NEXT_INSN (XEXP (link, 0));
12502            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12503                      || BB_HEAD (this_basic_block->next_bb) != insn));
12504            insn = NEXT_INSN (insn))
12505         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12506           {
12507             if (reg_referenced_p (reg, PATTERN (insn)))
12508               place = insn;
12509             break;
12510           }
12511         else if (CALL_P (insn)
12512                  && find_reg_fusage (insn, USE, reg))
12513           {
12514             place = insn;
12515             break;
12516           }
12517         else if (INSN_P (insn) && reg_set_p (reg, insn))
12518           break;
12519
12520       /* If we found a place to put the link, place it there unless there
12521          is already a link to the same insn as LINK at that point.  */
12522
12523       if (place)
12524         {
12525           rtx link2;
12526
12527           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12528             if (XEXP (link2, 0) == XEXP (link, 0))
12529               break;
12530
12531           if (link2 == 0)
12532             {
12533               XEXP (link, 1) = LOG_LINKS (place);
12534               LOG_LINKS (place) = link;
12535
12536               /* Set added_links_insn to the earliest insn we added a
12537                  link to.  */
12538               if (added_links_insn == 0
12539                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12540                 added_links_insn = place;
12541             }
12542         }
12543     }
12544 }
12545 \f
12546 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12547    Check whether the expression pointer to by LOC is a register or
12548    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12549    Otherwise return zero.  */
12550
12551 static int
12552 unmentioned_reg_p_1 (rtx *loc, void *expr)
12553 {
12554   rtx x = *loc;
12555
12556   if (x != NULL_RTX
12557       && (REG_P (x) || MEM_P (x))
12558       && ! reg_mentioned_p (x, (rtx) expr))
12559     return 1;
12560   return 0;
12561 }
12562
12563 /* Check for any register or memory mentioned in EQUIV that is not
12564    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12565    of EXPR where some registers may have been replaced by constants.  */
12566
12567 static bool
12568 unmentioned_reg_p (rtx equiv, rtx expr)
12569 {
12570   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12571 }
12572 \f
12573 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12574
12575 static int
12576 insn_cuid (rtx insn)
12577 {
12578   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12579          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12580     insn = NEXT_INSN (insn);
12581
12582   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12583
12584   return INSN_CUID (insn);
12585 }
12586 \f
12587 void
12588 dump_combine_stats (FILE *file)
12589 {
12590   fprintf
12591     (file,
12592      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12593      combine_attempts, combine_merges, combine_extras, combine_successes);
12594 }
12595
12596 void
12597 dump_combine_total_stats (FILE *file)
12598 {
12599   fprintf
12600     (file,
12601      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12602      total_attempts, total_merges, total_extras, total_successes);
12603 }
12604 \f
12605
12606 static bool
12607 gate_handle_combine (void)
12608 {
12609   return (optimize > 0);
12610 }
12611
12612 /* Try combining insns through substitution.  */
12613 static unsigned int
12614 rest_of_handle_combine (void)
12615 {
12616   int rebuild_jump_labels_after_combine
12617     = combine_instructions (get_insns (), max_reg_num ());
12618
12619   /* Combining insns may have turned an indirect jump into a
12620      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12621      instructions.  */
12622   if (rebuild_jump_labels_after_combine)
12623     {
12624       timevar_push (TV_JUMP);
12625       rebuild_jump_labels (get_insns ());
12626       timevar_pop (TV_JUMP);
12627
12628       delete_dead_jumptables ();
12629       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12630     }
12631   return 0;
12632 }
12633
12634 struct tree_opt_pass pass_combine =
12635 {
12636   "combine",                            /* name */
12637   gate_handle_combine,                  /* gate */
12638   rest_of_handle_combine,               /* execute */
12639   NULL,                                 /* sub */
12640   NULL,                                 /* next */
12641   0,                                    /* static_pass_number */
12642   TV_COMBINE,                           /* tv_id */
12643   0,                                    /* properties_required */
12644   0,                                    /* properties_provided */
12645   0,                                    /* properties_destroyed */
12646   0,                                    /* todo_flags_start */
12647   TODO_dump_func |
12648   TODO_ggc_collect,                     /* todo_flags_finish */
12649   'c'                                   /* letter */
12650 };
12651