| blob | e502fa147267d071adc0e47764ad8ded56ca0683 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 scalar_int_mode,
421 scalar_int_mode,
494 \f
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
516 \f
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
522 {
526 }
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
532 register. */
536 {
545 }
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
555 {
564 {
568 CASE_CONST_ANY:
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
596 }
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
603 {
605 {
610 else
616 /* Duplicate usage. */
618 }
620 {
624 {
630 else
637 }
638 }
639 }
642 }
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
661 {
662 basic_block bb;
668 {
678 }
688 {
694 {
699 }
700 }
703 }
704 \f
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
713 {
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
727 {
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
743 }
747 else
756 }
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
766 {
775 else
784 }
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
795 {
804 else
813 }
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
821 {
830 else
839 }
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
842 \f
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
854 {
859 /* Lookup the original insn_rtx_costs. */
864 {
867 {
871 }
872 else
873 {
877 }
878 }
879 else
880 {
883 }
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
891 /* Calculate the replacement insn_rtx_costs. */
894 {
898 }
899 else
900 {
903 }
906 {
912 {
915 }
916 else
918 }
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
925 {
944 else
946 }
951 /* Update the uid_insn_cost array with the replacement costs. */
955 {
959 }
962 }
965 /* Delete any insns that copy a register to itself. */
967 static void
969 {
971 basic_block bb;
974 {
976 {
979 {
984 }
985 }
986 }
987 }
989 \f
990 /* Return false if we do not want to (or cannot) combine DEF. */
991 static bool
993 {
994 /* Do not consider if it is pre/post modification in MEM. */
1000 /* Do not combine frame pointer adjustments. */
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1120 }
1121 \f
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1127 static int
1129 {
1134 basic_block last_bb;
1154 /* Allocate array for insn info. */
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1182 {
1187 label_tick++;
1195 {
1196 rtx links;
1202 insn);
1209 insn);
1211 /* Record the current insn_rtx_cost of this instruction. */
1214 optimize_this_for_speed_p);
1216 {
1219 }
1220 }
1221 }
1225 /* Now scan all the insns in forward order. */
1233 {
1239 label_tick++;
1249 {
1263 /* See if we know about function return values before this
1264 insn based upon SUBREG flags. */
1267 /* See if we can find hardregs and subreg of pseudos in
1268 narrower modes. This could help turning TRUNCATEs
1269 into SUBREGs. */
1272 /* Try this insn with each insn it links back to. */
1278 {
1281 }
1283 /* Try each sequence of three linked insns ending with this one. */
1287 {
1290 /* If the linked insn has been replaced by a note, then there
1291 is no point in pursuing this chain any further. */
1299 {
1302 }
1303 }
1305 /* Try to combine a jump insn that uses CC0
1306 with a preceding insn that sets CC0, and maybe with its
1307 logical predecessor as well.
1308 This is how we make decrement-and-branch insns.
1309 We need this special code because data flow connections
1310 via CC0 do not get entered in LOG_LINKS. */
1317 {
1328 }
1330 /* Do the same for an insn that explicitly references CC0. */
1337 {
1348 }
1350 /* Finally, see if any of the insns that this insn links to
1351 explicitly references CC0. If so, try this insn, that insn,
1352 and its predecessor if it sets CC0. */
1354 {
1366 }
1368 /* Try combining an insn with two different insns whose results it
1369 uses. */
1379 {
1382 }
1384 /* Try four-instruction combinations. */
1387 {
1391 /* If the linked insn has been replaced by a note, then there
1392 is no point in pursuing this chain any further. */
1397 {
1401 /* I0 -> I1 -> I2 -> I3. */
1407 {
1410 }
1411 /* I0, I1 -> I2, I2 -> I3. */
1418 {
1421 }
1422 }
1425 {
1429 /* I0 -> I2; I1, I2 -> I3. */
1435 {
1438 }
1439 /* I0 -> I1; I1, I2 -> I3. */
1445 {
1448 }
1449 }
1450 }
1452 /* Try this insn with each REG_EQUAL note it links back to. */
1454 {
1460 /* Avoid using a register that may already been marked
1461 dead by an earlier instruction. */
1469 {
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1483 last_combined_insn);
1486 {
1489 }
1492 }
1493 }
1498 retry:
1499 ;
1500 }
1501 }
1508 /* Clean up. */
1514 {
1517 {
1520 }
1522 }
1532 /* Make recognizer allow volatile MEMs again. */
1536 }
1538 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1540 static void
1542 {
1548 }
1549 \f
1550 /* Set up any promoted values for incoming argument registers. */
1552 static void
1554 {
1555 tree arg;
1560 {
1565 /* Only continue if the incoming argument is in a register. */
1569 /* Determine, if possible, whether all call sites of the current
1570 function lie within the current compilation unit. (This does
1571 take into account the exporting of a function via taking its
1572 address, and so forth.) */
1575 /* The mode and signedness of the argument before any promotions happen
1576 (equal to the mode of the pseudo holding it at that stage). */
1580 /* The mode and signedness of the argument after any source language and
1581 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1585 /* The mode and signedness of the argument as it is actually passed,
1586 see assign_parm_setup_reg in function.c. */
1590 /* The mode of the register in which the argument is being passed. */
1593 /* Eliminate sign extensions in the callee when:
1594 (a) A mode promotion has occurred; */
1597 /* (b) The mode of the register is the same as the mode of
1598 the argument as it is passed; */
1601 /* (c) There's no language level extension; */
1603 ;
1604 /* (c.1) All callers are from the current compilation unit. If that's
1605 the case we don't have to rely on an ABI, we only have to know
1606 what we're generating right now, and we know that we will do the
1607 mode1 to mode2 promotion with the given sign. */
1610 /* (c.2) The combination of the two promotions is useful. This is
1611 true when the signs match, or if the first promotion is unsigned.
1612 In the later case, (sign_extend (zero_extend x)) is the same as
1613 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1619 /* Record that the value was promoted from mode1 to mode3,
1620 so that any sign extension at the head of the current
1621 function may be eliminated. */
1625 }
1626 }
1628 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1629 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1630 because some machines (maybe most) will actually do the sign-extension and
1631 this is the conservative approach.
1633 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1634 kludge. */
1636 static rtx
1638 {
1639 scalar_int_mode int_mode;
1648 }
1650 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1651 and SET. */
1653 static void
1655 rtx x)
1656 {
1666 {
1670 }
1672 /* Don't call nonzero_bits if it cannot change anything. */
1674 {
1679 }
1681 /* Don't call num_sign_bit_copies if it cannot change anything. */
1683 {
1686 {
1690 }
1693 }
1694 }
1696 /* Called via note_stores. If X is a pseudo that is narrower than
1697 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1699 If we are setting only a portion of X and we can't figure out what
1700 portion, assume all bits will be used since we don't know what will
1701 be happening.
1703 Similarly, set how many bits of X are known to be copies of the sign bit
1704 at all locations in the function. This is the smallest number implied
1705 by any set of X. */
1707 static void
1709 {
1711 scalar_int_mode mode;
1715 /* If this register is undefined at the start of the file, we can't
1716 say what its contents were. */
1717 && ! REGNO_REG_SET_P
1721 {
1725 {
1729 }
1731 /* If this register is being initialized using itself, and the
1732 register is uninitialized in this basic block, and there are
1733 no LOG_LINKS which set the register, then part of the
1734 register is uninitialized. In that case we can't assume
1735 anything about the number of nonzero bits.
1737 ??? We could do better if we checked this in
1738 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1739 could avoid making assumptions about the insn which initially
1740 sets the register, while still using the information in other
1741 insns. We would have to be careful to check every insn
1742 involved in the combination. */
1748 {
1755 {
1759 }
1760 }
1762 /* If this is a complex assignment, see if we can convert it into a
1763 simple assignment. */
1766 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1767 set what we know about X. */
1773 else
1774 {
1777 }
1778 }
1779 }
1780 \f
1781 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1782 optionally insns that were previously combined into I3 or that will be
1783 combined into the merger of INSN and I3. The order is PRED, PRED2,
1784 INSN, SUCC, SUCC2, I3.
1786 Return 0 if the combination is not allowed for any reason.
1788 If the combination is allowed, *PDEST will be set to the single
1789 destination of INSN and *PSRC to the single source, and this function
1790 will return 1. */
1792 static int
1796 {
1801 rtx link;
1806 {
1808 {
1813 }
1818 }
1822 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1823 or a PARALLEL consisting of such a SET and CLOBBERs.
1825 If INSN has CLOBBER parallel parts, ignore them for our processing.
1826 By definition, these happen during the execution of the insn. When it
1827 is merged with another insn, all bets are off. If they are, in fact,
1828 needed and aren't also supplied in I3, they may be added by
1829 recog_for_combine. Otherwise, it won't match.
1831 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1832 note.
1834 Get the source and destination of INSN. If more than one, can't
1835 combine. */
1841 {
1843 {
1847 {
1848 /* This is important to combine floating point insns
1849 for the SH4 port. */
1851 /* Combining an isolated USE doesn't make sense.
1852 We depend here on combinable_i3pat to reject them. */
1853 /* The code below this loop only verifies that the inputs of
1854 the SET in INSN do not change. We call reg_set_between_p
1855 to verify that the REG in the USE does not change between
1856 I3 and INSN.
1857 If the USE in INSN was for a pseudo register, the matching
1858 insn pattern will likely match any register; combining this
1859 with any other USE would only be safe if we knew that the
1860 used registers have identical values, or if there was
1861 something to tell them apart, e.g. different modes. For
1862 now, we forgo such complicated tests and simply disallow
1863 combining of USES of pseudo registers with any other USE. */
1866 {
1871 do
1872 {
1882 }
1884 }
1887 /* We can ignore CLOBBERs. */
1892 /* Ignore SETs whose result isn't used but not those that
1893 have side-effects. */
1899 /* If we have already found a SET, this is a second one and
1900 so we cannot combine with this insn. */
1908 /* Anything else means we can't combine. */
1910 }
1911 }
1914 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1915 so don't do anything with it. */
1918 }
1919 else
1925 /* The simplification in expand_field_assignment may call back to
1926 get_last_value, so set safe guard here. */
1932 /* Do not eliminate user-specified register if it is in an
1933 asm input because we may break the register asm usage defined
1934 in GCC manual if allow to do so.
1935 Be aware that this may cover more cases than we expect but this
1936 should be harmless. */
1941 /* Don't eliminate a store in the stack pointer. */
1943 /* Don't combine with an insn that sets a register to itself if it has
1944 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1946 /* Can't merge an ASM_OPERANDS. */
1948 /* Can't merge a function call. */
1950 /* Don't eliminate a function call argument. */
1956 /* Don't substitute into an incremented register. */
1960 /* Don't substitute into a non-local goto, this confuses CFG. */
1962 /* Make sure that DEST is not used after INSN but before SUCC, or
1963 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1964 || (!all_adjacent
1965 && ((succ2
1969 || (succ
1970 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1971 that case SUCC is not in the insn stream, so use SUCC2
1972 instead for this test. */
1974 succ2
1977 /* Make sure that the value that is to be substituted for the register
1978 does not use any registers whose values alter in between. However,
1979 If the insns are adjacent, a use can't cross a set even though we
1980 think it might (this can happen for a sequence of insns each setting
1981 the same destination; last_set of that register might point to
1982 a NOTE). If INSN has a REG_EQUIV note, the register is always
1983 equivalent to the memory so the substitution is valid even if there
1984 are intervening stores. Also, don't move a volatile asm or
1985 UNSPEC_VOLATILE across any other insns. */
1986 || (! all_adjacent
1992 /* Don't combine across a CALL_INSN, because that would possibly
1993 change whether the life span of some REGs crosses calls or not,
1994 and it is a pain to update that information.
1995 Exception: if source is a constant, moving it later can't hurt.
1996 Accept that as a special case. */
2000 /* DEST must either be a REG or CC0. */
2002 {
2003 /* If register alignment is being enforced for multi-word items in all
2004 cases except for parameters, it is possible to have a register copy
2005 insn referencing a hard register that is not allowed to contain the
2006 mode being copied and which would not be valid as an operand of most
2007 insns. Eliminate this problem by not combining with such an insn.
2009 Also, on some machines we don't want to extend the life of a hard
2010 register. */
2015 /* Don't extend the life of a hard register unless it is
2016 user variable (if we have few registers) or it can't
2017 fit into the desired register (meaning something special
2018 is going on).
2019 Also avoid substituting a return register into I3, because
2020 reload can't handle a conflict with constraints of other
2021 inputs. */
2026 }
2034 {
2037 /* If the clobber represents an earlyclobber operand, we must not
2038 substitute an expression containing the clobbered register.
2039 As we do not analyze the constraint strings here, we have to
2040 make the conservative assumption. However, if the register is
2041 a fixed hard reg, the clobber cannot represent any operand;
2042 we leave it up to the machine description to either accept or
2043 reject use-and-clobber patterns. */
2049 }
2051 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2052 or not), reject, unless nothing volatile comes between it and I3 */
2055 {
2056 /* Make sure neither succ nor succ2 contains a volatile reference. */
2061 /* We'll check insns between INSN and I3 below. */
2062 }
2064 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2065 to be an explicit register variable, and was chosen for a reason. */
2071 /* If INSN contains volatile references (specifically volatile MEMs),
2072 we cannot combine across any other volatile references.
2073 Even if INSN doesn't contain volatile references, any intervening
2074 volatile insn might affect machine state. */
2077 ? volatile_refs_p
2084 /* If INSN contains an autoincrement or autodecrement, make sure that
2085 register is not used between there and I3, and not already used in
2086 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2087 Also insist that I3 not be a jump; if it were one
2088 and the incremented register were spilled, we would lose. */
2106 /* Don't combine an insn that follows a CC0-setting insn.
2107 An insn that uses CC0 must not be separated from the one that sets it.
2108 We do, however, allow I2 to follow a CC0-setting insn if that insn
2109 is passed as I1; in that case it will be deleted also.
2110 We also allow combining in this case if all the insns are adjacent
2111 because that would leave the two CC0 insns adjacent as well.
2112 It would be more logical to test whether CC0 occurs inside I1 or I2,
2113 but that would be much slower, and this ought to be equivalent. */
2116 {
2121 }
2123 /* If we get here, we have passed all the tests and the combination is
2124 to be allowed. */
2130 }
2131 \f
2132 /* LOC is the location within I3 that contains its pattern or the component
2133 of a PARALLEL of the pattern. We validate that it is valid for combining.
2135 One problem is if I3 modifies its output, as opposed to replacing it
2136 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2137 doing so would produce an insn that is not equivalent to the original insns.
2139 Consider:
2141 (set (reg:DI 101) (reg:DI 100))
2142 (set (subreg:SI (reg:DI 101) 0) <foo>)
2144 This is NOT equivalent to:
2146 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2147 (set (reg:DI 101) (reg:DI 100))])
2149 Not only does this modify 100 (in which case it might still be valid
2150 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2152 We can also run into a problem if I2 sets a register that I1
2153 uses and I1 gets directly substituted into I3 (not via I2). In that
2154 case, we would be getting the wrong value of I2DEST into I3, so we
2155 must reject the combination. This case occurs when I2 and I1 both
2156 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2157 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2158 of a SET must prevent combination from occurring. The same situation
2159 can occur for I0, in which case I0_NOT_IN_SRC is set.
2161 Before doing the above check, we first try to expand a field assignment
2162 into a set of logical operations.
2164 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2165 we place a register that is both set and used within I3. If more than one
2166 such register is detected, we fail.
2168 Return 1 if the combination is valid, zero otherwise. */
2170 static int
2173 {
2177 {
2182 rtx subdest;
2189 /* Check for the case where I3 modifies its output, as discussed
2190 above. We don't want to prevent pseudos from being combined
2191 into the address of a MEM, so only prevent the combination if
2192 i1 or i2 set the same MEM. */
2202 /* This is the same test done in can_combine_p except we can't test
2203 all_adjacent; we don't have to, since this instruction will stay
2204 in place, thus we are not considering increasing the lifetime of
2205 INNER_DEST.
2207 Also, if this insn sets a function argument, combining it with
2208 something that might need a spill could clobber a previous
2209 function argument; the all_adjacent test in can_combine_p also
2210 checks this; here, we do a more specific test for this case. */
2220 /* If DEST is used in I3, it is being killed in this insn, so
2221 record that for later. We have to consider paradoxical
2222 subregs here, since they kill the whole register, but we
2223 ignore partial subregs, STRICT_LOW_PART, etc.
2224 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2225 STACK_POINTER_REGNUM, since these are always considered to be
2226 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2234 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2240 {
2245 }
2246 }
2249 {
2256 }
2259 }
2260 \f
2261 /* Return 1 if X is an arithmetic expression that contains a multiplication
2262 and division. We don't count multiplications by powers of two here. */
2264 static int
2266 {
2268 {
2284 }
2285 }
2286 \f
2287 /* Determine whether INSN can be used in a combination. Return nonzero if
2288 not. This is used in try_combine to detect early some cases where we
2289 can't perform combinations. */
2291 static int
2293 {
2294 rtx set;
2297 /* If this isn't really an insn, we can't do anything.
2298 This can occur when flow deletes an insn that it has merged into an
2299 auto-increment address. */
2303 /* Never combine loads and stores involving hard regs that are likely
2304 to be spilled. The register allocator can usually handle such
2305 reg-reg moves by tying. If we allow the combiner to make
2306 substitutions of likely-spilled regs, reload might die.
2307 As an exception, we allow combinations involving fixed regs; these are
2308 not available to the register allocator so there's no risk involved. */
2329 }
2331 struct likely_spilled_retval_info
2332 {
2335 };
2337 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2338 hard registers that are known to be written to / clobbered in full. */
2339 static void
2341 {
2358 else
2361 }
2363 /* Return nonzero iff part of the return value is live during INSN, and
2364 it is likely spilled. This can happen when more than one insn is needed
2365 to copy the return value, e.g. when we consider to combine into the
2366 second copy insn for a complex value. */
2368 static int
2370 {
2372 rtx reg;
2375 /* We assume here that no machine mode needs more than
2376 32 hard registers when the value overlaps with a register
2377 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2392 /* Disregard parts of the return value that are set later. */
2401 /* Check if any of the (probably) live return value registers is
2402 likely spilled. */
2403 nregs --;
2404 do
2405 {
2411 }
2413 /* Adjust INSN after we made a change to its destination.
2415 Changing the destination can invalidate notes that say something about
2416 the results of the insn and a LOG_LINK pointing to the insn. */
2418 static void
2420 {
2421 /* For notes, be conservative and simply remove them. */
2424 /* The new insn will have a destination that was previously the destination
2425 of an insn just above it. Call distribute_links to make a LOG_LINK from
2426 the next use of that destination. */
2442 }
2444 /* Return TRUE if combine can reuse reg X in mode MODE.
2445 ADDED_SETS is nonzero if the original set is still required. */
2446 static bool
2448 {
2455 /* Allow hard registers if the new mode is legal, and occupies no more
2456 registers than the old mode. */
2461 /* Or a pseudo that is only used once. */
2464 && !added_sets
2466 }
2469 /* Check whether X, the destination of a set, refers to part of
2470 the register specified by REG. */
2472 static bool
2474 {
2475 /* Check that reg is an integer mode register. */
2486 }
2488 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2489 Note that the INSN should be deleted *after* removing dead edges, so
2490 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2491 but not for a (set (pc) (label_ref FOO)). */
2493 static void
2495 {
2503 {
2508 /* Remove barriers from the footer if there are any. */
2511 {
2514 else
2518 }
2521 }
2522 }
2524 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2525 by an arbitrary number of CLOBBERs. */
2526 static bool
2528 {
2547 }
2549 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2550 CLOBBERs), can be split into individual SETs in that order, without
2551 changing semantics. */
2552 static bool
2554 {
2562 {
2571 }
2574 }
2576 /* Try to combine the insns I0, I1 and I2 into I3.
2577 Here I0, I1 and I2 appear earlier than I3.
2578 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2579 I3.
2581 If we are combining more than two insns and the resulting insn is not
2582 recognized, try splitting it into two insns. If that happens, I2 and I3
2583 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2584 Otherwise, I0, I1 and I2 are pseudo-deleted.
2586 Return 0 if the combination does not work. Then nothing is changed.
2587 If we did the combination, return the insn at which combine should
2588 resume scanning.
2590 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2591 new direct jump instruction.
2593 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2594 been I3 passed to an earlier try_combine within the same basic
2595 block. */
2600 {
2601 /* New patterns for I3 and I2, respectively. */
2605 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2606 dead. */
2608 /* Total number of SETs to put into I3. */
2610 /* Nonzero if I2's or I1's body now appears in I3. */
2612 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2614 /* Contains I3 if the destination of I3 is used in its source, which means
2615 that the old life of I3 is being killed. If that usage is placed into
2616 I2 and not in I3, a REG_DEAD note must be made. */
2618 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2620 /* Copy of SET_SRC of I1 and I0, if needed. */
2622 /* Set if I2DEST was reused as a scratch register. */
2624 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2626 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2631 /* Notes that must be added to REG_NOTES in I3 and I2. */
2633 /* Notes that we substituted I3 into I2 instead of the normal case. */
2635 /* Notes that I1, I2 or I3 is a MULT operation. */
2642 rtx temp_expr;
2645 rtx new_other_notes;
2649 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2650 never be). */
2654 /* Only try four-insn combinations when there's high likelihood of
2655 success. Look for simple insns, such as loads of constants or
2656 binary operations involving a constant. */
2658 {
2668 {
2671 rtx src;
2676 {
2679 }
2681 ngood++;
2684 nshift++;
2685 }
2687 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2688 are likely manipulating its value. Ideally we'll be able to combine
2689 all four insns into a bitfield insertion of some kind.
2691 Note the source in I0 might be inside a sign/zero extension and the
2692 memory modes in I0 and I3 might be different. So extract the address
2693 from the destination of I3 and search for it in the source of I0.
2695 In the event that there's a match but the source/dest do not actually
2696 refer to the same memory, the worst that happens is we try some
2697 combinations that we wouldn't have otherwise. */
2699 /* Ensure the source of SET0 is a MEM, possibly buried inside
2700 an extension. */
2706 /* Ensure the destination of SET3 is a MEM. */
2708 /* Would it be better to extract the base address for the MEM
2709 in SET3 and look for that? I don't have cases where it matters
2710 but I could envision such cases. */
2716 }
2718 /* Exit early if one of the insns involved can't be used for
2719 combinations. */
2730 combine_attempts++;
2733 /* Reset the hard register usage information. */
2737 {
2744 else
2747 }
2749 /* If multiple insns feed into one of I2 or I3, they can be in any
2750 order. To simplify the code below, reorder them in sequence. */
2760 /* First check for one important special case that the code below will
2761 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2762 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2763 we may be able to replace that destination with the destination of I3.
2764 This occurs in the common code where we compute both a quotient and
2765 remainder into a structure, in which case we want to do the computation
2766 directly into the structure to avoid register-register copies.
2768 Note that this case handles both multiple sets in I2 and also cases
2769 where I2 has a number of CLOBBERs inside the PARALLEL.
2771 We make very conservative checks below and only try to handle the
2772 most common cases of this. For example, we only handle the case
2773 where I2 and I3 are adjacent to avoid making difficult register
2774 usage tests. */
2782 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2783 below would need to check what is inside (and reg_overlap_mentioned_p
2784 doesn't support those codes anyway). Don't allow those destinations;
2785 the resulting insn isn't likely to be recognized anyway. */
2791 {
2794 /* Make sure that the destination of I3,
2795 which we are going to substitute into one output of I2,
2796 is not used within another output of I2. We must avoid making this:
2797 (parallel [(set (mem (reg 69)) ...)
2798 (set (reg 69) ...)])
2799 which is not well-defined as to order of actions.
2800 (Besides, reload can't handle output reloads for this.)
2802 The problem can also happen if the dest of I3 is a memory ref,
2803 if another dest in I2 is an indirect memory ref.
2805 Neither can this PARALLEL be an asm. We do not allow combining
2806 that usually (see can_combine_p), so do not here either. */
2809 {
2818 }
2824 {
2825 combine_merges++;
2835 /* Replace the dest in I2 with our dest and make the resulting
2836 insn the new pattern for I3. Then skip to where we validate
2837 the pattern. Everything was set up above. */
2842 }
2843 }
2845 /* If I2 is setting a pseudo to a constant and I3 is setting some
2846 sub-part of it to another constant, merge them by making a new
2847 constant. */
2855 {
2862 {
2867 {
2873 }
2874 }
2875 else
2876 {
2880 {
2883 }
2884 }
2887 {
2888 /* If this is the low part, we're done. */
2890 ;
2891 /* Handle the case where inner is twice the size of outer. */
2895 /* Otherwise give up for now. */
2896 else
2898 }
2901 {
2909 combine_merges++;
2916 /* Replace the source in I2 with the new constant and make the
2917 resulting insn the new pattern for I3. Then skip to where we
2918 validate the pattern. Everything was set up above. */
2924 /* The dest of I3 has been replaced with the dest of I2. */
2927 }
2928 }
2930 /* If we have no I1 and I2 looks like:
2931 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2932 (set Y OP)])
2933 make up a dummy I1 that is
2934 (set Y OP)
2935 and change I2 to be
2936 (set (reg:CC X) (compare:CC Y (const_int 0)))
2938 (We can ignore any trailing CLOBBERs.)
2940 This undoes a previous combination and allows us to match a branch-and-
2941 decrement insn. */
2953 {
2954 /* We make I1 with the same INSN_UID as I2. This gives it
2955 the same DF_INSN_LUID for value tracking. Our fake I1 will
2956 never appear in the insn stream so giving it the same INSN_UID
2957 as I2 will not cause a problem. */
2970 }
2972 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2973 make those two SETs separate I1 and I2 insns, and make an I0 that is
2974 the original I1. */
2980 {
2981 /* If there is no I1, there is no I0 either. */
2984 /* We make I1 with the same INSN_UID as I2. This gives it
2985 the same DF_INSN_LUID for value tracking. Our fake I1 will
2986 never appear in the insn stream so giving it the same INSN_UID
2987 as I2 will not cause a problem. */
2995 }
2997 /* Verify that I2 and I1 are valid for combining. */
3003 {
3006 }
3008 /* Record whether I2DEST is used in I2SRC and similarly for the other
3009 cases. Knowing this will help in register status updating below. */
3020 /* For the earlier insns, determine which of the subsequent ones they
3021 feed. */
3028 /* Ensure that I3's pattern can be the destination of combines. */
3034 {
3037 }
3039 /* See if any of the insns is a MULT operation. Unless one is, we will
3040 reject a combination that is, since it must be slower. Be conservative
3041 here. */
3049 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3050 We used to do this EXCEPT in one case: I3 has a post-inc in an
3051 output operand. However, that exception can give rise to insns like
3052 mov r3,(r3)+
3053 which is a famous insn on the PDP-11 where the value of r3 used as the
3054 source was model-dependent. Avoid this sort of thing. */
3056 #if 0
3062 /* It's not the exception. */
3063 #endif
3065 {
3066 rtx link;
3072 {
3075 }
3076 }
3078 /* See if the SETs in I1 or I2 need to be kept around in the merged
3079 instruction: whenever the value set there is still needed past I3.
3080 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3082 For the SET in I1, we have two cases: if I1 and I2 independently feed
3083 into I3, the set in I1 needs to be kept around unless I1DEST dies
3084 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3085 in I1 needs to be kept around unless I1DEST dies or is set in either
3086 I2 or I3. The same considerations apply to I0. */
3093 else
3101 else
3104 /* We are about to copy insns for the case where they need to be kept
3105 around. Check that they can be copied in the merged instruction. */
3111 {
3114 }
3116 /* If the set in I2 needs to be kept around, we must make a copy of
3117 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3118 PATTERN (I2), we are only substituting for the original I1DEST, not into
3119 an already-substituted copy. This also prevents making self-referential
3120 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3121 I2DEST. */
3124 {
3127 else
3129 }
3132 {
3135 else
3137 }
3140 {
3143 else
3145 }
3147 combine_merges++;
3149 /* Substitute in the latest insn for the regs set by the earlier ones. */
3155 /* Many machines that don't use CC0 have insns that can both perform an
3156 arithmetic operation and set the condition code. These operations will
3157 be represented as a PARALLEL with the first element of the vector
3158 being a COMPARE of an arithmetic operation with the constant zero.
3159 The second element of the vector will set some pseudo to the result
3160 of the same arithmetic operation. If we simplify the COMPARE, we won't
3161 match such a pattern and so will generate an extra insn. Here we test
3162 for this case, where both the comparison and the operation result are
3163 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3164 I2SRC. Later we will make the PARALLEL that contains I2. */
3170 {
3171 rtx newpat_dest;
3177 scalar_int_mode mode;
3186 {
3192 }
3194 /* Do the rest only if op1 is const0_rtx, which may be the
3195 result of simplification. */
3197 {
3198 /* If a single use of the CC is found, prepare to modify it
3199 when SELECT_CC_MODE returns a new CC-class mode, or when
3200 the above simplify_compare_const() returned a new comparison
3201 operator. undobuf.other_insn is assigned the CC use insn
3202 when modifying it. */
3204 {
3205 #ifdef SELECT_CC_MODE
3206 machine_mode new_mode
3211 {
3216 else
3217 {
3220 }
3221 }
3222 #endif
3223 /* Cases for modifying the CC-using comparison. */
3225 /* ??? Do we need to verify the zero rtx? */
3227 {
3228 /* Replace cc_use_loc with entire new RTX. */
3233 }
3235 {
3236 /* Just replace the CC reg with a new mode. */
3239 }
3240 }
3242 /* Now we modify the current newpat:
3243 First, SET_DEST(newpat) is updated if the CC mode has been
3244 altered. For targets without SELECT_CC_MODE, this should be
3245 optimized away. */
3248 /* This is always done to propagate i2src into newpat. */
3251 /* Create new version of i2pat if needed; the below PARALLEL
3252 creation needs this to work correctly. */
3256 }
3257 }
3260 {
3261 /* It is possible that the source of I2 or I1 may be performing
3262 an unneeded operation, such as a ZERO_EXTEND of something
3263 that is known to have the high part zero. Handle that case
3264 by letting subst look at the inner insns.
3266 Another way to do this would be to have a function that tries
3267 to simplify a single insn instead of merging two or more
3268 insns. We don't do this because of the potential of infinite
3269 loops and because of the potential extra memory required.
3270 However, doing it the way we are is a bit of a kludge and
3271 doesn't catch all cases.
3273 But only do this if -fexpensive-optimizations since it slows
3274 things down and doesn't usually win.
3276 This is not done in the COMPARE case above because the
3277 unmodified I2PAT is used in the PARALLEL and so a pattern
3278 with a modified I2SRC would not match. */
3281 {
3282 /* Pass pc_rtx so no substitutions are done, just
3283 simplifications. */
3285 {
3288 }
3292 }
3297 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3298 copy of I2SRC each time we substitute it, in order to avoid creating
3299 self-referential RTL when we will be substituting I1SRC for I1DEST
3300 later. Likewise if I0 feeds into I2, either directly or indirectly
3301 through I1, and I0DEST is in I0SRC. */
3308 /* Record whether I2's body now appears within I3's body. */
3310 }
3312 /* If we already got a failure, don't try to do more. Otherwise, try to
3313 substitute I1 if we have it. */
3316 {
3317 /* Check that an autoincrement side-effect on I1 has not been lost.
3318 This happens if I1DEST is mentioned in I2 and dies there, and
3319 has disappeared from the new pattern. */
3321 && i1_feeds_i2_n
3324 /* Before we can do this substitution, we must redo the test done
3325 above (see detailed comments there) that ensures I1DEST isn't
3326 mentioned in any SETs in NEWPAT that are field assignments. */
3329 {
3332 }
3337 /* If the following substitution will modify I1SRC, make a copy of it
3338 for the case where it is substituted for I1DEST in I2PAT later. */
3342 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3343 copy of I1SRC each time we substitute it, in order to avoid creating
3344 self-referential RTL when we will be substituting I0SRC for I0DEST
3345 later. */
3350 /* Record whether I1's body now appears within I3's body. */
3352 }
3354 /* Likewise for I0 if we have it. */
3357 {
3364 {
3367 }
3369 /* If the following substitution will modify I0SRC, make a copy of it
3370 for the case where it is substituted for I0DEST in I1PAT later. */
3373 /* And a copy for I0DEST in I2PAT substitution. */
3382 }
3384 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3385 to count all the ways that I2SRC and I1SRC can be used. */
3396 /* Fail if we tried to make a new register. */
3398 /* Fail if we couldn't do something and have a CLOBBER. */
3400 /* Fail if this new pattern is a MULT and we didn't have one before
3401 at the outer level. */
3404 {
3407 }
3409 /* If the actions of the earlier insns must be kept
3410 in addition to substituting them into the latest one,
3411 we must make a new PARALLEL for the latest insn
3412 to hold additional the SETs. */
3415 {
3417 combine_extras++;
3420 {
3426 }
3427 else
3428 {
3433 }
3439 {
3445 }
3447 {
3456 }
3457 }
3459 validate_replacement:
3461 /* Note which hard regs this insn has as inputs. */
3464 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3465 consider splitting this pattern, we might need these clobbers. */
3468 {
3474 }
3476 /* We have recognized nothing yet. */
3479 /* See if this is a PARALLEL of two SETs where one SET's destination is
3480 a register that is unused and this isn't marked as an instruction that
3481 might trap in an EH region. In that case, we just need the other SET.
3482 We prefer this over the PARALLEL.
3484 This can occur when simplifying a divmod insn. We *must* test for this
3485 case here because the code below that splits two independent SETs doesn't
3486 handle this case correctly when it updates the register status.
3488 It's pointless doing this if we originally had two sets, one from
3489 i3, and one from i2. Combining then splitting the parallel results
3490 in the original i2 again plus an invalid insn (which we delete).
3491 The net effect is only to move instructions around, which makes
3492 debug info less accurate.
3494 If the remaining SET came from I2 its destination should not be used
3495 between I2 and I3. See PR82024. */
3500 {
3511 {
3514 }
3523 {
3528 {
3534 }
3535 }
3539 }
3541 /* Is the result of combination a valid instruction? */
3545 /* If we were combining three insns and the result is a simple SET
3546 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3547 insns. There are two ways to do this. It can be split using a
3548 machine-specific method (like when you have an addition of a large
3549 constant) or by combine in the function find_split_point. */
3553 {
3557 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3558 use I2DEST as a scratch register will help. In the latter case,
3559 convert I2DEST to the mode of the source of NEWPAT if we can. */
3563 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3564 inputs of NEWPAT. */
3566 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3567 possible to try that as a scratch reg. This would require adding
3568 more code to make it work though. */
3571 {
3574 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3575 (temporarily, until we are committed to this instruction
3576 combination) does not work: for example, any call to nonzero_bits
3577 on the register (from a splitter in the MD file, for example)
3578 will get the old information, which is invalid.
3580 Since nowadays we can create registers during combine just fine,
3581 we should just create a new one here, not reuse i2dest. */
3583 /* First try to split using the original register as a
3584 scratch register. */
3588 i2dest)));
3591 /* If that didn't work, try changing the mode of I2DEST if
3592 we can. */
3597 {
3599 rtx ni2dest;
3603 else
3604 {
3607 }
3609 parallel = (gen_rtx_PARALLEL
3613 ni2dest))));
3618 {
3626 }
3627 }
3630 }
3632 /* If recog_for_combine has discarded clobbers, try to use them
3633 again for the split. */
3635 {
3638 }
3641 {
3646 }
3650 {
3660 /* If I2 or I3 has multiple SETs, we won't know how to track
3661 register status, so don't use these insns. If I2's destination
3662 is used between I2 and I3, we also can't use these insns. */
3672 /* It is possible that both insns now set the destination of I3.
3673 If so, we must show an extra use of it. */
3676 {
3695 }
3696 }
3698 /* If we can split it and use I2DEST, go ahead and see if that
3699 helps things be recognized. Verify that none of the registers
3700 are set between I2 and I3. */
3704 /* We need I2DEST in the proper mode. If it is a hard register
3705 or the only use of a pseudo, we can change its mode.
3706 Make sure we don't change a hard register to have a mode that
3707 isn't valid for it, or change the number of registers. */
3714 /* We can't overwrite I2DEST if its value is still used by
3715 NEWPAT. */
3717 {
3726 /* *SPLIT may be part of I2SRC, so make sure we have the
3727 original expression around for later debug processing.
3728 We should not need I2SRC any more in other cases. */
3731 else
3734 /* Get NEWDEST as a register in the proper mode. We have already
3735 validated that we can do this. */
3737 {
3740 else
3741 {
3744 }
3745 }
3747 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3748 an ASHIFT. This can occur if it was inside a PLUS and hence
3749 appeared to be a memory address. This is a kludge. */
3754 {
3757 /* Update split_code because we may not have a multiply
3758 anymore. */
3760 }
3762 /* Similarly for (plus (mult FOO (const_int pow2))). */
3768 {
3772 /* Update split_code because we may not have a multiply
3773 anymore. */
3775 }
3777 #ifdef INSN_SCHEDULING
3778 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3779 be written as a ZERO_EXTEND. */
3781 {
3782 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3783 what it really is. */
3788 else
3791 }
3792 #endif
3794 /* Attempt to split binary operators using arithmetic identities. */
3798 {
3805 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3807 {
3812 }
3813 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3820 {
3826 /* Split both "((X op Y) op X) op Y" and
3827 "((X op Y) op Y) op X" as "T op T" where T is
3828 "X op Y". */
3831 {
3836 }
3837 /* Split "((X op X) op Y) op Y)" as "T op T" where
3838 T is "X op Y". */
3840 {
3846 }
3847 }
3848 }
3851 {
3854 }
3858 /* recog_for_combine might have added CLOBBERs to newi2pat.
3859 Make sure NEWPAT does not depend on the clobbered regs. */
3863 {
3866 {
3869 }
3870 }
3872 /* If the split point was a MULT and we didn't have one before,
3873 don't use one now. */
3876 }
3877 }
3879 /* Check for a case where we loaded from memory in a narrow mode and
3880 then sign extended it, but we need both registers. In that case,
3881 we have a PARALLEL with both loads from the same memory location.
3882 We can split this into a load from memory followed by a register-register
3883 copy. This saves at least one insn, more if register allocation can
3884 eliminate the copy.
3886 We cannot do this if the destination of the first assignment is a
3887 condition code register or cc0. We eliminate this case by making sure
3888 the SET_DEST and SET_SRC have the same mode.
3890 We cannot do this if the destination of the second assignment is
3891 a register that we have already assumed is zero-extended. Similarly
3892 for a SUBREG of such a register. */
3927 {
3928 rtx ni2dest;
3942 }
3944 /* Similarly, check for a case where we have a PARALLEL of two independent
3945 SETs but we started with three insns. In this case, we can do the sets
3946 as two separate insns. This case occurs when some SET allows two
3947 other insns to combine, but the destination of that SET is still live.
3949 Also do this if we started with two insns and (at least) one of the
3950 resulting sets is a noop; this noop will be deleted later. */
3969 {
3973 /* Normally, it doesn't matter which of the two is done first,
3974 but the one that references cc0 can't be the second, and
3975 one which uses any regs/memory set in between i2 and i3 can't
3976 be first. The PARALLEL might also have been pre-existing in i3,
3977 so we need to make sure that we won't wrongly hoist a SET to i2
3978 that would conflict with a death note present in there. */
3986 /* If I3 is a jump, ensure that set0 is a jump so that
3987 we do not create invalid RTL. */
3989 )
3990 {
3993 }
4001 /* If I3 is a jump, ensure that set1 is a jump so that
4002 we do not create invalid RTL. */
4004 )
4005 {
4008 }
4009 else
4010 {
4013 }
4018 {
4019 /* recog_for_combine might have added CLOBBERs to newi2pat.
4020 Make sure NEWPAT does not depend on the clobbered regs. */
4022 {
4025 {
4028 {
4031 }
4032 }
4033 }
4036 }
4037 }
4039 /* If it still isn't recognized, fail and change things back the way they
4040 were. */
4042 /* Is the result a reasonable ASM_OPERANDS? */
4044 {
4047 }
4049 /* If we had to change another insn, make sure it is valid also. */
4051 {
4059 {
4062 }
4063 }
4065 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4066 they are adjacent to each other or not. */
4068 {
4072 {
4075 }
4076 }
4078 /* Only allow this combination if insn_rtx_costs reports that the
4079 replacement instructions are cheaper than the originals. */
4081 {
4084 }
4087 {
4092 {
4097 /* Temporarily revert mode back. */
4101 {
4102 /* If we used i2dest as a scratch register with a
4103 different mode, substitute it for the original
4104 i2src while its original mode is temporarily
4105 restored, and then clear i2scratch so that we don't
4106 do it again later. */
4108 this_basic_block);
4110 /* Put back the new mode. */
4112 }
4113 else
4114 {
4119 {
4122 }
4123 else
4124 {
4131 }
4133 /* We're dealing with a reg that changed mode but not
4134 meaning, so we want to turn it into a subreg for
4135 the new mode. However, because of REG sharing and
4136 because its mode had already changed, we have to do
4137 it in two steps. First, replace any debug uses of
4138 reg, with its original mode temporarily restored,
4139 with this copy we have created; then, replace the
4140 copy with the SUBREG of the original shared reg,
4141 once again changed to the new mode. */
4143 this_basic_block);
4147 this_basic_block);
4148 }
4149 }
4150 }
4152 /* If we will be able to accept this, we have made a
4153 change to the destination of I3. This requires us to
4154 do a few adjustments. */
4157 {
4160 }
4162 /* We now know that we can do this combination. Merge the insns and
4163 update the status of registers and LOG_LINKS. */
4166 {
4171 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4172 ensure that they are still valid. Then add any non-duplicate
4173 notes added by recog_for_combine. */
4175 {
4184 /* Simply drop equal note since it may be no longer valid
4185 for other_insn. It may be possible to record that CC
4186 register is changed and only discard those notes, but
4187 in practice it's unnecessary complication and doesn't
4188 give any meaningful improvement.
4190 See PR78559. */
4194 }
4198 NULL_RTX);
4199 }
4202 {
4205 rtx ni2dest;
4207 /* I3 now uses what used to be its destination and which is now
4208 I2's destination. This requires us to do a few adjustments. */
4212 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4213 so we still will.
4215 However, some later insn might be using I2's dest and have
4216 a LOG_LINK pointing at I3. We must remove this link.
4217 The simplest way to remove the link is to point it at I1,
4218 which we know will be a NOTE. */
4220 /* newi2pat is usually a SET here; however, recog_for_combine might
4221 have added some clobbers. */
4224 else
4231 {
4234 {
4240 }
4241 }
4242 }
4244 {
4249 /* Compute which registers we expect to eliminate. newi2pat may be setting
4250 either i3dest or i2dest, so we must check it. */
4253 || !i2dest_killed
4255 /* For i1, we need to compute both local elimination and global
4256 elimination information with respect to newi2pat because i1dest
4257 may be the same as i3dest, in which case newi2pat may be setting
4258 i1dest. Global information is used when distributing REG_DEAD
4259 note for i2 and i3, in which case it does matter if newi2pat sets
4260 i1dest or not.
4262 Local information is used when distributing REG_DEAD note for i1,
4263 in which case it doesn't matter if newi2pat sets i1dest or not.
4264 See PR62151, if we have four insns combination:
4265 i0: r0 <- i0src
4266 i1: r1 <- i1src (using r0)
4267 REG_DEAD (r0)
4268 i2: r0 <- i2src (using r1)
4269 i3: r3 <- i3src (using r0)
4270 ix: using r0
4271 From i1's point of view, r0 is eliminated, no matter if it is set
4272 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4273 should be discarded.
4275 Note local information only affects cases in forms like "I1->I2->I3",
4276 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4277 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4278 i0dest anyway. */
4280 || !i1dest_killed
4285 /* Same case as i1. */
4292 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4293 clear them. */
4301 /* Ensure that we do not have something that should not be shared but
4302 occurs multiple times in the new insns. Check this by first
4303 resetting all the `used' flags and then copying anything is shared. */
4327 {
4330 {
4332 {
4333 /* I2SRC must still be meaningful at this point. Some
4334 splitting operations can invalidate I2SRC, but those
4335 operations do not apply to calls. */
4339 }
4346 }
4347 }
4352 /* We had one special case above where I2 had more than one set and
4353 we replaced a destination of one of those sets with the destination
4354 of I3. In that case, we have to update LOG_LINKS of insns later
4355 in this basic block. Note that this (expensive) case is rare.
4357 Also, in this case, we must pretend that all REG_NOTEs for I2
4358 actually came from I3, so that REG_UNUSED notes from I2 will be
4359 properly handled. */
4362 {
4371 temp_insn
4381 {
4386 }
4387 else
4390 }
4398 {
4401 this_basic_block);
4404 }
4405 else
4406 {
4409 this_basic_block);
4411 }
4414 {
4419 this_basic_block);
4421 }
4424 {
4429 this_basic_block);
4431 }
4433 /* Get death notes for everything that is now used in either I3 or
4434 I2 and used to die in a previous insn. If we built two new
4435 patterns, move from I1 to I2 then I2 to I3 so that we get the
4436 proper movement on registers that I2 modifies. */
4442 else
4448 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4465 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4466 know these are REG_UNUSED and want them to go to the desired insn,
4467 so we always pass it as i3. */
4471 NULL_RTX);
4475 NULL_RTX);
4477 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4478 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4479 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4480 in that case, it might delete I2. Similarly for I2 and I1.
4481 Show an additional death due to the REG_DEAD note we make here. If
4482 we discard it in distribute_notes, we will decrement it again. */
4485 {
4490 else
4493 }
4496 {
4501 else
4504 }
4507 {
4512 else
4515 }
4518 {
4523 else
4526 }
4534 {
4539 /* The insn that used to set this register doesn't exist, and
4540 this life of the register may not exist either. See if one of
4541 I3's links points to an insn that sets I2DEST. If it does,
4542 that is now the last known value for I2DEST. If we don't update
4543 this and I2 set the register to a value that depended on its old
4544 contents, we will get confused. If this insn is used, thing
4545 will be set correctly in combine_instructions. */
4553 /* If the reg formerly set in I2 died only once and that was in I3,
4554 zero its use count so it won't make `reload' do any work. */
4557 && ! i2dest_in_i2src
4560 }
4563 {
4576 && ! i1dest_in_i1src
4579 }
4582 {
4595 && ! i0dest_in_i0src
4598 }
4600 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4601 been made to this insn. The order is important, because newi2pat
4602 can affect nonzero_bits of newpat. */
4606 }
4609 {
4611 {
4614 }
4616 }
4619 {
4621 {
4624 }
4626 }
4629 {
4631 {
4634 }
4636 }
4639 {
4641 {
4644 }
4646 }
4649 {
4651 {
4654 }
4656 }
4658 /* Set new_direct_jump_p if a new return or simple jump instruction
4659 has been created. Adjust the CFG accordingly. */
4661 {
4665 }
4670 {
4673 }
4677 {
4683 }
4688 {
4694 }
4696 /* A noop might also need cleaning up of CFG, if it comes from the
4697 simplification of a jump. */
4702 {
4705 }
4712 {
4715 }
4717 combine_successes++;
4724 else
4726 }
4727 \f
4728 /* Get a marker for undoing to the current state. */
4732 {
4734 }
4736 /* Undo the modifications up to the marker. */
4738 static void
4740 {
4744 {
4749 {
4764 }
4768 }
4771 }
4773 /* Undo all the modifications recorded in undobuf. */
4775 static void
4777 {
4779 }
4781 /* We've committed to accepting the changes we made. Move all
4782 of the undos to the free list. */
4784 static void
4786 {
4790 {
4794 }
4796 }
4797 \f
4798 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4799 where we have an arithmetic expression and return that point. LOC will
4800 be inside INSN.
4802 try_combine will call this function to see if an insn can be split into
4803 two insns. */
4807 {
4817 /* First special-case some codes. */
4819 {
4821 #ifdef INSN_SCHEDULING
4822 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4823 point. */
4826 #endif
4830 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4831 using LO_SUM and HIGH. */
4834 {
4842 }
4844 /* If we have a PLUS whose second operand is a constant and the
4845 address is not valid, perhaps will can split it up using
4846 the machine-specific way to split large constants. We use
4847 the first pseudo-reg (one of the virtual regs) as a placeholder;
4848 it will not remain in the result. */
4853 {
4856 subst_insn);
4858 /* This should have produced two insns, each of which sets our
4859 placeholder. If the source of the second is a valid address,
4860 we can make put both sources together and make a split point
4861 in the middle. */
4874 && memory_address_addr_space_p
4877 {
4881 /* Replace the placeholder in SRC2 with SRC1. If we can
4882 find where in SRC2 it was placed, that can become our
4883 split point and we can replace this address with SRC2.
4884 Just try two obvious places. */
4895 {
4898 }
4899 }
4901 /* If that didn't work, perhaps the first operand is complex and
4902 needs to be computed separately, so make a split point there.
4903 This will occur on machines that just support REG + CONST
4904 and have a constant moved through some previous computation. */
4910 }
4912 /* If we have a PLUS whose first operand is complex, try computing it
4913 separately by making a split there. */
4924 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4925 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4926 we need to put the operand into a register. So split at that
4927 point. */
4937 /* See if we can split SET_SRC as it stands. */
4942 /* See if we can split SET_DEST as it stands. */
4947 /* See if this is a bitfield assignment with everything constant. If
4948 so, this is an IOR of an AND, so split it into that. */
4960 {
4965 unsigned HOST_WIDE_INT mask
4967 rtx or_mask;
4976 else
4977 {
4983 or_mask));
4984 }
4991 }
4993 /* Otherwise, see if this is an operation that we can split into two.
4994 If so, try to split that. */
4998 {
5000 /* If we are AND'ing with a large constant that is only a single
5001 bit and the result is only being used in a context where we
5002 need to know if it is zero or nonzero, replace it with a bit
5003 extraction. This will avoid the large constant, which might
5004 have taken more than one insn to make. If the constant were
5005 not a valid argument to the AND but took only one insn to make,
5006 this is no worse, but if it took more than one insn, it will
5007 be better. */
5017 {
5022 {
5025 }
5026 }
5030 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5031 is known to be on, this can be converted into a NEG of a shift. */
5037 {
5049 }
5055 /* We can't optimize if either mode is a partial integer
5056 mode as we don't know how many bits are significant
5057 in those modes. */
5073 {
5081 }
5086 }
5091 {
5092 /* For unsigned, we have a choice of a shift followed by an
5093 AND or two shifts. Use two shifts for field sizes where the
5094 constant might be too large. We assume here that we can
5095 always at least get 8-bit constants in an AND insn, which is
5096 true for every current RISC. */
5099 {
5100 unsigned HOST_WIDE_INT mask
5104 gen_rtx_LSHIFTRT
5112 }
5113 else
5114 {
5116 gen_rtx_fmt_ee
5127 }
5128 }
5130 /* See if this is a simple operation with a constant as the second
5131 operand. It might be that this constant is out of range and hence
5132 could be used as a split point. */
5140 /* Finally, see if this is a simple operation with its first operand
5141 not in a register. The operation might require this operand in a
5142 register, so return it as a split point. We can always do this
5143 because if the first operand were another operation, we would have
5144 already found it as a split point. */
5153 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5154 it is better to write this as (not (ior A B)) so we can split it.
5155 Similarly for IOR. */
5157 {
5165 }
5167 /* Many RISC machines have a large set of logical insns. If the
5168 second operand is a NOT, put it first so we will try to split the
5169 other operand first. */
5171 {
5175 }
5180 /* Canonicalization can produce (minus A (mult B C)), where C is a
5181 constant. It may be better to try splitting (plus (mult B -C) A)
5182 instead if this isn't a multiply by a power of two. */
5186 {
5194 mode)),
5197 }
5199 /* Split at a multiply-accumulate instruction. However if this is
5200 the SET_SRC, we likely do not have such an instruction and it's
5201 worthless to try this split. */
5210 }
5212 /* Otherwise, select our actions depending on our rtx class. */
5214 {
5220 /* fall through */
5228 /* fall through */
5230 /* Some machines have (and (shift ...) ...) insns. If X is not
5231 an AND, but XEXP (X, 0) is, use it as our split point. */
5241 /* Otherwise, we don't have a split point. */
5243 }
5244 }
5245 \f
5246 /* Throughout X, replace FROM with TO, and return the result.
5247 The result is TO if X is FROM;
5248 otherwise the result is X, but its contents may have been modified.
5249 If they were modified, a record was made in undobuf so that
5250 undo_all will (among other things) return X to its original state.
5252 If the number of changes necessary is too much to record to undo,
5253 the excess changes are not made, so the result is invalid.
5254 The changes already made can still be undone.
5255 undobuf.num_undo is incremented for such changes, so by testing that
5256 the caller can tell whether the result is valid.
5258 `n_occurrences' is incremented each time FROM is replaced.
5260 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5262 IN_COND is nonzero if we are at the top level of a condition.
5264 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5265 by copying if `n_occurrences' is nonzero. */
5267 static rtx
5269 {
5274 rtx new_rtx;
5276 /* Two expressions are equal if they are identical copies of a shared
5277 RTX or if they are both registers with the same register number
5278 and mode. */
5280 #define COMBINE_RTX_EQUAL_P(X,Y) \
5281 ((X) == (Y) \
5282 || (REG_P (X) && REG_P (Y) \
5283 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5285 /* Do not substitute into clobbers of regs -- this will never result in
5286 valid RTL. */
5291 {
5292 n_occurrences++;
5294 }
5296 /* If X and FROM are the same register but different modes, they
5297 will not have been seen as equal above. However, the log links code
5298 will make a LOG_LINKS entry for that case. If we do nothing, we
5299 will try to rerecognize our original insn and, when it succeeds,
5300 we will delete the feeding insn, which is incorrect.
5302 So force this insn not to match in this (rare) case. */
5307 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5308 of which may contain things that can be combined. */
5312 /* It is possible to have a subexpression appear twice in the insn.
5313 Suppose that FROM is a register that appears within TO.
5314 Then, after that subexpression has been scanned once by `subst',
5315 the second time it is scanned, TO may be found. If we were
5316 to scan TO here, we would find FROM within it and create a
5317 self-referent rtl structure which is completely wrong. */
5321 /* Parallel asm_operands need special attention because all of the
5322 inputs are shared across the arms. Furthermore, unsharing the
5323 rtl results in recognition failures. Failure to handle this case
5324 specially can result in circular rtl.
5326 Solve this by doing a normal pass across the first entry of the
5327 parallel, and only processing the SET_DESTs of the subsequent
5328 entries. Ug. */
5333 {
5336 /* If this substitution failed, this whole thing fails. */
5344 {
5350 {
5353 /* If this substitution failed, this whole thing fails. */
5359 }
5360 }
5361 }
5362 else
5363 {
5367 /* We don't need to process a SET_DEST that is a register, CC0,
5368 or PC, so set up to skip this common case. All other cases
5369 where we want to suppress replacing something inside a
5370 SET_SRC are handled via the IN_DEST operand. */
5377 /* Trying to simplify the operands of a widening MULT is not likely
5378 to create RTL matching a machine insn. */
5390 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5391 constant. */
5396 {
5398 {
5401 {
5403 {
5406 n_occurrences++;
5407 }
5408 else
5409 {
5411 unique_copy);
5413 /* If this substitution failed, this whole thing
5414 fails. */
5418 }
5421 }
5422 }
5424 {
5425 /* If this is a register being set, ignore it. */
5432 ;
5435 {
5436 /* In general, don't install a subreg involving two
5437 modes not tieable. It can worsen register
5438 allocation, and can even make invalid reload
5439 insns, since the reg inside may need to be copied
5440 from in the outside mode, and that may be invalid
5441 if it is an fp reg copied in integer mode.
5443 We allow two exceptions to this: It is valid if
5444 it is inside another SUBREG and the mode of that
5445 SUBREG and the mode of the inside of TO is
5446 tieable and it is valid if X is a SET that copies
5447 FROM to CC0. */
5455 && (!HAVE_cc0
5470 n_occurrences++;
5471 }
5472 else
5473 /* If we are in a SET_DEST, suppress most cases unless we
5474 have gone inside a MEM, in which case we want to
5475 simplify the address. We assume here that things that
5476 are actually part of the destination have their inner
5477 parts in the first expression. This is true for SUBREG,
5478 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5479 things aside from REG and MEM that should appear in a
5480 SET_DEST. */
5482 (((in_dest
5488 unique_copy);
5490 /* If we found that we will have to reject this combination,
5491 indicate that by returning the CLOBBER ourselves, rather than
5492 an expression containing it. This will speed things up as
5493 well as prevent accidents where two CLOBBERs are considered
5494 to be equal, thus producing an incorrect simplification. */
5500 {
5508 }
5511 {
5515 }
5516 else
5518 }
5519 }
5520 }
5522 /* Check if we are loading something from the constant pool via float
5523 extension; in this case we would undo compress_float_constant
5524 optimization and degenerate constant load to an immediate value. */
5528 {
5532 }
5534 /* Try to simplify X. If the simplification changed the code, it is likely
5535 that further simplification will help, so loop, but limit the number
5536 of repetitions that will be performed. */
5539 {
5540 /* If X is sufficiently simple, don't bother trying to do anything
5541 with it. */
5550 /* We no longer know the original mode of operand 0 since we
5551 have changed the form of X) */
5553 }
5556 }
5557 \f
5558 /* If X is a commutative operation whose operands are not in the canonical
5559 order, use substitutions to swap them. */
5561 static void
5563 {
5566 {
5570 }
5571 }
5573 /* Simplify X, a piece of RTL. We just operate on the expression at the
5574 outer level; call `subst' to simplify recursively. Return the new
5575 expression.
5577 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5578 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5579 of a condition. */
5581 static rtx
5584 {
5587 scalar_int_mode int_mode;
5588 rtx temp;
5591 /* If this is a commutative operation, put a constant last and a complex
5592 expression first. We don't need to do this for comparisons here. */
5595 /* Try to fold this expression in case we have constants that weren't
5596 present before. */
5599 {
5607 {
5610 {
5614 }
5617 }
5630 }
5633 {
5638 }
5640 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5641 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5642 things. Check for cases where both arms are testing the same
5643 condition.
5645 Don't do anything if all operands are very simple. */
5658 {
5663 /* If everything is a comparison, what we have is highly unlikely
5664 to be simpler, so don't use it. */
5667 {
5674 /* Simplify the alternative arms; this may collapse the true and
5675 false arms to store-flag values. Be careful to use copy_rtx
5676 here since true_rtx or false_rtx might share RTL with x as a
5677 result of the if_then_else_cond call above. */
5681 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5682 is unlikely to be simpler. */
5685 {
5688 /* Restarting if we generate a store-flag expression will cause
5689 us to loop. Just drop through in this case. */
5691 /* If the result values are STORE_FLAG_VALUE and zero, we can
5692 just make the comparison operation. */
5703 /* Likewise, we can make the negate of a comparison operation
5704 if the result values are - STORE_FLAG_VALUE and zero. */
5712 mode);
5723 mode);
5724 else
5727 mode,
5728 VOIDmode,
5729 cond,
5730 cop1),
5735 }
5736 }
5737 }
5739 /* First see if we can apply the inverse distributive law. */
5742 {
5746 }
5748 /* If CODE is an associative operation not otherwise handled, see if we
5749 can associate some operands. This can win if they are constants or
5750 if they are logically related (i.e. (a & b) & a). */
5756 {
5758 {
5762 rtx inner;
5764 /* Make sure we pass the constant operand if any as the second
5765 one if this is a commutative operation. */
5773 /* For commutative operations, try the other pair if that one
5774 didn't simplify. */
5776 {
5781 }
5785 }
5786 }
5788 /* A little bit of algebraic simplification here. */
5790 {
5792 /* Ensure that our address has any ASHIFTs converted to MULT in case
5793 address-recognizing predicates are called later. */
5802 /* See if this can be moved to simplify_subreg. */
5805 /* Don't call gen_lowpart if the inner mode
5806 is VOIDmode and we cannot simplify it, as SUBREG without
5807 inner mode is invalid. */
5814 {
5815 rtx temp;
5821 /* If op is known to have all lower bits zero, the result is zero. */
5834 }
5836 /* Don't change the mode of the MEM if that would change the meaning
5837 of the address. */
5844 /* Note that we cannot do any narrowing for non-constants since
5845 we might have been counting on using the fact that some bits were
5846 zero. We now do this in the SET. */
5853 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5854 replaced by (lshiftrt X C). This will convert
5855 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5863 /* If X has only a single bit that might be nonzero, say, bit I, convert
5864 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5865 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5866 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5867 or a SUBREG of one since we'd be making the expression more
5868 complex if it was just a register. */
5875 {
5876 rtx temp1 = simplify_shift_const
5882 /* If all we did was surround TEMP with the two shifts, we
5883 haven't improved anything, so don't use it. Otherwise,
5884 we are better off with TEMP1. */
5889 }
5893 /* We can't handle truncation to a partial integer mode here
5894 because we don't know the real bitsize of the partial
5895 integer mode. */
5904 /* We can truncate a constant value and return it. */
5908 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5909 whose value is a comparison can be replaced with a subreg if
5910 STORE_FLAG_VALUE permits. */
5919 /* (const (const X)) can become (const X). Do it this way rather than
5920 returning the inner CONST since CONST can be shared with a
5921 REG_EQUAL note. */
5927 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5928 can add in an offset. find_split_point will split this address up
5929 again if it doesn't match. */
5936 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5937 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5938 bit-field and can be replaced by either a sign_extend or a
5939 sign_extract. The `and' may be a zero_extend and the two
5940 <c>, -<c> constants may be reversed. */
5956 return simplify_shift_const
5963 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5964 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5965 the bitsize of the mode - 1. This allows simplification of
5966 "a = (b & 8) == 0;" */
5973 return simplify_shift_const
5977 const1_rtx),
5981 /* If we are adding two things that have no bits in common, convert
5982 the addition into an IOR. This will often be further simplified,
5983 for example in cases like ((a & 1) + (a & 2)), which can
5984 become a & 3. */
5989 {
5990 /* Try to simplify the expression further. */
5994 /* If we could, great. If not, do not go ahead with the IOR
5995 replacement, since PLUS appears in many special purpose
5996 address arithmetic instructions. */
6004 }
6006 /* Canonicalize x + x into x << 1. */
6015 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6016 (and <foo> (const_int pow2-1)) */
6027 /* If we have (mult (plus A B) C), apply the distributive law and then
6028 the inverse distributive law to see if things simplify. This
6029 occurs mostly in addresses, often when unrolling loops. */
6032 {
6036 }
6038 /* Try simplify a*(b/c) as (a*b)/c. */
6041 {
6047 }
6051 /* If this is a divide by a power of two, treat it as a shift if
6052 its first operand is a shift. */
6072 /* If the first operand is a condition code, we can't do anything
6073 with it. */
6077 {
6085 /* Simplify our comparison, if possible. */
6088 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6089 if only the low-order bit is possibly nonzero in X (such as when
6090 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6091 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6092 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6093 (plus X 1).
6095 Remove any ZERO_EXTRACT we made when thinking this was a
6096 comparison. It may now be simpler to use, e.g., an AND. If a
6097 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6098 the call to make_compound_operation in the SET case.
6100 Don't apply these optimizations if the caller would
6101 prefer a comparison rather than a value.
6102 E.g., for the condition in an IF_THEN_ELSE most targets need
6103 an explicit comparison. */
6106 ;
6124 {
6128 int_mode);
6129 }
6137 {
6141 const1_rtx);
6142 }
6151 {
6154 }
6156 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6157 those above. */
6159 ;
6176 {
6180 int_mode);
6181 }
6190 {
6194 int_mode);
6195 }
6197 /* If X is 0/1, (eq X 0) is X-1. */
6204 {
6207 }
6209 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6210 one bit that might be nonzero, we can convert (ne x 0) to
6211 (ashift x c) where C puts the bit in the sign bit. Remove any
6212 AND with STORE_FLAG_VALUE when we are done, since we are only
6213 going to test the sign bit. */
6221 {
6227 else
6229 }
6231 /* If the code changed, return a whole new comparison.
6232 We also need to avoid using SUBST in cases where
6233 simplify_comparison has widened a comparison with a CONST_INT,
6234 since in that case the wider CONST_INT may fail the sanity
6235 checks in do_SUBST. */
6242 /* Otherwise, keep this operation, but maybe change its operands.
6243 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6246 }
6256 /* If we are processing SET_DEST, we are done. */
6274 /* If this is a shift by a constant amount, simplify it. */
6282 (HOST_WIDE_INT_1U
6290 }
6293 }
6294 \f
6295 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6297 static rtx
6299 {
6306 rtx temp;
6309 rtx reversed;
6312 /* Simplify storing of the truth value. */
6317 /* Also when the truth value has to be reversed. */
6323 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6324 in it is being compared against certain values. Get the true and false
6325 comparisons and see if that says anything about the value of each arm. */
6331 {
6332 HOST_WIDE_INT nzb;
6338 /* If FALSE_CODE is EQ, swap the codes and arms. */
6341 {
6344 }
6346 scalar_int_mode from_mode;
6348 {
6349 /* If we are comparing against zero and the expression being
6350 tested has only a single bit that might be nonzero, that is
6351 its value when it is not equal to zero. Similarly if it is
6352 known to be -1 or 0. */
6356 {
6359 }
6364 {
6367 }
6368 }
6370 /* Now simplify an arm if we know the value of the register in the
6371 branch and it is used in the arm. Be careful due to the potential
6372 of locally-shared RTL. */
6389 }
6391 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6392 reversed, do so to avoid needing two sets of patterns for
6393 subtract-and-branch insns. Similarly if we have a constant in the true
6394 arm, the false arm is the same as the first operand of the comparison, or
6395 the false arm is more complicated than the true arm. */
6408 {
6417 /* It is possible that the conditional has been simplified out. */
6420 }
6422 /* If the two arms are identical, we don't need the comparison. */
6427 /* Convert a == b ? b : a to "a". */
6439 /* Look for cases where we have (abs x) or (neg (abs X)). */
6442 && comparison_p
6449 {
6455 return
6458 mode);
6461 }
6463 /* Look for MIN or MAX. */
6466 && comparison_p
6471 {
6486 }
6488 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6489 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6490 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6491 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6492 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6493 neither 1 or -1, but it isn't worth checking for. */
6496 && comparison_p
6499 {
6515 /* If an identity-zero op is commutative, check whether there
6516 would be a match if we swapped the operands. */
6537 {
6541 }
6554 {
6558 }
6575 {
6579 }
6592 {
6596 }
6599 {
6605 const_true_rtx));
6613 }
6614 }
6616 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6617 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6618 negation of a single bit, we can convert this operation to a shift. We
6619 can actually do this more generally, but it doesn't seem worth it. */
6631 return
6635 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6636 non-zero bit in A is C1. */
6644 {
6650 }
6653 }
6654 \f
6655 /* Simplify X, a SET expression. Return the new expression. */
6657 static rtx
6659 {
6662 machine_mode mode
6666 scalar_int_mode int_mode;
6668 /* (set (pc) (return)) gets written as (return). */
6672 /* Now that we know for sure which bits of SRC we are using, see if we can
6673 simplify the expression for the object knowing that we only need the
6674 low-order bits. */
6677 {
6680 }
6682 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6683 the comparison result and try to simplify it unless we already have used
6684 undobuf.other_insn. */
6692 {
6701 {
6704 {
6707 }
6708 }
6709 else
6717 {
6721 }
6722 else
6723 {
6728 /* Attempt to simplify CC user. */
6730 {
6734 }
6736 /* Convert X into a no-op move. */
6740 }
6742 /* Simplify our comparison, if possible. */
6745 #ifdef SELECT_CC_MODE
6746 /* If this machine has CC modes other than CCmode, check to see if we
6747 need to use a different CC mode here. */
6756 else
6759 /* If the mode changed, we have to change SET_DEST, the mode in the
6760 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6761 a hard register, just build new versions with the proper mode. If it
6762 is a pseudo, we lose unless it is only time we set the pseudo, in
6763 which case we can safely change its mode. */
6765 {
6767 {
6769 rtx new_dest;
6773 else
6774 {
6777 }
6784 }
6785 }
6788 /* If the code changed, we have to build a new comparison in
6789 undobuf.other_insn. */
6791 {
6800 /* If the only change we made was to change an EQ into an NE or
6801 vice versa, OP0 has only one bit that might be nonzero, and OP1
6802 is zero, check if changing the user of the condition code will
6803 produce a valid insn. If it won't, we can keep the original code
6804 in that insn by surrounding our operation with an XOR. */
6811 {
6816 {
6823 }
6824 }
6825 }
6830 /* Don't generate a compare of a CC with 0, just use that CC. */
6832 {
6835 }
6836 /* Otherwise, if we didn't previously have the same COMPARE we
6837 want, create it from scratch. */
6840 {
6843 }
6844 }
6845 else
6846 {
6847 /* Get SET_SRC in a form where we have placed back any
6848 compound expressions. Then do the checks below. */
6851 }
6853 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6854 and X being a REG or (subreg (reg)), we may be able to convert this to
6855 (set (subreg:m2 x) (op)).
6857 We can always do this if M1 is narrower than M2 because that means that
6858 we only care about the low bits of the result.
6860 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6861 perform a narrower operation than requested since the high-order bits will
6862 be undefined. On machine where it is defined, this transformation is safe
6863 as long as M1 and M2 have the same number of words. */
6879 {
6882 dest));
6886 }
6888 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6889 in SRC. */
6893 {
6897 /* Here we make sure that we don't have a sign bit on. */
6900 {
6903 }
6904 }
6906 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6907 would require a paradoxical subreg. Replace the subreg with a
6908 zero_extend to avoid the reload that would otherwise be required. */
6914 {
6919 }
6921 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6922 are comparing an item known to be 0 or -1 against 0, use a logical
6923 operation instead. Check for one of the arms being an IOR of the other
6924 arm with some value. We compute three terms to be IOR'ed together. In
6925 practice, at most two will be nonzero. Then we do the IOR's. */
6933 && (!HAVE_conditional_move
6938 {
6963 int_mode),
6964 false_rtx);
6970 term3));
6973 }
6975 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6976 whole thing fail. */
6981 else
6982 /* Convert this into a field assignment operation, if possible. */
6984 }
6985 \f
6986 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6987 result. */
6989 static rtx
6991 {
6994 scalar_int_mode mode;
6997 {
6999 /* We can call simplify_and_const_int only if we don't lose
7000 any (sign) bits when converting INTVAL (op1) to
7001 "unsigned HOST_WIDE_INT". */
7006 {
7013 }
7015 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7016 apply the distributive law and then the inverse distributive
7017 law to see if things simplify. */
7019 {
7023 }
7025 {
7029 }
7033 /* If we have (ior (and A B) C), apply the distributive law and then
7034 the inverse distributive law to see if things simplify. */
7037 {
7041 }
7044 {
7048 }
7053 }
7056 }
7057 \f
7058 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7059 operations" because they can be replaced with two more basic operations.
7060 ZERO_EXTEND is also considered "compound" because it can be replaced with
7061 an AND operation, which is simpler, though only one operation.
7063 The function expand_compound_operation is called with an rtx expression
7064 and will convert it to the appropriate shifts and AND operations,
7065 simplifying at each stage.
7067 The function make_compound_operation is called to convert an expression
7068 consisting of shifts and ANDs into the equivalent compound expression.
7069 It is the inverse of this function, loosely speaking. */
7071 static rtx
7073 {
7077 rtx tem;
7078 scalar_int_mode inner_mode;
7081 {
7084 /* FALLTHRU */
7086 /* We can't necessarily use a const_int for a multiword mode;
7087 it depends on implicitly extending the value.
7088 Since we don't know the right way to extend it,
7089 we can't tell whether the implicit way is right.
7091 Even for a mode that is no wider than a const_int,
7092 we can't win, because we need to sign extend one of its bits through
7093 the rest of it, and we don't know which bit. */
7097 /* Reject modes that aren't scalar integers because turning vector
7098 or complex modes into shifts causes problems. */
7102 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7103 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7104 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7105 reloaded. If not for that, MEM's would very rarely be safe.
7107 Reject modes bigger than a word, because we might not be able
7108 to reference a two-register group starting with an arbitrary register
7109 (and currently gen_lowpart might crash for a SUBREG). */
7115 /* If the inner object has VOIDmode (the only way this can happen
7116 is if it is an ASM_OPERANDS), we can't do anything since we don't
7117 know how much masking to do. */
7126 /* fall through */
7129 /* If the operand is a CLOBBER, just return it. */
7137 /* Reject modes that aren't scalar integers because turning vector
7138 or complex modes into shifts causes problems. */
7145 /* This should stay within the object being extracted, fail otherwise. */
7156 }
7158 /* We've rejected non-scalar operations by now. */
7161 /* Convert sign extension to zero extension, if we know that the high
7162 bit is not set, as this is easier to optimize. It will be converted
7163 back to cheaper alternative in make_extraction. */
7169 {
7173 /* Make sure this is a profitable operation. */
7180 else
7182 }
7184 /* We can optimize some special cases of ZERO_EXTEND. */
7186 {
7187 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7188 know that the last value didn't have any inappropriate bits
7189 set. */
7197 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7206 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7207 is a comparison and STORE_FLAG_VALUE permits. This is like
7208 the first case, but it works even when MODE is larger
7209 than HOST_WIDE_INT. */
7217 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7226 }
7228 /* If we reach here, we want to return a pair of shifts. The inner
7229 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7230 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7231 logical depending on the value of UNSIGNEDP.
7233 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7234 converted into an AND of a shift.
7236 We must check for the case where the left shift would have a negative
7237 count. This can happen in a case like (x >> 31) & 255 on machines
7238 that can't shift by a constant. On those machines, we would first
7239 combine the shift with the AND to produce a variable-position
7240 extraction. Then the constant of 31 would be substituted in
7241 to produce such a position. */
7245 {
7253 }
7258 pos),
7260 else
7261 /* Any other cases we can't handle. */
7264 /* If we couldn't do this for some reason, return the original
7265 expression. */
7270 }
7271 \f
7272 /* X is a SET which contains an assignment of one object into
7273 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7274 or certain SUBREGS). If possible, convert it into a series of
7275 logical operations.
7277 We half-heartedly support variable positions, but do not at all
7278 support variable lengths. */
7280 static const_rtx
7282 {
7283 rtx inner;
7287 scalar_int_mode compute_mode;
7289 /* Loop until we find something we can't simplify. */
7291 {
7294 {
7298 }
7301 {
7306 /* A constant position should stay within the width of INNER. */
7312 {
7320 /* If position is ADJUST - X, new position is X. */
7322 else
7323 {
7328 pos);
7329 }
7330 }
7331 }
7333 /* A SUBREG between two modes that occupy the same numbers of words
7334 can be done by moving the SUBREG to the source. */
7336 /* We need SUBREGs to compute nonzero_bits properly. */
7337 && nonzero_sign_valid
7342 {
7344 gen_lowpart
7348 }
7349 else
7355 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7357 {
7358 /* Don't do anything for vector or complex integral types. */
7362 /* Try to find an integral mode to pun with. */
7368 }
7370 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7374 /* Don't try to compute in too wide unsupported modes. */
7378 /* Now compute the equivalent expression. Make a copy of INNER
7379 for the SET_DEST in case it is a MEM into which we will substitute;
7380 we don't want shared RTL in that case. */
7382 compute_mode);
7386 compute_mode,
7388 compute_mode),
7389 inner);
7394 mask),
7395 pos);
7400 }
7403 }
7404 \f
7405 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7406 it is an RTX that represents the (variable) starting position; otherwise,
7407 POS is the (constant) starting bit position. Both are counted from the LSB.
7409 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7411 IN_DEST is nonzero if this is a reference in the destination of a SET.
7412 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7413 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7414 be used.
7416 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7417 ZERO_EXTRACT should be built even for bits starting at bit 0.
7419 MODE is the desired mode of the result (if IN_DEST == 0).
7421 The result is an RTX for the extraction or NULL_RTX if the target
7422 can't handle it. */
7424 static rtx
7428 {
7429 /* This mode describes the size of the storage area
7430 to fetch the overall value from. Within that, we
7431 ignore the POS lowest bits, etc. */
7433 machine_mode inner_mode;
7434 scalar_int_mode wanted_inner_mode;
7440 HOST_WIDE_INT orig_pos;
7448 /* If trying or potentionally trying to extract
7449 bits outside of is_mode, don't look through
7450 non-paradoxical SUBREGs. See PR82192. */
7453 {
7454 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7455 consider just the QI as the memory to extract from.
7456 The subreg adds or removes high bits; its mode is
7457 irrelevant to the meaning of this extraction,
7458 since POS and LEN count from the lsb. */
7462 }
7467 {
7468 /* We're extracting the least significant bits of an rtx
7469 (ashift X (const_int C)), where LEN > C. Extract the
7470 least significant (LEN - C) bits of X, giving an rtx
7471 whose mode is MODE, then shift it left C times. */
7477 }
7479 /* If trying or potentionally trying to extract
7480 bits outside of is_mode, don't look through
7481 TRUNCATE. See PR82192. */
7488 /* See if this can be done without an extraction. We never can if the
7489 width of the field is not the same as that of some integer mode. For
7490 registers, we can only avoid the extraction if the position is at the
7491 low-order bit and this is either not in the destination or we have the
7492 appropriate STRICT_LOW_PART operation available.
7494 For MEM, we can avoid an extract if the field starts on an appropriate
7495 boundary and we can change the mode of the memory reference. */
7497 scalar_int_mode tmode;
7506 && (! in_dest
7510 && (pos
7513 /* We can't do this if we are widening INNER_MODE (it
7514 may not be aligned, for one thing). */
7520 {
7521 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7522 field. If the original and current mode are the same, we need not
7523 adjust the offset. Otherwise, we do if bytes big endian.
7525 If INNER is not a MEM, get a piece consisting of just the field
7526 of interest (in this case POS % BITS_PER_WORD must be 0). */
7529 {
7530 HOST_WIDE_INT offset;
7532 /* POS counts from lsb, but make OFFSET count in memory order. */
7535 else
7539 }
7541 {
7543 {
7544 /* We can't call gen_lowpart in a DEST since we
7545 always want a SUBREG (see below) and it would sometimes
7546 return a new hard register. */
7548 {
7549 unsigned int offset
7552 /* Avoid creating invalid subregs, for example when
7553 simplifying (x>>32)&255. */
7558 }
7559 else
7561 }
7562 else
7564 }
7565 else
7567 len >= HOST_BITS_PER_WIDE_INT
7568 ? HOST_WIDE_INT_M1U
7571 /* If this extraction is going into the destination of a SET,
7572 make a STRICT_LOW_PART unless we made a MEM. */
7587 /* If we know that no extraneous bits are set, and that the high
7588 bit is not set, convert the extraction to the cheaper of
7589 sign and zero extension, that are equivalent in these cases. */
7595 {
7599 /* Prefer ZERO_EXTENSION, since it gives more information to
7600 backends. */
7605 }
7607 /* Otherwise, sign- or zero-extend unless we already are in the
7608 proper mode. */
7612 }
7614 /* Unless this is a COMPARE or we have a funny memory reference,
7615 don't do anything with zero-extending field extracts starting at
7616 the low-order bit since they are simple AND operations. */
7621 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7622 if the position is not a constant and the length is not 1. In all
7623 other cases, we would only be going outside our object in cases when
7624 an original shift would have been undefined. */
7633 /* If INNER is not from memory, we want it to have the mode of a register
7634 extraction pattern's structure operand, or word_mode if there is no
7635 such pattern. The same applies to extraction_mode and pos_mode
7636 and their respective operands.
7638 For memory, assume that the desired extraction_mode and pos_mode
7639 are the same as for a register operation, since at present we don't
7640 have named patterns for aligned memory structures. */
7644 {
7648 }
7650 /* Never narrow an object, since that might not be safe. */
7658 else
7659 {
7660 /* Be careful not to go beyond the extracted object and maintain the
7661 natural alignment of the memory. */
7666 }
7671 {
7672 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7673 BITS_BIG_ENDIAN style. If position is constant, compute new
7674 position. Otherwise, build subtraction.
7675 Note that POS is relative to the mode of the original argument.
7676 If it's a MEM we need to recompute POS relative to that.
7677 However, if we're extracting from (or inserting into) a register,
7678 we want to recompute POS relative to wanted_inner_mode. */
7685 else
7686 pos_rtx
7689 pos_rtx);
7690 /* POS may be less than 0 now, but we check for that below.
7691 Note that it can only be less than 0 if !MEM_P (inner). */
7692 }
7694 /* If INNER has a wider mode, and this is a constant extraction, try to
7695 make it smaller and adjust the byte to point to the byte containing
7696 the value. */
7699 && ! pos_rtx
7704 {
7707 /* The computations below will be correct if the machine is big
7708 endian in both bits and bytes or little endian in bits and bytes.
7709 If it is mixed, we must adjust. */
7711 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7712 adjust OFFSET to compensate. */
7717 /* We can now move to the desired byte. */
7728 }
7730 /* If INNER is not memory, get it into the proper mode. If we are changing
7731 its mode, POS must be a constant and smaller than the size of the new
7732 mode. */
7734 {
7735 /* On the LHS, don't create paradoxical subregs implicitely truncating
7736 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7739 wanted_inner_mode))
7751 pos_rtx
7753 ? HOST_WIDE_INT_M1U
7757 }
7759 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7760 have to zero extend. Otherwise, we can just use a SUBREG.
7762 We dealt with constant rtxes earlier, so pos_rtx cannot
7763 have VOIDmode at this point. */
7767 {
7771 /* If we know that no extraneous bits are set, and that the high
7772 bit is not set, convert extraction to cheaper one - either
7773 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7774 cases. */
7782 {
7786 /* Prefer ZERO_EXTENSION, since it gives more information to
7787 backends. */
7791 }
7793 }
7795 /* Make POS_RTX unless we already have it and it is correct. If we don't
7796 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7797 be a CONST_INT. */
7804 /* Make the required operation. See if we can use existing rtx. */
7811 }
7812 \f
7813 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7814 can be commuted with any other operations in X. Return X without
7815 that shift if so. */
7817 static rtx
7819 {
7821 rtx tem;
7824 {
7826 /* This is the shift itself. If it is wide enough, we will return
7827 either the value being shifted if the shift count is equal to
7828 COUNT or a shift for the difference. */
7842 /* If we can safely shift this constant and we find the inner shift,
7843 make a new operation. */
7848 {
7852 }
7857 }
7860 }
7861 \f
7862 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7863 level of the expression and MODE is its mode. IN_CODE is as for
7864 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7865 that should be used when recursing on operands of *X_PTR.
7867 There are two possible actions:
7869 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7870 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7872 - Return a new rtx, which the caller returns directly. */
7874 static rtx
7878 {
7886 rtx tem;
7887 scalar_int_mode inner_mode;
7891 {
7894 }
7896 /* Process depending on the code of this operation. If NEW is set
7897 nonzero, it will be returned. */
7900 {
7902 /* Convert shifts by constants into multiplications if inside
7903 an address. */
7907 {
7913 {
7916 }
7919 }
7928 {
7932 }
7935 {
7939 mode));
7941 }
7942 else
7943 {
7946 }
7956 {
7960 }
7963 {
7967 mode));
7969 }
7970 else
7971 {
7975 }
7978 /* If the second operand is not a constant, we can't do anything
7979 with it. */
7983 /* If the constant is a power of two minus one and the first operand
7984 is a logical right shift, make an extraction. */
7987 {
7991 }
7993 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8000 {
8007 /* If we narrowed the mode when dropping the subreg, then we lose. */
8011 /* If that didn't give anything, see if the AND simplifies on
8012 its own. */
8014 {
8018 }
8019 }
8020 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8026 {
8027 /* Apply the distributive law, and then try to make extractions. */
8034 }
8036 /* If we are have (and (rotate X C) M) and C is larger than the number
8037 of bits in M, this is an extraction. */
8043 {
8049 }
8051 /* On machines without logical shifts, if the operand of the AND is
8052 a logical shift and our mask turns off all the propagated sign
8053 bits, we can replace the logical shift with an arithmetic shift. */
8061 {
8071 next_code),
8073 }
8075 /* If the constant is one less than a power of two, this might be
8076 representable by an extraction even if no shift is present.
8077 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8078 we are in a COMPARE. */
8082 next_code),
8085 /* If we are in a comparison and this is an AND with a power of two,
8086 convert this into the appropriate bit extract. */
8092 next_code),
8095 /* If the one operand is a paradoxical subreg of a register or memory and
8096 the constant (limited to the smaller mode) has only zero bits where
8097 the sub expression has known zero bits, this can be expressed as
8098 a zero_extend. */
8100 {
8101 rtx sub;
8107 {
8111 /* original AND constant with all the known zero bits set */
8114 {
8119 }
8120 }
8121 }
8126 /* If the sign bit is known to be zero, replace this with an
8127 arithmetic shift. */
8132 {
8135 next_code),
8138 }
8140 /* fall through */
8146 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8147 this is a SIGN_EXTRACT. */
8154 {
8161 }
8163 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8164 If so, try to merge the shifts into a SIGN_EXTEND. We could
8165 also do this for some cases of SIGN_EXTRACT, but it doesn't
8166 seem worth the effort; the case checked for occurs on Alpha. */
8177 next_code),
8184 /* Call ourselves recursively on the inner expression. If we are
8185 narrowing the object and it has a different RTL code from
8186 what it originally did, do this SUBREG as a force_to_mode. */
8187 {
8191 /* If the SUBREG is masking of a logical right shift,
8192 make an extraction. */
8199 {
8208 }
8210 /* If in_code is COMPARE, it isn't always safe to pass it through
8211 to the recursive make_compound_operation call. */
8215 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8216 is (const_int 0), rather than
8217 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8218 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8219 for non-equality comparisons against 0 is not equivalent
8220 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8230 simplified
8238 {
8239 rtx newer
8242 /* If we have something other than a SUBREG, we might have
8243 done an expansion, so rerun ourselves. */
8247 /* force_to_mode can expand compounds. If it just re-expanded
8248 the compound, use gen_lowpart to convert to the desired
8249 mode. */
8251 /* Likewise if it re-expanded the compound only partially.
8252 This happens for SUBREG of ZERO_EXTRACT if they extract
8253 the same number of bits. */
8262 }
8266 }
8271 }
8277 }
8279 /* Look at the expression rooted at X. Look for expressions
8280 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8281 Form these expressions.
8283 Return the new rtx, usually just X.
8285 Also, for machines like the VAX that don't have logical shift insns,
8286 try to convert logical to arithmetic shift operations in cases where
8287 they are equivalent. This undoes the canonicalizations to logical
8288 shifts done elsewhere.
8290 We try, as much as possible, to re-use rtl expressions to save memory.
8292 IN_CODE says what kind of expression we are processing. Normally, it is
8293 SET. In a memory address it is MEM. When processing the arguments of
8294 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8295 precisely it is an equality comparison against zero. */
8297 rtx
8299 {
8306 /* Select the code to be used in recursive calls. Once we are inside an
8307 address, we stay there. If we have a comparison, set to COMPARE,
8308 but once inside, go back to our default of SET. */
8315 scalar_int_mode mode;
8317 {
8323 }
8325 /* Now recursively process each operand of this operation. We need to
8326 handle ZERO_EXTEND specially so that we don't lose track of the
8327 inner mode. */
8329 {
8337 }
8342 {
8345 }
8348 {
8351 }
8355 }
8356 \f
8357 /* Given M see if it is a value that would select a field of bits
8358 within an item, but not the entire word. Return -1 if not.
8359 Otherwise, return the starting position of the field, where 0 is the
8360 low-order bit.
8362 *PLEN is set to the length of the field. */
8364 static int
8366 {
8367 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8372 /* Now shift off the low-order zero bits and see if we have a
8373 power of two minus 1. */
8381 }
8382 \f
8383 /* If X refers to a register that equals REG in value, replace these
8384 references with REG. */
8385 static rtx
8387 {
8395 {
8428 /* FALLTHRU */
8432 {
8436 else
8438 }
8440 /* fall through */
8447 {
8450 {
8452 {
8455 }
8457 }
8458 }
8460 {
8463 {
8466 {
8468 {
8471 }
8473 }
8474 }
8475 }
8478 }
8481 }
8483 /* Return X converted to MODE. If the value is already truncated to
8484 MODE we can just return a subreg even though in the general case we
8485 would need an explicit truncation. */
8487 static rtx
8489 {
8494 {
8495 /* Bit-cast X into an integer mode. */
8500 }
8503 }
8505 /* See if X can be simplified knowing that we will only refer to it in
8506 MODE and will only refer to those bits that are nonzero in MASK.
8507 If other bits are being computed or if masking operations are done
8508 that select a superset of the bits in MASK, they can sometimes be
8509 ignored.
8511 Return a possibly simplified expression, but always convert X to
8512 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8514 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8515 are all off in X. This is used when X will be complemented, by either
8516 NOT, NEG, or XOR. */
8518 static rtx
8521 {
8524 machine_mode op_mode;
8527 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8528 code below will do the wrong thing since the mode of such an
8529 expression is VOIDmode.
8531 Also do nothing if X is a CLOBBER; this can happen if X was
8532 the return value from a call to gen_lowpart. */
8536 /* We want to perform the operation in its present mode unless we know
8537 that the operation is valid in MODE, in which case we do the operation
8538 in MODE. */
8543 /* It is not valid to do a right-shift in a narrower mode
8544 than the one it came in with. */
8549 /* Truncate MASK to fit OP_MODE. */
8553 /* Determine what bits of X are guaranteed to be (non)zero. */
8556 /* If none of the bits in X are needed, return a zero. */
8560 /* If X is a CONST_INT, return a new one. Do this here since the
8561 test below will fail. */
8563 {
8566 else
8567 {
8570 }
8571 }
8573 /* If X is narrower than MODE and we want all the bits in X's mode, just
8574 get X in the proper mode. */
8579 /* We can ignore the effect of a SUBREG if it narrows the mode or
8580 if the constant masks to zero all the bits the mode doesn't have. */
8592 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8593 integer too. */
8599 }
8601 /* Subroutine of force_to_mode that handles cases in which both X and
8602 the result are scalar integers. MODE is the mode of the result,
8603 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8604 is preferred for simplified versions of X. The other arguments
8605 are as for force_to_mode. */
8607 static rtx
8611 {
8617 /* When we have an arithmetic operation, or a shift whose count we
8618 do not know, we need to assume that all bits up to the highest-order
8619 bit in MASK will be needed. This is how we form such a mask. */
8622 else
8627 {
8629 /* If X is a (clobber (const_int)), return it since we know we are
8630 generating something that won't match. */
8643 /* Similarly for a truncate. */
8647 /* If this is an AND with a constant, convert it into an AND
8648 whose constant is the AND of that constant with MASK. If it
8649 remains an AND of MASK, delete it since it is redundant. */
8652 {
8657 /* If X is still an AND, see if it is an AND with a mask that
8658 is just some low-order bits. If so, and it is MASK, we don't
8659 need it. */
8665 /* If it remains an AND, try making another AND with the bits
8666 in the mode mask that aren't in MASK turned on. If the
8667 constant in the AND is wide enough, this might make a
8668 cheaper constant. */
8673 {
8674 unsigned HOST_WIDE_INT cval
8676 rtx y;
8683 }
8686 }
8691 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8692 low-order bits (as in an alignment operation) and FOO is already
8693 aligned to that boundary, mask C1 to that boundary as well.
8694 This may eliminate that PLUS and, later, the AND. */
8696 {
8700 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8701 number, sign extend it. */
8714 }
8716 /* fall through */
8719 /* Substituting into the operands of a widening MULT is not likely to
8720 create RTL matching a machine insn. */
8730 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8731 most significant bit in MASK since carries from those bits will
8732 affect the bits we are interested in. */
8737 /* If X is (minus C Y) where C's least set bit is larger than any bit
8738 in the mask, then we may replace with (neg Y). */
8741 {
8744 }
8746 /* Similarly, if C contains every bit in the fuller_mask, then we may
8747 replace with (not Y). */
8750 {
8753 }
8760 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8761 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8762 operation which may be a bitfield extraction. Ensure that the
8763 constant we form is not wider than the mode of X. */
8775 {
8778 xmode);
8784 }
8786 binop:
8787 /* For most binary operations, just propagate into the operation and
8788 change the mode if we have an operation of that mode. */
8793 /* If we ended up truncating both operands, truncate the result of the
8794 operation instead. */
8797 {
8800 }
8806 {
8809 }
8813 /* For left shifts, do the same, but just for the first operand.
8814 However, we cannot do anything with shifts where we cannot
8815 guarantee that the counts are smaller than the size of the mode
8816 because such a count will have a different meaning in a
8817 wider mode. */
8827 /* If the shift count is a constant and we can do arithmetic in
8828 the mode of the shift, refine which bits we need. Otherwise, use the
8829 conservative form of the mask. */
8835 else
8843 {
8846 }
8850 /* Here we can only do something if the shift count is a constant,
8851 this shift constant is valid for the host, and we can do arithmetic
8852 in OP_MODE. */
8858 {
8862 /* Select the mask of the bits we need for the shift operand. */
8865 /* We can only change the mode of the shift if we can do arithmetic
8866 in the mode of the shift and INNER_MASK is no wider than the
8867 width of X's mode. */
8874 {
8877 }
8878 }
8880 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8881 shift and AND produces only copies of the sign bit (C2 is one less
8882 than a power of two), we can do this with just a shift. */
8886 /* The shift puts one of the sign bit copies in the least significant
8887 bit. */
8892 /* Number of bits left after the shift must be more than the mask
8893 needs. */
8896 /* Must be more sign bit copies than the mask needs. */
8906 /* If we are just looking for the sign bit, we don't need this shift at
8907 all, even if it has a variable count. */
8911 /* If this is a shift by a constant, get a mask that contains those bits
8912 that are not copies of the sign bit. We then have two cases: If
8913 MASK only includes those bits, this can be a logical shift, which may
8914 allow simplifications. If MASK is a single-bit field not within
8915 those bits, we are requesting a copy of the sign bit and hence can
8916 shift the sign bit to the appropriate location. */
8920 {
8924 /* If the considered data is wider than HOST_WIDE_INT, we can't
8925 represent a mask for all its bits in a single scalar.
8926 But we only care about the lower bits, so calculate these. */
8929 {
8932 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8933 is the number of bits a full-width mask would have set.
8934 We need only shift if these are fewer than nonzero can
8935 hold. If not, we must keep all bits set in nonzero. */
8940 + HOST_BITS_PER_WIDE_INT
8942 }
8943 else
8944 {
8947 }
8950 {
8955 }
8958 {
8959 x = simplify_shift_const
8965 }
8966 }
8968 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8969 even if the shift count isn't a constant. */
8973 shiftrt:
8975 /* If this is a zero- or sign-extension operation that just affects bits
8976 we don't care about, remove it. Be sure the call above returned
8977 something that is still a shift. */
8987 next_select);
8993 /* If the shift count is constant and we can do computations
8994 in the mode of X, compute where the bits we care about are.
8995 Otherwise, we can't do anything. Don't change the mode of
8996 the shift or propagate MODE into the shift, though. */
8999 {
9008 }
9012 /* If we just want the low-order bit, the NEG isn't needed since it
9013 won't change the low-order bit. */
9017 /* We need any bits less significant than the most significant bit in
9018 MASK since carries from those bits will affect the bits we are
9019 interested in. */
9024 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9025 same as the XOR case above. Ensure that the constant we form is not
9026 wider than the mode of X. */
9034 {
9041 }
9043 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9044 use the full mask inside the NOT. */
9047 unop:
9050 next_select));
9052 {
9055 }
9059 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9060 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9061 which is equal to STORE_FLAG_VALUE. */
9073 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9074 written in a narrower mode. We play it safe and do not do so. */
9090 }
9092 /* Ensure we return a value of the proper mode. */
9094 }
9095 \f
9096 /* Return nonzero if X is an expression that has one of two values depending on
9097 whether some other value is zero or nonzero. In that case, we return the
9098 value that is being tested, *PTRUE is set to the value if the rtx being
9099 returned has a nonzero value, and *PFALSE is set to the other alternative.
9101 If we return zero, we set *PTRUE and *PFALSE to X. */
9103 static rtx
9105 {
9110 scalar_int_mode int_mode;
9112 /* If we are comparing a value against zero, we are done. */
9115 {
9119 }
9121 /* If this is a unary operation whose operand has one of two values, apply
9122 our opcode to compute those values. */
9125 {
9130 }
9132 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9133 make can't possibly match and would suppress other optimizations. */
9135 ;
9137 /* If this is a binary operation, see if either side has only one of two
9138 values. If either one does or if both do and they are conditional on
9139 the same value, compute the new true and false values. */
9141 {
9149 {
9150 /* Try to enable a simplification by undoing work done by
9151 if_then_else_cond if it converted a REG into something more
9152 complex. */
9154 {
9157 }
9158 else
9159 {
9162 }
9163 }
9167 {
9168 /* If if_then_else_cond returned zero, then true/false are the
9169 same rtl. We must copy one of them to prevent invalid rtl
9170 sharing. */
9177 {
9182 }
9183 else
9184 {
9187 }
9190 }
9192 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9193 operands is zero when the other is nonzero, and vice-versa,
9194 and STORE_FLAG_VALUE is 1 or -1. */
9200 {
9217 {
9224 const_true_rtx);
9226 }
9227 }
9229 /* Similarly for MULT, AND and UMIN, except that for these the result
9230 is always zero. */
9234 {
9248 {
9251 }
9252 }
9253 }
9256 {
9257 /* If we have IF_THEN_ELSE already, extract the condition and
9258 canonicalize it if it is NE or EQ. */
9264 {
9267 }
9268 else
9270 }
9272 /* If X is a SUBREG, we can narrow both the true and false values
9273 if the inner expression, if there is a condition. */
9277 {
9283 {
9287 }
9288 }
9290 /* If X is a constant, this isn't special and will cause confusions
9291 if we treat it as such. Likewise if it is equivalent to a constant. */
9294 ;
9296 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9297 will be least confusing to the rest of the compiler. */
9299 {
9302 }
9304 /* If X is known to be either 0 or -1, those are the true and
9305 false values when testing X. */
9310 {
9313 }
9315 /* Likewise for 0 or a single bit. */
9318 {
9321 }
9323 /* Otherwise fail; show no condition with true and false values the same. */
9326 }
9327 \f
9328 /* Return the value of expression X given the fact that condition COND
9329 is known to be true when applied to REG as its first operand and VAL
9330 as its second. X is known to not be shared and so can be modified in
9331 place.
9333 We only handle the simplest cases, and specifically those cases that
9334 arise with IF_THEN_ELSE expressions. */
9336 static rtx
9338 {
9346 /* If either operand of the condition is a floating point value,
9347 then we have to avoid collapsing an EQ comparison. */
9357 /* If X is (abs REG) and we know something about REG's relationship
9358 with zero, we may be able to simplify this. */
9362 {
9371 }
9373 /* The only other cases we handle are MIN, MAX, and comparisons if the
9374 operands are the same as REG and VAL. */
9377 {
9379 {
9382 }
9385 {
9387 {
9395 else
9397 }
9400 {
9403 /* Do not reverse the condition when it is NE or EQ.
9404 This is because we cannot conclude anything about
9405 the value of 'SMAX (x, y)' when x is not equal to y,
9406 but we can when x equals y. */
9412 {
9423 }
9424 }
9425 }
9426 }
9428 {
9433 {
9434 /* We must simplify subreg here, before we lose track of the
9435 original inner_mode. */
9440 else
9442 }
9445 }
9446 /* We don't have to handle SIGN_EXTEND here, because even in the
9447 case of replacing something with a modeless CONST_INT, a
9448 CONST_INT is already (supposed to be) a valid sign extension for
9449 its narrower mode, which implies it's already properly
9450 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9451 story is different. */
9453 {
9458 {
9459 /* We must simplify the zero_extend here, before we lose
9460 track of the original inner_mode. */
9465 else
9467 }
9470 }
9474 {
9481 }
9484 }
9485 \f
9486 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9487 assignment as a field assignment. */
9489 static int
9491 {
9493 {
9498 /* For big endian, adjust the memory offset. */
9503 else
9505 }
9513 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9514 Note that all SUBREGs of MEM are paradoxical; otherwise they
9515 would have been rewritten. */
9528 /* We used to see if get_last_value of X and Y were the same but that's
9529 not correct. In one direction, we'll cause the assignment to have
9530 the wrong destination and in the case, we'll import a register into this
9531 insn that might have already have been dead. So fail if none of the
9532 above cases are true. */
9534 }
9535 \f
9536 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9537 Return that assignment if so.
9539 We only handle the most common cases. */
9541 static rtx
9543 {
9546 rtx assign;
9548 HOST_WIDE_INT c1;
9549 HOST_WIDE_INT pos;
9551 rtx other;
9553 /* All the rules in this function are specific to scalar integers. */
9554 scalar_int_mode mode;
9558 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9559 a clear of a one-bit field. We will have changed it to
9560 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9561 for a SUBREG. */
9567 {
9573 }
9582 {
9589 }
9591 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9592 one-bit field. */
9596 {
9602 }
9604 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9605 SRC is an AND with all bits of that field set, then we can discard
9606 the AND. */
9611 {
9618 else
9621 /* Complete overlap. We can remove the source AND. */
9625 /* Partial overlap. We can reduce the source AND. */
9627 {
9631 }
9632 }
9634 /* The other case we handle is assignments into a constant-position
9635 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9636 a mask that has all one bits except for a group of zero bits and
9637 OTHER is known to have zeros where C1 has ones, this is such an
9638 assignment. Compute the position and length from C1. Shift OTHER
9639 to the appropriate position, force it to the required mode, and
9640 make the extraction. Check for the AND in both operands. */
9642 /* One or more SUBREGs might obscure the constant-position field
9643 assignment. The first one we are likely to encounter is an outer
9644 narrowing SUBREG, which we can just strip for the purposes of
9645 identifying the constant-field assignment. */
9662 /* The second SUBREG that might get in the way is a paradoxical
9663 SUBREG around the first operand of the AND. We want to
9664 pretend the operand is as wide as the destination here. We
9665 do this by adjusting the MEM to wider mode for the sole
9666 purpose of the call to rtx_equal_for_field_assignment_p. Also
9667 note this trick only works for MEMs. */
9679 /* The second SUBREG that might get in the way is a paradoxical
9680 SUBREG around the first operand of the AND. We want to
9681 pretend the operand is as wide as the destination here. We
9682 do this by adjusting the MEM to wider mode for the sole
9683 purpose of the call to rtx_equal_for_field_assignment_p. Also
9684 note this trick only works for MEMs. */
9692 else
9706 /* The mode to use for the source is the mode of the assignment, or of
9707 what is inside a possible STRICT_LOW_PART. */
9711 /* Shift OTHER right POS places and make it the source, restricting it
9712 to the proper length and mode. */
9716 dest);
9718 len >= HOST_BITS_PER_WIDE_INT
9719 ? HOST_WIDE_INT_M1U
9723 /* If SRC is masked by an AND that does not make a difference in
9724 the value being stored, strip it. */
9735 }
9736 \f
9737 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9738 if so. */
9740 static rtx
9742 {
9746 rtx tem;
9748 /* Distributivity is not true for floating point as it can change the
9749 value. So we don't do it unless -funsafe-math-optimizations. */
9754 /* The outer operation can only be one of the following: */
9762 /* If either operand is a primitive we can't do anything, so get out
9763 fast. */
9773 /* See if the inner and outer operations distribute. */
9775 {
9780 /* These all distribute except over PLUS. */
9791 /* This is also a multiply, so it distributes over everything. */
9794 /* This used to handle SUBREG, but this turned out to be counter-
9795 productive, since (subreg (op ...)) usually is not handled by
9796 insn patterns, and this "optimization" therefore transformed
9797 recognizable patterns into unrecognizable ones. Therefore the
9798 SUBREG case was removed from here.
9800 It is possible that distributing SUBREG over arithmetic operations
9801 leads to an intermediate result than can then be optimized further,
9802 e.g. by moving the outer SUBREG to the other side of a SET as done
9803 in simplify_set. This seems to have been the original intent of
9804 handling SUBREGs here.
9806 However, with current GCC this does not appear to actually happen,
9807 at least on major platforms. If some case is found where removing
9808 the SUBREG case here prevents follow-on optimizations, distributing
9809 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9813 }
9815 /* Set LHS and RHS to the inner operands (A and B in the example
9816 above) and set OTHER to the common operand (C in the example).
9817 There is only one way to do this unless the inner operation is
9818 commutative. */
9830 else
9833 /* Form the new inner operation, seeing if it simplifies first. */
9836 /* There is one exception to the general way of distributing:
9837 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9839 {
9842 }
9844 /* We may be able to continuing distributing the result, so call
9845 ourselves recursively on the inner operation before forming the
9846 outer operation, which we return. */
9849 }
9851 /* See if X is of the form (* (+ A B) C), and if so convert to
9852 (+ (* A C) (* B C)) and try to simplify.
9854 Most of the time, this results in no change. However, if some of
9855 the operands are the same or inverses of each other, simplifications
9856 will result.
9858 For example, (and (ior A B) (not B)) can occur as the result of
9859 expanding a bit field assignment. When we apply the distributive
9860 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9861 which then simplifies to (and (A (not B))).
9863 Note that no checks happen on the validity of applying the inverse
9864 distributive law. This is pointless since we can do it in the
9865 few places where this routine is called.
9867 N is the index of the term that is decomposed (the arithmetic operation,
9868 i.e. (+ A B) in the first example above). !N is the index of the term that
9869 is distributed, i.e. of C in the first example above. */
9870 static rtx
9872 {
9873 machine_mode mode;
9877 /* Distributivity is not true for floating point as it can change the
9878 value. So we don't do it unless -funsafe-math-optimizations. */
9895 /* Special case (and (xor B C) (not A)), which is equivalent to
9896 (xor (ior A B) (ior A C)) */
9898 {
9901 }
9904 {
9905 /* Distribute the second term. */
9908 }
9909 else
9910 {
9911 /* Distribute the first term. */
9914 }
9924 }
9925 \f
9926 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9927 in MODE. Return an equivalent form, if different from (and VAROP
9928 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9930 static rtx
9933 {
9936 rtx orig_varop;
9944 /* Simplify VAROP knowing that we will be only looking at some of the
9945 bits in it.
9947 Note by passing in CONSTOP, we guarantee that the bits not set in
9948 CONSTOP are not significant and will never be examined. We must
9949 ensure that is the case by explicitly masking out those bits
9950 before returning. */
9953 /* If VAROP is a CLOBBER, we will fail so return it. */
9957 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9958 to VAROP and return the new constant. */
9962 /* See what bits may be nonzero in VAROP. Unlike the general case of
9963 a call to nonzero_bits, here we don't care about bits outside
9964 MODE. */
9968 /* Turn off all bits in the constant that are known to already be zero.
9969 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9970 which is tested below. */
9974 /* If we don't have any bits left, return zero. */
9978 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9979 a power of two, we can replace this with an ASHIFT. */
9984 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9985 or XOR, then try to apply the distributive law. This may eliminate
9986 operations if either branch can be simplified because of the AND.
9987 It may also make some cases more complex, but those cases probably
9988 won't match a pattern either with or without this. */
9991 {
9993 return
9994 gen_lowpart
9996 apply_distributive_law
10000 constop),
10003 constop))));
10004 }
10006 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10007 the AND and see if one of the operands simplifies to zero. If so, we
10008 may eliminate it. */
10012 {
10021 }
10023 /* Make a SUBREG if necessary. If we can't make it, fail. */
10028 /* If we are only masking insignificant bits, return VAROP. */
10035 /* Otherwise, return an AND. */
10037 }
10040 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10041 in MODE.
10043 Return an equivalent form, if different from X. Otherwise, return X. If
10044 X is zero, we are to always construct the equivalent form. */
10046 static rtx
10049 {
10060 }
10061 \f
10062 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10063 We don't care about bits outside of those defined in MODE.
10065 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10066 a shift, AND, or zero_extract, we can do better. */
10068 static rtx
10070 scalar_int_mode mode,
10072 {
10073 rtx tem;
10076 /* If X is a register whose nonzero bits value is current, use it.
10077 Otherwise, if X is a register whose value we can find, use that
10078 value. Otherwise, use the previously-computed global nonzero bits
10079 for this register. */
10093 && !REGNO_REG_SET_P
10096 {
10097 /* Note that, even if the precision of last_set_mode is lower than that
10098 of mode, record_value_for_reg invoked nonzero_bits on the register
10099 with nonzero_bits_mode (because last_set_mode is necessarily integral
10100 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10101 are all valid, hence in mode too since nonzero_bits_mode is defined
10102 to the largest HWI_COMPUTABLE_MODE_P mode. */
10105 }
10109 {
10114 }
10117 {
10121 /* We don't know anything about the upper bits. */
10125 }
10128 }
10130 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10131 end of X that are known to be equal to the sign bit. X will be used
10132 in mode MODE; the returned value will always be between 1 and the
10133 number of bits in MODE. */
10135 static rtx
10137 scalar_int_mode mode,
10139 {
10140 rtx tem;
10153 && !REGNO_REG_SET_P
10156 {
10159 }
10170 }
10171 \f
10172 /* Return the number of "extended" bits there are in X, when interpreted
10173 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10174 unsigned quantities, this is the number of high-order zero bits.
10175 For signed quantities, this is the number of copies of the sign bit
10176 minus 1. In both case, this function returns the number of "spare"
10177 bits. For example, if two quantities for which this function returns
10178 at least 1 are added, the addition is known not to overflow.
10180 This function will always return 0 unless called during combine, which
10181 implies that it must be called from a define_split. */
10183 unsigned int
10185 {
10189 scalar_int_mode int_mode;
10197 }
10199 /* This function is called from `simplify_shift_const' to merge two
10200 outer operations. Specifically, we have already found that we need
10201 to perform operation *POP0 with constant *PCONST0 at the outermost
10202 position. We would now like to also perform OP1 with constant CONST1
10203 (with *POP0 being done last).
10205 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10206 the resulting operation. *PCOMP_P is set to 1 if we would need to
10207 complement the innermost operand, otherwise it is unchanged.
10209 MODE is the mode in which the operation will be done. No bits outside
10210 the width of this mode matter. It is assumed that the width of this mode
10211 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10213 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10214 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10215 result is simply *PCONST0.
10217 If the resulting operation cannot be expressed as one operation, we
10218 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10220 static int
10221 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10222 {
10229 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10233 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10234 if OP0 is SET. */
10243 {
10245 {
10263 }
10264 }
10266 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10270 /* If the two constants aren't the same, we can't do anything. The
10271 remaining six cases can all be done. */
10275 else
10277 {
10280 /* (a & b) | b == b */
10283 /* (a ^ b) | b == a | b */
10284 {;}
10289 /* (a & b) ^ b == (~a) & b */
10292 /* (a | b) ^ b == a & ~b */
10298 /* (a | b) & b == b */
10301 /* (a ^ b) & b) == (~a) & b */
10306 }
10308 /* Check for NO-OP cases. */
10321 /* ??? Slightly redundant with the above mask, but not entirely.
10322 Moving this above means we'd have to sign-extend the mode mask
10323 for the final test. */
10328 }
10329 \f
10330 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10331 the shift in. The original shift operation CODE is performed on OP in
10332 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10333 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10334 result of the shift is subject to operation OUTER_CODE with operand
10335 OUTER_CONST. */
10337 static scalar_int_mode
10341 {
10344 /* In general we can't perform in wider mode for right shift and rotate. */
10346 {
10348 /* We can still widen if the bits brought in from the left are identical
10349 to the sign bit of ORIG_MODE. */
10357 /* Similarly here but with zero bits. */
10362 /* We can also widen if the bits brought in will be masked off. This
10363 operation is performed in ORIG_MODE. */
10365 {
10371 }
10372 /* fall through */
10382 }
10383 }
10385 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10386 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10387 if we cannot simplify it. Otherwise, return a simplified value.
10389 The shift is normally computed in the widest mode we find in VAROP, as
10390 long as it isn't a different number of words than RESULT_MODE. Exceptions
10391 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10393 static rtx
10396 {
10401 machine_mode shift_mode;
10403 unsigned int mode_words
10405 /* We form (outer_op (code varop count) (outer_const)). */
10411 /* Make sure and truncate the "natural" shift on the way in. We don't
10412 want to do this inside the loop as it makes it more difficult to
10413 combine shifts. */
10417 /* If we were given an invalid count, don't do anything except exactly
10418 what was requested. */
10425 /* Unless one of the branches of the `if' in this loop does a `continue',
10426 we will `break' the loop after the `if'. */
10429 {
10430 /* If we have an operand of (clobber (const_int 0)), fail. */
10434 /* Convert ROTATERT to ROTATE. */
10436 {
10440 }
10444 {
10445 /* We only change the modes of scalar shifts. */
10451 }
10453 scalar_int_mode shift_unit_mode
10456 /* Handle cases where the count is greater than the size of the mode
10457 minus 1. For ASHIFT, use the size minus one as the count (this can
10458 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10459 take the count modulo the size. For other shifts, the result is
10460 zero.
10462 Since these shifts are being produced by the compiler by combining
10463 multiple operations, each of which are defined, we know what the
10464 result is supposed to be. */
10467 {
10472 else
10473 {
10474 /* We can't simply return zero because there may be an
10475 outer op. */
10479 }
10480 }
10482 /* If we discovered we had to complement VAROP, leave. Making a NOT
10483 here would cause an infinite loop. */
10488 {
10489 /* An arithmetic right shift of a quantity known to be -1 or 0
10490 is a no-op. */
10494 {
10497 }
10499 /* If we are doing an arithmetic right shift and discarding all but
10500 the sign bit copies, this is equivalent to doing a shift by the
10501 bitsize minus one. Convert it into that shift because it will
10502 often allow other simplifications. */
10509 /* We simplify the tests below and elsewhere by converting
10510 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10511 `make_compound_operation' will convert it to an ASHIFTRT for
10512 those machines (such as VAX) that don't have an LSHIFTRT. */
10517 shift_unit_mode)))
10529 }
10532 {
10539 {
10542 }
10546 /* The following rules apply only to scalars. */
10551 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10552 minus the width of a smaller mode, we can do this with a
10553 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10560 {
10569 }
10573 /* The following rules apply only to scalars. */
10579 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10580 the same number of words as what we've seen so far. Then store
10581 the widest mode in MODE. */
10587 == mode_words
10589 {
10594 }
10598 /* Some machines use MULT instead of ASHIFT because MULT
10599 is cheaper. But it is still better on those machines to
10600 merge two shifts into one. */
10603 {
10604 varop
10610 }
10614 /* Similar, for when divides are cheaper. */
10617 {
10618 varop
10624 }
10628 /* If we are extracting just the sign bit of an arithmetic
10629 right shift, that shift is not needed. However, the sign
10630 bit of a wider mode may be different from what would be
10631 interpreted as the sign bit in a narrower mode, so, if
10632 the result is narrower, don't discard the shift. */
10637 {
10640 }
10642 /* fall through */
10647 /* The following rules apply only to scalars. */
10654 /* Here we have two nested shifts. The result is usually the
10655 AND of a new shift with a mask. We compute the result below. */
10661 {
10665 rtx mask_rtx;
10667 /* We have one common special case. We can't do any merging if
10668 the inner code is an ASHIFTRT of a smaller mode. However, if
10669 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10670 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10671 we can convert it to
10672 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10673 This simplifies certain SIGN_EXTEND operations. */
10677 {
10678 /* C3 has the low-order C1 bits zero. */
10690 }
10692 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10693 than C1 high-order bits equal to the sign bit, we can convert
10694 this to either an ASHIFT or an ASHIFTRT depending on the
10695 two counts.
10697 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10703 {
10707 {
10710 }
10713 }
10715 /* There are some cases we can't do. If CODE is ASHIFTRT,
10716 we can only do this if FIRST_CODE is also ASHIFTRT.
10718 We can't do the case when CODE is ROTATE and FIRST_CODE is
10719 ASHIFTRT.
10721 If the mode of this shift is not the mode of the outer shift,
10722 we can't do this if either shift is a right shift or ROTATE.
10724 Finally, we can't do any of these if the mode is too wide
10725 unless the codes are the same.
10727 Handle the case where the shift codes are the same
10728 first. */
10731 {
10740 }
10751 /* To compute the mask to apply after the shift, shift the
10752 nonzero bits of the inner shift the same way the
10753 outer shift will. */
10756 int_result_mode);
10758 mask_rtx
10762 /* Give up if we can't compute an outer operation to use. */
10770 /* If the shifts are in the same direction, we add the
10771 counts. Otherwise, we subtract them. */
10775 else
10778 /* If COUNT is positive, the new shift is usually CODE,
10779 except for the two exceptions below, in which case it is
10780 FIRST_CODE. If the count is negative, FIRST_CODE should
10781 always be used */
10791 }
10793 /* If we have (A << B << C) for any shift, we can convert this to
10794 (A << C << B). This wins if A is a constant. Only try this if
10795 B is not a constant. */
10800 {
10801 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10802 sure the result will be masked. See PR70222. */
10810 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10811 up outer sign extension (often left and right shift) is
10812 hardly more efficient than the original. See PR70429. */
10822 }
10826 /* The following rules apply only to scalars. */
10830 /* Make this fit the case below. */
10837 /* The following rules apply only to scalars. */
10843 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10844 with C the size of VAROP - 1 and the shift is logical if
10845 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10846 we have an (le X 0) operation. If we have an arithmetic shift
10847 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10848 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10856 {
10859 const0_rtx);
10865 }
10867 /* If we have (shift (logical)), move the logical to the outside
10868 to allow it to possibly combine with another logical and the
10869 shift to combine with another shift. This also canonicalizes to
10870 what a ZERO_EXTRACT looks like. Also, some machines have
10871 (and (shift)) insns. */
10874 /* We can't do this if we have (ashiftrt (xor)) and the
10875 constant has its sign bit set in shift_unit_mode with
10876 shift_unit_mode wider than result_mode. */
10880 shift_unit_mode))
10889 {
10892 }
10894 /* If we can't do that, try to simplify the shift in each arm of the
10895 logical expression, make a new logical expression, and apply
10896 the inverse distributive law. This also can't be done for
10897 (ashiftrt (xor)) where we've widened the shift and the constant
10898 changes the sign bit. */
10903 shift_unit_mode)))
10904 {
10916 }
10920 /* The following rules apply only to scalars. */
10925 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10926 says that the sign bit can be tested, FOO has mode MODE, C is
10927 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10928 that may be nonzero. */
10938 {
10942 }
10946 /* The following rules apply only to scalars. */
10951 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10952 than the number of bits in the mode is equivalent to A. */
10956 {
10960 }
10962 /* NEG commutes with ASHIFT since it is multiplication. Move the
10963 NEG outside to allow shifts to combine. */
10967 {
10970 }
10974 /* The following rules apply only to scalars. */
10979 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10980 is one less than the number of bits in the mode is
10981 equivalent to (xor A 1). */
10988 {
10992 }
10994 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10995 that might be nonzero in BAR are those being shifted out and those
10996 bits are known zero in FOO, we can replace the PLUS with FOO.
10997 Similarly in the other operand order. This code occurs when
10998 we are computing the size of a variable-size array. */
11005 {
11008 }
11016 {
11019 }
11021 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11032 {
11035 }
11037 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11038 signbit', and attempt to change the PLUS to an XOR and move it to
11039 the outer operation as is done above in the AND/IOR/XOR case
11040 leg for shift(logical). See details in logical handling above
11041 for reasoning in doing so. */
11053 {
11056 }
11061 /* The following rules apply only to scalars. */
11066 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11067 with C the size of VAROP - 1 and the shift is logical if
11068 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11069 we have a (gt X 0) operation. If the shift is arithmetic with
11070 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11071 we have a (neg (gt X 0)) operation. */
11080 {
11083 const0_rtx);
11089 }
11093 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11094 if the truncate does not affect the value. */
11101 {
11104 varop_inner
11107 GEN_INT
11112 }
11117 }
11120 }
11124 {
11125 /* We only change the modes of scalar shifts. */
11130 }
11132 /* We have now finished analyzing the shift. The result should be
11133 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11134 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11135 to the result of the shift. OUTER_CONST is the relevant constant,
11136 but we must turn off all bits turned off in the shift. */
11144 /* Make a SUBREG if necessary. If we can't make it, fail. */
11149 /* If we have an outer operation and we just made a shift, it is
11150 possible that we could have simplified the shift were it not
11151 for the outer operation. So try to do the simplification
11152 recursively. */
11156 else
11162 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11163 turn off all the bits that the shift would have turned off. */
11165 /* We only change the modes of scalar shifts. */
11169 /* Do the remainder of the processing in RESULT_MODE. */
11172 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11173 operation. */
11178 {
11188 {
11189 /* This means that we have determined that the result is
11190 equivalent to a constant. This should be rare. */
11193 }
11196 else
11199 }
11202 }
11204 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11205 The result of the shift is RESULT_MODE. If we cannot simplify it,
11206 return X or, if it is NULL, synthesize the expression with
11207 simplify_gen_binary. Otherwise, return a simplified value.
11209 The shift is normally computed in the widest mode we find in VAROP, as
11210 long as it isn't a different number of words than RESULT_MODE. Exceptions
11211 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11213 static rtx
11216 {
11226 }
11228 \f
11229 /* A subroutine of recog_for_combine. See there for arguments and
11230 return value. */
11232 static int
11234 {
11236 rtx pat_without_clobbers;
11244 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11245 we use to indicate that something didn't match. If we find such a
11246 thing, force rejection. */
11260 {
11263 else
11266 }
11268 /* If it isn't, there is the possibility that we previously had an insn
11269 that clobbered some register as a side effect, but the combined
11270 insn doesn't need to do that. So try once more without the clobbers
11271 unless this represents an ASM insn. */
11275 {
11280 {
11283 pos++;
11284 }
11294 {
11297 else
11300 }
11301 }
11308 /* Recognize all noop sets, these will be killed by followup pass. */
11312 /* If we had any clobbers to add, make a new pattern than contains
11313 them. Then check to make sure that all of them are dead. */
11315 {
11325 else
11332 {
11337 {
11341 }
11342 }
11344 }
11348 {
11356 /* Allow targets to reject combined insn. */
11358 {
11361 dump_file);
11363 /* Callers expect recog_for_combine to strip
11364 clobbers from the pattern on failure. */
11369 }
11374 }
11380 }
11382 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11383 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11384 Return whether anything was so changed. */
11386 static bool
11388 {
11394 {
11406 {
11415 else
11419 }
11425 {
11431 }
11436 {
11440 }
11441 else
11447 {
11450 }
11454 }
11461 scalar_int_mode mode;
11467 {
11481 else
11489 }
11492 }
11494 /* Like recog, but we receive the address of a pointer to a new pattern.
11495 We try to match the rtx that the pointer points to.
11496 If that fails, we may try to modify or replace the pattern,
11497 storing the replacement into the same pointer object.
11499 Modifications include deletion or addition of CLOBBERs. If the
11500 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11501 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11502 (and undo if that fails).
11504 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11505 the CLOBBERs are placed.
11507 The value is the final insn code from the pattern ultimately matched,
11508 or -1. */
11510 static int
11512 {
11524 {
11527 {
11531 }
11532 }
11535 {
11540 }
11543 }
11544 \f
11545 /* Like gen_lowpart_general but for use by combine. In combine it
11546 is not possible to create any new pseudoregs. However, it is
11547 safe to create invalid memory addresses, because combine will
11548 try to recognize them and all they will do is make the combine
11549 attempt fail.
11551 If for some reason this cannot do its job, an rtx
11552 (clobber (const_int 0)) is returned.
11553 An insn containing that will not be recognized. */
11555 static rtx
11557 {
11561 rtx result;
11566 /* We can only support MODE being wider than a word if X is a
11567 constant integer or has a mode the same size. */
11572 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11573 won't know what to do. So we will strip off the SUBREG here and
11574 process normally. */
11576 {
11579 /* For use in case we fall down into the address adjustments
11580 further below, we need to adjust the known mode and size of
11581 x; imode and isize, since we just adjusted x. */
11588 }
11596 {
11599 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11600 address. */
11605 /* If we want to refer to something bigger than the original memref,
11606 generate a paradoxical subreg instead. That will force a reload
11607 of the original memref X. */
11614 /* Adjust the address so that the address-after-the-data is
11615 unchanged. */
11620 }
11622 /* If X is a comparison operator, rewrite it in a new mode. This
11623 probably won't match, but may allow further simplifications. */
11627 /* If we couldn't simplify X any other way, just enclose it in a
11628 SUBREG. Normally, this SUBREG won't match, but some patterns may
11629 include an explicit SUBREG or we may simplify it further in combine. */
11630 else
11631 {
11632 rtx res;
11635 {
11640 }
11644 }
11646 fail:
11648 }
11649 \f
11650 /* Try to simplify a comparison between OP0 and a constant OP1,
11651 where CODE is the comparison code that will be tested, into a
11652 (CODE OP0 const0_rtx) form.
11654 The result is a possibly different comparison code to use.
11655 *POP1 may be updated. */
11657 static enum rtx_code
11660 {
11661 scalar_int_mode int_mode;
11664 /* Get the constant we are comparing against and turn off all bits
11665 not on in our mode. */
11669 /* If we are comparing against a constant power of two and the value
11670 being compared can only have that single bit nonzero (e.g., it was
11671 `and'ed with that bit), we can replace this with a comparison
11672 with zero. */
11681 {
11684 }
11686 /* Similarly, if we are comparing a value known to be either -1 or
11687 0 with -1, change it to the opposite comparison against zero. */
11693 {
11696 }
11698 /* Do some canonicalizations based on the comparison code. We prefer
11699 comparisons against zero and then prefer equality comparisons.
11700 If we can reduce the size of a constant, we will do that too. */
11702 {
11704 /* < C is equivalent to <= (C - 1) */
11706 {
11709 /* ... fall through to LE case below. */
11711 }
11712 else
11716 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11718 {
11721 }
11723 /* If we are doing a <= 0 comparison on a value known to have
11724 a zero sign bit, we can replace this with == 0. */
11735 /* >= C is equivalent to > (C - 1). */
11737 {
11740 /* ... fall through to GT below. */
11742 }
11743 else
11747 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11749 {
11752 }
11754 /* If we are doing a > 0 comparison on a value known to have
11755 a zero sign bit, we can replace this with != 0. */
11766 /* < C is equivalent to <= (C - 1). */
11768 {
11771 /* ... fall through ... */
11772 }
11773 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11778 {
11782 }
11783 else
11787 /* unsigned <= 0 is equivalent to == 0 */
11790 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11794 == ((HOST_WIDE_INT_1U
11796 {
11799 }
11803 /* >= C is equivalent to > (C - 1). */
11805 {
11808 /* ... fall through ... */
11809 }
11811 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11816 {
11820 }
11821 else
11825 /* unsigned > 0 is equivalent to != 0 */
11828 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11832 == (HOST_WIDE_INT_1U
11834 {
11837 }
11842 }
11846 }
11847 \f
11848 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11849 comparison code that will be tested.
11851 The result is a possibly different comparison code to use. *POP0 and
11852 *POP1 may be updated.
11854 It is possible that we might detect that a comparison is either always
11855 true or always false. However, we do not perform general constant
11856 folding in combine, so this knowledge isn't useful. Such tautologies
11857 should have been detected earlier. Hence we ignore all such cases. */
11859 static enum rtx_code
11861 {
11867 opt_scalar_int_mode tmode_iter;
11869 /* Try a few ways of applying the same transformation to both operands. */
11871 {
11872 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11873 so check specially. */
11892 {
11895 }
11897 /* If both operands are the same constant shift, see if we can ignore the
11898 shift. We can if the shift is a rotate or if the bits shifted out of
11899 this shift are known to be zero for both inputs and if the type of
11900 comparison is compatible with the shift. */
11913 {
11926 else
11928 }
11930 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11931 SUBREGs are of the same mode, and, in both cases, the AND would
11932 be redundant if the comparison was done in the narrower mode,
11933 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11934 and the operand's possibly nonzero bits are 0xffffff01; in that case
11935 if we only care about QImode, we don't need the AND). This case
11936 occurs if the output mode of an scc insn is not SImode and
11937 STORE_FLAG_VALUE == 1 (e.g., the 386).
11939 Similarly, check for a case where the AND's are ZERO_EXTEND
11940 operations from some narrower mode even though a SUBREG is not
11941 present. */
11946 {
11963 {
11967 /* The resulting comparison is always unsigned since we masked
11968 off the original sign bit. */
11972 }
11978 {
11984 }
11988 }
11990 /* If both operands are NOT, we can strip off the outer operation
11991 and adjust the comparison code for swapped operands; similarly for
11992 NEG, except that this must be an equality comparison. */
11998 else
12000 }
12002 /* If the first operand is a constant, swap the operands and adjust the
12003 comparison code appropriately, but don't do this if the second operand
12004 is already a constant integer. */
12006 {
12009 }
12011 /* We now enter a loop during which we will try to simplify the comparison.
12012 For the most part, we only are concerned with comparisons with zero,
12013 but some things may really be comparisons with zero but not start
12014 out looking that way. */
12017 {
12019 scalar_int_mode int_mode;
12023 HOST_WIDE_INT const_op;
12025 /* We only want to handle integral modes. This catches VOIDmode,
12026 CCmode, and the floating-point modes. An exception is that we
12027 can handle VOIDmode if OP0 is a COMPARE or a comparison
12028 operation. */
12035 /* Try to simplify the compare to constant, possibly changing the
12036 comparison op, and/or changing op1 to zero. */
12040 /* Compute some predicates to simplify code below. */
12047 /* If this is a sign bit comparison and we can do arithmetic in
12048 MODE, say that we will only be needing the sign bit of OP0. */
12053 HOST_WIDE_INT_1U
12058 {
12059 /* We can't do anything if OP0 is a condition code value, rather
12060 than an actual data value. */
12066 /* Get the two operands being compared. */
12069 else
12072 /* Check for the cases where we simply want the result of the
12073 earlier test or the opposite of that result. */
12077 {
12081 else
12085 {
12090 }
12091 }
12093 }
12099 /* Now try cases based on the opcode of OP0. If none of the cases
12100 does a "continue", we exit this loop immediately after the
12101 switch. */
12106 {
12108 /* If we are extracting a single bit from a variable position in
12109 a constant that has only a single bit set and are comparing it
12110 with zero, we can convert this into an equality comparison
12111 between the position and the location of the single bit. */
12112 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12113 have already reduced the shift count modulo the word size. */
12119 {
12127 /* Result is nonzero iff shift count is equal to I. */
12130 }
12132 /* fall through */
12137 {
12140 }
12144 /* If testing for equality, we can take the NOT of the constant. */
12147 {
12151 }
12153 /* If just looking at the sign bit, reverse the sense of the
12154 comparison. */
12156 {
12160 }
12164 /* If testing for equality, we can take the NEG of the constant. */
12167 {
12171 }
12173 /* The remaining cases only apply to comparisons with zero. */
12177 /* When X is ABS or is known positive,
12178 (neg X) is < 0 if and only if X != 0. */
12186 {
12190 }
12192 /* If we have NEG of something whose two high-order bits are the
12193 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12195 {
12199 }
12203 /* If we are testing equality and our count is a constant, we
12204 can perform the inverse operation on our RHS. */
12208 {
12212 }
12214 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12215 a particular bit. Convert it to an AND of a constant of that
12216 bit. This will be converted into a ZERO_EXTRACT. */
12220 {
12222 (HOST_WIDE_INT_1U
12227 }
12229 /* Fall through. */
12232 /* ABS is ignorable inside an equality comparison with zero. */
12234 {
12237 }
12241 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12242 (compare FOO CONST) if CONST fits in FOO's mode and we
12243 are either testing inequality or have an unsigned
12244 comparison with ZERO_EXTEND or a signed comparison with
12245 SIGN_EXTEND. But don't do it if we don't have a compare
12246 insn of the given mode, since we'd have to revert it
12247 later on, and then we wouldn't know whether to sign- or
12248 zero-extend. */
12250 && ! unsigned_comparison_p
12254 {
12257 }
12261 /* Check for the case where we are comparing A - C1 with C2, that is
12263 (subreg:MODE (plus (A) (-C1))) op (C2)
12265 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12266 comparison in the wider mode. One of the following two conditions
12267 must be true in order for this to be valid:
12269 1. The mode extension results in the same bit pattern being added
12270 on both sides and the comparison is equality or unsigned. As
12271 C2 has been truncated to fit in MODE, the pattern can only be
12272 all 0s or all 1s.
12274 2. The mode extension results in the sign bit being copied on
12275 each side.
12277 The difficulty here is that we have predicates for A but not for
12278 (A - C1) so we need to check that C1 is within proper bounds so
12279 as to perturbate A as little as possible. */
12288 {
12296 /* (A - C1) zero-extends if it is positive and sign-extends
12297 if it is negative, C2 both zero- and sign-extends. */
12301 /* (A - C1) sign-extends if it is positive and 1-extends
12302 if it is negative, C2 both sign- and 1-extends. */
12309 /* (A - C1) always sign-extends, like C2. */
12313 {
12316 }
12317 }
12319 /* If the inner mode is narrower and we are extracting the low part,
12320 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12322 ;
12331 {
12332 /* Remove outer subregs that don't do anything. */
12337 {
12341 }
12343 }
12344 else
12347 /* FALLTHROUGH */
12356 {
12359 }
12363 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12364 this for equality comparisons due to pathological cases involving
12365 overflows. */
12369 {
12373 }
12375 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12378 {
12382 }
12386 /* We used to optimize signed comparisons against zero, but that
12387 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12388 arrive here as equality comparisons, or (GEU, LTU) are
12389 optimized away. No need to special-case them. */
12391 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12392 (eq B (minus A C)), whichever simplifies. We can only do
12393 this for equality comparisons due to pathological cases involving
12394 overflows. */
12398 {
12402 }
12407 {
12411 }
12413 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12414 of bits in X minus 1, is one iff X > 0. */
12419 {
12423 }
12427 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12428 if C is zero or B is a constant. */
12432 {
12436 }
12441 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12442 iff X <= 0. */
12446 {
12450 }
12454 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12455 will be converted to a ZERO_EXTRACT later. */
12459 {
12464 }
12466 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12467 zero and X is a comparison and C1 and C2 describe only bits set
12468 in STORE_FLAG_VALUE, we can compare with X. */
12476 {
12483 {
12486 }
12487 }
12489 /* If we are doing an equality comparison of an AND of a bit equal
12490 to the sign bit, replace this with a LT or GE comparison of
12491 the underlying value. */
12498 {
12502 }
12504 /* If this AND operation is really a ZERO_EXTEND from a narrower
12505 mode, the constant fits within that mode, and this is either an
12506 equality or unsigned comparison, try to do this comparison in
12507 the narrower mode.
12509 Note that in:
12511 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12512 -> (ne:DI (reg:SI 4) (const_int 0))
12514 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12515 known to hold a value of the required mode the
12516 transformation is invalid. */
12524 {
12527 }
12529 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12530 fits in both M1 and M2 and the SUBREG is either paradoxical
12531 or represents the low part, permute the SUBREG and the AND
12532 and try again. */
12535 {
12537 /* Require an integral mode, to avoid creating something like
12538 (AND:SF ...). */
12541 /* It is unsafe to commute the AND into the SUBREG if the
12542 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12543 not defined. As originally written the upper bits
12544 have a defined value due to the AND operation.
12545 However, if we commute the AND inside the SUBREG then
12546 they no longer have defined values and the meaning of
12547 the code has been changed.
12548 Also C1 should not change value in the smaller mode,
12549 see PR67028 (a positive C1 can become negative in the
12550 smaller mode, so that the AND does no longer mask the
12551 upper bits). */
12552 && ((WORD_REGISTER_OPERATIONS
12564 {
12570 }
12571 }
12573 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12577 {
12582 }
12584 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12585 (eq (and (lshiftrt X) 1) 0).
12586 Also handle the case where (not X) is expressed using xor. */
12590 {
12600 == HOST_WIDE_INT_1U
12602 {
12603 op0
12608 }
12609 }
12613 /* If we have (compare (ashift FOO N) (const_int C)) and
12614 the high order N bits of FOO (N+1 if an inequality comparison)
12615 are known to be zero, we can do this by comparing FOO with C
12616 shifted right N bits so long as the low-order N bits of C are
12617 zero. */
12629 {
12630 /* We must perform a logical shift, not an arithmetic one,
12631 as we want the top N bits of C to be zero. */
12638 }
12640 /* If we are doing a sign bit comparison, it means we are testing
12641 a particular bit. Convert it to the appropriate AND. */
12644 {
12646 (HOST_WIDE_INT_1U
12651 }
12653 /* If this an equality comparison with zero and we are shifting
12654 the low bit to the sign bit, we can convert this to an AND of the
12655 low-order bit. */
12659 {
12662 }
12666 /* If this is an equality comparison with zero, we can do this
12667 as a logical shift, which might be much simpler. */
12670 {
12675 }
12677 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12678 do the comparison in a narrower mode. */
12688 {
12691 }
12693 /* Likewise if OP0 is a PLUS of a sign extension with a
12694 constant, which is usually represented with the PLUS
12695 between the shifts. */
12707 {
12715 new_const);
12717 }
12719 /* FALLTHROUGH */
12721 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12722 the low order N bits of FOO are known to be zero, we can do this
12723 by comparing FOO with C shifted left N bits so long as no
12724 overflow occurs. Even if the low order N bits of FOO aren't known
12725 to be zero, if the comparison is >= or < we can use the same
12726 optimization and for > or <= by setting all the low
12727 order N bits in the comparison constant. */
12738 {
12739 unsigned HOST_WIDE_INT low_bits
12741 & ((HOST_WIDE_INT_1U
12744 {
12745 /* If the shift was logical, then we must make the condition
12746 unsigned. */
12755 const_op
12760 }
12761 }
12763 /* If we are using this shift to extract just the sign bit, we
12764 can replace this with an LT or GE comparison. */
12769 {
12773 }
12778 }
12781 }
12783 /* Now make any compound operations involved in this comparison. Then,
12784 check for an outmost SUBREG on OP0 that is not doing anything or is
12785 paradoxical. The latter transformation must only be performed when
12786 it is known that the "extra" bits will be the same in op0 and op1 or
12787 that they don't matter. There are three cases to consider:
12789 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12790 care bits and we can assume they have any convenient value. So
12791 making the transformation is safe.
12793 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12794 In this case the upper bits of op0 are undefined. We should not make
12795 the simplification in that case as we do not know the contents of
12796 those bits.
12798 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12799 In that case we know those bits are zeros or ones. We must also be
12800 sure that they are the same as the upper bits of op1.
12802 We can never remove a SUBREG for a non-equality comparison because
12803 the sign bit is in a different place in the underlying object. */
12816 {
12818 {
12819 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12820 implemented. */
12822 {
12825 }
12826 }
12830 {
12835 }
12836 }
12838 /* We now do the opposite procedure: Some machines don't have compare
12839 insns in all modes. If OP0's mode is an integer mode smaller than a
12840 word and we can't do a compare in that mode, see if there is a larger
12841 mode for which we can do the compare. There are a number of cases in
12842 which we can use the wider mode. */
12848 {
12853 {
12856 /* If this is a test for negative, we can make an explicit
12857 test of the sign bit. Test this first so we can use
12858 a paradoxical subreg to extend OP0. */
12862 {
12863 unsigned HOST_WIDE_INT sign
12870 }
12872 /* If the only nonzero bits in OP0 and OP1 are those in the
12873 narrower mode and this is an equality or unsigned comparison,
12874 we can use the wider mode. Similarly for sign-extended
12875 values, in which case it is true for all comparisons. */
12892 {
12893 /* If OP0 is an AND and we don't have an AND in MODE either,
12894 make a new AND in the proper mode. */
12902 else
12903 {
12905 {
12910 }
12911 else
12912 {
12917 }
12919 }
12920 }
12921 }
12922 }
12924 /* We may have changed the comparison operands. Re-canonicalize. */
12926 {
12929 }
12931 /* If this machine only supports a subset of valid comparisons, see if we
12932 can convert an unsupported one into a supported one. */
12939 }
12940 \f
12941 /* Utility function for record_value_for_reg. Count number of
12942 rtxs in X. */
12943 static int
12945 {
12952 {
12972 }
12983 }
12984 \f
12985 /* Utility function for following routine. Called when X is part of a value
12986 being stored into last_set_value. Sets last_set_table_tick
12987 for each register mentioned. Similar to mention_regs in cse.c */
12989 static void
12991 {
12997 {
13003 {
13006 }
13009 }
13013 {
13014 /* Check for identical subexpressions. If x contains
13015 identical subexpression we only have to traverse one of
13016 them. */
13018 {
13019 /* Note that at this point x1 has already been
13020 processed. */
13024 /* If x0 and x1 are identical then there is no need to
13025 process x0. */
13029 /* If x0 is identical to a subexpression of x1 then while
13030 processing x1, x0 has already been processed. Thus we
13031 are done with x. */
13036 /* If x1 is identical to a subexpression of x0 then we
13037 still have to process the rest of x0. */
13040 {
13043 }
13044 }
13047 }
13051 }
13053 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13054 are saying that the register is clobbered and we no longer know its
13055 value. If INSN is zero, don't update reg_stat[].last_set; this is
13056 only permitted with VALUE also zero and is used to invalidate the
13057 register. */
13059 static void
13061 {
13067 /* If VALUE contains REG and we have a previous value for REG, substitute
13068 the previous value. */
13070 {
13071 rtx tem;
13073 /* Set things up so get_last_value is allowed to see anything set up to
13074 our insn. */
13078 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13079 it isn't going to be useful and will take a lot of time to process,
13080 so just use the CLOBBER. */
13083 {
13089 {
13090 /* If there are two or more occurrences of REG in VALUE,
13091 prevent the value from growing too much. */
13094 }
13097 }
13098 }
13100 /* For each register modified, show we don't know its value, that
13101 we don't know about its bitwise content, that its value has been
13102 updated, and that we don't know the location of the death of the
13103 register. */
13105 {
13117 }
13119 /* Mark registers that are being referenced in this value. */
13123 /* Now update the status of each register being set.
13124 If someone is using this register in this block, set this register
13125 to invalid since we will get confused between the two lives in this
13126 basic block. This makes using this register always invalid. In cse, we
13127 scan the table to invalidate all entries using this register, but this
13128 is too much work for us. */
13131 {
13137 else
13139 }
13141 /* The value being assigned might refer to X (like in "x++;"). In that
13142 case, we must replace it with (clobber (const_int 0)) to prevent
13143 infinite loops. */
13146 {
13150 }
13152 /* For the main register being modified, update the value, the mode, the
13153 nonzero bits, and the number of sign bit copies. */
13158 {
13166 rsp->last_set_sign_bit_copies
13168 }
13169 }
13171 /* Called via note_stores from record_dead_and_set_regs to handle one
13172 SET or CLOBBER in an insn. DATA is the instruction in which the
13173 set is occurring. */
13175 static void
13177 {
13184 {
13188 }
13191 {
13192 /* If we are setting the whole register, we know its value. Otherwise
13193 show that we don't know the value. We can handle SUBREG in
13194 some cases. */
13205 else
13207 }
13209 /* Ignore pushes, they clobber nothing. */
13212 }
13214 /* Update the records of when each REG was most recently set or killed
13215 for the things done by INSN. This is the last thing done in processing
13216 INSN in the combiner loop.
13218 We update reg_stat[], in particular fields last_set, last_set_value,
13219 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13220 last_death, and also the similar information mem_last_set (which insn
13221 most recently modified memory) and last_call_luid (which insn was the
13222 most recent subroutine call). */
13224 static void
13226 {
13227 rtx link;
13231 {
13234 {
13239 {
13244 }
13245 }
13248 }
13251 {
13252 hard_reg_set_iterator hrsi;
13254 {
13266 }
13270 /* We can't combine into a call pattern. Remember, though, that
13271 the return value register is set at this LUID. We could
13272 still replace a register with the return value from the
13273 wrong subroutine call! */
13275 }
13276 else
13278 }
13280 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13281 register present in the SUBREG, so for each such SUBREG go back and
13282 adjust nonzero and sign bit information of the registers that are
13283 known to have some zero/sign bits set.
13285 This is needed because when combine blows the SUBREGs away, the
13286 information on zero/sign bits is lost and further combines can be
13287 missed because of that. */
13289 static void
13291 {
13293 rtx set;
13301 {
13310 {
13313 }
13317 {
13320 }
13323 {
13326 }
13327 else
13329 }
13330 }
13332 /* Check if X, a register, is known to contain a value already
13333 truncated to MODE. In this case we can use a subreg to refer to
13334 the truncated value even though in the generic case we would need
13335 an explicit truncation. */
13337 static bool
13339 {
13351 }
13353 /* If X is a hard reg or a subreg record the mode that the register is
13354 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13355 able to turn a truncate into a subreg using this information. Return true
13356 if traversing X is complete. */
13358 static bool
13360 {
13361 machine_mode truncated_mode;
13365 {
13377 }
13378 /* ??? For hard-regs we now record everything. We might be able to
13379 optimize this using last_set_mode. */
13382 else
13389 {
13392 }
13395 }
13397 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13398 the modes they are used in. This can help truning TRUNCATEs into
13399 SUBREGs. */
13401 static void
13403 {
13408 }
13410 /* Scan X for promoted SUBREGs. For each one found,
13411 note what it implies to the registers used in it. */
13413 static void
13415 {
13420 else
13421 {
13427 {
13437 }
13438 }
13439 }
13440 \f
13441 /* Verify that all the registers and memory references mentioned in *LOC are
13442 still valid. *LOC was part of a value set in INSN when label_tick was
13443 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13444 the invalid references with (clobber (const_int 0)) and return 1. This
13445 replacement is useful because we often can get useful information about
13446 the form of a value (e.g., if it was produced by a shift that always
13447 produces -1 or 0) even though we don't know exactly what registers it
13448 was produced from. */
13450 static int
13452 {
13459 {
13465 {
13468 /* If this is a pseudo-register that was only set once and not
13469 live at the beginning of the function, it is always valid. */
13473 && (!REGNO_REG_SET_P
13475 regno)))
13477 {
13481 }
13482 }
13485 }
13486 /* If this is a memory reference, make sure that there were no stores after
13487 it that might have clobbered the value. We don't have alias info, so we
13488 assume any store invalidates it. Moreover, we only have local UIDs, so
13489 we also assume that there were stores in the intervening basic blocks. */
13492 {
13496 }
13499 {
13501 {
13502 /* Check for identical subexpressions. If x contains
13503 identical subexpression we only have to traverse one of
13504 them. */
13506 {
13507 /* Note that at this point x0 has already been checked
13508 and found valid. */
13512 /* If x0 and x1 are identical then x is also valid. */
13516 /* If x1 is identical to a subexpression of x0 then
13517 while checking x0, x1 has already been checked. Thus
13518 it is valid and so as x. */
13523 /* If x0 is identical to a subexpression of x1 then x is
13524 valid iff the rest of x1 is valid. */
13527 return
13531 }
13536 }
13542 }
13544 /* If we haven't found a reason for it to be invalid, it is valid. */
13546 }
13548 /* Get the last value assigned to X, if known. Some registers
13549 in the value may be replaced with (clobber (const_int 0)) if their value
13550 is known longer known reliably. */
13552 static rtx
13554 {
13556 rtx value;
13559 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13560 then convert it to the desired mode. If this is a paradoxical SUBREG,
13561 we cannot predict what values the "extra" bits might have. */
13575 /* If we don't have a value, or if it isn't for this basic block and
13576 it's either a hard register, set more than once, or it's a live
13577 at the beginning of the function, return 0.
13579 Because if it's not live at the beginning of the function then the reg
13580 is always set before being used (is never used without being set).
13581 And, if it's set only once, and it's always set before use, then all
13582 uses must have the same last value, even if it's not from this basic
13583 block. */
13590 || REGNO_REG_SET_P
13594 /* If the value was set in a later insn than the ones we are processing,
13595 we can't use it even if the register was only set once. */
13600 /* If fewer bits were set than what we are asked for now, we cannot use
13601 the value. */
13606 /* If the value has all its registers valid, return it. */
13610 /* Otherwise, make a copy and replace any invalid register with
13611 (clobber (const_int 0)). If that fails for some reason, return 0. */
13618 }
13619 \f
13620 /* Return nonzero if expression X refers to a REG or to memory
13621 that is set in an instruction more recent than FROM_LUID. */
13623 static int
13625 {
13631 {
13635 #ifdef PUSH_ROUNDING
13636 /* Don't allow uses of the stack pointer to be moved,
13637 because we don't know whether the move crosses a push insn. */
13640 #endif
13642 {
13648 }
13650 }
13658 {
13660 {
13665 }
13669 }
13671 }
13672 \f
13673 /* Define three variables used for communication between the following
13674 routines. */
13679 /* Function called via note_stores from reg_dead_at_p.
13681 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13682 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13684 static void
13686 {
13696 }
13698 /* Return nonzero if REG is known to be dead at INSN.
13700 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13701 referencing REG, it is dead. If we hit a SET referencing REG, it is
13702 live. Otherwise, see if it is live or dead at the start of the basic
13703 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13704 must be assumed to be always live. */
13706 static int
13708 {
13709 basic_block block;
13712 /* Set variables for reg_dead_at_p_1. */
13718 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13719 we allow the machine description to decide whether use-and-clobber
13720 patterns are OK. */
13722 {
13726 }
13728 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13729 beginning of basic block. */
13732 {
13734 {
13744 }
13750 }
13752 /* Look at live-in sets for the basic block that we were in. */
13758 }
13759 \f
13760 /* Note hard registers in X that are used. */
13762 static void
13764 {
13770 {
13774 CASE_CONST_ANY:
13779 /* CC0 must die in the insn after it is set, so we don't need to take
13780 special note of it here. */
13785 /* If we are clobbering a MEM, mark any hard registers inside the
13786 address as used. */
13793 /* A hard reg in a wide mode may really be multiple registers.
13794 If so, mark all of them just like the first. */
13796 {
13797 /* None of this applies to the stack, frame or arg pointers. */
13799 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13807 }
13811 {
13812 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13813 the address. */
13825 }
13830 }
13832 /* Recursively scan the operands of this expression. */
13834 {
13838 {
13842 {
13847 }
13848 }
13849 }
13850 }
13851 \f
13852 /* Remove register number REGNO from the dead registers list of INSN.
13854 Return the note used to record the death, if there was one. */
13856 rtx
13858 {
13865 }
13867 /* For each register (hardware or pseudo) used within expression X, if its
13868 death is in an instruction with luid between FROM_LUID (inclusive) and
13869 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13870 list headed by PNOTES.
13872 That said, don't move registers killed by maybe_kill_insn.
13874 This is done when X is being merged by combination into TO_INSN. These
13875 notes will then be distributed as needed. */
13877 static void
13880 {
13886 {
13890 /* Don't move the register if it gets killed in between from and to. */
13899 {
13902 /* It is possible for the call above to return 0. This can occur
13903 when last_death points to I2 or I1 that we combined with.
13904 In that case make a new note.
13906 We must also check for the case where X is a hard register
13907 and NOTE is a death note for a range of hard registers
13908 including X. In that case, we must put REG_DEAD notes for
13909 the remaining registers in place of NOTE. */
13913 {
13922 }
13924 /* If we didn't find any note, or if we found a REG_DEAD note that
13925 covers only part of the given reg, and we have a multi-reg hard
13926 register, then to be safe we must check for REG_DEAD notes
13927 for each register other than the first. They could have
13928 their own REG_DEAD notes lying around. */
13935 {
13942 else
13948 }
13951 {
13954 }
13955 else
13957 }
13960 }
13963 {
13968 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13969 that accesses one word of a multi-word item, some
13970 piece of everything register in the expression is used by
13971 this insn, so remove any old death. */
13972 /* ??? So why do we test for equality of the sizes? */
13981 {
13984 }
13986 /* If this is some other SUBREG, we know it replaces the entire
13987 value, so use that as the destination. */
13991 /* If this is a MEM, adjust deaths of anything used in the address.
13992 For a REG (the only other possibility), the entire value is
13993 being replaced so the old value is not used in this insn. */
13999 }
14008 {
14010 {
14015 }
14018 }
14019 }
14020 \f
14021 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14022 pattern of an insn. X must be a REG. */
14024 static int
14026 {
14030 {
14032 rtx target;
14039 else
14056 }
14064 }
14065 \f
14066 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14067 as appropriate. I3 and I2 are the insns resulting from the combination
14068 insns including FROM (I2 may be zero).
14070 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14071 not need REG_DEAD notes because they are being substituted for. This
14072 saves searching in the most common cases.
14074 Each note in the list is either ignored or placed on some insns, depending
14075 on the type of note. */
14077 static void
14080 {
14082 rtx tem_note;
14086 {
14091 {
14094 /* Doesn't matter much where we put this, as long as it's somewhere.
14095 It is preferable to keep these notes on branches, which is most
14096 likely to be i3. */
14103 else
14104 {
14107 }
14111 /* These notes must remain with the call or trapping instruction. */
14116 else
14117 {
14123 /* ??? Otherwise assume we've combined things such that we
14124 can now prove that the instructions can't trap. Drop the
14125 note in this case. */
14126 }
14130 /* ??? How to distribute between i3-i1. Assume i3 contains the
14131 entire adjustment. Assert i3 contains at least some adjust. */
14133 {
14135 /* fixup_args_size_notes looks at REG_NORETURN note,
14136 so ensure the note is placed there first. */
14138 {
14142 {
14148 }
14149 }
14151 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14152 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14155 && !ACCUMULATE_OUTGOING_ARGS
14157 }
14164 /* These notes must remain with the call. It should not be
14165 possible for both I2 and I3 to be a call. */
14168 else
14169 {
14172 }
14176 /* Any clobbers for i3 may still exist, and so we must process
14177 REG_UNUSED notes from that insn.
14179 Any clobbers from i2 or i1 can only exist if they were added by
14180 recog_for_combine. In that case, recog_for_combine created the
14181 necessary REG_UNUSED notes. Trying to keep any original
14182 REG_UNUSED notes from these insns can cause incorrect output
14183 if it is for the same register as the original i3 dest.
14184 In that case, we will notice that the register is set in i3,
14185 and then add a REG_UNUSED note for the destination of i3, which
14186 is wrong. However, it is possible to have REG_UNUSED notes from
14187 i2 or i1 for register which were both used and clobbered, so
14188 we keep notes from i2 or i1 if they will turn into REG_DEAD
14189 notes. */
14191 /* If this register is set or clobbered in I3, put the note there
14192 unless there is one already. */
14194 {
14202 }
14203 /* Otherwise, if this register is used by I3, then this register
14204 now dies here, so we must put a REG_DEAD note here unless there
14205 is one already. */
14211 {
14214 }
14220 /* These notes say something about results of an insn. We can
14221 only support them if they used to be on I3 in which case they
14222 remain on I3. Otherwise they are ignored.
14224 If the note refers to an expression that is not a constant, we
14225 must also ignore the note since we cannot tell whether the
14226 equivalence is still true. It might be possible to do
14227 slightly better than this (we only have a problem if I2DEST
14228 or I1DEST is present in the expression), but it doesn't
14229 seem worth the trouble. */
14237 /* These notes say something about how a register is used. They must
14238 be present on any use of the register in I2 or I3. */
14243 {
14246 else
14248 }
14253 /* This can show up in several ways -- either directly in the
14254 pattern, or hidden off in the constant pool with (or without?)
14255 a REG_EQUAL note. */
14256 /* ??? Ignore the without-reg_equal-note problem for now. */
14268 {
14271 else
14273 }
14275 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14276 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14277 there. */
14282 {
14289 }
14295 {
14303 }
14307 /* This note says something about the value of a register prior
14308 to the execution of an insn. It is too much trouble to see
14309 if the note is still correct in all situations. It is better
14310 to simply delete it. */
14314 /* If we replaced the right hand side of FROM_INSN with a
14315 REG_EQUAL note, the original use of the dying register
14316 will not have been combined into I3 and I2. In such cases,
14317 FROM_INSN is guaranteed to be the first of the combined
14318 instructions, so we simply need to search back before
14319 FROM_INSN for the previous use or set of this register,
14320 then alter the notes there appropriately.
14322 If the register is used as an input in I3, it dies there.
14323 Similarly for I2, if it is nonzero and adjacent to I3.
14325 If the register is not used as an input in either I3 or I2
14326 and it is not one of the registers we were supposed to eliminate,
14327 there are two possibilities. We might have a non-adjacent I2
14328 or we might have somehow eliminated an additional register
14329 from a computation. For example, we might have had A & B where
14330 we discover that B will always be zero. In this case we will
14331 eliminate the reference to A.
14333 In both cases, we must search to see if we can find a previous
14334 use of A and put the death note there. */
14340 else
14341 {
14352 && !(i2mod
14354 i2mod_old_rhs)))
14359 /* If the new I2 sets the same register that is marked dead
14360 in the note, we do not know where to put the note.
14361 Give up. */
14364 }
14367 {
14371 {
14373 {
14377 }
14379 /* If the register is being set at TEM_INSN, see if that is all
14380 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14381 into a REG_UNUSED note instead. Don't delete sets to
14382 global register vars. */
14386 {
14397 ;
14399 /* Verify that it was the set, and not a clobber that
14400 modified the register.
14402 CC0 targets must be careful to maintain setter/user
14403 pairs. If we cannot delete the setter due to side
14404 effects, mark the user with an UNUSED note instead
14405 of deleting it. */
14409 && (!HAVE_cc0
14413 {
14414 /* Move the notes and links of TEM_INSN elsewhere.
14415 This might delete other dead insns recursively.
14416 First set the pattern to something that won't use
14417 any register. */
14436 /* Delete the setter too. */
14438 {
14451 }
14452 }
14453 else
14454 {
14457 /* If there isn't already a REG_UNUSED note, put one
14458 here. Do not place a REG_DEAD note, even if
14459 the register is also used here; that would not
14460 match the algorithm used in lifetime analysis
14461 and can cause the consistency check in the
14462 scheduler to fail. */
14467 }
14468 }
14472 {
14475 /* If we are doing a 3->2 combination, and we have a
14476 register which formerly died in i3 and was not used
14477 by i2, which now no longer dies in i3 and is used in
14478 i2 but does not die in i2, and place is between i2
14479 and i3, then we may need to move a link from place to
14480 i2. */
14482 && from_insn
14485 {
14489 }
14491 }
14495 }
14497 }
14499 /* If the register is set or already dead at PLACE, we needn't do
14500 anything with this note if it is still a REG_DEAD note.
14501 We check here if it is set at all, not if is it totally replaced,
14502 which is what `dead_or_set_p' checks, so also check for it being
14503 set partially. */
14506 {
14512 {
14513 /* Unless the register previously died in PLACE, clear
14514 last_death. [I no longer understand why this is
14515 being done.] */
14519 }
14520 else
14523 /* If this is a death note for a hard reg that is occupying
14524 multiple registers, ensure that we are still using all
14525 parts of the object. If we find a piece of the object
14526 that is unused, we must arrange for an appropriate REG_DEAD
14527 note to be added for it. However, we can't just emit a USE
14528 and tag the note to it, since the register might actually
14529 be dead; so we recourse, and the recursive call then finds
14530 the previous insn that used this register. */
14533 {
14542 {
14545 }
14548 {
14549 /* Put only REG_DEAD notes for pieces that are
14550 not already dead or set. */
14554 {
14561 {
14563 NULL_RTX);
14567 NULL_RTX);
14568 }
14573 {
14575 {
14579 }
14583 {
14586 }
14587 }
14588 }
14591 }
14592 }
14593 }
14597 /* Any other notes should not be present at this point in the
14598 compilation. */
14600 }
14603 {
14606 }
14610 }
14611 }
14612 \f
14613 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14614 I3, I2, and I1 to new locations. This is also called to add a link
14615 pointing at I3 when I3's destination is changed. */
14617 static void
14619 {
14623 {
14630 /* If the insn that this link points to is a NOTE, ignore it. */
14639 {
14642 {
14658 }
14661 }
14662 else
14672 /* A LOG_LINK is defined as being placed on the first insn that uses
14673 a register and points to the insn that sets the register. Start
14674 searching at the next insn after the target of the link and stop
14675 when we reach a set of the register or the end of the basic block.
14677 Note that this correctly handles the link that used to point from
14678 I3 to I2. Also note that not much searching is typically done here
14679 since most links don't point very far away. */
14688 {
14692 }
14695 {
14698 }
14702 /* If we found a place to put the link, place it there unless there
14703 is already a link to the same insn as LINK at that point. */
14706 {
14714 {
14718 /* Set added_links_insn to the earliest insn we added a
14719 link to. */
14723 }
14724 }
14725 }
14726 }
14727 \f
14728 /* Check for any register or memory mentioned in EQUIV that is not
14729 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14730 of EXPR where some registers may have been replaced by constants. */
14732 static bool
14734 {
14737 {
14742 }
14744 }
14745 \f
14746 DEBUG_FUNCTION void
14748 {
14749 fprintf
14751 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14753 }
14755 void
14757 {
14758 fprintf
14760 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14762 }
14763 \f
14764 /* Try combining insns through substitution. */
14765 static unsigned int
14767 {
14777 rebuild_jump_labels_after_combine
14780 /* Combining insns may have turned an indirect jump into a
14781 direct jump. Rebuild the JUMP_LABEL fields of jumping
14782 instructions. */
14784 {
14791 }
14795 }
14800 {
14810 };
14813 {
14817 {}
14819 /* opt_pass methods: */
14822 {
14824 }
14830 rtl_opt_pass *
14832 {
14834 }