| blob | 366cec0812a9b19c6cab8750f9d3eb863147a5c9 |
1 ;; Arm M-profile Vector Extension Machine Description
2 ;; Copyright (C) 2019-2023 Free Software Foundation, Inc.
3 ;;
4 ;; This file is part of GCC.
5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
9 ;; any later version.
10 ;;
11 ;; GCC is distributed in the hope that it will be useful, but
12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 ;; General Public License for more details.
15 ;;
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_insn "*mve_mov<mode>"
21 [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w , w, r,Ux,w")
22 (match_operand:MVE_types 1 "general_operand" " w,r,w,DnDm,UxUi,r,w, Ul"))]
23 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
24 {
25 switch (which_alternative)
26 {
27 case 0: /* [w,w]. */
28 return "vmov\t%q0, %q1";
30 case 1: /* [w,r]. */
31 return "vmov\t%e0, %Q1, %R1 %@ <mode>\;vmov\t%f0, %J1, %K1";
33 case 2: /* [r,w]. */
34 return "vmov\t%Q0, %R0, %e1 %@ <mode>\;vmov\t%J0, %K0, %f1";
36 case 3: /* [w,DnDm]. */
37 {
38 int width, is_valid;
40 is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode,
41 &operands[1], &width);
43 gcc_assert (is_valid);
45 if (width == 0)
46 return "vmov.f32\t%q0, %1 %@ <mode>";
47 else
48 {
49 const int templ_size = 40;
50 static char templ[templ_size];
51 if (snprintf (templ, templ_size,
52 "vmov.i%d\t%%q0, %%x1 %%@ <mode>", width)
53 > templ_size)
54 abort ();
55 return templ;
56 }
57 }
59 case 4: /* [w,UxUi]. */
60 if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode
61 || <MODE>mode == TImode)
62 return "vldrw.u32\t%q0, %E1";
63 else
64 return "vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1";
66 case 5: /* [r,r]. */
67 return output_move_quad (operands);
69 case 6: /* [Ux,w]. */
70 if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode
71 || <MODE>mode == TImode)
72 return "vstrw.32\t%q1, %E0";
73 else
74 return "vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0";
76 case 7: /* [w,Ul]. */
77 return output_move_neon (operands);
79 default:
80 gcc_unreachable ();
81 return "";
82 }
83 }
84 [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_store,mve_load")
85 (set_attr "length" "4,8,8,4,4,8,4,8")
86 (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*")
87 (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")])
89 (define_insn "*mve_vdup<mode>"
90 [(set (match_operand:MVE_vecs 0 "s_register_operand" "=w")
91 (vec_duplicate:MVE_vecs
92 (match_operand:<V_elem> 1 "s_register_operand" "r")))]
93 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
94 "vdup.<V_sz_elem>\t%q0, %1"
95 [(set_attr "length" "4")
96 (set_attr "type" "mve_move")])
98 ;;
99 ;; [vst4q])
100 ;;
101 (define_insn "mve_vst4q<mode>"
102 [(set (match_operand:XI 0 "mve_struct_operand" "=Ug")
103 (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
104 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
105 VST4Q))
106 ]
107 "TARGET_HAVE_MVE"
108 {
109 rtx ops[6];
110 int regno = REGNO (operands[1]);
111 ops[0] = gen_rtx_REG (TImode, regno);
112 ops[1] = gen_rtx_REG (TImode, regno+4);
113 ops[2] = gen_rtx_REG (TImode, regno+8);
114 ops[3] = gen_rtx_REG (TImode, regno+12);
115 rtx reg = operands[0];
116 while (reg && !REG_P (reg))
117 reg = XEXP (reg, 0);
118 gcc_assert (REG_P (reg));
119 ops[4] = reg;
120 ops[5] = operands[0];
121 /* Here in first three instructions data is stored to ops[4]'s location but
122 in the fourth instruction data is stored to operands[0], this is to
123 support the writeback. */
124 output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
125 "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
126 "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
127 "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
128 return "";
129 }
130 [(set_attr "length" "16")])
132 ;;
133 ;; [vrndaq_f]
134 ;; [vrndmq_f]
135 ;; [vrndnq_f]
136 ;; [vrndpq_f]
137 ;; [vrndq_f]
138 ;; [vrndxq_f]
139 ;;
140 (define_insn "@mve_<mve_insn>q_f<mode>"
141 [
142 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
143 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
144 MVE_FP_UNARY))
145 ]
146 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
147 "<mve_mnemo>.f%#<V_sz_elem>\t%q0, %q1"
148 [(set_attr "type" "mve_move")
149 ])
151 ;;
152 ;; [vrev64q_f])
153 ;;
154 (define_insn "@mve_<mve_insn>q_f<mode>"
155 [
156 (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
157 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
158 MVE_FP_VREV64Q_ONLY))
159 ]
160 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
161 "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
162 [(set_attr "type" "mve_move")
163 ])
165 ;;
166 ;; [vabsq_f]
167 ;; [vnegq_f]
168 ;;
169 (define_insn "mve_v<absneg_str>q_f<mode>"
170 [
171 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
172 (ABSNEG:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
173 ]
174 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
175 "v<absneg_str>.f%#<V_sz_elem>\t%q0, %q1"
176 [(set_attr "type" "mve_move")
177 ])
179 ;;
180 ;; [vdupq_n_f])
181 ;;
182 (define_insn "@mve_<mve_insn>q_n_f<mode>"
183 [
184 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
185 (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
186 MVE_FP_N_VDUPQ_ONLY))
187 ]
188 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
189 "<mve_insn>.%#<V_sz_elem>\t%q0, %1"
190 [(set_attr "type" "mve_move")
191 ])
193 ;;
194 ;; [vrev32q_f])
195 ;;
196 (define_insn "@mve_<mve_insn>q_f<mode>"
197 [
198 (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w")
199 (unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "w")]
200 MVE_FP_VREV32Q_ONLY))
201 ]
202 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
203 "<mve_insn>.<V_sz_elem>\t%q0, %q1"
204 [(set_attr "type" "mve_move")
205 ])
206 ;;
207 ;; [vcvttq_f32_f16])
208 ;;
209 (define_insn "mve_vcvttq_f32_f16v4sf"
210 [
211 (set (match_operand:V4SF 0 "s_register_operand" "=w")
212 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
213 VCVTTQ_F32_F16))
214 ]
215 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
216 "vcvtt.f32.f16\t%q0, %q1"
217 [(set_attr "type" "mve_move")
218 ])
220 ;;
221 ;; [vcvtbq_f32_f16])
222 ;;
223 (define_insn "mve_vcvtbq_f32_f16v4sf"
224 [
225 (set (match_operand:V4SF 0 "s_register_operand" "=w")
226 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")]
227 VCVTBQ_F32_F16))
228 ]
229 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
230 "vcvtb.f32.f16\t%q0, %q1"
231 [(set_attr "type" "mve_move")
232 ])
234 ;;
235 ;; [vcvtq_to_f_s, vcvtq_to_f_u])
236 ;;
237 (define_insn "mve_vcvtq_to_f_<supf><mode>"
238 [
239 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
240 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
241 VCVTQ_TO_F))
242 ]
243 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
244 "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1"
245 [(set_attr "type" "mve_move")
246 ])
248 ;;
249 ;; [vrev64q_u, vrev64q_s])
250 ;;
251 (define_insn "@mve_<mve_insn>q_<supf><mode>"
252 [
253 (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
254 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
255 VREV64Q))
256 ]
257 "TARGET_HAVE_MVE"
258 "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
259 [(set_attr "type" "mve_move")
260 ])
262 ;;
263 ;; [vcvtq_from_f_s, vcvtq_from_f_u])
264 ;;
265 (define_insn "mve_vcvtq_from_f_<supf><mode>"
266 [
267 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
268 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
269 VCVTQ_FROM_F))
270 ]
271 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
272 "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
273 [(set_attr "type" "mve_move")
274 ])
276 ;;
277 ;; [vabsq_s]
278 ;; [vnegq_s]
279 ;;
280 (define_insn "mve_v<absneg_str>q_s<mode>"
281 [
282 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
283 (ABSNEG:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
284 ]
285 "TARGET_HAVE_MVE"
286 "v<absneg_str>.s%#<V_sz_elem>\t%q0, %q1"
287 [(set_attr "type" "mve_move")
288 ])
290 ;;
291 ;; [vmvnq_u, vmvnq_s])
292 ;;
293 (define_insn "mve_vmvnq_u<mode>"
294 [
295 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
296 (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
297 ]
298 "TARGET_HAVE_MVE"
299 "vmvn\t%q0, %q1"
300 [(set_attr "type" "mve_move")
301 ])
302 (define_expand "mve_vmvnq_s<mode>"
303 [
304 (set (match_operand:MVE_2 0 "s_register_operand")
305 (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand")))
306 ]
307 "TARGET_HAVE_MVE"
308 )
310 ;;
311 ;; [vdupq_n_u, vdupq_n_s])
312 ;;
313 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
314 [
315 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
316 (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")]
317 VDUPQ_N))
318 ]
319 "TARGET_HAVE_MVE"
320 "<mve_insn>.%#<V_sz_elem>\t%q0, %1"
321 [(set_attr "type" "mve_move")
322 ])
324 ;;
325 ;; [vclzq_u, vclzq_s])
326 ;;
327 (define_insn "@mve_vclzq_s<mode>"
328 [
329 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
330 (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
331 ]
332 "TARGET_HAVE_MVE"
333 "vclz.i%#<V_sz_elem>\t%q0, %q1"
334 [(set_attr "type" "mve_move")
335 ])
336 (define_expand "mve_vclzq_u<mode>"
337 [
338 (set (match_operand:MVE_2 0 "s_register_operand")
339 (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand")))
340 ]
341 "TARGET_HAVE_MVE"
342 )
344 ;;
345 ;; [vclsq_s]
346 ;; [vqabsq_s]
347 ;; [vqnegq_s]
348 ;;
349 (define_insn "@mve_<mve_insn>q_<supf><mode>"
350 [
351 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
352 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
353 MVE_INT_UNARY))
354 ]
355 "TARGET_HAVE_MVE"
356 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1"
357 [(set_attr "type" "mve_move")
358 ])
360 ;;
361 ;; [vaddvq_s, vaddvq_u])
362 ;;
363 (define_insn "@mve_<mve_insn>q_<supf><mode>"
364 [
365 (set (match_operand:SI 0 "s_register_operand" "=Te")
366 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]
367 VADDVQ))
368 ]
369 "TARGET_HAVE_MVE"
370 "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q1"
371 [(set_attr "type" "mve_move")
372 ])
374 ;;
375 ;; [vrev32q_u, vrev32q_s])
376 ;;
377 (define_insn "@mve_<mve_insn>q_<supf><mode>"
378 [
379 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
380 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")]
381 VREV32Q))
382 ]
383 "TARGET_HAVE_MVE"
384 "<mve_insn>.%#<V_sz_elem>\t%q0, %q1"
385 [(set_attr "type" "mve_move")
386 ])
388 ;;
389 ;; [vmovlbq_s, vmovlbq_u]
390 ;; [vmovltq_u, vmovltq_s]
391 ;;
392 (define_insn "@mve_<mve_insn>q_<supf><mode>"
393 [
394 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
395 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")]
396 VMOVLxQ))
397 ]
398 "TARGET_HAVE_MVE"
399 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1"
400 [(set_attr "type" "mve_move")
401 ])
403 ;;
404 ;; [vcvtpq_s, vcvtpq_u])
405 ;;
406 (define_insn "mve_vcvtpq_<supf><mode>"
407 [
408 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
409 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
410 VCVTPQ))
411 ]
412 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
413 "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
414 [(set_attr "type" "mve_move")
415 ])
417 ;;
418 ;; [vcvtnq_s, vcvtnq_u])
419 ;;
420 (define_insn "mve_vcvtnq_<supf><mode>"
421 [
422 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
423 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
424 VCVTNQ))
425 ]
426 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
427 "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
428 [(set_attr "type" "mve_move")
429 ])
431 ;;
432 ;; [vcvtmq_s, vcvtmq_u])
433 ;;
434 (define_insn "mve_vcvtmq_<supf><mode>"
435 [
436 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
437 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
438 VCVTMQ))
439 ]
440 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
441 "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
442 [(set_attr "type" "mve_move")
443 ])
445 ;;
446 ;; [vcvtaq_u, vcvtaq_s])
447 ;;
448 (define_insn "mve_vcvtaq_<supf><mode>"
449 [
450 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
451 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")]
452 VCVTAQ))
453 ]
454 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
455 "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1"
456 [(set_attr "type" "mve_move")
457 ])
459 ;;
460 ;; [vmvnq_n_u, vmvnq_n_s])
461 ;;
462 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
463 [
464 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
465 (unspec:MVE_5 [(match_operand:<V_elem> 1 "immediate_operand" "i")]
466 VMVNQ_N))
467 ]
468 "TARGET_HAVE_MVE"
469 "<mve_insn>.i%#<V_sz_elem>\t%q0, %1"
470 [(set_attr "type" "mve_move")
471 ])
473 ;;
474 ;; [vrev16q_u, vrev16q_s])
475 ;;
476 (define_insn "@mve_<mve_insn>q_<supf><mode>"
477 [
478 (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w")
479 (unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "w")]
480 VREV16Q))
481 ]
482 "TARGET_HAVE_MVE"
483 "<mve_insn>.<V_sz_elem>\t%q0, %q1"
484 [(set_attr "type" "mve_move")
485 ])
487 ;;
488 ;; [vaddlvq_s vaddlvq_u])
489 ;;
490 (define_insn "@mve_<mve_insn>q_<supf>v4si"
491 [
492 (set (match_operand:DI 0 "s_register_operand" "=r")
493 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")]
494 VADDLVQ))
495 ]
496 "TARGET_HAVE_MVE"
497 "<mve_insn>.<supf>32\t%Q0, %R0, %q1"
498 [(set_attr "type" "mve_move")
499 ])
501 ;;
502 ;; [vctp8q vctp16q vctp32q vctp64q])
503 ;;
504 (define_insn "mve_vctp<MVE_vctp>q<MVE_vpred>"
505 [
506 (set (match_operand:MVE_7 0 "vpr_register_operand" "=Up")
507 (unspec:MVE_7 [(match_operand:SI 1 "s_register_operand" "r")]
508 VCTP))
509 ]
510 "TARGET_HAVE_MVE"
511 "vctp.<MVE_vctp>\t%1"
512 [(set_attr "type" "mve_move")
513 ])
515 ;;
516 ;; [vpnot])
517 ;;
518 (define_insn "mve_vpnotv16bi"
519 [
520 (set (match_operand:V16BI 0 "vpr_register_operand" "=Up")
521 (unspec:V16BI [(match_operand:V16BI 1 "vpr_register_operand" "0")]
522 VPNOT))
523 ]
524 "TARGET_HAVE_MVE"
525 "vpnot"
526 [(set_attr "type" "mve_move")
527 ])
529 ;;
530 ;; [vbrsrq_n_f])
531 ;;
532 (define_insn "@mve_<mve_insn>q_n_f<mode>"
533 [
534 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
535 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
536 (match_operand:SI 2 "s_register_operand" "r")]
537 MVE_VBRSR_N_FP))
538 ]
539 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
540 "<mve_insn>.<V_sz_elem>\t%q0, %q1, %2"
541 [(set_attr "type" "mve_move")
542 ])
544 ;;
545 ;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u])
546 ;;
547 (define_insn "mve_vcvtq_n_to_f_<supf><mode>"
548 [
549 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
550 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
551 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
552 VCVTQ_N_TO_F))
553 ]
554 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
555 "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2"
556 [(set_attr "type" "mve_move")
557 ])
559 ;; [vcreateq_f])
560 ;;
561 (define_insn "@mve_<mve_insn>q_f<mode>"
562 [
563 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
564 (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r")
565 (match_operand:DI 2 "s_register_operand" "r")]
566 MVE_FP_CREATE_ONLY))
567 ]
568 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
569 "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2"
570 [(set_attr "type" "mve_move")
571 (set_attr "length""8")])
573 ;;
574 ;; [vcreateq_u, vcreateq_s])
575 ;;
576 (define_insn "@mve_<mve_insn>q_<supf><mode>"
577 [
578 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
579 (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r")
580 (match_operand:DI 2 "s_register_operand" "r")]
581 VCREATEQ))
582 ]
583 "TARGET_HAVE_MVE"
584 "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2"
585 [(set_attr "type" "mve_move")
586 (set_attr "length""8")])
588 ;;
589 ;; [vrshrq_n_s, vrshrq_n_u]
590 ;; [vshrq_n_s, vshrq_n_u]
591 ;;
592 ;; Version that takes an immediate as operand 2.
593 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
594 [
595 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
596 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
597 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
598 MVE_VSHRQ_N))
599 ]
600 "TARGET_HAVE_MVE"
601 "<mve_insn>.<supf><V_sz_elem>\t%q0, %q1, %2"
602 [(set_attr "type" "mve_move")
603 ])
605 ;; Versions that take constant vectors as operand 2 (with all elements
606 ;; equal).
607 (define_insn "mve_vshrq_n_s<mode>_imm"
608 [
609 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
610 (ashiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
611 (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i")))
612 ]
613 "TARGET_HAVE_MVE"
614 {
615 return neon_output_shift_immediate ("vshr", 's', &operands[2],
616 <MODE>mode,
617 VALID_NEON_QREG_MODE (<MODE>mode),
618 true);
619 }
620 [(set_attr "type" "mve_move")
621 ])
622 (define_insn "mve_vshrq_n_u<mode>_imm"
623 [
624 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
625 (lshiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
626 (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i")))
627 ]
628 "TARGET_HAVE_MVE"
629 {
630 return neon_output_shift_immediate ("vshr", 'u', &operands[2],
631 <MODE>mode,
632 VALID_NEON_QREG_MODE (<MODE>mode),
633 true);
634 }
635 [(set_attr "type" "mve_move")
636 ])
638 ;;
639 ;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u])
640 ;;
641 (define_insn "mve_vcvtq_n_from_f_<supf><mode>"
642 [
643 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
644 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")
645 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
646 VCVTQ_N_FROM_F))
647 ]
648 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
649 "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2"
650 [(set_attr "type" "mve_move")
651 ])
653 ;;
654 ;; [vaddlvq_p_s])
655 ;;
656 (define_insn "@mve_<mve_insn>q_p_<supf>v4si"
657 [
658 (set (match_operand:DI 0 "s_register_operand" "=r")
659 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
660 (match_operand:V4BI 2 "vpr_register_operand" "Up")]
661 VADDLVQ_P))
662 ]
663 "TARGET_HAVE_MVE"
664 "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q1"
665 [(set_attr "type" "mve_move")
666 (set_attr "length""8")])
668 ;;
669 ;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_])
670 ;;
671 (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>"
672 [
673 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
674 (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1 "s_register_operand" "w")
675 (match_operand:MVE_2 2 "s_register_operand" "w")))
676 ]
677 "TARGET_HAVE_MVE"
678 "vcmp.<mve_cmp_type>%#<V_sz_elem>\t<mve_cmp_op>, %q1, %q2"
679 [(set_attr "type" "mve_move")
680 ])
682 ;;
683 ;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_])
684 ;;
685 (define_insn "@mve_vcmp<mve_cmp_op>q_n_<mode>"
686 [
687 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
688 (MVE_COMPARISONS:<MVE_VPRED>
689 (match_operand:MVE_2 1 "s_register_operand" "w")
690 (vec_duplicate:MVE_2 (match_operand:<V_elem> 2 "s_register_operand" "r"))))
691 ]
692 "TARGET_HAVE_MVE"
693 "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %2"
694 [(set_attr "type" "mve_move")
695 ])
697 ;;
698 ;; [vshlq_s, vshlq_u])
699 ;; See vec-common.md
701 ;;
702 ;; [vabdq_s, vabdq_u]
703 ;; [vhaddq_s, vhaddq_u]
704 ;; [vhsubq_s, vhsubq_u]
705 ;; [vmulhq_s, vmulhq_u]
706 ;; [vqaddq_u, vqaddq_s]
707 ;; [vqdmulhq_s]
708 ;; [vqrdmulhq_s]
709 ;; [vqrshlq_s, vqrshlq_u]
710 ;; [vqshlq_s, vqshlq_u]
711 ;; [vqsubq_u, vqsubq_s]
712 ;; [vrhaddq_s, vrhaddq_u]
713 ;; [vrmulhq_s, vrmulhq_u]
714 ;; [vrshlq_s, vrshlq_u]
715 ;;
716 (define_insn "@mve_<mve_insn>q_<supf><mode>"
717 [
718 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
719 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
720 (match_operand:MVE_2 2 "s_register_operand" "w")]
721 MVE_INT_SU_BINARY))
722 ]
723 "TARGET_HAVE_MVE"
724 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
725 [(set_attr "type" "mve_move")
726 ])
728 ;;
729 ;; [vaddq_n_s, vaddq_n_u]
730 ;; [vsubq_n_s, vsubq_n_u]
731 ;; [vmulq_n_s, vmulq_n_u]
732 ;;
733 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
734 [
735 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
736 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
737 (match_operand:<V_elem> 2 "s_register_operand" "r")]
738 MVE_INT_N_BINARY))
739 ]
740 "TARGET_HAVE_MVE"
741 "<mve_insn>.i%#<V_sz_elem>\t%q0, %q1, %2"
742 [(set_attr "type" "mve_move")
743 ])
745 ;;
746 ;; [vaddvaq_s, vaddvaq_u])
747 ;;
748 (define_insn "@mve_<mve_insn>q_<supf><mode>"
749 [
750 (set (match_operand:SI 0 "s_register_operand" "=Te")
751 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
752 (match_operand:MVE_2 2 "s_register_operand" "w")]
753 VADDVAQ))
754 ]
755 "TARGET_HAVE_MVE"
756 "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2"
757 [(set_attr "type" "mve_move")
758 ])
760 ;;
761 ;; [vaddvq_p_u, vaddvq_p_s])
762 ;;
763 (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
764 [
765 (set (match_operand:SI 0 "s_register_operand" "=Te")
766 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
767 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
768 VADDVQ_P))
769 ]
770 "TARGET_HAVE_MVE"
771 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q1"
772 [(set_attr "type" "mve_move")
773 (set_attr "length""8")])
775 ;;
776 ;; [vandq_u, vandq_s])
777 ;;
778 ;; signed and unsigned versions are the same: define the unsigned
779 ;; insn, and use an expander for the signed one as we still reference
780 ;; both names from arm_mve.h.
781 ;; We use the same code as in neon.md (TODO: avoid this duplication).
782 (define_insn "mve_vandq_u<mode>"
783 [
784 (set (match_operand:MVE_2 0 "s_register_operand" "=w,w")
785 (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0")
786 (match_operand:MVE_2 2 "neon_inv_logic_op2" "w,DL")))
787 ]
788 "TARGET_HAVE_MVE"
789 "@
790 vand\t%q0, %q1, %q2
791 * return neon_output_logic_immediate (\"vand\", &operands[2], <MODE>mode, 1, VALID_NEON_QREG_MODE (<MODE>mode));"
792 [(set_attr "type" "mve_move")
793 ])
794 (define_expand "mve_vandq_s<mode>"
795 [
796 (set (match_operand:MVE_2 0 "s_register_operand")
797 (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
798 (match_operand:MVE_2 2 "neon_inv_logic_op2")))
799 ]
800 "TARGET_HAVE_MVE"
801 )
803 ;;
804 ;; [vbicq_s, vbicq_u])
805 ;;
806 (define_insn "mve_vbicq_u<mode>"
807 [
808 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
809 (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w"))
810 (match_operand:MVE_2 1 "s_register_operand" "w")))
811 ]
812 "TARGET_HAVE_MVE"
813 "vbic\t%q0, %q1, %q2"
814 [(set_attr "type" "mve_move")
815 ])
817 (define_expand "mve_vbicq_s<mode>"
818 [
819 (set (match_operand:MVE_2 0 "s_register_operand")
820 (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand"))
821 (match_operand:MVE_2 1 "s_register_operand")))
822 ]
823 "TARGET_HAVE_MVE"
824 )
826 ;;
827 ;; [vbrsrq_n_u, vbrsrq_n_s])
828 ;;
829 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
830 [
831 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
832 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
833 (match_operand:SI 2 "s_register_operand" "r")]
834 VBRSRQ_N))
835 ]
836 "TARGET_HAVE_MVE"
837 "<mve_insn>.%#<V_sz_elem>\t%q0, %q1, %2"
838 [(set_attr "type" "mve_move")
839 ])
841 ;;
842 ;; [vcaddq_rot90_s, vcaddq_rot90_u]
843 ;; [vcaddq_rot270_s, vcaddq_rot270_u]
844 ;; [vhcaddq_rot90_s]
845 ;; [vhcaddq_rot270_s]
846 ;;
847 (define_insn "@mve_<mve_insn>q<mve_rot>_<supf><mode>"
848 [
849 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
850 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
851 (match_operand:MVE_2 2 "s_register_operand" "w")]
852 VxCADDQ))
853 ]
854 "TARGET_HAVE_MVE"
855 "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q1, %q2, #<rot>"
856 [(set_attr "type" "mve_move")
857 ])
859 ;; Auto vectorizer pattern for int vcadd
860 (define_expand "cadd<rot><mode>3"
861 [(set (match_operand:MVE_2 0 "register_operand")
862 (unspec:MVE_2 [(match_operand:MVE_2 1 "register_operand")
863 (match_operand:MVE_2 2 "register_operand")]
864 VCADD))]
865 "TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN"
866 )
868 ;;
869 ;; [veorq_u, veorq_s])
870 ;;
871 (define_insn "mve_veorq_u<mode>"
872 [
873 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
874 (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
875 (match_operand:MVE_2 2 "s_register_operand" "w")))
876 ]
877 "TARGET_HAVE_MVE"
878 "veor\t%q0, %q1, %q2"
879 [(set_attr "type" "mve_move")
880 ])
881 (define_expand "mve_veorq_s<mode>"
882 [
883 (set (match_operand:MVE_2 0 "s_register_operand")
884 (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
885 (match_operand:MVE_2 2 "s_register_operand")))
886 ]
887 "TARGET_HAVE_MVE"
888 )
890 ;;
891 ;; [vhaddq_n_u, vhaddq_n_s]
892 ;; [vhsubq_n_u, vhsubq_n_s]
893 ;; [vqaddq_n_s, vqaddq_n_u]
894 ;; [vqdmulhq_n_s]
895 ;; [vqrdmulhq_n_s]
896 ;; [vqsubq_n_s, vqsubq_n_u]
897 ;;
898 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
899 [
900 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
901 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
902 (match_operand:<V_elem> 2 "s_register_operand" "r")]
903 MVE_INT_SU_N_BINARY))
904 ]
905 "TARGET_HAVE_MVE"
906 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
907 [(set_attr "type" "mve_move")
908 ])
910 ;;
911 ;; [vmaxaq_s]
912 ;; [vminaq_s]
913 ;;
914 (define_insn "@mve_<mve_insn>q_<supf><mode>"
915 [
916 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
917 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
918 (match_operand:MVE_2 2 "s_register_operand" "w")]
919 MVE_VMAXAVMINAQ))
920 ]
921 "TARGET_HAVE_MVE"
922 "<mve_insn>.s%#<V_sz_elem>\t%q0, %q2"
923 [(set_attr "type" "mve_move")
924 ])
926 ;;
927 ;; [vmaxq_u, vmaxq_s]
928 ;; [vminq_s, vminq_u]
929 ;;
930 (define_insn "mve_<max_min_su_str>q_<max_min_supf><mode>"
931 [
932 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
933 (MAX_MIN_SU:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
934 (match_operand:MVE_2 2 "s_register_operand" "w")))
935 ]
936 "TARGET_HAVE_MVE"
937 "<max_min_su_str>.<max_min_supf>%#<V_sz_elem>\t%q0, %q1, %q2"
938 [(set_attr "type" "mve_move")
939 ])
942 ;;
943 ;; [vmaxavq_s]
944 ;; [vmaxvq_u, vmaxvq_s]
945 ;; [vminavq_s]
946 ;; [vminvq_u, vminvq_s]
947 ;;
948 (define_insn "@mve_<mve_insn>q_<supf><mode>"
949 [
950 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
951 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
952 (match_operand:MVE_2 2 "s_register_operand" "w")]
953 MVE_VMAXVQ_VMINVQ))
954 ]
955 "TARGET_HAVE_MVE"
956 "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2"
957 [(set_attr "type" "mve_move")
958 ])
960 ;;
961 ;; [vmladavq_u, vmladavq_s]
962 ;; [vmladavxq_s]
963 ;; [vmlsdavq_s]
964 ;; [vmlsdavxq_s]
965 ;;
966 (define_insn "@mve_<mve_insn>q_<supf><mode>"
967 [
968 (set (match_operand:SI 0 "s_register_operand" "=Te")
969 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
970 (match_operand:MVE_2 2 "s_register_operand" "w")]
971 MVE_VMLxDAVQ))
972 ]
973 "TARGET_HAVE_MVE"
974 "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
975 [(set_attr "type" "mve_move")
976 ])
978 ;;
979 ;; [vmullbq_int_u, vmullbq_int_s]
980 ;; [vmulltq_int_u, vmulltq_int_s]
981 ;;
982 (define_insn "@mve_<mve_insn>q_int_<supf><mode>"
983 [
984 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
985 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w")
986 (match_operand:MVE_2 2 "s_register_operand" "w")]
987 VMULLxQ_INT))
988 ]
989 "TARGET_HAVE_MVE"
990 "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q1, %q2"
991 [(set_attr "type" "mve_move")
992 ])
994 ;;
995 ;; [vaddq_s, vaddq_u]
996 ;; [vmulq_u, vmulq_s]
997 ;; [vsubq_s, vsubq_u]
998 ;;
999 (define_insn "mve_<mve_addsubmul>q<mode>"
1000 [
1001 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1002 (MVE_INT_BINARY_RTX:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
1003 (match_operand:MVE_2 2 "s_register_operand" "w")))
1004 ]
1005 "TARGET_HAVE_MVE"
1006 "<mve_addsubmul>.i%#<V_sz_elem>\t%q0, %q1, %q2"
1007 [(set_attr "type" "mve_move")
1008 ])
1010 ;;
1011 ;; [vornq_u, vornq_s])
1012 ;;
1013 (define_insn "mve_vornq_s<mode>"
1014 [
1015 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1016 (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w"))
1017 (match_operand:MVE_2 1 "s_register_operand" "w")))
1018 ]
1019 "TARGET_HAVE_MVE"
1020 "vorn\t%q0, %q1, %q2"
1021 [(set_attr "type" "mve_move")
1022 ])
1024 (define_expand "mve_vornq_u<mode>"
1025 [
1026 (set (match_operand:MVE_2 0 "s_register_operand")
1027 (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand"))
1028 (match_operand:MVE_2 1 "s_register_operand")))
1029 ]
1030 "TARGET_HAVE_MVE"
1031 )
1033 ;;
1034 ;; [vorrq_s, vorrq_u])
1035 ;;
1036 ;; signed and unsigned versions are the same: define the unsigned
1037 ;; insn, and use an expander for the signed one as we still reference
1038 ;; both names from arm_mve.h.
1039 ;; We use the same code as in neon.md (TODO: avoid this duplication).
1040 (define_insn "mve_vorrq_s<mode>"
1041 [
1042 (set (match_operand:MVE_2 0 "s_register_operand" "=w,w")
1043 (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0")
1044 (match_operand:MVE_2 2 "neon_logic_op2" "w,Dl")))
1045 ]
1046 "TARGET_HAVE_MVE"
1047 "@
1048 vorr\t%q0, %q1, %q2
1049 * return neon_output_logic_immediate (\"vorr\", &operands[2], <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));"
1050 [(set_attr "type" "mve_move")
1051 ])
1052 (define_expand "mve_vorrq_u<mode>"
1053 [
1054 (set (match_operand:MVE_2 0 "s_register_operand")
1055 (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
1056 (match_operand:MVE_2 2 "neon_logic_op2")))
1057 ]
1058 "TARGET_HAVE_MVE"
1059 )
1061 ;;
1062 ;; [vqrshlq_n_s, vqrshlq_n_u]
1063 ;; [vrshlq_n_u, vrshlq_n_s]
1064 ;;
1065 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1066 [
1067 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1068 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1069 (match_operand:SI 2 "s_register_operand" "r")]
1070 MVE_RSHIFT_N))
1071 ]
1072 "TARGET_HAVE_MVE"
1073 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %2"
1074 [(set_attr "type" "mve_move")
1075 ])
1077 ;;
1078 ;; [vqshlq_n_s, vqshlq_n_u]
1079 ;; [vshlq_n_u, vshlq_n_s]
1080 ;;
1081 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1082 [
1083 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1084 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1085 (match_operand:SI 2 "immediate_operand" "i")]
1086 MVE_SHIFT_N))
1087 ]
1088 "TARGET_HAVE_MVE"
1089 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1090 [(set_attr "type" "mve_move")
1091 ])
1093 ;;
1094 ;; [vqshlq_r_u, vqshlq_r_s]
1095 ;; [vshlq_r_s, vshlq_r_u]
1096 ;;
1097 (define_insn "@mve_<mve_insn>q_r_<supf><mode>"
1098 [
1099 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1100 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1101 (match_operand:SI 2 "s_register_operand" "r")]
1102 MVE_SHIFT_R))
1103 ]
1104 "TARGET_HAVE_MVE"
1105 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %2"
1106 [(set_attr "type" "mve_move")
1107 ])
1109 ;;
1110 ;; [vqshluq_n_s])
1111 ;;
1112 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1113 [
1114 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1115 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
1116 (match_operand:SI 2 "<MVE_pred>" "<MVE_constraint>")]
1117 VQSHLUQ_N))
1118 ]
1119 "TARGET_HAVE_MVE"
1120 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1121 [(set_attr "type" "mve_move")
1122 ])
1124 ;;
1125 ;; [vabdq_f]
1126 ;;
1127 (define_insn "@mve_<mve_insn>q_f<mode>"
1128 [
1129 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1130 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1131 (match_operand:MVE_0 2 "s_register_operand" "w")]
1132 MVE_FP_VABDQ_ONLY))
1133 ]
1134 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1135 "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %q2"
1136 [(set_attr "type" "mve_move")
1137 ])
1139 ;;
1140 ;; [vaddlvaq_s vaddlvaq_u])
1141 ;;
1142 (define_insn "@mve_<mve_insn>q_<supf>v4si"
1143 [
1144 (set (match_operand:DI 0 "s_register_operand" "=r")
1145 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
1146 (match_operand:V4SI 2 "s_register_operand" "w")]
1147 VADDLVAQ))
1148 ]
1149 "TARGET_HAVE_MVE"
1150 "<mve_insn>.<supf>32\t%Q0, %R0, %q2"
1151 [(set_attr "type" "mve_move")
1152 ])
1154 ;;
1155 ;; [vaddq_n_f]
1156 ;; [vsubq_n_f]
1157 ;; [vmulq_n_f]
1158 ;;
1159 (define_insn "@mve_<mve_insn>q_n_f<mode>"
1160 [
1161 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1162 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1163 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1164 MVE_FP_N_BINARY))
1165 ]
1166 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1167 "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %2"
1168 [(set_attr "type" "mve_move")
1169 ])
1171 ;;
1172 ;; [vandq_f])
1173 ;;
1174 (define_insn "mve_vandq_f<mode>"
1175 [
1176 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1177 (and:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
1178 (match_operand:MVE_0 2 "s_register_operand" "w")))
1179 ]
1180 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1181 "vand\t%q0, %q1, %q2"
1182 [(set_attr "type" "mve_move")
1183 ])
1185 ;;
1186 ;; [vbicq_f])
1187 ;;
1188 (define_insn "mve_vbicq_f<mode>"
1189 [
1190 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1191 (and:MVE_0 (not:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))
1192 (match_operand:MVE_0 2 "s_register_operand" "w")))
1193 ]
1194 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1195 "vbic\t%q0, %q1, %q2"
1196 [(set_attr "type" "mve_move")
1197 ])
1199 ;;
1200 ;; [vcaddq_rot90_f, vcaddq_rot270_f]
1201 ;; [vcmulq, vcmulq_rot90, vcmulq_rot180, vcmulq_rot270]
1202 ;;
1203 (define_insn "@mve_<mve_insn>q<mve_rot>_f<mode>"
1204 [
1205 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
1206 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
1207 (match_operand:MVE_0 2 "s_register_operand" "w")]
1208 MVE_VCADDQ_VCMULQ))
1209 ]
1210 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1211 "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %q2, #<rot>"
1212 [(set_attr "type" "mve_move")
1213 ])
1215 ;;
1216 ;; [vcmpeqq_f, vcmpgeq_f, vcmpgtq_f, vcmpleq_f, vcmpltq_f, vcmpneq_f])
1217 ;;
1218 (define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>"
1219 [
1220 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
1221 (MVE_FP_COMPARISONS:<MVE_VPRED> (match_operand:MVE_0 1 "s_register_operand" "w")
1222 (match_operand:MVE_0 2 "s_register_operand" "w")))
1223 ]
1224 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1225 "vcmp.f%#<V_sz_elem> <mve_cmp_op>, %q1, %q2"
1226 [(set_attr "type" "mve_move")
1227 ])
1229 ;;
1230 ;; [vcmpeqq_n_f, vcmpgeq_n_f, vcmpgtq_n_f, vcmpleq_n_f, vcmpltq_n_f, vcmpneq_n_f])
1231 ;;
1232 (define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>"
1233 [
1234 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
1235 (MVE_FP_COMPARISONS:<MVE_VPRED>
1236 (match_operand:MVE_0 1 "s_register_operand" "w")
1237 (vec_duplicate:MVE_0 (match_operand:<V_elem> 2 "s_register_operand" "r"))))
1238 ]
1239 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1240 "vcmp.f%#<V_sz_elem> <mve_cmp_op>, %q1, %2"
1241 [(set_attr "type" "mve_move")
1242 ])
1244 ;;
1245 ;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m])
1246 ;;
1247 (define_insn "mve_vctp<MVE_vctp>q_m<MVE_vpred>"
1248 [
1249 (set (match_operand:MVE_7 0 "vpr_register_operand" "=Up")
1250 (unspec:MVE_7 [(match_operand:SI 1 "s_register_operand" "r")
1251 (match_operand:MVE_7 2 "vpr_register_operand" "Up")]
1252 VCTP_M))
1253 ]
1254 "TARGET_HAVE_MVE"
1255 "vpst\;vctpt.<MVE_vctp>\t%1"
1256 [(set_attr "type" "mve_move")
1257 (set_attr "length""8")])
1259 ;;
1260 ;; [vcvtbq_f16_f32])
1261 ;;
1262 (define_insn "mve_vcvtbq_f16_f32v8hf"
1263 [
1264 (set (match_operand:V8HF 0 "s_register_operand" "=w")
1265 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
1266 (match_operand:V4SF 2 "s_register_operand" "w")]
1267 VCVTBQ_F16_F32))
1268 ]
1269 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1270 "vcvtb.f16.f32\t%q0, %q2"
1271 [(set_attr "type" "mve_move")
1272 ])
1274 ;;
1275 ;; [vcvttq_f16_f32])
1276 ;;
1277 (define_insn "mve_vcvttq_f16_f32v8hf"
1278 [
1279 (set (match_operand:V8HF 0 "s_register_operand" "=w")
1280 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
1281 (match_operand:V4SF 2 "s_register_operand" "w")]
1282 VCVTTQ_F16_F32))
1283 ]
1284 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1285 "vcvtt.f16.f32\t%q0, %q2"
1286 [(set_attr "type" "mve_move")
1287 ])
1289 ;;
1290 ;; [veorq_f])
1291 ;;
1292 (define_insn "mve_veorq_f<mode>"
1293 [
1294 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1295 (xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
1296 (match_operand:MVE_0 2 "s_register_operand" "w")))
1297 ]
1298 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1299 "veor\t%q0, %q1, %q2"
1300 [(set_attr "type" "mve_move")
1301 ])
1303 ;;
1304 ;; [vmaxnmaq_f]
1305 ;; [vminnmaq_f]
1306 ;;
1307 (define_insn "@mve_<mve_insn>q_f<mode>"
1308 [
1309 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1310 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
1311 (match_operand:MVE_0 2 "s_register_operand" "w")]
1312 MVE_VMAXNMA_VMINNMAQ))
1313 ]
1314 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1315 "<mve_insn>.f%#<V_sz_elem>\t%q0, %q2"
1316 [(set_attr "type" "mve_move")
1317 ])
1319 ;;
1320 ;; [vmaxnmavq_f]
1321 ;; [vmaxnmvq_f]
1322 ;; [vminnmavq_f]
1323 ;; [vminnmvq_f]
1324 ;;
1325 (define_insn "@mve_<mve_insn>q_f<mode>"
1326 [
1327 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1328 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1329 (match_operand:MVE_0 2 "s_register_operand" "w")]
1330 MVE_VMAXNMxV_MINNMxVQ))
1331 ]
1332 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1333 "<mve_insn>.f%#<V_sz_elem>\t%0, %q2"
1334 [(set_attr "type" "mve_move")
1335 ])
1337 ;;
1338 ;; [vmaxnmq_f]
1339 ;; [vminnmq_f]
1340 ;;
1341 (define_insn "@mve_<max_min_f_str>q_f<mode>"
1342 [
1343 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1344 (MAX_MIN_F:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
1345 (match_operand:MVE_0 2 "s_register_operand" "w")))
1346 ]
1347 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1348 "<max_min_f_str>.f%#<V_sz_elem> %q0, %q1, %q2"
1349 [(set_attr "type" "mve_move")
1350 ])
1352 ;;
1353 ;; [vmlaldavq_u, vmlaldavq_s]
1354 ;; [vmlaldavxq_s]
1355 ;; [vmlsldavq_s]
1356 ;; [vmlsldavxq_s]
1357 ;;
1358 (define_insn "@mve_<mve_insn>q_<supf><mode>"
1359 [
1360 (set (match_operand:DI 0 "s_register_operand" "=r")
1361 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
1362 (match_operand:MVE_5 2 "s_register_operand" "w")]
1363 MVE_VMLxLDAVxQ))
1364 ]
1365 "TARGET_HAVE_MVE"
1366 "<mve_insn>.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
1367 [(set_attr "type" "mve_move")
1368 ])
1370 ;;
1371 ;; [vmovnbq_u, vmovnbq_s]
1372 ;; [vmovntq_s, vmovntq_u]
1373 ;; [vqmovnbq_u, vqmovnbq_s]
1374 ;; [vqmovntq_u, vqmovntq_s]
1375 ;; [vqmovunbq_s]
1376 ;; [vqmovuntq_s]
1377 ;;
1378 (define_insn "@mve_<mve_insn>q_<supf><mode>"
1379 [
1380 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
1381 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
1382 (match_operand:MVE_5 2 "s_register_operand" "w")]
1383 MVE_MOVN))
1384 ]
1385 "TARGET_HAVE_MVE"
1386 "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q2"
1387 [(set_attr "type" "mve_move")
1388 ])
1390 ;;
1391 ;; [vaddq_f]
1392 ;; [vmulq_f]
1393 ;; [vsubq_f]
1394 ;;
1395 (define_insn "mve_<mve_addsubmul>q_f<mode>"
1396 [
1397 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1398 (MVE_INT_BINARY_RTX:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
1399 (match_operand:MVE_0 2 "s_register_operand" "w")))
1400 ]
1401 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1402 "<mve_addsubmul>.f%#<V_sz_elem>\t%q0, %q1, %q2"
1403 [(set_attr "type" "mve_move")
1404 ])
1406 ;;
1407 ;; [vornq_f])
1408 ;;
1409 (define_insn "mve_vornq_f<mode>"
1410 [
1411 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1412 (ior:MVE_0 (not:MVE_0 (match_operand:MVE_0 2 "s_register_operand" "w"))
1413 (match_operand:MVE_0 1 "s_register_operand" "w")))
1414 ]
1415 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1416 "vorn\t%q0, %q1, %q2"
1417 [(set_attr "type" "mve_move")
1418 ])
1420 ;;
1421 ;; [vorrq_f])
1422 ;;
1423 (define_insn "mve_vorrq_f<mode>"
1424 [
1425 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1426 (ior:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
1427 (match_operand:MVE_0 2 "s_register_operand" "w")))
1428 ]
1429 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1430 "vorr\t%q0, %q1, %q2"
1431 [(set_attr "type" "mve_move")
1432 ])
1434 ;;
1435 ;; [vbicq_n_s, vbicq_n_u]
1436 ;; [vorrq_n_u, vorrq_n_s]
1437 ;;
1438 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1439 [
1440 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1441 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
1442 (match_operand:SI 2 "immediate_operand" "i")]
1443 MVE_INT_N_BINARY_LOGIC))
1444 ]
1445 "TARGET_HAVE_MVE"
1446 "<mve_insn>.i%#<V_sz_elem> %q0, %2"
1447 [(set_attr "type" "mve_move")
1448 ])
1450 ;;
1451 ;; [vqdmullbq_n_s]
1452 ;; [vqdmulltq_n_s]
1453 ;;
1454 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1455 [
1456 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
1457 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
1458 (match_operand:<V_elem> 2 "s_register_operand" "r")]
1459 MVE_VQDMULLxQ_N))
1460 ]
1461 "TARGET_HAVE_MVE"
1462 "<mve_insn>.s%#<V_sz_elem>\t%q0, %q1, %2"
1463 [(set_attr "type" "mve_move")
1464 ])
1466 ;;
1467 ;; [vqdmullbq_s]
1468 ;; [vqdmulltq_s]
1469 ;;
1470 (define_insn "@mve_<mve_insn>q_<supf><mode>"
1471 [
1472 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
1473 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
1474 (match_operand:MVE_5 2 "s_register_operand" "w")]
1475 MVE_VQDMULLxQ))
1476 ]
1477 "TARGET_HAVE_MVE"
1478 "<mve_insn>.s%#<V_sz_elem>\t%q0, %q1, %q2"
1479 [(set_attr "type" "mve_move")
1480 ])
1482 ;;
1483 ;; [vrmlaldavhq_u vrmlaldavhq_s]
1484 ;; [vrmlaldavhxq_s]
1485 ;; [vrmlsldavhq_s]
1486 ;; [vrmlsldavhxq_s]
1487 ;;
1488 (define_insn "@mve_<mve_insn>q_<supf>v4si"
1489 [
1490 (set (match_operand:DI 0 "s_register_operand" "=r")
1491 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
1492 (match_operand:V4SI 2 "s_register_operand" "w")]
1493 MVE_VRMLxLDAVxQ))
1494 ]
1495 "TARGET_HAVE_MVE"
1496 "<mve_insn>.<supf>32\t%Q0, %R0, %q1, %q2"
1497 [(set_attr "type" "mve_move")
1498 ])
1500 ;;
1501 ;; [vshllbq_n_s, vshllbq_n_u]
1502 ;; [vshlltq_n_u, vshlltq_n_s]
1503 ;;
1504 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1505 [
1506 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1507 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
1508 (match_operand:SI 2 "immediate_operand" "i")]
1509 VSHLLxQ_N))
1510 ]
1511 "TARGET_HAVE_MVE"
1512 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
1513 [(set_attr "type" "mve_move")
1514 ])
1516 ;;
1517 ;; [vmulltq_poly_p]
1518 ;; [vmullbq_poly_p]
1519 ;;
1520 (define_insn "@mve_<mve_insn>q_poly_<supf><mode>"
1521 [
1522 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
1523 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")
1524 (match_operand:MVE_3 2 "s_register_operand" "w")]
1525 VMULLxQ_POLY))
1526 ]
1527 "TARGET_HAVE_MVE"
1528 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %q2"
1529 [(set_attr "type" "mve_move")
1530 ])
1532 ;;
1533 ;; [vcmpeqq_m_f]
1534 ;; [vcmpgeq_m_f]
1535 ;; [vcmpgtq_m_f]
1536 ;; [vcmpleq_m_f]
1537 ;; [vcmpltq_m_f]
1538 ;; [vcmpneq_m_f]
1539 ;;
1540 (define_insn "@mve_vcmp<mve_cmp_op1>q_m_f<mode>"
1541 [
1542 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
1543 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
1544 (match_operand:MVE_0 2 "s_register_operand" "w")
1545 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1546 MVE_CMP_M_F))
1547 ]
1548 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1549 "vpst\;vcmpt.f%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %q2"
1550 [(set_attr "type" "mve_move")
1551 (set_attr "length""8")])
1552 ;;
1553 ;; [vcvtaq_m_u, vcvtaq_m_s])
1554 ;;
1555 (define_insn "mve_vcvtaq_m_<supf><mode>"
1556 [
1557 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
1558 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
1559 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
1560 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1561 VCVTAQ_M))
1562 ]
1563 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1564 "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
1565 [(set_attr "type" "mve_move")
1566 (set_attr "length""8")])
1567 ;;
1568 ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u])
1569 ;;
1570 (define_insn "mve_vcvtq_m_to_f_<supf><mode>"
1571 [
1572 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
1573 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
1574 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
1575 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1576 VCVTQ_M_TO_F))
1577 ]
1578 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
1579 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2"
1580 [(set_attr "type" "mve_move")
1581 (set_attr "length""8")])
1583 ;;
1584 ;; [vqrshrnbq_n_u, vqrshrnbq_n_s]
1585 ;; [vqrshrntq_n_u, vqrshrntq_n_s]
1586 ;; [vqrshrunbq_n_s]
1587 ;; [vqrshruntq_n_s]
1588 ;; [vqshrnbq_n_u, vqshrnbq_n_s]
1589 ;; [vqshrntq_n_u, vqshrntq_n_s]
1590 ;; [vqshrunbq_n_s]
1591 ;; [vqshruntq_n_s]
1592 ;; [vrshrnbq_n_s, vrshrnbq_n_u]
1593 ;; [vrshrntq_n_u, vrshrntq_n_s]
1594 ;; [vshrnbq_n_u, vshrnbq_n_s]
1595 ;; [vshrntq_n_s, vshrntq_n_u]
1596 ;;
1597 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1598 [
1599 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
1600 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
1601 (match_operand:MVE_5 2 "s_register_operand" "w")
1602 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")]
1603 MVE_SHRN_N))
1604 ]
1605 "TARGET_HAVE_MVE"
1606 "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q2, %3"
1607 [(set_attr "type" "mve_move")
1608 ])
1610 ;;
1611 ;; [vrmlaldavhaq_s vrmlaldavhaq_u]
1612 ;; [vrmlaldavhaxq_s]
1613 ;; [vrmlsldavhaq_s]
1614 ;; [vrmlsldavhaxq_s]
1615 ;;
1616 (define_insn "@mve_<mve_insn>q_<supf>v4si"
1617 [
1618 (set (match_operand:DI 0 "s_register_operand" "=r")
1619 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
1620 (match_operand:V4SI 2 "s_register_operand" "w")
1621 (match_operand:V4SI 3 "s_register_operand" "w")]
1622 MVE_VRMLxLDAVHAxQ))
1623 ]
1624 "TARGET_HAVE_MVE"
1625 "<mve_insn>.<supf>32\t%Q0, %R0, %q2, %q3"
1626 [(set_attr "type" "mve_move")
1627 ])
1629 ;;
1630 ;; [vabavq_s, vabavq_u])
1631 ;;
1632 (define_insn "@mve_<mve_insn>q_<supf><mode>"
1633 [
1634 (set (match_operand:SI 0 "s_register_operand" "=r")
1635 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1636 (match_operand:MVE_2 2 "s_register_operand" "w")
1637 (match_operand:MVE_2 3 "s_register_operand" "w")]
1638 VABAVQ))
1639 ]
1640 "TARGET_HAVE_MVE"
1641 "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
1642 [(set_attr "type" "mve_move")
1643 ])
1645 ;;
1646 ;; [vshlcq_u vshlcq_s]
1647 ;;
1648 (define_expand "mve_vshlcq_vec_<supf><mode>"
1649 [(match_operand:MVE_2 0 "s_register_operand")
1650 (match_operand:MVE_2 1 "s_register_operand")
1651 (match_operand:SI 2 "s_register_operand")
1652 (match_operand:SI 3 "mve_imm_32")
1653 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
1654 "TARGET_HAVE_MVE"
1655 {
1656 rtx ignore_wb = gen_reg_rtx (SImode);
1657 emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1],
1658 operands[2], operands[3]));
1659 DONE;
1660 })
1662 (define_expand "mve_vshlcq_carry_<supf><mode>"
1663 [(match_operand:SI 0 "s_register_operand")
1664 (match_operand:MVE_2 1 "s_register_operand")
1665 (match_operand:SI 2 "s_register_operand")
1666 (match_operand:SI 3 "mve_imm_32")
1667 (unspec:MVE_2 [(const_int 0)] VSHLCQ)]
1668 "TARGET_HAVE_MVE"
1669 {
1670 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
1671 emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1],
1672 operands[2], operands[3]));
1673 DONE;
1674 })
1676 (define_insn "mve_vshlcq_<supf><mode>"
1677 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
1678 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
1679 (match_operand:SI 3 "s_register_operand" "1")
1680 (match_operand:SI 4 "mve_imm_32" "Rf")]
1681 VSHLCQ))
1682 (set (match_operand:SI 1 "s_register_operand" "=r")
1683 (unspec:SI [(match_dup 2)
1684 (match_dup 3)
1685 (match_dup 4)]
1686 VSHLCQ))]
1687 "TARGET_HAVE_MVE"
1688 "vshlc\t%q0, %1, %4")
1690 ;;
1691 ;; [vabsq_m_s]
1692 ;; [vclsq_m_s]
1693 ;; [vclzq_m_s, vclzq_m_u]
1694 ;; [vnegq_m_s]
1695 ;; [vqabsq_m_s]
1696 ;; [vqnegq_m_s]
1697 ;;
1698 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
1699 [
1700 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1701 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1702 (match_operand:MVE_2 2 "s_register_operand" "w")
1703 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1704 MVE_INT_M_UNARY))
1705 ]
1706 "TARGET_HAVE_MVE"
1707 "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2"
1708 [(set_attr "type" "mve_move")
1709 (set_attr "length""8")])
1711 ;;
1712 ;; [vaddvaq_p_u, vaddvaq_p_s])
1713 ;;
1714 (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
1715 [
1716 (set (match_operand:SI 0 "s_register_operand" "=Te")
1717 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1718 (match_operand:MVE_2 2 "s_register_operand" "w")
1719 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1720 VADDVAQ_P))
1721 ]
1722 "TARGET_HAVE_MVE"
1723 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2"
1724 [(set_attr "type" "mve_move")
1725 (set_attr "length""8")])
1727 ;;
1728 ;; [vcmpcsq_m_n_u])
1729 ;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s])
1730 ;; [vcmpgeq_m_n_s])
1731 ;; [vcmpgtq_m_n_s])
1732 ;; [vcmphiq_m_n_u])
1733 ;; [vcmpleq_m_n_s])
1734 ;; [vcmpltq_m_n_s])
1735 ;; [vcmpneq_m_n_u, vcmpneq_m_n_s])
1736 ;;
1737 (define_insn "@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>"
1738 [
1739 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
1740 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
1741 (match_operand:<V_elem> 2 "s_register_operand" "r")
1742 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1743 MVE_CMP_M_N))
1744 ]
1745 "TARGET_HAVE_MVE"
1746 "vpst\;vcmpt.<isu>%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %2"
1747 [(set_attr "type" "mve_move")
1748 (set_attr "length""8")])
1750 ;;
1751 ;; [vcmpcsq_m_u]
1752 ;; [vcmpeqq_m_u, vcmpeqq_m_s]
1753 ;; [vcmpgeq_m_s]
1754 ;; [vcmpgtq_m_s]
1755 ;; [vcmphiq_m_u]
1756 ;; [vcmpleq_m_s]
1757 ;; [vcmpltq_m_s]
1758 ;; [vcmpneq_m_s, vcmpneq_m_u]
1759 ;;
1760 (define_insn "@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>"
1761 [
1762 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
1763 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
1764 (match_operand:MVE_2 2 "s_register_operand" "w")
1765 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1766 MVE_CMP_M))
1767 ]
1768 "TARGET_HAVE_MVE"
1769 "vpst\;vcmpt.<isu>%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %q2"
1770 [(set_attr "type" "mve_move")
1771 (set_attr "length""8")])
1773 ;;
1774 ;; [vdupq_m_n_s, vdupq_m_n_u])
1775 ;;
1776 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
1777 [
1778 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1779 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1780 (match_operand:<V_elem> 2 "s_register_operand" "r")
1781 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1782 VDUPQ_M_N))
1783 ]
1784 "TARGET_HAVE_MVE"
1785 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %2"
1786 [(set_attr "type" "mve_move")
1787 (set_attr "length""8")])
1789 ;;
1790 ;; [vmaxaq_m_s]
1791 ;; [vminaq_m_s]
1792 ;;
1793 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
1794 [
1795 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1796 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1797 (match_operand:MVE_2 2 "s_register_operand" "w")
1798 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1799 MVE_VMAXAVMINAQ_M))
1800 ]
1801 "TARGET_HAVE_MVE"
1802 "vpst\;<mve_insn>t.s%#<V_sz_elem>\t%q0, %q2"
1803 [(set_attr "type" "mve_move")
1804 (set_attr "length""8")])
1806 ;;
1807 ;; [vmaxavq_p_s]
1808 ;; [vmaxvq_p_u, vmaxvq_p_s]
1809 ;; [vminavq_p_s]
1810 ;; [vminvq_p_s, vminvq_p_u]
1811 ;;
1812 (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
1813 [
1814 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
1815 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
1816 (match_operand:MVE_2 2 "s_register_operand" "w")
1817 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1818 MVE_VMAXVQ_VMINVQ_P))
1819 ]
1820 "TARGET_HAVE_MVE"
1821 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2"
1822 [(set_attr "type" "mve_move")
1823 (set_attr "length""8")])
1825 ;;
1826 ;; [vmladavaq_u, vmladavaq_s]
1827 ;; [vmladavaxq_s]
1828 ;; [vmlsdavaq_s]
1829 ;; [vmlsdavaxq_s]
1830 ;;
1831 (define_insn "@mve_<mve_insn>q_<supf><mode>"
1832 [
1833 (set (match_operand:SI 0 "s_register_operand" "=Te")
1834 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
1835 (match_operand:MVE_2 2 "s_register_operand" "w")
1836 (match_operand:MVE_2 3 "s_register_operand" "w")]
1837 MVE_VMLxDAVAQ))
1838 ]
1839 "TARGET_HAVE_MVE"
1840 "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
1841 [(set_attr "type" "mve_move")
1842 ])
1844 ;;
1845 ;; [vmladavq_p_u, vmladavq_p_s]
1846 ;; [vmladavxq_p_s]
1847 ;; [vmlsdavq_p_s]
1848 ;; [vmlsdavxq_p_s]
1849 ;;
1850 (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
1851 [
1852 (set (match_operand:SI 0 "s_register_operand" "=Te")
1853 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
1854 (match_operand:MVE_2 2 "s_register_operand" "w")
1855 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1856 MVE_VMLxDAVQ_P))
1857 ]
1858 "TARGET_HAVE_MVE"
1859 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
1860 [(set_attr "type" "mve_move")
1861 (set_attr "length""8")])
1863 ;;
1864 ;; [vmlaq_n_u, vmlaq_n_s]
1865 ;; [vmlasq_n_u, vmlasq_n_s]
1866 ;; [vqdmlahq_n_s]
1867 ;; [vqdmlashq_n_s]
1868 ;; [vqrdmlahq_n_s]
1869 ;; [vqrdmlashq_n_s]
1870 ;;
1871 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1872 [
1873 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1874 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1875 (match_operand:MVE_2 2 "s_register_operand" "w")
1876 (match_operand:<V_elem> 3 "s_register_operand" "r")]
1877 MVE_VMLxQ_N))
1878 ]
1879 "TARGET_HAVE_MVE"
1880 "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
1881 [(set_attr "type" "mve_move")
1882 ])
1884 ;;
1885 ;; [vmvnq_m_s, vmvnq_m_u])
1886 ;;
1887 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
1888 [
1889 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1890 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1891 (match_operand:MVE_2 2 "s_register_operand" "w")
1892 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1893 VMVNQ_M))
1894 ]
1895 "TARGET_HAVE_MVE"
1896 "vpst\;<mve_insn>t\t%q0, %q2"
1897 [(set_attr "type" "mve_move")
1898 (set_attr "length""8")])
1900 ;;
1901 ;; [vpselq_u, vpselq_s])
1902 ;;
1903 (define_insn "@mve_<mve_insn>q_<supf><mode>"
1904 [
1905 (set (match_operand:MVE_1 0 "s_register_operand" "=w")
1906 (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w")
1907 (match_operand:MVE_1 2 "s_register_operand" "w")
1908 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1909 VPSELQ))
1910 ]
1911 "TARGET_HAVE_MVE"
1912 "<mve_insn>\t%q0, %q1, %q2"
1913 [(set_attr "type" "mve_move")
1914 ])
1916 ;;
1917 ;; [vqdmladhq_s]
1918 ;; [vqdmladhxq_s]
1919 ;; [vqdmlsdhq_s]
1920 ;; [vqdmlsdhxq_s]
1921 ;; [vqrdmladhq_s]
1922 ;; [vqrdmladhxq_s]
1923 ;; [vqrdmlsdhq_s]
1924 ;; [vqrdmlsdhxq_s]
1925 ;;
1926 (define_insn "@mve_<mve_insn>q_<supf><mode>"
1927 [
1928 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1929 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1930 (match_operand:MVE_2 2 "s_register_operand" "w")
1931 (match_operand:MVE_2 3 "s_register_operand" "w")]
1932 MVE_VQxDMLxDHxQ_S))
1933 ]
1934 "TARGET_HAVE_MVE"
1935 "<mve_insn>.s%#<V_sz_elem>\t%q0, %q2, %q3"
1936 [(set_attr "type" "mve_move")
1937 ])
1939 ;;
1940 ;; [vqrshlq_m_n_s, vqrshlq_m_n_u]
1941 ;; [vrshlq_m_n_s, vrshlq_m_n_u]
1942 ;;
1943 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
1944 [
1945 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1946 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1947 (match_operand:SI 2 "s_register_operand" "r")
1948 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1949 MVE_RSHIFT_M_N))
1950 ]
1951 "TARGET_HAVE_MVE"
1952 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %2"
1953 [(set_attr "type" "mve_move")
1954 (set_attr "length""8")])
1956 ;;
1957 ;; [vqshlq_m_r_u, vqshlq_m_r_s]
1958 ;; [vshlq_m_r_u, vshlq_m_r_s]
1959 ;;
1960 (define_insn "@mve_<mve_insn>q_m_r_<supf><mode>"
1961 [
1962 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1963 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1964 (match_operand:SI 2 "s_register_operand" "r")
1965 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1966 MVE_SHIFT_M_R))
1967 ]
1968 "TARGET_HAVE_MVE"
1969 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %2"
1970 [(set_attr "type" "mve_move")
1971 (set_attr "length""8")])
1973 ;;
1974 ;; [vrev64q_m_u, vrev64q_m_s])
1975 ;;
1976 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
1977 [
1978 (set (match_operand:MVE_2 0 "s_register_operand" "=&w")
1979 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1980 (match_operand:MVE_2 2 "s_register_operand" "w")
1981 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
1982 VREV64Q_M))
1983 ]
1984 "TARGET_HAVE_MVE"
1985 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
1986 [(set_attr "type" "mve_move")
1987 (set_attr "length""8")])
1989 ;;
1990 ;; [vsliq_n_u, vsliq_n_s])
1991 ;;
1992 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
1993 [
1994 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
1995 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
1996 (match_operand:MVE_2 2 "s_register_operand" "w")
1997 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")]
1998 VSLIQ_N))
1999 ]
2000 "TARGET_HAVE_MVE"
2001 "<mve_insn>.%#<V_sz_elem>\t%q0, %q2, %3"
2002 [(set_attr "type" "mve_move")
2003 ])
2005 ;;
2006 ;; [vsriq_n_u, vsriq_n_s])
2007 ;;
2008 (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
2009 [
2010 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2011 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2012 (match_operand:MVE_2 2 "s_register_operand" "w")
2013 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")]
2014 VSRIQ_N))
2015 ]
2016 "TARGET_HAVE_MVE"
2017 "<mve_insn>.%#<V_sz_elem>\t%q0, %q2, %3"
2018 [(set_attr "type" "mve_move")
2019 ])
2021 ;;
2022 ;; [vabsq_m_f]
2023 ;; [vnegq_m_f]
2024 ;; [vrndaq_m_f]
2025 ;; [vrndmq_m_f]
2026 ;; [vrndnq_m_f]
2027 ;; [vrndpq_m_f]
2028 ;; [vrndq_m_f]
2029 ;; [vrndxq_m_f]
2030 ;;
2031 (define_insn "@mve_<mve_insn>q_m_f<mode>"
2032 [
2033 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2034 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2035 (match_operand:MVE_0 2 "s_register_operand" "w")
2036 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2037 MVE_FP_M_UNARY))
2038 ]
2039 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2040 "vpst\;<mve_mnemo>t.f%#<V_sz_elem>\t%q0, %q2"
2041 [(set_attr "type" "mve_move")
2042 (set_attr "length""8")])
2044 ;;
2045 ;; [vaddlvaq_p_s vaddlvaq_p_u])
2046 ;;
2047 (define_insn "@mve_<mve_insn>q_p_<supf>v4si"
2048 [
2049 (set (match_operand:DI 0 "s_register_operand" "=r")
2050 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2051 (match_operand:V4SI 2 "s_register_operand" "w")
2052 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
2053 VADDLVAQ_P))
2054 ]
2055 "TARGET_HAVE_MVE"
2056 "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q2"
2057 [(set_attr "type" "mve_move")
2058 (set_attr "length""8")])
2059 ;;
2060 ;; [vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270])
2061 ;;
2062 (define_insn "@mve_<mve_insn>q<mve_rot>_f<mode>"
2063 [
2064 (set (match_operand:MVE_0 0 "s_register_operand" "=w,w")
2065 (plus:MVE_0 (match_operand:MVE_0 1 "reg_or_zero_operand" "Dz,0")
2066 (unspec:MVE_0
2067 [(match_operand:MVE_0 2 "s_register_operand" "w,w")
2068 (match_operand:MVE_0 3 "s_register_operand" "w,w")]
2069 VCMLA)))
2070 ]
2071 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2072 "@
2073 vcmul.f%#<V_sz_elem> %q0, %q2, %q3, #<rot>
2074 vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #<rot>"
2075 [(set_attr "type" "mve_move")
2076 ])
2078 ;;
2079 ;; [vcmpeqq_m_n_f])
2080 ;; [vcmpgeq_m_n_f])
2081 ;; [vcmpgtq_m_n_f])
2082 ;; [vcmpleq_m_n_f])
2083 ;; [vcmpltq_m_n_f])
2084 ;; [vcmpneq_m_n_f])
2085 ;;
2086 (define_insn "@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>"
2087 [
2088 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
2089 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
2090 (match_operand:<V_elem> 2 "s_register_operand" "r")
2091 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2092 MVE_CMP_M_N_F))
2093 ]
2094 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2095 "vpst\;vcmpt.f%#<V_sz_elem>\t<mve_cmp_op1>, %q1, %2"
2096 [(set_attr "type" "mve_move")
2097 (set_attr "length""8")])
2099 ;;
2100 ;; [vcvtbq_m_f16_f32])
2101 ;;
2102 (define_insn "mve_vcvtbq_m_f16_f32v8hf"
2103 [
2104 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2105 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2106 (match_operand:V4SF 2 "s_register_operand" "w")
2107 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2108 VCVTBQ_M_F16_F32))
2109 ]
2110 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2111 "vpst\;vcvtbt.f16.f32\t%q0, %q2"
2112 [(set_attr "type" "mve_move")
2113 (set_attr "length""8")])
2115 ;;
2116 ;; [vcvtbq_m_f32_f16])
2117 ;;
2118 (define_insn "mve_vcvtbq_m_f32_f16v4sf"
2119 [
2120 (set (match_operand:V4SF 0 "s_register_operand" "=w")
2121 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
2122 (match_operand:V8HF 2 "s_register_operand" "w")
2123 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2124 VCVTBQ_M_F32_F16))
2125 ]
2126 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2127 "vpst\;vcvtbt.f32.f16\t%q0, %q2"
2128 [(set_attr "type" "mve_move")
2129 (set_attr "length""8")])
2131 ;;
2132 ;; [vcvttq_m_f16_f32])
2133 ;;
2134 (define_insn "mve_vcvttq_m_f16_f32v8hf"
2135 [
2136 (set (match_operand:V8HF 0 "s_register_operand" "=w")
2137 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
2138 (match_operand:V4SF 2 "s_register_operand" "w")
2139 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2140 VCVTTQ_M_F16_F32))
2141 ]
2142 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2143 "vpst\;vcvttt.f16.f32\t%q0, %q2"
2144 [(set_attr "type" "mve_move")
2145 (set_attr "length""8")])
2147 ;;
2148 ;; [vcvttq_m_f32_f16])
2149 ;;
2150 (define_insn "mve_vcvttq_m_f32_f16v4sf"
2151 [
2152 (set (match_operand:V4SF 0 "s_register_operand" "=w")
2153 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
2154 (match_operand:V8HF 2 "s_register_operand" "w")
2155 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2156 VCVTTQ_M_F32_F16))
2157 ]
2158 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2159 "vpst\;vcvttt.f32.f16\t%q0, %q2"
2160 [(set_attr "type" "mve_move")
2161 (set_attr "length""8")])
2163 ;;
2164 ;; [vdupq_m_n_f])
2165 ;;
2166 (define_insn "@mve_<mve_insn>q_m_n_f<mode>"
2167 [
2168 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2169 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2170 (match_operand:<V_elem> 2 "s_register_operand" "r")
2171 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2172 MVE_FP_M_N_VDUPQ_ONLY))
2173 ]
2174 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2175 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %2"
2176 [(set_attr "type" "mve_move")
2177 (set_attr "length""8")])
2179 ;;
2180 ;; [vfmaq_f]
2181 ;; [vfmsq_f]
2182 ;;
2183 (define_insn "@mve_<mve_insn>q_f<mode>"
2184 [
2185 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2186 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2187 (match_operand:MVE_0 2 "s_register_operand" "w")
2188 (match_operand:MVE_0 3 "s_register_operand" "w")]
2189 MVE_VFMxQ_F))
2190 ]
2191 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2192 "<mve_insn>.f%#<V_sz_elem>\t%q0, %q2, %q3"
2193 [(set_attr "type" "mve_move")
2194 ])
2196 ;;
2197 ;; [vfmaq_n_f]
2198 ;; [vfmasq_n_f]
2199 ;;
2200 (define_insn "@mve_<mve_insn>q_n_f<mode>"
2201 [
2202 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2203 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2204 (match_operand:MVE_0 2 "s_register_operand" "w")
2205 (match_operand:<V_elem> 3 "s_register_operand" "r")]
2206 MVE_VFMAxQ_N_F))
2207 ]
2208 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2209 "<mve_insn>.f%#<V_sz_elem>\t%q0, %q2, %3"
2210 [(set_attr "type" "mve_move")
2211 ])
2213 ;;
2214 ;; [vmaxnmaq_m_f]
2215 ;; [vminnmaq_m_f]
2216 ;;
2217 (define_insn "@mve_<mve_insn>q_m_f<mode>"
2218 [
2219 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2220 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2221 (match_operand:MVE_0 2 "s_register_operand" "w")
2222 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2223 MVE_VMAXNMA_VMINNMAQ_M))
2224 ]
2225 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2226 "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2"
2227 [(set_attr "type" "mve_move")
2228 (set_attr "length""8")])
2230 ;;
2231 ;; [vmaxnmavq_p_f]
2232 ;; [vmaxnmvq_p_f]
2233 ;; [vminnmavq_p_f]
2234 ;; [vminnmvq_p_f]
2235 ;;
2236 (define_insn "@mve_<mve_insn>q_p_f<mode>"
2237 [
2238 (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
2239 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
2240 (match_operand:MVE_0 2 "s_register_operand" "w")
2241 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2242 MVE_VMAXNMxV_MINNMxVQ_P))
2243 ]
2244 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2245 "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%0, %q2"
2246 [(set_attr "type" "mve_move")
2247 (set_attr "length""8")])
2249 ;;
2250 ;; [vmlaldavaq_s, vmlaldavaq_u]
2251 ;; [vmlaldavaxq_s]
2252 ;; [vmlsldavaq_s]
2253 ;; [vmlsldavaxq_s]
2254 ;;
2255 (define_insn "@mve_<mve_insn>q_<supf><mode>"
2256 [
2257 (set (match_operand:DI 0 "s_register_operand" "=r")
2258 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2259 (match_operand:MVE_5 2 "s_register_operand" "w")
2260 (match_operand:MVE_5 3 "s_register_operand" "w")]
2261 MVE_VMLxLDAVAxQ))
2262 ]
2263 "TARGET_HAVE_MVE"
2264 "<mve_insn>.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
2265 [(set_attr "type" "mve_move")
2266 ])
2268 ;;
2269 ;; [vmlaldavq_p_u, vmlaldavq_p_s]
2270 ;; [vmlaldavxq_p_s]
2271 ;; [vmlsldavq_p_s]
2272 ;; [vmlsldavxq_p_s]
2273 ;;
2274 (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
2275 [
2276 (set (match_operand:DI 0 "s_register_operand" "=r")
2277 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w")
2278 (match_operand:MVE_5 2 "s_register_operand" "w")
2279 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2280 MVE_VMLxLDAVxQ_P))
2281 ]
2282 "TARGET_HAVE_MVE"
2283 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2"
2284 [(set_attr "type" "mve_move")
2285 (set_attr "length""8")])
2287 ;;
2288 ;; [vmovlbq_m_u, vmovlbq_m_s])
2289 ;; [vmovltq_m_u, vmovltq_m_s])
2290 ;;
2291 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
2292 [
2293 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2294 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
2295 (match_operand:MVE_3 2 "s_register_operand" "w")
2296 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2297 VMOVLxQ_M))
2298 ]
2299 "TARGET_HAVE_MVE"
2300 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2"
2301 [(set_attr "type" "mve_move")
2302 (set_attr "length""8")])
2304 ;;
2305 ;; [vmovnbq_m_u, vmovnbq_m_s]
2306 ;; [vmovntq_m_u, vmovntq_m_s]
2307 ;; [vqmovnbq_m_s, vqmovnbq_m_u]
2308 ;; [vqmovntq_m_u, vqmovntq_m_s]
2309 ;; [vqmovunbq_m_s]
2310 ;; [vqmovuntq_m_s]
2311 ;;
2312 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
2313 [
2314 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2315 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2316 (match_operand:MVE_5 2 "s_register_operand" "w")
2317 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2318 MVE_MOVN_M))
2319 ]
2320 "TARGET_HAVE_MVE"
2321 "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2"
2322 [(set_attr "type" "mve_move")
2323 (set_attr "length""8")])
2325 ;;
2326 ;; [vmvnq_m_n_u, vmvnq_m_n_s])
2327 ;;
2328 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2329 [
2330 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2331 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2332 (match_operand:SI 2 "immediate_operand" "i")
2333 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2334 VMVNQ_M_N))
2335 ]
2336 "TARGET_HAVE_MVE"
2337 "vpst\;<mve_insn>t.i%#<V_sz_elem>\t%q0, %2"
2338 [(set_attr "type" "mve_move")
2339 (set_attr "length""8")])
2341 ;;
2342 ;; [vbicq_m_n_s, vbicq_m_n_u]
2343 ;; [vorrq_m_n_s, vorrq_m_n_u]
2344 ;;
2345 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2346 [
2347 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2348 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2349 (match_operand:SI 2 "immediate_operand" "i")
2350 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2351 MVE_INT_M_N_BINARY_LOGIC))
2352 ]
2353 "TARGET_HAVE_MVE"
2354 "vpst\;<mve_insn>t.i%#<V_sz_elem>\t%q0, %2"
2355 [(set_attr "type" "mve_move")
2356 (set_attr "length""8")])
2358 ;;
2359 ;; [vpselq_f])
2360 ;;
2361 (define_insn "@mve_<mve_insn>q_f<mode>"
2362 [
2363 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2364 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
2365 (match_operand:MVE_0 2 "s_register_operand" "w")
2366 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2367 MVE_VPSELQ_F))
2368 ]
2369 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2370 "<mve_insn>\t%q0, %q1, %q2"
2371 [(set_attr "type" "mve_move")
2372 ])
2374 ;;
2375 ;; [vrev32q_m_f])
2376 ;;
2377 (define_insn "@mve_<mve_insn>q_m_f<mode>"
2378 [
2379 (set (match_operand:MVE_V8HF 0 "s_register_operand" "=w")
2380 (unspec:MVE_V8HF [(match_operand:MVE_V8HF 1 "s_register_operand" "0")
2381 (match_operand:MVE_V8HF 2 "s_register_operand" "w")
2382 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2383 MVE_FP_M_VREV32Q_ONLY))
2384 ]
2385 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2386 "vpst\;<mve_insn>t.<V_sz_elem>\t%q0, %q2"
2387 [(set_attr "type" "mve_move")
2388 (set_attr "length""8")])
2390 ;;
2391 ;; [vrev32q_m_s, vrev32q_m_u])
2392 ;;
2393 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
2394 [
2395 (set (match_operand:MVE_3 0 "s_register_operand" "=w")
2396 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0")
2397 (match_operand:MVE_3 2 "s_register_operand" "w")
2398 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2399 VREV32Q_M))
2400 ]
2401 "TARGET_HAVE_MVE"
2402 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
2403 [(set_attr "type" "mve_move")
2404 (set_attr "length""8")])
2406 ;;
2407 ;; [vrev64q_m_f])
2408 ;;
2409 (define_insn "@mve_<mve_insn>q_m_f<mode>"
2410 [
2411 (set (match_operand:MVE_0 0 "s_register_operand" "=&w")
2412 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2413 (match_operand:MVE_0 2 "s_register_operand" "w")
2414 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2415 MVE_FP_M_VREV64Q_ONLY))
2416 ]
2417 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2418 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2"
2419 [(set_attr "type" "mve_move")
2420 (set_attr "length""8")])
2422 ;;
2423 ;; [vrmlaldavhq_p_u vrmlaldavhq_p_s]
2424 ;; [vrmlaldavhxq_p_s]
2425 ;; [vrmlsldavhq_p_s]
2426 ;; [vrmlsldavhxq_p_s]
2427 ;;
2428 (define_insn "@mve_<mve_insn>q_p_<supf>v4si"
2429 [
2430 (set (match_operand:DI 0 "s_register_operand" "=r")
2431 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
2432 (match_operand:V4SI 2 "s_register_operand" "w")
2433 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
2434 MVE_VRMLxLDAVHxQ_P))
2435 ]
2436 "TARGET_HAVE_MVE"
2437 "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q1, %q2"
2438 [(set_attr "type" "mve_move")
2439 (set_attr "length""8")])
2441 ;;
2442 ;; [vcvtmq_m_s, vcvtmq_m_u])
2443 ;;
2444 (define_insn "mve_vcvtmq_m_<supf><mode>"
2445 [
2446 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2447 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2448 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
2449 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2450 VCVTMQ_M))
2451 ]
2452 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2453 "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
2454 [(set_attr "type" "mve_move")
2455 (set_attr "length""8")])
2457 ;;
2458 ;; [vcvtpq_m_u, vcvtpq_m_s])
2459 ;;
2460 (define_insn "mve_vcvtpq_m_<supf><mode>"
2461 [
2462 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2463 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2464 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
2465 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2466 VCVTPQ_M))
2467 ]
2468 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2469 "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
2470 [(set_attr "type" "mve_move")
2471 (set_attr "length""8")])
2473 ;;
2474 ;; [vcvtnq_m_s, vcvtnq_m_u])
2475 ;;
2476 (define_insn "mve_vcvtnq_m_<supf><mode>"
2477 [
2478 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2479 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2480 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
2481 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2482 VCVTNQ_M))
2483 ]
2484 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2485 "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
2486 [(set_attr "type" "mve_move")
2487 (set_attr "length""8")])
2489 ;;
2490 ;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u])
2491 ;;
2492 (define_insn "mve_vcvtq_m_n_from_f_<supf><mode>"
2493 [
2494 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2495 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2496 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
2497 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
2498 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2499 VCVTQ_M_N_FROM_F))
2500 ]
2501 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2502 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3"
2503 [(set_attr "type" "mve_move")
2504 (set_attr "length""8")])
2506 ;;
2507 ;; [vrev16q_m_u, vrev16q_m_s])
2508 ;;
2509 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
2510 [
2511 (set (match_operand:MVE_V16QI 0 "s_register_operand" "=w")
2512 (unspec:MVE_V16QI [(match_operand:MVE_V16QI 1 "s_register_operand" "0")
2513 (match_operand:MVE_V16QI 2 "s_register_operand" "w")
2514 (match_operand:V16BI 3 "vpr_register_operand" "Up")]
2515 VREV16Q_M))
2516 ]
2517 "TARGET_HAVE_MVE"
2518 "vpst\;<mve_insn>t.<V_sz_elem>\t%q0, %q2"
2519 [(set_attr "type" "mve_move")
2520 (set_attr "length""8")])
2522 ;;
2523 ;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s])
2524 ;;
2525 (define_insn "mve_vcvtq_m_from_f_<supf><mode>"
2526 [
2527 (set (match_operand:MVE_5 0 "s_register_operand" "=w")
2528 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
2529 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
2530 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
2531 VCVTQ_M_FROM_F))
2532 ]
2533 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2534 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2"
2535 [(set_attr "type" "mve_move")
2536 (set_attr "length""8")])
2538 ;;
2539 ;; [vabavq_p_s, vabavq_p_u])
2540 ;;
2541 (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
2542 [
2543 (set (match_operand:SI 0 "s_register_operand" "=r")
2544 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
2545 (match_operand:MVE_2 2 "s_register_operand" "w")
2546 (match_operand:MVE_2 3 "s_register_operand" "w")
2547 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2548 VABAVQ_P))
2549 ]
2550 "TARGET_HAVE_MVE"
2551 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
2552 [(set_attr "type" "mve_move")
2553 (set_attr "length" "8")])
2555 ;;
2556 ;; [vqshluq_m_n_s])
2557 ;;
2558 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2559 [
2560 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2561 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2562 (match_operand:MVE_2 2 "s_register_operand" "w")
2563 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
2564 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2565 VQSHLUQ_M_N))
2566 ]
2567 "TARGET_HAVE_MVE"
2568 "vpst\n\t<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
2569 [(set_attr "type" "mve_move")
2570 (set_attr "length" "8")])
2572 ;;
2573 ;; [vsriq_m_n_s, vsriq_m_n_u])
2574 ;;
2575 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2576 [
2577 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2578 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2579 (match_operand:MVE_2 2 "s_register_operand" "w")
2580 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
2581 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2582 VSRIQ_M_N))
2583 ]
2584 "TARGET_HAVE_MVE"
2585 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
2586 [(set_attr "type" "mve_move")
2587 (set_attr "length" "8")])
2589 ;;
2590 ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s])
2591 ;;
2592 (define_insn "mve_vcvtq_m_n_to_f_<supf><mode>"
2593 [
2594 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
2595 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
2596 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w")
2597 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
2598 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2599 VCVTQ_M_N_TO_F))
2600 ]
2601 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
2602 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
2603 [(set_attr "type" "mve_move")
2604 (set_attr "length""8")])
2606 ;;
2607 ;; [vabdq_m_s, vabdq_m_u]
2608 ;; [vhaddq_m_s, vhaddq_m_u]
2609 ;; [vhsubq_m_s, vhsubq_m_u]
2610 ;; [vmaxq_m_s, vmaxq_m_u]
2611 ;; [vminq_m_s, vminq_m_u]
2612 ;; [vmulhq_m_s, vmulhq_m_u]
2613 ;; [vqaddq_m_u, vqaddq_m_s]
2614 ;; [vqdmladhq_m_s]
2615 ;; [vqdmladhxq_m_s]
2616 ;; [vqdmlsdhq_m_s]
2617 ;; [vqdmlsdhxq_m_s]
2618 ;; [vqdmulhq_m_s]
2619 ;; [vqrdmladhq_m_s]
2620 ;; [vqrdmladhxq_m_s]
2621 ;; [vqrdmlsdhq_m_s]
2622 ;; [vqrdmlsdhxq_m_s]
2623 ;; [vqrdmulhq_m_s]
2624 ;; [vqrshlq_m_u, vqrshlq_m_s]
2625 ;; [vqshlq_m_u, vqshlq_m_s]
2626 ;; [vqsubq_m_u, vqsubq_m_s]
2627 ;; [vrhaddq_m_u, vrhaddq_m_s]
2628 ;; [vrmulhq_m_u, vrmulhq_m_s]
2629 ;; [vrshlq_m_s, vrshlq_m_u]
2630 ;; [vshlq_m_s, vshlq_m_u]
2631 ;;
2632 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
2633 [
2634 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2635 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2636 (match_operand:MVE_2 2 "s_register_operand" "w")
2637 (match_operand:MVE_2 3 "s_register_operand" "w")
2638 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2639 MVE_INT_SU_M_BINARY))
2640 ]
2641 "TARGET_HAVE_MVE"
2642 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
2643 [(set_attr "type" "mve_move")
2644 (set_attr "length""8")])
2646 ;;
2647 ;; [vaddq_m_n_s, vaddq_m_n_u]
2648 ;; [vsubq_m_n_s, vsubq_m_n_u]
2649 ;; [vmulq_m_n_s, vmulq_m_n_u]
2650 ;;
2651 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2652 [
2653 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2654 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2655 (match_operand:MVE_2 2 "s_register_operand" "w")
2656 (match_operand:<V_elem> 3 "s_register_operand" "r")
2657 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2658 MVE_INT_M_N_BINARY))
2659 ]
2660 "TARGET_HAVE_MVE"
2661 "vpst\;<mve_insn>t.i%#<V_sz_elem> %q0, %q2, %3"
2662 [(set_attr "type" "mve_move")
2663 (set_attr "length""8")])
2665 ;;
2666 ;; [vaddq_m_u, vaddq_m_s]
2667 ;; [vsubq_m_u, vsubq_m_s]
2668 ;; [vmulq_m_u, vmulq_m_s]
2669 ;;
2670 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
2671 [
2672 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2673 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2674 (match_operand:MVE_2 2 "s_register_operand" "w")
2675 (match_operand:MVE_2 3 "s_register_operand" "w")
2676 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2677 MVE_INT_M_BINARY))
2678 ]
2679 "TARGET_HAVE_MVE"
2680 "vpst\;<mve_insn>t.i%#<V_sz_elem>\t%q0, %q2, %q3"
2681 [(set_attr "type" "mve_move")
2682 (set_attr "length""8")])
2684 ;;
2685 ;; [vandq_m_u, vandq_m_s]
2686 ;; [vbicq_m_u, vbicq_m_s]
2687 ;; [veorq_m_u, veorq_m_s]
2688 ;; [vorrq_m_u, vorrq_m_s]
2689 ;;
2690 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
2691 [
2692 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2693 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2694 (match_operand:MVE_2 2 "s_register_operand" "w")
2695 (match_operand:MVE_2 3 "s_register_operand" "w")
2696 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2697 MVE_INT_M_BINARY_LOGIC))
2698 ]
2699 "TARGET_HAVE_MVE"
2700 "vpst\;<mve_insn>t\t%q0, %q2, %q3"
2701 [(set_attr "type" "mve_move")
2702 (set_attr "length""8")])
2704 ;;
2705 ;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
2706 ;;
2707 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2708 [
2709 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2710 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2711 (match_operand:MVE_2 2 "s_register_operand" "w")
2712 (match_operand:SI 3 "s_register_operand" "r")
2713 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2714 VBRSRQ_M_N))
2715 ]
2716 "TARGET_HAVE_MVE"
2717 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
2718 [(set_attr "type" "mve_move")
2719 (set_attr "length""8")])
2721 ;;
2722 ;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s]
2723 ;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s]
2724 ;; [vhcaddq_rot90_m_s]
2725 ;; [vhcaddq_rot270_m_s]
2726 ;;
2727 (define_insn "@mve_<mve_insn>q<mve_rot>_m_<supf><mode>"
2728 [
2729 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
2730 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2731 (match_operand:MVE_2 2 "s_register_operand" "w")
2732 (match_operand:MVE_2 3 "s_register_operand" "w")
2733 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2734 VxCADDQ_M))
2735 ]
2736 "TARGET_HAVE_MVE"
2737 "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2, %q3, #<rot>"
2738 [(set_attr "type" "mve_move")
2739 (set_attr "length""8")])
2741 ;;
2742 ;; [vhaddq_m_n_s, vhaddq_m_n_u]
2743 ;; [vhsubq_m_n_s, vhsubq_m_n_u]
2744 ;; [vmlaq_m_n_s, vmlaq_m_n_u]
2745 ;; [vmlasq_m_n_u, vmlasq_m_n_s]
2746 ;; [vqaddq_m_n_u, vqaddq_m_n_s]
2747 ;; [vqdmlahq_m_n_s]
2748 ;; [vqdmlashq_m_n_s]
2749 ;; [vqdmulhq_m_n_s]
2750 ;; [vqrdmlahq_m_n_s]
2751 ;; [vqrdmlashq_m_n_s]
2752 ;; [vqrdmulhq_m_n_s]
2753 ;; [vqsubq_m_n_u, vqsubq_m_n_s]
2754 ;;
2755 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2756 [
2757 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2758 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2759 (match_operand:MVE_2 2 "s_register_operand" "w")
2760 (match_operand:<V_elem> 3 "s_register_operand" "r")
2761 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2762 MVE_INT_SU_M_N_BINARY))
2763 ]
2764 "TARGET_HAVE_MVE"
2765 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
2766 [(set_attr "type" "mve_move")
2767 (set_attr "length""8")])
2769 ;;
2770 ;;
2771 ;; [vmladavaq_p_u, vmladavaq_p_s]
2772 ;; [vmladavaxq_p_s]
2773 ;; [vmlsdavaq_p_s]
2774 ;; [vmlsdavaxq_p_s]
2775 ;;
2776 (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
2777 [
2778 (set (match_operand:SI 0 "s_register_operand" "=Te")
2779 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
2780 (match_operand:MVE_2 2 "s_register_operand" "w")
2781 (match_operand:MVE_2 3 "s_register_operand" "w")
2782 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2783 MVE_VMLxDAVAQ_P))
2784 ]
2785 "TARGET_HAVE_MVE"
2786 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
2787 [(set_attr "type" "mve_move")
2788 (set_attr "length""8")])
2790 ;;
2791 ;; [vmullbq_int_m_u, vmullbq_int_m_s]
2792 ;; [vmulltq_int_m_s, vmulltq_int_m_u]
2793 ;;
2794 (define_insn "@mve_<mve_insn>q_int_m_<supf><mode>"
2795 [
2796 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
2797 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
2798 (match_operand:MVE_2 2 "s_register_operand" "w")
2799 (match_operand:MVE_2 3 "s_register_operand" "w")
2800 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2801 VMULLxQ_INT_M))
2802 ]
2803 "TARGET_HAVE_MVE"
2804 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
2805 [(set_attr "type" "mve_move")
2806 (set_attr "length""8")])
2808 ;;
2809 ;; [vornq_m_u, vornq_m_s])
2810 ;;
2811 (define_insn "mve_vornq_m_<supf><mode>"
2812 [
2813 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2814 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2815 (match_operand:MVE_2 2 "s_register_operand" "w")
2816 (match_operand:MVE_2 3 "s_register_operand" "w")
2817 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2818 VORNQ_M))
2819 ]
2820 "TARGET_HAVE_MVE"
2821 "vpst\;vornt\t%q0, %q2, %q3"
2822 [(set_attr "type" "mve_move")
2823 (set_attr "length""8")])
2825 ;;
2826 ;; [vqshlq_m_n_s, vqshlq_m_n_u]
2827 ;; [vshlq_m_n_s, vshlq_m_n_u]
2828 ;;
2829 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2830 [
2831 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2832 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2833 (match_operand:MVE_2 2 "s_register_operand" "w")
2834 (match_operand:SI 3 "immediate_operand" "i")
2835 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2836 MVE_SHIFT_M_N))
2837 ]
2838 "TARGET_HAVE_MVE"
2839 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
2840 [(set_attr "type" "mve_move")
2841 (set_attr "length""8")])
2843 ;;
2844 ;; [vrshrq_m_n_s, vrshrq_m_n_u])
2845 ;; [vshrq_m_n_s, vshrq_m_n_u])
2846 ;;
2847 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2848 [
2849 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2850 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2851 (match_operand:MVE_2 2 "s_register_operand" "w")
2852 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
2853 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2854 MVE_VSHRQ_M_N))
2855 ]
2856 "TARGET_HAVE_MVE"
2857 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
2858 [(set_attr "type" "mve_move")
2859 (set_attr "length""8")])
2861 ;;
2862 ;; [vsliq_m_n_u, vsliq_m_n_s])
2863 ;;
2864 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2865 [
2866 (set (match_operand:MVE_2 0 "s_register_operand" "=w")
2867 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
2868 (match_operand:MVE_2 2 "s_register_operand" "w")
2869 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")
2870 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2871 VSLIQ_M_N))
2872 ]
2873 "TARGET_HAVE_MVE"
2874 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
2875 [(set_attr "type" "mve_move")
2876 (set_attr "length""8")])
2878 ;;
2879 ;; [vmlaldavaq_p_u, vmlaldavaq_p_s]
2880 ;; [vmlaldavaxq_p_s]
2881 ;; [vmlsldavaq_p_s]
2882 ;; [vmlsldavaxq_p_s]
2883 ;;
2884 (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
2885 [
2886 (set (match_operand:DI 0 "s_register_operand" "=r")
2887 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2888 (match_operand:MVE_5 2 "s_register_operand" "w")
2889 (match_operand:MVE_5 3 "s_register_operand" "w")
2890 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2891 MVE_VMLxLDAVAxQ_P))
2892 ]
2893 "TARGET_HAVE_MVE"
2894 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3"
2895 [(set_attr "type" "mve_move")
2896 (set_attr "length""8")])
2898 ;;
2899 ;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s]
2900 ;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u]
2901 ;; [vqrshrunbq_m_n_s]
2902 ;; [vqrshruntq_m_n_s]
2903 ;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s]
2904 ;; [vqshrntq_m_n_s, vqshrntq_m_n_u]
2905 ;; [vqshrunbq_m_n_s]
2906 ;; [vqshruntq_m_n_s]
2907 ;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s]
2908 ;; [vrshrntq_m_n_u, vrshrntq_m_n_s]
2909 ;; [vshrnbq_m_n_s, vshrnbq_m_n_u]
2910 ;; [vshrntq_m_n_s, vshrntq_m_n_u]
2911 ;;
2912 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2913 [
2914 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w")
2915 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0")
2916 (match_operand:MVE_5 2 "s_register_operand" "w")
2917 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")
2918 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2919 MVE_SHRN_M_N))
2920 ]
2921 "TARGET_HAVE_MVE"
2922 "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2, %3"
2923 [(set_attr "type" "mve_move")
2924 (set_attr "length""8")])
2926 ;;
2927 ;; [vrmlaldavhaq_p_s, vrmlaldavhaq_p_u]
2928 ;; [vrmlaldavhaxq_p_s]
2929 ;; [vrmlsldavhaq_p_s]
2930 ;; [vrmlsldavhaxq_p_s]
2931 ;;
2932 (define_insn "@mve_<mve_insn>q_p_<supf>v4si"
2933 [
2934 (set (match_operand:DI 0 "s_register_operand" "=r")
2935 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
2936 (match_operand:V4SI 2 "s_register_operand" "w")
2937 (match_operand:V4SI 3 "s_register_operand" "w")
2938 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
2939 MVE_VRMLxLDAVHAxQ_P))
2940 ]
2941 "TARGET_HAVE_MVE"
2942 "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q2, %q3"
2943 [(set_attr "type" "mve_move")
2944 (set_attr "length""8")])
2946 ;;
2947 ;; [vshllbq_m_n_u, vshllbq_m_n_s]
2948 ;; [vshlltq_m_n_u, vshlltq_m_n_s]
2949 ;;
2950 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2951 [
2952 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2953 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
2954 (match_operand:MVE_3 2 "s_register_operand" "w")
2955 (match_operand:SI 3 "immediate_operand" "i")
2956 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2957 VSHLLxQ_M_N))
2958 ]
2959 "TARGET_HAVE_MVE"
2960 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
2961 [(set_attr "type" "mve_move")
2962 (set_attr "length""8")])
2964 ;;
2965 ;; [vmullbq_poly_m_p]
2966 ;; [vmulltq_poly_m_p]
2967 ;;
2968 (define_insn "@mve_<mve_insn>q_poly_m_<supf><mode>"
2969 [
2970 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
2971 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
2972 (match_operand:MVE_3 2 "s_register_operand" "w")
2973 (match_operand:MVE_3 3 "s_register_operand" "w")
2974 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2975 VMULLxQ_POLY_M))
2976 ]
2977 "TARGET_HAVE_MVE"
2978 "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %q3"
2979 [(set_attr "type" "mve_move")
2980 (set_attr "length""8")])
2982 ;;
2983 ;; [vqdmullbq_m_n_s]
2984 ;; [vqdmulltq_m_n_s]
2985 ;;
2986 (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
2987 [
2988 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
2989 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
2990 (match_operand:MVE_5 2 "s_register_operand" "w")
2991 (match_operand:<V_elem> 3 "s_register_operand" "r")
2992 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
2993 MVE_VQDMULLxQ_M_N))
2994 ]
2995 "TARGET_HAVE_MVE"
2996 "vpst\;<mve_insn>t.s%#<V_sz_elem>\t%q0, %q2, %3"
2997 [(set_attr "type" "mve_move")
2998 (set_attr "length""8")])
3000 ;;
3001 ;; [vqdmullbq_m_s]
3002 ;; [vqdmulltq_m_s]
3003 ;;
3004 (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
3005 [
3006 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
3007 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
3008 (match_operand:MVE_5 2 "s_register_operand" "w")
3009 (match_operand:MVE_5 3 "s_register_operand" "w")
3010 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
3011 MVE_VQDMULLxQ_M))
3012 ]
3013 "TARGET_HAVE_MVE"
3014 "vpst\;<mve_insn>t.s%#<V_sz_elem>\t%q0, %q2, %q3"
3015 [(set_attr "type" "mve_move")
3016 (set_attr "length""8")])
3018 ;;
3019 ;; [vabdq_m_f]
3020 ;; [vaddq_m_f]
3021 ;; [vfmaq_m_f]
3022 ;; [vfmsq_m_f]
3023 ;; [vmaxnmq_m_f]
3024 ;; [vminnmq_m_f]
3025 ;; [vmulq_m_f]
3026 ;; [vsubq_m_f]
3027 ;;
3028 (define_insn "@mve_<mve_insn>q_m_f<mode>"
3029 [
3030 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3031 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3032 (match_operand:MVE_0 2 "s_register_operand" "w")
3033 (match_operand:MVE_0 3 "s_register_operand" "w")
3034 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
3035 MVE_FP_M_BINARY))
3036 ]
3037 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3038 "vpst\;<mve_insn>t.f%#<V_sz_elem> %q0, %q2, %q3"
3039 [(set_attr "type" "mve_move")
3040 (set_attr "length""8")])
3042 ;;
3043 ;; [vaddq_m_n_f]
3044 ;; [vsubq_m_n_f]
3045 ;; [vmulq_m_n_f]
3046 ;; [vfmaq_m_n_f]
3047 ;; [vfmasq_m_n_f]
3048 ;;
3049 (define_insn "@mve_<mve_insn>q_m_n_f<mode>"
3050 [
3051 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3052 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3053 (match_operand:MVE_0 2 "s_register_operand" "w")
3054 (match_operand:<V_elem> 3 "s_register_operand" "r")
3055 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
3056 MVE_FP_M_N_BINARY))
3057 ]
3058 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3059 "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2, %3"
3060 [(set_attr "type" "mve_move")
3061 (set_attr "length""8")])
3063 ;;
3064 ;; [vandq_m_f]
3065 ;; [vbicq_m_f]
3066 ;; [veorq_m_f]
3067 ;; [vorrq_m_f]
3068 ;;
3069 (define_insn "@mve_<mve_insn>q_m_f<mode>"
3070 [
3071 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3072 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3073 (match_operand:MVE_0 2 "s_register_operand" "w")
3074 (match_operand:MVE_0 3 "s_register_operand" "w")
3075 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
3076 MVE_FP_M_BINARY_LOGIC))
3077 ]
3078 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3079 "vpst\;<mve_insn>t\t%q0, %q2, %q3"
3080 [(set_attr "type" "mve_move")
3081 (set_attr "length""8")])
3083 ;;
3084 ;; [vbrsrq_m_n_f])
3085 ;;
3086 (define_insn "@mve_<mve_insn>q_m_n_f<mode>"
3087 [
3088 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3089 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3090 (match_operand:MVE_0 2 "s_register_operand" "w")
3091 (match_operand:SI 3 "s_register_operand" "r")
3092 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
3093 MVE_VBRSR_M_N_FP))
3094 ]
3095 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3096 "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
3097 [(set_attr "type" "mve_move")
3098 (set_attr "length""8")])
3100 ;;
3101 ;; [vcaddq_rot90_m_f]
3102 ;; [vcaddq_rot270_m_f]
3103 ;; [vcmulq_m_f]
3104 ;; [vcmulq_rot90_m_f]
3105 ;; [vcmulq_rot180_m_f]
3106 ;; [vcmulq_rot270_m_f]
3107 ;;
3108 (define_insn "@mve_<mve_insn>q<mve_rot>_m_f<mode>"
3109 [
3110 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
3111 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3112 (match_operand:MVE_0 2 "s_register_operand" "w")
3113 (match_operand:MVE_0 3 "s_register_operand" "w")
3114 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
3115 MVE_VCADDQ_VCMULQ_M))
3116 ]
3117 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3118 "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2, %q3, #<rot>"
3119 [(set_attr "type" "mve_move")
3120 (set_attr "length""8")])
3122 ;;
3123 ;; [vcmlaq_m_f]
3124 ;; [vcmlaq_rot90_m_f]
3125 ;; [vcmlaq_rot180_m_f]
3126 ;; [vcmlaq_rot270_m_f]
3127 ;;
3128 (define_insn "@mve_<mve_insn>q<mve_rot>_m_f<mode>"
3129 [
3130 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3131 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3132 (match_operand:MVE_0 2 "s_register_operand" "w")
3133 (match_operand:MVE_0 3 "s_register_operand" "w")
3134 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
3135 MVE_VCMLAQ_M))
3136 ]
3137 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3138 "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2, %q3, #<rot>"
3139 [(set_attr "type" "mve_move")
3140 (set_attr "length""8")])
3142 ;;
3143 ;; [vornq_m_f])
3144 ;;
3145 (define_insn "mve_vornq_m_f<mode>"
3146 [
3147 (set (match_operand:MVE_0 0 "s_register_operand" "=w")
3148 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
3149 (match_operand:MVE_0 2 "s_register_operand" "w")
3150 (match_operand:MVE_0 3 "s_register_operand" "w")
3151 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
3152 VORNQ_M_F))
3153 ]
3154 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3155 "vpst\;vornt\t%q0, %q2, %q3"
3156 [(set_attr "type" "mve_move")
3157 (set_attr "length""8")])
3159 ;;
3160 ;; [vstrbq_s vstrbq_u]
3161 ;;
3162 (define_insn "mve_vstrbq_<supf><mode>"
3163 [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
3164 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")]
3165 VSTRBQ))
3166 ]
3167 "TARGET_HAVE_MVE"
3168 {
3169 rtx ops[2];
3170 int regno = REGNO (operands[1]);
3171 ops[1] = gen_rtx_REG (TImode, regno);
3172 ops[0] = operands[0];
3173 output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops);
3174 return "";
3175 }
3176 [(set_attr "length" "4")])
3178 ;;
3179 ;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u]
3180 ;;
3181 (define_expand "mve_vstrbq_scatter_offset_<supf><mode>"
3182 [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory")
3183 (match_operand:MVE_2 1 "s_register_operand")
3184 (match_operand:MVE_2 2 "s_register_operand")
3185 (unspec:V4SI [(const_int 0)] VSTRBSOQ)]
3186 "TARGET_HAVE_MVE"
3187 {
3188 rtx ind = XEXP (operands[0], 0);
3189 gcc_assert (REG_P (ind));
3190 emit_insn (gen_mve_vstrbq_scatter_offset_<supf><mode>_insn (ind, operands[1],
3191 operands[2]));
3192 DONE;
3193 })
3195 (define_insn "mve_vstrbq_scatter_offset_<supf><mode>_insn"
3196 [(set (mem:BLK (scratch))
3197 (unspec:BLK
3198 [(match_operand:SI 0 "register_operand" "r")
3199 (match_operand:MVE_2 1 "s_register_operand" "w")
3200 (match_operand:MVE_2 2 "s_register_operand" "w")]
3201 VSTRBSOQ))]
3202 "TARGET_HAVE_MVE"
3203 "vstrb.<V_sz_elem>\t%q2, [%0, %q1]"
3204 [(set_attr "length" "4")])
3206 ;;
3207 ;; [vstrwq_scatter_base_s vstrwq_scatter_base_u]
3208 ;;
3209 (define_insn "mve_vstrwq_scatter_base_<supf>v4si"
3210 [(set (mem:BLK (scratch))
3211 (unspec:BLK
3212 [(match_operand:V4SI 0 "s_register_operand" "w")
3213 (match_operand:SI 1 "immediate_operand" "i")
3214 (match_operand:V4SI 2 "s_register_operand" "w")]
3215 VSTRWSBQ))
3216 ]
3217 "TARGET_HAVE_MVE"
3218 {
3219 rtx ops[3];
3220 ops[0] = operands[0];
3221 ops[1] = operands[1];
3222 ops[2] = operands[2];
3223 output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops);
3224 return "";
3225 }
3226 [(set_attr "length" "4")])
3228 ;;
3229 ;; [vldrbq_gather_offset_s vldrbq_gather_offset_u]
3230 ;;
3231 (define_insn "mve_vldrbq_gather_offset_<supf><mode>"
3232 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
3233 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
3234 (match_operand:MVE_2 2 "s_register_operand" "w")]
3235 VLDRBGOQ))
3236 ]
3237 "TARGET_HAVE_MVE"
3238 {
3239 rtx ops[3];
3240 ops[0] = operands[0];
3241 ops[1] = operands[1];
3242 ops[2] = operands[2];
3243 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
3244 output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops);
3245 else
3246 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
3247 return "";
3248 }
3249 [(set_attr "length" "4")])
3251 ;;
3252 ;; [vldrbq_s vldrbq_u]
3253 ;;
3254 (define_insn "mve_vldrbq_<supf><mode>"
3255 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
3256 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux")]
3257 VLDRBQ))
3258 ]
3259 "TARGET_HAVE_MVE"
3260 {
3261 rtx ops[2];
3262 int regno = REGNO (operands[0]);
3263 ops[0] = gen_rtx_REG (TImode, regno);
3264 ops[1] = operands[1];
3265 if (<V_sz_elem> == 8)
3266 output_asm_insn ("vldrb.<V_sz_elem>\t%q0, %E1",ops);
3267 else
3268 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops);
3269 return "";
3270 }
3271 [(set_attr "length" "4")])
3273 ;;
3274 ;; [vldrwq_gather_base_s vldrwq_gather_base_u]
3275 ;;
3276 (define_insn "mve_vldrwq_gather_base_<supf>v4si"
3277 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
3278 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
3279 (match_operand:SI 2 "immediate_operand" "i")]
3280 VLDRWGBQ))
3281 ]
3282 "TARGET_HAVE_MVE"
3283 {
3284 rtx ops[3];
3285 ops[0] = operands[0];
3286 ops[1] = operands[1];
3287 ops[2] = operands[2];
3288 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
3289 return "";
3290 }
3291 [(set_attr "length" "4")])
3293 ;;
3294 ;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u]
3295 ;;
3296 (define_expand "mve_vstrbq_scatter_offset_p_<supf><mode>"
3297 [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory")
3298 (match_operand:MVE_2 1 "s_register_operand")
3299 (match_operand:MVE_2 2 "s_register_operand")
3300 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")
3301 (unspec:V4SI [(const_int 0)] VSTRBSOQ)]
3302 "TARGET_HAVE_MVE"
3303 {
3304 rtx ind = XEXP (operands[0], 0);
3305 gcc_assert (REG_P (ind));
3306 emit_insn (
3307 gen_mve_vstrbq_scatter_offset_p_<supf><mode>_insn (ind, operands[1],
3308 operands[2],
3309 operands[3]));
3310 DONE;
3311 })
3313 (define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>_insn"
3314 [(set (mem:BLK (scratch))
3315 (unspec:BLK
3316 [(match_operand:SI 0 "register_operand" "r")
3317 (match_operand:MVE_2 1 "s_register_operand" "w")
3318 (match_operand:MVE_2 2 "s_register_operand" "w")
3319 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
3320 VSTRBSOQ))]
3321 "TARGET_HAVE_MVE"
3322 "vpst\;vstrbt.<V_sz_elem>\t%q2, [%0, %q1]"
3323 [(set_attr "length" "8")])
3325 ;;
3326 ;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u]
3327 ;;
3328 (define_insn "mve_vstrwq_scatter_base_p_<supf>v4si"
3329 [(set (mem:BLK (scratch))
3330 (unspec:BLK
3331 [(match_operand:V4SI 0 "s_register_operand" "w")
3332 (match_operand:SI 1 "immediate_operand" "i")
3333 (match_operand:V4SI 2 "s_register_operand" "w")
3334 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
3335 VSTRWSBQ))
3336 ]
3337 "TARGET_HAVE_MVE"
3338 {
3339 rtx ops[3];
3340 ops[0] = operands[0];
3341 ops[1] = operands[1];
3342 ops[2] = operands[2];
3343 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
3344 return "";
3345 }
3346 [(set_attr "length" "8")])
3348 (define_insn "mve_vstrbq_p_<supf><mode>"
3349 [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux")
3350 (unspec:<MVE_B_ELEM>
3351 [(match_operand:MVE_2 1 "s_register_operand" "w")
3352 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
3353 (match_dup 0)]
3354 VSTRBQ))]
3355 "TARGET_HAVE_MVE"
3356 {
3357 rtx ops[2];
3358 int regno = REGNO (operands[1]);
3359 ops[1] = gen_rtx_REG (TImode, regno);
3360 ops[0] = operands[0];
3361 output_asm_insn ("vpst\;vstrbt.<V_sz_elem>\t%q1, %E0",ops);
3362 return "";
3363 }
3364 [(set_attr "length" "8")])
3366 ;;
3367 ;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u]
3368 ;;
3369 (define_insn "mve_vldrbq_gather_offset_z_<supf><mode>"
3370 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w")
3371 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us")
3372 (match_operand:MVE_2 2 "s_register_operand" "w")
3373 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
3374 VLDRBGOQ))
3375 ]
3376 "TARGET_HAVE_MVE"
3377 {
3378 rtx ops[4];
3379 ops[0] = operands[0];
3380 ops[1] = operands[1];
3381 ops[2] = operands[2];
3382 ops[3] = operands[3];
3383 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8)
3384 output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops);
3385 else
3386 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
3387 return "";
3388 }
3389 [(set_attr "length" "8")])
3391 ;;
3392 ;; [vldrbq_z_s vldrbq_z_u]
3393 ;;
3394 (define_insn "mve_vldrbq_z_<supf><mode>"
3395 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
3396 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux")
3397 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
3398 VLDRBQ))
3399 ]
3400 "TARGET_HAVE_MVE"
3401 {
3402 rtx ops[2];
3403 int regno = REGNO (operands[0]);
3404 ops[0] = gen_rtx_REG (TImode, regno);
3405 ops[1] = operands[1];
3406 if (<V_sz_elem> == 8)
3407 output_asm_insn ("vpst\;vldrbt.<V_sz_elem>\t%q0, %E1",ops);
3408 else
3409 output_asm_insn ("vpst\;vldrbt.<supf><V_sz_elem>\t%q0, %E1",ops);
3410 return "";
3411 }
3412 [(set_attr "length" "8")])
3414 ;;
3415 ;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u]
3416 ;;
3417 (define_insn "mve_vldrwq_gather_base_z_<supf>v4si"
3418 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
3419 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
3420 (match_operand:SI 2 "immediate_operand" "i")
3421 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
3422 VLDRWGBQ))
3423 ]
3424 "TARGET_HAVE_MVE"
3425 {
3426 rtx ops[3];
3427 ops[0] = operands[0];
3428 ops[1] = operands[1];
3429 ops[2] = operands[2];
3430 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
3431 return "";
3432 }
3433 [(set_attr "length" "8")])
3435 ;;
3436 ;; [vldrhq_f]
3437 ;;
3438 (define_insn "mve_vldrhq_fv8hf"
3439 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
3440 (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")]
3441 VLDRHQ_F))
3442 ]
3443 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3444 {
3445 rtx ops[2];
3446 int regno = REGNO (operands[0]);
3447 ops[0] = gen_rtx_REG (TImode, regno);
3448 ops[1] = operands[1];
3449 output_asm_insn ("vldrh.16\t%q0, %E1",ops);
3450 return "";
3451 }
3452 [(set_attr "length" "4")])
3454 ;;
3455 ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
3456 ;;
3457 (define_insn "mve_vldrhq_gather_offset_<supf><mode>"
3458 [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
3459 (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
3460 (match_operand:MVE_5 2 "s_register_operand" "w")]
3461 VLDRHGOQ))
3462 ]
3463 "TARGET_HAVE_MVE"
3464 {
3465 rtx ops[3];
3466 ops[0] = operands[0];
3467 ops[1] = operands[1];
3468 ops[2] = operands[2];
3469 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
3470 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops);
3471 else
3472 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
3473 return "";
3474 }
3475 [(set_attr "length" "4")])
3477 ;;
3478 ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
3479 ;;
3480 (define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"
3481 [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
3482 (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
3483 (match_operand:MVE_5 2 "s_register_operand" "w")
3484 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")
3485 ]VLDRHGOQ))
3486 ]
3487 "TARGET_HAVE_MVE"
3488 {
3489 rtx ops[4];
3490 ops[0] = operands[0];
3491 ops[1] = operands[1];
3492 ops[2] = operands[2];
3493 ops[3] = operands[3];
3494 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
3495 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops);
3496 else
3497 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops);
3498 return "";
3499 }
3500 [(set_attr "length" "8")])
3502 ;;
3503 ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
3504 ;;
3505 (define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"
3506 [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
3507 (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
3508 (match_operand:MVE_5 2 "s_register_operand" "w")]
3509 VLDRHGSOQ))
3510 ]
3511 "TARGET_HAVE_MVE"
3512 {
3513 rtx ops[3];
3514 ops[0] = operands[0];
3515 ops[1] = operands[1];
3516 ops[2] = operands[2];
3517 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
3518 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
3519 else
3520 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
3521 return "";
3522 }
3523 [(set_attr "length" "4")])
3525 ;;
3526 ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
3527 ;;
3528 (define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"
3529 [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
3530 (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
3531 (match_operand:MVE_5 2 "s_register_operand" "w")
3532 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")
3533 ]VLDRHGSOQ))
3534 ]
3535 "TARGET_HAVE_MVE"
3536 {
3537 rtx ops[4];
3538 ops[0] = operands[0];
3539 ops[1] = operands[1];
3540 ops[2] = operands[2];
3541 ops[3] = operands[3];
3542 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16)
3543 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops);
3544 else
3545 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops);
3546 return "";
3547 }
3548 [(set_attr "length" "8")])
3550 ;;
3551 ;; [vldrhq_s, vldrhq_u]
3552 ;;
3553 (define_insn "mve_vldrhq_<supf><mode>"
3554 [(set (match_operand:MVE_5 0 "s_register_operand" "=w")
3555 (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")]
3556 VLDRHQ))
3557 ]
3558 "TARGET_HAVE_MVE"
3559 {
3560 rtx ops[2];
3561 int regno = REGNO (operands[0]);
3562 ops[0] = gen_rtx_REG (TImode, regno);
3563 ops[1] = operands[1];
3564 if (<V_sz_elem> == 16)
3565 output_asm_insn ("vldrh.16\t%q0, %E1",ops);
3566 else
3567 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops);
3568 return "";
3569 }
3570 [(set_attr "length" "4")])
3572 ;;
3573 ;; [vldrhq_z_f]
3574 ;;
3575 (define_insn "mve_vldrhq_z_fv8hf"
3576 [(set (match_operand:V8HF 0 "s_register_operand" "=w")
3577 (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")
3578 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
3579 VLDRHQ_F))
3580 ]
3581 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3582 {
3583 rtx ops[2];
3584 int regno = REGNO (operands[0]);
3585 ops[0] = gen_rtx_REG (TImode, regno);
3586 ops[1] = operands[1];
3587 output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops);
3588 return "";
3589 }
3590 [(set_attr "length" "8")])
3592 ;;
3593 ;; [vldrhq_z_s vldrhq_z_u]
3594 ;;
3595 (define_insn "mve_vldrhq_z_<supf><mode>"
3596 [(set (match_operand:MVE_5 0 "s_register_operand" "=w")
3597 (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")
3598 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
3599 VLDRHQ))
3600 ]
3601 "TARGET_HAVE_MVE"
3602 {
3603 rtx ops[2];
3604 int regno = REGNO (operands[0]);
3605 ops[0] = gen_rtx_REG (TImode, regno);
3606 ops[1] = operands[1];
3607 if (<V_sz_elem> == 16)
3608 output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops);
3609 else
3610 output_asm_insn ("vpst\;vldrht.<supf><V_sz_elem>\t%q0, %E1",ops);
3611 return "";
3612 }
3613 [(set_attr "length" "8")])
3615 ;;
3616 ;; [vldrwq_f]
3617 ;;
3618 (define_insn "mve_vldrwq_fv4sf"
3619 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
3620 (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand" "Ux")]
3621 VLDRWQ_F))
3622 ]
3623 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3624 {
3625 rtx ops[2];
3626 int regno = REGNO (operands[0]);
3627 ops[0] = gen_rtx_REG (TImode, regno);
3628 ops[1] = operands[1];
3629 output_asm_insn ("vldrw.32\t%q0, %E1",ops);
3630 return "";
3631 }
3632 [(set_attr "length" "4")])
3634 ;;
3635 ;; [vldrwq_s vldrwq_u]
3636 ;;
3637 (define_insn "mve_vldrwq_<supf>v4si"
3638 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
3639 (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand" "Ux")]
3640 VLDRWQ))
3641 ]
3642 "TARGET_HAVE_MVE"
3643 {
3644 rtx ops[2];
3645 int regno = REGNO (operands[0]);
3646 ops[0] = gen_rtx_REG (TImode, regno);
3647 ops[1] = operands[1];
3648 output_asm_insn ("vldrw.32\t%q0, %E1",ops);
3649 return "";
3650 }
3651 [(set_attr "length" "4")])
3653 ;;
3654 ;; [vldrwq_z_f]
3655 ;;
3656 (define_insn "mve_vldrwq_z_fv4sf"
3657 [(set (match_operand:V4SF 0 "s_register_operand" "=w")
3658 (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand" "Ux")
3659 (match_operand:V4BI 2 "vpr_register_operand" "Up")]
3660 VLDRWQ_F))
3661 ]
3662 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3663 {
3664 rtx ops[2];
3665 int regno = REGNO (operands[0]);
3666 ops[0] = gen_rtx_REG (TImode, regno);
3667 ops[1] = operands[1];
3668 output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops);
3669 return "";
3670 }
3671 [(set_attr "length" "8")])
3673 ;;
3674 ;; [vldrwq_z_s vldrwq_z_u]
3675 ;;
3676 (define_insn "mve_vldrwq_z_<supf>v4si"
3677 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
3678 (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand" "Ux")
3679 (match_operand:V4BI 2 "vpr_register_operand" "Up")]
3680 VLDRWQ))
3681 ]
3682 "TARGET_HAVE_MVE"
3683 {
3684 rtx ops[2];
3685 int regno = REGNO (operands[0]);
3686 ops[0] = gen_rtx_REG (TImode, regno);
3687 ops[1] = operands[1];
3688 output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops);
3689 return "";
3690 }
3691 [(set_attr "length" "8")])
3693 (define_expand "mve_vld1q_f<mode>"
3694 [(match_operand:MVE_0 0 "s_register_operand")
3695 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "mve_memory_operand")] VLD1Q_F)
3696 ]
3697 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
3698 {
3699 emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
3700 DONE;
3701 })
3703 (define_expand "mve_vld1q_<supf><mode>"
3704 [(match_operand:MVE_2 0 "s_register_operand")
3705 (unspec:MVE_2 [(match_operand:MVE_2 1 "mve_memory_operand")] VLD1Q)
3706 ]
3707 "TARGET_HAVE_MVE"
3708 {
3709 emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
3710 DONE;
3711 })
3713 ;;
3714 ;; [vldrdq_gather_base_s vldrdq_gather_base_u]
3715 ;;
3716 (define_insn "mve_vldrdq_gather_base_<supf>v2di"
3717 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
3718 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")
3719 (match_operand:SI 2 "immediate_operand" "i")]
3720 VLDRDGBQ))
3721 ]
3722 "TARGET_HAVE_MVE"
3723 {
3724 rtx ops[3];
3725 ops[0] = operands[0];
3726 ops[1] = operands[1];
3727 ops[2] = operands[2];
3728 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops);
3729 return "";
3730 }
3731 [(set_attr "length" "4")])
3733 ;;
3734 ;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u]
3735 ;;
3736 (define_insn "mve_vldrdq_gather_base_z_<supf>v2di"
3737 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
3738 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w")
3739 (match_operand:SI 2 "immediate_operand" "i")
3740 (match_operand:V2QI 3 "vpr_register_operand" "Up")]
3741 VLDRDGBQ))
3742 ]
3743 "TARGET_HAVE_MVE"
3744 {
3745 rtx ops[3];
3746 ops[0] = operands[0];
3747 ops[1] = operands[1];
3748 ops[2] = operands[2];
3749 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops);
3750 return "";
3751 }
3752 [(set_attr "length" "8")])
3754 ;;
3755 ;; [vldrdq_gather_offset_s vldrdq_gather_offset_u]
3756 ;;
3757 (define_insn "mve_vldrdq_gather_offset_<supf>v2di"
3758 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
3759 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
3760 (match_operand:V2DI 2 "s_register_operand" "w")]
3761 VLDRDGOQ))
3762 ]
3763 "TARGET_HAVE_MVE"
3764 {
3765 rtx ops[3];
3766 ops[0] = operands[0];
3767 ops[1] = operands[1];
3768 ops[2] = operands[2];
3769 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops);
3770 return "";
3771 }
3772 [(set_attr "length" "4")])
3774 ;;
3775 ;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u]
3776 ;;
3777 (define_insn "mve_vldrdq_gather_offset_z_<supf>v2di"
3778 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
3779 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
3780 (match_operand:V2DI 2 "s_register_operand" "w")
3781 (match_operand:V2QI 3 "vpr_register_operand" "Up")]
3782 VLDRDGOQ))
3783 ]
3784 "TARGET_HAVE_MVE"
3785 {
3786 rtx ops[3];
3787 ops[0] = operands[0];
3788 ops[1] = operands[1];
3789 ops[2] = operands[2];
3790 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops);
3791 return "";
3792 }
3793 [(set_attr "length" "8")])
3795 ;;
3796 ;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u]
3797 ;;
3798 (define_insn "mve_vldrdq_gather_shifted_offset_<supf>v2di"
3799 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
3800 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
3801 (match_operand:V2DI 2 "s_register_operand" "w")]
3802 VLDRDGSOQ))
3803 ]
3804 "TARGET_HAVE_MVE"
3805 {
3806 rtx ops[3];
3807 ops[0] = operands[0];
3808 ops[1] = operands[1];
3809 ops[2] = operands[2];
3810 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops);
3811 return "";
3812 }
3813 [(set_attr "length" "4")])
3815 ;;
3816 ;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u]
3817 ;;
3818 (define_insn "mve_vldrdq_gather_shifted_offset_z_<supf>v2di"
3819 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
3820 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us")
3821 (match_operand:V2DI 2 "s_register_operand" "w")
3822 (match_operand:V2QI 3 "vpr_register_operand" "Up")]
3823 VLDRDGSOQ))
3824 ]
3825 "TARGET_HAVE_MVE"
3826 {
3827 rtx ops[3];
3828 ops[0] = operands[0];
3829 ops[1] = operands[1];
3830 ops[2] = operands[2];
3831 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops);
3832 return "";
3833 }
3834 [(set_attr "length" "8")])
3836 ;;
3837 ;; [vldrhq_gather_offset_f]
3838 ;;
3839 (define_insn "mve_vldrhq_gather_offset_fv8hf"
3840 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
3841 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
3842 (match_operand:V8HI 2 "s_register_operand" "w")]
3843 VLDRHQGO_F))
3844 ]
3845 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3846 {
3847 rtx ops[3];
3848 ops[0] = operands[0];
3849 ops[1] = operands[1];
3850 ops[2] = operands[2];
3851 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops);
3852 return "";
3853 }
3854 [(set_attr "length" "4")])
3856 ;;
3857 ;; [vldrhq_gather_offset_z_f]
3858 ;;
3859 (define_insn "mve_vldrhq_gather_offset_z_fv8hf"
3860 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
3861 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
3862 (match_operand:V8HI 2 "s_register_operand" "w")
3863 (match_operand:V8BI 3 "vpr_register_operand" "Up")]
3864 VLDRHQGO_F))
3865 ]
3866 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3867 {
3868 rtx ops[4];
3869 ops[0] = operands[0];
3870 ops[1] = operands[1];
3871 ops[2] = operands[2];
3872 ops[3] = operands[3];
3873 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops);
3874 return "";
3875 }
3876 [(set_attr "length" "8")])
3878 ;;
3879 ;; [vldrhq_gather_shifted_offset_f]
3880 ;;
3881 (define_insn "mve_vldrhq_gather_shifted_offset_fv8hf"
3882 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
3883 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
3884 (match_operand:V8HI 2 "s_register_operand" "w")]
3885 VLDRHQGSO_F))
3886 ]
3887 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3888 {
3889 rtx ops[3];
3890 ops[0] = operands[0];
3891 ops[1] = operands[1];
3892 ops[2] = operands[2];
3893 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops);
3894 return "";
3895 }
3896 [(set_attr "length" "4")])
3898 ;;
3899 ;; [vldrhq_gather_shifted_offset_z_f]
3900 ;;
3901 (define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf"
3902 [(set (match_operand:V8HF 0 "s_register_operand" "=&w")
3903 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us")
3904 (match_operand:V8HI 2 "s_register_operand" "w")
3905 (match_operand:V8BI 3 "vpr_register_operand" "Up")]
3906 VLDRHQGSO_F))
3907 ]
3908 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3909 {
3910 rtx ops[4];
3911 ops[0] = operands[0];
3912 ops[1] = operands[1];
3913 ops[2] = operands[2];
3914 ops[3] = operands[3];
3915 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops);
3916 return "";
3917 }
3918 [(set_attr "length" "8")])
3920 ;;
3921 ;; [vldrwq_gather_base_f]
3922 ;;
3923 (define_insn "mve_vldrwq_gather_base_fv4sf"
3924 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
3925 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
3926 (match_operand:SI 2 "immediate_operand" "i")]
3927 VLDRWQGB_F))
3928 ]
3929 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3930 {
3931 rtx ops[3];
3932 ops[0] = operands[0];
3933 ops[1] = operands[1];
3934 ops[2] = operands[2];
3935 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops);
3936 return "";
3937 }
3938 [(set_attr "length" "4")])
3940 ;;
3941 ;; [vldrwq_gather_base_z_f]
3942 ;;
3943 (define_insn "mve_vldrwq_gather_base_z_fv4sf"
3944 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
3945 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w")
3946 (match_operand:SI 2 "immediate_operand" "i")
3947 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
3948 VLDRWQGB_F))
3949 ]
3950 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3951 {
3952 rtx ops[3];
3953 ops[0] = operands[0];
3954 ops[1] = operands[1];
3955 ops[2] = operands[2];
3956 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops);
3957 return "";
3958 }
3959 [(set_attr "length" "8")])
3961 ;;
3962 ;; [vldrwq_gather_offset_f]
3963 ;;
3964 (define_insn "mve_vldrwq_gather_offset_fv4sf"
3965 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
3966 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
3967 (match_operand:V4SI 2 "s_register_operand" "w")]
3968 VLDRWQGO_F))
3969 ]
3970 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
3971 {
3972 rtx ops[3];
3973 ops[0] = operands[0];
3974 ops[1] = operands[1];
3975 ops[2] = operands[2];
3976 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops);
3977 return "";
3978 }
3979 [(set_attr "length" "4")])
3981 ;;
3982 ;; [vldrwq_gather_offset_s vldrwq_gather_offset_u]
3983 ;;
3984 (define_insn "mve_vldrwq_gather_offset_<supf>v4si"
3985 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
3986 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
3987 (match_operand:V4SI 2 "s_register_operand" "w")]
3988 VLDRWGOQ))
3989 ]
3990 "TARGET_HAVE_MVE"
3991 {
3992 rtx ops[3];
3993 ops[0] = operands[0];
3994 ops[1] = operands[1];
3995 ops[2] = operands[2];
3996 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops);
3997 return "";
3998 }
3999 [(set_attr "length" "4")])
4001 ;;
4002 ;; [vldrwq_gather_offset_z_f]
4003 ;;
4004 (define_insn "mve_vldrwq_gather_offset_z_fv4sf"
4005 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
4006 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
4007 (match_operand:V4SI 2 "s_register_operand" "w")
4008 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4009 VLDRWQGO_F))
4010 ]
4011 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4012 {
4013 rtx ops[4];
4014 ops[0] = operands[0];
4015 ops[1] = operands[1];
4016 ops[2] = operands[2];
4017 ops[3] = operands[3];
4018 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops);
4019 return "";
4020 }
4021 [(set_attr "length" "8")])
4023 ;;
4024 ;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u]
4025 ;;
4026 (define_insn "mve_vldrwq_gather_offset_z_<supf>v4si"
4027 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
4028 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
4029 (match_operand:V4SI 2 "s_register_operand" "w")
4030 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4031 VLDRWGOQ))
4032 ]
4033 "TARGET_HAVE_MVE"
4034 {
4035 rtx ops[4];
4036 ops[0] = operands[0];
4037 ops[1] = operands[1];
4038 ops[2] = operands[2];
4039 ops[3] = operands[3];
4040 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops);
4041 return "";
4042 }
4043 [(set_attr "length" "8")])
4045 ;;
4046 ;; [vldrwq_gather_shifted_offset_f]
4047 ;;
4048 (define_insn "mve_vldrwq_gather_shifted_offset_fv4sf"
4049 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
4050 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
4051 (match_operand:V4SI 2 "s_register_operand" "w")]
4052 VLDRWQGSO_F))
4053 ]
4054 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4055 {
4056 rtx ops[3];
4057 ops[0] = operands[0];
4058 ops[1] = operands[1];
4059 ops[2] = operands[2];
4060 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
4061 return "";
4062 }
4063 [(set_attr "length" "4")])
4065 ;;
4066 ;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u]
4067 ;;
4068 (define_insn "mve_vldrwq_gather_shifted_offset_<supf>v4si"
4069 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
4070 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
4071 (match_operand:V4SI 2 "s_register_operand" "w")]
4072 VLDRWGSOQ))
4073 ]
4074 "TARGET_HAVE_MVE"
4075 {
4076 rtx ops[3];
4077 ops[0] = operands[0];
4078 ops[1] = operands[1];
4079 ops[2] = operands[2];
4080 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
4081 return "";
4082 }
4083 [(set_attr "length" "4")])
4085 ;;
4086 ;; [vldrwq_gather_shifted_offset_z_f]
4087 ;;
4088 (define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf"
4089 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
4090 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us")
4091 (match_operand:V4SI 2 "s_register_operand" "w")
4092 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4093 VLDRWQGSO_F))
4094 ]
4095 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4096 {
4097 rtx ops[4];
4098 ops[0] = operands[0];
4099 ops[1] = operands[1];
4100 ops[2] = operands[2];
4101 ops[3] = operands[3];
4102 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
4103 return "";
4104 }
4105 [(set_attr "length" "8")])
4107 ;;
4108 ;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u]
4109 ;;
4110 (define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si"
4111 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
4112 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us")
4113 (match_operand:V4SI 2 "s_register_operand" "w")
4114 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4115 VLDRWGSOQ))
4116 ]
4117 "TARGET_HAVE_MVE"
4118 {
4119 rtx ops[4];
4120 ops[0] = operands[0];
4121 ops[1] = operands[1];
4122 ops[2] = operands[2];
4123 ops[3] = operands[3];
4124 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops);
4125 return "";
4126 }
4127 [(set_attr "length" "8")])
4129 ;;
4130 ;; [vstrhq_f]
4131 ;;
4132 (define_insn "mve_vstrhq_fv8hf"
4133 [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
4134 (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")]
4135 VSTRHQ_F))
4136 ]
4137 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4138 {
4139 rtx ops[2];
4140 int regno = REGNO (operands[1]);
4141 ops[1] = gen_rtx_REG (TImode, regno);
4142 ops[0] = operands[0];
4143 output_asm_insn ("vstrh.16\t%q1, %E0",ops);
4144 return "";
4145 }
4146 [(set_attr "length" "4")])
4148 ;;
4149 ;; [vstrhq_p_f]
4150 ;;
4151 (define_insn "mve_vstrhq_p_fv8hf"
4152 [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux")
4153 (unspec:V8HI
4154 [(match_operand:V8HF 1 "s_register_operand" "w")
4155 (match_operand:V8BI 2 "vpr_register_operand" "Up")
4156 (match_dup 0)]
4157 VSTRHQ_F))]
4158 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4159 {
4160 rtx ops[2];
4161 int regno = REGNO (operands[1]);
4162 ops[1] = gen_rtx_REG (TImode, regno);
4163 ops[0] = operands[0];
4164 output_asm_insn ("vpst\;vstrht.16\t%q1, %E0",ops);
4165 return "";
4166 }
4167 [(set_attr "length" "8")])
4169 ;;
4170 ;; [vstrhq_p_s vstrhq_p_u]
4171 ;;
4172 (define_insn "mve_vstrhq_p_<supf><mode>"
4173 [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
4174 (unspec:<MVE_H_ELEM>
4175 [(match_operand:MVE_5 1 "s_register_operand" "w")
4176 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
4177 (match_dup 0)]
4178 VSTRHQ))
4179 ]
4180 "TARGET_HAVE_MVE"
4181 {
4182 rtx ops[2];
4183 int regno = REGNO (operands[1]);
4184 ops[1] = gen_rtx_REG (TImode, regno);
4185 ops[0] = operands[0];
4186 output_asm_insn ("vpst\;vstrht.<V_sz_elem>\t%q1, %E0",ops);
4187 return "";
4188 }
4189 [(set_attr "length" "8")])
4191 ;;
4192 ;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u]
4193 ;;
4194 (define_expand "mve_vstrhq_scatter_offset_p_<supf><mode>"
4195 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
4196 (match_operand:MVE_5 1 "s_register_operand")
4197 (match_operand:MVE_5 2 "s_register_operand")
4198 (match_operand:<MVE_VPRED> 3 "vpr_register_operand")
4199 (unspec:V4SI [(const_int 0)] VSTRHSOQ)]
4200 "TARGET_HAVE_MVE"
4201 {
4202 rtx ind = XEXP (operands[0], 0);
4203 gcc_assert (REG_P (ind));
4204 emit_insn (
4205 gen_mve_vstrhq_scatter_offset_p_<supf><mode>_insn (ind, operands[1],
4206 operands[2],
4207 operands[3]));
4208 DONE;
4209 })
4211 (define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>_insn"
4212 [(set (mem:BLK (scratch))
4213 (unspec:BLK
4214 [(match_operand:SI 0 "register_operand" "r")
4215 (match_operand:MVE_5 1 "s_register_operand" "w")
4216 (match_operand:MVE_5 2 "s_register_operand" "w")
4217 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
4218 VSTRHSOQ))]
4219 "TARGET_HAVE_MVE"
4220 "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1]"
4221 [(set_attr "length" "8")])
4223 ;;
4224 ;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u]
4225 ;;
4226 (define_expand "mve_vstrhq_scatter_offset_<supf><mode>"
4227 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
4228 (match_operand:MVE_5 1 "s_register_operand")
4229 (match_operand:MVE_5 2 "s_register_operand")
4230 (unspec:V4SI [(const_int 0)] VSTRHSOQ)]
4231 "TARGET_HAVE_MVE"
4232 {
4233 rtx ind = XEXP (operands[0], 0);
4234 gcc_assert (REG_P (ind));
4235 emit_insn (gen_mve_vstrhq_scatter_offset_<supf><mode>_insn (ind, operands[1],
4236 operands[2]));
4237 DONE;
4238 })
4240 (define_insn "mve_vstrhq_scatter_offset_<supf><mode>_insn"
4241 [(set (mem:BLK (scratch))
4242 (unspec:BLK
4243 [(match_operand:SI 0 "register_operand" "r")
4244 (match_operand:MVE_5 1 "s_register_operand" "w")
4245 (match_operand:MVE_5 2 "s_register_operand" "w")]
4246 VSTRHSOQ))]
4247 "TARGET_HAVE_MVE"
4248 "vstrh.<V_sz_elem>\t%q2, [%0, %q1]"
4249 [(set_attr "length" "4")])
4251 ;;
4252 ;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u]
4253 ;;
4254 (define_expand "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>"
4255 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
4256 (match_operand:MVE_5 1 "s_register_operand")
4257 (match_operand:MVE_5 2 "s_register_operand")
4258 (match_operand:<MVE_VPRED> 3 "vpr_register_operand")
4259 (unspec:V4SI [(const_int 0)] VSTRHSSOQ)]
4260 "TARGET_HAVE_MVE"
4261 {
4262 rtx ind = XEXP (operands[0], 0);
4263 gcc_assert (REG_P (ind));
4264 emit_insn (
4265 gen_mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn (ind, operands[1],
4266 operands[2],
4267 operands[3]));
4268 DONE;
4269 })
4271 (define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn"
4272 [(set (mem:BLK (scratch))
4273 (unspec:BLK
4274 [(match_operand:SI 0 "register_operand" "r")
4275 (match_operand:MVE_5 1 "s_register_operand" "w")
4276 (match_operand:MVE_5 2 "s_register_operand" "w")
4277 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
4278 VSTRHSSOQ))]
4279 "TARGET_HAVE_MVE"
4280 "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]"
4281 [(set_attr "length" "8")])
4283 ;;
4284 ;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u]
4285 ;;
4286 (define_expand "mve_vstrhq_scatter_shifted_offset_<supf><mode>"
4287 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
4288 (match_operand:MVE_5 1 "s_register_operand")
4289 (match_operand:MVE_5 2 "s_register_operand")
4290 (unspec:V4SI [(const_int 0)] VSTRHSSOQ)]
4291 "TARGET_HAVE_MVE"
4292 {
4293 rtx ind = XEXP (operands[0], 0);
4294 gcc_assert (REG_P (ind));
4295 emit_insn (
4296 gen_mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn (ind, operands[1],
4297 operands[2]));
4298 DONE;
4299 })
4301 (define_insn "mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn"
4302 [(set (mem:BLK (scratch))
4303 (unspec:BLK
4304 [(match_operand:SI 0 "register_operand" "r")
4305 (match_operand:MVE_5 1 "s_register_operand" "w")
4306 (match_operand:MVE_5 2 "s_register_operand" "w")]
4307 VSTRHSSOQ))]
4308 "TARGET_HAVE_MVE"
4309 "vstrh.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]"
4310 [(set_attr "length" "4")])
4312 ;;
4313 ;; [vstrhq_s, vstrhq_u]
4314 ;;
4315 (define_insn "mve_vstrhq_<supf><mode>"
4316 [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
4317 (unspec:<MVE_H_ELEM> [(match_operand:MVE_5 1 "s_register_operand" "w")]
4318 VSTRHQ))
4319 ]
4320 "TARGET_HAVE_MVE"
4321 {
4322 rtx ops[2];
4323 int regno = REGNO (operands[1]);
4324 ops[1] = gen_rtx_REG (TImode, regno);
4325 ops[0] = operands[0];
4326 output_asm_insn ("vstrh.<V_sz_elem>\t%q1, %E0",ops);
4327 return "";
4328 }
4329 [(set_attr "length" "4")])
4331 ;;
4332 ;; [vstrwq_f]
4333 ;;
4334 (define_insn "mve_vstrwq_fv4sf"
4335 [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
4336 (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")]
4337 VSTRWQ_F))
4338 ]
4339 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4340 {
4341 rtx ops[2];
4342 int regno = REGNO (operands[1]);
4343 ops[1] = gen_rtx_REG (TImode, regno);
4344 ops[0] = operands[0];
4345 output_asm_insn ("vstrw.32\t%q1, %E0",ops);
4346 return "";
4347 }
4348 [(set_attr "length" "4")])
4350 ;;
4351 ;; [vstrwq_p_f]
4352 ;;
4353 (define_insn "mve_vstrwq_p_fv4sf"
4354 [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
4355 (unspec:V4SI
4356 [(match_operand:V4SF 1 "s_register_operand" "w")
4357 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
4358 (match_dup 0)]
4359 VSTRWQ_F))]
4360 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4361 {
4362 rtx ops[2];
4363 int regno = REGNO (operands[1]);
4364 ops[1] = gen_rtx_REG (TImode, regno);
4365 ops[0] = operands[0];
4366 output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops);
4367 return "";
4368 }
4369 [(set_attr "length" "8")])
4371 ;;
4372 ;; [vstrwq_p_s vstrwq_p_u]
4373 ;;
4374 (define_insn "mve_vstrwq_p_<supf>v4si"
4375 [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
4376 (unspec:V4SI
4377 [(match_operand:V4SI 1 "s_register_operand" "w")
4378 (match_operand:V4BI 2 "vpr_register_operand" "Up")
4379 (match_dup 0)]
4380 VSTRWQ))]
4381 "TARGET_HAVE_MVE"
4382 {
4383 rtx ops[2];
4384 int regno = REGNO (operands[1]);
4385 ops[1] = gen_rtx_REG (TImode, regno);
4386 ops[0] = operands[0];
4387 output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops);
4388 return "";
4389 }
4390 [(set_attr "length" "8")])
4392 ;;
4393 ;; [vstrwq_s vstrwq_u]
4394 ;;
4395 (define_insn "mve_vstrwq_<supf>v4si"
4396 [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
4397 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")]
4398 VSTRWQ))
4399 ]
4400 "TARGET_HAVE_MVE"
4401 {
4402 rtx ops[2];
4403 int regno = REGNO (operands[1]);
4404 ops[1] = gen_rtx_REG (TImode, regno);
4405 ops[0] = operands[0];
4406 output_asm_insn ("vstrw.32\t%q1, %E0",ops);
4407 return "";
4408 }
4409 [(set_attr "length" "4")])
4411 (define_expand "mve_vst1q_f<mode>"
4412 [(match_operand:<MVE_CNVT> 0 "mve_memory_operand")
4413 (unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F)
4414 ]
4415 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
4416 {
4417 emit_insn (gen_mve_vstr<V_sz_elem1>q_f<mode>(operands[0],operands[1]));
4418 DONE;
4419 })
4421 (define_expand "mve_vst1q_<supf><mode>"
4422 [(match_operand:MVE_2 0 "mve_memory_operand")
4423 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q)
4424 ]
4425 "TARGET_HAVE_MVE"
4426 {
4427 emit_insn (gen_mve_vstr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1]));
4428 DONE;
4429 })
4431 ;;
4432 ;; [vstrdq_scatter_base_p_s vstrdq_scatter_base_p_u]
4433 ;;
4434 (define_insn "mve_vstrdq_scatter_base_p_<supf>v2di"
4435 [(set (mem:BLK (scratch))
4436 (unspec:BLK
4437 [(match_operand:V2DI 0 "s_register_operand" "w")
4438 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
4439 (match_operand:V2DI 2 "s_register_operand" "w")
4440 (match_operand:V2QI 3 "vpr_register_operand" "Up")]
4441 VSTRDSBQ))
4442 ]
4443 "TARGET_HAVE_MVE"
4444 {
4445 rtx ops[3];
4446 ops[0] = operands[0];
4447 ops[1] = operands[1];
4448 ops[2] = operands[2];
4449 output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]",ops);
4450 return "";
4451 }
4452 [(set_attr "length" "8")])
4454 ;;
4455 ;; [vstrdq_scatter_base_s vstrdq_scatter_base_u]
4456 ;;
4457 (define_insn "mve_vstrdq_scatter_base_<supf>v2di"
4458 [(set (mem:BLK (scratch))
4459 (unspec:BLK
4460 [(match_operand:V2DI 0 "s_register_operand" "=w")
4461 (match_operand:SI 1 "mve_vldrd_immediate" "Ri")
4462 (match_operand:V2DI 2 "s_register_operand" "w")]
4463 VSTRDSBQ))
4464 ]
4465 "TARGET_HAVE_MVE"
4466 {
4467 rtx ops[3];
4468 ops[0] = operands[0];
4469 ops[1] = operands[1];
4470 ops[2] = operands[2];
4471 output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]",ops);
4472 return "";
4473 }
4474 [(set_attr "length" "4")])
4476 ;;
4477 ;; [vstrdq_scatter_offset_p_s vstrdq_scatter_offset_p_u]
4478 ;;
4479 (define_expand "mve_vstrdq_scatter_offset_p_<supf>v2di"
4480 [(match_operand:V2DI 0 "mve_scatter_memory")
4481 (match_operand:V2DI 1 "s_register_operand")
4482 (match_operand:V2DI 2 "s_register_operand")
4483 (match_operand:V2QI 3 "vpr_register_operand")
4484 (unspec:V4SI [(const_int 0)] VSTRDSOQ)]
4485 "TARGET_HAVE_MVE"
4486 {
4487 rtx ind = XEXP (operands[0], 0);
4488 gcc_assert (REG_P (ind));
4489 emit_insn (gen_mve_vstrdq_scatter_offset_p_<supf>v2di_insn (ind, operands[1],
4490 operands[2],
4491 operands[3]));
4492 DONE;
4493 })
4495 (define_insn "mve_vstrdq_scatter_offset_p_<supf>v2di_insn"
4496 [(set (mem:BLK (scratch))
4497 (unspec:BLK
4498 [(match_operand:SI 0 "register_operand" "r")
4499 (match_operand:V2DI 1 "s_register_operand" "w")
4500 (match_operand:V2DI 2 "s_register_operand" "w")
4501 (match_operand:V2QI 3 "vpr_register_operand" "Up")]
4502 VSTRDSOQ))]
4503 "TARGET_HAVE_MVE"
4504 "vpst\;vstrdt.64\t%q2, [%0, %q1]"
4505 [(set_attr "length" "8")])
4507 ;;
4508 ;; [vstrdq_scatter_offset_s vstrdq_scatter_offset_u]
4509 ;;
4510 (define_expand "mve_vstrdq_scatter_offset_<supf>v2di"
4511 [(match_operand:V2DI 0 "mve_scatter_memory")
4512 (match_operand:V2DI 1 "s_register_operand")
4513 (match_operand:V2DI 2 "s_register_operand")
4514 (unspec:V4SI [(const_int 0)] VSTRDSOQ)]
4515 "TARGET_HAVE_MVE"
4516 {
4517 rtx ind = XEXP (operands[0], 0);
4518 gcc_assert (REG_P (ind));
4519 emit_insn (gen_mve_vstrdq_scatter_offset_<supf>v2di_insn (ind, operands[1],
4520 operands[2]));
4521 DONE;
4522 })
4524 (define_insn "mve_vstrdq_scatter_offset_<supf>v2di_insn"
4525 [(set (mem:BLK (scratch))
4526 (unspec:BLK
4527 [(match_operand:SI 0 "register_operand" "r")
4528 (match_operand:V2DI 1 "s_register_operand" "w")
4529 (match_operand:V2DI 2 "s_register_operand" "w")]
4530 VSTRDSOQ))]
4531 "TARGET_HAVE_MVE"
4532 "vstrd.64\t%q2, [%0, %q1]"
4533 [(set_attr "length" "4")])
4535 ;;
4536 ;; [vstrdq_scatter_shifted_offset_p_s vstrdq_scatter_shifted_offset_p_u]
4537 ;;
4538 (define_expand "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di"
4539 [(match_operand:V2DI 0 "mve_scatter_memory")
4540 (match_operand:V2DI 1 "s_register_operand")
4541 (match_operand:V2DI 2 "s_register_operand")
4542 (match_operand:V2QI 3 "vpr_register_operand")
4543 (unspec:V4SI [(const_int 0)] VSTRDSSOQ)]
4544 "TARGET_HAVE_MVE"
4545 {
4546 rtx ind = XEXP (operands[0], 0);
4547 gcc_assert (REG_P (ind));
4548 emit_insn (
4549 gen_mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn (ind, operands[1],
4550 operands[2],
4551 operands[3]));
4552 DONE;
4553 })
4555 (define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn"
4556 [(set (mem:BLK (scratch))
4557 (unspec:BLK
4558 [(match_operand:SI 0 "register_operand" "r")
4559 (match_operand:V2DI 1 "s_register_operand" "w")
4560 (match_operand:V2DI 2 "s_register_operand" "w")
4561 (match_operand:V2QI 3 "vpr_register_operand" "Up")]
4562 VSTRDSSOQ))]
4563 "TARGET_HAVE_MVE"
4564 "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]"
4565 [(set_attr "length" "8")])
4567 ;;
4568 ;; [vstrdq_scatter_shifted_offset_s vstrdq_scatter_shifted_offset_u]
4569 ;;
4570 (define_expand "mve_vstrdq_scatter_shifted_offset_<supf>v2di"
4571 [(match_operand:V2DI 0 "mve_scatter_memory")
4572 (match_operand:V2DI 1 "s_register_operand")
4573 (match_operand:V2DI 2 "s_register_operand")
4574 (unspec:V4SI [(const_int 0)] VSTRDSSOQ)]
4575 "TARGET_HAVE_MVE"
4576 {
4577 rtx ind = XEXP (operands[0], 0);
4578 gcc_assert (REG_P (ind));
4579 emit_insn (
4580 gen_mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn (ind, operands[1],
4581 operands[2]));
4582 DONE;
4583 })
4585 (define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn"
4586 [(set (mem:BLK (scratch))
4587 (unspec:BLK
4588 [(match_operand:SI 0 "register_operand" "r")
4589 (match_operand:V2DI 1 "s_register_operand" "w")
4590 (match_operand:V2DI 2 "s_register_operand" "w")]
4591 VSTRDSSOQ))]
4592 "TARGET_HAVE_MVE"
4593 "vstrd.64\t%q2, [%0, %q1, uxtw #3]"
4594 [(set_attr "length" "4")])
4596 ;;
4597 ;; [vstrhq_scatter_offset_f]
4598 ;;
4599 (define_expand "mve_vstrhq_scatter_offset_fv8hf"
4600 [(match_operand:V8HI 0 "mve_scatter_memory")
4601 (match_operand:V8HI 1 "s_register_operand")
4602 (match_operand:V8HF 2 "s_register_operand")
4603 (unspec:V4SI [(const_int 0)] VSTRHQSO_F)]
4604 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4605 {
4606 rtx ind = XEXP (operands[0], 0);
4607 gcc_assert (REG_P (ind));
4608 emit_insn (gen_mve_vstrhq_scatter_offset_fv8hf_insn (ind, operands[1],
4609 operands[2]));
4610 DONE;
4611 })
4613 (define_insn "mve_vstrhq_scatter_offset_fv8hf_insn"
4614 [(set (mem:BLK (scratch))
4615 (unspec:BLK
4616 [(match_operand:SI 0 "register_operand" "r")
4617 (match_operand:V8HI 1 "s_register_operand" "w")
4618 (match_operand:V8HF 2 "s_register_operand" "w")]
4619 VSTRHQSO_F))]
4620 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4621 "vstrh.16\t%q2, [%0, %q1]"
4622 [(set_attr "length" "4")])
4624 ;;
4625 ;; [vstrhq_scatter_offset_p_f]
4626 ;;
4627 (define_expand "mve_vstrhq_scatter_offset_p_fv8hf"
4628 [(match_operand:V8HI 0 "mve_scatter_memory")
4629 (match_operand:V8HI 1 "s_register_operand")
4630 (match_operand:V8HF 2 "s_register_operand")
4631 (match_operand:V8BI 3 "vpr_register_operand")
4632 (unspec:V4SI [(const_int 0)] VSTRHQSO_F)]
4633 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4634 {
4635 rtx ind = XEXP (operands[0], 0);
4636 gcc_assert (REG_P (ind));
4637 emit_insn (gen_mve_vstrhq_scatter_offset_p_fv8hf_insn (ind, operands[1],
4638 operands[2],
4639 operands[3]));
4640 DONE;
4641 })
4643 (define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn"
4644 [(set (mem:BLK (scratch))
4645 (unspec:BLK
4646 [(match_operand:SI 0 "register_operand" "r")
4647 (match_operand:V8HI 1 "s_register_operand" "w")
4648 (match_operand:V8HF 2 "s_register_operand" "w")
4649 (match_operand:V8BI 3 "vpr_register_operand" "Up")]
4650 VSTRHQSO_F))]
4651 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4652 "vpst\;vstrht.16\t%q2, [%0, %q1]"
4653 [(set_attr "length" "8")])
4655 ;;
4656 ;; [vstrhq_scatter_shifted_offset_f]
4657 ;;
4658 (define_expand "mve_vstrhq_scatter_shifted_offset_fv8hf"
4659 [(match_operand:V8HI 0 "memory_operand" "=Us")
4660 (match_operand:V8HI 1 "s_register_operand" "w")
4661 (match_operand:V8HF 2 "s_register_operand" "w")
4662 (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)]
4663 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4664 {
4665 rtx ind = XEXP (operands[0], 0);
4666 gcc_assert (REG_P (ind));
4667 emit_insn (gen_mve_vstrhq_scatter_shifted_offset_fv8hf_insn (ind, operands[1],
4668 operands[2]));
4669 DONE;
4670 })
4672 (define_insn "mve_vstrhq_scatter_shifted_offset_fv8hf_insn"
4673 [(set (mem:BLK (scratch))
4674 (unspec:BLK
4675 [(match_operand:SI 0 "register_operand" "r")
4676 (match_operand:V8HI 1 "s_register_operand" "w")
4677 (match_operand:V8HF 2 "s_register_operand" "w")]
4678 VSTRHQSSO_F))]
4679 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4680 "vstrh.16\t%q2, [%0, %q1, uxtw #1]"
4681 [(set_attr "length" "4")])
4683 ;;
4684 ;; [vstrhq_scatter_shifted_offset_p_f]
4685 ;;
4686 (define_expand "mve_vstrhq_scatter_shifted_offset_p_fv8hf"
4687 [(match_operand:V8HI 0 "memory_operand" "=Us")
4688 (match_operand:V8HI 1 "s_register_operand" "w")
4689 (match_operand:V8HF 2 "s_register_operand" "w")
4690 (match_operand:V8BI 3 "vpr_register_operand" "Up")
4691 (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)]
4692 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4693 {
4694 rtx ind = XEXP (operands[0], 0);
4695 gcc_assert (REG_P (ind));
4696 emit_insn (
4697 gen_mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn (ind, operands[1],
4698 operands[2],
4699 operands[3]));
4700 DONE;
4701 })
4703 (define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn"
4704 [(set (mem:BLK (scratch))
4705 (unspec:BLK
4706 [(match_operand:SI 0 "register_operand" "r")
4707 (match_operand:V8HI 1 "s_register_operand" "w")
4708 (match_operand:V8HF 2 "s_register_operand" "w")
4709 (match_operand:V8BI 3 "vpr_register_operand" "Up")]
4710 VSTRHQSSO_F))]
4711 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4712 "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]"
4713 [(set_attr "length" "8")])
4715 ;;
4716 ;; [vstrwq_scatter_base_f]
4717 ;;
4718 (define_insn "mve_vstrwq_scatter_base_fv4sf"
4719 [(set (mem:BLK (scratch))
4720 (unspec:BLK
4721 [(match_operand:V4SI 0 "s_register_operand" "w")
4722 (match_operand:SI 1 "immediate_operand" "i")
4723 (match_operand:V4SF 2 "s_register_operand" "w")]
4724 VSTRWQSB_F))
4725 ]
4726 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4727 {
4728 rtx ops[3];
4729 ops[0] = operands[0];
4730 ops[1] = operands[1];
4731 ops[2] = operands[2];
4732 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]",ops);
4733 return "";
4734 }
4735 [(set_attr "length" "4")])
4737 ;;
4738 ;; [vstrwq_scatter_base_p_f]
4739 ;;
4740 (define_insn "mve_vstrwq_scatter_base_p_fv4sf"
4741 [(set (mem:BLK (scratch))
4742 (unspec:BLK
4743 [(match_operand:V4SI 0 "s_register_operand" "w")
4744 (match_operand:SI 1 "immediate_operand" "i")
4745 (match_operand:V4SF 2 "s_register_operand" "w")
4746 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4747 VSTRWQSB_F))
4748 ]
4749 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4750 {
4751 rtx ops[3];
4752 ops[0] = operands[0];
4753 ops[1] = operands[1];
4754 ops[2] = operands[2];
4755 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops);
4756 return "";
4757 }
4758 [(set_attr "length" "8")])
4760 ;;
4761 ;; [vstrwq_scatter_offset_f]
4762 ;;
4763 (define_expand "mve_vstrwq_scatter_offset_fv4sf"
4764 [(match_operand:V4SI 0 "mve_scatter_memory")
4765 (match_operand:V4SI 1 "s_register_operand")
4766 (match_operand:V4SF 2 "s_register_operand")
4767 (unspec:V4SI [(const_int 0)] VSTRWQSO_F)]
4768 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4769 {
4770 rtx ind = XEXP (operands[0], 0);
4771 gcc_assert (REG_P (ind));
4772 emit_insn (gen_mve_vstrwq_scatter_offset_fv4sf_insn (ind, operands[1],
4773 operands[2]));
4774 DONE;
4775 })
4777 (define_insn "mve_vstrwq_scatter_offset_fv4sf_insn"
4778 [(set (mem:BLK (scratch))
4779 (unspec:BLK
4780 [(match_operand:SI 0 "register_operand" "r")
4781 (match_operand:V4SI 1 "s_register_operand" "w")
4782 (match_operand:V4SF 2 "s_register_operand" "w")]
4783 VSTRWQSO_F))]
4784 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4785 "vstrw.32\t%q2, [%0, %q1]"
4786 [(set_attr "length" "4")])
4788 ;;
4789 ;; [vstrwq_scatter_offset_p_f]
4790 ;;
4791 (define_expand "mve_vstrwq_scatter_offset_p_fv4sf"
4792 [(match_operand:V4SI 0 "mve_scatter_memory")
4793 (match_operand:V4SI 1 "s_register_operand")
4794 (match_operand:V4SF 2 "s_register_operand")
4795 (match_operand:V4BI 3 "vpr_register_operand")
4796 (unspec:V4SI [(const_int 0)] VSTRWQSO_F)]
4797 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4798 {
4799 rtx ind = XEXP (operands[0], 0);
4800 gcc_assert (REG_P (ind));
4801 emit_insn (gen_mve_vstrwq_scatter_offset_p_fv4sf_insn (ind, operands[1],
4802 operands[2],
4803 operands[3]));
4804 DONE;
4805 })
4807 (define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn"
4808 [(set (mem:BLK (scratch))
4809 (unspec:BLK
4810 [(match_operand:SI 0 "register_operand" "r")
4811 (match_operand:V4SI 1 "s_register_operand" "w")
4812 (match_operand:V4SF 2 "s_register_operand" "w")
4813 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4814 VSTRWQSO_F))]
4815 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4816 "vpst\;vstrwt.32\t%q2, [%0, %q1]"
4817 [(set_attr "length" "8")])
4819 ;;
4820 ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u]
4821 ;;
4822 (define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si"
4823 [(match_operand:V4SI 0 "mve_scatter_memory")
4824 (match_operand:V4SI 1 "s_register_operand")
4825 (match_operand:V4SI 2 "s_register_operand")
4826 (match_operand:V4BI 3 "vpr_register_operand")
4827 (unspec:V4SI [(const_int 0)] VSTRWSOQ)]
4828 "TARGET_HAVE_MVE"
4829 {
4830 rtx ind = XEXP (operands[0], 0);
4831 gcc_assert (REG_P (ind));
4832 emit_insn (gen_mve_vstrwq_scatter_offset_p_<supf>v4si_insn (ind, operands[1],
4833 operands[2],
4834 operands[3]));
4835 DONE;
4836 })
4838 (define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si_insn"
4839 [(set (mem:BLK (scratch))
4840 (unspec:BLK
4841 [(match_operand:SI 0 "register_operand" "r")
4842 (match_operand:V4SI 1 "s_register_operand" "w")
4843 (match_operand:V4SI 2 "s_register_operand" "w")
4844 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4845 VSTRWSOQ))]
4846 "TARGET_HAVE_MVE"
4847 "vpst\;vstrwt.32\t%q2, [%0, %q1]"
4848 [(set_attr "length" "8")])
4850 ;;
4851 ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u]
4852 ;;
4853 (define_expand "mve_vstrwq_scatter_offset_<supf>v4si"
4854 [(match_operand:V4SI 0 "mve_scatter_memory")
4855 (match_operand:V4SI 1 "s_register_operand")
4856 (match_operand:V4SI 2 "s_register_operand")
4857 (unspec:V4SI [(const_int 0)] VSTRWSOQ)]
4858 "TARGET_HAVE_MVE"
4859 {
4860 rtx ind = XEXP (operands[0], 0);
4861 gcc_assert (REG_P (ind));
4862 emit_insn (gen_mve_vstrwq_scatter_offset_<supf>v4si_insn (ind, operands[1],
4863 operands[2]));
4864 DONE;
4865 })
4867 (define_insn "mve_vstrwq_scatter_offset_<supf>v4si_insn"
4868 [(set (mem:BLK (scratch))
4869 (unspec:BLK
4870 [(match_operand:SI 0 "register_operand" "r")
4871 (match_operand:V4SI 1 "s_register_operand" "w")
4872 (match_operand:V4SI 2 "s_register_operand" "w")]
4873 VSTRWSOQ))]
4874 "TARGET_HAVE_MVE"
4875 "vstrw.32\t%q2, [%0, %q1]"
4876 [(set_attr "length" "4")])
4878 ;;
4879 ;; [vstrwq_scatter_shifted_offset_f]
4880 ;;
4881 (define_expand "mve_vstrwq_scatter_shifted_offset_fv4sf"
4882 [(match_operand:V4SI 0 "mve_scatter_memory")
4883 (match_operand:V4SI 1 "s_register_operand")
4884 (match_operand:V4SF 2 "s_register_operand")
4885 (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)]
4886 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4887 {
4888 rtx ind = XEXP (operands[0], 0);
4889 gcc_assert (REG_P (ind));
4890 emit_insn (gen_mve_vstrwq_scatter_shifted_offset_fv4sf_insn (ind, operands[1],
4891 operands[2]));
4892 DONE;
4893 })
4895 (define_insn "mve_vstrwq_scatter_shifted_offset_fv4sf_insn"
4896 [(set (mem:BLK (scratch))
4897 (unspec:BLK
4898 [(match_operand:SI 0 "register_operand" "r")
4899 (match_operand:V4SI 1 "s_register_operand" "w")
4900 (match_operand:V4SF 2 "s_register_operand" "w")]
4901 VSTRWQSSO_F))]
4902 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4903 "vstrw.32\t%q2, [%0, %q1, uxtw #2]"
4904 [(set_attr "length" "8")])
4906 ;;
4907 ;; [vstrwq_scatter_shifted_offset_p_f]
4908 ;;
4909 (define_expand "mve_vstrwq_scatter_shifted_offset_p_fv4sf"
4910 [(match_operand:V4SI 0 "mve_scatter_memory")
4911 (match_operand:V4SI 1 "s_register_operand")
4912 (match_operand:V4SF 2 "s_register_operand")
4913 (match_operand:V4BI 3 "vpr_register_operand")
4914 (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)]
4915 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4916 {
4917 rtx ind = XEXP (operands[0], 0);
4918 gcc_assert (REG_P (ind));
4919 emit_insn (
4920 gen_mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn (ind, operands[1],
4921 operands[2],
4922 operands[3]));
4923 DONE;
4924 })
4926 (define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn"
4927 [(set (mem:BLK (scratch))
4928 (unspec:BLK
4929 [(match_operand:SI 0 "register_operand" "r")
4930 (match_operand:V4SI 1 "s_register_operand" "w")
4931 (match_operand:V4SF 2 "s_register_operand" "w")
4932 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4933 VSTRWQSSO_F))]
4934 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
4935 "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]"
4936 [(set_attr "length" "8")])
4938 ;;
4939 ;; [vstrwq_scatter_shifted_offset_p_s vstrwq_scatter_shifted_offset_p_u]
4940 ;;
4941 (define_expand "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si"
4942 [(match_operand:V4SI 0 "mve_scatter_memory")
4943 (match_operand:V4SI 1 "s_register_operand")
4944 (match_operand:V4SI 2 "s_register_operand")
4945 (match_operand:V4BI 3 "vpr_register_operand")
4946 (unspec:V4SI [(const_int 0)] VSTRWSSOQ)]
4947 "TARGET_HAVE_MVE"
4948 {
4949 rtx ind = XEXP (operands[0], 0);
4950 gcc_assert (REG_P (ind));
4951 emit_insn (
4952 gen_mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn (ind, operands[1],
4953 operands[2],
4954 operands[3]));
4955 DONE;
4956 })
4958 (define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn"
4959 [(set (mem:BLK (scratch))
4960 (unspec:BLK
4961 [(match_operand:SI 0 "register_operand" "r")
4962 (match_operand:V4SI 1 "s_register_operand" "w")
4963 (match_operand:V4SI 2 "s_register_operand" "w")
4964 (match_operand:V4BI 3 "vpr_register_operand" "Up")]
4965 VSTRWSSOQ))]
4966 "TARGET_HAVE_MVE"
4967 "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]"
4968 [(set_attr "length" "8")])
4970 ;;
4971 ;; [vstrwq_scatter_shifted_offset_s vstrwq_scatter_shifted_offset_u]
4972 ;;
4973 (define_expand "mve_vstrwq_scatter_shifted_offset_<supf>v4si"
4974 [(match_operand:V4SI 0 "mve_scatter_memory")
4975 (match_operand:V4SI 1 "s_register_operand")
4976 (match_operand:V4SI 2 "s_register_operand")
4977 (unspec:V4SI [(const_int 0)] VSTRWSSOQ)]
4978 "TARGET_HAVE_MVE"
4979 {
4980 rtx ind = XEXP (operands[0], 0);
4981 gcc_assert (REG_P (ind));
4982 emit_insn (
4983 gen_mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn (ind, operands[1],
4984 operands[2]));
4985 DONE;
4986 })
4988 (define_insn "mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn"
4989 [(set (mem:BLK (scratch))
4990 (unspec:BLK
4991 [(match_operand:SI 0 "register_operand" "r")
4992 (match_operand:V4SI 1 "s_register_operand" "w")
4993 (match_operand:V4SI 2 "s_register_operand" "w")]
4994 VSTRWSSOQ))]
4995 "TARGET_HAVE_MVE"
4996 "vstrw.32\t%q2, [%0, %q1, uxtw #2]"
4997 [(set_attr "length" "4")])
4999 ;;
5000 ;; [vidupq_n_u])
5001 ;;
5002 (define_expand "mve_vidupq_n_u<mode>"
5003 [(match_operand:MVE_2 0 "s_register_operand")
5004 (match_operand:SI 1 "s_register_operand")
5005 (match_operand:SI 2 "mve_imm_selective_upto_8")]
5006 "TARGET_HAVE_MVE"
5007 {
5008 rtx temp = gen_reg_rtx (SImode);
5009 emit_move_insn (temp, operands[1]);
5010 rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode);
5011 emit_insn (gen_mve_vidupq_u<mode>_insn (operands[0], temp, operands[1],
5012 operands[2], inc));
5013 DONE;
5014 })
5016 ;;
5017 ;; [vidupq_u_insn])
5018 ;;
5019 (define_insn "mve_vidupq_u<mode>_insn"
5020 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
5021 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
5022 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")]
5023 VIDUPQ))
5024 (set (match_operand:SI 1 "s_register_operand" "=Te")
5025 (plus:SI (match_dup 2)
5026 (match_operand:SI 4 "immediate_operand" "i")))]
5027 "TARGET_HAVE_MVE"
5028 "vidup.u%#<V_sz_elem>\t%q0, %1, %3")
5030 ;;
5031 ;; [vidupq_m_n_u])
5032 ;;
5033 (define_expand "mve_vidupq_m_n_u<mode>"
5034 [(match_operand:MVE_2 0 "s_register_operand")
5035 (match_operand:MVE_2 1 "s_register_operand")
5036 (match_operand:SI 2 "s_register_operand")
5037 (match_operand:SI 3 "mve_imm_selective_upto_8")
5038 (match_operand:<MVE_VPRED> 4 "vpr_register_operand")]
5039 "TARGET_HAVE_MVE"
5040 {
5041 rtx temp = gen_reg_rtx (SImode);
5042 emit_move_insn (temp, operands[2]);
5043 rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode);
5044 emit_insn (gen_mve_vidupq_m_wb_u<mode>_insn(operands[0], operands[1], temp,
5045 operands[2], operands[3],
5046 operands[4], inc));
5047 DONE;
5048 })
5050 ;;
5051 ;; [vidupq_m_wb_u_insn])
5052 ;;
5053 (define_insn "mve_vidupq_m_wb_u<mode>_insn"
5054 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
5055 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5056 (match_operand:SI 3 "s_register_operand" "2")
5057 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
5058 (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")]
5059 VIDUPQ_M))
5060 (set (match_operand:SI 2 "s_register_operand" "=Te")
5061 (plus:SI (match_dup 3)
5062 (match_operand:SI 6 "immediate_operand" "i")))]
5063 "TARGET_HAVE_MVE"
5064 "vpst\;\tvidupt.u%#<V_sz_elem>\t%q0, %2, %4"
5065 [(set_attr "length""8")])
5067 ;;
5068 ;; [vddupq_n_u])
5069 ;;
5070 (define_expand "mve_vddupq_n_u<mode>"
5071 [(match_operand:MVE_2 0 "s_register_operand")
5072 (match_operand:SI 1 "s_register_operand")
5073 (match_operand:SI 2 "mve_imm_selective_upto_8")]
5074 "TARGET_HAVE_MVE"
5075 {
5076 rtx temp = gen_reg_rtx (SImode);
5077 emit_move_insn (temp, operands[1]);
5078 rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode);
5079 emit_insn (gen_mve_vddupq_u<mode>_insn (operands[0], temp, operands[1],
5080 operands[2], inc));
5081 DONE;
5082 })
5084 ;;
5085 ;; [vddupq_u_insn])
5086 ;;
5087 (define_insn "mve_vddupq_u<mode>_insn"
5088 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
5089 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
5090 (match_operand:SI 3 "immediate_operand" "i")]
5091 VDDUPQ))
5092 (set (match_operand:SI 1 "s_register_operand" "=Te")
5093 (minus:SI (match_dup 2)
5094 (match_operand:SI 4 "immediate_operand" "i")))]
5095 "TARGET_HAVE_MVE"
5096 "vddup.u%#<V_sz_elem>\t%q0, %1, %3")
5098 ;;
5099 ;; [vddupq_m_n_u])
5100 ;;
5101 (define_expand "mve_vddupq_m_n_u<mode>"
5102 [(match_operand:MVE_2 0 "s_register_operand")
5103 (match_operand:MVE_2 1 "s_register_operand")
5104 (match_operand:SI 2 "s_register_operand")
5105 (match_operand:SI 3 "mve_imm_selective_upto_8")
5106 (match_operand:<MVE_VPRED> 4 "vpr_register_operand")]
5107 "TARGET_HAVE_MVE"
5108 {
5109 rtx temp = gen_reg_rtx (SImode);
5110 emit_move_insn (temp, operands[2]);
5111 rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode);
5112 emit_insn (gen_mve_vddupq_m_wb_u<mode>_insn(operands[0], operands[1], temp,
5113 operands[2], operands[3],
5114 operands[4], inc));
5115 DONE;
5116 })
5118 ;;
5119 ;; [vddupq_m_wb_u_insn])
5120 ;;
5121 (define_insn "mve_vddupq_m_wb_u<mode>_insn"
5122 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
5123 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
5124 (match_operand:SI 3 "s_register_operand" "2")
5125 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")
5126 (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")]
5127 VDDUPQ_M))
5128 (set (match_operand:SI 2 "s_register_operand" "=Te")
5129 (minus:SI (match_dup 3)
5130 (match_operand:SI 6 "immediate_operand" "i")))]
5131 "TARGET_HAVE_MVE"
5132 "vpst\;vddupt.u%#<V_sz_elem>\t%q0, %2, %4"
5133 [(set_attr "length""8")])
5135 ;;
5136 ;; [vdwdupq_n_u])
5137 ;;
5138 (define_expand "mve_vdwdupq_n_u<mode>"
5139 [(match_operand:MVE_2 0 "s_register_operand")
5140 (match_operand:SI 1 "s_register_operand")
5141 (match_operand:DI 2 "s_register_operand")
5142 (match_operand:SI 3 "mve_imm_selective_upto_8")]
5143 "TARGET_HAVE_MVE"
5144 {
5145 rtx ignore_wb = gen_reg_rtx (SImode);
5146 emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (operands[0], ignore_wb,
5147 operands[1], operands[2],
5148 operands[3]));
5149 DONE;
5150 })
5152 ;;
5153 ;; [vdwdupq_wb_u])
5154 ;;
5155 (define_expand "mve_vdwdupq_wb_u<mode>"
5156 [(match_operand:SI 0 "s_register_operand")
5157 (match_operand:SI 1 "s_register_operand")
5158 (match_operand:DI 2 "s_register_operand")
5159 (match_operand:SI 3 "mve_imm_selective_upto_8")
5160 (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
5161 "TARGET_HAVE_MVE"
5162 {
5163 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
5164 emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (ignore_vec, operands[0],
5165 operands[1], operands[2],
5166 operands[3]));
5167 DONE;
5168 })
5170 ;;
5171 ;; [vdwdupq_wb_u_insn])
5172 ;;
5173 (define_insn "mve_vdwdupq_wb_u<mode>_insn"
5174 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
5175 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
5176 (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
5177 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
5178 VDWDUPQ))
5179 (set (match_operand:SI 1 "s_register_operand" "=Te")
5180 (unspec:SI [(match_dup 2)
5181 (subreg:SI (match_dup 3) 4)
5182 (match_dup 4)]
5183 VDWDUPQ))]
5184 "TARGET_HAVE_MVE"
5185 "vdwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4"
5186 )
5188 ;;
5189 ;; [vdwdupq_m_n_u])
5190 ;;
5191 (define_expand "mve_vdwdupq_m_n_u<mode>"
5192 [(match_operand:MVE_2 0 "s_register_operand")
5193 (match_operand:MVE_2 1 "s_register_operand")
5194 (match_operand:SI 2 "s_register_operand")
5195 (match_operand:DI 3 "s_register_operand")
5196 (match_operand:SI 4 "mve_imm_selective_upto_8")
5197 (match_operand:<MVE_VPRED> 5 "vpr_register_operand")]
5198 "TARGET_HAVE_MVE"
5199 {
5200 rtx ignore_wb = gen_reg_rtx (SImode);
5201 emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb,
5202 operands[1], operands[2],
5203 operands[3], operands[4],
5204 operands[5]));
5205 DONE;
5206 })
5208 ;;
5209 ;; [vdwdupq_m_wb_u])
5210 ;;
5211 (define_expand "mve_vdwdupq_m_wb_u<mode>"
5212 [(match_operand:SI 0 "s_register_operand")
5213 (match_operand:MVE_2 1 "s_register_operand")
5214 (match_operand:SI 2 "s_register_operand")
5215 (match_operand:DI 3 "s_register_operand")
5216 (match_operand:SI 4 "mve_imm_selective_upto_8")
5217 (match_operand:<MVE_VPRED> 5 "vpr_register_operand")]
5218 "TARGET_HAVE_MVE"
5219 {
5220 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
5221 emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0],
5222 operands[1], operands[2],
5223 operands[3], operands[4],
5224 operands[5]));
5225 DONE;
5226 })
5228 ;;
5229 ;; [vdwdupq_m_wb_u_insn])
5230 ;;
5231 (define_insn "mve_vdwdupq_m_wb_u<mode>_insn"
5232 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
5233 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
5234 (match_operand:SI 3 "s_register_operand" "1")
5235 (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4)
5236 (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
5237 (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")]
5238 VDWDUPQ_M))
5239 (set (match_operand:SI 1 "s_register_operand" "=Te")
5240 (unspec:SI [(match_dup 2)
5241 (match_dup 3)
5242 (subreg:SI (match_dup 4) 4)
5243 (match_dup 5)
5244 (match_dup 6)]
5245 VDWDUPQ_M))
5246 ]
5247 "TARGET_HAVE_MVE"
5248 "vpst\;vdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
5249 [(set_attr "type" "mve_move")
5250 (set_attr "length""8")])
5252 ;;
5253 ;; [viwdupq_n_u])
5254 ;;
5255 (define_expand "mve_viwdupq_n_u<mode>"
5256 [(match_operand:MVE_2 0 "s_register_operand")
5257 (match_operand:SI 1 "s_register_operand")
5258 (match_operand:DI 2 "s_register_operand")
5259 (match_operand:SI 3 "mve_imm_selective_upto_8")]
5260 "TARGET_HAVE_MVE"
5261 {
5262 rtx ignore_wb = gen_reg_rtx (SImode);
5263 emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (operands[0], ignore_wb,
5264 operands[1], operands[2],
5265 operands[3]));
5266 DONE;
5267 })
5269 ;;
5270 ;; [viwdupq_wb_u])
5271 ;;
5272 (define_expand "mve_viwdupq_wb_u<mode>"
5273 [(match_operand:SI 0 "s_register_operand")
5274 (match_operand:SI 1 "s_register_operand")
5275 (match_operand:DI 2 "s_register_operand")
5276 (match_operand:SI 3 "mve_imm_selective_upto_8")
5277 (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
5278 "TARGET_HAVE_MVE"
5279 {
5280 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
5281 emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (ignore_vec, operands[0],
5282 operands[1], operands[2],
5283 operands[3]));
5284 DONE;
5285 })
5287 ;;
5288 ;; [viwdupq_wb_u_insn])
5289 ;;
5290 (define_insn "mve_viwdupq_wb_u<mode>_insn"
5291 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
5292 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
5293 (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
5294 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
5295 VIWDUPQ))
5296 (set (match_operand:SI 1 "s_register_operand" "=Te")
5297 (unspec:SI [(match_dup 2)
5298 (subreg:SI (match_dup 3) 4)
5299 (match_dup 4)]
5300 VIWDUPQ))]
5301 "TARGET_HAVE_MVE"
5302 "viwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4"
5303 )
5305 ;;
5306 ;; [viwdupq_m_n_u])
5307 ;;
5308 (define_expand "mve_viwdupq_m_n_u<mode>"
5309 [(match_operand:MVE_2 0 "s_register_operand")
5310 (match_operand:MVE_2 1 "s_register_operand")
5311 (match_operand:SI 2 "s_register_operand")
5312 (match_operand:DI 3 "s_register_operand")
5313 (match_operand:SI 4 "mve_imm_selective_upto_8")
5314 (match_operand:<MVE_VPRED> 5 "vpr_register_operand")]
5315 "TARGET_HAVE_MVE"
5316 {
5317 rtx ignore_wb = gen_reg_rtx (SImode);
5318 emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb,
5319 operands[1], operands[2],
5320 operands[3], operands[4],
5321 operands[5]));
5322 DONE;
5323 })
5325 ;;
5326 ;; [viwdupq_m_wb_u])
5327 ;;
5328 (define_expand "mve_viwdupq_m_wb_u<mode>"
5329 [(match_operand:SI 0 "s_register_operand")
5330 (match_operand:MVE_2 1 "s_register_operand")
5331 (match_operand:SI 2 "s_register_operand")
5332 (match_operand:DI 3 "s_register_operand")
5333 (match_operand:SI 4 "mve_imm_selective_upto_8")
5334 (match_operand:<MVE_VPRED> 5 "vpr_register_operand")]
5335 "TARGET_HAVE_MVE"
5336 {
5337 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
5338 emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0],
5339 operands[1], operands[2],
5340 operands[3], operands[4],
5341 operands[5]));
5342 DONE;
5343 })
5345 ;;
5346 ;; [viwdupq_m_wb_u_insn])
5347 ;;
5348 (define_insn "mve_viwdupq_m_wb_u<mode>_insn"
5349 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
5350 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
5351 (match_operand:SI 3 "s_register_operand" "1")
5352 (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4)
5353 (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
5354 (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")]
5355 VIWDUPQ_M))
5356 (set (match_operand:SI 1 "s_register_operand" "=Te")
5357 (unspec:SI [(match_dup 2)
5358 (match_dup 3)
5359 (subreg:SI (match_dup 4) 4)
5360 (match_dup 5)
5361 (match_dup 6)]
5362 VIWDUPQ_M))
5363 ]
5364 "TARGET_HAVE_MVE"
5365 "vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
5366 [(set_attr "type" "mve_move")
5367 (set_attr "length""8")])
5369 ;;
5370 ;; [vstrwq_scatter_base_wb_s vstrwq_scatter_base_wb_u]
5371 ;;
5372 (define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si"
5373 [(set (mem:BLK (scratch))
5374 (unspec:BLK
5375 [(match_operand:V4SI 1 "s_register_operand" "0")
5376 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
5377 (match_operand:V4SI 3 "s_register_operand" "w")]
5378 VSTRWSBWBQ))
5379 (set (match_operand:V4SI 0 "s_register_operand" "=w")
5380 (unspec:V4SI [(match_dup 1) (match_dup 2)]
5381 VSTRWSBWBQ))
5382 ]
5383 "TARGET_HAVE_MVE"
5384 {
5385 rtx ops[3];
5386 ops[0] = operands[1];
5387 ops[1] = operands[2];
5388 ops[2] = operands[3];
5389 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops);
5390 return "";
5391 }
5392 [(set_attr "length" "4")])
5394 ;;
5395 ;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u]
5396 ;;
5397 (define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
5398 [(set (mem:BLK (scratch))
5399 (unspec:BLK
5400 [(match_operand:V4SI 1 "s_register_operand" "0")
5401 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
5402 (match_operand:V4SI 3 "s_register_operand" "w")
5403 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
5404 VSTRWSBWBQ))
5405 (set (match_operand:V4SI 0 "s_register_operand" "=w")
5406 (unspec:V4SI [(match_dup 1) (match_dup 2)]
5407 VSTRWSBWBQ))
5408 ]
5409 "TARGET_HAVE_MVE"
5410 {
5411 rtx ops[3];
5412 ops[0] = operands[1];
5413 ops[1] = operands[2];
5414 ops[2] = operands[3];
5415 output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
5416 return "";
5417 }
5418 [(set_attr "length" "8")])
5420 ;;
5421 ;; [vstrwq_scatter_base_wb_f]
5422 ;;
5423 (define_insn "mve_vstrwq_scatter_base_wb_fv4sf"
5424 [(set (mem:BLK (scratch))
5425 (unspec:BLK
5426 [(match_operand:V4SI 1 "s_register_operand" "0")
5427 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
5428 (match_operand:V4SF 3 "s_register_operand" "w")]
5429 VSTRWQSBWB_F))
5430 (set (match_operand:V4SI 0 "s_register_operand" "=w")
5431 (unspec:V4SI [(match_dup 1) (match_dup 2)]
5432 VSTRWQSBWB_F))
5433 ]
5434 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5435 {
5436 rtx ops[3];
5437 ops[0] = operands[1];
5438 ops[1] = operands[2];
5439 ops[2] = operands[3];
5440 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops);
5441 return "";
5442 }
5443 [(set_attr "length" "4")])
5445 ;;
5446 ;; [vstrwq_scatter_base_wb_p_f]
5447 ;;
5448 (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf"
5449 [(set (mem:BLK (scratch))
5450 (unspec:BLK
5451 [(match_operand:V4SI 1 "s_register_operand" "0")
5452 (match_operand:SI 2 "mve_vstrw_immediate" "Rl")
5453 (match_operand:V4SF 3 "s_register_operand" "w")
5454 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
5455 VSTRWQSBWB_F))
5456 (set (match_operand:V4SI 0 "s_register_operand" "=w")
5457 (unspec:V4SI [(match_dup 1) (match_dup 2)]
5458 VSTRWQSBWB_F))
5459 ]
5460 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5461 {
5462 rtx ops[3];
5463 ops[0] = operands[1];
5464 ops[1] = operands[2];
5465 ops[2] = operands[3];
5466 output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops);
5467 return "";
5468 }
5469 [(set_attr "length" "8")])
5471 ;;
5472 ;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u]
5473 ;;
5474 (define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di"
5475 [(set (mem:BLK (scratch))
5476 (unspec:BLK
5477 [(match_operand:V2DI 1 "s_register_operand" "0")
5478 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
5479 (match_operand:V2DI 3 "s_register_operand" "w")]
5480 VSTRDSBWBQ))
5481 (set (match_operand:V2DI 0 "s_register_operand" "=&w")
5482 (unspec:V2DI [(match_dup 1) (match_dup 2)]
5483 VSTRDSBWBQ))
5484 ]
5485 "TARGET_HAVE_MVE"
5486 {
5487 rtx ops[3];
5488 ops[0] = operands[1];
5489 ops[1] = operands[2];
5490 ops[2] = operands[3];
5491 output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]!",ops);
5492 return "";
5493 }
5494 [(set_attr "length" "4")])
5496 ;;
5497 ;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u]
5498 ;;
5499 (define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
5500 [(set (mem:BLK (scratch))
5501 (unspec:BLK
5502 [(match_operand:V2DI 1 "s_register_operand" "0")
5503 (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
5504 (match_operand:V2DI 3 "s_register_operand" "w")
5505 (match_operand:V2QI 4 "vpr_register_operand" "Up")]
5506 VSTRDSBWBQ))
5507 (set (match_operand:V2DI 0 "s_register_operand" "=w")
5508 (unspec:V2DI [(match_dup 1) (match_dup 2)]
5509 VSTRDSBWBQ))
5510 ]
5511 "TARGET_HAVE_MVE"
5512 {
5513 rtx ops[3];
5514 ops[0] = operands[1];
5515 ops[1] = operands[2];
5516 ops[2] = operands[3];
5517 output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops);
5518 return "";
5519 }
5520 [(set_attr "length" "8")])
5522 (define_expand "mve_vldrwq_gather_base_wb_<supf>v4si"
5523 [(match_operand:V4SI 0 "s_register_operand")
5524 (match_operand:V4SI 1 "s_register_operand")
5525 (match_operand:SI 2 "mve_vldrd_immediate")
5526 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
5527 "TARGET_HAVE_MVE"
5528 {
5529 rtx ignore_result = gen_reg_rtx (V4SImode);
5530 emit_insn (
5531 gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (ignore_result, operands[0],
5532 operands[1], operands[2]));
5533 DONE;
5534 })
5536 (define_expand "mve_vldrwq_gather_base_nowb_<supf>v4si"
5537 [(match_operand:V4SI 0 "s_register_operand")
5538 (match_operand:V4SI 1 "s_register_operand")
5539 (match_operand:SI 2 "mve_vldrd_immediate")
5540 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
5541 "TARGET_HAVE_MVE"
5542 {
5543 rtx ignore_wb = gen_reg_rtx (V4SImode);
5544 emit_insn (
5545 gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (operands[0], ignore_wb,
5546 operands[1], operands[2]));
5547 DONE;
5548 })
5550 ;;
5551 ;; [vldrwq_gather_base_wb_s vldrwq_gather_base_wb_u]
5552 ;;
5553 (define_insn "mve_vldrwq_gather_base_wb_<supf>v4si_insn"
5554 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
5555 (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1")
5556 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
5557 (mem:BLK (scratch))]
5558 VLDRWGBWBQ))
5559 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
5560 (unspec:V4SI [(match_dup 2) (match_dup 3)]
5561 VLDRWGBWBQ))
5562 ]
5563 "TARGET_HAVE_MVE"
5564 {
5565 rtx ops[3];
5566 ops[0] = operands[0];
5567 ops[1] = operands[2];
5568 ops[2] = operands[3];
5569 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops);
5570 return "";
5571 }
5572 [(set_attr "length" "4")])
5574 (define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si"
5575 [(match_operand:V4SI 0 "s_register_operand")
5576 (match_operand:V4SI 1 "s_register_operand")
5577 (match_operand:SI 2 "mve_vldrd_immediate")
5578 (match_operand:V4BI 3 "vpr_register_operand")
5579 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
5580 "TARGET_HAVE_MVE"
5581 {
5582 rtx ignore_result = gen_reg_rtx (V4SImode);
5583 emit_insn (
5584 gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (ignore_result, operands[0],
5585 operands[1], operands[2],
5586 operands[3]));
5587 DONE;
5588 })
5589 (define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si"
5590 [(match_operand:V4SI 0 "s_register_operand")
5591 (match_operand:V4SI 1 "s_register_operand")
5592 (match_operand:SI 2 "mve_vldrd_immediate")
5593 (match_operand:V4BI 3 "vpr_register_operand")
5594 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)]
5595 "TARGET_HAVE_MVE"
5596 {
5597 rtx ignore_wb = gen_reg_rtx (V4SImode);
5598 emit_insn (
5599 gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (operands[0], ignore_wb,
5600 operands[1], operands[2],
5601 operands[3]));
5602 DONE;
5603 })
5605 ;;
5606 ;; [vldrwq_gather_base_wb_z_s vldrwq_gather_base_wb_z_u]
5607 ;;
5608 (define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn"
5609 [(set (match_operand:V4SI 0 "s_register_operand" "=&w")
5610 (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1")
5611 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
5612 (match_operand:V4BI 4 "vpr_register_operand" "Up")
5613 (mem:BLK (scratch))]
5614 VLDRWGBWBQ))
5615 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
5616 (unspec:V4SI [(match_dup 2) (match_dup 3)]
5617 VLDRWGBWBQ))
5618 ]
5619 "TARGET_HAVE_MVE"
5620 {
5621 rtx ops[3];
5622 ops[0] = operands[0];
5623 ops[1] = operands[2];
5624 ops[2] = operands[3];
5625 output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops);
5626 return "";
5627 }
5628 [(set_attr "length" "8")])
5630 (define_expand "mve_vldrwq_gather_base_wb_fv4sf"
5631 [(match_operand:V4SI 0 "s_register_operand")
5632 (match_operand:V4SI 1 "s_register_operand")
5633 (match_operand:SI 2 "mve_vldrd_immediate")
5634 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
5635 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5636 {
5637 rtx ignore_result = gen_reg_rtx (V4SFmode);
5638 emit_insn (
5639 gen_mve_vldrwq_gather_base_wb_fv4sf_insn (ignore_result, operands[0],
5640 operands[1], operands[2]));
5641 DONE;
5642 })
5644 (define_expand "mve_vldrwq_gather_base_nowb_fv4sf"
5645 [(match_operand:V4SF 0 "s_register_operand")
5646 (match_operand:V4SI 1 "s_register_operand")
5647 (match_operand:SI 2 "mve_vldrd_immediate")
5648 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
5649 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5650 {
5651 rtx ignore_wb = gen_reg_rtx (V4SImode);
5652 emit_insn (
5653 gen_mve_vldrwq_gather_base_wb_fv4sf_insn (operands[0], ignore_wb,
5654 operands[1], operands[2]));
5655 DONE;
5656 })
5658 ;;
5659 ;; [vldrwq_gather_base_wb_f]
5660 ;;
5661 (define_insn "mve_vldrwq_gather_base_wb_fv4sf_insn"
5662 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
5663 (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1")
5664 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
5665 (mem:BLK (scratch))]
5666 VLDRWQGBWB_F))
5667 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
5668 (unspec:V4SI [(match_dup 2) (match_dup 3)]
5669 VLDRWQGBWB_F))
5670 ]
5671 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5672 {
5673 rtx ops[3];
5674 ops[0] = operands[0];
5675 ops[1] = operands[2];
5676 ops[2] = operands[3];
5677 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops);
5678 return "";
5679 }
5680 [(set_attr "length" "4")])
5682 (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf"
5683 [(match_operand:V4SI 0 "s_register_operand")
5684 (match_operand:V4SI 1 "s_register_operand")
5685 (match_operand:SI 2 "mve_vldrd_immediate")
5686 (match_operand:V4BI 3 "vpr_register_operand")
5687 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
5688 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5689 {
5690 rtx ignore_result = gen_reg_rtx (V4SFmode);
5691 emit_insn (
5692 gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (ignore_result, operands[0],
5693 operands[1], operands[2],
5694 operands[3]));
5695 DONE;
5696 })
5698 (define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf"
5699 [(match_operand:V4SF 0 "s_register_operand")
5700 (match_operand:V4SI 1 "s_register_operand")
5701 (match_operand:SI 2 "mve_vldrd_immediate")
5702 (match_operand:V4BI 3 "vpr_register_operand")
5703 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)]
5704 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5705 {
5706 rtx ignore_wb = gen_reg_rtx (V4SImode);
5707 emit_insn (
5708 gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (operands[0], ignore_wb,
5709 operands[1], operands[2],
5710 operands[3]));
5711 DONE;
5712 })
5714 ;;
5715 ;; [vldrwq_gather_base_wb_z_f]
5716 ;;
5717 (define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn"
5718 [(set (match_operand:V4SF 0 "s_register_operand" "=&w")
5719 (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1")
5720 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
5721 (match_operand:V4BI 4 "vpr_register_operand" "Up")
5722 (mem:BLK (scratch))]
5723 VLDRWQGBWB_F))
5724 (set (match_operand:V4SI 1 "s_register_operand" "=&w")
5725 (unspec:V4SI [(match_dup 2) (match_dup 3)]
5726 VLDRWQGBWB_F))
5727 ]
5728 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
5729 {
5730 rtx ops[3];
5731 ops[0] = operands[0];
5732 ops[1] = operands[2];
5733 ops[2] = operands[3];
5734 output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops);
5735 return "";
5736 }
5737 [(set_attr "length" "8")])
5739 (define_expand "mve_vldrdq_gather_base_wb_<supf>v2di"
5740 [(match_operand:V2DI 0 "s_register_operand")
5741 (match_operand:V2DI 1 "s_register_operand")
5742 (match_operand:SI 2 "mve_vldrd_immediate")
5743 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
5744 "TARGET_HAVE_MVE"
5745 {
5746 rtx ignore_result = gen_reg_rtx (V2DImode);
5747 emit_insn (
5748 gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (ignore_result, operands[0],
5749 operands[1], operands[2]));
5750 DONE;
5751 })
5753 (define_expand "mve_vldrdq_gather_base_nowb_<supf>v2di"
5754 [(match_operand:V2DI 0 "s_register_operand")
5755 (match_operand:V2DI 1 "s_register_operand")
5756 (match_operand:SI 2 "mve_vldrd_immediate")
5757 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
5758 "TARGET_HAVE_MVE"
5759 {
5760 rtx ignore_wb = gen_reg_rtx (V2DImode);
5761 emit_insn (
5762 gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (operands[0], ignore_wb,
5763 operands[1], operands[2]));
5764 DONE;
5765 })
5768 ;;
5769 ;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u]
5770 ;;
5771 (define_insn "mve_vldrdq_gather_base_wb_<supf>v2di_insn"
5772 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
5773 (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1")
5774 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
5775 (mem:BLK (scratch))]
5776 VLDRDGBWBQ))
5777 (set (match_operand:V2DI 1 "s_register_operand" "=&w")
5778 (unspec:V2DI [(match_dup 2) (match_dup 3)]
5779 VLDRDGBWBQ))
5780 ]
5781 "TARGET_HAVE_MVE"
5782 {
5783 rtx ops[3];
5784 ops[0] = operands[0];
5785 ops[1] = operands[2];
5786 ops[2] = operands[3];
5787 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]!",ops);
5788 return "";
5789 }
5790 [(set_attr "length" "4")])
5792 (define_expand "mve_vldrdq_gather_base_wb_z_<supf>v2di"
5793 [(match_operand:V2DI 0 "s_register_operand")
5794 (match_operand:V2DI 1 "s_register_operand")
5795 (match_operand:SI 2 "mve_vldrd_immediate")
5796 (match_operand:V2QI 3 "vpr_register_operand")
5797 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
5798 "TARGET_HAVE_MVE"
5799 {
5800 rtx ignore_result = gen_reg_rtx (V2DImode);
5801 emit_insn (
5802 gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (ignore_result, operands[0],
5803 operands[1], operands[2],
5804 operands[3]));
5805 DONE;
5806 })
5808 (define_expand "mve_vldrdq_gather_base_nowb_z_<supf>v2di"
5809 [(match_operand:V2DI 0 "s_register_operand")
5810 (match_operand:V2DI 1 "s_register_operand")
5811 (match_operand:SI 2 "mve_vldrd_immediate")
5812 (match_operand:V2QI 3 "vpr_register_operand")
5813 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)]
5814 "TARGET_HAVE_MVE"
5815 {
5816 rtx ignore_wb = gen_reg_rtx (V2DImode);
5817 emit_insn (
5818 gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (operands[0], ignore_wb,
5819 operands[1], operands[2],
5820 operands[3]));
5821 DONE;
5822 })
5824 (define_insn "get_fpscr_nzcvqc"
5825 [(set (match_operand:SI 0 "register_operand" "=r")
5826 (unspec_volatile:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))]
5827 "TARGET_HAVE_MVE"
5828 "vmrs\\t%0, FPSCR_nzcvqc"
5829 [(set_attr "type" "mve_move")])
5831 (define_insn "set_fpscr_nzcvqc"
5832 [(set (reg:SI VFPCC_REGNUM)
5833 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
5834 VUNSPEC_SET_FPSCR_NZCVQC))]
5835 "TARGET_HAVE_MVE"
5836 "vmsr\\tFPSCR_nzcvqc, %0"
5837 [(set_attr "type" "mve_move")])
5839 ;;
5840 ;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u]
5841 ;;
5842 (define_insn "mve_vldrdq_gather_base_wb_z_<supf>v2di_insn"
5843 [(set (match_operand:V2DI 0 "s_register_operand" "=&w")
5844 (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1")
5845 (match_operand:SI 3 "mve_vldrd_immediate" "Ri")
5846 (match_operand:V2QI 4 "vpr_register_operand" "Up")
5847 (mem:BLK (scratch))]
5848 VLDRDGBWBQ))
5849 (set (match_operand:V2DI 1 "s_register_operand" "=&w")
5850 (unspec:V2DI [(match_dup 2) (match_dup 3)]
5851 VLDRDGBWBQ))
5852 ]
5853 "TARGET_HAVE_MVE"
5854 {
5855 rtx ops[3];
5856 ops[0] = operands[0];
5857 ops[1] = operands[2];
5858 ops[2] = operands[3];
5859 output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops);
5860 return "";
5861 }
5862 [(set_attr "length" "8")])
5863 ;;
5864 ;; [vadciq_m_s, vadciq_m_u])
5865 ;;
5866 (define_insn "mve_vadciq_m_<supf>v4si"
5867 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
5868 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
5869 (match_operand:V4SI 2 "s_register_operand" "w")
5870 (match_operand:V4SI 3 "s_register_operand" "w")
5871 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
5872 VADCIQ_M))
5873 (set (reg:SI VFPCC_REGNUM)
5874 (unspec:SI [(const_int 0)]
5875 VADCIQ_M))
5876 ]
5877 "TARGET_HAVE_MVE"
5878 "vpst\;vadcit.i32\t%q0, %q2, %q3"
5879 [(set_attr "type" "mve_move")
5880 (set_attr "length" "8")])
5882 ;;
5883 ;; [vadciq_u, vadciq_s])
5884 ;;
5885 (define_insn "mve_vadciq_<supf>v4si"
5886 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
5887 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
5888 (match_operand:V4SI 2 "s_register_operand" "w")]
5889 VADCIQ))
5890 (set (reg:SI VFPCC_REGNUM)
5891 (unspec:SI [(const_int 0)]
5892 VADCIQ))
5893 ]
5894 "TARGET_HAVE_MVE"
5895 "vadci.i32\t%q0, %q1, %q2"
5896 [(set_attr "type" "mve_move")
5897 (set_attr "length" "4")])
5899 ;;
5900 ;; [vadcq_m_s, vadcq_m_u])
5901 ;;
5902 (define_insn "mve_vadcq_m_<supf>v4si"
5903 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
5904 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
5905 (match_operand:V4SI 2 "s_register_operand" "w")
5906 (match_operand:V4SI 3 "s_register_operand" "w")
5907 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
5908 VADCQ_M))
5909 (set (reg:SI VFPCC_REGNUM)
5910 (unspec:SI [(reg:SI VFPCC_REGNUM)]
5911 VADCQ_M))
5912 ]
5913 "TARGET_HAVE_MVE"
5914 "vpst\;vadct.i32\t%q0, %q2, %q3"
5915 [(set_attr "type" "mve_move")
5916 (set_attr "length" "8")])
5918 ;;
5919 ;; [vadcq_u, vadcq_s])
5920 ;;
5921 (define_insn "mve_vadcq_<supf>v4si"
5922 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
5923 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
5924 (match_operand:V4SI 2 "s_register_operand" "w")]
5925 VADCQ))
5926 (set (reg:SI VFPCC_REGNUM)
5927 (unspec:SI [(reg:SI VFPCC_REGNUM)]
5928 VADCQ))
5929 ]
5930 "TARGET_HAVE_MVE"
5931 "vadc.i32\t%q0, %q1, %q2"
5932 [(set_attr "type" "mve_move")
5933 (set_attr "length" "4")
5934 (set_attr "conds" "set")])
5936 ;;
5937 ;; [vsbciq_m_u, vsbciq_m_s])
5938 ;;
5939 (define_insn "mve_vsbciq_m_<supf>v4si"
5940 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
5941 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
5942 (match_operand:V4SI 2 "s_register_operand" "w")
5943 (match_operand:V4SI 3 "s_register_operand" "w")
5944 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
5945 VSBCIQ_M))
5946 (set (reg:SI VFPCC_REGNUM)
5947 (unspec:SI [(const_int 0)]
5948 VSBCIQ_M))
5949 ]
5950 "TARGET_HAVE_MVE"
5951 "vpst\;vsbcit.i32\t%q0, %q2, %q3"
5952 [(set_attr "type" "mve_move")
5953 (set_attr "length" "8")])
5955 ;;
5956 ;; [vsbciq_s, vsbciq_u])
5957 ;;
5958 (define_insn "mve_vsbciq_<supf>v4si"
5959 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
5960 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
5961 (match_operand:V4SI 2 "s_register_operand" "w")]
5962 VSBCIQ))
5963 (set (reg:SI VFPCC_REGNUM)
5964 (unspec:SI [(const_int 0)]
5965 VSBCIQ))
5966 ]
5967 "TARGET_HAVE_MVE"
5968 "vsbci.i32\t%q0, %q1, %q2"
5969 [(set_attr "type" "mve_move")
5970 (set_attr "length" "4")])
5972 ;;
5973 ;; [vsbcq_m_u, vsbcq_m_s])
5974 ;;
5975 (define_insn "mve_vsbcq_m_<supf>v4si"
5976 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
5977 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
5978 (match_operand:V4SI 2 "s_register_operand" "w")
5979 (match_operand:V4SI 3 "s_register_operand" "w")
5980 (match_operand:V4BI 4 "vpr_register_operand" "Up")]
5981 VSBCQ_M))
5982 (set (reg:SI VFPCC_REGNUM)
5983 (unspec:SI [(reg:SI VFPCC_REGNUM)]
5984 VSBCQ_M))
5985 ]
5986 "TARGET_HAVE_MVE"
5987 "vpst\;vsbct.i32\t%q0, %q2, %q3"
5988 [(set_attr "type" "mve_move")
5989 (set_attr "length" "8")])
5991 ;;
5992 ;; [vsbcq_s, vsbcq_u])
5993 ;;
5994 (define_insn "mve_vsbcq_<supf>v4si"
5995 [(set (match_operand:V4SI 0 "s_register_operand" "=w")
5996 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
5997 (match_operand:V4SI 2 "s_register_operand" "w")]
5998 VSBCQ))
5999 (set (reg:SI VFPCC_REGNUM)
6000 (unspec:SI [(reg:SI VFPCC_REGNUM)]
6001 VSBCQ))
6002 ]
6003 "TARGET_HAVE_MVE"
6004 "vsbc.i32\t%q0, %q1, %q2"
6005 [(set_attr "type" "mve_move")
6006 (set_attr "length" "4")])
6008 ;;
6009 ;; [vst2q])
6010 ;;
6011 (define_insn "mve_vst2q<mode>"
6012 [(set (match_operand:OI 0 "mve_struct_operand" "=Ug")
6013 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
6014 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
6015 VST2Q))
6016 ]
6017 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6018 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
6019 {
6020 rtx ops[4];
6021 int regno = REGNO (operands[1]);
6022 ops[0] = gen_rtx_REG (TImode, regno);
6023 ops[1] = gen_rtx_REG (TImode, regno + 4);
6024 rtx reg = operands[0];
6025 while (reg && !REG_P (reg))
6026 reg = XEXP (reg, 0);
6027 gcc_assert (REG_P (reg));
6028 ops[2] = reg;
6029 ops[3] = operands[0];
6030 output_asm_insn ("vst20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t"
6031 "vst21.<V_sz_elem>\t{%q0, %q1}, %3", ops);
6032 return "";
6033 }
6034 [(set_attr "length" "8")])
6036 ;;
6037 ;; [vld2q])
6038 ;;
6039 (define_insn "mve_vld2q<mode>"
6040 [(set (match_operand:OI 0 "s_register_operand" "=w")
6041 (unspec:OI [(match_operand:OI 1 "mve_struct_operand" "Ug")
6042 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
6043 VLD2Q))
6044 ]
6045 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6046 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
6047 {
6048 rtx ops[4];
6049 int regno = REGNO (operands[0]);
6050 ops[0] = gen_rtx_REG (TImode, regno);
6051 ops[1] = gen_rtx_REG (TImode, regno + 4);
6052 rtx reg = operands[1];
6053 while (reg && !REG_P (reg))
6054 reg = XEXP (reg, 0);
6055 gcc_assert (REG_P (reg));
6056 ops[2] = reg;
6057 ops[3] = operands[1];
6058 output_asm_insn ("vld20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t"
6059 "vld21.<V_sz_elem>\t{%q0, %q1}, %3", ops);
6060 return "";
6061 }
6062 [(set_attr "length" "8")])
6064 ;;
6065 ;; [vld4q])
6066 ;;
6067 (define_insn "mve_vld4q<mode>"
6068 [(set (match_operand:XI 0 "s_register_operand" "=w")
6069 (unspec:XI [(match_operand:XI 1 "mve_struct_operand" "Ug")
6070 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
6071 VLD4Q))
6072 ]
6073 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6074 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
6075 {
6076 rtx ops[6];
6077 int regno = REGNO (operands[0]);
6078 ops[0] = gen_rtx_REG (TImode, regno);
6079 ops[1] = gen_rtx_REG (TImode, regno+4);
6080 ops[2] = gen_rtx_REG (TImode, regno+8);
6081 ops[3] = gen_rtx_REG (TImode, regno + 12);
6082 rtx reg = operands[1];
6083 while (reg && !REG_P (reg))
6084 reg = XEXP (reg, 0);
6085 gcc_assert (REG_P (reg));
6086 ops[4] = reg;
6087 ops[5] = operands[1];
6088 output_asm_insn ("vld40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
6089 "vld41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
6090 "vld42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t"
6091 "vld43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops);
6092 return "";
6093 }
6094 [(set_attr "length" "16")])
6095 ;;
6096 ;; [vgetq_lane_u, vgetq_lane_s, vgetq_lane_f])
6097 ;;
6098 (define_insn "mve_vec_extract<mode><V_elem_l>"
6099 [(set (match_operand:<V_elem> 0 "nonimmediate_operand" "=r")
6100 (vec_select:<V_elem>
6101 (match_operand:MVE_VLD_ST 1 "s_register_operand" "w")
6102 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
6103 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6104 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
6105 {
6106 if (BYTES_BIG_ENDIAN)
6107 {
6108 int elt = INTVAL (operands[2]);
6109 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
6110 operands[2] = GEN_INT (elt);
6111 }
6112 return "vmov.<V_extr_elem>\t%0, %q1[%c2]";
6113 }
6114 [(set_attr "type" "mve_move")])
6116 (define_insn "mve_vec_extractv2didi"
6117 [(set (match_operand:DI 0 "nonimmediate_operand" "=r")
6118 (vec_select:DI
6119 (match_operand:V2DI 1 "s_register_operand" "w")
6120 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
6121 "TARGET_HAVE_MVE"
6122 {
6123 int elt = INTVAL (operands[2]);
6124 if (BYTES_BIG_ENDIAN)
6125 elt = 1 - elt;
6127 if (elt == 0)
6128 return "vmov\t%Q0, %R0, %e1";
6129 else
6130 return "vmov\t%Q0, %R0, %f1";
6131 }
6132 [(set_attr "type" "mve_move")])
6134 (define_insn "*mve_vec_extract_sext_internal<mode>"
6135 [(set (match_operand:SI 0 "s_register_operand" "=r")
6136 (sign_extend:SI
6137 (vec_select:<V_elem>
6138 (match_operand:MVE_2 1 "s_register_operand" "w")
6139 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
6140 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6141 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
6142 {
6143 if (BYTES_BIG_ENDIAN)
6144 {
6145 int elt = INTVAL (operands[2]);
6146 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
6147 operands[2] = GEN_INT (elt);
6148 }
6149 return "vmov.s<V_sz_elem>\t%0, %q1[%c2]";
6150 }
6151 [(set_attr "type" "mve_move")])
6153 (define_insn "*mve_vec_extract_zext_internal<mode>"
6154 [(set (match_operand:SI 0 "s_register_operand" "=r")
6155 (zero_extend:SI
6156 (vec_select:<V_elem>
6157 (match_operand:MVE_2 1 "s_register_operand" "w")
6158 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
6159 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6160 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
6161 {
6162 if (BYTES_BIG_ENDIAN)
6163 {
6164 int elt = INTVAL (operands[2]);
6165 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
6166 operands[2] = GEN_INT (elt);
6167 }
6168 return "vmov.u<V_sz_elem>\t%0, %q1[%c2]";
6169 }
6170 [(set_attr "type" "mve_move")])
6172 ;;
6173 ;; [vsetq_lane_u, vsetq_lane_s, vsetq_lane_f])
6174 ;;
6175 (define_insn "mve_vec_set<mode>_internal"
6176 [(set (match_operand:VQ2 0 "s_register_operand" "=w")
6177 (vec_merge:VQ2
6178 (vec_duplicate:VQ2
6179 (match_operand:<V_elem> 1 "nonimmediate_operand" "r"))
6180 (match_operand:VQ2 3 "s_register_operand" "0")
6181 (match_operand:SI 2 "immediate_operand" "i")))]
6182 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6183 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
6184 {
6185 int elt = ffs ((int) INTVAL (operands[2])) - 1;
6186 if (BYTES_BIG_ENDIAN)
6187 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
6188 operands[2] = GEN_INT (elt);
6190 return "vmov.<V_sz_elem>\t%q0[%c2], %1";
6191 }
6192 [(set_attr "type" "mve_move")])
6194 (define_insn "mve_vec_setv2di_internal"
6195 [(set (match_operand:V2DI 0 "s_register_operand" "=w")
6196 (vec_merge:V2DI
6197 (vec_duplicate:V2DI
6198 (match_operand:DI 1 "nonimmediate_operand" "r"))
6199 (match_operand:V2DI 3 "s_register_operand" "0")
6200 (match_operand:SI 2 "immediate_operand" "i")))]
6201 "TARGET_HAVE_MVE"
6202 {
6203 int elt = ffs ((int) INTVAL (operands[2])) - 1;
6204 if (BYTES_BIG_ENDIAN)
6205 elt = 1 - elt;
6207 if (elt == 0)
6208 return "vmov\t%e0, %Q1, %R1";
6209 else
6210 return "vmov\t%f0, %J1, %K1";
6211 }
6212 [(set_attr "type" "mve_move")])
6214 ;;
6215 ;; [uqrshll_di]
6216 ;;
6217 (define_insn "mve_uqrshll_sat<supf>_di"
6218 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
6219 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
6220 (match_operand:SI 2 "register_operand" "r")]
6221 UQRSHLLQ))]
6222 "TARGET_HAVE_MVE"
6223 "uqrshll%?\\t%Q1, %R1, #<supf>, %2"
6224 [(set_attr "predicable" "yes")])
6226 ;;
6227 ;; [sqrshrl_di]
6228 ;;
6229 (define_insn "mve_sqrshrl_sat<supf>_di"
6230 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
6231 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
6232 (match_operand:SI 2 "register_operand" "r")]
6233 SQRSHRLQ))]
6234 "TARGET_HAVE_MVE"
6235 "sqrshrl%?\\t%Q1, %R1, #<supf>, %2"
6236 [(set_attr "predicable" "yes")])
6238 ;;
6239 ;; [uqrshl_si]
6240 ;;
6241 (define_insn "mve_uqrshl_si"
6242 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
6243 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
6244 (match_operand:SI 2 "register_operand" "r")]
6245 UQRSHL))]
6246 "TARGET_HAVE_MVE"
6247 "uqrshl%?\\t%1, %2"
6248 [(set_attr "predicable" "yes")])
6250 ;;
6251 ;; [sqrshr_si]
6252 ;;
6253 (define_insn "mve_sqrshr_si"
6254 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
6255 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
6256 (match_operand:SI 2 "register_operand" "r")]
6257 SQRSHR))]
6258 "TARGET_HAVE_MVE"
6259 "sqrshr%?\\t%1, %2"
6260 [(set_attr "predicable" "yes")])
6262 ;;
6263 ;; [uqshll_di]
6264 ;;
6265 (define_insn "mve_uqshll_di"
6266 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
6267 (us_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0")
6268 (match_operand:SI 2 "immediate_operand" "Pg")))]
6269 "TARGET_HAVE_MVE"
6270 "uqshll%?\\t%Q1, %R1, %2"
6271 [(set_attr "predicable" "yes")])
6273 ;;
6274 ;; [urshrl_di]
6275 ;;
6276 (define_insn "mve_urshrl_di"
6277 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
6278 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
6279 (match_operand:SI 2 "immediate_operand" "Pg")]
6280 URSHRL))]
6281 "TARGET_HAVE_MVE"
6282 "urshrl%?\\t%Q1, %R1, %2"
6283 [(set_attr "predicable" "yes")])
6285 ;;
6286 ;; [uqshl_si]
6287 ;;
6288 (define_insn "mve_uqshl_si"
6289 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
6290 (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "0")
6291 (match_operand:SI 2 "immediate_operand" "Pg")))]
6292 "TARGET_HAVE_MVE"
6293 "uqshl%?\\t%1, %2"
6294 [(set_attr "predicable" "yes")])
6296 ;;
6297 ;; [urshr_si]
6298 ;;
6299 (define_insn "mve_urshr_si"
6300 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
6301 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0")
6302 (match_operand:SI 2 "immediate_operand" "Pg")]
6303 URSHR))]
6304 "TARGET_HAVE_MVE"
6305 "urshr%?\\t%1, %2"
6306 [(set_attr "predicable" "yes")])
6308 ;;
6309 ;; [sqshl_si]
6310 ;;
6311 (define_insn "mve_sqshl_si"
6312 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
6313 (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "0")
6314 (match_operand:SI 2 "immediate_operand" "Pg")))]
6315 "TARGET_HAVE_MVE"
6316 "sqshl%?\\t%1, %2"
6317 [(set_attr "predicable" "yes")])
6319 ;;
6320 ;; [srshr_si]
6321 ;;
6322 (define_insn "mve_srshr_si"
6323 [(set (match_operand:SI 0 "arm_general_register_operand" "=r")
6324 (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "0")
6325 (match_operand:SI 2 "immediate_operand" "Pg")]
6326 SRSHR))]
6327 "TARGET_HAVE_MVE"
6328 "srshr%?\\t%1, %2"
6329 [(set_attr "predicable" "yes")])
6331 ;;
6332 ;; [srshrl_di]
6333 ;;
6334 (define_insn "mve_srshrl_di"
6335 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
6336 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0")
6337 (match_operand:SI 2 "immediate_operand" "Pg")]
6338 SRSHRL))]
6339 "TARGET_HAVE_MVE"
6340 "srshrl%?\\t%Q1, %R1, %2"
6341 [(set_attr "predicable" "yes")])
6343 ;;
6344 ;; [sqshll_di]
6345 ;;
6346 (define_insn "mve_sqshll_di"
6347 [(set (match_operand:DI 0 "arm_low_register_operand" "=l")
6348 (ss_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0")
6349 (match_operand:SI 2 "immediate_operand" "Pg")))]
6350 "TARGET_HAVE_MVE"
6351 "sqshll%?\\t%Q1, %R1, %2"
6352 [(set_attr "predicable" "yes")])
6354 ;;
6355 ;; [vshlcq_m_u vshlcq_m_s]
6356 ;;
6357 (define_expand "mve_vshlcq_m_vec_<supf><mode>"
6358 [(match_operand:MVE_2 0 "s_register_operand")
6359 (match_operand:MVE_2 1 "s_register_operand")
6360 (match_operand:SI 2 "s_register_operand")
6361 (match_operand:SI 3 "mve_imm_32")
6362 (match_operand:<MVE_VPRED> 4 "vpr_register_operand")
6363 (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)]
6364 "TARGET_HAVE_MVE"
6365 {
6366 rtx ignore_wb = gen_reg_rtx (SImode);
6367 emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb, operands[1],
6368 operands[2], operands[3],
6369 operands[4]));
6370 DONE;
6371 })
6373 (define_expand "mve_vshlcq_m_carry_<supf><mode>"
6374 [(match_operand:SI 0 "s_register_operand")
6375 (match_operand:MVE_2 1 "s_register_operand")
6376 (match_operand:SI 2 "s_register_operand")
6377 (match_operand:SI 3 "mve_imm_32")
6378 (match_operand:<MVE_VPRED> 4 "vpr_register_operand")
6379 (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)]
6380 "TARGET_HAVE_MVE"
6381 {
6382 rtx ignore_vec = gen_reg_rtx (<MODE>mode);
6383 emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0],
6384 operands[1], operands[2],
6385 operands[3], operands[4]));
6386 DONE;
6387 })
6389 (define_insn "mve_vshlcq_m_<supf><mode>"
6390 [(set (match_operand:MVE_2 0 "s_register_operand" "=w")
6391 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
6392 (match_operand:SI 3 "s_register_operand" "1")
6393 (match_operand:SI 4 "mve_imm_32" "Rf")
6394 (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")]
6395 VSHLCQ_M))
6396 (set (match_operand:SI 1 "s_register_operand" "=r")
6397 (unspec:SI [(match_dup 2)
6398 (match_dup 3)
6399 (match_dup 4)
6400 (match_dup 5)]
6401 VSHLCQ_M))
6402 ]
6403 "TARGET_HAVE_MVE"
6404 "vpst\;vshlct\t%q0, %1, %4"
6405 [(set_attr "type" "mve_move")
6406 (set_attr "length" "8")])
6408 ;; CDE instructions on MVE registers.
6410 (define_insn "arm_vcx1qv16qi"
6411 [(set (match_operand:V16QI 0 "register_operand" "=t")
6412 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6413 (match_operand:SI 2 "const_int_mve_cde1_operand" "i")]
6414 UNSPEC_VCDE))]
6415 "TARGET_CDE && TARGET_HAVE_MVE"
6416 "vcx1\\tp%c1, %q0, #%c2"
6417 [(set_attr "type" "coproc")]
6418 )
6420 (define_insn "arm_vcx1qav16qi"
6421 [(set (match_operand:V16QI 0 "register_operand" "=t")
6422 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6423 (match_operand:V16QI 2 "register_operand" "0")
6424 (match_operand:SI 3 "const_int_mve_cde1_operand" "i")]
6425 UNSPEC_VCDEA))]
6426 "TARGET_CDE && TARGET_HAVE_MVE"
6427 "vcx1a\\tp%c1, %q0, #%c3"
6428 [(set_attr "type" "coproc")]
6429 )
6431 (define_insn "arm_vcx2qv16qi"
6432 [(set (match_operand:V16QI 0 "register_operand" "=t")
6433 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6434 (match_operand:V16QI 2 "register_operand" "t")
6435 (match_operand:SI 3 "const_int_mve_cde2_operand" "i")]
6436 UNSPEC_VCDE))]
6437 "TARGET_CDE && TARGET_HAVE_MVE"
6438 "vcx2\\tp%c1, %q0, %q2, #%c3"
6439 [(set_attr "type" "coproc")]
6440 )
6442 (define_insn "arm_vcx2qav16qi"
6443 [(set (match_operand:V16QI 0 "register_operand" "=t")
6444 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6445 (match_operand:V16QI 2 "register_operand" "0")
6446 (match_operand:V16QI 3 "register_operand" "t")
6447 (match_operand:SI 4 "const_int_mve_cde2_operand" "i")]
6448 UNSPEC_VCDEA))]
6449 "TARGET_CDE && TARGET_HAVE_MVE"
6450 "vcx2a\\tp%c1, %q0, %q3, #%c4"
6451 [(set_attr "type" "coproc")]
6452 )
6454 (define_insn "arm_vcx3qv16qi"
6455 [(set (match_operand:V16QI 0 "register_operand" "=t")
6456 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6457 (match_operand:V16QI 2 "register_operand" "t")
6458 (match_operand:V16QI 3 "register_operand" "t")
6459 (match_operand:SI 4 "const_int_mve_cde3_operand" "i")]
6460 UNSPEC_VCDE))]
6461 "TARGET_CDE && TARGET_HAVE_MVE"
6462 "vcx3\\tp%c1, %q0, %q2, %q3, #%c4"
6463 [(set_attr "type" "coproc")]
6464 )
6466 (define_insn "arm_vcx3qav16qi"
6467 [(set (match_operand:V16QI 0 "register_operand" "=t")
6468 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6469 (match_operand:V16QI 2 "register_operand" "0")
6470 (match_operand:V16QI 3 "register_operand" "t")
6471 (match_operand:V16QI 4 "register_operand" "t")
6472 (match_operand:SI 5 "const_int_mve_cde3_operand" "i")]
6473 UNSPEC_VCDEA))]
6474 "TARGET_CDE && TARGET_HAVE_MVE"
6475 "vcx3a\\tp%c1, %q0, %q3, %q4, #%c5"
6476 [(set_attr "type" "coproc")]
6477 )
6479 (define_insn "arm_vcx1q<a>_p_v16qi"
6480 [(set (match_operand:V16QI 0 "register_operand" "=t")
6481 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6482 (match_operand:V16QI 2 "register_operand" "0")
6483 (match_operand:SI 3 "const_int_mve_cde1_operand" "i")
6484 (match_operand:V16BI 4 "vpr_register_operand" "Up")]
6485 CDE_VCX))]
6486 "TARGET_CDE && TARGET_HAVE_MVE"
6487 "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3"
6488 [(set_attr "type" "coproc")
6489 (set_attr "length" "8")]
6490 )
6492 (define_insn "arm_vcx2q<a>_p_v16qi"
6493 [(set (match_operand:V16QI 0 "register_operand" "=t")
6494 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6495 (match_operand:V16QI 2 "register_operand" "0")
6496 (match_operand:V16QI 3 "register_operand" "t")
6497 (match_operand:SI 4 "const_int_mve_cde2_operand" "i")
6498 (match_operand:V16BI 5 "vpr_register_operand" "Up")]
6499 CDE_VCX))]
6500 "TARGET_CDE && TARGET_HAVE_MVE"
6501 "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4"
6502 [(set_attr "type" "coproc")
6503 (set_attr "length" "8")]
6504 )
6506 (define_insn "arm_vcx3q<a>_p_v16qi"
6507 [(set (match_operand:V16QI 0 "register_operand" "=t")
6508 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
6509 (match_operand:V16QI 2 "register_operand" "0")
6510 (match_operand:V16QI 3 "register_operand" "t")
6511 (match_operand:V16QI 4 "register_operand" "t")
6512 (match_operand:SI 5 "const_int_mve_cde3_operand" "i")
6513 (match_operand:V16BI 6 "vpr_register_operand" "Up")]
6514 CDE_VCX))]
6515 "TARGET_CDE && TARGET_HAVE_MVE"
6516 "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5"
6517 [(set_attr "type" "coproc")
6518 (set_attr "length" "8")]
6519 )
6521 (define_insn "*movmisalign<mode>_mve_store"
6522 [(set (match_operand:MVE_VLD_ST 0 "mve_memory_operand" "=Ux")
6523 (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "s_register_operand" " w")]
6524 UNSPEC_MISALIGNED_ACCESS))]
6525 "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6526 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode)))
6527 && !BYTES_BIG_ENDIAN && unaligned_access"
6528 "vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0"
6529 [(set_attr "type" "mve_store")]
6530 )
6533 (define_insn "*movmisalign<mode>_mve_load"
6534 [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w")
6535 (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "mve_memory_operand" " Ux")]
6536 UNSPEC_MISALIGNED_ACCESS))]
6537 "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6538 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode)))
6539 && !BYTES_BIG_ENDIAN && unaligned_access"
6540 "vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1"
6541 [(set_attr "type" "mve_load")]
6542 )
6544 ;; Expander for VxBI moves
6545 (define_expand "mov<mode>"
6546 [(set (match_operand:MVE_7 0 "nonimmediate_operand")
6547 (match_operand:MVE_7 1 "general_operand"))]
6548 "TARGET_HAVE_MVE"
6549 {
6550 if (!register_operand (operands[0], <MODE>mode))
6551 operands[1] = force_reg (<MODE>mode, operands[1]);
6552 }
6553 )
6555 ;; Expanders for vec_cmp and vcond
6557 (define_expand "vec_cmp<mode><MVE_vpred>"
6558 [(set (match_operand:<MVE_VPRED> 0 "s_register_operand")
6559 (match_operator:<MVE_VPRED> 1 "comparison_operator"
6560 [(match_operand:MVE_VLD_ST 2 "s_register_operand")
6561 (match_operand:MVE_VLD_ST 3 "reg_or_zero_operand")]))]
6562 "TARGET_HAVE_MVE
6563 && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
6564 {
6565 arm_expand_vector_compare (operands[0], GET_CODE (operands[1]),
6566 operands[2], operands[3], false);
6567 DONE;
6568 })
6570 (define_expand "vec_cmpu<mode><MVE_vpred>"
6571 [(set (match_operand:<MVE_VPRED> 0 "s_register_operand")
6572 (match_operator:<MVE_VPRED> 1 "comparison_operator"
6573 [(match_operand:MVE_2 2 "s_register_operand")
6574 (match_operand:MVE_2 3 "reg_or_zero_operand")]))]
6575 "TARGET_HAVE_MVE"
6576 {
6577 arm_expand_vector_compare (operands[0], GET_CODE (operands[1]),
6578 operands[2], operands[3], false);
6579 DONE;
6580 })
6582 (define_expand "vcond_mask_<mode><MVE_vpred>"
6583 [(set (match_operand:MVE_VLD_ST 0 "s_register_operand")
6584 (if_then_else:MVE_VLD_ST
6585 (match_operand:<MVE_VPRED> 3 "s_register_operand")
6586 (match_operand:MVE_VLD_ST 1 "s_register_operand")
6587 (match_operand:MVE_VLD_ST 2 "s_register_operand")))]
6588 "TARGET_HAVE_MVE"
6589 {
6590 switch (GET_MODE_CLASS (<MODE>mode))
6591 {
6592 case MODE_VECTOR_INT:
6593 emit_insn (gen_mve_q (VPSELQ_S, VPSELQ_S, <MODE>mode, operands[0],
6594 operands[1], operands[2], operands[3]));
6595 break;
6596 case MODE_VECTOR_FLOAT:
6597 emit_insn (gen_mve_q_f (VPSELQ_F, <MODE>mode, operands[0],
6598 operands[1], operands[2], operands[3]));
6599 break;
6600 default:
6601 gcc_unreachable ();
6602 }
6603 DONE;
6604 })
6606 ;; Reinterpret operand 1 in operand 0's mode, without changing its contents.
6607 (define_expand "@arm_mve_reinterpret<mode>"
6608 [(set (match_operand:MVE_vecs 0 "register_operand")
6609 (unspec:MVE_vecs
6610 [(match_operand 1 "arm_any_register_operand")]
6611 REINTERPRET))]
6612 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
6613 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
6614 {
6615 machine_mode src_mode = GET_MODE (operands[1]);
6616 if (targetm.can_change_mode_class (<MODE>mode, src_mode, VFP_REGS))
6617 {
6618 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
6619 DONE;
6620 }
6621 }
6622 )