1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "double-int.h"
35 #include "rtl-error.h"
37 #include "insn-config.h"
38 #include "insn-attr.h"
39 #include "hard-reg-set.h"
42 #include "addresses.h"
47 #include "statistics.h"
49 #include "fixed-value.h"
59 #include "dominance.h"
63 #include "cfgcleanup.h"
64 #include "basic-block.h"
67 #include "tree-pass.h"
69 #include "insn-codes.h"
71 #ifndef STACK_PUSH_CODE
72 #ifdef STACK_GROWS_DOWNWARD
73 #define STACK_PUSH_CODE PRE_DEC
75 #define STACK_PUSH_CODE PRE_INC
79 #ifndef STACK_POP_CODE
80 #ifdef STACK_GROWS_DOWNWARD
81 #define STACK_POP_CODE POST_INC
83 #define STACK_POP_CODE POST_DEC
87 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
88 static void validate_replace_src_1 (rtx
*, void *);
89 static rtx
split_insn (rtx_insn
*);
91 struct target_recog default_target_recog
;
93 struct target_recog
*this_target_recog
= &default_target_recog
;
96 /* Nonzero means allow operands to be volatile.
97 This should be 0 if you are generating rtl, such as if you are calling
98 the functions in optabs.c and expmed.c (most of the time).
99 This should be 1 if all valid insns need to be recognized,
100 such as in reginfo.c and final.c and reload.c.
102 init_recog and init_recog_no_volatile are responsible for setting this. */
106 struct recog_data_d recog_data
;
108 /* Contains a vector of operand_alternative structures, such that
109 operand OP of alternative A is at index A * n_operands + OP.
110 Set up by preprocess_constraints. */
111 const operand_alternative
*recog_op_alt
;
113 /* Used to provide recog_op_alt for asms. */
114 static operand_alternative asm_op_alt
[MAX_RECOG_OPERANDS
115 * MAX_RECOG_ALTERNATIVES
];
117 /* On return from `constrain_operands', indicate which alternative
120 int which_alternative
;
122 /* Nonzero after end of reload pass.
123 Set to 1 or 0 by toplev.c.
124 Controls the significance of (SUBREG (MEM)). */
126 int reload_completed
;
128 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
129 int epilogue_completed
;
131 /* Initialize data used by the function `recog'.
132 This must be called once in the compilation of a function
133 before any insn recognition may be done in the function. */
136 init_recog_no_volatile (void)
148 /* Return true if labels in asm operands BODY are LABEL_REFs. */
151 asm_labels_ok (rtx body
)
156 asmop
= extract_asm_operands (body
);
157 if (asmop
== NULL_RTX
)
160 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
161 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
167 /* Check that X is an insn-body for an `asm' with operands
168 and that the operands mentioned in it are legitimate. */
171 check_asm_operands (rtx x
)
175 const char **constraints
;
178 if (!asm_labels_ok (x
))
181 /* Post-reload, be more strict with things. */
182 if (reload_completed
)
184 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
185 rtx_insn
*insn
= make_insn_raw (x
);
187 constrain_operands (1, get_enabled_alternatives (insn
));
188 return which_alternative
>= 0;
191 noperands
= asm_noperands (x
);
197 operands
= XALLOCAVEC (rtx
, noperands
);
198 constraints
= XALLOCAVEC (const char *, noperands
);
200 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
202 for (i
= 0; i
< noperands
; i
++)
204 const char *c
= constraints
[i
];
207 if (! asm_operand_ok (operands
[i
], c
, constraints
))
214 /* Static data for the next two routines. */
216 typedef struct change_t
225 static change_t
*changes
;
226 static int changes_allocated
;
228 static int num_changes
= 0;
230 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
231 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
232 the change is simply made.
234 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
235 will be called with the address and mode as parameters. If OBJECT is
236 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
239 IN_GROUP is nonzero if this is part of a group of changes that must be
240 performed as a group. In that case, the changes will be stored. The
241 function `apply_change_group' will validate and apply the changes.
243 If IN_GROUP is zero, this is a single change. Try to recognize the insn
244 or validate the memory reference with the change applied. If the result
245 is not valid for the machine, suppress the change and return zero.
246 Otherwise, perform the change and return 1. */
249 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
253 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
256 gcc_assert (in_group
!= 0 || num_changes
== 0);
260 /* Save the information describing this change. */
261 if (num_changes
>= changes_allocated
)
263 if (changes_allocated
== 0)
264 /* This value allows for repeated substitutions inside complex
265 indexed addresses, or changes in up to 5 insns. */
266 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
268 changes_allocated
*= 2;
270 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
273 changes
[num_changes
].object
= object
;
274 changes
[num_changes
].loc
= loc
;
275 changes
[num_changes
].old
= old
;
276 changes
[num_changes
].unshare
= unshare
;
278 if (object
&& !MEM_P (object
))
280 /* Set INSN_CODE to force rerecognition of insn. Save old code in
282 changes
[num_changes
].old_code
= INSN_CODE (object
);
283 INSN_CODE (object
) = -1;
288 /* If we are making a group of changes, return 1. Otherwise, validate the
289 change group we made. */
294 return apply_change_group ();
297 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
301 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
303 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
306 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
310 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
312 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
316 /* Keep X canonicalized if some changes have made it non-canonical; only
317 modifies the operands of X, not (for example) its code. Simplifications
318 are not the job of this routine.
320 Return true if anything was changed. */
322 canonicalize_change_group (rtx insn
, rtx x
)
324 if (COMMUTATIVE_P (x
)
325 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
327 /* Oops, the caller has made X no longer canonical.
328 Let's redo the changes in the correct order. */
329 rtx tem
= XEXP (x
, 0);
330 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
331 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
339 /* This subroutine of apply_change_group verifies whether the changes to INSN
340 were valid; i.e. whether INSN can still be recognized.
342 If IN_GROUP is true clobbers which have to be added in order to
343 match the instructions will be added to the current change group.
344 Otherwise the changes will take effect immediately. */
347 insn_invalid_p (rtx_insn
*insn
, bool in_group
)
349 rtx pat
= PATTERN (insn
);
350 int num_clobbers
= 0;
351 /* If we are before reload and the pattern is a SET, see if we can add
353 int icode
= recog (pat
, insn
,
354 (GET_CODE (pat
) == SET
355 && ! reload_completed
356 && ! reload_in_progress
)
357 ? &num_clobbers
: 0);
358 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
361 /* If this is an asm and the operand aren't legal, then fail. Likewise if
362 this is not an asm and the insn wasn't recognized. */
363 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
364 || (!is_asm
&& icode
< 0))
367 /* If we have to add CLOBBERs, fail if we have to add ones that reference
368 hard registers since our callers can't know if they are live or not.
369 Otherwise, add them. */
370 if (num_clobbers
> 0)
374 if (added_clobbers_hard_reg_p (icode
))
377 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
378 XVECEXP (newpat
, 0, 0) = pat
;
379 add_clobbers (newpat
, icode
);
381 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
383 PATTERN (insn
) = pat
= newpat
;
386 /* After reload, verify that all constraints are satisfied. */
387 if (reload_completed
)
391 if (! constrain_operands (1, get_preferred_alternatives (insn
)))
395 INSN_CODE (insn
) = icode
;
399 /* Return number of changes made and not validated yet. */
401 num_changes_pending (void)
406 /* Tentatively apply the changes numbered NUM and up.
407 Return 1 if all changes are valid, zero otherwise. */
410 verify_changes (int num
)
413 rtx last_validated
= NULL_RTX
;
415 /* The changes have been applied and all INSN_CODEs have been reset to force
418 The changes are valid if we aren't given an object, or if we are
419 given a MEM and it still is a valid address, or if this is in insn
420 and it is recognized. In the latter case, if reload has completed,
421 we also require that the operands meet the constraints for
424 for (i
= num
; i
< num_changes
; i
++)
426 rtx object
= changes
[i
].object
;
428 /* If there is no object to test or if it is the same as the one we
429 already tested, ignore it. */
430 if (object
== 0 || object
== last_validated
)
435 if (! memory_address_addr_space_p (GET_MODE (object
),
437 MEM_ADDR_SPACE (object
)))
440 else if (/* changes[i].old might be zero, e.g. when putting a
441 REG_FRAME_RELATED_EXPR into a previously empty list. */
443 && REG_P (changes
[i
].old
)
444 && asm_noperands (PATTERN (object
)) > 0
445 && REG_EXPR (changes
[i
].old
) != NULL_TREE
446 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
447 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
449 /* Don't allow changes of hard register operands to inline
450 assemblies if they have been defined as register asm ("x"). */
453 else if (DEBUG_INSN_P (object
))
455 else if (insn_invalid_p (as_a
<rtx_insn
*> (object
), true))
457 rtx pat
= PATTERN (object
);
459 /* Perhaps we couldn't recognize the insn because there were
460 extra CLOBBERs at the end. If so, try to re-recognize
461 without the last CLOBBER (later iterations will cause each of
462 them to be eliminated, in turn). But don't do this if we
463 have an ASM_OPERAND. */
464 if (GET_CODE (pat
) == PARALLEL
465 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
466 && asm_noperands (PATTERN (object
)) < 0)
470 if (XVECLEN (pat
, 0) == 2)
471 newpat
= XVECEXP (pat
, 0, 0);
477 = gen_rtx_PARALLEL (VOIDmode
,
478 rtvec_alloc (XVECLEN (pat
, 0) - 1));
479 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
480 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
483 /* Add a new change to this group to replace the pattern
484 with this new pattern. Then consider this change
485 as having succeeded. The change we added will
486 cause the entire call to fail if things remain invalid.
488 Note that this can lose if a later change than the one
489 we are processing specified &XVECEXP (PATTERN (object), 0, X)
490 but this shouldn't occur. */
492 validate_change (object
, &PATTERN (object
), newpat
, 1);
495 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
496 || GET_CODE (pat
) == VAR_LOCATION
)
497 /* If this insn is a CLOBBER or USE, it is always valid, but is
503 last_validated
= object
;
506 return (i
== num_changes
);
509 /* A group of changes has previously been issued with validate_change
510 and verified with verify_changes. Call df_insn_rescan for each of
511 the insn changed and clear num_changes. */
514 confirm_change_group (void)
517 rtx last_object
= NULL
;
519 for (i
= 0; i
< num_changes
; i
++)
521 rtx object
= changes
[i
].object
;
523 if (changes
[i
].unshare
)
524 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
526 /* Avoid unnecessary rescanning when multiple changes to same instruction
530 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
531 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
532 last_object
= object
;
536 if (last_object
&& INSN_P (last_object
))
537 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
541 /* Apply a group of changes previously issued with `validate_change'.
542 If all changes are valid, call confirm_change_group and return 1,
543 otherwise, call cancel_changes and return 0. */
546 apply_change_group (void)
548 if (verify_changes (0))
550 confirm_change_group ();
561 /* Return the number of changes so far in the current group. */
564 num_validated_changes (void)
569 /* Retract the changes numbered NUM and up. */
572 cancel_changes (int num
)
576 /* Back out all the changes. Do this in the opposite order in which
578 for (i
= num_changes
- 1; i
>= num
; i
--)
580 *changes
[i
].loc
= changes
[i
].old
;
581 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
582 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
587 /* Reduce conditional compilation elsewhere. */
590 #define CODE_FOR_extv CODE_FOR_nothing
594 #define CODE_FOR_extzv CODE_FOR_nothing
597 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
601 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
602 machine_mode op0_mode
)
605 enum rtx_code code
= GET_CODE (x
);
606 rtx new_rtx
= NULL_RTX
;
608 if (SWAPPABLE_OPERANDS_P (x
)
609 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
611 validate_unshare_change (object
, loc
,
612 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
613 : swap_condition (code
),
614 GET_MODE (x
), XEXP (x
, 1),
620 /* Canonicalize arithmetics with all constant operands. */
621 switch (GET_RTX_CLASS (code
))
624 if (CONSTANT_P (XEXP (x
, 0)))
625 new_rtx
= simplify_unary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
630 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
631 new_rtx
= simplify_binary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
635 case RTX_COMM_COMPARE
:
636 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
637 new_rtx
= simplify_relational_operation (code
, GET_MODE (x
), op0_mode
,
638 XEXP (x
, 0), XEXP (x
, 1));
645 validate_change (object
, loc
, new_rtx
, 1);
652 /* If we have a PLUS whose second operand is now a CONST_INT, use
653 simplify_gen_binary to try to simplify it.
654 ??? We may want later to remove this, once simplification is
655 separated from this function. */
656 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
657 validate_change (object
, loc
,
659 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
662 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
663 validate_change (object
, loc
,
665 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
666 simplify_gen_unary (NEG
,
667 GET_MODE (x
), XEXP (x
, 1),
672 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
674 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
676 /* If any of the above failed, substitute in something that
677 we know won't be recognized. */
679 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
680 validate_change (object
, loc
, new_rtx
, 1);
684 /* All subregs possible to simplify should be simplified. */
685 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
688 /* Subregs of VOIDmode operands are incorrect. */
689 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
690 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
692 validate_change (object
, loc
, new_rtx
, 1);
696 /* If we are replacing a register with memory, try to change the memory
697 to be the mode required for memory in extract operations (this isn't
698 likely to be an insertion operation; if it was, nothing bad will
699 happen, we might just fail in some cases). */
701 if (MEM_P (XEXP (x
, 0))
702 && CONST_INT_P (XEXP (x
, 1))
703 && CONST_INT_P (XEXP (x
, 2))
704 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
705 MEM_ADDR_SPACE (XEXP (x
, 0)))
706 && !MEM_VOLATILE_P (XEXP (x
, 0)))
708 machine_mode wanted_mode
= VOIDmode
;
709 machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
710 int pos
= INTVAL (XEXP (x
, 2));
712 if (GET_CODE (x
) == ZERO_EXTRACT
&& HAVE_extzv
)
714 wanted_mode
= insn_data
[CODE_FOR_extzv
].operand
[1].mode
;
715 if (wanted_mode
== VOIDmode
)
716 wanted_mode
= word_mode
;
718 else if (GET_CODE (x
) == SIGN_EXTRACT
&& HAVE_extv
)
720 wanted_mode
= insn_data
[CODE_FOR_extv
].operand
[1].mode
;
721 if (wanted_mode
== VOIDmode
)
722 wanted_mode
= word_mode
;
725 /* If we have a narrower mode, we can do something. */
726 if (wanted_mode
!= VOIDmode
727 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
729 int offset
= pos
/ BITS_PER_UNIT
;
732 /* If the bytes and bits are counted differently, we
733 must adjust the offset. */
734 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
736 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
739 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
740 == GET_MODE_BITSIZE (wanted_mode
));
741 pos
%= GET_MODE_BITSIZE (wanted_mode
);
743 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
745 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
746 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
757 /* Replace every occurrence of FROM in X with TO. Mark each change with
758 validate_change passing OBJECT. */
761 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
768 machine_mode op0_mode
= VOIDmode
;
769 int prev_changes
= num_changes
;
775 fmt
= GET_RTX_FORMAT (code
);
777 op0_mode
= GET_MODE (XEXP (x
, 0));
779 /* X matches FROM if it is the same rtx or they are both referring to the
780 same register in the same mode. Avoid calling rtx_equal_p unless the
781 operands look similar. */
784 || (REG_P (x
) && REG_P (from
)
785 && GET_MODE (x
) == GET_MODE (from
)
786 && REGNO (x
) == REGNO (from
))
787 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
788 && rtx_equal_p (x
, from
)))
790 validate_unshare_change (object
, loc
, to
, 1);
794 /* Call ourself recursively to perform the replacements.
795 We must not replace inside already replaced expression, otherwise we
796 get infinite recursion for replacements like (reg X)->(subreg (reg X))
797 so we must special case shared ASM_OPERANDS. */
799 if (GET_CODE (x
) == PARALLEL
)
801 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
803 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
804 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
806 /* Verify that operands are really shared. */
807 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
808 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
810 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
811 from
, to
, object
, simplify
);
814 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
819 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
822 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
823 else if (fmt
[i
] == 'E')
824 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
825 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
829 /* If we didn't substitute, there is nothing more to do. */
830 if (num_changes
== prev_changes
)
833 /* ??? The regmove is no more, so is this aberration still necessary? */
834 /* Allow substituted expression to have different mode. This is used by
835 regmove to change mode of pseudo register. */
836 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
837 op0_mode
= GET_MODE (XEXP (x
, 0));
839 /* Do changes needed to keep rtx consistent. Don't do any other
840 simplifications, as it is not our job. */
842 simplify_while_replacing (loc
, to
, object
, op0_mode
);
845 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
846 with TO. After all changes have been made, validate by seeing
847 if INSN is still valid. */
850 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
852 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
853 return apply_change_group ();
856 /* Try replacing every occurrence of FROM in INSN with TO. After all
857 changes have been made, validate by seeing if INSN is still valid. */
860 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
862 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
863 return apply_change_group ();
866 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
867 is a part of INSN. After all changes have been made, validate by seeing if
869 validate_replace_rtx (from, to, insn) is equivalent to
870 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
873 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
875 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
876 return apply_change_group ();
879 /* Same as above, but do not simplify rtx afterwards. */
881 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
884 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
885 return apply_change_group ();
889 /* Try replacing every occurrence of FROM in INSN with TO. This also
890 will replace in REG_EQUAL and REG_EQUIV notes. */
893 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
896 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
897 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
898 if (REG_NOTE_KIND (note
) == REG_EQUAL
899 || REG_NOTE_KIND (note
) == REG_EQUIV
)
900 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
903 /* Function called by note_uses to replace used subexpressions. */
904 struct validate_replace_src_data
906 rtx from
; /* Old RTX */
907 rtx to
; /* New RTX */
908 rtx insn
; /* Insn in which substitution is occurring. */
912 validate_replace_src_1 (rtx
*x
, void *data
)
914 struct validate_replace_src_data
*d
915 = (struct validate_replace_src_data
*) data
;
917 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
920 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
924 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
926 struct validate_replace_src_data d
;
931 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
934 /* Try simplify INSN.
935 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
936 pattern and return true if something was simplified. */
939 validate_simplify_insn (rtx insn
)
945 pat
= PATTERN (insn
);
947 if (GET_CODE (pat
) == SET
)
949 newpat
= simplify_rtx (SET_SRC (pat
));
950 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
951 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
952 newpat
= simplify_rtx (SET_DEST (pat
));
953 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
954 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
956 else if (GET_CODE (pat
) == PARALLEL
)
957 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
959 rtx s
= XVECEXP (pat
, 0, i
);
961 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
963 newpat
= simplify_rtx (SET_SRC (s
));
964 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
965 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
966 newpat
= simplify_rtx (SET_DEST (s
));
967 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
968 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
971 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
975 /* Return 1 if the insn using CC0 set by INSN does not contain
976 any ordered tests applied to the condition codes.
977 EQ and NE tests do not count. */
980 next_insn_tests_no_inequality (rtx insn
)
982 rtx next
= next_cc0_user (insn
);
984 /* If there is no next insn, we have to take the conservative choice. */
988 return (INSN_P (next
)
989 && ! inequality_comparisons_p (PATTERN (next
)));
993 /* Return 1 if OP is a valid general operand for machine mode MODE.
994 This is either a register reference, a memory reference,
995 or a constant. In the case of a memory reference, the address
996 is checked for general validity for the target machine.
998 Register and memory references must have mode MODE in order to be valid,
999 but some constants have no machine mode and are valid for any mode.
1001 If MODE is VOIDmode, OP is checked for validity for whatever mode
1004 The main use of this function is as a predicate in match_operand
1005 expressions in the machine description. */
1008 general_operand (rtx op
, machine_mode mode
)
1010 enum rtx_code code
= GET_CODE (op
);
1012 if (mode
== VOIDmode
)
1013 mode
= GET_MODE (op
);
1015 /* Don't accept CONST_INT or anything similar
1016 if the caller wants something floating. */
1017 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1018 && GET_MODE_CLASS (mode
) != MODE_INT
1019 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1022 if (CONST_INT_P (op
)
1024 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1027 if (CONSTANT_P (op
))
1028 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1029 || mode
== VOIDmode
)
1030 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1031 && targetm
.legitimate_constant_p (mode
== VOIDmode
1035 /* Except for certain constants with VOIDmode, already checked for,
1036 OP's mode must match MODE if MODE specifies a mode. */
1038 if (GET_MODE (op
) != mode
)
1043 rtx sub
= SUBREG_REG (op
);
1045 #ifdef INSN_SCHEDULING
1046 /* On machines that have insn scheduling, we want all memory
1047 reference to be explicit, so outlaw paradoxical SUBREGs.
1048 However, we must allow them after reload so that they can
1049 get cleaned up by cleanup_subreg_operands. */
1050 if (!reload_completed
&& MEM_P (sub
)
1051 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
1054 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1055 may result in incorrect reference. We should simplify all valid
1056 subregs of MEM anyway. But allow this after reload because we
1057 might be called from cleanup_subreg_operands.
1059 ??? This is a kludge. */
1060 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
1064 #ifdef CANNOT_CHANGE_MODE_CLASS
1066 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1067 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1068 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1069 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1070 /* LRA can generate some invalid SUBREGS just for matched
1071 operand reload presentation. LRA needs to treat them as
1073 && ! LRA_SUBREG_P (op
))
1077 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1078 create such rtl, and we must reject it. */
1079 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1080 /* LRA can use subreg to store a floating point value in an
1081 integer mode. Although the floating point and the
1082 integer modes need the same number of hard registers, the
1083 size of floating point mode can be less than the integer
1085 && ! lra_in_progress
1086 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1090 code
= GET_CODE (op
);
1094 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1095 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1099 rtx y
= XEXP (op
, 0);
1101 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1104 /* Use the mem's mode, since it will be reloaded thus. LRA can
1105 generate move insn with invalid addresses which is made valid
1106 and efficiently calculated by LRA through further numerous
1109 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1116 /* Return 1 if OP is a valid memory address for a memory reference
1119 The main use of this function is as a predicate in match_operand
1120 expressions in the machine description. */
1123 address_operand (rtx op
, machine_mode mode
)
1125 return memory_address_p (mode
, op
);
1128 /* Return 1 if OP is a register reference of mode MODE.
1129 If MODE is VOIDmode, accept a register in any mode.
1131 The main use of this function is as a predicate in match_operand
1132 expressions in the machine description. */
1135 register_operand (rtx op
, machine_mode mode
)
1137 if (GET_CODE (op
) == SUBREG
)
1139 rtx sub
= SUBREG_REG (op
);
1141 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1142 because it is guaranteed to be reloaded into one.
1143 Just make sure the MEM is valid in itself.
1144 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1145 but currently it does result from (SUBREG (REG)...) where the
1146 reg went on the stack.) */
1147 if (!REG_P (sub
) && (reload_completed
|| !MEM_P (sub
)))
1150 else if (!REG_P (op
))
1152 return general_operand (op
, mode
);
1155 /* Return 1 for a register in Pmode; ignore the tested mode. */
1158 pmode_register_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1160 return register_operand (op
, Pmode
);
1163 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1164 or a hard register. */
1167 scratch_operand (rtx op
, machine_mode mode
)
1169 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1172 return (GET_CODE (op
) == SCRATCH
1175 || (REGNO (op
) < FIRST_PSEUDO_REGISTER
1176 && REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
))));
1179 /* Return 1 if OP is a valid immediate operand for mode MODE.
1181 The main use of this function is as a predicate in match_operand
1182 expressions in the machine description. */
1185 immediate_operand (rtx op
, machine_mode mode
)
1187 /* Don't accept CONST_INT or anything similar
1188 if the caller wants something floating. */
1189 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1190 && GET_MODE_CLASS (mode
) != MODE_INT
1191 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1194 if (CONST_INT_P (op
)
1196 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1199 return (CONSTANT_P (op
)
1200 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1201 || GET_MODE (op
) == VOIDmode
)
1202 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1203 && targetm
.legitimate_constant_p (mode
== VOIDmode
1208 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1211 const_int_operand (rtx op
, machine_mode mode
)
1213 if (!CONST_INT_P (op
))
1216 if (mode
!= VOIDmode
1217 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1223 #if TARGET_SUPPORTS_WIDE_INT
1224 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1227 const_scalar_int_operand (rtx op
, machine_mode mode
)
1229 if (!CONST_SCALAR_INT_P (op
))
1232 if (CONST_INT_P (op
))
1233 return const_int_operand (op
, mode
);
1235 if (mode
!= VOIDmode
)
1237 int prec
= GET_MODE_PRECISION (mode
);
1238 int bitsize
= GET_MODE_BITSIZE (mode
);
1240 if (CONST_WIDE_INT_NUNITS (op
) * HOST_BITS_PER_WIDE_INT
> bitsize
)
1243 if (prec
== bitsize
)
1247 /* Multiword partial int. */
1249 = CONST_WIDE_INT_ELT (op
, CONST_WIDE_INT_NUNITS (op
) - 1);
1250 return (sext_hwi (x
, prec
& (HOST_BITS_PER_WIDE_INT
- 1)) == x
);
1256 /* Returns 1 if OP is an operand that is a constant integer or constant
1257 floating-point number of MODE. */
1260 const_double_operand (rtx op
, machine_mode mode
)
1262 return (GET_CODE (op
) == CONST_DOUBLE
)
1263 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
);
1266 /* Returns 1 if OP is an operand that is a constant integer or constant
1267 floating-point number of MODE. */
1270 const_double_operand (rtx op
, machine_mode mode
)
1272 /* Don't accept CONST_INT or anything similar
1273 if the caller wants something floating. */
1274 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1275 && GET_MODE_CLASS (mode
) != MODE_INT
1276 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1279 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1280 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1281 || GET_MODE (op
) == VOIDmode
));
1284 /* Return 1 if OP is a general operand that is not an immediate
1285 operand of mode MODE. */
1288 nonimmediate_operand (rtx op
, machine_mode mode
)
1290 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1293 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1296 nonmemory_operand (rtx op
, machine_mode mode
)
1298 if (CONSTANT_P (op
))
1299 return immediate_operand (op
, mode
);
1300 return register_operand (op
, mode
);
1303 /* Return 1 if OP is a valid operand that stands for pushing a
1304 value of mode MODE onto the stack.
1306 The main use of this function is as a predicate in match_operand
1307 expressions in the machine description. */
1310 push_operand (rtx op
, machine_mode mode
)
1312 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1314 #ifdef PUSH_ROUNDING
1315 rounded_size
= PUSH_ROUNDING (rounded_size
);
1321 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1326 if (rounded_size
== GET_MODE_SIZE (mode
))
1328 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1333 if (GET_CODE (op
) != PRE_MODIFY
1334 || GET_CODE (XEXP (op
, 1)) != PLUS
1335 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1336 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1337 #ifdef STACK_GROWS_DOWNWARD
1338 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1340 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1346 return XEXP (op
, 0) == stack_pointer_rtx
;
1349 /* Return 1 if OP is a valid operand that stands for popping a
1350 value of mode MODE off the stack.
1352 The main use of this function is as a predicate in match_operand
1353 expressions in the machine description. */
1356 pop_operand (rtx op
, machine_mode mode
)
1361 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1366 if (GET_CODE (op
) != STACK_POP_CODE
)
1369 return XEXP (op
, 0) == stack_pointer_rtx
;
1372 /* Return 1 if ADDR is a valid memory address
1373 for mode MODE in address space AS. */
1376 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED
,
1377 rtx addr
, addr_space_t as
)
1379 #ifdef GO_IF_LEGITIMATE_ADDRESS
1380 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1381 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1387 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1391 /* Return 1 if OP is a valid memory reference with mode MODE,
1392 including a valid address.
1394 The main use of this function is as a predicate in match_operand
1395 expressions in the machine description. */
1398 memory_operand (rtx op
, machine_mode mode
)
1402 if (! reload_completed
)
1403 /* Note that no SUBREG is a memory operand before end of reload pass,
1404 because (SUBREG (MEM...)) forces reloading into a register. */
1405 return MEM_P (op
) && general_operand (op
, mode
);
1407 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1411 if (GET_CODE (inner
) == SUBREG
)
1412 inner
= SUBREG_REG (inner
);
1414 return (MEM_P (inner
) && general_operand (op
, mode
));
1417 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1418 that is, a memory reference whose address is a general_operand. */
1421 indirect_operand (rtx op
, machine_mode mode
)
1423 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1424 if (! reload_completed
1425 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1427 int offset
= SUBREG_BYTE (op
);
1428 rtx inner
= SUBREG_REG (op
);
1430 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1433 /* The only way that we can have a general_operand as the resulting
1434 address is if OFFSET is zero and the address already is an operand
1435 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1438 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1439 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1440 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1441 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1442 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1446 && memory_operand (op
, mode
)
1447 && general_operand (XEXP (op
, 0), Pmode
));
1450 /* Return 1 if this is an ordered comparison operator (not including
1451 ORDERED and UNORDERED). */
1454 ordered_comparison_operator (rtx op
, machine_mode mode
)
1456 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1458 switch (GET_CODE (op
))
1476 /* Return 1 if this is a comparison operator. This allows the use of
1477 MATCH_OPERATOR to recognize all the branch insns. */
1480 comparison_operator (rtx op
, machine_mode mode
)
1482 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1483 && COMPARISON_P (op
));
1486 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1489 extract_asm_operands (rtx body
)
1492 switch (GET_CODE (body
))
1498 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1499 tmp
= SET_SRC (body
);
1500 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1505 tmp
= XVECEXP (body
, 0, 0);
1506 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1508 if (GET_CODE (tmp
) == SET
)
1510 tmp
= SET_SRC (tmp
);
1511 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1522 /* If BODY is an insn body that uses ASM_OPERANDS,
1523 return the number of operands (both input and output) in the insn.
1524 Otherwise return -1. */
1527 asm_noperands (const_rtx body
)
1529 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1535 if (GET_CODE (body
) == SET
)
1537 else if (GET_CODE (body
) == PARALLEL
)
1540 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1542 /* Multiple output operands, or 1 output plus some clobbers:
1544 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1545 /* Count backwards through CLOBBERs to determine number of SETs. */
1546 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1548 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1550 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1554 /* N_SETS is now number of output operands. */
1557 /* Verify that all the SETs we have
1558 came from a single original asm_operands insn
1559 (so that invalid combinations are blocked). */
1560 for (i
= 0; i
< n_sets
; i
++)
1562 rtx elt
= XVECEXP (body
, 0, i
);
1563 if (GET_CODE (elt
) != SET
)
1565 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1567 /* If these ASM_OPERANDS rtx's came from different original insns
1568 then they aren't allowed together. */
1569 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1570 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1576 /* 0 outputs, but some clobbers:
1577 body is [(asm_operands ...) (clobber (reg ...))...]. */
1578 /* Make sure all the other parallel things really are clobbers. */
1579 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1580 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1585 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1586 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1589 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1590 copy its operands (both input and output) into the vector OPERANDS,
1591 the locations of the operands within the insn into the vector OPERAND_LOCS,
1592 and the constraints for the operands into CONSTRAINTS.
1593 Write the modes of the operands into MODES.
1594 Return the assembler-template.
1596 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1597 we don't store that info. */
1600 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1601 const char **constraints
, machine_mode
*modes
,
1604 int nbase
= 0, n
, i
;
1607 switch (GET_CODE (body
))
1610 /* Zero output asm: BODY is (asm_operands ...). */
1615 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1616 asmop
= SET_SRC (body
);
1618 /* The output is in the SET.
1619 Its constraint is in the ASM_OPERANDS itself. */
1621 operands
[0] = SET_DEST (body
);
1623 operand_locs
[0] = &SET_DEST (body
);
1625 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1627 modes
[0] = GET_MODE (SET_DEST (body
));
1633 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1635 asmop
= XVECEXP (body
, 0, 0);
1636 if (GET_CODE (asmop
) == SET
)
1638 asmop
= SET_SRC (asmop
);
1640 /* At least one output, plus some CLOBBERs. The outputs are in
1641 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1642 for (i
= 0; i
< nparallel
; i
++)
1644 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1645 break; /* Past last SET */
1647 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1649 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1651 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1653 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1664 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1665 for (i
= 0; i
< n
; i
++)
1668 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1670 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1672 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1674 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1678 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1679 for (i
= 0; i
< n
; i
++)
1682 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1684 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1686 constraints
[nbase
+ i
] = "";
1688 modes
[nbase
+ i
] = Pmode
;
1692 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1694 return ASM_OPERANDS_TEMPLATE (asmop
);
1697 /* Parse inline assembly string STRING and determine which operands are
1698 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1699 to true if operand I is referenced.
1701 This is intended to distinguish barrier-like asms such as:
1703 asm ("" : "=m" (...));
1705 from real references such as:
1707 asm ("sw\t$0, %0" : "=m" (...)); */
1710 get_referenced_operands (const char *string
, bool *used
,
1711 unsigned int noperands
)
1713 memset (used
, 0, sizeof (bool) * noperands
);
1714 const char *p
= string
;
1720 /* A letter followed by a digit indicates an operand number. */
1721 if (ISALPHA (p
[0]) && ISDIGIT (p
[1]))
1726 unsigned long opnum
= strtoul (p
, &endptr
, 10);
1727 if (endptr
!= p
&& opnum
< noperands
)
1741 /* Check if an asm_operand matches its constraints.
1742 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1745 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1749 bool incdec_ok
= false;
1752 /* Use constrain_operands after reload. */
1753 gcc_assert (!reload_completed
);
1755 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1756 many alternatives as required to match the other operands. */
1757 if (*constraint
== '\0')
1762 enum constraint_num cn
;
1763 char c
= *constraint
;
1771 case '0': case '1': case '2': case '3': case '4':
1772 case '5': case '6': case '7': case '8': case '9':
1773 /* If caller provided constraints pointer, look up
1774 the matching constraint. Otherwise, our caller should have
1775 given us the proper matching constraint, but we can't
1776 actually fail the check if they didn't. Indicate that
1777 results are inconclusive. */
1781 unsigned long match
;
1783 match
= strtoul (constraint
, &end
, 10);
1785 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1786 constraint
= (const char *) end
;
1792 while (ISDIGIT (*constraint
));
1798 /* The rest of the compiler assumes that reloading the address
1799 of a MEM into a register will make it fit an 'o' constraint.
1800 That is, if it sees a MEM operand for an 'o' constraint,
1801 it assumes that (mem (base-reg)) will fit.
1803 That assumption fails on targets that don't have offsettable
1804 addresses at all. We therefore need to treat 'o' asm
1805 constraints as a special case and only accept operands that
1806 are already offsettable, thus proving that at least one
1807 offsettable address exists. */
1808 case 'o': /* offsettable */
1809 if (offsettable_nonstrict_memref_p (op
))
1814 if (general_operand (op
, VOIDmode
))
1821 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1822 to exist, excepting those that expand_call created. Further,
1823 on some machines which do not have generalized auto inc/dec,
1824 an inc/dec is not a memory_operand.
1826 Match any memory and hope things are resolved after reload. */
1830 cn
= lookup_constraint (constraint
);
1831 switch (get_constraint_type (cn
))
1835 && reg_class_for_constraint (cn
) != NO_REGS
1836 && GET_MODE (op
) != BLKmode
1837 && register_operand (op
, VOIDmode
))
1844 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1849 /* Every memory operand can be reloaded to fit. */
1850 result
= result
|| memory_operand (op
, VOIDmode
);
1854 /* Every address operand can be reloaded to fit. */
1855 result
= result
|| address_operand (op
, VOIDmode
);
1859 result
= result
|| constraint_satisfied_p (op
, cn
);
1864 len
= CONSTRAINT_LEN (c
, constraint
);
1867 while (--len
&& *constraint
);
1873 /* For operands without < or > constraints reject side-effects. */
1874 if (!incdec_ok
&& result
&& MEM_P (op
))
1875 switch (GET_CODE (XEXP (op
, 0)))
1892 /* Given an rtx *P, if it is a sum containing an integer constant term,
1893 return the location (type rtx *) of the pointer to that constant term.
1894 Otherwise, return a null pointer. */
1897 find_constant_term_loc (rtx
*p
)
1900 enum rtx_code code
= GET_CODE (*p
);
1902 /* If *P IS such a constant term, P is its location. */
1904 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1908 /* Otherwise, if not a sum, it has no constant term. */
1910 if (GET_CODE (*p
) != PLUS
)
1913 /* If one of the summands is constant, return its location. */
1915 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1916 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1919 /* Otherwise, check each summand for containing a constant term. */
1921 if (XEXP (*p
, 0) != 0)
1923 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1928 if (XEXP (*p
, 1) != 0)
1930 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1938 /* Return 1 if OP is a memory reference
1939 whose address contains no side effects
1940 and remains valid after the addition
1941 of a positive integer less than the
1942 size of the object being referenced.
1944 We assume that the original address is valid and do not check it.
1946 This uses strict_memory_address_p as a subroutine, so
1947 don't use it before reload. */
1950 offsettable_memref_p (rtx op
)
1952 return ((MEM_P (op
))
1953 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1954 MEM_ADDR_SPACE (op
)));
1957 /* Similar, but don't require a strictly valid mem ref:
1958 consider pseudo-regs valid as index or base regs. */
1961 offsettable_nonstrict_memref_p (rtx op
)
1963 return ((MEM_P (op
))
1964 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1965 MEM_ADDR_SPACE (op
)));
1968 /* Return 1 if Y is a memory address which contains no side effects
1969 and would remain valid for address space AS after the addition of
1970 a positive integer less than the size of that mode.
1972 We assume that the original address is valid and do not check it.
1973 We do check that it is valid for narrower modes.
1975 If STRICTP is nonzero, we require a strictly valid address,
1976 for the sake of use in reload.c. */
1979 offsettable_address_addr_space_p (int strictp
, machine_mode mode
, rtx y
,
1982 enum rtx_code ycode
= GET_CODE (y
);
1986 int (*addressp
) (machine_mode
, rtx
, addr_space_t
) =
1987 (strictp
? strict_memory_address_addr_space_p
1988 : memory_address_addr_space_p
);
1989 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1991 if (CONSTANT_ADDRESS_P (y
))
1994 /* Adjusting an offsettable address involves changing to a narrower mode.
1995 Make sure that's OK. */
1997 if (mode_dependent_address_p (y
, as
))
2000 machine_mode address_mode
= GET_MODE (y
);
2001 if (address_mode
== VOIDmode
)
2002 address_mode
= targetm
.addr_space
.address_mode (as
);
2003 #ifdef POINTERS_EXTEND_UNSIGNED
2004 machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
2007 /* ??? How much offset does an offsettable BLKmode reference need?
2008 Clearly that depends on the situation in which it's being used.
2009 However, the current situation in which we test 0xffffffff is
2010 less than ideal. Caveat user. */
2012 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
2014 /* If the expression contains a constant term,
2015 see if it remains valid when max possible offset is added. */
2017 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
2022 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
2023 /* Use QImode because an odd displacement may be automatically invalid
2024 for any wider mode. But it should be valid for a single byte. */
2025 good
= (*addressp
) (QImode
, y
, as
);
2027 /* In any case, restore old contents of memory. */
2032 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
2035 /* The offset added here is chosen as the maximum offset that
2036 any instruction could need to add when operating on something
2037 of the specified mode. We assume that if Y and Y+c are
2038 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2039 go inside a LO_SUM here, so we do so as well. */
2040 if (GET_CODE (y
) == LO_SUM
2042 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
2043 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
2044 plus_constant (address_mode
, XEXP (y
, 1),
2046 #ifdef POINTERS_EXTEND_UNSIGNED
2047 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2048 else if (POINTERS_EXTEND_UNSIGNED
> 0
2049 && GET_CODE (y
) == ZERO_EXTEND
2050 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2051 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2052 plus_constant (pointer_mode
, XEXP (y
, 0),
2056 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2058 /* Use QImode because an odd displacement may be automatically invalid
2059 for any wider mode. But it should be valid for a single byte. */
2060 return (*addressp
) (QImode
, z
, as
);
2063 /* Return 1 if ADDR is an address-expression whose effect depends
2064 on the mode of the memory reference it is used in.
2066 ADDRSPACE is the address space associated with the address.
2068 Autoincrement addressing is a typical example of mode-dependence
2069 because the amount of the increment depends on the mode. */
2072 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2074 /* Auto-increment addressing with anything other than post_modify
2075 or pre_modify always introduces a mode dependency. Catch such
2076 cases now instead of deferring to the target. */
2077 if (GET_CODE (addr
) == PRE_INC
2078 || GET_CODE (addr
) == POST_INC
2079 || GET_CODE (addr
) == PRE_DEC
2080 || GET_CODE (addr
) == POST_DEC
)
2083 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2086 /* Return true if boolean attribute ATTR is supported. */
2089 have_bool_attr (bool_attr attr
)
2094 return HAVE_ATTR_enabled
;
2095 case BA_PREFERRED_FOR_SIZE
:
2096 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_size
;
2097 case BA_PREFERRED_FOR_SPEED
:
2098 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_speed
;
2103 /* Return the value of ATTR for instruction INSN. */
2106 get_bool_attr (rtx_insn
*insn
, bool_attr attr
)
2111 return get_attr_enabled (insn
);
2112 case BA_PREFERRED_FOR_SIZE
:
2113 return get_attr_enabled (insn
) && get_attr_preferred_for_size (insn
);
2114 case BA_PREFERRED_FOR_SPEED
:
2115 return get_attr_enabled (insn
) && get_attr_preferred_for_speed (insn
);
2120 /* Like get_bool_attr_mask, but don't use the cache. */
2122 static alternative_mask
2123 get_bool_attr_mask_uncached (rtx_insn
*insn
, bool_attr attr
)
2125 /* Temporarily install enough information for get_attr_<foo> to assume
2126 that the insn operands are already cached. As above, the attribute
2127 mustn't depend on the values of operands, so we don't provide their
2128 real values here. */
2129 rtx old_insn
= recog_data
.insn
;
2130 int old_alternative
= which_alternative
;
2132 recog_data
.insn
= insn
;
2133 alternative_mask mask
= ALL_ALTERNATIVES
;
2134 int n_alternatives
= insn_data
[INSN_CODE (insn
)].n_alternatives
;
2135 for (int i
= 0; i
< n_alternatives
; i
++)
2137 which_alternative
= i
;
2138 if (!get_bool_attr (insn
, attr
))
2139 mask
&= ~ALTERNATIVE_BIT (i
);
2142 recog_data
.insn
= old_insn
;
2143 which_alternative
= old_alternative
;
2147 /* Return the mask of operand alternatives that are allowed for INSN
2148 by boolean attribute ATTR. This mask depends only on INSN and on
2149 the current target; it does not depend on things like the values of
2152 static alternative_mask
2153 get_bool_attr_mask (rtx_insn
*insn
, bool_attr attr
)
2155 /* Quick exit for asms and for targets that don't use these attributes. */
2156 int code
= INSN_CODE (insn
);
2157 if (code
< 0 || !have_bool_attr (attr
))
2158 return ALL_ALTERNATIVES
;
2160 /* Calling get_attr_<foo> can be expensive, so cache the mask
2162 if (!this_target_recog
->x_bool_attr_masks
[code
][attr
])
2163 this_target_recog
->x_bool_attr_masks
[code
][attr
]
2164 = get_bool_attr_mask_uncached (insn
, attr
);
2165 return this_target_recog
->x_bool_attr_masks
[code
][attr
];
2168 /* Return the set of alternatives of INSN that are allowed by the current
2172 get_enabled_alternatives (rtx_insn
*insn
)
2174 return get_bool_attr_mask (insn
, BA_ENABLED
);
2177 /* Return the set of alternatives of INSN that are allowed by the current
2178 target and are preferred for the current size/speed optimization
2182 get_preferred_alternatives (rtx_insn
*insn
)
2184 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
)))
2185 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2187 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2190 /* Return the set of alternatives of INSN that are allowed by the current
2191 target and are preferred for the size/speed optimization choice
2192 associated with BB. Passing a separate BB is useful if INSN has not
2193 been emitted yet or if we are considering moving it to a different
2197 get_preferred_alternatives (rtx_insn
*insn
, basic_block bb
)
2199 if (optimize_bb_for_speed_p (bb
))
2200 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2202 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2205 /* Assert that the cached boolean attributes for INSN are still accurate.
2206 The backend is required to define these attributes in a way that only
2207 depends on the current target (rather than operands, compiler phase,
2211 check_bool_attrs (rtx_insn
*insn
)
2213 int code
= INSN_CODE (insn
);
2215 for (int i
= 0; i
<= BA_LAST
; ++i
)
2217 enum bool_attr attr
= (enum bool_attr
) i
;
2218 if (this_target_recog
->x_bool_attr_masks
[code
][attr
])
2219 gcc_assert (this_target_recog
->x_bool_attr_masks
[code
][attr
]
2220 == get_bool_attr_mask_uncached (insn
, attr
));
2225 /* Like extract_insn, but save insn extracted and don't extract again, when
2226 called again for the same insn expecting that recog_data still contain the
2227 valid information. This is used primary by gen_attr infrastructure that
2228 often does extract insn again and again. */
2230 extract_insn_cached (rtx_insn
*insn
)
2232 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2234 extract_insn (insn
);
2235 recog_data
.insn
= insn
;
2238 /* Do uncached extract_insn, constrain_operands and complain about failures.
2239 This should be used when extracting a pre-existing constrained instruction
2240 if the caller wants to know which alternative was chosen. */
2242 extract_constrain_insn (rtx_insn
*insn
)
2244 extract_insn (insn
);
2245 if (!constrain_operands (reload_completed
, get_enabled_alternatives (insn
)))
2246 fatal_insn_not_found (insn
);
2249 /* Do cached extract_insn, constrain_operands and complain about failures.
2250 Used by insn_attrtab. */
2252 extract_constrain_insn_cached (rtx_insn
*insn
)
2254 extract_insn_cached (insn
);
2255 if (which_alternative
== -1
2256 && !constrain_operands (reload_completed
,
2257 get_enabled_alternatives (insn
)))
2258 fatal_insn_not_found (insn
);
2261 /* Do cached constrain_operands on INSN and complain about failures. */
2263 constrain_operands_cached (rtx_insn
*insn
, int strict
)
2265 if (which_alternative
== -1)
2266 return constrain_operands (strict
, get_enabled_alternatives (insn
));
2271 /* Analyze INSN and fill in recog_data. */
2274 extract_insn (rtx_insn
*insn
)
2279 rtx body
= PATTERN (insn
);
2281 recog_data
.n_operands
= 0;
2282 recog_data
.n_alternatives
= 0;
2283 recog_data
.n_dups
= 0;
2284 recog_data
.is_asm
= false;
2286 switch (GET_CODE (body
))
2297 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2302 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2303 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2304 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2310 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2313 /* This insn is an `asm' with operands. */
2315 /* expand_asm_operands makes sure there aren't too many operands. */
2316 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2318 /* Now get the operand values and constraints out of the insn. */
2319 decode_asm_operands (body
, recog_data
.operand
,
2320 recog_data
.operand_loc
,
2321 recog_data
.constraints
,
2322 recog_data
.operand_mode
, NULL
);
2323 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2326 const char *p
= recog_data
.constraints
[0];
2327 recog_data
.n_alternatives
= 1;
2329 recog_data
.n_alternatives
+= (*p
++ == ',');
2331 recog_data
.is_asm
= true;
2334 fatal_insn_not_found (insn
);
2338 /* Ordinary insn: recognize it, get the operands via insn_extract
2339 and get the constraints. */
2341 icode
= recog_memoized (insn
);
2343 fatal_insn_not_found (insn
);
2345 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2346 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2347 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2349 insn_extract (insn
);
2351 for (i
= 0; i
< noperands
; i
++)
2353 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2354 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2355 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2356 /* VOIDmode match_operands gets mode from their real operand. */
2357 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2358 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2361 for (i
= 0; i
< noperands
; i
++)
2362 recog_data
.operand_type
[i
]
2363 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2364 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2367 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2369 recog_data
.insn
= NULL
;
2370 which_alternative
= -1;
2373 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2374 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2375 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2376 has N_OPERANDS entries. */
2379 preprocess_constraints (int n_operands
, int n_alternatives
,
2380 const char **constraints
,
2381 operand_alternative
*op_alt_base
)
2383 for (int i
= 0; i
< n_operands
; i
++)
2386 struct operand_alternative
*op_alt
;
2387 const char *p
= constraints
[i
];
2389 op_alt
= op_alt_base
;
2391 for (j
= 0; j
< n_alternatives
; j
++, op_alt
+= n_operands
)
2393 op_alt
[i
].cl
= NO_REGS
;
2394 op_alt
[i
].constraint
= p
;
2395 op_alt
[i
].matches
= -1;
2396 op_alt
[i
].matched
= -1;
2398 if (*p
== '\0' || *p
== ',')
2400 op_alt
[i
].anything_ok
= 1;
2410 while (c
!= ',' && c
!= '\0');
2411 if (c
== ',' || c
== '\0')
2420 op_alt
[i
].reject
+= 6;
2423 op_alt
[i
].reject
+= 600;
2426 op_alt
[i
].earlyclobber
= 1;
2429 case '0': case '1': case '2': case '3': case '4':
2430 case '5': case '6': case '7': case '8': case '9':
2433 op_alt
[i
].matches
= strtoul (p
, &end
, 10);
2434 op_alt
[op_alt
[i
].matches
].matched
= i
;
2440 op_alt
[i
].anything_ok
= 1;
2445 reg_class_subunion
[(int) op_alt
[i
].cl
][(int) GENERAL_REGS
];
2449 enum constraint_num cn
= lookup_constraint (p
);
2451 switch (get_constraint_type (cn
))
2454 cl
= reg_class_for_constraint (cn
);
2456 op_alt
[i
].cl
= reg_class_subunion
[op_alt
[i
].cl
][cl
];
2463 op_alt
[i
].memory_ok
= 1;
2467 op_alt
[i
].is_address
= 1;
2469 = (reg_class_subunion
2470 [(int) op_alt
[i
].cl
]
2471 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2472 ADDRESS
, SCRATCH
)]);
2480 p
+= CONSTRAINT_LEN (c
, p
);
2486 /* Return an array of operand_alternative instructions for
2487 instruction ICODE. */
2489 const operand_alternative
*
2490 preprocess_insn_constraints (int icode
)
2492 gcc_checking_assert (IN_RANGE (icode
, 0, LAST_INSN_CODE
));
2493 if (this_target_recog
->x_op_alt
[icode
])
2494 return this_target_recog
->x_op_alt
[icode
];
2496 int n_operands
= insn_data
[icode
].n_operands
;
2497 if (n_operands
== 0)
2499 /* Always provide at least one alternative so that which_op_alt ()
2500 works correctly. If the instruction has 0 alternatives (i.e. all
2501 constraint strings are empty) then each operand in this alternative
2502 will have anything_ok set. */
2503 int n_alternatives
= MAX (insn_data
[icode
].n_alternatives
, 1);
2504 int n_entries
= n_operands
* n_alternatives
;
2506 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
, n_entries
);
2507 const char **constraints
= XALLOCAVEC (const char *, n_operands
);
2509 for (int i
= 0; i
< n_operands
; ++i
)
2510 constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2511 preprocess_constraints (n_operands
, n_alternatives
, constraints
, op_alt
);
2513 this_target_recog
->x_op_alt
[icode
] = op_alt
;
2517 /* After calling extract_insn, you can use this function to extract some
2518 information from the constraint strings into a more usable form.
2519 The collected data is stored in recog_op_alt. */
2522 preprocess_constraints (rtx insn
)
2524 int icode
= INSN_CODE (insn
);
2526 recog_op_alt
= preprocess_insn_constraints (icode
);
2529 int n_operands
= recog_data
.n_operands
;
2530 int n_alternatives
= recog_data
.n_alternatives
;
2531 int n_entries
= n_operands
* n_alternatives
;
2532 memset (asm_op_alt
, 0, n_entries
* sizeof (operand_alternative
));
2533 preprocess_constraints (n_operands
, n_alternatives
,
2534 recog_data
.constraints
, asm_op_alt
);
2535 recog_op_alt
= asm_op_alt
;
2539 /* Check the operands of an insn against the insn's operand constraints
2540 and return 1 if they match any of the alternatives in ALTERNATIVES.
2542 The information about the insn's operands, constraints, operand modes
2543 etc. is obtained from the global variables set up by extract_insn.
2545 WHICH_ALTERNATIVE is set to a number which indicates which
2546 alternative of constraints was matched: 0 for the first alternative,
2547 1 for the next, etc.
2549 In addition, when two operands are required to match
2550 and it happens that the output operand is (reg) while the
2551 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2552 make the output operand look like the input.
2553 This is because the output operand is the one the template will print.
2555 This is used in final, just before printing the assembler code and by
2556 the routines that determine an insn's attribute.
2558 If STRICT is a positive nonzero value, it means that we have been
2559 called after reload has been completed. In that case, we must
2560 do all checks strictly. If it is zero, it means that we have been called
2561 before reload has completed. In that case, we first try to see if we can
2562 find an alternative that matches strictly. If not, we try again, this
2563 time assuming that reload will fix up the insn. This provides a "best
2564 guess" for the alternative and is used to compute attributes of insns prior
2565 to reload. A negative value of STRICT is used for this internal call. */
2573 constrain_operands (int strict
, alternative_mask alternatives
)
2575 const char *constraints
[MAX_RECOG_OPERANDS
];
2576 int matching_operands
[MAX_RECOG_OPERANDS
];
2577 int earlyclobber
[MAX_RECOG_OPERANDS
];
2580 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2581 int funny_match_index
;
2583 which_alternative
= 0;
2584 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2587 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2589 constraints
[c
] = recog_data
.constraints
[c
];
2590 matching_operands
[c
] = -1;
2595 int seen_earlyclobber_at
= -1;
2598 funny_match_index
= 0;
2600 if (!TEST_BIT (alternatives
, which_alternative
))
2604 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2605 constraints
[i
] = skip_alternative (constraints
[i
]);
2607 which_alternative
++;
2611 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2613 rtx op
= recog_data
.operand
[opno
];
2614 machine_mode mode
= GET_MODE (op
);
2615 const char *p
= constraints
[opno
];
2621 earlyclobber
[opno
] = 0;
2623 /* A unary operator may be accepted by the predicate, but it
2624 is irrelevant for matching constraints. */
2628 if (GET_CODE (op
) == SUBREG
)
2630 if (REG_P (SUBREG_REG (op
))
2631 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2632 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2633 GET_MODE (SUBREG_REG (op
)),
2636 op
= SUBREG_REG (op
);
2639 /* An empty constraint or empty alternative
2640 allows anything which matched the pattern. */
2641 if (*p
== 0 || *p
== ',')
2645 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2655 /* Ignore rest of this alternative as far as
2656 constraint checking is concerned. */
2659 while (*p
&& *p
!= ',');
2664 earlyclobber
[opno
] = 1;
2665 if (seen_earlyclobber_at
< 0)
2666 seen_earlyclobber_at
= opno
;
2669 case '0': case '1': case '2': case '3': case '4':
2670 case '5': case '6': case '7': case '8': case '9':
2672 /* This operand must be the same as a previous one.
2673 This kind of constraint is used for instructions such
2674 as add when they take only two operands.
2676 Note that the lower-numbered operand is passed first.
2678 If we are not testing strictly, assume that this
2679 constraint will be satisfied. */
2684 match
= strtoul (p
, &end
, 10);
2691 rtx op1
= recog_data
.operand
[match
];
2692 rtx op2
= recog_data
.operand
[opno
];
2694 /* A unary operator may be accepted by the predicate,
2695 but it is irrelevant for matching constraints. */
2697 op1
= XEXP (op1
, 0);
2699 op2
= XEXP (op2
, 0);
2701 val
= operands_match_p (op1
, op2
);
2704 matching_operands
[opno
] = match
;
2705 matching_operands
[match
] = opno
;
2710 /* If output is *x and input is *--x, arrange later
2711 to change the output to *--x as well, since the
2712 output op is the one that will be printed. */
2713 if (val
== 2 && strict
> 0)
2715 funny_match
[funny_match_index
].this_op
= opno
;
2716 funny_match
[funny_match_index
++].other
= match
;
2723 /* p is used for address_operands. When we are called by
2724 gen_reload, no one will have checked that the address is
2725 strictly valid, i.e., that all pseudos requiring hard regs
2726 have gotten them. */
2728 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2733 /* No need to check general_operand again;
2734 it was done in insn-recog.c. Well, except that reload
2735 doesn't check the validity of its replacements, but
2736 that should only matter when there's a bug. */
2738 /* Anything goes unless it is a REG and really has a hard reg
2739 but the hard reg is not in the class GENERAL_REGS. */
2743 || GENERAL_REGS
== ALL_REGS
2744 || (reload_in_progress
2745 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2746 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2749 else if (strict
< 0 || general_operand (op
, mode
))
2755 enum constraint_num cn
= lookup_constraint (p
);
2756 enum reg_class cl
= reg_class_for_constraint (cn
);
2762 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2763 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2765 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2769 else if (constraint_satisfied_p (op
, cn
))
2772 else if (insn_extra_memory_constraint (cn
)
2773 /* Every memory operand can be reloaded to fit. */
2774 && ((strict
< 0 && MEM_P (op
))
2775 /* Before reload, accept what reload can turn
2777 || (strict
< 0 && CONSTANT_P (op
))
2778 /* During reload, accept a pseudo */
2779 || (reload_in_progress
&& REG_P (op
)
2780 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2782 else if (insn_extra_address_constraint (cn
)
2783 /* Every address operand can be reloaded to fit. */
2786 /* Cater to architectures like IA-64 that define extra memory
2787 constraints without using define_memory_constraint. */
2788 else if (reload_in_progress
2790 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2791 && reg_renumber
[REGNO (op
)] < 0
2792 && reg_equiv_mem (REGNO (op
)) != 0
2793 && constraint_satisfied_p
2794 (reg_equiv_mem (REGNO (op
)), cn
))
2799 while (p
+= len
, c
);
2801 constraints
[opno
] = p
;
2802 /* If this operand did not win somehow,
2803 this alternative loses. */
2807 /* This alternative won; the operands are ok.
2808 Change whichever operands this alternative says to change. */
2813 /* See if any earlyclobber operand conflicts with some other
2816 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2817 for (eopno
= seen_earlyclobber_at
;
2818 eopno
< recog_data
.n_operands
;
2820 /* Ignore earlyclobber operands now in memory,
2821 because we would often report failure when we have
2822 two memory operands, one of which was formerly a REG. */
2823 if (earlyclobber
[eopno
]
2824 && REG_P (recog_data
.operand
[eopno
]))
2825 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2826 if ((MEM_P (recog_data
.operand
[opno
])
2827 || recog_data
.operand_type
[opno
] != OP_OUT
)
2829 /* Ignore things like match_operator operands. */
2830 && *recog_data
.constraints
[opno
] != 0
2831 && ! (matching_operands
[opno
] == eopno
2832 && operands_match_p (recog_data
.operand
[opno
],
2833 recog_data
.operand
[eopno
]))
2834 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2835 recog_data
.operand
[eopno
]))
2840 while (--funny_match_index
>= 0)
2842 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2843 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2847 /* For operands without < or > constraints reject side-effects. */
2848 if (recog_data
.is_asm
)
2850 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2851 if (MEM_P (recog_data
.operand
[opno
]))
2852 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2860 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2861 && strchr (recog_data
.constraints
[opno
], '>')
2874 which_alternative
++;
2876 while (which_alternative
< recog_data
.n_alternatives
);
2878 which_alternative
= -1;
2879 /* If we are about to reject this, but we are not to test strictly,
2880 try a very loose test. Only return failure if it fails also. */
2882 return constrain_operands (-1, alternatives
);
2887 /* Return true iff OPERAND (assumed to be a REG rtx)
2888 is a hard reg in class CLASS when its regno is offset by OFFSET
2889 and changed to mode MODE.
2890 If REG occupies multiple hard regs, all of them must be in CLASS. */
2893 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2896 unsigned int regno
= REGNO (operand
);
2901 /* Regno must not be a pseudo register. Offset may be negative. */
2902 return (HARD_REGISTER_NUM_P (regno
)
2903 && HARD_REGISTER_NUM_P (regno
+ offset
)
2904 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2908 /* Split single instruction. Helper function for split_all_insns and
2909 split_all_insns_noflow. Return last insn in the sequence if successful,
2910 or NULL if unsuccessful. */
2913 split_insn (rtx_insn
*insn
)
2915 /* Split insns here to get max fine-grain parallelism. */
2916 rtx_insn
*first
= PREV_INSN (insn
);
2917 rtx_insn
*last
= try_split (PATTERN (insn
), insn
, 1);
2918 rtx insn_set
, last_set
, note
;
2923 /* If the original instruction was a single set that was known to be
2924 equivalent to a constant, see if we can say the same about the last
2925 instruction in the split sequence. The two instructions must set
2926 the same destination. */
2927 insn_set
= single_set (insn
);
2930 last_set
= single_set (last
);
2931 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2933 note
= find_reg_equal_equiv_note (insn
);
2934 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2935 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2936 else if (CONSTANT_P (SET_SRC (insn_set
)))
2937 set_unique_reg_note (last
, REG_EQUAL
,
2938 copy_rtx (SET_SRC (insn_set
)));
2942 /* try_split returns the NOTE that INSN became. */
2943 SET_INSN_DELETED (insn
);
2945 /* ??? Coddle to md files that generate subregs in post-reload
2946 splitters instead of computing the proper hard register. */
2947 if (reload_completed
&& first
!= last
)
2949 first
= NEXT_INSN (first
);
2953 cleanup_subreg_operands (first
);
2956 first
= NEXT_INSN (first
);
2963 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2966 split_all_insns (void)
2972 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2973 bitmap_clear (blocks
);
2976 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
2978 rtx_insn
*insn
, *next
;
2979 bool finish
= false;
2981 rtl_profile_for_bb (bb
);
2982 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2984 /* Can't use `next_real_insn' because that might go across
2985 CODE_LABELS and short-out basic blocks. */
2986 next
= NEXT_INSN (insn
);
2987 finish
= (insn
== BB_END (bb
));
2990 rtx set
= single_set (insn
);
2992 /* Don't split no-op move insns. These should silently
2993 disappear later in final. Splitting such insns would
2994 break the code that handles LIBCALL blocks. */
2995 if (set
&& set_noop_p (set
))
2997 /* Nops get in the way while scheduling, so delete them
2998 now if register allocation has already been done. It
2999 is too risky to try to do this before register
3000 allocation, and there are unlikely to be very many
3001 nops then anyways. */
3002 if (reload_completed
)
3003 delete_insn_and_edges (insn
);
3007 if (split_insn (insn
))
3009 bitmap_set_bit (blocks
, bb
->index
);
3017 default_rtl_profile ();
3019 find_many_sub_basic_blocks (blocks
);
3021 #ifdef ENABLE_CHECKING
3022 verify_flow_info ();
3025 sbitmap_free (blocks
);
3028 /* Same as split_all_insns, but do not expect CFG to be available.
3029 Used by machine dependent reorg passes. */
3032 split_all_insns_noflow (void)
3034 rtx_insn
*next
, *insn
;
3036 for (insn
= get_insns (); insn
; insn
= next
)
3038 next
= NEXT_INSN (insn
);
3041 /* Don't split no-op move insns. These should silently
3042 disappear later in final. Splitting such insns would
3043 break the code that handles LIBCALL blocks. */
3044 rtx set
= single_set (insn
);
3045 if (set
&& set_noop_p (set
))
3047 /* Nops get in the way while scheduling, so delete them
3048 now if register allocation has already been done. It
3049 is too risky to try to do this before register
3050 allocation, and there are unlikely to be very many
3053 ??? Should we use delete_insn when the CFG isn't valid? */
3054 if (reload_completed
)
3055 delete_insn_and_edges (insn
);
3064 #ifdef HAVE_peephole2
3065 struct peep2_insn_data
3071 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3072 static int peep2_current
;
3074 static bool peep2_do_rebuild_jump_labels
;
3075 static bool peep2_do_cleanup_cfg
;
3077 /* The number of instructions available to match a peep2. */
3078 int peep2_current_count
;
3080 /* A non-insn marker indicating the last insn of the block.
3081 The live_before regset for this element is correct, indicating
3082 DF_LIVE_OUT for the block. */
3083 #define PEEP2_EOB pc_rtx
3085 /* Wrap N to fit into the peep2_insn_data buffer. */
3088 peep2_buf_position (int n
)
3090 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3091 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3095 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3096 does not exist. Used by the recognizer to find the next insn to match
3097 in a multi-insn pattern. */
3100 peep2_next_insn (int n
)
3102 gcc_assert (n
<= peep2_current_count
);
3104 n
= peep2_buf_position (peep2_current
+ n
);
3106 return peep2_insn_data
[n
].insn
;
3109 /* Return true if REGNO is dead before the Nth non-note insn
3113 peep2_regno_dead_p (int ofs
, int regno
)
3115 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3117 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3119 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3121 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3124 /* Similarly for a REG. */
3127 peep2_reg_dead_p (int ofs
, rtx reg
)
3131 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3133 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3135 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3137 regno
= REGNO (reg
);
3138 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3140 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3145 /* Regno offset to be used in the register search. */
3146 static int search_ofs
;
3148 /* Try to find a hard register of mode MODE, matching the register class in
3149 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3150 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3151 in which case the only condition is that the register must be available
3152 before CURRENT_INSN.
3153 Registers that already have bits set in REG_SET will not be considered.
3155 If an appropriate register is available, it will be returned and the
3156 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3160 peep2_find_free_register (int from
, int to
, const char *class_str
,
3161 machine_mode mode
, HARD_REG_SET
*reg_set
)
3168 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3169 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3171 from
= peep2_buf_position (peep2_current
+ from
);
3172 to
= peep2_buf_position (peep2_current
+ to
);
3174 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3175 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3179 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3181 /* Don't use registers set or clobbered by the insn. */
3182 FOR_EACH_INSN_DEF (def
, peep2_insn_data
[from
].insn
)
3183 SET_HARD_REG_BIT (live
, DF_REF_REGNO (def
));
3185 from
= peep2_buf_position (from
+ 1);
3188 cl
= reg_class_for_constraint (lookup_constraint (class_str
));
3190 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3192 int raw_regno
, regno
, success
, j
;
3194 /* Distribute the free registers as much as possible. */
3195 raw_regno
= search_ofs
+ i
;
3196 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3197 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3198 #ifdef REG_ALLOC_ORDER
3199 regno
= reg_alloc_order
[raw_regno
];
3204 /* Can it support the mode we need? */
3205 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3209 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3211 /* Don't allocate fixed registers. */
3212 if (fixed_regs
[regno
+ j
])
3217 /* Don't allocate global registers. */
3218 if (global_regs
[regno
+ j
])
3223 /* Make sure the register is of the right class. */
3224 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3229 /* And that we don't create an extra save/restore. */
3230 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3236 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3242 /* And we don't clobber traceback for noreturn functions. */
3243 if ((regno
+ j
== FRAME_POINTER_REGNUM
3244 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3245 && (! reload_completed
|| frame_pointer_needed
))
3251 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3252 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3261 add_to_hard_reg_set (reg_set
, mode
, regno
);
3263 /* Start the next search with the next register. */
3264 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3266 search_ofs
= raw_regno
;
3268 return gen_rtx_REG (mode
, regno
);
3276 /* Forget all currently tracked instructions, only remember current
3280 peep2_reinit_state (regset live
)
3284 /* Indicate that all slots except the last holds invalid data. */
3285 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3286 peep2_insn_data
[i
].insn
= NULL_RTX
;
3287 peep2_current_count
= 0;
3289 /* Indicate that the last slot contains live_after data. */
3290 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3291 peep2_current
= MAX_INSNS_PER_PEEP2
;
3293 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3296 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3297 starting at INSN. Perform the replacement, removing the old insns and
3298 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3299 if the replacement is rejected. */
3302 peep2_attempt (basic_block bb
, rtx uncast_insn
, int match_len
, rtx_insn
*attempt
)
3304 rtx_insn
*insn
= safe_as_a
<rtx_insn
*> (uncast_insn
);
3306 rtx_insn
*last
, *before_try
, *x
;
3307 rtx eh_note
, as_note
;
3310 bool was_call
= false;
3312 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3313 match more than one insn, or to be split into more than one insn. */
3314 old_insn
= as_a
<rtx_insn
*> (peep2_insn_data
[peep2_current
].insn
);
3315 if (RTX_FRAME_RELATED_P (old_insn
))
3317 bool any_note
= false;
3323 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3324 may be in the stream for the purpose of register allocation. */
3325 if (active_insn_p (attempt
))
3328 new_insn
= next_active_insn (attempt
);
3329 if (next_active_insn (new_insn
))
3332 /* We have a 1-1 replacement. Copy over any frame-related info. */
3333 RTX_FRAME_RELATED_P (new_insn
) = 1;
3335 /* Allow the backend to fill in a note during the split. */
3336 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3337 switch (REG_NOTE_KIND (note
))
3339 case REG_FRAME_RELATED_EXPR
:
3340 case REG_CFA_DEF_CFA
:
3341 case REG_CFA_ADJUST_CFA
:
3342 case REG_CFA_OFFSET
:
3343 case REG_CFA_REGISTER
:
3344 case REG_CFA_EXPRESSION
:
3345 case REG_CFA_RESTORE
:
3346 case REG_CFA_SET_VDRAP
:
3353 /* If the backend didn't supply a note, copy one over. */
3355 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3356 switch (REG_NOTE_KIND (note
))
3358 case REG_FRAME_RELATED_EXPR
:
3359 case REG_CFA_DEF_CFA
:
3360 case REG_CFA_ADJUST_CFA
:
3361 case REG_CFA_OFFSET
:
3362 case REG_CFA_REGISTER
:
3363 case REG_CFA_EXPRESSION
:
3364 case REG_CFA_RESTORE
:
3365 case REG_CFA_SET_VDRAP
:
3366 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3373 /* If there still isn't a note, make sure the unwind info sees the
3374 same expression as before the split. */
3377 rtx old_set
, new_set
;
3379 /* The old insn had better have been simple, or annotated. */
3380 old_set
= single_set (old_insn
);
3381 gcc_assert (old_set
!= NULL
);
3383 new_set
= single_set (new_insn
);
3384 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3385 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3388 /* Copy prologue/epilogue status. This is required in order to keep
3389 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3390 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3393 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3394 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3395 cfg-related call notes. */
3396 for (i
= 0; i
<= match_len
; ++i
)
3401 j
= peep2_buf_position (peep2_current
+ i
);
3402 old_insn
= as_a
<rtx_insn
*> (peep2_insn_data
[j
].insn
);
3403 if (!CALL_P (old_insn
))
3408 while (new_insn
!= NULL_RTX
)
3410 if (CALL_P (new_insn
))
3412 new_insn
= NEXT_INSN (new_insn
);
3415 gcc_assert (new_insn
!= NULL_RTX
);
3417 CALL_INSN_FUNCTION_USAGE (new_insn
)
3418 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3419 SIBLING_CALL_P (new_insn
) = SIBLING_CALL_P (old_insn
);
3421 for (note
= REG_NOTES (old_insn
);
3423 note
= XEXP (note
, 1))
3424 switch (REG_NOTE_KIND (note
))
3429 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3433 /* Discard all other reg notes. */
3437 /* Croak if there is another call in the sequence. */
3438 while (++i
<= match_len
)
3440 j
= peep2_buf_position (peep2_current
+ i
);
3441 old_insn
= as_a
<rtx_insn
*> (peep2_insn_data
[j
].insn
);
3442 gcc_assert (!CALL_P (old_insn
));
3447 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3448 move those notes over to the new sequence. */
3450 for (i
= match_len
; i
>= 0; --i
)
3452 int j
= peep2_buf_position (peep2_current
+ i
);
3453 old_insn
= as_a
<rtx_insn
*> (peep2_insn_data
[j
].insn
);
3455 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3460 i
= peep2_buf_position (peep2_current
+ match_len
);
3461 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3463 /* Replace the old sequence with the new. */
3464 rtx_insn
*peepinsn
= as_a
<rtx_insn
*> (peep2_insn_data
[i
].insn
);
3465 last
= emit_insn_after_setloc (attempt
,
3466 peep2_insn_data
[i
].insn
,
3467 INSN_LOCATION (peepinsn
));
3468 before_try
= PREV_INSN (insn
);
3469 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3471 /* Re-insert the EH_REGION notes. */
3472 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3477 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3478 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3482 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3485 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3486 if (x
!= BB_END (bb
)
3487 && (can_throw_internal (x
)
3488 || can_nonlocal_goto (x
)))
3493 nfte
= split_block (bb
, x
);
3494 flags
= (eh_edge
->flags
3495 & (EDGE_EH
| EDGE_ABNORMAL
));
3497 flags
|= EDGE_ABNORMAL_CALL
;
3498 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3501 nehe
->probability
= eh_edge
->probability
;
3503 = REG_BR_PROB_BASE
- nehe
->probability
;
3505 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3510 /* Converting possibly trapping insn to non-trapping is
3511 possible. Zap dummy outgoing edges. */
3512 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3515 /* Re-insert the ARGS_SIZE notes. */
3517 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3519 /* If we generated a jump instruction, it won't have
3520 JUMP_LABEL set. Recompute after we're done. */
3521 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3524 peep2_do_rebuild_jump_labels
= true;
3531 /* After performing a replacement in basic block BB, fix up the life
3532 information in our buffer. LAST is the last of the insns that we
3533 emitted as a replacement. PREV is the insn before the start of
3534 the replacement. MATCH_LEN is the number of instructions that were
3535 matched, and which now need to be replaced in the buffer. */
3538 peep2_update_life (basic_block bb
, int match_len
, rtx_insn
*last
,
3541 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3545 INIT_REG_SET (&live
);
3546 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3548 gcc_assert (peep2_current_count
>= match_len
+ 1);
3549 peep2_current_count
-= match_len
+ 1;
3557 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3559 peep2_current_count
++;
3561 i
= MAX_INSNS_PER_PEEP2
;
3562 peep2_insn_data
[i
].insn
= x
;
3563 df_simulate_one_insn_backwards (bb
, x
, &live
);
3564 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3570 CLEAR_REG_SET (&live
);
3575 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3576 Return true if we added it, false otherwise. The caller will try to match
3577 peepholes against the buffer if we return false; otherwise it will try to
3578 add more instructions to the buffer. */
3581 peep2_fill_buffer (basic_block bb
, rtx insn
, regset live
)
3585 /* Once we have filled the maximum number of insns the buffer can hold,
3586 allow the caller to match the insns against peepholes. We wait until
3587 the buffer is full in case the target has similar peepholes of different
3588 length; we always want to match the longest if possible. */
3589 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3592 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3593 any other pattern, lest it change the semantics of the frame info. */
3594 if (RTX_FRAME_RELATED_P (insn
))
3596 /* Let the buffer drain first. */
3597 if (peep2_current_count
> 0)
3599 /* Now the insn will be the only thing in the buffer. */
3602 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3603 peep2_insn_data
[pos
].insn
= insn
;
3604 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3605 peep2_current_count
++;
3607 df_simulate_one_insn_forwards (bb
, as_a
<rtx_insn
*> (insn
), live
);
3611 /* Perform the peephole2 optimization pass. */
3614 peephole2_optimize (void)
3621 peep2_do_cleanup_cfg
= false;
3622 peep2_do_rebuild_jump_labels
= false;
3624 df_set_flags (DF_LR_RUN_DCE
);
3625 df_note_add_problem ();
3628 /* Initialize the regsets we're going to use. */
3629 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3630 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3632 live
= BITMAP_ALLOC (®_obstack
);
3634 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3636 bool past_end
= false;
3639 rtl_profile_for_bb (bb
);
3641 /* Start up propagation. */
3642 bitmap_copy (live
, DF_LR_IN (bb
));
3643 df_simulate_initialize_forwards (bb
, live
);
3644 peep2_reinit_state (live
);
3646 insn
= BB_HEAD (bb
);
3653 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3656 insn
= NEXT_INSN (insn
);
3657 if (insn
== NEXT_INSN (BB_END (bb
)))
3661 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3664 /* If we did not fill an empty buffer, it signals the end of the
3666 if (peep2_current_count
== 0)
3669 /* The buffer filled to the current maximum, so try to match. */
3671 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3672 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3673 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3675 /* Match the peephole. */
3676 head
= peep2_insn_data
[peep2_current
].insn
;
3677 attempt
= safe_as_a
<rtx_insn
*> (
3678 peephole2_insns (PATTERN (head
), head
, &match_len
));
3679 if (attempt
!= NULL
)
3681 rtx_insn
*last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3684 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3689 /* No match: advance the buffer by one insn. */
3690 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3691 peep2_current_count
--;
3695 default_rtl_profile ();
3696 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3697 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3699 if (peep2_do_rebuild_jump_labels
)
3700 rebuild_jump_labels (get_insns ());
3701 if (peep2_do_cleanup_cfg
)
3702 cleanup_cfg (CLEANUP_CFG_CHANGED
);
3704 #endif /* HAVE_peephole2 */
3706 /* Common predicates for use with define_bypass. */
3708 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3709 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3710 must be either a single_set or a PARALLEL with SETs inside. */
3713 store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3715 rtx out_set
, in_set
;
3716 rtx out_pat
, in_pat
;
3717 rtx out_exp
, in_exp
;
3720 in_set
= single_set (in_insn
);
3723 if (!MEM_P (SET_DEST (in_set
)))
3726 out_set
= single_set (out_insn
);
3729 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3734 out_pat
= PATTERN (out_insn
);
3736 if (GET_CODE (out_pat
) != PARALLEL
)
3739 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3741 out_exp
= XVECEXP (out_pat
, 0, i
);
3743 if (GET_CODE (out_exp
) == CLOBBER
)
3746 gcc_assert (GET_CODE (out_exp
) == SET
);
3748 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3755 in_pat
= PATTERN (in_insn
);
3756 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3758 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3760 in_exp
= XVECEXP (in_pat
, 0, i
);
3762 if (GET_CODE (in_exp
) == CLOBBER
)
3765 gcc_assert (GET_CODE (in_exp
) == SET
);
3767 if (!MEM_P (SET_DEST (in_exp
)))
3770 out_set
= single_set (out_insn
);
3773 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3778 out_pat
= PATTERN (out_insn
);
3779 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3781 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3783 out_exp
= XVECEXP (out_pat
, 0, j
);
3785 if (GET_CODE (out_exp
) == CLOBBER
)
3788 gcc_assert (GET_CODE (out_exp
) == SET
);
3790 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3800 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3801 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3802 or multiple set; IN_INSN should be single_set for truth, but for convenience
3803 of insn categorization may be any JUMP or CALL insn. */
3806 if_test_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3808 rtx out_set
, in_set
;
3810 in_set
= single_set (in_insn
);
3813 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3817 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3819 in_set
= SET_SRC (in_set
);
3821 out_set
= single_set (out_insn
);
3824 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3825 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3833 out_pat
= PATTERN (out_insn
);
3834 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3836 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3838 rtx exp
= XVECEXP (out_pat
, 0, i
);
3840 if (GET_CODE (exp
) == CLOBBER
)
3843 gcc_assert (GET_CODE (exp
) == SET
);
3845 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3846 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3855 rest_of_handle_peephole2 (void)
3857 #ifdef HAVE_peephole2
3858 peephole2_optimize ();
3865 const pass_data pass_data_peephole2
=
3867 RTL_PASS
, /* type */
3868 "peephole2", /* name */
3869 OPTGROUP_NONE
, /* optinfo_flags */
3870 TV_PEEPHOLE2
, /* tv_id */
3871 0, /* properties_required */
3872 0, /* properties_provided */
3873 0, /* properties_destroyed */
3874 0, /* todo_flags_start */
3875 TODO_df_finish
, /* todo_flags_finish */
3878 class pass_peephole2
: public rtl_opt_pass
3881 pass_peephole2 (gcc::context
*ctxt
)
3882 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3885 /* opt_pass methods: */
3886 /* The epiphany backend creates a second instance of this pass, so we need
3888 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3889 virtual bool gate (function
*) { return (optimize
> 0 && flag_peephole2
); }
3890 virtual unsigned int execute (function
*)
3892 return rest_of_handle_peephole2 ();
3895 }; // class pass_peephole2
3900 make_pass_peephole2 (gcc::context
*ctxt
)
3902 return new pass_peephole2 (ctxt
);
3907 const pass_data pass_data_split_all_insns
=
3909 RTL_PASS
, /* type */
3910 "split1", /* name */
3911 OPTGROUP_NONE
, /* optinfo_flags */
3912 TV_NONE
, /* tv_id */
3913 0, /* properties_required */
3914 0, /* properties_provided */
3915 0, /* properties_destroyed */
3916 0, /* todo_flags_start */
3917 0, /* todo_flags_finish */
3920 class pass_split_all_insns
: public rtl_opt_pass
3923 pass_split_all_insns (gcc::context
*ctxt
)
3924 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3927 /* opt_pass methods: */
3928 /* The epiphany backend creates a second instance of this pass, so
3929 we need a clone method. */
3930 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3931 virtual unsigned int execute (function
*)
3937 }; // class pass_split_all_insns
3942 make_pass_split_all_insns (gcc::context
*ctxt
)
3944 return new pass_split_all_insns (ctxt
);
3948 rest_of_handle_split_after_reload (void)
3950 /* If optimizing, then go ahead and split insns now. */
3960 const pass_data pass_data_split_after_reload
=
3962 RTL_PASS
, /* type */
3963 "split2", /* name */
3964 OPTGROUP_NONE
, /* optinfo_flags */
3965 TV_NONE
, /* tv_id */
3966 0, /* properties_required */
3967 0, /* properties_provided */
3968 0, /* properties_destroyed */
3969 0, /* todo_flags_start */
3970 0, /* todo_flags_finish */
3973 class pass_split_after_reload
: public rtl_opt_pass
3976 pass_split_after_reload (gcc::context
*ctxt
)
3977 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
3980 /* opt_pass methods: */
3981 virtual unsigned int execute (function
*)
3983 return rest_of_handle_split_after_reload ();
3986 }; // class pass_split_after_reload
3991 make_pass_split_after_reload (gcc::context
*ctxt
)
3993 return new pass_split_after_reload (ctxt
);
3998 const pass_data pass_data_split_before_regstack
=
4000 RTL_PASS
, /* type */
4001 "split3", /* name */
4002 OPTGROUP_NONE
, /* optinfo_flags */
4003 TV_NONE
, /* tv_id */
4004 0, /* properties_required */
4005 0, /* properties_provided */
4006 0, /* properties_destroyed */
4007 0, /* todo_flags_start */
4008 0, /* todo_flags_finish */
4011 class pass_split_before_regstack
: public rtl_opt_pass
4014 pass_split_before_regstack (gcc::context
*ctxt
)
4015 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
4018 /* opt_pass methods: */
4019 virtual bool gate (function
*);
4020 virtual unsigned int execute (function
*)
4026 }; // class pass_split_before_regstack
4029 pass_split_before_regstack::gate (function
*)
4031 #if HAVE_ATTR_length && defined (STACK_REGS)
4032 /* If flow2 creates new instructions which need splitting
4033 and scheduling after reload is not done, they might not be
4034 split until final which doesn't allow splitting
4035 if HAVE_ATTR_length. */
4036 # ifdef INSN_SCHEDULING
4037 return (optimize
&& !flag_schedule_insns_after_reload
);
4049 make_pass_split_before_regstack (gcc::context
*ctxt
)
4051 return new pass_split_before_regstack (ctxt
);
4055 rest_of_handle_split_before_sched2 (void)
4057 #ifdef INSN_SCHEDULING
4065 const pass_data pass_data_split_before_sched2
=
4067 RTL_PASS
, /* type */
4068 "split4", /* name */
4069 OPTGROUP_NONE
, /* optinfo_flags */
4070 TV_NONE
, /* tv_id */
4071 0, /* properties_required */
4072 0, /* properties_provided */
4073 0, /* properties_destroyed */
4074 0, /* todo_flags_start */
4075 0, /* todo_flags_finish */
4078 class pass_split_before_sched2
: public rtl_opt_pass
4081 pass_split_before_sched2 (gcc::context
*ctxt
)
4082 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4085 /* opt_pass methods: */
4086 virtual bool gate (function
*)
4088 #ifdef INSN_SCHEDULING
4089 return optimize
> 0 && flag_schedule_insns_after_reload
;
4095 virtual unsigned int execute (function
*)
4097 return rest_of_handle_split_before_sched2 ();
4100 }; // class pass_split_before_sched2
4105 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4107 return new pass_split_before_sched2 (ctxt
);
4112 const pass_data pass_data_split_for_shorten_branches
=
4114 RTL_PASS
, /* type */
4115 "split5", /* name */
4116 OPTGROUP_NONE
, /* optinfo_flags */
4117 TV_NONE
, /* tv_id */
4118 0, /* properties_required */
4119 0, /* properties_provided */
4120 0, /* properties_destroyed */
4121 0, /* todo_flags_start */
4122 0, /* todo_flags_finish */
4125 class pass_split_for_shorten_branches
: public rtl_opt_pass
4128 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4129 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4132 /* opt_pass methods: */
4133 virtual bool gate (function
*)
4135 /* The placement of the splitting that we do for shorten_branches
4136 depends on whether regstack is used by the target or not. */
4137 #if HAVE_ATTR_length && !defined (STACK_REGS)
4144 virtual unsigned int execute (function
*)
4146 return split_all_insns_noflow ();
4149 }; // class pass_split_for_shorten_branches
4154 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4156 return new pass_split_for_shorten_branches (ctxt
);
4159 /* (Re)initialize the target information after a change in target. */
4164 /* The information is zero-initialized, so we don't need to do anything
4165 first time round. */
4166 if (!this_target_recog
->x_initialized
)
4168 this_target_recog
->x_initialized
= true;
4171 memset (this_target_recog
->x_bool_attr_masks
, 0,
4172 sizeof (this_target_recog
->x_bool_attr_masks
));
4173 for (int i
= 0; i
< LAST_INSN_CODE
; ++i
)
4174 if (this_target_recog
->x_op_alt
[i
])
4176 free (this_target_recog
->x_op_alt
[i
]);
4177 this_target_recog
->x_op_alt
[i
] = 0;