1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
596 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
597 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
601 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
604 dump_value_slim (lra_dump_file
, original
, 1);
606 if (new_class
!= lra_get_allocno_class (regno
))
607 lra_change_class (regno
, new_class
, ", change to", false);
608 if (lra_dump_file
!= NULL
)
609 fprintf (lra_dump_file
, "\n");
612 /* If we have an input reload with a different mode, make sure it
613 will get a different hard reg. */
614 else if (REG_P (original
)
615 && REG_P (curr_insn_input_reloads
[i
].input
)
616 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
617 && (GET_MODE (original
)
618 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
621 *result_reg
= (unique_p
622 ? lra_create_new_reg_with_unique_value
623 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
624 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
625 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
633 /* The page contains code to extract memory address parts. */
635 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 ok_for_index_p_nonstrict (rtx reg
)
639 unsigned regno
= REGNO (reg
);
641 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
644 /* A version of regno_ok_for_base_p for use here, when all pseudos
645 should count as OK. Arguments as for regno_ok_for_base_p. */
647 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
648 enum rtx_code outer_code
, enum rtx_code index_code
)
650 unsigned regno
= REGNO (reg
);
652 if (regno
>= FIRST_PSEUDO_REGISTER
)
654 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
659 /* The page contains major code to choose the current insn alternative
660 and generate reloads for it. */
662 /* Return the offset from REGNO of the least significant register
665 This function is used to tell whether two registers satisfy
666 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
668 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
669 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
671 lra_constraint_offset (int regno
, machine_mode mode
)
673 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
674 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
675 && SCALAR_INT_MODE_P (mode
))
676 return hard_regno_nregs
[regno
][mode
] - 1;
680 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
681 if they are the same hard reg, and has special hacks for
682 auto-increment and auto-decrement. This is specifically intended for
683 process_alt_operands to use in determining whether two operands
684 match. X is the operand whose number is the lower of the two.
686 It is supposed that X is the output operand and Y is the input
687 operand. Y_HARD_REGNO is the final hard regno of register Y or
688 register in subreg Y as we know it now. Otherwise, it is a
691 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
694 RTX_CODE code
= GET_CODE (x
);
699 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
700 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
704 i
= get_hard_regno (x
, false);
708 if ((j
= y_hard_regno
) < 0)
711 i
+= lra_constraint_offset (i
, GET_MODE (x
));
712 j
+= lra_constraint_offset (j
, GET_MODE (y
));
717 /* If two operands must match, because they are really a single
718 operand of an assembler insn, then two post-increments are invalid
719 because the assembler insn would increment only once. On the
720 other hand, a post-increment matches ordinary indexing if the
721 post-increment is the output operand. */
722 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
723 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
725 /* Two pre-increments are invalid because the assembler insn would
726 increment only once. On the other hand, a pre-increment matches
727 ordinary indexing if the pre-increment is the input operand. */
728 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
729 || GET_CODE (y
) == PRE_MODIFY
)
730 return operands_match_p (x
, XEXP (y
, 0), -1);
734 if (code
== REG
&& REG_P (y
))
735 return REGNO (x
) == REGNO (y
);
737 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
738 && x
== SUBREG_REG (y
))
740 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
741 && SUBREG_REG (x
) == y
)
744 /* Now we have disposed of all the cases in which different rtx
746 if (code
!= GET_CODE (y
))
749 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
750 if (GET_MODE (x
) != GET_MODE (y
))
759 return label_ref_label (x
) == label_ref_label (y
);
761 return XSTR (x
, 0) == XSTR (y
, 0);
767 /* Compare the elements. If any pair of corresponding elements fail
768 to match, return false for the whole things. */
770 fmt
= GET_RTX_FORMAT (code
);
771 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
777 if (XWINT (x
, i
) != XWINT (y
, i
))
782 if (XINT (x
, i
) != XINT (y
, i
))
787 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
796 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
798 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
800 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
806 /* It is believed that rtx's at this level will never
807 contain anything but integers and other rtx's, except for
808 within LABEL_REFs and SYMBOL_REFs. */
816 /* True if X is a constant that can be forced into the constant pool.
817 MODE is the mode of the operand, or VOIDmode if not known. */
818 #define CONST_POOL_OK_P(MODE, X) \
819 ((MODE) != VOIDmode \
821 && GET_CODE (X) != HIGH \
822 && !targetm.cannot_force_const_mem (MODE, X))
824 /* True if C is a non-empty register class that has too few registers
825 to be safely used as a reload target class. */
826 #define SMALL_REGISTER_CLASS_P(C) \
827 (ira_class_hard_regs_num [(C)] == 1 \
828 || (ira_class_hard_regs_num [(C)] >= 1 \
829 && targetm.class_likely_spilled_p (C)))
831 /* If REG is a reload pseudo, try to make its class satisfying CL. */
833 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
835 enum reg_class rclass
;
837 /* Do not make more accurate class from reloads generated. They are
838 mostly moves with a lot of constraints. Making more accurate
839 class may results in very narrow class and impossibility of find
840 registers for several reloads of one insn. */
841 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
843 if (GET_CODE (reg
) == SUBREG
)
844 reg
= SUBREG_REG (reg
);
845 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
847 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
848 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
851 /* Searches X for any reference to a reg with the same value as REGNO,
852 returning the rtx of the reference found if any. Otherwise,
855 regno_val_use_in (unsigned int regno
, rtx x
)
861 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
864 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
865 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
869 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
872 else if (fmt
[i
] == 'E')
873 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
874 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
881 /* Return true if all current insn non-output operands except INS (it
882 has a negaitve end marker) do not use pseudos with the same value
885 check_conflict_input_operands (int regno
, signed char *ins
)
888 int n_operands
= curr_static_id
->n_operands
;
890 for (int nop
= 0; nop
< n_operands
; nop
++)
891 if (! curr_static_id
->operand
[nop
].is_operator
892 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
894 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
898 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
904 /* Generate reloads for matching OUT and INS (array of input operand
905 numbers with end marker -1) with reg class GOAL_CLASS, considering
906 output operands OUTS (similar array to INS) needing to be in different
907 registers. Add input and output reloads correspondingly to the lists
908 *BEFORE and *AFTER. OUT might be negative. In this case we generate
909 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
910 that the output operand is early clobbered for chosen alternative. */
912 match_reload (signed char out
, signed char *ins
, signed char *outs
,
913 enum reg_class goal_class
, rtx_insn
**before
,
914 rtx_insn
**after
, bool early_clobber_p
)
918 rtx new_in_reg
, new_out_reg
, reg
;
919 machine_mode inmode
, outmode
;
920 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
921 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
923 inmode
= curr_operand_mode
[ins
[0]];
924 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
925 push_to_sequence (*before
);
926 if (inmode
!= outmode
)
928 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
931 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
933 if (SCALAR_INT_MODE_P (inmode
))
934 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
936 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
937 LRA_SUBREG_P (new_out_reg
) = 1;
938 /* If the input reg is dying here, we can use the same hard
939 register for REG and IN_RTX. We do it only for original
940 pseudos as reload pseudos can die although original
941 pseudos still live where reload pseudos dies. */
942 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
943 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
945 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
946 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
951 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
953 if (SCALAR_INT_MODE_P (outmode
))
954 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
956 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
957 /* NEW_IN_REG is non-paradoxical subreg. We don't want
958 NEW_OUT_REG living above. We add clobber clause for
959 this. This is just a temporary clobber. We can remove
960 it at the end of LRA work. */
961 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
962 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
963 LRA_SUBREG_P (new_in_reg
) = 1;
964 if (GET_CODE (in_rtx
) == SUBREG
)
966 rtx subreg_reg
= SUBREG_REG (in_rtx
);
968 /* If SUBREG_REG is dying here and sub-registers IN_RTX
969 and NEW_IN_REG are similar, we can use the same hard
970 register for REG and SUBREG_REG. */
971 if (REG_P (subreg_reg
)
972 && (int) REGNO (subreg_reg
) < lra_new_regno_start
973 && GET_MODE (subreg_reg
) == outmode
974 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
975 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
976 && (! early_clobber_p
977 || check_conflict_input_operands (REGNO (subreg_reg
),
979 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
985 /* Pseudos have values -- see comments for lra_reg_info.
986 Different pseudos with the same value do not conflict even if
987 they live in the same place. When we create a pseudo we
988 assign value of original pseudo (if any) from which we
989 created the new pseudo. If we create the pseudo from the
990 input pseudo, the new pseudo will have no conflict with the
991 input pseudo which is wrong when the input pseudo lives after
992 the insn and as the new pseudo value is changed by the insn
993 output. Therefore we create the new pseudo from the output
994 except the case when we have single matched dying input
997 We cannot reuse the current output register because we might
998 have a situation like "a <- a op b", where the constraints
999 force the second input operand ("b") to match the output
1000 operand ("a"). "b" must then be copied into a new register
1001 so that it doesn't clobber the current value of "a".
1003 We can not use the same value if the output pseudo is
1004 early clobbered or the input pseudo is mentioned in the
1005 output, e.g. as an address part in memory, because
1006 output reload will actually extend the pseudo liveness.
1007 We don't care about eliminable hard regs here as we are
1008 interesting only in pseudos. */
1010 /* Matching input's register value is the same as one of the other
1011 output operand. Output operands in a parallel insn must be in
1012 different registers. */
1013 out_conflict
= false;
1016 for (i
= 0; outs
[i
] >= 0; i
++)
1018 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1019 if (REG_P (other_out_rtx
)
1020 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1023 out_conflict
= true;
1029 new_in_reg
= new_out_reg
1030 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1031 && (int) REGNO (in_rtx
) < lra_new_regno_start
1032 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1033 && (! early_clobber_p
1034 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1036 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1038 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1039 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1042 /* In operand can be got from transformations before processing insn
1043 constraints. One example of such transformations is subreg
1044 reloading (see function simplify_operand_subreg). The new
1045 pseudos created by the transformations might have inaccurate
1046 class (ALL_REGS) and we should make their classes more
1048 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1049 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1050 *before
= get_insns ();
1052 /* Add the new pseudo to consider values of subsequent input reload
1054 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1055 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1056 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1057 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1058 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1061 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1062 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1063 *curr_id
->operand_loc
[in
] = new_in_reg
;
1065 lra_update_dups (curr_id
, ins
);
1068 /* See a comment for the input operand above. */
1069 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1070 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1073 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1075 *after
= get_insns ();
1078 *curr_id
->operand_loc
[out
] = new_out_reg
;
1079 lra_update_dup (curr_id
, out
);
1082 /* Return register class which is union of all reg classes in insn
1083 constraint alternative string starting with P. */
1084 static enum reg_class
1085 reg_class_from_constraints (const char *p
)
1088 enum reg_class op_class
= NO_REGS
;
1091 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1098 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1102 enum constraint_num cn
= lookup_constraint (p
);
1103 enum reg_class cl
= reg_class_for_constraint (cn
);
1106 if (insn_extra_address_constraint (cn
))
1108 = (reg_class_subunion
1109 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1110 ADDRESS
, SCRATCH
)]);
1114 op_class
= reg_class_subunion
[op_class
][cl
];
1117 while ((p
+= len
), c
);
1121 /* If OP is a register, return the class of the register as per
1122 get_reg_class, otherwise return NO_REGS. */
1123 static inline enum reg_class
1124 get_op_class (rtx op
)
1126 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1129 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1130 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1131 SUBREG for VAL to make them equal. */
1133 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1135 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1137 /* Usually size of mem_pseudo is greater than val size but in
1138 rare cases it can be less as it can be defined by target
1139 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1142 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1143 GET_CODE (val
) == SUBREG
1144 ? SUBREG_REG (val
) : val
);
1145 LRA_SUBREG_P (val
) = 1;
1149 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1150 LRA_SUBREG_P (mem_pseudo
) = 1;
1153 return to_p
? gen_move_insn (mem_pseudo
, val
)
1154 : gen_move_insn (val
, mem_pseudo
);
1157 /* Process a special case insn (register move), return true if we
1158 don't need to process it anymore. INSN should be a single set
1159 insn. Set up that RTL was changed through CHANGE_P and macro
1160 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1163 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1166 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1168 enum reg_class dclass
, sclass
, secondary_class
;
1169 secondary_reload_info sri
;
1171 lra_assert (curr_insn_set
!= NULL_RTX
);
1172 dreg
= dest
= SET_DEST (curr_insn_set
);
1173 sreg
= src
= SET_SRC (curr_insn_set
);
1174 if (GET_CODE (dest
) == SUBREG
)
1175 dreg
= SUBREG_REG (dest
);
1176 if (GET_CODE (src
) == SUBREG
)
1177 sreg
= SUBREG_REG (src
);
1178 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1180 sclass
= dclass
= NO_REGS
;
1182 dclass
= get_reg_class (REGNO (dreg
));
1183 gcc_assert (dclass
< LIM_REG_CLASSES
);
1184 if (dclass
== ALL_REGS
)
1185 /* ALL_REGS is used for new pseudos created by transformations
1186 like reload of SUBREG_REG (see function
1187 simplify_operand_subreg). We don't know their class yet. We
1188 should figure out the class from processing the insn
1189 constraints not in this fast path function. Even if ALL_REGS
1190 were a right class for the pseudo, secondary_... hooks usually
1191 are not define for ALL_REGS. */
1194 sclass
= get_reg_class (REGNO (sreg
));
1195 gcc_assert (sclass
< LIM_REG_CLASSES
);
1196 if (sclass
== ALL_REGS
)
1197 /* See comments above. */
1199 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1201 #ifdef SECONDARY_MEMORY_NEEDED
1202 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1203 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1204 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1205 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1213 if (! REG_P (dreg
) || ! REG_P (sreg
))
1215 sri
.prev_sri
= NULL
;
1216 sri
.icode
= CODE_FOR_nothing
;
1218 secondary_class
= NO_REGS
;
1219 /* Set up hard register for a reload pseudo for hook
1220 secondary_reload because some targets just ignore unassigned
1221 pseudos in the hook. */
1222 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1224 dregno
= REGNO (dreg
);
1225 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1229 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1231 sregno
= REGNO (sreg
);
1232 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1236 if (sclass
!= NO_REGS
)
1238 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1239 (reg_class_t
) sclass
,
1240 GET_MODE (src
), &sri
);
1241 if (sclass
== NO_REGS
1242 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1243 && dclass
!= NO_REGS
))
1245 enum reg_class old_sclass
= secondary_class
;
1246 secondary_reload_info old_sri
= sri
;
1248 sri
.prev_sri
= NULL
;
1249 sri
.icode
= CODE_FOR_nothing
;
1252 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1253 (reg_class_t
) dclass
,
1254 GET_MODE (src
), &sri
);
1255 /* Check the target hook consistency. */
1257 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1258 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1259 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1262 reg_renumber
[sregno
] = -1;
1264 reg_renumber
[dregno
] = -1;
1265 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1269 if (secondary_class
!= NO_REGS
)
1270 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1274 if (sri
.icode
== CODE_FOR_nothing
)
1275 lra_emit_move (new_reg
, src
);
1278 enum reg_class scratch_class
;
1280 scratch_class
= (reg_class_from_constraints
1281 (insn_data
[sri
.icode
].operand
[2].constraint
));
1282 scratch_reg
= (lra_create_new_reg_with_unique_value
1283 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1284 scratch_class
, "scratch"));
1285 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1288 before
= get_insns ();
1290 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1291 if (new_reg
!= NULL_RTX
)
1292 SET_SRC (curr_insn_set
) = new_reg
;
1295 if (lra_dump_file
!= NULL
)
1297 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1298 dump_insn_slim (lra_dump_file
, curr_insn
);
1300 lra_set_insn_deleted (curr_insn
);
1306 /* The following data describe the result of process_alt_operands.
1307 The data are used in curr_insn_transform to generate reloads. */
1309 /* The chosen reg classes which should be used for the corresponding
1311 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1312 /* True if the operand should be the same as another operand and that
1313 other operand does not need a reload. */
1314 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1315 /* True if the operand does not need a reload. */
1316 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1317 /* True if the operand can be offsetable memory. */
1318 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1319 /* The number of an operand to which given operand can be matched to. */
1320 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1321 /* The number of elements in the following array. */
1322 static int goal_alt_dont_inherit_ops_num
;
1323 /* Numbers of operands whose reload pseudos should not be inherited. */
1324 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1325 /* True if the insn commutative operands should be swapped. */
1326 static bool goal_alt_swapped
;
1327 /* The chosen insn alternative. */
1328 static int goal_alt_number
;
1330 /* True if the corresponding operand is the result of an equivalence
1332 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1334 /* The following five variables are used to choose the best insn
1335 alternative. They reflect final characteristics of the best
1338 /* Number of necessary reloads and overall cost reflecting the
1339 previous value and other unpleasantness of the best alternative. */
1340 static int best_losers
, best_overall
;
1341 /* Overall number hard registers used for reloads. For example, on
1342 some targets we need 2 general registers to reload DFmode and only
1343 one floating point register. */
1344 static int best_reload_nregs
;
1345 /* Overall number reflecting distances of previous reloading the same
1346 value. The distances are counted from the current BB start. It is
1347 used to improve inheritance chances. */
1348 static int best_reload_sum
;
1350 /* True if the current insn should have no correspondingly input or
1352 static bool no_input_reloads_p
, no_output_reloads_p
;
1354 /* True if we swapped the commutative operands in the current
1356 static int curr_swapped
;
1358 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1359 register of class CL. Add any input reloads to list BEFORE. AFTER
1360 is nonnull if *LOC is an automodified value; handle that case by
1361 adding the required output reloads to list AFTER. Return true if
1362 the RTL was changed.
1364 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1365 register. Return false if the address register is correct. */
1367 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1371 enum reg_class rclass
, new_class
;
1375 bool subreg_p
, before_p
= false;
1377 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1380 reg
= SUBREG_REG (*loc
);
1381 mode
= GET_MODE (reg
);
1383 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1384 between two registers with different classes, but there normally will
1385 be "mov" which transfers element of vector register into the general
1386 register, and this normally will be a subreg which should be reloaded
1387 as a whole. This is particularly likely to be triggered when
1388 -fno-split-wide-types specified. */
1390 || in_class_p (reg
, cl
, &new_class
)
1391 || GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (ptr_mode
))
1392 loc
= &SUBREG_REG (*loc
);
1396 mode
= GET_MODE (reg
);
1401 /* Always reload memory in an address even if the target supports
1403 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1408 regno
= REGNO (reg
);
1409 rclass
= get_reg_class (regno
);
1411 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1413 if (lra_dump_file
!= NULL
)
1415 fprintf (lra_dump_file
,
1416 "Changing pseudo %d in address of insn %u on equiv ",
1417 REGNO (reg
), INSN_UID (curr_insn
));
1418 dump_value_slim (lra_dump_file
, *loc
, 1);
1419 fprintf (lra_dump_file
, "\n");
1421 *loc
= copy_rtx (*loc
);
1423 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1428 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1429 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1432 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1436 lra_change_class (regno
, new_class
, " Change to", true);
1444 push_to_sequence (*before
);
1445 lra_emit_move (new_reg
, reg
);
1446 *before
= get_insns ();
1453 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1455 *after
= get_insns ();
1461 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1462 the insn to be inserted before curr insn. AFTER returns the
1463 the insn to be inserted after curr insn. ORIGREG and NEWREG
1464 are the original reg and new reg for reload. */
1466 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1471 push_to_sequence (*before
);
1472 lra_emit_move (newreg
, origreg
);
1473 *before
= get_insns ();
1479 lra_emit_move (origreg
, newreg
);
1481 *after
= get_insns ();
1486 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1487 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1489 /* Make reloads for subreg in operand NOP with internal subreg mode
1490 REG_MODE, add new reloads for further processing. Return true if
1491 any change was done. */
1493 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1496 rtx_insn
*before
, *after
;
1497 machine_mode mode
, innermode
;
1499 rtx operand
= *curr_id
->operand_loc
[nop
];
1500 enum reg_class regclass
;
1503 before
= after
= NULL
;
1505 if (GET_CODE (operand
) != SUBREG
)
1508 mode
= GET_MODE (operand
);
1509 reg
= SUBREG_REG (operand
);
1510 innermode
= GET_MODE (reg
);
1511 type
= curr_static_id
->operand
[nop
].type
;
1514 const bool addr_was_valid
1515 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1516 alter_subreg (curr_id
->operand_loc
[nop
], false);
1517 rtx subst
= *curr_id
->operand_loc
[nop
];
1518 lra_assert (MEM_P (subst
));
1521 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1522 MEM_ADDR_SPACE (subst
))
1523 || ((get_constraint_type (lookup_constraint
1524 (curr_static_id
->operand
[nop
].constraint
))
1525 != CT_SPECIAL_MEMORY
)
1526 /* We still can reload address and if the address is
1527 valid, we can remove subreg without reloading its
1529 && valid_address_p (GET_MODE (subst
),
1531 [ira_class_hard_regs
1532 [base_reg_class (GET_MODE (subst
),
1533 MEM_ADDR_SPACE (subst
),
1534 ADDRESS
, SCRATCH
)][0]],
1535 MEM_ADDR_SPACE (subst
))))
1537 /* If we change the address for a paradoxical subreg of memory, the
1538 new address might violate the necessary alignment or the access
1539 might be slow; take this into consideration. We need not worry
1540 about accesses beyond allocated memory for paradoxical memory
1541 subregs as we don't substitute such equiv memory (see processing
1542 equivalences in function lra_constraints) and because for spilled
1543 pseudos we allocate stack memory enough for the biggest
1544 corresponding paradoxical subreg.
1546 However, do not blindly simplify a (subreg (mem ...)) for
1547 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1548 data into a register when the inner is narrower than outer or
1549 missing important data from memory when the inner is wider than
1550 outer. This rule only applies to modes that are no wider than
1552 if (!(GET_MODE_PRECISION (mode
) != GET_MODE_PRECISION (innermode
)
1553 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1554 && GET_MODE_SIZE (innermode
) <= UNITS_PER_WORD
1555 && WORD_REGISTER_OPERATIONS
)
1556 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1557 && SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (subst
)))
1558 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1559 && SLOW_UNALIGNED_ACCESS (innermode
, MEM_ALIGN (reg
)))))
1562 *curr_id
->operand_loc
[nop
] = operand
;
1564 /* But if the address was not valid, we cannot reload the MEM without
1565 reloading the address first. */
1566 if (!addr_was_valid
)
1567 process_address (nop
, false, &before
, &after
);
1569 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1570 enum reg_class rclass
1571 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1572 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1573 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1575 bool insert_before
, insert_after
;
1576 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1578 insert_before
= (type
!= OP_OUT
1579 || GET_MODE_SIZE (innermode
)
1580 > GET_MODE_SIZE (mode
));
1581 insert_after
= type
!= OP_IN
;
1582 insert_move_for_subreg (insert_before
? &before
: NULL
,
1583 insert_after
? &after
: NULL
,
1586 SUBREG_REG (operand
) = new_reg
;
1588 /* Convert to MODE. */
1591 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1592 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1593 rclass
, TRUE
, "slow mem", &new_reg
))
1595 bool insert_before
, insert_after
;
1596 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1598 insert_before
= type
!= OP_OUT
;
1599 insert_after
= type
!= OP_IN
;
1600 insert_move_for_subreg (insert_before
? &before
: NULL
,
1601 insert_after
? &after
: NULL
,
1604 *curr_id
->operand_loc
[nop
] = new_reg
;
1605 lra_process_new_insns (curr_insn
, before
, after
,
1606 "Inserting slow mem reload");
1610 /* If the address was valid and became invalid, prefer to reload
1611 the memory. Typical case is when the index scale should
1612 correspond the memory. */
1613 *curr_id
->operand_loc
[nop
] = operand
;
1614 /* Do not return false here as the MEM_P (reg) will be processed
1615 later in this function. */
1617 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1619 alter_subreg (curr_id
->operand_loc
[nop
], false);
1622 else if (CONSTANT_P (reg
))
1624 /* Try to simplify subreg of constant. It is usually result of
1625 equivalence substitution. */
1626 if (innermode
== VOIDmode
1627 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1628 innermode
= curr_static_id
->operand
[nop
].mode
;
1629 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1630 SUBREG_BYTE (operand
))) != NULL_RTX
)
1632 *curr_id
->operand_loc
[nop
] = new_reg
;
1636 /* Put constant into memory when we have mixed modes. It generates
1637 a better code in most cases as it does not need a secondary
1638 reload memory. It also prevents LRA looping when LRA is using
1639 secondary reload memory again and again. */
1640 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1641 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1643 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1644 alter_subreg (curr_id
->operand_loc
[nop
], false);
1647 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1648 if there may be a problem accessing OPERAND in the outer
1651 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1652 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1653 /* Don't reload paradoxical subregs because we could be looping
1654 having repeatedly final regno out of hard regs range. */
1655 && (hard_regno_nregs
[hard_regno
][innermode
]
1656 >= hard_regno_nregs
[hard_regno
][mode
])
1657 && simplify_subreg_regno (hard_regno
, innermode
,
1658 SUBREG_BYTE (operand
), mode
) < 0
1659 /* Don't reload subreg for matching reload. It is actually
1660 valid subreg in LRA. */
1661 && ! LRA_SUBREG_P (operand
))
1662 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1664 enum reg_class rclass
;
1667 /* There is a big probability that we will get the same class
1668 for the new pseudo and we will get the same insn which
1669 means infinite looping. So spill the new pseudo. */
1672 /* The class will be defined later in curr_insn_transform. */
1674 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1676 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1677 rclass
, TRUE
, "subreg reg", &new_reg
))
1679 bool insert_before
, insert_after
;
1680 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1682 insert_before
= (type
!= OP_OUT
1683 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1684 insert_after
= (type
!= OP_IN
);
1685 insert_move_for_subreg (insert_before
? &before
: NULL
,
1686 insert_after
? &after
: NULL
,
1689 SUBREG_REG (operand
) = new_reg
;
1690 lra_process_new_insns (curr_insn
, before
, after
,
1691 "Inserting subreg reload");
1694 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1695 IRA allocates hardreg to the inner pseudo reg according to its mode
1696 instead of the outermode, so the size of the hardreg may not be enough
1697 to contain the outermode operand, in that case we may need to insert
1698 reload for the reg. For the following two types of paradoxical subreg,
1699 we need to insert reload:
1700 1. If the op_type is OP_IN, and the hardreg could not be paired with
1701 other hardreg to contain the outermode operand
1702 (checked by in_hard_reg_set_p), we need to insert the reload.
1703 2. If the op_type is OP_OUT or OP_INOUT.
1705 Here is a paradoxical subreg example showing how the reload is generated:
1707 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1708 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1710 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1711 here, if reg107 is assigned to hardreg R15, because R15 is the last
1712 hardreg, compiler cannot find another hardreg to pair with R15 to
1713 contain TImode data. So we insert a TImode reload reg180 for it.
1714 After reload is inserted:
1716 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1717 (reg:DI 107 [ __comp ])) -1
1718 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1719 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1721 Two reload hard registers will be allocated to reg180 to save TImode data
1723 else if (REG_P (reg
)
1724 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1725 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1726 && (hard_regno_nregs
[hard_regno
][innermode
]
1727 < hard_regno_nregs
[hard_regno
][mode
])
1728 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1730 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1733 /* The class will be defined later in curr_insn_transform. */
1734 enum reg_class rclass
1735 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1737 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1738 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1741 bool insert_before
, insert_after
;
1743 PUT_MODE (new_reg
, mode
);
1744 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1745 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1747 insert_before
= (type
!= OP_OUT
);
1748 insert_after
= (type
!= OP_IN
);
1749 insert_move_for_subreg (insert_before
? &before
: NULL
,
1750 insert_after
? &after
: NULL
,
1753 SUBREG_REG (operand
) = new_reg
;
1754 lra_process_new_insns (curr_insn
, before
, after
,
1755 "Inserting paradoxical subreg reload");
1761 /* Return TRUE if X refers for a hard register from SET. */
1763 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1765 int i
, j
, x_hard_regno
;
1772 code
= GET_CODE (x
);
1773 mode
= GET_MODE (x
);
1777 code
= GET_CODE (x
);
1778 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1779 mode
= GET_MODE (x
);
1784 x_hard_regno
= get_hard_regno (x
, true);
1785 return (x_hard_regno
>= 0
1786 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1790 struct address_info ad
;
1792 decompose_mem_address (&ad
, x
);
1793 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1795 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1798 fmt
= GET_RTX_FORMAT (code
);
1799 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1803 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1806 else if (fmt
[i
] == 'E')
1808 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1809 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1816 /* Return true if OP is a spilled pseudo. */
1818 spilled_pseudo_p (rtx op
)
1821 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1824 /* Return true if X is a general constant. */
1826 general_constant_p (rtx x
)
1828 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1832 reg_in_class_p (rtx reg
, enum reg_class cl
)
1835 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1836 return in_class_p (reg
, cl
, NULL
);
1839 /* Return true if SET of RCLASS contains no hard regs which can be
1842 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1844 enum machine_mode mode
)
1848 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1849 COPY_HARD_REG_SET (temp
, set
);
1850 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1851 return (hard_reg_set_subset_p
1852 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1855 /* Major function to choose the current insn alternative and what
1856 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1857 negative we should consider only this alternative. Return false if
1858 we can not choose the alternative or find how to reload the
1861 process_alt_operands (int only_alternative
)
1864 int nop
, overall
, nalt
;
1865 int n_alternatives
= curr_static_id
->n_alternatives
;
1866 int n_operands
= curr_static_id
->n_operands
;
1867 /* LOSERS counts the operands that don't fit this alternative and
1868 would require loading. */
1871 /* REJECT is a count of how undesirable this alternative says it is
1872 if any reloading is required. If the alternative matches exactly
1873 then REJECT is ignored, but otherwise it gets this much counted
1874 against it in addition to the reloading needed. */
1876 /* This is defined by '!' or '?' alternative constraint and added to
1877 reject. But in some cases it can be ignored. */
1880 /* The number of elements in the following array. */
1881 int early_clobbered_regs_num
;
1882 /* Numbers of operands which are early clobber registers. */
1883 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1884 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1885 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1886 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1887 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1888 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1889 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1890 /* The number of elements in the following array. */
1891 int curr_alt_dont_inherit_ops_num
;
1892 /* Numbers of operands whose reload pseudos should not be inherited. */
1893 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1895 /* The register when the operand is a subreg of register, otherwise the
1897 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1898 /* The register if the operand is a register or subreg of register,
1900 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1901 int hard_regno
[MAX_RECOG_OPERANDS
];
1902 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1903 int reload_nregs
, reload_sum
;
1907 /* Calculate some data common for all alternatives to speed up the
1909 for (nop
= 0; nop
< n_operands
; nop
++)
1913 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1914 /* The real hard regno of the operand after the allocation. */
1915 hard_regno
[nop
] = get_hard_regno (op
, true);
1917 operand_reg
[nop
] = reg
= op
;
1918 biggest_mode
[nop
] = GET_MODE (op
);
1919 if (GET_CODE (op
) == SUBREG
)
1921 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1922 if (GET_MODE_SIZE (biggest_mode
[nop
])
1923 < GET_MODE_SIZE (GET_MODE (reg
)))
1924 biggest_mode
[nop
] = GET_MODE (reg
);
1927 operand_reg
[nop
] = NULL_RTX
;
1928 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1929 || ((int) REGNO (reg
)
1930 == lra_get_elimination_hard_regno (REGNO (reg
))))
1931 no_subreg_reg_operand
[nop
] = reg
;
1933 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1934 /* Just use natural mode for elimination result. It should
1935 be enough for extra constraints hooks. */
1936 = regno_reg_rtx
[hard_regno
[nop
]];
1939 /* The constraints are made of several alternatives. Each operand's
1940 constraint looks like foo,bar,... with commas separating the
1941 alternatives. The first alternatives for all operands go
1942 together, the second alternatives go together, etc.
1944 First loop over alternatives. */
1945 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1946 if (only_alternative
>= 0)
1947 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1949 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1951 /* Loop over operands for one constraint alternative. */
1952 if (!TEST_BIT (preferred
, nalt
))
1955 overall
= losers
= addr_losers
= 0;
1956 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
1957 for (nop
= 0; nop
< n_operands
; nop
++)
1959 int inc
= (curr_static_id
1960 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1961 if (lra_dump_file
!= NULL
&& inc
!= 0)
1962 fprintf (lra_dump_file
,
1963 " Staticly defined alt reject+=%d\n", inc
);
1964 static_reject
+= inc
;
1966 reject
+= static_reject
;
1967 early_clobbered_regs_num
= 0;
1969 for (nop
= 0; nop
< n_operands
; nop
++)
1973 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1974 bool win
, did_match
, offmemok
, early_clobber_p
;
1975 /* false => this operand can be reloaded somehow for this
1978 /* true => this operand can be reloaded if the alternative
1981 /* True if a constant forced into memory would be OK for
1984 enum reg_class this_alternative
, this_costly_alternative
;
1985 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1986 bool this_alternative_match_win
, this_alternative_win
;
1987 bool this_alternative_offmemok
;
1990 enum constraint_num cn
;
1992 opalt_num
= nalt
* n_operands
+ nop
;
1993 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1995 /* Fast track for no constraints at all. */
1996 curr_alt
[nop
] = NO_REGS
;
1997 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1998 curr_alt_win
[nop
] = true;
1999 curr_alt_match_win
[nop
] = false;
2000 curr_alt_offmemok
[nop
] = false;
2001 curr_alt_matches
[nop
] = -1;
2005 op
= no_subreg_reg_operand
[nop
];
2006 mode
= curr_operand_mode
[nop
];
2008 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2011 early_clobber_p
= false;
2012 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2014 this_costly_alternative
= this_alternative
= NO_REGS
;
2015 /* We update set of possible hard regs besides its class
2016 because reg class might be inaccurate. For example,
2017 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2018 is translated in HI_REGS because classes are merged by
2019 pairs and there is no accurate intermediate class. */
2020 CLEAR_HARD_REG_SET (this_alternative_set
);
2021 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2022 this_alternative_win
= false;
2023 this_alternative_match_win
= false;
2024 this_alternative_offmemok
= false;
2025 this_alternative_matches
= -1;
2027 /* An empty constraint should be excluded by the fast
2029 lra_assert (*p
!= 0 && *p
!= ',');
2032 /* Scan this alternative's specs for this operand; set WIN
2033 if the operand fits any letter in this alternative.
2034 Otherwise, clear BADOP if this operand could fit some
2035 letter after reloads, or set WINREG if this operand could
2036 fit after reloads provided the constraint allows some
2041 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2051 early_clobber_p
= true;
2055 op_reject
+= LRA_MAX_REJECT
;
2058 op_reject
+= LRA_LOSER_COST_FACTOR
;
2062 /* Ignore rest of this alternative. */
2066 case '0': case '1': case '2': case '3': case '4':
2067 case '5': case '6': case '7': case '8': case '9':
2072 m
= strtoul (p
, &end
, 10);
2075 lra_assert (nop
> m
);
2077 this_alternative_matches
= m
;
2078 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2079 /* We are supposed to match a previous operand.
2080 If we do, we win if that one did. If we do
2081 not, count both of the operands as losers.
2082 (This is too conservative, since most of the
2083 time only a single reload insn will be needed
2084 to make the two operands win. As a result,
2085 this alternative may be rejected when it is
2086 actually desirable.) */
2088 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2089 *curr_id
->operand_loc
[m
], m_hregno
))
2091 /* We should reject matching of an early
2092 clobber operand if the matching operand is
2093 not dying in the insn. */
2094 if (! curr_static_id
->operand
[m
].early_clobber
2095 || operand_reg
[nop
] == NULL_RTX
2096 || (find_regno_note (curr_insn
, REG_DEAD
,
2098 || REGNO (op
) == REGNO (operand_reg
[m
])))
2103 /* If we are matching a non-offsettable
2104 address where an offsettable address was
2105 expected, then we must reject this
2106 combination, because we can't reload
2108 if (curr_alt_offmemok
[m
]
2109 && MEM_P (*curr_id
->operand_loc
[m
])
2110 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2115 /* Operands don't match. Both operands must
2116 allow a reload register, otherwise we
2117 cannot make them match. */
2118 if (curr_alt
[m
] == NO_REGS
)
2120 /* Retroactively mark the operand we had to
2121 match as a loser, if it wasn't already and
2122 it wasn't matched to a register constraint
2123 (e.g it might be matched by memory). */
2125 && (operand_reg
[m
] == NULL_RTX
2126 || hard_regno
[m
] < 0))
2130 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2131 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2134 /* Prefer matching earlyclobber alternative as
2135 it results in less hard regs required for
2136 the insn than a non-matching earlyclobber
2138 if (curr_static_id
->operand
[m
].early_clobber
)
2140 if (lra_dump_file
!= NULL
)
2143 " %d Matching earlyclobber alt:"
2148 /* Otherwise we prefer no matching
2149 alternatives because it gives more freedom
2151 else if (operand_reg
[nop
] == NULL_RTX
2152 || (find_regno_note (curr_insn
, REG_DEAD
,
2153 REGNO (operand_reg
[nop
]))
2156 if (lra_dump_file
!= NULL
)
2159 " %d Matching alt: reject+=2\n",
2164 /* If we have to reload this operand and some
2165 previous operand also had to match the same
2166 thing as this operand, we don't know how to do
2168 if (!match_p
|| !curr_alt_win
[m
])
2170 for (i
= 0; i
< nop
; i
++)
2171 if (curr_alt_matches
[i
] == m
)
2179 /* This can be fixed with reloads if the operand
2180 we are supposed to match can be fixed with
2183 this_alternative
= curr_alt
[m
];
2184 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2185 winreg
= this_alternative
!= NO_REGS
;
2191 || general_constant_p (op
)
2192 || spilled_pseudo_p (op
))
2198 cn
= lookup_constraint (p
);
2199 switch (get_constraint_type (cn
))
2202 cl
= reg_class_for_constraint (cn
);
2208 if (CONST_INT_P (op
)
2209 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2215 && satisfies_memory_constraint_p (op
, cn
))
2217 else if (spilled_pseudo_p (op
))
2220 /* If we didn't already win, we can reload constants
2221 via force_const_mem or put the pseudo value into
2222 memory, or make other memory by reloading the
2223 address like for 'o'. */
2224 if (CONST_POOL_OK_P (mode
, op
)
2225 || MEM_P (op
) || REG_P (op
)
2226 /* We can restore the equiv insn by a
2228 || equiv_substition_p
[nop
])
2235 /* If we didn't already win, we can reload the address
2236 into a base register. */
2237 if (satisfies_address_constraint_p (op
, cn
))
2239 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2245 if (constraint_satisfied_p (op
, cn
))
2249 case CT_SPECIAL_MEMORY
:
2251 && satisfies_memory_constraint_p (op
, cn
))
2253 else if (spilled_pseudo_p (op
))
2260 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2261 IOR_HARD_REG_SET (this_alternative_set
,
2262 reg_class_contents
[cl
]);
2265 this_costly_alternative
2266 = reg_class_subunion
[this_costly_alternative
][cl
];
2267 IOR_HARD_REG_SET (this_costly_alternative_set
,
2268 reg_class_contents
[cl
]);
2270 if (mode
== BLKmode
)
2275 if (hard_regno
[nop
] >= 0
2276 && in_hard_reg_set_p (this_alternative_set
,
2277 mode
, hard_regno
[nop
]))
2279 else if (hard_regno
[nop
] < 0
2280 && in_class_p (op
, this_alternative
, NULL
))
2285 if (c
!= ' ' && c
!= '\t')
2286 costly_p
= c
== '*';
2288 while ((p
+= len
), c
);
2290 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2291 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2292 /* Record which operands fit this alternative. */
2295 this_alternative_win
= true;
2296 if (operand_reg
[nop
] != NULL_RTX
)
2298 if (hard_regno
[nop
] >= 0)
2300 if (in_hard_reg_set_p (this_costly_alternative_set
,
2301 mode
, hard_regno
[nop
]))
2303 if (lra_dump_file
!= NULL
)
2304 fprintf (lra_dump_file
,
2305 " %d Costly set: reject++\n",
2312 /* Prefer won reg to spilled pseudo under other
2313 equal conditions for possibe inheritance. */
2316 if (lra_dump_file
!= NULL
)
2319 " %d Non pseudo reload: reject++\n",
2323 if (in_class_p (operand_reg
[nop
],
2324 this_costly_alternative
, NULL
))
2326 if (lra_dump_file
!= NULL
)
2329 " %d Non pseudo costly reload:"
2335 /* We simulate the behavior of old reload here.
2336 Although scratches need hard registers and it
2337 might result in spilling other pseudos, no reload
2338 insns are generated for the scratches. So it
2339 might cost something but probably less than old
2340 reload pass believes. */
2343 if (lra_dump_file
!= NULL
)
2344 fprintf (lra_dump_file
,
2345 " %d Scratch win: reject+=2\n",
2352 this_alternative_match_win
= true;
2355 int const_to_mem
= 0;
2358 reject
+= op_reject
;
2359 /* Never do output reload of stack pointer. It makes
2360 impossible to do elimination when SP is changed in
2362 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2363 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2366 /* If this alternative asks for a specific reg class, see if there
2367 is at least one allocatable register in that class. */
2369 = (this_alternative
== NO_REGS
2370 || (hard_reg_set_subset_p
2371 (reg_class_contents
[this_alternative
],
2372 lra_no_alloc_regs
)));
2374 /* For asms, verify that the class for this alternative is possible
2375 for the mode that is specified. */
2376 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2379 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2380 if (HARD_REGNO_MODE_OK (i
, mode
)
2381 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2384 if (i
== FIRST_PSEUDO_REGISTER
)
2388 /* If this operand accepts a register, and if the
2389 register class has at least one allocatable register,
2390 then this operand can be reloaded. */
2391 if (winreg
&& !no_regs_p
)
2396 if (lra_dump_file
!= NULL
)
2397 fprintf (lra_dump_file
,
2398 " alt=%d: Bad operand -- refuse\n",
2403 if (this_alternative
!= NO_REGS
)
2405 HARD_REG_SET available_regs
;
2407 COPY_HARD_REG_SET (available_regs
,
2408 reg_class_contents
[this_alternative
]);
2409 AND_COMPL_HARD_REG_SET
2411 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2412 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2413 if (hard_reg_set_empty_p (available_regs
))
2415 /* There are no hard regs holding a value of given
2419 this_alternative
= NO_REGS
;
2420 if (lra_dump_file
!= NULL
)
2421 fprintf (lra_dump_file
,
2422 " %d Using memory because of"
2423 " a bad mode: reject+=2\n",
2429 if (lra_dump_file
!= NULL
)
2430 fprintf (lra_dump_file
,
2431 " alt=%d: Wrong mode -- refuse\n",
2438 /* If not assigned pseudo has a class which a subset of
2439 required reg class, it is a less costly alternative
2440 as the pseudo still can get a hard reg of necessary
2442 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2443 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2444 && ira_class_subset_p
[this_alternative
][cl
])
2446 if (lra_dump_file
!= NULL
)
2449 " %d Super set class reg: reject-=3\n", nop
);
2453 this_alternative_offmemok
= offmemok
;
2454 if (this_costly_alternative
!= NO_REGS
)
2456 if (lra_dump_file
!= NULL
)
2457 fprintf (lra_dump_file
,
2458 " %d Costly loser: reject++\n", nop
);
2461 /* If the operand is dying, has a matching constraint,
2462 and satisfies constraints of the matched operand
2463 which failed to satisfy the own constraints, most probably
2464 the reload for this operand will be gone. */
2465 if (this_alternative_matches
>= 0
2466 && !curr_alt_win
[this_alternative_matches
]
2468 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2469 && (hard_regno
[nop
] >= 0
2470 ? in_hard_reg_set_p (this_alternative_set
,
2471 mode
, hard_regno
[nop
])
2472 : in_class_p (op
, this_alternative
, NULL
)))
2474 if (lra_dump_file
!= NULL
)
2477 " %d Dying matched operand reload: reject++\n",
2483 /* Strict_low_part requires to reload the register
2484 not the sub-register. In this case we should
2485 check that a final reload hard reg can hold the
2487 if (curr_static_id
->operand
[nop
].strict_low
2489 && hard_regno
[nop
] < 0
2490 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2491 && ira_class_hard_regs_num
[this_alternative
] > 0
2492 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2493 [this_alternative
][0],
2495 (*curr_id
->operand_loc
[nop
])))
2497 if (lra_dump_file
!= NULL
)
2500 " alt=%d: Strict low subreg reload -- refuse\n",
2506 if (operand_reg
[nop
] != NULL_RTX
2507 /* Output operands and matched input operands are
2508 not inherited. The following conditions do not
2509 exactly describe the previous statement but they
2510 are pretty close. */
2511 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2512 && (this_alternative_matches
< 0
2513 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2515 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2519 /* The value of reload_sum has sense only if we
2520 process insns in their order. It happens only on
2521 the first constraints sub-pass when we do most of
2523 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2524 reload_sum
+= last_reload
- bb_reload_num
;
2526 /* If this is a constant that is reloaded into the
2527 desired class by copying it to memory first, count
2528 that as another reload. This is consistent with
2529 other code and is required to avoid choosing another
2530 alternative when the constant is moved into memory.
2531 Note that the test here is precisely the same as in
2532 the code below that calls force_const_mem. */
2533 if (CONST_POOL_OK_P (mode
, op
)
2534 && ((targetm
.preferred_reload_class
2535 (op
, this_alternative
) == NO_REGS
)
2536 || no_input_reloads_p
))
2543 /* Alternative loses if it requires a type of reload not
2544 permitted for this insn. We can always reload
2545 objects with a REG_UNUSED note. */
2546 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2547 && no_output_reloads_p
2548 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2549 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2550 && no_input_reloads_p
&& ! const_to_mem
)
2551 || (this_alternative_matches
>= 0
2552 && (no_input_reloads_p
2553 || (no_output_reloads_p
2554 && (curr_static_id
->operand
2555 [this_alternative_matches
].type
!= OP_IN
)
2556 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2557 no_subreg_reg_operand
2558 [this_alternative_matches
])))))
2560 if (lra_dump_file
!= NULL
)
2563 " alt=%d: No input/otput reload -- refuse\n",
2568 /* Alternative loses if it required class pseudo can not
2569 hold value of required mode. Such insns can be
2570 described by insn definitions with mode iterators. */
2571 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2572 && ! hard_reg_set_empty_p (this_alternative_set
)
2573 /* It is common practice for constraints to use a
2574 class which does not have actually enough regs to
2575 hold the value (e.g. x86 AREG for mode requiring
2576 more one general reg). Therefore we have 2
2577 conditions to check that the reload pseudo can
2578 not hold the mode value. */
2579 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2580 [this_alternative
][0],
2581 GET_MODE (*curr_id
->operand_loc
[nop
]))
2582 /* The above condition is not enough as the first
2583 reg in ira_class_hard_regs can be not aligned for
2584 multi-words mode values. */
2585 && (prohibited_class_reg_set_mode_p
2586 (this_alternative
, this_alternative_set
,
2587 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2589 if (lra_dump_file
!= NULL
)
2590 fprintf (lra_dump_file
,
2591 " alt=%d: reload pseudo for op %d "
2592 " can not hold the mode value -- refuse\n",
2597 /* Check strong discouragement of reload of non-constant
2598 into class THIS_ALTERNATIVE. */
2599 if (! CONSTANT_P (op
) && ! no_regs_p
2600 && (targetm
.preferred_reload_class
2601 (op
, this_alternative
) == NO_REGS
2602 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2603 && (targetm
.preferred_output_reload_class
2604 (op
, this_alternative
) == NO_REGS
))))
2606 if (lra_dump_file
!= NULL
)
2607 fprintf (lra_dump_file
,
2608 " %d Non-prefered reload: reject+=%d\n",
2609 nop
, LRA_MAX_REJECT
);
2610 reject
+= LRA_MAX_REJECT
;
2613 if (! (MEM_P (op
) && offmemok
)
2614 && ! (const_to_mem
&& constmemok
))
2616 /* We prefer to reload pseudos over reloading other
2617 things, since such reloads may be able to be
2618 eliminated later. So bump REJECT in other cases.
2619 Don't do this in the case where we are forcing a
2620 constant into memory and it will then win since
2621 we don't want to have a different alternative
2623 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2625 if (lra_dump_file
!= NULL
)
2628 " %d Non-pseudo reload: reject+=2\n",
2635 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2637 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2639 if (lra_dump_file
!= NULL
)
2642 " %d Small class reload: reject+=%d\n",
2643 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2644 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2648 /* We are trying to spill pseudo into memory. It is
2649 usually more costly than moving to a hard register
2650 although it might takes the same number of
2653 Non-pseudo spill may happen also. Suppose a target allows both
2654 register and memory in the operand constraint alternatives,
2655 then it's typical that an eliminable register has a substition
2656 of "base + offset" which can either be reloaded by a simple
2657 "new_reg <= base + offset" which will match the register
2658 constraint, or a similar reg addition followed by further spill
2659 to and reload from memory which will match the memory
2660 constraint, but this memory spill will be much more costly
2663 Code below increases the reject for both pseudo and non-pseudo
2666 && !(MEM_P (op
) && offmemok
)
2667 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2669 if (lra_dump_file
!= NULL
)
2672 " %d Spill %spseudo into memory: reject+=3\n",
2673 nop
, REG_P (op
) ? "" : "Non-");
2675 if (VECTOR_MODE_P (mode
))
2677 /* Spilling vectors into memory is usually more
2678 costly as they contain big values. */
2679 if (lra_dump_file
!= NULL
)
2682 " %d Spill vector pseudo: reject+=2\n",
2688 #ifdef SECONDARY_MEMORY_NEEDED
2689 /* If reload requires moving value through secondary
2690 memory, it will need one more insn at least. */
2691 if (this_alternative
!= NO_REGS
2692 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2693 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2694 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2696 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2697 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2701 /* Input reloads can be inherited more often than output
2702 reloads can be removed, so penalize output
2704 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2706 if (lra_dump_file
!= NULL
)
2709 " %d Non input pseudo reload: reject++\n",
2714 if (MEM_P (op
) && offmemok
)
2718 if (early_clobber_p
&& ! scratch_p
)
2720 if (lra_dump_file
!= NULL
)
2721 fprintf (lra_dump_file
,
2722 " %d Early clobber: reject++\n", nop
);
2725 /* ??? We check early clobbers after processing all operands
2726 (see loop below) and there we update the costs more.
2727 Should we update the cost (may be approximately) here
2728 because of early clobber register reloads or it is a rare
2729 or non-important thing to be worth to do it. */
2730 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2731 - (addr_losers
== losers
? static_reject
: 0));
2732 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2734 if (lra_dump_file
!= NULL
)
2735 fprintf (lra_dump_file
,
2736 " alt=%d,overall=%d,losers=%d -- refuse\n",
2737 nalt
, overall
, losers
);
2741 curr_alt
[nop
] = this_alternative
;
2742 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2743 curr_alt_win
[nop
] = this_alternative_win
;
2744 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2745 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2746 curr_alt_matches
[nop
] = this_alternative_matches
;
2748 if (this_alternative_matches
>= 0
2749 && !did_match
&& !this_alternative_win
)
2750 curr_alt_win
[this_alternative_matches
] = false;
2752 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2753 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2756 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2757 /* Prevent processing non-move insns. */
2758 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2759 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2760 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2761 && REG_P (no_subreg_reg_operand
[0])
2762 && REG_P (no_subreg_reg_operand
[1])
2763 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2764 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2765 || (! curr_alt_win
[0] && curr_alt_win
[1]
2766 && REG_P (no_subreg_reg_operand
[1])
2767 /* Check that we reload memory not the memory
2769 && !curr_alt_offmemok
[0]
2770 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2771 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2772 && REG_P (no_subreg_reg_operand
[0])
2773 /* Check that we reload memory not the memory
2775 && !curr_alt_offmemok
[1]
2776 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2777 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2778 no_subreg_reg_operand
[1])
2779 || (targetm
.preferred_reload_class
2780 (no_subreg_reg_operand
[1],
2781 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2782 /* If it is a result of recent elimination in move
2783 insn we can transform it into an add still by
2784 using this alternative. */
2785 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2787 /* We have a move insn and a new reload insn will be similar
2788 to the current insn. We should avoid such situation as it
2789 results in LRA cycling. */
2790 overall
+= LRA_MAX_REJECT
;
2793 curr_alt_dont_inherit_ops_num
= 0;
2794 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2796 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2797 HARD_REG_SET temp_set
;
2799 i
= early_clobbered_nops
[nop
];
2800 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2801 || hard_regno
[i
] < 0)
2803 lra_assert (operand_reg
[i
] != NULL_RTX
);
2804 clobbered_hard_regno
= hard_regno
[i
];
2805 CLEAR_HARD_REG_SET (temp_set
);
2806 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2807 first_conflict_j
= last_conflict_j
= -1;
2808 for (j
= 0; j
< n_operands
; j
++)
2810 /* We don't want process insides of match_operator and
2811 match_parallel because otherwise we would process
2812 their operands once again generating a wrong
2814 || curr_static_id
->operand
[j
].is_operator
)
2816 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2817 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2819 /* If we don't reload j-th operand, check conflicts. */
2820 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2821 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2823 if (first_conflict_j
< 0)
2824 first_conflict_j
= j
;
2825 last_conflict_j
= j
;
2827 if (last_conflict_j
< 0)
2829 /* If earlyclobber operand conflicts with another
2830 non-matching operand which is actually the same register
2831 as the earlyclobber operand, it is better to reload the
2832 another operand as an operand matching the earlyclobber
2833 operand can be also the same. */
2834 if (first_conflict_j
== last_conflict_j
2835 && operand_reg
[last_conflict_j
] != NULL_RTX
2836 && ! curr_alt_match_win
[last_conflict_j
]
2837 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2839 curr_alt_win
[last_conflict_j
] = false;
2840 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2843 /* Early clobber was already reflected in REJECT. */
2844 lra_assert (reject
> 0);
2845 if (lra_dump_file
!= NULL
)
2848 " %d Conflict early clobber reload: reject--\n",
2851 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2855 /* We need to reload early clobbered register and the
2856 matched registers. */
2857 for (j
= 0; j
< n_operands
; j
++)
2858 if (curr_alt_matches
[j
] == i
)
2860 curr_alt_match_win
[j
] = false;
2862 overall
+= LRA_LOSER_COST_FACTOR
;
2864 if (! curr_alt_match_win
[i
])
2865 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2868 /* Remember pseudos used for match reloads are never
2870 lra_assert (curr_alt_matches
[i
] >= 0);
2871 curr_alt_win
[curr_alt_matches
[i
]] = false;
2873 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2875 /* Early clobber was already reflected in REJECT. */
2876 lra_assert (reject
> 0);
2877 if (lra_dump_file
!= NULL
)
2880 " %d Matched conflict early clobber reloads: "
2884 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2887 if (lra_dump_file
!= NULL
)
2888 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2889 nalt
, overall
, losers
, reload_nregs
);
2891 /* If this alternative can be made to work by reloading, and it
2892 needs less reloading than the others checked so far, record
2893 it as the chosen goal for reloading. */
2894 if ((best_losers
!= 0 && losers
== 0)
2895 || (((best_losers
== 0 && losers
== 0)
2896 || (best_losers
!= 0 && losers
!= 0))
2897 && (best_overall
> overall
2898 || (best_overall
== overall
2899 /* If the cost of the reloads is the same,
2900 prefer alternative which requires minimal
2901 number of reload regs. */
2902 && (reload_nregs
< best_reload_nregs
2903 || (reload_nregs
== best_reload_nregs
2904 && (best_reload_sum
< reload_sum
2905 || (best_reload_sum
== reload_sum
2906 && nalt
< goal_alt_number
))))))))
2908 for (nop
= 0; nop
< n_operands
; nop
++)
2910 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2911 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2912 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2913 goal_alt
[nop
] = curr_alt
[nop
];
2914 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2916 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2917 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2918 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2919 goal_alt_swapped
= curr_swapped
;
2920 best_overall
= overall
;
2921 best_losers
= losers
;
2922 best_reload_nregs
= reload_nregs
;
2923 best_reload_sum
= reload_sum
;
2924 goal_alt_number
= nalt
;
2927 /* Everything is satisfied. Do not process alternatives
2936 /* Make reload base reg from address AD. */
2938 base_to_reg (struct address_info
*ad
)
2942 rtx new_inner
= NULL_RTX
;
2943 rtx new_reg
= NULL_RTX
;
2945 rtx_insn
*last_insn
= get_last_insn();
2947 lra_assert (ad
->disp
== ad
->disp_term
);
2948 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2949 get_index_code (ad
));
2950 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
2952 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2953 ad
->disp_term
== NULL
2956 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2958 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
2959 code
= recog_memoized (insn
);
2962 delete_insns_since (last_insn
);
2969 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2971 base_plus_disp_to_reg (struct address_info
*ad
)
2976 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2977 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2978 get_index_code (ad
));
2979 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2981 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2985 /* Make reload of index part of address AD. Return the new
2988 index_part_to_reg (struct address_info
*ad
)
2992 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2993 INDEX_REG_CLASS
, "index term");
2994 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2995 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2999 /* Return true if we can add a displacement to address AD, even if that
3000 makes the address invalid. The fix-up code requires any new address
3001 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3003 can_add_disp_p (struct address_info
*ad
)
3005 return (!ad
->autoinc_p
3006 && ad
->segment
== NULL
3007 && ad
->base
== ad
->base_term
3008 && ad
->disp
== ad
->disp_term
);
3011 /* Make equiv substitution in address AD. Return true if a substitution
3014 equiv_address_substitution (struct address_info
*ad
)
3016 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3017 HOST_WIDE_INT disp
, scale
;
3020 base_term
= strip_subreg (ad
->base_term
);
3021 if (base_term
== NULL
)
3022 base_reg
= new_base_reg
= NULL_RTX
;
3025 base_reg
= *base_term
;
3026 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3028 index_term
= strip_subreg (ad
->index_term
);
3029 if (index_term
== NULL
)
3030 index_reg
= new_index_reg
= NULL_RTX
;
3033 index_reg
= *index_term
;
3034 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3036 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3040 if (lra_dump_file
!= NULL
)
3042 fprintf (lra_dump_file
, "Changing address in insn %d ",
3043 INSN_UID (curr_insn
));
3044 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3046 if (base_reg
!= new_base_reg
)
3048 if (REG_P (new_base_reg
))
3050 *base_term
= new_base_reg
;
3053 else if (GET_CODE (new_base_reg
) == PLUS
3054 && REG_P (XEXP (new_base_reg
, 0))
3055 && CONST_INT_P (XEXP (new_base_reg
, 1))
3056 && can_add_disp_p (ad
))
3058 disp
+= INTVAL (XEXP (new_base_reg
, 1));
3059 *base_term
= XEXP (new_base_reg
, 0);
3062 if (ad
->base_term2
!= NULL
)
3063 *ad
->base_term2
= *ad
->base_term
;
3065 if (index_reg
!= new_index_reg
)
3067 if (REG_P (new_index_reg
))
3069 *index_term
= new_index_reg
;
3072 else if (GET_CODE (new_index_reg
) == PLUS
3073 && REG_P (XEXP (new_index_reg
, 0))
3074 && CONST_INT_P (XEXP (new_index_reg
, 1))
3075 && can_add_disp_p (ad
)
3076 && (scale
= get_index_scale (ad
)))
3078 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
3079 *index_term
= XEXP (new_index_reg
, 0);
3085 if (ad
->disp
!= NULL
)
3086 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3089 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3090 update_address (ad
);
3094 if (lra_dump_file
!= NULL
)
3097 fprintf (lra_dump_file
, " -- no change\n");
3100 fprintf (lra_dump_file
, " on equiv ");
3101 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3102 fprintf (lra_dump_file
, "\n");
3108 /* Major function to make reloads for an address in operand NOP or
3109 check its correctness (If CHECK_ONLY_P is true). The supported
3112 1) an address that existed before LRA started, at which point it
3113 must have been valid. These addresses are subject to elimination
3114 and may have become invalid due to the elimination offset being out
3117 2) an address created by forcing a constant to memory
3118 (force_const_to_mem). The initial form of these addresses might
3119 not be valid, and it is this function's job to make them valid.
3121 3) a frame address formed from a register and a (possibly zero)
3122 constant offset. As above, these addresses might not be valid and
3123 this function must make them so.
3125 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3126 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3127 address. Return true for any RTL change.
3129 The function is a helper function which does not produce all
3130 transformations (when CHECK_ONLY_P is false) which can be
3131 necessary. It does just basic steps. To do all necessary
3132 transformations use function process_address. */
3134 process_address_1 (int nop
, bool check_only_p
,
3135 rtx_insn
**before
, rtx_insn
**after
)
3137 struct address_info ad
;
3139 HOST_WIDE_INT scale
;
3140 rtx op
= *curr_id
->operand_loc
[nop
];
3141 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3142 enum constraint_num cn
= lookup_constraint (constraint
);
3143 bool change_p
= false;
3146 && GET_MODE (op
) == BLKmode
3147 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3150 if (insn_extra_address_constraint (cn
))
3151 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3152 /* Do not attempt to decompose arbitrary addresses generated by combine
3153 for asm operands with loose constraints, e.g 'X'. */
3155 && !(get_constraint_type (cn
) == CT_FIXED_FORM
3156 && constraint_satisfied_p (op
, cn
)))
3157 decompose_mem_address (&ad
, op
);
3158 else if (GET_CODE (op
) == SUBREG
3159 && MEM_P (SUBREG_REG (op
)))
3160 decompose_mem_address (&ad
, SUBREG_REG (op
));
3163 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3164 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3165 when INDEX_REG_CLASS is a single register class. */
3166 if (ad
.base_term
!= NULL
3167 && ad
.index_term
!= NULL
3168 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3169 && REG_P (*ad
.base_term
)
3170 && REG_P (*ad
.index_term
)
3171 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3172 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3174 std::swap (ad
.base
, ad
.index
);
3175 std::swap (ad
.base_term
, ad
.index_term
);
3178 change_p
= equiv_address_substitution (&ad
);
3179 if (ad
.base_term
!= NULL
3180 && (process_addr_reg
3181 (ad
.base_term
, check_only_p
, before
,
3183 && !(REG_P (*ad
.base_term
)
3184 && find_regno_note (curr_insn
, REG_DEAD
,
3185 REGNO (*ad
.base_term
)) != NULL_RTX
)
3187 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3188 get_index_code (&ad
)))))
3191 if (ad
.base_term2
!= NULL
)
3192 *ad
.base_term2
= *ad
.base_term
;
3194 if (ad
.index_term
!= NULL
3195 && process_addr_reg (ad
.index_term
, check_only_p
,
3196 before
, NULL
, INDEX_REG_CLASS
))
3199 /* Target hooks sometimes don't treat extra-constraint addresses as
3200 legitimate address_operands, so handle them specially. */
3201 if (insn_extra_address_constraint (cn
)
3202 && satisfies_address_constraint_p (&ad
, cn
))
3208 /* There are three cases where the shape of *AD.INNER may now be invalid:
3210 1) the original address was valid, but either elimination or
3211 equiv_address_substitution was applied and that made
3212 the address invalid.
3214 2) the address is an invalid symbolic address created by
3217 3) the address is a frame address with an invalid offset.
3219 4) the address is a frame address with an invalid base.
3221 All these cases involve a non-autoinc address, so there is no
3222 point revalidating other types. */
3223 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3226 /* Any index existed before LRA started, so we can assume that the
3227 presence and shape of the index is valid. */
3228 push_to_sequence (*before
);
3229 lra_assert (ad
.disp
== ad
.disp_term
);
3230 if (ad
.base
== NULL
)
3232 if (ad
.index
== NULL
)
3235 rtx_insn
*last
= get_last_insn ();
3237 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3239 rtx addr
= *ad
.inner
;
3241 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3244 /* addr => lo_sum (new_base, addr), case (2) above. */
3245 insn
= emit_insn (gen_rtx_SET
3247 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3248 code
= recog_memoized (insn
);
3251 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3252 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3254 /* Try to put lo_sum into register. */
3255 insn
= emit_insn (gen_rtx_SET
3257 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3258 code
= recog_memoized (insn
);
3261 *ad
.inner
= new_reg
;
3262 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3272 delete_insns_since (last
);
3277 /* addr => new_base, case (2) above. */
3278 lra_emit_move (new_reg
, addr
);
3280 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3282 insn
= NEXT_INSN (insn
))
3283 if (recog_memoized (insn
) < 0)
3285 if (insn
!= NULL_RTX
)
3287 /* Do nothing if we cannot generate right insns.
3288 This is analogous to reload pass behavior. */
3289 delete_insns_since (last
);
3293 *ad
.inner
= new_reg
;
3298 /* index * scale + disp => new base + index * scale,
3300 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3301 GET_CODE (*ad
.index
));
3303 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3304 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3305 lra_emit_move (new_reg
, *ad
.disp
);
3306 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3307 new_reg
, *ad
.index
);
3310 else if (ad
.index
== NULL
)
3315 rtx_insn
*insns
, *last_insn
;
3316 /* Try to reload base into register only if the base is invalid
3317 for the address but with valid offset, case (4) above. */
3319 new_reg
= base_to_reg (&ad
);
3321 /* base + disp => new base, cases (1) and (3) above. */
3322 /* Another option would be to reload the displacement into an
3323 index register. However, postreload has code to optimize
3324 address reloads that have the same base and different
3325 displacements, so reloading into an index register would
3326 not necessarily be a win. */
3327 if (new_reg
== NULL_RTX
)
3328 new_reg
= base_plus_disp_to_reg (&ad
);
3329 insns
= get_insns ();
3330 last_insn
= get_last_insn ();
3331 /* If we generated at least two insns, try last insn source as
3332 an address. If we succeed, we generate one less insn. */
3333 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3334 && GET_CODE (SET_SRC (set
)) == PLUS
3335 && REG_P (XEXP (SET_SRC (set
), 0))
3336 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3338 *ad
.inner
= SET_SRC (set
);
3339 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3341 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3342 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3343 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3344 get_index_code (&ad
));
3345 regno
= REGNO (*ad
.base_term
);
3346 if (regno
>= FIRST_PSEUDO_REGISTER
3347 && cl
!= lra_get_allocno_class (regno
))
3348 lra_change_class (regno
, cl
, " Change to", true);
3349 new_reg
= SET_SRC (set
);
3350 delete_insns_since (PREV_INSN (last_insn
));
3353 /* Try if target can split displacement into legitimite new disp
3354 and offset. If it's the case, we replace the last insn with
3355 insns for base + offset => new_reg and set new_reg + new disp
3357 last_insn
= get_last_insn ();
3358 if ((set
= single_set (last_insn
)) != NULL_RTX
3359 && GET_CODE (SET_SRC (set
)) == PLUS
3360 && REG_P (XEXP (SET_SRC (set
), 0))
3361 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3362 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3364 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3365 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3368 rtx_insn
*new_insns
;
3370 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3371 new_insns
= get_insns ();
3373 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3374 delete_insns_since (PREV_INSN (last_insn
));
3375 add_insn (new_insns
);
3376 insns
= get_insns ();
3381 *ad
.inner
= new_reg
;
3383 else if (ad
.disp_term
!= NULL
)
3385 /* base + scale * index + disp => new base + scale * index,
3387 new_reg
= base_plus_disp_to_reg (&ad
);
3388 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3389 new_reg
, *ad
.index
);
3391 else if ((scale
= get_index_scale (&ad
)) == 1)
3393 /* The last transformation to one reg will be made in
3394 curr_insn_transform function. */
3398 else if (scale
!= 0)
3400 /* base + scale * index => base + new_reg,
3402 Index part of address may become invalid. For example, we
3403 changed pseudo on the equivalent memory and a subreg of the
3404 pseudo onto the memory of different mode for which the scale is
3406 new_reg
= index_part_to_reg (&ad
);
3407 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3408 *ad
.base_term
, new_reg
);
3412 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3414 rtx addr
= *ad
.inner
;
3416 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3417 /* addr => new_base. */
3418 lra_emit_move (new_reg
, addr
);
3419 *ad
.inner
= new_reg
;
3421 *before
= get_insns ();
3426 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3427 Use process_address_1 as a helper function. Return true for any
3430 If CHECK_ONLY_P is true, just check address correctness. Return
3431 false if the address correct. */
3433 process_address (int nop
, bool check_only_p
,
3434 rtx_insn
**before
, rtx_insn
**after
)
3438 while (process_address_1 (nop
, check_only_p
, before
, after
))
3447 /* Emit insns to reload VALUE into a new register. VALUE is an
3448 auto-increment or auto-decrement RTX whose operand is a register or
3449 memory location; so reloading involves incrementing that location.
3450 IN is either identical to VALUE, or some cheaper place to reload
3451 value being incremented/decremented from.
3453 INC_AMOUNT is the number to increment or decrement by (always
3454 positive and ignored for POST_MODIFY/PRE_MODIFY).
3456 Return pseudo containing the result. */
3458 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3460 /* REG or MEM to be copied and incremented. */
3461 rtx incloc
= XEXP (value
, 0);
3462 /* Nonzero if increment after copying. */
3463 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3464 || GET_CODE (value
) == POST_MODIFY
);
3469 rtx real_in
= in
== value
? incloc
: in
;
3473 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3475 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3476 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3477 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3478 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3479 inc
= XEXP (XEXP (value
, 1), 1);
3483 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3484 inc_amount
= -inc_amount
;
3486 inc
= GEN_INT (inc_amount
);
3489 if (! post
&& REG_P (incloc
))
3492 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3495 if (real_in
!= result
)
3497 /* First copy the location to the result register. */
3498 lra_assert (REG_P (result
));
3499 emit_insn (gen_move_insn (result
, real_in
));
3502 /* We suppose that there are insns to add/sub with the constant
3503 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3504 old reload worked with this assumption. If the assumption
3505 becomes wrong, we should use approach in function
3506 base_plus_disp_to_reg. */
3509 /* See if we can directly increment INCLOC. */
3510 last
= get_last_insn ();
3511 add_insn
= emit_insn (plus_p
3512 ? gen_add2_insn (incloc
, inc
)
3513 : gen_sub2_insn (incloc
, inc
));
3515 code
= recog_memoized (add_insn
);
3518 if (! post
&& result
!= incloc
)
3519 emit_insn (gen_move_insn (result
, incloc
));
3522 delete_insns_since (last
);
3525 /* If couldn't do the increment directly, must increment in RESULT.
3526 The way we do this depends on whether this is pre- or
3527 post-increment. For pre-increment, copy INCLOC to the reload
3528 register, increment it there, then save back. */
3531 if (real_in
!= result
)
3532 emit_insn (gen_move_insn (result
, real_in
));
3534 emit_insn (gen_add2_insn (result
, inc
));
3536 emit_insn (gen_sub2_insn (result
, inc
));
3537 if (result
!= incloc
)
3538 emit_insn (gen_move_insn (incloc
, result
));
3544 Because this might be a jump insn or a compare, and because
3545 RESULT may not be available after the insn in an input
3546 reload, we must do the incrementing before the insn being
3549 We have already copied IN to RESULT. Increment the copy in
3550 RESULT, save that back, then decrement RESULT so it has
3551 the original value. */
3553 emit_insn (gen_add2_insn (result
, inc
));
3555 emit_insn (gen_sub2_insn (result
, inc
));
3556 emit_insn (gen_move_insn (incloc
, result
));
3557 /* Restore non-modified value for the result. We prefer this
3558 way because it does not require an additional hard
3562 if (CONST_INT_P (inc
))
3563 emit_insn (gen_add2_insn (result
,
3564 gen_int_mode (-INTVAL (inc
),
3565 GET_MODE (result
))));
3567 emit_insn (gen_sub2_insn (result
, inc
));
3570 emit_insn (gen_add2_insn (result
, inc
));
3575 /* Return true if the current move insn does not need processing as we
3576 already know that it satisfies its constraints. */
3578 simple_move_p (void)
3581 enum reg_class dclass
, sclass
;
3583 lra_assert (curr_insn_set
!= NULL_RTX
);
3584 dest
= SET_DEST (curr_insn_set
);
3585 src
= SET_SRC (curr_insn_set
);
3587 /* If the instruction has multiple sets we need to process it even if it
3588 is single_set. This can happen if one or more of the SETs are dead.
3590 if (multiple_sets (curr_insn
))
3593 return ((dclass
= get_op_class (dest
)) != NO_REGS
3594 && (sclass
= get_op_class (src
)) != NO_REGS
3595 /* The backend guarantees that register moves of cost 2
3596 never need reloads. */
3597 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3600 /* Swap operands NOP and NOP + 1. */
3602 swap_operands (int nop
)
3604 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3605 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3606 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3607 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3608 /* Swap the duplicates too. */
3609 lra_update_dup (curr_id
, nop
);
3610 lra_update_dup (curr_id
, nop
+ 1);
3613 /* Main entry point of the constraint code: search the body of the
3614 current insn to choose the best alternative. It is mimicking insn
3615 alternative cost calculation model of former reload pass. That is
3616 because machine descriptions were written to use this model. This
3617 model can be changed in future. Make commutative operand exchange
3620 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3621 constraints. Return true if any change happened during function
3624 If CHECK_ONLY_P is true then don't do any transformation. Just
3625 check that the insn satisfies all constraints. If the insn does
3626 not satisfy any constraint, return true. */
3628 curr_insn_transform (bool check_only_p
)
3635 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3636 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3637 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3638 rtx_insn
*before
, *after
;
3640 /* Flag that the insn has been changed through a transformation. */
3643 #ifdef SECONDARY_MEMORY_NEEDED
3646 int max_regno_before
;
3647 int reused_alternative_num
;
3649 curr_insn_set
= single_set (curr_insn
);
3650 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3653 no_input_reloads_p
= no_output_reloads_p
= false;
3654 goal_alt_number
= -1;
3655 change_p
= sec_mem_p
= false;
3656 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3657 reloads; neither are insns that SET cc0. Insns that use CC0 are
3658 not allowed to have any input reloads. */
3659 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3660 no_output_reloads_p
= true;
3662 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3663 no_input_reloads_p
= true;
3664 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3665 no_output_reloads_p
= true;
3667 n_operands
= curr_static_id
->n_operands
;
3668 n_alternatives
= curr_static_id
->n_alternatives
;
3670 /* Just return "no reloads" if insn has no operands with
3672 if (n_operands
== 0 || n_alternatives
== 0)
3675 max_regno_before
= max_reg_num ();
3677 for (i
= 0; i
< n_operands
; i
++)
3679 goal_alt_matched
[i
][0] = -1;
3680 goal_alt_matches
[i
] = -1;
3683 commutative
= curr_static_id
->commutative
;
3685 /* Now see what we need for pseudos that didn't get hard regs or got
3686 the wrong kind of hard reg. For this, we must consider all the
3687 operands together against the register constraints. */
3689 best_losers
= best_overall
= INT_MAX
;
3690 best_reload_sum
= 0;
3692 curr_swapped
= false;
3693 goal_alt_swapped
= false;
3696 /* Make equivalence substitution and memory subreg elimination
3697 before address processing because an address legitimacy can
3698 depend on memory mode. */
3699 for (i
= 0; i
< n_operands
; i
++)
3702 bool op_change_p
= false;
3704 if (curr_static_id
->operand
[i
].is_operator
)
3707 old
= op
= *curr_id
->operand_loc
[i
];
3708 if (GET_CODE (old
) == SUBREG
)
3709 old
= SUBREG_REG (old
);
3710 subst
= get_equiv_with_elimination (old
, curr_insn
);
3711 original_subreg_reg_mode
[i
] = VOIDmode
;
3712 equiv_substition_p
[i
] = false;
3715 equiv_substition_p
[i
] = true;
3716 subst
= copy_rtx (subst
);
3717 lra_assert (REG_P (old
));
3718 if (GET_CODE (op
) != SUBREG
)
3719 *curr_id
->operand_loc
[i
] = subst
;
3722 SUBREG_REG (op
) = subst
;
3723 if (GET_MODE (subst
) == VOIDmode
)
3724 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3726 if (lra_dump_file
!= NULL
)
3728 fprintf (lra_dump_file
,
3729 "Changing pseudo %d in operand %i of insn %u on equiv ",
3730 REGNO (old
), i
, INSN_UID (curr_insn
));
3731 dump_value_slim (lra_dump_file
, subst
, 1);
3732 fprintf (lra_dump_file
, "\n");
3734 op_change_p
= change_p
= true;
3736 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3739 lra_update_dup (curr_id
, i
);
3743 /* Reload address registers and displacements. We do it before
3744 finding an alternative because of memory constraints. */
3745 before
= after
= NULL
;
3746 for (i
= 0; i
< n_operands
; i
++)
3747 if (! curr_static_id
->operand
[i
].is_operator
3748 && process_address (i
, check_only_p
, &before
, &after
))
3753 lra_update_dup (curr_id
, i
);
3757 /* If we've changed the instruction then any alternative that
3758 we chose previously may no longer be valid. */
3759 lra_set_used_insn_alternative (curr_insn
, -1);
3761 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3762 && check_and_process_move (&change_p
, &sec_mem_p
))
3767 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3768 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3769 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3770 reused_alternative_num
, INSN_UID (curr_insn
));
3772 if (process_alt_operands (reused_alternative_num
))
3776 return ! alt_p
|| best_losers
!= 0;
3778 /* If insn is commutative (it's safe to exchange a certain pair of
3779 operands) then we need to try each alternative twice, the second
3780 time matching those two operands as if we had exchanged them. To
3781 do this, really exchange them in operands.
3783 If we have just tried the alternatives the second time, return
3784 operands to normal and drop through. */
3786 if (reused_alternative_num
< 0 && commutative
>= 0)
3788 curr_swapped
= !curr_swapped
;
3791 swap_operands (commutative
);
3795 swap_operands (commutative
);
3798 if (! alt_p
&& ! sec_mem_p
)
3800 /* No alternative works with reloads?? */
3801 if (INSN_CODE (curr_insn
) >= 0)
3802 fatal_insn ("unable to generate reloads for:", curr_insn
);
3803 error_for_asm (curr_insn
,
3804 "inconsistent operand constraints in an %<asm%>");
3805 /* Avoid further trouble with this insn. Don't generate use
3806 pattern here as we could use the insn SP offset. */
3807 lra_set_insn_deleted (curr_insn
);
3811 /* If the best alternative is with operands 1 and 2 swapped, swap
3812 them. Update the operand numbers of any reloads already
3815 if (goal_alt_swapped
)
3817 if (lra_dump_file
!= NULL
)
3818 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3819 INSN_UID (curr_insn
));
3821 /* Swap the duplicates too. */
3822 swap_operands (commutative
);
3826 #ifdef SECONDARY_MEMORY_NEEDED
3827 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3828 too conservatively. So we use the secondary memory only if there
3829 is no any alternative without reloads. */
3830 use_sec_mem_p
= false;
3832 use_sec_mem_p
= true;
3835 for (i
= 0; i
< n_operands
; i
++)
3836 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3838 use_sec_mem_p
= i
< n_operands
;
3843 int in
= -1, out
= -1;
3844 rtx new_reg
, src
, dest
, rld
;
3845 machine_mode sec_mode
, rld_mode
;
3847 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3848 dest
= SET_DEST (curr_insn_set
);
3849 src
= SET_SRC (curr_insn_set
);
3850 for (i
= 0; i
< n_operands
; i
++)
3851 if (*curr_id
->operand_loc
[i
] == dest
)
3853 else if (*curr_id
->operand_loc
[i
] == src
)
3855 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3856 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3857 out
= curr_static_id
->dup_num
[i
];
3858 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3859 in
= curr_static_id
->dup_num
[i
];
3860 lra_assert (out
>= 0 && in
>= 0
3861 && curr_static_id
->operand
[out
].type
== OP_OUT
3862 && curr_static_id
->operand
[in
].type
== OP_IN
);
3863 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3865 rld_mode
= GET_MODE (rld
);
3866 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3867 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3869 sec_mode
= rld_mode
;
3871 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3872 NO_REGS
, "secondary");
3873 /* If the mode is changed, it should be wider. */
3874 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3875 if (sec_mode
!= rld_mode
)
3877 /* If the target says specifically to use another mode for
3878 secondary memory moves we can not reuse the original
3880 after
= emit_spill_move (false, new_reg
, dest
);
3881 lra_process_new_insns (curr_insn
, NULL
, after
,
3882 "Inserting the sec. move");
3883 /* We may have non null BEFORE here (e.g. after address
3885 push_to_sequence (before
);
3886 before
= emit_spill_move (true, new_reg
, src
);
3888 before
= get_insns ();
3890 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3891 lra_set_insn_deleted (curr_insn
);
3893 else if (dest
== rld
)
3895 *curr_id
->operand_loc
[out
] = new_reg
;
3896 lra_update_dup (curr_id
, out
);
3897 after
= emit_spill_move (false, new_reg
, dest
);
3898 lra_process_new_insns (curr_insn
, NULL
, after
,
3899 "Inserting the sec. move");
3903 *curr_id
->operand_loc
[in
] = new_reg
;
3904 lra_update_dup (curr_id
, in
);
3905 /* See comments above. */
3906 push_to_sequence (before
);
3907 before
= emit_spill_move (true, new_reg
, src
);
3909 before
= get_insns ();
3911 lra_process_new_insns (curr_insn
, before
, NULL
,
3912 "Inserting the sec. move");
3914 lra_update_insn_regno_info (curr_insn
);
3919 lra_assert (goal_alt_number
>= 0);
3920 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3922 if (lra_dump_file
!= NULL
)
3926 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3927 goal_alt_number
, INSN_UID (curr_insn
));
3928 for (i
= 0; i
< n_operands
; i
++)
3930 p
= (curr_static_id
->operand_alternative
3931 [goal_alt_number
* n_operands
+ i
].constraint
);
3934 fprintf (lra_dump_file
, " (%d) ", i
);
3935 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3936 fputc (*p
, lra_dump_file
);
3938 if (INSN_CODE (curr_insn
) >= 0
3939 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3940 fprintf (lra_dump_file
, " {%s}", p
);
3941 if (curr_id
->sp_offset
!= 0)
3942 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3943 curr_id
->sp_offset
);
3944 fprintf (lra_dump_file
, "\n");
3947 /* Right now, for any pair of operands I and J that are required to
3948 match, with J < I, goal_alt_matches[I] is J. Add I to
3949 goal_alt_matched[J]. */
3951 for (i
= 0; i
< n_operands
; i
++)
3952 if ((j
= goal_alt_matches
[i
]) >= 0)
3954 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3956 /* We allow matching one output operand and several input
3959 || (curr_static_id
->operand
[j
].type
== OP_OUT
3960 && curr_static_id
->operand
[i
].type
== OP_IN
3961 && (curr_static_id
->operand
3962 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3963 goal_alt_matched
[j
][k
] = i
;
3964 goal_alt_matched
[j
][k
+ 1] = -1;
3967 for (i
= 0; i
< n_operands
; i
++)
3968 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3970 /* Any constants that aren't allowed and can't be reloaded into
3971 registers are here changed into memory references. */
3972 for (i
= 0; i
< n_operands
; i
++)
3973 if (goal_alt_win
[i
])
3976 enum reg_class new_class
;
3977 rtx reg
= *curr_id
->operand_loc
[i
];
3979 if (GET_CODE (reg
) == SUBREG
)
3980 reg
= SUBREG_REG (reg
);
3982 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3984 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3986 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3989 lra_change_class (regno
, new_class
, " Change to", true);
3995 const char *constraint
;
3997 rtx op
= *curr_id
->operand_loc
[i
];
3998 rtx subreg
= NULL_RTX
;
3999 machine_mode mode
= curr_operand_mode
[i
];
4001 if (GET_CODE (op
) == SUBREG
)
4004 op
= SUBREG_REG (op
);
4005 mode
= GET_MODE (op
);
4008 if (CONST_POOL_OK_P (mode
, op
)
4009 && ((targetm
.preferred_reload_class
4010 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4011 || no_input_reloads_p
))
4013 rtx tem
= force_const_mem (mode
, op
);
4016 if (subreg
!= NULL_RTX
)
4017 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4019 *curr_id
->operand_loc
[i
] = tem
;
4020 lra_update_dup (curr_id
, i
);
4021 process_address (i
, false, &before
, &after
);
4023 /* If the alternative accepts constant pool refs directly
4024 there will be no reload needed at all. */
4025 if (subreg
!= NULL_RTX
)
4027 /* Skip alternatives before the one requested. */
4028 constraint
= (curr_static_id
->operand_alternative
4029 [goal_alt_number
* n_operands
+ i
].constraint
);
4031 (c
= *constraint
) && c
!= ',' && c
!= '#';
4032 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4034 enum constraint_num cn
= lookup_constraint (constraint
);
4035 if ((insn_extra_memory_constraint (cn
)
4036 || insn_extra_special_memory_constraint (cn
))
4037 && satisfies_memory_constraint_p (tem
, cn
))
4040 if (c
== '\0' || c
== ',' || c
== '#')
4043 goal_alt_win
[i
] = true;
4049 for (i
= 0; i
< n_operands
; i
++)
4052 bool optional_p
= false;
4054 rtx op
= *curr_id
->operand_loc
[i
];
4056 if (goal_alt_win
[i
])
4058 if (goal_alt
[i
] == NO_REGS
4060 /* When we assign NO_REGS it means that we will not
4061 assign a hard register to the scratch pseudo by
4062 assigment pass and the scratch pseudo will be
4063 spilled. Spilled scratch pseudos are transformed
4064 back to scratches at the LRA end. */
4065 && lra_former_scratch_operand_p (curr_insn
, i
)
4066 && lra_former_scratch_p (REGNO (op
)))
4068 int regno
= REGNO (op
);
4069 lra_change_class (regno
, NO_REGS
, " Change to", true);
4070 if (lra_get_regno_hard_regno (regno
) >= 0)
4071 /* We don't have to mark all insn affected by the
4072 spilled pseudo as there is only one such insn, the
4074 reg_renumber
[regno
] = -1;
4075 lra_assert (bitmap_single_bit_set_p
4076 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4078 /* We can do an optional reload. If the pseudo got a hard
4079 reg, we might improve the code through inheritance. If
4080 it does not get a hard register we coalesce memory/memory
4081 moves later. Ignore move insns to avoid cycling. */
4083 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4084 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4085 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4086 && regno
< new_regno_start
4087 && ! lra_former_scratch_p (regno
)
4088 && reg_renumber
[regno
] < 0
4089 /* Check that the optional reload pseudo will be able to
4090 hold given mode value. */
4091 && ! (prohibited_class_reg_set_mode_p
4092 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4093 PSEUDO_REGNO_MODE (regno
)))
4094 && (curr_insn_set
== NULL_RTX
4095 || !((REG_P (SET_SRC (curr_insn_set
))
4096 || MEM_P (SET_SRC (curr_insn_set
))
4097 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4098 && (REG_P (SET_DEST (curr_insn_set
))
4099 || MEM_P (SET_DEST (curr_insn_set
))
4100 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4106 /* Operands that match previous ones have already been handled. */
4107 if (goal_alt_matches
[i
] >= 0)
4110 /* We should not have an operand with a non-offsettable address
4111 appearing where an offsettable address will do. It also may
4112 be a case when the address should be special in other words
4113 not a general one (e.g. it needs no index reg). */
4114 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4116 enum reg_class rclass
;
4117 rtx
*loc
= &XEXP (op
, 0);
4118 enum rtx_code code
= GET_CODE (*loc
);
4120 push_to_sequence (before
);
4121 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4123 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4124 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4125 /* This value does not matter for MODIFY. */
4126 GET_MODE_SIZE (GET_MODE (op
)));
4127 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4128 "offsetable address", &new_reg
))
4129 lra_emit_move (new_reg
, *loc
);
4130 before
= get_insns ();
4133 lra_update_dup (curr_id
, i
);
4135 else if (goal_alt_matched
[i
][0] == -1)
4139 int hard_regno
, byte
;
4140 enum op_type type
= curr_static_id
->operand
[i
].type
;
4142 loc
= curr_id
->operand_loc
[i
];
4143 mode
= curr_operand_mode
[i
];
4144 if (GET_CODE (*loc
) == SUBREG
)
4146 reg
= SUBREG_REG (*loc
);
4147 byte
= SUBREG_BYTE (*loc
);
4149 /* Strict_low_part requires reload the register not
4150 the sub-register. */
4151 && (curr_static_id
->operand
[i
].strict_low
4152 || (GET_MODE_SIZE (mode
)
4153 <= GET_MODE_SIZE (GET_MODE (reg
))
4155 = get_try_hard_regno (REGNO (reg
))) >= 0
4156 && (simplify_subreg_regno
4158 GET_MODE (reg
), byte
, mode
) < 0)
4159 && (goal_alt
[i
] == NO_REGS
4160 || (simplify_subreg_regno
4161 (ira_class_hard_regs
[goal_alt
[i
]][0],
4162 GET_MODE (reg
), byte
, mode
) >= 0)))))
4164 /* An OP_INOUT is required when reloading a subreg of a
4165 mode wider than a word to ensure that data beyond the
4166 word being reloaded is preserved. Also automatically
4167 ensure that strict_low_part reloads are made into
4168 OP_INOUT which should already be true from the backend
4171 && (curr_static_id
->operand
[i
].strict_low
4172 || (GET_MODE_SIZE (GET_MODE (reg
)) > UNITS_PER_WORD
4173 && (GET_MODE_SIZE (mode
)
4174 < GET_MODE_SIZE (GET_MODE (reg
))))))
4176 loc
= &SUBREG_REG (*loc
);
4177 mode
= GET_MODE (*loc
);
4181 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4182 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4185 push_to_sequence (before
);
4186 lra_emit_move (new_reg
, old
);
4187 before
= get_insns ();
4192 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4195 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4197 after
= get_insns ();
4201 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4202 if (goal_alt_dont_inherit_ops
[j
] == i
)
4204 lra_set_regno_unique_value (REGNO (new_reg
));
4207 lra_update_dup (curr_id
, i
);
4209 else if (curr_static_id
->operand
[i
].type
== OP_IN
4210 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4213 /* generate reloads for input and matched outputs. */
4214 match_inputs
[0] = i
;
4215 match_inputs
[1] = -1;
4216 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4217 goal_alt
[i
], &before
, &after
,
4218 curr_static_id
->operand_alternative
4219 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4222 else if (curr_static_id
->operand
[i
].type
== OP_OUT
4223 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4225 /* Generate reloads for output and matched inputs. */
4226 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4227 &after
, curr_static_id
->operand_alternative
4228 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4229 else if (curr_static_id
->operand
[i
].type
== OP_IN
4230 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4233 /* Generate reloads for matched inputs. */
4234 match_inputs
[0] = i
;
4235 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4236 match_inputs
[j
+ 1] = k
;
4237 match_inputs
[j
+ 1] = -1;
4238 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4242 /* We must generate code in any case when function
4243 process_alt_operands decides that it is possible. */
4246 /* Memorise processed outputs so that output remaining to be processed
4247 can avoid using the same register value (see match_reload). */
4248 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4250 outputs
[n_outputs
++] = i
;
4251 outputs
[n_outputs
] = -1;
4258 lra_assert (REG_P (reg
));
4259 regno
= REGNO (reg
);
4260 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4261 if (GET_CODE (op
) == SUBREG
)
4262 op
= SUBREG_REG (op
);
4263 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4264 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4265 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4266 if (lra_dump_file
!= NULL
)
4267 fprintf (lra_dump_file
,
4268 " Making reload reg %d for reg %d optional\n",
4272 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4273 || max_regno_before
!= max_reg_num ())
4277 lra_update_operator_dups (curr_id
);
4278 /* Something changes -- process the insn. */
4279 lra_update_insn_regno_info (curr_insn
);
4281 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4285 /* Return true if INSN satisfies all constraints. In other words, no
4286 reload insns are needed. */
4288 lra_constrain_insn (rtx_insn
*insn
)
4290 int saved_new_regno_start
= new_regno_start
;
4291 int saved_new_insn_uid_start
= new_insn_uid_start
;
4295 curr_id
= lra_get_insn_recog_data (curr_insn
);
4296 curr_static_id
= curr_id
->insn_static_data
;
4297 new_insn_uid_start
= get_max_uid ();
4298 new_regno_start
= max_reg_num ();
4299 change_p
= curr_insn_transform (true);
4300 new_regno_start
= saved_new_regno_start
;
4301 new_insn_uid_start
= saved_new_insn_uid_start
;
4305 /* Return true if X is in LIST. */
4307 in_list_p (rtx x
, rtx list
)
4309 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4310 if (XEXP (list
, 0) == x
)
4315 /* Return true if X contains an allocatable hard register (if
4316 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4318 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4324 code
= GET_CODE (x
);
4327 int regno
= REGNO (x
);
4328 HARD_REG_SET alloc_regs
;
4332 if (regno
>= FIRST_PSEUDO_REGISTER
)
4333 regno
= lra_get_regno_hard_regno (regno
);
4336 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4337 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4341 if (regno
< FIRST_PSEUDO_REGISTER
)
4345 return lra_get_regno_hard_regno (regno
) < 0;
4348 fmt
= GET_RTX_FORMAT (code
);
4349 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4353 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4356 else if (fmt
[i
] == 'E')
4358 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4359 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4366 /* Process all regs in location *LOC and change them on equivalent
4367 substitution. Return true if any change was done. */
4369 loc_equivalence_change_p (rtx
*loc
)
4371 rtx subst
, reg
, x
= *loc
;
4372 bool result
= false;
4373 enum rtx_code code
= GET_CODE (x
);
4379 reg
= SUBREG_REG (x
);
4380 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4381 && GET_MODE (subst
) == VOIDmode
)
4383 /* We cannot reload debug location. Simplify subreg here
4384 while we know the inner mode. */
4385 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4386 GET_MODE (reg
), SUBREG_BYTE (x
));
4390 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4396 /* Scan all the operand sub-expressions. */
4397 fmt
= GET_RTX_FORMAT (code
);
4398 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4401 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4402 else if (fmt
[i
] == 'E')
4403 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4405 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4410 /* Similar to loc_equivalence_change_p, but for use as
4411 simplify_replace_fn_rtx callback. DATA is insn for which the
4412 elimination is done. If it null we don't do the elimination. */
4414 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4419 rtx subst
= (data
== NULL
4420 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4427 /* Maximum number of generated reload insns per an insn. It is for
4428 preventing this pass cycling in a bug case. */
4429 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4431 /* The current iteration number of this LRA pass. */
4432 int lra_constraint_iter
;
4434 /* True if we substituted equiv which needs checking register
4435 allocation correctness because the equivalent value contains
4436 allocatable hard registers or when we restore multi-register
4438 bool lra_risky_transformations_p
;
4440 /* Return true if REGNO is referenced in more than one block. */
4442 multi_block_pseudo_p (int regno
)
4444 basic_block bb
= NULL
;
4448 if (regno
< FIRST_PSEUDO_REGISTER
)
4451 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4453 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4454 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4459 /* Return true if LIST contains a deleted insn. */
4461 contains_deleted_insn_p (rtx_insn_list
*list
)
4463 for (; list
!= NULL_RTX
; list
= list
->next ())
4464 if (NOTE_P (list
->insn ())
4465 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4470 /* Return true if X contains a pseudo dying in INSN. */
4472 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4479 return (insn
!= NULL_RTX
4480 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4481 code
= GET_CODE (x
);
4482 fmt
= GET_RTX_FORMAT (code
);
4483 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4487 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4490 else if (fmt
[i
] == 'E')
4492 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4493 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4500 /* Return true if INSN contains a dying pseudo in INSN right hand
4503 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4505 rtx set
= single_set (insn
);
4507 gcc_assert (set
!= NULL
);
4508 return dead_pseudo_p (SET_SRC (set
), insn
);
4511 /* Return true if any init insn of REGNO contains a dying pseudo in
4512 insn right hand side. */
4514 init_insn_rhs_dead_pseudo_p (int regno
)
4516 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4520 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4521 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4526 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4527 reverse only if we have one init insn with given REGNO as a
4530 reverse_equiv_p (int regno
)
4532 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4537 if (! INSN_P (insns
->insn ())
4538 || insns
->next () != NULL
)
4540 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4542 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4545 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4546 call this function only for non-reverse equivalence. */
4548 contains_reloaded_insn_p (int regno
)
4551 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4553 for (; list
!= NULL
; list
= list
->next ())
4554 if ((set
= single_set (list
->insn ())) == NULL_RTX
4555 || ! REG_P (SET_DEST (set
))
4556 || (int) REGNO (SET_DEST (set
)) != regno
)
4561 /* Entry function of LRA constraint pass. Return true if the
4562 constraint pass did change the code. */
4564 lra_constraints (bool first_p
)
4567 int i
, hard_regno
, new_insns_num
;
4568 unsigned int min_len
, new_min_len
, uid
;
4569 rtx set
, x
, reg
, dest_reg
;
4570 basic_block last_bb
;
4571 bitmap_head equiv_insn_bitmap
;
4574 lra_constraint_iter
++;
4575 if (lra_dump_file
!= NULL
)
4576 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4577 lra_constraint_iter
);
4579 if (pic_offset_table_rtx
4580 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4581 lra_risky_transformations_p
= true;
4583 /* On the first iteration we should check IRA assignment
4584 correctness. In rare cases, the assignments can be wrong as
4585 early clobbers operands are ignored in IRA. */
4586 lra_risky_transformations_p
= first_p
;
4587 new_insn_uid_start
= get_max_uid ();
4588 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4589 /* Mark used hard regs for target stack size calulations. */
4590 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4591 if (lra_reg_info
[i
].nrefs
!= 0
4592 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4596 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4597 for (j
= 0; j
< nregs
; j
++)
4598 df_set_regs_ever_live (hard_regno
+ j
, true);
4600 /* Do elimination before the equivalence processing as we can spill
4601 some pseudos during elimination. */
4602 lra_eliminate (false, first_p
);
4603 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4604 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4605 if (lra_reg_info
[i
].nrefs
!= 0)
4607 ira_reg_equiv
[i
].profitable_p
= true;
4608 reg
= regno_reg_rtx
[i
];
4609 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4611 bool pseudo_p
= contains_reg_p (x
, false, false);
4613 /* After RTL transformation, we can not guarantee that
4614 pseudo in the substitution was not reloaded which might
4615 make equivalence invalid. For example, in reverse
4622 the memory address register was reloaded before the 2nd
4624 if ((! first_p
&& pseudo_p
)
4625 /* We don't use DF for compilation speed sake. So it
4626 is problematic to update live info when we use an
4627 equivalence containing pseudos in more than one
4629 || (pseudo_p
&& multi_block_pseudo_p (i
))
4630 /* If an init insn was deleted for some reason, cancel
4631 the equiv. We could update the equiv insns after
4632 transformations including an equiv insn deletion
4633 but it is not worthy as such cases are extremely
4635 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4636 /* If it is not a reverse equivalence, we check that a
4637 pseudo in rhs of the init insn is not dying in the
4638 insn. Otherwise, the live info at the beginning of
4639 the corresponding BB might be wrong after we
4640 removed the insn. When the equiv can be a
4641 constant, the right hand side of the init insn can
4643 || (! reverse_equiv_p (i
)
4644 && (init_insn_rhs_dead_pseudo_p (i
)
4645 /* If we reloaded the pseudo in an equivalence
4646 init insn, we can not remove the equiv init
4647 insns and the init insns might write into
4648 const memory in this case. */
4649 || contains_reloaded_insn_p (i
)))
4650 /* Prevent access beyond equivalent memory for
4651 paradoxical subregs. */
4653 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4654 > GET_MODE_SIZE (GET_MODE (x
))))
4655 || (pic_offset_table_rtx
4656 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4657 && (targetm
.preferred_reload_class
4658 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4659 || contains_symbol_ref_p (x
))))
4660 ira_reg_equiv
[i
].defined_p
= false;
4661 if (contains_reg_p (x
, false, true))
4662 ira_reg_equiv
[i
].profitable_p
= false;
4663 if (get_equiv (reg
) != reg
)
4664 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4667 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4669 /* We should add all insns containing pseudos which should be
4670 substituted by their equivalences. */
4671 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4672 lra_push_insn_by_uid (uid
);
4673 min_len
= lra_insn_stack_length ();
4677 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4679 curr_insn
= lra_pop_insn ();
4681 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4682 if (curr_bb
!= last_bb
)
4685 bb_reload_num
= lra_curr_reload_num
;
4687 if (min_len
> new_min_len
)
4689 min_len
= new_min_len
;
4692 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4694 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4695 MAX_RELOAD_INSNS_NUMBER
);
4697 if (DEBUG_INSN_P (curr_insn
))
4699 /* We need to check equivalence in debug insn and change
4700 pseudo to the equivalent value if necessary. */
4701 curr_id
= lra_get_insn_recog_data (curr_insn
);
4702 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4704 rtx old
= *curr_id
->operand_loc
[0];
4705 *curr_id
->operand_loc
[0]
4706 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4707 loc_equivalence_callback
, curr_insn
);
4708 if (old
!= *curr_id
->operand_loc
[0])
4710 lra_update_insn_regno_info (curr_insn
);
4715 else if (INSN_P (curr_insn
))
4717 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4719 dest_reg
= SET_DEST (set
);
4720 /* The equivalence pseudo could be set up as SUBREG in a
4721 case when it is a call restore insn in a mode
4722 different from the pseudo mode. */
4723 if (GET_CODE (dest_reg
) == SUBREG
)
4724 dest_reg
= SUBREG_REG (dest_reg
);
4725 if ((REG_P (dest_reg
)
4726 && (x
= get_equiv (dest_reg
)) != dest_reg
4727 /* Remove insns which set up a pseudo whose value
4728 can not be changed. Such insns might be not in
4729 init_insns because we don't update equiv data
4730 during insn transformations.
4732 As an example, let suppose that a pseudo got
4733 hard register and on the 1st pass was not
4734 changed to equivalent constant. We generate an
4735 additional insn setting up the pseudo because of
4736 secondary memory movement. Then the pseudo is
4737 spilled and we use the equiv constant. In this
4738 case we should remove the additional insn and
4739 this insn is not init_insns list. */
4740 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4741 /* Check that this is actually an insn setting
4742 up the equivalence. */
4743 || in_list_p (curr_insn
,
4745 [REGNO (dest_reg
)].init_insns
)))
4746 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4747 && in_list_p (curr_insn
,
4749 [REGNO (SET_SRC (set
))].init_insns
)))
4751 /* This is equiv init insn of pseudo which did not get a
4752 hard register -- remove the insn. */
4753 if (lra_dump_file
!= NULL
)
4755 fprintf (lra_dump_file
,
4756 " Removing equiv init insn %i (freq=%d)\n",
4757 INSN_UID (curr_insn
),
4758 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4759 dump_insn_slim (lra_dump_file
, curr_insn
);
4761 if (contains_reg_p (x
, true, false))
4762 lra_risky_transformations_p
= true;
4763 lra_set_insn_deleted (curr_insn
);
4767 curr_id
= lra_get_insn_recog_data (curr_insn
);
4768 curr_static_id
= curr_id
->insn_static_data
;
4769 init_curr_insn_input_reloads ();
4770 init_curr_operand_mode ();
4771 if (curr_insn_transform (false))
4773 /* Check non-transformed insns too for equiv change as USE
4774 or CLOBBER don't need reloads but can contain pseudos
4775 being changed on their equivalences. */
4776 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4777 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4779 lra_update_insn_regno_info (curr_insn
);
4784 bitmap_clear (&equiv_insn_bitmap
);
4785 /* If we used a new hard regno, changed_p should be true because the
4786 hard reg is assigned to a new pseudo. */
4787 if (flag_checking
&& !changed_p
)
4789 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4790 if (lra_reg_info
[i
].nrefs
!= 0
4791 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4793 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4795 for (j
= 0; j
< nregs
; j
++)
4796 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4802 static void initiate_invariants (void);
4803 static void finish_invariants (void);
4805 /* Initiate the LRA constraint pass. It is done once per
4808 lra_constraints_init (void)
4810 initiate_invariants ();
4813 /* Finalize the LRA constraint pass. It is done once per
4816 lra_constraints_finish (void)
4818 finish_invariants ();
4823 /* Structure describes invariants for ineheritance. */
4824 struct lra_invariant
4826 /* The order number of the invariant. */
4828 /* The invariant RTX. */
4830 /* The origin insn of the invariant. */
4834 typedef lra_invariant invariant_t
;
4835 typedef invariant_t
*invariant_ptr_t
;
4836 typedef const invariant_t
*const_invariant_ptr_t
;
4838 /* Pointer to the inheritance invariants. */
4839 static vec
<invariant_ptr_t
> invariants
;
4841 /* Allocation pool for the invariants. */
4842 static object_allocator
<lra_invariant
> *invariants_pool
;
4844 /* Hash table for the invariants. */
4845 static htab_t invariant_table
;
4847 /* Hash function for INVARIANT. */
4849 invariant_hash (const void *invariant
)
4851 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4852 return lra_rtx_hash (inv
);
4855 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4857 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4859 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4860 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4862 return rtx_equal_p (inv1
, inv2
);
4865 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4866 invariant which is in the table. */
4867 static invariant_ptr_t
4868 insert_invariant (rtx invariant_rtx
)
4871 invariant_t invariant
;
4872 invariant_ptr_t invariant_ptr
;
4874 invariant
.invariant_rtx
= invariant_rtx
;
4875 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4876 if (*entry_ptr
== NULL
)
4878 invariant_ptr
= invariants_pool
->allocate ();
4879 invariant_ptr
->invariant_rtx
= invariant_rtx
;
4880 invariant_ptr
->insn
= NULL
;
4881 invariants
.safe_push (invariant_ptr
);
4882 *entry_ptr
= (void *) invariant_ptr
;
4884 return (invariant_ptr_t
) *entry_ptr
;
4887 /* Initiate the invariant table. */
4889 initiate_invariants (void)
4891 invariants
.create (100);
4893 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
4894 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
4897 /* Finish the invariant table. */
4899 finish_invariants (void)
4901 htab_delete (invariant_table
);
4902 delete invariants_pool
;
4903 invariants
.release ();
4906 /* Make the invariant table empty. */
4908 clear_invariants (void)
4910 htab_empty (invariant_table
);
4911 invariants_pool
->release ();
4912 invariants
.truncate (0);
4917 /* This page contains code to do inheritance/split
4920 /* Number of reloads passed so far in current EBB. */
4921 static int reloads_num
;
4923 /* Number of calls passed so far in current EBB. */
4924 static int calls_num
;
4926 /* Current reload pseudo check for validity of elements in
4928 static int curr_usage_insns_check
;
4930 /* Info about last usage of registers in EBB to do inheritance/split
4931 transformation. Inheritance transformation is done from a spilled
4932 pseudo and split transformations from a hard register or a pseudo
4933 assigned to a hard register. */
4936 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4937 value INSNS is valid. The insns is chain of optional debug insns
4938 and a finishing non-debug insn using the corresponding reg. The
4939 value is also used to mark the registers which are set up in the
4940 current insn. The negated insn uid is used for this. */
4942 /* Value of global reloads_num at the last insn in INSNS. */
4944 /* Value of global reloads_nums at the last insn in INSNS. */
4946 /* It can be true only for splitting. And it means that the restore
4947 insn should be put after insn given by the following member. */
4949 /* Next insns in the current EBB which use the original reg and the
4950 original reg value is not changed between the current insn and
4951 the next insns. In order words, e.g. for inheritance, if we need
4952 to use the original reg value again in the next insns we can try
4953 to use the value in a hard register from a reload insn of the
4958 /* Map: regno -> corresponding pseudo usage insns. */
4959 static struct usage_insns
*usage_insns
;
4962 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4964 usage_insns
[regno
].check
= curr_usage_insns_check
;
4965 usage_insns
[regno
].insns
= insn
;
4966 usage_insns
[regno
].reloads_num
= reloads_num
;
4967 usage_insns
[regno
].calls_num
= calls_num
;
4968 usage_insns
[regno
].after_p
= after_p
;
4971 /* The function is used to form list REGNO usages which consists of
4972 optional debug insns finished by a non-debug insn using REGNO.
4973 RELOADS_NUM is current number of reload insns processed so far. */
4975 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
4977 rtx next_usage_insns
;
4979 if (usage_insns
[regno
].check
== curr_usage_insns_check
4980 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4981 && DEBUG_INSN_P (insn
))
4983 /* Check that we did not add the debug insn yet. */
4984 if (next_usage_insns
!= insn
4985 && (GET_CODE (next_usage_insns
) != INSN_LIST
4986 || XEXP (next_usage_insns
, 0) != insn
))
4987 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4990 else if (NONDEBUG_INSN_P (insn
))
4991 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4993 usage_insns
[regno
].check
= 0;
4996 /* Return first non-debug insn in list USAGE_INSNS. */
4998 skip_usage_debug_insns (rtx usage_insns
)
5002 /* Skip debug insns. */
5003 for (insn
= usage_insns
;
5004 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5005 insn
= XEXP (insn
, 1))
5007 return safe_as_a
<rtx_insn
*> (insn
);
5010 /* Return true if we need secondary memory moves for insn in
5011 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5014 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5015 rtx usage_insns ATTRIBUTE_UNUSED
)
5017 #ifndef SECONDARY_MEMORY_NEEDED
5024 if (inher_cl
== ALL_REGS
5025 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5027 lra_assert (INSN_P (insn
));
5028 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5030 dest
= SET_DEST (set
);
5033 lra_assert (inher_cl
!= NO_REGS
);
5034 cl
= get_reg_class (REGNO (dest
));
5035 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5036 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
5040 /* Registers involved in inheritance/split in the current EBB
5041 (inheritance/split pseudos and original registers). */
5042 static bitmap_head check_only_regs
;
5044 /* Reload pseudos can not be involded in invariant inheritance in the
5046 static bitmap_head invalid_invariant_regs
;
5048 /* Do inheritance transformations for insn INSN, which defines (if
5049 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5050 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5051 form as the "insns" field of usage_insns. Return true if we
5052 succeed in such transformation.
5054 The transformations look like:
5057 ... p <- i (new insn)
5059 <- ... p ... <- ... i ...
5061 ... i <- p (new insn)
5062 <- ... p ... <- ... i ...
5064 <- ... p ... <- ... i ...
5065 where p is a spilled original pseudo and i is a new inheritance pseudo.
5068 The inheritance pseudo has the smallest class of two classes CL and
5069 class of ORIGINAL REGNO. */
5071 inherit_reload_reg (bool def_p
, int original_regno
,
5072 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5074 if (optimize_function_for_size_p (cfun
))
5077 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5078 rtx original_reg
= regno_reg_rtx
[original_regno
];
5079 rtx new_reg
, usage_insn
;
5080 rtx_insn
*new_insns
;
5082 lra_assert (! usage_insns
[original_regno
].after_p
);
5083 if (lra_dump_file
!= NULL
)
5084 fprintf (lra_dump_file
,
5085 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5086 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5088 if (lra_dump_file
!= NULL
)
5090 fprintf (lra_dump_file
,
5091 " Rejecting inheritance for %d "
5092 "because of disjoint classes %s and %s\n",
5093 original_regno
, reg_class_names
[cl
],
5094 reg_class_names
[rclass
]);
5095 fprintf (lra_dump_file
,
5096 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5100 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5101 /* We don't use a subset of two classes because it can be
5102 NO_REGS. This transformation is still profitable in most
5103 cases even if the classes are not intersected as register
5104 move is probably cheaper than a memory load. */
5105 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5107 if (lra_dump_file
!= NULL
)
5108 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5109 reg_class_names
[cl
], reg_class_names
[rclass
]);
5113 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5115 /* Reject inheritance resulting in secondary memory moves.
5116 Otherwise, there is a danger in LRA cycling. Also such
5117 transformation will be unprofitable. */
5118 if (lra_dump_file
!= NULL
)
5120 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5121 rtx set
= single_set (insn
);
5123 lra_assert (set
!= NULL_RTX
);
5125 rtx dest
= SET_DEST (set
);
5127 lra_assert (REG_P (dest
));
5128 fprintf (lra_dump_file
,
5129 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5130 "as secondary mem is needed\n",
5131 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5132 original_regno
, reg_class_names
[rclass
]);
5133 fprintf (lra_dump_file
,
5134 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5138 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5139 rclass
, "inheritance");
5142 lra_emit_move (original_reg
, new_reg
);
5144 lra_emit_move (new_reg
, original_reg
);
5145 new_insns
= get_insns ();
5147 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5149 if (lra_dump_file
!= NULL
)
5151 fprintf (lra_dump_file
,
5152 " Rejecting inheritance %d->%d "
5153 "as it results in 2 or more insns:\n",
5154 original_regno
, REGNO (new_reg
));
5155 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5156 fprintf (lra_dump_file
,
5157 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5161 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5162 lra_update_insn_regno_info (insn
);
5164 /* We now have a new usage insn for original regno. */
5165 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5166 if (lra_dump_file
!= NULL
)
5167 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5168 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5169 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5170 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5171 bitmap_set_bit (&check_only_regs
, original_regno
);
5172 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5174 lra_process_new_insns (insn
, NULL
, new_insns
,
5175 "Add original<-inheritance");
5177 lra_process_new_insns (insn
, new_insns
, NULL
,
5178 "Add inheritance<-original");
5179 while (next_usage_insns
!= NULL_RTX
)
5181 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5183 usage_insn
= next_usage_insns
;
5184 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5185 next_usage_insns
= NULL
;
5189 usage_insn
= XEXP (next_usage_insns
, 0);
5190 lra_assert (DEBUG_INSN_P (usage_insn
));
5191 next_usage_insns
= XEXP (next_usage_insns
, 1);
5193 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5194 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5195 if (lra_dump_file
!= NULL
)
5197 fprintf (lra_dump_file
,
5198 " Inheritance reuse change %d->%d (bb%d):\n",
5199 original_regno
, REGNO (new_reg
),
5200 BLOCK_FOR_INSN (usage_insn
)->index
);
5201 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5204 if (lra_dump_file
!= NULL
)
5205 fprintf (lra_dump_file
,
5206 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5210 /* Return true if we need a caller save/restore for pseudo REGNO which
5211 was assigned to a hard register. */
5213 need_for_call_save_p (int regno
)
5215 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5216 return (usage_insns
[regno
].calls_num
< calls_num
5217 && (overlaps_hard_reg_set_p
5219 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5220 ? lra_reg_info
[regno
].actual_call_used_reg_set
5221 : call_used_reg_set
,
5222 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5223 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
5224 PSEUDO_REGNO_MODE (regno
))));
5227 /* Global registers occurring in the current EBB. */
5228 static bitmap_head ebb_global_regs
;
5230 /* Return true if we need a split for hard register REGNO or pseudo
5231 REGNO which was assigned to a hard register.
5232 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5233 used for reloads since the EBB end. It is an approximation of the
5234 used hard registers in the split range. The exact value would
5235 require expensive calculations. If we were aggressive with
5236 splitting because of the approximation, the split pseudo will save
5237 the same hard register assignment and will be removed in the undo
5238 pass. We still need the approximation because too aggressive
5239 splitting would result in too inaccurate cost calculation in the
5240 assignment pass because of too many generated moves which will be
5241 probably removed in the undo pass. */
5243 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5245 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5247 lra_assert (hard_regno
>= 0);
5248 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5249 /* Don't split eliminable hard registers, otherwise we can
5250 split hard registers like hard frame pointer, which
5251 lives on BB start/end according to DF-infrastructure,
5252 when there is a pseudo assigned to the register and
5253 living in the same BB. */
5254 && (regno
>= FIRST_PSEUDO_REGISTER
5255 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5256 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5257 /* Don't split call clobbered hard regs living through
5258 calls, otherwise we might have a check problem in the
5259 assign sub-pass as in the most cases (exception is a
5260 situation when lra_risky_transformations_p value is
5261 true) the assign pass assumes that all pseudos living
5262 through calls are assigned to call saved hard regs. */
5263 && (regno
>= FIRST_PSEUDO_REGISTER
5264 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5265 || usage_insns
[regno
].calls_num
== calls_num
)
5266 /* We need at least 2 reloads to make pseudo splitting
5267 profitable. We should provide hard regno splitting in
5268 any case to solve 1st insn scheduling problem when
5269 moving hard register definition up might result in
5270 impossibility to find hard register for reload pseudo of
5271 small register class. */
5272 && (usage_insns
[regno
].reloads_num
5273 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5274 && (regno
< FIRST_PSEUDO_REGISTER
5275 /* For short living pseudos, spilling + inheritance can
5276 be considered a substitution for splitting.
5277 Therefore we do not splitting for local pseudos. It
5278 decreases also aggressiveness of splitting. The
5279 minimal number of references is chosen taking into
5280 account that for 2 references splitting has no sense
5281 as we can just spill the pseudo. */
5282 || (regno
>= FIRST_PSEUDO_REGISTER
5283 && lra_reg_info
[regno
].nrefs
> 3
5284 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5285 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5288 /* Return class for the split pseudo created from original pseudo with
5289 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5290 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5291 results in no secondary memory movements. */
5292 static enum reg_class
5293 choose_split_class (enum reg_class allocno_class
,
5294 int hard_regno ATTRIBUTE_UNUSED
,
5295 machine_mode mode ATTRIBUTE_UNUSED
)
5297 #ifndef SECONDARY_MEMORY_NEEDED
5298 return allocno_class
;
5301 enum reg_class cl
, best_cl
= NO_REGS
;
5302 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5303 = REGNO_REG_CLASS (hard_regno
);
5305 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
5306 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5307 return allocno_class
;
5309 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5311 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
5312 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
5313 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5314 && (best_cl
== NO_REGS
5315 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5321 /* Do split transformations for insn INSN, which defines or uses
5322 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5323 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5324 "insns" field of usage_insns.
5326 The transformations look like:
5329 ... s <- p (new insn -- save)
5331 ... p <- s (new insn -- restore)
5332 <- ... p ... <- ... p ...
5334 <- ... p ... <- ... p ...
5335 ... s <- p (new insn -- save)
5337 ... p <- s (new insn -- restore)
5338 <- ... p ... <- ... p ...
5340 where p is an original pseudo got a hard register or a hard
5341 register and s is a new split pseudo. The save is put before INSN
5342 if BEFORE_P is true. Return true if we succeed in such
5345 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5346 rtx next_usage_insns
)
5348 enum reg_class rclass
;
5350 int hard_regno
, nregs
;
5351 rtx new_reg
, usage_insn
;
5352 rtx_insn
*restore
, *save
;
5357 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5359 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5360 hard_regno
= original_regno
;
5361 call_save_p
= false;
5363 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5364 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5365 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5366 as part of a multi-word register. In that case, or if the biggest
5367 mode was larger than a register, just use the reg_rtx. Otherwise,
5368 limit the size to that of the biggest access in the function. */
5369 if (mode
== VOIDmode
5370 || GET_MODE_SIZE (mode
) > GET_MODE_SIZE (reg_rtx_mode
))
5372 original_reg
= regno_reg_rtx
[hard_regno
];
5373 mode
= reg_rtx_mode
;
5376 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5380 mode
= PSEUDO_REGNO_MODE (original_regno
);
5381 hard_regno
= reg_renumber
[original_regno
];
5382 nregs
= hard_regno_nregs
[hard_regno
][mode
];
5383 rclass
= lra_get_allocno_class (original_regno
);
5384 original_reg
= regno_reg_rtx
[original_regno
];
5385 call_save_p
= need_for_call_save_p (original_regno
);
5387 lra_assert (hard_regno
>= 0);
5388 if (lra_dump_file
!= NULL
)
5389 fprintf (lra_dump_file
,
5390 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5394 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5395 hard_regno_nregs
[hard_regno
][mode
],
5397 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5401 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5402 if (rclass
== NO_REGS
)
5404 if (lra_dump_file
!= NULL
)
5406 fprintf (lra_dump_file
,
5407 " Rejecting split of %d(%s): "
5408 "no good reg class for %d(%s)\n",
5410 reg_class_names
[lra_get_allocno_class (original_regno
)],
5412 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5415 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5419 /* Split_if_necessary can split hard registers used as part of a
5420 multi-register mode but splits each register individually. The
5421 mode used for each independent register may not be supported
5422 so reject the split. Splitting the wider mode should theoretically
5423 be possible but is not implemented. */
5424 if (! HARD_REGNO_MODE_OK (hard_regno
, mode
))
5426 if (lra_dump_file
!= NULL
)
5428 fprintf (lra_dump_file
,
5429 " Rejecting split of %d(%s): unsuitable mode %s\n",
5431 reg_class_names
[lra_get_allocno_class (original_regno
)],
5432 GET_MODE_NAME (mode
));
5435 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5439 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5440 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5442 save
= emit_spill_move (true, new_reg
, original_reg
);
5443 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5445 if (lra_dump_file
!= NULL
)
5449 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5450 original_regno
, REGNO (new_reg
));
5451 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5452 fprintf (lra_dump_file
,
5453 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5457 restore
= emit_spill_move (false, new_reg
, original_reg
);
5458 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5460 if (lra_dump_file
!= NULL
)
5462 fprintf (lra_dump_file
,
5463 " Rejecting split %d->%d "
5464 "resulting in > 2 restore insns:\n",
5465 original_regno
, REGNO (new_reg
));
5466 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5467 fprintf (lra_dump_file
,
5468 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5472 after_p
= usage_insns
[original_regno
].after_p
;
5473 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5474 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5475 bitmap_set_bit (&check_only_regs
, original_regno
);
5476 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
5479 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5481 usage_insn
= next_usage_insns
;
5484 usage_insn
= XEXP (next_usage_insns
, 0);
5485 lra_assert (DEBUG_INSN_P (usage_insn
));
5486 next_usage_insns
= XEXP (next_usage_insns
, 1);
5487 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5488 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5489 if (lra_dump_file
!= NULL
)
5491 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5492 original_regno
, REGNO (new_reg
));
5493 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5496 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5497 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5498 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5499 after_p
? NULL
: restore
,
5500 after_p
? restore
: NULL
,
5502 ? "Add reg<-save" : "Add reg<-split");
5503 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5504 before_p
? NULL
: save
,
5506 ? "Add save<-reg" : "Add split<-reg");
5508 /* If we are trying to split multi-register. We should check
5509 conflicts on the next assignment sub-pass. IRA can allocate on
5510 sub-register levels, LRA do this on pseudos level right now and
5511 this discrepancy may create allocation conflicts after
5513 lra_risky_transformations_p
= true;
5514 if (lra_dump_file
!= NULL
)
5515 fprintf (lra_dump_file
,
5516 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5520 /* Recognize that we need a split transformation for insn INSN, which
5521 defines or uses REGNO in its insn biggest MODE (we use it only if
5522 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5523 hard registers which might be used for reloads since the EBB end.
5524 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5525 uid before starting INSN processing. Return true if we succeed in
5526 such transformation. */
5528 split_if_necessary (int regno
, machine_mode mode
,
5529 HARD_REG_SET potential_reload_hard_regs
,
5530 bool before_p
, rtx_insn
*insn
, int max_uid
)
5534 rtx next_usage_insns
;
5536 if (regno
< FIRST_PSEUDO_REGISTER
)
5537 nregs
= hard_regno_nregs
[regno
][mode
];
5538 for (i
= 0; i
< nregs
; i
++)
5539 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5540 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5541 /* To avoid processing the register twice or more. */
5542 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5543 && INSN_UID (next_usage_insns
) < max_uid
)
5544 || (GET_CODE (next_usage_insns
) == INSN_LIST
5545 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5546 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5547 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5552 /* Return TRUE if rtx X is considered as an invariant for
5555 invariant_p (const_rtx x
)
5562 code
= GET_CODE (x
);
5563 mode
= GET_MODE (x
);
5567 code
= GET_CODE (x
);
5568 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
5569 mode
= GET_MODE (x
);
5577 int i
, nregs
, regno
= REGNO (x
);
5579 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5580 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5581 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5583 nregs
= hard_regno_nregs
[regno
][mode
];
5584 for (i
= 0; i
< nregs
; i
++)
5585 if (! fixed_regs
[regno
+ i
]
5586 /* A hard register may be clobbered in the current insn
5587 but we can ignore this case because if the hard
5588 register is used it should be set somewhere after the
5590 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5593 fmt
= GET_RTX_FORMAT (code
);
5594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5598 if (! invariant_p (XEXP (x
, i
)))
5601 else if (fmt
[i
] == 'E')
5603 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5604 if (! invariant_p (XVECEXP (x
, i
, j
)))
5611 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5612 inheritance transformation (using dest_reg instead invariant in a
5613 subsequent insn). */
5615 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5617 invariant_ptr_t invariant_ptr
;
5618 rtx_insn
*insn
, *new_insns
;
5619 rtx insn_set
, insn_reg
, new_reg
;
5621 bool succ_p
= false;
5622 int dst_regno
= REGNO (dst_reg
);
5623 enum machine_mode dst_mode
= GET_MODE (dst_reg
);
5624 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5626 invariant_ptr
= insert_invariant (invariant_rtx
);
5627 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5629 /* We have a subsequent insn using the invariant. */
5630 insn_set
= single_set (insn
);
5631 lra_assert (insn_set
!= NULL
);
5632 insn_reg
= SET_DEST (insn_set
);
5633 lra_assert (REG_P (insn_reg
));
5634 insn_regno
= REGNO (insn_reg
);
5635 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5637 if (dst_mode
== GET_MODE (insn_reg
)
5638 /* We should consider only result move reg insns which are
5640 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5641 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5643 if (lra_dump_file
!= NULL
)
5644 fprintf (lra_dump_file
,
5645 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5646 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5647 cl
, "invariant inheritance");
5648 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5649 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5650 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5652 lra_emit_move (new_reg
, dst_reg
);
5653 new_insns
= get_insns ();
5655 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5656 "Add invariant inheritance<-original");
5658 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5659 new_insns
= get_insns ();
5661 lra_process_new_insns (insn
, NULL
, new_insns
,
5662 "Changing reload<-inheritance");
5663 lra_set_insn_deleted (insn
);
5665 if (lra_dump_file
!= NULL
)
5667 fprintf (lra_dump_file
,
5668 " Invariant inheritance reuse change %d (bb%d):\n",
5669 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5670 dump_insn_slim (lra_dump_file
, insn
);
5671 fprintf (lra_dump_file
,
5672 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5676 invariant_ptr
->insn
= curr_insn
;
5680 /* Check only registers living at the current program point in the
5682 static bitmap_head live_regs
;
5684 /* Update live info in EBB given by its HEAD and TAIL insns after
5685 inheritance/split transformation. The function removes dead moves
5688 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5693 rtx_insn
*prev_insn
;
5696 basic_block last_bb
, prev_bb
, curr_bb
;
5698 struct lra_insn_reg
*reg
;
5702 last_bb
= BLOCK_FOR_INSN (tail
);
5704 for (curr_insn
= tail
;
5705 curr_insn
!= PREV_INSN (head
);
5706 curr_insn
= prev_insn
)
5708 prev_insn
= PREV_INSN (curr_insn
);
5709 /* We need to process empty blocks too. They contain
5710 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5711 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5713 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5714 if (curr_bb
!= prev_bb
)
5716 if (prev_bb
!= NULL
)
5718 /* Update df_get_live_in (prev_bb): */
5719 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5720 if (bitmap_bit_p (&live_regs
, j
))
5721 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5723 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5725 if (curr_bb
!= last_bb
)
5727 /* Update df_get_live_out (curr_bb): */
5728 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5730 live_p
= bitmap_bit_p (&live_regs
, j
);
5732 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5733 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5739 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5741 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5745 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5747 if (! NONDEBUG_INSN_P (curr_insn
))
5749 curr_id
= lra_get_insn_recog_data (curr_insn
);
5750 curr_static_id
= curr_id
->insn_static_data
;
5752 if ((set
= single_set (curr_insn
)) != NULL_RTX
5753 && REG_P (SET_DEST (set
))
5754 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5755 && SET_DEST (set
) != pic_offset_table_rtx
5756 && bitmap_bit_p (&check_only_regs
, regno
)
5757 && ! bitmap_bit_p (&live_regs
, regno
))
5759 /* See which defined values die here. */
5760 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5761 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5762 bitmap_clear_bit (&live_regs
, reg
->regno
);
5763 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5764 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5765 bitmap_clear_bit (&live_regs
, reg
->regno
);
5766 if (curr_id
->arg_hard_regs
!= NULL
)
5767 /* Make clobbered argument hard registers die. */
5768 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5769 if (regno
>= FIRST_PSEUDO_REGISTER
)
5770 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5771 /* Mark each used value as live. */
5772 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5773 if (reg
->type
!= OP_OUT
5774 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5775 bitmap_set_bit (&live_regs
, reg
->regno
);
5776 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5777 if (reg
->type
!= OP_OUT
5778 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5779 bitmap_set_bit (&live_regs
, reg
->regno
);
5780 if (curr_id
->arg_hard_regs
!= NULL
)
5781 /* Make used argument hard registers live. */
5782 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5783 if (regno
< FIRST_PSEUDO_REGISTER
5784 && bitmap_bit_p (&check_only_regs
, regno
))
5785 bitmap_set_bit (&live_regs
, regno
);
5786 /* It is quite important to remove dead move insns because it
5787 means removing dead store. We don't need to process them for
5791 if (lra_dump_file
!= NULL
)
5793 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5794 dump_insn_slim (lra_dump_file
, curr_insn
);
5796 lra_set_insn_deleted (curr_insn
);
5801 /* The structure describes info to do an inheritance for the current
5802 insn. We need to collect such info first before doing the
5803 transformations because the transformations change the insn
5804 internal representation. */
5807 /* Original regno. */
5809 /* Subsequent insns which can inherit original reg value. */
5813 /* Array containing all info for doing inheritance from the current
5815 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5817 /* Number elements in the previous array. */
5818 static int to_inherit_num
;
5820 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5821 structure to_inherit. */
5823 add_to_inherit (int regno
, rtx insns
)
5827 for (i
= 0; i
< to_inherit_num
; i
++)
5828 if (to_inherit
[i
].regno
== regno
)
5830 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5831 to_inherit
[to_inherit_num
].regno
= regno
;
5832 to_inherit
[to_inherit_num
++].insns
= insns
;
5835 /* Return the last non-debug insn in basic block BB, or the block begin
5838 get_last_insertion_point (basic_block bb
)
5842 FOR_BB_INSNS_REVERSE (bb
, insn
)
5843 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5848 /* Set up RES by registers living on edges FROM except the edge (FROM,
5849 TO) or by registers set up in a jump insn in BB FROM. */
5851 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5854 struct lra_insn_reg
*reg
;
5858 lra_assert (to
!= NULL
);
5860 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5862 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5863 last
= get_last_insertion_point (from
);
5864 if (! JUMP_P (last
))
5866 curr_id
= lra_get_insn_recog_data (last
);
5867 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5868 if (reg
->type
!= OP_IN
)
5869 bitmap_set_bit (res
, reg
->regno
);
5872 /* Used as a temporary results of some bitmap calculations. */
5873 static bitmap_head temp_bitmap
;
5875 /* We split for reloads of small class of hard regs. The following
5876 defines how many hard regs the class should have to be qualified as
5877 small. The code is mostly oriented to x86/x86-64 architecture
5878 where some insns need to use only specific register or pair of
5879 registers and these register can live in RTL explicitly, e.g. for
5880 parameter passing. */
5881 static const int max_small_class_regs_num
= 2;
5883 /* Do inheritance/split transformations in EBB starting with HEAD and
5884 finishing on TAIL. We process EBB insns in the reverse order.
5885 Return true if we did any inheritance/split transformation in the
5888 We should avoid excessive splitting which results in worse code
5889 because of inaccurate cost calculations for spilling new split
5890 pseudos in such case. To achieve this we do splitting only if
5891 register pressure is high in given basic block and there are reload
5892 pseudos requiring hard registers. We could do more register
5893 pressure calculations at any given program point to avoid necessary
5894 splitting even more but it is to expensive and the current approach
5895 works well enough. */
5897 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5899 int i
, src_regno
, dst_regno
, nregs
;
5900 bool change_p
, succ_p
, update_reloads_num_p
;
5901 rtx_insn
*prev_insn
, *last_insn
;
5902 rtx next_usage_insns
, curr_set
;
5904 struct lra_insn_reg
*reg
;
5905 basic_block last_processed_bb
, curr_bb
= NULL
;
5906 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5910 bool head_p
, after_p
;
5913 curr_usage_insns_check
++;
5914 clear_invariants ();
5915 reloads_num
= calls_num
= 0;
5916 bitmap_clear (&check_only_regs
);
5917 bitmap_clear (&invalid_invariant_regs
);
5918 last_processed_bb
= NULL
;
5919 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5920 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5921 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5922 /* We don't process new insns generated in the loop. */
5923 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5925 prev_insn
= PREV_INSN (curr_insn
);
5926 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5927 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5928 if (last_processed_bb
!= curr_bb
)
5930 /* We are at the end of BB. Add qualified living
5931 pseudos for potential splitting. */
5932 to_process
= df_get_live_out (curr_bb
);
5933 if (last_processed_bb
!= NULL
)
5935 /* We are somewhere in the middle of EBB. */
5936 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5938 to_process
= &temp_bitmap
;
5940 last_processed_bb
= curr_bb
;
5941 last_insn
= get_last_insertion_point (curr_bb
);
5942 after_p
= (! JUMP_P (last_insn
)
5943 && (! CALL_P (last_insn
)
5944 || (find_reg_note (last_insn
,
5945 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5946 && ! SIBLING_CALL_P (last_insn
))));
5947 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5948 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5950 if ((int) j
>= lra_constraint_new_regno_start
)
5952 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5954 if (j
< FIRST_PSEUDO_REGISTER
)
5955 SET_HARD_REG_BIT (live_hard_regs
, j
);
5957 add_to_hard_reg_set (&live_hard_regs
,
5958 PSEUDO_REGNO_MODE (j
),
5960 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5964 src_regno
= dst_regno
= -1;
5965 curr_set
= single_set (curr_insn
);
5966 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
5967 dst_regno
= REGNO (SET_DEST (curr_set
));
5968 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
5969 src_regno
= REGNO (SET_SRC (curr_set
));
5970 update_reloads_num_p
= true;
5971 if (src_regno
< lra_constraint_new_regno_start
5972 && src_regno
>= FIRST_PSEUDO_REGISTER
5973 && reg_renumber
[src_regno
] < 0
5974 && dst_regno
>= lra_constraint_new_regno_start
5975 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5977 /* 'reload_pseudo <- original_pseudo'. */
5978 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5980 update_reloads_num_p
= false;
5982 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5983 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5984 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5985 curr_insn
, next_usage_insns
);
5989 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5990 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5991 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5992 reg_class_contents
[cl
]);
5994 else if (src_regno
< 0
5995 && dst_regno
>= lra_constraint_new_regno_start
5996 && invariant_p (SET_SRC (curr_set
))
5997 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
5998 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
5999 && ! bitmap_bit_p (&invalid_invariant_regs
,
6000 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6002 /* 'reload_pseudo <- invariant'. */
6003 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6005 update_reloads_num_p
= false;
6006 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6008 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6009 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6010 reg_class_contents
[cl
]);
6012 else if (src_regno
>= lra_constraint_new_regno_start
6013 && dst_regno
< lra_constraint_new_regno_start
6014 && dst_regno
>= FIRST_PSEUDO_REGISTER
6015 && reg_renumber
[dst_regno
] < 0
6016 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6017 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6018 && (next_usage_insns
6019 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6021 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6023 update_reloads_num_p
= false;
6024 /* 'original_pseudo <- reload_pseudo'. */
6025 if (! JUMP_P (curr_insn
)
6026 && inherit_reload_reg (true, dst_regno
, cl
,
6027 curr_insn
, next_usage_insns
))
6030 usage_insns
[dst_regno
].check
= 0;
6031 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6032 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6033 reg_class_contents
[cl
]);
6035 else if (INSN_P (curr_insn
))
6038 int max_uid
= get_max_uid ();
6040 curr_id
= lra_get_insn_recog_data (curr_insn
);
6041 curr_static_id
= curr_id
->insn_static_data
;
6043 /* Process insn definitions. */
6044 for (iter
= 0; iter
< 2; iter
++)
6045 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6048 if (reg
->type
!= OP_IN
6049 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6051 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6052 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6053 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6054 && (next_usage_insns
6055 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6057 struct lra_insn_reg
*r
;
6059 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6060 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6062 /* Don't do inheritance if the pseudo is also
6063 used in the insn. */
6065 /* We can not do inheritance right now
6066 because the current insn reg info (chain
6067 regs) can change after that. */
6068 add_to_inherit (dst_regno
, next_usage_insns
);
6070 /* We can not process one reg twice here because of
6071 usage_insns invalidation. */
6072 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6073 || reg_renumber
[dst_regno
] >= 0)
6074 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6078 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6079 potential_reload_hard_regs
,
6080 false, curr_insn
, max_uid
))
6082 CLEAR_HARD_REG_SET (s
);
6083 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6084 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6086 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6087 reg_renumber
[dst_regno
]);
6088 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6090 /* We should invalidate potential inheritance or
6091 splitting for the current insn usages to the next
6092 usage insns (see code below) as the output pseudo
6094 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6095 && reg_renumber
[dst_regno
] < 0)
6096 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6097 && (dst_regno
< FIRST_PSEUDO_REGISTER
6098 || reg_renumber
[dst_regno
] >= 0)))
6100 /* Invalidate and mark definitions. */
6101 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6102 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6105 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
6106 for (i
= 0; i
< nregs
; i
++)
6107 usage_insns
[dst_regno
+ i
].check
6108 = -(int) INSN_UID (curr_insn
);
6112 /* Process clobbered call regs. */
6113 if (curr_id
->arg_hard_regs
!= NULL
)
6114 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6115 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6116 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6117 = -(int) INSN_UID (curr_insn
);
6118 if (! JUMP_P (curr_insn
))
6119 for (i
= 0; i
< to_inherit_num
; i
++)
6120 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6121 ALL_REGS
, curr_insn
,
6122 to_inherit
[i
].insns
))
6124 if (CALL_P (curr_insn
))
6126 rtx cheap
, pat
, dest
;
6128 int regno
, hard_regno
;
6131 if ((cheap
= find_reg_note (curr_insn
,
6132 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6133 && ((cheap
= XEXP (cheap
, 0)), true)
6134 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6135 && (hard_regno
= reg_renumber
[regno
]) >= 0
6136 /* If there are pending saves/restores, the
6137 optimization is not worth. */
6138 && usage_insns
[regno
].calls_num
== calls_num
- 1
6139 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6141 /* Restore the pseudo from the call result as
6142 REG_RETURNED note says that the pseudo value is
6143 in the call result and the pseudo is an argument
6145 pat
= PATTERN (curr_insn
);
6146 if (GET_CODE (pat
) == PARALLEL
)
6147 pat
= XVECEXP (pat
, 0, 0);
6148 dest
= SET_DEST (pat
);
6149 /* For multiple return values dest is PARALLEL.
6150 Currently we handle only single return value case. */
6154 emit_move_insn (cheap
, copy_rtx (dest
));
6155 restore
= get_insns ();
6157 lra_process_new_insns (curr_insn
, NULL
, restore
,
6158 "Inserting call parameter restore");
6159 /* We don't need to save/restore of the pseudo from
6161 usage_insns
[regno
].calls_num
= calls_num
;
6162 bitmap_set_bit (&check_only_regs
, regno
);
6167 /* Process insn usages. */
6168 for (iter
= 0; iter
< 2; iter
++)
6169 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6172 if ((reg
->type
!= OP_OUT
6173 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6174 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6176 if (src_regno
>= FIRST_PSEUDO_REGISTER
6177 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6179 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6180 && (next_usage_insns
6181 = usage_insns
[src_regno
].insns
) != NULL_RTX
6182 && NONDEBUG_INSN_P (curr_insn
))
6183 add_to_inherit (src_regno
, next_usage_insns
);
6184 else if (usage_insns
[src_regno
].check
6185 != -(int) INSN_UID (curr_insn
))
6186 /* Add usages but only if the reg is not set up
6187 in the same insn. */
6188 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6190 else if (src_regno
< FIRST_PSEUDO_REGISTER
6191 || reg_renumber
[src_regno
] >= 0)
6194 rtx_insn
*use_insn
= curr_insn
;
6196 before_p
= (JUMP_P (curr_insn
)
6197 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6198 if (NONDEBUG_INSN_P (curr_insn
)
6199 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6200 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6201 potential_reload_hard_regs
,
6202 before_p
, curr_insn
, max_uid
))
6205 lra_risky_transformations_p
= true;
6208 usage_insns
[src_regno
].check
= 0;
6210 use_insn
= PREV_INSN (curr_insn
);
6212 if (NONDEBUG_INSN_P (curr_insn
))
6214 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6215 add_to_hard_reg_set (&live_hard_regs
,
6216 reg
->biggest_mode
, src_regno
);
6218 add_to_hard_reg_set (&live_hard_regs
,
6219 PSEUDO_REGNO_MODE (src_regno
),
6220 reg_renumber
[src_regno
]);
6222 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6225 /* Process used call regs. */
6226 if (curr_id
->arg_hard_regs
!= NULL
)
6227 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6228 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6230 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6231 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6233 for (i
= 0; i
< to_inherit_num
; i
++)
6235 src_regno
= to_inherit
[i
].regno
;
6236 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6237 curr_insn
, to_inherit
[i
].insns
))
6240 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6243 if (update_reloads_num_p
6244 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6247 if ((REG_P (SET_DEST (curr_set
))
6248 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6249 && reg_renumber
[regno
] < 0
6250 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6251 || (REG_P (SET_SRC (curr_set
))
6252 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6253 && reg_renumber
[regno
] < 0
6254 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6256 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6258 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6259 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6260 reg_class_contents
[cl
]);
6263 if (NONDEBUG_INSN_P (curr_insn
))
6267 /* Invalidate invariants with changed regs. */
6268 curr_id
= lra_get_insn_recog_data (curr_insn
);
6269 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6270 if (reg
->type
!= OP_IN
)
6272 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6273 bitmap_set_bit (&invalid_invariant_regs
,
6274 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6276 curr_static_id
= curr_id
->insn_static_data
;
6277 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6278 if (reg
->type
!= OP_IN
)
6279 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6280 if (curr_id
->arg_hard_regs
!= NULL
)
6281 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6282 if (regno
>= FIRST_PSEUDO_REGISTER
)
6283 bitmap_set_bit (&invalid_invariant_regs
,
6284 regno
- FIRST_PSEUDO_REGISTER
);
6286 /* We reached the start of the current basic block. */
6287 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6288 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6290 /* We reached the beginning of the current block -- do
6291 rest of spliting in the current BB. */
6292 to_process
= df_get_live_in (curr_bb
);
6293 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6295 /* We are somewhere in the middle of EBB. */
6296 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6297 curr_bb
, &temp_bitmap
);
6298 to_process
= &temp_bitmap
;
6301 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6303 if ((int) j
>= lra_constraint_new_regno_start
)
6305 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6306 && usage_insns
[j
].check
== curr_usage_insns_check
6307 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6309 if (need_for_split_p (potential_reload_hard_regs
, j
))
6311 if (lra_dump_file
!= NULL
&& head_p
)
6313 fprintf (lra_dump_file
,
6314 " ----------------------------------\n");
6317 if (split_reg (false, j
, bb_note (curr_bb
),
6321 usage_insns
[j
].check
= 0;
6329 /* This value affects EBB forming. If probability of edge from EBB to
6330 a BB is not greater than the following value, we don't add the BB
6332 #define EBB_PROBABILITY_CUTOFF \
6333 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6335 /* Current number of inheritance/split iteration. */
6336 int lra_inheritance_iter
;
6338 /* Entry function for inheritance/split pass. */
6340 lra_inheritance (void)
6343 basic_block bb
, start_bb
;
6346 lra_inheritance_iter
++;
6347 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6349 timevar_push (TV_LRA_INHERITANCE
);
6350 if (lra_dump_file
!= NULL
)
6351 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6352 lra_inheritance_iter
);
6353 curr_usage_insns_check
= 0;
6354 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6355 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6356 usage_insns
[i
].check
= 0;
6357 bitmap_initialize (&check_only_regs
, ®_obstack
);
6358 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6359 bitmap_initialize (&live_regs
, ®_obstack
);
6360 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6361 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6362 FOR_EACH_BB_FN (bb
, cfun
)
6365 if (lra_dump_file
!= NULL
)
6366 fprintf (lra_dump_file
, "EBB");
6367 /* Form a EBB starting with BB. */
6368 bitmap_clear (&ebb_global_regs
);
6369 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6372 if (lra_dump_file
!= NULL
)
6373 fprintf (lra_dump_file
, " %d", bb
->index
);
6374 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6375 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6377 e
= find_fallthru_edge (bb
->succs
);
6380 if (e
->probability
< EBB_PROBABILITY_CUTOFF
)
6384 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6385 if (lra_dump_file
!= NULL
)
6386 fprintf (lra_dump_file
, "\n");
6387 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6388 /* Remember that the EBB head and tail can change in
6390 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6392 bitmap_clear (&ebb_global_regs
);
6393 bitmap_clear (&temp_bitmap
);
6394 bitmap_clear (&live_regs
);
6395 bitmap_clear (&invalid_invariant_regs
);
6396 bitmap_clear (&check_only_regs
);
6399 timevar_pop (TV_LRA_INHERITANCE
);
6404 /* This page contains code to undo failed inheritance/split
6407 /* Current number of iteration undoing inheritance/split. */
6408 int lra_undo_inheritance_iter
;
6410 /* Fix BB live info LIVE after removing pseudos created on pass doing
6411 inheritance/split which are REMOVED_PSEUDOS. */
6413 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6418 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6419 if (bitmap_clear_bit (live
, regno
)
6420 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6421 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6424 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6429 if (GET_CODE (reg
) == SUBREG
)
6430 reg
= SUBREG_REG (reg
);
6436 /* Delete a move INSN with destination reg DREGNO and a previous
6437 clobber insn with the same regno. The inheritance/split code can
6438 generate moves with preceding clobber and when we delete such moves
6439 we should delete the clobber insn too to keep the correct life
6442 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6444 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6446 lra_set_insn_deleted (insn
);
6447 lra_assert (dregno
>= 0);
6448 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6449 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6450 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6451 lra_set_insn_deleted (prev_insn
);
6454 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6455 return true if we did any change. The undo transformations for
6456 inheritance looks like
6460 p <- i, i <- p, and i <- i3
6461 where p is original pseudo from which inheritance pseudo i was
6462 created, i and i3 are removed inheritance pseudos, i2 is another
6463 not removed inheritance pseudo. All split pseudos or other
6464 occurrences of removed inheritance pseudos are changed on the
6465 corresponding original pseudos.
6467 The function also schedules insns changed and created during
6468 inheritance/split pass for processing by the subsequent constraint
6471 remove_inheritance_pseudos (bitmap remove_pseudos
)
6474 int regno
, sregno
, prev_sregno
, dregno
;
6477 rtx_insn
*prev_insn
;
6478 bool change_p
, done_p
;
6480 change_p
= ! bitmap_empty_p (remove_pseudos
);
6481 /* We can not finish the function right away if CHANGE_P is true
6482 because we need to marks insns affected by previous
6483 inheritance/split pass for processing by the subsequent
6485 FOR_EACH_BB_FN (bb
, cfun
)
6487 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6488 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6489 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6491 if (! INSN_P (curr_insn
))
6494 sregno
= dregno
= -1;
6495 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6496 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6498 dregno
= get_regno (SET_DEST (set
));
6499 sregno
= get_regno (SET_SRC (set
));
6502 if (sregno
>= 0 && dregno
>= 0)
6504 if (bitmap_bit_p (remove_pseudos
, dregno
)
6505 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6507 /* invariant inheritance pseudo <- original pseudo */
6508 if (lra_dump_file
!= NULL
)
6510 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6511 dump_insn_slim (lra_dump_file
, curr_insn
);
6512 fprintf (lra_dump_file
, "\n");
6514 delete_move_and_clobber (curr_insn
, dregno
);
6517 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6518 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6520 /* reload pseudo <- invariant inheritance pseudo */
6522 /* We can not just change the source. It might be
6523 an insn different from the move. */
6524 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6525 rtx_insn
*new_insns
= get_insns ();
6527 lra_assert (single_set (new_insns
) != NULL
6528 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6529 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6530 "Changing reload<-invariant inheritance");
6531 delete_move_and_clobber (curr_insn
, dregno
);
6534 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6535 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6536 || (bitmap_bit_p (remove_pseudos
, dregno
)
6537 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6538 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6539 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6540 || (bitmap_bit_p (remove_pseudos
, dregno
)
6541 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6542 /* One of the following cases:
6543 original <- removed inheritance pseudo
6544 removed inherit pseudo <- another removed inherit pseudo
6545 removed inherit pseudo <- original pseudo
6547 removed_split_pseudo <- original_reg
6548 original_reg <- removed_split_pseudo */
6550 if (lra_dump_file
!= NULL
)
6552 fprintf (lra_dump_file
, " Removing %s:\n",
6553 bitmap_bit_p (&lra_split_regs
, sregno
)
6554 || bitmap_bit_p (&lra_split_regs
, dregno
)
6555 ? "split" : "inheritance");
6556 dump_insn_slim (lra_dump_file
, curr_insn
);
6558 delete_move_and_clobber (curr_insn
, dregno
);
6561 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6562 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6564 /* Search the following pattern:
6565 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6566 original_pseudo <- inherit_or_split_pseudo1
6567 where the 2nd insn is the current insn and
6568 inherit_or_split_pseudo2 is not removed. If it is found,
6569 change the current insn onto:
6570 original_pseudo <- inherit_or_split_pseudo2. */
6571 for (prev_insn
= PREV_INSN (curr_insn
);
6572 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6573 prev_insn
= PREV_INSN (prev_insn
))
6575 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6576 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6577 /* There should be no subregs in insn we are
6578 searching because only the original reg might
6579 be in subreg when we changed the mode of
6580 load/store for splitting. */
6581 && REG_P (SET_DEST (prev_set
))
6582 && REG_P (SET_SRC (prev_set
))
6583 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6584 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6585 >= FIRST_PSEUDO_REGISTER
)
6586 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6588 /* As we consider chain of inheritance or
6589 splitting described in above comment we should
6590 check that sregno and prev_sregno were
6591 inheritance/split pseudos created from the
6592 same original regno. */
6593 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6594 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6595 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6596 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6598 lra_assert (GET_MODE (SET_SRC (prev_set
))
6599 == GET_MODE (regno_reg_rtx
[sregno
]));
6600 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6601 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6603 SET_SRC (set
) = SET_SRC (prev_set
);
6604 /* As we are finishing with processing the insn
6605 here, check the destination too as it might
6606 inheritance pseudo for another pseudo. */
6607 if (bitmap_bit_p (remove_pseudos
, dregno
)
6608 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6610 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6612 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6613 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6615 SET_DEST (set
) = restore_rtx
;
6617 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6618 lra_set_used_insn_alternative_by_uid
6619 (INSN_UID (curr_insn
), -1);
6621 if (lra_dump_file
!= NULL
)
6623 fprintf (lra_dump_file
, " Change reload insn:\n");
6624 dump_insn_slim (lra_dump_file
, curr_insn
);
6631 struct lra_insn_reg
*reg
;
6632 bool restored_regs_p
= false;
6633 bool kept_regs_p
= false;
6635 curr_id
= lra_get_insn_recog_data (curr_insn
);
6636 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6639 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6640 if (restore_rtx
!= NULL_RTX
)
6642 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6644 lra_substitute_pseudo_within_insn
6645 (curr_insn
, regno
, restore_rtx
, false);
6646 restored_regs_p
= true;
6652 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6654 /* The instruction has changed since the previous
6655 constraints pass. */
6656 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6657 lra_set_used_insn_alternative_by_uid
6658 (INSN_UID (curr_insn
), -1);
6660 else if (restored_regs_p
)
6661 /* The instruction has been restored to the form that
6662 it had during the previous constraints pass. */
6663 lra_update_insn_regno_info (curr_insn
);
6664 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6666 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6667 dump_insn_slim (lra_dump_file
, curr_insn
);
6675 /* If optional reload pseudos failed to get a hard register or was not
6676 inherited, it is better to remove optional reloads. We do this
6677 transformation after undoing inheritance to figure out necessity to
6678 remove optional reloads easier. Return true if we do any
6681 undo_optional_reloads (void)
6683 bool change_p
, keep_p
;
6684 unsigned int regno
, uid
;
6685 bitmap_iterator bi
, bi2
;
6688 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
6690 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
6691 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6692 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6695 /* Keep optional reloads from previous subpasses. */
6696 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6697 /* If the original pseudo changed its allocation, just
6698 removing the optional pseudo is dangerous as the original
6699 pseudo will have longer live range. */
6700 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6702 else if (reg_renumber
[regno
] >= 0)
6703 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6705 insn
= lra_insn_recog_data
[uid
]->insn
;
6706 if ((set
= single_set (insn
)) == NULL_RTX
)
6708 src
= SET_SRC (set
);
6709 dest
= SET_DEST (set
);
6710 if (! REG_P (src
) || ! REG_P (dest
))
6712 if (REGNO (dest
) == regno
6713 /* Ignore insn for optional reloads itself. */
6714 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6715 /* Check only inheritance on last inheritance pass. */
6716 && (int) REGNO (src
) >= new_regno_start
6717 /* Check that the optional reload was inherited. */
6718 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6726 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
6727 if (lra_dump_file
!= NULL
)
6728 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6731 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
6732 bitmap_initialize (&insn_bitmap
, ®_obstack
);
6733 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
6735 if (lra_dump_file
!= NULL
)
6736 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6737 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6738 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
6740 insn
= lra_insn_recog_data
[uid
]->insn
;
6741 if ((set
= single_set (insn
)) != NULL_RTX
)
6743 src
= SET_SRC (set
);
6744 dest
= SET_DEST (set
);
6745 if (REG_P (src
) && REG_P (dest
)
6746 && ((REGNO (src
) == regno
6747 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6749 || (REGNO (dest
) == regno
6750 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6753 if (lra_dump_file
!= NULL
)
6755 fprintf (lra_dump_file
, " Deleting move %u\n",
6757 dump_insn_slim (lra_dump_file
, insn
);
6759 delete_move_and_clobber (insn
, REGNO (dest
));
6762 /* We should not worry about generation memory-memory
6763 moves here as if the corresponding inheritance did
6764 not work (inheritance pseudo did not get a hard reg),
6765 we remove the inheritance pseudo and the optional
6768 lra_substitute_pseudo_within_insn
6769 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6770 lra_update_insn_regno_info (insn
);
6771 if (lra_dump_file
!= NULL
)
6773 fprintf (lra_dump_file
,
6774 " Restoring original insn:\n");
6775 dump_insn_slim (lra_dump_file
, insn
);
6779 /* Clear restore_regnos. */
6780 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6781 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6782 bitmap_clear (&insn_bitmap
);
6783 bitmap_clear (&removed_optional_reload_pseudos
);
6787 /* Entry function for undoing inheritance/split transformation. Return true
6788 if we did any RTL change in this pass. */
6790 lra_undo_inheritance (void)
6794 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6796 bitmap_head remove_pseudos
;
6800 lra_undo_inheritance_iter
++;
6801 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6803 if (lra_dump_file
!= NULL
)
6804 fprintf (lra_dump_file
,
6805 "\n********** Undoing inheritance #%d: **********\n\n",
6806 lra_undo_inheritance_iter
);
6807 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6808 n_inherit
= n_all_inherit
= 0;
6809 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6810 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
6813 if (reg_renumber
[regno
] < 0
6814 /* If the original pseudo changed its allocation, just
6815 removing inheritance is dangerous as for changing
6816 allocation we used shorter live-ranges. */
6817 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
6818 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
6819 bitmap_set_bit (&remove_pseudos
, regno
);
6823 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6824 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6825 n_inherit
, n_all_inherit
,
6826 (double) n_inherit
/ n_all_inherit
* 100);
6827 n_split
= n_all_split
= 0;
6828 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6829 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
6831 int restore_regno
= REGNO (restore_rtx
);
6834 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6835 ? reg_renumber
[restore_regno
] : restore_regno
);
6836 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6837 bitmap_set_bit (&remove_pseudos
, regno
);
6841 if (lra_dump_file
!= NULL
)
6842 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6843 regno
, restore_regno
);
6846 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6847 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6848 n_split
, n_all_split
,
6849 (double) n_split
/ n_all_split
* 100);
6850 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6851 bitmap_clear (&remove_pseudos
);
6852 /* Clear restore_regnos. */
6853 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6854 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6855 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6856 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6857 change_p
= undo_optional_reloads () || change_p
;