1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
6 and Martin Simmons (@harleqn.co.uk).
7 More major hacks by Richard Earnshaw (rearnsha@arm.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 3, or (at your
14 option) any later version.
16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
50 #include "integrate.h"
53 #include "target-def.h"
55 #include "langhooks.h"
60 /* Forward definitions of types. */
61 typedef struct minipool_node Mnode
;
62 typedef struct minipool_fixup Mfix
;
64 void (*arm_lang_output_object_attributes_hook
)(void);
66 /* Forward function declarations. */
67 static int arm_compute_static_chain_stack_bytes (void);
68 static arm_stack_offsets
*arm_get_frame_offsets (void);
69 static void arm_add_gc_roots (void);
70 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
71 HOST_WIDE_INT
, rtx
, rtx
, int, int);
72 static unsigned bit_count (unsigned long);
73 static int arm_address_register_rtx_p (rtx
, int);
74 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
75 static int thumb2_legitimate_index_p (enum machine_mode
, rtx
, int);
76 static int thumb1_base_register_rtx_p (rtx
, enum machine_mode
, int);
77 static rtx
arm_legitimize_address (rtx
, rtx
, enum machine_mode
);
78 static rtx
thumb_legitimize_address (rtx
, rtx
, enum machine_mode
);
79 inline static int thumb1_index_register_rtx_p (rtx
, int);
80 static bool arm_legitimate_address_p (enum machine_mode
, rtx
, bool);
81 static int thumb_far_jump_used_p (void);
82 static bool thumb_force_lr_save (void);
83 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
84 static rtx
emit_sfm (int, int);
85 static unsigned arm_size_return_regs (void);
86 static bool arm_assemble_integer (rtx
, unsigned int, int);
87 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
88 static arm_cc
get_arm_condition_code (rtx
);
89 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
90 static rtx
is_jump_table (rtx
);
91 static const char *output_multi_immediate (rtx
*, const char *, const char *,
93 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
94 static struct machine_function
*arm_init_machine_status (void);
95 static void thumb_exit (FILE *, int);
96 static rtx
is_jump_table (rtx
);
97 static HOST_WIDE_INT
get_jump_table_size (rtx
);
98 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
99 static Mnode
*add_minipool_forward_ref (Mfix
*);
100 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
101 static Mnode
*add_minipool_backward_ref (Mfix
*);
102 static void assign_minipool_offsets (Mfix
*);
103 static void arm_print_value (FILE *, rtx
);
104 static void dump_minipool (rtx
);
105 static int arm_barrier_cost (rtx
);
106 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
107 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
108 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
110 static void arm_reorg (void);
111 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
112 static unsigned long arm_compute_save_reg0_reg12_mask (void);
113 static unsigned long arm_compute_save_reg_mask (void);
114 static unsigned long arm_isr_value (tree
);
115 static unsigned long arm_compute_func_type (void);
116 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
117 static tree
arm_handle_pcs_attribute (tree
*, tree
, tree
, int, bool *);
118 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
119 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
120 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
122 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
123 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
124 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT
);
125 static int arm_comp_type_attributes (const_tree
, const_tree
);
126 static void arm_set_default_type_attributes (tree
);
127 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
128 static int count_insns_for_constant (HOST_WIDE_INT
, int);
129 static int arm_get_strip_length (int);
130 static bool arm_function_ok_for_sibcall (tree
, tree
);
131 static enum machine_mode
arm_promote_function_mode (const_tree
,
132 enum machine_mode
, int *,
134 static bool arm_return_in_memory (const_tree
, const_tree
);
135 static rtx
arm_function_value (const_tree
, const_tree
, bool);
136 static rtx
arm_libcall_value (enum machine_mode
, const_rtx
);
138 static void arm_internal_label (FILE *, const char *, unsigned long);
139 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
141 static bool arm_have_conditional_execution (void);
142 static bool arm_rtx_costs_1 (rtx
, enum rtx_code
, int*, bool);
143 static bool arm_size_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *);
144 static bool arm_slowmul_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
145 static bool arm_fastmul_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
146 static bool arm_xscale_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
147 static bool arm_9e_rtx_costs (rtx
, enum rtx_code
, enum rtx_code
, int *, bool);
148 static bool arm_rtx_costs (rtx
, int, int, int *, bool);
149 static int arm_address_cost (rtx
, bool);
150 static bool arm_memory_load_p (rtx
);
151 static bool arm_cirrus_insn_p (rtx
);
152 static void cirrus_reorg (rtx
);
153 static void arm_init_builtins (void);
154 static void arm_init_iwmmxt_builtins (void);
155 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
156 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
157 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
158 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
159 static void emit_constant_insn (rtx cond
, rtx pattern
);
160 static rtx
emit_set_insn (rtx
, rtx
);
161 static int arm_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
163 static rtx
aapcs_allocate_return_reg (enum machine_mode
, const_tree
,
165 static int aapcs_select_return_coproc (const_tree
, const_tree
);
167 #ifdef OBJECT_FORMAT_ELF
168 static void arm_elf_asm_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
169 static void arm_elf_asm_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
172 static void arm_encode_section_info (tree
, rtx
, int);
175 static void arm_file_end (void);
176 static void arm_file_start (void);
178 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
180 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
181 enum machine_mode
, const_tree
, bool);
182 static bool arm_promote_prototypes (const_tree
);
183 static bool arm_default_short_enums (void);
184 static bool arm_align_anon_bitfield (void);
185 static bool arm_return_in_msb (const_tree
);
186 static bool arm_must_pass_in_stack (enum machine_mode
, const_tree
);
187 static bool arm_return_in_memory (const_tree
, const_tree
);
188 #ifdef TARGET_UNWIND_INFO
189 static void arm_unwind_emit (FILE *, rtx
);
190 static bool arm_output_ttype (rtx
);
192 static void arm_dwarf_handle_frame_unspec (const char *, rtx
, int);
193 static rtx
arm_dwarf_register_span (rtx
);
195 static tree
arm_cxx_guard_type (void);
196 static bool arm_cxx_guard_mask_bit (void);
197 static tree
arm_get_cookie_size (tree
);
198 static bool arm_cookie_has_size (void);
199 static bool arm_cxx_cdtor_returns_this (void);
200 static bool arm_cxx_key_method_may_be_inline (void);
201 static void arm_cxx_determine_class_data_visibility (tree
);
202 static bool arm_cxx_class_data_always_comdat (void);
203 static bool arm_cxx_use_aeabi_atexit (void);
204 static void arm_init_libfuncs (void);
205 static tree
arm_build_builtin_va_list (void);
206 static void arm_expand_builtin_va_start (tree
, rtx
);
207 static tree
arm_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
208 static bool arm_handle_option (size_t, const char *, int);
209 static void arm_target_help (void);
210 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (enum machine_mode
);
211 static bool arm_cannot_copy_insn_p (rtx
);
212 static bool arm_tls_symbol_p (rtx x
);
213 static int arm_issue_rate (void);
214 static void arm_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
215 static bool arm_allocate_stack_slots_for_args (void);
216 static const char *arm_invalid_parameter_type (const_tree t
);
217 static const char *arm_invalid_return_type (const_tree t
);
218 static tree
arm_promoted_type (const_tree t
);
219 static tree
arm_convert_to_type (tree type
, tree expr
);
220 static bool arm_scalar_mode_supported_p (enum machine_mode
);
221 static bool arm_frame_pointer_required (void);
222 static bool arm_can_eliminate (const int, const int);
223 static void arm_asm_trampoline_template (FILE *);
224 static void arm_trampoline_init (rtx
, tree
, rtx
);
225 static rtx
arm_trampoline_adjust_address (rtx
);
226 static rtx
arm_pic_static_addr (rtx orig
, rtx reg
);
229 /* Table of machine attributes. */
230 static const struct attribute_spec arm_attribute_table
[] =
232 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
233 /* Function calls made to this symbol must be done indirectly, because
234 it may lie outside of the 26 bit addressing range of a normal function
236 { "long_call", 0, 0, false, true, true, NULL
},
237 /* Whereas these functions are always known to reside within the 26 bit
239 { "short_call", 0, 0, false, true, true, NULL
},
240 /* Specify the procedure call conventions for a function. */
241 { "pcs", 1, 1, false, true, true, arm_handle_pcs_attribute
},
242 /* Interrupt Service Routines have special prologue and epilogue requirements. */
243 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
244 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
245 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
247 /* ARM/PE has three new attributes:
249 dllexport - for exporting a function/variable that will live in a dll
250 dllimport - for importing a function/variable from a dll
252 Microsoft allows multiple declspecs in one __declspec, separating
253 them with spaces. We do NOT support this. Instead, use __declspec
256 { "dllimport", 0, 0, true, false, false, NULL
},
257 { "dllexport", 0, 0, true, false, false, NULL
},
258 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
259 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
260 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
261 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
262 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute
},
264 { NULL
, 0, 0, false, false, false, NULL
}
267 /* Initialize the GCC target structure. */
268 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
269 #undef TARGET_MERGE_DECL_ATTRIBUTES
270 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
273 #undef TARGET_LEGITIMIZE_ADDRESS
274 #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address
276 #undef TARGET_ATTRIBUTE_TABLE
277 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
279 #undef TARGET_ASM_FILE_START
280 #define TARGET_ASM_FILE_START arm_file_start
281 #undef TARGET_ASM_FILE_END
282 #define TARGET_ASM_FILE_END arm_file_end
284 #undef TARGET_ASM_ALIGNED_SI_OP
285 #define TARGET_ASM_ALIGNED_SI_OP NULL
286 #undef TARGET_ASM_INTEGER
287 #define TARGET_ASM_INTEGER arm_assemble_integer
289 #undef TARGET_ASM_FUNCTION_PROLOGUE
290 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
292 #undef TARGET_ASM_FUNCTION_EPILOGUE
293 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
295 #undef TARGET_DEFAULT_TARGET_FLAGS
296 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
297 #undef TARGET_HANDLE_OPTION
298 #define TARGET_HANDLE_OPTION arm_handle_option
300 #define TARGET_HELP arm_target_help
302 #undef TARGET_COMP_TYPE_ATTRIBUTES
303 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
305 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
306 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
308 #undef TARGET_SCHED_ADJUST_COST
309 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
311 #undef TARGET_ENCODE_SECTION_INFO
313 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
315 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
318 #undef TARGET_STRIP_NAME_ENCODING
319 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
321 #undef TARGET_ASM_INTERNAL_LABEL
322 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
324 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
325 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
327 #undef TARGET_FUNCTION_VALUE
328 #define TARGET_FUNCTION_VALUE arm_function_value
330 #undef TARGET_LIBCALL_VALUE
331 #define TARGET_LIBCALL_VALUE arm_libcall_value
333 #undef TARGET_ASM_OUTPUT_MI_THUNK
334 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
335 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
336 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
338 #undef TARGET_RTX_COSTS
339 #define TARGET_RTX_COSTS arm_rtx_costs
340 #undef TARGET_ADDRESS_COST
341 #define TARGET_ADDRESS_COST arm_address_cost
343 #undef TARGET_SHIFT_TRUNCATION_MASK
344 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
345 #undef TARGET_VECTOR_MODE_SUPPORTED_P
346 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
348 #undef TARGET_MACHINE_DEPENDENT_REORG
349 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
351 #undef TARGET_INIT_BUILTINS
352 #define TARGET_INIT_BUILTINS arm_init_builtins
353 #undef TARGET_EXPAND_BUILTIN
354 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
356 #undef TARGET_INIT_LIBFUNCS
357 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
359 #undef TARGET_PROMOTE_FUNCTION_MODE
360 #define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode
361 #undef TARGET_PROMOTE_PROTOTYPES
362 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
363 #undef TARGET_PASS_BY_REFERENCE
364 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
365 #undef TARGET_ARG_PARTIAL_BYTES
366 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
368 #undef TARGET_SETUP_INCOMING_VARARGS
369 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
371 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
372 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args
374 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
375 #define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template
376 #undef TARGET_TRAMPOLINE_INIT
377 #define TARGET_TRAMPOLINE_INIT arm_trampoline_init
378 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
379 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
381 #undef TARGET_DEFAULT_SHORT_ENUMS
382 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
384 #undef TARGET_ALIGN_ANON_BITFIELD
385 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
387 #undef TARGET_NARROW_VOLATILE_BITFIELD
388 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
390 #undef TARGET_CXX_GUARD_TYPE
391 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
393 #undef TARGET_CXX_GUARD_MASK_BIT
394 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
396 #undef TARGET_CXX_GET_COOKIE_SIZE
397 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
399 #undef TARGET_CXX_COOKIE_HAS_SIZE
400 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
402 #undef TARGET_CXX_CDTOR_RETURNS_THIS
403 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
405 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
406 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
408 #undef TARGET_CXX_USE_AEABI_ATEXIT
409 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
411 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
412 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
413 arm_cxx_determine_class_data_visibility
415 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
416 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
418 #undef TARGET_RETURN_IN_MSB
419 #define TARGET_RETURN_IN_MSB arm_return_in_msb
421 #undef TARGET_RETURN_IN_MEMORY
422 #define TARGET_RETURN_IN_MEMORY arm_return_in_memory
424 #undef TARGET_MUST_PASS_IN_STACK
425 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
427 #ifdef TARGET_UNWIND_INFO
428 #undef TARGET_UNWIND_EMIT
429 #define TARGET_UNWIND_EMIT arm_unwind_emit
431 /* EABI unwinding tables use a different format for the typeinfo tables. */
432 #undef TARGET_ASM_TTYPE
433 #define TARGET_ASM_TTYPE arm_output_ttype
435 #undef TARGET_ARM_EABI_UNWINDER
436 #define TARGET_ARM_EABI_UNWINDER true
437 #endif /* TARGET_UNWIND_INFO */
439 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
440 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
442 #undef TARGET_DWARF_REGISTER_SPAN
443 #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
445 #undef TARGET_CANNOT_COPY_INSN_P
446 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
449 #undef TARGET_HAVE_TLS
450 #define TARGET_HAVE_TLS true
453 #undef TARGET_HAVE_CONDITIONAL_EXECUTION
454 #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
456 #undef TARGET_CANNOT_FORCE_CONST_MEM
457 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
459 #undef TARGET_MAX_ANCHOR_OFFSET
460 #define TARGET_MAX_ANCHOR_OFFSET 4095
462 /* The minimum is set such that the total size of the block
463 for a particular anchor is -4088 + 1 + 4095 bytes, which is
464 divisible by eight, ensuring natural spacing of anchors. */
465 #undef TARGET_MIN_ANCHOR_OFFSET
466 #define TARGET_MIN_ANCHOR_OFFSET -4088
468 #undef TARGET_SCHED_ISSUE_RATE
469 #define TARGET_SCHED_ISSUE_RATE arm_issue_rate
471 #undef TARGET_MANGLE_TYPE
472 #define TARGET_MANGLE_TYPE arm_mangle_type
474 #undef TARGET_BUILD_BUILTIN_VA_LIST
475 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
476 #undef TARGET_EXPAND_BUILTIN_VA_START
477 #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start
478 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
479 #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr
482 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
483 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
486 #undef TARGET_LEGITIMATE_ADDRESS_P
487 #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p
489 #undef TARGET_INVALID_PARAMETER_TYPE
490 #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type
492 #undef TARGET_INVALID_RETURN_TYPE
493 #define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type
495 #undef TARGET_PROMOTED_TYPE
496 #define TARGET_PROMOTED_TYPE arm_promoted_type
498 #undef TARGET_CONVERT_TO_TYPE
499 #define TARGET_CONVERT_TO_TYPE arm_convert_to_type
501 #undef TARGET_SCALAR_MODE_SUPPORTED_P
502 #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p
504 #undef TARGET_FRAME_POINTER_REQUIRED
505 #define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required
507 #undef TARGET_CAN_ELIMINATE
508 #define TARGET_CAN_ELIMINATE arm_can_eliminate
510 struct gcc_target targetm
= TARGET_INITIALIZER
;
512 /* Obstack for minipool constant handling. */
513 static struct obstack minipool_obstack
;
514 static char * minipool_startobj
;
516 /* The maximum number of insns skipped which
517 will be conditionalised if possible. */
518 static int max_insns_skipped
= 5;
520 extern FILE * asm_out_file
;
522 /* True if we are currently building a constant table. */
523 int making_const_table
;
525 /* The processor for which instructions should be scheduled. */
526 enum processor_type arm_tune
= arm_none
;
528 /* The current tuning set. */
529 const struct tune_params
*current_tune
;
531 /* The default processor used if not overridden by commandline. */
532 static enum processor_type arm_default_cpu
= arm_none
;
534 /* Which floating point hardware to schedule for. */
537 /* Which floating popint hardware to use. */
538 const struct arm_fpu_desc
*arm_fpu_desc
;
540 /* Whether to use floating point hardware. */
541 enum float_abi_type arm_float_abi
;
543 /* Which __fp16 format to use. */
544 enum arm_fp16_format_type arm_fp16_format
;
546 /* Which ABI to use. */
547 enum arm_abi_type arm_abi
;
549 /* Which thread pointer model to use. */
550 enum arm_tp_type target_thread_pointer
= TP_AUTO
;
552 /* Used to parse -mstructure_size_boundary command line option. */
553 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
555 /* Used for Thumb call_via trampolines. */
556 rtx thumb_call_via_label
[14];
557 static int thumb_call_reg_needed
;
559 /* Bit values used to identify processor capabilities. */
560 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
561 #define FL_ARCH3M (1 << 1) /* Extended multiply */
562 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
563 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
564 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
565 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
566 #define FL_THUMB (1 << 6) /* Thumb aware */
567 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
568 #define FL_STRONG (1 << 8) /* StrongARM */
569 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
570 #define FL_XSCALE (1 << 10) /* XScale */
571 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
572 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
573 media instructions. */
574 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
575 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
576 Note: ARM6 & 7 derivatives only. */
577 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
578 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
579 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
581 #define FL_DIV (1 << 18) /* Hardware divide. */
582 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
583 #define FL_NEON (1 << 20) /* Neon instructions. */
584 #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
587 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
589 #define FL_FOR_ARCH2 FL_NOTM
590 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
591 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
592 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
593 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
594 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
595 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
596 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
597 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
598 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
599 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
600 #define FL_FOR_ARCH6J FL_FOR_ARCH6
601 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
602 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
603 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
604 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
605 #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
606 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
607 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
608 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
609 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
610 #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
612 /* The bits in this mask specify which
613 instructions we are allowed to generate. */
614 static unsigned long insn_flags
= 0;
616 /* The bits in this mask specify which instruction scheduling options should
618 static unsigned long tune_flags
= 0;
620 /* The following are used in the arm.md file as equivalents to bits
621 in the above two flag variables. */
623 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
626 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
629 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
632 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
635 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
638 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
641 /* Nonzero if this chip supports the ARM 6K extensions. */
644 /* Nonzero if instructions not present in the 'M' profile can be used. */
645 int arm_arch_notm
= 0;
647 /* Nonzero if instructions present in ARMv7E-M can be used. */
650 /* Nonzero if this chip can benefit from load scheduling. */
651 int arm_ld_sched
= 0;
653 /* Nonzero if this chip is a StrongARM. */
654 int arm_tune_strongarm
= 0;
656 /* Nonzero if this chip is a Cirrus variant. */
657 int arm_arch_cirrus
= 0;
659 /* Nonzero if this chip supports Intel Wireless MMX technology. */
660 int arm_arch_iwmmxt
= 0;
662 /* Nonzero if this chip is an XScale. */
663 int arm_arch_xscale
= 0;
665 /* Nonzero if tuning for XScale */
666 int arm_tune_xscale
= 0;
668 /* Nonzero if we want to tune for stores that access the write-buffer.
669 This typically means an ARM6 or ARM7 with MMU or MPU. */
670 int arm_tune_wbuf
= 0;
672 /* Nonzero if tuning for Cortex-A9. */
673 int arm_tune_cortex_a9
= 0;
675 /* Nonzero if generating Thumb instructions. */
678 /* Nonzero if we should define __THUMB_INTERWORK__ in the
680 XXX This is a bit of a hack, it's intended to help work around
681 problems in GLD which doesn't understand that armv5t code is
682 interworking clean. */
683 int arm_cpp_interwork
= 0;
685 /* Nonzero if chip supports Thumb 2. */
688 /* Nonzero if chip supports integer division instruction. */
691 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
692 must report the mode of the memory reference from PRINT_OPERAND to
693 PRINT_OPERAND_ADDRESS. */
694 enum machine_mode output_memory_reference_mode
;
696 /* The register number to be used for the PIC offset register. */
697 unsigned arm_pic_register
= INVALID_REGNUM
;
699 /* Set to 1 after arm_reorg has started. Reset to start at the start of
700 the next function. */
701 static int after_arm_reorg
= 0;
703 static enum arm_pcs arm_pcs_default
;
705 /* For an explanation of these variables, see final_prescan_insn below. */
707 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
708 enum arm_cond_code arm_current_cc
;
710 int arm_target_label
;
711 /* The number of conditionally executed insns, including the current insn. */
712 int arm_condexec_count
= 0;
713 /* A bitmask specifying the patterns for the IT block.
714 Zero means do not output an IT block before this insn. */
715 int arm_condexec_mask
= 0;
716 /* The number of bits used in arm_condexec_mask. */
717 int arm_condexec_masklen
= 0;
719 /* The condition codes of the ARM, and the inverse function. */
720 static const char * const arm_condition_codes
[] =
722 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
723 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
726 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
727 #define streq(string1, string2) (strcmp (string1, string2) == 0)
729 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
730 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
731 | (1 << PIC_OFFSET_TABLE_REGNUM)))
733 /* Initialization code. */
737 const char *const name
;
738 enum processor_type core
;
740 const unsigned long flags
;
741 const struct tune_params
*const tune
;
744 const struct tune_params arm_slowmul_tune
=
746 arm_slowmul_rtx_costs
,
750 const struct tune_params arm_fastmul_tune
=
752 arm_fastmul_rtx_costs
,
756 const struct tune_params arm_xscale_tune
=
758 arm_xscale_rtx_costs
,
762 const struct tune_params arm_9e_tune
=
768 /* Not all of these give usefully different compilation alternatives,
769 but there is no simple way of generalizing them. */
770 static const struct processors all_cores
[] =
773 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
774 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
775 #include "arm-cores.def"
777 {NULL
, arm_none
, NULL
, 0, NULL
}
780 static const struct processors all_architectures
[] =
782 /* ARM Architectures */
783 /* We don't specify tuning costs here as it will be figured out
786 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
787 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
788 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
789 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
790 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
791 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
792 implementations that support it, so we will leave it out for now. */
793 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
794 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
795 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
796 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
797 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
798 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
799 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
800 {"armv6k", mpcore
, "6K", FL_CO_PROC
| FL_FOR_ARCH6K
, NULL
},
801 {"armv6z", arm1176jzs
, "6Z", FL_CO_PROC
| FL_FOR_ARCH6Z
, NULL
},
802 {"armv6zk", arm1176jzs
, "6ZK", FL_CO_PROC
| FL_FOR_ARCH6ZK
, NULL
},
803 {"armv6t2", arm1156t2s
, "6T2", FL_CO_PROC
| FL_FOR_ARCH6T2
, NULL
},
804 {"armv6-m", cortexm1
, "6M", FL_FOR_ARCH6M
, NULL
},
805 {"armv7", cortexa8
, "7", FL_CO_PROC
| FL_FOR_ARCH7
, NULL
},
806 {"armv7-a", cortexa8
, "7A", FL_CO_PROC
| FL_FOR_ARCH7A
, NULL
},
807 {"armv7-r", cortexr4
, "7R", FL_CO_PROC
| FL_FOR_ARCH7R
, NULL
},
808 {"armv7-m", cortexm3
, "7M", FL_CO_PROC
| FL_FOR_ARCH7M
, NULL
},
809 {"armv7e-m", cortexm3
, "7EM", FL_CO_PROC
| FL_FOR_ARCH7EM
, NULL
},
810 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
811 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
812 {"iwmmxt2", iwmmxt2
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
813 {NULL
, arm_none
, NULL
, 0 , NULL
}
816 struct arm_cpu_select
820 const struct processors
* processors
;
823 /* This is a magic structure. The 'string' field is magically filled in
824 with a pointer to the value specified by the user on the command line
825 assuming that the user has specified such a value. */
827 static struct arm_cpu_select arm_select
[] =
829 /* string name processors */
830 { NULL
, "-mcpu=", all_cores
},
831 { NULL
, "-march=", all_architectures
},
832 { NULL
, "-mtune=", all_cores
}
835 /* Defines representing the indexes into the above table. */
836 #define ARM_OPT_SET_CPU 0
837 #define ARM_OPT_SET_ARCH 1
838 #define ARM_OPT_SET_TUNE 2
840 /* The name of the preprocessor macro to define for this architecture. */
842 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
844 /* Available values for -mfpu=. */
846 static const struct arm_fpu_desc all_fpus
[] =
848 {"fpa", ARM_FP_MODEL_FPA
, 0, VFP_NONE
, false, false},
849 {"fpe2", ARM_FP_MODEL_FPA
, 2, VFP_NONE
, false, false},
850 {"fpe3", ARM_FP_MODEL_FPA
, 3, VFP_NONE
, false, false},
851 {"maverick", ARM_FP_MODEL_MAVERICK
, 0, VFP_NONE
, false, false},
852 {"vfp", ARM_FP_MODEL_VFP
, 2, VFP_REG_D16
, false, false},
853 {"vfpv3", ARM_FP_MODEL_VFP
, 3, VFP_REG_D32
, false, false},
854 {"vfpv3-fp16", ARM_FP_MODEL_VFP
, 3, VFP_REG_D32
, false, true},
855 {"vfpv3-d16", ARM_FP_MODEL_VFP
, 3, VFP_REG_D16
, false, false},
856 {"vfpv3-d16-fp16", ARM_FP_MODEL_VFP
, 3, VFP_REG_D16
, false, true},
857 {"vfpv3xd", ARM_FP_MODEL_VFP
, 3, VFP_REG_SINGLE
, false, false},
858 {"vfpv3xd-fp16", ARM_FP_MODEL_VFP
, 3, VFP_REG_SINGLE
, false, true},
859 {"neon", ARM_FP_MODEL_VFP
, 3, VFP_REG_D32
, true , false},
860 {"neon-fp16", ARM_FP_MODEL_VFP
, 3, VFP_REG_D32
, true , true },
861 {"vfpv4", ARM_FP_MODEL_VFP
, 4, VFP_REG_D32
, false, true},
862 {"vfpv4-d16", ARM_FP_MODEL_VFP
, 4, VFP_REG_D16
, false, true},
863 {"fpv4-sp-d16", ARM_FP_MODEL_VFP
, 4, VFP_REG_SINGLE
, false, true},
864 {"neon-vfpv4", ARM_FP_MODEL_VFP
, 4, VFP_REG_D32
, true, true},
865 /* Compatibility aliases. */
866 {"vfp3", ARM_FP_MODEL_VFP
, 3, VFP_REG_D32
, false, false},
873 enum float_abi_type abi_type
;
877 /* Available values for -mfloat-abi=. */
879 static const struct float_abi all_float_abis
[] =
881 {"soft", ARM_FLOAT_ABI_SOFT
},
882 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
883 {"hard", ARM_FLOAT_ABI_HARD
}
890 enum arm_fp16_format_type fp16_format_type
;
894 /* Available values for -mfp16-format=. */
896 static const struct fp16_format all_fp16_formats
[] =
898 {"none", ARM_FP16_FORMAT_NONE
},
899 {"ieee", ARM_FP16_FORMAT_IEEE
},
900 {"alternative", ARM_FP16_FORMAT_ALTERNATIVE
}
907 enum arm_abi_type abi_type
;
911 /* Available values for -mabi=. */
913 static const struct abi_name arm_all_abis
[] =
915 {"apcs-gnu", ARM_ABI_APCS
},
916 {"atpcs", ARM_ABI_ATPCS
},
917 {"aapcs", ARM_ABI_AAPCS
},
918 {"iwmmxt", ARM_ABI_IWMMXT
},
919 {"aapcs-linux", ARM_ABI_AAPCS_LINUX
}
922 /* Supported TLS relocations. */
932 /* The maximum number of insns to be used when loading a constant. */
934 arm_constant_limit (bool size_p
)
936 return size_p
? 1 : current_tune
->constant_limit
;
939 /* Emit an insn that's a simple single-set. Both the operands must be known
942 emit_set_insn (rtx x
, rtx y
)
944 return emit_insn (gen_rtx_SET (VOIDmode
, x
, y
));
947 /* Return the number of bits set in VALUE. */
949 bit_count (unsigned long value
)
951 unsigned long count
= 0;
956 value
&= value
- 1; /* Clear the least-significant set bit. */
962 /* Set up library functions unique to ARM. */
965 arm_init_libfuncs (void)
967 /* There are no special library functions unless we are using the
972 /* The functions below are described in Section 4 of the "Run-Time
973 ABI for the ARM architecture", Version 1.0. */
975 /* Double-precision floating-point arithmetic. Table 2. */
976 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
977 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
978 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
979 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
980 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
982 /* Double-precision comparisons. Table 3. */
983 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
984 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
985 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
986 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
987 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
988 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
989 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
991 /* Single-precision floating-point arithmetic. Table 4. */
992 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
993 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
994 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
995 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
996 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
998 /* Single-precision comparisons. Table 5. */
999 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
1000 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
1001 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
1002 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
1003 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
1004 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
1005 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
1007 /* Floating-point to integer conversions. Table 6. */
1008 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
1009 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
1010 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
1011 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
1012 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
1013 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
1014 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
1015 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
1017 /* Conversions between floating types. Table 7. */
1018 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
1019 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
1021 /* Integer to floating-point conversions. Table 8. */
1022 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
1023 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
1024 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
1025 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
1026 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
1027 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
1028 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
1029 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
1031 /* Long long. Table 9. */
1032 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
1033 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
1034 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
1035 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
1036 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
1037 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
1038 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
1039 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
1041 /* Integer (32/32->32) division. \S 4.3.1. */
1042 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
1043 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
1045 /* The divmod functions are designed so that they can be used for
1046 plain division, even though they return both the quotient and the
1047 remainder. The quotient is returned in the usual location (i.e.,
1048 r0 for SImode, {r0, r1} for DImode), just as would be expected
1049 for an ordinary division routine. Because the AAPCS calling
1050 conventions specify that all of { r0, r1, r2, r3 } are
1051 callee-saved registers, there is no need to tell the compiler
1052 explicitly that those registers are clobbered by these
1054 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
1055 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
1057 /* For SImode division the ABI provides div-without-mod routines,
1058 which are faster. */
1059 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
1060 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
1062 /* We don't have mod libcalls. Fortunately gcc knows how to use the
1063 divmod libcalls instead. */
1064 set_optab_libfunc (smod_optab
, DImode
, NULL
);
1065 set_optab_libfunc (umod_optab
, DImode
, NULL
);
1066 set_optab_libfunc (smod_optab
, SImode
, NULL
);
1067 set_optab_libfunc (umod_optab
, SImode
, NULL
);
1069 /* Half-precision float operations. The compiler handles all operations
1070 with NULL libfuncs by converting the SFmode. */
1071 switch (arm_fp16_format
)
1073 case ARM_FP16_FORMAT_IEEE
:
1074 case ARM_FP16_FORMAT_ALTERNATIVE
:
1077 set_conv_libfunc (trunc_optab
, HFmode
, SFmode
,
1078 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
1080 : "__gnu_f2h_alternative"));
1081 set_conv_libfunc (sext_optab
, SFmode
, HFmode
,
1082 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
1084 : "__gnu_h2f_alternative"));
1087 set_optab_libfunc (add_optab
, HFmode
, NULL
);
1088 set_optab_libfunc (sdiv_optab
, HFmode
, NULL
);
1089 set_optab_libfunc (smul_optab
, HFmode
, NULL
);
1090 set_optab_libfunc (neg_optab
, HFmode
, NULL
);
1091 set_optab_libfunc (sub_optab
, HFmode
, NULL
);
1094 set_optab_libfunc (eq_optab
, HFmode
, NULL
);
1095 set_optab_libfunc (ne_optab
, HFmode
, NULL
);
1096 set_optab_libfunc (lt_optab
, HFmode
, NULL
);
1097 set_optab_libfunc (le_optab
, HFmode
, NULL
);
1098 set_optab_libfunc (ge_optab
, HFmode
, NULL
);
1099 set_optab_libfunc (gt_optab
, HFmode
, NULL
);
1100 set_optab_libfunc (unord_optab
, HFmode
, NULL
);
1107 if (TARGET_AAPCS_BASED
)
1108 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
1111 /* On AAPCS systems, this is the "struct __va_list". */
1112 static GTY(()) tree va_list_type
;
1114 /* Return the type to use as __builtin_va_list. */
1116 arm_build_builtin_va_list (void)
1121 if (!TARGET_AAPCS_BASED
)
1122 return std_build_builtin_va_list ();
1124 /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type
1132 The C Library ABI further reinforces this definition in \S
1135 We must follow this definition exactly. The structure tag
1136 name is visible in C++ mangled names, and thus forms a part
1137 of the ABI. The field name may be used by people who
1138 #include <stdarg.h>. */
1139 /* Create the type. */
1140 va_list_type
= lang_hooks
.types
.make_type (RECORD_TYPE
);
1141 /* Give it the required name. */
1142 va_list_name
= build_decl (BUILTINS_LOCATION
,
1144 get_identifier ("__va_list"),
1146 DECL_ARTIFICIAL (va_list_name
) = 1;
1147 TYPE_NAME (va_list_type
) = va_list_name
;
1148 /* Create the __ap field. */
1149 ap_field
= build_decl (BUILTINS_LOCATION
,
1151 get_identifier ("__ap"),
1153 DECL_ARTIFICIAL (ap_field
) = 1;
1154 DECL_FIELD_CONTEXT (ap_field
) = va_list_type
;
1155 TYPE_FIELDS (va_list_type
) = ap_field
;
1156 /* Compute its layout. */
1157 layout_type (va_list_type
);
1159 return va_list_type
;
1162 /* Return an expression of type "void *" pointing to the next
1163 available argument in a variable-argument list. VALIST is the
1164 user-level va_list object, of type __builtin_va_list. */
1166 arm_extract_valist_ptr (tree valist
)
1168 if (TREE_TYPE (valist
) == error_mark_node
)
1169 return error_mark_node
;
1171 /* On an AAPCS target, the pointer is stored within "struct
1173 if (TARGET_AAPCS_BASED
)
1175 tree ap_field
= TYPE_FIELDS (TREE_TYPE (valist
));
1176 valist
= build3 (COMPONENT_REF
, TREE_TYPE (ap_field
),
1177 valist
, ap_field
, NULL_TREE
);
1183 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
1185 arm_expand_builtin_va_start (tree valist
, rtx nextarg
)
1187 valist
= arm_extract_valist_ptr (valist
);
1188 std_expand_builtin_va_start (valist
, nextarg
);
1191 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
1193 arm_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
1196 valist
= arm_extract_valist_ptr (valist
);
1197 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
1200 /* Implement TARGET_HANDLE_OPTION. */
1203 arm_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
1208 arm_select
[1].string
= arg
;
1212 arm_select
[0].string
= arg
;
1215 case OPT_mhard_float
:
1216 target_float_abi_name
= "hard";
1219 case OPT_msoft_float
:
1220 target_float_abi_name
= "soft";
1224 arm_select
[2].string
= arg
;
1233 arm_target_help (void)
1236 static int columns
= 0;
1239 /* If we have not done so already, obtain the desired maximum width of
1240 the output. Note - this is a duplication of the code at the start of
1241 gcc/opts.c:print_specific_help() - the two copies should probably be
1242 replaced by a single function. */
1247 GET_ENVIRONMENT (p
, "COLUMNS");
1250 int value
= atoi (p
);
1257 /* Use a reasonable default. */
1261 printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n");
1263 /* The - 2 is because we know that the last entry in the array is NULL. */
1264 i
= ARRAY_SIZE (all_cores
) - 2;
1266 printf (" %s", all_cores
[i
].name
);
1267 remaining
= columns
- (strlen (all_cores
[i
].name
) + 4);
1268 gcc_assert (remaining
>= 0);
1272 int len
= strlen (all_cores
[i
].name
);
1274 if (remaining
> len
+ 2)
1276 printf (", %s", all_cores
[i
].name
);
1277 remaining
-= len
+ 2;
1283 printf ("\n %s", all_cores
[i
].name
);
1284 remaining
= columns
- (len
+ 4);
1288 printf ("\n\n Known ARM architectures (for use with the -march= option):\n");
1290 i
= ARRAY_SIZE (all_architectures
) - 2;
1293 printf (" %s", all_architectures
[i
].name
);
1294 remaining
= columns
- (strlen (all_architectures
[i
].name
) + 4);
1295 gcc_assert (remaining
>= 0);
1299 int len
= strlen (all_architectures
[i
].name
);
1301 if (remaining
> len
+ 2)
1303 printf (", %s", all_architectures
[i
].name
);
1304 remaining
-= len
+ 2;
1310 printf ("\n %s", all_architectures
[i
].name
);
1311 remaining
= columns
- (len
+ 4);
1318 /* Fix up any incompatible options that the user has specified.
1319 This has now turned into a maze. */
1321 arm_override_options (void)
1324 enum processor_type target_arch_cpu
= arm_none
;
1325 enum processor_type selected_cpu
= arm_none
;
1327 /* Set up the flags based on the cpu/architecture selected by the user. */
1328 for (i
= ARRAY_SIZE (arm_select
); i
--;)
1330 struct arm_cpu_select
* ptr
= arm_select
+ i
;
1332 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
1334 const struct processors
* sel
;
1336 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
1337 if (streq (ptr
->string
, sel
->name
))
1339 /* Set the architecture define. */
1340 if (i
!= ARM_OPT_SET_TUNE
)
1341 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1343 /* Determine the processor core for which we should
1344 tune code-generation. */
1345 if (/* -mcpu= is a sensible default. */
1346 i
== ARM_OPT_SET_CPU
1347 /* -mtune= overrides -mcpu= and -march=. */
1348 || i
== ARM_OPT_SET_TUNE
)
1349 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
1351 /* Remember the CPU associated with this architecture.
1352 If no other option is used to set the CPU type,
1353 we'll use this to guess the most suitable tuning
1355 if (i
== ARM_OPT_SET_ARCH
)
1356 target_arch_cpu
= sel
->core
;
1358 if (i
== ARM_OPT_SET_CPU
)
1359 selected_cpu
= (enum processor_type
) (sel
- ptr
->processors
);
1361 if (i
!= ARM_OPT_SET_TUNE
)
1363 /* If we have been given an architecture and a processor
1364 make sure that they are compatible. We only generate
1365 a warning though, and we prefer the CPU over the
1367 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
1368 warning (0, "switch -mcpu=%s conflicts with -march= switch",
1371 insn_flags
= sel
->flags
;
1377 if (sel
->name
== NULL
)
1378 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
1382 /* Guess the tuning options from the architecture if necessary. */
1383 if (arm_tune
== arm_none
)
1384 arm_tune
= target_arch_cpu
;
1386 /* If the user did not specify a processor, choose one for them. */
1387 if (insn_flags
== 0)
1389 const struct processors
* sel
;
1390 unsigned int sought
;
1392 selected_cpu
= (enum processor_type
) TARGET_CPU_DEFAULT
;
1393 if (selected_cpu
== arm_none
)
1395 #ifdef SUBTARGET_CPU_DEFAULT
1396 /* Use the subtarget default CPU if none was specified by
1398 selected_cpu
= (enum processor_type
) SUBTARGET_CPU_DEFAULT
;
1400 /* Default to ARM6. */
1401 if (selected_cpu
== arm_none
)
1402 selected_cpu
= arm6
;
1404 sel
= &all_cores
[selected_cpu
];
1406 insn_flags
= sel
->flags
;
1408 /* Now check to see if the user has specified some command line
1409 switch that require certain abilities from the cpu. */
1412 if (TARGET_INTERWORK
|| TARGET_THUMB
)
1414 sought
|= (FL_THUMB
| FL_MODE32
);
1416 /* There are no ARM processors that support both APCS-26 and
1417 interworking. Therefore we force FL_MODE26 to be removed
1418 from insn_flags here (if it was set), so that the search
1419 below will always be able to find a compatible processor. */
1420 insn_flags
&= ~FL_MODE26
;
1423 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
1425 /* Try to locate a CPU type that supports all of the abilities
1426 of the default CPU, plus the extra abilities requested by
1428 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1429 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
1432 if (sel
->name
== NULL
)
1434 unsigned current_bit_count
= 0;
1435 const struct processors
* best_fit
= NULL
;
1437 /* Ideally we would like to issue an error message here
1438 saying that it was not possible to find a CPU compatible
1439 with the default CPU, but which also supports the command
1440 line options specified by the programmer, and so they
1441 ought to use the -mcpu=<name> command line option to
1442 override the default CPU type.
1444 If we cannot find a cpu that has both the
1445 characteristics of the default cpu and the given
1446 command line options we scan the array again looking
1447 for a best match. */
1448 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
1449 if ((sel
->flags
& sought
) == sought
)
1453 count
= bit_count (sel
->flags
& insn_flags
);
1455 if (count
>= current_bit_count
)
1458 current_bit_count
= count
;
1462 gcc_assert (best_fit
);
1466 insn_flags
= sel
->flags
;
1468 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
1469 arm_default_cpu
= (enum processor_type
) (sel
- all_cores
);
1470 if (arm_tune
== arm_none
)
1471 arm_tune
= arm_default_cpu
;
1474 /* The processor for which we should tune should now have been
1476 gcc_assert (arm_tune
!= arm_none
);
1478 tune_flags
= all_cores
[(int)arm_tune
].flags
;
1479 current_tune
= all_cores
[(int)arm_tune
].tune
;
1481 if (target_fp16_format_name
)
1483 for (i
= 0; i
< ARRAY_SIZE (all_fp16_formats
); i
++)
1485 if (streq (all_fp16_formats
[i
].name
, target_fp16_format_name
))
1487 arm_fp16_format
= all_fp16_formats
[i
].fp16_format_type
;
1491 if (i
== ARRAY_SIZE (all_fp16_formats
))
1492 error ("invalid __fp16 format option: -mfp16-format=%s",
1493 target_fp16_format_name
);
1496 arm_fp16_format
= ARM_FP16_FORMAT_NONE
;
1498 if (target_abi_name
)
1500 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
1502 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
1504 arm_abi
= arm_all_abis
[i
].abi_type
;
1508 if (i
== ARRAY_SIZE (arm_all_abis
))
1509 error ("invalid ABI option: -mabi=%s", target_abi_name
);
1512 arm_abi
= ARM_DEFAULT_ABI
;
1514 /* Make sure that the processor choice does not conflict with any of the
1515 other command line choices. */
1516 if (TARGET_ARM
&& !(insn_flags
& FL_NOTM
))
1517 error ("target CPU does not support ARM mode");
1519 /* BPABI targets use linker tricks to allow interworking on cores
1520 without thumb support. */
1521 if (TARGET_INTERWORK
&& !((insn_flags
& FL_THUMB
) || TARGET_BPABI
))
1523 warning (0, "target CPU does not support interworking" );
1524 target_flags
&= ~MASK_INTERWORK
;
1527 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
1529 warning (0, "target CPU does not support THUMB instructions");
1530 target_flags
&= ~MASK_THUMB
;
1533 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
1535 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1536 target_flags
&= ~MASK_APCS_FRAME
;
1539 /* Callee super interworking implies thumb interworking. Adding
1540 this to the flags here simplifies the logic elsewhere. */
1541 if (TARGET_THUMB
&& TARGET_CALLEE_INTERWORKING
)
1542 target_flags
|= MASK_INTERWORK
;
1544 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1545 from here where no function is being compiled currently. */
1546 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM
)
1547 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1549 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
1550 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1552 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
1553 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1555 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
1557 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1558 target_flags
|= MASK_APCS_FRAME
;
1561 if (TARGET_POKE_FUNCTION_NAME
)
1562 target_flags
|= MASK_APCS_FRAME
;
1564 if (TARGET_APCS_REENT
&& flag_pic
)
1565 error ("-fpic and -mapcs-reent are incompatible");
1567 if (TARGET_APCS_REENT
)
1568 warning (0, "APCS reentrant code not supported. Ignored");
1570 /* If this target is normally configured to use APCS frames, warn if they
1571 are turned off and debugging is turned on. */
1573 && write_symbols
!= NO_DEBUG
1574 && !TARGET_APCS_FRAME
1575 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
1576 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1578 if (TARGET_APCS_FLOAT
)
1579 warning (0, "passing floating point arguments in fp regs not yet supported");
1581 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1582 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
1583 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
1584 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
1585 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
1586 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
1587 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
1588 arm_arch6k
= (insn_flags
& FL_ARCH6K
) != 0;
1589 arm_arch_notm
= (insn_flags
& FL_NOTM
) != 0;
1590 arm_arch7em
= (insn_flags
& FL_ARCH7EM
) != 0;
1591 arm_arch_thumb2
= (insn_flags
& FL_THUMB2
) != 0;
1592 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
1593 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
1595 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
1596 arm_tune_strongarm
= (tune_flags
& FL_STRONG
) != 0;
1597 thumb_code
= (TARGET_ARM
== 0);
1598 arm_tune_wbuf
= (tune_flags
& FL_WBUF
) != 0;
1599 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
1600 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
1601 arm_arch_hwdiv
= (insn_flags
& FL_DIV
) != 0;
1602 arm_tune_cortex_a9
= (arm_tune
== cortexa9
) != 0;
1604 /* If we are not using the default (ARM mode) section anchor offset
1605 ranges, then set the correct ranges now. */
1608 /* Thumb-1 LDR instructions cannot have negative offsets.
1609 Permissible positive offset ranges are 5-bit (for byte loads),
1610 6-bit (for halfword loads), or 7-bit (for word loads).
1611 Empirical results suggest a 7-bit anchor range gives the best
1612 overall code size. */
1613 targetm
.min_anchor_offset
= 0;
1614 targetm
.max_anchor_offset
= 127;
1616 else if (TARGET_THUMB2
)
1618 /* The minimum is set such that the total size of the block
1619 for a particular anchor is 248 + 1 + 4095 bytes, which is
1620 divisible by eight, ensuring natural spacing of anchors. */
1621 targetm
.min_anchor_offset
= -248;
1622 targetm
.max_anchor_offset
= 4095;
1625 /* V5 code we generate is completely interworking capable, so we turn off
1626 TARGET_INTERWORK here to avoid many tests later on. */
1628 /* XXX However, we must pass the right pre-processor defines to CPP
1629 or GLD can get confused. This is a hack. */
1630 if (TARGET_INTERWORK
)
1631 arm_cpp_interwork
= 1;
1634 target_flags
&= ~MASK_INTERWORK
;
1636 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
1637 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1639 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
1640 error ("iwmmxt abi requires an iwmmxt capable cpu");
1642 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
1644 if (streq (target_fpe_name
, "2"))
1645 target_fpu_name
= "fpe2";
1646 else if (streq (target_fpe_name
, "3"))
1647 target_fpu_name
= "fpe3";
1649 error ("invalid floating point emulation option: -mfpe=%s",
1653 if (target_fpu_name
== NULL
)
1655 #ifdef FPUTYPE_DEFAULT
1656 target_fpu_name
= FPUTYPE_DEFAULT
;
1658 if (arm_arch_cirrus
)
1659 target_fpu_name
= "maverick";
1661 target_fpu_name
= "fpe2";
1665 arm_fpu_desc
= NULL
;
1666 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1668 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1670 arm_fpu_desc
= &all_fpus
[i
];
1677 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1681 switch (arm_fpu_desc
->model
)
1683 case ARM_FP_MODEL_FPA
:
1684 if (arm_fpu_desc
->rev
== 2)
1685 arm_fpu_attr
= FPU_FPE2
;
1686 else if (arm_fpu_desc
->rev
== 3)
1687 arm_fpu_attr
= FPU_FPE3
;
1689 arm_fpu_attr
= FPU_FPA
;
1692 case ARM_FP_MODEL_MAVERICK
:
1693 arm_fpu_attr
= FPU_MAVERICK
;
1696 case ARM_FP_MODEL_VFP
:
1697 arm_fpu_attr
= FPU_VFP
;
1704 if (target_float_abi_name
!= NULL
)
1706 /* The user specified a FP ABI. */
1707 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1709 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1711 arm_float_abi
= all_float_abis
[i
].abi_type
;
1715 if (i
== ARRAY_SIZE (all_float_abis
))
1716 error ("invalid floating point abi: -mfloat-abi=%s",
1717 target_float_abi_name
);
1720 arm_float_abi
= TARGET_DEFAULT_FLOAT_ABI
;
1722 if (TARGET_AAPCS_BASED
1723 && (arm_fpu_desc
->model
== ARM_FP_MODEL_FPA
))
1724 error ("FPA is unsupported in the AAPCS");
1726 if (TARGET_AAPCS_BASED
)
1728 if (TARGET_CALLER_INTERWORKING
)
1729 error ("AAPCS does not support -mcaller-super-interworking");
1731 if (TARGET_CALLEE_INTERWORKING
)
1732 error ("AAPCS does not support -mcallee-super-interworking");
1735 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1736 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1737 will ever exist. GCC makes no attempt to support this combination. */
1738 if (TARGET_IWMMXT
&& !TARGET_SOFT_FLOAT
)
1739 sorry ("iWMMXt and hardware floating point");
1741 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1742 if (TARGET_THUMB2
&& TARGET_IWMMXT
)
1743 sorry ("Thumb-2 iWMMXt");
1745 /* __fp16 support currently assumes the core has ldrh. */
1746 if (!arm_arch4
&& arm_fp16_format
!= ARM_FP16_FORMAT_NONE
)
1747 sorry ("__fp16 and no ldrh");
1749 /* If soft-float is specified then don't use FPU. */
1750 if (TARGET_SOFT_FLOAT
)
1751 arm_fpu_attr
= FPU_NONE
;
1753 if (TARGET_AAPCS_BASED
)
1755 if (arm_abi
== ARM_ABI_IWMMXT
)
1756 arm_pcs_default
= ARM_PCS_AAPCS_IWMMXT
;
1757 else if (arm_float_abi
== ARM_FLOAT_ABI_HARD
1758 && TARGET_HARD_FLOAT
1760 arm_pcs_default
= ARM_PCS_AAPCS_VFP
;
1762 arm_pcs_default
= ARM_PCS_AAPCS
;
1766 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
&& TARGET_VFP
)
1767 sorry ("-mfloat-abi=hard and VFP");
1769 if (arm_abi
== ARM_ABI_APCS
)
1770 arm_pcs_default
= ARM_PCS_APCS
;
1772 arm_pcs_default
= ARM_PCS_ATPCS
;
1775 /* For arm2/3 there is no need to do any scheduling if there is only
1776 a floating point emulator, or we are doing software floating-point. */
1777 if ((TARGET_SOFT_FLOAT
1778 || (TARGET_FPA
&& arm_fpu_desc
->rev
))
1779 && (tune_flags
& FL_MODE32
) == 0)
1780 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1782 if (target_thread_switch
)
1784 if (strcmp (target_thread_switch
, "soft") == 0)
1785 target_thread_pointer
= TP_SOFT
;
1786 else if (strcmp (target_thread_switch
, "auto") == 0)
1787 target_thread_pointer
= TP_AUTO
;
1788 else if (strcmp (target_thread_switch
, "cp15") == 0)
1789 target_thread_pointer
= TP_CP15
;
1791 error ("invalid thread pointer option: -mtp=%s", target_thread_switch
);
1794 /* Use the cp15 method if it is available. */
1795 if (target_thread_pointer
== TP_AUTO
)
1797 if (arm_arch6k
&& !TARGET_THUMB1
)
1798 target_thread_pointer
= TP_CP15
;
1800 target_thread_pointer
= TP_SOFT
;
1803 if (TARGET_HARD_TP
&& TARGET_THUMB1
)
1804 error ("can not use -mtp=cp15 with 16-bit Thumb");
1806 /* Override the default structure alignment for AAPCS ABI. */
1807 if (TARGET_AAPCS_BASED
)
1808 arm_structure_size_boundary
= 8;
1810 if (structure_size_string
!= NULL
)
1812 int size
= strtol (structure_size_string
, NULL
, 0);
1814 if (size
== 8 || size
== 32
1815 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1816 arm_structure_size_boundary
= size
;
1818 warning (0, "structure size boundary can only be set to %s",
1819 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1822 if (!TARGET_ARM
&& TARGET_VXWORKS_RTP
&& flag_pic
)
1824 error ("RTP PIC is incompatible with Thumb");
1828 /* If stack checking is disabled, we can use r10 as the PIC register,
1829 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1830 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
1832 if (TARGET_VXWORKS_RTP
)
1833 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
1834 arm_pic_register
= (TARGET_APCS_STACK
|| TARGET_AAPCS_BASED
) ? 9 : 10;
1837 if (flag_pic
&& TARGET_VXWORKS_RTP
)
1838 arm_pic_register
= 9;
1840 if (arm_pic_register_string
!= NULL
)
1842 int pic_register
= decode_reg_name (arm_pic_register_string
);
1845 warning (0, "-mpic-register= is useless without -fpic");
1847 /* Prevent the user from choosing an obviously stupid PIC register. */
1848 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1849 || pic_register
== HARD_FRAME_POINTER_REGNUM
1850 || pic_register
== STACK_POINTER_REGNUM
1851 || pic_register
>= PC_REGNUM
1852 || (TARGET_VXWORKS_RTP
1853 && (unsigned int) pic_register
!= arm_pic_register
))
1854 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1856 arm_pic_register
= pic_register
;
1859 /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
1860 if (fix_cm3_ldrd
== 2)
1862 if (selected_cpu
== cortexm3
)
1868 if (TARGET_THUMB1
&& flag_schedule_insns
)
1870 /* Don't warn since it's on by default in -O2. */
1871 flag_schedule_insns
= 0;
1876 /* If optimizing for size, bump the number of instructions that we
1877 are prepared to conditionally execute (even on a StrongARM). */
1878 max_insns_skipped
= 6;
1882 /* StrongARM has early execution of branches, so a sequence
1883 that is worth skipping is shorter. */
1884 if (arm_tune_strongarm
)
1885 max_insns_skipped
= 3;
1888 /* Hot/Cold partitioning is not currently supported, since we can't
1889 handle literal pool placement in that case. */
1890 if (flag_reorder_blocks_and_partition
)
1892 inform (input_location
,
1893 "-freorder-blocks-and-partition not supported on this architecture");
1894 flag_reorder_blocks_and_partition
= 0;
1895 flag_reorder_blocks
= 1;
1898 /* Register global variables with the garbage collector. */
1899 arm_add_gc_roots ();
1903 arm_add_gc_roots (void)
1905 gcc_obstack_init(&minipool_obstack
);
1906 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1909 /* A table of known ARM exception types.
1910 For use with the interrupt function attribute. */
1914 const char *const arg
;
1915 const unsigned long return_value
;
1919 static const isr_attribute_arg isr_attribute_args
[] =
1921 { "IRQ", ARM_FT_ISR
},
1922 { "irq", ARM_FT_ISR
},
1923 { "FIQ", ARM_FT_FIQ
},
1924 { "fiq", ARM_FT_FIQ
},
1925 { "ABORT", ARM_FT_ISR
},
1926 { "abort", ARM_FT_ISR
},
1927 { "ABORT", ARM_FT_ISR
},
1928 { "abort", ARM_FT_ISR
},
1929 { "UNDEF", ARM_FT_EXCEPTION
},
1930 { "undef", ARM_FT_EXCEPTION
},
1931 { "SWI", ARM_FT_EXCEPTION
},
1932 { "swi", ARM_FT_EXCEPTION
},
1933 { NULL
, ARM_FT_NORMAL
}
1936 /* Returns the (interrupt) function type of the current
1937 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1939 static unsigned long
1940 arm_isr_value (tree argument
)
1942 const isr_attribute_arg
* ptr
;
1946 return ARM_FT_NORMAL
| ARM_FT_STACKALIGN
;
1948 /* No argument - default to IRQ. */
1949 if (argument
== NULL_TREE
)
1952 /* Get the value of the argument. */
1953 if (TREE_VALUE (argument
) == NULL_TREE
1954 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1955 return ARM_FT_UNKNOWN
;
1957 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1959 /* Check it against the list of known arguments. */
1960 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1961 if (streq (arg
, ptr
->arg
))
1962 return ptr
->return_value
;
1964 /* An unrecognized interrupt type. */
1965 return ARM_FT_UNKNOWN
;
1968 /* Computes the type of the current function. */
1970 static unsigned long
1971 arm_compute_func_type (void)
1973 unsigned long type
= ARM_FT_UNKNOWN
;
1977 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
1979 /* Decide if the current function is volatile. Such functions
1980 never return, and many memory cycles can be saved by not storing
1981 register values that will never be needed again. This optimization
1982 was added to speed up context switching in a kernel application. */
1984 && (TREE_NOTHROW (current_function_decl
)
1985 || !(flag_unwind_tables
1986 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
)))
1987 && TREE_THIS_VOLATILE (current_function_decl
))
1988 type
|= ARM_FT_VOLATILE
;
1990 if (cfun
->static_chain_decl
!= NULL
)
1991 type
|= ARM_FT_NESTED
;
1993 attr
= DECL_ATTRIBUTES (current_function_decl
);
1995 a
= lookup_attribute ("naked", attr
);
1997 type
|= ARM_FT_NAKED
;
1999 a
= lookup_attribute ("isr", attr
);
2001 a
= lookup_attribute ("interrupt", attr
);
2004 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
2006 type
|= arm_isr_value (TREE_VALUE (a
));
2011 /* Returns the type of the current function. */
2014 arm_current_func_type (void)
2016 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
2017 cfun
->machine
->func_type
= arm_compute_func_type ();
2019 return cfun
->machine
->func_type
;
2023 arm_allocate_stack_slots_for_args (void)
2025 /* Naked functions should not allocate stack slots for arguments. */
2026 return !IS_NAKED (arm_current_func_type ());
2030 /* Output assembler code for a block containing the constant parts
2031 of a trampoline, leaving space for the variable parts.
2033 On the ARM, (if r8 is the static chain regnum, and remembering that
2034 referencing pc adds an offset of 8) the trampoline looks like:
2037 .word static chain value
2038 .word function's address
2039 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
2042 arm_asm_trampoline_template (FILE *f
)
2046 asm_fprintf (f
, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM
, PC_REGNUM
);
2047 asm_fprintf (f
, "\tldr\t%r, [%r, #0]\n", PC_REGNUM
, PC_REGNUM
);
2049 else if (TARGET_THUMB2
)
2051 /* The Thumb-2 trampoline is similar to the arm implementation.
2052 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
2053 asm_fprintf (f
, "\tldr.w\t%r, [%r, #4]\n",
2054 STATIC_CHAIN_REGNUM
, PC_REGNUM
);
2055 asm_fprintf (f
, "\tldr.w\t%r, [%r, #4]\n", PC_REGNUM
, PC_REGNUM
);
2059 ASM_OUTPUT_ALIGN (f
, 2);
2060 fprintf (f
, "\t.code\t16\n");
2061 fprintf (f
, ".Ltrampoline_start:\n");
2062 asm_fprintf (f
, "\tpush\t{r0, r1}\n");
2063 asm_fprintf (f
, "\tldr\tr0, [%r, #8]\n", PC_REGNUM
);
2064 asm_fprintf (f
, "\tmov\t%r, r0\n", STATIC_CHAIN_REGNUM
);
2065 asm_fprintf (f
, "\tldr\tr0, [%r, #8]\n", PC_REGNUM
);
2066 asm_fprintf (f
, "\tstr\tr0, [%r, #4]\n", SP_REGNUM
);
2067 asm_fprintf (f
, "\tpop\t{r0, %r}\n", PC_REGNUM
);
2069 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
2070 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
2073 /* Emit RTL insns to initialize the variable parts of a trampoline. */
2076 arm_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2078 rtx fnaddr
, mem
, a_tramp
;
2080 emit_block_move (m_tramp
, assemble_trampoline_template (),
2081 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
2083 mem
= adjust_address (m_tramp
, SImode
, TARGET_32BIT
? 8 : 12);
2084 emit_move_insn (mem
, chain_value
);
2086 mem
= adjust_address (m_tramp
, SImode
, TARGET_32BIT
? 12 : 16);
2087 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2088 emit_move_insn (mem
, fnaddr
);
2090 a_tramp
= XEXP (m_tramp
, 0);
2091 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__clear_cache"),
2092 LCT_NORMAL
, VOIDmode
, 2, a_tramp
, Pmode
,
2093 plus_constant (a_tramp
, TRAMPOLINE_SIZE
), Pmode
);
2096 /* Thumb trampolines should be entered in thumb mode, so set
2097 the bottom bit of the address. */
2100 arm_trampoline_adjust_address (rtx addr
)
2103 addr
= expand_simple_binop (Pmode
, IOR
, addr
, const1_rtx
,
2104 NULL
, 0, OPTAB_LIB_WIDEN
);
2108 /* Return 1 if it is possible to return using a single instruction.
2109 If SIBLING is non-null, this is a test for a return before a sibling
2110 call. SIBLING is the call insn, so we can examine its register usage. */
2113 use_return_insn (int iscond
, rtx sibling
)
2116 unsigned int func_type
;
2117 unsigned long saved_int_regs
;
2118 unsigned HOST_WIDE_INT stack_adjust
;
2119 arm_stack_offsets
*offsets
;
2121 /* Never use a return instruction before reload has run. */
2122 if (!reload_completed
)
2125 func_type
= arm_current_func_type ();
2127 /* Naked, volatile and stack alignment functions need special
2129 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
| ARM_FT_STACKALIGN
))
2132 /* So do interrupt functions that use the frame pointer and Thumb
2133 interrupt functions. */
2134 if (IS_INTERRUPT (func_type
) && (frame_pointer_needed
|| TARGET_THUMB
))
2137 offsets
= arm_get_frame_offsets ();
2138 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
2140 /* As do variadic functions. */
2141 if (crtl
->args
.pretend_args_size
2142 || cfun
->machine
->uses_anonymous_args
2143 /* Or if the function calls __builtin_eh_return () */
2144 || crtl
->calls_eh_return
2145 /* Or if the function calls alloca */
2146 || cfun
->calls_alloca
2147 /* Or if there is a stack adjustment. However, if the stack pointer
2148 is saved on the stack, we can use a pre-incrementing stack load. */
2149 || !(stack_adjust
== 0 || (TARGET_APCS_FRAME
&& frame_pointer_needed
2150 && stack_adjust
== 4)))
2153 saved_int_regs
= offsets
->saved_regs_mask
;
2155 /* Unfortunately, the insn
2157 ldmib sp, {..., sp, ...}
2159 triggers a bug on most SA-110 based devices, such that the stack
2160 pointer won't be correctly restored if the instruction takes a
2161 page fault. We work around this problem by popping r3 along with
2162 the other registers, since that is never slower than executing
2163 another instruction.
2165 We test for !arm_arch5 here, because code for any architecture
2166 less than this could potentially be run on one of the buggy
2168 if (stack_adjust
== 4 && !arm_arch5
&& TARGET_ARM
)
2170 /* Validate that r3 is a call-clobbered register (always true in
2171 the default abi) ... */
2172 if (!call_used_regs
[3])
2175 /* ... that it isn't being used for a return value ... */
2176 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
2179 /* ... or for a tail-call argument ... */
2182 gcc_assert (GET_CODE (sibling
) == CALL_INSN
);
2184 if (find_regno_fusage (sibling
, USE
, 3))
2188 /* ... and that there are no call-saved registers in r0-r2
2189 (always true in the default ABI). */
2190 if (saved_int_regs
& 0x7)
2194 /* Can't be done if interworking with Thumb, and any registers have been
2196 if (TARGET_INTERWORK
&& saved_int_regs
!= 0 && !IS_INTERRUPT(func_type
))
2199 /* On StrongARM, conditional returns are expensive if they aren't
2200 taken and multiple registers have been stacked. */
2201 if (iscond
&& arm_tune_strongarm
)
2203 /* Conditional return when just the LR is stored is a simple
2204 conditional-load instruction, that's not expensive. */
2205 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
2209 && arm_pic_register
!= INVALID_REGNUM
2210 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
2214 /* If there are saved registers but the LR isn't saved, then we need
2215 two instructions for the return. */
2216 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
2219 /* Can't be done if any of the FPA regs are pushed,
2220 since this also requires an insn. */
2221 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
2222 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
2223 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
2226 /* Likewise VFP regs. */
2227 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
2228 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
2229 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
2232 if (TARGET_REALLY_IWMMXT
)
2233 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
2234 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
2240 /* Return TRUE if int I is a valid immediate ARM constant. */
2243 const_ok_for_arm (HOST_WIDE_INT i
)
2247 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
2248 be all zero, or all one. */
2249 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
2250 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
2251 != ((~(unsigned HOST_WIDE_INT
) 0)
2252 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
2255 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
2257 /* Fast return for 0 and small values. We must do this for zero, since
2258 the code below can't handle that one case. */
2259 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
2262 /* Get the number of trailing zeros. */
2263 lowbit
= ffs((int) i
) - 1;
2265 /* Only even shifts are allowed in ARM mode so round down to the
2266 nearest even number. */
2270 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
2275 /* Allow rotated constants in ARM mode. */
2277 && ((i
& ~0xc000003f) == 0
2278 || (i
& ~0xf000000f) == 0
2279 || (i
& ~0xfc000003) == 0))
2286 /* Allow repeated pattern. */
2289 if (i
== v
|| i
== (v
| (v
<< 8)))
2296 /* Return true if I is a valid constant for the operation CODE. */
2298 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
2300 if (const_ok_for_arm (i
))
2324 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
2326 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
2332 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
2336 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
2343 /* Emit a sequence of insns to handle a large constant.
2344 CODE is the code of the operation required, it can be any of SET, PLUS,
2345 IOR, AND, XOR, MINUS;
2346 MODE is the mode in which the operation is being performed;
2347 VAL is the integer to operate on;
2348 SOURCE is the other operand (a register, or a null-pointer for SET);
2349 SUBTARGETS means it is safe to create scratch registers if that will
2350 either produce a simpler sequence, or we will want to cse the values.
2351 Return value is the number of insns emitted. */
2353 /* ??? Tweak this for thumb2. */
2355 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
2356 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
2360 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
2361 cond
= COND_EXEC_TEST (PATTERN (insn
));
2365 if (subtargets
|| code
== SET
2366 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
2367 && REGNO (target
) != REGNO (source
)))
2369 /* After arm_reorg has been called, we can't fix up expensive
2370 constants by pushing them into memory so we must synthesize
2371 them in-line, regardless of the cost. This is only likely to
2372 be more costly on chips that have load delay slots and we are
2373 compiling without running the scheduler (so no splitting
2374 occurred before the final instruction emission).
2376 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
2378 if (!after_arm_reorg
2380 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
2382 > (arm_constant_limit (optimize_function_for_size_p (cfun
))
2387 /* Currently SET is the only monadic value for CODE, all
2388 the rest are diadic. */
2389 if (TARGET_USE_MOVT
)
2390 arm_emit_movpair (target
, GEN_INT (val
));
2392 emit_set_insn (target
, GEN_INT (val
));
2398 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
2400 if (TARGET_USE_MOVT
)
2401 arm_emit_movpair (temp
, GEN_INT (val
));
2403 emit_set_insn (temp
, GEN_INT (val
));
2405 /* For MINUS, the value is subtracted from, since we never
2406 have subtraction of a constant. */
2408 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
2410 emit_set_insn (target
,
2411 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
2417 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
2421 /* Return the number of instructions required to synthesize the given
2422 constant, if we start emitting them from bit-position I. */
2424 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
2426 HOST_WIDE_INT temp1
;
2427 int step_size
= TARGET_ARM
? 2 : 1;
2430 gcc_assert (TARGET_ARM
|| i
== 0);
2438 if (remainder
& (((1 << step_size
) - 1) << (i
- step_size
)))
2443 temp1
= remainder
& ((0x0ff << end
)
2444 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2445 remainder
&= ~temp1
;
2450 } while (remainder
);
2455 find_best_start (unsigned HOST_WIDE_INT remainder
)
2457 int best_consecutive_zeros
= 0;
2461 /* If we aren't targetting ARM, the best place to start is always at
2466 for (i
= 0; i
< 32; i
+= 2)
2468 int consecutive_zeros
= 0;
2470 if (!(remainder
& (3 << i
)))
2472 while ((i
< 32) && !(remainder
& (3 << i
)))
2474 consecutive_zeros
+= 2;
2477 if (consecutive_zeros
> best_consecutive_zeros
)
2479 best_consecutive_zeros
= consecutive_zeros
;
2480 best_start
= i
- consecutive_zeros
;
2486 /* So long as it won't require any more insns to do so, it's
2487 desirable to emit a small constant (in bits 0...9) in the last
2488 insn. This way there is more chance that it can be combined with
2489 a later addressing insn to form a pre-indexed load or store
2490 operation. Consider:
2492 *((volatile int *)0xe0000100) = 1;
2493 *((volatile int *)0xe0000110) = 2;
2495 We want this to wind up as:
2499 str rB, [rA, #0x100]
2501 str rB, [rA, #0x110]
2503 rather than having to synthesize both large constants from scratch.
2505 Therefore, we calculate how many insns would be required to emit
2506 the constant starting from `best_start', and also starting from
2507 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2508 yield a shorter sequence, we may as well use zero. */
2510 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2511 && (count_insns_for_constant (remainder
, 0) <=
2512 count_insns_for_constant (remainder
, best_start
)))
2518 /* Emit an instruction with the indicated PATTERN. If COND is
2519 non-NULL, conditionalize the execution of the instruction on COND
2523 emit_constant_insn (rtx cond
, rtx pattern
)
2526 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
2527 emit_insn (pattern
);
2530 /* As above, but extra parameter GENERATE which, if clear, suppresses
2532 /* ??? This needs more work for thumb2. */
2535 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
2536 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
2541 int final_invert
= 0;
2542 int can_negate_initial
= 0;
2544 int num_bits_set
= 0;
2545 int set_sign_bit_copies
= 0;
2546 int clear_sign_bit_copies
= 0;
2547 int clear_zero_bit_copies
= 0;
2548 int set_zero_bit_copies
= 0;
2550 unsigned HOST_WIDE_INT temp1
, temp2
;
2551 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
2552 int step_size
= TARGET_ARM
? 2 : 1;
2554 /* Find out which operations are safe for a given CODE. Also do a quick
2555 check for degenerate cases; these can occur when DImode operations
2566 can_negate_initial
= 1;
2570 if (remainder
== 0xffffffff)
2573 emit_constant_insn (cond
,
2574 gen_rtx_SET (VOIDmode
, target
,
2575 GEN_INT (ARM_SIGN_EXTEND (val
))));
2581 if (reload_completed
&& rtx_equal_p (target
, source
))
2585 emit_constant_insn (cond
,
2586 gen_rtx_SET (VOIDmode
, target
, source
));
2598 emit_constant_insn (cond
,
2599 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
2602 if (remainder
== 0xffffffff)
2604 if (reload_completed
&& rtx_equal_p (target
, source
))
2607 emit_constant_insn (cond
,
2608 gen_rtx_SET (VOIDmode
, target
, source
));
2617 if (reload_completed
&& rtx_equal_p (target
, source
))
2620 emit_constant_insn (cond
,
2621 gen_rtx_SET (VOIDmode
, target
, source
));
2625 if (remainder
== 0xffffffff)
2628 emit_constant_insn (cond
,
2629 gen_rtx_SET (VOIDmode
, target
,
2630 gen_rtx_NOT (mode
, source
)));
2636 /* We treat MINUS as (val - source), since (source - val) is always
2637 passed as (source + (-val)). */
2641 emit_constant_insn (cond
,
2642 gen_rtx_SET (VOIDmode
, target
,
2643 gen_rtx_NEG (mode
, source
)));
2646 if (const_ok_for_arm (val
))
2649 emit_constant_insn (cond
,
2650 gen_rtx_SET (VOIDmode
, target
,
2651 gen_rtx_MINUS (mode
, GEN_INT (val
),
2663 /* If we can do it in one insn get out quickly. */
2664 if (const_ok_for_arm (val
)
2665 || (can_negate_initial
&& const_ok_for_arm (-val
))
2666 || (can_invert
&& const_ok_for_arm (~val
)))
2669 emit_constant_insn (cond
,
2670 gen_rtx_SET (VOIDmode
, target
,
2672 ? gen_rtx_fmt_ee (code
, mode
, source
,
2678 /* Calculate a few attributes that may be useful for specific
2680 /* Count number of leading zeros. */
2681 for (i
= 31; i
>= 0; i
--)
2683 if ((remainder
& (1 << i
)) == 0)
2684 clear_sign_bit_copies
++;
2689 /* Count number of leading 1's. */
2690 for (i
= 31; i
>= 0; i
--)
2692 if ((remainder
& (1 << i
)) != 0)
2693 set_sign_bit_copies
++;
2698 /* Count number of trailing zero's. */
2699 for (i
= 0; i
<= 31; i
++)
2701 if ((remainder
& (1 << i
)) == 0)
2702 clear_zero_bit_copies
++;
2707 /* Count number of trailing 1's. */
2708 for (i
= 0; i
<= 31; i
++)
2710 if ((remainder
& (1 << i
)) != 0)
2711 set_zero_bit_copies
++;
2719 /* See if we can use movw. */
2720 if (arm_arch_thumb2
&& (remainder
& 0xffff0000) == 0)
2723 emit_constant_insn (cond
, gen_rtx_SET (VOIDmode
, target
,
2728 /* See if we can do this by sign_extending a constant that is known
2729 to be negative. This is a good, way of doing it, since the shift
2730 may well merge into a subsequent insn. */
2731 if (set_sign_bit_copies
> 1)
2733 if (const_ok_for_arm
2734 (temp1
= ARM_SIGN_EXTEND (remainder
2735 << (set_sign_bit_copies
- 1))))
2739 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2740 emit_constant_insn (cond
,
2741 gen_rtx_SET (VOIDmode
, new_src
,
2743 emit_constant_insn (cond
,
2744 gen_ashrsi3 (target
, new_src
,
2745 GEN_INT (set_sign_bit_copies
- 1)));
2749 /* For an inverted constant, we will need to set the low bits,
2750 these will be shifted out of harm's way. */
2751 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
2752 if (const_ok_for_arm (~temp1
))
2756 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2757 emit_constant_insn (cond
,
2758 gen_rtx_SET (VOIDmode
, new_src
,
2760 emit_constant_insn (cond
,
2761 gen_ashrsi3 (target
, new_src
,
2762 GEN_INT (set_sign_bit_copies
- 1)));
2768 /* See if we can calculate the value as the difference between two
2769 valid immediates. */
2770 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
2772 int topshift
= clear_sign_bit_copies
& ~1;
2774 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
2775 & (0xff000000 >> topshift
));
2777 /* If temp1 is zero, then that means the 9 most significant
2778 bits of remainder were 1 and we've caused it to overflow.
2779 When topshift is 0 we don't need to do anything since we
2780 can borrow from 'bit 32'. */
2781 if (temp1
== 0 && topshift
!= 0)
2782 temp1
= 0x80000000 >> (topshift
- 1);
2784 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
2786 if (const_ok_for_arm (temp2
))
2790 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2791 emit_constant_insn (cond
,
2792 gen_rtx_SET (VOIDmode
, new_src
,
2794 emit_constant_insn (cond
,
2795 gen_addsi3 (target
, new_src
,
2803 /* See if we can generate this by setting the bottom (or the top)
2804 16 bits, and then shifting these into the other half of the
2805 word. We only look for the simplest cases, to do more would cost
2806 too much. Be careful, however, not to generate this when the
2807 alternative would take fewer insns. */
2808 if (val
& 0xffff0000)
2810 temp1
= remainder
& 0xffff0000;
2811 temp2
= remainder
& 0x0000ffff;
2813 /* Overlaps outside this range are best done using other methods. */
2814 for (i
= 9; i
< 24; i
++)
2816 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
2817 && !const_ok_for_arm (temp2
))
2819 rtx new_src
= (subtargets
2820 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2822 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
2823 source
, subtargets
, generate
);
2831 gen_rtx_ASHIFT (mode
, source
,
2838 /* Don't duplicate cases already considered. */
2839 for (i
= 17; i
< 24; i
++)
2841 if (((temp1
| (temp1
>> i
)) == remainder
)
2842 && !const_ok_for_arm (temp1
))
2844 rtx new_src
= (subtargets
2845 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
2847 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
2848 source
, subtargets
, generate
);
2853 gen_rtx_SET (VOIDmode
, target
,
2856 gen_rtx_LSHIFTRT (mode
, source
,
2867 /* If we have IOR or XOR, and the constant can be loaded in a
2868 single instruction, and we can find a temporary to put it in,
2869 then this can be done in two instructions instead of 3-4. */
2871 /* TARGET can't be NULL if SUBTARGETS is 0 */
2872 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
2874 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
2878 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2880 emit_constant_insn (cond
,
2881 gen_rtx_SET (VOIDmode
, sub
,
2883 emit_constant_insn (cond
,
2884 gen_rtx_SET (VOIDmode
, target
,
2885 gen_rtx_fmt_ee (code
, mode
,
2896 x = y | constant ( which is composed of set_sign_bit_copies of leading 1s
2897 and the remainder 0s for e.g. 0xfff00000)
2898 x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies)
2900 This can be done in 2 instructions by using shifts with mov or mvn.
2905 mvn r0, r0, lsr #12 */
2906 if (set_sign_bit_copies
> 8
2907 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
2911 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2912 rtx shift
= GEN_INT (set_sign_bit_copies
);
2916 gen_rtx_SET (VOIDmode
, sub
,
2918 gen_rtx_ASHIFT (mode
,
2923 gen_rtx_SET (VOIDmode
, target
,
2925 gen_rtx_LSHIFTRT (mode
, sub
,
2932 x = y | constant (which has set_zero_bit_copies number of trailing ones).
2934 x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies).
2936 For eg. r0 = r0 | 0xfff
2941 if (set_zero_bit_copies
> 8
2942 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
2946 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2947 rtx shift
= GEN_INT (set_zero_bit_copies
);
2951 gen_rtx_SET (VOIDmode
, sub
,
2953 gen_rtx_LSHIFTRT (mode
,
2958 gen_rtx_SET (VOIDmode
, target
,
2960 gen_rtx_ASHIFT (mode
, sub
,
2966 /* This will never be reached for Thumb2 because orn is a valid
2967 instruction. This is for Thumb1 and the ARM 32 bit cases.
2969 x = y | constant (such that ~constant is a valid constant)
2971 x = ~(~y & ~constant).
2973 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
2977 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
2978 emit_constant_insn (cond
,
2979 gen_rtx_SET (VOIDmode
, sub
,
2980 gen_rtx_NOT (mode
, source
)));
2983 sub
= gen_reg_rtx (mode
);
2984 emit_constant_insn (cond
,
2985 gen_rtx_SET (VOIDmode
, sub
,
2986 gen_rtx_AND (mode
, source
,
2988 emit_constant_insn (cond
,
2989 gen_rtx_SET (VOIDmode
, target
,
2990 gen_rtx_NOT (mode
, sub
)));
2997 /* See if two shifts will do 2 or more insn's worth of work. */
2998 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
3000 HOST_WIDE_INT shift_mask
= ((0xffffffff
3001 << (32 - clear_sign_bit_copies
))
3004 if ((remainder
| shift_mask
) != 0xffffffff)
3008 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3009 insns
= arm_gen_constant (AND
, mode
, cond
,
3010 remainder
| shift_mask
,
3011 new_src
, source
, subtargets
, 1);
3016 rtx targ
= subtargets
? NULL_RTX
: target
;
3017 insns
= arm_gen_constant (AND
, mode
, cond
,
3018 remainder
| shift_mask
,
3019 targ
, source
, subtargets
, 0);
3025 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3026 rtx shift
= GEN_INT (clear_sign_bit_copies
);
3028 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
3029 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
3035 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
3037 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
3039 if ((remainder
| shift_mask
) != 0xffffffff)
3043 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3045 insns
= arm_gen_constant (AND
, mode
, cond
,
3046 remainder
| shift_mask
,
3047 new_src
, source
, subtargets
, 1);
3052 rtx targ
= subtargets
? NULL_RTX
: target
;
3054 insns
= arm_gen_constant (AND
, mode
, cond
,
3055 remainder
| shift_mask
,
3056 targ
, source
, subtargets
, 0);
3062 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
3063 rtx shift
= GEN_INT (clear_zero_bit_copies
);
3065 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
3066 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
3078 for (i
= 0; i
< 32; i
++)
3079 if (remainder
& (1 << i
))
3083 || (code
!= IOR
&& can_invert
&& num_bits_set
> 16))
3084 remainder
^= 0xffffffff;
3085 else if (code
== PLUS
&& num_bits_set
> 16)
3086 remainder
= (-remainder
) & 0xffffffff;
3088 /* For XOR, if more than half the bits are set and there's a sequence
3089 of more than 8 consecutive ones in the pattern then we can XOR by the
3090 inverted constant and then invert the final result; this may save an
3091 instruction and might also lead to the final mvn being merged with
3092 some other operation. */
3093 else if (code
== XOR
&& num_bits_set
> 16
3094 && (count_insns_for_constant (remainder
^ 0xffffffff,
3096 (remainder
^ 0xffffffff))
3097 < count_insns_for_constant (remainder
,
3098 find_best_start (remainder
))))
3100 remainder
^= 0xffffffff;
3109 /* Now try and find a way of doing the job in either two or three
3111 We start by looking for the largest block of zeros that are aligned on
3112 a 2-bit boundary, we then fill up the temps, wrapping around to the
3113 top of the word when we drop off the bottom.
3114 In the worst case this code should produce no more than four insns.
3115 Thumb-2 constants are shifted, not rotated, so the MSB is always the
3116 best place to start. */
3118 /* ??? Use thumb2 replicated constants when the high and low halfwords are
3121 /* Now start emitting the insns. */
3122 i
= find_best_start (remainder
);
3129 if (remainder
& (3 << (i
- 2)))
3134 temp1
= remainder
& ((0x0ff << end
)
3135 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
3136 remainder
&= ~temp1
;
3140 rtx new_src
, temp1_rtx
;
3142 if (code
== SET
|| code
== MINUS
)
3144 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
3145 if (can_invert
&& code
!= MINUS
)
3150 if ((final_invert
|| remainder
) && subtargets
)
3151 new_src
= gen_reg_rtx (mode
);
3156 else if (can_negate
)
3160 temp1
= trunc_int_for_mode (temp1
, mode
);
3161 temp1_rtx
= GEN_INT (temp1
);
3165 else if (code
== MINUS
)
3166 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
3168 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
3170 emit_constant_insn (cond
,
3171 gen_rtx_SET (VOIDmode
, new_src
,
3181 else if (code
== MINUS
)
3187 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
3197 emit_constant_insn (cond
, gen_rtx_SET (VOIDmode
, target
,
3198 gen_rtx_NOT (mode
, source
)));
3205 /* Canonicalize a comparison so that we are more likely to recognize it.
3206 This can be done for a few constant compares, where we can make the
3207 immediate value easier to load. */
3210 arm_canonicalize_comparison (enum rtx_code code
, enum machine_mode mode
,
3213 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
3214 unsigned HOST_WIDE_INT maxval
;
3215 maxval
= (((unsigned HOST_WIDE_INT
) 1) << (GET_MODE_BITSIZE(mode
) - 1)) - 1;
3226 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
3228 *op1
= GEN_INT (i
+ 1);
3229 return code
== GT
? GE
: LT
;
3236 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
3238 *op1
= GEN_INT (i
- 1);
3239 return code
== GE
? GT
: LE
;
3245 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
3246 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
3248 *op1
= GEN_INT (i
+ 1);
3249 return code
== GTU
? GEU
: LTU
;
3256 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
3258 *op1
= GEN_INT (i
- 1);
3259 return code
== GEU
? GTU
: LEU
;
3271 /* Define how to find the value returned by a function. */
3274 arm_function_value(const_tree type
, const_tree func
,
3275 bool outgoing ATTRIBUTE_UNUSED
)
3277 enum machine_mode mode
;
3278 int unsignedp ATTRIBUTE_UNUSED
;
3279 rtx r ATTRIBUTE_UNUSED
;
3281 mode
= TYPE_MODE (type
);
3283 if (TARGET_AAPCS_BASED
)
3284 return aapcs_allocate_return_reg (mode
, type
, func
);
3286 /* Promote integer types. */
3287 if (INTEGRAL_TYPE_P (type
))
3288 mode
= arm_promote_function_mode (type
, mode
, &unsignedp
, func
, 1);
3290 /* Promotes small structs returned in a register to full-word size
3291 for big-endian AAPCS. */
3292 if (arm_return_in_msb (type
))
3294 HOST_WIDE_INT size
= int_size_in_bytes (type
);
3295 if (size
% UNITS_PER_WORD
!= 0)
3297 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
3298 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
3302 return LIBCALL_VALUE (mode
);
3306 libcall_eq (const void *p1
, const void *p2
)
3308 return rtx_equal_p ((const_rtx
) p1
, (const_rtx
) p2
);
3312 libcall_hash (const void *p1
)
3314 return hash_rtx ((const_rtx
) p1
, VOIDmode
, NULL
, NULL
, FALSE
);
3318 add_libcall (htab_t htab
, rtx libcall
)
3320 *htab_find_slot (htab
, libcall
, INSERT
) = libcall
;
3324 arm_libcall_uses_aapcs_base (const_rtx libcall
)
3326 static bool init_done
= false;
3327 static htab_t libcall_htab
;
3333 libcall_htab
= htab_create (31, libcall_hash
, libcall_eq
,
3335 add_libcall (libcall_htab
,
3336 convert_optab_libfunc (sfloat_optab
, SFmode
, SImode
));
3337 add_libcall (libcall_htab
,
3338 convert_optab_libfunc (sfloat_optab
, DFmode
, SImode
));
3339 add_libcall (libcall_htab
,
3340 convert_optab_libfunc (sfloat_optab
, SFmode
, DImode
));
3341 add_libcall (libcall_htab
,
3342 convert_optab_libfunc (sfloat_optab
, DFmode
, DImode
));
3344 add_libcall (libcall_htab
,
3345 convert_optab_libfunc (ufloat_optab
, SFmode
, SImode
));
3346 add_libcall (libcall_htab
,
3347 convert_optab_libfunc (ufloat_optab
, DFmode
, SImode
));
3348 add_libcall (libcall_htab
,
3349 convert_optab_libfunc (ufloat_optab
, SFmode
, DImode
));
3350 add_libcall (libcall_htab
,
3351 convert_optab_libfunc (ufloat_optab
, DFmode
, DImode
));
3353 add_libcall (libcall_htab
,
3354 convert_optab_libfunc (sext_optab
, SFmode
, HFmode
));
3355 add_libcall (libcall_htab
,
3356 convert_optab_libfunc (trunc_optab
, HFmode
, SFmode
));
3357 add_libcall (libcall_htab
,
3358 convert_optab_libfunc (sfix_optab
, DImode
, DFmode
));
3359 add_libcall (libcall_htab
,
3360 convert_optab_libfunc (ufix_optab
, DImode
, DFmode
));
3361 add_libcall (libcall_htab
,
3362 convert_optab_libfunc (sfix_optab
, DImode
, SFmode
));
3363 add_libcall (libcall_htab
,
3364 convert_optab_libfunc (ufix_optab
, DImode
, SFmode
));
3367 return libcall
&& htab_find (libcall_htab
, libcall
) != NULL
;
3371 arm_libcall_value (enum machine_mode mode
, const_rtx libcall
)
3373 if (TARGET_AAPCS_BASED
&& arm_pcs_default
!= ARM_PCS_AAPCS
3374 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3376 /* The following libcalls return their result in integer registers,
3377 even though they return a floating point value. */
3378 if (arm_libcall_uses_aapcs_base (libcall
))
3379 return gen_rtx_REG (mode
, ARG_REGISTER(1));
3383 return LIBCALL_VALUE (mode
);
3386 /* Determine the amount of memory needed to store the possible return
3387 registers of an untyped call. */
3389 arm_apply_result_size (void)
3395 if (TARGET_HARD_FLOAT_ABI
)
3401 if (TARGET_MAVERICK
)
3404 if (TARGET_IWMMXT_ABI
)
3411 /* Decide whether TYPE should be returned in memory (true)
3412 or in a register (false). FNTYPE is the type of the function making
3415 arm_return_in_memory (const_tree type
, const_tree fntype
)
3419 size
= int_size_in_bytes (type
); /* Negative if not fixed size. */
3421 if (TARGET_AAPCS_BASED
)
3423 /* Simple, non-aggregate types (ie not including vectors and
3424 complex) are always returned in a register (or registers).
3425 We don't care about which register here, so we can short-cut
3426 some of the detail. */
3427 if (!AGGREGATE_TYPE_P (type
)
3428 && TREE_CODE (type
) != VECTOR_TYPE
3429 && TREE_CODE (type
) != COMPLEX_TYPE
)
3432 /* Any return value that is no larger than one word can be
3434 if (((unsigned HOST_WIDE_INT
) size
) <= UNITS_PER_WORD
)
3437 /* Check any available co-processors to see if they accept the
3438 type as a register candidate (VFP, for example, can return
3439 some aggregates in consecutive registers). These aren't
3440 available if the call is variadic. */
3441 if (aapcs_select_return_coproc (type
, fntype
) >= 0)
3444 /* Vector values should be returned using ARM registers, not
3445 memory (unless they're over 16 bytes, which will break since
3446 we only have four call-clobbered registers to play with). */
3447 if (TREE_CODE (type
) == VECTOR_TYPE
)
3448 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
3450 /* The rest go in memory. */
3454 if (TREE_CODE (type
) == VECTOR_TYPE
)
3455 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
3457 if (!AGGREGATE_TYPE_P (type
) &&
3458 (TREE_CODE (type
) != VECTOR_TYPE
))
3459 /* All simple types are returned in registers. */
3462 if (arm_abi
!= ARM_ABI_APCS
)
3464 /* ATPCS and later return aggregate types in memory only if they are
3465 larger than a word (or are variable size). */
3466 return (size
< 0 || size
> UNITS_PER_WORD
);
3469 /* For the arm-wince targets we choose to be compatible with Microsoft's
3470 ARM and Thumb compilers, which always return aggregates in memory. */
3472 /* All structures/unions bigger than one word are returned in memory.
3473 Also catch the case where int_size_in_bytes returns -1. In this case
3474 the aggregate is either huge or of variable size, and in either case
3475 we will want to return it via memory and not in a register. */
3476 if (size
< 0 || size
> UNITS_PER_WORD
)
3479 if (TREE_CODE (type
) == RECORD_TYPE
)
3483 /* For a struct the APCS says that we only return in a register
3484 if the type is 'integer like' and every addressable element
3485 has an offset of zero. For practical purposes this means
3486 that the structure can have at most one non bit-field element
3487 and that this element must be the first one in the structure. */
3489 /* Find the first field, ignoring non FIELD_DECL things which will
3490 have been created by C++. */
3491 for (field
= TYPE_FIELDS (type
);
3492 field
&& TREE_CODE (field
) != FIELD_DECL
;
3493 field
= TREE_CHAIN (field
))
3497 return false; /* An empty structure. Allowed by an extension to ANSI C. */
3499 /* Check that the first field is valid for returning in a register. */
3501 /* ... Floats are not allowed */
3502 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
3505 /* ... Aggregates that are not themselves valid for returning in
3506 a register are not allowed. */
3507 if (arm_return_in_memory (TREE_TYPE (field
), NULL_TREE
))
3510 /* Now check the remaining fields, if any. Only bitfields are allowed,
3511 since they are not addressable. */
3512 for (field
= TREE_CHAIN (field
);
3514 field
= TREE_CHAIN (field
))
3516 if (TREE_CODE (field
) != FIELD_DECL
)
3519 if (!DECL_BIT_FIELD_TYPE (field
))
3526 if (TREE_CODE (type
) == UNION_TYPE
)
3530 /* Unions can be returned in registers if every element is
3531 integral, or can be returned in an integer register. */
3532 for (field
= TYPE_FIELDS (type
);
3534 field
= TREE_CHAIN (field
))
3536 if (TREE_CODE (field
) != FIELD_DECL
)
3539 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
3542 if (arm_return_in_memory (TREE_TYPE (field
), NULL_TREE
))
3548 #endif /* not ARM_WINCE */
3550 /* Return all other types in memory. */
3554 /* Indicate whether or not words of a double are in big-endian order. */
3557 arm_float_words_big_endian (void)
3559 if (TARGET_MAVERICK
)
3562 /* For FPA, float words are always big-endian. For VFP, floats words
3563 follow the memory system mode. */
3571 return (TARGET_BIG_END
? 1 : 0);
3576 const struct pcs_attribute_arg
3580 } pcs_attribute_args
[] =
3582 {"aapcs", ARM_PCS_AAPCS
},
3583 {"aapcs-vfp", ARM_PCS_AAPCS_VFP
},
3585 /* We could recognize these, but changes would be needed elsewhere
3586 * to implement them. */
3587 {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT
},
3588 {"atpcs", ARM_PCS_ATPCS
},
3589 {"apcs", ARM_PCS_APCS
},
3591 {NULL
, ARM_PCS_UNKNOWN
}
3595 arm_pcs_from_attribute (tree attr
)
3597 const struct pcs_attribute_arg
*ptr
;
3600 /* Get the value of the argument. */
3601 if (TREE_VALUE (attr
) == NULL_TREE
3602 || TREE_CODE (TREE_VALUE (attr
)) != STRING_CST
)
3603 return ARM_PCS_UNKNOWN
;
3605 arg
= TREE_STRING_POINTER (TREE_VALUE (attr
));
3607 /* Check it against the list of known arguments. */
3608 for (ptr
= pcs_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
3609 if (streq (arg
, ptr
->arg
))
3612 /* An unrecognized interrupt type. */
3613 return ARM_PCS_UNKNOWN
;
3616 /* Get the PCS variant to use for this call. TYPE is the function's type
3617 specification, DECL is the specific declartion. DECL may be null if
3618 the call could be indirect or if this is a library call. */
3620 arm_get_pcs_model (const_tree type
, const_tree decl
)
3622 bool user_convention
= false;
3623 enum arm_pcs user_pcs
= arm_pcs_default
;
3628 attr
= lookup_attribute ("pcs", TYPE_ATTRIBUTES (type
));
3631 user_pcs
= arm_pcs_from_attribute (TREE_VALUE (attr
));
3632 user_convention
= true;
3635 if (TARGET_AAPCS_BASED
)
3637 /* Detect varargs functions. These always use the base rules
3638 (no argument is ever a candidate for a co-processor
3640 bool base_rules
= (TYPE_ARG_TYPES (type
) != 0
3641 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (type
)))
3642 != void_type_node
));
3644 if (user_convention
)
3646 if (user_pcs
> ARM_PCS_AAPCS_LOCAL
)
3647 sorry ("Non-AAPCS derived PCS variant");
3648 else if (base_rules
&& user_pcs
!= ARM_PCS_AAPCS
)
3649 error ("Variadic functions must use the base AAPCS variant");
3653 return ARM_PCS_AAPCS
;
3654 else if (user_convention
)
3656 else if (decl
&& flag_unit_at_a_time
)
3658 /* Local functions never leak outside this compilation unit,
3659 so we are free to use whatever conventions are
3661 /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */
3662 struct cgraph_local_info
*i
= cgraph_local_info (CONST_CAST_TREE(decl
));
3664 return ARM_PCS_AAPCS_LOCAL
;
3667 else if (user_convention
&& user_pcs
!= arm_pcs_default
)
3668 sorry ("PCS variant");
3670 /* For everything else we use the target's default. */
3671 return arm_pcs_default
;
3676 aapcs_vfp_cum_init (CUMULATIVE_ARGS
*pcum ATTRIBUTE_UNUSED
,
3677 const_tree fntype ATTRIBUTE_UNUSED
,
3678 rtx libcall ATTRIBUTE_UNUSED
,
3679 const_tree fndecl ATTRIBUTE_UNUSED
)
3681 /* Record the unallocated VFP registers. */
3682 pcum
->aapcs_vfp_regs_free
= (1 << NUM_VFP_ARG_REGS
) - 1;
3683 pcum
->aapcs_vfp_reg_alloc
= 0;
3686 /* Walk down the type tree of TYPE counting consecutive base elements.
3687 If *MODEP is VOIDmode, then set it to the first valid floating point
3688 type. If a non-floating point type is found, or if a floating point
3689 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
3690 otherwise return the count in the sub-tree. */
3692 aapcs_vfp_sub_candidate (const_tree type
, enum machine_mode
*modep
)
3694 enum machine_mode mode
;
3697 switch (TREE_CODE (type
))
3700 mode
= TYPE_MODE (type
);
3701 if (mode
!= DFmode
&& mode
!= SFmode
)
3704 if (*modep
== VOIDmode
)
3713 mode
= TYPE_MODE (TREE_TYPE (type
));
3714 if (mode
!= DFmode
&& mode
!= SFmode
)
3717 if (*modep
== VOIDmode
)
3726 /* Use V2SImode and V4SImode as representatives of all 64-bit
3727 and 128-bit vector types, whether or not those modes are
3728 supported with the present options. */
3729 size
= int_size_in_bytes (type
);
3742 if (*modep
== VOIDmode
)
3745 /* Vector modes are considered to be opaque: two vectors are
3746 equivalent for the purposes of being homogeneous aggregates
3747 if they are the same size. */
3756 tree index
= TYPE_DOMAIN (type
);
3758 /* Can't handle incomplete types. */
3759 if (!COMPLETE_TYPE_P(type
))
3762 count
= aapcs_vfp_sub_candidate (TREE_TYPE (type
), modep
);
3765 || !TYPE_MAX_VALUE (index
)
3766 || !host_integerp (TYPE_MAX_VALUE (index
), 1)
3767 || !TYPE_MIN_VALUE (index
)
3768 || !host_integerp (TYPE_MIN_VALUE (index
), 1)
3772 count
*= (1 + tree_low_cst (TYPE_MAX_VALUE (index
), 1)
3773 - tree_low_cst (TYPE_MIN_VALUE (index
), 1));
3775 /* There must be no padding. */
3776 if (!host_integerp (TYPE_SIZE (type
), 1)
3777 || (tree_low_cst (TYPE_SIZE (type
), 1)
3778 != count
* GET_MODE_BITSIZE (*modep
)))
3790 /* Can't handle incomplete types. */
3791 if (!COMPLETE_TYPE_P(type
))
3794 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3796 if (TREE_CODE (field
) != FIELD_DECL
)
3799 sub_count
= aapcs_vfp_sub_candidate (TREE_TYPE (field
), modep
);
3805 /* There must be no padding. */
3806 if (!host_integerp (TYPE_SIZE (type
), 1)
3807 || (tree_low_cst (TYPE_SIZE (type
), 1)
3808 != count
* GET_MODE_BITSIZE (*modep
)))
3815 case QUAL_UNION_TYPE
:
3817 /* These aren't very interesting except in a degenerate case. */
3822 /* Can't handle incomplete types. */
3823 if (!COMPLETE_TYPE_P(type
))
3826 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3828 if (TREE_CODE (field
) != FIELD_DECL
)
3831 sub_count
= aapcs_vfp_sub_candidate (TREE_TYPE (field
), modep
);
3834 count
= count
> sub_count
? count
: sub_count
;
3837 /* There must be no padding. */
3838 if (!host_integerp (TYPE_SIZE (type
), 1)
3839 || (tree_low_cst (TYPE_SIZE (type
), 1)
3840 != count
* GET_MODE_BITSIZE (*modep
)))
3853 /* Return true if PCS_VARIANT should use VFP registers. */
3855 use_vfp_abi (enum arm_pcs pcs_variant
, bool is_double
)
3857 if (pcs_variant
== ARM_PCS_AAPCS_VFP
)
3860 if (pcs_variant
!= ARM_PCS_AAPCS_LOCAL
)
3863 return (TARGET_32BIT
&& TARGET_VFP
&& TARGET_HARD_FLOAT
&&
3864 (TARGET_VFP_DOUBLE
|| !is_double
));
3868 aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant
,
3869 enum machine_mode mode
, const_tree type
,
3870 enum machine_mode
*base_mode
, int *count
)
3872 enum machine_mode new_mode
= VOIDmode
;
3874 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3875 || GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
3876 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
3881 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3884 new_mode
= (mode
== DCmode
? DFmode
: SFmode
);
3886 else if (type
&& (mode
== BLKmode
|| TREE_CODE (type
) == VECTOR_TYPE
))
3888 int ag_count
= aapcs_vfp_sub_candidate (type
, &new_mode
);
3890 if (ag_count
> 0 && ag_count
<= 4)
3899 if (!use_vfp_abi (pcs_variant
, ARM_NUM_REGS (new_mode
) > 1))
3902 *base_mode
= new_mode
;
3907 aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant
,
3908 enum machine_mode mode
, const_tree type
)
3910 int count ATTRIBUTE_UNUSED
;
3911 enum machine_mode ag_mode ATTRIBUTE_UNUSED
;
3913 if (!use_vfp_abi (pcs_variant
, false))
3915 return aapcs_vfp_is_call_or_return_candidate (pcs_variant
, mode
, type
,
3920 aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
3923 if (!use_vfp_abi (pcum
->pcs_variant
, false))
3926 return aapcs_vfp_is_call_or_return_candidate (pcum
->pcs_variant
, mode
, type
,
3927 &pcum
->aapcs_vfp_rmode
,
3928 &pcum
->aapcs_vfp_rcount
);
3932 aapcs_vfp_allocate (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
3933 const_tree type ATTRIBUTE_UNUSED
)
3935 int shift
= GET_MODE_SIZE (pcum
->aapcs_vfp_rmode
) / GET_MODE_SIZE (SFmode
);
3936 unsigned mask
= (1 << (shift
* pcum
->aapcs_vfp_rcount
)) - 1;
3939 for (regno
= 0; regno
< NUM_VFP_ARG_REGS
; regno
+= shift
)
3940 if (((pcum
->aapcs_vfp_regs_free
>> regno
) & mask
) == mask
)
3942 pcum
->aapcs_vfp_reg_alloc
= mask
<< regno
;
3943 if (mode
== BLKmode
|| (mode
== TImode
&& !TARGET_NEON
))
3946 int rcount
= pcum
->aapcs_vfp_rcount
;
3948 enum machine_mode rmode
= pcum
->aapcs_vfp_rmode
;
3952 /* Avoid using unsupported vector modes. */
3953 if (rmode
== V2SImode
)
3955 else if (rmode
== V4SImode
)
3962 par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (rcount
));
3963 for (i
= 0; i
< rcount
; i
++)
3965 rtx tmp
= gen_rtx_REG (rmode
,
3966 FIRST_VFP_REGNUM
+ regno
+ i
* rshift
);
3967 tmp
= gen_rtx_EXPR_LIST
3969 GEN_INT (i
* GET_MODE_SIZE (rmode
)));
3970 XVECEXP (par
, 0, i
) = tmp
;
3973 pcum
->aapcs_reg
= par
;
3976 pcum
->aapcs_reg
= gen_rtx_REG (mode
, FIRST_VFP_REGNUM
+ regno
);
3983 aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED
,
3984 enum machine_mode mode
,
3985 const_tree type ATTRIBUTE_UNUSED
)
3987 if (!use_vfp_abi (pcs_variant
, false))
3990 if (mode
== BLKmode
|| (mode
== TImode
&& !TARGET_NEON
))
3993 enum machine_mode ag_mode
;
3998 aapcs_vfp_is_call_or_return_candidate (pcs_variant
, mode
, type
,
4003 if (ag_mode
== V2SImode
)
4005 else if (ag_mode
== V4SImode
)
4011 shift
= GET_MODE_SIZE(ag_mode
) / GET_MODE_SIZE(SFmode
);
4012 par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (count
));
4013 for (i
= 0; i
< count
; i
++)
4015 rtx tmp
= gen_rtx_REG (ag_mode
, FIRST_VFP_REGNUM
+ i
* shift
);
4016 tmp
= gen_rtx_EXPR_LIST (VOIDmode
, tmp
,
4017 GEN_INT (i
* GET_MODE_SIZE (ag_mode
)));
4018 XVECEXP (par
, 0, i
) = tmp
;
4024 return gen_rtx_REG (mode
, FIRST_VFP_REGNUM
);
4028 aapcs_vfp_advance (CUMULATIVE_ARGS
*pcum ATTRIBUTE_UNUSED
,
4029 enum machine_mode mode ATTRIBUTE_UNUSED
,
4030 const_tree type ATTRIBUTE_UNUSED
)
4032 pcum
->aapcs_vfp_regs_free
&= ~pcum
->aapcs_vfp_reg_alloc
;
4033 pcum
->aapcs_vfp_reg_alloc
= 0;
4037 #define AAPCS_CP(X) \
4039 aapcs_ ## X ## _cum_init, \
4040 aapcs_ ## X ## _is_call_candidate, \
4041 aapcs_ ## X ## _allocate, \
4042 aapcs_ ## X ## _is_return_candidate, \
4043 aapcs_ ## X ## _allocate_return_reg, \
4044 aapcs_ ## X ## _advance \
4047 /* Table of co-processors that can be used to pass arguments in
4048 registers. Idealy no arugment should be a candidate for more than
4049 one co-processor table entry, but the table is processed in order
4050 and stops after the first match. If that entry then fails to put
4051 the argument into a co-processor register, the argument will go on
4055 /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */
4056 void (*cum_init
) (CUMULATIVE_ARGS
*, const_tree
, rtx
, const_tree
);
4058 /* Return true if an argument of mode MODE (or type TYPE if MODE is
4059 BLKmode) is a candidate for this co-processor's registers; this
4060 function should ignore any position-dependent state in
4061 CUMULATIVE_ARGS and only use call-type dependent information. */
4062 bool (*is_call_candidate
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
4064 /* Return true if the argument does get a co-processor register; it
4065 should set aapcs_reg to an RTX of the register allocated as is
4066 required for a return from FUNCTION_ARG. */
4067 bool (*allocate
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
4069 /* Return true if a result of mode MODE (or type TYPE if MODE is
4070 BLKmode) is can be returned in this co-processor's registers. */
4071 bool (*is_return_candidate
) (enum arm_pcs
, enum machine_mode
, const_tree
);
4073 /* Allocate and return an RTX element to hold the return type of a
4074 call, this routine must not fail and will only be called if
4075 is_return_candidate returned true with the same parameters. */
4076 rtx (*allocate_return_reg
) (enum arm_pcs
, enum machine_mode
, const_tree
);
4078 /* Finish processing this argument and prepare to start processing
4080 void (*advance
) (CUMULATIVE_ARGS
*, enum machine_mode
, const_tree
);
4081 } aapcs_cp_arg_layout
[ARM_NUM_COPROC_SLOTS
] =
4089 aapcs_select_call_coproc (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4094 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4095 if (aapcs_cp_arg_layout
[i
].is_call_candidate (pcum
, mode
, type
))
4102 aapcs_select_return_coproc (const_tree type
, const_tree fntype
)
4104 /* We aren't passed a decl, so we can't check that a call is local.
4105 However, it isn't clear that that would be a win anyway, since it
4106 might limit some tail-calling opportunities. */
4107 enum arm_pcs pcs_variant
;
4111 const_tree fndecl
= NULL_TREE
;
4113 if (TREE_CODE (fntype
) == FUNCTION_DECL
)
4116 fntype
= TREE_TYPE (fntype
);
4119 pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4122 pcs_variant
= arm_pcs_default
;
4124 if (pcs_variant
!= ARM_PCS_AAPCS
)
4128 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4129 if (aapcs_cp_arg_layout
[i
].is_return_candidate (pcs_variant
,
4138 aapcs_allocate_return_reg (enum machine_mode mode
, const_tree type
,
4141 /* We aren't passed a decl, so we can't check that a call is local.
4142 However, it isn't clear that that would be a win anyway, since it
4143 might limit some tail-calling opportunities. */
4144 enum arm_pcs pcs_variant
;
4145 int unsignedp ATTRIBUTE_UNUSED
;
4149 const_tree fndecl
= NULL_TREE
;
4151 if (TREE_CODE (fntype
) == FUNCTION_DECL
)
4154 fntype
= TREE_TYPE (fntype
);
4157 pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4160 pcs_variant
= arm_pcs_default
;
4162 /* Promote integer types. */
4163 if (type
&& INTEGRAL_TYPE_P (type
))
4164 mode
= arm_promote_function_mode (type
, mode
, &unsignedp
, fntype
, 1);
4166 if (pcs_variant
!= ARM_PCS_AAPCS
)
4170 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4171 if (aapcs_cp_arg_layout
[i
].is_return_candidate (pcs_variant
, mode
,
4173 return aapcs_cp_arg_layout
[i
].allocate_return_reg (pcs_variant
,
4177 /* Promotes small structs returned in a register to full-word size
4178 for big-endian AAPCS. */
4179 if (type
&& arm_return_in_msb (type
))
4181 HOST_WIDE_INT size
= int_size_in_bytes (type
);
4182 if (size
% UNITS_PER_WORD
!= 0)
4184 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
4185 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
4189 return gen_rtx_REG (mode
, R0_REGNUM
);
4193 aapcs_libcall_value (enum machine_mode mode
)
4195 return aapcs_allocate_return_reg (mode
, NULL_TREE
, NULL_TREE
);
4198 /* Lay out a function argument using the AAPCS rules. The rule
4199 numbers referred to here are those in the AAPCS. */
4201 aapcs_layout_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4202 tree type
, int named
)
4207 /* We only need to do this once per argument. */
4208 if (pcum
->aapcs_arg_processed
)
4211 pcum
->aapcs_arg_processed
= true;
4213 /* Special case: if named is false then we are handling an incoming
4214 anonymous argument which is on the stack. */
4218 /* Is this a potential co-processor register candidate? */
4219 if (pcum
->pcs_variant
!= ARM_PCS_AAPCS
)
4221 int slot
= aapcs_select_call_coproc (pcum
, mode
, type
);
4222 pcum
->aapcs_cprc_slot
= slot
;
4224 /* We don't have to apply any of the rules from part B of the
4225 preparation phase, these are handled elsewhere in the
4230 /* A Co-processor register candidate goes either in its own
4231 class of registers or on the stack. */
4232 if (!pcum
->aapcs_cprc_failed
[slot
])
4234 /* C1.cp - Try to allocate the argument to co-processor
4236 if (aapcs_cp_arg_layout
[slot
].allocate (pcum
, mode
, type
))
4239 /* C2.cp - Put the argument on the stack and note that we
4240 can't assign any more candidates in this slot. We also
4241 need to note that we have allocated stack space, so that
4242 we won't later try to split a non-cprc candidate between
4243 core registers and the stack. */
4244 pcum
->aapcs_cprc_failed
[slot
] = true;
4245 pcum
->can_split
= false;
4248 /* We didn't get a register, so this argument goes on the
4250 gcc_assert (pcum
->can_split
== false);
4255 /* C3 - For double-word aligned arguments, round the NCRN up to the
4256 next even number. */
4257 ncrn
= pcum
->aapcs_ncrn
;
4258 if ((ncrn
& 1) && arm_needs_doubleword_align (mode
, type
))
4261 nregs
= ARM_NUM_REGS2(mode
, type
);
4263 /* Sigh, this test should really assert that nregs > 0, but a GCC
4264 extension allows empty structs and then gives them empty size; it
4265 then allows such a structure to be passed by value. For some of
4266 the code below we have to pretend that such an argument has
4267 non-zero size so that we 'locate' it correctly either in
4268 registers or on the stack. */
4269 gcc_assert (nregs
>= 0);
4271 nregs2
= nregs
? nregs
: 1;
4273 /* C4 - Argument fits entirely in core registers. */
4274 if (ncrn
+ nregs2
<= NUM_ARG_REGS
)
4276 pcum
->aapcs_reg
= gen_rtx_REG (mode
, ncrn
);
4277 pcum
->aapcs_next_ncrn
= ncrn
+ nregs
;
4281 /* C5 - Some core registers left and there are no arguments already
4282 on the stack: split this argument between the remaining core
4283 registers and the stack. */
4284 if (ncrn
< NUM_ARG_REGS
&& pcum
->can_split
)
4286 pcum
->aapcs_reg
= gen_rtx_REG (mode
, ncrn
);
4287 pcum
->aapcs_next_ncrn
= NUM_ARG_REGS
;
4288 pcum
->aapcs_partial
= (NUM_ARG_REGS
- ncrn
) * UNITS_PER_WORD
;
4292 /* C6 - NCRN is set to 4. */
4293 pcum
->aapcs_next_ncrn
= NUM_ARG_REGS
;
4295 /* C7,C8 - arugment goes on the stack. We have nothing to do here. */
4299 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4300 for a call to a function whose data type is FNTYPE.
4301 For a library call, FNTYPE is NULL. */
4303 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
4305 tree fndecl ATTRIBUTE_UNUSED
)
4307 /* Long call handling. */
4309 pcum
->pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
4311 pcum
->pcs_variant
= arm_pcs_default
;
4313 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4315 if (arm_libcall_uses_aapcs_base (libname
))
4316 pcum
->pcs_variant
= ARM_PCS_AAPCS
;
4318 pcum
->aapcs_ncrn
= pcum
->aapcs_next_ncrn
= 0;
4319 pcum
->aapcs_reg
= NULL_RTX
;
4320 pcum
->aapcs_partial
= 0;
4321 pcum
->aapcs_arg_processed
= false;
4322 pcum
->aapcs_cprc_slot
= -1;
4323 pcum
->can_split
= true;
4325 if (pcum
->pcs_variant
!= ARM_PCS_AAPCS
)
4329 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
4331 pcum
->aapcs_cprc_failed
[i
] = false;
4332 aapcs_cp_arg_layout
[i
].cum_init (pcum
, fntype
, libname
, fndecl
);
4340 /* On the ARM, the offset starts at 0. */
4342 pcum
->iwmmxt_nregs
= 0;
4343 pcum
->can_split
= true;
4345 /* Varargs vectors are treated the same as long long.
4346 named_count avoids having to change the way arm handles 'named' */
4347 pcum
->named_count
= 0;
4350 if (TARGET_REALLY_IWMMXT
&& fntype
)
4354 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
4356 fn_arg
= TREE_CHAIN (fn_arg
))
4357 pcum
->named_count
+= 1;
4359 if (! pcum
->named_count
)
4360 pcum
->named_count
= INT_MAX
;
4365 /* Return true if mode/type need doubleword alignment. */
4367 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
4369 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
4370 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
4374 /* Determine where to put an argument to a function.
4375 Value is zero to push the argument on the stack,
4376 or a hard register in which to store the argument.
4378 MODE is the argument's machine mode.
4379 TYPE is the data type of the argument (as a tree).
4380 This is null for libcalls where that information may
4382 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4383 the preceding args and about the function being called.
4384 NAMED is nonzero if this argument is a named parameter
4385 (otherwise it is an extra parameter matching an ellipsis). */
4388 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4389 tree type
, int named
)
4393 /* Handle the special case quickly. Pick an arbitrary value for op2 of
4394 a call insn (op3 of a call_value insn). */
4395 if (mode
== VOIDmode
)
4398 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4400 aapcs_layout_arg (pcum
, mode
, type
, named
);
4401 return pcum
->aapcs_reg
;
4404 /* Varargs vectors are treated the same as long long.
4405 named_count avoids having to change the way arm handles 'named' */
4406 if (TARGET_IWMMXT_ABI
4407 && arm_vector_mode_supported_p (mode
)
4408 && pcum
->named_count
> pcum
->nargs
+ 1)
4410 if (pcum
->iwmmxt_nregs
<= 9)
4411 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
4414 pcum
->can_split
= false;
4419 /* Put doubleword aligned quantities in even register pairs. */
4421 && ARM_DOUBLEWORD_ALIGN
4422 && arm_needs_doubleword_align (mode
, type
))
4425 if (mode
== VOIDmode
)
4426 /* Pick an arbitrary value for operand 2 of the call insn. */
4429 /* Only allow splitting an arg between regs and memory if all preceding
4430 args were allocated to regs. For args passed by reference we only count
4431 the reference pointer. */
4432 if (pcum
->can_split
)
4435 nregs
= ARM_NUM_REGS2 (mode
, type
);
4437 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
4440 return gen_rtx_REG (mode
, pcum
->nregs
);
4444 arm_arg_partial_bytes (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4445 tree type
, bool named
)
4447 int nregs
= pcum
->nregs
;
4449 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4451 aapcs_layout_arg (pcum
, mode
, type
, named
);
4452 return pcum
->aapcs_partial
;
4455 if (TARGET_IWMMXT_ABI
&& arm_vector_mode_supported_p (mode
))
4458 if (NUM_ARG_REGS
> nregs
4459 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (mode
, type
))
4461 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
4467 arm_function_arg_advance (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
4468 tree type
, bool named
)
4470 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
4472 aapcs_layout_arg (pcum
, mode
, type
, named
);
4474 if (pcum
->aapcs_cprc_slot
>= 0)
4476 aapcs_cp_arg_layout
[pcum
->aapcs_cprc_slot
].advance (pcum
, mode
,
4478 pcum
->aapcs_cprc_slot
= -1;
4481 /* Generic stuff. */
4482 pcum
->aapcs_arg_processed
= false;
4483 pcum
->aapcs_ncrn
= pcum
->aapcs_next_ncrn
;
4484 pcum
->aapcs_reg
= NULL_RTX
;
4485 pcum
->aapcs_partial
= 0;
4490 if (arm_vector_mode_supported_p (mode
)
4491 && pcum
->named_count
> pcum
->nargs
4492 && TARGET_IWMMXT_ABI
)
4493 pcum
->iwmmxt_nregs
+= 1;
4495 pcum
->nregs
+= ARM_NUM_REGS2 (mode
, type
);
4499 /* Variable sized types are passed by reference. This is a GCC
4500 extension to the ARM ABI. */
4503 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4504 enum machine_mode mode ATTRIBUTE_UNUSED
,
4505 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4507 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
4510 /* Encode the current state of the #pragma [no_]long_calls. */
4513 OFF
, /* No #pragma [no_]long_calls is in effect. */
4514 LONG
, /* #pragma long_calls is in effect. */
4515 SHORT
/* #pragma no_long_calls is in effect. */
4518 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
4521 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
4523 arm_pragma_long_calls
= LONG
;
4527 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
4529 arm_pragma_long_calls
= SHORT
;
4533 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
4535 arm_pragma_long_calls
= OFF
;
4538 /* Handle an attribute requiring a FUNCTION_DECL;
4539 arguments as in struct attribute_spec.handler. */
4541 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
4542 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
4544 if (TREE_CODE (*node
) != FUNCTION_DECL
)
4546 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
4548 *no_add_attrs
= true;
4554 /* Handle an "interrupt" or "isr" attribute;
4555 arguments as in struct attribute_spec.handler. */
4557 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
4562 if (TREE_CODE (*node
) != FUNCTION_DECL
)
4564 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
4566 *no_add_attrs
= true;
4568 /* FIXME: the argument if any is checked for type attributes;
4569 should it be checked for decl ones? */
4573 if (TREE_CODE (*node
) == FUNCTION_TYPE
4574 || TREE_CODE (*node
) == METHOD_TYPE
)
4576 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
4578 warning (OPT_Wattributes
, "%qE attribute ignored",
4580 *no_add_attrs
= true;
4583 else if (TREE_CODE (*node
) == POINTER_TYPE
4584 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
4585 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
4586 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
4588 *node
= build_variant_type_copy (*node
);
4589 TREE_TYPE (*node
) = build_type_attribute_variant
4591 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
4592 *no_add_attrs
= true;
4596 /* Possibly pass this attribute on from the type to a decl. */
4597 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
4598 | (int) ATTR_FLAG_FUNCTION_NEXT
4599 | (int) ATTR_FLAG_ARRAY_NEXT
))
4601 *no_add_attrs
= true;
4602 return tree_cons (name
, args
, NULL_TREE
);
4606 warning (OPT_Wattributes
, "%qE attribute ignored",
4615 /* Handle a "pcs" attribute; arguments as in struct
4616 attribute_spec.handler. */
4618 arm_handle_pcs_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
4619 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
4621 if (arm_pcs_from_attribute (args
) == ARM_PCS_UNKNOWN
)
4623 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
4624 *no_add_attrs
= true;
4629 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
4630 /* Handle the "notshared" attribute. This attribute is another way of
4631 requesting hidden visibility. ARM's compiler supports
4632 "__declspec(notshared)"; we support the same thing via an
4636 arm_handle_notshared_attribute (tree
*node
,
4637 tree name ATTRIBUTE_UNUSED
,
4638 tree args ATTRIBUTE_UNUSED
,
4639 int flags ATTRIBUTE_UNUSED
,
4642 tree decl
= TYPE_NAME (*node
);
4646 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
4647 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
4648 *no_add_attrs
= false;
4654 /* Return 0 if the attributes for two types are incompatible, 1 if they
4655 are compatible, and 2 if they are nearly compatible (which causes a
4656 warning to be generated). */
4658 arm_comp_type_attributes (const_tree type1
, const_tree type2
)
4662 /* Check for mismatch of non-default calling convention. */
4663 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
4666 /* Check for mismatched call attributes. */
4667 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
4668 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
4669 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
4670 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
4672 /* Only bother to check if an attribute is defined. */
4673 if (l1
| l2
| s1
| s2
)
4675 /* If one type has an attribute, the other must have the same attribute. */
4676 if ((l1
!= l2
) || (s1
!= s2
))
4679 /* Disallow mixed attributes. */
4680 if ((l1
& s2
) || (l2
& s1
))
4684 /* Check for mismatched ISR attribute. */
4685 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
4687 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
4688 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
4690 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
4697 /* Assigns default attributes to newly defined type. This is used to
4698 set short_call/long_call attributes for function types of
4699 functions defined inside corresponding #pragma scopes. */
4701 arm_set_default_type_attributes (tree type
)
4703 /* Add __attribute__ ((long_call)) to all functions, when
4704 inside #pragma long_calls or __attribute__ ((short_call)),
4705 when inside #pragma no_long_calls. */
4706 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
4708 tree type_attr_list
, attr_name
;
4709 type_attr_list
= TYPE_ATTRIBUTES (type
);
4711 if (arm_pragma_long_calls
== LONG
)
4712 attr_name
= get_identifier ("long_call");
4713 else if (arm_pragma_long_calls
== SHORT
)
4714 attr_name
= get_identifier ("short_call");
4718 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
4719 TYPE_ATTRIBUTES (type
) = type_attr_list
;
4723 /* Return true if DECL is known to be linked into section SECTION. */
4726 arm_function_in_section_p (tree decl
, section
*section
)
4728 /* We can only be certain about functions defined in the same
4729 compilation unit. */
4730 if (!TREE_STATIC (decl
))
4733 /* Make sure that SYMBOL always binds to the definition in this
4734 compilation unit. */
4735 if (!targetm
.binds_local_p (decl
))
4738 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
4739 if (!DECL_SECTION_NAME (decl
))
4741 /* Make sure that we will not create a unique section for DECL. */
4742 if (flag_function_sections
|| DECL_ONE_ONLY (decl
))
4746 return function_section (decl
) == section
;
4749 /* Return nonzero if a 32-bit "long_call" should be generated for
4750 a call from the current function to DECL. We generate a long_call
4753 a. has an __attribute__((long call))
4754 or b. is within the scope of a #pragma long_calls
4755 or c. the -mlong-calls command line switch has been specified
4757 However we do not generate a long call if the function:
4759 d. has an __attribute__ ((short_call))
4760 or e. is inside the scope of a #pragma no_long_calls
4761 or f. is defined in the same section as the current function. */
4764 arm_is_long_call_p (tree decl
)
4769 return TARGET_LONG_CALLS
;
4771 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
4772 if (lookup_attribute ("short_call", attrs
))
4775 /* For "f", be conservative, and only cater for cases in which the
4776 whole of the current function is placed in the same section. */
4777 if (!flag_reorder_blocks_and_partition
4778 && TREE_CODE (decl
) == FUNCTION_DECL
4779 && arm_function_in_section_p (decl
, current_function_section ()))
4782 if (lookup_attribute ("long_call", attrs
))
4785 return TARGET_LONG_CALLS
;
4788 /* Return nonzero if it is ok to make a tail-call to DECL. */
4790 arm_function_ok_for_sibcall (tree decl
, tree exp
)
4792 unsigned long func_type
;
4794 if (cfun
->machine
->sibcall_blocked
)
4797 /* Never tailcall something for which we have no decl, or if we
4798 are in Thumb mode. */
4799 if (decl
== NULL
|| TARGET_THUMB
)
4802 /* The PIC register is live on entry to VxWorks PLT entries, so we
4803 must make the call before restoring the PIC register. */
4804 if (TARGET_VXWORKS_RTP
&& flag_pic
&& !targetm
.binds_local_p (decl
))
4807 /* Cannot tail-call to long calls, since these are out of range of
4808 a branch instruction. */
4809 if (arm_is_long_call_p (decl
))
4812 /* If we are interworking and the function is not declared static
4813 then we can't tail-call it unless we know that it exists in this
4814 compilation unit (since it might be a Thumb routine). */
4815 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
4818 func_type
= arm_current_func_type ();
4819 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
4820 if (IS_INTERRUPT (func_type
))
4823 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
4825 /* Check that the return value locations are the same. For
4826 example that we aren't returning a value from the sibling in
4827 a VFP register but then need to transfer it to a core
4831 a
= arm_function_value (TREE_TYPE (exp
), decl
, false);
4832 b
= arm_function_value (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
4834 if (!rtx_equal_p (a
, b
))
4838 /* Never tailcall if function may be called with a misaligned SP. */
4839 if (IS_STACKALIGN (func_type
))
4842 /* Everything else is ok. */
4847 /* Addressing mode support functions. */
4849 /* Return nonzero if X is a legitimate immediate operand when compiling
4850 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
4852 legitimate_pic_operand_p (rtx x
)
4854 if (GET_CODE (x
) == SYMBOL_REF
4855 || (GET_CODE (x
) == CONST
4856 && GET_CODE (XEXP (x
, 0)) == PLUS
4857 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
4863 /* Record that the current function needs a PIC register. Initialize
4864 cfun->machine->pic_reg if we have not already done so. */
4867 require_pic_register (void)
4869 /* A lot of the logic here is made obscure by the fact that this
4870 routine gets called as part of the rtx cost estimation process.
4871 We don't want those calls to affect any assumptions about the real
4872 function; and further, we can't call entry_of_function() until we
4873 start the real expansion process. */
4874 if (!crtl
->uses_pic_offset_table
)
4876 gcc_assert (can_create_pseudo_p ());
4877 if (arm_pic_register
!= INVALID_REGNUM
)
4879 if (!cfun
->machine
->pic_reg
)
4880 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
4882 /* Play games to avoid marking the function as needing pic
4883 if we are being called as part of the cost-estimation
4885 if (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
)
4886 crtl
->uses_pic_offset_table
= 1;
4892 if (!cfun
->machine
->pic_reg
)
4893 cfun
->machine
->pic_reg
= gen_reg_rtx (Pmode
);
4895 /* Play games to avoid marking the function as needing pic
4896 if we are being called as part of the cost-estimation
4898 if (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
)
4900 crtl
->uses_pic_offset_table
= 1;
4903 arm_load_pic_register (0UL);
4907 /* We can be called during expansion of PHI nodes, where
4908 we can't yet emit instructions directly in the final
4909 insn stream. Queue the insns on the entry edge, they will
4910 be committed after everything else is expanded. */
4911 insert_insn_on_edge (seq
, single_succ_edge (ENTRY_BLOCK_PTR
));
4918 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
4920 if (GET_CODE (orig
) == SYMBOL_REF
4921 || GET_CODE (orig
) == LABEL_REF
)
4923 rtx pic_ref
, address
;
4928 gcc_assert (can_create_pseudo_p ());
4929 reg
= gen_reg_rtx (Pmode
);
4930 address
= gen_reg_rtx (Pmode
);
4935 /* VxWorks does not impose a fixed gap between segments; the run-time
4936 gap can be different from the object-file gap. We therefore can't
4937 use GOTOFF unless we are absolutely sure that the symbol is in the
4938 same segment as the GOT. Unfortunately, the flexibility of linker
4939 scripts means that we can't be sure of that in general, so assume
4940 that GOTOFF is never valid on VxWorks. */
4941 if ((GET_CODE (orig
) == LABEL_REF
4942 || (GET_CODE (orig
) == SYMBOL_REF
&&
4943 SYMBOL_REF_LOCAL_P (orig
)))
4945 && !TARGET_VXWORKS_RTP
)
4946 insn
= arm_pic_static_addr (orig
, reg
);
4949 /* If this function doesn't have a pic register, create one now. */
4950 require_pic_register ();
4953 emit_insn (gen_pic_load_addr_32bit (address
, orig
));
4954 else /* TARGET_THUMB1 */
4955 emit_insn (gen_pic_load_addr_thumb1 (address
, orig
));
4957 pic_ref
= gen_const_mem (Pmode
,
4958 gen_rtx_PLUS (Pmode
, cfun
->machine
->pic_reg
,
4960 insn
= emit_move_insn (reg
, pic_ref
);
4963 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4965 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4969 else if (GET_CODE (orig
) == CONST
)
4973 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4974 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
4977 /* Handle the case where we have: const (UNSPEC_TLS). */
4978 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
4979 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
4982 /* Handle the case where we have:
4983 const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a
4985 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4986 && GET_CODE (XEXP (XEXP (orig
, 0), 0)) == UNSPEC
4987 && XINT (XEXP (XEXP (orig
, 0), 0), 1) == UNSPEC_TLS
)
4989 gcc_assert (GET_CODE (XEXP (XEXP (orig
, 0), 1)) == CONST_INT
);
4995 gcc_assert (can_create_pseudo_p ());
4996 reg
= gen_reg_rtx (Pmode
);
4999 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
5001 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
5002 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
5003 base
== reg
? 0 : reg
);
5005 if (GET_CODE (offset
) == CONST_INT
)
5007 /* The base register doesn't really matter, we only want to
5008 test the index for the appropriate mode. */
5009 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
5011 gcc_assert (can_create_pseudo_p ());
5012 offset
= force_reg (Pmode
, offset
);
5015 if (GET_CODE (offset
) == CONST_INT
)
5016 return plus_constant (base
, INTVAL (offset
));
5019 if (GET_MODE_SIZE (mode
) > 4
5020 && (GET_MODE_CLASS (mode
) == MODE_INT
5021 || TARGET_SOFT_FLOAT
))
5023 emit_insn (gen_addsi3 (reg
, base
, offset
));
5027 return gen_rtx_PLUS (Pmode
, base
, offset
);
5034 /* Find a spare register to use during the prolog of a function. */
5037 thumb_find_work_register (unsigned long pushed_regs_mask
)
5041 /* Check the argument registers first as these are call-used. The
5042 register allocation order means that sometimes r3 might be used
5043 but earlier argument registers might not, so check them all. */
5044 for (reg
= LAST_ARG_REGNUM
; reg
>= 0; reg
--)
5045 if (!df_regs_ever_live_p (reg
))
5048 /* Before going on to check the call-saved registers we can try a couple
5049 more ways of deducing that r3 is available. The first is when we are
5050 pushing anonymous arguments onto the stack and we have less than 4
5051 registers worth of fixed arguments(*). In this case r3 will be part of
5052 the variable argument list and so we can be sure that it will be
5053 pushed right at the start of the function. Hence it will be available
5054 for the rest of the prologue.
5055 (*): ie crtl->args.pretend_args_size is greater than 0. */
5056 if (cfun
->machine
->uses_anonymous_args
5057 && crtl
->args
.pretend_args_size
> 0)
5058 return LAST_ARG_REGNUM
;
5060 /* The other case is when we have fixed arguments but less than 4 registers
5061 worth. In this case r3 might be used in the body of the function, but
5062 it is not being used to convey an argument into the function. In theory
5063 we could just check crtl->args.size to see how many bytes are
5064 being passed in argument registers, but it seems that it is unreliable.
5065 Sometimes it will have the value 0 when in fact arguments are being
5066 passed. (See testcase execute/20021111-1.c for an example). So we also
5067 check the args_info.nregs field as well. The problem with this field is
5068 that it makes no allowances for arguments that are passed to the
5069 function but which are not used. Hence we could miss an opportunity
5070 when a function has an unused argument in r3. But it is better to be
5071 safe than to be sorry. */
5072 if (! cfun
->machine
->uses_anonymous_args
5073 && crtl
->args
.size
>= 0
5074 && crtl
->args
.size
<= (LAST_ARG_REGNUM
* UNITS_PER_WORD
)
5075 && crtl
->args
.info
.nregs
< 4)
5076 return LAST_ARG_REGNUM
;
5078 /* Otherwise look for a call-saved register that is going to be pushed. */
5079 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
5080 if (pushed_regs_mask
& (1 << reg
))
5085 /* Thumb-2 can use high regs. */
5086 for (reg
= FIRST_HI_REGNUM
; reg
< 15; reg
++)
5087 if (pushed_regs_mask
& (1 << reg
))
5090 /* Something went wrong - thumb_compute_save_reg_mask()
5091 should have arranged for a suitable register to be pushed. */
5095 static GTY(()) int pic_labelno
;
5097 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
5101 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
)
5103 rtx l1
, labelno
, pic_tmp
, pic_rtx
, pic_reg
;
5105 if (crtl
->uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
5108 gcc_assert (flag_pic
);
5110 pic_reg
= cfun
->machine
->pic_reg
;
5111 if (TARGET_VXWORKS_RTP
)
5113 pic_rtx
= gen_rtx_SYMBOL_REF (Pmode
, VXWORKS_GOTT_BASE
);
5114 pic_rtx
= gen_rtx_CONST (Pmode
, pic_rtx
);
5115 emit_insn (gen_pic_load_addr_32bit (pic_reg
, pic_rtx
));
5117 emit_insn (gen_rtx_SET (Pmode
, pic_reg
, gen_rtx_MEM (Pmode
, pic_reg
)));
5119 pic_tmp
= gen_rtx_SYMBOL_REF (Pmode
, VXWORKS_GOTT_INDEX
);
5120 emit_insn (gen_pic_offset_arm (pic_reg
, pic_reg
, pic_tmp
));
5124 /* We use an UNSPEC rather than a LABEL_REF because this label
5125 never appears in the code stream. */
5127 labelno
= GEN_INT (pic_labelno
++);
5128 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5129 l1
= gen_rtx_CONST (VOIDmode
, l1
);
5131 /* On the ARM the PC register contains 'dot + 8' at the time of the
5132 addition, on the Thumb it is 'dot + 4'. */
5133 pic_rtx
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
5134 pic_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, pic_rtx
),
5136 pic_rtx
= gen_rtx_CONST (Pmode
, pic_rtx
);
5140 emit_insn (gen_pic_load_addr_32bit (pic_reg
, pic_rtx
));
5142 emit_insn (gen_pic_add_dot_plus_eight (pic_reg
, pic_reg
, labelno
));
5144 emit_insn (gen_pic_add_dot_plus_four (pic_reg
, pic_reg
, labelno
));
5146 else /* TARGET_THUMB1 */
5148 if (arm_pic_register
!= INVALID_REGNUM
5149 && REGNO (pic_reg
) > LAST_LO_REGNUM
)
5151 /* We will have pushed the pic register, so we should always be
5152 able to find a work register. */
5153 pic_tmp
= gen_rtx_REG (SImode
,
5154 thumb_find_work_register (saved_regs
));
5155 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp
, pic_rtx
));
5156 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
5159 emit_insn (gen_pic_load_addr_thumb1 (pic_reg
, pic_rtx
));
5160 emit_insn (gen_pic_add_dot_plus_four (pic_reg
, pic_reg
, labelno
));
5164 /* Need to emit this whether or not we obey regdecls,
5165 since setjmp/longjmp can cause life info to screw up. */
5169 /* Generate code to load the address of a static var when flag_pic is set. */
5171 arm_pic_static_addr (rtx orig
, rtx reg
)
5173 rtx l1
, labelno
, offset_rtx
, insn
;
5175 gcc_assert (flag_pic
);
5177 /* We use an UNSPEC rather than a LABEL_REF because this label
5178 never appears in the code stream. */
5179 labelno
= GEN_INT (pic_labelno
++);
5180 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5181 l1
= gen_rtx_CONST (VOIDmode
, l1
);
5183 /* On the ARM the PC register contains 'dot + 8' at the time of the
5184 addition, on the Thumb it is 'dot + 4'. */
5185 offset_rtx
= plus_constant (l1
, TARGET_ARM
? 8 : 4);
5186 offset_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, orig
, offset_rtx
),
5187 UNSPEC_SYMBOL_OFFSET
);
5188 offset_rtx
= gen_rtx_CONST (Pmode
, offset_rtx
);
5192 emit_insn (gen_pic_load_addr_32bit (reg
, offset_rtx
));
5194 insn
= emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
5196 insn
= emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5198 else /* TARGET_THUMB1 */
5200 emit_insn (gen_pic_load_addr_thumb1 (reg
, offset_rtx
));
5201 insn
= emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5207 /* Return nonzero if X is valid as an ARM state addressing register. */
5209 arm_address_register_rtx_p (rtx x
, int strict_p
)
5213 if (GET_CODE (x
) != REG
)
5219 return ARM_REGNO_OK_FOR_BASE_P (regno
);
5221 return (regno
<= LAST_ARM_REGNUM
5222 || regno
>= FIRST_PSEUDO_REGISTER
5223 || regno
== FRAME_POINTER_REGNUM
5224 || regno
== ARG_POINTER_REGNUM
);
5227 /* Return TRUE if this rtx is the difference of a symbol and a label,
5228 and will reduce to a PC-relative relocation in the object file.
5229 Expressions like this can be left alone when generating PIC, rather
5230 than forced through the GOT. */
5232 pcrel_constant_p (rtx x
)
5234 if (GET_CODE (x
) == MINUS
)
5235 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
5240 /* Return nonzero if X is a valid ARM state address operand. */
5242 arm_legitimate_address_outer_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
5246 enum rtx_code code
= GET_CODE (x
);
5248 if (arm_address_register_rtx_p (x
, strict_p
))
5251 use_ldrd
= (TARGET_LDRD
5253 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
5255 if (code
== POST_INC
|| code
== PRE_DEC
5256 || ((code
== PRE_INC
|| code
== POST_DEC
)
5257 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
5258 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
5260 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
5261 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
5262 && GET_CODE (XEXP (x
, 1)) == PLUS
5263 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5265 rtx addend
= XEXP (XEXP (x
, 1), 1);
5267 /* Don't allow ldrd post increment by register because it's hard
5268 to fixup invalid register choices. */
5270 && GET_CODE (x
) == POST_MODIFY
5271 && GET_CODE (addend
) == REG
)
5274 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
5275 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
5278 /* After reload constants split into minipools will have addresses
5279 from a LABEL_REF. */
5280 else if (reload_completed
5281 && (code
== LABEL_REF
5283 && GET_CODE (XEXP (x
, 0)) == PLUS
5284 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5285 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5288 else if (mode
== TImode
|| (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
)))
5291 else if (code
== PLUS
)
5293 rtx xop0
= XEXP (x
, 0);
5294 rtx xop1
= XEXP (x
, 1);
5296 return ((arm_address_register_rtx_p (xop0
, strict_p
)
5297 && GET_CODE(xop1
) == CONST_INT
5298 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
5299 || (arm_address_register_rtx_p (xop1
, strict_p
)
5300 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
5304 /* Reload currently can't handle MINUS, so disable this for now */
5305 else if (GET_CODE (x
) == MINUS
)
5307 rtx xop0
= XEXP (x
, 0);
5308 rtx xop1
= XEXP (x
, 1);
5310 return (arm_address_register_rtx_p (xop0
, strict_p
)
5311 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
5315 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
5316 && code
== SYMBOL_REF
5317 && CONSTANT_POOL_ADDRESS_P (x
)
5319 && symbol_mentioned_p (get_pool_constant (x
))
5320 && ! pcrel_constant_p (get_pool_constant (x
))))
5326 /* Return nonzero if X is a valid Thumb-2 address operand. */
5328 thumb2_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
5331 enum rtx_code code
= GET_CODE (x
);
5333 if (arm_address_register_rtx_p (x
, strict_p
))
5336 use_ldrd
= (TARGET_LDRD
5338 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
5340 if (code
== POST_INC
|| code
== PRE_DEC
5341 || ((code
== PRE_INC
|| code
== POST_DEC
)
5342 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
5343 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
5345 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
5346 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
5347 && GET_CODE (XEXP (x
, 1)) == PLUS
5348 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5350 /* Thumb-2 only has autoincrement by constant. */
5351 rtx addend
= XEXP (XEXP (x
, 1), 1);
5352 HOST_WIDE_INT offset
;
5354 if (GET_CODE (addend
) != CONST_INT
)
5357 offset
= INTVAL(addend
);
5358 if (GET_MODE_SIZE (mode
) <= 4)
5359 return (offset
> -256 && offset
< 256);
5361 return (use_ldrd
&& offset
> -1024 && offset
< 1024
5362 && (offset
& 3) == 0);
5365 /* After reload constants split into minipools will have addresses
5366 from a LABEL_REF. */
5367 else if (reload_completed
5368 && (code
== LABEL_REF
5370 && GET_CODE (XEXP (x
, 0)) == PLUS
5371 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5372 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5375 else if (mode
== TImode
|| (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
)))
5378 else if (code
== PLUS
)
5380 rtx xop0
= XEXP (x
, 0);
5381 rtx xop1
= XEXP (x
, 1);
5383 return ((arm_address_register_rtx_p (xop0
, strict_p
)
5384 && thumb2_legitimate_index_p (mode
, xop1
, strict_p
))
5385 || (arm_address_register_rtx_p (xop1
, strict_p
)
5386 && thumb2_legitimate_index_p (mode
, xop0
, strict_p
)));
5389 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
5390 && code
== SYMBOL_REF
5391 && CONSTANT_POOL_ADDRESS_P (x
)
5393 && symbol_mentioned_p (get_pool_constant (x
))
5394 && ! pcrel_constant_p (get_pool_constant (x
))))
5400 /* Return nonzero if INDEX is valid for an address index operand in
5403 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
5406 HOST_WIDE_INT range
;
5407 enum rtx_code code
= GET_CODE (index
);
5409 /* Standard coprocessor addressing modes. */
5410 if (TARGET_HARD_FLOAT
5411 && (TARGET_FPA
|| TARGET_MAVERICK
)
5412 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5413 || (TARGET_MAVERICK
&& mode
== DImode
)))
5414 return (code
== CONST_INT
&& INTVAL (index
) < 1024
5415 && INTVAL (index
) > -1024
5416 && (INTVAL (index
) & 3) == 0);
5419 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
)))
5420 return (code
== CONST_INT
5421 && INTVAL (index
) < 1016
5422 && INTVAL (index
) > -1024
5423 && (INTVAL (index
) & 3) == 0);
5425 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
5426 return (code
== CONST_INT
5427 && INTVAL (index
) < 1024
5428 && INTVAL (index
) > -1024
5429 && (INTVAL (index
) & 3) == 0);
5431 if (arm_address_register_rtx_p (index
, strict_p
)
5432 && (GET_MODE_SIZE (mode
) <= 4))
5435 if (mode
== DImode
|| mode
== DFmode
)
5437 if (code
== CONST_INT
)
5439 HOST_WIDE_INT val
= INTVAL (index
);
5442 return val
> -256 && val
< 256;
5444 return val
> -4096 && val
< 4092;
5447 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
5450 if (GET_MODE_SIZE (mode
) <= 4
5454 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
5458 rtx xiop0
= XEXP (index
, 0);
5459 rtx xiop1
= XEXP (index
, 1);
5461 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
5462 && power_of_two_operand (xiop1
, SImode
))
5463 || (arm_address_register_rtx_p (xiop1
, strict_p
)
5464 && power_of_two_operand (xiop0
, SImode
)));
5466 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
5467 || code
== ASHIFT
|| code
== ROTATERT
)
5469 rtx op
= XEXP (index
, 1);
5471 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
5472 && GET_CODE (op
) == CONST_INT
5474 && INTVAL (op
) <= 31);
5478 /* For ARM v4 we may be doing a sign-extend operation during the
5484 || (outer
== SIGN_EXTEND
&& mode
== QImode
))
5490 range
= (mode
== HImode
|| mode
== HFmode
) ? 4095 : 4096;
5492 return (code
== CONST_INT
5493 && INTVAL (index
) < range
5494 && INTVAL (index
) > -range
);
5497 /* Return true if OP is a valid index scaling factor for Thumb-2 address
5498 index operand. i.e. 1, 2, 4 or 8. */
5500 thumb2_index_mul_operand (rtx op
)
5504 if (GET_CODE(op
) != CONST_INT
)
5508 return (val
== 1 || val
== 2 || val
== 4 || val
== 8);
5511 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
5513 thumb2_legitimate_index_p (enum machine_mode mode
, rtx index
, int strict_p
)
5515 enum rtx_code code
= GET_CODE (index
);
5517 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
5518 /* Standard coprocessor addressing modes. */
5519 if (TARGET_HARD_FLOAT
5520 && (TARGET_FPA
|| TARGET_MAVERICK
)
5521 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5522 || (TARGET_MAVERICK
&& mode
== DImode
)))
5523 return (code
== CONST_INT
&& INTVAL (index
) < 1024
5524 && INTVAL (index
) > -1024
5525 && (INTVAL (index
) & 3) == 0);
5527 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
5529 /* For DImode assume values will usually live in core regs
5530 and only allow LDRD addressing modes. */
5531 if (!TARGET_LDRD
|| mode
!= DImode
)
5532 return (code
== CONST_INT
5533 && INTVAL (index
) < 1024
5534 && INTVAL (index
) > -1024
5535 && (INTVAL (index
) & 3) == 0);
5539 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
)))
5540 return (code
== CONST_INT
5541 && INTVAL (index
) < 1016
5542 && INTVAL (index
) > -1024
5543 && (INTVAL (index
) & 3) == 0);
5545 if (arm_address_register_rtx_p (index
, strict_p
)
5546 && (GET_MODE_SIZE (mode
) <= 4))
5549 if (mode
== DImode
|| mode
== DFmode
)
5551 if (code
== CONST_INT
)
5553 HOST_WIDE_INT val
= INTVAL (index
);
5554 /* ??? Can we assume ldrd for thumb2? */
5555 /* Thumb-2 ldrd only has reg+const addressing modes. */
5556 /* ldrd supports offsets of +-1020.
5557 However the ldr fallback does not. */
5558 return val
> -256 && val
< 256 && (val
& 3) == 0;
5566 rtx xiop0
= XEXP (index
, 0);
5567 rtx xiop1
= XEXP (index
, 1);
5569 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
5570 && thumb2_index_mul_operand (xiop1
))
5571 || (arm_address_register_rtx_p (xiop1
, strict_p
)
5572 && thumb2_index_mul_operand (xiop0
)));
5574 else if (code
== ASHIFT
)
5576 rtx op
= XEXP (index
, 1);
5578 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
5579 && GET_CODE (op
) == CONST_INT
5581 && INTVAL (op
) <= 3);
5584 return (code
== CONST_INT
5585 && INTVAL (index
) < 4096
5586 && INTVAL (index
) > -256);
5589 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
5591 thumb1_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
5595 if (GET_CODE (x
) != REG
)
5601 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
5603 return (regno
<= LAST_LO_REGNUM
5604 || regno
> LAST_VIRTUAL_REGISTER
5605 || regno
== FRAME_POINTER_REGNUM
5606 || (GET_MODE_SIZE (mode
) >= 4
5607 && (regno
== STACK_POINTER_REGNUM
5608 || regno
>= FIRST_PSEUDO_REGISTER
5609 || x
== hard_frame_pointer_rtx
5610 || x
== arg_pointer_rtx
)));
5613 /* Return nonzero if x is a legitimate index register. This is the case
5614 for any base register that can access a QImode object. */
5616 thumb1_index_register_rtx_p (rtx x
, int strict_p
)
5618 return thumb1_base_register_rtx_p (x
, QImode
, strict_p
);
5621 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
5623 The AP may be eliminated to either the SP or the FP, so we use the
5624 least common denominator, e.g. SImode, and offsets from 0 to 64.
5626 ??? Verify whether the above is the right approach.
5628 ??? Also, the FP may be eliminated to the SP, so perhaps that
5629 needs special handling also.
5631 ??? Look at how the mips16 port solves this problem. It probably uses
5632 better ways to solve some of these problems.
5634 Although it is not incorrect, we don't accept QImode and HImode
5635 addresses based on the frame pointer or arg pointer until the
5636 reload pass starts. This is so that eliminating such addresses
5637 into stack based ones won't produce impossible code. */
5639 thumb1_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
5641 /* ??? Not clear if this is right. Experiment. */
5642 if (GET_MODE_SIZE (mode
) < 4
5643 && !(reload_in_progress
|| reload_completed
)
5644 && (reg_mentioned_p (frame_pointer_rtx
, x
)
5645 || reg_mentioned_p (arg_pointer_rtx
, x
)
5646 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
5647 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
5648 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
5649 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
5652 /* Accept any base register. SP only in SImode or larger. */
5653 else if (thumb1_base_register_rtx_p (x
, mode
, strict_p
))
5656 /* This is PC relative data before arm_reorg runs. */
5657 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
5658 && GET_CODE (x
) == SYMBOL_REF
5659 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
)
5662 /* This is PC relative data after arm_reorg runs. */
5663 else if ((GET_MODE_SIZE (mode
) >= 4 || mode
== HFmode
)
5665 && (GET_CODE (x
) == LABEL_REF
5666 || (GET_CODE (x
) == CONST
5667 && GET_CODE (XEXP (x
, 0)) == PLUS
5668 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5669 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5672 /* Post-inc indexing only supported for SImode and larger. */
5673 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
5674 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
))
5677 else if (GET_CODE (x
) == PLUS
)
5679 /* REG+REG address can be any two index registers. */
5680 /* We disallow FRAME+REG addressing since we know that FRAME
5681 will be replaced with STACK, and SP relative addressing only
5682 permits SP+OFFSET. */
5683 if (GET_MODE_SIZE (mode
) <= 4
5684 && XEXP (x
, 0) != frame_pointer_rtx
5685 && XEXP (x
, 1) != frame_pointer_rtx
5686 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
5687 && thumb1_index_register_rtx_p (XEXP (x
, 1), strict_p
))
5690 /* REG+const has 5-7 bit offset for non-SP registers. */
5691 else if ((thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
5692 || XEXP (x
, 0) == arg_pointer_rtx
)
5693 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5694 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
5697 /* REG+const has 10-bit offset for SP, but only SImode and
5698 larger is supported. */
5699 /* ??? Should probably check for DI/DFmode overflow here
5700 just like GO_IF_LEGITIMATE_OFFSET does. */
5701 else if (GET_CODE (XEXP (x
, 0)) == REG
5702 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
5703 && GET_MODE_SIZE (mode
) >= 4
5704 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5705 && INTVAL (XEXP (x
, 1)) >= 0
5706 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
5707 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
5710 else if (GET_CODE (XEXP (x
, 0)) == REG
5711 && (REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
5712 || REGNO (XEXP (x
, 0)) == ARG_POINTER_REGNUM
5713 || (REGNO (XEXP (x
, 0)) >= FIRST_VIRTUAL_REGISTER
5714 && REGNO (XEXP (x
, 0)) <= LAST_VIRTUAL_REGISTER
))
5715 && GET_MODE_SIZE (mode
) >= 4
5716 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5717 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
5721 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
5722 && GET_MODE_SIZE (mode
) == 4
5723 && GET_CODE (x
) == SYMBOL_REF
5724 && CONSTANT_POOL_ADDRESS_P (x
)
5726 && symbol_mentioned_p (get_pool_constant (x
))
5727 && ! pcrel_constant_p (get_pool_constant (x
))))
5733 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
5734 instruction of mode MODE. */
5736 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
5738 switch (GET_MODE_SIZE (mode
))
5741 return val
>= 0 && val
< 32;
5744 return val
>= 0 && val
< 64 && (val
& 1) == 0;
5748 && (val
+ GET_MODE_SIZE (mode
)) <= 128
5754 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
5757 return arm_legitimate_address_outer_p (mode
, x
, SET
, strict_p
);
5758 else if (TARGET_THUMB2
)
5759 return thumb2_legitimate_address_p (mode
, x
, strict_p
);
5760 else /* if (TARGET_THUMB1) */
5761 return thumb1_legitimate_address_p (mode
, x
, strict_p
);
5764 /* Build the SYMBOL_REF for __tls_get_addr. */
5766 static GTY(()) rtx tls_get_addr_libfunc
;
5769 get_tls_get_addr (void)
5771 if (!tls_get_addr_libfunc
)
5772 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
5773 return tls_get_addr_libfunc
;
5777 arm_load_tp (rtx target
)
5780 target
= gen_reg_rtx (SImode
);
5784 /* Can return in any reg. */
5785 emit_insn (gen_load_tp_hard (target
));
5789 /* Always returned in r0. Immediately copy the result into a pseudo,
5790 otherwise other uses of r0 (e.g. setting up function arguments) may
5791 clobber the value. */
5795 emit_insn (gen_load_tp_soft ());
5797 tmp
= gen_rtx_REG (SImode
, 0);
5798 emit_move_insn (target
, tmp
);
5804 load_tls_operand (rtx x
, rtx reg
)
5808 if (reg
== NULL_RTX
)
5809 reg
= gen_reg_rtx (SImode
);
5811 tmp
= gen_rtx_CONST (SImode
, x
);
5813 emit_move_insn (reg
, tmp
);
5819 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
5821 rtx insns
, label
, labelno
, sum
;
5825 labelno
= GEN_INT (pic_labelno
++);
5826 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5827 label
= gen_rtx_CONST (VOIDmode
, label
);
5829 sum
= gen_rtx_UNSPEC (Pmode
,
5830 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
5831 GEN_INT (TARGET_ARM
? 8 : 4)),
5833 reg
= load_tls_operand (sum
, reg
);
5836 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
5837 else if (TARGET_THUMB2
)
5838 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5839 else /* TARGET_THUMB1 */
5840 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5842 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
, LCT_PURE
, /* LCT_CONST? */
5843 Pmode
, 1, reg
, Pmode
);
5845 insns
= get_insns ();
5852 legitimize_tls_address (rtx x
, rtx reg
)
5854 rtx dest
, tp
, label
, labelno
, sum
, insns
, ret
, eqv
, addend
;
5855 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
5859 case TLS_MODEL_GLOBAL_DYNAMIC
:
5860 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
5861 dest
= gen_reg_rtx (Pmode
);
5862 emit_libcall_block (insns
, dest
, ret
, x
);
5865 case TLS_MODEL_LOCAL_DYNAMIC
:
5866 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
5868 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
5869 share the LDM result with other LD model accesses. */
5870 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
5872 dest
= gen_reg_rtx (Pmode
);
5873 emit_libcall_block (insns
, dest
, ret
, eqv
);
5875 /* Load the addend. */
5876 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (TLS_LDO32
)),
5878 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
5879 return gen_rtx_PLUS (Pmode
, dest
, addend
);
5881 case TLS_MODEL_INITIAL_EXEC
:
5882 labelno
= GEN_INT (pic_labelno
++);
5883 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
5884 label
= gen_rtx_CONST (VOIDmode
, label
);
5885 sum
= gen_rtx_UNSPEC (Pmode
,
5886 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
5887 GEN_INT (TARGET_ARM
? 8 : 4)),
5889 reg
= load_tls_operand (sum
, reg
);
5892 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
5893 else if (TARGET_THUMB2
)
5894 emit_insn (gen_tls_load_dot_plus_four (reg
, NULL
, reg
, labelno
));
5897 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
5898 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
5901 tp
= arm_load_tp (NULL_RTX
);
5903 return gen_rtx_PLUS (Pmode
, tp
, reg
);
5905 case TLS_MODEL_LOCAL_EXEC
:
5906 tp
= arm_load_tp (NULL_RTX
);
5908 reg
= gen_rtx_UNSPEC (Pmode
,
5909 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
5911 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
5913 return gen_rtx_PLUS (Pmode
, tp
, reg
);
5920 /* Try machine-dependent ways of modifying an illegitimate address
5921 to be legitimate. If we find one, return the new, valid address. */
5923 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
5927 /* TODO: legitimize_address for Thumb2. */
5930 return thumb_legitimize_address (x
, orig_x
, mode
);
5933 if (arm_tls_symbol_p (x
))
5934 return legitimize_tls_address (x
, NULL_RTX
);
5936 if (GET_CODE (x
) == PLUS
)
5938 rtx xop0
= XEXP (x
, 0);
5939 rtx xop1
= XEXP (x
, 1);
5941 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
5942 xop0
= force_reg (SImode
, xop0
);
5944 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
5945 xop1
= force_reg (SImode
, xop1
);
5947 if (ARM_BASE_REGISTER_RTX_P (xop0
)
5948 && GET_CODE (xop1
) == CONST_INT
)
5950 HOST_WIDE_INT n
, low_n
;
5954 /* VFP addressing modes actually allow greater offsets, but for
5955 now we just stick with the lowest common denominator. */
5957 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
5969 low_n
= ((mode
) == TImode
? 0
5970 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
5974 base_reg
= gen_reg_rtx (SImode
);
5975 val
= force_operand (plus_constant (xop0
, n
), NULL_RTX
);
5976 emit_move_insn (base_reg
, val
);
5977 x
= plus_constant (base_reg
, low_n
);
5979 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
5980 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
5983 /* XXX We don't allow MINUS any more -- see comment in
5984 arm_legitimate_address_outer_p (). */
5985 else if (GET_CODE (x
) == MINUS
)
5987 rtx xop0
= XEXP (x
, 0);
5988 rtx xop1
= XEXP (x
, 1);
5990 if (CONSTANT_P (xop0
))
5991 xop0
= force_reg (SImode
, xop0
);
5993 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
5994 xop1
= force_reg (SImode
, xop1
);
5996 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
5997 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
6000 /* Make sure to take full advantage of the pre-indexed addressing mode
6001 with absolute addresses which often allows for the base register to
6002 be factorized for multiple adjacent memory references, and it might
6003 even allows for the mini pool to be avoided entirely. */
6004 else if (GET_CODE (x
) == CONST_INT
&& optimize
> 0)
6007 HOST_WIDE_INT mask
, base
, index
;
6010 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
6011 use a 8-bit index. So let's use a 12-bit index for SImode only and
6012 hope that arm_gen_constant will enable ldrb to use more bits. */
6013 bits
= (mode
== SImode
) ? 12 : 8;
6014 mask
= (1 << bits
) - 1;
6015 base
= INTVAL (x
) & ~mask
;
6016 index
= INTVAL (x
) & mask
;
6017 if (bit_count (base
& 0xffffffff) > (32 - bits
)/2)
6019 /* It'll most probably be more efficient to generate the base
6020 with more bits set and use a negative index instead. */
6024 base_reg
= force_reg (SImode
, GEN_INT (base
));
6025 x
= plus_constant (base_reg
, index
);
6030 /* We need to find and carefully transform any SYMBOL and LABEL
6031 references; so go back to the original address expression. */
6032 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
6034 if (new_x
!= orig_x
)
6042 /* Try machine-dependent ways of modifying an illegitimate Thumb address
6043 to be legitimate. If we find one, return the new, valid address. */
6045 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
6047 if (arm_tls_symbol_p (x
))
6048 return legitimize_tls_address (x
, NULL_RTX
);
6050 if (GET_CODE (x
) == PLUS
6051 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6052 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
6053 || INTVAL (XEXP (x
, 1)) < 0))
6055 rtx xop0
= XEXP (x
, 0);
6056 rtx xop1
= XEXP (x
, 1);
6057 HOST_WIDE_INT offset
= INTVAL (xop1
);
6059 /* Try and fold the offset into a biasing of the base register and
6060 then offsetting that. Don't do this when optimizing for space
6061 since it can cause too many CSEs. */
6062 if (optimize_size
&& offset
>= 0
6063 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
6065 HOST_WIDE_INT delta
;
6068 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
6069 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
6070 delta
= 31 * GET_MODE_SIZE (mode
);
6072 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
6074 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
6076 x
= plus_constant (xop0
, delta
);
6078 else if (offset
< 0 && offset
> -256)
6079 /* Small negative offsets are best done with a subtract before the
6080 dereference, forcing these into a register normally takes two
6082 x
= force_operand (x
, NULL_RTX
);
6085 /* For the remaining cases, force the constant into a register. */
6086 xop1
= force_reg (SImode
, xop1
);
6087 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
6090 else if (GET_CODE (x
) == PLUS
6091 && s_register_operand (XEXP (x
, 1), SImode
)
6092 && !s_register_operand (XEXP (x
, 0), SImode
))
6094 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
6096 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
6101 /* We need to find and carefully transform any SYMBOL and LABEL
6102 references; so go back to the original address expression. */
6103 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
6105 if (new_x
!= orig_x
)
6113 thumb_legitimize_reload_address (rtx
*x_p
,
6114 enum machine_mode mode
,
6115 int opnum
, int type
,
6116 int ind_levels ATTRIBUTE_UNUSED
)
6120 if (GET_CODE (x
) == PLUS
6121 && GET_MODE_SIZE (mode
) < 4
6122 && REG_P (XEXP (x
, 0))
6123 && XEXP (x
, 0) == stack_pointer_rtx
6124 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6125 && !thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
6130 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
6131 Pmode
, VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
6135 /* If both registers are hi-regs, then it's better to reload the
6136 entire expression rather than each register individually. That
6137 only requires one reload register rather than two. */
6138 if (GET_CODE (x
) == PLUS
6139 && REG_P (XEXP (x
, 0))
6140 && REG_P (XEXP (x
, 1))
6141 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 0), mode
)
6142 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x
, 1), mode
))
6147 push_reload (orig_x
, NULL_RTX
, x_p
, NULL
, MODE_BASE_REG_CLASS (mode
),
6148 Pmode
, VOIDmode
, 0, 0, opnum
, (enum reload_type
) type
);
6155 /* Test for various thread-local symbols. */
6157 /* Return TRUE if X is a thread-local symbol. */
6160 arm_tls_symbol_p (rtx x
)
6162 if (! TARGET_HAVE_TLS
)
6165 if (GET_CODE (x
) != SYMBOL_REF
)
6168 return SYMBOL_REF_TLS_MODEL (x
) != 0;
6171 /* Helper for arm_tls_referenced_p. */
6174 arm_tls_operand_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6176 if (GET_CODE (*x
) == SYMBOL_REF
)
6177 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
6179 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
6180 TLS offsets, not real symbol references. */
6181 if (GET_CODE (*x
) == UNSPEC
6182 && XINT (*x
, 1) == UNSPEC_TLS
)
6188 /* Return TRUE if X contains any TLS symbol references. */
6191 arm_tls_referenced_p (rtx x
)
6193 if (! TARGET_HAVE_TLS
)
6196 return for_each_rtx (&x
, arm_tls_operand_p_1
, NULL
);
6199 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6202 arm_cannot_force_const_mem (rtx x
)
6206 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
6208 split_const (x
, &base
, &offset
);
6209 if (GET_CODE (base
) == SYMBOL_REF
6210 && !offset_within_block_p (base
, INTVAL (offset
)))
6213 return arm_tls_referenced_p (x
);
6216 #define REG_OR_SUBREG_REG(X) \
6217 (GET_CODE (X) == REG \
6218 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
6220 #define REG_OR_SUBREG_RTX(X) \
6221 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
6223 #ifndef COSTS_N_INSNS
6224 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
6227 thumb1_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
6229 enum machine_mode mode
= GET_MODE (x
);
6242 return COSTS_N_INSNS (1);
6245 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6248 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
6255 return COSTS_N_INSNS (2) + cycles
;
6257 return COSTS_N_INSNS (1) + 16;
6260 return (COSTS_N_INSNS (1)
6261 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
6262 + GET_CODE (SET_DEST (x
)) == MEM
));
6267 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
6269 if (thumb_shiftable_const (INTVAL (x
)))
6270 return COSTS_N_INSNS (2);
6271 return COSTS_N_INSNS (3);
6273 else if ((outer
== PLUS
|| outer
== COMPARE
)
6274 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
6276 else if ((outer
== IOR
|| outer
== XOR
|| outer
== AND
)
6277 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
6278 return COSTS_N_INSNS (1);
6279 else if (outer
== AND
)
6282 /* This duplicates the tests in the andsi3 expander. */
6283 for (i
= 9; i
<= 31; i
++)
6284 if ((((HOST_WIDE_INT
) 1) << i
) - 1 == INTVAL (x
)
6285 || (((HOST_WIDE_INT
) 1) << i
) - 1 == ~INTVAL (x
))
6286 return COSTS_N_INSNS (2);
6288 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
6289 || outer
== LSHIFTRT
)
6291 return COSTS_N_INSNS (2);
6297 return COSTS_N_INSNS (3);
6315 /* XXX another guess. */
6316 /* Memory costs quite a lot for the first word, but subsequent words
6317 load at the equivalent of a single insn each. */
6318 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
6319 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
6324 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
6329 /* XXX still guessing. */
6330 switch (GET_MODE (XEXP (x
, 0)))
6333 return (1 + (mode
== DImode
? 4 : 0)
6334 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
6337 return (4 + (mode
== DImode
? 4 : 0)
6338 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
6341 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
6353 arm_rtx_costs_1 (rtx x
, enum rtx_code outer
, int* total
, bool speed
)
6355 enum machine_mode mode
= GET_MODE (x
);
6356 enum rtx_code subcode
;
6358 enum rtx_code code
= GET_CODE (x
);
6364 /* Memory costs quite a lot for the first word, but subsequent words
6365 load at the equivalent of a single insn each. */
6366 *total
= COSTS_N_INSNS (2 + ARM_NUM_REGS (mode
));
6373 if (TARGET_HARD_FLOAT
&& mode
== SFmode
)
6374 *total
= COSTS_N_INSNS (2);
6375 else if (TARGET_HARD_FLOAT
&& mode
== DFmode
&& !TARGET_VFP_SINGLE
)
6376 *total
= COSTS_N_INSNS (4);
6378 *total
= COSTS_N_INSNS (20);
6382 if (GET_CODE (XEXP (x
, 1)) == REG
)
6383 *total
= COSTS_N_INSNS (1); /* Need to subtract from 32 */
6384 else if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6385 *total
= rtx_cost (XEXP (x
, 1), code
, speed
);
6391 *total
+= COSTS_N_INSNS (4);
6396 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
6397 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6400 *total
+= COSTS_N_INSNS (3);
6404 *total
+= COSTS_N_INSNS (1);
6405 /* Increase the cost of complex shifts because they aren't any faster,
6406 and reduce dual issue opportunities. */
6407 if (arm_tune_cortex_a9
6408 && outer
!= SET
&& GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6416 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6418 if (TARGET_HARD_FLOAT
&& (mode
== SFmode
|| mode
== DFmode
))
6419 *total
= COSTS_N_INSNS (1);
6421 *total
= COSTS_N_INSNS (20);
6424 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
6425 /* Thumb2 does not have RSB, so all arguments must be
6426 registers (subtracting a constant is canonicalized as
6427 addition of the negated constant). */
6433 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
6434 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6435 && const_ok_for_arm (INTVAL (XEXP (x
, 0))))
6437 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6441 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6442 && const_ok_for_arm (INTVAL (XEXP (x
, 1))))
6444 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6451 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6453 if (TARGET_HARD_FLOAT
6455 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
6457 *total
= COSTS_N_INSNS (1);
6458 if (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
6459 && arm_const_double_rtx (XEXP (x
, 0)))
6461 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6465 if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
6466 && arm_const_double_rtx (XEXP (x
, 1)))
6468 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6474 *total
= COSTS_N_INSNS (20);
6478 *total
= COSTS_N_INSNS (1);
6479 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6480 && const_ok_for_arm (INTVAL (XEXP (x
, 0))))
6482 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6486 subcode
= GET_CODE (XEXP (x
, 1));
6487 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
6488 || subcode
== LSHIFTRT
6489 || subcode
== ROTATE
|| subcode
== ROTATERT
)
6491 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6492 *total
+= rtx_cost (XEXP (XEXP (x
, 1), 0), subcode
, speed
);
6496 /* A shift as a part of RSB costs no more than RSB itself. */
6497 if (GET_CODE (XEXP (x
, 0)) == MULT
6498 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
6500 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), code
, speed
);
6501 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6506 && power_of_two_operand (XEXP (XEXP (x
, 1), 1), SImode
))
6508 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6509 *total
+= rtx_cost (XEXP (XEXP (x
, 1), 0), subcode
, speed
);
6513 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == RTX_COMPARE
6514 || GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == RTX_COMM_COMPARE
)
6516 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, speed
);
6517 if (GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
6518 && REGNO (XEXP (XEXP (x
, 1), 0)) != CC_REGNUM
)
6519 *total
+= COSTS_N_INSNS (1);
6527 if (code
== PLUS
&& arm_arch6
&& mode
== SImode
6528 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
6529 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
6531 *total
= COSTS_N_INSNS (1);
6532 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), GET_CODE (XEXP (x
, 0)),
6534 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6538 /* MLA: All arguments must be registers. We filter out
6539 multiplication by a power of two, so that we fall down into
6541 if (GET_CODE (XEXP (x
, 0)) == MULT
6542 && !power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
6544 /* The cost comes from the cost of the multiply. */
6548 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6550 if (TARGET_HARD_FLOAT
6552 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
6554 *total
= COSTS_N_INSNS (1);
6555 if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
6556 && arm_const_double_rtx (XEXP (x
, 1)))
6558 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6565 *total
= COSTS_N_INSNS (20);
6569 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == RTX_COMPARE
6570 || GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == RTX_COMM_COMPARE
)
6572 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 1), code
, speed
);
6573 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
6574 && REGNO (XEXP (XEXP (x
, 0), 0)) != CC_REGNUM
)
6575 *total
+= COSTS_N_INSNS (1);
6581 case AND
: case XOR
: case IOR
:
6583 /* Normally the frame registers will be spilt into reg+const during
6584 reload, so it is a bad idea to combine them with other instructions,
6585 since then they might not be moved outside of loops. As a compromise
6586 we allow integration with ops that have a constant as their second
6588 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
6589 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
6590 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6591 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
6592 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
6597 *total
+= COSTS_N_INSNS (2);
6598 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6599 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
6601 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6608 *total
+= COSTS_N_INSNS (1);
6609 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6610 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
6612 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6615 subcode
= GET_CODE (XEXP (x
, 0));
6616 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
6617 || subcode
== LSHIFTRT
6618 || subcode
== ROTATE
|| subcode
== ROTATERT
)
6620 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6621 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6626 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
6628 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6629 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6633 if (subcode
== UMIN
|| subcode
== UMAX
6634 || subcode
== SMIN
|| subcode
== SMAX
)
6636 *total
= COSTS_N_INSNS (3);
6643 /* This should have been handled by the CPU specific routines. */
6647 if (arm_arch3m
&& mode
== SImode
6648 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6649 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
6650 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
6651 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
6652 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
6653 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
6655 *total
= rtx_cost (XEXP (XEXP (x
, 0), 0), LSHIFTRT
, speed
);
6658 *total
= COSTS_N_INSNS (2); /* Plus the cost of the MULT */
6662 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6664 if (TARGET_HARD_FLOAT
6666 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
6668 *total
= COSTS_N_INSNS (1);
6671 *total
= COSTS_N_INSNS (2);
6677 *total
= COSTS_N_INSNS (ARM_NUM_REGS(mode
));
6678 if (mode
== SImode
&& code
== NOT
)
6680 subcode
= GET_CODE (XEXP (x
, 0));
6681 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
6682 || subcode
== LSHIFTRT
6683 || subcode
== ROTATE
|| subcode
== ROTATERT
6685 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
)))
6687 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6688 /* Register shifts cost an extra cycle. */
6689 if (GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
6690 *total
+= COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x
, 0), 1),
6699 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
6701 *total
= COSTS_N_INSNS (4);
6705 operand
= XEXP (x
, 0);
6707 if (!((GET_RTX_CLASS (GET_CODE (operand
)) == RTX_COMPARE
6708 || GET_RTX_CLASS (GET_CODE (operand
)) == RTX_COMM_COMPARE
)
6709 && GET_CODE (XEXP (operand
, 0)) == REG
6710 && REGNO (XEXP (operand
, 0)) == CC_REGNUM
))
6711 *total
+= COSTS_N_INSNS (1);
6712 *total
+= (rtx_cost (XEXP (x
, 1), code
, speed
)
6713 + rtx_cost (XEXP (x
, 2), code
, speed
));
6717 if (mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
6719 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, speed
);
6725 if ((GET_CODE (XEXP (x
, 0)) != REG
|| REGNO (XEXP (x
, 0)) != CC_REGNUM
)
6726 && mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
6728 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, speed
);
6734 if ((GET_CODE (XEXP (x
, 0)) != REG
|| REGNO (XEXP (x
, 0)) != CC_REGNUM
)
6735 && mode
== SImode
&& XEXP (x
, 1) == const0_rtx
)
6737 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, speed
);
6757 /* SCC insns. In the case where the comparison has already been
6758 performed, then they cost 2 instructions. Otherwise they need
6759 an additional comparison before them. */
6760 *total
= COSTS_N_INSNS (2);
6761 if (GET_CODE (XEXP (x
, 0)) == REG
&& REGNO (XEXP (x
, 0)) == CC_REGNUM
)
6768 if (GET_CODE (XEXP (x
, 0)) == REG
&& REGNO (XEXP (x
, 0)) == CC_REGNUM
)
6774 *total
+= COSTS_N_INSNS (1);
6775 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6776 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
))
6778 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6782 subcode
= GET_CODE (XEXP (x
, 0));
6783 if (subcode
== ASHIFT
|| subcode
== ASHIFTRT
6784 || subcode
== LSHIFTRT
6785 || subcode
== ROTATE
|| subcode
== ROTATERT
)
6787 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6788 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6793 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
6795 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6796 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), subcode
, speed
);
6806 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, speed
);
6807 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
6808 || !const_ok_for_arm (INTVAL (XEXP (x
, 1))))
6809 *total
+= rtx_cost (XEXP (x
, 1), code
, speed
);
6813 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6815 if (TARGET_HARD_FLOAT
6817 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
6819 *total
= COSTS_N_INSNS (1);
6822 *total
= COSTS_N_INSNS (20);
6825 *total
= COSTS_N_INSNS (1);
6827 *total
+= COSTS_N_INSNS (3);
6831 if (GET_MODE_CLASS (mode
) == MODE_INT
)
6835 *total
+= COSTS_N_INSNS (1);
6837 if (GET_MODE (XEXP (x
, 0)) != SImode
)
6841 if (GET_CODE (XEXP (x
, 0)) != MEM
)
6842 *total
+= COSTS_N_INSNS (1);
6844 else if (!arm_arch4
|| GET_CODE (XEXP (x
, 0)) != MEM
)
6845 *total
+= COSTS_N_INSNS (2);
6854 if (GET_MODE_CLASS (mode
) == MODE_INT
)
6857 *total
+= COSTS_N_INSNS (1);
6859 if (GET_MODE (XEXP (x
, 0)) != SImode
)
6863 if (GET_CODE (XEXP (x
, 0)) != MEM
)
6864 *total
+= COSTS_N_INSNS (1);
6866 else if (!arm_arch4
|| GET_CODE (XEXP (x
, 0)) != MEM
)
6867 *total
+= COSTS_N_INSNS (GET_MODE (XEXP (x
, 0)) == QImode
?
6874 switch (GET_MODE (XEXP (x
, 0)))
6881 *total
= COSTS_N_INSNS (1);
6891 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, speed
);
6895 if (const_ok_for_arm (INTVAL (x
))
6896 || const_ok_for_arm (~INTVAL (x
)))
6897 *total
= COSTS_N_INSNS (1);
6899 *total
= COSTS_N_INSNS (arm_gen_constant (SET
, mode
, NULL_RTX
,
6900 INTVAL (x
), NULL_RTX
,
6907 *total
= COSTS_N_INSNS (3);
6911 *total
= COSTS_N_INSNS (1);
6915 *total
= COSTS_N_INSNS (1);
6916 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
6920 if (TARGET_HARD_FLOAT
&& vfp3_const_double_rtx (x
)
6921 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
6922 *total
= COSTS_N_INSNS (1);
6924 *total
= COSTS_N_INSNS (4);
6928 *total
= COSTS_N_INSNS (4);
6933 /* Estimates the size cost of thumb1 instructions.
6934 For now most of the code is copied from thumb1_rtx_costs. We need more
6935 fine grain tuning when we have more related test cases. */
6937 thumb1_size_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
6939 enum machine_mode mode
= GET_MODE (x
);
6952 return COSTS_N_INSNS (1);
6955 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6957 /* Thumb1 mul instruction can't operate on const. We must Load it
6958 into a register first. */
6959 int const_size
= thumb1_size_rtx_costs (XEXP (x
, 1), CONST_INT
, SET
);
6960 return COSTS_N_INSNS (1) + const_size
;
6962 return COSTS_N_INSNS (1);
6965 return (COSTS_N_INSNS (1)
6966 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
6967 + GET_CODE (SET_DEST (x
)) == MEM
));
6972 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
6974 if (thumb_shiftable_const (INTVAL (x
)))
6975 return COSTS_N_INSNS (2);
6976 return COSTS_N_INSNS (3);
6978 else if ((outer
== PLUS
|| outer
== COMPARE
)
6979 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
6981 else if ((outer
== IOR
|| outer
== XOR
|| outer
== AND
)
6982 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
6983 return COSTS_N_INSNS (1);
6984 else if (outer
== AND
)
6987 /* This duplicates the tests in the andsi3 expander. */
6988 for (i
= 9; i
<= 31; i
++)
6989 if ((((HOST_WIDE_INT
) 1) << i
) - 1 == INTVAL (x
)
6990 || (((HOST_WIDE_INT
) 1) << i
) - 1 == ~INTVAL (x
))
6991 return COSTS_N_INSNS (2);
6993 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
6994 || outer
== LSHIFTRT
)
6996 return COSTS_N_INSNS (2);
7002 return COSTS_N_INSNS (3);
7020 /* XXX another guess. */
7021 /* Memory costs quite a lot for the first word, but subsequent words
7022 load at the equivalent of a single insn each. */
7023 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
7024 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
7029 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
7034 /* XXX still guessing. */
7035 switch (GET_MODE (XEXP (x
, 0)))
7038 return (1 + (mode
== DImode
? 4 : 0)
7039 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
7042 return (4 + (mode
== DImode
? 4 : 0)
7043 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
7046 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
7057 /* RTX costs when optimizing for size. */
7059 arm_size_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7062 enum machine_mode mode
= GET_MODE (x
);
7065 *total
= thumb1_size_rtx_costs (x
, code
, outer_code
);
7069 /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */
7073 /* A memory access costs 1 insn if the mode is small, or the address is
7074 a single register, otherwise it costs one insn per word. */
7075 if (REG_P (XEXP (x
, 0)))
7076 *total
= COSTS_N_INSNS (1);
7078 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7085 /* Needs a libcall, so it costs about this. */
7086 *total
= COSTS_N_INSNS (2);
7090 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
7092 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), code
, false);
7100 if (mode
== DImode
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7102 *total
= COSTS_N_INSNS (3) + rtx_cost (XEXP (x
, 0), code
, false);
7105 else if (mode
== SImode
)
7107 *total
= COSTS_N_INSNS (1) + rtx_cost (XEXP (x
, 0), code
, false);
7108 /* Slightly disparage register shifts, but not by much. */
7109 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
7110 *total
+= 1 + rtx_cost (XEXP (x
, 1), code
, false);
7114 /* Needs a libcall. */
7115 *total
= COSTS_N_INSNS (2);
7119 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
7120 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7122 *total
= COSTS_N_INSNS (1);
7128 enum rtx_code subcode0
= GET_CODE (XEXP (x
, 0));
7129 enum rtx_code subcode1
= GET_CODE (XEXP (x
, 1));
7131 if (subcode0
== ROTATE
|| subcode0
== ROTATERT
|| subcode0
== ASHIFT
7132 || subcode0
== LSHIFTRT
|| subcode0
== ASHIFTRT
7133 || subcode1
== ROTATE
|| subcode1
== ROTATERT
7134 || subcode1
== ASHIFT
|| subcode1
== LSHIFTRT
7135 || subcode1
== ASHIFTRT
)
7137 /* It's just the cost of the two operands. */
7142 *total
= COSTS_N_INSNS (1);
7146 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7150 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
7151 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7153 *total
= COSTS_N_INSNS (1);
7157 /* A shift as a part of ADD costs nothing. */
7158 if (GET_CODE (XEXP (x
, 0)) == MULT
7159 && power_of_two_operand (XEXP (XEXP (x
, 0), 1), SImode
))
7161 *total
= COSTS_N_INSNS (TARGET_THUMB2
? 2 : 1);
7162 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), code
, false);
7163 *total
+= rtx_cost (XEXP (x
, 1), code
, false);
7168 case AND
: case XOR
: case IOR
:
7171 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
7173 if (subcode
== ROTATE
|| subcode
== ROTATERT
|| subcode
== ASHIFT
7174 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
7175 || (code
== AND
&& subcode
== NOT
))
7177 /* It's just the cost of the two operands. */
7183 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7187 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7191 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
7192 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7194 *total
= COSTS_N_INSNS (1);
7200 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7209 if (cc_register (XEXP (x
, 0), VOIDmode
))
7212 *total
= COSTS_N_INSNS (1);
7216 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
7217 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
7218 *total
= COSTS_N_INSNS (1);
7220 *total
= COSTS_N_INSNS (1 + ARM_NUM_REGS (mode
));
7225 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) < 4)
7227 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
7228 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
7231 *total
+= COSTS_N_INSNS (1);
7236 if (!(arm_arch4
&& MEM_P (XEXP (x
, 0))))
7238 switch (GET_MODE (XEXP (x
, 0)))
7241 *total
+= COSTS_N_INSNS (1);
7245 *total
+= COSTS_N_INSNS (arm_arch6
? 1 : 2);
7251 *total
+= COSTS_N_INSNS (2);
7256 *total
+= COSTS_N_INSNS (1);
7261 if (const_ok_for_arm (INTVAL (x
)))
7262 /* A multiplication by a constant requires another instruction
7263 to load the constant to a register. */
7264 *total
= COSTS_N_INSNS ((outer_code
== SET
|| outer_code
== MULT
)
7266 else if (const_ok_for_arm (~INTVAL (x
)))
7267 *total
= COSTS_N_INSNS (outer_code
== AND
? 0 : 1);
7268 else if (const_ok_for_arm (-INTVAL (x
)))
7270 if (outer_code
== COMPARE
|| outer_code
== PLUS
7271 || outer_code
== MINUS
)
7274 *total
= COSTS_N_INSNS (1);
7277 *total
= COSTS_N_INSNS (2);
7283 *total
= COSTS_N_INSNS (2);
7287 *total
= COSTS_N_INSNS (4);
7292 /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
7293 cost of these slightly. */
7294 *total
= COSTS_N_INSNS (1) + 1;
7298 if (mode
!= VOIDmode
)
7299 *total
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
7301 *total
= COSTS_N_INSNS (4); /* How knows? */
7306 /* RTX costs when optimizing for size. */
7308 arm_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
7312 return arm_size_rtx_costs (x
, (enum rtx_code
) code
,
7313 (enum rtx_code
) outer_code
, total
);
7315 return current_tune
->rtx_costs (x
, (enum rtx_code
) code
,
7316 (enum rtx_code
) outer_code
,
7320 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
7321 supported on any "slowmul" cores, so it can be ignored. */
7324 arm_slowmul_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7325 int *total
, bool speed
)
7327 enum machine_mode mode
= GET_MODE (x
);
7331 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
7338 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
7341 *total
= COSTS_N_INSNS (20);
7345 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7347 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
7348 & (unsigned HOST_WIDE_INT
) 0xffffffff);
7349 int cost
, const_ok
= const_ok_for_arm (i
);
7350 int j
, booth_unit_size
;
7352 /* Tune as appropriate. */
7353 cost
= const_ok
? 4 : 8;
7354 booth_unit_size
= 2;
7355 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
7357 i
>>= booth_unit_size
;
7361 *total
= COSTS_N_INSNS (cost
);
7362 *total
+= rtx_cost (XEXP (x
, 0), code
, speed
);
7366 *total
= COSTS_N_INSNS (20);
7370 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);;
7375 /* RTX cost for cores with a fast multiply unit (M variants). */
7378 arm_fastmul_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7379 int *total
, bool speed
)
7381 enum machine_mode mode
= GET_MODE (x
);
7385 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
7389 /* ??? should thumb2 use different costs? */
7393 /* There is no point basing this on the tuning, since it is always the
7394 fast variant if it exists at all. */
7396 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
7397 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
7398 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
7400 *total
= COSTS_N_INSNS(2);
7407 *total
= COSTS_N_INSNS (5);
7411 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7413 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
7414 & (unsigned HOST_WIDE_INT
) 0xffffffff);
7415 int cost
, const_ok
= const_ok_for_arm (i
);
7416 int j
, booth_unit_size
;
7418 /* Tune as appropriate. */
7419 cost
= const_ok
? 4 : 8;
7420 booth_unit_size
= 8;
7421 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
7423 i
>>= booth_unit_size
;
7427 *total
= COSTS_N_INSNS(cost
);
7433 *total
= COSTS_N_INSNS (4);
7437 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7439 if (TARGET_HARD_FLOAT
7441 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
7443 *total
= COSTS_N_INSNS (1);
7448 /* Requires a lib call */
7449 *total
= COSTS_N_INSNS (20);
7453 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
7458 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
7459 so it can be ignored. */
7462 arm_xscale_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7463 int *total
, bool speed
)
7465 enum machine_mode mode
= GET_MODE (x
);
7469 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
7476 if (GET_CODE (XEXP (x
, 0)) != MULT
)
7477 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
7479 /* A COMPARE of a MULT is slow on XScale; the muls instruction
7480 will stall until the multiplication is complete. */
7481 *total
= COSTS_N_INSNS (3);
7485 /* There is no point basing this on the tuning, since it is always the
7486 fast variant if it exists at all. */
7488 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
7489 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
7490 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
7492 *total
= COSTS_N_INSNS (2);
7499 *total
= COSTS_N_INSNS (5);
7503 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7505 /* If operand 1 is a constant we can more accurately
7506 calculate the cost of the multiply. The multiplier can
7507 retire 15 bits on the first cycle and a further 12 on the
7508 second. We do, of course, have to load the constant into
7509 a register first. */
7510 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
7511 /* There's a general overhead of one cycle. */
7513 unsigned HOST_WIDE_INT masked_const
;
7518 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
7520 masked_const
= i
& 0xffff8000;
7521 if (masked_const
!= 0)
7524 masked_const
= i
& 0xf8000000;
7525 if (masked_const
!= 0)
7528 *total
= COSTS_N_INSNS (cost
);
7534 *total
= COSTS_N_INSNS (3);
7538 /* Requires a lib call */
7539 *total
= COSTS_N_INSNS (20);
7543 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
7548 /* RTX costs for 9e (and later) cores. */
7551 arm_9e_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
7552 int *total
, bool speed
)
7554 enum machine_mode mode
= GET_MODE (x
);
7561 *total
= COSTS_N_INSNS (3);
7565 *total
= thumb1_rtx_costs (x
, code
, outer_code
);
7573 /* There is no point basing this on the tuning, since it is always the
7574 fast variant if it exists at all. */
7576 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
7577 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
7578 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
7580 *total
= COSTS_N_INSNS (2);
7587 *total
= COSTS_N_INSNS (5);
7593 *total
= COSTS_N_INSNS (2);
7597 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
7599 if (TARGET_HARD_FLOAT
7601 || (mode
== DFmode
&& !TARGET_VFP_SINGLE
)))
7603 *total
= COSTS_N_INSNS (1);
7608 *total
= COSTS_N_INSNS (20);
7612 return arm_rtx_costs_1 (x
, outer_code
, total
, speed
);
7615 /* All address computations that can be done are free, but rtx cost returns
7616 the same for practically all of them. So we weight the different types
7617 of address here in the order (most pref first):
7618 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
7620 arm_arm_address_cost (rtx x
)
7622 enum rtx_code c
= GET_CODE (x
);
7624 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
7626 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
7631 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7634 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
7644 arm_thumb_address_cost (rtx x
)
7646 enum rtx_code c
= GET_CODE (x
);
7651 && GET_CODE (XEXP (x
, 0)) == REG
7652 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7659 arm_address_cost (rtx x
, bool speed ATTRIBUTE_UNUSED
)
7661 return TARGET_32BIT
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
7665 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
7669 /* Some true dependencies can have a higher cost depending
7670 on precisely how certain input operands are used. */
7672 && REG_NOTE_KIND (link
) == 0
7673 && recog_memoized (insn
) >= 0
7674 && recog_memoized (dep
) >= 0)
7676 int shift_opnum
= get_attr_shift (insn
);
7677 enum attr_type attr_type
= get_attr_type (dep
);
7679 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
7680 operand for INSN. If we have a shifted input operand and the
7681 instruction we depend on is another ALU instruction, then we may
7682 have to account for an additional stall. */
7683 if (shift_opnum
!= 0
7684 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
7686 rtx shifted_operand
;
7689 /* Get the shifted operand. */
7690 extract_insn (insn
);
7691 shifted_operand
= recog_data
.operand
[shift_opnum
];
7693 /* Iterate over all the operands in DEP. If we write an operand
7694 that overlaps with SHIFTED_OPERAND, then we have increase the
7695 cost of this dependency. */
7697 preprocess_constraints ();
7698 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7700 /* We can ignore strict inputs. */
7701 if (recog_data
.operand_type
[opno
] == OP_IN
)
7704 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
7711 /* XXX This is not strictly true for the FPA. */
7712 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
7713 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
7716 /* Call insns don't incur a stall, even if they follow a load. */
7717 if (REG_NOTE_KIND (link
) == 0
7718 && GET_CODE (insn
) == CALL_INSN
)
7721 if ((i_pat
= single_set (insn
)) != NULL
7722 && GET_CODE (SET_SRC (i_pat
)) == MEM
7723 && (d_pat
= single_set (dep
)) != NULL
7724 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
7726 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
7727 /* This is a load after a store, there is no conflict if the load reads
7728 from a cached area. Assume that loads from the stack, and from the
7729 constant pool are cached, and that others will miss. This is a
7732 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
7733 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
7734 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
7735 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
7742 static int fp_consts_inited
= 0;
7744 /* Only zero is valid for VFP. Other values are also valid for FPA. */
7745 static const char * const strings_fp
[8] =
7748 "4", "5", "0.5", "10"
7751 static REAL_VALUE_TYPE values_fp
[8];
7754 init_fp_table (void)
7760 fp_consts_inited
= 1;
7762 fp_consts_inited
= 8;
7764 for (i
= 0; i
< fp_consts_inited
; i
++)
7766 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
7771 /* Return TRUE if rtx X is a valid immediate FP constant. */
7773 arm_const_double_rtx (rtx x
)
7778 if (!fp_consts_inited
)
7781 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7782 if (REAL_VALUE_MINUS_ZERO (r
))
7785 for (i
= 0; i
< fp_consts_inited
; i
++)
7786 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7792 /* Return TRUE if rtx X is a valid immediate FPA constant. */
7794 neg_const_double_rtx_ok_for_fpa (rtx x
)
7799 if (!fp_consts_inited
)
7802 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7803 r
= REAL_VALUE_NEGATE (r
);
7804 if (REAL_VALUE_MINUS_ZERO (r
))
7807 for (i
= 0; i
< 8; i
++)
7808 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7815 /* VFPv3 has a fairly wide range of representable immediates, formed from
7816 "quarter-precision" floating-point values. These can be evaluated using this
7817 formula (with ^ for exponentiation):
7821 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
7822 16 <= n <= 31 and 0 <= r <= 7.
7824 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
7826 - A (most-significant) is the sign bit.
7827 - BCD are the exponent (encoded as r XOR 3).
7828 - EFGH are the mantissa (encoded as n - 16).
7831 /* Return an integer index for a VFPv3 immediate operand X suitable for the
7832 fconst[sd] instruction, or -1 if X isn't suitable. */
7834 vfp3_const_double_index (rtx x
)
7836 REAL_VALUE_TYPE r
, m
;
7838 unsigned HOST_WIDE_INT mantissa
, mant_hi
;
7839 unsigned HOST_WIDE_INT mask
;
7840 HOST_WIDE_INT m1
, m2
;
7841 int point_pos
= 2 * HOST_BITS_PER_WIDE_INT
- 1;
7843 if (!TARGET_VFP3
|| GET_CODE (x
) != CONST_DOUBLE
)
7846 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7848 /* We can't represent these things, so detect them first. */
7849 if (REAL_VALUE_ISINF (r
) || REAL_VALUE_ISNAN (r
) || REAL_VALUE_MINUS_ZERO (r
))
7852 /* Extract sign, exponent and mantissa. */
7853 sign
= REAL_VALUE_NEGATIVE (r
) ? 1 : 0;
7854 r
= REAL_VALUE_ABS (r
);
7855 exponent
= REAL_EXP (&r
);
7856 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
7857 highest (sign) bit, with a fixed binary point at bit point_pos.
7858 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
7859 bits for the mantissa, this may fail (low bits would be lost). */
7860 real_ldexp (&m
, &r
, point_pos
- exponent
);
7861 REAL_VALUE_TO_INT (&m1
, &m2
, m
);
7865 /* If there are bits set in the low part of the mantissa, we can't
7866 represent this value. */
7870 /* Now make it so that mantissa contains the most-significant bits, and move
7871 the point_pos to indicate that the least-significant bits have been
7873 point_pos
-= HOST_BITS_PER_WIDE_INT
;
7876 /* We can permit four significant bits of mantissa only, plus a high bit
7877 which is always 1. */
7878 mask
= ((unsigned HOST_WIDE_INT
)1 << (point_pos
- 5)) - 1;
7879 if ((mantissa
& mask
) != 0)
7882 /* Now we know the mantissa is in range, chop off the unneeded bits. */
7883 mantissa
>>= point_pos
- 5;
7885 /* The mantissa may be zero. Disallow that case. (It's possible to load the
7886 floating-point immediate zero with Neon using an integer-zero load, but
7887 that case is handled elsewhere.) */
7891 gcc_assert (mantissa
>= 16 && mantissa
<= 31);
7893 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
7894 normalized significands are in the range [1, 2). (Our mantissa is shifted
7895 left 4 places at this point relative to normalized IEEE754 values). GCC
7896 internally uses [0.5, 1) (see real.c), so the exponent returned from
7897 REAL_EXP must be altered. */
7898 exponent
= 5 - exponent
;
7900 if (exponent
< 0 || exponent
> 7)
7903 /* Sign, mantissa and exponent are now in the correct form to plug into the
7904 formula described in the comment above. */
7905 return (sign
<< 7) | ((exponent
^ 3) << 4) | (mantissa
- 16);
7908 /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
7910 vfp3_const_double_rtx (rtx x
)
7915 return vfp3_const_double_index (x
) != -1;
7918 /* Recognize immediates which can be used in various Neon instructions. Legal
7919 immediates are described by the following table (for VMVN variants, the
7920 bitwise inverse of the constant shown is recognized. In either case, VMOV
7921 is output and the correct instruction to use for a given constant is chosen
7922 by the assembler). The constant shown is replicated across all elements of
7923 the destination vector.
7925 insn elems variant constant (binary)
7926 ---- ----- ------- -----------------
7927 vmov i32 0 00000000 00000000 00000000 abcdefgh
7928 vmov i32 1 00000000 00000000 abcdefgh 00000000
7929 vmov i32 2 00000000 abcdefgh 00000000 00000000
7930 vmov i32 3 abcdefgh 00000000 00000000 00000000
7931 vmov i16 4 00000000 abcdefgh
7932 vmov i16 5 abcdefgh 00000000
7933 vmvn i32 6 00000000 00000000 00000000 abcdefgh
7934 vmvn i32 7 00000000 00000000 abcdefgh 00000000
7935 vmvn i32 8 00000000 abcdefgh 00000000 00000000
7936 vmvn i32 9 abcdefgh 00000000 00000000 00000000
7937 vmvn i16 10 00000000 abcdefgh
7938 vmvn i16 11 abcdefgh 00000000
7939 vmov i32 12 00000000 00000000 abcdefgh 11111111
7940 vmvn i32 13 00000000 00000000 abcdefgh 11111111
7941 vmov i32 14 00000000 abcdefgh 11111111 11111111
7942 vmvn i32 15 00000000 abcdefgh 11111111 11111111
7944 vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
7945 eeeeeeee ffffffff gggggggg hhhhhhhh
7946 vmov f32 18 aBbbbbbc defgh000 00000000 00000000
7948 For case 18, B = !b. Representable values are exactly those accepted by
7949 vfp3_const_double_index, but are output as floating-point numbers rather
7952 Variants 0-5 (inclusive) may also be used as immediates for the second
7953 operand of VORR/VBIC instructions.
7955 The INVERSE argument causes the bitwise inverse of the given operand to be
7956 recognized instead (used for recognizing legal immediates for the VAND/VORN
7957 pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is
7958 *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be
7959 output, rather than the real insns vbic/vorr).
7961 INVERSE makes no difference to the recognition of float vectors.
7963 The return value is the variant of immediate as shown in the above table, or
7964 -1 if the given value doesn't match any of the listed patterns.
7967 neon_valid_immediate (rtx op
, enum machine_mode mode
, int inverse
,
7968 rtx
*modconst
, int *elementwidth
)
7970 #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \
7972 for (i = 0; i < idx; i += (STRIDE)) \
7977 immtype = (CLASS); \
7978 elsize = (ELSIZE); \
7982 unsigned int i
, elsize
= 0, idx
= 0, n_elts
= CONST_VECTOR_NUNITS (op
);
7983 unsigned int innersize
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
7984 unsigned char bytes
[16];
7985 int immtype
= -1, matches
;
7986 unsigned int invmask
= inverse
? 0xff : 0;
7988 /* Vectors of float constants. */
7989 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
7991 rtx el0
= CONST_VECTOR_ELT (op
, 0);
7994 if (!vfp3_const_double_rtx (el0
))
7997 REAL_VALUE_FROM_CONST_DOUBLE (r0
, el0
);
7999 for (i
= 1; i
< n_elts
; i
++)
8001 rtx elt
= CONST_VECTOR_ELT (op
, i
);
8004 REAL_VALUE_FROM_CONST_DOUBLE (re
, elt
);
8006 if (!REAL_VALUES_EQUAL (r0
, re
))
8011 *modconst
= CONST_VECTOR_ELT (op
, 0);
8019 /* Splat vector constant out into a byte vector. */
8020 for (i
= 0; i
< n_elts
; i
++)
8022 rtx el
= CONST_VECTOR_ELT (op
, i
);
8023 unsigned HOST_WIDE_INT elpart
;
8024 unsigned int part
, parts
;
8026 if (GET_CODE (el
) == CONST_INT
)
8028 elpart
= INTVAL (el
);
8031 else if (GET_CODE (el
) == CONST_DOUBLE
)
8033 elpart
= CONST_DOUBLE_LOW (el
);
8039 for (part
= 0; part
< parts
; part
++)
8042 for (byte
= 0; byte
< innersize
; byte
++)
8044 bytes
[idx
++] = (elpart
& 0xff) ^ invmask
;
8045 elpart
>>= BITS_PER_UNIT
;
8047 if (GET_CODE (el
) == CONST_DOUBLE
)
8048 elpart
= CONST_DOUBLE_HIGH (el
);
8053 gcc_assert (idx
== GET_MODE_SIZE (mode
));
8057 CHECK (4, 32, 0, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0
8058 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
8060 CHECK (4, 32, 1, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]
8061 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
8063 CHECK (4, 32, 2, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
8064 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0);
8066 CHECK (4, 32, 3, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
8067 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == bytes
[3]);
8069 CHECK (2, 16, 4, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0);
8071 CHECK (2, 16, 5, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]);
8073 CHECK (4, 32, 6, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0xff
8074 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
8076 CHECK (4, 32, 7, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]
8077 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
8079 CHECK (4, 32, 8, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
8080 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0xff);
8082 CHECK (4, 32, 9, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
8083 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == bytes
[3]);
8085 CHECK (2, 16, 10, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0xff);
8087 CHECK (2, 16, 11, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]);
8089 CHECK (4, 32, 12, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]
8090 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
8092 CHECK (4, 32, 13, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]
8093 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
8095 CHECK (4, 32, 14, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
8096 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0);
8098 CHECK (4, 32, 15, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
8099 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0xff);
8101 CHECK (1, 8, 16, bytes
[i
] == bytes
[0]);
8103 CHECK (1, 64, 17, (bytes
[i
] == 0 || bytes
[i
] == 0xff)
8104 && bytes
[i
] == bytes
[(i
+ 8) % idx
]);
8112 *elementwidth
= elsize
;
8116 unsigned HOST_WIDE_INT imm
= 0;
8118 /* Un-invert bytes of recognized vector, if necessary. */
8120 for (i
= 0; i
< idx
; i
++)
8121 bytes
[i
] ^= invmask
;
8125 /* FIXME: Broken on 32-bit H_W_I hosts. */
8126 gcc_assert (sizeof (HOST_WIDE_INT
) == 8);
8128 for (i
= 0; i
< 8; i
++)
8129 imm
|= (unsigned HOST_WIDE_INT
) (bytes
[i
] ? 0xff : 0)
8130 << (i
* BITS_PER_UNIT
);
8132 *modconst
= GEN_INT (imm
);
8136 unsigned HOST_WIDE_INT imm
= 0;
8138 for (i
= 0; i
< elsize
/ BITS_PER_UNIT
; i
++)
8139 imm
|= (unsigned HOST_WIDE_INT
) bytes
[i
] << (i
* BITS_PER_UNIT
);
8141 *modconst
= GEN_INT (imm
);
8149 /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly,
8150 VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for
8151 float elements), and a modified constant (whatever should be output for a
8152 VMOV) in *MODCONST. */
8155 neon_immediate_valid_for_move (rtx op
, enum machine_mode mode
,
8156 rtx
*modconst
, int *elementwidth
)
8160 int retval
= neon_valid_immediate (op
, mode
, 0, &tmpconst
, &tmpwidth
);
8166 *modconst
= tmpconst
;
8169 *elementwidth
= tmpwidth
;
8174 /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If
8175 the immediate is valid, write a constant suitable for using as an operand
8176 to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to
8177 *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */
8180 neon_immediate_valid_for_logic (rtx op
, enum machine_mode mode
, int inverse
,
8181 rtx
*modconst
, int *elementwidth
)
8185 int retval
= neon_valid_immediate (op
, mode
, inverse
, &tmpconst
, &tmpwidth
);
8187 if (retval
< 0 || retval
> 5)
8191 *modconst
= tmpconst
;
8194 *elementwidth
= tmpwidth
;
8199 /* Return a string suitable for output of Neon immediate logic operation
8203 neon_output_logic_immediate (const char *mnem
, rtx
*op2
, enum machine_mode mode
,
8204 int inverse
, int quad
)
8206 int width
, is_valid
;
8207 static char templ
[40];
8209 is_valid
= neon_immediate_valid_for_logic (*op2
, mode
, inverse
, op2
, &width
);
8211 gcc_assert (is_valid
!= 0);
8214 sprintf (templ
, "%s.i%d\t%%q0, %%2", mnem
, width
);
8216 sprintf (templ
, "%s.i%d\t%%P0, %%2", mnem
, width
);
8221 /* Output a sequence of pairwise operations to implement a reduction.
8222 NOTE: We do "too much work" here, because pairwise operations work on two
8223 registers-worth of operands in one go. Unfortunately we can't exploit those
8224 extra calculations to do the full operation in fewer steps, I don't think.
8225 Although all vector elements of the result but the first are ignored, we
8226 actually calculate the same result in each of the elements. An alternative
8227 such as initially loading a vector with zero to use as each of the second
8228 operands would use up an additional register and take an extra instruction,
8229 for no particular gain. */
8232 neon_pairwise_reduce (rtx op0
, rtx op1
, enum machine_mode mode
,
8233 rtx (*reduc
) (rtx
, rtx
, rtx
))
8235 enum machine_mode inner
= GET_MODE_INNER (mode
);
8236 unsigned int i
, parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (inner
);
8239 for (i
= parts
/ 2; i
>= 1; i
/= 2)
8241 rtx dest
= (i
== 1) ? op0
: gen_reg_rtx (mode
);
8242 emit_insn (reduc (dest
, tmpsum
, tmpsum
));
8247 /* If VALS is a vector constant that can be loaded into a register
8248 using VDUP, generate instructions to do so and return an RTX to
8249 assign to the register. Otherwise return NULL_RTX. */
8252 neon_vdup_constant (rtx vals
)
8254 enum machine_mode mode
= GET_MODE (vals
);
8255 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
8256 int n_elts
= GET_MODE_NUNITS (mode
);
8257 bool all_same
= true;
8261 if (GET_CODE (vals
) != CONST_VECTOR
|| GET_MODE_SIZE (inner_mode
) > 4)
8264 for (i
= 0; i
< n_elts
; ++i
)
8266 x
= XVECEXP (vals
, 0, i
);
8267 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
8272 /* The elements are not all the same. We could handle repeating
8273 patterns of a mode larger than INNER_MODE here (e.g. int8x8_t
8274 {0, C, 0, C, 0, C, 0, C} which can be loaded using
8278 /* We can load this constant by using VDUP and a constant in a
8279 single ARM register. This will be cheaper than a vector
8282 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, 0));
8283 return gen_rtx_UNSPEC (mode
, gen_rtvec (1, x
),
8287 /* Generate code to load VALS, which is a PARALLEL containing only
8288 constants (for vec_init) or CONST_VECTOR, efficiently into a
8289 register. Returns an RTX to copy into the register, or NULL_RTX
8290 for a PARALLEL that can not be converted into a CONST_VECTOR. */
8293 neon_make_constant (rtx vals
)
8295 enum machine_mode mode
= GET_MODE (vals
);
8297 rtx const_vec
= NULL_RTX
;
8298 int n_elts
= GET_MODE_NUNITS (mode
);
8302 if (GET_CODE (vals
) == CONST_VECTOR
)
8304 else if (GET_CODE (vals
) == PARALLEL
)
8306 /* A CONST_VECTOR must contain only CONST_INTs and
8307 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
8308 Only store valid constants in a CONST_VECTOR. */
8309 for (i
= 0; i
< n_elts
; ++i
)
8311 rtx x
= XVECEXP (vals
, 0, i
);
8312 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
8315 if (n_const
== n_elts
)
8316 const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
8321 if (const_vec
!= NULL
8322 && neon_immediate_valid_for_move (const_vec
, mode
, NULL
, NULL
))
8323 /* Load using VMOV. On Cortex-A8 this takes one cycle. */
8325 else if ((target
= neon_vdup_constant (vals
)) != NULL_RTX
)
8326 /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON
8327 pipeline cycle; creating the constant takes one or two ARM
8330 else if (const_vec
!= NULL_RTX
)
8331 /* Load from constant pool. On Cortex-A8 this takes two cycles
8332 (for either double or quad vectors). We can not take advantage
8333 of single-cycle VLD1 because we need a PC-relative addressing
8337 /* A PARALLEL containing something not valid inside CONST_VECTOR.
8338 We can not construct an initializer. */
8342 /* Initialize vector TARGET to VALS. */
8345 neon_expand_vector_init (rtx target
, rtx vals
)
8347 enum machine_mode mode
= GET_MODE (target
);
8348 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
8349 int n_elts
= GET_MODE_NUNITS (mode
);
8350 int n_var
= 0, one_var
= -1;
8351 bool all_same
= true;
8355 for (i
= 0; i
< n_elts
; ++i
)
8357 x
= XVECEXP (vals
, 0, i
);
8358 if (!CONSTANT_P (x
))
8359 ++n_var
, one_var
= i
;
8361 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
8367 rtx constant
= neon_make_constant (vals
);
8368 if (constant
!= NULL_RTX
)
8370 emit_move_insn (target
, constant
);
8375 /* Splat a single non-constant element if we can. */
8376 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
8378 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, 0));
8379 emit_insn (gen_rtx_SET (VOIDmode
, target
,
8380 gen_rtx_UNSPEC (mode
, gen_rtvec (1, x
),
8385 /* One field is non-constant. Load constant then overwrite varying
8386 field. This is more efficient than using the stack. */
8389 rtx copy
= copy_rtx (vals
);
8392 /* Load constant part of vector, substitute neighboring value for
8394 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
8395 neon_expand_vector_init (target
, copy
);
8397 /* Insert variable. */
8398 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, one_var
));
8399 ops
= gen_rtvec (3, x
, target
, GEN_INT (one_var
));
8400 emit_insn (gen_rtx_SET (VOIDmode
, target
,
8401 gen_rtx_UNSPEC (mode
, ops
, UNSPEC_VSET_LANE
)));
8405 /* Construct the vector in memory one field at a time
8406 and load the whole vector. */
8407 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
8408 for (i
= 0; i
< n_elts
; i
++)
8409 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
8410 i
* GET_MODE_SIZE (inner_mode
)),
8411 XVECEXP (vals
, 0, i
));
8412 emit_move_insn (target
, mem
);
8415 /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise
8416 ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so
8417 reported source locations are bogus. */
8420 bounds_check (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
,
8425 gcc_assert (GET_CODE (operand
) == CONST_INT
);
8427 lane
= INTVAL (operand
);
8429 if (lane
< low
|| lane
>= high
)
8433 /* Bounds-check lanes. */
8436 neon_lane_bounds (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
)
8438 bounds_check (operand
, low
, high
, "lane out of range");
8441 /* Bounds-check constants. */
8444 neon_const_bounds (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
)
8446 bounds_check (operand
, low
, high
, "constant out of range");
8450 neon_element_bits (enum machine_mode mode
)
8453 return GET_MODE_BITSIZE (mode
);
8455 return GET_MODE_BITSIZE (GET_MODE_INNER (mode
));
8459 /* Predicates for `match_operand' and `match_operator'. */
8461 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
8463 cirrus_memory_offset (rtx op
)
8465 /* Reject eliminable registers. */
8466 if (! (reload_in_progress
|| reload_completed
)
8467 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
8468 || reg_mentioned_p (arg_pointer_rtx
, op
)
8469 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
8470 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
8471 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
8472 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
8475 if (GET_CODE (op
) == MEM
)
8481 /* Match: (mem (reg)). */
8482 if (GET_CODE (ind
) == REG
)
8488 if (GET_CODE (ind
) == PLUS
8489 && GET_CODE (XEXP (ind
, 0)) == REG
8490 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
8491 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
8498 /* Return TRUE if OP is a valid coprocessor memory address pattern.
8499 WB is true if full writeback address modes are allowed and is false
8500 if limited writeback address modes (POST_INC and PRE_DEC) are
8504 arm_coproc_mem_operand (rtx op
, bool wb
)
8508 /* Reject eliminable registers. */
8509 if (! (reload_in_progress
|| reload_completed
)
8510 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
8511 || reg_mentioned_p (arg_pointer_rtx
, op
)
8512 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
8513 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
8514 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
8515 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
8518 /* Constants are converted into offsets from labels. */
8519 if (GET_CODE (op
) != MEM
)
8524 if (reload_completed
8525 && (GET_CODE (ind
) == LABEL_REF
8526 || (GET_CODE (ind
) == CONST
8527 && GET_CODE (XEXP (ind
, 0)) == PLUS
8528 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
8529 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
8532 /* Match: (mem (reg)). */
8533 if (GET_CODE (ind
) == REG
)
8534 return arm_address_register_rtx_p (ind
, 0);
8536 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
8537 acceptable in any case (subject to verification by
8538 arm_address_register_rtx_p). We need WB to be true to accept
8539 PRE_INC and POST_DEC. */
8540 if (GET_CODE (ind
) == POST_INC
8541 || GET_CODE (ind
) == PRE_DEC
8543 && (GET_CODE (ind
) == PRE_INC
8544 || GET_CODE (ind
) == POST_DEC
)))
8545 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
8548 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
8549 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
8550 && GET_CODE (XEXP (ind
, 1)) == PLUS
8551 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
8552 ind
= XEXP (ind
, 1);
8557 if (GET_CODE (ind
) == PLUS
8558 && GET_CODE (XEXP (ind
, 0)) == REG
8559 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
8560 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
8561 && INTVAL (XEXP (ind
, 1)) > -1024
8562 && INTVAL (XEXP (ind
, 1)) < 1024
8563 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
8569 /* Return TRUE if OP is a memory operand which we can load or store a vector
8570 to/from. TYPE is one of the following values:
8571 0 - Vector load/stor (vldr)
8572 1 - Core registers (ldm)
8573 2 - Element/structure loads (vld1)
8576 neon_vector_mem_operand (rtx op
, int type
)
8580 /* Reject eliminable registers. */
8581 if (! (reload_in_progress
|| reload_completed
)
8582 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
8583 || reg_mentioned_p (arg_pointer_rtx
, op
)
8584 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
8585 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
8586 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
8587 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
8590 /* Constants are converted into offsets from labels. */
8591 if (GET_CODE (op
) != MEM
)
8596 if (reload_completed
8597 && (GET_CODE (ind
) == LABEL_REF
8598 || (GET_CODE (ind
) == CONST
8599 && GET_CODE (XEXP (ind
, 0)) == PLUS
8600 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
8601 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
8604 /* Match: (mem (reg)). */
8605 if (GET_CODE (ind
) == REG
)
8606 return arm_address_register_rtx_p (ind
, 0);
8608 /* Allow post-increment with Neon registers. */
8609 if (type
!= 1 && (GET_CODE (ind
) == POST_INC
|| GET_CODE (ind
) == PRE_DEC
))
8610 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
8612 /* FIXME: vld1 allows register post-modify. */
8618 && GET_CODE (ind
) == PLUS
8619 && GET_CODE (XEXP (ind
, 0)) == REG
8620 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
8621 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
8622 && INTVAL (XEXP (ind
, 1)) > -1024
8623 && INTVAL (XEXP (ind
, 1)) < 1016
8624 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
8630 /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
8633 neon_struct_mem_operand (rtx op
)
8637 /* Reject eliminable registers. */
8638 if (! (reload_in_progress
|| reload_completed
)
8639 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
8640 || reg_mentioned_p (arg_pointer_rtx
, op
)
8641 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
8642 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
8643 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
8644 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
8647 /* Constants are converted into offsets from labels. */
8648 if (GET_CODE (op
) != MEM
)
8653 if (reload_completed
8654 && (GET_CODE (ind
) == LABEL_REF
8655 || (GET_CODE (ind
) == CONST
8656 && GET_CODE (XEXP (ind
, 0)) == PLUS
8657 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
8658 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
8661 /* Match: (mem (reg)). */
8662 if (GET_CODE (ind
) == REG
)
8663 return arm_address_register_rtx_p (ind
, 0);
8668 /* Return true if X is a register that will be eliminated later on. */
8670 arm_eliminable_register (rtx x
)
8672 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
8673 || REGNO (x
) == ARG_POINTER_REGNUM
8674 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
8675 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
8678 /* Return GENERAL_REGS if a scratch register required to reload x to/from
8679 coprocessor registers. Otherwise return NO_REGS. */
8682 coproc_secondary_reload_class (enum machine_mode mode
, rtx x
, bool wb
)
8686 if (!TARGET_NEON_FP16
)
8687 return GENERAL_REGS
;
8688 if (s_register_operand (x
, mode
) || neon_vector_mem_operand (x
, 2))
8690 return GENERAL_REGS
;
8694 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
8695 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
8696 && neon_vector_mem_operand (x
, 0))
8699 if (arm_coproc_mem_operand (x
, wb
) || s_register_operand (x
, mode
))
8702 return GENERAL_REGS
;
8705 /* Values which must be returned in the most-significant end of the return
8709 arm_return_in_msb (const_tree valtype
)
8711 return (TARGET_AAPCS_BASED
8713 && (AGGREGATE_TYPE_P (valtype
)
8714 || TREE_CODE (valtype
) == COMPLEX_TYPE
));
8717 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
8718 Use by the Cirrus Maverick code which has to workaround
8719 a hardware bug triggered by such instructions. */
8721 arm_memory_load_p (rtx insn
)
8723 rtx body
, lhs
, rhs
;;
8725 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
8728 body
= PATTERN (insn
);
8730 if (GET_CODE (body
) != SET
)
8733 lhs
= XEXP (body
, 0);
8734 rhs
= XEXP (body
, 1);
8736 lhs
= REG_OR_SUBREG_RTX (lhs
);
8738 /* If the destination is not a general purpose
8739 register we do not have to worry. */
8740 if (GET_CODE (lhs
) != REG
8741 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
8744 /* As well as loads from memory we also have to react
8745 to loads of invalid constants which will be turned
8746 into loads from the minipool. */
8747 return (GET_CODE (rhs
) == MEM
8748 || GET_CODE (rhs
) == SYMBOL_REF
8749 || note_invalid_constants (insn
, -1, false));
8752 /* Return TRUE if INSN is a Cirrus instruction. */
8754 arm_cirrus_insn_p (rtx insn
)
8756 enum attr_cirrus attr
;
8758 /* get_attr cannot accept USE or CLOBBER. */
8760 || GET_CODE (insn
) != INSN
8761 || GET_CODE (PATTERN (insn
)) == USE
8762 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
8765 attr
= get_attr_cirrus (insn
);
8767 return attr
!= CIRRUS_NOT
;
8770 /* Cirrus reorg for invalid instruction combinations. */
8772 cirrus_reorg (rtx first
)
8774 enum attr_cirrus attr
;
8775 rtx body
= PATTERN (first
);
8779 /* Any branch must be followed by 2 non Cirrus instructions. */
8780 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
8783 t
= next_nonnote_insn (first
);
8785 if (arm_cirrus_insn_p (t
))
8788 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
8792 emit_insn_after (gen_nop (), first
);
8797 /* (float (blah)) is in parallel with a clobber. */
8798 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
8799 body
= XVECEXP (body
, 0, 0);
8801 if (GET_CODE (body
) == SET
)
8803 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
8805 /* cfldrd, cfldr64, cfstrd, cfstr64 must
8806 be followed by a non Cirrus insn. */
8807 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
8809 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
8810 emit_insn_after (gen_nop (), first
);
8814 else if (arm_memory_load_p (first
))
8816 unsigned int arm_regno
;
8818 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
8819 ldr/cfmv64hr combination where the Rd field is the same
8820 in both instructions must be split with a non Cirrus
8827 /* Get Arm register number for ldr insn. */
8828 if (GET_CODE (lhs
) == REG
)
8829 arm_regno
= REGNO (lhs
);
8832 gcc_assert (GET_CODE (rhs
) == REG
);
8833 arm_regno
= REGNO (rhs
);
8837 first
= next_nonnote_insn (first
);
8839 if (! arm_cirrus_insn_p (first
))
8842 body
= PATTERN (first
);
8844 /* (float (blah)) is in parallel with a clobber. */
8845 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
8846 body
= XVECEXP (body
, 0, 0);
8848 if (GET_CODE (body
) == FLOAT
)
8849 body
= XEXP (body
, 0);
8851 if (get_attr_cirrus (first
) == CIRRUS_MOVE
8852 && GET_CODE (XEXP (body
, 1)) == REG
8853 && arm_regno
== REGNO (XEXP (body
, 1)))
8854 emit_insn_after (gen_nop (), first
);
8860 /* get_attr cannot accept USE or CLOBBER. */
8862 || GET_CODE (first
) != INSN
8863 || GET_CODE (PATTERN (first
)) == USE
8864 || GET_CODE (PATTERN (first
)) == CLOBBER
)
8867 attr
= get_attr_cirrus (first
);
8869 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
8870 must be followed by a non-coprocessor instruction. */
8871 if (attr
== CIRRUS_COMPARE
)
8875 t
= next_nonnote_insn (first
);
8877 if (arm_cirrus_insn_p (t
))
8880 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
8884 emit_insn_after (gen_nop (), first
);
8890 /* Return TRUE if X references a SYMBOL_REF. */
8892 symbol_mentioned_p (rtx x
)
8897 if (GET_CODE (x
) == SYMBOL_REF
)
8900 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
8901 are constant offsets, not symbols. */
8902 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
8905 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
8907 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8913 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8914 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
8917 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
8924 /* Return TRUE if X references a LABEL_REF. */
8926 label_mentioned_p (rtx x
)
8931 if (GET_CODE (x
) == LABEL_REF
)
8934 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
8935 instruction, but they are constant offsets, not symbols. */
8936 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
8939 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
8940 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8946 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8947 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
8950 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
8958 tls_mentioned_p (rtx x
)
8960 switch (GET_CODE (x
))
8963 return tls_mentioned_p (XEXP (x
, 0));
8966 if (XINT (x
, 1) == UNSPEC_TLS
)
8974 /* Must not copy any rtx that uses a pc-relative address. */
8977 arm_note_pic_base (rtx
*x
, void *date ATTRIBUTE_UNUSED
)
8979 if (GET_CODE (*x
) == UNSPEC
8980 && XINT (*x
, 1) == UNSPEC_PIC_BASE
)
8986 arm_cannot_copy_insn_p (rtx insn
)
8988 return for_each_rtx (&PATTERN (insn
), arm_note_pic_base
, NULL
);
8994 enum rtx_code code
= GET_CODE (x
);
9011 /* Return 1 if memory locations are adjacent. */
9013 adjacent_mem_locations (rtx a
, rtx b
)
9015 /* We don't guarantee to preserve the order of these memory refs. */
9016 if (volatile_refs_p (a
) || volatile_refs_p (b
))
9019 if ((GET_CODE (XEXP (a
, 0)) == REG
9020 || (GET_CODE (XEXP (a
, 0)) == PLUS
9021 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
9022 && (GET_CODE (XEXP (b
, 0)) == REG
9023 || (GET_CODE (XEXP (b
, 0)) == PLUS
9024 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
9026 HOST_WIDE_INT val0
= 0, val1
= 0;
9030 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
9032 reg0
= XEXP (XEXP (a
, 0), 0);
9033 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
9038 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
9040 reg1
= XEXP (XEXP (b
, 0), 0);
9041 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
9046 /* Don't accept any offset that will require multiple
9047 instructions to handle, since this would cause the
9048 arith_adjacentmem pattern to output an overlong sequence. */
9049 if (!const_ok_for_op (val0
, PLUS
) || !const_ok_for_op (val1
, PLUS
))
9052 /* Don't allow an eliminable register: register elimination can make
9053 the offset too large. */
9054 if (arm_eliminable_register (reg0
))
9057 val_diff
= val1
- val0
;
9061 /* If the target has load delay slots, then there's no benefit
9062 to using an ldm instruction unless the offset is zero and
9063 we are optimizing for size. */
9064 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
9065 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
9066 && (val_diff
== 4 || val_diff
== -4));
9069 return ((REGNO (reg0
) == REGNO (reg1
))
9070 && (val_diff
== 4 || val_diff
== -4));
9077 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
9078 HOST_WIDE_INT
*load_offset
)
9080 int unsorted_regs
[4];
9081 HOST_WIDE_INT unsorted_offsets
[4];
9086 /* Can only handle 2, 3, or 4 insns at present,
9087 though could be easily extended if required. */
9088 gcc_assert (nops
>= 2 && nops
<= 4);
9090 memset (order
, 0, 4 * sizeof (int));
9092 /* Loop over the operands and check that the memory references are
9093 suitable (i.e. immediate offsets from the same base register). At
9094 the same time, extract the target register, and the memory
9096 for (i
= 0; i
< nops
; i
++)
9101 /* Convert a subreg of a mem into the mem itself. */
9102 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
9103 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
9105 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
9107 /* Don't reorder volatile memory references; it doesn't seem worth
9108 looking for the case where the order is ok anyway. */
9109 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
9112 offset
= const0_rtx
;
9114 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
9115 || (GET_CODE (reg
) == SUBREG
9116 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
9117 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
9118 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
9120 || (GET_CODE (reg
) == SUBREG
9121 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
9122 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
9127 base_reg
= REGNO (reg
);
9128 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
9129 ? REGNO (operands
[i
])
9130 : REGNO (SUBREG_REG (operands
[i
])));
9135 if (base_reg
!= (int) REGNO (reg
))
9136 /* Not addressed from the same base register. */
9139 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
9140 ? REGNO (operands
[i
])
9141 : REGNO (SUBREG_REG (operands
[i
])));
9142 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
9146 /* If it isn't an integer register, or if it overwrites the
9147 base register but isn't the last insn in the list, then
9148 we can't do this. */
9149 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
9150 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
9153 unsorted_offsets
[i
] = INTVAL (offset
);
9156 /* Not a suitable memory address. */
9160 /* All the useful information has now been extracted from the
9161 operands into unsorted_regs and unsorted_offsets; additionally,
9162 order[0] has been set to the lowest numbered register in the
9163 list. Sort the registers into order, and check that the memory
9164 offsets are ascending and adjacent. */
9166 for (i
= 1; i
< nops
; i
++)
9170 order
[i
] = order
[i
- 1];
9171 for (j
= 0; j
< nops
; j
++)
9172 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
9173 && (order
[i
] == order
[i
- 1]
9174 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
9177 /* Have we found a suitable register? if not, one must be used more
9179 if (order
[i
] == order
[i
- 1])
9182 /* Is the memory address adjacent and ascending? */
9183 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
9191 for (i
= 0; i
< nops
; i
++)
9192 regs
[i
] = unsorted_regs
[order
[i
]];
9194 *load_offset
= unsorted_offsets
[order
[0]];
9197 if (unsorted_offsets
[order
[0]] == 0)
9198 return 1; /* ldmia */
9200 if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
9201 return 2; /* ldmib */
9203 if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
9204 return 3; /* ldmda */
9206 if (unsorted_offsets
[order
[nops
- 1]] == -4)
9207 return 4; /* ldmdb */
9209 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
9210 if the offset isn't small enough. The reason 2 ldrs are faster
9211 is because these ARMs are able to do more than one cache access
9212 in a single cycle. The ARM9 and StrongARM have Harvard caches,
9213 whilst the ARM8 has a double bandwidth cache. This means that
9214 these cores can do both an instruction fetch and a data fetch in
9215 a single cycle, so the trick of calculating the address into a
9216 scratch register (one of the result regs) and then doing a load
9217 multiple actually becomes slower (and no smaller in code size).
9218 That is the transformation
9220 ldr rd1, [rbase + offset]
9221 ldr rd2, [rbase + offset + 4]
9225 add rd1, rbase, offset
9226 ldmia rd1, {rd1, rd2}
9228 produces worse code -- '3 cycles + any stalls on rd2' instead of
9229 '2 cycles + any stalls on rd2'. On ARMs with only one cache
9230 access per cycle, the first sequence could never complete in less
9231 than 6 cycles, whereas the ldm sequence would only take 5 and
9232 would make better use of sequential accesses if not hitting the
9235 We cheat here and test 'arm_ld_sched' which we currently know to
9236 only be true for the ARM8, ARM9 and StrongARM. If this ever
9237 changes, then the test below needs to be reworked. */
9238 if (nops
== 2 && arm_ld_sched
)
9241 /* Can't do it without setting up the offset, only do this if it takes
9242 no more than one insn. */
9243 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
9244 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
9248 emit_ldm_seq (rtx
*operands
, int nops
)
9252 HOST_WIDE_INT offset
;
9256 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
9259 strcpy (buf
, "ldm%(ia%)\t");
9263 strcpy (buf
, "ldm%(ib%)\t");
9267 strcpy (buf
, "ldm%(da%)\t");
9271 strcpy (buf
, "ldm%(db%)\t");
9276 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
9277 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
9280 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
9281 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
9283 output_asm_insn (buf
, operands
);
9285 strcpy (buf
, "ldm%(ia%)\t");
9292 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
9293 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
9295 for (i
= 1; i
< nops
; i
++)
9296 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
9297 reg_names
[regs
[i
]]);
9299 strcat (buf
, "}\t%@ phole ldm");
9301 output_asm_insn (buf
, operands
);
9306 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
9307 HOST_WIDE_INT
* load_offset
)
9309 int unsorted_regs
[4];
9310 HOST_WIDE_INT unsorted_offsets
[4];
9315 /* Can only handle 2, 3, or 4 insns at present, though could be easily
9316 extended if required. */
9317 gcc_assert (nops
>= 2 && nops
<= 4);
9319 memset (order
, 0, 4 * sizeof (int));
9321 /* Loop over the operands and check that the memory references are
9322 suitable (i.e. immediate offsets from the same base register). At
9323 the same time, extract the target register, and the memory
9325 for (i
= 0; i
< nops
; i
++)
9330 /* Convert a subreg of a mem into the mem itself. */
9331 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
9332 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
9334 gcc_assert (GET_CODE (operands
[nops
+ i
]) == MEM
);
9336 /* Don't reorder volatile memory references; it doesn't seem worth
9337 looking for the case where the order is ok anyway. */
9338 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
9341 offset
= const0_rtx
;
9343 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
9344 || (GET_CODE (reg
) == SUBREG
9345 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
9346 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
9347 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
9349 || (GET_CODE (reg
) == SUBREG
9350 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
9351 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
9356 base_reg
= REGNO (reg
);
9357 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
9358 ? REGNO (operands
[i
])
9359 : REGNO (SUBREG_REG (operands
[i
])));
9364 if (base_reg
!= (int) REGNO (reg
))
9365 /* Not addressed from the same base register. */
9368 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
9369 ? REGNO (operands
[i
])
9370 : REGNO (SUBREG_REG (operands
[i
])));
9371 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
9375 /* If it isn't an integer register, then we can't do this. */
9376 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
9379 unsorted_offsets
[i
] = INTVAL (offset
);
9382 /* Not a suitable memory address. */
9386 /* All the useful information has now been extracted from the
9387 operands into unsorted_regs and unsorted_offsets; additionally,
9388 order[0] has been set to the lowest numbered register in the
9389 list. Sort the registers into order, and check that the memory
9390 offsets are ascending and adjacent. */
9392 for (i
= 1; i
< nops
; i
++)
9396 order
[i
] = order
[i
- 1];
9397 for (j
= 0; j
< nops
; j
++)
9398 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
9399 && (order
[i
] == order
[i
- 1]
9400 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
9403 /* Have we found a suitable register? if not, one must be used more
9405 if (order
[i
] == order
[i
- 1])
9408 /* Is the memory address adjacent and ascending? */
9409 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
9417 for (i
= 0; i
< nops
; i
++)
9418 regs
[i
] = unsorted_regs
[order
[i
]];
9420 *load_offset
= unsorted_offsets
[order
[0]];
9423 if (unsorted_offsets
[order
[0]] == 0)
9424 return 1; /* stmia */
9426 if (unsorted_offsets
[order
[0]] == 4)
9427 return 2; /* stmib */
9429 if (unsorted_offsets
[order
[nops
- 1]] == 0)
9430 return 3; /* stmda */
9432 if (unsorted_offsets
[order
[nops
- 1]] == -4)
9433 return 4; /* stmdb */
9439 emit_stm_seq (rtx
*operands
, int nops
)
9443 HOST_WIDE_INT offset
;
9447 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
9450 strcpy (buf
, "stm%(ia%)\t");
9454 strcpy (buf
, "stm%(ib%)\t");
9458 strcpy (buf
, "stm%(da%)\t");
9462 strcpy (buf
, "stm%(db%)\t");
9469 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
9470 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
9472 for (i
= 1; i
< nops
; i
++)
9473 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
9474 reg_names
[regs
[i
]]);
9476 strcat (buf
, "}\t%@ phole stm");
9478 output_asm_insn (buf
, operands
);
9482 /* Routines for use in generating RTL. */
9485 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
9486 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
9488 HOST_WIDE_INT offset
= *offsetp
;
9491 int sign
= up
? 1 : -1;
9494 /* XScale has load-store double instructions, but they have stricter
9495 alignment requirements than load-store multiple, so we cannot
9498 For XScale ldm requires 2 + NREGS cycles to complete and blocks
9499 the pipeline until completion.
9507 An ldr instruction takes 1-3 cycles, but does not block the
9516 Best case ldr will always win. However, the more ldr instructions
9517 we issue, the less likely we are to be able to schedule them well.
9518 Using ldr instructions also increases code size.
9520 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
9521 for counts of 3 or 4 regs. */
9522 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
9528 for (i
= 0; i
< count
; i
++)
9530 addr
= plus_constant (from
, i
* 4 * sign
);
9531 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
9532 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
9538 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
9548 result
= gen_rtx_PARALLEL (VOIDmode
,
9549 rtvec_alloc (count
+ (write_back
? 1 : 0)));
9552 XVECEXP (result
, 0, 0)
9553 = gen_rtx_SET (VOIDmode
, from
, plus_constant (from
, count
* 4 * sign
));
9558 for (j
= 0; i
< count
; i
++, j
++)
9560 addr
= plus_constant (from
, j
* 4 * sign
);
9561 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
9562 XVECEXP (result
, 0, i
)
9563 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
9574 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
9575 int write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
9577 HOST_WIDE_INT offset
= *offsetp
;
9580 int sign
= up
? 1 : -1;
9583 /* See arm_gen_load_multiple for discussion of
9584 the pros/cons of ldm/stm usage for XScale. */
9585 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
9591 for (i
= 0; i
< count
; i
++)
9593 addr
= plus_constant (to
, i
* 4 * sign
);
9594 mem
= adjust_automodify_address (basemem
, SImode
, addr
, offset
);
9595 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
9601 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
9611 result
= gen_rtx_PARALLEL (VOIDmode
,
9612 rtvec_alloc (count
+ (write_back
? 1 : 0)));
9615 XVECEXP (result
, 0, 0)
9616 = gen_rtx_SET (VOIDmode
, to
,
9617 plus_constant (to
, count
* 4 * sign
));
9622 for (j
= 0; i
< count
; i
++, j
++)
9624 addr
= plus_constant (to
, j
* 4 * sign
);
9625 mem
= adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
9626 XVECEXP (result
, 0, i
)
9627 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
9638 arm_gen_movmemqi (rtx
*operands
)
9640 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
9641 HOST_WIDE_INT srcoffset
, dstoffset
;
9643 rtx src
, dst
, srcbase
, dstbase
;
9644 rtx part_bytes_reg
= NULL
;
9647 if (GET_CODE (operands
[2]) != CONST_INT
9648 || GET_CODE (operands
[3]) != CONST_INT
9649 || INTVAL (operands
[2]) > 64
9650 || INTVAL (operands
[3]) & 3)
9653 dstbase
= operands
[0];
9654 srcbase
= operands
[1];
9656 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
9657 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
9659 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
9660 out_words_to_go
= INTVAL (operands
[2]) / 4;
9661 last_bytes
= INTVAL (operands
[2]) & 3;
9662 dstoffset
= srcoffset
= 0;
9664 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
9665 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
9667 for (i
= 0; in_words_to_go
>= 2; i
+=4)
9669 if (in_words_to_go
> 4)
9670 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
9671 srcbase
, &srcoffset
));
9673 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
9674 FALSE
, srcbase
, &srcoffset
));
9676 if (out_words_to_go
)
9678 if (out_words_to_go
> 4)
9679 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
9680 dstbase
, &dstoffset
));
9681 else if (out_words_to_go
!= 1)
9682 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
9686 dstbase
, &dstoffset
));
9689 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
9690 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
9691 if (last_bytes
!= 0)
9693 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
9699 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
9700 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
9703 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
9704 if (out_words_to_go
)
9708 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
9709 sreg
= copy_to_reg (mem
);
9711 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
9712 emit_move_insn (mem
, sreg
);
9715 gcc_assert (!in_words_to_go
); /* Sanity check */
9720 gcc_assert (in_words_to_go
> 0);
9722 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
9723 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
9726 gcc_assert (!last_bytes
|| part_bytes_reg
);
9728 if (BYTES_BIG_ENDIAN
&& last_bytes
)
9730 rtx tmp
= gen_reg_rtx (SImode
);
9732 /* The bytes we want are in the top end of the word. */
9733 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
9734 GEN_INT (8 * (4 - last_bytes
))));
9735 part_bytes_reg
= tmp
;
9739 mem
= adjust_automodify_address (dstbase
, QImode
,
9740 plus_constant (dst
, last_bytes
- 1),
9741 dstoffset
+ last_bytes
- 1);
9742 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
9746 tmp
= gen_reg_rtx (SImode
);
9747 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
9748 part_bytes_reg
= tmp
;
9757 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
9758 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
9762 rtx tmp
= gen_reg_rtx (SImode
);
9763 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
9764 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
9765 part_bytes_reg
= tmp
;
9772 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
9773 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
9780 /* Select a dominance comparison mode if possible for a test of the general
9781 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
9782 COND_OR == DOM_CC_X_AND_Y => (X && Y)
9783 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
9784 COND_OR == DOM_CC_X_OR_Y => (X || Y)
9785 In all cases OP will be either EQ or NE, but we don't need to know which
9786 here. If we are unable to support a dominance comparison we return
9787 CC mode. This will then fail to match for the RTL expressions that
9788 generate this call. */
9790 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
9792 enum rtx_code cond1
, cond2
;
9795 /* Currently we will probably get the wrong result if the individual
9796 comparisons are not simple. This also ensures that it is safe to
9797 reverse a comparison if necessary. */
9798 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
9800 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
9804 /* The if_then_else variant of this tests the second condition if the
9805 first passes, but is true if the first fails. Reverse the first
9806 condition to get a true "inclusive-or" expression. */
9807 if (cond_or
== DOM_CC_NX_OR_Y
)
9808 cond1
= reverse_condition (cond1
);
9810 /* If the comparisons are not equal, and one doesn't dominate the other,
9811 then we can't do this. */
9813 && !comparison_dominates_p (cond1
, cond2
)
9814 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
9819 enum rtx_code temp
= cond1
;
9827 if (cond_or
== DOM_CC_X_AND_Y
)
9832 case EQ
: return CC_DEQmode
;
9833 case LE
: return CC_DLEmode
;
9834 case LEU
: return CC_DLEUmode
;
9835 case GE
: return CC_DGEmode
;
9836 case GEU
: return CC_DGEUmode
;
9837 default: gcc_unreachable ();
9841 if (cond_or
== DOM_CC_X_AND_Y
)
9857 if (cond_or
== DOM_CC_X_AND_Y
)
9873 if (cond_or
== DOM_CC_X_AND_Y
)
9889 if (cond_or
== DOM_CC_X_AND_Y
)
9904 /* The remaining cases only occur when both comparisons are the
9907 gcc_assert (cond1
== cond2
);
9911 gcc_assert (cond1
== cond2
);
9915 gcc_assert (cond1
== cond2
);
9919 gcc_assert (cond1
== cond2
);
9923 gcc_assert (cond1
== cond2
);
9932 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
9934 /* All floating point compares return CCFP if it is an equality
9935 comparison, and CCFPE otherwise. */
9936 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
9956 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
9965 /* A compare with a shifted operand. Because of canonicalization, the
9966 comparison will have to be swapped when we emit the assembler. */
9967 if (GET_MODE (y
) == SImode
9968 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
))
9969 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
9970 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
9971 || GET_CODE (x
) == ROTATERT
))
9974 /* This operation is performed swapped, but since we only rely on the Z
9975 flag we don't need an additional mode. */
9976 if (GET_MODE (y
) == SImode
9977 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
))
9978 && GET_CODE (x
) == NEG
9979 && (op
== EQ
|| op
== NE
))
9982 /* This is a special case that is used by combine to allow a
9983 comparison of a shifted byte load to be split into a zero-extend
9984 followed by a comparison of the shifted integer (only valid for
9985 equalities and unsigned inequalities). */
9986 if (GET_MODE (x
) == SImode
9987 && GET_CODE (x
) == ASHIFT
9988 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
9989 && GET_CODE (XEXP (x
, 0)) == SUBREG
9990 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
9991 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
9992 && (op
== EQ
|| op
== NE
9993 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
9994 && GET_CODE (y
) == CONST_INT
)
9997 /* A construct for a conditional compare, if the false arm contains
9998 0, then both conditions must be true, otherwise either condition
9999 must be true. Not all conditions are possible, so CCmode is
10000 returned if it can't be done. */
10001 if (GET_CODE (x
) == IF_THEN_ELSE
10002 && (XEXP (x
, 2) == const0_rtx
10003 || XEXP (x
, 2) == const1_rtx
)
10004 && COMPARISON_P (XEXP (x
, 0))
10005 && COMPARISON_P (XEXP (x
, 1)))
10006 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
10007 INTVAL (XEXP (x
, 2)));
10009 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
10010 if (GET_CODE (x
) == AND
10011 && COMPARISON_P (XEXP (x
, 0))
10012 && COMPARISON_P (XEXP (x
, 1)))
10013 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
10016 if (GET_CODE (x
) == IOR
10017 && COMPARISON_P (XEXP (x
, 0))
10018 && COMPARISON_P (XEXP (x
, 1)))
10019 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
10022 /* An operation (on Thumb) where we want to test for a single bit.
10023 This is done by shifting that bit up into the top bit of a
10024 scratch register; we can then branch on the sign bit. */
10026 && GET_MODE (x
) == SImode
10027 && (op
== EQ
|| op
== NE
)
10028 && GET_CODE (x
) == ZERO_EXTRACT
10029 && XEXP (x
, 1) == const1_rtx
)
10032 /* An operation that sets the condition codes as a side-effect, the
10033 V flag is not set correctly, so we can only use comparisons where
10034 this doesn't matter. (For LT and GE we can use "mi" and "pl"
10036 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
10037 if (GET_MODE (x
) == SImode
10039 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
10040 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
10041 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
10042 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
10043 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
10044 || GET_CODE (x
) == LSHIFTRT
10045 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
10046 || GET_CODE (x
) == ROTATERT
10047 || (TARGET_32BIT
&& GET_CODE (x
) == ZERO_EXTRACT
)))
10048 return CC_NOOVmode
;
10050 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
10053 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
10054 && GET_CODE (x
) == PLUS
10055 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
10061 /* X and Y are two things to compare using CODE. Emit the compare insn and
10062 return the rtx for register 0 in the proper mode. FP means this is a
10063 floating point compare: I don't think that it is needed on the arm. */
10065 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
10067 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
10068 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
10070 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
10075 /* Generate a sequence of insns that will generate the correct return
10076 address mask depending on the physical architecture that the program
10079 arm_gen_return_addr_mask (void)
10081 rtx reg
= gen_reg_rtx (Pmode
);
10083 emit_insn (gen_return_addr_mask (reg
));
10088 arm_reload_in_hi (rtx
*operands
)
10090 rtx ref
= operands
[1];
10092 HOST_WIDE_INT offset
= 0;
10094 if (GET_CODE (ref
) == SUBREG
)
10096 offset
= SUBREG_BYTE (ref
);
10097 ref
= SUBREG_REG (ref
);
10100 if (GET_CODE (ref
) == REG
)
10102 /* We have a pseudo which has been spilt onto the stack; there
10103 are two cases here: the first where there is a simple
10104 stack-slot replacement and a second where the stack-slot is
10105 out of range, or is used as a subreg. */
10106 if (reg_equiv_mem
[REGNO (ref
)])
10108 ref
= reg_equiv_mem
[REGNO (ref
)];
10109 base
= find_replacement (&XEXP (ref
, 0));
10112 /* The slot is out of range, or was dressed up in a SUBREG. */
10113 base
= reg_equiv_address
[REGNO (ref
)];
10116 base
= find_replacement (&XEXP (ref
, 0));
10118 /* Handle the case where the address is too complex to be offset by 1. */
10119 if (GET_CODE (base
) == MINUS
10120 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
10122 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10124 emit_set_insn (base_plus
, base
);
10127 else if (GET_CODE (base
) == PLUS
)
10129 /* The addend must be CONST_INT, or we would have dealt with it above. */
10130 HOST_WIDE_INT hi
, lo
;
10132 offset
+= INTVAL (XEXP (base
, 1));
10133 base
= XEXP (base
, 0);
10135 /* Rework the address into a legal sequence of insns. */
10136 /* Valid range for lo is -4095 -> 4095 */
10139 : -((-offset
) & 0xfff));
10141 /* Corner case, if lo is the max offset then we would be out of range
10142 once we have added the additional 1 below, so bump the msb into the
10143 pre-loading insn(s). */
10147 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
10148 ^ (HOST_WIDE_INT
) 0x80000000)
10149 - (HOST_WIDE_INT
) 0x80000000);
10151 gcc_assert (hi
+ lo
== offset
);
10155 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10157 /* Get the base address; addsi3 knows how to handle constants
10158 that require more than one insn. */
10159 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
10165 /* Operands[2] may overlap operands[0] (though it won't overlap
10166 operands[1]), that's why we asked for a DImode reg -- so we can
10167 use the bit that does not overlap. */
10168 if (REGNO (operands
[2]) == REGNO (operands
[0]))
10169 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10171 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
10173 emit_insn (gen_zero_extendqisi2 (scratch
,
10174 gen_rtx_MEM (QImode
,
10175 plus_constant (base
,
10177 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
10178 gen_rtx_MEM (QImode
,
10179 plus_constant (base
,
10181 if (!BYTES_BIG_ENDIAN
)
10182 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
10183 gen_rtx_IOR (SImode
,
10186 gen_rtx_SUBREG (SImode
, operands
[0], 0),
10190 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
10191 gen_rtx_IOR (SImode
,
10192 gen_rtx_ASHIFT (SImode
, scratch
,
10194 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
10197 /* Handle storing a half-word to memory during reload by synthesizing as two
10198 byte stores. Take care not to clobber the input values until after we
10199 have moved them somewhere safe. This code assumes that if the DImode
10200 scratch in operands[2] overlaps either the input value or output address
10201 in some way, then that value must die in this insn (we absolutely need
10202 two scratch registers for some corner cases). */
10204 arm_reload_out_hi (rtx
*operands
)
10206 rtx ref
= operands
[0];
10207 rtx outval
= operands
[1];
10209 HOST_WIDE_INT offset
= 0;
10211 if (GET_CODE (ref
) == SUBREG
)
10213 offset
= SUBREG_BYTE (ref
);
10214 ref
= SUBREG_REG (ref
);
10217 if (GET_CODE (ref
) == REG
)
10219 /* We have a pseudo which has been spilt onto the stack; there
10220 are two cases here: the first where there is a simple
10221 stack-slot replacement and a second where the stack-slot is
10222 out of range, or is used as a subreg. */
10223 if (reg_equiv_mem
[REGNO (ref
)])
10225 ref
= reg_equiv_mem
[REGNO (ref
)];
10226 base
= find_replacement (&XEXP (ref
, 0));
10229 /* The slot is out of range, or was dressed up in a SUBREG. */
10230 base
= reg_equiv_address
[REGNO (ref
)];
10233 base
= find_replacement (&XEXP (ref
, 0));
10235 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
10237 /* Handle the case where the address is too complex to be offset by 1. */
10238 if (GET_CODE (base
) == MINUS
10239 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
10241 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10243 /* Be careful not to destroy OUTVAL. */
10244 if (reg_overlap_mentioned_p (base_plus
, outval
))
10246 /* Updating base_plus might destroy outval, see if we can
10247 swap the scratch and base_plus. */
10248 if (!reg_overlap_mentioned_p (scratch
, outval
))
10251 scratch
= base_plus
;
10256 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
10258 /* Be conservative and copy OUTVAL into the scratch now,
10259 this should only be necessary if outval is a subreg
10260 of something larger than a word. */
10261 /* XXX Might this clobber base? I can't see how it can,
10262 since scratch is known to overlap with OUTVAL, and
10263 must be wider than a word. */
10264 emit_insn (gen_movhi (scratch_hi
, outval
));
10265 outval
= scratch_hi
;
10269 emit_set_insn (base_plus
, base
);
10272 else if (GET_CODE (base
) == PLUS
)
10274 /* The addend must be CONST_INT, or we would have dealt with it above. */
10275 HOST_WIDE_INT hi
, lo
;
10277 offset
+= INTVAL (XEXP (base
, 1));
10278 base
= XEXP (base
, 0);
10280 /* Rework the address into a legal sequence of insns. */
10281 /* Valid range for lo is -4095 -> 4095 */
10284 : -((-offset
) & 0xfff));
10286 /* Corner case, if lo is the max offset then we would be out of range
10287 once we have added the additional 1 below, so bump the msb into the
10288 pre-loading insn(s). */
10292 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
10293 ^ (HOST_WIDE_INT
) 0x80000000)
10294 - (HOST_WIDE_INT
) 0x80000000);
10296 gcc_assert (hi
+ lo
== offset
);
10300 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
10302 /* Be careful not to destroy OUTVAL. */
10303 if (reg_overlap_mentioned_p (base_plus
, outval
))
10305 /* Updating base_plus might destroy outval, see if we
10306 can swap the scratch and base_plus. */
10307 if (!reg_overlap_mentioned_p (scratch
, outval
))
10310 scratch
= base_plus
;
10315 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
10317 /* Be conservative and copy outval into scratch now,
10318 this should only be necessary if outval is a
10319 subreg of something larger than a word. */
10320 /* XXX Might this clobber base? I can't see how it
10321 can, since scratch is known to overlap with
10323 emit_insn (gen_movhi (scratch_hi
, outval
));
10324 outval
= scratch_hi
;
10328 /* Get the base address; addsi3 knows how to handle constants
10329 that require more than one insn. */
10330 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
10336 if (BYTES_BIG_ENDIAN
)
10338 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
10339 plus_constant (base
, offset
+ 1)),
10340 gen_lowpart (QImode
, outval
)));
10341 emit_insn (gen_lshrsi3 (scratch
,
10342 gen_rtx_SUBREG (SImode
, outval
, 0),
10344 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
10345 gen_lowpart (QImode
, scratch
)));
10349 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
10350 gen_lowpart (QImode
, outval
)));
10351 emit_insn (gen_lshrsi3 (scratch
,
10352 gen_rtx_SUBREG (SImode
, outval
, 0),
10354 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
10355 plus_constant (base
, offset
+ 1)),
10356 gen_lowpart (QImode
, scratch
)));
10360 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
10361 (padded to the size of a word) should be passed in a register. */
10364 arm_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
10366 if (TARGET_AAPCS_BASED
)
10367 return must_pass_in_stack_var_size (mode
, type
);
10369 return must_pass_in_stack_var_size_or_pad (mode
, type
);
10373 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
10374 Return true if an argument passed on the stack should be padded upwards,
10375 i.e. if the least-significant byte has useful data.
10376 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
10377 aggregate types are placed in the lowest memory address. */
10380 arm_pad_arg_upward (enum machine_mode mode
, const_tree type
)
10382 if (!TARGET_AAPCS_BASED
)
10383 return DEFAULT_FUNCTION_ARG_PADDING(mode
, type
) == upward
;
10385 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
10392 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
10393 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
10394 byte of the register has useful data, and return the opposite if the
10395 most significant byte does.
10396 For AAPCS, small aggregates and small complex types are always padded
10400 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED
,
10401 tree type
, int first ATTRIBUTE_UNUSED
)
10403 if (TARGET_AAPCS_BASED
10404 && BYTES_BIG_ENDIAN
10405 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == COMPLEX_TYPE
)
10406 && int_size_in_bytes (type
) <= 4)
10409 /* Otherwise, use default padding. */
10410 return !BYTES_BIG_ENDIAN
;
10414 /* Print a symbolic form of X to the debug file, F. */
10416 arm_print_value (FILE *f
, rtx x
)
10418 switch (GET_CODE (x
))
10421 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
10425 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
10433 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
10435 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
10436 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
10444 fprintf (f
, "\"%s\"", XSTR (x
, 0));
10448 fprintf (f
, "`%s'", XSTR (x
, 0));
10452 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
10456 arm_print_value (f
, XEXP (x
, 0));
10460 arm_print_value (f
, XEXP (x
, 0));
10462 arm_print_value (f
, XEXP (x
, 1));
10470 fprintf (f
, "????");
10475 /* Routines for manipulation of the constant pool. */
10477 /* Arm instructions cannot load a large constant directly into a
10478 register; they have to come from a pc relative load. The constant
10479 must therefore be placed in the addressable range of the pc
10480 relative load. Depending on the precise pc relative load
10481 instruction the range is somewhere between 256 bytes and 4k. This
10482 means that we often have to dump a constant inside a function, and
10483 generate code to branch around it.
10485 It is important to minimize this, since the branches will slow
10486 things down and make the code larger.
10488 Normally we can hide the table after an existing unconditional
10489 branch so that there is no interruption of the flow, but in the
10490 worst case the code looks like this:
10508 We fix this by performing a scan after scheduling, which notices
10509 which instructions need to have their operands fetched from the
10510 constant table and builds the table.
10512 The algorithm starts by building a table of all the constants that
10513 need fixing up and all the natural barriers in the function (places
10514 where a constant table can be dropped without breaking the flow).
10515 For each fixup we note how far the pc-relative replacement will be
10516 able to reach and the offset of the instruction into the function.
10518 Having built the table we then group the fixes together to form
10519 tables that are as large as possible (subject to addressing
10520 constraints) and emit each table of constants after the last
10521 barrier that is within range of all the instructions in the group.
10522 If a group does not contain a barrier, then we forcibly create one
10523 by inserting a jump instruction into the flow. Once the table has
10524 been inserted, the insns are then modified to reference the
10525 relevant entry in the pool.
10527 Possible enhancements to the algorithm (not implemented) are:
10529 1) For some processors and object formats, there may be benefit in
10530 aligning the pools to the start of cache lines; this alignment
10531 would need to be taken into account when calculating addressability
10534 /* These typedefs are located at the start of this file, so that
10535 they can be used in the prototypes there. This comment is to
10536 remind readers of that fact so that the following structures
10537 can be understood more easily.
10539 typedef struct minipool_node Mnode;
10540 typedef struct minipool_fixup Mfix; */
10542 struct minipool_node
10544 /* Doubly linked chain of entries. */
10547 /* The maximum offset into the code that this entry can be placed. While
10548 pushing fixes for forward references, all entries are sorted in order
10549 of increasing max_address. */
10550 HOST_WIDE_INT max_address
;
10551 /* Similarly for an entry inserted for a backwards ref. */
10552 HOST_WIDE_INT min_address
;
10553 /* The number of fixes referencing this entry. This can become zero
10554 if we "unpush" an entry. In this case we ignore the entry when we
10555 come to emit the code. */
10557 /* The offset from the start of the minipool. */
10558 HOST_WIDE_INT offset
;
10559 /* The value in table. */
10561 /* The mode of value. */
10562 enum machine_mode mode
;
10563 /* The size of the value. With iWMMXt enabled
10564 sizes > 4 also imply an alignment of 8-bytes. */
10568 struct minipool_fixup
10572 HOST_WIDE_INT address
;
10574 enum machine_mode mode
;
10578 HOST_WIDE_INT forwards
;
10579 HOST_WIDE_INT backwards
;
10582 /* Fixes less than a word need padding out to a word boundary. */
10583 #define MINIPOOL_FIX_SIZE(mode) \
10584 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
10586 static Mnode
* minipool_vector_head
;
10587 static Mnode
* minipool_vector_tail
;
10588 static rtx minipool_vector_label
;
10589 static int minipool_pad
;
10591 /* The linked list of all minipool fixes required for this function. */
10592 Mfix
* minipool_fix_head
;
10593 Mfix
* minipool_fix_tail
;
10594 /* The fix entry for the current minipool, once it has been placed. */
10595 Mfix
* minipool_barrier
;
10597 /* Determines if INSN is the start of a jump table. Returns the end
10598 of the TABLE or NULL_RTX. */
10600 is_jump_table (rtx insn
)
10604 if (GET_CODE (insn
) == JUMP_INSN
10605 && JUMP_LABEL (insn
) != NULL
10606 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
10607 == next_real_insn (insn
))
10609 && GET_CODE (table
) == JUMP_INSN
10610 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
10611 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
10617 #ifndef JUMP_TABLES_IN_TEXT_SECTION
10618 #define JUMP_TABLES_IN_TEXT_SECTION 0
10621 static HOST_WIDE_INT
10622 get_jump_table_size (rtx insn
)
10624 /* ADDR_VECs only take room if read-only data does into the text
10626 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
10628 rtx body
= PATTERN (insn
);
10629 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
10630 HOST_WIDE_INT size
;
10631 HOST_WIDE_INT modesize
;
10633 modesize
= GET_MODE_SIZE (GET_MODE (body
));
10634 size
= modesize
* XVECLEN (body
, elt
);
10638 /* Round up size of TBB table to a halfword boundary. */
10639 size
= (size
+ 1) & ~(HOST_WIDE_INT
)1;
10642 /* No padding necessary for TBH. */
10645 /* Add two bytes for alignment on Thumb. */
10650 gcc_unreachable ();
10658 /* Move a minipool fix MP from its current location to before MAX_MP.
10659 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
10660 constraints may need updating. */
10662 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
10663 HOST_WIDE_INT max_address
)
10665 /* The code below assumes these are different. */
10666 gcc_assert (mp
!= max_mp
);
10668 if (max_mp
== NULL
)
10670 if (max_address
< mp
->max_address
)
10671 mp
->max_address
= max_address
;
10675 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
10676 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
10678 mp
->max_address
= max_address
;
10680 /* Unlink MP from its current position. Since max_mp is non-null,
10681 mp->prev must be non-null. */
10682 mp
->prev
->next
= mp
->next
;
10683 if (mp
->next
!= NULL
)
10684 mp
->next
->prev
= mp
->prev
;
10686 minipool_vector_tail
= mp
->prev
;
10688 /* Re-insert it before MAX_MP. */
10690 mp
->prev
= max_mp
->prev
;
10693 if (mp
->prev
!= NULL
)
10694 mp
->prev
->next
= mp
;
10696 minipool_vector_head
= mp
;
10699 /* Save the new entry. */
10702 /* Scan over the preceding entries and adjust their addresses as
10704 while (mp
->prev
!= NULL
10705 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
10707 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
10714 /* Add a constant to the minipool for a forward reference. Returns the
10715 node added or NULL if the constant will not fit in this pool. */
10717 add_minipool_forward_ref (Mfix
*fix
)
10719 /* If set, max_mp is the first pool_entry that has a lower
10720 constraint than the one we are trying to add. */
10721 Mnode
* max_mp
= NULL
;
10722 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
- minipool_pad
;
10725 /* If the minipool starts before the end of FIX->INSN then this FIX
10726 can not be placed into the current pool. Furthermore, adding the
10727 new constant pool entry may cause the pool to start FIX_SIZE bytes
10729 if (minipool_vector_head
&&
10730 (fix
->address
+ get_attr_length (fix
->insn
)
10731 >= minipool_vector_head
->max_address
- fix
->fix_size
))
10734 /* Scan the pool to see if a constant with the same value has
10735 already been added. While we are doing this, also note the
10736 location where we must insert the constant if it doesn't already
10738 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
10740 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
10741 && fix
->mode
== mp
->mode
10742 && (GET_CODE (fix
->value
) != CODE_LABEL
10743 || (CODE_LABEL_NUMBER (fix
->value
)
10744 == CODE_LABEL_NUMBER (mp
->value
)))
10745 && rtx_equal_p (fix
->value
, mp
->value
))
10747 /* More than one fix references this entry. */
10749 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
10752 /* Note the insertion point if necessary. */
10754 && mp
->max_address
> max_address
)
10757 /* If we are inserting an 8-bytes aligned quantity and
10758 we have not already found an insertion point, then
10759 make sure that all such 8-byte aligned quantities are
10760 placed at the start of the pool. */
10761 if (ARM_DOUBLEWORD_ALIGN
10763 && fix
->fix_size
>= 8
10764 && mp
->fix_size
< 8)
10767 max_address
= mp
->max_address
;
10771 /* The value is not currently in the minipool, so we need to create
10772 a new entry for it. If MAX_MP is NULL, the entry will be put on
10773 the end of the list since the placement is less constrained than
10774 any existing entry. Otherwise, we insert the new fix before
10775 MAX_MP and, if necessary, adjust the constraints on the other
10778 mp
->fix_size
= fix
->fix_size
;
10779 mp
->mode
= fix
->mode
;
10780 mp
->value
= fix
->value
;
10782 /* Not yet required for a backwards ref. */
10783 mp
->min_address
= -65536;
10785 if (max_mp
== NULL
)
10787 mp
->max_address
= max_address
;
10789 mp
->prev
= minipool_vector_tail
;
10791 if (mp
->prev
== NULL
)
10793 minipool_vector_head
= mp
;
10794 minipool_vector_label
= gen_label_rtx ();
10797 mp
->prev
->next
= mp
;
10799 minipool_vector_tail
= mp
;
10803 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
10804 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
10806 mp
->max_address
= max_address
;
10809 mp
->prev
= max_mp
->prev
;
10811 if (mp
->prev
!= NULL
)
10812 mp
->prev
->next
= mp
;
10814 minipool_vector_head
= mp
;
10817 /* Save the new entry. */
10820 /* Scan over the preceding entries and adjust their addresses as
10822 while (mp
->prev
!= NULL
10823 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
10825 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
10833 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
10834 HOST_WIDE_INT min_address
)
10836 HOST_WIDE_INT offset
;
10838 /* The code below assumes these are different. */
10839 gcc_assert (mp
!= min_mp
);
10841 if (min_mp
== NULL
)
10843 if (min_address
> mp
->min_address
)
10844 mp
->min_address
= min_address
;
10848 /* We will adjust this below if it is too loose. */
10849 mp
->min_address
= min_address
;
10851 /* Unlink MP from its current position. Since min_mp is non-null,
10852 mp->next must be non-null. */
10853 mp
->next
->prev
= mp
->prev
;
10854 if (mp
->prev
!= NULL
)
10855 mp
->prev
->next
= mp
->next
;
10857 minipool_vector_head
= mp
->next
;
10859 /* Reinsert it after MIN_MP. */
10861 mp
->next
= min_mp
->next
;
10863 if (mp
->next
!= NULL
)
10864 mp
->next
->prev
= mp
;
10866 minipool_vector_tail
= mp
;
10872 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
10874 mp
->offset
= offset
;
10875 if (mp
->refcount
> 0)
10876 offset
+= mp
->fix_size
;
10878 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
10879 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
10885 /* Add a constant to the minipool for a backward reference. Returns the
10886 node added or NULL if the constant will not fit in this pool.
10888 Note that the code for insertion for a backwards reference can be
10889 somewhat confusing because the calculated offsets for each fix do
10890 not take into account the size of the pool (which is still under
10893 add_minipool_backward_ref (Mfix
*fix
)
10895 /* If set, min_mp is the last pool_entry that has a lower constraint
10896 than the one we are trying to add. */
10897 Mnode
*min_mp
= NULL
;
10898 /* This can be negative, since it is only a constraint. */
10899 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
10902 /* If we can't reach the current pool from this insn, or if we can't
10903 insert this entry at the end of the pool without pushing other
10904 fixes out of range, then we don't try. This ensures that we
10905 can't fail later on. */
10906 if (min_address
>= minipool_barrier
->address
10907 || (minipool_vector_tail
->min_address
+ fix
->fix_size
10908 >= minipool_barrier
->address
))
10911 /* Scan the pool to see if a constant with the same value has
10912 already been added. While we are doing this, also note the
10913 location where we must insert the constant if it doesn't already
10915 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
10917 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
10918 && fix
->mode
== mp
->mode
10919 && (GET_CODE (fix
->value
) != CODE_LABEL
10920 || (CODE_LABEL_NUMBER (fix
->value
)
10921 == CODE_LABEL_NUMBER (mp
->value
)))
10922 && rtx_equal_p (fix
->value
, mp
->value
)
10923 /* Check that there is enough slack to move this entry to the
10924 end of the table (this is conservative). */
10925 && (mp
->max_address
10926 > (minipool_barrier
->address
10927 + minipool_vector_tail
->offset
10928 + minipool_vector_tail
->fix_size
)))
10931 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
10934 if (min_mp
!= NULL
)
10935 mp
->min_address
+= fix
->fix_size
;
10938 /* Note the insertion point if necessary. */
10939 if (mp
->min_address
< min_address
)
10941 /* For now, we do not allow the insertion of 8-byte alignment
10942 requiring nodes anywhere but at the start of the pool. */
10943 if (ARM_DOUBLEWORD_ALIGN
10944 && fix
->fix_size
>= 8 && mp
->fix_size
< 8)
10949 else if (mp
->max_address
10950 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
10952 /* Inserting before this entry would push the fix beyond
10953 its maximum address (which can happen if we have
10954 re-located a forwards fix); force the new fix to come
10956 if (ARM_DOUBLEWORD_ALIGN
10957 && fix
->fix_size
>= 8 && mp
->fix_size
< 8)
10962 min_address
= mp
->min_address
+ fix
->fix_size
;
10965 /* Do not insert a non-8-byte aligned quantity before 8-byte
10966 aligned quantities. */
10967 else if (ARM_DOUBLEWORD_ALIGN
10968 && fix
->fix_size
< 8
10969 && mp
->fix_size
>= 8)
10972 min_address
= mp
->min_address
+ fix
->fix_size
;
10977 /* We need to create a new entry. */
10979 mp
->fix_size
= fix
->fix_size
;
10980 mp
->mode
= fix
->mode
;
10981 mp
->value
= fix
->value
;
10983 mp
->max_address
= minipool_barrier
->address
+ 65536;
10985 mp
->min_address
= min_address
;
10987 if (min_mp
== NULL
)
10990 mp
->next
= minipool_vector_head
;
10992 if (mp
->next
== NULL
)
10994 minipool_vector_tail
= mp
;
10995 minipool_vector_label
= gen_label_rtx ();
10998 mp
->next
->prev
= mp
;
11000 minipool_vector_head
= mp
;
11004 mp
->next
= min_mp
->next
;
11008 if (mp
->next
!= NULL
)
11009 mp
->next
->prev
= mp
;
11011 minipool_vector_tail
= mp
;
11014 /* Save the new entry. */
11022 /* Scan over the following entries and adjust their offsets. */
11023 while (mp
->next
!= NULL
)
11025 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
11026 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
11029 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
11031 mp
->next
->offset
= mp
->offset
;
11040 assign_minipool_offsets (Mfix
*barrier
)
11042 HOST_WIDE_INT offset
= 0;
11045 minipool_barrier
= barrier
;
11047 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
11049 mp
->offset
= offset
;
11051 if (mp
->refcount
> 0)
11052 offset
+= mp
->fix_size
;
11056 /* Output the literal table */
11058 dump_minipool (rtx scan
)
11064 if (ARM_DOUBLEWORD_ALIGN
)
11065 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
11066 if (mp
->refcount
> 0 && mp
->fix_size
>= 8)
11073 fprintf (dump_file
,
11074 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
11075 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
11077 scan
= emit_label_after (gen_label_rtx (), scan
);
11078 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
11079 scan
= emit_label_after (minipool_vector_label
, scan
);
11081 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
11083 if (mp
->refcount
> 0)
11087 fprintf (dump_file
,
11088 ";; Offset %u, min %ld, max %ld ",
11089 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
11090 (unsigned long) mp
->max_address
);
11091 arm_print_value (dump_file
, mp
->value
);
11092 fputc ('\n', dump_file
);
11095 switch (mp
->fix_size
)
11097 #ifdef HAVE_consttable_1
11099 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
11103 #ifdef HAVE_consttable_2
11105 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
11109 #ifdef HAVE_consttable_4
11111 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
11115 #ifdef HAVE_consttable_8
11117 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
11121 #ifdef HAVE_consttable_16
11123 scan
= emit_insn_after (gen_consttable_16 (mp
->value
), scan
);
11128 gcc_unreachable ();
11136 minipool_vector_head
= minipool_vector_tail
= NULL
;
11137 scan
= emit_insn_after (gen_consttable_end (), scan
);
11138 scan
= emit_barrier_after (scan
);
11141 /* Return the cost of forcibly inserting a barrier after INSN. */
11143 arm_barrier_cost (rtx insn
)
11145 /* Basing the location of the pool on the loop depth is preferable,
11146 but at the moment, the basic block information seems to be
11147 corrupt by this stage of the compilation. */
11148 int base_cost
= 50;
11149 rtx next
= next_nonnote_insn (insn
);
11151 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
11154 switch (GET_CODE (insn
))
11157 /* It will always be better to place the table before the label, rather
11166 return base_cost
- 10;
11169 return base_cost
+ 10;
11173 /* Find the best place in the insn stream in the range
11174 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
11175 Create the barrier by inserting a jump and add a new fix entry for
11178 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
11180 HOST_WIDE_INT count
= 0;
11182 rtx from
= fix
->insn
;
11183 /* The instruction after which we will insert the jump. */
11184 rtx selected
= NULL
;
11186 /* The address at which the jump instruction will be placed. */
11187 HOST_WIDE_INT selected_address
;
11189 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
11190 rtx label
= gen_label_rtx ();
11192 selected_cost
= arm_barrier_cost (from
);
11193 selected_address
= fix
->address
;
11195 while (from
&& count
< max_count
)
11200 /* This code shouldn't have been called if there was a natural barrier
11202 gcc_assert (GET_CODE (from
) != BARRIER
);
11204 /* Count the length of this insn. */
11205 count
+= get_attr_length (from
);
11207 /* If there is a jump table, add its length. */
11208 tmp
= is_jump_table (from
);
11211 count
+= get_jump_table_size (tmp
);
11213 /* Jump tables aren't in a basic block, so base the cost on
11214 the dispatch insn. If we select this location, we will
11215 still put the pool after the table. */
11216 new_cost
= arm_barrier_cost (from
);
11218 if (count
< max_count
11219 && (!selected
|| new_cost
<= selected_cost
))
11222 selected_cost
= new_cost
;
11223 selected_address
= fix
->address
+ count
;
11226 /* Continue after the dispatch table. */
11227 from
= NEXT_INSN (tmp
);
11231 new_cost
= arm_barrier_cost (from
);
11233 if (count
< max_count
11234 && (!selected
|| new_cost
<= selected_cost
))
11237 selected_cost
= new_cost
;
11238 selected_address
= fix
->address
+ count
;
11241 from
= NEXT_INSN (from
);
11244 /* Make sure that we found a place to insert the jump. */
11245 gcc_assert (selected
);
11247 /* Create a new JUMP_INSN that branches around a barrier. */
11248 from
= emit_jump_insn_after (gen_jump (label
), selected
);
11249 JUMP_LABEL (from
) = label
;
11250 barrier
= emit_barrier_after (from
);
11251 emit_label_after (label
, barrier
);
11253 /* Create a minipool barrier entry for the new barrier. */
11254 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
11255 new_fix
->insn
= barrier
;
11256 new_fix
->address
= selected_address
;
11257 new_fix
->next
= fix
->next
;
11258 fix
->next
= new_fix
;
11263 /* Record that there is a natural barrier in the insn stream at
11266 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
11268 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
11271 fix
->address
= address
;
11274 if (minipool_fix_head
!= NULL
)
11275 minipool_fix_tail
->next
= fix
;
11277 minipool_fix_head
= fix
;
11279 minipool_fix_tail
= fix
;
11282 /* Record INSN, which will need fixing up to load a value from the
11283 minipool. ADDRESS is the offset of the insn since the start of the
11284 function; LOC is a pointer to the part of the insn which requires
11285 fixing; VALUE is the constant that must be loaded, which is of type
11288 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
11289 enum machine_mode mode
, rtx value
)
11291 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
11294 fix
->address
= address
;
11297 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
11298 fix
->value
= value
;
11299 fix
->forwards
= get_attr_pool_range (insn
);
11300 fix
->backwards
= get_attr_neg_pool_range (insn
);
11301 fix
->minipool
= NULL
;
11303 /* If an insn doesn't have a range defined for it, then it isn't
11304 expecting to be reworked by this code. Better to stop now than
11305 to generate duff assembly code. */
11306 gcc_assert (fix
->forwards
|| fix
->backwards
);
11308 /* If an entry requires 8-byte alignment then assume all constant pools
11309 require 4 bytes of padding. Trying to do this later on a per-pool
11310 basis is awkward because existing pool entries have to be modified. */
11311 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
>= 8)
11316 fprintf (dump_file
,
11317 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
11318 GET_MODE_NAME (mode
),
11319 INSN_UID (insn
), (unsigned long) address
,
11320 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
11321 arm_print_value (dump_file
, fix
->value
);
11322 fprintf (dump_file
, "\n");
11325 /* Add it to the chain of fixes. */
11328 if (minipool_fix_head
!= NULL
)
11329 minipool_fix_tail
->next
= fix
;
11331 minipool_fix_head
= fix
;
11333 minipool_fix_tail
= fix
;
11336 /* Return the cost of synthesizing a 64-bit constant VAL inline.
11337 Returns the number of insns needed, or 99 if we don't know how to
11340 arm_const_double_inline_cost (rtx val
)
11342 rtx lowpart
, highpart
;
11343 enum machine_mode mode
;
11345 mode
= GET_MODE (val
);
11347 if (mode
== VOIDmode
)
11350 gcc_assert (GET_MODE_SIZE (mode
) == 8);
11352 lowpart
= gen_lowpart (SImode
, val
);
11353 highpart
= gen_highpart_mode (SImode
, mode
, val
);
11355 gcc_assert (GET_CODE (lowpart
) == CONST_INT
);
11356 gcc_assert (GET_CODE (highpart
) == CONST_INT
);
11358 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
11359 NULL_RTX
, NULL_RTX
, 0, 0)
11360 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
11361 NULL_RTX
, NULL_RTX
, 0, 0));
11364 /* Return true if it is worthwhile to split a 64-bit constant into two
11365 32-bit operations. This is the case if optimizing for size, or
11366 if we have load delay slots, or if one 32-bit part can be done with
11367 a single data operation. */
11369 arm_const_double_by_parts (rtx val
)
11371 enum machine_mode mode
= GET_MODE (val
);
11374 if (optimize_size
|| arm_ld_sched
)
11377 if (mode
== VOIDmode
)
11380 part
= gen_highpart_mode (SImode
, mode
, val
);
11382 gcc_assert (GET_CODE (part
) == CONST_INT
);
11384 if (const_ok_for_arm (INTVAL (part
))
11385 || const_ok_for_arm (~INTVAL (part
)))
11388 part
= gen_lowpart (SImode
, val
);
11390 gcc_assert (GET_CODE (part
) == CONST_INT
);
11392 if (const_ok_for_arm (INTVAL (part
))
11393 || const_ok_for_arm (~INTVAL (part
)))
11399 /* Scan INSN and note any of its operands that need fixing.
11400 If DO_PUSHES is false we do not actually push any of the fixups
11401 needed. The function returns TRUE if any fixups were needed/pushed.
11402 This is used by arm_memory_load_p() which needs to know about loads
11403 of constants that will be converted into minipool loads. */
11405 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
11407 bool result
= false;
11410 extract_insn (insn
);
11412 if (!constrain_operands (1))
11413 fatal_insn_not_found (insn
);
11415 if (recog_data
.n_alternatives
== 0)
11418 /* Fill in recog_op_alt with information about the constraints of
11420 preprocess_constraints ();
11422 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
11424 /* Things we need to fix can only occur in inputs. */
11425 if (recog_data
.operand_type
[opno
] != OP_IN
)
11428 /* If this alternative is a memory reference, then any mention
11429 of constants in this alternative is really to fool reload
11430 into allowing us to accept one there. We need to fix them up
11431 now so that we output the right code. */
11432 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
11434 rtx op
= recog_data
.operand
[opno
];
11436 if (CONSTANT_P (op
))
11439 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
11440 recog_data
.operand_mode
[opno
], op
);
11443 else if (GET_CODE (op
) == MEM
11444 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
11445 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
11449 rtx cop
= avoid_constant_pool_reference (op
);
11451 /* Casting the address of something to a mode narrower
11452 than a word can cause avoid_constant_pool_reference()
11453 to return the pool reference itself. That's no good to
11454 us here. Lets just hope that we can use the
11455 constant pool value directly. */
11457 cop
= get_pool_constant (XEXP (op
, 0));
11459 push_minipool_fix (insn
, address
,
11460 recog_data
.operand_loc
[opno
],
11461 recog_data
.operand_mode
[opno
], cop
);
11472 /* Gcc puts the pool in the wrong place for ARM, since we can only
11473 load addresses a limited distance around the pc. We do some
11474 special munging to move the constant pool values to the correct
11475 point in the code. */
11480 HOST_WIDE_INT address
= 0;
11483 minipool_fix_head
= minipool_fix_tail
= NULL
;
11485 /* The first insn must always be a note, or the code below won't
11486 scan it properly. */
11487 insn
= get_insns ();
11488 gcc_assert (GET_CODE (insn
) == NOTE
);
11491 /* Scan all the insns and record the operands that will need fixing. */
11492 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
11494 if (TARGET_CIRRUS_FIX_INVALID_INSNS
11495 && (arm_cirrus_insn_p (insn
)
11496 || GET_CODE (insn
) == JUMP_INSN
11497 || arm_memory_load_p (insn
)))
11498 cirrus_reorg (insn
);
11500 if (GET_CODE (insn
) == BARRIER
)
11501 push_minipool_barrier (insn
, address
);
11502 else if (INSN_P (insn
))
11506 note_invalid_constants (insn
, address
, true);
11507 address
+= get_attr_length (insn
);
11509 /* If the insn is a vector jump, add the size of the table
11510 and skip the table. */
11511 if ((table
= is_jump_table (insn
)) != NULL
)
11513 address
+= get_jump_table_size (table
);
11519 fix
= minipool_fix_head
;
11521 /* Now scan the fixups and perform the required changes. */
11526 Mfix
* last_added_fix
;
11527 Mfix
* last_barrier
= NULL
;
11530 /* Skip any further barriers before the next fix. */
11531 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
11534 /* No more fixes. */
11538 last_added_fix
= NULL
;
11540 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
11542 if (GET_CODE (ftmp
->insn
) == BARRIER
)
11544 if (ftmp
->address
>= minipool_vector_head
->max_address
)
11547 last_barrier
= ftmp
;
11549 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
11552 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
11555 /* If we found a barrier, drop back to that; any fixes that we
11556 could have reached but come after the barrier will now go in
11557 the next mini-pool. */
11558 if (last_barrier
!= NULL
)
11560 /* Reduce the refcount for those fixes that won't go into this
11562 for (fdel
= last_barrier
->next
;
11563 fdel
&& fdel
!= ftmp
;
11566 fdel
->minipool
->refcount
--;
11567 fdel
->minipool
= NULL
;
11570 ftmp
= last_barrier
;
11574 /* ftmp is first fix that we can't fit into this pool and
11575 there no natural barriers that we could use. Insert a
11576 new barrier in the code somewhere between the previous
11577 fix and this one, and arrange to jump around it. */
11578 HOST_WIDE_INT max_address
;
11580 /* The last item on the list of fixes must be a barrier, so
11581 we can never run off the end of the list of fixes without
11582 last_barrier being set. */
11585 max_address
= minipool_vector_head
->max_address
;
11586 /* Check that there isn't another fix that is in range that
11587 we couldn't fit into this pool because the pool was
11588 already too large: we need to put the pool before such an
11589 instruction. The pool itself may come just after the
11590 fix because create_fix_barrier also allows space for a
11591 jump instruction. */
11592 if (ftmp
->address
< max_address
)
11593 max_address
= ftmp
->address
+ 1;
11595 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
11598 assign_minipool_offsets (last_barrier
);
11602 if (GET_CODE (ftmp
->insn
) != BARRIER
11603 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
11610 /* Scan over the fixes we have identified for this pool, fixing them
11611 up and adding the constants to the pool itself. */
11612 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
11613 this_fix
= this_fix
->next
)
11614 if (GET_CODE (this_fix
->insn
) != BARRIER
)
11617 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
11618 minipool_vector_label
),
11619 this_fix
->minipool
->offset
);
11620 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
11623 dump_minipool (last_barrier
->insn
);
11627 /* From now on we must synthesize any constants that we can't handle
11628 directly. This can happen if the RTL gets split during final
11629 instruction generation. */
11630 after_arm_reorg
= 1;
11632 /* Free the minipool memory. */
11633 obstack_free (&minipool_obstack
, minipool_startobj
);
11636 /* Routines to output assembly language. */
11638 /* If the rtx is the correct value then return the string of the number.
11639 In this way we can ensure that valid double constants are generated even
11640 when cross compiling. */
11642 fp_immediate_constant (rtx x
)
11647 if (!fp_consts_inited
)
11650 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
11651 for (i
= 0; i
< 8; i
++)
11652 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
11653 return strings_fp
[i
];
11655 gcc_unreachable ();
11658 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
11659 static const char *
11660 fp_const_from_val (REAL_VALUE_TYPE
*r
)
11664 if (!fp_consts_inited
)
11667 for (i
= 0; i
< 8; i
++)
11668 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
11669 return strings_fp
[i
];
11671 gcc_unreachable ();
11674 /* Output the operands of a LDM/STM instruction to STREAM.
11675 MASK is the ARM register set mask of which only bits 0-15 are important.
11676 REG is the base register, either the frame pointer or the stack pointer,
11677 INSTR is the possibly suffixed load or store instruction.
11678 RFE is nonzero if the instruction should also copy spsr to cpsr. */
11681 print_multi_reg (FILE *stream
, const char *instr
, unsigned reg
,
11682 unsigned long mask
, int rfe
)
11685 bool not_first
= FALSE
;
11687 gcc_assert (!rfe
|| (mask
& (1 << PC_REGNUM
)));
11688 fputc ('\t', stream
);
11689 asm_fprintf (stream
, instr
, reg
);
11690 fputc ('{', stream
);
11692 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
11693 if (mask
& (1 << i
))
11696 fprintf (stream
, ", ");
11698 asm_fprintf (stream
, "%r", i
);
11703 fprintf (stream
, "}^\n");
11705 fprintf (stream
, "}\n");
11709 /* Output a FLDMD instruction to STREAM.
11710 BASE if the register containing the address.
11711 REG and COUNT specify the register range.
11712 Extra registers may be added to avoid hardware bugs.
11714 We output FLDMD even for ARMv5 VFP implementations. Although
11715 FLDMD is technically not supported until ARMv6, it is believed
11716 that all VFP implementations support its use in this context. */
11719 vfp_output_fldmd (FILE * stream
, unsigned int base
, int reg
, int count
)
11723 /* Workaround ARM10 VFPr1 bug. */
11724 if (count
== 2 && !arm_arch6
)
11731 /* FLDMD may not load more than 16 doubleword registers at a time. Split the
11732 load into multiple parts if we have to handle more than 16 registers. */
11735 vfp_output_fldmd (stream
, base
, reg
, 16);
11736 vfp_output_fldmd (stream
, base
, reg
+ 16, count
- 16);
11740 fputc ('\t', stream
);
11741 asm_fprintf (stream
, "fldmfdd\t%r!, {", base
);
11743 for (i
= reg
; i
< reg
+ count
; i
++)
11746 fputs (", ", stream
);
11747 asm_fprintf (stream
, "d%d", i
);
11749 fputs ("}\n", stream
);
11754 /* Output the assembly for a store multiple. */
11757 vfp_output_fstmd (rtx
* operands
)
11764 strcpy (pattern
, "fstmfdd\t%m0!, {%P1");
11765 p
= strlen (pattern
);
11767 gcc_assert (GET_CODE (operands
[1]) == REG
);
11769 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
11770 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
11772 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
11774 strcpy (&pattern
[p
], "}");
11776 output_asm_insn (pattern
, operands
);
11781 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
11782 number of bytes pushed. */
11785 vfp_emit_fstmd (int base_reg
, int count
)
11792 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
11793 register pairs are stored by a store multiple insn. We avoid this
11794 by pushing an extra pair. */
11795 if (count
== 2 && !arm_arch6
)
11797 if (base_reg
== LAST_VFP_REGNUM
- 3)
11802 /* FSTMD may not store more than 16 doubleword registers at once. Split
11803 larger stores into multiple parts (up to a maximum of two, in
11808 /* NOTE: base_reg is an internal register number, so each D register
11810 saved
= vfp_emit_fstmd (base_reg
+ 32, count
- 16);
11811 saved
+= vfp_emit_fstmd (base_reg
, 16);
11815 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
11816 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
11818 reg
= gen_rtx_REG (DFmode
, base_reg
);
11821 XVECEXP (par
, 0, 0)
11822 = gen_rtx_SET (VOIDmode
,
11825 gen_rtx_PRE_MODIFY (Pmode
,
11828 (stack_pointer_rtx
,
11831 gen_rtx_UNSPEC (BLKmode
,
11832 gen_rtvec (1, reg
),
11833 UNSPEC_PUSH_MULT
));
11835 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11836 plus_constant (stack_pointer_rtx
, -(count
* 8)));
11837 RTX_FRAME_RELATED_P (tmp
) = 1;
11838 XVECEXP (dwarf
, 0, 0) = tmp
;
11840 tmp
= gen_rtx_SET (VOIDmode
,
11841 gen_frame_mem (DFmode
, stack_pointer_rtx
),
11843 RTX_FRAME_RELATED_P (tmp
) = 1;
11844 XVECEXP (dwarf
, 0, 1) = tmp
;
11846 for (i
= 1; i
< count
; i
++)
11848 reg
= gen_rtx_REG (DFmode
, base_reg
);
11850 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
11852 tmp
= gen_rtx_SET (VOIDmode
,
11853 gen_frame_mem (DFmode
,
11854 plus_constant (stack_pointer_rtx
,
11857 RTX_FRAME_RELATED_P (tmp
) = 1;
11858 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
11861 par
= emit_insn (par
);
11862 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
11863 RTX_FRAME_RELATED_P (par
) = 1;
11868 /* Emit a call instruction with pattern PAT. ADDR is the address of
11869 the call target. */
11872 arm_emit_call_insn (rtx pat
, rtx addr
)
11876 insn
= emit_call_insn (pat
);
11878 /* The PIC register is live on entry to VxWorks PIC PLT entries.
11879 If the call might use such an entry, add a use of the PIC register
11880 to the instruction's CALL_INSN_FUNCTION_USAGE. */
11881 if (TARGET_VXWORKS_RTP
11883 && GET_CODE (addr
) == SYMBOL_REF
11884 && (SYMBOL_REF_DECL (addr
)
11885 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
11886 : !SYMBOL_REF_LOCAL_P (addr
)))
11888 require_pic_register ();
11889 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), cfun
->machine
->pic_reg
);
11893 /* Output a 'call' insn. */
11895 output_call (rtx
*operands
)
11897 gcc_assert (!arm_arch5
); /* Patterns should call blx <reg> directly. */
11899 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
11900 if (REGNO (operands
[0]) == LR_REGNUM
)
11902 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
11903 output_asm_insn ("mov%?\t%0, %|lr", operands
);
11906 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
11908 if (TARGET_INTERWORK
|| arm_arch4t
)
11909 output_asm_insn ("bx%?\t%0", operands
);
11911 output_asm_insn ("mov%?\t%|pc, %0", operands
);
11916 /* Output a 'call' insn that is a reference in memory. This is
11917 disabled for ARMv5 and we prefer a blx instead because otherwise
11918 there's a significant performance overhead. */
11920 output_call_mem (rtx
*operands
)
11922 gcc_assert (!arm_arch5
);
11923 if (TARGET_INTERWORK
)
11925 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
11926 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
11927 output_asm_insn ("bx%?\t%|ip", operands
);
11929 else if (regno_use_in (LR_REGNUM
, operands
[0]))
11931 /* LR is used in the memory address. We load the address in the
11932 first instruction. It's safe to use IP as the target of the
11933 load since the call will kill it anyway. */
11934 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
11935 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
11937 output_asm_insn ("bx%?\t%|ip", operands
);
11939 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
11943 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
11944 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
11951 /* Output a move from arm registers to an fpa registers.
11952 OPERANDS[0] is an fpa register.
11953 OPERANDS[1] is the first registers of an arm register pair. */
11955 output_mov_long_double_fpa_from_arm (rtx
*operands
)
11957 int arm_reg0
= REGNO (operands
[1]);
11960 gcc_assert (arm_reg0
!= IP_REGNUM
);
11962 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
11963 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
11964 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
11966 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops
);
11967 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
11972 /* Output a move from an fpa register to arm registers.
11973 OPERANDS[0] is the first registers of an arm register pair.
11974 OPERANDS[1] is an fpa register. */
11976 output_mov_long_double_arm_from_fpa (rtx
*operands
)
11978 int arm_reg0
= REGNO (operands
[0]);
11981 gcc_assert (arm_reg0
!= IP_REGNUM
);
11983 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
11984 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
11985 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
11987 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
11988 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops
);
11992 /* Output a move from arm registers to arm registers of a long double
11993 OPERANDS[0] is the destination.
11994 OPERANDS[1] is the source. */
11996 output_mov_long_double_arm_from_arm (rtx
*operands
)
11998 /* We have to be careful here because the two might overlap. */
11999 int dest_start
= REGNO (operands
[0]);
12000 int src_start
= REGNO (operands
[1]);
12004 if (dest_start
< src_start
)
12006 for (i
= 0; i
< 3; i
++)
12008 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
12009 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
12010 output_asm_insn ("mov%?\t%0, %1", ops
);
12015 for (i
= 2; i
>= 0; i
--)
12017 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
12018 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
12019 output_asm_insn ("mov%?\t%0, %1", ops
);
12027 arm_emit_movpair (rtx dest
, rtx src
)
12029 /* If the src is an immediate, simplify it. */
12030 if (CONST_INT_P (src
))
12032 HOST_WIDE_INT val
= INTVAL (src
);
12033 emit_set_insn (dest
, GEN_INT (val
& 0x0000ffff));
12034 if ((val
>> 16) & 0x0000ffff)
12035 emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode
, dest
, GEN_INT (16),
12037 GEN_INT ((val
>> 16) & 0x0000ffff));
12040 emit_set_insn (dest
, gen_rtx_HIGH (SImode
, src
));
12041 emit_set_insn (dest
, gen_rtx_LO_SUM (SImode
, dest
, src
));
12044 /* Output a move from arm registers to an fpa registers.
12045 OPERANDS[0] is an fpa register.
12046 OPERANDS[1] is the first registers of an arm register pair. */
12048 output_mov_double_fpa_from_arm (rtx
*operands
)
12050 int arm_reg0
= REGNO (operands
[1]);
12053 gcc_assert (arm_reg0
!= IP_REGNUM
);
12055 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
12056 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
12057 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops
);
12058 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
12062 /* Output a move from an fpa register to arm registers.
12063 OPERANDS[0] is the first registers of an arm register pair.
12064 OPERANDS[1] is an fpa register. */
12066 output_mov_double_arm_from_fpa (rtx
*operands
)
12068 int arm_reg0
= REGNO (operands
[0]);
12071 gcc_assert (arm_reg0
!= IP_REGNUM
);
12073 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
12074 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
12075 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
12076 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops
);
12080 /* Output a move between double words.
12081 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
12082 or MEM<-REG and all MEMs must be offsettable addresses. */
12084 output_move_double (rtx
*operands
)
12086 enum rtx_code code0
= GET_CODE (operands
[0]);
12087 enum rtx_code code1
= GET_CODE (operands
[1]);
12092 unsigned int reg0
= REGNO (operands
[0]);
12094 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
12096 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
12098 switch (GET_CODE (XEXP (operands
[1], 0)))
12102 && !(fix_cm3_ldrd
&& reg0
== REGNO(XEXP (operands
[1], 0))))
12103 output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands
);
12105 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands
);
12109 gcc_assert (TARGET_LDRD
);
12110 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands
);
12115 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands
);
12117 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands
);
12122 output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands
);
12124 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands
);
12128 gcc_assert (TARGET_LDRD
);
12129 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands
);
12134 /* Autoicrement addressing modes should never have overlapping
12135 base and destination registers, and overlapping index registers
12136 are already prohibited, so this doesn't need to worry about
12138 otherops
[0] = operands
[0];
12139 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
12140 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
12142 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
12144 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
12146 /* Registers overlap so split out the increment. */
12147 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
12148 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops
);
12152 /* Use a single insn if we can.
12153 FIXME: IWMMXT allows offsets larger than ldrd can
12154 handle, fix these up with a pair of ldr. */
12156 || GET_CODE (otherops
[2]) != CONST_INT
12157 || (INTVAL (otherops
[2]) > -256
12158 && INTVAL (otherops
[2]) < 256))
12159 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops
);
12162 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops
);
12163 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
12169 /* Use a single insn if we can.
12170 FIXME: IWMMXT allows offsets larger than ldrd can handle,
12171 fix these up with a pair of ldr. */
12173 || GET_CODE (otherops
[2]) != CONST_INT
12174 || (INTVAL (otherops
[2]) > -256
12175 && INTVAL (otherops
[2]) < 256))
12176 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops
);
12179 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
12180 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops
);
12187 /* We might be able to use ldrd %0, %1 here. However the range is
12188 different to ldr/adr, and it is broken on some ARMv7-M
12189 implementations. */
12190 /* Use the second register of the pair to avoid problematic
12192 otherops
[1] = operands
[1];
12193 output_asm_insn ("adr%?\t%0, %1", otherops
);
12194 operands
[1] = otherops
[0];
12196 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands
);
12198 output_asm_insn ("ldm%(ia%)\t%1, %M0", operands
);
12201 /* ??? This needs checking for thumb2. */
12203 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
12204 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
12206 otherops
[0] = operands
[0];
12207 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
12208 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
12210 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
12212 if (GET_CODE (otherops
[2]) == CONST_INT
&& !TARGET_LDRD
)
12214 switch ((int) INTVAL (otherops
[2]))
12217 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops
);
12222 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops
);
12227 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops
);
12231 otherops
[0] = gen_rtx_REG(SImode
, REGNO(operands
[0]) + 1);
12232 operands
[1] = otherops
[0];
12234 && (GET_CODE (otherops
[2]) == REG
12236 || (GET_CODE (otherops
[2]) == CONST_INT
12237 && INTVAL (otherops
[2]) > -256
12238 && INTVAL (otherops
[2]) < 256)))
12240 if (reg_overlap_mentioned_p (operands
[0],
12244 /* Swap base and index registers over to
12245 avoid a conflict. */
12247 otherops
[1] = otherops
[2];
12250 /* If both registers conflict, it will usually
12251 have been fixed by a splitter. */
12252 if (reg_overlap_mentioned_p (operands
[0], otherops
[2])
12253 || (fix_cm3_ldrd
&& reg0
== REGNO (otherops
[1])))
12255 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
12256 output_asm_insn ("ldr%(d%)\t%0, [%1]", operands
);
12260 otherops
[0] = operands
[0];
12261 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops
);
12266 if (GET_CODE (otherops
[2]) == CONST_INT
)
12268 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
12269 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
12271 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
12274 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
12277 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
12280 return "ldr%(d%)\t%0, [%1]";
12282 return "ldm%(ia%)\t%1, %M0";
12286 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
12287 /* Take care of overlapping base/data reg. */
12288 if (reg_mentioned_p (operands
[0], operands
[1]))
12290 output_asm_insn ("ldr%?\t%0, %1", otherops
);
12291 output_asm_insn ("ldr%?\t%0, %1", operands
);
12295 output_asm_insn ("ldr%?\t%0, %1", operands
);
12296 output_asm_insn ("ldr%?\t%0, %1", otherops
);
12303 /* Constraints should ensure this. */
12304 gcc_assert (code0
== MEM
&& code1
== REG
);
12305 gcc_assert (REGNO (operands
[1]) != IP_REGNUM
);
12307 switch (GET_CODE (XEXP (operands
[0], 0)))
12311 output_asm_insn ("str%(d%)\t%1, [%m0]", operands
);
12313 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands
);
12317 gcc_assert (TARGET_LDRD
);
12318 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands
);
12323 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands
);
12325 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands
);
12330 output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands
);
12332 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands
);
12336 gcc_assert (TARGET_LDRD
);
12337 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands
);
12342 otherops
[0] = operands
[1];
12343 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
12344 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
12346 /* IWMMXT allows offsets larger than ldrd can handle,
12347 fix these up with a pair of ldr. */
12349 && GET_CODE (otherops
[2]) == CONST_INT
12350 && (INTVAL(otherops
[2]) <= -256
12351 || INTVAL(otherops
[2]) >= 256))
12353 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
12355 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops
);
12356 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
12360 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
12361 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops
);
12364 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
12365 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops
);
12367 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops
);
12371 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
12372 if (GET_CODE (otherops
[2]) == CONST_INT
&& !TARGET_LDRD
)
12374 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
12377 output_asm_insn ("stm%(db%)\t%m0, %M1", operands
);
12383 output_asm_insn ("stm%(da%)\t%m0, %M1", operands
);
12389 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands
);
12394 && (GET_CODE (otherops
[2]) == REG
12396 || (GET_CODE (otherops
[2]) == CONST_INT
12397 && INTVAL (otherops
[2]) > -256
12398 && INTVAL (otherops
[2]) < 256)))
12400 otherops
[0] = operands
[1];
12401 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
12402 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops
);
12408 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
12409 otherops
[1] = operands
[1];
12410 output_asm_insn ("str%?\t%1, %0", operands
);
12411 output_asm_insn ("str%?\t%H1, %0", otherops
);
12418 /* Output a move, load or store for quad-word vectors in ARM registers. Only
12419 handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */
12422 output_move_quad (rtx
*operands
)
12424 if (REG_P (operands
[0]))
12426 /* Load, or reg->reg move. */
12428 if (MEM_P (operands
[1]))
12430 switch (GET_CODE (XEXP (operands
[1], 0)))
12433 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands
);
12438 output_asm_insn ("adr%?\t%0, %1", operands
);
12439 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands
);
12443 gcc_unreachable ();
12451 gcc_assert (REG_P (operands
[1]));
12453 dest
= REGNO (operands
[0]);
12454 src
= REGNO (operands
[1]);
12456 /* This seems pretty dumb, but hopefully GCC won't try to do it
12459 for (i
= 0; i
< 4; i
++)
12461 ops
[0] = gen_rtx_REG (SImode
, dest
+ i
);
12462 ops
[1] = gen_rtx_REG (SImode
, src
+ i
);
12463 output_asm_insn ("mov%?\t%0, %1", ops
);
12466 for (i
= 3; i
>= 0; i
--)
12468 ops
[0] = gen_rtx_REG (SImode
, dest
+ i
);
12469 ops
[1] = gen_rtx_REG (SImode
, src
+ i
);
12470 output_asm_insn ("mov%?\t%0, %1", ops
);
12476 gcc_assert (MEM_P (operands
[0]));
12477 gcc_assert (REG_P (operands
[1]));
12478 gcc_assert (!reg_overlap_mentioned_p (operands
[1], operands
[0]));
12480 switch (GET_CODE (XEXP (operands
[0], 0)))
12483 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands
);
12487 gcc_unreachable ();
12494 /* Output a VFP load or store instruction. */
12497 output_move_vfp (rtx
*operands
)
12499 rtx reg
, mem
, addr
, ops
[2];
12500 int load
= REG_P (operands
[0]);
12501 int dp
= GET_MODE_SIZE (GET_MODE (operands
[0])) == 8;
12502 int integer_p
= GET_MODE_CLASS (GET_MODE (operands
[0])) == MODE_INT
;
12505 enum machine_mode mode
;
12507 reg
= operands
[!load
];
12508 mem
= operands
[load
];
12510 mode
= GET_MODE (reg
);
12512 gcc_assert (REG_P (reg
));
12513 gcc_assert (IS_VFP_REGNUM (REGNO (reg
)));
12514 gcc_assert (mode
== SFmode
12518 || (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
)));
12519 gcc_assert (MEM_P (mem
));
12521 addr
= XEXP (mem
, 0);
12523 switch (GET_CODE (addr
))
12526 templ
= "f%smdb%c%%?\t%%0!, {%%%s1}%s";
12527 ops
[0] = XEXP (addr
, 0);
12532 templ
= "f%smia%c%%?\t%%0!, {%%%s1}%s";
12533 ops
[0] = XEXP (addr
, 0);
12538 templ
= "f%s%c%%?\t%%%s0, %%1%s";
12544 sprintf (buff
, templ
,
12545 load
? "ld" : "st",
12548 integer_p
? "\t%@ int" : "");
12549 output_asm_insn (buff
, ops
);
12554 /* Output a Neon quad-word load or store, or a load or store for
12555 larger structure modes.
12557 WARNING: The ordering of elements is weird in big-endian mode,
12558 because we use VSTM, as required by the EABI. GCC RTL defines
12559 element ordering based on in-memory order. This can be differ
12560 from the architectural ordering of elements within a NEON register.
12561 The intrinsics defined in arm_neon.h use the NEON register element
12562 ordering, not the GCC RTL element ordering.
12564 For example, the in-memory ordering of a big-endian a quadword
12565 vector with 16-bit elements when stored from register pair {d0,d1}
12566 will be (lowest address first, d0[N] is NEON register element N):
12568 [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]]
12570 When necessary, quadword registers (dN, dN+1) are moved to ARM
12571 registers from rN in the order:
12573 dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
12575 So that STM/LDM can be used on vectors in ARM registers, and the
12576 same memory layout will result as if VSTM/VLDM were used. */
12579 output_move_neon (rtx
*operands
)
12581 rtx reg
, mem
, addr
, ops
[2];
12582 int regno
, load
= REG_P (operands
[0]);
12585 enum machine_mode mode
;
12587 reg
= operands
[!load
];
12588 mem
= operands
[load
];
12590 mode
= GET_MODE (reg
);
12592 gcc_assert (REG_P (reg
));
12593 regno
= REGNO (reg
);
12594 gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno
)
12595 || NEON_REGNO_OK_FOR_QUAD (regno
));
12596 gcc_assert (VALID_NEON_DREG_MODE (mode
)
12597 || VALID_NEON_QREG_MODE (mode
)
12598 || VALID_NEON_STRUCT_MODE (mode
));
12599 gcc_assert (MEM_P (mem
));
12601 addr
= XEXP (mem
, 0);
12603 /* Strip off const from addresses like (const (plus (...))). */
12604 if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
)
12605 addr
= XEXP (addr
, 0);
12607 switch (GET_CODE (addr
))
12610 templ
= "v%smia%%?\t%%0!, %%h1";
12611 ops
[0] = XEXP (addr
, 0);
12616 /* FIXME: We should be using vld1/vst1 here in BE mode? */
12617 templ
= "v%smdb%%?\t%%0!, %%h1";
12618 ops
[0] = XEXP (addr
, 0);
12623 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
12624 gcc_unreachable ();
12629 int nregs
= HARD_REGNO_NREGS (REGNO (reg
), mode
) / 2;
12632 for (i
= 0; i
< nregs
; i
++)
12634 /* We're only using DImode here because it's a convenient size. */
12635 ops
[0] = gen_rtx_REG (DImode
, REGNO (reg
) + 2 * i
);
12636 ops
[1] = adjust_address (mem
, DImode
, 8 * i
);
12637 if (reg_overlap_mentioned_p (ops
[0], mem
))
12639 gcc_assert (overlap
== -1);
12644 sprintf (buff
, "v%sr%%?\t%%P0, %%1", load
? "ld" : "st");
12645 output_asm_insn (buff
, ops
);
12650 ops
[0] = gen_rtx_REG (DImode
, REGNO (reg
) + 2 * overlap
);
12651 ops
[1] = adjust_address (mem
, SImode
, 8 * overlap
);
12652 sprintf (buff
, "v%sr%%?\t%%P0, %%1", load
? "ld" : "st");
12653 output_asm_insn (buff
, ops
);
12660 templ
= "v%smia%%?\t%%m0, %%h1";
12665 sprintf (buff
, templ
, load
? "ld" : "st");
12666 output_asm_insn (buff
, ops
);
12671 /* Output an ADD r, s, #n where n may be too big for one instruction.
12672 If adding zero to one register, output nothing. */
12674 output_add_immediate (rtx
*operands
)
12676 HOST_WIDE_INT n
= INTVAL (operands
[2]);
12678 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
12681 output_multi_immediate (operands
,
12682 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
12685 output_multi_immediate (operands
,
12686 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
12693 /* Output a multiple immediate operation.
12694 OPERANDS is the vector of operands referred to in the output patterns.
12695 INSTR1 is the output pattern to use for the first constant.
12696 INSTR2 is the output pattern to use for subsequent constants.
12697 IMMED_OP is the index of the constant slot in OPERANDS.
12698 N is the constant value. */
12699 static const char *
12700 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
12701 int immed_op
, HOST_WIDE_INT n
)
12703 #if HOST_BITS_PER_WIDE_INT > 32
12709 /* Quick and easy output. */
12710 operands
[immed_op
] = const0_rtx
;
12711 output_asm_insn (instr1
, operands
);
12716 const char * instr
= instr1
;
12718 /* Note that n is never zero here (which would give no output). */
12719 for (i
= 0; i
< 32; i
+= 2)
12723 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
12724 output_asm_insn (instr
, operands
);
12734 /* Return the name of a shifter operation. */
12735 static const char *
12736 arm_shift_nmem(enum rtx_code code
)
12741 return ARM_LSL_NAME
;
12757 /* Return the appropriate ARM instruction for the operation code.
12758 The returned result should not be overwritten. OP is the rtx of the
12759 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
12762 arithmetic_instr (rtx op
, int shift_first_arg
)
12764 switch (GET_CODE (op
))
12770 return shift_first_arg
? "rsb" : "sub";
12785 return arm_shift_nmem(GET_CODE(op
));
12788 gcc_unreachable ();
12792 /* Ensure valid constant shifts and return the appropriate shift mnemonic
12793 for the operation code. The returned result should not be overwritten.
12794 OP is the rtx code of the shift.
12795 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
12797 static const char *
12798 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
12801 enum rtx_code code
= GET_CODE (op
);
12803 switch (GET_CODE (XEXP (op
, 1)))
12811 *amountp
= INTVAL (XEXP (op
, 1));
12815 gcc_unreachable ();
12821 gcc_assert (*amountp
!= -1);
12822 *amountp
= 32 - *amountp
;
12825 /* Fall through. */
12831 mnem
= arm_shift_nmem(code
);
12835 /* We never have to worry about the amount being other than a
12836 power of 2, since this case can never be reloaded from a reg. */
12837 gcc_assert (*amountp
!= -1);
12838 *amountp
= int_log2 (*amountp
);
12839 return ARM_LSL_NAME
;
12842 gcc_unreachable ();
12845 if (*amountp
!= -1)
12847 /* This is not 100% correct, but follows from the desire to merge
12848 multiplication by a power of 2 with the recognizer for a
12849 shift. >=32 is not a valid shift for "lsl", so we must try and
12850 output a shift that produces the correct arithmetical result.
12851 Using lsr #32 is identical except for the fact that the carry bit
12852 is not set correctly if we set the flags; but we never use the
12853 carry bit from such an operation, so we can ignore that. */
12854 if (code
== ROTATERT
)
12855 /* Rotate is just modulo 32. */
12857 else if (*amountp
!= (*amountp
& 31))
12859 if (code
== ASHIFT
)
12864 /* Shifts of 0 are no-ops. */
12872 /* Obtain the shift from the POWER of two. */
12874 static HOST_WIDE_INT
12875 int_log2 (HOST_WIDE_INT power
)
12877 HOST_WIDE_INT shift
= 0;
12879 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
12881 gcc_assert (shift
<= 31);
12888 /* Output a .ascii pseudo-op, keeping track of lengths. This is
12889 because /bin/as is horribly restrictive. The judgement about
12890 whether or not each character is 'printable' (and can be output as
12891 is) or not (and must be printed with an octal escape) must be made
12892 with reference to the *host* character set -- the situation is
12893 similar to that discussed in the comments above pp_c_char in
12894 c-pretty-print.c. */
12896 #define MAX_ASCII_LEN 51
12899 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
12902 int len_so_far
= 0;
12904 fputs ("\t.ascii\t\"", stream
);
12906 for (i
= 0; i
< len
; i
++)
12910 if (len_so_far
>= MAX_ASCII_LEN
)
12912 fputs ("\"\n\t.ascii\t\"", stream
);
12918 if (c
== '\\' || c
== '\"')
12920 putc ('\\', stream
);
12928 fprintf (stream
, "\\%03o", c
);
12933 fputs ("\"\n", stream
);
12936 /* Compute the register save mask for registers 0 through 12
12937 inclusive. This code is used by arm_compute_save_reg_mask. */
12939 static unsigned long
12940 arm_compute_save_reg0_reg12_mask (void)
12942 unsigned long func_type
= arm_current_func_type ();
12943 unsigned long save_reg_mask
= 0;
12946 if (IS_INTERRUPT (func_type
))
12948 unsigned int max_reg
;
12949 /* Interrupt functions must not corrupt any registers,
12950 even call clobbered ones. If this is a leaf function
12951 we can just examine the registers used by the RTL, but
12952 otherwise we have to assume that whatever function is
12953 called might clobber anything, and so we have to save
12954 all the call-clobbered registers as well. */
12955 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
12956 /* FIQ handlers have registers r8 - r12 banked, so
12957 we only need to check r0 - r7, Normal ISRs only
12958 bank r14 and r15, so we must check up to r12.
12959 r13 is the stack pointer which is always preserved,
12960 so we do not need to consider it here. */
12965 for (reg
= 0; reg
<= max_reg
; reg
++)
12966 if (df_regs_ever_live_p (reg
)
12967 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
12968 save_reg_mask
|= (1 << reg
);
12970 /* Also save the pic base register if necessary. */
12972 && !TARGET_SINGLE_PIC_BASE
12973 && arm_pic_register
!= INVALID_REGNUM
12974 && crtl
->uses_pic_offset_table
)
12975 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
12977 else if (IS_VOLATILE(func_type
))
12979 /* For noreturn functions we historically omitted register saves
12980 altogether. However this really messes up debugging. As a
12981 compromise save just the frame pointers. Combined with the link
12982 register saved elsewhere this should be sufficient to get
12984 if (frame_pointer_needed
)
12985 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
12986 if (df_regs_ever_live_p (ARM_HARD_FRAME_POINTER_REGNUM
))
12987 save_reg_mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
12988 if (df_regs_ever_live_p (THUMB_HARD_FRAME_POINTER_REGNUM
))
12989 save_reg_mask
|= 1 << THUMB_HARD_FRAME_POINTER_REGNUM
;
12993 /* In the normal case we only need to save those registers
12994 which are call saved and which are used by this function. */
12995 for (reg
= 0; reg
<= 11; reg
++)
12996 if (df_regs_ever_live_p (reg
) && ! call_used_regs
[reg
])
12997 save_reg_mask
|= (1 << reg
);
12999 /* Handle the frame pointer as a special case. */
13000 if (frame_pointer_needed
)
13001 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
13003 /* If we aren't loading the PIC register,
13004 don't stack it even though it may be live. */
13006 && !TARGET_SINGLE_PIC_BASE
13007 && arm_pic_register
!= INVALID_REGNUM
13008 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
)
13009 || crtl
->uses_pic_offset_table
))
13010 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
13012 /* The prologue will copy SP into R0, so save it. */
13013 if (IS_STACKALIGN (func_type
))
13014 save_reg_mask
|= 1;
13017 /* Save registers so the exception handler can modify them. */
13018 if (crtl
->calls_eh_return
)
13024 reg
= EH_RETURN_DATA_REGNO (i
);
13025 if (reg
== INVALID_REGNUM
)
13027 save_reg_mask
|= 1 << reg
;
13031 return save_reg_mask
;
13035 /* Compute the number of bytes used to store the static chain register on the
13036 stack, above the stack frame. We need to know this accurately to get the
13037 alignment of the rest of the stack frame correct. */
13039 static int arm_compute_static_chain_stack_bytes (void)
13041 unsigned long func_type
= arm_current_func_type ();
13042 int static_chain_stack_bytes
= 0;
13044 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
&&
13045 IS_NESTED (func_type
) &&
13046 df_regs_ever_live_p (3) && crtl
->args
.pretend_args_size
== 0)
13047 static_chain_stack_bytes
= 4;
13049 return static_chain_stack_bytes
;
13053 /* Compute a bit mask of which registers need to be
13054 saved on the stack for the current function.
13055 This is used by arm_get_frame_offsets, which may add extra registers. */
13057 static unsigned long
13058 arm_compute_save_reg_mask (void)
13060 unsigned int save_reg_mask
= 0;
13061 unsigned long func_type
= arm_current_func_type ();
13064 if (IS_NAKED (func_type
))
13065 /* This should never really happen. */
13068 /* If we are creating a stack frame, then we must save the frame pointer,
13069 IP (which will hold the old stack pointer), LR and the PC. */
13070 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
13072 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
13075 | (1 << PC_REGNUM
);
13077 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
13079 /* Decide if we need to save the link register.
13080 Interrupt routines have their own banked link register,
13081 so they never need to save it.
13082 Otherwise if we do not use the link register we do not need to save
13083 it. If we are pushing other registers onto the stack however, we
13084 can save an instruction in the epilogue by pushing the link register
13085 now and then popping it back into the PC. This incurs extra memory
13086 accesses though, so we only do it when optimizing for size, and only
13087 if we know that we will not need a fancy return sequence. */
13088 if (df_regs_ever_live_p (LR_REGNUM
)
13091 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
13092 && !crtl
->calls_eh_return
))
13093 save_reg_mask
|= 1 << LR_REGNUM
;
13095 if (cfun
->machine
->lr_save_eliminated
)
13096 save_reg_mask
&= ~ (1 << LR_REGNUM
);
13098 if (TARGET_REALLY_IWMMXT
13099 && ((bit_count (save_reg_mask
)
13100 + ARM_NUM_INTS (crtl
->args
.pretend_args_size
+
13101 arm_compute_static_chain_stack_bytes())
13104 /* The total number of registers that are going to be pushed
13105 onto the stack is odd. We need to ensure that the stack
13106 is 64-bit aligned before we start to save iWMMXt registers,
13107 and also before we start to create locals. (A local variable
13108 might be a double or long long which we will load/store using
13109 an iWMMXt instruction). Therefore we need to push another
13110 ARM register, so that the stack will be 64-bit aligned. We
13111 try to avoid using the arg registers (r0 -r3) as they might be
13112 used to pass values in a tail call. */
13113 for (reg
= 4; reg
<= 12; reg
++)
13114 if ((save_reg_mask
& (1 << reg
)) == 0)
13118 save_reg_mask
|= (1 << reg
);
13121 cfun
->machine
->sibcall_blocked
= 1;
13122 save_reg_mask
|= (1 << 3);
13126 /* We may need to push an additional register for use initializing the
13127 PIC base register. */
13128 if (TARGET_THUMB2
&& IS_NESTED (func_type
) && flag_pic
13129 && (save_reg_mask
& THUMB2_WORK_REGS
) == 0)
13131 reg
= thumb_find_work_register (1 << 4);
13132 if (!call_used_regs
[reg
])
13133 save_reg_mask
|= (1 << reg
);
13136 return save_reg_mask
;
13140 /* Compute a bit mask of which registers need to be
13141 saved on the stack for the current function. */
13142 static unsigned long
13143 thumb1_compute_save_reg_mask (void)
13145 unsigned long mask
;
13149 for (reg
= 0; reg
< 12; reg
++)
13150 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
13154 && !TARGET_SINGLE_PIC_BASE
13155 && arm_pic_register
!= INVALID_REGNUM
13156 && crtl
->uses_pic_offset_table
)
13157 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
13159 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
13160 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
13161 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
13163 /* LR will also be pushed if any lo regs are pushed. */
13164 if (mask
& 0xff || thumb_force_lr_save ())
13165 mask
|= (1 << LR_REGNUM
);
13167 /* Make sure we have a low work register if we need one.
13168 We will need one if we are going to push a high register,
13169 but we are not currently intending to push a low register. */
13170 if ((mask
& 0xff) == 0
13171 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
13173 /* Use thumb_find_work_register to choose which register
13174 we will use. If the register is live then we will
13175 have to push it. Use LAST_LO_REGNUM as our fallback
13176 choice for the register to select. */
13177 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
13178 /* Make sure the register returned by thumb_find_work_register is
13179 not part of the return value. */
13180 if (reg
* UNITS_PER_WORD
<= (unsigned) arm_size_return_regs ())
13181 reg
= LAST_LO_REGNUM
;
13183 if (! call_used_regs
[reg
])
13187 /* The 504 below is 8 bytes less than 512 because there are two possible
13188 alignment words. We can't tell here if they will be present or not so we
13189 have to play it safe and assume that they are. */
13190 if ((CALLER_INTERWORKING_SLOT_SIZE
+
13191 ROUND_UP_WORD (get_frame_size ()) +
13192 crtl
->outgoing_args_size
) >= 504)
13194 /* This is the same as the code in thumb1_expand_prologue() which
13195 determines which register to use for stack decrement. */
13196 for (reg
= LAST_ARG_REGNUM
+ 1; reg
<= LAST_LO_REGNUM
; reg
++)
13197 if (mask
& (1 << reg
))
13200 if (reg
> LAST_LO_REGNUM
)
13202 /* Make sure we have a register available for stack decrement. */
13203 mask
|= 1 << LAST_LO_REGNUM
;
13211 /* Return the number of bytes required to save VFP registers. */
13213 arm_get_vfp_saved_size (void)
13215 unsigned int regno
;
13220 /* Space for saved VFP registers. */
13221 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
13224 for (regno
= FIRST_VFP_REGNUM
;
13225 regno
< LAST_VFP_REGNUM
;
13228 if ((!df_regs_ever_live_p (regno
) || call_used_regs
[regno
])
13229 && (!df_regs_ever_live_p (regno
+ 1) || call_used_regs
[regno
+ 1]))
13233 /* Workaround ARM10 VFPr1 bug. */
13234 if (count
== 2 && !arm_arch6
)
13236 saved
+= count
* 8;
13245 if (count
== 2 && !arm_arch6
)
13247 saved
+= count
* 8;
13254 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
13255 everything bar the final return instruction. */
13257 output_return_instruction (rtx operand
, int really_return
, int reverse
)
13259 char conditional
[10];
13262 unsigned long live_regs_mask
;
13263 unsigned long func_type
;
13264 arm_stack_offsets
*offsets
;
13266 func_type
= arm_current_func_type ();
13268 if (IS_NAKED (func_type
))
13271 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
13273 /* If this function was declared non-returning, and we have
13274 found a tail call, then we have to trust that the called
13275 function won't return. */
13280 /* Otherwise, trap an attempted return by aborting. */
13282 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
13284 assemble_external_libcall (ops
[1]);
13285 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
13291 gcc_assert (!cfun
->calls_alloca
|| really_return
);
13293 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
13295 cfun
->machine
->return_used_this_function
= 1;
13297 offsets
= arm_get_frame_offsets ();
13298 live_regs_mask
= offsets
->saved_regs_mask
;
13300 if (live_regs_mask
)
13302 const char * return_reg
;
13304 /* If we do not have any special requirements for function exit
13305 (e.g. interworking) then we can load the return address
13306 directly into the PC. Otherwise we must load it into LR. */
13308 && (IS_INTERRUPT (func_type
) || !TARGET_INTERWORK
))
13309 return_reg
= reg_names
[PC_REGNUM
];
13311 return_reg
= reg_names
[LR_REGNUM
];
13313 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
13315 /* There are three possible reasons for the IP register
13316 being saved. 1) a stack frame was created, in which case
13317 IP contains the old stack pointer, or 2) an ISR routine
13318 corrupted it, or 3) it was saved to align the stack on
13319 iWMMXt. In case 1, restore IP into SP, otherwise just
13321 if (frame_pointer_needed
)
13323 live_regs_mask
&= ~ (1 << IP_REGNUM
);
13324 live_regs_mask
|= (1 << SP_REGNUM
);
13327 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
13330 /* On some ARM architectures it is faster to use LDR rather than
13331 LDM to load a single register. On other architectures, the
13332 cost is the same. In 26 bit mode, or for exception handlers,
13333 we have to use LDM to load the PC so that the CPSR is also
13335 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
13336 if (live_regs_mask
== (1U << reg
))
13339 if (reg
<= LAST_ARM_REGNUM
13340 && (reg
!= LR_REGNUM
13342 || ! IS_INTERRUPT (func_type
)))
13344 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
13345 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
13352 /* Generate the load multiple instruction to restore the
13353 registers. Note we can get here, even if
13354 frame_pointer_needed is true, but only if sp already
13355 points to the base of the saved core registers. */
13356 if (live_regs_mask
& (1 << SP_REGNUM
))
13358 unsigned HOST_WIDE_INT stack_adjust
;
13360 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
13361 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
13363 if (stack_adjust
&& arm_arch5
&& TARGET_ARM
)
13364 if (TARGET_UNIFIED_ASM
)
13365 sprintf (instr
, "ldmib%s\t%%|sp, {", conditional
);
13367 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
13370 /* If we can't use ldmib (SA110 bug),
13371 then try to pop r3 instead. */
13373 live_regs_mask
|= 1 << 3;
13375 if (TARGET_UNIFIED_ASM
)
13376 sprintf (instr
, "ldmfd%s\t%%|sp, {", conditional
);
13378 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
13382 if (TARGET_UNIFIED_ASM
)
13383 sprintf (instr
, "pop%s\t{", conditional
);
13385 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
13387 p
= instr
+ strlen (instr
);
13389 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
13390 if (live_regs_mask
& (1 << reg
))
13392 int l
= strlen (reg_names
[reg
]);
13398 memcpy (p
, ", ", 2);
13402 memcpy (p
, "%|", 2);
13403 memcpy (p
+ 2, reg_names
[reg
], l
);
13407 if (live_regs_mask
& (1 << LR_REGNUM
))
13409 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
13410 /* If returning from an interrupt, restore the CPSR. */
13411 if (IS_INTERRUPT (func_type
))
13418 output_asm_insn (instr
, & operand
);
13420 /* See if we need to generate an extra instruction to
13421 perform the actual function return. */
13423 && func_type
!= ARM_FT_INTERWORKED
13424 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
13426 /* The return has already been handled
13427 by loading the LR into the PC. */
13434 switch ((int) ARM_FUNC_TYPE (func_type
))
13438 /* ??? This is wrong for unified assembly syntax. */
13439 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
13442 case ARM_FT_INTERWORKED
:
13443 sprintf (instr
, "bx%s\t%%|lr", conditional
);
13446 case ARM_FT_EXCEPTION
:
13447 /* ??? This is wrong for unified assembly syntax. */
13448 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
13452 /* Use bx if it's available. */
13453 if (arm_arch5
|| arm_arch4t
)
13454 sprintf (instr
, "bx%s\t%%|lr", conditional
);
13456 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
13460 output_asm_insn (instr
, & operand
);
13466 /* Write the function name into the code section, directly preceding
13467 the function prologue.
13469 Code will be output similar to this:
13471 .ascii "arm_poke_function_name", 0
13474 .word 0xff000000 + (t1 - t0)
13475 arm_poke_function_name
13477 stmfd sp!, {fp, ip, lr, pc}
13480 When performing a stack backtrace, code can inspect the value
13481 of 'pc' stored at 'fp' + 0. If the trace function then looks
13482 at location pc - 12 and the top 8 bits are set, then we know
13483 that there is a function name embedded immediately preceding this
13484 location and has length ((pc[-3]) & 0xff000000).
13486 We assume that pc is declared as a pointer to an unsigned long.
13488 It is of no benefit to output the function name if we are assembling
13489 a leaf function. These function types will not contain a stack
13490 backtrace structure, therefore it is not possible to determine the
13493 arm_poke_function_name (FILE *stream
, const char *name
)
13495 unsigned long alignlength
;
13496 unsigned long length
;
13499 length
= strlen (name
) + 1;
13500 alignlength
= ROUND_UP_WORD (length
);
13502 ASM_OUTPUT_ASCII (stream
, name
, length
);
13503 ASM_OUTPUT_ALIGN (stream
, 2);
13504 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
13505 assemble_aligned_integer (UNITS_PER_WORD
, x
);
13508 /* Place some comments into the assembler stream
13509 describing the current function. */
13511 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
13513 unsigned long func_type
;
13517 thumb1_output_function_prologue (f
, frame_size
);
13521 /* Sanity check. */
13522 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
13524 func_type
= arm_current_func_type ();
13526 switch ((int) ARM_FUNC_TYPE (func_type
))
13529 case ARM_FT_NORMAL
:
13531 case ARM_FT_INTERWORKED
:
13532 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
13535 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
13538 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
13540 case ARM_FT_EXCEPTION
:
13541 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
13545 if (IS_NAKED (func_type
))
13546 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
13548 if (IS_VOLATILE (func_type
))
13549 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
13551 if (IS_NESTED (func_type
))
13552 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
13553 if (IS_STACKALIGN (func_type
))
13554 asm_fprintf (f
, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
13556 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
13558 crtl
->args
.pretend_args_size
, frame_size
);
13560 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
13561 frame_pointer_needed
,
13562 cfun
->machine
->uses_anonymous_args
);
13564 if (cfun
->machine
->lr_save_eliminated
)
13565 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
13567 if (crtl
->calls_eh_return
)
13568 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
13573 arm_output_epilogue (rtx sibling
)
13576 unsigned long saved_regs_mask
;
13577 unsigned long func_type
;
13578 /* Floats_offset is the offset from the "virtual" frame. In an APCS
13579 frame that is $fp + 4 for a non-variadic function. */
13580 int floats_offset
= 0;
13582 FILE * f
= asm_out_file
;
13583 unsigned int lrm_count
= 0;
13584 int really_return
= (sibling
== NULL
);
13586 arm_stack_offsets
*offsets
;
13588 /* If we have already generated the return instruction
13589 then it is futile to generate anything else. */
13590 if (use_return_insn (FALSE
, sibling
) &&
13591 (cfun
->machine
->return_used_this_function
!= 0))
13594 func_type
= arm_current_func_type ();
13596 if (IS_NAKED (func_type
))
13597 /* Naked functions don't have epilogues. */
13600 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
13604 /* A volatile function should never return. Call abort. */
13605 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
13606 assemble_external_libcall (op
);
13607 output_asm_insn ("bl\t%a0", &op
);
13612 /* If we are throwing an exception, then we really must be doing a
13613 return, so we can't tail-call. */
13614 gcc_assert (!crtl
->calls_eh_return
|| really_return
);
13616 offsets
= arm_get_frame_offsets ();
13617 saved_regs_mask
= offsets
->saved_regs_mask
;
13620 lrm_count
= bit_count (saved_regs_mask
);
13622 floats_offset
= offsets
->saved_args
;
13623 /* Compute how far away the floats will be. */
13624 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
13625 if (saved_regs_mask
& (1 << reg
))
13626 floats_offset
+= 4;
13628 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
13630 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
13631 int vfp_offset
= offsets
->frame
;
13633 if (TARGET_FPA_EMU2
)
13635 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
13636 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
13638 floats_offset
+= 12;
13639 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
13640 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
13645 start_reg
= LAST_FPA_REGNUM
;
13647 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
13649 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
13651 floats_offset
+= 12;
13653 /* We can't unstack more than four registers at once. */
13654 if (start_reg
- reg
== 3)
13656 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
13657 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
13658 start_reg
= reg
- 1;
13663 if (reg
!= start_reg
)
13664 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
13665 reg
+ 1, start_reg
- reg
,
13666 FP_REGNUM
, floats_offset
- vfp_offset
);
13667 start_reg
= reg
- 1;
13671 /* Just in case the last register checked also needs unstacking. */
13672 if (reg
!= start_reg
)
13673 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
13674 reg
+ 1, start_reg
- reg
,
13675 FP_REGNUM
, floats_offset
- vfp_offset
);
13678 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
13682 /* The fldmd insns do not have base+offset addressing
13683 modes, so we use IP to hold the address. */
13684 saved_size
= arm_get_vfp_saved_size ();
13686 if (saved_size
> 0)
13688 floats_offset
+= saved_size
;
13689 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
13690 FP_REGNUM
, floats_offset
- vfp_offset
);
13692 start_reg
= FIRST_VFP_REGNUM
;
13693 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
13695 if ((!df_regs_ever_live_p (reg
) || call_used_regs
[reg
])
13696 && (!df_regs_ever_live_p (reg
+ 1) || call_used_regs
[reg
+ 1]))
13698 if (start_reg
!= reg
)
13699 vfp_output_fldmd (f
, IP_REGNUM
,
13700 (start_reg
- FIRST_VFP_REGNUM
) / 2,
13701 (reg
- start_reg
) / 2);
13702 start_reg
= reg
+ 2;
13705 if (start_reg
!= reg
)
13706 vfp_output_fldmd (f
, IP_REGNUM
,
13707 (start_reg
- FIRST_VFP_REGNUM
) / 2,
13708 (reg
- start_reg
) / 2);
13713 /* The frame pointer is guaranteed to be non-double-word aligned.
13714 This is because it is set to (old_stack_pointer - 4) and the
13715 old_stack_pointer was double word aligned. Thus the offset to
13716 the iWMMXt registers to be loaded must also be non-double-word
13717 sized, so that the resultant address *is* double-word aligned.
13718 We can ignore floats_offset since that was already included in
13719 the live_regs_mask. */
13720 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
13722 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
13723 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
13725 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
13726 reg
, FP_REGNUM
, lrm_count
* 4);
13731 /* saved_regs_mask should contain the IP, which at the time of stack
13732 frame generation actually contains the old stack pointer. So a
13733 quick way to unwind the stack is just pop the IP register directly
13734 into the stack pointer. */
13735 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
13736 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
13737 saved_regs_mask
|= (1 << SP_REGNUM
);
13739 /* There are two registers left in saved_regs_mask - LR and PC. We
13740 only need to restore the LR register (the return address), but to
13741 save time we can load it directly into the PC, unless we need a
13742 special function exit sequence, or we are not really returning. */
13744 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
13745 && !crtl
->calls_eh_return
)
13746 /* Delete the LR from the register mask, so that the LR on
13747 the stack is loaded into the PC in the register mask. */
13748 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
13750 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
13752 /* We must use SP as the base register, because SP is one of the
13753 registers being restored. If an interrupt or page fault
13754 happens in the ldm instruction, the SP might or might not
13755 have been restored. That would be bad, as then SP will no
13756 longer indicate the safe area of stack, and we can get stack
13757 corruption. Using SP as the base register means that it will
13758 be reset correctly to the original value, should an interrupt
13759 occur. If the stack pointer already points at the right
13760 place, then omit the subtraction. */
13761 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
13762 || cfun
->calls_alloca
)
13763 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
13764 4 * bit_count (saved_regs_mask
));
13765 print_multi_reg (f
, "ldmfd\t%r, ", SP_REGNUM
, saved_regs_mask
, 0);
13767 if (IS_INTERRUPT (func_type
))
13768 /* Interrupt handlers will have pushed the
13769 IP onto the stack, so restore it now. */
13770 print_multi_reg (f
, "ldmfd\t%r!, ", SP_REGNUM
, 1 << IP_REGNUM
, 0);
13774 /* This branch is executed for ARM mode (non-apcs frames) and
13775 Thumb-2 mode. Frame layout is essentially the same for those
13776 cases, except that in ARM mode frame pointer points to the
13777 first saved register, while in Thumb-2 mode the frame pointer points
13778 to the last saved register.
13780 It is possible to make frame pointer point to last saved
13781 register in both cases, and remove some conditionals below.
13782 That means that fp setup in prologue would be just "mov fp, sp"
13783 and sp restore in epilogue would be just "mov sp, fp", whereas
13784 now we have to use add/sub in those cases. However, the value
13785 of that would be marginal, as both mov and add/sub are 32-bit
13786 in ARM mode, and it would require extra conditionals
13787 in arm_expand_prologue to distingish ARM-apcs-frame case
13788 (where frame pointer is required to point at first register)
13789 and ARM-non-apcs-frame. Therefore, such change is postponed
13790 until real need arise. */
13791 unsigned HOST_WIDE_INT amount
;
13793 /* Restore stack pointer if necessary. */
13794 if (TARGET_ARM
&& frame_pointer_needed
)
13796 operands
[0] = stack_pointer_rtx
;
13797 operands
[1] = hard_frame_pointer_rtx
;
13799 operands
[2] = GEN_INT (offsets
->frame
- offsets
->saved_regs
);
13800 output_add_immediate (operands
);
13804 if (frame_pointer_needed
)
13806 /* For Thumb-2 restore sp from the frame pointer.
13807 Operand restrictions mean we have to incrememnt FP, then copy
13809 amount
= offsets
->locals_base
- offsets
->saved_regs
;
13810 operands
[0] = hard_frame_pointer_rtx
;
13814 unsigned long count
;
13815 operands
[0] = stack_pointer_rtx
;
13816 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13817 /* pop call clobbered registers if it avoids a
13818 separate stack adjustment. */
13819 count
= offsets
->saved_regs
- offsets
->saved_args
;
13822 && !crtl
->calls_eh_return
13823 && bit_count(saved_regs_mask
) * 4 == count
13824 && !IS_INTERRUPT (func_type
)
13825 && !crtl
->tail_call_emit
)
13827 unsigned long mask
;
13828 mask
= (1 << (arm_size_return_regs() / 4)) - 1;
13830 mask
&= ~saved_regs_mask
;
13832 while (bit_count (mask
) * 4 > amount
)
13834 while ((mask
& (1 << reg
)) == 0)
13836 mask
&= ~(1 << reg
);
13838 if (bit_count (mask
) * 4 == amount
) {
13840 saved_regs_mask
|= mask
;
13847 operands
[1] = operands
[0];
13848 operands
[2] = GEN_INT (amount
);
13849 output_add_immediate (operands
);
13851 if (frame_pointer_needed
)
13852 asm_fprintf (f
, "\tmov\t%r, %r\n",
13853 SP_REGNUM
, HARD_FRAME_POINTER_REGNUM
);
13856 if (TARGET_FPA_EMU2
)
13858 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
13859 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
13860 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
13865 start_reg
= FIRST_FPA_REGNUM
;
13867 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
13869 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
13871 if (reg
- start_reg
== 3)
13873 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
13874 start_reg
, SP_REGNUM
);
13875 start_reg
= reg
+ 1;
13880 if (reg
!= start_reg
)
13881 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
13882 start_reg
, reg
- start_reg
,
13885 start_reg
= reg
+ 1;
13889 /* Just in case the last register checked also needs unstacking. */
13890 if (reg
!= start_reg
)
13891 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
13892 start_reg
, reg
- start_reg
, SP_REGNUM
);
13895 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
13897 int end_reg
= LAST_VFP_REGNUM
+ 1;
13899 /* Scan the registers in reverse order. We need to match
13900 any groupings made in the prologue and generate matching
13902 for (reg
= LAST_VFP_REGNUM
- 1; reg
>= FIRST_VFP_REGNUM
; reg
-= 2)
13904 if ((!df_regs_ever_live_p (reg
) || call_used_regs
[reg
])
13905 && (!df_regs_ever_live_p (reg
+ 1)
13906 || call_used_regs
[reg
+ 1]))
13908 if (end_reg
> reg
+ 2)
13909 vfp_output_fldmd (f
, SP_REGNUM
,
13910 (reg
+ 2 - FIRST_VFP_REGNUM
) / 2,
13911 (end_reg
- (reg
+ 2)) / 2);
13915 if (end_reg
> reg
+ 2)
13916 vfp_output_fldmd (f
, SP_REGNUM
, 0,
13917 (end_reg
- (reg
+ 2)) / 2);
13921 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
13922 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
13923 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
13925 /* If we can, restore the LR into the PC. */
13926 if (ARM_FUNC_TYPE (func_type
) != ARM_FT_INTERWORKED
13927 && (TARGET_ARM
|| ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
13928 && !IS_STACKALIGN (func_type
)
13930 && crtl
->args
.pretend_args_size
== 0
13931 && saved_regs_mask
& (1 << LR_REGNUM
)
13932 && !crtl
->calls_eh_return
)
13934 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
13935 saved_regs_mask
|= (1 << PC_REGNUM
);
13936 rfe
= IS_INTERRUPT (func_type
);
13941 /* Load the registers off the stack. If we only have one register
13942 to load use the LDR instruction - it is faster. For Thumb-2
13943 always use pop and the assembler will pick the best instruction.*/
13944 if (TARGET_ARM
&& saved_regs_mask
== (1 << LR_REGNUM
)
13945 && !IS_INTERRUPT(func_type
))
13947 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
13949 else if (saved_regs_mask
)
13951 if (saved_regs_mask
& (1 << SP_REGNUM
))
13952 /* Note - write back to the stack register is not enabled
13953 (i.e. "ldmfd sp!..."). We know that the stack pointer is
13954 in the list of registers and if we add writeback the
13955 instruction becomes UNPREDICTABLE. */
13956 print_multi_reg (f
, "ldmfd\t%r, ", SP_REGNUM
, saved_regs_mask
,
13958 else if (TARGET_ARM
)
13959 print_multi_reg (f
, "ldmfd\t%r!, ", SP_REGNUM
, saved_regs_mask
,
13962 print_multi_reg (f
, "pop\t", SP_REGNUM
, saved_regs_mask
, 0);
13965 if (crtl
->args
.pretend_args_size
)
13967 /* Unwind the pre-pushed regs. */
13968 operands
[0] = operands
[1] = stack_pointer_rtx
;
13969 operands
[2] = GEN_INT (crtl
->args
.pretend_args_size
);
13970 output_add_immediate (operands
);
13974 /* We may have already restored PC directly from the stack. */
13975 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
13978 /* Stack adjustment for exception handler. */
13979 if (crtl
->calls_eh_return
)
13980 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
13981 ARM_EH_STACKADJ_REGNUM
);
13983 /* Generate the return instruction. */
13984 switch ((int) ARM_FUNC_TYPE (func_type
))
13988 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
13991 case ARM_FT_EXCEPTION
:
13992 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
13995 case ARM_FT_INTERWORKED
:
13996 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
14000 if (IS_STACKALIGN (func_type
))
14002 /* See comment in arm_expand_prologue. */
14003 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, 0);
14005 if (arm_arch5
|| arm_arch4t
)
14006 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
14008 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
14016 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
14017 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
14019 arm_stack_offsets
*offsets
;
14025 /* Emit any call-via-reg trampolines that are needed for v4t support
14026 of call_reg and call_value_reg type insns. */
14027 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
14029 rtx label
= cfun
->machine
->call_via
[regno
];
14033 switch_to_section (function_section (current_function_decl
));
14034 targetm
.asm_out
.internal_label (asm_out_file
, "L",
14035 CODE_LABEL_NUMBER (label
));
14036 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
14040 /* ??? Probably not safe to set this here, since it assumes that a
14041 function will be emitted as assembly immediately after we generate
14042 RTL for it. This does not happen for inline functions. */
14043 cfun
->machine
->return_used_this_function
= 0;
14045 else /* TARGET_32BIT */
14047 /* We need to take into account any stack-frame rounding. */
14048 offsets
= arm_get_frame_offsets ();
14050 gcc_assert (!use_return_insn (FALSE
, NULL
)
14051 || (cfun
->machine
->return_used_this_function
!= 0)
14052 || offsets
->saved_regs
== offsets
->outgoing_args
14053 || frame_pointer_needed
);
14055 /* Reset the ARM-specific per-function variables. */
14056 after_arm_reorg
= 0;
14060 /* Generate and emit an insn that we will recognize as a push_multi.
14061 Unfortunately, since this insn does not reflect very well the actual
14062 semantics of the operation, we need to annotate the insn for the benefit
14063 of DWARF2 frame unwind information. */
14065 emit_multi_reg_push (unsigned long mask
)
14068 int num_dwarf_regs
;
14072 int dwarf_par_index
;
14075 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
14076 if (mask
& (1 << i
))
14079 gcc_assert (num_regs
&& num_regs
<= 16);
14081 /* We don't record the PC in the dwarf frame information. */
14082 num_dwarf_regs
= num_regs
;
14083 if (mask
& (1 << PC_REGNUM
))
14086 /* For the body of the insn we are going to generate an UNSPEC in
14087 parallel with several USEs. This allows the insn to be recognized
14088 by the push_multi pattern in the arm.md file.
14090 The body of the insn looks something like this:
14093 (set (mem:BLK (pre_modify:SI (reg:SI sp)
14094 (const_int:SI <num>)))
14095 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
14101 For the frame note however, we try to be more explicit and actually
14102 show each register being stored into the stack frame, plus a (single)
14103 decrement of the stack pointer. We do it this way in order to be
14104 friendly to the stack unwinding code, which only wants to see a single
14105 stack decrement per instruction. The RTL we generate for the note looks
14106 something like this:
14109 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
14110 (set (mem:SI (reg:SI sp)) (reg:SI r4))
14111 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI XX))
14112 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI YY))
14116 FIXME:: In an ideal world the PRE_MODIFY would not exist and
14117 instead we'd have a parallel expression detailing all
14118 the stores to the various memory addresses so that debug
14119 information is more up-to-date. Remember however while writing
14120 this to take care of the constraints with the push instruction.
14122 Note also that this has to be taken care of for the VFP registers.
14124 For more see PR43399. */
14126 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
14127 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
14128 dwarf_par_index
= 1;
14130 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
14132 if (mask
& (1 << i
))
14134 reg
= gen_rtx_REG (SImode
, i
);
14136 XVECEXP (par
, 0, 0)
14137 = gen_rtx_SET (VOIDmode
,
14140 gen_rtx_PRE_MODIFY (Pmode
,
14143 (stack_pointer_rtx
,
14146 gen_rtx_UNSPEC (BLKmode
,
14147 gen_rtvec (1, reg
),
14148 UNSPEC_PUSH_MULT
));
14150 if (i
!= PC_REGNUM
)
14152 tmp
= gen_rtx_SET (VOIDmode
,
14153 gen_frame_mem (SImode
, stack_pointer_rtx
),
14155 RTX_FRAME_RELATED_P (tmp
) = 1;
14156 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
14164 for (j
= 1, i
++; j
< num_regs
; i
++)
14166 if (mask
& (1 << i
))
14168 reg
= gen_rtx_REG (SImode
, i
);
14170 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
14172 if (i
!= PC_REGNUM
)
14175 = gen_rtx_SET (VOIDmode
,
14178 plus_constant (stack_pointer_rtx
,
14181 RTX_FRAME_RELATED_P (tmp
) = 1;
14182 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
14189 par
= emit_insn (par
);
14191 tmp
= gen_rtx_SET (VOIDmode
,
14193 plus_constant (stack_pointer_rtx
, -4 * num_regs
));
14194 RTX_FRAME_RELATED_P (tmp
) = 1;
14195 XVECEXP (dwarf
, 0, 0) = tmp
;
14197 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
14202 /* Calculate the size of the return value that is passed in registers. */
14204 arm_size_return_regs (void)
14206 enum machine_mode mode
;
14208 if (crtl
->return_rtx
!= 0)
14209 mode
= GET_MODE (crtl
->return_rtx
);
14211 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
14213 return GET_MODE_SIZE (mode
);
14217 emit_sfm (int base_reg
, int count
)
14224 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
14225 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
14227 reg
= gen_rtx_REG (XFmode
, base_reg
++);
14229 XVECEXP (par
, 0, 0)
14230 = gen_rtx_SET (VOIDmode
,
14233 gen_rtx_PRE_MODIFY (Pmode
,
14236 (stack_pointer_rtx
,
14239 gen_rtx_UNSPEC (BLKmode
,
14240 gen_rtvec (1, reg
),
14241 UNSPEC_PUSH_MULT
));
14242 tmp
= gen_rtx_SET (VOIDmode
,
14243 gen_frame_mem (XFmode
, stack_pointer_rtx
), reg
);
14244 RTX_FRAME_RELATED_P (tmp
) = 1;
14245 XVECEXP (dwarf
, 0, 1) = tmp
;
14247 for (i
= 1; i
< count
; i
++)
14249 reg
= gen_rtx_REG (XFmode
, base_reg
++);
14250 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
14252 tmp
= gen_rtx_SET (VOIDmode
,
14253 gen_frame_mem (XFmode
,
14254 plus_constant (stack_pointer_rtx
,
14257 RTX_FRAME_RELATED_P (tmp
) = 1;
14258 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
14261 tmp
= gen_rtx_SET (VOIDmode
,
14263 plus_constant (stack_pointer_rtx
, -12 * count
));
14265 RTX_FRAME_RELATED_P (tmp
) = 1;
14266 XVECEXP (dwarf
, 0, 0) = tmp
;
14268 par
= emit_insn (par
);
14269 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
14275 /* Return true if the current function needs to save/restore LR. */
14278 thumb_force_lr_save (void)
14280 return !cfun
->machine
->lr_save_eliminated
14281 && (!leaf_function_p ()
14282 || thumb_far_jump_used_p ()
14283 || df_regs_ever_live_p (LR_REGNUM
));
14287 /* Compute the distance from register FROM to register TO.
14288 These can be the arg pointer (26), the soft frame pointer (25),
14289 the stack pointer (13) or the hard frame pointer (11).
14290 In thumb mode r7 is used as the soft frame pointer, if needed.
14291 Typical stack layout looks like this:
14293 old stack pointer -> | |
14296 | | saved arguments for
14297 | | vararg functions
14300 hard FP & arg pointer -> | | \
14308 soft frame pointer -> | | /
14313 locals base pointer -> | | /
14318 current stack pointer -> | | /
14321 For a given function some or all of these stack components
14322 may not be needed, giving rise to the possibility of
14323 eliminating some of the registers.
14325 The values returned by this function must reflect the behavior
14326 of arm_expand_prologue() and arm_compute_save_reg_mask().
14328 The sign of the number returned reflects the direction of stack
14329 growth, so the values are positive for all eliminations except
14330 from the soft frame pointer to the hard frame pointer.
14332 SFP may point just inside the local variables block to ensure correct
14336 /* Calculate stack offsets. These are used to calculate register elimination
14337 offsets and in prologue/epilogue code. Also calculates which registers
14338 should be saved. */
14340 static arm_stack_offsets
*
14341 arm_get_frame_offsets (void)
14343 struct arm_stack_offsets
*offsets
;
14344 unsigned long func_type
;
14348 HOST_WIDE_INT frame_size
;
14351 offsets
= &cfun
->machine
->stack_offsets
;
14353 /* We need to know if we are a leaf function. Unfortunately, it
14354 is possible to be called after start_sequence has been called,
14355 which causes get_insns to return the insns for the sequence,
14356 not the function, which will cause leaf_function_p to return
14357 the incorrect result.
14359 to know about leaf functions once reload has completed, and the
14360 frame size cannot be changed after that time, so we can safely
14361 use the cached value. */
14363 if (reload_completed
)
14366 /* Initially this is the size of the local variables. It will translated
14367 into an offset once we have determined the size of preceding data. */
14368 frame_size
= ROUND_UP_WORD (get_frame_size ());
14370 leaf
= leaf_function_p ();
14372 /* Space for variadic functions. */
14373 offsets
->saved_args
= crtl
->args
.pretend_args_size
;
14375 /* In Thumb mode this is incorrect, but never used. */
14376 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0) +
14377 arm_compute_static_chain_stack_bytes();
14381 unsigned int regno
;
14383 offsets
->saved_regs_mask
= arm_compute_save_reg_mask ();
14384 core_saved
= bit_count (offsets
->saved_regs_mask
) * 4;
14385 saved
= core_saved
;
14387 /* We know that SP will be doubleword aligned on entry, and we must
14388 preserve that condition at any subroutine call. We also require the
14389 soft frame pointer to be doubleword aligned. */
14391 if (TARGET_REALLY_IWMMXT
)
14393 /* Check for the call-saved iWMMXt registers. */
14394 for (regno
= FIRST_IWMMXT_REGNUM
;
14395 regno
<= LAST_IWMMXT_REGNUM
;
14397 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
14401 func_type
= arm_current_func_type ();
14402 if (! IS_VOLATILE (func_type
))
14404 /* Space for saved FPA registers. */
14405 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
14406 if (df_regs_ever_live_p (regno
) && ! call_used_regs
[regno
])
14409 /* Space for saved VFP registers. */
14410 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
14411 saved
+= arm_get_vfp_saved_size ();
14414 else /* TARGET_THUMB1 */
14416 offsets
->saved_regs_mask
= thumb1_compute_save_reg_mask ();
14417 core_saved
= bit_count (offsets
->saved_regs_mask
) * 4;
14418 saved
= core_saved
;
14419 if (TARGET_BACKTRACE
)
14423 /* Saved registers include the stack frame. */
14424 offsets
->saved_regs
= offsets
->saved_args
+ saved
+
14425 arm_compute_static_chain_stack_bytes();
14426 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
14427 /* A leaf function does not need any stack alignment if it has nothing
14429 if (leaf
&& frame_size
== 0)
14431 offsets
->outgoing_args
= offsets
->soft_frame
;
14432 offsets
->locals_base
= offsets
->soft_frame
;
14436 /* Ensure SFP has the correct alignment. */
14437 if (ARM_DOUBLEWORD_ALIGN
14438 && (offsets
->soft_frame
& 7))
14440 offsets
->soft_frame
+= 4;
14441 /* Try to align stack by pushing an extra reg. Don't bother doing this
14442 when there is a stack frame as the alignment will be rolled into
14443 the normal stack adjustment. */
14444 if (frame_size
+ crtl
->outgoing_args_size
== 0)
14448 /* If it is safe to use r3, then do so. This sometimes
14449 generates better code on Thumb-2 by avoiding the need to
14450 use 32-bit push/pop instructions. */
14451 if (!crtl
->tail_call_emit
14452 && arm_size_return_regs () <= 12)
14457 for (i
= 4; i
<= (TARGET_THUMB1
? LAST_LO_REGNUM
: 11); i
++)
14459 if ((offsets
->saved_regs_mask
& (1 << i
)) == 0)
14468 offsets
->saved_regs
+= 4;
14469 offsets
->saved_regs_mask
|= (1 << reg
);
14474 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
14475 offsets
->outgoing_args
= (offsets
->locals_base
14476 + crtl
->outgoing_args_size
);
14478 if (ARM_DOUBLEWORD_ALIGN
)
14480 /* Ensure SP remains doubleword aligned. */
14481 if (offsets
->outgoing_args
& 7)
14482 offsets
->outgoing_args
+= 4;
14483 gcc_assert (!(offsets
->outgoing_args
& 7));
14490 /* Calculate the relative offsets for the different stack pointers. Positive
14491 offsets are in the direction of stack growth. */
14494 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
14496 arm_stack_offsets
*offsets
;
14498 offsets
= arm_get_frame_offsets ();
14500 /* OK, now we have enough information to compute the distances.
14501 There must be an entry in these switch tables for each pair
14502 of registers in ELIMINABLE_REGS, even if some of the entries
14503 seem to be redundant or useless. */
14506 case ARG_POINTER_REGNUM
:
14509 case THUMB_HARD_FRAME_POINTER_REGNUM
:
14512 case FRAME_POINTER_REGNUM
:
14513 /* This is the reverse of the soft frame pointer
14514 to hard frame pointer elimination below. */
14515 return offsets
->soft_frame
- offsets
->saved_args
;
14517 case ARM_HARD_FRAME_POINTER_REGNUM
:
14518 /* This is only non-zero in the case where the static chain register
14519 is stored above the frame. */
14520 return offsets
->frame
- offsets
->saved_args
- 4;
14522 case STACK_POINTER_REGNUM
:
14523 /* If nothing has been pushed on the stack at all
14524 then this will return -4. This *is* correct! */
14525 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
14528 gcc_unreachable ();
14530 gcc_unreachable ();
14532 case FRAME_POINTER_REGNUM
:
14535 case THUMB_HARD_FRAME_POINTER_REGNUM
:
14538 case ARM_HARD_FRAME_POINTER_REGNUM
:
14539 /* The hard frame pointer points to the top entry in the
14540 stack frame. The soft frame pointer to the bottom entry
14541 in the stack frame. If there is no stack frame at all,
14542 then they are identical. */
14544 return offsets
->frame
- offsets
->soft_frame
;
14546 case STACK_POINTER_REGNUM
:
14547 return offsets
->outgoing_args
- offsets
->soft_frame
;
14550 gcc_unreachable ();
14552 gcc_unreachable ();
14555 /* You cannot eliminate from the stack pointer.
14556 In theory you could eliminate from the hard frame
14557 pointer to the stack pointer, but this will never
14558 happen, since if a stack frame is not needed the
14559 hard frame pointer will never be used. */
14560 gcc_unreachable ();
14564 /* Given FROM and TO register numbers, say whether this elimination is
14565 allowed. Frame pointer elimination is automatically handled.
14567 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
14568 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
14569 pointer, we must eliminate FRAME_POINTER_REGNUM into
14570 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
14571 ARG_POINTER_REGNUM. */
14574 arm_can_eliminate (const int from
, const int to
)
14576 return ((to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
) ? false :
14577 (to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
) ? false :
14578 (to
== ARM_HARD_FRAME_POINTER_REGNUM
&& TARGET_THUMB
) ? false :
14579 (to
== THUMB_HARD_FRAME_POINTER_REGNUM
&& TARGET_ARM
) ? false :
14583 /* Emit RTL to save coprocessor registers on function entry. Returns the
14584 number of bytes pushed. */
14587 arm_save_coproc_regs(void)
14589 int saved_size
= 0;
14591 unsigned start_reg
;
14594 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
14595 if (df_regs_ever_live_p (reg
) && ! call_used_regs
[reg
])
14597 insn
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
14598 insn
= gen_rtx_MEM (V2SImode
, insn
);
14599 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
14600 RTX_FRAME_RELATED_P (insn
) = 1;
14604 /* Save any floating point call-saved registers used by this
14606 if (TARGET_FPA_EMU2
)
14608 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
14609 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
14611 insn
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
14612 insn
= gen_rtx_MEM (XFmode
, insn
);
14613 insn
= emit_set_insn (insn
, gen_rtx_REG (XFmode
, reg
));
14614 RTX_FRAME_RELATED_P (insn
) = 1;
14620 start_reg
= LAST_FPA_REGNUM
;
14622 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
14624 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
14626 if (start_reg
- reg
== 3)
14628 insn
= emit_sfm (reg
, 4);
14629 RTX_FRAME_RELATED_P (insn
) = 1;
14631 start_reg
= reg
- 1;
14636 if (start_reg
!= reg
)
14638 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
14639 RTX_FRAME_RELATED_P (insn
) = 1;
14640 saved_size
+= (start_reg
- reg
) * 12;
14642 start_reg
= reg
- 1;
14646 if (start_reg
!= reg
)
14648 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
14649 saved_size
+= (start_reg
- reg
) * 12;
14650 RTX_FRAME_RELATED_P (insn
) = 1;
14653 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
14655 start_reg
= FIRST_VFP_REGNUM
;
14657 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
14659 if ((!df_regs_ever_live_p (reg
) || call_used_regs
[reg
])
14660 && (!df_regs_ever_live_p (reg
+ 1) || call_used_regs
[reg
+ 1]))
14662 if (start_reg
!= reg
)
14663 saved_size
+= vfp_emit_fstmd (start_reg
,
14664 (reg
- start_reg
) / 2);
14665 start_reg
= reg
+ 2;
14668 if (start_reg
!= reg
)
14669 saved_size
+= vfp_emit_fstmd (start_reg
,
14670 (reg
- start_reg
) / 2);
14676 /* Set the Thumb frame pointer from the stack pointer. */
14679 thumb_set_frame_pointer (arm_stack_offsets
*offsets
)
14681 HOST_WIDE_INT amount
;
14684 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
14686 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
14687 stack_pointer_rtx
, GEN_INT (amount
)));
14690 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
14691 /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1
14692 expects the first two operands to be the same. */
14695 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
14697 hard_frame_pointer_rtx
));
14701 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
14702 hard_frame_pointer_rtx
,
14703 stack_pointer_rtx
));
14705 dwarf
= gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
14706 plus_constant (stack_pointer_rtx
, amount
));
14707 RTX_FRAME_RELATED_P (dwarf
) = 1;
14708 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
14711 RTX_FRAME_RELATED_P (insn
) = 1;
14714 /* Generate the prologue instructions for entry into an ARM or Thumb-2
14717 arm_expand_prologue (void)
14722 unsigned long live_regs_mask
;
14723 unsigned long func_type
;
14725 int saved_pretend_args
= 0;
14726 int saved_regs
= 0;
14727 unsigned HOST_WIDE_INT args_to_push
;
14728 arm_stack_offsets
*offsets
;
14730 func_type
= arm_current_func_type ();
14732 /* Naked functions don't have prologues. */
14733 if (IS_NAKED (func_type
))
14736 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
14737 args_to_push
= crtl
->args
.pretend_args_size
;
14739 /* Compute which register we will have to save onto the stack. */
14740 offsets
= arm_get_frame_offsets ();
14741 live_regs_mask
= offsets
->saved_regs_mask
;
14743 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
14745 if (IS_STACKALIGN (func_type
))
14750 /* Handle a word-aligned stack pointer. We generate the following:
14755 <save and restore r0 in normal prologue/epilogue>
14759 The unwinder doesn't need to know about the stack realignment.
14760 Just tell it we saved SP in r0. */
14761 gcc_assert (TARGET_THUMB2
&& !arm_arch_notm
&& args_to_push
== 0);
14763 r0
= gen_rtx_REG (SImode
, 0);
14764 r1
= gen_rtx_REG (SImode
, 1);
14765 /* Use a real rtvec rather than NULL_RTVEC so the rest of the
14766 compiler won't choke. */
14767 dwarf
= gen_rtx_UNSPEC (SImode
, rtvec_alloc (0), UNSPEC_STACK_ALIGN
);
14768 dwarf
= gen_rtx_SET (VOIDmode
, r0
, dwarf
);
14769 insn
= gen_movsi (r0
, stack_pointer_rtx
);
14770 RTX_FRAME_RELATED_P (insn
) = 1;
14771 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
14773 emit_insn (gen_andsi3 (r1
, r0
, GEN_INT (~(HOST_WIDE_INT
)7)));
14774 emit_insn (gen_movsi (stack_pointer_rtx
, r1
));
14777 /* For APCS frames, if IP register is clobbered
14778 when creating frame, save that register in a special
14780 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
14782 if (IS_INTERRUPT (func_type
))
14784 /* Interrupt functions must not corrupt any registers.
14785 Creating a frame pointer however, corrupts the IP
14786 register, so we must push it first. */
14787 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
14789 /* Do not set RTX_FRAME_RELATED_P on this insn.
14790 The dwarf stack unwinding code only wants to see one
14791 stack decrement per function, and this is not it. If
14792 this instruction is labeled as being part of the frame
14793 creation sequence then dwarf2out_frame_debug_expr will
14794 die when it encounters the assignment of IP to FP
14795 later on, since the use of SP here establishes SP as
14796 the CFA register and not IP.
14798 Anyway this instruction is not really part of the stack
14799 frame creation although it is part of the prologue. */
14801 else if (IS_NESTED (func_type
))
14803 /* The Static chain register is the same as the IP register
14804 used as a scratch register during stack frame creation.
14805 To get around this need to find somewhere to store IP
14806 whilst the frame is being created. We try the following
14809 1. The last argument register.
14810 2. A slot on the stack above the frame. (This only
14811 works if the function is not a varargs function).
14812 3. Register r3, after pushing the argument registers
14815 Note - we only need to tell the dwarf2 backend about the SP
14816 adjustment in the second variant; the static chain register
14817 doesn't need to be unwound, as it doesn't contain a value
14818 inherited from the caller. */
14820 if (df_regs_ever_live_p (3) == false)
14821 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
14822 else if (args_to_push
== 0)
14826 gcc_assert(arm_compute_static_chain_stack_bytes() == 4);
14829 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
14830 insn
= emit_set_insn (gen_frame_mem (SImode
, insn
), ip_rtx
);
14833 /* Just tell the dwarf backend that we adjusted SP. */
14834 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
14835 plus_constant (stack_pointer_rtx
,
14837 RTX_FRAME_RELATED_P (insn
) = 1;
14838 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
14842 /* Store the args on the stack. */
14843 if (cfun
->machine
->uses_anonymous_args
)
14844 insn
= emit_multi_reg_push
14845 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
14848 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
14849 GEN_INT (- args_to_push
)));
14851 RTX_FRAME_RELATED_P (insn
) = 1;
14853 saved_pretend_args
= 1;
14854 fp_offset
= args_to_push
;
14857 /* Now reuse r3 to preserve IP. */
14858 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
14862 insn
= emit_set_insn (ip_rtx
,
14863 plus_constant (stack_pointer_rtx
, fp_offset
));
14864 RTX_FRAME_RELATED_P (insn
) = 1;
14869 /* Push the argument registers, or reserve space for them. */
14870 if (cfun
->machine
->uses_anonymous_args
)
14871 insn
= emit_multi_reg_push
14872 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
14875 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
14876 GEN_INT (- args_to_push
)));
14877 RTX_FRAME_RELATED_P (insn
) = 1;
14880 /* If this is an interrupt service routine, and the link register
14881 is going to be pushed, and we're not generating extra
14882 push of IP (needed when frame is needed and frame layout if apcs),
14883 subtracting four from LR now will mean that the function return
14884 can be done with a single instruction. */
14885 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
14886 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
14887 && !(frame_pointer_needed
&& TARGET_APCS_FRAME
)
14890 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
14892 emit_set_insn (lr
, plus_constant (lr
, -4));
14895 if (live_regs_mask
)
14897 saved_regs
+= bit_count (live_regs_mask
) * 4;
14898 if (optimize_size
&& !frame_pointer_needed
14899 && saved_regs
== offsets
->saved_regs
- offsets
->saved_args
)
14901 /* If no coprocessor registers are being pushed and we don't have
14902 to worry about a frame pointer then push extra registers to
14903 create the stack frame. This is done is a way that does not
14904 alter the frame layout, so is independent of the epilogue. */
14908 while (n
< 8 && (live_regs_mask
& (1 << n
)) == 0)
14910 frame
= offsets
->outgoing_args
- (offsets
->saved_args
+ saved_regs
);
14911 if (frame
&& n
* 4 >= frame
)
14914 live_regs_mask
|= (1 << n
) - 1;
14915 saved_regs
+= frame
;
14918 insn
= emit_multi_reg_push (live_regs_mask
);
14919 RTX_FRAME_RELATED_P (insn
) = 1;
14922 if (! IS_VOLATILE (func_type
))
14923 saved_regs
+= arm_save_coproc_regs ();
14925 if (frame_pointer_needed
&& TARGET_ARM
)
14927 /* Create the new frame pointer. */
14928 if (TARGET_APCS_FRAME
)
14930 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
14931 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
14932 RTX_FRAME_RELATED_P (insn
) = 1;
14934 if (IS_NESTED (func_type
))
14936 /* Recover the static chain register. */
14937 if (!df_regs_ever_live_p (3)
14938 || saved_pretend_args
)
14939 insn
= gen_rtx_REG (SImode
, 3);
14940 else /* if (crtl->args.pretend_args_size == 0) */
14942 insn
= plus_constant (hard_frame_pointer_rtx
, 4);
14943 insn
= gen_frame_mem (SImode
, insn
);
14945 emit_set_insn (ip_rtx
, insn
);
14946 /* Add a USE to stop propagate_one_insn() from barfing. */
14947 emit_insn (gen_prologue_use (ip_rtx
));
14952 insn
= GEN_INT (saved_regs
- 4);
14953 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
14954 stack_pointer_rtx
, insn
));
14955 RTX_FRAME_RELATED_P (insn
) = 1;
14959 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
14961 /* This add can produce multiple insns for a large constant, so we
14962 need to get tricky. */
14963 rtx last
= get_last_insn ();
14965 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
14966 - offsets
->outgoing_args
);
14968 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
14972 last
= last
? NEXT_INSN (last
) : get_insns ();
14973 RTX_FRAME_RELATED_P (last
) = 1;
14975 while (last
!= insn
);
14977 /* If the frame pointer is needed, emit a special barrier that
14978 will prevent the scheduler from moving stores to the frame
14979 before the stack adjustment. */
14980 if (frame_pointer_needed
)
14981 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
14982 hard_frame_pointer_rtx
));
14986 if (frame_pointer_needed
&& TARGET_THUMB2
)
14987 thumb_set_frame_pointer (offsets
);
14989 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
14991 unsigned long mask
;
14993 mask
= live_regs_mask
;
14994 mask
&= THUMB2_WORK_REGS
;
14995 if (!IS_NESTED (func_type
))
14996 mask
|= (1 << IP_REGNUM
);
14997 arm_load_pic_register (mask
);
15000 /* If we are profiling, make sure no instructions are scheduled before
15001 the call to mcount. Similarly if the user has requested no
15002 scheduling in the prolog. Similarly if we want non-call exceptions
15003 using the EABI unwinder, to prevent faulting instructions from being
15004 swapped with a stack adjustment. */
15005 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
15006 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
15007 emit_insn (gen_blockage ());
15009 /* If the link register is being kept alive, with the return address in it,
15010 then make sure that it does not get reused by the ce2 pass. */
15011 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
15012 cfun
->machine
->lr_save_eliminated
= 1;
15015 /* Print condition code to STREAM. Helper function for arm_print_operand. */
15017 arm_print_condition (FILE *stream
)
15019 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
15021 /* Branch conversion is not implemented for Thumb-2. */
15024 output_operand_lossage ("predicated Thumb instruction");
15027 if (current_insn_predicate
!= NULL
)
15029 output_operand_lossage
15030 ("predicated instruction in conditional sequence");
15034 fputs (arm_condition_codes
[arm_current_cc
], stream
);
15036 else if (current_insn_predicate
)
15038 enum arm_cond_code code
;
15042 output_operand_lossage ("predicated Thumb instruction");
15046 code
= get_arm_condition_code (current_insn_predicate
);
15047 fputs (arm_condition_codes
[code
], stream
);
15052 /* If CODE is 'd', then the X is a condition operand and the instruction
15053 should only be executed if the condition is true.
15054 if CODE is 'D', then the X is a condition operand and the instruction
15055 should only be executed if the condition is false: however, if the mode
15056 of the comparison is CCFPEmode, then always execute the instruction -- we
15057 do this because in these circumstances !GE does not necessarily imply LT;
15058 in these cases the instruction pattern will take care to make sure that
15059 an instruction containing %d will follow, thereby undoing the effects of
15060 doing this instruction unconditionally.
15061 If CODE is 'N' then X is a floating point operand that must be negated
15063 If CODE is 'B' then output a bitwise inverted value of X (a const int).
15064 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
15066 arm_print_operand (FILE *stream
, rtx x
, int code
)
15071 fputs (ASM_COMMENT_START
, stream
);
15075 fputs (user_label_prefix
, stream
);
15079 fputs (REGISTER_PREFIX
, stream
);
15083 arm_print_condition (stream
);
15087 /* Nothing in unified syntax, otherwise the current condition code. */
15088 if (!TARGET_UNIFIED_ASM
)
15089 arm_print_condition (stream
);
15093 /* The current condition code in unified syntax, otherwise nothing. */
15094 if (TARGET_UNIFIED_ASM
)
15095 arm_print_condition (stream
);
15099 /* The current condition code for a condition code setting instruction.
15100 Preceded by 's' in unified syntax, otherwise followed by 's'. */
15101 if (TARGET_UNIFIED_ASM
)
15103 fputc('s', stream
);
15104 arm_print_condition (stream
);
15108 arm_print_condition (stream
);
15109 fputc('s', stream
);
15114 /* If the instruction is conditionally executed then print
15115 the current condition code, otherwise print 's'. */
15116 gcc_assert (TARGET_THUMB2
&& TARGET_UNIFIED_ASM
);
15117 if (current_insn_predicate
)
15118 arm_print_condition (stream
);
15120 fputc('s', stream
);
15123 /* %# is a "break" sequence. It doesn't output anything, but is used to
15124 separate e.g. operand numbers from following text, if that text consists
15125 of further digits which we don't want to be part of the operand
15133 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
15134 r
= REAL_VALUE_NEGATE (r
);
15135 fprintf (stream
, "%s", fp_const_from_val (&r
));
15139 /* An integer or symbol address without a preceding # sign. */
15141 switch (GET_CODE (x
))
15144 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
15148 output_addr_const (stream
, x
);
15152 gcc_unreachable ();
15157 if (GET_CODE (x
) == CONST_INT
)
15160 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
15161 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
15165 putc ('~', stream
);
15166 output_addr_const (stream
, x
);
15171 /* The low 16 bits of an immediate constant. */
15172 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL(x
) & 0xffff);
15176 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
15179 /* Truncate Cirrus shift counts. */
15181 if (GET_CODE (x
) == CONST_INT
)
15183 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
15186 arm_print_operand (stream
, x
, 0);
15190 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
15198 if (!shift_operator (x
, SImode
))
15200 output_operand_lossage ("invalid shift operand");
15204 shift
= shift_op (x
, &val
);
15208 fprintf (stream
, ", %s ", shift
);
15210 arm_print_operand (stream
, XEXP (x
, 1), 0);
15212 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
15217 /* An explanation of the 'Q', 'R' and 'H' register operands:
15219 In a pair of registers containing a DI or DF value the 'Q'
15220 operand returns the register number of the register containing
15221 the least significant part of the value. The 'R' operand returns
15222 the register number of the register containing the most
15223 significant part of the value.
15225 The 'H' operand returns the higher of the two register numbers.
15226 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
15227 same as the 'Q' operand, since the most significant part of the
15228 value is held in the lower number register. The reverse is true
15229 on systems where WORDS_BIG_ENDIAN is false.
15231 The purpose of these operands is to distinguish between cases
15232 where the endian-ness of the values is important (for example
15233 when they are added together), and cases where the endian-ness
15234 is irrelevant, but the order of register operations is important.
15235 For example when loading a value from memory into a register
15236 pair, the endian-ness does not matter. Provided that the value
15237 from the lower memory address is put into the lower numbered
15238 register, and the value from the higher address is put into the
15239 higher numbered register, the load will work regardless of whether
15240 the value being loaded is big-wordian or little-wordian. The
15241 order of the two register loads can matter however, if the address
15242 of the memory location is actually held in one of the registers
15243 being overwritten by the load. */
15245 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
15247 output_operand_lossage ("invalid operand for code '%c'", code
);
15251 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
15255 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
15257 output_operand_lossage ("invalid operand for code '%c'", code
);
15261 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
15265 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
15267 output_operand_lossage ("invalid operand for code '%c'", code
);
15271 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
15275 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
15277 output_operand_lossage ("invalid operand for code '%c'", code
);
15281 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 3 : 2));
15285 if (GET_CODE (x
) != REG
|| REGNO (x
) > LAST_ARM_REGNUM
)
15287 output_operand_lossage ("invalid operand for code '%c'", code
);
15291 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 2 : 3));
15295 asm_fprintf (stream
, "%r",
15296 GET_CODE (XEXP (x
, 0)) == REG
15297 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
15301 asm_fprintf (stream
, "{%r-%r}",
15303 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
15306 /* Like 'M', but writing doubleword vector registers, for use by Neon
15310 int regno
= (REGNO (x
) - FIRST_VFP_REGNUM
) / 2;
15311 int numregs
= ARM_NUM_REGS (GET_MODE (x
)) / 2;
15313 asm_fprintf (stream
, "{d%d}", regno
);
15315 asm_fprintf (stream
, "{d%d-d%d}", regno
, regno
+ numregs
- 1);
15320 /* CONST_TRUE_RTX means always -- that's the default. */
15321 if (x
== const_true_rtx
)
15324 if (!COMPARISON_P (x
))
15326 output_operand_lossage ("invalid operand for code '%c'", code
);
15330 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
15335 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
15336 want to do that. */
15337 if (x
== const_true_rtx
)
15339 output_operand_lossage ("instruction never executed");
15342 if (!COMPARISON_P (x
))
15344 output_operand_lossage ("invalid operand for code '%c'", code
);
15348 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
15349 (get_arm_condition_code (x
))],
15353 /* Cirrus registers can be accessed in a variety of ways:
15354 single floating point (f)
15355 double floating point (d)
15357 64bit integer (dx). */
15358 case 'W': /* Cirrus register in F mode. */
15359 case 'X': /* Cirrus register in D mode. */
15360 case 'Y': /* Cirrus register in FX mode. */
15361 case 'Z': /* Cirrus register in DX mode. */
15362 gcc_assert (GET_CODE (x
) == REG
15363 && REGNO_REG_CLASS (REGNO (x
)) == CIRRUS_REGS
);
15365 fprintf (stream
, "mv%s%s",
15367 : code
== 'X' ? "d"
15368 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
15372 /* Print cirrus register in the mode specified by the register's mode. */
15375 int mode
= GET_MODE (x
);
15377 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
15379 output_operand_lossage ("invalid operand for code '%c'", code
);
15383 fprintf (stream
, "mv%s%s",
15384 mode
== DFmode
? "d"
15385 : mode
== SImode
? "fx"
15386 : mode
== DImode
? "dx"
15387 : "f", reg_names
[REGNO (x
)] + 2);
15393 if (GET_CODE (x
) != REG
15394 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
15395 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
15396 /* Bad value for wCG register number. */
15398 output_operand_lossage ("invalid operand for code '%c'", code
);
15403 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
15406 /* Print an iWMMXt control register name. */
15408 if (GET_CODE (x
) != CONST_INT
15410 || INTVAL (x
) >= 16)
15411 /* Bad value for wC register number. */
15413 output_operand_lossage ("invalid operand for code '%c'", code
);
15419 static const char * wc_reg_names
[16] =
15421 "wCID", "wCon", "wCSSF", "wCASF",
15422 "wC4", "wC5", "wC6", "wC7",
15423 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
15424 "wC12", "wC13", "wC14", "wC15"
15427 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
15431 /* Print the high single-precision register of a VFP double-precision
15435 int mode
= GET_MODE (x
);
15438 if (GET_MODE_SIZE (mode
) != 8 || GET_CODE (x
) != REG
)
15440 output_operand_lossage ("invalid operand for code '%c'", code
);
15445 if (!VFP_REGNO_OK_FOR_DOUBLE (regno
))
15447 output_operand_lossage ("invalid operand for code '%c'", code
);
15451 fprintf (stream
, "s%d", regno
- FIRST_VFP_REGNUM
+ 1);
15455 /* Print a VFP/Neon double precision or quad precision register name. */
15459 int mode
= GET_MODE (x
);
15460 int is_quad
= (code
== 'q');
15463 if (GET_MODE_SIZE (mode
) != (is_quad
? 16 : 8))
15465 output_operand_lossage ("invalid operand for code '%c'", code
);
15469 if (GET_CODE (x
) != REG
15470 || !IS_VFP_REGNUM (REGNO (x
)))
15472 output_operand_lossage ("invalid operand for code '%c'", code
);
15477 if ((is_quad
&& !NEON_REGNO_OK_FOR_QUAD (regno
))
15478 || (!is_quad
&& !VFP_REGNO_OK_FOR_DOUBLE (regno
)))
15480 output_operand_lossage ("invalid operand for code '%c'", code
);
15484 fprintf (stream
, "%c%d", is_quad
? 'q' : 'd',
15485 (regno
- FIRST_VFP_REGNUM
) >> (is_quad
? 2 : 1));
15489 /* These two codes print the low/high doubleword register of a Neon quad
15490 register, respectively. For pair-structure types, can also print
15491 low/high quadword registers. */
15495 int mode
= GET_MODE (x
);
15498 if ((GET_MODE_SIZE (mode
) != 16
15499 && GET_MODE_SIZE (mode
) != 32) || GET_CODE (x
) != REG
)
15501 output_operand_lossage ("invalid operand for code '%c'", code
);
15506 if (!NEON_REGNO_OK_FOR_QUAD (regno
))
15508 output_operand_lossage ("invalid operand for code '%c'", code
);
15512 if (GET_MODE_SIZE (mode
) == 16)
15513 fprintf (stream
, "d%d", ((regno
- FIRST_VFP_REGNUM
) >> 1)
15514 + (code
== 'f' ? 1 : 0));
15516 fprintf (stream
, "q%d", ((regno
- FIRST_VFP_REGNUM
) >> 2)
15517 + (code
== 'f' ? 1 : 0));
15521 /* Print a VFPv3 floating-point constant, represented as an integer
15525 int index
= vfp3_const_double_index (x
);
15526 gcc_assert (index
!= -1);
15527 fprintf (stream
, "%d", index
);
15531 /* Print bits representing opcode features for Neon.
15533 Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed
15534 and polynomials as unsigned.
15536 Bit 1 is 1 for floats and polynomials, 0 for ordinary integers.
15538 Bit 2 is 1 for rounding functions, 0 otherwise. */
15540 /* Identify the type as 's', 'u', 'p' or 'f'. */
15543 HOST_WIDE_INT bits
= INTVAL (x
);
15544 fputc ("uspf"[bits
& 3], stream
);
15548 /* Likewise, but signed and unsigned integers are both 'i'. */
15551 HOST_WIDE_INT bits
= INTVAL (x
);
15552 fputc ("iipf"[bits
& 3], stream
);
15556 /* As for 'T', but emit 'u' instead of 'p'. */
15559 HOST_WIDE_INT bits
= INTVAL (x
);
15560 fputc ("usuf"[bits
& 3], stream
);
15564 /* Bit 2: rounding (vs none). */
15567 HOST_WIDE_INT bits
= INTVAL (x
);
15568 fputs ((bits
& 4) != 0 ? "r" : "", stream
);
15572 /* Memory operand for vld1/vst1 instruction. */
15576 bool postinc
= FALSE
;
15577 gcc_assert (GET_CODE (x
) == MEM
);
15578 addr
= XEXP (x
, 0);
15579 if (GET_CODE (addr
) == POST_INC
)
15582 addr
= XEXP (addr
, 0);
15584 asm_fprintf (stream
, "[%r]", REGNO (addr
));
15586 fputs("!", stream
);
15590 /* Translate an S register number into a D register number and element index. */
15593 int mode
= GET_MODE (x
);
15596 if (GET_MODE_SIZE (mode
) != 4 || GET_CODE (x
) != REG
)
15598 output_operand_lossage ("invalid operand for code '%c'", code
);
15603 if (!VFP_REGNO_OK_FOR_SINGLE (regno
))
15605 output_operand_lossage ("invalid operand for code '%c'", code
);
15609 regno
= regno
- FIRST_VFP_REGNUM
;
15610 fprintf (stream
, "d%d[%d]", regno
/ 2, regno
% 2);
15614 /* Register specifier for vld1.16/vst1.16. Translate the S register
15615 number into a D register number and element index. */
15618 int mode
= GET_MODE (x
);
15621 if (GET_MODE_SIZE (mode
) != 2 || GET_CODE (x
) != REG
)
15623 output_operand_lossage ("invalid operand for code '%c'", code
);
15628 if (!VFP_REGNO_OK_FOR_SINGLE (regno
))
15630 output_operand_lossage ("invalid operand for code '%c'", code
);
15634 regno
= regno
- FIRST_VFP_REGNUM
;
15635 fprintf (stream
, "d%d[%d]", regno
/2, ((regno
% 2) ? 2 : 0));
15642 output_operand_lossage ("missing operand");
15646 switch (GET_CODE (x
))
15649 asm_fprintf (stream
, "%r", REGNO (x
));
15653 output_memory_reference_mode
= GET_MODE (x
);
15654 output_address (XEXP (x
, 0));
15661 real_to_decimal (fpstr
, CONST_DOUBLE_REAL_VALUE (x
),
15662 sizeof (fpstr
), 0, 1);
15663 fprintf (stream
, "#%s", fpstr
);
15666 fprintf (stream
, "#%s", fp_immediate_constant (x
));
15670 gcc_assert (GET_CODE (x
) != NEG
);
15671 fputc ('#', stream
);
15672 if (GET_CODE (x
) == HIGH
)
15674 fputs (":lower16:", stream
);
15678 output_addr_const (stream
, x
);
15684 /* Target hook for assembling integer objects. The ARM version needs to
15685 handle word-sized values specially. */
15687 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
15689 enum machine_mode mode
;
15691 if (size
== UNITS_PER_WORD
&& aligned_p
)
15693 fputs ("\t.word\t", asm_out_file
);
15694 output_addr_const (asm_out_file
, x
);
15696 /* Mark symbols as position independent. We only do this in the
15697 .text segment, not in the .data segment. */
15698 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
15699 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
15701 /* See legitimize_pic_address for an explanation of the
15702 TARGET_VXWORKS_RTP check. */
15703 if (TARGET_VXWORKS_RTP
15704 || (GET_CODE (x
) == SYMBOL_REF
&& !SYMBOL_REF_LOCAL_P (x
)))
15705 fputs ("(GOT)", asm_out_file
);
15707 fputs ("(GOTOFF)", asm_out_file
);
15709 fputc ('\n', asm_out_file
);
15713 mode
= GET_MODE (x
);
15715 if (arm_vector_mode_supported_p (mode
))
15719 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
15721 units
= CONST_VECTOR_NUNITS (x
);
15722 size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
15724 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
15725 for (i
= 0; i
< units
; i
++)
15727 rtx elt
= CONST_VECTOR_ELT (x
, i
);
15729 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
15732 for (i
= 0; i
< units
; i
++)
15734 rtx elt
= CONST_VECTOR_ELT (x
, i
);
15735 REAL_VALUE_TYPE rval
;
15737 REAL_VALUE_FROM_CONST_DOUBLE (rval
, elt
);
15740 (rval
, GET_MODE_INNER (mode
),
15741 i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
);
15747 return default_assemble_integer (x
, size
, aligned_p
);
15751 arm_elf_asm_cdtor (rtx symbol
, int priority
, bool is_ctor
)
15755 if (!TARGET_AAPCS_BASED
)
15758 default_named_section_asm_out_constructor
15759 : default_named_section_asm_out_destructor
) (symbol
, priority
);
15763 /* Put these in the .init_array section, using a special relocation. */
15764 if (priority
!= DEFAULT_INIT_PRIORITY
)
15767 sprintf (buf
, "%s.%.5u",
15768 is_ctor
? ".init_array" : ".fini_array",
15770 s
= get_section (buf
, SECTION_WRITE
, NULL_TREE
);
15777 switch_to_section (s
);
15778 assemble_align (POINTER_SIZE
);
15779 fputs ("\t.word\t", asm_out_file
);
15780 output_addr_const (asm_out_file
, symbol
);
15781 fputs ("(target1)\n", asm_out_file
);
15784 /* Add a function to the list of static constructors. */
15787 arm_elf_asm_constructor (rtx symbol
, int priority
)
15789 arm_elf_asm_cdtor (symbol
, priority
, /*is_ctor=*/true);
15792 /* Add a function to the list of static destructors. */
15795 arm_elf_asm_destructor (rtx symbol
, int priority
)
15797 arm_elf_asm_cdtor (symbol
, priority
, /*is_ctor=*/false);
15800 /* A finite state machine takes care of noticing whether or not instructions
15801 can be conditionally executed, and thus decrease execution time and code
15802 size by deleting branch instructions. The fsm is controlled by
15803 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
15805 /* The state of the fsm controlling condition codes are:
15806 0: normal, do nothing special
15807 1: make ASM_OUTPUT_OPCODE not output this instruction
15808 2: make ASM_OUTPUT_OPCODE not output this instruction
15809 3: make instructions conditional
15810 4: make instructions conditional
15812 State transitions (state->state by whom under condition):
15813 0 -> 1 final_prescan_insn if the `target' is a label
15814 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
15815 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
15816 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
15817 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
15818 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
15819 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
15820 (the target insn is arm_target_insn).
15822 If the jump clobbers the conditions then we use states 2 and 4.
15824 A similar thing can be done with conditional return insns.
15826 XXX In case the `target' is an unconditional branch, this conditionalising
15827 of the instructions always reduces code size, but not always execution
15828 time. But then, I want to reduce the code size to somewhere near what
15829 /bin/cc produces. */
15831 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
15832 instructions. When a COND_EXEC instruction is seen the subsequent
15833 instructions are scanned so that multiple conditional instructions can be
15834 combined into a single IT block. arm_condexec_count and arm_condexec_mask
15835 specify the length and true/false mask for the IT block. These will be
15836 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
15838 /* Returns the index of the ARM condition code string in
15839 `arm_condition_codes'. COMPARISON should be an rtx like
15840 `(eq (...) (...))'. */
15841 static enum arm_cond_code
15842 get_arm_condition_code (rtx comparison
)
15844 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
15845 enum arm_cond_code code
;
15846 enum rtx_code comp_code
= GET_CODE (comparison
);
15848 if (GET_MODE_CLASS (mode
) != MODE_CC
)
15849 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
15850 XEXP (comparison
, 1));
15854 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
15855 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
15856 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
15857 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
15858 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
15859 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
15860 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
15861 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
15862 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
15863 case CC_DLTUmode
: code
= ARM_CC
;
15866 gcc_assert (comp_code
== EQ
|| comp_code
== NE
);
15868 if (comp_code
== EQ
)
15869 return ARM_INVERSE_CONDITION_CODE (code
);
15875 case NE
: return ARM_NE
;
15876 case EQ
: return ARM_EQ
;
15877 case GE
: return ARM_PL
;
15878 case LT
: return ARM_MI
;
15879 default: gcc_unreachable ();
15885 case NE
: return ARM_NE
;
15886 case EQ
: return ARM_EQ
;
15887 default: gcc_unreachable ();
15893 case NE
: return ARM_MI
;
15894 case EQ
: return ARM_PL
;
15895 default: gcc_unreachable ();
15900 /* These encodings assume that AC=1 in the FPA system control
15901 byte. This allows us to handle all cases except UNEQ and
15905 case GE
: return ARM_GE
;
15906 case GT
: return ARM_GT
;
15907 case LE
: return ARM_LS
;
15908 case LT
: return ARM_MI
;
15909 case NE
: return ARM_NE
;
15910 case EQ
: return ARM_EQ
;
15911 case ORDERED
: return ARM_VC
;
15912 case UNORDERED
: return ARM_VS
;
15913 case UNLT
: return ARM_LT
;
15914 case UNLE
: return ARM_LE
;
15915 case UNGT
: return ARM_HI
;
15916 case UNGE
: return ARM_PL
;
15917 /* UNEQ and LTGT do not have a representation. */
15918 case UNEQ
: /* Fall through. */
15919 case LTGT
: /* Fall through. */
15920 default: gcc_unreachable ();
15926 case NE
: return ARM_NE
;
15927 case EQ
: return ARM_EQ
;
15928 case GE
: return ARM_LE
;
15929 case GT
: return ARM_LT
;
15930 case LE
: return ARM_GE
;
15931 case LT
: return ARM_GT
;
15932 case GEU
: return ARM_LS
;
15933 case GTU
: return ARM_CC
;
15934 case LEU
: return ARM_CS
;
15935 case LTU
: return ARM_HI
;
15936 default: gcc_unreachable ();
15942 case LTU
: return ARM_CS
;
15943 case GEU
: return ARM_CC
;
15944 default: gcc_unreachable ();
15950 case NE
: return ARM_NE
;
15951 case EQ
: return ARM_EQ
;
15952 case GE
: return ARM_GE
;
15953 case GT
: return ARM_GT
;
15954 case LE
: return ARM_LE
;
15955 case LT
: return ARM_LT
;
15956 case GEU
: return ARM_CS
;
15957 case GTU
: return ARM_HI
;
15958 case LEU
: return ARM_LS
;
15959 case LTU
: return ARM_CC
;
15960 default: gcc_unreachable ();
15963 default: gcc_unreachable ();
15967 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
15970 thumb2_final_prescan_insn (rtx insn
)
15972 rtx first_insn
= insn
;
15973 rtx body
= PATTERN (insn
);
15975 enum arm_cond_code code
;
15979 /* Remove the previous insn from the count of insns to be output. */
15980 if (arm_condexec_count
)
15981 arm_condexec_count
--;
15983 /* Nothing to do if we are already inside a conditional block. */
15984 if (arm_condexec_count
)
15987 if (GET_CODE (body
) != COND_EXEC
)
15990 /* Conditional jumps are implemented directly. */
15991 if (GET_CODE (insn
) == JUMP_INSN
)
15994 predicate
= COND_EXEC_TEST (body
);
15995 arm_current_cc
= get_arm_condition_code (predicate
);
15997 n
= get_attr_ce_count (insn
);
15998 arm_condexec_count
= 1;
15999 arm_condexec_mask
= (1 << n
) - 1;
16000 arm_condexec_masklen
= n
;
16001 /* See if subsequent instructions can be combined into the same block. */
16004 insn
= next_nonnote_insn (insn
);
16006 /* Jumping into the middle of an IT block is illegal, so a label or
16007 barrier terminates the block. */
16008 if (GET_CODE (insn
) != INSN
&& GET_CODE(insn
) != JUMP_INSN
)
16011 body
= PATTERN (insn
);
16012 /* USE and CLOBBER aren't really insns, so just skip them. */
16013 if (GET_CODE (body
) == USE
16014 || GET_CODE (body
) == CLOBBER
)
16017 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
16018 if (GET_CODE (body
) != COND_EXEC
)
16020 /* Allow up to 4 conditionally executed instructions in a block. */
16021 n
= get_attr_ce_count (insn
);
16022 if (arm_condexec_masklen
+ n
> 4)
16025 predicate
= COND_EXEC_TEST (body
);
16026 code
= get_arm_condition_code (predicate
);
16027 mask
= (1 << n
) - 1;
16028 if (arm_current_cc
== code
)
16029 arm_condexec_mask
|= (mask
<< arm_condexec_masklen
);
16030 else if (arm_current_cc
!= ARM_INVERSE_CONDITION_CODE(code
))
16033 arm_condexec_count
++;
16034 arm_condexec_masklen
+= n
;
16036 /* A jump must be the last instruction in a conditional block. */
16037 if (GET_CODE(insn
) == JUMP_INSN
)
16040 /* Restore recog_data (getting the attributes of other insns can
16041 destroy this array, but final.c assumes that it remains intact
16042 across this call). */
16043 extract_constrain_insn_cached (first_insn
);
16047 arm_final_prescan_insn (rtx insn
)
16049 /* BODY will hold the body of INSN. */
16050 rtx body
= PATTERN (insn
);
16052 /* This will be 1 if trying to repeat the trick, and things need to be
16053 reversed if it appears to fail. */
16056 /* If we start with a return insn, we only succeed if we find another one. */
16057 int seeking_return
= 0;
16059 /* START_INSN will hold the insn from where we start looking. This is the
16060 first insn after the following code_label if REVERSE is true. */
16061 rtx start_insn
= insn
;
16063 /* If in state 4, check if the target branch is reached, in order to
16064 change back to state 0. */
16065 if (arm_ccfsm_state
== 4)
16067 if (insn
== arm_target_insn
)
16069 arm_target_insn
= NULL
;
16070 arm_ccfsm_state
= 0;
16075 /* If in state 3, it is possible to repeat the trick, if this insn is an
16076 unconditional branch to a label, and immediately following this branch
16077 is the previous target label which is only used once, and the label this
16078 branch jumps to is not too far off. */
16079 if (arm_ccfsm_state
== 3)
16081 if (simplejump_p (insn
))
16083 start_insn
= next_nonnote_insn (start_insn
);
16084 if (GET_CODE (start_insn
) == BARRIER
)
16086 /* XXX Isn't this always a barrier? */
16087 start_insn
= next_nonnote_insn (start_insn
);
16089 if (GET_CODE (start_insn
) == CODE_LABEL
16090 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
16091 && LABEL_NUSES (start_insn
) == 1)
16096 else if (GET_CODE (body
) == RETURN
)
16098 start_insn
= next_nonnote_insn (start_insn
);
16099 if (GET_CODE (start_insn
) == BARRIER
)
16100 start_insn
= next_nonnote_insn (start_insn
);
16101 if (GET_CODE (start_insn
) == CODE_LABEL
16102 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
16103 && LABEL_NUSES (start_insn
) == 1)
16106 seeking_return
= 1;
16115 gcc_assert (!arm_ccfsm_state
|| reverse
);
16116 if (GET_CODE (insn
) != JUMP_INSN
)
16119 /* This jump might be paralleled with a clobber of the condition codes
16120 the jump should always come first */
16121 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
16122 body
= XVECEXP (body
, 0, 0);
16125 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
16126 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
16129 int fail
= FALSE
, succeed
= FALSE
;
16130 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
16131 int then_not_else
= TRUE
;
16132 rtx this_insn
= start_insn
, label
= 0;
16134 /* Register the insn jumped to. */
16137 if (!seeking_return
)
16138 label
= XEXP (SET_SRC (body
), 0);
16140 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
16141 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
16142 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
16144 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
16145 then_not_else
= FALSE
;
16147 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
16148 seeking_return
= 1;
16149 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
16151 seeking_return
= 1;
16152 then_not_else
= FALSE
;
16155 gcc_unreachable ();
16157 /* See how many insns this branch skips, and what kind of insns. If all
16158 insns are okay, and the label or unconditional branch to the same
16159 label is not too far away, succeed. */
16160 for (insns_skipped
= 0;
16161 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
16165 this_insn
= next_nonnote_insn (this_insn
);
16169 switch (GET_CODE (this_insn
))
16172 /* Succeed if it is the target label, otherwise fail since
16173 control falls in from somewhere else. */
16174 if (this_insn
== label
)
16176 arm_ccfsm_state
= 1;
16184 /* Succeed if the following insn is the target label.
16186 If return insns are used then the last insn in a function
16187 will be a barrier. */
16188 this_insn
= next_nonnote_insn (this_insn
);
16189 if (this_insn
&& this_insn
== label
)
16191 arm_ccfsm_state
= 1;
16199 /* The AAPCS says that conditional calls should not be
16200 used since they make interworking inefficient (the
16201 linker can't transform BL<cond> into BLX). That's
16202 only a problem if the machine has BLX. */
16209 /* Succeed if the following insn is the target label, or
16210 if the following two insns are a barrier and the
16212 this_insn
= next_nonnote_insn (this_insn
);
16213 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
16214 this_insn
= next_nonnote_insn (this_insn
);
16216 if (this_insn
&& this_insn
== label
16217 && insns_skipped
< max_insns_skipped
)
16219 arm_ccfsm_state
= 1;
16227 /* If this is an unconditional branch to the same label, succeed.
16228 If it is to another label, do nothing. If it is conditional,
16230 /* XXX Probably, the tests for SET and the PC are
16233 scanbody
= PATTERN (this_insn
);
16234 if (GET_CODE (scanbody
) == SET
16235 && GET_CODE (SET_DEST (scanbody
)) == PC
)
16237 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
16238 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
16240 arm_ccfsm_state
= 2;
16243 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
16246 /* Fail if a conditional return is undesirable (e.g. on a
16247 StrongARM), but still allow this if optimizing for size. */
16248 else if (GET_CODE (scanbody
) == RETURN
16249 && !use_return_insn (TRUE
, NULL
)
16252 else if (GET_CODE (scanbody
) == RETURN
16255 arm_ccfsm_state
= 2;
16258 else if (GET_CODE (scanbody
) == PARALLEL
)
16260 switch (get_attr_conds (this_insn
))
16270 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
16275 /* Instructions using or affecting the condition codes make it
16277 scanbody
= PATTERN (this_insn
);
16278 if (!(GET_CODE (scanbody
) == SET
16279 || GET_CODE (scanbody
) == PARALLEL
)
16280 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
16283 /* A conditional cirrus instruction must be followed by
16284 a non Cirrus instruction. However, since we
16285 conditionalize instructions in this function and by
16286 the time we get here we can't add instructions
16287 (nops), because shorten_branches() has already been
16288 called, we will disable conditionalizing Cirrus
16289 instructions to be safe. */
16290 if (GET_CODE (scanbody
) != USE
16291 && GET_CODE (scanbody
) != CLOBBER
16292 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
16302 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
16303 arm_target_label
= CODE_LABEL_NUMBER (label
);
16306 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
16308 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
16310 this_insn
= next_nonnote_insn (this_insn
);
16311 gcc_assert (!this_insn
16312 || (GET_CODE (this_insn
) != BARRIER
16313 && GET_CODE (this_insn
) != CODE_LABEL
));
16317 /* Oh, dear! we ran off the end.. give up. */
16318 extract_constrain_insn_cached (insn
);
16319 arm_ccfsm_state
= 0;
16320 arm_target_insn
= NULL
;
16323 arm_target_insn
= this_insn
;
16326 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
16329 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
), 0));
16331 if (reverse
|| then_not_else
)
16332 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
16335 /* Restore recog_data (getting the attributes of other insns can
16336 destroy this array, but final.c assumes that it remains intact
16337 across this call. */
16338 extract_constrain_insn_cached (insn
);
16342 /* Output IT instructions. */
16344 thumb2_asm_output_opcode (FILE * stream
)
16349 if (arm_condexec_mask
)
16351 for (n
= 0; n
< arm_condexec_masklen
; n
++)
16352 buff
[n
] = (arm_condexec_mask
& (1 << n
)) ? 't' : 'e';
16354 asm_fprintf(stream
, "i%s\t%s\n\t", buff
,
16355 arm_condition_codes
[arm_current_cc
]);
16356 arm_condexec_mask
= 0;
16360 /* Returns true if REGNO is a valid register
16361 for holding a quantity of type MODE. */
16363 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
16365 if (GET_MODE_CLASS (mode
) == MODE_CC
)
16366 return (regno
== CC_REGNUM
16367 || (TARGET_HARD_FLOAT
&& TARGET_VFP
16368 && regno
== VFPCC_REGNUM
));
16371 /* For the Thumb we only allow values bigger than SImode in
16372 registers 0 - 6, so that there is always a second low
16373 register available to hold the upper part of the value.
16374 We probably we ought to ensure that the register is the
16375 start of an even numbered register pair. */
16376 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
16378 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
16379 && IS_CIRRUS_REGNUM (regno
))
16380 /* We have outlawed SI values in Cirrus registers because they
16381 reside in the lower 32 bits, but SF values reside in the
16382 upper 32 bits. This causes gcc all sorts of grief. We can't
16383 even split the registers into pairs because Cirrus SI values
16384 get sign extended to 64bits-- aldyh. */
16385 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
16387 if (TARGET_HARD_FLOAT
&& TARGET_VFP
16388 && IS_VFP_REGNUM (regno
))
16390 if (mode
== SFmode
|| mode
== SImode
)
16391 return VFP_REGNO_OK_FOR_SINGLE (regno
);
16393 if (mode
== DFmode
)
16394 return VFP_REGNO_OK_FOR_DOUBLE (regno
);
16396 /* VFP registers can hold HFmode values, but there is no point in
16397 putting them there unless we have hardware conversion insns. */
16398 if (mode
== HFmode
)
16399 return TARGET_FP16
&& VFP_REGNO_OK_FOR_SINGLE (regno
);
16402 return (VALID_NEON_DREG_MODE (mode
) && VFP_REGNO_OK_FOR_DOUBLE (regno
))
16403 || (VALID_NEON_QREG_MODE (mode
)
16404 && NEON_REGNO_OK_FOR_QUAD (regno
))
16405 || (mode
== TImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 2))
16406 || (mode
== EImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 3))
16407 || (mode
== OImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 4))
16408 || (mode
== CImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 6))
16409 || (mode
== XImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 8));
16414 if (TARGET_REALLY_IWMMXT
)
16416 if (IS_IWMMXT_GR_REGNUM (regno
))
16417 return mode
== SImode
;
16419 if (IS_IWMMXT_REGNUM (regno
))
16420 return VALID_IWMMXT_REG_MODE (mode
);
16423 /* We allow almost any value to be stored in the general registers.
16424 Restrict doubleword quantities to even register pairs so that we can
16425 use ldrd. Do not allow very large Neon structure opaque modes in
16426 general registers; they would use too many. */
16427 if (regno
<= LAST_ARM_REGNUM
)
16428 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0)
16429 && ARM_NUM_REGS (mode
) <= 4;
16431 if (regno
== FRAME_POINTER_REGNUM
16432 || regno
== ARG_POINTER_REGNUM
)
16433 /* We only allow integers in the fake hard registers. */
16434 return GET_MODE_CLASS (mode
) == MODE_INT
;
16436 /* The only registers left are the FPA registers
16437 which we only allow to hold FP values. */
16438 return (TARGET_HARD_FLOAT
&& TARGET_FPA
16439 && GET_MODE_CLASS (mode
) == MODE_FLOAT
16440 && regno
>= FIRST_FPA_REGNUM
16441 && regno
<= LAST_FPA_REGNUM
);
16444 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
16445 not used in arm mode. */
16448 arm_regno_class (int regno
)
16452 if (regno
== STACK_POINTER_REGNUM
)
16454 if (regno
== CC_REGNUM
)
16461 if (TARGET_THUMB2
&& regno
< 8)
16464 if ( regno
<= LAST_ARM_REGNUM
16465 || regno
== FRAME_POINTER_REGNUM
16466 || regno
== ARG_POINTER_REGNUM
)
16467 return TARGET_THUMB2
? HI_REGS
: GENERAL_REGS
;
16469 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
16470 return TARGET_THUMB2
? CC_REG
: NO_REGS
;
16472 if (IS_CIRRUS_REGNUM (regno
))
16473 return CIRRUS_REGS
;
16475 if (IS_VFP_REGNUM (regno
))
16477 if (regno
<= D7_VFP_REGNUM
)
16478 return VFP_D0_D7_REGS
;
16479 else if (regno
<= LAST_LO_VFP_REGNUM
)
16480 return VFP_LO_REGS
;
16482 return VFP_HI_REGS
;
16485 if (IS_IWMMXT_REGNUM (regno
))
16486 return IWMMXT_REGS
;
16488 if (IS_IWMMXT_GR_REGNUM (regno
))
16489 return IWMMXT_GR_REGS
;
16494 /* Handle a special case when computing the offset
16495 of an argument from the frame pointer. */
16497 arm_debugger_arg_offset (int value
, rtx addr
)
16501 /* We are only interested if dbxout_parms() failed to compute the offset. */
16505 /* We can only cope with the case where the address is held in a register. */
16506 if (GET_CODE (addr
) != REG
)
16509 /* If we are using the frame pointer to point at the argument, then
16510 an offset of 0 is correct. */
16511 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
16514 /* If we are using the stack pointer to point at the
16515 argument, then an offset of 0 is correct. */
16516 /* ??? Check this is consistent with thumb2 frame layout. */
16517 if ((TARGET_THUMB
|| !frame_pointer_needed
)
16518 && REGNO (addr
) == SP_REGNUM
)
16521 /* Oh dear. The argument is pointed to by a register rather
16522 than being held in a register, or being stored at a known
16523 offset from the frame pointer. Since GDB only understands
16524 those two kinds of argument we must translate the address
16525 held in the register into an offset from the frame pointer.
16526 We do this by searching through the insns for the function
16527 looking to see where this register gets its value. If the
16528 register is initialized from the frame pointer plus an offset
16529 then we are in luck and we can continue, otherwise we give up.
16531 This code is exercised by producing debugging information
16532 for a function with arguments like this:
16534 double func (double a, double b, int c, double d) {return d;}
16536 Without this code the stab for parameter 'd' will be set to
16537 an offset of 0 from the frame pointer, rather than 8. */
16539 /* The if() statement says:
16541 If the insn is a normal instruction
16542 and if the insn is setting the value in a register
16543 and if the register being set is the register holding the address of the argument
16544 and if the address is computing by an addition
16545 that involves adding to a register
16546 which is the frame pointer
16551 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16553 if ( GET_CODE (insn
) == INSN
16554 && GET_CODE (PATTERN (insn
)) == SET
16555 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
16556 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
16557 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
16558 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
16559 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
16562 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
16571 warning (0, "unable to compute real location of stacked parameter");
16572 value
= 8; /* XXX magic hack */
16578 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
16581 if ((MASK) & insn_flags) \
16582 add_builtin_function ((NAME), (TYPE), (CODE), \
16583 BUILT_IN_MD, NULL, NULL_TREE); \
16587 struct builtin_description
16589 const unsigned int mask
;
16590 const enum insn_code icode
;
16591 const char * const name
;
16592 const enum arm_builtins code
;
16593 const enum rtx_code comparison
;
16594 const unsigned int flag
;
16597 static const struct builtin_description bdesc_2arg
[] =
16599 #define IWMMXT_BUILTIN(code, string, builtin) \
16600 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
16601 ARM_BUILTIN_##builtin, UNKNOWN, 0 },
16603 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
16604 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
16605 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
16606 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
16607 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
16608 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
16609 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
16610 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
16611 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
16612 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
16613 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
16614 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
16615 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
16616 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
16617 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
16618 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
16619 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
16620 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
16621 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
16622 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
16623 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
16624 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
16625 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
16626 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
16627 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
16628 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
16629 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
16630 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
16631 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
16632 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
16633 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
16634 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
16635 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
16636 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
16637 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
16638 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
16639 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
16640 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
16641 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
16642 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
16643 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
16644 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
16645 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
16646 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
16647 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
16648 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
16649 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
16650 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
16651 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
16652 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
16653 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
16654 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
16655 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
16656 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
16657 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
16658 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
16659 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
16660 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
16662 #define IWMMXT_BUILTIN2(code, builtin) \
16663 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
16665 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
16666 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
16667 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
16668 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
16669 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
16670 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
16671 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
16672 IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt
, WSLLHI
)
16673 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
16674 IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt
, WSLLWI
)
16675 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
16676 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
16677 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
16678 IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt
, WSRLHI
)
16679 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
16680 IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt
, WSRLWI
)
16681 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
16682 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
16683 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
16684 IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt
, WSRAHI
)
16685 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
16686 IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt
, WSRAWI
)
16687 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
16688 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
16689 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
16690 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
16691 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
16692 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
16693 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
16694 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
16695 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
16696 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
16699 static const struct builtin_description bdesc_1arg
[] =
16701 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
16702 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
16703 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
16704 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
16705 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
16706 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
16707 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
16708 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
16709 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
16710 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
16711 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
16712 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
16713 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
16714 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
16715 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
16716 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
16717 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
16718 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
16721 /* Set up all the iWMMXt builtins. This is
16722 not called if TARGET_IWMMXT is zero. */
16725 arm_init_iwmmxt_builtins (void)
16727 const struct builtin_description
* d
;
16729 tree endlink
= void_list_node
;
16731 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
16732 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
16733 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
16736 = build_function_type (integer_type_node
,
16737 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
16738 tree v8qi_ftype_v8qi_v8qi_int
16739 = build_function_type (V8QI_type_node
,
16740 tree_cons (NULL_TREE
, V8QI_type_node
,
16741 tree_cons (NULL_TREE
, V8QI_type_node
,
16742 tree_cons (NULL_TREE
,
16745 tree v4hi_ftype_v4hi_int
16746 = build_function_type (V4HI_type_node
,
16747 tree_cons (NULL_TREE
, V4HI_type_node
,
16748 tree_cons (NULL_TREE
, integer_type_node
,
16750 tree v2si_ftype_v2si_int
16751 = build_function_type (V2SI_type_node
,
16752 tree_cons (NULL_TREE
, V2SI_type_node
,
16753 tree_cons (NULL_TREE
, integer_type_node
,
16755 tree v2si_ftype_di_di
16756 = build_function_type (V2SI_type_node
,
16757 tree_cons (NULL_TREE
, long_long_integer_type_node
,
16758 tree_cons (NULL_TREE
, long_long_integer_type_node
,
16760 tree di_ftype_di_int
16761 = build_function_type (long_long_integer_type_node
,
16762 tree_cons (NULL_TREE
, long_long_integer_type_node
,
16763 tree_cons (NULL_TREE
, integer_type_node
,
16765 tree di_ftype_di_int_int
16766 = build_function_type (long_long_integer_type_node
,
16767 tree_cons (NULL_TREE
, long_long_integer_type_node
,
16768 tree_cons (NULL_TREE
, integer_type_node
,
16769 tree_cons (NULL_TREE
,
16772 tree int_ftype_v8qi
16773 = build_function_type (integer_type_node
,
16774 tree_cons (NULL_TREE
, V8QI_type_node
,
16776 tree int_ftype_v4hi
16777 = build_function_type (integer_type_node
,
16778 tree_cons (NULL_TREE
, V4HI_type_node
,
16780 tree int_ftype_v2si
16781 = build_function_type (integer_type_node
,
16782 tree_cons (NULL_TREE
, V2SI_type_node
,
16784 tree int_ftype_v8qi_int
16785 = build_function_type (integer_type_node
,
16786 tree_cons (NULL_TREE
, V8QI_type_node
,
16787 tree_cons (NULL_TREE
, integer_type_node
,
16789 tree int_ftype_v4hi_int
16790 = build_function_type (integer_type_node
,
16791 tree_cons (NULL_TREE
, V4HI_type_node
,
16792 tree_cons (NULL_TREE
, integer_type_node
,
16794 tree int_ftype_v2si_int
16795 = build_function_type (integer_type_node
,
16796 tree_cons (NULL_TREE
, V2SI_type_node
,
16797 tree_cons (NULL_TREE
, integer_type_node
,
16799 tree v8qi_ftype_v8qi_int_int
16800 = build_function_type (V8QI_type_node
,
16801 tree_cons (NULL_TREE
, V8QI_type_node
,
16802 tree_cons (NULL_TREE
, integer_type_node
,
16803 tree_cons (NULL_TREE
,
16806 tree v4hi_ftype_v4hi_int_int
16807 = build_function_type (V4HI_type_node
,
16808 tree_cons (NULL_TREE
, V4HI_type_node
,
16809 tree_cons (NULL_TREE
, integer_type_node
,
16810 tree_cons (NULL_TREE
,
16813 tree v2si_ftype_v2si_int_int
16814 = build_function_type (V2SI_type_node
,
16815 tree_cons (NULL_TREE
, V2SI_type_node
,
16816 tree_cons (NULL_TREE
, integer_type_node
,
16817 tree_cons (NULL_TREE
,
16820 /* Miscellaneous. */
16821 tree v8qi_ftype_v4hi_v4hi
16822 = build_function_type (V8QI_type_node
,
16823 tree_cons (NULL_TREE
, V4HI_type_node
,
16824 tree_cons (NULL_TREE
, V4HI_type_node
,
16826 tree v4hi_ftype_v2si_v2si
16827 = build_function_type (V4HI_type_node
,
16828 tree_cons (NULL_TREE
, V2SI_type_node
,
16829 tree_cons (NULL_TREE
, V2SI_type_node
,
16831 tree v2si_ftype_v4hi_v4hi
16832 = build_function_type (V2SI_type_node
,
16833 tree_cons (NULL_TREE
, V4HI_type_node
,
16834 tree_cons (NULL_TREE
, V4HI_type_node
,
16836 tree v2si_ftype_v8qi_v8qi
16837 = build_function_type (V2SI_type_node
,
16838 tree_cons (NULL_TREE
, V8QI_type_node
,
16839 tree_cons (NULL_TREE
, V8QI_type_node
,
16841 tree v4hi_ftype_v4hi_di
16842 = build_function_type (V4HI_type_node
,
16843 tree_cons (NULL_TREE
, V4HI_type_node
,
16844 tree_cons (NULL_TREE
,
16845 long_long_integer_type_node
,
16847 tree v2si_ftype_v2si_di
16848 = build_function_type (V2SI_type_node
,
16849 tree_cons (NULL_TREE
, V2SI_type_node
,
16850 tree_cons (NULL_TREE
,
16851 long_long_integer_type_node
,
16853 tree void_ftype_int_int
16854 = build_function_type (void_type_node
,
16855 tree_cons (NULL_TREE
, integer_type_node
,
16856 tree_cons (NULL_TREE
, integer_type_node
,
16859 = build_function_type (long_long_unsigned_type_node
, endlink
);
16861 = build_function_type (long_long_integer_type_node
,
16862 tree_cons (NULL_TREE
, V8QI_type_node
,
16865 = build_function_type (long_long_integer_type_node
,
16866 tree_cons (NULL_TREE
, V4HI_type_node
,
16869 = build_function_type (long_long_integer_type_node
,
16870 tree_cons (NULL_TREE
, V2SI_type_node
,
16872 tree v2si_ftype_v4hi
16873 = build_function_type (V2SI_type_node
,
16874 tree_cons (NULL_TREE
, V4HI_type_node
,
16876 tree v4hi_ftype_v8qi
16877 = build_function_type (V4HI_type_node
,
16878 tree_cons (NULL_TREE
, V8QI_type_node
,
16881 tree di_ftype_di_v4hi_v4hi
16882 = build_function_type (long_long_unsigned_type_node
,
16883 tree_cons (NULL_TREE
,
16884 long_long_unsigned_type_node
,
16885 tree_cons (NULL_TREE
, V4HI_type_node
,
16886 tree_cons (NULL_TREE
,
16890 tree di_ftype_v4hi_v4hi
16891 = build_function_type (long_long_unsigned_type_node
,
16892 tree_cons (NULL_TREE
, V4HI_type_node
,
16893 tree_cons (NULL_TREE
, V4HI_type_node
,
16896 /* Normal vector binops. */
16897 tree v8qi_ftype_v8qi_v8qi
16898 = build_function_type (V8QI_type_node
,
16899 tree_cons (NULL_TREE
, V8QI_type_node
,
16900 tree_cons (NULL_TREE
, V8QI_type_node
,
16902 tree v4hi_ftype_v4hi_v4hi
16903 = build_function_type (V4HI_type_node
,
16904 tree_cons (NULL_TREE
, V4HI_type_node
,
16905 tree_cons (NULL_TREE
, V4HI_type_node
,
16907 tree v2si_ftype_v2si_v2si
16908 = build_function_type (V2SI_type_node
,
16909 tree_cons (NULL_TREE
, V2SI_type_node
,
16910 tree_cons (NULL_TREE
, V2SI_type_node
,
16912 tree di_ftype_di_di
16913 = build_function_type (long_long_unsigned_type_node
,
16914 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
16915 tree_cons (NULL_TREE
,
16916 long_long_unsigned_type_node
,
16919 /* Add all builtins that are more or less simple operations on two
16921 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
16923 /* Use one of the operands; the target can have a different mode for
16924 mask-generating compares. */
16925 enum machine_mode mode
;
16931 mode
= insn_data
[d
->icode
].operand
[1].mode
;
16936 type
= v8qi_ftype_v8qi_v8qi
;
16939 type
= v4hi_ftype_v4hi_v4hi
;
16942 type
= v2si_ftype_v2si_v2si
;
16945 type
= di_ftype_di_di
;
16949 gcc_unreachable ();
16952 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
16955 /* Add the remaining MMX insns with somewhat more complicated types. */
16956 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
16957 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
16958 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
16960 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
16961 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
16962 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
16963 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
16964 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
16965 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
16967 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
16968 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
16969 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
16970 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
16971 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
16972 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
16974 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
16975 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
16976 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
16977 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
16978 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
16979 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
16981 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
16982 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
16983 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
16984 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
16985 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
16986 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
16988 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
16990 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
16991 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
16992 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
16993 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
16995 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
16996 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
16997 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
16998 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
16999 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
17000 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
17001 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
17002 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
17003 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
17005 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
17006 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
17007 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
17009 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
17010 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
17011 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
17013 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
17014 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
17015 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
17016 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
17017 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
17018 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
17020 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
17021 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
17022 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
17023 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
17024 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
17025 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
17026 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
17027 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
17028 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
17029 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
17030 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
17031 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
17033 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
17034 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
17035 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
17036 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
17038 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
17039 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
17040 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
17041 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
17042 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
17043 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
17044 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
17048 arm_init_tls_builtins (void)
17052 ftype
= build_function_type (ptr_type_node
, void_list_node
);
17053 decl
= add_builtin_function ("__builtin_thread_pointer", ftype
,
17054 ARM_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
17056 TREE_NOTHROW (decl
) = 1;
17057 TREE_READONLY (decl
) = 1;
17060 enum neon_builtin_type_bits
{
17076 #define v8qi_UP T_V8QI
17077 #define v4hi_UP T_V4HI
17078 #define v2si_UP T_V2SI
17079 #define v2sf_UP T_V2SF
17081 #define v16qi_UP T_V16QI
17082 #define v8hi_UP T_V8HI
17083 #define v4si_UP T_V4SI
17084 #define v4sf_UP T_V4SF
17085 #define v2di_UP T_V2DI
17090 #define UP(X) X##_UP
17125 NEON_LOADSTRUCTLANE
,
17127 NEON_STORESTRUCTLANE
,
17136 const neon_itype itype
;
17138 const enum insn_code codes
[T_MAX
];
17139 const unsigned int num_vars
;
17140 unsigned int base_fcode
;
17141 } neon_builtin_datum
;
17143 #define CF(N,X) CODE_FOR_neon_##N##X
17145 #define VAR1(T, N, A) \
17146 #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0
17147 #define VAR2(T, N, A, B) \
17148 #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0
17149 #define VAR3(T, N, A, B, C) \
17150 #N, NEON_##T, UP (A) | UP (B) | UP (C), \
17151 { CF (N, A), CF (N, B), CF (N, C) }, 3, 0
17152 #define VAR4(T, N, A, B, C, D) \
17153 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \
17154 { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0
17155 #define VAR5(T, N, A, B, C, D, E) \
17156 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \
17157 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0
17158 #define VAR6(T, N, A, B, C, D, E, F) \
17159 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \
17160 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0
17161 #define VAR7(T, N, A, B, C, D, E, F, G) \
17162 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \
17163 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
17165 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
17166 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
17168 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
17169 CF (N, G), CF (N, H) }, 8, 0
17170 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
17171 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
17172 | UP (H) | UP (I), \
17173 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
17174 CF (N, G), CF (N, H), CF (N, I) }, 9, 0
17175 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
17176 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
17177 | UP (H) | UP (I) | UP (J), \
17178 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
17179 CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0
17181 /* The mode entries in the following table correspond to the "key" type of the
17182 instruction variant, i.e. equivalent to that which would be specified after
17183 the assembler mnemonic, which usually refers to the last vector operand.
17184 (Signed/unsigned/polynomial types are not differentiated between though, and
17185 are all mapped onto the same mode for a given element size.) The modes
17186 listed per instruction should be the same as those defined for that
17187 instruction's pattern in neon.md.
17188 WARNING: Variants should be listed in the same increasing order as
17189 neon_builtin_type_bits. */
17191 static neon_builtin_datum neon_builtin_data
[] =
17193 { VAR10 (BINOP
, vadd
,
17194 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17195 { VAR3 (BINOP
, vaddl
, v8qi
, v4hi
, v2si
) },
17196 { VAR3 (BINOP
, vaddw
, v8qi
, v4hi
, v2si
) },
17197 { VAR6 (BINOP
, vhadd
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17198 { VAR8 (BINOP
, vqadd
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17199 { VAR3 (BINOP
, vaddhn
, v8hi
, v4si
, v2di
) },
17200 { VAR8 (BINOP
, vmul
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17201 { VAR8 (TERNOP
, vmla
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17202 { VAR3 (TERNOP
, vmlal
, v8qi
, v4hi
, v2si
) },
17203 { VAR8 (TERNOP
, vmls
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17204 { VAR3 (TERNOP
, vmlsl
, v8qi
, v4hi
, v2si
) },
17205 { VAR4 (BINOP
, vqdmulh
, v4hi
, v2si
, v8hi
, v4si
) },
17206 { VAR2 (TERNOP
, vqdmlal
, v4hi
, v2si
) },
17207 { VAR2 (TERNOP
, vqdmlsl
, v4hi
, v2si
) },
17208 { VAR3 (BINOP
, vmull
, v8qi
, v4hi
, v2si
) },
17209 { VAR2 (SCALARMULL
, vmull_n
, v4hi
, v2si
) },
17210 { VAR2 (LANEMULL
, vmull_lane
, v4hi
, v2si
) },
17211 { VAR2 (SCALARMULL
, vqdmull_n
, v4hi
, v2si
) },
17212 { VAR2 (LANEMULL
, vqdmull_lane
, v4hi
, v2si
) },
17213 { VAR4 (SCALARMULH
, vqdmulh_n
, v4hi
, v2si
, v8hi
, v4si
) },
17214 { VAR4 (LANEMULH
, vqdmulh_lane
, v4hi
, v2si
, v8hi
, v4si
) },
17215 { VAR2 (BINOP
, vqdmull
, v4hi
, v2si
) },
17216 { VAR8 (BINOP
, vshl
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17217 { VAR8 (BINOP
, vqshl
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17218 { VAR8 (SHIFTIMM
, vshr_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17219 { VAR3 (SHIFTIMM
, vshrn_n
, v8hi
, v4si
, v2di
) },
17220 { VAR3 (SHIFTIMM
, vqshrn_n
, v8hi
, v4si
, v2di
) },
17221 { VAR3 (SHIFTIMM
, vqshrun_n
, v8hi
, v4si
, v2di
) },
17222 { VAR8 (SHIFTIMM
, vshl_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17223 { VAR8 (SHIFTIMM
, vqshl_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17224 { VAR8 (SHIFTIMM
, vqshlu_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17225 { VAR3 (SHIFTIMM
, vshll_n
, v8qi
, v4hi
, v2si
) },
17226 { VAR8 (SHIFTACC
, vsra_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17227 { VAR10 (BINOP
, vsub
,
17228 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17229 { VAR3 (BINOP
, vsubl
, v8qi
, v4hi
, v2si
) },
17230 { VAR3 (BINOP
, vsubw
, v8qi
, v4hi
, v2si
) },
17231 { VAR8 (BINOP
, vqsub
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17232 { VAR6 (BINOP
, vhsub
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17233 { VAR3 (BINOP
, vsubhn
, v8hi
, v4si
, v2di
) },
17234 { VAR8 (BINOP
, vceq
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17235 { VAR8 (BINOP
, vcge
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17236 { VAR8 (BINOP
, vcgt
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17237 { VAR2 (BINOP
, vcage
, v2sf
, v4sf
) },
17238 { VAR2 (BINOP
, vcagt
, v2sf
, v4sf
) },
17239 { VAR6 (BINOP
, vtst
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17240 { VAR8 (BINOP
, vabd
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17241 { VAR3 (BINOP
, vabdl
, v8qi
, v4hi
, v2si
) },
17242 { VAR6 (TERNOP
, vaba
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17243 { VAR3 (TERNOP
, vabal
, v8qi
, v4hi
, v2si
) },
17244 { VAR8 (BINOP
, vmax
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17245 { VAR8 (BINOP
, vmin
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17246 { VAR4 (BINOP
, vpadd
, v8qi
, v4hi
, v2si
, v2sf
) },
17247 { VAR6 (UNOP
, vpaddl
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17248 { VAR6 (BINOP
, vpadal
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17249 { VAR4 (BINOP
, vpmax
, v8qi
, v4hi
, v2si
, v2sf
) },
17250 { VAR4 (BINOP
, vpmin
, v8qi
, v4hi
, v2si
, v2sf
) },
17251 { VAR2 (BINOP
, vrecps
, v2sf
, v4sf
) },
17252 { VAR2 (BINOP
, vrsqrts
, v2sf
, v4sf
) },
17253 { VAR8 (SHIFTINSERT
, vsri_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17254 { VAR8 (SHIFTINSERT
, vsli_n
, v8qi
, v4hi
, v2si
, di
, v16qi
, v8hi
, v4si
, v2di
) },
17255 { VAR8 (UNOP
, vabs
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17256 { VAR6 (UNOP
, vqabs
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17257 { VAR8 (UNOP
, vneg
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17258 { VAR6 (UNOP
, vqneg
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17259 { VAR6 (UNOP
, vcls
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17260 { VAR6 (UNOP
, vclz
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17261 { VAR2 (UNOP
, vcnt
, v8qi
, v16qi
) },
17262 { VAR4 (UNOP
, vrecpe
, v2si
, v2sf
, v4si
, v4sf
) },
17263 { VAR4 (UNOP
, vrsqrte
, v2si
, v2sf
, v4si
, v4sf
) },
17264 { VAR6 (UNOP
, vmvn
, v8qi
, v4hi
, v2si
, v16qi
, v8hi
, v4si
) },
17265 /* FIXME: vget_lane supports more variants than this! */
17266 { VAR10 (GETLANE
, vget_lane
,
17267 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17268 { VAR10 (SETLANE
, vset_lane
,
17269 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17270 { VAR5 (CREATE
, vcreate
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17271 { VAR10 (DUP
, vdup_n
,
17272 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17273 { VAR10 (DUPLANE
, vdup_lane
,
17274 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17275 { VAR5 (COMBINE
, vcombine
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17276 { VAR5 (SPLIT
, vget_high
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17277 { VAR5 (SPLIT
, vget_low
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17278 { VAR3 (UNOP
, vmovn
, v8hi
, v4si
, v2di
) },
17279 { VAR3 (UNOP
, vqmovn
, v8hi
, v4si
, v2di
) },
17280 { VAR3 (UNOP
, vqmovun
, v8hi
, v4si
, v2di
) },
17281 { VAR3 (UNOP
, vmovl
, v8qi
, v4hi
, v2si
) },
17282 { VAR6 (LANEMUL
, vmul_lane
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17283 { VAR6 (LANEMAC
, vmla_lane
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17284 { VAR2 (LANEMAC
, vmlal_lane
, v4hi
, v2si
) },
17285 { VAR2 (LANEMAC
, vqdmlal_lane
, v4hi
, v2si
) },
17286 { VAR6 (LANEMAC
, vmls_lane
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17287 { VAR2 (LANEMAC
, vmlsl_lane
, v4hi
, v2si
) },
17288 { VAR2 (LANEMAC
, vqdmlsl_lane
, v4hi
, v2si
) },
17289 { VAR6 (SCALARMUL
, vmul_n
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17290 { VAR6 (SCALARMAC
, vmla_n
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17291 { VAR2 (SCALARMAC
, vmlal_n
, v4hi
, v2si
) },
17292 { VAR2 (SCALARMAC
, vqdmlal_n
, v4hi
, v2si
) },
17293 { VAR6 (SCALARMAC
, vmls_n
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17294 { VAR2 (SCALARMAC
, vmlsl_n
, v4hi
, v2si
) },
17295 { VAR2 (SCALARMAC
, vqdmlsl_n
, v4hi
, v2si
) },
17296 { VAR10 (BINOP
, vext
,
17297 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17298 { VAR8 (UNOP
, vrev64
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17299 { VAR4 (UNOP
, vrev32
, v8qi
, v4hi
, v16qi
, v8hi
) },
17300 { VAR2 (UNOP
, vrev16
, v8qi
, v16qi
) },
17301 { VAR4 (CONVERT
, vcvt
, v2si
, v2sf
, v4si
, v4sf
) },
17302 { VAR4 (FIXCONV
, vcvt_n
, v2si
, v2sf
, v4si
, v4sf
) },
17303 { VAR10 (SELECT
, vbsl
,
17304 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17305 { VAR1 (VTBL
, vtbl1
, v8qi
) },
17306 { VAR1 (VTBL
, vtbl2
, v8qi
) },
17307 { VAR1 (VTBL
, vtbl3
, v8qi
) },
17308 { VAR1 (VTBL
, vtbl4
, v8qi
) },
17309 { VAR1 (VTBX
, vtbx1
, v8qi
) },
17310 { VAR1 (VTBX
, vtbx2
, v8qi
) },
17311 { VAR1 (VTBX
, vtbx3
, v8qi
) },
17312 { VAR1 (VTBX
, vtbx4
, v8qi
) },
17313 { VAR8 (RESULTPAIR
, vtrn
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17314 { VAR8 (RESULTPAIR
, vzip
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17315 { VAR8 (RESULTPAIR
, vuzp
, v8qi
, v4hi
, v2si
, v2sf
, v16qi
, v8hi
, v4si
, v4sf
) },
17316 { VAR5 (REINTERP
, vreinterpretv8qi
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17317 { VAR5 (REINTERP
, vreinterpretv4hi
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17318 { VAR5 (REINTERP
, vreinterpretv2si
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17319 { VAR5 (REINTERP
, vreinterpretv2sf
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17320 { VAR5 (REINTERP
, vreinterpretdi
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17321 { VAR5 (REINTERP
, vreinterpretv16qi
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17322 { VAR5 (REINTERP
, vreinterpretv8hi
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17323 { VAR5 (REINTERP
, vreinterpretv4si
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17324 { VAR5 (REINTERP
, vreinterpretv4sf
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17325 { VAR5 (REINTERP
, vreinterpretv2di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17326 { VAR10 (LOAD1
, vld1
,
17327 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17328 { VAR10 (LOAD1LANE
, vld1_lane
,
17329 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17330 { VAR10 (LOAD1
, vld1_dup
,
17331 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17332 { VAR10 (STORE1
, vst1
,
17333 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17334 { VAR10 (STORE1LANE
, vst1_lane
,
17335 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17336 { VAR9 (LOADSTRUCT
,
17337 vld2
, v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
) },
17338 { VAR7 (LOADSTRUCTLANE
, vld2_lane
,
17339 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17340 { VAR5 (LOADSTRUCT
, vld2_dup
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17341 { VAR9 (STORESTRUCT
, vst2
,
17342 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
) },
17343 { VAR7 (STORESTRUCTLANE
, vst2_lane
,
17344 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17345 { VAR9 (LOADSTRUCT
,
17346 vld3
, v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
) },
17347 { VAR7 (LOADSTRUCTLANE
, vld3_lane
,
17348 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17349 { VAR5 (LOADSTRUCT
, vld3_dup
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17350 { VAR9 (STORESTRUCT
, vst3
,
17351 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
) },
17352 { VAR7 (STORESTRUCTLANE
, vst3_lane
,
17353 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17354 { VAR9 (LOADSTRUCT
, vld4
,
17355 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
) },
17356 { VAR7 (LOADSTRUCTLANE
, vld4_lane
,
17357 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17358 { VAR5 (LOADSTRUCT
, vld4_dup
, v8qi
, v4hi
, v2si
, v2sf
, di
) },
17359 { VAR9 (STORESTRUCT
, vst4
,
17360 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
) },
17361 { VAR7 (STORESTRUCTLANE
, vst4_lane
,
17362 v8qi
, v4hi
, v2si
, v2sf
, v8hi
, v4si
, v4sf
) },
17363 { VAR10 (LOGICBINOP
, vand
,
17364 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17365 { VAR10 (LOGICBINOP
, vorr
,
17366 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17367 { VAR10 (BINOP
, veor
,
17368 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17369 { VAR10 (LOGICBINOP
, vbic
,
17370 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) },
17371 { VAR10 (LOGICBINOP
, vorn
,
17372 v8qi
, v4hi
, v2si
, v2sf
, di
, v16qi
, v8hi
, v4si
, v4sf
, v2di
) }
17388 arm_init_neon_builtins (void)
17390 unsigned int i
, fcode
= ARM_BUILTIN_NEON_BASE
;
17392 tree neon_intQI_type_node
;
17393 tree neon_intHI_type_node
;
17394 tree neon_polyQI_type_node
;
17395 tree neon_polyHI_type_node
;
17396 tree neon_intSI_type_node
;
17397 tree neon_intDI_type_node
;
17398 tree neon_float_type_node
;
17400 tree intQI_pointer_node
;
17401 tree intHI_pointer_node
;
17402 tree intSI_pointer_node
;
17403 tree intDI_pointer_node
;
17404 tree float_pointer_node
;
17406 tree const_intQI_node
;
17407 tree const_intHI_node
;
17408 tree const_intSI_node
;
17409 tree const_intDI_node
;
17410 tree const_float_node
;
17412 tree const_intQI_pointer_node
;
17413 tree const_intHI_pointer_node
;
17414 tree const_intSI_pointer_node
;
17415 tree const_intDI_pointer_node
;
17416 tree const_float_pointer_node
;
17418 tree V8QI_type_node
;
17419 tree V4HI_type_node
;
17420 tree V2SI_type_node
;
17421 tree V2SF_type_node
;
17422 tree V16QI_type_node
;
17423 tree V8HI_type_node
;
17424 tree V4SI_type_node
;
17425 tree V4SF_type_node
;
17426 tree V2DI_type_node
;
17428 tree intUQI_type_node
;
17429 tree intUHI_type_node
;
17430 tree intUSI_type_node
;
17431 tree intUDI_type_node
;
17433 tree intEI_type_node
;
17434 tree intOI_type_node
;
17435 tree intCI_type_node
;
17436 tree intXI_type_node
;
17438 tree V8QI_pointer_node
;
17439 tree V4HI_pointer_node
;
17440 tree V2SI_pointer_node
;
17441 tree V2SF_pointer_node
;
17442 tree V16QI_pointer_node
;
17443 tree V8HI_pointer_node
;
17444 tree V4SI_pointer_node
;
17445 tree V4SF_pointer_node
;
17446 tree V2DI_pointer_node
;
17448 tree void_ftype_pv8qi_v8qi_v8qi
;
17449 tree void_ftype_pv4hi_v4hi_v4hi
;
17450 tree void_ftype_pv2si_v2si_v2si
;
17451 tree void_ftype_pv2sf_v2sf_v2sf
;
17452 tree void_ftype_pdi_di_di
;
17453 tree void_ftype_pv16qi_v16qi_v16qi
;
17454 tree void_ftype_pv8hi_v8hi_v8hi
;
17455 tree void_ftype_pv4si_v4si_v4si
;
17456 tree void_ftype_pv4sf_v4sf_v4sf
;
17457 tree void_ftype_pv2di_v2di_v2di
;
17459 tree reinterp_ftype_dreg
[5][5];
17460 tree reinterp_ftype_qreg
[5][5];
17461 tree dreg_types
[5], qreg_types
[5];
17463 /* Create distinguished type nodes for NEON vector element types,
17464 and pointers to values of such types, so we can detect them later. */
17465 neon_intQI_type_node
= make_signed_type (GET_MODE_PRECISION (QImode
));
17466 neon_intHI_type_node
= make_signed_type (GET_MODE_PRECISION (HImode
));
17467 neon_polyQI_type_node
= make_signed_type (GET_MODE_PRECISION (QImode
));
17468 neon_polyHI_type_node
= make_signed_type (GET_MODE_PRECISION (HImode
));
17469 neon_intSI_type_node
= make_signed_type (GET_MODE_PRECISION (SImode
));
17470 neon_intDI_type_node
= make_signed_type (GET_MODE_PRECISION (DImode
));
17471 neon_float_type_node
= make_node (REAL_TYPE
);
17472 TYPE_PRECISION (neon_float_type_node
) = FLOAT_TYPE_SIZE
;
17473 layout_type (neon_float_type_node
);
17475 /* Define typedefs which exactly correspond to the modes we are basing vector
17476 types on. If you change these names you'll need to change
17477 the table used by arm_mangle_type too. */
17478 (*lang_hooks
.types
.register_builtin_type
) (neon_intQI_type_node
,
17479 "__builtin_neon_qi");
17480 (*lang_hooks
.types
.register_builtin_type
) (neon_intHI_type_node
,
17481 "__builtin_neon_hi");
17482 (*lang_hooks
.types
.register_builtin_type
) (neon_intSI_type_node
,
17483 "__builtin_neon_si");
17484 (*lang_hooks
.types
.register_builtin_type
) (neon_float_type_node
,
17485 "__builtin_neon_sf");
17486 (*lang_hooks
.types
.register_builtin_type
) (neon_intDI_type_node
,
17487 "__builtin_neon_di");
17488 (*lang_hooks
.types
.register_builtin_type
) (neon_polyQI_type_node
,
17489 "__builtin_neon_poly8");
17490 (*lang_hooks
.types
.register_builtin_type
) (neon_polyHI_type_node
,
17491 "__builtin_neon_poly16");
17493 intQI_pointer_node
= build_pointer_type (neon_intQI_type_node
);
17494 intHI_pointer_node
= build_pointer_type (neon_intHI_type_node
);
17495 intSI_pointer_node
= build_pointer_type (neon_intSI_type_node
);
17496 intDI_pointer_node
= build_pointer_type (neon_intDI_type_node
);
17497 float_pointer_node
= build_pointer_type (neon_float_type_node
);
17499 /* Next create constant-qualified versions of the above types. */
17500 const_intQI_node
= build_qualified_type (neon_intQI_type_node
,
17502 const_intHI_node
= build_qualified_type (neon_intHI_type_node
,
17504 const_intSI_node
= build_qualified_type (neon_intSI_type_node
,
17506 const_intDI_node
= build_qualified_type (neon_intDI_type_node
,
17508 const_float_node
= build_qualified_type (neon_float_type_node
,
17511 const_intQI_pointer_node
= build_pointer_type (const_intQI_node
);
17512 const_intHI_pointer_node
= build_pointer_type (const_intHI_node
);
17513 const_intSI_pointer_node
= build_pointer_type (const_intSI_node
);
17514 const_intDI_pointer_node
= build_pointer_type (const_intDI_node
);
17515 const_float_pointer_node
= build_pointer_type (const_float_node
);
17517 /* Now create vector types based on our NEON element types. */
17518 /* 64-bit vectors. */
17520 build_vector_type_for_mode (neon_intQI_type_node
, V8QImode
);
17522 build_vector_type_for_mode (neon_intHI_type_node
, V4HImode
);
17524 build_vector_type_for_mode (neon_intSI_type_node
, V2SImode
);
17526 build_vector_type_for_mode (neon_float_type_node
, V2SFmode
);
17527 /* 128-bit vectors. */
17529 build_vector_type_for_mode (neon_intQI_type_node
, V16QImode
);
17531 build_vector_type_for_mode (neon_intHI_type_node
, V8HImode
);
17533 build_vector_type_for_mode (neon_intSI_type_node
, V4SImode
);
17535 build_vector_type_for_mode (neon_float_type_node
, V4SFmode
);
17537 build_vector_type_for_mode (neon_intDI_type_node
, V2DImode
);
17539 /* Unsigned integer types for various mode sizes. */
17540 intUQI_type_node
= make_unsigned_type (GET_MODE_PRECISION (QImode
));
17541 intUHI_type_node
= make_unsigned_type (GET_MODE_PRECISION (HImode
));
17542 intUSI_type_node
= make_unsigned_type (GET_MODE_PRECISION (SImode
));
17543 intUDI_type_node
= make_unsigned_type (GET_MODE_PRECISION (DImode
));
17545 (*lang_hooks
.types
.register_builtin_type
) (intUQI_type_node
,
17546 "__builtin_neon_uqi");
17547 (*lang_hooks
.types
.register_builtin_type
) (intUHI_type_node
,
17548 "__builtin_neon_uhi");
17549 (*lang_hooks
.types
.register_builtin_type
) (intUSI_type_node
,
17550 "__builtin_neon_usi");
17551 (*lang_hooks
.types
.register_builtin_type
) (intUDI_type_node
,
17552 "__builtin_neon_udi");
17554 /* Opaque integer types for structures of vectors. */
17555 intEI_type_node
= make_signed_type (GET_MODE_PRECISION (EImode
));
17556 intOI_type_node
= make_signed_type (GET_MODE_PRECISION (OImode
));
17557 intCI_type_node
= make_signed_type (GET_MODE_PRECISION (CImode
));
17558 intXI_type_node
= make_signed_type (GET_MODE_PRECISION (XImode
));
17560 (*lang_hooks
.types
.register_builtin_type
) (intTI_type_node
,
17561 "__builtin_neon_ti");
17562 (*lang_hooks
.types
.register_builtin_type
) (intEI_type_node
,
17563 "__builtin_neon_ei");
17564 (*lang_hooks
.types
.register_builtin_type
) (intOI_type_node
,
17565 "__builtin_neon_oi");
17566 (*lang_hooks
.types
.register_builtin_type
) (intCI_type_node
,
17567 "__builtin_neon_ci");
17568 (*lang_hooks
.types
.register_builtin_type
) (intXI_type_node
,
17569 "__builtin_neon_xi");
17571 /* Pointers to vector types. */
17572 V8QI_pointer_node
= build_pointer_type (V8QI_type_node
);
17573 V4HI_pointer_node
= build_pointer_type (V4HI_type_node
);
17574 V2SI_pointer_node
= build_pointer_type (V2SI_type_node
);
17575 V2SF_pointer_node
= build_pointer_type (V2SF_type_node
);
17576 V16QI_pointer_node
= build_pointer_type (V16QI_type_node
);
17577 V8HI_pointer_node
= build_pointer_type (V8HI_type_node
);
17578 V4SI_pointer_node
= build_pointer_type (V4SI_type_node
);
17579 V4SF_pointer_node
= build_pointer_type (V4SF_type_node
);
17580 V2DI_pointer_node
= build_pointer_type (V2DI_type_node
);
17582 /* Operations which return results as pairs. */
17583 void_ftype_pv8qi_v8qi_v8qi
=
17584 build_function_type_list (void_type_node
, V8QI_pointer_node
, V8QI_type_node
,
17585 V8QI_type_node
, NULL
);
17586 void_ftype_pv4hi_v4hi_v4hi
=
17587 build_function_type_list (void_type_node
, V4HI_pointer_node
, V4HI_type_node
,
17588 V4HI_type_node
, NULL
);
17589 void_ftype_pv2si_v2si_v2si
=
17590 build_function_type_list (void_type_node
, V2SI_pointer_node
, V2SI_type_node
,
17591 V2SI_type_node
, NULL
);
17592 void_ftype_pv2sf_v2sf_v2sf
=
17593 build_function_type_list (void_type_node
, V2SF_pointer_node
, V2SF_type_node
,
17594 V2SF_type_node
, NULL
);
17595 void_ftype_pdi_di_di
=
17596 build_function_type_list (void_type_node
, intDI_pointer_node
,
17597 neon_intDI_type_node
, neon_intDI_type_node
, NULL
);
17598 void_ftype_pv16qi_v16qi_v16qi
=
17599 build_function_type_list (void_type_node
, V16QI_pointer_node
,
17600 V16QI_type_node
, V16QI_type_node
, NULL
);
17601 void_ftype_pv8hi_v8hi_v8hi
=
17602 build_function_type_list (void_type_node
, V8HI_pointer_node
, V8HI_type_node
,
17603 V8HI_type_node
, NULL
);
17604 void_ftype_pv4si_v4si_v4si
=
17605 build_function_type_list (void_type_node
, V4SI_pointer_node
, V4SI_type_node
,
17606 V4SI_type_node
, NULL
);
17607 void_ftype_pv4sf_v4sf_v4sf
=
17608 build_function_type_list (void_type_node
, V4SF_pointer_node
, V4SF_type_node
,
17609 V4SF_type_node
, NULL
);
17610 void_ftype_pv2di_v2di_v2di
=
17611 build_function_type_list (void_type_node
, V2DI_pointer_node
, V2DI_type_node
,
17612 V2DI_type_node
, NULL
);
17614 dreg_types
[0] = V8QI_type_node
;
17615 dreg_types
[1] = V4HI_type_node
;
17616 dreg_types
[2] = V2SI_type_node
;
17617 dreg_types
[3] = V2SF_type_node
;
17618 dreg_types
[4] = neon_intDI_type_node
;
17620 qreg_types
[0] = V16QI_type_node
;
17621 qreg_types
[1] = V8HI_type_node
;
17622 qreg_types
[2] = V4SI_type_node
;
17623 qreg_types
[3] = V4SF_type_node
;
17624 qreg_types
[4] = V2DI_type_node
;
17626 for (i
= 0; i
< 5; i
++)
17629 for (j
= 0; j
< 5; j
++)
17631 reinterp_ftype_dreg
[i
][j
]
17632 = build_function_type_list (dreg_types
[i
], dreg_types
[j
], NULL
);
17633 reinterp_ftype_qreg
[i
][j
]
17634 = build_function_type_list (qreg_types
[i
], qreg_types
[j
], NULL
);
17638 for (i
= 0; i
< ARRAY_SIZE (neon_builtin_data
); i
++)
17640 neon_builtin_datum
*d
= &neon_builtin_data
[i
];
17641 unsigned int j
, codeidx
= 0;
17643 d
->base_fcode
= fcode
;
17645 for (j
= 0; j
< T_MAX
; j
++)
17647 const char* const modenames
[] = {
17648 "v8qi", "v4hi", "v2si", "v2sf", "di",
17649 "v16qi", "v8hi", "v4si", "v4sf", "v2di"
17653 enum insn_code icode
;
17654 int is_load
= 0, is_store
= 0;
17656 if ((d
->bits
& (1 << j
)) == 0)
17659 icode
= d
->codes
[codeidx
++];
17664 case NEON_LOAD1LANE
:
17665 case NEON_LOADSTRUCT
:
17666 case NEON_LOADSTRUCTLANE
:
17668 /* Fall through. */
17670 case NEON_STORE1LANE
:
17671 case NEON_STORESTRUCT
:
17672 case NEON_STORESTRUCTLANE
:
17675 /* Fall through. */
17678 case NEON_LOGICBINOP
:
17679 case NEON_SHIFTINSERT
:
17686 case NEON_SHIFTIMM
:
17687 case NEON_SHIFTACC
:
17693 case NEON_LANEMULL
:
17694 case NEON_LANEMULH
:
17696 case NEON_SCALARMUL
:
17697 case NEON_SCALARMULL
:
17698 case NEON_SCALARMULH
:
17699 case NEON_SCALARMAC
:
17705 tree return_type
= void_type_node
, args
= void_list_node
;
17707 /* Build a function type directly from the insn_data for this
17708 builtin. The build_function_type() function takes care of
17709 removing duplicates for us. */
17710 for (k
= insn_data
[icode
].n_operands
- 1; k
>= 0; k
--)
17714 if (is_load
&& k
== 1)
17716 /* Neon load patterns always have the memory operand
17717 (a SImode pointer) in the operand 1 position. We
17718 want a const pointer to the element type in that
17720 gcc_assert (insn_data
[icode
].operand
[k
].mode
== SImode
);
17726 eltype
= const_intQI_pointer_node
;
17731 eltype
= const_intHI_pointer_node
;
17736 eltype
= const_intSI_pointer_node
;
17741 eltype
= const_float_pointer_node
;
17746 eltype
= const_intDI_pointer_node
;
17749 default: gcc_unreachable ();
17752 else if (is_store
&& k
== 0)
17754 /* Similarly, Neon store patterns use operand 0 as
17755 the memory location to store to (a SImode pointer).
17756 Use a pointer to the element type of the store in
17758 gcc_assert (insn_data
[icode
].operand
[k
].mode
== SImode
);
17764 eltype
= intQI_pointer_node
;
17769 eltype
= intHI_pointer_node
;
17774 eltype
= intSI_pointer_node
;
17779 eltype
= float_pointer_node
;
17784 eltype
= intDI_pointer_node
;
17787 default: gcc_unreachable ();
17792 switch (insn_data
[icode
].operand
[k
].mode
)
17794 case VOIDmode
: eltype
= void_type_node
; break;
17796 case QImode
: eltype
= neon_intQI_type_node
; break;
17797 case HImode
: eltype
= neon_intHI_type_node
; break;
17798 case SImode
: eltype
= neon_intSI_type_node
; break;
17799 case SFmode
: eltype
= neon_float_type_node
; break;
17800 case DImode
: eltype
= neon_intDI_type_node
; break;
17801 case TImode
: eltype
= intTI_type_node
; break;
17802 case EImode
: eltype
= intEI_type_node
; break;
17803 case OImode
: eltype
= intOI_type_node
; break;
17804 case CImode
: eltype
= intCI_type_node
; break;
17805 case XImode
: eltype
= intXI_type_node
; break;
17806 /* 64-bit vectors. */
17807 case V8QImode
: eltype
= V8QI_type_node
; break;
17808 case V4HImode
: eltype
= V4HI_type_node
; break;
17809 case V2SImode
: eltype
= V2SI_type_node
; break;
17810 case V2SFmode
: eltype
= V2SF_type_node
; break;
17811 /* 128-bit vectors. */
17812 case V16QImode
: eltype
= V16QI_type_node
; break;
17813 case V8HImode
: eltype
= V8HI_type_node
; break;
17814 case V4SImode
: eltype
= V4SI_type_node
; break;
17815 case V4SFmode
: eltype
= V4SF_type_node
; break;
17816 case V2DImode
: eltype
= V2DI_type_node
; break;
17817 default: gcc_unreachable ();
17821 if (k
== 0 && !is_store
)
17822 return_type
= eltype
;
17824 args
= tree_cons (NULL_TREE
, eltype
, args
);
17827 ftype
= build_function_type (return_type
, args
);
17831 case NEON_RESULTPAIR
:
17833 switch (insn_data
[icode
].operand
[1].mode
)
17835 case V8QImode
: ftype
= void_ftype_pv8qi_v8qi_v8qi
; break;
17836 case V4HImode
: ftype
= void_ftype_pv4hi_v4hi_v4hi
; break;
17837 case V2SImode
: ftype
= void_ftype_pv2si_v2si_v2si
; break;
17838 case V2SFmode
: ftype
= void_ftype_pv2sf_v2sf_v2sf
; break;
17839 case DImode
: ftype
= void_ftype_pdi_di_di
; break;
17840 case V16QImode
: ftype
= void_ftype_pv16qi_v16qi_v16qi
; break;
17841 case V8HImode
: ftype
= void_ftype_pv8hi_v8hi_v8hi
; break;
17842 case V4SImode
: ftype
= void_ftype_pv4si_v4si_v4si
; break;
17843 case V4SFmode
: ftype
= void_ftype_pv4sf_v4sf_v4sf
; break;
17844 case V2DImode
: ftype
= void_ftype_pv2di_v2di_v2di
; break;
17845 default: gcc_unreachable ();
17850 case NEON_REINTERP
:
17852 /* We iterate over 5 doubleword types, then 5 quadword
17855 switch (insn_data
[icode
].operand
[0].mode
)
17857 case V8QImode
: ftype
= reinterp_ftype_dreg
[0][rhs
]; break;
17858 case V4HImode
: ftype
= reinterp_ftype_dreg
[1][rhs
]; break;
17859 case V2SImode
: ftype
= reinterp_ftype_dreg
[2][rhs
]; break;
17860 case V2SFmode
: ftype
= reinterp_ftype_dreg
[3][rhs
]; break;
17861 case DImode
: ftype
= reinterp_ftype_dreg
[4][rhs
]; break;
17862 case V16QImode
: ftype
= reinterp_ftype_qreg
[0][rhs
]; break;
17863 case V8HImode
: ftype
= reinterp_ftype_qreg
[1][rhs
]; break;
17864 case V4SImode
: ftype
= reinterp_ftype_qreg
[2][rhs
]; break;
17865 case V4SFmode
: ftype
= reinterp_ftype_qreg
[3][rhs
]; break;
17866 case V2DImode
: ftype
= reinterp_ftype_qreg
[4][rhs
]; break;
17867 default: gcc_unreachable ();
17873 gcc_unreachable ();
17876 gcc_assert (ftype
!= NULL
);
17878 sprintf (namebuf
, "__builtin_neon_%s%s", d
->name
, modenames
[j
]);
17880 add_builtin_function (namebuf
, ftype
, fcode
++, BUILT_IN_MD
, NULL
,
17887 arm_init_fp16_builtins (void)
17889 tree fp16_type
= make_node (REAL_TYPE
);
17890 TYPE_PRECISION (fp16_type
) = 16;
17891 layout_type (fp16_type
);
17892 (*lang_hooks
.types
.register_builtin_type
) (fp16_type
, "__fp16");
17896 arm_init_builtins (void)
17898 arm_init_tls_builtins ();
17900 if (TARGET_REALLY_IWMMXT
)
17901 arm_init_iwmmxt_builtins ();
17904 arm_init_neon_builtins ();
17906 if (arm_fp16_format
)
17907 arm_init_fp16_builtins ();
17910 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
17912 static const char *
17913 arm_invalid_parameter_type (const_tree t
)
17915 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
17916 return N_("function parameters cannot have __fp16 type");
17920 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
17922 static const char *
17923 arm_invalid_return_type (const_tree t
)
17925 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
17926 return N_("functions cannot return __fp16 type");
17930 /* Implement TARGET_PROMOTED_TYPE. */
17933 arm_promoted_type (const_tree t
)
17935 if (SCALAR_FLOAT_TYPE_P (t
) && TYPE_PRECISION (t
) == 16)
17936 return float_type_node
;
17940 /* Implement TARGET_CONVERT_TO_TYPE.
17941 Specifically, this hook implements the peculiarity of the ARM
17942 half-precision floating-point C semantics that requires conversions between
17943 __fp16 to or from double to do an intermediate conversion to float. */
17946 arm_convert_to_type (tree type
, tree expr
)
17948 tree fromtype
= TREE_TYPE (expr
);
17949 if (!SCALAR_FLOAT_TYPE_P (fromtype
) || !SCALAR_FLOAT_TYPE_P (type
))
17951 if ((TYPE_PRECISION (fromtype
) == 16 && TYPE_PRECISION (type
) > 32)
17952 || (TYPE_PRECISION (type
) == 16 && TYPE_PRECISION (fromtype
) > 32))
17953 return convert (type
, convert (float_type_node
, expr
));
17957 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P.
17958 This simply adds HFmode as a supported mode; even though we don't
17959 implement arithmetic on this type directly, it's supported by
17960 optabs conversions, much the way the double-word arithmetic is
17961 special-cased in the default hook. */
17964 arm_scalar_mode_supported_p (enum machine_mode mode
)
17966 if (mode
== HFmode
)
17967 return (arm_fp16_format
!= ARM_FP16_FORMAT_NONE
);
17969 return default_scalar_mode_supported_p (mode
);
17972 /* Errors in the source file can cause expand_expr to return const0_rtx
17973 where we expect a vector. To avoid crashing, use one of the vector
17974 clear instructions. */
17977 safe_vector_operand (rtx x
, enum machine_mode mode
)
17979 if (x
!= const0_rtx
)
17981 x
= gen_reg_rtx (mode
);
17983 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
17984 : gen_rtx_SUBREG (DImode
, x
, 0)));
17988 /* Subroutine of arm_expand_builtin to take care of binop insns. */
17991 arm_expand_binop_builtin (enum insn_code icode
,
17992 tree exp
, rtx target
)
17995 tree arg0
= CALL_EXPR_ARG (exp
, 0);
17996 tree arg1
= CALL_EXPR_ARG (exp
, 1);
17997 rtx op0
= expand_normal (arg0
);
17998 rtx op1
= expand_normal (arg1
);
17999 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
18000 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
18001 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
18003 if (VECTOR_MODE_P (mode0
))
18004 op0
= safe_vector_operand (op0
, mode0
);
18005 if (VECTOR_MODE_P (mode1
))
18006 op1
= safe_vector_operand (op1
, mode1
);
18009 || GET_MODE (target
) != tmode
18010 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
18011 target
= gen_reg_rtx (tmode
);
18013 gcc_assert (GET_MODE (op0
) == mode0
&& GET_MODE (op1
) == mode1
);
18015 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
18016 op0
= copy_to_mode_reg (mode0
, op0
);
18017 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
18018 op1
= copy_to_mode_reg (mode1
, op1
);
18020 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
18027 /* Subroutine of arm_expand_builtin to take care of unop insns. */
18030 arm_expand_unop_builtin (enum insn_code icode
,
18031 tree exp
, rtx target
, int do_load
)
18034 tree arg0
= CALL_EXPR_ARG (exp
, 0);
18035 rtx op0
= expand_normal (arg0
);
18036 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
18037 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
18040 || GET_MODE (target
) != tmode
18041 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
18042 target
= gen_reg_rtx (tmode
);
18044 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
18047 if (VECTOR_MODE_P (mode0
))
18048 op0
= safe_vector_operand (op0
, mode0
);
18050 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
18051 op0
= copy_to_mode_reg (mode0
, op0
);
18054 pat
= GEN_FCN (icode
) (target
, op0
);
18062 neon_builtin_compare (const void *a
, const void *b
)
18064 const neon_builtin_datum
*const key
= (const neon_builtin_datum
*) a
;
18065 const neon_builtin_datum
*const memb
= (const neon_builtin_datum
*) b
;
18066 unsigned int soughtcode
= key
->base_fcode
;
18068 if (soughtcode
>= memb
->base_fcode
18069 && soughtcode
< memb
->base_fcode
+ memb
->num_vars
)
18071 else if (soughtcode
< memb
->base_fcode
)
18077 static enum insn_code
18078 locate_neon_builtin_icode (int fcode
, neon_itype
*itype
)
18080 neon_builtin_datum key
, *found
;
18083 key
.base_fcode
= fcode
;
18084 found
= (neon_builtin_datum
*)
18085 bsearch (&key
, &neon_builtin_data
[0], ARRAY_SIZE (neon_builtin_data
),
18086 sizeof (neon_builtin_data
[0]), neon_builtin_compare
);
18087 gcc_assert (found
);
18088 idx
= fcode
- (int) found
->base_fcode
;
18089 gcc_assert (idx
>= 0 && idx
< T_MAX
&& idx
< (int)found
->num_vars
);
18092 *itype
= found
->itype
;
18094 return found
->codes
[idx
];
18098 NEON_ARG_COPY_TO_REG
,
18103 #define NEON_MAX_BUILTIN_ARGS 5
18105 /* Expand a Neon builtin. */
18107 arm_expand_neon_args (rtx target
, int icode
, int have_retval
,
18112 tree arg
[NEON_MAX_BUILTIN_ARGS
];
18113 rtx op
[NEON_MAX_BUILTIN_ARGS
];
18114 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
18115 enum machine_mode mode
[NEON_MAX_BUILTIN_ARGS
];
18120 || GET_MODE (target
) != tmode
18121 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
)))
18122 target
= gen_reg_rtx (tmode
);
18124 va_start (ap
, exp
);
18128 builtin_arg thisarg
= (builtin_arg
) va_arg (ap
, int);
18130 if (thisarg
== NEON_ARG_STOP
)
18134 arg
[argc
] = CALL_EXPR_ARG (exp
, argc
);
18135 op
[argc
] = expand_normal (arg
[argc
]);
18136 mode
[argc
] = insn_data
[icode
].operand
[argc
+ have_retval
].mode
;
18140 case NEON_ARG_COPY_TO_REG
:
18141 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
18142 if (!(*insn_data
[icode
].operand
[argc
+ have_retval
].predicate
)
18143 (op
[argc
], mode
[argc
]))
18144 op
[argc
] = copy_to_mode_reg (mode
[argc
], op
[argc
]);
18147 case NEON_ARG_CONSTANT
:
18148 /* FIXME: This error message is somewhat unhelpful. */
18149 if (!(*insn_data
[icode
].operand
[argc
+ have_retval
].predicate
)
18150 (op
[argc
], mode
[argc
]))
18151 error ("argument must be a constant");
18154 case NEON_ARG_STOP
:
18155 gcc_unreachable ();
18168 pat
= GEN_FCN (icode
) (target
, op
[0]);
18172 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
18176 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2]);
18180 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3]);
18184 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4]);
18188 gcc_unreachable ();
18194 pat
= GEN_FCN (icode
) (op
[0]);
18198 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
18202 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
18206 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
18210 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4]);
18214 gcc_unreachable ();
18225 /* Expand a Neon builtin. These are "special" because they don't have symbolic
18226 constants defined per-instruction or per instruction-variant. Instead, the
18227 required info is looked up in the table neon_builtin_data. */
18229 arm_expand_neon_builtin (int fcode
, tree exp
, rtx target
)
18232 enum insn_code icode
= locate_neon_builtin_icode (fcode
, &itype
);
18239 return arm_expand_neon_args (target
, icode
, 1, exp
,
18240 NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
18244 case NEON_SCALARMUL
:
18245 case NEON_SCALARMULL
:
18246 case NEON_SCALARMULH
:
18247 case NEON_SHIFTINSERT
:
18248 case NEON_LOGICBINOP
:
18249 return arm_expand_neon_args (target
, icode
, 1, exp
,
18250 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
18254 return arm_expand_neon_args (target
, icode
, 1, exp
,
18255 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
18256 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
18260 case NEON_SHIFTIMM
:
18261 return arm_expand_neon_args (target
, icode
, 1, exp
,
18262 NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
, NEON_ARG_CONSTANT
,
18266 return arm_expand_neon_args (target
, icode
, 1, exp
,
18267 NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
18271 case NEON_REINTERP
:
18272 return arm_expand_neon_args (target
, icode
, 1, exp
,
18273 NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
18277 return arm_expand_neon_args (target
, icode
, 1, exp
,
18278 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
18280 case NEON_RESULTPAIR
:
18281 return arm_expand_neon_args (target
, icode
, 0, exp
,
18282 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
18286 case NEON_LANEMULL
:
18287 case NEON_LANEMULH
:
18288 return arm_expand_neon_args (target
, icode
, 1, exp
,
18289 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
18290 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
18293 return arm_expand_neon_args (target
, icode
, 1, exp
,
18294 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
18295 NEON_ARG_CONSTANT
, NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
18297 case NEON_SHIFTACC
:
18298 return arm_expand_neon_args (target
, icode
, 1, exp
,
18299 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
18300 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
18302 case NEON_SCALARMAC
:
18303 return arm_expand_neon_args (target
, icode
, 1, exp
,
18304 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
18305 NEON_ARG_CONSTANT
, NEON_ARG_STOP
);
18309 return arm_expand_neon_args (target
, icode
, 1, exp
,
18310 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
,
18314 case NEON_LOADSTRUCT
:
18315 return arm_expand_neon_args (target
, icode
, 1, exp
,
18316 NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
18318 case NEON_LOAD1LANE
:
18319 case NEON_LOADSTRUCTLANE
:
18320 return arm_expand_neon_args (target
, icode
, 1, exp
,
18321 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
18325 case NEON_STORESTRUCT
:
18326 return arm_expand_neon_args (target
, icode
, 0, exp
,
18327 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_STOP
);
18329 case NEON_STORE1LANE
:
18330 case NEON_STORESTRUCTLANE
:
18331 return arm_expand_neon_args (target
, icode
, 0, exp
,
18332 NEON_ARG_COPY_TO_REG
, NEON_ARG_COPY_TO_REG
, NEON_ARG_CONSTANT
,
18336 gcc_unreachable ();
18339 /* Emit code to reinterpret one Neon type as another, without altering bits. */
18341 neon_reinterpret (rtx dest
, rtx src
)
18343 emit_move_insn (dest
, gen_lowpart (GET_MODE (dest
), src
));
18346 /* Emit code to place a Neon pair result in memory locations (with equal
18349 neon_emit_pair_result_insn (enum machine_mode mode
,
18350 rtx (*intfn
) (rtx
, rtx
, rtx
, rtx
), rtx destaddr
,
18353 rtx mem
= gen_rtx_MEM (mode
, destaddr
);
18354 rtx tmp1
= gen_reg_rtx (mode
);
18355 rtx tmp2
= gen_reg_rtx (mode
);
18357 emit_insn (intfn (tmp1
, op1
, tmp2
, op2
));
18359 emit_move_insn (mem
, tmp1
);
18360 mem
= adjust_address (mem
, mode
, GET_MODE_SIZE (mode
));
18361 emit_move_insn (mem
, tmp2
);
18364 /* Set up operands for a register copy from src to dest, taking care not to
18365 clobber registers in the process.
18366 FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't
18367 be called with a large N, so that should be OK. */
18370 neon_disambiguate_copy (rtx
*operands
, rtx
*dest
, rtx
*src
, unsigned int count
)
18372 unsigned int copied
= 0, opctr
= 0;
18373 unsigned int done
= (1 << count
) - 1;
18376 while (copied
!= done
)
18378 for (i
= 0; i
< count
; i
++)
18382 for (j
= 0; good
&& j
< count
; j
++)
18383 if (i
!= j
&& (copied
& (1 << j
)) == 0
18384 && reg_overlap_mentioned_p (src
[j
], dest
[i
]))
18389 operands
[opctr
++] = dest
[i
];
18390 operands
[opctr
++] = src
[i
];
18396 gcc_assert (opctr
== count
* 2);
18399 /* Expand an expression EXP that calls a built-in function,
18400 with result going to TARGET if that's convenient
18401 (and in mode MODE if that's convenient).
18402 SUBTARGET may be used as the target for computing one of EXP's operands.
18403 IGNORE is nonzero if the value is to be ignored. */
18406 arm_expand_builtin (tree exp
,
18408 rtx subtarget ATTRIBUTE_UNUSED
,
18409 enum machine_mode mode ATTRIBUTE_UNUSED
,
18410 int ignore ATTRIBUTE_UNUSED
)
18412 const struct builtin_description
* d
;
18413 enum insn_code icode
;
18414 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
18422 int fcode
= DECL_FUNCTION_CODE (fndecl
);
18424 enum machine_mode tmode
;
18425 enum machine_mode mode0
;
18426 enum machine_mode mode1
;
18427 enum machine_mode mode2
;
18429 if (fcode
>= ARM_BUILTIN_NEON_BASE
)
18430 return arm_expand_neon_builtin (fcode
, exp
, target
);
18434 case ARM_BUILTIN_TEXTRMSB
:
18435 case ARM_BUILTIN_TEXTRMUB
:
18436 case ARM_BUILTIN_TEXTRMSH
:
18437 case ARM_BUILTIN_TEXTRMUH
:
18438 case ARM_BUILTIN_TEXTRMSW
:
18439 case ARM_BUILTIN_TEXTRMUW
:
18440 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
18441 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
18442 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
18443 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
18444 : CODE_FOR_iwmmxt_textrmw
);
18446 arg0
= CALL_EXPR_ARG (exp
, 0);
18447 arg1
= CALL_EXPR_ARG (exp
, 1);
18448 op0
= expand_normal (arg0
);
18449 op1
= expand_normal (arg1
);
18450 tmode
= insn_data
[icode
].operand
[0].mode
;
18451 mode0
= insn_data
[icode
].operand
[1].mode
;
18452 mode1
= insn_data
[icode
].operand
[2].mode
;
18454 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
18455 op0
= copy_to_mode_reg (mode0
, op0
);
18456 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
18458 /* @@@ better error message */
18459 error ("selector must be an immediate");
18460 return gen_reg_rtx (tmode
);
18463 || GET_MODE (target
) != tmode
18464 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
18465 target
= gen_reg_rtx (tmode
);
18466 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
18472 case ARM_BUILTIN_TINSRB
:
18473 case ARM_BUILTIN_TINSRH
:
18474 case ARM_BUILTIN_TINSRW
:
18475 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
18476 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
18477 : CODE_FOR_iwmmxt_tinsrw
);
18478 arg0
= CALL_EXPR_ARG (exp
, 0);
18479 arg1
= CALL_EXPR_ARG (exp
, 1);
18480 arg2
= CALL_EXPR_ARG (exp
, 2);
18481 op0
= expand_normal (arg0
);
18482 op1
= expand_normal (arg1
);
18483 op2
= expand_normal (arg2
);
18484 tmode
= insn_data
[icode
].operand
[0].mode
;
18485 mode0
= insn_data
[icode
].operand
[1].mode
;
18486 mode1
= insn_data
[icode
].operand
[2].mode
;
18487 mode2
= insn_data
[icode
].operand
[3].mode
;
18489 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
18490 op0
= copy_to_mode_reg (mode0
, op0
);
18491 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
18492 op1
= copy_to_mode_reg (mode1
, op1
);
18493 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
18495 /* @@@ better error message */
18496 error ("selector must be an immediate");
18500 || GET_MODE (target
) != tmode
18501 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
18502 target
= gen_reg_rtx (tmode
);
18503 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
18509 case ARM_BUILTIN_SETWCX
:
18510 arg0
= CALL_EXPR_ARG (exp
, 0);
18511 arg1
= CALL_EXPR_ARG (exp
, 1);
18512 op0
= force_reg (SImode
, expand_normal (arg0
));
18513 op1
= expand_normal (arg1
);
18514 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
18517 case ARM_BUILTIN_GETWCX
:
18518 arg0
= CALL_EXPR_ARG (exp
, 0);
18519 op0
= expand_normal (arg0
);
18520 target
= gen_reg_rtx (SImode
);
18521 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
18524 case ARM_BUILTIN_WSHUFH
:
18525 icode
= CODE_FOR_iwmmxt_wshufh
;
18526 arg0
= CALL_EXPR_ARG (exp
, 0);
18527 arg1
= CALL_EXPR_ARG (exp
, 1);
18528 op0
= expand_normal (arg0
);
18529 op1
= expand_normal (arg1
);
18530 tmode
= insn_data
[icode
].operand
[0].mode
;
18531 mode1
= insn_data
[icode
].operand
[1].mode
;
18532 mode2
= insn_data
[icode
].operand
[2].mode
;
18534 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
18535 op0
= copy_to_mode_reg (mode1
, op0
);
18536 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
18538 /* @@@ better error message */
18539 error ("mask must be an immediate");
18543 || GET_MODE (target
) != tmode
18544 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
18545 target
= gen_reg_rtx (tmode
);
18546 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
18552 case ARM_BUILTIN_WSADB
:
18553 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, exp
, target
);
18554 case ARM_BUILTIN_WSADH
:
18555 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, exp
, target
);
18556 case ARM_BUILTIN_WSADBZ
:
18557 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, exp
, target
);
18558 case ARM_BUILTIN_WSADHZ
:
18559 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, exp
, target
);
18561 /* Several three-argument builtins. */
18562 case ARM_BUILTIN_WMACS
:
18563 case ARM_BUILTIN_WMACU
:
18564 case ARM_BUILTIN_WALIGN
:
18565 case ARM_BUILTIN_TMIA
:
18566 case ARM_BUILTIN_TMIAPH
:
18567 case ARM_BUILTIN_TMIATT
:
18568 case ARM_BUILTIN_TMIATB
:
18569 case ARM_BUILTIN_TMIABT
:
18570 case ARM_BUILTIN_TMIABB
:
18571 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
18572 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
18573 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
18574 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
18575 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
18576 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
18577 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
18578 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
18579 : CODE_FOR_iwmmxt_walign
);
18580 arg0
= CALL_EXPR_ARG (exp
, 0);
18581 arg1
= CALL_EXPR_ARG (exp
, 1);
18582 arg2
= CALL_EXPR_ARG (exp
, 2);
18583 op0
= expand_normal (arg0
);
18584 op1
= expand_normal (arg1
);
18585 op2
= expand_normal (arg2
);
18586 tmode
= insn_data
[icode
].operand
[0].mode
;
18587 mode0
= insn_data
[icode
].operand
[1].mode
;
18588 mode1
= insn_data
[icode
].operand
[2].mode
;
18589 mode2
= insn_data
[icode
].operand
[3].mode
;
18591 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
18592 op0
= copy_to_mode_reg (mode0
, op0
);
18593 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
18594 op1
= copy_to_mode_reg (mode1
, op1
);
18595 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
18596 op2
= copy_to_mode_reg (mode2
, op2
);
18598 || GET_MODE (target
) != tmode
18599 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
18600 target
= gen_reg_rtx (tmode
);
18601 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
18607 case ARM_BUILTIN_WZERO
:
18608 target
= gen_reg_rtx (DImode
);
18609 emit_insn (gen_iwmmxt_clrdi (target
));
18612 case ARM_BUILTIN_THREAD_POINTER
:
18613 return arm_load_tp (target
);
18619 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
18620 if (d
->code
== (const enum arm_builtins
) fcode
)
18621 return arm_expand_binop_builtin (d
->icode
, exp
, target
);
18623 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
18624 if (d
->code
== (const enum arm_builtins
) fcode
)
18625 return arm_expand_unop_builtin (d
->icode
, exp
, target
, 0);
18627 /* @@@ Should really do something sensible here. */
18631 /* Return the number (counting from 0) of
18632 the least significant set bit in MASK. */
18635 number_of_first_bit_set (unsigned mask
)
18640 (mask
& (1 << bit
)) == 0;
18647 /* Emit code to push or pop registers to or from the stack. F is the
18648 assembly file. MASK is the registers to push or pop. PUSH is
18649 nonzero if we should push, and zero if we should pop. For debugging
18650 output, if pushing, adjust CFA_OFFSET by the amount of space added
18651 to the stack. REAL_REGS should have the same number of bits set as
18652 MASK, and will be used instead (in the same order) to describe which
18653 registers were saved - this is used to mark the save slots when we
18654 push high registers after moving them to low registers. */
18656 thumb_pushpop (FILE *f
, unsigned long mask
, int push
, int *cfa_offset
,
18657 unsigned long real_regs
)
18660 int lo_mask
= mask
& 0xFF;
18661 int pushed_words
= 0;
18665 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
18667 /* Special case. Do not generate a POP PC statement here, do it in
18669 thumb_exit (f
, -1);
18673 if (ARM_EABI_UNWIND_TABLES
&& push
)
18675 fprintf (f
, "\t.save\t{");
18676 for (regno
= 0; regno
< 15; regno
++)
18678 if (real_regs
& (1 << regno
))
18680 if (real_regs
& ((1 << regno
) -1))
18682 asm_fprintf (f
, "%r", regno
);
18685 fprintf (f
, "}\n");
18688 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
18690 /* Look at the low registers first. */
18691 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
18695 asm_fprintf (f
, "%r", regno
);
18697 if ((lo_mask
& ~1) != 0)
18704 if (push
&& (mask
& (1 << LR_REGNUM
)))
18706 /* Catch pushing the LR. */
18710 asm_fprintf (f
, "%r", LR_REGNUM
);
18714 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
18716 /* Catch popping the PC. */
18717 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
18718 || crtl
->calls_eh_return
)
18720 /* The PC is never poped directly, instead
18721 it is popped into r3 and then BX is used. */
18722 fprintf (f
, "}\n");
18724 thumb_exit (f
, -1);
18733 asm_fprintf (f
, "%r", PC_REGNUM
);
18737 fprintf (f
, "}\n");
18739 if (push
&& pushed_words
&& dwarf2out_do_frame ())
18741 char *l
= dwarf2out_cfi_label (false);
18742 int pushed_mask
= real_regs
;
18744 *cfa_offset
+= pushed_words
* 4;
18745 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
18748 pushed_mask
= real_regs
;
18749 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
18751 if (pushed_mask
& 1)
18752 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
18757 /* Generate code to return from a thumb function.
18758 If 'reg_containing_return_addr' is -1, then the return address is
18759 actually on the stack, at the stack pointer. */
18761 thumb_exit (FILE *f
, int reg_containing_return_addr
)
18763 unsigned regs_available_for_popping
;
18764 unsigned regs_to_pop
;
18766 unsigned available
;
18770 int restore_a4
= FALSE
;
18772 /* Compute the registers we need to pop. */
18776 if (reg_containing_return_addr
== -1)
18778 regs_to_pop
|= 1 << LR_REGNUM
;
18782 if (TARGET_BACKTRACE
)
18784 /* Restore the (ARM) frame pointer and stack pointer. */
18785 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
18789 /* If there is nothing to pop then just emit the BX instruction and
18791 if (pops_needed
== 0)
18793 if (crtl
->calls_eh_return
)
18794 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
18796 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
18799 /* Otherwise if we are not supporting interworking and we have not created
18800 a backtrace structure and the function was not entered in ARM mode then
18801 just pop the return address straight into the PC. */
18802 else if (!TARGET_INTERWORK
18803 && !TARGET_BACKTRACE
18804 && !is_called_in_ARM_mode (current_function_decl
)
18805 && !crtl
->calls_eh_return
)
18807 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
18811 /* Find out how many of the (return) argument registers we can corrupt. */
18812 regs_available_for_popping
= 0;
18814 /* If returning via __builtin_eh_return, the bottom three registers
18815 all contain information needed for the return. */
18816 if (crtl
->calls_eh_return
)
18820 /* If we can deduce the registers used from the function's
18821 return value. This is more reliable that examining
18822 df_regs_ever_live_p () because that will be set if the register is
18823 ever used in the function, not just if the register is used
18824 to hold a return value. */
18826 if (crtl
->return_rtx
!= 0)
18827 mode
= GET_MODE (crtl
->return_rtx
);
18829 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
18831 size
= GET_MODE_SIZE (mode
);
18835 /* In a void function we can use any argument register.
18836 In a function that returns a structure on the stack
18837 we can use the second and third argument registers. */
18838 if (mode
== VOIDmode
)
18839 regs_available_for_popping
=
18840 (1 << ARG_REGISTER (1))
18841 | (1 << ARG_REGISTER (2))
18842 | (1 << ARG_REGISTER (3));
18844 regs_available_for_popping
=
18845 (1 << ARG_REGISTER (2))
18846 | (1 << ARG_REGISTER (3));
18848 else if (size
<= 4)
18849 regs_available_for_popping
=
18850 (1 << ARG_REGISTER (2))
18851 | (1 << ARG_REGISTER (3));
18852 else if (size
<= 8)
18853 regs_available_for_popping
=
18854 (1 << ARG_REGISTER (3));
18857 /* Match registers to be popped with registers into which we pop them. */
18858 for (available
= regs_available_for_popping
,
18859 required
= regs_to_pop
;
18860 required
!= 0 && available
!= 0;
18861 available
&= ~(available
& - available
),
18862 required
&= ~(required
& - required
))
18865 /* If we have any popping registers left over, remove them. */
18867 regs_available_for_popping
&= ~available
;
18869 /* Otherwise if we need another popping register we can use
18870 the fourth argument register. */
18871 else if (pops_needed
)
18873 /* If we have not found any free argument registers and
18874 reg a4 contains the return address, we must move it. */
18875 if (regs_available_for_popping
== 0
18876 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
18878 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
18879 reg_containing_return_addr
= LR_REGNUM
;
18881 else if (size
> 12)
18883 /* Register a4 is being used to hold part of the return value,
18884 but we have dire need of a free, low register. */
18887 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
18890 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
18892 /* The fourth argument register is available. */
18893 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
18899 /* Pop as many registers as we can. */
18900 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
18901 regs_available_for_popping
);
18903 /* Process the registers we popped. */
18904 if (reg_containing_return_addr
== -1)
18906 /* The return address was popped into the lowest numbered register. */
18907 regs_to_pop
&= ~(1 << LR_REGNUM
);
18909 reg_containing_return_addr
=
18910 number_of_first_bit_set (regs_available_for_popping
);
18912 /* Remove this register for the mask of available registers, so that
18913 the return address will not be corrupted by further pops. */
18914 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
18917 /* If we popped other registers then handle them here. */
18918 if (regs_available_for_popping
)
18922 /* Work out which register currently contains the frame pointer. */
18923 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
18925 /* Move it into the correct place. */
18926 asm_fprintf (f
, "\tmov\t%r, %r\n",
18927 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
18929 /* (Temporarily) remove it from the mask of popped registers. */
18930 regs_available_for_popping
&= ~(1 << frame_pointer
);
18931 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
18933 if (regs_available_for_popping
)
18937 /* We popped the stack pointer as well,
18938 find the register that contains it. */
18939 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
18941 /* Move it into the stack register. */
18942 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
18944 /* At this point we have popped all necessary registers, so
18945 do not worry about restoring regs_available_for_popping
18946 to its correct value:
18948 assert (pops_needed == 0)
18949 assert (regs_available_for_popping == (1 << frame_pointer))
18950 assert (regs_to_pop == (1 << STACK_POINTER)) */
18954 /* Since we have just move the popped value into the frame
18955 pointer, the popping register is available for reuse, and
18956 we know that we still have the stack pointer left to pop. */
18957 regs_available_for_popping
|= (1 << frame_pointer
);
18961 /* If we still have registers left on the stack, but we no longer have
18962 any registers into which we can pop them, then we must move the return
18963 address into the link register and make available the register that
18965 if (regs_available_for_popping
== 0 && pops_needed
> 0)
18967 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
18969 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
18970 reg_containing_return_addr
);
18972 reg_containing_return_addr
= LR_REGNUM
;
18975 /* If we have registers left on the stack then pop some more.
18976 We know that at most we will want to pop FP and SP. */
18977 if (pops_needed
> 0)
18982 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
18983 regs_available_for_popping
);
18985 /* We have popped either FP or SP.
18986 Move whichever one it is into the correct register. */
18987 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
18988 move_to
= number_of_first_bit_set (regs_to_pop
);
18990 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
18992 regs_to_pop
&= ~(1 << move_to
);
18997 /* If we still have not popped everything then we must have only
18998 had one register available to us and we are now popping the SP. */
18999 if (pops_needed
> 0)
19003 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
19004 regs_available_for_popping
);
19006 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
19008 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
19010 assert (regs_to_pop == (1 << STACK_POINTER))
19011 assert (pops_needed == 1)
19015 /* If necessary restore the a4 register. */
19018 if (reg_containing_return_addr
!= LR_REGNUM
)
19020 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
19021 reg_containing_return_addr
= LR_REGNUM
;
19024 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
19027 if (crtl
->calls_eh_return
)
19028 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
19030 /* Return to caller. */
19031 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
19036 thumb1_final_prescan_insn (rtx insn
)
19038 if (flag_print_asm_name
)
19039 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
19040 INSN_ADDRESSES (INSN_UID (insn
)));
19044 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
19046 unsigned HOST_WIDE_INT mask
= 0xff;
19049 val
= val
& (unsigned HOST_WIDE_INT
)0xffffffffu
;
19050 if (val
== 0) /* XXX */
19053 for (i
= 0; i
< 25; i
++)
19054 if ((val
& (mask
<< i
)) == val
)
19060 /* Returns nonzero if the current function contains,
19061 or might contain a far jump. */
19063 thumb_far_jump_used_p (void)
19067 /* This test is only important for leaf functions. */
19068 /* assert (!leaf_function_p ()); */
19070 /* If we have already decided that far jumps may be used,
19071 do not bother checking again, and always return true even if
19072 it turns out that they are not being used. Once we have made
19073 the decision that far jumps are present (and that hence the link
19074 register will be pushed onto the stack) we cannot go back on it. */
19075 if (cfun
->machine
->far_jump_used
)
19078 /* If this function is not being called from the prologue/epilogue
19079 generation code then it must be being called from the
19080 INITIAL_ELIMINATION_OFFSET macro. */
19081 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
19083 /* In this case we know that we are being asked about the elimination
19084 of the arg pointer register. If that register is not being used,
19085 then there are no arguments on the stack, and we do not have to
19086 worry that a far jump might force the prologue to push the link
19087 register, changing the stack offsets. In this case we can just
19088 return false, since the presence of far jumps in the function will
19089 not affect stack offsets.
19091 If the arg pointer is live (or if it was live, but has now been
19092 eliminated and so set to dead) then we do have to test to see if
19093 the function might contain a far jump. This test can lead to some
19094 false negatives, since before reload is completed, then length of
19095 branch instructions is not known, so gcc defaults to returning their
19096 longest length, which in turn sets the far jump attribute to true.
19098 A false negative will not result in bad code being generated, but it
19099 will result in a needless push and pop of the link register. We
19100 hope that this does not occur too often.
19102 If we need doubleword stack alignment this could affect the other
19103 elimination offsets so we can't risk getting it wrong. */
19104 if (df_regs_ever_live_p (ARG_POINTER_REGNUM
))
19105 cfun
->machine
->arg_pointer_live
= 1;
19106 else if (!cfun
->machine
->arg_pointer_live
)
19110 /* Check to see if the function contains a branch
19111 insn with the far jump attribute set. */
19112 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
19114 if (GET_CODE (insn
) == JUMP_INSN
19115 /* Ignore tablejump patterns. */
19116 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
19117 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
19118 && get_attr_far_jump (insn
) == FAR_JUMP_YES
19121 /* Record the fact that we have decided that
19122 the function does use far jumps. */
19123 cfun
->machine
->far_jump_used
= 1;
19131 /* Return nonzero if FUNC must be entered in ARM mode. */
19133 is_called_in_ARM_mode (tree func
)
19135 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
19137 /* Ignore the problem about functions whose address is taken. */
19138 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
19142 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
19148 /* The bits which aren't usefully expanded as rtl. */
19150 thumb_unexpanded_epilogue (void)
19152 arm_stack_offsets
*offsets
;
19154 unsigned long live_regs_mask
= 0;
19155 int high_regs_pushed
= 0;
19156 int had_to_push_lr
;
19159 if (cfun
->machine
->return_used_this_function
!= 0)
19162 if (IS_NAKED (arm_current_func_type ()))
19165 offsets
= arm_get_frame_offsets ();
19166 live_regs_mask
= offsets
->saved_regs_mask
;
19167 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
19169 /* If we can deduce the registers used from the function's return value.
19170 This is more reliable that examining df_regs_ever_live_p () because that
19171 will be set if the register is ever used in the function, not just if
19172 the register is used to hold a return value. */
19173 size
= arm_size_return_regs ();
19175 /* The prolog may have pushed some high registers to use as
19176 work registers. e.g. the testsuite file:
19177 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
19178 compiles to produce:
19179 push {r4, r5, r6, r7, lr}
19183 as part of the prolog. We have to undo that pushing here. */
19185 if (high_regs_pushed
)
19187 unsigned long mask
= live_regs_mask
& 0xff;
19190 /* The available low registers depend on the size of the value we are
19198 /* Oh dear! We have no low registers into which we can pop
19201 ("no low registers available for popping high registers");
19203 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
19204 if (live_regs_mask
& (1 << next_hi_reg
))
19207 while (high_regs_pushed
)
19209 /* Find lo register(s) into which the high register(s) can
19211 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
19213 if (mask
& (1 << regno
))
19214 high_regs_pushed
--;
19215 if (high_regs_pushed
== 0)
19219 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
19221 /* Pop the values into the low register(s). */
19222 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
19224 /* Move the value(s) into the high registers. */
19225 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
19227 if (mask
& (1 << regno
))
19229 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
19232 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
19233 if (live_regs_mask
& (1 << next_hi_reg
))
19238 live_regs_mask
&= ~0x0f00;
19241 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
19242 live_regs_mask
&= 0xff;
19244 if (crtl
->args
.pretend_args_size
== 0 || TARGET_BACKTRACE
)
19246 /* Pop the return address into the PC. */
19247 if (had_to_push_lr
)
19248 live_regs_mask
|= 1 << PC_REGNUM
;
19250 /* Either no argument registers were pushed or a backtrace
19251 structure was created which includes an adjusted stack
19252 pointer, so just pop everything. */
19253 if (live_regs_mask
)
19254 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
19257 /* We have either just popped the return address into the
19258 PC or it is was kept in LR for the entire function. */
19259 if (!had_to_push_lr
)
19260 thumb_exit (asm_out_file
, LR_REGNUM
);
19264 /* Pop everything but the return address. */
19265 if (live_regs_mask
)
19266 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
19269 if (had_to_push_lr
)
19273 /* We have no free low regs, so save one. */
19274 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
19278 /* Get the return address into a temporary register. */
19279 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
19280 1 << LAST_ARG_REGNUM
);
19284 /* Move the return address to lr. */
19285 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
19287 /* Restore the low register. */
19288 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
19293 regno
= LAST_ARG_REGNUM
;
19298 /* Remove the argument registers that were pushed onto the stack. */
19299 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
19300 SP_REGNUM
, SP_REGNUM
,
19301 crtl
->args
.pretend_args_size
);
19303 thumb_exit (asm_out_file
, regno
);
19309 /* Functions to save and restore machine-specific function data. */
19310 static struct machine_function
*
19311 arm_init_machine_status (void)
19313 struct machine_function
*machine
;
19314 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
19316 #if ARM_FT_UNKNOWN != 0
19317 machine
->func_type
= ARM_FT_UNKNOWN
;
19322 /* Return an RTX indicating where the return address to the
19323 calling function can be found. */
19325 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
19330 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
19333 /* Do anything needed before RTL is emitted for each function. */
19335 arm_init_expanders (void)
19337 /* Arrange to initialize and mark the machine per-function status. */
19338 init_machine_status
= arm_init_machine_status
;
19340 /* This is to stop the combine pass optimizing away the alignment
19341 adjustment of va_arg. */
19342 /* ??? It is claimed that this should not be necessary. */
19344 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
19348 /* Like arm_compute_initial_elimination offset. Simpler because there
19349 isn't an ABI specified frame pointer for Thumb. Instead, we set it
19350 to point at the base of the local variables after static stack
19351 space for a function has been allocated. */
19354 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
19356 arm_stack_offsets
*offsets
;
19358 offsets
= arm_get_frame_offsets ();
19362 case ARG_POINTER_REGNUM
:
19365 case STACK_POINTER_REGNUM
:
19366 return offsets
->outgoing_args
- offsets
->saved_args
;
19368 case FRAME_POINTER_REGNUM
:
19369 return offsets
->soft_frame
- offsets
->saved_args
;
19371 case ARM_HARD_FRAME_POINTER_REGNUM
:
19372 return offsets
->saved_regs
- offsets
->saved_args
;
19374 case THUMB_HARD_FRAME_POINTER_REGNUM
:
19375 return offsets
->locals_base
- offsets
->saved_args
;
19378 gcc_unreachable ();
19382 case FRAME_POINTER_REGNUM
:
19385 case STACK_POINTER_REGNUM
:
19386 return offsets
->outgoing_args
- offsets
->soft_frame
;
19388 case ARM_HARD_FRAME_POINTER_REGNUM
:
19389 return offsets
->saved_regs
- offsets
->soft_frame
;
19391 case THUMB_HARD_FRAME_POINTER_REGNUM
:
19392 return offsets
->locals_base
- offsets
->soft_frame
;
19395 gcc_unreachable ();
19400 gcc_unreachable ();
19404 /* Given the stack offsets and register mask in OFFSETS, decide
19405 how many additional registers to push instead of subtracting
19406 a constant from SP. */
19408 thumb1_extra_regs_pushed (arm_stack_offsets
*offsets
)
19410 HOST_WIDE_INT amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
19411 unsigned long live_regs_mask
= offsets
->saved_regs_mask
;
19412 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
19413 unsigned long l_mask
= live_regs_mask
& 0x40ff;
19414 /* Then count how many other high registers will need to be pushed. */
19415 unsigned long high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
19418 /* If the stack frame size is 512 exactly, we can save one load
19419 instruction, which should make this a win even when optimizing
19421 if (!optimize_size
&& amount
!= 512)
19424 /* Can't do this if there are high registers to push, or if we
19425 are not going to do a push at all. */
19426 if (high_regs_pushed
!= 0 || l_mask
== 0)
19429 /* Don't do this if thumb1_expand_prologue wants to emit instructions
19430 between the push and the stack frame allocation. */
19431 if ((flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
19432 || (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0))
19435 for (n_free
= 0; n_free
< 8 && !(live_regs_mask
& 1); live_regs_mask
>>= 1)
19440 gcc_assert (amount
/ 4 * 4 == amount
);
19442 if (amount
>= 512 && (amount
- n_free
* 4) < 512)
19443 return (amount
- 508) / 4;
19444 if (amount
<= n_free
* 4)
19449 /* Generate the rest of a function's prologue. */
19451 thumb1_expand_prologue (void)
19455 HOST_WIDE_INT amount
;
19456 arm_stack_offsets
*offsets
;
19457 unsigned long func_type
;
19459 unsigned long live_regs_mask
;
19461 func_type
= arm_current_func_type ();
19463 /* Naked functions don't have prologues. */
19464 if (IS_NAKED (func_type
))
19467 if (IS_INTERRUPT (func_type
))
19469 error ("interrupt Service Routines cannot be coded in Thumb mode");
19473 offsets
= arm_get_frame_offsets ();
19474 live_regs_mask
= offsets
->saved_regs_mask
;
19475 /* Load the pic register before setting the frame pointer,
19476 so we can use r7 as a temporary work register. */
19477 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
19478 arm_load_pic_register (live_regs_mask
);
19480 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
19481 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
19482 stack_pointer_rtx
);
19484 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
19485 amount
-= 4 * thumb1_extra_regs_pushed (offsets
);
19490 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
19491 GEN_INT (- amount
)));
19492 RTX_FRAME_RELATED_P (insn
) = 1;
19498 /* The stack decrement is too big for an immediate value in a single
19499 insn. In theory we could issue multiple subtracts, but after
19500 three of them it becomes more space efficient to place the full
19501 value in the constant pool and load into a register. (Also the
19502 ARM debugger really likes to see only one stack decrement per
19503 function). So instead we look for a scratch register into which
19504 we can load the decrement, and then we subtract this from the
19505 stack pointer. Unfortunately on the thumb the only available
19506 scratch registers are the argument registers, and we cannot use
19507 these as they may hold arguments to the function. Instead we
19508 attempt to locate a call preserved register which is used by this
19509 function. If we can find one, then we know that it will have
19510 been pushed at the start of the prologue and so we can corrupt
19512 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
19513 if (live_regs_mask
& (1 << regno
))
19516 gcc_assert(regno
<= LAST_LO_REGNUM
);
19518 reg
= gen_rtx_REG (SImode
, regno
);
19520 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
19522 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
19523 stack_pointer_rtx
, reg
));
19524 RTX_FRAME_RELATED_P (insn
) = 1;
19525 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
19526 plus_constant (stack_pointer_rtx
,
19528 RTX_FRAME_RELATED_P (dwarf
) = 1;
19529 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
19533 if (frame_pointer_needed
)
19534 thumb_set_frame_pointer (offsets
);
19536 /* If we are profiling, make sure no instructions are scheduled before
19537 the call to mcount. Similarly if the user has requested no
19538 scheduling in the prolog. Similarly if we want non-call exceptions
19539 using the EABI unwinder, to prevent faulting instructions from being
19540 swapped with a stack adjustment. */
19541 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
19542 || (ARM_EABI_UNWIND_TABLES
&& flag_non_call_exceptions
))
19543 emit_insn (gen_blockage ());
19545 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
19546 if (live_regs_mask
& 0xff)
19547 cfun
->machine
->lr_save_eliminated
= 0;
19552 thumb1_expand_epilogue (void)
19554 HOST_WIDE_INT amount
;
19555 arm_stack_offsets
*offsets
;
19558 /* Naked functions don't have prologues. */
19559 if (IS_NAKED (arm_current_func_type ()))
19562 offsets
= arm_get_frame_offsets ();
19563 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
19565 if (frame_pointer_needed
)
19567 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
19568 amount
= offsets
->locals_base
- offsets
->saved_regs
;
19571 gcc_assert (amount
>= 0);
19575 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
19576 GEN_INT (amount
)));
19579 /* r3 is always free in the epilogue. */
19580 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
19582 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
19583 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
19587 /* Emit a USE (stack_pointer_rtx), so that
19588 the stack adjustment will not be deleted. */
19589 emit_insn (gen_prologue_use (stack_pointer_rtx
));
19591 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
)
19592 emit_insn (gen_blockage ());
19594 /* Emit a clobber for each insn that will be restored in the epilogue,
19595 so that flow2 will get register lifetimes correct. */
19596 for (regno
= 0; regno
< 13; regno
++)
19597 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
19598 emit_clobber (gen_rtx_REG (SImode
, regno
));
19600 if (! df_regs_ever_live_p (LR_REGNUM
))
19601 emit_use (gen_rtx_REG (SImode
, LR_REGNUM
));
19605 thumb1_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
19607 arm_stack_offsets
*offsets
;
19608 unsigned long live_regs_mask
= 0;
19609 unsigned long l_mask
;
19610 unsigned high_regs_pushed
= 0;
19611 int cfa_offset
= 0;
19614 if (IS_NAKED (arm_current_func_type ()))
19617 if (is_called_in_ARM_mode (current_function_decl
))
19621 gcc_assert (GET_CODE (DECL_RTL (current_function_decl
)) == MEM
);
19622 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
19624 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
19626 /* Generate code sequence to switch us into Thumb mode. */
19627 /* The .code 32 directive has already been emitted by
19628 ASM_DECLARE_FUNCTION_NAME. */
19629 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
19630 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
19632 /* Generate a label, so that the debugger will notice the
19633 change in instruction sets. This label is also used by
19634 the assembler to bypass the ARM code when this function
19635 is called from a Thumb encoded function elsewhere in the
19636 same file. Hence the definition of STUB_NAME here must
19637 agree with the definition in gas/config/tc-arm.c. */
19639 #define STUB_NAME ".real_start_of"
19641 fprintf (f
, "\t.code\t16\n");
19643 if (arm_dllexport_name_p (name
))
19644 name
= arm_strip_name_encoding (name
);
19646 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
19647 fprintf (f
, "\t.thumb_func\n");
19648 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
19651 if (crtl
->args
.pretend_args_size
)
19653 /* Output unwind directive for the stack adjustment. */
19654 if (ARM_EABI_UNWIND_TABLES
)
19655 fprintf (f
, "\t.pad #%d\n",
19656 crtl
->args
.pretend_args_size
);
19658 if (cfun
->machine
->uses_anonymous_args
)
19662 fprintf (f
, "\tpush\t{");
19664 num_pushes
= ARM_NUM_INTS (crtl
->args
.pretend_args_size
);
19666 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
19667 regno
<= LAST_ARG_REGNUM
;
19669 asm_fprintf (f
, "%r%s", regno
,
19670 regno
== LAST_ARG_REGNUM
? "" : ", ");
19672 fprintf (f
, "}\n");
19675 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
19676 SP_REGNUM
, SP_REGNUM
,
19677 crtl
->args
.pretend_args_size
);
19679 /* We don't need to record the stores for unwinding (would it
19680 help the debugger any if we did?), but record the change in
19681 the stack pointer. */
19682 if (dwarf2out_do_frame ())
19684 char *l
= dwarf2out_cfi_label (false);
19686 cfa_offset
= cfa_offset
+ crtl
->args
.pretend_args_size
;
19687 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
19691 /* Get the registers we are going to push. */
19692 offsets
= arm_get_frame_offsets ();
19693 live_regs_mask
= offsets
->saved_regs_mask
;
19694 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
19695 l_mask
= live_regs_mask
& 0x40ff;
19696 /* Then count how many other high registers will need to be pushed. */
19697 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
19699 if (TARGET_BACKTRACE
)
19702 unsigned work_register
;
19704 /* We have been asked to create a stack backtrace structure.
19705 The code looks like this:
19709 0 sub SP, #16 Reserve space for 4 registers.
19710 2 push {R7} Push low registers.
19711 4 add R7, SP, #20 Get the stack pointer before the push.
19712 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
19713 8 mov R7, PC Get hold of the start of this code plus 12.
19714 10 str R7, [SP, #16] Store it.
19715 12 mov R7, FP Get hold of the current frame pointer.
19716 14 str R7, [SP, #4] Store it.
19717 16 mov R7, LR Get hold of the current return address.
19718 18 str R7, [SP, #12] Store it.
19719 20 add R7, SP, #16 Point at the start of the backtrace structure.
19720 22 mov FP, R7 Put this value into the frame pointer. */
19722 work_register
= thumb_find_work_register (live_regs_mask
);
19724 if (ARM_EABI_UNWIND_TABLES
)
19725 asm_fprintf (f
, "\t.pad #16\n");
19728 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
19729 SP_REGNUM
, SP_REGNUM
);
19731 if (dwarf2out_do_frame ())
19733 char *l
= dwarf2out_cfi_label (false);
19735 cfa_offset
= cfa_offset
+ 16;
19736 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
19741 thumb_pushpop (f
, l_mask
, 1, &cfa_offset
, l_mask
);
19742 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
19747 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
19748 offset
+ 16 + crtl
->args
.pretend_args_size
);
19750 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
19753 /* Make sure that the instruction fetching the PC is in the right place
19754 to calculate "start of backtrace creation code + 12". */
19757 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
19758 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
19760 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
19761 ARM_HARD_FRAME_POINTER_REGNUM
);
19762 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
19767 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
19768 ARM_HARD_FRAME_POINTER_REGNUM
);
19769 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
19771 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
19772 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
19776 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
19777 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
19779 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
19781 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
19782 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
19784 /* Optimization: If we are not pushing any low registers but we are going
19785 to push some high registers then delay our first push. This will just
19786 be a push of LR and we can combine it with the push of the first high
19788 else if ((l_mask
& 0xff) != 0
19789 || (high_regs_pushed
== 0 && l_mask
))
19791 unsigned long mask
= l_mask
;
19792 mask
|= (1 << thumb1_extra_regs_pushed (offsets
)) - 1;
19793 thumb_pushpop (f
, mask
, 1, &cfa_offset
, mask
);
19796 if (high_regs_pushed
)
19798 unsigned pushable_regs
;
19799 unsigned next_hi_reg
;
19801 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
19802 if (live_regs_mask
& (1 << next_hi_reg
))
19805 pushable_regs
= l_mask
& 0xff;
19807 if (pushable_regs
== 0)
19808 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
19810 while (high_regs_pushed
> 0)
19812 unsigned long real_regs_mask
= 0;
19814 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
19816 if (pushable_regs
& (1 << regno
))
19818 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
19820 high_regs_pushed
--;
19821 real_regs_mask
|= (1 << next_hi_reg
);
19823 if (high_regs_pushed
)
19825 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
19827 if (live_regs_mask
& (1 << next_hi_reg
))
19832 pushable_regs
&= ~((1 << regno
) - 1);
19838 /* If we had to find a work register and we have not yet
19839 saved the LR then add it to the list of regs to push. */
19840 if (l_mask
== (1 << LR_REGNUM
))
19842 thumb_pushpop (f
, pushable_regs
| (1 << LR_REGNUM
),
19844 real_regs_mask
| (1 << LR_REGNUM
));
19848 thumb_pushpop (f
, pushable_regs
, 1, &cfa_offset
, real_regs_mask
);
19853 /* Handle the case of a double word load into a low register from
19854 a computed memory address. The computed address may involve a
19855 register which is overwritten by the load. */
19857 thumb_load_double_from_address (rtx
*operands
)
19865 gcc_assert (GET_CODE (operands
[0]) == REG
);
19866 gcc_assert (GET_CODE (operands
[1]) == MEM
);
19868 /* Get the memory address. */
19869 addr
= XEXP (operands
[1], 0);
19871 /* Work out how the memory address is computed. */
19872 switch (GET_CODE (addr
))
19875 operands
[2] = adjust_address (operands
[1], SImode
, 4);
19877 if (REGNO (operands
[0]) == REGNO (addr
))
19879 output_asm_insn ("ldr\t%H0, %2", operands
);
19880 output_asm_insn ("ldr\t%0, %1", operands
);
19884 output_asm_insn ("ldr\t%0, %1", operands
);
19885 output_asm_insn ("ldr\t%H0, %2", operands
);
19890 /* Compute <address> + 4 for the high order load. */
19891 operands
[2] = adjust_address (operands
[1], SImode
, 4);
19893 output_asm_insn ("ldr\t%0, %1", operands
);
19894 output_asm_insn ("ldr\t%H0, %2", operands
);
19898 arg1
= XEXP (addr
, 0);
19899 arg2
= XEXP (addr
, 1);
19901 if (CONSTANT_P (arg1
))
19902 base
= arg2
, offset
= arg1
;
19904 base
= arg1
, offset
= arg2
;
19906 gcc_assert (GET_CODE (base
) == REG
);
19908 /* Catch the case of <address> = <reg> + <reg> */
19909 if (GET_CODE (offset
) == REG
)
19911 int reg_offset
= REGNO (offset
);
19912 int reg_base
= REGNO (base
);
19913 int reg_dest
= REGNO (operands
[0]);
19915 /* Add the base and offset registers together into the
19916 higher destination register. */
19917 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
19918 reg_dest
+ 1, reg_base
, reg_offset
);
19920 /* Load the lower destination register from the address in
19921 the higher destination register. */
19922 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
19923 reg_dest
, reg_dest
+ 1);
19925 /* Load the higher destination register from its own address
19927 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
19928 reg_dest
+ 1, reg_dest
+ 1);
19932 /* Compute <address> + 4 for the high order load. */
19933 operands
[2] = adjust_address (operands
[1], SImode
, 4);
19935 /* If the computed address is held in the low order register
19936 then load the high order register first, otherwise always
19937 load the low order register first. */
19938 if (REGNO (operands
[0]) == REGNO (base
))
19940 output_asm_insn ("ldr\t%H0, %2", operands
);
19941 output_asm_insn ("ldr\t%0, %1", operands
);
19945 output_asm_insn ("ldr\t%0, %1", operands
);
19946 output_asm_insn ("ldr\t%H0, %2", operands
);
19952 /* With no registers to worry about we can just load the value
19954 operands
[2] = adjust_address (operands
[1], SImode
, 4);
19956 output_asm_insn ("ldr\t%H0, %2", operands
);
19957 output_asm_insn ("ldr\t%0, %1", operands
);
19961 gcc_unreachable ();
19968 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
19975 if (REGNO (operands
[4]) > REGNO (operands
[5]))
19978 operands
[4] = operands
[5];
19981 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
19982 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
19986 if (REGNO (operands
[4]) > REGNO (operands
[5]))
19989 operands
[4] = operands
[5];
19992 if (REGNO (operands
[5]) > REGNO (operands
[6]))
19995 operands
[5] = operands
[6];
19998 if (REGNO (operands
[4]) > REGNO (operands
[5]))
20001 operands
[4] = operands
[5];
20005 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
20006 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
20010 gcc_unreachable ();
20016 /* Output a call-via instruction for thumb state. */
20018 thumb_call_via_reg (rtx reg
)
20020 int regno
= REGNO (reg
);
20023 gcc_assert (regno
< LR_REGNUM
);
20025 /* If we are in the normal text section we can use a single instance
20026 per compilation unit. If we are doing function sections, then we need
20027 an entry per section, since we can't rely on reachability. */
20028 if (in_section
== text_section
)
20030 thumb_call_reg_needed
= 1;
20032 if (thumb_call_via_label
[regno
] == NULL
)
20033 thumb_call_via_label
[regno
] = gen_label_rtx ();
20034 labelp
= thumb_call_via_label
+ regno
;
20038 if (cfun
->machine
->call_via
[regno
] == NULL
)
20039 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
20040 labelp
= cfun
->machine
->call_via
+ regno
;
20043 output_asm_insn ("bl\t%a0", labelp
);
20047 /* Routines for generating rtl. */
20049 thumb_expand_movmemqi (rtx
*operands
)
20051 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
20052 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
20053 HOST_WIDE_INT len
= INTVAL (operands
[2]);
20054 HOST_WIDE_INT offset
= 0;
20058 emit_insn (gen_movmem12b (out
, in
, out
, in
));
20064 emit_insn (gen_movmem8b (out
, in
, out
, in
));
20070 rtx reg
= gen_reg_rtx (SImode
);
20071 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
20072 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
20079 rtx reg
= gen_reg_rtx (HImode
);
20080 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
20081 plus_constant (in
, offset
))));
20082 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
20090 rtx reg
= gen_reg_rtx (QImode
);
20091 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
20092 plus_constant (in
, offset
))));
20093 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
20099 thumb_reload_out_hi (rtx
*operands
)
20101 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
20104 /* Handle reading a half-word from memory during reload. */
20106 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
20108 gcc_unreachable ();
20111 /* Return the length of a function name prefix
20112 that starts with the character 'c'. */
20114 arm_get_strip_length (int c
)
20118 ARM_NAME_ENCODING_LENGTHS
20123 /* Return a pointer to a function's name with any
20124 and all prefix encodings stripped from it. */
20126 arm_strip_name_encoding (const char *name
)
20130 while ((skip
= arm_get_strip_length (* name
)))
20136 /* If there is a '*' anywhere in the name's prefix, then
20137 emit the stripped name verbatim, otherwise prepend an
20138 underscore if leading underscores are being used. */
20140 arm_asm_output_labelref (FILE *stream
, const char *name
)
20145 while ((skip
= arm_get_strip_length (* name
)))
20147 verbatim
|= (*name
== '*');
20152 fputs (name
, stream
);
20154 asm_fprintf (stream
, "%U%s", name
);
20158 arm_file_start (void)
20162 if (TARGET_UNIFIED_ASM
)
20163 asm_fprintf (asm_out_file
, "\t.syntax unified\n");
20167 const char *fpu_name
;
20168 if (arm_select
[0].string
)
20169 asm_fprintf (asm_out_file
, "\t.cpu %s\n", arm_select
[0].string
);
20170 else if (arm_select
[1].string
)
20171 asm_fprintf (asm_out_file
, "\t.arch %s\n", arm_select
[1].string
);
20173 asm_fprintf (asm_out_file
, "\t.cpu %s\n",
20174 all_cores
[arm_default_cpu
].name
);
20176 if (TARGET_SOFT_FLOAT
)
20179 fpu_name
= "softvfp";
20181 fpu_name
= "softfpa";
20185 fpu_name
= arm_fpu_desc
->name
;
20186 if (arm_fpu_desc
->model
== ARM_FP_MODEL_VFP
)
20188 if (TARGET_HARD_FLOAT
)
20189 asm_fprintf (asm_out_file
, "\t.eabi_attribute 27, 3\n");
20190 if (TARGET_HARD_FLOAT_ABI
)
20191 asm_fprintf (asm_out_file
, "\t.eabi_attribute 28, 1\n");
20194 asm_fprintf (asm_out_file
, "\t.fpu %s\n", fpu_name
);
20196 /* Some of these attributes only apply when the corresponding features
20197 are used. However we don't have any easy way of figuring this out.
20198 Conservatively record the setting that would have been used. */
20200 /* Tag_ABI_FP_rounding. */
20201 if (flag_rounding_math
)
20202 asm_fprintf (asm_out_file
, "\t.eabi_attribute 19, 1\n");
20203 if (!flag_unsafe_math_optimizations
)
20205 /* Tag_ABI_FP_denomal. */
20206 asm_fprintf (asm_out_file
, "\t.eabi_attribute 20, 1\n");
20207 /* Tag_ABI_FP_exceptions. */
20208 asm_fprintf (asm_out_file
, "\t.eabi_attribute 21, 1\n");
20210 /* Tag_ABI_FP_user_exceptions. */
20211 if (flag_signaling_nans
)
20212 asm_fprintf (asm_out_file
, "\t.eabi_attribute 22, 1\n");
20213 /* Tag_ABI_FP_number_model. */
20214 asm_fprintf (asm_out_file
, "\t.eabi_attribute 23, %d\n",
20215 flag_finite_math_only
? 1 : 3);
20217 /* Tag_ABI_align8_needed. */
20218 asm_fprintf (asm_out_file
, "\t.eabi_attribute 24, 1\n");
20219 /* Tag_ABI_align8_preserved. */
20220 asm_fprintf (asm_out_file
, "\t.eabi_attribute 25, 1\n");
20221 /* Tag_ABI_enum_size. */
20222 asm_fprintf (asm_out_file
, "\t.eabi_attribute 26, %d\n",
20223 flag_short_enums
? 1 : 2);
20225 /* Tag_ABI_optimization_goals. */
20228 else if (optimize
>= 2)
20234 asm_fprintf (asm_out_file
, "\t.eabi_attribute 30, %d\n", val
);
20236 /* Tag_ABI_FP_16bit_format. */
20237 if (arm_fp16_format
)
20238 asm_fprintf (asm_out_file
, "\t.eabi_attribute 38, %d\n",
20239 (int)arm_fp16_format
);
20241 if (arm_lang_output_object_attributes_hook
)
20242 arm_lang_output_object_attributes_hook();
20244 default_file_start();
20248 arm_file_end (void)
20252 if (NEED_INDICATE_EXEC_STACK
)
20253 /* Add .note.GNU-stack. */
20254 file_end_indicate_exec_stack ();
20256 if (! thumb_call_reg_needed
)
20259 switch_to_section (text_section
);
20260 asm_fprintf (asm_out_file
, "\t.code 16\n");
20261 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
20263 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
20265 rtx label
= thumb_call_via_label
[regno
];
20269 targetm
.asm_out
.internal_label (asm_out_file
, "L",
20270 CODE_LABEL_NUMBER (label
));
20271 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
20277 /* Symbols in the text segment can be accessed without indirecting via the
20278 constant pool; it may take an extra binary operation, but this is still
20279 faster than indirecting via memory. Don't do this when not optimizing,
20280 since we won't be calculating al of the offsets necessary to do this
20284 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
20286 if (optimize
> 0 && TREE_CONSTANT (decl
))
20287 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
20289 default_encode_section_info (decl
, rtl
, first
);
20291 #endif /* !ARM_PE */
20294 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
20296 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
20297 && !strcmp (prefix
, "L"))
20299 arm_ccfsm_state
= 0;
20300 arm_target_insn
= NULL
;
20302 default_internal_label (stream
, prefix
, labelno
);
20305 /* Output code to add DELTA to the first argument, and then jump
20306 to FUNCTION. Used for C++ multiple inheritance. */
20308 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
20309 HOST_WIDE_INT delta
,
20310 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
20313 static int thunk_label
= 0;
20316 int mi_delta
= delta
;
20317 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
20319 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
20322 mi_delta
= - mi_delta
;
20326 int labelno
= thunk_label
++;
20327 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
20328 /* Thunks are entered in arm mode when avaiable. */
20329 if (TARGET_THUMB1_ONLY
)
20331 /* push r3 so we can use it as a temporary. */
20332 /* TODO: Omit this save if r3 is not used. */
20333 fputs ("\tpush {r3}\n", file
);
20334 fputs ("\tldr\tr3, ", file
);
20338 fputs ("\tldr\tr12, ", file
);
20340 assemble_name (file
, label
);
20341 fputc ('\n', file
);
20344 /* If we are generating PIC, the ldr instruction below loads
20345 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
20346 the address of the add + 8, so we have:
20348 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
20351 Note that we have "+ 1" because some versions of GNU ld
20352 don't set the low bit of the result for R_ARM_REL32
20353 relocations against thumb function symbols.
20354 On ARMv6M this is +4, not +8. */
20355 ASM_GENERATE_INTERNAL_LABEL (labelpc
, "LTHUNKPC", labelno
);
20356 assemble_name (file
, labelpc
);
20357 fputs (":\n", file
);
20358 if (TARGET_THUMB1_ONLY
)
20360 /* This is 2 insns after the start of the thunk, so we know it
20361 is 4-byte aligned. */
20362 fputs ("\tadd\tr3, pc, r3\n", file
);
20363 fputs ("\tmov r12, r3\n", file
);
20366 fputs ("\tadd\tr12, pc, r12\n", file
);
20368 else if (TARGET_THUMB1_ONLY
)
20369 fputs ("\tmov r12, r3\n", file
);
20371 if (TARGET_THUMB1_ONLY
)
20373 if (mi_delta
> 255)
20375 fputs ("\tldr\tr3, ", file
);
20376 assemble_name (file
, label
);
20377 fputs ("+4\n", file
);
20378 asm_fprintf (file
, "\t%s\t%r, %r, r3\n",
20379 mi_op
, this_regno
, this_regno
);
20381 else if (mi_delta
!= 0)
20383 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
20384 mi_op
, this_regno
, this_regno
,
20390 /* TODO: Use movw/movt for large constants when available. */
20391 while (mi_delta
!= 0)
20393 if ((mi_delta
& (3 << shift
)) == 0)
20397 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
20398 mi_op
, this_regno
, this_regno
,
20399 mi_delta
& (0xff << shift
));
20400 mi_delta
&= ~(0xff << shift
);
20407 if (TARGET_THUMB1_ONLY
)
20408 fputs ("\tpop\t{r3}\n", file
);
20410 fprintf (file
, "\tbx\tr12\n");
20411 ASM_OUTPUT_ALIGN (file
, 2);
20412 assemble_name (file
, label
);
20413 fputs (":\n", file
);
20416 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
20417 rtx tem
= XEXP (DECL_RTL (function
), 0);
20418 tem
= gen_rtx_PLUS (GET_MODE (tem
), tem
, GEN_INT (-7));
20419 tem
= gen_rtx_MINUS (GET_MODE (tem
),
20421 gen_rtx_SYMBOL_REF (Pmode
,
20422 ggc_strdup (labelpc
)));
20423 assemble_integer (tem
, 4, BITS_PER_WORD
, 1);
20426 /* Output ".word .LTHUNKn". */
20427 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
20429 if (TARGET_THUMB1_ONLY
&& mi_delta
> 255)
20430 assemble_integer (GEN_INT(mi_delta
), 4, BITS_PER_WORD
, 1);
20434 fputs ("\tb\t", file
);
20435 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
20436 if (NEED_PLT_RELOC
)
20437 fputs ("(PLT)", file
);
20438 fputc ('\n', file
);
20443 arm_emit_vector_const (FILE *file
, rtx x
)
20446 const char * pattern
;
20448 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
20450 switch (GET_MODE (x
))
20452 case V2SImode
: pattern
= "%08x"; break;
20453 case V4HImode
: pattern
= "%04x"; break;
20454 case V8QImode
: pattern
= "%02x"; break;
20455 default: gcc_unreachable ();
20458 fprintf (file
, "0x");
20459 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
20463 element
= CONST_VECTOR_ELT (x
, i
);
20464 fprintf (file
, pattern
, INTVAL (element
));
20470 /* Emit a fp16 constant appropriately padded to occupy a 4-byte word.
20471 HFmode constant pool entries are actually loaded with ldr. */
20473 arm_emit_fp16_const (rtx c
)
20478 REAL_VALUE_FROM_CONST_DOUBLE (r
, c
);
20479 bits
= real_to_target (NULL
, &r
, HFmode
);
20480 if (WORDS_BIG_ENDIAN
)
20481 assemble_zeros (2);
20482 assemble_integer (GEN_INT (bits
), 2, BITS_PER_WORD
, 1);
20483 if (!WORDS_BIG_ENDIAN
)
20484 assemble_zeros (2);
20488 arm_output_load_gr (rtx
*operands
)
20495 if (GET_CODE (operands
[1]) != MEM
20496 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
20497 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
20498 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
20499 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
20500 return "wldrw%?\t%0, %1";
20502 /* Fix up an out-of-range load of a GR register. */
20503 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
20504 wcgr
= operands
[0];
20506 output_asm_insn ("ldr%?\t%0, %1", operands
);
20508 operands
[0] = wcgr
;
20510 output_asm_insn ("tmcr%?\t%0, %1", operands
);
20511 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
20516 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
20518 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
20519 named arg and all anonymous args onto the stack.
20520 XXX I know the prologue shouldn't be pushing registers, but it is faster
20524 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
,
20525 enum machine_mode mode
,
20528 int second_time ATTRIBUTE_UNUSED
)
20532 cfun
->machine
->uses_anonymous_args
= 1;
20533 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
20535 nregs
= pcum
->aapcs_ncrn
;
20536 if ((nregs
& 1) && arm_needs_doubleword_align (mode
, type
))
20540 nregs
= pcum
->nregs
;
20542 if (nregs
< NUM_ARG_REGS
)
20543 *pretend_size
= (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
20546 /* Return nonzero if the CONSUMER instruction (a store) does not need
20547 PRODUCER's value to calculate the address. */
20550 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
20552 rtx value
= PATTERN (producer
);
20553 rtx addr
= PATTERN (consumer
);
20555 if (GET_CODE (value
) == COND_EXEC
)
20556 value
= COND_EXEC_CODE (value
);
20557 if (GET_CODE (value
) == PARALLEL
)
20558 value
= XVECEXP (value
, 0, 0);
20559 value
= XEXP (value
, 0);
20560 if (GET_CODE (addr
) == COND_EXEC
)
20561 addr
= COND_EXEC_CODE (addr
);
20562 if (GET_CODE (addr
) == PARALLEL
)
20563 addr
= XVECEXP (addr
, 0, 0);
20564 addr
= XEXP (addr
, 0);
20566 return !reg_overlap_mentioned_p (value
, addr
);
20569 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
20570 have an early register shift value or amount dependency on the
20571 result of PRODUCER. */
20574 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
20576 rtx value
= PATTERN (producer
);
20577 rtx op
= PATTERN (consumer
);
20580 if (GET_CODE (value
) == COND_EXEC
)
20581 value
= COND_EXEC_CODE (value
);
20582 if (GET_CODE (value
) == PARALLEL
)
20583 value
= XVECEXP (value
, 0, 0);
20584 value
= XEXP (value
, 0);
20585 if (GET_CODE (op
) == COND_EXEC
)
20586 op
= COND_EXEC_CODE (op
);
20587 if (GET_CODE (op
) == PARALLEL
)
20588 op
= XVECEXP (op
, 0, 0);
20591 early_op
= XEXP (op
, 0);
20592 /* This is either an actual independent shift, or a shift applied to
20593 the first operand of another operation. We want the whole shift
20595 if (GET_CODE (early_op
) == REG
)
20598 return !reg_overlap_mentioned_p (value
, early_op
);
20601 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
20602 have an early register shift value dependency on the result of
20606 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
20608 rtx value
= PATTERN (producer
);
20609 rtx op
= PATTERN (consumer
);
20612 if (GET_CODE (value
) == COND_EXEC
)
20613 value
= COND_EXEC_CODE (value
);
20614 if (GET_CODE (value
) == PARALLEL
)
20615 value
= XVECEXP (value
, 0, 0);
20616 value
= XEXP (value
, 0);
20617 if (GET_CODE (op
) == COND_EXEC
)
20618 op
= COND_EXEC_CODE (op
);
20619 if (GET_CODE (op
) == PARALLEL
)
20620 op
= XVECEXP (op
, 0, 0);
20623 early_op
= XEXP (op
, 0);
20625 /* This is either an actual independent shift, or a shift applied to
20626 the first operand of another operation. We want the value being
20627 shifted, in either case. */
20628 if (GET_CODE (early_op
) != REG
)
20629 early_op
= XEXP (early_op
, 0);
20631 return !reg_overlap_mentioned_p (value
, early_op
);
20634 /* Return nonzero if the CONSUMER (a mul or mac op) does not
20635 have an early register mult dependency on the result of
20639 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
20641 rtx value
= PATTERN (producer
);
20642 rtx op
= PATTERN (consumer
);
20644 if (GET_CODE (value
) == COND_EXEC
)
20645 value
= COND_EXEC_CODE (value
);
20646 if (GET_CODE (value
) == PARALLEL
)
20647 value
= XVECEXP (value
, 0, 0);
20648 value
= XEXP (value
, 0);
20649 if (GET_CODE (op
) == COND_EXEC
)
20650 op
= COND_EXEC_CODE (op
);
20651 if (GET_CODE (op
) == PARALLEL
)
20652 op
= XVECEXP (op
, 0, 0);
20655 if (GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
20657 if (GET_CODE (XEXP (op
, 0)) == MULT
)
20658 return !reg_overlap_mentioned_p (value
, XEXP (op
, 0));
20660 return !reg_overlap_mentioned_p (value
, XEXP (op
, 1));
20666 /* We can't rely on the caller doing the proper promotion when
20667 using APCS or ATPCS. */
20670 arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED
)
20672 return !TARGET_AAPCS_BASED
;
20675 static enum machine_mode
20676 arm_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
20677 enum machine_mode mode
,
20678 int *punsignedp ATTRIBUTE_UNUSED
,
20679 const_tree fntype ATTRIBUTE_UNUSED
,
20680 int for_return ATTRIBUTE_UNUSED
)
20682 if (GET_MODE_CLASS (mode
) == MODE_INT
20683 && GET_MODE_SIZE (mode
) < 4)
20689 /* AAPCS based ABIs use short enums by default. */
20692 arm_default_short_enums (void)
20694 return TARGET_AAPCS_BASED
&& arm_abi
!= ARM_ABI_AAPCS_LINUX
;
20698 /* AAPCS requires that anonymous bitfields affect structure alignment. */
20701 arm_align_anon_bitfield (void)
20703 return TARGET_AAPCS_BASED
;
20707 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
20710 arm_cxx_guard_type (void)
20712 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
20715 /* Return non-zero if the consumer (a multiply-accumulate instruction)
20716 has an accumulator dependency on the result of the producer (a
20717 multiplication instruction) and no other dependency on that result. */
20719 arm_mac_accumulator_is_mul_result (rtx producer
, rtx consumer
)
20721 rtx mul
= PATTERN (producer
);
20722 rtx mac
= PATTERN (consumer
);
20724 rtx mac_op0
, mac_op1
, mac_acc
;
20726 if (GET_CODE (mul
) == COND_EXEC
)
20727 mul
= COND_EXEC_CODE (mul
);
20728 if (GET_CODE (mac
) == COND_EXEC
)
20729 mac
= COND_EXEC_CODE (mac
);
20731 /* Check that mul is of the form (set (...) (mult ...))
20732 and mla is of the form (set (...) (plus (mult ...) (...))). */
20733 if ((GET_CODE (mul
) != SET
|| GET_CODE (XEXP (mul
, 1)) != MULT
)
20734 || (GET_CODE (mac
) != SET
|| GET_CODE (XEXP (mac
, 1)) != PLUS
20735 || GET_CODE (XEXP (XEXP (mac
, 1), 0)) != MULT
))
20738 mul_result
= XEXP (mul
, 0);
20739 mac_op0
= XEXP (XEXP (XEXP (mac
, 1), 0), 0);
20740 mac_op1
= XEXP (XEXP (XEXP (mac
, 1), 0), 1);
20741 mac_acc
= XEXP (XEXP (mac
, 1), 1);
20743 return (reg_overlap_mentioned_p (mul_result
, mac_acc
)
20744 && !reg_overlap_mentioned_p (mul_result
, mac_op0
)
20745 && !reg_overlap_mentioned_p (mul_result
, mac_op1
));
20749 /* The EABI says test the least significant bit of a guard variable. */
20752 arm_cxx_guard_mask_bit (void)
20754 return TARGET_AAPCS_BASED
;
20758 /* The EABI specifies that all array cookies are 8 bytes long. */
20761 arm_get_cookie_size (tree type
)
20765 if (!TARGET_AAPCS_BASED
)
20766 return default_cxx_get_cookie_size (type
);
20768 size
= build_int_cst (sizetype
, 8);
20773 /* The EABI says that array cookies should also contain the element size. */
20776 arm_cookie_has_size (void)
20778 return TARGET_AAPCS_BASED
;
20782 /* The EABI says constructors and destructors should return a pointer to
20783 the object constructed/destroyed. */
20786 arm_cxx_cdtor_returns_this (void)
20788 return TARGET_AAPCS_BASED
;
20791 /* The EABI says that an inline function may never be the key
20795 arm_cxx_key_method_may_be_inline (void)
20797 return !TARGET_AAPCS_BASED
;
20801 arm_cxx_determine_class_data_visibility (tree decl
)
20803 if (!TARGET_AAPCS_BASED
20804 || !TARGET_DLLIMPORT_DECL_ATTRIBUTES
)
20807 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
20808 is exported. However, on systems without dynamic vague linkage,
20809 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
20810 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
20811 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
20813 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
20814 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
20818 arm_cxx_class_data_always_comdat (void)
20820 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
20821 vague linkage if the class has no key function. */
20822 return !TARGET_AAPCS_BASED
;
20826 /* The EABI says __aeabi_atexit should be used to register static
20830 arm_cxx_use_aeabi_atexit (void)
20832 return TARGET_AAPCS_BASED
;
20837 arm_set_return_address (rtx source
, rtx scratch
)
20839 arm_stack_offsets
*offsets
;
20840 HOST_WIDE_INT delta
;
20842 unsigned long saved_regs
;
20844 offsets
= arm_get_frame_offsets ();
20845 saved_regs
= offsets
->saved_regs_mask
;
20847 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
20848 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
20851 if (frame_pointer_needed
)
20852 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
20855 /* LR will be the first saved register. */
20856 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
20861 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
20862 GEN_INT (delta
& ~4095)));
20867 addr
= stack_pointer_rtx
;
20869 addr
= plus_constant (addr
, delta
);
20871 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
20877 thumb_set_return_address (rtx source
, rtx scratch
)
20879 arm_stack_offsets
*offsets
;
20880 HOST_WIDE_INT delta
;
20881 HOST_WIDE_INT limit
;
20884 unsigned long mask
;
20888 offsets
= arm_get_frame_offsets ();
20889 mask
= offsets
->saved_regs_mask
;
20890 if (mask
& (1 << LR_REGNUM
))
20893 /* Find the saved regs. */
20894 if (frame_pointer_needed
)
20896 delta
= offsets
->soft_frame
- offsets
->saved_args
;
20897 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
20903 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
20906 /* Allow for the stack frame. */
20907 if (TARGET_THUMB1
&& TARGET_BACKTRACE
)
20909 /* The link register is always the first saved register. */
20912 /* Construct the address. */
20913 addr
= gen_rtx_REG (SImode
, reg
);
20916 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
20917 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
20921 addr
= plus_constant (addr
, delta
);
20923 emit_move_insn (gen_frame_mem (Pmode
, addr
), source
);
20926 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
20929 /* Implements target hook vector_mode_supported_p. */
20931 arm_vector_mode_supported_p (enum machine_mode mode
)
20933 /* Neon also supports V2SImode, etc. listed in the clause below. */
20934 if (TARGET_NEON
&& (mode
== V2SFmode
|| mode
== V4SImode
|| mode
== V8HImode
20935 || mode
== V16QImode
|| mode
== V4SFmode
|| mode
== V2DImode
))
20938 if ((TARGET_NEON
|| TARGET_IWMMXT
)
20939 && ((mode
== V2SImode
)
20940 || (mode
== V4HImode
)
20941 || (mode
== V8QImode
)))
20947 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
20948 ARM insns and therefore guarantee that the shift count is modulo 256.
20949 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
20950 guarantee no particular behavior for out-of-range counts. */
20952 static unsigned HOST_WIDE_INT
20953 arm_shift_truncation_mask (enum machine_mode mode
)
20955 return mode
== SImode
? 255 : 0;
20959 /* Map internal gcc register numbers to DWARF2 register numbers. */
20962 arm_dbx_register_number (unsigned int regno
)
20967 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
20968 compatibility. The EABI defines them as registers 96-103. */
20969 if (IS_FPA_REGNUM (regno
))
20970 return (TARGET_AAPCS_BASED
? 96 : 16) + regno
- FIRST_FPA_REGNUM
;
20972 if (IS_VFP_REGNUM (regno
))
20974 /* See comment in arm_dwarf_register_span. */
20975 if (VFP_REGNO_OK_FOR_SINGLE (regno
))
20976 return 64 + regno
- FIRST_VFP_REGNUM
;
20978 return 256 + (regno
- FIRST_VFP_REGNUM
) / 2;
20981 if (IS_IWMMXT_GR_REGNUM (regno
))
20982 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
20984 if (IS_IWMMXT_REGNUM (regno
))
20985 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
20987 gcc_unreachable ();
20990 /* Dwarf models VFPv3 registers as 32 64-bit registers.
20991 GCC models tham as 64 32-bit registers, so we need to describe this to
20992 the DWARF generation code. Other registers can use the default. */
20994 arm_dwarf_register_span (rtx rtl
)
21001 regno
= REGNO (rtl
);
21002 if (!IS_VFP_REGNUM (regno
))
21005 /* XXX FIXME: The EABI defines two VFP register ranges:
21006 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent)
21008 The recommended encoding for S0-S31 is a DW_OP_bit_piece of the
21009 corresponding D register. Until GDB supports this, we shall use the
21010 legacy encodings. We also use these encodings for D0-D15 for
21011 compatibility with older debuggers. */
21012 if (VFP_REGNO_OK_FOR_SINGLE (regno
))
21015 nregs
= GET_MODE_SIZE (GET_MODE (rtl
)) / 8;
21016 p
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
21017 regno
= (regno
- FIRST_VFP_REGNUM
) / 2;
21018 for (i
= 0; i
< nregs
; i
++)
21019 XVECEXP (p
, 0, i
) = gen_rtx_REG (DImode
, 256 + regno
+ i
);
21024 #ifdef TARGET_UNWIND_INFO
21025 /* Emit unwind directives for a store-multiple instruction or stack pointer
21026 push during alignment.
21027 These should only ever be generated by the function prologue code, so
21028 expect them to have a particular form. */
21031 arm_unwind_emit_sequence (FILE * asm_out_file
, rtx p
)
21034 HOST_WIDE_INT offset
;
21035 HOST_WIDE_INT nregs
;
21041 e
= XVECEXP (p
, 0, 0);
21042 if (GET_CODE (e
) != SET
)
21045 /* First insn will adjust the stack pointer. */
21046 if (GET_CODE (e
) != SET
21047 || GET_CODE (XEXP (e
, 0)) != REG
21048 || REGNO (XEXP (e
, 0)) != SP_REGNUM
21049 || GET_CODE (XEXP (e
, 1)) != PLUS
)
21052 offset
= -INTVAL (XEXP (XEXP (e
, 1), 1));
21053 nregs
= XVECLEN (p
, 0) - 1;
21055 reg
= REGNO (XEXP (XVECEXP (p
, 0, 1), 1));
21058 /* The function prologue may also push pc, but not annotate it as it is
21059 never restored. We turn this into a stack pointer adjustment. */
21060 if (nregs
* 4 == offset
- 4)
21062 fprintf (asm_out_file
, "\t.pad #4\n");
21066 fprintf (asm_out_file
, "\t.save {");
21068 else if (IS_VFP_REGNUM (reg
))
21071 fprintf (asm_out_file
, "\t.vsave {");
21073 else if (reg
>= FIRST_FPA_REGNUM
&& reg
<= LAST_FPA_REGNUM
)
21075 /* FPA registers are done differently. */
21076 asm_fprintf (asm_out_file
, "\t.save %r, %wd\n", reg
, nregs
);
21080 /* Unknown register type. */
21083 /* If the stack increment doesn't match the size of the saved registers,
21084 something has gone horribly wrong. */
21085 if (offset
!= nregs
* reg_size
)
21090 /* The remaining insns will describe the stores. */
21091 for (i
= 1; i
<= nregs
; i
++)
21093 /* Expect (set (mem <addr>) (reg)).
21094 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
21095 e
= XVECEXP (p
, 0, i
);
21096 if (GET_CODE (e
) != SET
21097 || GET_CODE (XEXP (e
, 0)) != MEM
21098 || GET_CODE (XEXP (e
, 1)) != REG
)
21101 reg
= REGNO (XEXP (e
, 1));
21106 fprintf (asm_out_file
, ", ");
21107 /* We can't use %r for vfp because we need to use the
21108 double precision register names. */
21109 if (IS_VFP_REGNUM (reg
))
21110 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
21112 asm_fprintf (asm_out_file
, "%r", reg
);
21114 #ifdef ENABLE_CHECKING
21115 /* Check that the addresses are consecutive. */
21116 e
= XEXP (XEXP (e
, 0), 0);
21117 if (GET_CODE (e
) == PLUS
)
21119 offset
+= reg_size
;
21120 if (GET_CODE (XEXP (e
, 0)) != REG
21121 || REGNO (XEXP (e
, 0)) != SP_REGNUM
21122 || GET_CODE (XEXP (e
, 1)) != CONST_INT
21123 || offset
!= INTVAL (XEXP (e
, 1)))
21127 || GET_CODE (e
) != REG
21128 || REGNO (e
) != SP_REGNUM
)
21132 fprintf (asm_out_file
, "}\n");
21135 /* Emit unwind directives for a SET. */
21138 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
21146 switch (GET_CODE (e0
))
21149 /* Pushing a single register. */
21150 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
21151 || GET_CODE (XEXP (XEXP (e0
, 0), 0)) != REG
21152 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
21155 asm_fprintf (asm_out_file
, "\t.save ");
21156 if (IS_VFP_REGNUM (REGNO (e1
)))
21157 asm_fprintf(asm_out_file
, "{d%d}\n",
21158 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
21160 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
21164 if (REGNO (e0
) == SP_REGNUM
)
21166 /* A stack increment. */
21167 if (GET_CODE (e1
) != PLUS
21168 || GET_CODE (XEXP (e1
, 0)) != REG
21169 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
21170 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
21173 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
21174 -INTVAL (XEXP (e1
, 1)));
21176 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
21178 HOST_WIDE_INT offset
;
21180 if (GET_CODE (e1
) == PLUS
)
21182 if (GET_CODE (XEXP (e1
, 0)) != REG
21183 || GET_CODE (XEXP (e1
, 1)) != CONST_INT
)
21185 reg
= REGNO (XEXP (e1
, 0));
21186 offset
= INTVAL (XEXP (e1
, 1));
21187 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
21188 HARD_FRAME_POINTER_REGNUM
, reg
,
21191 else if (GET_CODE (e1
) == REG
)
21194 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
21195 HARD_FRAME_POINTER_REGNUM
, reg
);
21200 else if (GET_CODE (e1
) == REG
&& REGNO (e1
) == SP_REGNUM
)
21202 /* Move from sp to reg. */
21203 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
21205 else if (GET_CODE (e1
) == PLUS
21206 && GET_CODE (XEXP (e1
, 0)) == REG
21207 && REGNO (XEXP (e1
, 0)) == SP_REGNUM
21208 && GET_CODE (XEXP (e1
, 1)) == CONST_INT
)
21210 /* Set reg to offset from sp. */
21211 asm_fprintf (asm_out_file
, "\t.movsp %r, #%d\n",
21212 REGNO (e0
), (int)INTVAL(XEXP (e1
, 1)));
21214 else if (GET_CODE (e1
) == UNSPEC
&& XINT (e1
, 1) == UNSPEC_STACK_ALIGN
)
21216 /* Stack pointer save before alignment. */
21218 asm_fprintf (asm_out_file
, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
21231 /* Emit unwind directives for the given insn. */
21234 arm_unwind_emit (FILE * asm_out_file
, rtx insn
)
21238 if (!ARM_EABI_UNWIND_TABLES
)
21241 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
21242 && (TREE_NOTHROW (current_function_decl
)
21243 || crtl
->all_throwers_are_sibcalls
))
21246 if (GET_CODE (insn
) == NOTE
|| !RTX_FRAME_RELATED_P (insn
))
21249 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
21251 pat
= XEXP (pat
, 0);
21253 pat
= PATTERN (insn
);
21255 switch (GET_CODE (pat
))
21258 arm_unwind_emit_set (asm_out_file
, pat
);
21262 /* Store multiple. */
21263 arm_unwind_emit_sequence (asm_out_file
, pat
);
21272 /* Output a reference from a function exception table to the type_info
21273 object X. The EABI specifies that the symbol should be relocated by
21274 an R_ARM_TARGET2 relocation. */
21277 arm_output_ttype (rtx x
)
21279 fputs ("\t.word\t", asm_out_file
);
21280 output_addr_const (asm_out_file
, x
);
21281 /* Use special relocations for symbol references. */
21282 if (GET_CODE (x
) != CONST_INT
)
21283 fputs ("(TARGET2)", asm_out_file
);
21284 fputc ('\n', asm_out_file
);
21288 #endif /* TARGET_UNWIND_INFO */
21291 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
21292 stack alignment. */
21295 arm_dwarf_handle_frame_unspec (const char *label
, rtx pattern
, int index
)
21297 rtx unspec
= SET_SRC (pattern
);
21298 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
21302 case UNSPEC_STACK_ALIGN
:
21303 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
21304 put anything on the stack, so hopefully it won't matter.
21305 CFA = SP will be correct after alignment. */
21306 dwarf2out_reg_save_reg (label
, stack_pointer_rtx
,
21307 SET_DEST (pattern
));
21310 gcc_unreachable ();
21315 /* Output unwind directives for the start/end of a function. */
21318 arm_output_fn_unwind (FILE * f
, bool prologue
)
21320 if (!ARM_EABI_UNWIND_TABLES
)
21324 fputs ("\t.fnstart\n", f
);
21327 /* If this function will never be unwound, then mark it as such.
21328 The came condition is used in arm_unwind_emit to suppress
21329 the frame annotations. */
21330 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
21331 && (TREE_NOTHROW (current_function_decl
)
21332 || crtl
->all_throwers_are_sibcalls
))
21333 fputs("\t.cantunwind\n", f
);
21335 fputs ("\t.fnend\n", f
);
21340 arm_emit_tls_decoration (FILE *fp
, rtx x
)
21342 enum tls_reloc reloc
;
21345 val
= XVECEXP (x
, 0, 0);
21346 reloc
= (enum tls_reloc
) INTVAL (XVECEXP (x
, 0, 1));
21348 output_addr_const (fp
, val
);
21353 fputs ("(tlsgd)", fp
);
21356 fputs ("(tlsldm)", fp
);
21359 fputs ("(tlsldo)", fp
);
21362 fputs ("(gottpoff)", fp
);
21365 fputs ("(tpoff)", fp
);
21368 gcc_unreachable ();
21376 fputs (" + (. - ", fp
);
21377 output_addr_const (fp
, XVECEXP (x
, 0, 2));
21379 output_addr_const (fp
, XVECEXP (x
, 0, 3));
21389 /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
21392 arm_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
21394 gcc_assert (size
== 4);
21395 fputs ("\t.word\t", file
);
21396 output_addr_const (file
, x
);
21397 fputs ("(tlsldo)", file
);
21401 arm_output_addr_const_extra (FILE *fp
, rtx x
)
21403 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
21404 return arm_emit_tls_decoration (fp
, x
);
21405 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
21408 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
21410 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
21411 assemble_name_raw (fp
, label
);
21415 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOTSYM_OFF
)
21417 assemble_name (fp
, "_GLOBAL_OFFSET_TABLE_");
21421 output_addr_const (fp
, XVECEXP (x
, 0, 0));
21425 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_SYMBOL_OFFSET
)
21427 output_addr_const (fp
, XVECEXP (x
, 0, 0));
21431 output_addr_const (fp
, XVECEXP (x
, 0, 1));
21435 else if (GET_CODE (x
) == CONST_VECTOR
)
21436 return arm_emit_vector_const (fp
, x
);
21441 /* Output assembly for a shift instruction.
21442 SET_FLAGS determines how the instruction modifies the condition codes.
21443 0 - Do not set condition codes.
21444 1 - Set condition codes.
21445 2 - Use smallest instruction. */
21447 arm_output_shift(rtx
* operands
, int set_flags
)
21450 static const char flag_chars
[3] = {'?', '.', '!'};
21455 c
= flag_chars
[set_flags
];
21456 if (TARGET_UNIFIED_ASM
)
21458 shift
= shift_op(operands
[3], &val
);
21462 operands
[2] = GEN_INT(val
);
21463 sprintf (pattern
, "%s%%%c\t%%0, %%1, %%2", shift
, c
);
21466 sprintf (pattern
, "mov%%%c\t%%0, %%1", c
);
21469 sprintf (pattern
, "mov%%%c\t%%0, %%1%%S3", c
);
21470 output_asm_insn (pattern
, operands
);
21474 /* Output a Thumb-1 casesi dispatch sequence. */
21476 thumb1_output_casesi (rtx
*operands
)
21478 rtx diff_vec
= PATTERN (next_real_insn (operands
[0]));
21480 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
21482 switch (GET_MODE(diff_vec
))
21485 return (ADDR_DIFF_VEC_FLAGS (diff_vec
).offset_unsigned
?
21486 "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi");
21488 return (ADDR_DIFF_VEC_FLAGS (diff_vec
).offset_unsigned
?
21489 "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi");
21491 return "bl\t%___gnu_thumb1_case_si";
21493 gcc_unreachable ();
21497 /* Output a Thumb-2 casesi instruction. */
21499 thumb2_output_casesi (rtx
*operands
)
21501 rtx diff_vec
= PATTERN (next_real_insn (operands
[2]));
21503 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
21505 output_asm_insn ("cmp\t%0, %1", operands
);
21506 output_asm_insn ("bhi\t%l3", operands
);
21507 switch (GET_MODE(diff_vec
))
21510 return "tbb\t[%|pc, %0]";
21512 return "tbh\t[%|pc, %0, lsl #1]";
21516 output_asm_insn ("adr\t%4, %l2", operands
);
21517 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands
);
21518 output_asm_insn ("add\t%4, %4, %5", operands
);
21523 output_asm_insn ("adr\t%4, %l2", operands
);
21524 return "ldr\t%|pc, [%4, %0, lsl #2]";
21527 gcc_unreachable ();
21531 /* Most ARM cores are single issue, but some newer ones can dual issue.
21532 The scheduler descriptions rely on this being correct. */
21534 arm_issue_rate (void)
21549 /* A table and a function to perform ARM-specific name mangling for
21550 NEON vector types in order to conform to the AAPCS (see "Procedure
21551 Call Standard for the ARM Architecture", Appendix A). To qualify
21552 for emission with the mangled names defined in that document, a
21553 vector type must not only be of the correct mode but also be
21554 composed of NEON vector element types (e.g. __builtin_neon_qi). */
21557 enum machine_mode mode
;
21558 const char *element_type_name
;
21559 const char *aapcs_name
;
21560 } arm_mangle_map_entry
;
21562 static arm_mangle_map_entry arm_mangle_map
[] = {
21563 /* 64-bit containerized types. */
21564 { V8QImode
, "__builtin_neon_qi", "15__simd64_int8_t" },
21565 { V8QImode
, "__builtin_neon_uqi", "16__simd64_uint8_t" },
21566 { V4HImode
, "__builtin_neon_hi", "16__simd64_int16_t" },
21567 { V4HImode
, "__builtin_neon_uhi", "17__simd64_uint16_t" },
21568 { V2SImode
, "__builtin_neon_si", "16__simd64_int32_t" },
21569 { V2SImode
, "__builtin_neon_usi", "17__simd64_uint32_t" },
21570 { V2SFmode
, "__builtin_neon_sf", "18__simd64_float32_t" },
21571 { V8QImode
, "__builtin_neon_poly8", "16__simd64_poly8_t" },
21572 { V4HImode
, "__builtin_neon_poly16", "17__simd64_poly16_t" },
21573 /* 128-bit containerized types. */
21574 { V16QImode
, "__builtin_neon_qi", "16__simd128_int8_t" },
21575 { V16QImode
, "__builtin_neon_uqi", "17__simd128_uint8_t" },
21576 { V8HImode
, "__builtin_neon_hi", "17__simd128_int16_t" },
21577 { V8HImode
, "__builtin_neon_uhi", "18__simd128_uint16_t" },
21578 { V4SImode
, "__builtin_neon_si", "17__simd128_int32_t" },
21579 { V4SImode
, "__builtin_neon_usi", "18__simd128_uint32_t" },
21580 { V4SFmode
, "__builtin_neon_sf", "19__simd128_float32_t" },
21581 { V16QImode
, "__builtin_neon_poly8", "17__simd128_poly8_t" },
21582 { V8HImode
, "__builtin_neon_poly16", "18__simd128_poly16_t" },
21583 { VOIDmode
, NULL
, NULL
}
21587 arm_mangle_type (const_tree type
)
21589 arm_mangle_map_entry
*pos
= arm_mangle_map
;
21591 /* The ARM ABI documents (10th October 2008) say that "__va_list"
21592 has to be managled as if it is in the "std" namespace. */
21593 if (TARGET_AAPCS_BASED
21594 && lang_hooks
.types_compatible_p (CONST_CAST_TREE (type
), va_list_type
))
21596 static bool warned
;
21597 if (!warned
&& warn_psabi
&& !in_system_header
)
21600 inform (input_location
,
21601 "the mangling of %<va_list%> has changed in GCC 4.4");
21603 return "St9__va_list";
21606 /* Half-precision float. */
21607 if (TREE_CODE (type
) == REAL_TYPE
&& TYPE_PRECISION (type
) == 16)
21610 if (TREE_CODE (type
) != VECTOR_TYPE
)
21613 /* Check the mode of the vector type, and the name of the vector
21614 element type, against the table. */
21615 while (pos
->mode
!= VOIDmode
)
21617 tree elt_type
= TREE_TYPE (type
);
21619 if (pos
->mode
== TYPE_MODE (type
)
21620 && TREE_CODE (TYPE_NAME (elt_type
)) == TYPE_DECL
21621 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type
))),
21622 pos
->element_type_name
))
21623 return pos
->aapcs_name
;
21628 /* Use the default mangling for unrecognized (possibly user-defined)
21633 /* Order of allocation of core registers for Thumb: this allocation is
21634 written over the corresponding initial entries of the array
21635 initialized with REG_ALLOC_ORDER. We allocate all low registers
21636 first. Saving and restoring a low register is usually cheaper than
21637 using a call-clobbered high register. */
21639 static const int thumb_core_reg_alloc_order
[] =
21641 3, 2, 1, 0, 4, 5, 6, 7,
21642 14, 12, 8, 9, 10, 11, 13, 15
21645 /* Adjust register allocation order when compiling for Thumb. */
21648 arm_order_regs_for_local_alloc (void)
21650 const int arm_reg_alloc_order
[] = REG_ALLOC_ORDER
;
21651 memcpy(reg_alloc_order
, arm_reg_alloc_order
, sizeof (reg_alloc_order
));
21653 memcpy (reg_alloc_order
, thumb_core_reg_alloc_order
,
21654 sizeof (thumb_core_reg_alloc_order
));
21657 /* Set default optimization options. */
21659 arm_optimization_options (int level
, int size ATTRIBUTE_UNUSED
)
21661 /* Enable section anchors by default at -O1 or higher.
21662 Use 2 to distinguish from an explicit -fsection-anchors
21663 given on the command line. */
21665 flag_section_anchors
= 2;
21668 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
21671 arm_frame_pointer_required (void)
21673 return (cfun
->has_nonlocal_label
21674 || SUBTARGET_FRAME_POINTER_REQUIRED
21675 || (TARGET_ARM
&& TARGET_APCS_FRAME
&& ! leaf_function_p ()));
21678 /* Only thumb1 can't support conditional execution, so return true if
21679 the target is not thumb1. */
21681 arm_have_conditional_execution (void)
21683 return !TARGET_THUMB1
;
21686 #include "gt-arm.h"