[AArch64] Enable VECT_COMPARE_COSTS by default for SVE
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / slp_6.c
blob44d128477d27afc4f944cb3b788b4e70f633feef
1 /* { dg-do compile } */
2 /* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
4 #include <stdint.h>
6 #define VEC_PERM(TYPE) \
7 void __attribute__ ((noinline, noclone)) \
8 vec_slp_##TYPE (TYPE *restrict a, TYPE *restrict b, int n) \
9 { \
10 TYPE x0 = b[0]; \
11 TYPE x1 = b[1]; \
12 TYPE x2 = b[2]; \
13 for (int i = 0; i < n; ++i) \
14 { \
15 x0 += a[i * 3]; \
16 x1 += a[i * 3 + 1]; \
17 x2 += a[i * 3 + 2]; \
18 } \
19 b[0] = x0; \
20 b[1] = x1; \
21 b[2] = x2; \
24 #define TEST_ALL(T) \
25 T (int8_t) \
26 T (uint8_t) \
27 T (int16_t) \
28 T (uint16_t) \
29 T (int32_t) \
30 T (uint32_t) \
31 T (int64_t) \
32 T (uint64_t) \
33 T (_Float16) \
34 T (float) \
35 T (double)
37 TEST_ALL (VEC_PERM)
39 /* These loops can't use SLP. */
40 /* { dg-final { scan-assembler-not {\tld1b\t} } } */
41 /* { dg-final { scan-assembler-not {\tld1h\t} } } */
42 /* { dg-final { scan-assembler-not {\tld1w\t} } } */
43 /* { dg-final { scan-assembler-not {\tld1d\t} } } */
44 /* { dg-final { scan-assembler {\tld3b\t} } } */
45 /* { dg-final { scan-assembler {\tld3h\t} } } */
46 /* { dg-final { scan-assembler {\tld3w\t} } } */
47 /* { dg-final { scan-assembler {\tld3d\t} } } */
49 /* { dg-final { scan-assembler-not {\tuqdec} } } */