1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
6 ;; Changes by Michael Meissner, meissner@osf.org
7 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 ;; Brendan Eich, brendan@microunity.com.
10 ;; This file is part of GCC.
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
33 (UNSPEC_EH_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
52 (UNSPEC_CLEAR_HAZARD 33)
56 (UNSPEC_COMPARE_AND_SWAP 37)
57 (UNSPEC_SYNC_OLD_OP 38)
58 (UNSPEC_SYNC_NEW_OP 39)
59 (UNSPEC_SYNC_EXCHANGE 40)
60 (UNSPEC_MEMORY_BARRIER 41)
62 (UNSPEC_ADDRESS_FIRST 100)
66 ;; For MIPS Paired-Singled Floating Point Instructions.
68 (UNSPEC_MOVE_TF_PS 200)
71 ;; MIPS64/MIPS32R2 alnv.ps
74 ;; MIPS-3D instructions
78 (UNSPEC_CVT_PW_PS 205)
79 (UNSPEC_CVT_PS_PW 206)
87 (UNSPEC_SINGLE_CC 213)
90 ;; MIPS DSP ASE Revision 0.98 3/24/2005
98 (UNSPEC_RADDU_W_QB 307)
100 (UNSPEC_PRECRQ_QB_PH 309)
101 (UNSPEC_PRECRQ_PH_W 310)
102 (UNSPEC_PRECRQ_RS_PH_W 311)
103 (UNSPEC_PRECRQU_S_QB_PH 312)
104 (UNSPEC_PRECEQ_W_PHL 313)
105 (UNSPEC_PRECEQ_W_PHR 314)
106 (UNSPEC_PRECEQU_PH_QBL 315)
107 (UNSPEC_PRECEQU_PH_QBR 316)
108 (UNSPEC_PRECEQU_PH_QBLA 317)
109 (UNSPEC_PRECEQU_PH_QBRA 318)
110 (UNSPEC_PRECEU_PH_QBL 319)
111 (UNSPEC_PRECEU_PH_QBR 320)
112 (UNSPEC_PRECEU_PH_QBLA 321)
113 (UNSPEC_PRECEU_PH_QBRA 322)
119 (UNSPEC_MULEU_S_PH_QBL 328)
120 (UNSPEC_MULEU_S_PH_QBR 329)
121 (UNSPEC_MULQ_RS_PH 330)
122 (UNSPEC_MULEQ_S_W_PHL 331)
123 (UNSPEC_MULEQ_S_W_PHR 332)
124 (UNSPEC_DPAU_H_QBL 333)
125 (UNSPEC_DPAU_H_QBR 334)
126 (UNSPEC_DPSU_H_QBL 335)
127 (UNSPEC_DPSU_H_QBR 336)
128 (UNSPEC_DPAQ_S_W_PH 337)
129 (UNSPEC_DPSQ_S_W_PH 338)
130 (UNSPEC_MULSAQ_S_W_PH 339)
131 (UNSPEC_DPAQ_SA_L_W 340)
132 (UNSPEC_DPSQ_SA_L_W 341)
133 (UNSPEC_MAQ_S_W_PHL 342)
134 (UNSPEC_MAQ_S_W_PHR 343)
135 (UNSPEC_MAQ_SA_W_PHL 344)
136 (UNSPEC_MAQ_SA_W_PHR 345)
144 (UNSPEC_CMPGU_EQ_QB 353)
145 (UNSPEC_CMPGU_LT_QB 354)
146 (UNSPEC_CMPGU_LE_QB 355)
148 (UNSPEC_PACKRL_PH 357)
150 (UNSPEC_EXTR_R_W 359)
151 (UNSPEC_EXTR_RS_W 360)
152 (UNSPEC_EXTR_S_H 361)
160 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
161 (UNSPEC_ABSQ_S_QB 400)
163 (UNSPEC_ADDU_S_PH 402)
164 (UNSPEC_ADDUH_QB 403)
165 (UNSPEC_ADDUH_R_QB 404)
168 (UNSPEC_CMPGDU_EQ_QB 407)
169 (UNSPEC_CMPGDU_LT_QB 408)
170 (UNSPEC_CMPGDU_LE_QB 409)
171 (UNSPEC_DPA_W_PH 410)
172 (UNSPEC_DPS_W_PH 411)
178 (UNSPEC_MUL_S_PH 417)
179 (UNSPEC_MULQ_RS_W 418)
180 (UNSPEC_MULQ_S_PH 419)
181 (UNSPEC_MULQ_S_W 420)
182 (UNSPEC_MULSA_W_PH 421)
185 (UNSPEC_PRECR_QB_PH 424)
186 (UNSPEC_PRECR_SRA_PH_W 425)
187 (UNSPEC_PRECR_SRA_R_PH_W 426)
190 (UNSPEC_SHRA_R_QB 429)
193 (UNSPEC_SUBU_S_PH 432)
194 (UNSPEC_SUBUH_QB 433)
195 (UNSPEC_SUBUH_R_QB 434)
196 (UNSPEC_ADDQH_PH 435)
197 (UNSPEC_ADDQH_R_PH 436)
199 (UNSPEC_ADDQH_R_W 438)
200 (UNSPEC_SUBQH_PH 439)
201 (UNSPEC_SUBQH_R_PH 440)
203 (UNSPEC_SUBQH_R_W 442)
204 (UNSPEC_DPAX_W_PH 443)
205 (UNSPEC_DPSX_W_PH 444)
206 (UNSPEC_DPAQX_S_W_PH 445)
207 (UNSPEC_DPAQX_SA_W_PH 446)
208 (UNSPEC_DPSQX_S_W_PH 447)
209 (UNSPEC_DPSQX_SA_W_PH 448)
213 (include "predicates.md")
214 (include "constraints.md")
216 ;; ....................
220 ;; ....................
222 (define_attr "got" "unset,xgot_high,load"
223 (const_string "unset"))
225 ;; For jal instructions, this attribute is DIRECT when the target address
226 ;; is symbolic and INDIRECT when it is a register.
227 (define_attr "jal" "unset,direct,indirect"
228 (const_string "unset"))
230 ;; This attribute is YES if the instruction is a jal macro (not a
231 ;; real jal instruction).
233 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
234 ;; an instruction to restore $gp. Direct jals are also macros for
235 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
236 ;; the target address into a register.
237 (define_attr "jal_macro" "no,yes"
238 (cond [(eq_attr "jal" "direct")
239 (symbol_ref "TARGET_CALL_CLOBBERED_GP
240 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
241 (eq_attr "jal" "indirect")
242 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
243 (const_string "no")))
245 ;; Classification of each insn.
246 ;; branch conditional branch
247 ;; jump unconditional jump
248 ;; call unconditional call
249 ;; load load instruction(s)
250 ;; fpload floating point load
251 ;; fpidxload floating point indexed load
252 ;; store store instruction(s)
253 ;; fpstore floating point store
254 ;; fpidxstore floating point indexed store
255 ;; prefetch memory prefetch (register + offset)
256 ;; prefetchx memory indexed prefetch (register + register)
257 ;; condmove conditional moves
258 ;; mfc transfer from coprocessor
259 ;; mtc transfer to coprocessor
260 ;; mthilo transfer to hi/lo registers
261 ;; mfhilo transfer from hi/lo registers
262 ;; const load constant
263 ;; arith integer arithmetic instructions
264 ;; logical integer logical instructions
265 ;; shift integer shift instructions
266 ;; slt set less than instructions
267 ;; signext sign extend instructions
268 ;; clz the clz and clo instructions
269 ;; trap trap if instructions
270 ;; imul integer multiply 2 operands
271 ;; imul3 integer multiply 3 operands
272 ;; imadd integer multiply-add
273 ;; idiv integer divide
274 ;; move integer register move ({,D}ADD{,U} with rt = 0)
275 ;; fmove floating point register move
276 ;; fadd floating point add/subtract
277 ;; fmul floating point multiply
278 ;; fmadd floating point multiply-add
279 ;; fdiv floating point divide
280 ;; frdiv floating point reciprocal divide
281 ;; frdiv1 floating point reciprocal divide step 1
282 ;; frdiv2 floating point reciprocal divide step 2
283 ;; fabs floating point absolute value
284 ;; fneg floating point negation
285 ;; fcmp floating point compare
286 ;; fcvt floating point convert
287 ;; fsqrt floating point square root
288 ;; frsqrt floating point reciprocal square root
289 ;; frsqrt1 floating point reciprocal square root step1
290 ;; frsqrt2 floating point reciprocal square root step2
291 ;; multi multiword sequence (or user asm statements)
294 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
295 (cond [(eq_attr "jal" "!unset") (const_string "call")
296 (eq_attr "got" "load") (const_string "load")]
297 (const_string "unknown")))
299 ;; Main data type used by the insn
300 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
301 (const_string "unknown"))
303 ;; Mode for conversion types (fcvt)
304 ;; I2S integer to float single (SI/DI to SF)
305 ;; I2D integer to float double (SI/DI to DF)
306 ;; S2I float to integer (SF to SI/DI)
307 ;; D2I float to integer (DF to SI/DI)
308 ;; D2S double to float single
309 ;; S2D float single to double
311 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
312 (const_string "unknown"))
314 ;; Is this an extended instruction in mips16 mode?
315 (define_attr "extended_mips16" "no,yes"
318 ;; Length of instruction in bytes.
319 (define_attr "length" ""
320 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
321 ;; If a branch is outside this range, we have a choice of two
322 ;; sequences. For PIC, an out-of-range branch like:
327 ;; becomes the equivalent of:
336 ;; where the load address can be up to three instructions long
339 ;; The non-PIC case is similar except that we use a direct
340 ;; jump instead of an la/jr pair. Since the target of this
341 ;; jump is an absolute 28-bit bit address (the other bits
342 ;; coming from the address of the delay slot) this form cannot
343 ;; cross a 256MB boundary. We could provide the option of
344 ;; using la/jr in this case too, but we do not do so at
347 ;; Note that this value does not account for the delay slot
348 ;; instruction, whose length is added separately. If the RTL
349 ;; pattern has no explicit delay slot, mips_adjust_insn_length
350 ;; will add the length of the implicit nop. The values for
351 ;; forward and backward branches will be different as well.
352 (eq_attr "type" "branch")
353 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
354 (le (minus (pc) (match_dup 1)) (const_int 131068)))
356 (ne (symbol_ref "flag_pic") (const_int 0))
360 (eq_attr "got" "load")
362 (eq_attr "got" "xgot_high")
365 (eq_attr "type" "const")
366 (symbol_ref "mips_const_insns (operands[1]) * 4")
367 (eq_attr "type" "load,fpload")
368 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
369 (eq_attr "type" "store,fpstore")
370 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
372 ;; In the worst case, a call macro will take 8 instructions:
374 ;; lui $25,%call_hi(FOO)
376 ;; lw $25,%call_lo(FOO)($25)
382 (eq_attr "jal_macro" "yes")
385 (and (eq_attr "extended_mips16" "yes")
386 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
389 ;; Various VR4120 errata require a nop to be inserted after a macc
390 ;; instruction. The assembler does this for us, so account for
391 ;; the worst-case length here.
392 (and (eq_attr "type" "imadd")
393 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
396 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
397 ;; the result of the second one is missed. The assembler should work
398 ;; around this by inserting a nop after the first dmult.
399 (and (eq_attr "type" "imul,imul3")
400 (and (eq_attr "mode" "DI")
401 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
404 (eq_attr "type" "idiv")
405 (symbol_ref "mips_idiv_insns () * 4")
408 ;; Attribute describing the processor. This attribute must match exactly
409 ;; with the processor_type enumeration in mips.h.
411 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
412 (const (symbol_ref "mips_tune")))
414 ;; The type of hardware hazard associated with this instruction.
415 ;; DELAY means that the next instruction cannot read the result
416 ;; of this one. HILO means that the next two instructions cannot
417 ;; write to HI or LO.
418 (define_attr "hazard" "none,delay,hilo"
419 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
420 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
421 (const_string "delay")
423 (and (eq_attr "type" "mfc,mtc")
424 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
425 (const_string "delay")
427 (and (eq_attr "type" "fcmp")
428 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
429 (const_string "delay")
431 ;; The r4000 multiplication patterns include an mflo instruction.
432 (and (eq_attr "type" "imul")
433 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
434 (const_string "hilo")
436 (and (eq_attr "type" "mfhilo")
437 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
438 (const_string "hilo")]
439 (const_string "none")))
441 ;; Indicates which SET in an instruction pattern induces a hazard.
442 ;; Only meaningful when "hazard" is not "none". SINGLE means that
443 ;; the pattern has only one set while the other values are indexes
444 ;; into a PARALLEL vector.
446 ;; Hazardous instructions with multiple sets should generally put the
447 ;; hazardous set first. The only purpose of this attribute is to force
448 ;; each multi-set pattern to explicitly assert that this condition holds.
449 (define_attr "hazard_set" "single,0"
450 (const_string "single"))
452 ;; Is it a single instruction?
453 (define_attr "single_insn" "no,yes"
454 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
456 ;; Can the instruction be put into a delay slot?
457 (define_attr "can_delay" "no,yes"
458 (if_then_else (and (eq_attr "type" "!branch,call,jump")
459 (and (eq_attr "hazard" "none")
460 (eq_attr "single_insn" "yes")))
462 (const_string "no")))
464 ;; Attribute defining whether or not we can use the branch-likely instructions
465 (define_attr "branch_likely" "no,yes"
467 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
469 (const_string "no"))))
471 ;; True if an instruction might assign to hi or lo when reloaded.
472 ;; This is used by the TUNE_MACC_CHAINS code.
473 (define_attr "may_clobber_hilo" "no,yes"
474 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
476 (const_string "no")))
478 ;; Describe a user's asm statement.
479 (define_asm_attributes
480 [(set_attr "type" "multi")
481 (set_attr "can_delay" "no")])
483 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
484 ;; from the same template.
485 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
487 ;; This mode iterator allows :P to be used for patterns that operate on
488 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
489 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
491 ;; This mode iterator allows :MOVECC to be used anywhere that a
492 ;; conditional-move-type condition is needed.
493 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
495 ;; 64-bit modes for which we provide move patterns.
496 (define_mode_iterator MOVE64
497 [DI DF (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
499 ;; This mode iterator allows the QI and HI extension patterns to be
500 ;; defined from the same template.
501 (define_mode_iterator SHORT [QI HI])
503 ;; Likewise the 64-bit truncate-and-shift patterns.
504 (define_mode_iterator SUBDI [QI HI SI])
506 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
507 ;; floating-point mode is allowed.
508 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
509 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
510 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
512 ;; Like ANYF, but only applies to scalar modes.
513 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
514 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
516 ;; A floating-point mode for which moves involving FPRs may need to be split.
517 (define_mode_iterator SPLITF
518 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
519 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
520 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
521 (TF "TARGET_64BIT && TARGET_FLOAT64")])
523 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
524 ;; 32-bit version and "dsubu" in the 64-bit version.
525 (define_mode_attr d [(SI "") (DI "d")
526 (QQ "") (HQ "") (SQ "") (DQ "d")
527 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
528 (HA "") (SA "") (DA "d")
529 (UHA "") (USA "") (UDA "d")])
531 ;; This attribute gives the length suffix for a sign- or zero-extension
533 (define_mode_attr size [(QI "b") (HI "h")])
535 ;; This attributes gives the mode mask of a SHORT.
536 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
538 ;; Mode attributes for GPR loads and stores.
539 (define_mode_attr load [(SI "lw") (DI "ld")])
540 (define_mode_attr store [(SI "sw") (DI "sd")])
542 ;; Similarly for MIPS IV indexed FPR loads and stores.
543 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
544 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
546 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
547 ;; are different. Some forms of unextended addiu have an 8-bit immediate
548 ;; field but the equivalent daddiu has only a 5-bit field.
549 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
551 ;; This attribute gives the best constraint to use for registers of
553 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
555 ;; This attribute gives the format suffix for floating-point operations.
556 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
558 ;; This attribute gives the upper-case mode name for one unit of a
559 ;; floating-point mode.
560 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
562 ;; This attribute gives the integer mode that has the same size as a
564 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
565 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
566 (HA "HI") (SA "SI") (DA "DI")
567 (UHA "HI") (USA "SI") (UDA "DI")
568 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
569 (V2HQ "SI") (V2HA "SI")])
571 ;; This attribute gives the integer mode that has half the size of
572 ;; the controlling mode.
573 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI") (TF "DI")])
575 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
577 ;; In certain cases, div.s and div.ps may have a rounding error
578 ;; and/or wrong inexact flag.
580 ;; Therefore, we only allow div.s if not working around SB-1 rev2
581 ;; errata or if a slight loss of precision is OK.
582 (define_mode_attr divide_condition
583 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
584 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
586 ; This attribute gives the condition for which sqrt instructions exist.
587 (define_mode_attr sqrt_condition
588 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
590 ; This attribute gives the condition for which recip and rsqrt instructions
592 (define_mode_attr recip_condition
593 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
595 ;; This code iterator allows all branch instructions to be generated from
596 ;; a single define_expand template.
597 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
598 eq ne gt ge lt le gtu geu ltu leu])
600 ;; This code iterator allows signed and unsigned widening multiplications
601 ;; to use the same template.
602 (define_code_iterator any_extend [sign_extend zero_extend])
604 ;; This code iterator allows the three shift instructions to be generated
605 ;; from the same template.
606 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
608 ;; This code iterator allows all native floating-point comparisons to be
609 ;; generated from the same template.
610 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
612 ;; This code iterator is used for comparisons that can be implemented
613 ;; by swapping the operands.
614 (define_code_iterator swapped_fcond [ge gt unge ungt])
616 ;; <u> expands to an empty string when doing a signed operation and
617 ;; "u" when doing an unsigned operation.
618 (define_code_attr u [(sign_extend "") (zero_extend "u")])
620 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
621 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
623 ;; <optab> expands to the name of the optab for a particular code.
624 (define_code_attr optab [(ashift "ashl")
631 ;; <insn> expands to the name of the insn that implements a particular code.
632 (define_code_attr insn [(ashift "sll")
639 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
640 (define_code_attr fcond [(unordered "un")
648 ;; Similar, but for swapped conditions.
649 (define_code_attr swapped_fcond [(ge "le")
654 ;; Atomic fetch bitwise operations.
655 (define_code_iterator fetchop_bit [ior xor and])
657 ;; <immediate_insn> expands to the name of the insn that implements
658 ;; a particular code to operate in immediate values.
659 (define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")])
662 ;; .........................
664 ;; Branch, call and jump delay slots
666 ;; .........................
668 (define_delay (and (eq_attr "type" "branch")
669 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
670 [(eq_attr "can_delay" "yes")
672 (and (eq_attr "branch_likely" "yes")
673 (eq_attr "can_delay" "yes"))])
675 (define_delay (eq_attr "type" "jump")
676 [(eq_attr "can_delay" "yes")
680 (define_delay (and (eq_attr "type" "call")
681 (eq_attr "jal_macro" "no"))
682 [(eq_attr "can_delay" "yes")
686 ;; Pipeline descriptions.
688 ;; generic.md provides a fallback for processors without a specific
689 ;; pipeline description. It is derived from the old define_function_unit
690 ;; version and uses the "alu" and "imuldiv" units declared below.
692 ;; Some of the processor-specific files are also derived from old
693 ;; define_function_unit descriptions and simply override the parts of
694 ;; generic.md that don't apply. The other processor-specific files
695 ;; are self-contained.
696 (define_automaton "alu,imuldiv")
698 (define_cpu_unit "alu" "alu")
699 (define_cpu_unit "imuldiv" "imuldiv")
720 (include "generic.md")
723 ;; ....................
727 ;; ....................
731 [(trap_if (const_int 1) (const_int 0))]
734 if (ISA_HAS_COND_TRAP)
736 else if (TARGET_MIPS16)
741 [(set_attr "type" "trap")])
743 (define_expand "conditional_trap"
744 [(trap_if (match_operator 0 "comparison_operator"
745 [(match_dup 2) (match_dup 3)])
746 (match_operand 1 "const_int_operand"))]
749 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
750 && operands[1] == const0_rtx)
752 mips_expand_conditional_trap (GET_CODE (operands[0]));
758 (define_insn "*conditional_trap<mode>"
759 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
760 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
761 (match_operand:GPR 2 "arith_operand" "dI")])
765 [(set_attr "type" "trap")])
768 ;; ....................
772 ;; ....................
775 (define_insn "add<mode>3"
776 [(set (match_operand:ANYF 0 "register_operand" "=f")
777 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
778 (match_operand:ANYF 2 "register_operand" "f")))]
780 "add.<fmt>\t%0,%1,%2"
781 [(set_attr "type" "fadd")
782 (set_attr "mode" "<UNITMODE>")])
784 (define_expand "add<mode>3"
785 [(set (match_operand:GPR 0 "register_operand")
786 (plus:GPR (match_operand:GPR 1 "register_operand")
787 (match_operand:GPR 2 "arith_operand")))]
790 (define_insn "*add<mode>3"
791 [(set (match_operand:GPR 0 "register_operand" "=d,d")
792 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
793 (match_operand:GPR 2 "arith_operand" "d,Q")))]
798 [(set_attr "type" "arith")
799 (set_attr "mode" "<MODE>")])
801 (define_insn "*add<mode>3_mips16"
802 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
803 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
804 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
812 [(set_attr "type" "arith")
813 (set_attr "mode" "<MODE>")
814 (set_attr_alternative "length"
815 [(if_then_else (match_operand 2 "m16_simm8_8")
818 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
821 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
824 (if_then_else (match_operand 2 "m16_simm4_1")
829 ;; On the mips16, we can sometimes split an add of a constant which is
830 ;; a 4 byte instruction into two adds which are both 2 byte
831 ;; instructions. There are two cases: one where we are adding a
832 ;; constant plus a register to another register, and one where we are
833 ;; simply adding a constant to a register.
836 [(set (match_operand:SI 0 "register_operand")
837 (plus:SI (match_dup 0)
838 (match_operand:SI 1 "const_int_operand")))]
839 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
840 && REG_P (operands[0])
841 && M16_REG_P (REGNO (operands[0]))
842 && GET_CODE (operands[1]) == CONST_INT
843 && ((INTVAL (operands[1]) > 0x7f
844 && INTVAL (operands[1]) <= 0x7f + 0x7f)
845 || (INTVAL (operands[1]) < - 0x80
846 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
847 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
848 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
850 HOST_WIDE_INT val = INTVAL (operands[1]);
854 operands[1] = GEN_INT (0x7f);
855 operands[2] = GEN_INT (val - 0x7f);
859 operands[1] = GEN_INT (- 0x80);
860 operands[2] = GEN_INT (val + 0x80);
865 [(set (match_operand:SI 0 "register_operand")
866 (plus:SI (match_operand:SI 1 "register_operand")
867 (match_operand:SI 2 "const_int_operand")))]
868 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
869 && REG_P (operands[0])
870 && M16_REG_P (REGNO (operands[0]))
871 && REG_P (operands[1])
872 && M16_REG_P (REGNO (operands[1]))
873 && REGNO (operands[0]) != REGNO (operands[1])
874 && GET_CODE (operands[2]) == CONST_INT
875 && ((INTVAL (operands[2]) > 0x7
876 && INTVAL (operands[2]) <= 0x7 + 0x7f)
877 || (INTVAL (operands[2]) < - 0x8
878 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
879 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
880 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
882 HOST_WIDE_INT val = INTVAL (operands[2]);
886 operands[2] = GEN_INT (0x7);
887 operands[3] = GEN_INT (val - 0x7);
891 operands[2] = GEN_INT (- 0x8);
892 operands[3] = GEN_INT (val + 0x8);
897 [(set (match_operand:DI 0 "register_operand")
898 (plus:DI (match_dup 0)
899 (match_operand:DI 1 "const_int_operand")))]
900 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
901 && REG_P (operands[0])
902 && M16_REG_P (REGNO (operands[0]))
903 && GET_CODE (operands[1]) == CONST_INT
904 && ((INTVAL (operands[1]) > 0xf
905 && INTVAL (operands[1]) <= 0xf + 0xf)
906 || (INTVAL (operands[1]) < - 0x10
907 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
908 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
909 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
911 HOST_WIDE_INT val = INTVAL (operands[1]);
915 operands[1] = GEN_INT (0xf);
916 operands[2] = GEN_INT (val - 0xf);
920 operands[1] = GEN_INT (- 0x10);
921 operands[2] = GEN_INT (val + 0x10);
926 [(set (match_operand:DI 0 "register_operand")
927 (plus:DI (match_operand:DI 1 "register_operand")
928 (match_operand:DI 2 "const_int_operand")))]
929 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
930 && REG_P (operands[0])
931 && M16_REG_P (REGNO (operands[0]))
932 && REG_P (operands[1])
933 && M16_REG_P (REGNO (operands[1]))
934 && REGNO (operands[0]) != REGNO (operands[1])
935 && GET_CODE (operands[2]) == CONST_INT
936 && ((INTVAL (operands[2]) > 0x7
937 && INTVAL (operands[2]) <= 0x7 + 0xf)
938 || (INTVAL (operands[2]) < - 0x8
939 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
940 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
941 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
943 HOST_WIDE_INT val = INTVAL (operands[2]);
947 operands[2] = GEN_INT (0x7);
948 operands[3] = GEN_INT (val - 0x7);
952 operands[2] = GEN_INT (- 0x8);
953 operands[3] = GEN_INT (val + 0x8);
957 (define_insn "*addsi3_extended"
958 [(set (match_operand:DI 0 "register_operand" "=d,d")
960 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
961 (match_operand:SI 2 "arith_operand" "d,Q"))))]
962 "TARGET_64BIT && !TARGET_MIPS16"
966 [(set_attr "type" "arith")
967 (set_attr "mode" "SI")])
969 ;; Split this insn so that the addiu splitters can have a crack at it.
970 ;; Use a conservative length estimate until the split.
971 (define_insn_and_split "*addsi3_extended_mips16"
972 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
974 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
975 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
976 "TARGET_64BIT && TARGET_MIPS16"
978 "&& reload_completed"
979 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
980 { operands[3] = gen_lowpart (SImode, operands[0]); }
981 [(set_attr "type" "arith")
982 (set_attr "mode" "SI")
983 (set_attr "extended_mips16" "yes")])
986 ;; ....................
990 ;; ....................
993 (define_insn "sub<mode>3"
994 [(set (match_operand:ANYF 0 "register_operand" "=f")
995 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
996 (match_operand:ANYF 2 "register_operand" "f")))]
998 "sub.<fmt>\t%0,%1,%2"
999 [(set_attr "type" "fadd")
1000 (set_attr "mode" "<UNITMODE>")])
1002 (define_insn "sub<mode>3"
1003 [(set (match_operand:GPR 0 "register_operand" "=d")
1004 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1005 (match_operand:GPR 2 "register_operand" "d")))]
1008 [(set_attr "type" "arith")
1009 (set_attr "mode" "<MODE>")])
1011 (define_insn "*subsi3_extended"
1012 [(set (match_operand:DI 0 "register_operand" "=d")
1014 (minus:SI (match_operand:SI 1 "register_operand" "d")
1015 (match_operand:SI 2 "register_operand" "d"))))]
1018 [(set_attr "type" "arith")
1019 (set_attr "mode" "DI")])
1022 ;; ....................
1026 ;; ....................
1029 (define_expand "mul<mode>3"
1030 [(set (match_operand:SCALARF 0 "register_operand")
1031 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1032 (match_operand:SCALARF 2 "register_operand")))]
1036 (define_insn "*mul<mode>3"
1037 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1038 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1039 (match_operand:SCALARF 2 "register_operand" "f")))]
1040 "!TARGET_4300_MUL_FIX"
1041 "mul.<fmt>\t%0,%1,%2"
1042 [(set_attr "type" "fmul")
1043 (set_attr "mode" "<MODE>")])
1045 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1046 ;; operands may corrupt immediately following multiplies. This is a
1047 ;; simple fix to insert NOPs.
1049 (define_insn "*mul<mode>3_r4300"
1050 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1051 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1052 (match_operand:SCALARF 2 "register_operand" "f")))]
1053 "TARGET_4300_MUL_FIX"
1054 "mul.<fmt>\t%0,%1,%2\;nop"
1055 [(set_attr "type" "fmul")
1056 (set_attr "mode" "<MODE>")
1057 (set_attr "length" "8")])
1059 (define_insn "mulv2sf3"
1060 [(set (match_operand:V2SF 0 "register_operand" "=f")
1061 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1062 (match_operand:V2SF 2 "register_operand" "f")))]
1063 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1065 [(set_attr "type" "fmul")
1066 (set_attr "mode" "SF")])
1068 ;; The original R4000 has a cpu bug. If a double-word or a variable
1069 ;; shift executes while an integer multiplication is in progress, the
1070 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1071 ;; with the mult on the R4000.
1073 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1074 ;; (also valid for MIPS R4000MC processors):
1076 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1077 ;; this errata description.
1078 ;; The following code sequence causes the R4000 to incorrectly
1079 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1080 ;; instruction. If the dsra32 instruction is executed during an
1081 ;; integer multiply, the dsra32 will only shift by the amount in
1082 ;; specified in the instruction rather than the amount plus 32
1084 ;; instruction 1: mult rs,rt integer multiply
1085 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1086 ;; right arithmetic + 32
1087 ;; Workaround: A dsra32 instruction placed after an integer
1088 ;; multiply should not be one of the 11 instructions after the
1089 ;; multiply instruction."
1093 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1094 ;; the following description.
1095 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1096 ;; 64-bit versions) may produce incorrect results under the
1097 ;; following conditions:
1098 ;; 1) An integer multiply is currently executing
1099 ;; 2) These types of shift instructions are executed immediately
1100 ;; following an integer divide instruction.
1102 ;; 1) Make sure no integer multiply is running wihen these
1103 ;; instruction are executed. If this cannot be predicted at
1104 ;; compile time, then insert a "mfhi" to R0 instruction
1105 ;; immediately after the integer multiply instruction. This
1106 ;; will cause the integer multiply to complete before the shift
1108 ;; 2) Separate integer divide and these two classes of shift
1109 ;; instructions by another instruction or a noop."
1111 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1114 (define_expand "mulsi3"
1115 [(set (match_operand:SI 0 "register_operand")
1116 (mult:SI (match_operand:SI 1 "register_operand")
1117 (match_operand:SI 2 "register_operand")))]
1121 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1122 else if (TARGET_FIX_R4000)
1123 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1125 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1129 (define_expand "muldi3"
1130 [(set (match_operand:DI 0 "register_operand")
1131 (mult:DI (match_operand:DI 1 "register_operand")
1132 (match_operand:DI 2 "register_operand")))]
1135 if (TARGET_FIX_R4000)
1136 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1138 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1142 (define_insn "mulsi3_mult3"
1143 [(set (match_operand:SI 0 "register_operand" "=d,l")
1144 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1145 (match_operand:SI 2 "register_operand" "d,d")))
1146 (clobber (match_scratch:SI 3 "=h,h"))
1147 (clobber (match_scratch:SI 4 "=l,X"))]
1150 if (which_alternative == 1)
1151 return "mult\t%1,%2";
1152 if (TARGET_MIPS3900)
1153 return "mult\t%0,%1,%2";
1154 return "mul\t%0,%1,%2";
1156 [(set_attr "type" "imul3,imul")
1157 (set_attr "mode" "SI")])
1159 ;; If a register gets allocated to LO, and we spill to memory, the reload
1160 ;; will include a move from LO to a GPR. Merge it into the multiplication
1161 ;; if it can set the GPR directly.
1164 ;; Operand 1: GPR (1st multiplication operand)
1165 ;; Operand 2: GPR (2nd multiplication operand)
1167 ;; Operand 4: GPR (destination)
1170 [(set (match_operand:SI 0 "register_operand")
1171 (mult:SI (match_operand:SI 1 "register_operand")
1172 (match_operand:SI 2 "register_operand")))
1173 (clobber (match_operand:SI 3 "register_operand"))
1174 (clobber (scratch:SI))])
1175 (set (match_operand:SI 4 "register_operand")
1176 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1177 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1180 (mult:SI (match_dup 1)
1182 (clobber (match_dup 3))
1183 (clobber (match_dup 0))])])
1185 (define_insn "mul<mode>3_internal"
1186 [(set (match_operand:GPR 0 "register_operand" "=l")
1187 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1188 (match_operand:GPR 2 "register_operand" "d")))
1189 (clobber (match_scratch:GPR 3 "=h"))]
1192 [(set_attr "type" "imul")
1193 (set_attr "mode" "<MODE>")])
1195 (define_insn "mul<mode>3_r4000"
1196 [(set (match_operand:GPR 0 "register_operand" "=d")
1197 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1198 (match_operand:GPR 2 "register_operand" "d")))
1199 (clobber (match_scratch:GPR 3 "=h"))
1200 (clobber (match_scratch:GPR 4 "=l"))]
1202 "<d>mult\t%1,%2\;mflo\t%0"
1203 [(set_attr "type" "imul")
1204 (set_attr "mode" "<MODE>")
1205 (set_attr "length" "8")])
1207 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1208 ;; of "mult; mflo". They have the same latency, but the first form gives
1209 ;; us an extra cycle to compute the operands.
1212 ;; Operand 1: GPR (1st multiplication operand)
1213 ;; Operand 2: GPR (2nd multiplication operand)
1215 ;; Operand 4: GPR (destination)
1218 [(set (match_operand:SI 0 "register_operand")
1219 (mult:SI (match_operand:SI 1 "register_operand")
1220 (match_operand:SI 2 "register_operand")))
1221 (clobber (match_operand:SI 3 "register_operand"))])
1222 (set (match_operand:SI 4 "register_operand")
1223 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1224 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1229 (plus:SI (mult:SI (match_dup 1)
1233 (plus:SI (mult:SI (match_dup 1)
1236 (clobber (match_dup 3))])])
1238 ;; Multiply-accumulate patterns
1240 ;; For processors that can copy the output to a general register:
1242 ;; The all-d alternative is needed because the combiner will find this
1243 ;; pattern and then register alloc/reload will move registers around to
1244 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1246 ;; The last alternative should be made slightly less desirable, but adding
1247 ;; "?" to the constraint is too strong, and causes values to be loaded into
1248 ;; LO even when that's more costly. For now, using "*d" mostly does the
1250 (define_insn "*mul_acc_si"
1251 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1252 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1253 (match_operand:SI 2 "register_operand" "d,d,d"))
1254 (match_operand:SI 3 "register_operand" "0,l,*d")))
1255 (clobber (match_scratch:SI 4 "=h,h,h"))
1256 (clobber (match_scratch:SI 5 "=X,3,l"))
1257 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1259 || GENERATE_MADD_MSUB)
1262 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1263 if (which_alternative == 2)
1265 if (GENERATE_MADD_MSUB && which_alternative != 0)
1267 return madd[which_alternative];
1269 [(set_attr "type" "imadd")
1270 (set_attr "mode" "SI")
1271 (set_attr "length" "4,4,8")])
1273 ;; Split the above insn if we failed to get LO allocated.
1275 [(set (match_operand:SI 0 "register_operand")
1276 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1277 (match_operand:SI 2 "register_operand"))
1278 (match_operand:SI 3 "register_operand")))
1279 (clobber (match_scratch:SI 4))
1280 (clobber (match_scratch:SI 5))
1281 (clobber (match_scratch:SI 6))]
1282 "reload_completed && !TARGET_DEBUG_D_MODE
1283 && GP_REG_P (true_regnum (operands[0]))
1284 && GP_REG_P (true_regnum (operands[3]))"
1285 [(parallel [(set (match_dup 6)
1286 (mult:SI (match_dup 1) (match_dup 2)))
1287 (clobber (match_dup 4))
1288 (clobber (match_dup 5))])
1289 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1292 ;; Splitter to copy result of MADD to a general register
1294 [(set (match_operand:SI 0 "register_operand")
1295 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1296 (match_operand:SI 2 "register_operand"))
1297 (match_operand:SI 3 "register_operand")))
1298 (clobber (match_scratch:SI 4))
1299 (clobber (match_scratch:SI 5))
1300 (clobber (match_scratch:SI 6))]
1301 "reload_completed && !TARGET_DEBUG_D_MODE
1302 && GP_REG_P (true_regnum (operands[0]))
1303 && true_regnum (operands[3]) == LO_REGNUM"
1304 [(parallel [(set (match_dup 3)
1305 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1307 (clobber (match_dup 4))
1308 (clobber (match_dup 5))
1309 (clobber (match_dup 6))])
1310 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1313 (define_insn "*macc"
1314 [(set (match_operand:SI 0 "register_operand" "=l,d")
1315 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1316 (match_operand:SI 2 "register_operand" "d,d"))
1317 (match_operand:SI 3 "register_operand" "0,l")))
1318 (clobber (match_scratch:SI 4 "=h,h"))
1319 (clobber (match_scratch:SI 5 "=X,3"))]
1322 if (which_alternative == 1)
1323 return "macc\t%0,%1,%2";
1324 else if (TARGET_MIPS5500)
1325 return "madd\t%1,%2";
1327 /* The VR4130 assumes that there is a two-cycle latency between a macc
1328 that "writes" to $0 and an instruction that reads from it. We avoid
1329 this by assigning to $1 instead. */
1330 return "%[macc\t%@,%1,%2%]";
1332 [(set_attr "type" "imadd")
1333 (set_attr "mode" "SI")])
1335 (define_insn "*msac"
1336 [(set (match_operand:SI 0 "register_operand" "=l,d")
1337 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1338 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1339 (match_operand:SI 3 "register_operand" "d,d"))))
1340 (clobber (match_scratch:SI 4 "=h,h"))
1341 (clobber (match_scratch:SI 5 "=X,1"))]
1344 if (which_alternative == 1)
1345 return "msac\t%0,%2,%3";
1346 else if (TARGET_MIPS5500)
1347 return "msub\t%2,%3";
1349 return "msac\t$0,%2,%3";
1351 [(set_attr "type" "imadd")
1352 (set_attr "mode" "SI")])
1354 ;; An msac-like instruction implemented using negation and a macc.
1355 (define_insn_and_split "*msac_using_macc"
1356 [(set (match_operand:SI 0 "register_operand" "=l,d")
1357 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1358 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1359 (match_operand:SI 3 "register_operand" "d,d"))))
1360 (clobber (match_scratch:SI 4 "=h,h"))
1361 (clobber (match_scratch:SI 5 "=X,1"))
1362 (clobber (match_scratch:SI 6 "=d,d"))]
1363 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1365 "&& reload_completed"
1367 (neg:SI (match_dup 3)))
1370 (plus:SI (mult:SI (match_dup 2)
1373 (clobber (match_dup 4))
1374 (clobber (match_dup 5))])]
1376 [(set_attr "type" "imadd")
1377 (set_attr "length" "8")])
1379 ;; Patterns generated by the define_peephole2 below.
1381 (define_insn "*macc2"
1382 [(set (match_operand:SI 0 "register_operand" "=l")
1383 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1384 (match_operand:SI 2 "register_operand" "d"))
1386 (set (match_operand:SI 3 "register_operand" "=d")
1387 (plus:SI (mult:SI (match_dup 1)
1390 (clobber (match_scratch:SI 4 "=h"))]
1391 "ISA_HAS_MACC && reload_completed"
1393 [(set_attr "type" "imadd")
1394 (set_attr "mode" "SI")])
1396 (define_insn "*msac2"
1397 [(set (match_operand:SI 0 "register_operand" "=l")
1398 (minus:SI (match_dup 0)
1399 (mult:SI (match_operand:SI 1 "register_operand" "d")
1400 (match_operand:SI 2 "register_operand" "d"))))
1401 (set (match_operand:SI 3 "register_operand" "=d")
1402 (minus:SI (match_dup 0)
1403 (mult:SI (match_dup 1)
1405 (clobber (match_scratch:SI 4 "=h"))]
1406 "ISA_HAS_MSAC && reload_completed"
1408 [(set_attr "type" "imadd")
1409 (set_attr "mode" "SI")])
1411 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1415 ;; Operand 1: macc/msac
1417 ;; Operand 3: GPR (destination)
1420 [(set (match_operand:SI 0 "register_operand")
1421 (match_operand:SI 1 "macc_msac_operand"))
1422 (clobber (match_operand:SI 2 "register_operand"))
1423 (clobber (scratch:SI))])
1424 (set (match_operand:SI 3 "register_operand")
1425 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1427 [(parallel [(set (match_dup 0)
1431 (clobber (match_dup 2))])]
1434 ;; When we have a three-address multiplication instruction, it should
1435 ;; be faster to do a separate multiply and add, rather than moving
1436 ;; something into LO in order to use a macc instruction.
1438 ;; This peephole needs a scratch register to cater for the case when one
1439 ;; of the multiplication operands is the same as the destination.
1441 ;; Operand 0: GPR (scratch)
1443 ;; Operand 2: GPR (addend)
1444 ;; Operand 3: GPR (destination)
1445 ;; Operand 4: macc/msac
1447 ;; Operand 6: new multiplication
1448 ;; Operand 7: new addition/subtraction
1450 [(match_scratch:SI 0 "d")
1451 (set (match_operand:SI 1 "register_operand")
1452 (match_operand:SI 2 "register_operand"))
1455 [(set (match_operand:SI 3 "register_operand")
1456 (match_operand:SI 4 "macc_msac_operand"))
1457 (clobber (match_operand:SI 5 "register_operand"))
1458 (clobber (match_dup 1))])]
1460 && true_regnum (operands[1]) == LO_REGNUM
1461 && peep2_reg_dead_p (2, operands[1])
1462 && GP_REG_P (true_regnum (operands[3]))"
1463 [(parallel [(set (match_dup 0)
1465 (clobber (match_dup 5))
1466 (clobber (match_dup 1))])
1470 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1471 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1472 operands[2], operands[0]);
1475 ;; Same as above, except LO is the initial target of the macc.
1477 ;; Operand 0: GPR (scratch)
1479 ;; Operand 2: GPR (addend)
1480 ;; Operand 3: macc/msac
1482 ;; Operand 5: GPR (destination)
1483 ;; Operand 6: new multiplication
1484 ;; Operand 7: new addition/subtraction
1486 [(match_scratch:SI 0 "d")
1487 (set (match_operand:SI 1 "register_operand")
1488 (match_operand:SI 2 "register_operand"))
1492 (match_operand:SI 3 "macc_msac_operand"))
1493 (clobber (match_operand:SI 4 "register_operand"))
1494 (clobber (scratch:SI))])
1496 (set (match_operand:SI 5 "register_operand")
1497 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1498 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1499 [(parallel [(set (match_dup 0)
1501 (clobber (match_dup 4))
1502 (clobber (match_dup 1))])
1506 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1507 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1508 operands[2], operands[0]);
1511 (define_insn "*mul_sub_si"
1512 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1513 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1514 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1515 (match_operand:SI 3 "register_operand" "d,d,d"))))
1516 (clobber (match_scratch:SI 4 "=h,h,h"))
1517 (clobber (match_scratch:SI 5 "=X,1,l"))
1518 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1519 "GENERATE_MADD_MSUB"
1524 [(set_attr "type" "imadd")
1525 (set_attr "mode" "SI")
1526 (set_attr "length" "4,8,8")])
1528 ;; Split the above insn if we failed to get LO allocated.
1530 [(set (match_operand:SI 0 "register_operand")
1531 (minus:SI (match_operand:SI 1 "register_operand")
1532 (mult:SI (match_operand:SI 2 "register_operand")
1533 (match_operand:SI 3 "register_operand"))))
1534 (clobber (match_scratch:SI 4))
1535 (clobber (match_scratch:SI 5))
1536 (clobber (match_scratch:SI 6))]
1537 "reload_completed && !TARGET_DEBUG_D_MODE
1538 && GP_REG_P (true_regnum (operands[0]))
1539 && GP_REG_P (true_regnum (operands[1]))"
1540 [(parallel [(set (match_dup 6)
1541 (mult:SI (match_dup 2) (match_dup 3)))
1542 (clobber (match_dup 4))
1543 (clobber (match_dup 5))])
1544 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1547 ;; Splitter to copy result of MSUB to a general register
1549 [(set (match_operand:SI 0 "register_operand")
1550 (minus:SI (match_operand:SI 1 "register_operand")
1551 (mult:SI (match_operand:SI 2 "register_operand")
1552 (match_operand:SI 3 "register_operand"))))
1553 (clobber (match_scratch:SI 4))
1554 (clobber (match_scratch:SI 5))
1555 (clobber (match_scratch:SI 6))]
1556 "reload_completed && !TARGET_DEBUG_D_MODE
1557 && GP_REG_P (true_regnum (operands[0]))
1558 && true_regnum (operands[1]) == LO_REGNUM"
1559 [(parallel [(set (match_dup 1)
1560 (minus:SI (match_dup 1)
1561 (mult:SI (match_dup 2) (match_dup 3))))
1562 (clobber (match_dup 4))
1563 (clobber (match_dup 5))
1564 (clobber (match_dup 6))])
1565 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1568 (define_insn "*muls"
1569 [(set (match_operand:SI 0 "register_operand" "=l,d")
1570 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1571 (match_operand:SI 2 "register_operand" "d,d"))))
1572 (clobber (match_scratch:SI 3 "=h,h"))
1573 (clobber (match_scratch:SI 4 "=X,l"))]
1578 [(set_attr "type" "imul,imul3")
1579 (set_attr "mode" "SI")])
1581 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1583 (define_expand "<u>mulsidi3"
1585 [(set (match_operand:DI 0 "register_operand")
1586 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1587 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1588 (clobber (scratch:DI))
1589 (clobber (scratch:DI))
1590 (clobber (scratch:DI))])]
1591 "!TARGET_64BIT || !TARGET_FIX_R4000"
1595 if (!TARGET_FIX_R4000)
1596 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1599 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1605 (define_insn "<u>mulsidi3_32bit_internal"
1606 [(set (match_operand:DI 0 "register_operand" "=x")
1607 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1608 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1609 "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
1611 [(set_attr "type" "imul")
1612 (set_attr "mode" "SI")])
1614 (define_insn "<u>mulsidi3_32bit_r4000"
1615 [(set (match_operand:DI 0 "register_operand" "=d")
1616 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1617 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1618 (clobber (match_scratch:DI 3 "=x"))]
1619 "!TARGET_64BIT && TARGET_FIX_R4000"
1620 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1621 [(set_attr "type" "imul")
1622 (set_attr "mode" "SI")
1623 (set_attr "length" "12")])
1625 (define_insn_and_split "*<u>mulsidi3_64bit"
1626 [(set (match_operand:DI 0 "register_operand" "=d")
1627 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1628 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1629 (clobber (match_scratch:DI 3 "=l"))
1630 (clobber (match_scratch:DI 4 "=h"))
1631 (clobber (match_scratch:DI 5 "=d"))]
1632 "TARGET_64BIT && !TARGET_FIX_R4000"
1634 "&& reload_completed"
1638 (mult:SI (match_dup 1)
1642 (mult:DI (any_extend:DI (match_dup 1))
1643 (any_extend:DI (match_dup 2)))
1646 ;; OP5 <- LO, OP0 <- HI
1647 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1648 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1652 (ashift:DI (match_dup 5)
1655 (lshiftrt:DI (match_dup 5)
1658 ;; Shift OP0 into place.
1660 (ashift:DI (match_dup 0)
1663 ;; OR the two halves together
1665 (ior:DI (match_dup 0)
1668 [(set_attr "type" "imul")
1669 (set_attr "mode" "SI")
1670 (set_attr "length" "24")])
1672 (define_insn "*<u>mulsidi3_64bit_parts"
1673 [(set (match_operand:DI 0 "register_operand" "=l")
1675 (mult:SI (match_operand:SI 2 "register_operand" "d")
1676 (match_operand:SI 3 "register_operand" "d"))))
1677 (set (match_operand:DI 1 "register_operand" "=h")
1679 (mult:DI (any_extend:DI (match_dup 2))
1680 (any_extend:DI (match_dup 3)))
1682 "TARGET_64BIT && !TARGET_FIX_R4000"
1684 [(set_attr "type" "imul")
1685 (set_attr "mode" "SI")])
1687 ;; Widening multiply with negation.
1688 (define_insn "*muls<u>_di"
1689 [(set (match_operand:DI 0 "register_operand" "=x")
1692 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1693 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1694 "!TARGET_64BIT && ISA_HAS_MULS"
1696 [(set_attr "type" "imul")
1697 (set_attr "mode" "SI")])
1699 (define_insn "<u>msubsidi4"
1700 [(set (match_operand:DI 0 "register_operand" "=ka")
1702 (match_operand:DI 3 "register_operand" "0")
1704 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1705 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1706 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
1709 return "msub<u>\t%q0,%1,%2";
1710 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
1711 return "msub<u>\t%1,%2";
1713 return "msac<u>\t$0,%1,%2";
1715 [(set_attr "type" "imadd")
1716 (set_attr "mode" "SI")])
1718 ;; _highpart patterns
1720 (define_expand "<su>mulsi3_highpart"
1721 [(set (match_operand:SI 0 "register_operand")
1724 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1725 (any_extend:DI (match_operand:SI 2 "register_operand")))
1727 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1730 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1734 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1739 (define_insn "<su>mulsi3_highpart_internal"
1740 [(set (match_operand:SI 0 "register_operand" "=h")
1743 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1744 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1746 (clobber (match_scratch:SI 3 "=l"))]
1747 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1749 [(set_attr "type" "imul")
1750 (set_attr "mode" "SI")])
1752 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1753 [(set (match_operand:SI 0 "register_operand" "=h,d")
1757 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1758 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1760 (clobber (match_scratch:SI 3 "=l,l"))
1761 (clobber (match_scratch:SI 4 "=X,h"))]
1766 [(set_attr "type" "imul,imul3")
1767 (set_attr "mode" "SI")])
1769 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1770 [(set (match_operand:SI 0 "register_operand" "=h,d")
1775 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1776 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1778 (clobber (match_scratch:SI 3 "=l,l"))
1779 (clobber (match_scratch:SI 4 "=X,h"))]
1783 mulshi<u>\t%0,%1,%2"
1784 [(set_attr "type" "imul,imul3")
1785 (set_attr "mode" "SI")])
1787 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1788 ;; errata MD(0), which says that dmultu does not always produce the
1790 (define_insn "<su>muldi3_highpart"
1791 [(set (match_operand:DI 0 "register_operand" "=h")
1795 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1796 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1798 (clobber (match_scratch:DI 3 "=l"))]
1799 "TARGET_64BIT && !TARGET_FIX_R4000
1800 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1802 [(set_attr "type" "imul")
1803 (set_attr "mode" "DI")])
1805 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1806 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1808 (define_insn "madsi"
1809 [(set (match_operand:SI 0 "register_operand" "+l")
1810 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1811 (match_operand:SI 2 "register_operand" "d"))
1813 (clobber (match_scratch:SI 3 "=h"))]
1816 [(set_attr "type" "imadd")
1817 (set_attr "mode" "SI")])
1819 (define_insn "<u>maddsidi4"
1820 [(set (match_operand:DI 0 "register_operand" "=ka")
1822 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1823 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1824 (match_operand:DI 3 "register_operand" "0")))]
1825 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
1829 return "mad<u>\t%1,%2";
1830 else if (ISA_HAS_DSPR2)
1831 return "madd<u>\t%q0,%1,%2";
1832 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
1833 return "madd<u>\t%1,%2";
1835 /* See comment in *macc. */
1836 return "%[macc<u>\t%@,%1,%2%]";
1838 [(set_attr "type" "imadd")
1839 (set_attr "mode" "SI")])
1841 ;; Floating point multiply accumulate instructions.
1843 (define_insn "*madd<mode>"
1844 [(set (match_operand:ANYF 0 "register_operand" "=f")
1845 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1846 (match_operand:ANYF 2 "register_operand" "f"))
1847 (match_operand:ANYF 3 "register_operand" "f")))]
1848 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1849 "madd.<fmt>\t%0,%3,%1,%2"
1850 [(set_attr "type" "fmadd")
1851 (set_attr "mode" "<UNITMODE>")])
1853 (define_insn "*msub<mode>"
1854 [(set (match_operand:ANYF 0 "register_operand" "=f")
1855 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1856 (match_operand:ANYF 2 "register_operand" "f"))
1857 (match_operand:ANYF 3 "register_operand" "f")))]
1858 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1859 "msub.<fmt>\t%0,%3,%1,%2"
1860 [(set_attr "type" "fmadd")
1861 (set_attr "mode" "<UNITMODE>")])
1863 (define_insn "*nmadd<mode>"
1864 [(set (match_operand:ANYF 0 "register_operand" "=f")
1865 (neg:ANYF (plus:ANYF
1866 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1867 (match_operand:ANYF 2 "register_operand" "f"))
1868 (match_operand:ANYF 3 "register_operand" "f"))))]
1869 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1870 && TARGET_FUSED_MADD
1871 && HONOR_SIGNED_ZEROS (<MODE>mode)
1872 && !HONOR_NANS (<MODE>mode)"
1873 "nmadd.<fmt>\t%0,%3,%1,%2"
1874 [(set_attr "type" "fmadd")
1875 (set_attr "mode" "<UNITMODE>")])
1877 (define_insn "*nmadd<mode>_fastmath"
1878 [(set (match_operand:ANYF 0 "register_operand" "=f")
1880 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1881 (match_operand:ANYF 2 "register_operand" "f"))
1882 (match_operand:ANYF 3 "register_operand" "f")))]
1883 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1884 && TARGET_FUSED_MADD
1885 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1886 && !HONOR_NANS (<MODE>mode)"
1887 "nmadd.<fmt>\t%0,%3,%1,%2"
1888 [(set_attr "type" "fmadd")
1889 (set_attr "mode" "<UNITMODE>")])
1891 (define_insn "*nmsub<mode>"
1892 [(set (match_operand:ANYF 0 "register_operand" "=f")
1893 (neg:ANYF (minus:ANYF
1894 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1895 (match_operand:ANYF 3 "register_operand" "f"))
1896 (match_operand:ANYF 1 "register_operand" "f"))))]
1897 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1898 && TARGET_FUSED_MADD
1899 && HONOR_SIGNED_ZEROS (<MODE>mode)
1900 && !HONOR_NANS (<MODE>mode)"
1901 "nmsub.<fmt>\t%0,%1,%2,%3"
1902 [(set_attr "type" "fmadd")
1903 (set_attr "mode" "<UNITMODE>")])
1905 (define_insn "*nmsub<mode>_fastmath"
1906 [(set (match_operand:ANYF 0 "register_operand" "=f")
1908 (match_operand:ANYF 1 "register_operand" "f")
1909 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1910 (match_operand:ANYF 3 "register_operand" "f"))))]
1911 "ISA_HAS_NMADD_NMSUB (<MODE>mode)
1912 && TARGET_FUSED_MADD
1913 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1914 && !HONOR_NANS (<MODE>mode)"
1915 "nmsub.<fmt>\t%0,%1,%2,%3"
1916 [(set_attr "type" "fmadd")
1917 (set_attr "mode" "<UNITMODE>")])
1920 ;; ....................
1922 ;; DIVISION and REMAINDER
1924 ;; ....................
1927 (define_expand "div<mode>3"
1928 [(set (match_operand:ANYF 0 "register_operand")
1929 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1930 (match_operand:ANYF 2 "register_operand")))]
1931 "<divide_condition>"
1933 if (const_1_operand (operands[1], <MODE>mode))
1934 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1935 operands[1] = force_reg (<MODE>mode, operands[1]);
1938 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1940 ;; If an mfc1 or dmfc1 happens to access the floating point register
1941 ;; file at the same time a long latency operation (div, sqrt, recip,
1942 ;; sqrt) iterates an intermediate result back through the floating
1943 ;; point register file bypass, then instead returning the correct
1944 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1945 ;; result of the long latency operation.
1947 ;; The workaround is to insert an unconditional 'mov' from/to the
1948 ;; long latency op destination register.
1950 (define_insn "*div<mode>3"
1951 [(set (match_operand:ANYF 0 "register_operand" "=f")
1952 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1953 (match_operand:ANYF 2 "register_operand" "f")))]
1954 "<divide_condition>"
1957 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1959 return "div.<fmt>\t%0,%1,%2";
1961 [(set_attr "type" "fdiv")
1962 (set_attr "mode" "<UNITMODE>")
1963 (set (attr "length")
1964 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1968 (define_insn "*recip<mode>3"
1969 [(set (match_operand:ANYF 0 "register_operand" "=f")
1970 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1971 (match_operand:ANYF 2 "register_operand" "f")))]
1972 "<recip_condition> && flag_unsafe_math_optimizations"
1975 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1977 return "recip.<fmt>\t%0,%2";
1979 [(set_attr "type" "frdiv")
1980 (set_attr "mode" "<UNITMODE>")
1981 (set (attr "length")
1982 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1986 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1987 ;; with negative operands. We use special libgcc functions instead.
1988 (define_insn "divmod<mode>4"
1989 [(set (match_operand:GPR 0 "register_operand" "=l")
1990 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1991 (match_operand:GPR 2 "register_operand" "d")))
1992 (set (match_operand:GPR 3 "register_operand" "=h")
1993 (mod:GPR (match_dup 1)
1995 "!TARGET_FIX_VR4120"
1996 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1997 [(set_attr "type" "idiv")
1998 (set_attr "mode" "<MODE>")])
2000 (define_insn "udivmod<mode>4"
2001 [(set (match_operand:GPR 0 "register_operand" "=l")
2002 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2003 (match_operand:GPR 2 "register_operand" "d")))
2004 (set (match_operand:GPR 3 "register_operand" "=h")
2005 (umod:GPR (match_dup 1)
2008 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
2009 [(set_attr "type" "idiv")
2010 (set_attr "mode" "<MODE>")])
2013 ;; ....................
2017 ;; ....................
2019 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2020 ;; "*div[sd]f3" comment for details).
2022 (define_insn "sqrt<mode>2"
2023 [(set (match_operand:ANYF 0 "register_operand" "=f")
2024 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2028 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2030 return "sqrt.<fmt>\t%0,%1";
2032 [(set_attr "type" "fsqrt")
2033 (set_attr "mode" "<UNITMODE>")
2034 (set (attr "length")
2035 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2039 (define_insn "*rsqrt<mode>a"
2040 [(set (match_operand:ANYF 0 "register_operand" "=f")
2041 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2042 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2043 "<recip_condition> && flag_unsafe_math_optimizations"
2046 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2048 return "rsqrt.<fmt>\t%0,%2";
2050 [(set_attr "type" "frsqrt")
2051 (set_attr "mode" "<UNITMODE>")
2052 (set (attr "length")
2053 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2057 (define_insn "*rsqrt<mode>b"
2058 [(set (match_operand:ANYF 0 "register_operand" "=f")
2059 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2060 (match_operand:ANYF 2 "register_operand" "f"))))]
2061 "<recip_condition> && flag_unsafe_math_optimizations"
2064 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2066 return "rsqrt.<fmt>\t%0,%2";
2068 [(set_attr "type" "frsqrt")
2069 (set_attr "mode" "<UNITMODE>")
2070 (set (attr "length")
2071 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2076 ;; ....................
2080 ;; ....................
2082 ;; Do not use the integer abs macro instruction, since that signals an
2083 ;; exception on -2147483648 (sigh).
2085 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2086 ;; invalid; it does not clear their sign bits. We therefore can't use
2087 ;; abs.fmt if the signs of NaNs matter.
2089 (define_insn "abs<mode>2"
2090 [(set (match_operand:ANYF 0 "register_operand" "=f")
2091 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2092 "!HONOR_NANS (<MODE>mode)"
2094 [(set_attr "type" "fabs")
2095 (set_attr "mode" "<UNITMODE>")])
2098 ;; ...................
2100 ;; Count leading zeroes.
2102 ;; ...................
2105 (define_insn "clz<mode>2"
2106 [(set (match_operand:GPR 0 "register_operand" "=d")
2107 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2110 [(set_attr "type" "clz")
2111 (set_attr "mode" "<MODE>")])
2114 ;; ....................
2116 ;; NEGATION and ONE'S COMPLEMENT
2118 ;; ....................
2120 (define_insn "negsi2"
2121 [(set (match_operand:SI 0 "register_operand" "=d")
2122 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2126 return "neg\t%0,%1";
2128 return "subu\t%0,%.,%1";
2130 [(set_attr "type" "arith")
2131 (set_attr "mode" "SI")])
2133 (define_insn "negdi2"
2134 [(set (match_operand:DI 0 "register_operand" "=d")
2135 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2136 "TARGET_64BIT && !TARGET_MIPS16"
2138 [(set_attr "type" "arith")
2139 (set_attr "mode" "DI")])
2141 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2142 ;; invalid; it does not flip their sign bit. We therefore can't use
2143 ;; neg.fmt if the signs of NaNs matter.
2145 (define_insn "neg<mode>2"
2146 [(set (match_operand:ANYF 0 "register_operand" "=f")
2147 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2148 "!HONOR_NANS (<MODE>mode)"
2150 [(set_attr "type" "fneg")
2151 (set_attr "mode" "<UNITMODE>")])
2153 (define_insn "one_cmpl<mode>2"
2154 [(set (match_operand:GPR 0 "register_operand" "=d")
2155 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2159 return "not\t%0,%1";
2161 return "nor\t%0,%.,%1";
2163 [(set_attr "type" "logical")
2164 (set_attr "mode" "<MODE>")])
2167 ;; ....................
2171 ;; ....................
2174 ;; Many of these instructions use trivial define_expands, because we
2175 ;; want to use a different set of constraints when TARGET_MIPS16.
2177 (define_expand "and<mode>3"
2178 [(set (match_operand:GPR 0 "register_operand")
2179 (and:GPR (match_operand:GPR 1 "register_operand")
2180 (match_operand:GPR 2 "uns_arith_operand")))]
2184 operands[2] = force_reg (<MODE>mode, operands[2]);
2187 (define_insn "*and<mode>3"
2188 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2189 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2190 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2195 [(set_attr "type" "logical")
2196 (set_attr "mode" "<MODE>")])
2198 (define_insn "*and<mode>3_mips16"
2199 [(set (match_operand:GPR 0 "register_operand" "=d")
2200 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2201 (match_operand:GPR 2 "register_operand" "d")))]
2204 [(set_attr "type" "logical")
2205 (set_attr "mode" "<MODE>")])
2207 (define_expand "ior<mode>3"
2208 [(set (match_operand:GPR 0 "register_operand")
2209 (ior:GPR (match_operand:GPR 1 "register_operand")
2210 (match_operand:GPR 2 "uns_arith_operand")))]
2214 operands[2] = force_reg (<MODE>mode, operands[2]);
2217 (define_insn "*ior<mode>3"
2218 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2219 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2220 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2225 [(set_attr "type" "logical")
2226 (set_attr "mode" "<MODE>")])
2228 (define_insn "*ior<mode>3_mips16"
2229 [(set (match_operand:GPR 0 "register_operand" "=d")
2230 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2231 (match_operand:GPR 2 "register_operand" "d")))]
2234 [(set_attr "type" "logical")
2235 (set_attr "mode" "<MODE>")])
2237 (define_expand "xor<mode>3"
2238 [(set (match_operand:GPR 0 "register_operand")
2239 (xor:GPR (match_operand:GPR 1 "register_operand")
2240 (match_operand:GPR 2 "uns_arith_operand")))]
2245 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2246 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2247 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2252 [(set_attr "type" "logical")
2253 (set_attr "mode" "<MODE>")])
2256 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2257 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2258 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2264 [(set_attr "type" "logical,arith,arith")
2265 (set_attr "mode" "<MODE>")
2266 (set_attr_alternative "length"
2268 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2273 (define_insn "*nor<mode>3"
2274 [(set (match_operand:GPR 0 "register_operand" "=d")
2275 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2276 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2279 [(set_attr "type" "logical")
2280 (set_attr "mode" "<MODE>")])
2283 ;; ....................
2287 ;; ....................
2291 (define_insn "truncdfsf2"
2292 [(set (match_operand:SF 0 "register_operand" "=f")
2293 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2294 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2296 [(set_attr "type" "fcvt")
2297 (set_attr "cnv_mode" "D2S")
2298 (set_attr "mode" "SF")])
2300 ;; Integer truncation patterns. Truncating SImode values to smaller
2301 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2302 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2303 ;; need to make sure that the lower 32 bits are properly sign-extended
2304 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2305 ;; smaller than SImode is equivalent to two separate truncations:
2308 ;; DI ---> HI == DI ---> SI ---> HI
2309 ;; DI ---> QI == DI ---> SI ---> QI
2311 ;; Step A needs a real instruction but step B does not.
2313 (define_insn "truncdisi2"
2314 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2315 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2320 [(set_attr "type" "shift,store")
2321 (set_attr "mode" "SI")
2322 (set_attr "extended_mips16" "yes,*")])
2324 (define_insn "truncdihi2"
2325 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2326 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2331 [(set_attr "type" "shift,store")
2332 (set_attr "mode" "SI")
2333 (set_attr "extended_mips16" "yes,*")])
2335 (define_insn "truncdiqi2"
2336 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2337 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2342 [(set_attr "type" "shift,store")
2343 (set_attr "mode" "SI")
2344 (set_attr "extended_mips16" "yes,*")])
2346 ;; Combiner patterns to optimize shift/truncate combinations.
2349 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2351 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2352 (match_operand:DI 2 "const_arith_operand" ""))))]
2353 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2355 [(set_attr "type" "shift")
2356 (set_attr "mode" "SI")])
2359 [(set (match_operand:SUBDI 0 "register_operand" "=d")
2361 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2363 "TARGET_64BIT && !TARGET_MIPS16"
2365 [(set_attr "type" "shift")
2366 (set_attr "mode" "SI")])
2369 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
2370 ;; use the shift/truncate patterns above.
2372 (define_insn_and_split "*extenddi_truncate<mode>"
2373 [(set (match_operand:DI 0 "register_operand" "=d")
2375 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2376 "TARGET_64BIT && !TARGET_MIPS16"
2378 "&& reload_completed"
2380 (ashift:DI (match_dup 1)
2383 (ashiftrt:DI (match_dup 2)
2386 operands[2] = gen_lowpart (DImode, operands[0]);
2387 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2390 (define_insn_and_split "*extendsi_truncate<mode>"
2391 [(set (match_operand:SI 0 "register_operand" "=d")
2393 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
2394 "TARGET_64BIT && !TARGET_MIPS16"
2396 "&& reload_completed"
2398 (ashift:DI (match_dup 1)
2401 (truncate:SI (ashiftrt:DI (match_dup 2)
2404 operands[2] = gen_lowpart (DImode, operands[0]);
2405 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
2408 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2410 (define_insn "*zero_extend<mode>_trunchi"
2411 [(set (match_operand:GPR 0 "register_operand" "=d")
2413 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2414 "TARGET_64BIT && !TARGET_MIPS16"
2415 "andi\t%0,%1,0xffff"
2416 [(set_attr "type" "logical")
2417 (set_attr "mode" "<MODE>")])
2419 (define_insn "*zero_extend<mode>_truncqi"
2420 [(set (match_operand:GPR 0 "register_operand" "=d")
2422 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2423 "TARGET_64BIT && !TARGET_MIPS16"
2425 [(set_attr "type" "logical")
2426 (set_attr "mode" "<MODE>")])
2429 [(set (match_operand:HI 0 "register_operand" "=d")
2431 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2432 "TARGET_64BIT && !TARGET_MIPS16"
2434 [(set_attr "type" "logical")
2435 (set_attr "mode" "HI")])
2438 ;; ....................
2442 ;; ....................
2446 (define_insn_and_split "zero_extendsidi2"
2447 [(set (match_operand:DI 0 "register_operand" "=d,d")
2448 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2453 "&& reload_completed && REG_P (operands[1])"
2455 (ashift:DI (match_dup 1) (const_int 32)))
2457 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2458 { operands[1] = gen_lowpart (DImode, operands[1]); }
2459 [(set_attr "type" "multi,load")
2460 (set_attr "mode" "DI")
2461 (set_attr "length" "8,*")])
2463 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2464 ;; because of TRULY_NOOP_TRUNCATION.
2466 (define_insn_and_split "*clear_upper32"
2467 [(set (match_operand:DI 0 "register_operand" "=d,d")
2468 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,W")
2469 (const_int 4294967295)))]
2472 if (which_alternative == 0)
2475 operands[1] = gen_lowpart (SImode, operands[1]);
2476 return "lwu\t%0,%1";
2478 "&& reload_completed && REG_P (operands[1])"
2480 (ashift:DI (match_dup 1) (const_int 32)))
2482 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2484 [(set_attr "type" "multi,load")
2485 (set_attr "mode" "DI")
2486 (set_attr "length" "8,*")])
2488 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2489 [(set (match_operand:GPR 0 "register_operand")
2490 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2493 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2494 && !memory_operand (operands[1], <SHORT:MODE>mode))
2496 emit_insn (gen_and<GPR:mode>3 (operands[0],
2497 gen_lowpart (<GPR:MODE>mode, operands[1]),
2498 force_reg (<GPR:MODE>mode,
2499 GEN_INT (<SHORT:mask>))));
2504 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2505 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2507 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2510 andi\t%0,%1,<SHORT:mask>
2511 l<SHORT:size>u\t%0,%1"
2512 [(set_attr "type" "logical,load")
2513 (set_attr "mode" "<GPR:MODE>")])
2515 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2516 [(set (match_operand:GPR 0 "register_operand" "=d")
2517 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2519 "ze<SHORT:size>\t%0"
2520 [(set_attr "type" "arith")
2521 (set_attr "mode" "<GPR:MODE>")])
2523 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2524 [(set (match_operand:GPR 0 "register_operand" "=d")
2525 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2527 "l<SHORT:size>u\t%0,%1"
2528 [(set_attr "type" "load")
2529 (set_attr "mode" "<GPR:MODE>")])
2531 (define_expand "zero_extendqihi2"
2532 [(set (match_operand:HI 0 "register_operand")
2533 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2536 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2538 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2544 (define_insn "*zero_extendqihi2"
2545 [(set (match_operand:HI 0 "register_operand" "=d,d")
2546 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2551 [(set_attr "type" "logical,load")
2552 (set_attr "mode" "HI")])
2554 (define_insn "*zero_extendqihi2_mips16"
2555 [(set (match_operand:HI 0 "register_operand" "=d")
2556 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2559 [(set_attr "type" "load")
2560 (set_attr "mode" "HI")])
2563 ;; ....................
2567 ;; ....................
2570 ;; Those for integer source operand are ordered widest source type first.
2572 ;; When TARGET_64BIT, all SImode integer registers should already be in
2573 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2574 ;; therefore get rid of register->register instructions if we constrain
2575 ;; the source to be in the same register as the destination.
2577 ;; The register alternative has type "arith" so that the pre-reload
2578 ;; scheduler will treat it as a move. This reflects what happens if
2579 ;; the register alternative needs a reload.
2580 (define_insn_and_split "extendsidi2"
2581 [(set (match_operand:DI 0 "register_operand" "=d,d")
2582 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2587 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2590 emit_note (NOTE_INSN_DELETED);
2593 [(set_attr "type" "arith,load")
2594 (set_attr "mode" "DI")])
2596 (define_expand "extend<SHORT:mode><GPR:mode>2"
2597 [(set (match_operand:GPR 0 "register_operand")
2598 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2601 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2602 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2603 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2607 l<SHORT:size>\t%0,%1"
2608 [(set_attr "type" "signext,load")
2609 (set_attr "mode" "<GPR:MODE>")])
2611 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2612 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2614 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2615 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2618 l<SHORT:size>\t%0,%1"
2619 "&& reload_completed && REG_P (operands[1])"
2620 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2621 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2623 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2624 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2625 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2627 [(set_attr "type" "arith,load")
2628 (set_attr "mode" "<GPR:MODE>")
2629 (set_attr "length" "8,*")])
2631 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2632 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2634 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2637 se<SHORT:size>\t%0,%1
2638 l<SHORT:size>\t%0,%1"
2639 [(set_attr "type" "signext,load")
2640 (set_attr "mode" "<GPR:MODE>")])
2642 (define_expand "extendqihi2"
2643 [(set (match_operand:HI 0 "register_operand")
2644 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2647 (define_insn "*extendqihi2_mips16e"
2648 [(set (match_operand:HI 0 "register_operand" "=d,d")
2649 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
2654 [(set_attr "type" "signext,load")
2655 (set_attr "mode" "SI")])
2657 (define_insn_and_split "*extendqihi2"
2658 [(set (match_operand:HI 0 "register_operand" "=d,d")
2660 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2661 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2665 "&& reload_completed && REG_P (operands[1])"
2666 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2667 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
2669 operands[0] = gen_lowpart (SImode, operands[0]);
2670 operands[1] = gen_lowpart (SImode, operands[1]);
2671 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
2672 - GET_MODE_BITSIZE (QImode));
2674 [(set_attr "type" "multi,load")
2675 (set_attr "mode" "SI")
2676 (set_attr "length" "8,*")])
2678 (define_insn "*extendqihi2_seb"
2679 [(set (match_operand:HI 0 "register_operand" "=d,d")
2681 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2686 [(set_attr "type" "signext,load")
2687 (set_attr "mode" "SI")])
2689 (define_insn "extendsfdf2"
2690 [(set (match_operand:DF 0 "register_operand" "=f")
2691 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2692 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2694 [(set_attr "type" "fcvt")
2695 (set_attr "cnv_mode" "S2D")
2696 (set_attr "mode" "DF")])
2699 ;; ....................
2703 ;; ....................
2705 (define_expand "fix_truncdfsi2"
2706 [(set (match_operand:SI 0 "register_operand")
2707 (fix:SI (match_operand:DF 1 "register_operand")))]
2708 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2710 if (!ISA_HAS_TRUNC_W)
2712 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2717 (define_insn "fix_truncdfsi2_insn"
2718 [(set (match_operand:SI 0 "register_operand" "=f")
2719 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2720 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2722 [(set_attr "type" "fcvt")
2723 (set_attr "mode" "DF")
2724 (set_attr "cnv_mode" "D2I")
2725 (set_attr "length" "4")])
2727 (define_insn "fix_truncdfsi2_macro"
2728 [(set (match_operand:SI 0 "register_operand" "=f")
2729 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2730 (clobber (match_scratch:DF 2 "=d"))]
2731 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2734 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2736 return "trunc.w.d %0,%1,%2";
2738 [(set_attr "type" "fcvt")
2739 (set_attr "mode" "DF")
2740 (set_attr "cnv_mode" "D2I")
2741 (set_attr "length" "36")])
2743 (define_expand "fix_truncsfsi2"
2744 [(set (match_operand:SI 0 "register_operand")
2745 (fix:SI (match_operand:SF 1 "register_operand")))]
2748 if (!ISA_HAS_TRUNC_W)
2750 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2755 (define_insn "fix_truncsfsi2_insn"
2756 [(set (match_operand:SI 0 "register_operand" "=f")
2757 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2758 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2760 [(set_attr "type" "fcvt")
2761 (set_attr "mode" "SF")
2762 (set_attr "cnv_mode" "S2I")
2763 (set_attr "length" "4")])
2765 (define_insn "fix_truncsfsi2_macro"
2766 [(set (match_operand:SI 0 "register_operand" "=f")
2767 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2768 (clobber (match_scratch:SF 2 "=d"))]
2769 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2772 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2774 return "trunc.w.s %0,%1,%2";
2776 [(set_attr "type" "fcvt")
2777 (set_attr "mode" "SF")
2778 (set_attr "cnv_mode" "S2I")
2779 (set_attr "length" "36")])
2782 (define_insn "fix_truncdfdi2"
2783 [(set (match_operand:DI 0 "register_operand" "=f")
2784 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2785 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2787 [(set_attr "type" "fcvt")
2788 (set_attr "mode" "DF")
2789 (set_attr "cnv_mode" "D2I")
2790 (set_attr "length" "4")])
2793 (define_insn "fix_truncsfdi2"
2794 [(set (match_operand:DI 0 "register_operand" "=f")
2795 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2796 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2798 [(set_attr "type" "fcvt")
2799 (set_attr "mode" "SF")
2800 (set_attr "cnv_mode" "S2I")
2801 (set_attr "length" "4")])
2804 (define_insn "floatsidf2"
2805 [(set (match_operand:DF 0 "register_operand" "=f")
2806 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2807 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2809 [(set_attr "type" "fcvt")
2810 (set_attr "mode" "DF")
2811 (set_attr "cnv_mode" "I2D")
2812 (set_attr "length" "4")])
2815 (define_insn "floatdidf2"
2816 [(set (match_operand:DF 0 "register_operand" "=f")
2817 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2818 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2820 [(set_attr "type" "fcvt")
2821 (set_attr "mode" "DF")
2822 (set_attr "cnv_mode" "I2D")
2823 (set_attr "length" "4")])
2826 (define_insn "floatsisf2"
2827 [(set (match_operand:SF 0 "register_operand" "=f")
2828 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2831 [(set_attr "type" "fcvt")
2832 (set_attr "mode" "SF")
2833 (set_attr "cnv_mode" "I2S")
2834 (set_attr "length" "4")])
2837 (define_insn "floatdisf2"
2838 [(set (match_operand:SF 0 "register_operand" "=f")
2839 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2840 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2842 [(set_attr "type" "fcvt")
2843 (set_attr "mode" "SF")
2844 (set_attr "cnv_mode" "I2S")
2845 (set_attr "length" "4")])
2848 (define_expand "fixuns_truncdfsi2"
2849 [(set (match_operand:SI 0 "register_operand")
2850 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2851 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2853 rtx reg1 = gen_reg_rtx (DFmode);
2854 rtx reg2 = gen_reg_rtx (DFmode);
2855 rtx reg3 = gen_reg_rtx (SImode);
2856 rtx label1 = gen_label_rtx ();
2857 rtx label2 = gen_label_rtx ();
2858 REAL_VALUE_TYPE offset;
2860 real_2expN (&offset, 31, DFmode);
2862 if (reg1) /* Turn off complaints about unreached code. */
2864 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2865 do_pending_stack_adjust ();
2867 emit_insn (gen_cmpdf (operands[1], reg1));
2868 emit_jump_insn (gen_bge (label1));
2870 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2871 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2872 gen_rtx_LABEL_REF (VOIDmode, label2)));
2875 emit_label (label1);
2876 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2877 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2878 (BITMASK_HIGH, SImode)));
2880 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2881 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2883 emit_label (label2);
2885 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2886 fields, and can't be used for REG_NOTES anyway). */
2887 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2893 (define_expand "fixuns_truncdfdi2"
2894 [(set (match_operand:DI 0 "register_operand")
2895 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2896 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2898 rtx reg1 = gen_reg_rtx (DFmode);
2899 rtx reg2 = gen_reg_rtx (DFmode);
2900 rtx reg3 = gen_reg_rtx (DImode);
2901 rtx label1 = gen_label_rtx ();
2902 rtx label2 = gen_label_rtx ();
2903 REAL_VALUE_TYPE offset;
2905 real_2expN (&offset, 63, DFmode);
2907 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2908 do_pending_stack_adjust ();
2910 emit_insn (gen_cmpdf (operands[1], reg1));
2911 emit_jump_insn (gen_bge (label1));
2913 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2914 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2915 gen_rtx_LABEL_REF (VOIDmode, label2)));
2918 emit_label (label1);
2919 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2920 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
2921 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2923 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2924 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2926 emit_label (label2);
2928 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2929 fields, and can't be used for REG_NOTES anyway). */
2930 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2935 (define_expand "fixuns_truncsfsi2"
2936 [(set (match_operand:SI 0 "register_operand")
2937 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2940 rtx reg1 = gen_reg_rtx (SFmode);
2941 rtx reg2 = gen_reg_rtx (SFmode);
2942 rtx reg3 = gen_reg_rtx (SImode);
2943 rtx label1 = gen_label_rtx ();
2944 rtx label2 = gen_label_rtx ();
2945 REAL_VALUE_TYPE offset;
2947 real_2expN (&offset, 31, SFmode);
2949 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2950 do_pending_stack_adjust ();
2952 emit_insn (gen_cmpsf (operands[1], reg1));
2953 emit_jump_insn (gen_bge (label1));
2955 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2956 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2957 gen_rtx_LABEL_REF (VOIDmode, label2)));
2960 emit_label (label1);
2961 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2962 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
2963 (BITMASK_HIGH, SImode)));
2965 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2966 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2968 emit_label (label2);
2970 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2971 fields, and can't be used for REG_NOTES anyway). */
2972 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2977 (define_expand "fixuns_truncsfdi2"
2978 [(set (match_operand:DI 0 "register_operand")
2979 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2980 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2982 rtx reg1 = gen_reg_rtx (SFmode);
2983 rtx reg2 = gen_reg_rtx (SFmode);
2984 rtx reg3 = gen_reg_rtx (DImode);
2985 rtx label1 = gen_label_rtx ();
2986 rtx label2 = gen_label_rtx ();
2987 REAL_VALUE_TYPE offset;
2989 real_2expN (&offset, 63, SFmode);
2991 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2992 do_pending_stack_adjust ();
2994 emit_insn (gen_cmpsf (operands[1], reg1));
2995 emit_jump_insn (gen_bge (label1));
2997 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2998 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2999 gen_rtx_LABEL_REF (VOIDmode, label2)));
3002 emit_label (label1);
3003 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3004 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3005 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3007 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3008 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3010 emit_label (label2);
3012 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3013 fields, and can't be used for REG_NOTES anyway). */
3014 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
3019 ;; ....................
3023 ;; ....................
3025 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3027 (define_expand "extv"
3028 [(set (match_operand 0 "register_operand")
3029 (sign_extract (match_operand:QI 1 "memory_operand")
3030 (match_operand 2 "immediate_operand")
3031 (match_operand 3 "immediate_operand")))]
3034 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3035 INTVAL (operands[2]),
3036 INTVAL (operands[3])))
3042 (define_expand "extzv"
3043 [(set (match_operand 0 "register_operand")
3044 (zero_extract (match_operand 1 "nonimmediate_operand")
3045 (match_operand 2 "immediate_operand")
3046 (match_operand 3 "immediate_operand")))]
3049 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3050 INTVAL (operands[2]),
3051 INTVAL (operands[3])))
3053 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3054 INTVAL (operands[3])))
3056 if (GET_MODE (operands[0]) == DImode)
3057 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3060 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3068 (define_insn "extzv<mode>"
3069 [(set (match_operand:GPR 0 "register_operand" "=d")
3070 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3071 (match_operand:SI 2 "immediate_operand" "I")
3072 (match_operand:SI 3 "immediate_operand" "I")))]
3073 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3074 INTVAL (operands[3]))"
3075 "<d>ext\t%0,%1,%3,%2"
3076 [(set_attr "type" "arith")
3077 (set_attr "mode" "<MODE>")])
3080 (define_expand "insv"
3081 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3082 (match_operand 1 "immediate_operand")
3083 (match_operand 2 "immediate_operand"))
3084 (match_operand 3 "reg_or_0_operand"))]
3087 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3088 INTVAL (operands[1]),
3089 INTVAL (operands[2])))
3091 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3092 INTVAL (operands[2])))
3094 if (GET_MODE (operands[0]) == DImode)
3095 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3098 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3106 (define_insn "insv<mode>"
3107 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3108 (match_operand:SI 1 "immediate_operand" "I")
3109 (match_operand:SI 2 "immediate_operand" "I"))
3110 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3111 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3112 INTVAL (operands[2]))"
3113 "<d>ins\t%0,%z3,%2,%1"
3114 [(set_attr "type" "arith")
3115 (set_attr "mode" "<MODE>")])
3117 ;; Unaligned word moves generated by the bit field patterns.
3119 ;; As far as the rtl is concerned, both the left-part and right-part
3120 ;; instructions can access the whole field. However, the real operand
3121 ;; refers to just the first or the last byte (depending on endianness).
3122 ;; We therefore use two memory operands to each instruction, one to
3123 ;; describe the rtl effect and one to use in the assembly output.
3125 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3126 ;; This allows us to use the standard length calculations for the "load"
3127 ;; and "store" type attributes.
3129 (define_insn "mov_<load>l"
3130 [(set (match_operand:GPR 0 "register_operand" "=d")
3131 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3132 (match_operand:QI 2 "memory_operand" "m")]
3134 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3136 [(set_attr "type" "load")
3137 (set_attr "mode" "<MODE>")])
3139 (define_insn "mov_<load>r"
3140 [(set (match_operand:GPR 0 "register_operand" "=d")
3141 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3142 (match_operand:QI 2 "memory_operand" "m")
3143 (match_operand:GPR 3 "register_operand" "0")]
3144 UNSPEC_LOAD_RIGHT))]
3145 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3147 [(set_attr "type" "load")
3148 (set_attr "mode" "<MODE>")])
3150 (define_insn "mov_<store>l"
3151 [(set (match_operand:BLK 0 "memory_operand" "=m")
3152 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3153 (match_operand:QI 2 "memory_operand" "m")]
3154 UNSPEC_STORE_LEFT))]
3155 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3157 [(set_attr "type" "store")
3158 (set_attr "mode" "<MODE>")])
3160 (define_insn "mov_<store>r"
3161 [(set (match_operand:BLK 0 "memory_operand" "+m")
3162 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3163 (match_operand:QI 2 "memory_operand" "m")
3165 UNSPEC_STORE_RIGHT))]
3166 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3168 [(set_attr "type" "store")
3169 (set_attr "mode" "<MODE>")])
3171 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3172 ;; The required value is:
3174 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3176 ;; which translates to:
3178 ;; lui op0,%highest(op1)
3179 ;; daddiu op0,op0,%higher(op1)
3181 ;; daddiu op0,op0,%hi(op1)
3184 ;; The split is deferred until after flow2 to allow the peephole2 below
3186 (define_insn_and_split "*lea_high64"
3187 [(set (match_operand:DI 0 "register_operand" "=d")
3188 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3189 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3191 "&& epilogue_completed"
3192 [(set (match_dup 0) (high:DI (match_dup 2)))
3193 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3194 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3195 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3196 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3198 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3199 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3201 [(set_attr "length" "20")])
3203 ;; Use a scratch register to reduce the latency of the above pattern
3204 ;; on superscalar machines. The optimized sequence is:
3206 ;; lui op1,%highest(op2)
3208 ;; daddiu op1,op1,%higher(op2)
3210 ;; daddu op1,op1,op0
3212 [(set (match_operand:DI 1 "register_operand")
3213 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
3214 (match_scratch:DI 0 "d")]
3215 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3216 [(set (match_dup 1) (high:DI (match_dup 3)))
3217 (set (match_dup 0) (high:DI (match_dup 4)))
3218 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3219 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3220 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3222 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3223 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3226 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3227 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
3228 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3229 ;; used once. We can then use the sequence:
3231 ;; lui op0,%highest(op1)
3233 ;; daddiu op0,op0,%higher(op1)
3234 ;; daddiu op2,op2,%lo(op1)
3236 ;; daddu op0,op0,op2
3238 ;; which takes 4 cycles on most superscalar targets.
3239 (define_insn_and_split "*lea64"
3240 [(set (match_operand:DI 0 "register_operand" "=d")
3241 (match_operand:DI 1 "absolute_symbolic_operand" ""))
3242 (clobber (match_scratch:DI 2 "=&d"))]
3243 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3245 "&& reload_completed"
3246 [(set (match_dup 0) (high:DI (match_dup 3)))
3247 (set (match_dup 2) (high:DI (match_dup 4)))
3248 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3249 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3250 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3251 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3253 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3254 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3256 [(set_attr "length" "24")])
3258 ;; Split HIGHs into:
3263 ;; on MIPS16 targets.
3265 [(set (match_operand:SI 0 "register_operand" "=d")
3266 (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
3267 "TARGET_MIPS16 && reload_completed"
3268 [(set (match_dup 0) (match_dup 2))
3269 (set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
3271 operands[2] = mips_unspec_address (operands[1], SYMBOL_32_HIGH);
3274 ;; Insns to fetch a symbol from a big GOT.
3276 (define_insn_and_split "*xgot_hi<mode>"
3277 [(set (match_operand:P 0 "register_operand" "=d")
3278 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3279 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3281 "&& reload_completed"
3282 [(set (match_dup 0) (high:P (match_dup 2)))
3283 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3285 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3286 operands[3] = pic_offset_table_rtx;
3288 [(set_attr "got" "xgot_high")
3289 (set_attr "mode" "<MODE>")])
3291 (define_insn_and_split "*xgot_lo<mode>"
3292 [(set (match_operand:P 0 "register_operand" "=d")
3293 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3294 (match_operand:P 2 "got_disp_operand" "")))]
3295 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3297 "&& reload_completed"
3299 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3300 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3301 [(set_attr "got" "load")
3302 (set_attr "mode" "<MODE>")])
3304 ;; Insns to fetch a symbol from a normal GOT.
3306 (define_insn_and_split "*got_disp<mode>"
3307 [(set (match_operand:P 0 "register_operand" "=d")
3308 (match_operand:P 1 "got_disp_operand" ""))]
3309 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3311 "&& reload_completed"
3313 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3315 operands[2] = pic_offset_table_rtx;
3316 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3318 [(set_attr "got" "load")
3319 (set_attr "mode" "<MODE>")])
3321 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3323 (define_insn_and_split "*got_page<mode>"
3324 [(set (match_operand:P 0 "register_operand" "=d")
3325 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3326 "TARGET_EXPLICIT_RELOCS"
3328 "&& reload_completed"
3330 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3332 operands[2] = pic_offset_table_rtx;
3333 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3335 [(set_attr "got" "load")
3336 (set_attr "mode" "<MODE>")])
3338 ;; Lower-level instructions for loading an address from the GOT.
3339 ;; We could use MEMs, but an unspec gives more optimization
3342 (define_insn "load_got<mode>"
3343 [(set (match_operand:P 0 "register_operand" "=d")
3344 (unspec:P [(match_operand:P 1 "register_operand" "d")
3345 (match_operand:P 2 "immediate_operand" "")]
3348 "<load>\t%0,%R2(%1)"
3349 [(set_attr "type" "load")
3350 (set_attr "mode" "<MODE>")
3351 (set_attr "length" "4")])
3353 ;; Instructions for adding the low 16 bits of an address to a register.
3354 ;; Operand 2 is the address: mips_print_operand works out which relocation
3355 ;; should be applied.
3357 (define_insn "*low<mode>"
3358 [(set (match_operand:P 0 "register_operand" "=d")
3359 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3360 (match_operand:P 2 "immediate_operand" "")))]
3362 "<d>addiu\t%0,%1,%R2"
3363 [(set_attr "type" "arith")
3364 (set_attr "mode" "<MODE>")])
3366 (define_insn "*low<mode>_mips16"
3367 [(set (match_operand:P 0 "register_operand" "=d")
3368 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3369 (match_operand:P 2 "immediate_operand" "")))]
3372 [(set_attr "type" "arith")
3373 (set_attr "mode" "<MODE>")
3374 (set_attr "length" "8")])
3376 ;; Allow combine to split complex const_int load sequences, using operand 2
3377 ;; to store the intermediate results. See move_operand for details.
3379 [(set (match_operand:GPR 0 "register_operand")
3380 (match_operand:GPR 1 "splittable_const_int_operand"))
3381 (clobber (match_operand:GPR 2 "register_operand"))]
3385 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
3389 ;; Likewise, for symbolic operands.
3391 [(set (match_operand:P 0 "register_operand")
3392 (match_operand:P 1))
3393 (clobber (match_operand:P 2 "register_operand"))]
3394 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
3395 [(set (match_dup 0) (match_dup 3))]
3397 mips_split_symbol (operands[2], operands[1],
3398 MAX_MACHINE_MODE, &operands[3]);
3401 ;; 64-bit integer moves
3403 ;; Unlike most other insns, the move insns can't be split with
3404 ;; different predicates, because register spilling and other parts of
3405 ;; the compiler, have memoized the insn number already.
3407 (define_expand "movdi"
3408 [(set (match_operand:DI 0 "")
3409 (match_operand:DI 1 ""))]
3412 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3416 ;; For mips16, we need a special case to handle storing $31 into
3417 ;; memory, since we don't have a constraint to match $31. This
3418 ;; instruction can be generated by save_restore_insns.
3420 (define_insn "*mov<mode>_ra"
3421 [(set (match_operand:GPR 0 "stack_operand" "=m")
3425 [(set_attr "type" "store")
3426 (set_attr "mode" "<MODE>")])
3428 (define_insn "*movdi_32bit"
3429 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3430 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3431 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3432 && (register_operand (operands[0], DImode)
3433 || reg_or_0_operand (operands[1], DImode))"
3434 { return mips_output_move (operands[0], operands[1]); }
3435 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3436 (set_attr "mode" "DI")
3437 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3439 (define_insn "*movdi_gp32_fp64"
3440 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m")
3441 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f"))]
3442 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3443 && (register_operand (operands[0], DImode)
3444 || reg_or_0_operand (operands[1], DImode))"
3445 { return mips_output_move (operands[0], operands[1]); }
3446 [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
3447 (set_attr "mode" "DI")
3448 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3450 (define_insn "*movdi_32bit_mips16"
3451 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3452 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3453 "!TARGET_64BIT && TARGET_MIPS16
3454 && (register_operand (operands[0], DImode)
3455 || register_operand (operands[1], DImode))"
3456 { return mips_output_move (operands[0], operands[1]); }
3457 [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
3458 (set_attr "mode" "DI")
3459 (set_attr "length" "8,8,8,8,12,*,*,8")])
3461 (define_insn "*movdi_64bit"
3462 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3463 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3464 "TARGET_64BIT && !TARGET_MIPS16
3465 && (register_operand (operands[0], DImode)
3466 || reg_or_0_operand (operands[1], DImode))"
3467 { return mips_output_move (operands[0], operands[1]); }
3468 [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3469 (set_attr "mode" "DI")
3470 (set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")])
3472 (define_insn "*movdi_64bit_mips16"
3473 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3474 (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3475 "TARGET_64BIT && TARGET_MIPS16
3476 && (register_operand (operands[0], DImode)
3477 || register_operand (operands[1], DImode))"
3478 { return mips_output_move (operands[0], operands[1]); }
3479 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3480 (set_attr "mode" "DI")
3481 (set_attr_alternative "length"
3485 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3488 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3494 (const_string "*")])])
3497 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3498 ;; when the original load is a 4 byte instruction but the add and the
3499 ;; load are 2 2 byte instructions.
3502 [(set (match_operand:DI 0 "register_operand")
3503 (mem:DI (plus:DI (match_dup 0)
3504 (match_operand:DI 1 "const_int_operand"))))]
3505 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3506 && !TARGET_DEBUG_D_MODE
3507 && REG_P (operands[0])
3508 && M16_REG_P (REGNO (operands[0]))
3509 && GET_CODE (operands[1]) == CONST_INT
3510 && ((INTVAL (operands[1]) < 0
3511 && INTVAL (operands[1]) >= -0x10)
3512 || (INTVAL (operands[1]) >= 32 * 8
3513 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3514 || (INTVAL (operands[1]) >= 0
3515 && INTVAL (operands[1]) < 32 * 8
3516 && (INTVAL (operands[1]) & 7) != 0))"
3517 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3518 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3520 HOST_WIDE_INT val = INTVAL (operands[1]);
3523 operands[2] = const0_rtx;
3524 else if (val >= 32 * 8)
3528 operands[1] = GEN_INT (0x8 + off);
3529 operands[2] = GEN_INT (val - off - 0x8);
3535 operands[1] = GEN_INT (off);
3536 operands[2] = GEN_INT (val - off);
3540 ;; 32-bit Integer moves
3542 ;; Unlike most other insns, the move insns can't be split with
3543 ;; different predicates, because register spilling and other parts of
3544 ;; the compiler, have memoized the insn number already.
3546 (define_expand "movsi"
3547 [(set (match_operand:SI 0 "")
3548 (match_operand:SI 1 ""))]
3551 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3555 ;; The difference between these two is whether or not ints are allowed
3556 ;; in FP registers (off by default, use -mdebugh to enable).
3558 (define_insn "*movsi_internal"
3559 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3560 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3562 && (register_operand (operands[0], SImode)
3563 || reg_or_0_operand (operands[1], SImode))"
3564 { return mips_output_move (operands[0], operands[1]); }
3565 [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3566 (set_attr "mode" "SI")
3567 (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,4,4,4,*,4,*")])
3569 (define_insn "*movsi_mips16"
3570 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
3571 (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
3573 && (register_operand (operands[0], SImode)
3574 || register_operand (operands[1], SImode))"
3575 { return mips_output_move (operands[0], operands[1]); }
3576 [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
3577 (set_attr "mode" "SI")
3578 (set_attr_alternative "length"
3582 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3585 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3591 (const_string "*")])])
3593 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3594 ;; when the original load is a 4 byte instruction but the add and the
3595 ;; load are 2 2 byte instructions.
3598 [(set (match_operand:SI 0 "register_operand")
3599 (mem:SI (plus:SI (match_dup 0)
3600 (match_operand:SI 1 "const_int_operand"))))]
3601 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3602 && REG_P (operands[0])
3603 && M16_REG_P (REGNO (operands[0]))
3604 && GET_CODE (operands[1]) == CONST_INT
3605 && ((INTVAL (operands[1]) < 0
3606 && INTVAL (operands[1]) >= -0x80)
3607 || (INTVAL (operands[1]) >= 32 * 4
3608 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3609 || (INTVAL (operands[1]) >= 0
3610 && INTVAL (operands[1]) < 32 * 4
3611 && (INTVAL (operands[1]) & 3) != 0))"
3612 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3613 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3615 HOST_WIDE_INT val = INTVAL (operands[1]);
3618 operands[2] = const0_rtx;
3619 else if (val >= 32 * 4)
3623 operands[1] = GEN_INT (0x7c + off);
3624 operands[2] = GEN_INT (val - off - 0x7c);
3630 operands[1] = GEN_INT (off);
3631 operands[2] = GEN_INT (val - off);
3635 ;; On the mips16, we can split a load of certain constants into a load
3636 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3640 [(set (match_operand:SI 0 "register_operand")
3641 (match_operand:SI 1 "const_int_operand"))]
3642 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3643 && REG_P (operands[0])
3644 && M16_REG_P (REGNO (operands[0]))
3645 && GET_CODE (operands[1]) == CONST_INT
3646 && INTVAL (operands[1]) >= 0x100
3647 && INTVAL (operands[1]) <= 0xff + 0x7f"
3648 [(set (match_dup 0) (match_dup 1))
3649 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3651 int val = INTVAL (operands[1]);
3653 operands[1] = GEN_INT (0xff);
3654 operands[2] = GEN_INT (val - 0xff);
3657 ;; This insn handles moving CCmode values. It's really just a
3658 ;; slightly simplified copy of movsi_internal2, with additional cases
3659 ;; to move a condition register to a general register and to move
3660 ;; between the general registers and the floating point registers.
3662 (define_insn "movcc"
3663 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3664 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3665 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3666 { return mips_output_move (operands[0], operands[1]); }
3667 [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
3668 (set_attr "mode" "SI")
3669 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3671 ;; Reload condition code registers. reload_incc and reload_outcc
3672 ;; both handle moves from arbitrary operands into condition code
3673 ;; registers. reload_incc handles the more common case in which
3674 ;; a source operand is constrained to be in a condition-code
3675 ;; register, but has not been allocated to one.
3677 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3678 ;; constraints do not include 'z'. reload_outcc handles the case
3679 ;; when such an operand is allocated to a condition-code register.
3681 ;; Note that reloads from a condition code register to some
3682 ;; other location can be done using ordinary moves. Moving
3683 ;; into a GPR takes a single movcc, moving elsewhere takes
3684 ;; two. We can leave these cases to the generic reload code.
3685 (define_expand "reload_incc"
3686 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3687 (match_operand:CC 1 "general_operand" ""))
3688 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3689 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3691 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
3695 (define_expand "reload_outcc"
3696 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3697 (match_operand:CC 1 "register_operand" ""))
3698 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3699 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3701 mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
3705 ;; MIPS4 supports loading and storing a floating point register from
3706 ;; the sum of two general registers. We use two versions for each of
3707 ;; these four instructions: one where the two general registers are
3708 ;; SImode, and one where they are DImode. This is because general
3709 ;; registers will be in SImode when they hold 32-bit values, but,
3710 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3711 ;; instructions will still work correctly.
3713 ;; ??? Perhaps it would be better to support these instructions by
3714 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3715 ;; these instructions can only be used to load and store floating
3716 ;; point registers, that would probably cause trouble in reload.
3718 (define_insn "*<ANYF:loadx>_<P:mode>"
3719 [(set (match_operand:ANYF 0 "register_operand" "=f")
3720 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3721 (match_operand:P 2 "register_operand" "d"))))]
3723 "<ANYF:loadx>\t%0,%1(%2)"
3724 [(set_attr "type" "fpidxload")
3725 (set_attr "mode" "<ANYF:UNITMODE>")])
3727 (define_insn "*<ANYF:storex>_<P:mode>"
3728 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3729 (match_operand:P 2 "register_operand" "d")))
3730 (match_operand:ANYF 0 "register_operand" "f"))]
3732 "<ANYF:storex>\t%0,%1(%2)"
3733 [(set_attr "type" "fpidxstore")
3734 (set_attr "mode" "<ANYF:UNITMODE>")])
3736 ;; Scaled indexed address load.
3737 ;; Per md.texi, we only need to look for a pattern with multiply in the
3738 ;; address expression, not shift.
3740 (define_insn "*lwxs"
3741 [(set (match_operand:SI 0 "register_operand" "=d")
3742 (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
3744 (match_operand:SI 2 "register_operand" "d"))))]
3747 [(set_attr "type" "load")
3748 (set_attr "mode" "SI")
3749 (set_attr "length" "4")])
3751 ;; 16-bit Integer moves
3753 ;; Unlike most other insns, the move insns can't be split with
3754 ;; different predicates, because register spilling and other parts of
3755 ;; the compiler, have memoized the insn number already.
3756 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3758 (define_expand "movhi"
3759 [(set (match_operand:HI 0 "")
3760 (match_operand:HI 1 ""))]
3763 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3767 (define_insn "*movhi_internal"
3768 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*x")
3769 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d"))]
3771 && (register_operand (operands[0], HImode)
3772 || reg_or_0_operand (operands[1], HImode))"
3779 [(set_attr "type" "move,arith,load,store,mthilo")
3780 (set_attr "mode" "HI")
3781 (set_attr "length" "4,4,*,*,4")])
3783 (define_insn "*movhi_mips16"
3784 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3785 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3787 && (register_operand (operands[0], HImode)
3788 || register_operand (operands[1], HImode))"
3797 [(set_attr "type" "move,move,move,arith,arith,load,store")
3798 (set_attr "mode" "HI")
3799 (set_attr_alternative "length"
3803 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3806 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3810 (const_string "*")])])
3813 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3814 ;; when the original load is a 4 byte instruction but the add and the
3815 ;; load are 2 2 byte instructions.
3818 [(set (match_operand:HI 0 "register_operand")
3819 (mem:HI (plus:SI (match_dup 0)
3820 (match_operand:SI 1 "const_int_operand"))))]
3821 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3822 && REG_P (operands[0])
3823 && M16_REG_P (REGNO (operands[0]))
3824 && GET_CODE (operands[1]) == CONST_INT
3825 && ((INTVAL (operands[1]) < 0
3826 && INTVAL (operands[1]) >= -0x80)
3827 || (INTVAL (operands[1]) >= 32 * 2
3828 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3829 || (INTVAL (operands[1]) >= 0
3830 && INTVAL (operands[1]) < 32 * 2
3831 && (INTVAL (operands[1]) & 1) != 0))"
3832 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3833 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3835 HOST_WIDE_INT val = INTVAL (operands[1]);
3838 operands[2] = const0_rtx;
3839 else if (val >= 32 * 2)
3843 operands[1] = GEN_INT (0x7e + off);
3844 operands[2] = GEN_INT (val - off - 0x7e);
3850 operands[1] = GEN_INT (off);
3851 operands[2] = GEN_INT (val - off);
3855 ;; 8-bit Integer moves
3857 ;; Unlike most other insns, the move insns can't be split with
3858 ;; different predicates, because register spilling and other parts of
3859 ;; the compiler, have memoized the insn number already.
3860 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3862 (define_expand "movqi"
3863 [(set (match_operand:QI 0 "")
3864 (match_operand:QI 1 ""))]
3867 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3871 (define_insn "*movqi_internal"
3872 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*x")
3873 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d"))]
3875 && (register_operand (operands[0], QImode)
3876 || reg_or_0_operand (operands[1], QImode))"
3883 [(set_attr "type" "move,arith,load,store,mthilo")
3884 (set_attr "mode" "QI")
3885 (set_attr "length" "4,4,*,*,4")])
3887 (define_insn "*movqi_mips16"
3888 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3889 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3891 && (register_operand (operands[0], QImode)
3892 || register_operand (operands[1], QImode))"
3901 [(set_attr "type" "move,move,move,arith,arith,load,store")
3902 (set_attr "mode" "QI")
3903 (set_attr "length" "4,4,4,4,8,*,*")])
3905 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3906 ;; when the original load is a 4 byte instruction but the add and the
3907 ;; load are 2 2 byte instructions.
3910 [(set (match_operand:QI 0 "register_operand")
3911 (mem:QI (plus:SI (match_dup 0)
3912 (match_operand:SI 1 "const_int_operand"))))]
3913 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3914 && REG_P (operands[0])
3915 && M16_REG_P (REGNO (operands[0]))
3916 && GET_CODE (operands[1]) == CONST_INT
3917 && ((INTVAL (operands[1]) < 0
3918 && INTVAL (operands[1]) >= -0x80)
3919 || (INTVAL (operands[1]) >= 32
3920 && INTVAL (operands[1]) <= 31 + 0x7f))"
3921 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3922 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3924 HOST_WIDE_INT val = INTVAL (operands[1]);
3927 operands[2] = const0_rtx;
3930 operands[1] = GEN_INT (0x7f);
3931 operands[2] = GEN_INT (val - 0x7f);
3935 ;; 32-bit floating point moves
3937 (define_expand "movsf"
3938 [(set (match_operand:SF 0 "")
3939 (match_operand:SF 1 ""))]
3942 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3946 (define_insn "*movsf_hardfloat"
3947 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3948 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3950 && (register_operand (operands[0], SFmode)
3951 || reg_or_0_operand (operands[1], SFmode))"
3952 { return mips_output_move (operands[0], operands[1]); }
3953 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3954 (set_attr "mode" "SF")
3955 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3957 (define_insn "*movsf_softfloat"
3958 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3959 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3960 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3961 && (register_operand (operands[0], SFmode)
3962 || reg_or_0_operand (operands[1], SFmode))"
3963 { return mips_output_move (operands[0], operands[1]); }
3964 [(set_attr "type" "move,load,store")
3965 (set_attr "mode" "SF")
3966 (set_attr "length" "4,*,*")])
3968 (define_insn "*movsf_mips16"
3969 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3970 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3972 && (register_operand (operands[0], SFmode)
3973 || register_operand (operands[1], SFmode))"
3974 { return mips_output_move (operands[0], operands[1]); }
3975 [(set_attr "type" "move,move,move,load,store")
3976 (set_attr "mode" "SF")
3977 (set_attr "length" "4,4,4,*,*")])
3980 ;; 64-bit floating point moves
3982 (define_expand "movdf"
3983 [(set (match_operand:DF 0 "")
3984 (match_operand:DF 1 ""))]
3987 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3991 (define_insn "*movdf_hardfloat_64bit"
3992 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3993 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3994 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3995 && (register_operand (operands[0], DFmode)
3996 || reg_or_0_operand (operands[1], DFmode))"
3997 { return mips_output_move (operands[0], operands[1]); }
3998 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
3999 (set_attr "mode" "DF")
4000 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4002 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
4003 (define_insn "*movdf_hardfloat_32bit"
4004 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4005 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4006 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
4007 && (register_operand (operands[0], DFmode)
4008 || reg_or_0_operand (operands[1], DFmode))"
4009 { return mips_output_move (operands[0], operands[1]); }
4010 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4011 (set_attr "mode" "DF")
4012 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
4014 (define_insn "*movdf_softfloat"
4015 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
4016 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
4017 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4018 && (register_operand (operands[0], DFmode)
4019 || reg_or_0_operand (operands[1], DFmode))"
4020 { return mips_output_move (operands[0], operands[1]); }
4021 [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
4022 (set_attr "mode" "DF")
4023 (set_attr "length" "8,*,*,4,4,4")])
4025 (define_insn "*movdf_mips16"
4026 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4027 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4029 && (register_operand (operands[0], DFmode)
4030 || register_operand (operands[1], DFmode))"
4031 { return mips_output_move (operands[0], operands[1]); }
4032 [(set_attr "type" "multi,multi,multi,load,store")
4033 (set_attr "mode" "DF")
4034 (set_attr "length" "8,8,8,*,*")])
4036 ;; 128-bit floating point moves
4038 (define_expand "movtf"
4039 [(set (match_operand:TF 0 "")
4040 (match_operand:TF 1 ""))]
4043 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4047 ;; This pattern handles both hard- and soft-float cases.
4048 (define_insn_and_split "*movtf_internal"
4049 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,R,f,dR")
4050 (match_operand:TF 1 "move_operand" "dGR,dG,dGR,f"))]
4053 "&& reload_completed"
4056 mips_split_doubleword_move (operands[0], operands[1]);
4059 [(set_attr "type" "multi")
4060 (set_attr "length" "16")])
4063 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4064 (match_operand:MOVE64 1 "move_operand"))]
4065 "reload_completed && !TARGET_64BIT
4066 && mips_split_64bit_move_p (operands[0], operands[1])"
4069 mips_split_doubleword_move (operands[0], operands[1]);
4073 ;; When generating mips16 code, split moves of negative constants into
4074 ;; a positive "li" followed by a negation.
4076 [(set (match_operand 0 "register_operand")
4077 (match_operand 1 "const_int_operand"))]
4078 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4082 (neg:SI (match_dup 2)))]
4084 operands[2] = gen_lowpart (SImode, operands[0]);
4085 operands[3] = GEN_INT (-INTVAL (operands[1]));
4088 ;; 64-bit paired-single floating point moves
4090 (define_expand "movv2sf"
4091 [(set (match_operand:V2SF 0)
4092 (match_operand:V2SF 1))]
4093 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4095 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4099 (define_insn "movv2sf_hardfloat_64bit"
4100 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4101 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4103 && TARGET_PAIRED_SINGLE_FLOAT
4105 && (register_operand (operands[0], V2SFmode)
4106 || reg_or_0_operand (operands[1], V2SFmode))"
4107 { return mips_output_move (operands[0], operands[1]); }
4108 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4109 (set_attr "mode" "SF")
4110 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
4112 (define_insn "movv2sf_hardfloat_32bit"
4113 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4114 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4116 && TARGET_PAIRED_SINGLE_FLOAT
4118 && (register_operand (operands[0], V2SFmode)
4119 || reg_or_0_operand (operands[1], V2SFmode))"
4120 { return mips_output_move (operands[0], operands[1]); }
4121 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4122 (set_attr "mode" "SF")
4123 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
4125 ;; The HI and LO registers are not truly independent. If we move an mthi
4126 ;; instruction before an mflo instruction, it will make the result of the
4127 ;; mflo unpredictable. The same goes for mtlo and mfhi.
4129 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
4130 ;; Operand 1 is the register we want, operand 2 is the other one.
4132 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
4133 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
4134 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
4136 (define_expand "mfhilo_<mode>"
4137 [(set (match_operand:GPR 0 "register_operand")
4138 (unspec:GPR [(match_operand:GPR 1 "register_operand")
4139 (match_operand:GPR 2 "register_operand")]
4142 (define_insn "*mfhilo_<mode>"
4143 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4144 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4145 (match_operand:GPR 2 "register_operand" "l,h")]
4149 [(set_attr "type" "mfhilo")
4150 (set_attr "mode" "<MODE>")])
4152 (define_insn "*mfhilo_<mode>_macc"
4153 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4154 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
4155 (match_operand:GPR 2 "register_operand" "l,h")]
4161 [(set_attr "type" "mfhilo")
4162 (set_attr "mode" "<MODE>")])
4164 ;; Emit a doubleword move in which exactly one of the operands is
4165 ;; a floating-point register. We can't just emit two normal moves
4166 ;; because of the constraints imposed by the FPU register model;
4167 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4168 ;; the FPR whole and use special patterns to refer to each word of
4169 ;; the other operand.
4171 (define_expand "move_doubleword_fpr<mode>"
4172 [(set (match_operand:SPLITF 0)
4173 (match_operand:SPLITF 1))]
4176 if (FP_REG_RTX_P (operands[0]))
4178 rtx low = mips_subword (operands[1], 0);
4179 rtx high = mips_subword (operands[1], 1);
4180 emit_insn (gen_load_low<mode> (operands[0], low));
4182 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4184 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4188 rtx low = mips_subword (operands[0], 0);
4189 rtx high = mips_subword (operands[0], 1);
4190 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4192 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4194 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4199 ;; Load the low word of operand 0 with operand 1.
4200 (define_insn "load_low<mode>"
4201 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4202 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4206 operands[0] = mips_subword (operands[0], 0);
4207 return mips_output_move (operands[0], operands[1]);
4209 [(set_attr "type" "mtc,fpload")
4210 (set_attr "mode" "<HALFMODE>")])
4212 ;; Load the high word of operand 0 from operand 1, preserving the value
4214 (define_insn "load_high<mode>"
4215 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4216 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4217 (match_operand:SPLITF 2 "register_operand" "0,0")]
4221 operands[0] = mips_subword (operands[0], 1);
4222 return mips_output_move (operands[0], operands[1]);
4224 [(set_attr "type" "mtc,fpload")
4225 (set_attr "mode" "<HALFMODE>")])
4227 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4228 ;; high word and 0 to store the low word.
4229 (define_insn "store_word<mode>"
4230 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4231 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4232 (match_operand 2 "const_int_operand")]
4233 UNSPEC_STORE_WORD))]
4236 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4237 return mips_output_move (operands[0], operands[1]);
4239 [(set_attr "type" "mfc,fpstore")
4240 (set_attr "mode" "<HALFMODE>")])
4242 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4243 ;; value in the low word.
4244 (define_insn "mthc1<mode>"
4245 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4246 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ")
4247 (match_operand:SPLITF 2 "register_operand" "0")]
4249 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4251 [(set_attr "type" "mtc")
4252 (set_attr "mode" "<HALFMODE>")])
4254 ;; Move high word of operand 1 to operand 0 using mfhc1.
4255 (define_insn "mfhc1<mode>"
4256 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4257 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4259 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4261 [(set_attr "type" "mfc")
4262 (set_attr "mode" "<HALFMODE>")])
4264 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4265 (define_expand "load_const_gp"
4266 [(set (match_operand 0 "register_operand" "=d")
4267 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4269 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4270 ;; of _gp from the start of this function. Operand 1 is the incoming
4271 ;; function address.
4272 (define_insn_and_split "loadgp_newabi"
4273 [(unspec_volatile [(match_operand 0 "" "")
4274 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
4275 "mips_current_loadgp_style () == LOADGP_NEWABI"
4278 [(set (match_dup 2) (match_dup 3))
4279 (set (match_dup 2) (match_dup 4))
4280 (set (match_dup 2) (match_dup 5))]
4282 operands[2] = pic_offset_table_rtx;
4283 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
4284 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
4285 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
4287 [(set_attr "length" "12")])
4289 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4290 (define_insn_and_split "loadgp_absolute"
4291 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4292 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4297 mips_emit_move (pic_offset_table_rtx, operands[0]);
4300 [(set_attr "length" "8")])
4302 ;; The use of gp is hidden when not using explicit relocations.
4303 ;; This blockage instruction prevents the gp load from being
4304 ;; scheduled after an implicit use of gp. It also prevents
4305 ;; the load from being deleted as dead.
4306 (define_insn "loadgp_blockage"
4307 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4310 [(set_attr "type" "unknown")
4311 (set_attr "mode" "none")
4312 (set_attr "length" "0")])
4314 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4315 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4316 (define_insn "loadgp_rtp"
4317 [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
4318 (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4319 "mips_current_loadgp_style () == LOADGP_RTP"
4321 [(set_attr "length" "12")])
4324 [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
4325 (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4326 "mips_current_loadgp_style () == LOADGP_RTP"
4327 [(set (match_dup 2) (high:P (match_dup 3)))
4328 (set (match_dup 2) (unspec:P [(match_dup 2)
4329 (match_dup 3)] UNSPEC_LOAD_GOT))
4330 (set (match_dup 2) (unspec:P [(match_dup 2)
4331 (match_dup 4)] UNSPEC_LOAD_GOT))]
4333 operands[2] = pic_offset_table_rtx;
4334 operands[3] = mips_unspec_address (operands[0], SYMBOL_ABSOLUTE);
4335 operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
4338 ;; Emit a .cprestore directive, which normally expands to a single store
4339 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4340 ;; code so that jals inside inline asms will work correctly.
4341 (define_insn "cprestore"
4342 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")
4347 if (set_nomacro && which_alternative == 1)
4348 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4350 return ".cprestore\t%0";
4352 [(set_attr "type" "store")
4353 (set_attr "length" "4,12")])
4355 ;; Expand in-line code to clear the instruction cache between operand[0] and
4357 (define_expand "clear_cache"
4358 [(match_operand 0 "pmode_register_operand")
4359 (match_operand 1 "pmode_register_operand")]
4365 mips_expand_synci_loop (operands[0], operands[1]);
4366 emit_insn (gen_sync ());
4367 emit_insn (gen_clear_hazard ());
4369 else if (mips_cache_flush_func && mips_cache_flush_func[0])
4371 rtx len = gen_reg_rtx (Pmode);
4372 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
4373 MIPS_ICACHE_SYNC (operands[0], len);
4379 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
4383 (define_insn "synci"
4384 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
4389 (define_insn "rdhwr"
4390 [(set (match_operand:SI 0 "register_operand" "=d")
4391 (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
4396 (define_insn "clear_hazard"
4397 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
4398 (clobber (reg:SI 31))]
4401 return ".set\tpush\n"
4402 "\t.set\tnoreorder\n"
4406 "1:\taddiu\t$31,$31,12\n"
4411 [(set_attr "length" "20")])
4413 ;; Atomic memory operations.
4415 (define_insn "memory_barrier"
4416 [(set (mem:BLK (scratch))
4417 (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))]
4421 (define_insn "sync_compare_and_swap<mode>"
4422 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
4423 (match_operand:GPR 1 "memory_operand" "+R,R"))
4425 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
4426 (match_operand:GPR 3 "arith_operand" "I,d")]
4427 UNSPEC_COMPARE_AND_SWAP))]
4430 if (which_alternative == 0)
4431 return MIPS_COMPARE_AND_SWAP ("<d>", "li");
4433 return MIPS_COMPARE_AND_SWAP ("<d>", "move");
4435 [(set_attr "length" "32")])
4437 (define_insn "sync_add<mode>"
4438 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4439 (unspec_volatile:GPR
4440 [(plus:GPR (match_dup 0)
4441 (match_operand:GPR 1 "arith_operand" "I,d"))]
4442 UNSPEC_SYNC_OLD_OP))]
4445 if (which_alternative == 0)
4446 return MIPS_SYNC_OP ("<d>", "<d>addiu");
4448 return MIPS_SYNC_OP ("<d>", "<d>addu");
4450 [(set_attr "length" "28")])
4452 (define_insn "sync_sub<mode>"
4453 [(set (match_operand:GPR 0 "memory_operand" "+R")
4454 (unspec_volatile:GPR
4455 [(minus:GPR (match_dup 0)
4456 (match_operand:GPR 1 "register_operand" "d"))]
4457 UNSPEC_SYNC_OLD_OP))]
4460 return MIPS_SYNC_OP ("<d>", "<d>subu");
4462 [(set_attr "length" "28")])
4464 (define_insn "sync_old_add<mode>"
4465 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4466 (match_operand:GPR 1 "memory_operand" "+R,R"))
4468 (unspec_volatile:GPR
4469 [(plus:GPR (match_dup 1)
4470 (match_operand:GPR 2 "arith_operand" "I,d"))]
4471 UNSPEC_SYNC_OLD_OP))]
4474 if (which_alternative == 0)
4475 return MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
4477 return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
4479 [(set_attr "length" "28")])
4481 (define_insn "sync_old_sub<mode>"
4482 [(set (match_operand:GPR 0 "register_operand" "=&d")
4483 (match_operand:GPR 1 "memory_operand" "+R"))
4485 (unspec_volatile:GPR
4486 [(minus:GPR (match_dup 1)
4487 (match_operand:GPR 2 "register_operand" "d"))]
4488 UNSPEC_SYNC_OLD_OP))]
4491 return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
4493 [(set_attr "length" "28")])
4495 (define_insn "sync_new_add<mode>"
4496 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4497 (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
4498 (match_operand:GPR 2 "arith_operand" "I,d")))
4500 (unspec_volatile:GPR
4501 [(plus:GPR (match_dup 1) (match_dup 2))]
4502 UNSPEC_SYNC_NEW_OP))]
4505 if (which_alternative == 0)
4506 return MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
4508 return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
4510 [(set_attr "length" "28")])
4512 (define_insn "sync_new_sub<mode>"
4513 [(set (match_operand:GPR 0 "register_operand" "=&d")
4514 (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
4515 (match_operand:GPR 2 "register_operand" "d")))
4517 (unspec_volatile:GPR
4518 [(minus:GPR (match_dup 1) (match_dup 2))]
4519 UNSPEC_SYNC_NEW_OP))]
4522 return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
4524 [(set_attr "length" "28")])
4526 (define_insn "sync_<optab><mode>"
4527 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4528 (unspec_volatile:GPR
4529 [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
4531 UNSPEC_SYNC_OLD_OP))]
4534 if (which_alternative == 0)
4535 return MIPS_SYNC_OP ("<d>", "<immediate_insn>");
4537 return MIPS_SYNC_OP ("<d>", "<insn>");
4539 [(set_attr "length" "28")])
4541 (define_insn "sync_old_<optab><mode>"
4542 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4543 (match_operand:GPR 1 "memory_operand" "+R,R"))
4545 (unspec_volatile:GPR
4546 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4548 UNSPEC_SYNC_OLD_OP))]
4551 if (which_alternative == 0)
4552 return MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
4554 return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
4556 [(set_attr "length" "28")])
4558 (define_insn "sync_new_<optab><mode>"
4559 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4560 (match_operand:GPR 1 "memory_operand" "+R,R"))
4562 (unspec_volatile:GPR
4563 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
4565 UNSPEC_SYNC_NEW_OP))]
4568 if (which_alternative == 0)
4569 return MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
4571 return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
4573 [(set_attr "length" "28")])
4575 (define_insn "sync_nand<mode>"
4576 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
4577 (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
4578 UNSPEC_SYNC_OLD_OP))]
4581 if (which_alternative == 0)
4582 return MIPS_SYNC_NAND ("<d>", "andi");
4584 return MIPS_SYNC_NAND ("<d>", "and");
4586 [(set_attr "length" "32")])
4588 (define_insn "sync_old_nand<mode>"
4589 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4590 (match_operand:GPR 1 "memory_operand" "+R,R"))
4592 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4593 UNSPEC_SYNC_OLD_OP))]
4596 if (which_alternative == 0)
4597 return MIPS_SYNC_OLD_NAND ("<d>", "andi");
4599 return MIPS_SYNC_OLD_NAND ("<d>", "and");
4601 [(set_attr "length" "32")])
4603 (define_insn "sync_new_nand<mode>"
4604 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4605 (match_operand:GPR 1 "memory_operand" "+R,R"))
4607 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
4608 UNSPEC_SYNC_NEW_OP))]
4611 if (which_alternative == 0)
4612 return MIPS_SYNC_NEW_NAND ("<d>", "andi");
4614 return MIPS_SYNC_NEW_NAND ("<d>", "and");
4616 [(set_attr "length" "32")])
4618 (define_insn "sync_lock_test_and_set<mode>"
4619 [(set (match_operand:GPR 0 "register_operand" "=d,&d")
4620 (match_operand:GPR 1 "memory_operand" "+R,R"))
4622 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
4623 UNSPEC_SYNC_EXCHANGE))]
4626 if (which_alternative == 0)
4627 return MIPS_SYNC_EXCHANGE ("<d>", "li");
4629 return MIPS_SYNC_EXCHANGE ("<d>", "move");
4631 [(set_attr "length" "24")])
4633 ;; Block moves, see mips.c for more details.
4634 ;; Argument 0 is the destination
4635 ;; Argument 1 is the source
4636 ;; Argument 2 is the length
4637 ;; Argument 3 is the alignment
4639 (define_expand "movmemsi"
4640 [(parallel [(set (match_operand:BLK 0 "general_operand")
4641 (match_operand:BLK 1 "general_operand"))
4642 (use (match_operand:SI 2 ""))
4643 (use (match_operand:SI 3 "const_int_operand"))])]
4644 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4646 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4653 ;; ....................
4657 ;; ....................
4659 (define_expand "<optab><mode>3"
4660 [(set (match_operand:GPR 0 "register_operand")
4661 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4662 (match_operand:SI 2 "arith_operand")))]
4665 /* On the mips16, a shift of more than 8 is a four byte instruction,
4666 so, for a shift between 8 and 16, it is just as fast to do two
4667 shifts of 8 or less. If there is a lot of shifting going on, we
4668 may win in CSE. Otherwise combine will put the shifts back
4669 together again. This can be called by mips_function_arg, so we must
4670 be careful not to allocate a new register if we've reached the
4674 && GET_CODE (operands[2]) == CONST_INT
4675 && INTVAL (operands[2]) > 8
4676 && INTVAL (operands[2]) <= 16
4677 && !reload_in_progress
4678 && !reload_completed)
4680 rtx temp = gen_reg_rtx (<MODE>mode);
4682 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4683 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4684 GEN_INT (INTVAL (operands[2]) - 8)));
4689 (define_insn "*<optab><mode>3"
4690 [(set (match_operand:GPR 0 "register_operand" "=d")
4691 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4692 (match_operand:SI 2 "arith_operand" "dI")))]
4695 if (GET_CODE (operands[2]) == CONST_INT)
4696 operands[2] = GEN_INT (INTVAL (operands[2])
4697 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4699 return "<d><insn>\t%0,%1,%2";
4701 [(set_attr "type" "shift")
4702 (set_attr "mode" "<MODE>")])
4704 (define_insn "*<optab>si3_extend"
4705 [(set (match_operand:DI 0 "register_operand" "=d")
4707 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4708 (match_operand:SI 2 "arith_operand" "dI"))))]
4709 "TARGET_64BIT && !TARGET_MIPS16"
4711 if (GET_CODE (operands[2]) == CONST_INT)
4712 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4714 return "<insn>\t%0,%1,%2";
4716 [(set_attr "type" "shift")
4717 (set_attr "mode" "SI")])
4719 (define_insn "*<optab>si3_mips16"
4720 [(set (match_operand:SI 0 "register_operand" "=d,d")
4721 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4722 (match_operand:SI 2 "arith_operand" "d,I")))]
4725 if (which_alternative == 0)
4726 return "<insn>\t%0,%2";
4728 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4729 return "<insn>\t%0,%1,%2";
4731 [(set_attr "type" "shift")
4732 (set_attr "mode" "SI")
4733 (set_attr_alternative "length"
4735 (if_then_else (match_operand 2 "m16_uimm3_b")
4739 ;; We need separate DImode MIPS16 patterns because of the irregularity
4741 (define_insn "*ashldi3_mips16"
4742 [(set (match_operand:DI 0 "register_operand" "=d,d")
4743 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4744 (match_operand:SI 2 "arith_operand" "d,I")))]
4745 "TARGET_64BIT && TARGET_MIPS16"
4747 if (which_alternative == 0)
4748 return "dsll\t%0,%2";
4750 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4751 return "dsll\t%0,%1,%2";
4753 [(set_attr "type" "shift")
4754 (set_attr "mode" "DI")
4755 (set_attr_alternative "length"
4757 (if_then_else (match_operand 2 "m16_uimm3_b")
4761 (define_insn "*ashrdi3_mips16"
4762 [(set (match_operand:DI 0 "register_operand" "=d,d")
4763 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4764 (match_operand:SI 2 "arith_operand" "d,I")))]
4765 "TARGET_64BIT && TARGET_MIPS16"
4767 if (GET_CODE (operands[2]) == CONST_INT)
4768 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4770 return "dsra\t%0,%2";
4772 [(set_attr "type" "shift")
4773 (set_attr "mode" "DI")
4774 (set_attr_alternative "length"
4776 (if_then_else (match_operand 2 "m16_uimm3_b")
4780 (define_insn "*lshrdi3_mips16"
4781 [(set (match_operand:DI 0 "register_operand" "=d,d")
4782 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4783 (match_operand:SI 2 "arith_operand" "d,I")))]
4784 "TARGET_64BIT && TARGET_MIPS16"
4786 if (GET_CODE (operands[2]) == CONST_INT)
4787 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4789 return "dsrl\t%0,%2";
4791 [(set_attr "type" "shift")
4792 (set_attr "mode" "DI")
4793 (set_attr_alternative "length"
4795 (if_then_else (match_operand 2 "m16_uimm3_b")
4799 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4802 [(set (match_operand:GPR 0 "register_operand")
4803 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4804 (match_operand:GPR 2 "const_int_operand")))]
4805 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4806 && GET_CODE (operands[2]) == CONST_INT
4807 && INTVAL (operands[2]) > 8
4808 && INTVAL (operands[2]) <= 16"
4809 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4810 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4811 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4813 ;; If we load a byte on the mips16 as a bitfield, the resulting
4814 ;; sequence of instructions is too complicated for combine, because it
4815 ;; involves four instructions: a load, a shift, a constant load into a
4816 ;; register, and an and (the key problem here is that the mips16 does
4817 ;; not have and immediate). We recognize a shift of a load in order
4818 ;; to make it simple enough for combine to understand.
4820 ;; The length here is the worst case: the length of the split version
4821 ;; will be more accurate.
4822 (define_insn_and_split ""
4823 [(set (match_operand:SI 0 "register_operand" "=d")
4824 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4825 (match_operand:SI 2 "immediate_operand" "I")))]
4829 [(set (match_dup 0) (match_dup 1))
4830 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4832 [(set_attr "type" "load")
4833 (set_attr "mode" "SI")
4834 (set_attr "length" "16")])
4836 (define_insn "rotr<mode>3"
4837 [(set (match_operand:GPR 0 "register_operand" "=d")
4838 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4839 (match_operand:SI 2 "arith_operand" "dI")))]
4842 if (GET_CODE (operands[2]) == CONST_INT)
4843 gcc_assert (INTVAL (operands[2]) >= 0
4844 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4846 return "<d>ror\t%0,%1,%2";
4848 [(set_attr "type" "shift")
4849 (set_attr "mode" "<MODE>")])
4852 ;; ....................
4856 ;; ....................
4858 ;; Flow here is rather complex:
4860 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4861 ;; into cmp_operands[] but generates no RTL.
4863 ;; 2) The appropriate branch define_expand is called, which then
4864 ;; creates the appropriate RTL for the comparison and branch.
4865 ;; Different CC modes are used, based on what type of branch is
4866 ;; done, so that we can constrain things appropriately. There
4867 ;; are assumptions in the rest of GCC that break if we fold the
4868 ;; operands into the branches for integer operations, and use cc0
4869 ;; for floating point, so we use the fp status register instead.
4870 ;; If needed, an appropriate temporary is created to hold the
4871 ;; of the integer compare.
4873 (define_expand "cmp<mode>"
4875 (compare:CC (match_operand:GPR 0 "register_operand")
4876 (match_operand:GPR 1 "nonmemory_operand")))]
4879 cmp_operands[0] = operands[0];
4880 cmp_operands[1] = operands[1];
4884 (define_expand "cmp<mode>"
4886 (compare:CC (match_operand:SCALARF 0 "register_operand")
4887 (match_operand:SCALARF 1 "register_operand")))]
4890 cmp_operands[0] = operands[0];
4891 cmp_operands[1] = operands[1];
4896 ;; ....................
4898 ;; CONDITIONAL BRANCHES
4900 ;; ....................
4902 ;; Conditional branches on floating-point equality tests.
4904 (define_insn "*branch_fp"
4907 (match_operator 0 "equality_operator"
4908 [(match_operand:CC 2 "register_operand" "z")
4910 (label_ref (match_operand 1 "" ""))
4914 return mips_output_conditional_branch (insn, operands,
4915 MIPS_BRANCH ("b%F0", "%Z2%1"),
4916 MIPS_BRANCH ("b%W0", "%Z2%1"));
4918 [(set_attr "type" "branch")
4919 (set_attr "mode" "none")])
4921 (define_insn "*branch_fp_inverted"
4924 (match_operator 0 "equality_operator"
4925 [(match_operand:CC 2 "register_operand" "z")
4928 (label_ref (match_operand 1 "" ""))))]
4931 return mips_output_conditional_branch (insn, operands,
4932 MIPS_BRANCH ("b%W0", "%Z2%1"),
4933 MIPS_BRANCH ("b%F0", "%Z2%1"));
4935 [(set_attr "type" "branch")
4936 (set_attr "mode" "none")])
4938 ;; Conditional branches on ordered comparisons with zero.
4940 (define_insn "*branch_order<mode>"
4943 (match_operator 0 "order_operator"
4944 [(match_operand:GPR 2 "register_operand" "d")
4946 (label_ref (match_operand 1 "" ""))
4949 { return mips_output_order_conditional_branch (insn, operands, false); }
4950 [(set_attr "type" "branch")
4951 (set_attr "mode" "none")])
4953 (define_insn "*branch_order<mode>_inverted"
4956 (match_operator 0 "order_operator"
4957 [(match_operand:GPR 2 "register_operand" "d")
4960 (label_ref (match_operand 1 "" ""))))]
4962 { return mips_output_order_conditional_branch (insn, operands, true); }
4963 [(set_attr "type" "branch")
4964 (set_attr "mode" "none")])
4966 ;; Conditional branch on equality comparison.
4968 (define_insn "*branch_equality<mode>"
4971 (match_operator 0 "equality_operator"
4972 [(match_operand:GPR 2 "register_operand" "d")
4973 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4974 (label_ref (match_operand 1 "" ""))
4978 return mips_output_conditional_branch (insn, operands,
4979 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4980 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4982 [(set_attr "type" "branch")
4983 (set_attr "mode" "none")])
4985 (define_insn "*branch_equality<mode>_inverted"
4988 (match_operator 0 "equality_operator"
4989 [(match_operand:GPR 2 "register_operand" "d")
4990 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4992 (label_ref (match_operand 1 "" ""))))]
4995 return mips_output_conditional_branch (insn, operands,
4996 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4997 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4999 [(set_attr "type" "branch")
5000 (set_attr "mode" "none")])
5004 (define_insn "*branch_equality<mode>_mips16"
5007 (match_operator 0 "equality_operator"
5008 [(match_operand:GPR 1 "register_operand" "d,t")
5010 (match_operand 2 "pc_or_label_operand" "")
5011 (match_operand 3 "pc_or_label_operand" "")))]
5014 if (operands[2] != pc_rtx)
5016 if (which_alternative == 0)
5017 return "b%C0z\t%1,%2";
5019 return "bt%C0z\t%2";
5023 if (which_alternative == 0)
5024 return "b%N0z\t%1,%3";
5026 return "bt%N0z\t%3";
5029 [(set_attr "type" "branch")
5030 (set_attr "mode" "none")
5031 (set_attr "length" "8")])
5033 (define_expand "b<code>"
5035 (if_then_else (any_cond:CC (cc0)
5037 (label_ref (match_operand 0 ""))
5041 mips_expand_conditional_branch (operands, <CODE>);
5045 ;; Used to implement built-in functions.
5046 (define_expand "condjump"
5048 (if_then_else (match_operand 0)
5049 (label_ref (match_operand 1))
5053 ;; ....................
5055 ;; SETTING A REGISTER FROM A COMPARISON
5057 ;; ....................
5059 (define_expand "seq"
5060 [(set (match_operand:SI 0 "register_operand")
5061 (eq:SI (match_dup 1)
5064 { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
5066 (define_insn "*seq_<mode>"
5067 [(set (match_operand:GPR 0 "register_operand" "=d")
5068 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
5072 [(set_attr "type" "slt")
5073 (set_attr "mode" "<MODE>")])
5075 (define_insn "*seq_<mode>_mips16"
5076 [(set (match_operand:GPR 0 "register_operand" "=t")
5077 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
5081 [(set_attr "type" "slt")
5082 (set_attr "mode" "<MODE>")])
5084 ;; "sne" uses sltu instructions in which the first operand is $0.
5085 ;; This isn't possible in mips16 code.
5087 (define_expand "sne"
5088 [(set (match_operand:SI 0 "register_operand")
5089 (ne:SI (match_dup 1)
5092 { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
5094 (define_insn "*sne_<mode>"
5095 [(set (match_operand:GPR 0 "register_operand" "=d")
5096 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
5100 [(set_attr "type" "slt")
5101 (set_attr "mode" "<MODE>")])
5103 (define_expand "sgt"
5104 [(set (match_operand:SI 0 "register_operand")
5105 (gt:SI (match_dup 1)
5108 { if (mips_expand_scc (GT, operands[0])) DONE; else FAIL; })
5110 (define_insn "*sgt_<mode>"
5111 [(set (match_operand:GPR 0 "register_operand" "=d")
5112 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5113 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5116 [(set_attr "type" "slt")
5117 (set_attr "mode" "<MODE>")])
5119 (define_insn "*sgt_<mode>_mips16"
5120 [(set (match_operand:GPR 0 "register_operand" "=t")
5121 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
5122 (match_operand:GPR 2 "register_operand" "d")))]
5125 [(set_attr "type" "slt")
5126 (set_attr "mode" "<MODE>")])
5128 (define_expand "sge"
5129 [(set (match_operand:SI 0 "register_operand")
5130 (ge:SI (match_dup 1)
5133 { if (mips_expand_scc (GE, operands[0])) DONE; else FAIL; })
5135 (define_insn "*sge_<mode>"
5136 [(set (match_operand:GPR 0 "register_operand" "=d")
5137 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
5141 [(set_attr "type" "slt")
5142 (set_attr "mode" "<MODE>")])
5144 (define_expand "slt"
5145 [(set (match_operand:SI 0 "register_operand")
5146 (lt:SI (match_dup 1)
5149 { if (mips_expand_scc (LT, operands[0])) DONE; else FAIL; })
5151 (define_insn "*slt_<mode>"
5152 [(set (match_operand:GPR 0 "register_operand" "=d")
5153 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
5154 (match_operand:GPR 2 "arith_operand" "dI")))]
5157 [(set_attr "type" "slt")
5158 (set_attr "mode" "<MODE>")])
5160 (define_insn "*slt_<mode>_mips16"
5161 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5162 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
5163 (match_operand:GPR 2 "arith_operand" "d,I")))]
5166 [(set_attr "type" "slt")
5167 (set_attr "mode" "<MODE>")
5168 (set_attr_alternative "length"
5170 (if_then_else (match_operand 2 "m16_uimm8_1")
5174 (define_expand "sle"
5175 [(set (match_operand:SI 0 "register_operand")
5176 (le:SI (match_dup 1)
5179 { if (mips_expand_scc (LE, operands[0])) DONE; else FAIL; })
5181 (define_insn "*sle_<mode>"
5182 [(set (match_operand:GPR 0 "register_operand" "=d")
5183 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5184 (match_operand:GPR 2 "sle_operand" "")))]
5187 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5188 return "slt\t%0,%1,%2";
5190 [(set_attr "type" "slt")
5191 (set_attr "mode" "<MODE>")])
5193 (define_insn "*sle_<mode>_mips16"
5194 [(set (match_operand:GPR 0 "register_operand" "=t")
5195 (le:GPR (match_operand:GPR 1 "register_operand" "d")
5196 (match_operand:GPR 2 "sle_operand" "")))]
5199 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5200 return "slt\t%1,%2";
5202 [(set_attr "type" "slt")
5203 (set_attr "mode" "<MODE>")
5204 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5208 (define_expand "sgtu"
5209 [(set (match_operand:SI 0 "register_operand")
5210 (gtu:SI (match_dup 1)
5213 { if (mips_expand_scc (GTU, operands[0])) DONE; else FAIL; })
5215 (define_insn "*sgtu_<mode>"
5216 [(set (match_operand:GPR 0 "register_operand" "=d")
5217 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5218 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5221 [(set_attr "type" "slt")
5222 (set_attr "mode" "<MODE>")])
5224 (define_insn "*sgtu_<mode>_mips16"
5225 [(set (match_operand:GPR 0 "register_operand" "=t")
5226 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
5227 (match_operand:GPR 2 "register_operand" "d")))]
5230 [(set_attr "type" "slt")
5231 (set_attr "mode" "<MODE>")])
5233 (define_expand "sgeu"
5234 [(set (match_operand:SI 0 "register_operand")
5235 (geu:SI (match_dup 1)
5238 { if (mips_expand_scc (GEU, operands[0])) DONE; else FAIL; })
5240 (define_insn "*sge_<mode>"
5241 [(set (match_operand:GPR 0 "register_operand" "=d")
5242 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
5246 [(set_attr "type" "slt")
5247 (set_attr "mode" "<MODE>")])
5249 (define_expand "sltu"
5250 [(set (match_operand:SI 0 "register_operand")
5251 (ltu:SI (match_dup 1)
5254 { if (mips_expand_scc (LTU, operands[0])) DONE; else FAIL; })
5256 (define_insn "*sltu_<mode>"
5257 [(set (match_operand:GPR 0 "register_operand" "=d")
5258 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
5259 (match_operand:GPR 2 "arith_operand" "dI")))]
5262 [(set_attr "type" "slt")
5263 (set_attr "mode" "<MODE>")])
5265 (define_insn "*sltu_<mode>_mips16"
5266 [(set (match_operand:GPR 0 "register_operand" "=t,t")
5267 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
5268 (match_operand:GPR 2 "arith_operand" "d,I")))]
5271 [(set_attr "type" "slt")
5272 (set_attr "mode" "<MODE>")
5273 (set_attr_alternative "length"
5275 (if_then_else (match_operand 2 "m16_uimm8_1")
5279 (define_expand "sleu"
5280 [(set (match_operand:SI 0 "register_operand")
5281 (leu:SI (match_dup 1)
5284 { if (mips_expand_scc (LEU, operands[0])) DONE; else FAIL; })
5286 (define_insn "*sleu_<mode>"
5287 [(set (match_operand:GPR 0 "register_operand" "=d")
5288 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5289 (match_operand:GPR 2 "sleu_operand" "")))]
5292 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5293 return "sltu\t%0,%1,%2";
5295 [(set_attr "type" "slt")
5296 (set_attr "mode" "<MODE>")])
5298 (define_insn "*sleu_<mode>_mips16"
5299 [(set (match_operand:GPR 0 "register_operand" "=t")
5300 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
5301 (match_operand:GPR 2 "sleu_operand" "")))]
5304 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5305 return "sltu\t%1,%2";
5307 [(set_attr "type" "slt")
5308 (set_attr "mode" "<MODE>")
5309 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5314 ;; ....................
5316 ;; FLOATING POINT COMPARISONS
5318 ;; ....................
5320 (define_insn "s<code>_<mode>"
5321 [(set (match_operand:CC 0 "register_operand" "=z")
5322 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5323 (match_operand:SCALARF 2 "register_operand" "f")))]
5325 "c.<fcond>.<fmt>\t%Z0%1,%2"
5326 [(set_attr "type" "fcmp")
5327 (set_attr "mode" "FPSW")])
5329 (define_insn "s<code>_<mode>"
5330 [(set (match_operand:CC 0 "register_operand" "=z")
5331 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5332 (match_operand:SCALARF 2 "register_operand" "f")))]
5334 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5335 [(set_attr "type" "fcmp")
5336 (set_attr "mode" "FPSW")])
5339 ;; ....................
5341 ;; UNCONDITIONAL BRANCHES
5343 ;; ....................
5345 ;; Unconditional branches.
5349 (label_ref (match_operand 0 "" "")))]
5354 if (get_attr_length (insn) <= 8)
5355 return "%*b\t%l0%/";
5358 output_asm_insn (mips_output_load_label (), operands);
5359 return "%*jr\t%@%/%]";
5363 return "%*j\t%l0%/";
5365 [(set_attr "type" "jump")
5366 (set_attr "mode" "none")
5367 (set (attr "length")
5368 ;; We can't use `j' when emitting PIC. Emit a branch if it's
5369 ;; in range, otherwise load the address of the branch target into
5370 ;; $at and then jump to it.
5372 (ior (eq (symbol_ref "flag_pic") (const_int 0))
5373 (lt (abs (minus (match_dup 0)
5374 (plus (pc) (const_int 4))))
5375 (const_int 131072)))
5376 (const_int 4) (const_int 16)))])
5378 ;; We need a different insn for the mips16, because a mips16 branch
5379 ;; does not have a delay slot.
5383 (label_ref (match_operand 0 "" "")))]
5386 [(set_attr "type" "branch")
5387 (set_attr "mode" "none")
5388 (set_attr "length" "8")])
5390 (define_expand "indirect_jump"
5391 [(set (pc) (match_operand 0 "register_operand"))]
5394 operands[0] = force_reg (Pmode, operands[0]);
5395 if (Pmode == SImode)
5396 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
5398 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
5402 (define_insn "indirect_jump<mode>"
5403 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5406 [(set_attr "type" "jump")
5407 (set_attr "mode" "none")])
5409 (define_expand "tablejump"
5411 (match_operand 0 "register_operand"))
5412 (use (label_ref (match_operand 1 "")))]
5415 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
5416 operands[0] = expand_binop (Pmode, add_optab,
5417 convert_to_mode (Pmode, operands[0], false),
5418 gen_rtx_LABEL_REF (Pmode, operands[1]),
5420 else if (TARGET_GPWORD)
5421 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5422 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5423 else if (TARGET_RTP_PIC)
5425 /* When generating RTP PIC, we use case table entries that are relative
5426 to the start of the function. Add the function's address to the
5428 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5429 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5430 start, 0, 0, OPTAB_WIDEN);
5433 if (Pmode == SImode)
5434 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
5436 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
5440 (define_insn "tablejump<mode>"
5442 (match_operand:P 0 "register_operand" "d"))
5443 (use (label_ref (match_operand 1 "" "")))]
5446 [(set_attr "type" "jump")
5447 (set_attr "mode" "none")])
5449 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5450 ;; While it is possible to either pull it off the stack (in the
5451 ;; o32 case) or recalculate it given t9 and our target label,
5452 ;; it takes 3 or 4 insns to do so.
5454 (define_expand "builtin_setjmp_setup"
5455 [(use (match_operand 0 "register_operand"))]
5460 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
5461 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5465 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5466 ;; that older code did recalculate the gp from $25. Continue to jump through
5467 ;; $25 for compatibility (we lose nothing by doing so).
5469 (define_expand "builtin_longjmp"
5470 [(use (match_operand 0 "register_operand"))]
5473 /* The elements of the buffer are, in order: */
5474 int W = GET_MODE_SIZE (Pmode);
5475 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5476 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5477 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5478 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5479 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5480 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5481 The target is bound to be using $28 as the global pointer
5482 but the current function might not be. */
5483 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5485 /* This bit is similar to expand_builtin_longjmp except that it
5486 restores $gp as well. */
5487 mips_emit_move (hard_frame_pointer_rtx, fp);
5488 mips_emit_move (pv, lab);
5489 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5490 mips_emit_move (gp, gpv);
5491 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5492 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5493 emit_insn (gen_rtx_USE (VOIDmode, gp));
5494 emit_indirect_jump (pv);
5499 ;; ....................
5501 ;; Function prologue/epilogue
5503 ;; ....................
5506 (define_expand "prologue"
5510 mips_expand_prologue ();
5514 ;; Block any insns from being moved before this point, since the
5515 ;; profiling call to mcount can use various registers that aren't
5516 ;; saved or used to pass arguments.
5518 (define_insn "blockage"
5519 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5522 [(set_attr "type" "unknown")
5523 (set_attr "mode" "none")
5524 (set_attr "length" "0")])
5526 (define_expand "epilogue"
5530 mips_expand_epilogue (false);
5534 (define_expand "sibcall_epilogue"
5538 mips_expand_epilogue (true);
5542 ;; Trivial return. Make it look like a normal return insn as that
5543 ;; allows jump optimizations to work better.
5545 (define_insn "return"
5547 "mips_can_use_return_insn ()"
5549 [(set_attr "type" "jump")
5550 (set_attr "mode" "none")])
5554 (define_insn "return_internal"
5556 (use (match_operand 0 "pmode_register_operand" ""))]
5559 [(set_attr "type" "jump")
5560 (set_attr "mode" "none")])
5562 ;; This is used in compiling the unwind routines.
5563 (define_expand "eh_return"
5564 [(use (match_operand 0 "general_operand"))]
5567 if (GET_MODE (operands[0]) != word_mode)
5568 operands[0] = convert_to_mode (word_mode, operands[0], 0);
5570 emit_insn (gen_eh_set_lr_di (operands[0]));
5572 emit_insn (gen_eh_set_lr_si (operands[0]));
5576 ;; Clobber the return address on the stack. We can't expand this
5577 ;; until we know where it will be put in the stack frame.
5579 (define_insn "eh_set_lr_si"
5580 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5581 (clobber (match_scratch:SI 1 "=&d"))]
5585 (define_insn "eh_set_lr_di"
5586 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5587 (clobber (match_scratch:DI 1 "=&d"))]
5592 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5593 (clobber (match_scratch 1))]
5594 "reload_completed && !TARGET_DEBUG_D_MODE"
5597 mips_set_return_address (operands[0], operands[1]);
5601 (define_insn_and_split "exception_receiver"
5603 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
5604 "TARGET_CALL_CLOBBERED_GP"
5606 "&& reload_completed"
5612 [(set_attr "type" "load")
5613 (set_attr "length" "12")])
5616 ;; ....................
5620 ;; ....................
5622 ;; Instructions to load a call address from the GOT. The address might
5623 ;; point to a function or to a lazy binding stub. In the latter case,
5624 ;; the stub will use the dynamic linker to resolve the function, which
5625 ;; in turn will change the GOT entry to point to the function's real
5628 ;; This means that every call, even pure and constant ones, can
5629 ;; potentially modify the GOT entry. And once a stub has been called,
5630 ;; we must not call it again.
5632 ;; We represent this restriction using an imaginary fixed register that
5633 ;; is set by the GOT load and used by the call. By making this register
5634 ;; call-clobbered, and by making the GOT load the only way of setting
5635 ;; the register, we ensure that the load cannot be moved past a call.
5636 (define_insn "load_call<mode>"
5637 [(set (match_operand:P 0 "register_operand" "=d")
5638 (unspec:P [(match_operand:P 1 "register_operand" "r")
5639 (match_operand:P 2 "immediate_operand" "")]
5641 (set (reg:P FAKE_CALL_REGNO)
5642 (unspec:P [(match_dup 2)] UNSPEC_LOAD_CALL))]
5644 "<load>\t%0,%R2(%1)"
5645 [(set_attr "type" "load")
5646 (set_attr "mode" "<MODE>")
5647 (set_attr "hazard_set" "0")
5648 (set_attr "length" "4")])
5650 ;; Sibling calls. All these patterns use jump instructions.
5652 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5653 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5654 ;; is defined in terms of call_insn_operand, the same is true of the
5657 ;; When we use an indirect jump, we need a register that will be
5658 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5659 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5660 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5663 (define_expand "sibcall"
5664 [(parallel [(call (match_operand 0 "")
5665 (match_operand 1 ""))
5666 (use (match_operand 2 "")) ;; next_arg_reg
5667 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5670 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5674 (define_insn "sibcall_internal"
5675 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5676 (match_operand 1 "" ""))]
5677 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5678 { return MIPS_CALL ("j", operands, 0); }
5679 [(set_attr "type" "call")])
5681 (define_expand "sibcall_value"
5682 [(parallel [(set (match_operand 0 "")
5683 (call (match_operand 1 "")
5684 (match_operand 2 "")))
5685 (use (match_operand 3 ""))])] ;; next_arg_reg
5688 mips_expand_call (operands[0], XEXP (operands[1], 0),
5689 operands[2], operands[3], true);
5693 (define_insn "sibcall_value_internal"
5694 [(set (match_operand 0 "register_operand" "")
5695 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5696 (match_operand 2 "" "")))]
5697 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5698 { return MIPS_CALL ("j", operands, 1); }
5699 [(set_attr "type" "call")])
5701 (define_insn "sibcall_value_multiple_internal"
5702 [(set (match_operand 0 "register_operand" "")
5703 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5704 (match_operand 2 "" "")))
5705 (set (match_operand 3 "register_operand" "")
5706 (call (mem:SI (match_dup 1))
5708 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5709 { return MIPS_CALL ("j", operands, 1); }
5710 [(set_attr "type" "call")])
5712 (define_expand "call"
5713 [(parallel [(call (match_operand 0 "")
5714 (match_operand 1 ""))
5715 (use (match_operand 2 "")) ;; next_arg_reg
5716 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5719 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5723 ;; This instruction directly corresponds to an assembly-language "jal".
5724 ;; There are four cases:
5727 ;; Both symbolic and register destinations are OK. The pattern
5728 ;; always expands to a single mips instruction.
5730 ;; - -mabicalls/-mno-explicit-relocs:
5731 ;; Again, both symbolic and register destinations are OK.
5732 ;; The call is treated as a multi-instruction black box.
5734 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5735 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5738 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5739 ;; Only "jal $25" is allowed. The call is actually two instructions:
5740 ;; "jalr $25" followed by an insn to reload $gp.
5742 ;; In the last case, we can generate the individual instructions with
5743 ;; a define_split. There are several things to be wary of:
5745 ;; - We can't expose the load of $gp before reload. If we did,
5746 ;; it might get removed as dead, but reload can introduce new
5747 ;; uses of $gp by rematerializing constants.
5749 ;; - We shouldn't restore $gp after calls that never return.
5750 ;; It isn't valid to insert instructions between a noreturn
5751 ;; call and the following barrier.
5753 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5754 ;; instruction preserves $gp and so have no effect on its liveness.
5755 ;; But once we generate the separate insns, it becomes obvious that
5756 ;; $gp is not live on entry to the call.
5758 ;; ??? The operands[2] = insn check is a hack to make the original insn
5759 ;; available to the splitter.
5760 (define_insn_and_split "call_internal"
5761 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5762 (match_operand 1 "" ""))
5763 (clobber (reg:SI 31))]
5765 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5766 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5769 emit_call_insn (gen_call_split (operands[0], operands[1]));
5770 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5774 [(set_attr "jal" "indirect,direct")
5775 (set_attr "extended_mips16" "no,yes")])
5777 ;; A pattern for calls that must be made directly. It is used for
5778 ;; MIPS16 calls that the linker may need to redirect to a hard-float
5779 ;; stub; the linker relies on the call relocation type to detect when
5780 ;; such redirection is needed.
5781 (define_insn "call_internal_direct"
5782 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
5785 (clobber (reg:SI 31))]
5787 { return MIPS_CALL ("jal", operands, 0); })
5789 (define_insn "call_split"
5790 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5791 (match_operand 1 "" ""))
5792 (clobber (reg:SI 31))
5793 (clobber (reg:SI 28))]
5794 "TARGET_SPLIT_CALLS"
5795 { return MIPS_CALL ("jal", operands, 0); }
5796 [(set_attr "type" "call")])
5798 (define_expand "call_value"
5799 [(parallel [(set (match_operand 0 "")
5800 (call (match_operand 1 "")
5801 (match_operand 2 "")))
5802 (use (match_operand 3 ""))])] ;; next_arg_reg
5805 mips_expand_call (operands[0], XEXP (operands[1], 0),
5806 operands[2], operands[3], false);
5810 ;; See comment for call_internal.
5811 (define_insn_and_split "call_value_internal"
5812 [(set (match_operand 0 "register_operand" "")
5813 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5814 (match_operand 2 "" "")))
5815 (clobber (reg:SI 31))]
5817 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5818 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5821 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5823 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5827 [(set_attr "jal" "indirect,direct")
5828 (set_attr "extended_mips16" "no,yes")])
5830 (define_insn "call_value_split"
5831 [(set (match_operand 0 "register_operand" "")
5832 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5833 (match_operand 2 "" "")))
5834 (clobber (reg:SI 31))
5835 (clobber (reg:SI 28))]
5836 "TARGET_SPLIT_CALLS"
5837 { return MIPS_CALL ("jal", operands, 1); }
5838 [(set_attr "type" "call")])
5840 ;; See call_internal_direct.
5841 (define_insn "call_value_internal_direct"
5842 [(set (match_operand 0 "register_operand")
5843 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
5846 (clobber (reg:SI 31))]
5848 { return MIPS_CALL ("jal", operands, 1); })
5850 ;; See comment for call_internal.
5851 (define_insn_and_split "call_value_multiple_internal"
5852 [(set (match_operand 0 "register_operand" "")
5853 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5854 (match_operand 2 "" "")))
5855 (set (match_operand 3 "register_operand" "")
5856 (call (mem:SI (match_dup 1))
5858 (clobber (reg:SI 31))]
5860 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5861 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5864 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5865 operands[2], operands[3]));
5866 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5870 [(set_attr "jal" "indirect,direct")
5871 (set_attr "extended_mips16" "no,yes")])
5873 (define_insn "call_value_multiple_split"
5874 [(set (match_operand 0 "register_operand" "")
5875 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5876 (match_operand 2 "" "")))
5877 (set (match_operand 3 "register_operand" "")
5878 (call (mem:SI (match_dup 1))
5880 (clobber (reg:SI 31))
5881 (clobber (reg:SI 28))]
5882 "TARGET_SPLIT_CALLS"
5883 { return MIPS_CALL ("jal", operands, 1); }
5884 [(set_attr "type" "call")])
5886 ;; Call subroutine returning any type.
5888 (define_expand "untyped_call"
5889 [(parallel [(call (match_operand 0 "")
5891 (match_operand 1 "")
5892 (match_operand 2 "")])]
5897 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5899 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5901 rtx set = XVECEXP (operands[2], 0, i);
5902 mips_emit_move (SET_DEST (set), SET_SRC (set));
5905 emit_insn (gen_blockage ());
5910 ;; ....................
5914 ;; ....................
5918 (define_insn "prefetch"
5919 [(prefetch (match_operand:QI 0 "address_operand" "p")
5920 (match_operand 1 "const_int_operand" "n")
5921 (match_operand 2 "const_int_operand" "n"))]
5922 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5924 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5925 return "pref\t%1,%a0";
5927 [(set_attr "type" "prefetch")])
5929 (define_insn "*prefetch_indexed_<mode>"
5930 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5931 (match_operand:P 1 "register_operand" "d"))
5932 (match_operand 2 "const_int_operand" "n")
5933 (match_operand 3 "const_int_operand" "n"))]
5934 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5936 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5937 return "prefx\t%2,%1(%0)";
5939 [(set_attr "type" "prefetchx")])
5945 [(set_attr "type" "nop")
5946 (set_attr "mode" "none")])
5948 ;; Like nop, but commented out when outside a .set noreorder block.
5949 (define_insn "hazard_nop"
5958 [(set_attr "type" "nop")])
5960 ;; MIPS4 Conditional move instructions.
5962 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5963 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5965 (match_operator:MOVECC 4 "equality_operator"
5966 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5968 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5969 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5974 [(set_attr "type" "condmove")
5975 (set_attr "mode" "<GPR:MODE>")])
5977 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5978 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5979 (if_then_else:SCALARF
5980 (match_operator:MOVECC 4 "equality_operator"
5981 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5983 (match_operand:SCALARF 2 "register_operand" "f,0")
5984 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5987 mov%T4.<fmt>\t%0,%2,%1
5988 mov%t4.<fmt>\t%0,%3,%1"
5989 [(set_attr "type" "condmove")
5990 (set_attr "mode" "<SCALARF:MODE>")])
5992 ;; These are the main define_expand's used to make conditional moves.
5994 (define_expand "mov<mode>cc"
5995 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5996 (set (match_operand:GPR 0 "register_operand")
5997 (if_then_else:GPR (match_dup 5)
5998 (match_operand:GPR 2 "reg_or_0_operand")
5999 (match_operand:GPR 3 "reg_or_0_operand")))]
6002 mips_expand_conditional_move (operands);
6006 (define_expand "mov<mode>cc"
6007 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6008 (set (match_operand:SCALARF 0 "register_operand")
6009 (if_then_else:SCALARF (match_dup 5)
6010 (match_operand:SCALARF 2 "register_operand")
6011 (match_operand:SCALARF 3 "register_operand")))]
6014 mips_expand_conditional_move (operands);
6019 ;; ....................
6021 ;; mips16 inline constant tables
6023 ;; ....................
6026 (define_insn "consttable_int"
6027 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6028 (match_operand 1 "const_int_operand" "")]
6029 UNSPEC_CONSTTABLE_INT)]
6032 assemble_integer (operands[0], INTVAL (operands[1]),
6033 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6036 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6038 (define_insn "consttable_float"
6039 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6040 UNSPEC_CONSTTABLE_FLOAT)]
6045 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6046 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6047 assemble_real (d, GET_MODE (operands[0]),
6048 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6051 [(set (attr "length")
6052 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6054 (define_insn "align"
6055 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6058 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6061 [(match_operand 0 "small_data_pattern")]
6064 { operands[0] = mips_rewrite_small_data (operands[0]); })
6067 ;; ....................
6069 ;; MIPS16e Save/Restore
6071 ;; ....................
6074 (define_insn "*mips16e_save_restore"
6075 [(match_parallel 0 ""
6076 [(set (match_operand:SI 1 "register_operand")
6077 (plus:SI (match_dup 1)
6078 (match_operand:SI 2 "const_int_operand")))])]
6079 "operands[1] == stack_pointer_rtx
6080 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6081 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6082 [(set_attr "type" "arith")
6083 (set_attr "extended_mips16" "yes")])
6085 ; Thread-Local Storage
6087 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
6088 ; MIPS architecture defines this register, and no current
6089 ; implementation provides it; instead, any OS which supports TLS is
6090 ; expected to trap and emulate this instruction. rdhwr is part of the
6091 ; MIPS 32r2 specification, but we use it on any architecture because
6092 ; we expect it to be emulated. Use .set to force the assembler to
6095 (define_insn "tls_get_tp_<mode>"
6096 [(set (match_operand:P 0 "register_operand" "=v")
6097 (unspec:P [(const_int 0)]
6098 UNSPEC_TLS_GET_TP))]
6099 "HAVE_AS_TLS && !TARGET_MIPS16"
6100 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
6101 [(set_attr "type" "unknown")
6102 ; Since rdhwr always generates a trap for now, putting it in a delay
6103 ; slot would make the kernel's emulation of it much slower.
6104 (set_attr "can_delay" "no")
6105 (set_attr "mode" "<MODE>")])
6107 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6109 (include "mips-ps-3d.md")
6111 ; The MIPS DSP Instructions.
6113 (include "mips-dsp.md")
6115 ; The MIPS DSP REV 2 Instructions.
6117 (include "mips-dspr2.md")
6119 ; MIPS fixed-point instructions.
6120 (include "mips-fixed.md")