1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992-2017 Free Software Foundation, Inc.
3 ;; Contributed by the Center for Software Science at the University
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; This machine description is inspired by sparc.md and to a lesser
25 ;; Possible improvements:
27 ;; * With PA1.1, most computational instructions can conditionally nullify
28 ;; the execution of the following instruction. A nullified instruction
29 ;; does not cause the instruction pipeline to stall, making it a very
30 ;; efficient alternative to e.g. branching or conditional moves.
32 ;; Nullification is performed conditionally based on the outcome of a
33 ;; test specified in the opcode. The test result is stored in PSW[N]
34 ;; and can only be used to nullify the instruction following immediately
35 ;; after the test. For example:
39 ;; sub,< %r26,%r25,%r28
40 ;; sub %r28,%r25,%r28 ; %r28 == 0
41 ;; sub,> %r26,%r25,%r29
42 ;; sub %r29,%r25,%r29 ; %r29 == 5
44 ;; This could be tricky to implement because the result of the test has
45 ;; to be propagated one instruction forward, which, in the worst case,
46 ;; would involve (1) adding a fake register for PSW[N]; (2) adding the
47 ;; variants of the computational instructions that set or consume this
48 ;; fake register. The cond_exec infrastructure is probably not helpful
51 ;; * PA-RISC includes a set of conventions for branch instruction usage
52 ;; to indicate whether a particular branch is more likely to be taken
53 ;; or not taken. For example, the prediction for CMPB instructions
54 ;; (CMPB,cond,n r1,r2,target) depends on the direction of the branch
55 ;; (forward or backward) and on the order of the operands:
57 ;; | branch | operand | branch |
58 ;; | direction | compare | prediction |
59 ;; +-----------+----------+------------+
60 ;; | backward | r1 < r2 | taken |
61 ;; | backward | r1 >= r2 | not taken |
62 ;; | forward | r1 < r2 | not taken |
63 ;; | forward | r1 >= r2 | taken |
65 ;; By choosing instructions and operand order carefully, the compiler
66 ;; could give the CPU branch predictor some help.
69 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
71 ;; Uses of UNSPEC in this file:
73 (define_c_enum "unspec"
74 [UNSPEC_CFFC ; canonicalize_funcptr_for_compare
75 UNSPEC_GOTO ; indirect_goto
91 (define_c_enum "unspecv"
92 [UNSPECV_BLOCKAGE ; blockage
93 UNSPECV_DCACHE ; dcacheflush
94 UNSPECV_ICACHE ; icacheflush
95 UNSPECV_OPC ; outline_prologue_call
96 UNSPECV_OEC ; outline_epilogue_call
97 UNSPECV_LONGJMP ; builtin_longjmp
100 ;; Maximum pc-relative branch offsets.
102 ;; These numbers are a bit smaller than the maximum allowable offsets
103 ;; so that a few instructions may be inserted before the actual branch.
106 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
107 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
110 ;; Mode and code iterators
112 ;; This mode iterator allows :P to be used for patterns that operate on
113 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
114 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
116 ;; This attribute defines the condition prefix for word and double word
117 ;; add, compare, subtract and logical instructions.
118 (define_mode_attr dwc [(SI "") (DI "*")])
120 ;; Insn type. Used to default other attribute values.
122 ;; type "unary" insns have one input operand (1) and one output operand (0)
123 ;; type "binary" insns have two input operands (1,2) and one output (0)
126 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload,trap"
127 (const_string "binary"))
129 (define_attr "pa_combine_type"
130 "fmpy,faddsub,uncond_branch,addmove,none"
131 (const_string "none"))
133 ;; Processor type (for scheduling, not code generation) -- this attribute
134 ;; must exactly match the processor_type enumeration in pa.h.
136 ;; FIXME: Add 800 scheduling for completeness?
138 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
140 ;; Length (in # of bytes).
141 (define_attr "length" ""
142 (cond [(eq_attr "type" "load,fpload")
143 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
144 (const_int 8) (const_int 4))
146 (eq_attr "type" "store,fpstore")
147 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
148 (const_int 8) (const_int 4))
150 (eq_attr "type" "binary,shift,nullshift")
151 (if_then_else (match_operand 2 "arith14_operand" "")
152 (const_int 4) (const_int 12))
154 (eq_attr "type" "move,unary,shift,nullshift")
155 (if_then_else (match_operand 1 "arith14_operand" "")
156 (const_int 4) (const_int 8))]
160 (define_asm_attributes
161 [(set_attr "length" "4")
162 (set_attr "type" "multi")])
164 ;; Attributes for instruction and branch scheduling
166 ;; For conditional branches. Frame related instructions are not allowed
167 ;; because they confuse the unwind support.
168 (define_attr "in_branch_delay" "false,true"
169 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
170 (eq_attr "length" "4")
171 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
172 (const_string "true")
173 (const_string "false")))
175 ;; Disallow instructions which use the FPU since they will tie up the FPU
176 ;; even if the instruction is nullified.
177 (define_attr "in_nullified_branch_delay" "false,true"
178 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch,trap")
179 (eq_attr "length" "4")
180 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
181 (const_string "true")
182 (const_string "false")))
184 ;; For calls and millicode calls.
185 (define_attr "in_call_delay" "false,true"
186 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
187 (eq_attr "length" "4")
188 (not (match_test "RTX_FRAME_RELATED_P (insn)")))
189 (const_string "true")
190 (const_string "false")))
192 ;; Call delay slot description.
193 (define_delay (eq_attr "type" "call")
194 [(eq_attr "in_call_delay" "true") (nil) (nil)])
196 ;; Sibcall delay slot description.
197 (define_delay (eq_attr "type" "sibcall")
198 [(eq_attr "in_call_delay" "true") (nil) (nil)])
200 ;; Millicode call delay slot description.
201 (define_delay (eq_attr "type" "milli")
202 [(eq_attr "in_call_delay" "true") (nil) (nil)])
204 ;; Return and other similar instructions.
205 (define_delay (eq_attr "type" "branch,parallel_branch")
206 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
208 ;; Floating point conditional branch delay slot description.
209 (define_delay (eq_attr "type" "fbranch")
210 [(eq_attr "in_branch_delay" "true")
211 (eq_attr "in_nullified_branch_delay" "true")
214 ;; Integer conditional branch delay slot description.
215 ;; Nullification of conditional branches on the PA is dependent on the
216 ;; direction of the branch. Forward branches nullify true and
217 ;; backward branches nullify false. If the direction is unknown
218 ;; then nullification is not allowed.
219 (define_delay (eq_attr "type" "cbranch")
220 [(eq_attr "in_branch_delay" "true")
221 (and (eq_attr "in_nullified_branch_delay" "true")
222 (attr_flag "forward"))
223 (and (eq_attr "in_nullified_branch_delay" "true")
224 (attr_flag "backward"))])
226 (define_delay (eq_attr "type" "uncond_branch")
227 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
229 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
230 ;; load: 2, fpload: 3
231 ;; store, fpstore: 3, no D-cache operations should be scheduled.
233 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
235 ;; Instruction Time Unit Minimum Distance (unit contention)
242 ;; fmpyadd 3 ALU,MPY 2
243 ;; fmpysub 3 ALU,MPY 2
244 ;; fmpycfxt 3 ALU,MPY 2
247 ;; fdiv,sgl 10 MPY 10
248 ;; fdiv,dbl 12 MPY 12
249 ;; fsqrt,sgl 14 MPY 14
250 ;; fsqrt,dbl 18 MPY 18
252 ;; We don't model fmpyadd/fmpysub properly as those instructions
253 ;; keep both the FP ALU and MPY units busy. Given that these
254 ;; processors are obsolete, I'm not going to spend the time to
255 ;; model those instructions correctly.
257 (define_automaton "pa700")
258 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
260 (define_insn_reservation "W0" 4
261 (and (eq_attr "type" "fpcc")
262 (eq_attr "cpu" "700"))
265 (define_insn_reservation "W1" 3
266 (and (eq_attr "type" "fpalu")
267 (eq_attr "cpu" "700"))
270 (define_insn_reservation "W2" 3
271 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
272 (eq_attr "cpu" "700"))
275 (define_insn_reservation "W3" 10
276 (and (eq_attr "type" "fpdivsgl")
277 (eq_attr "cpu" "700"))
280 (define_insn_reservation "W4" 12
281 (and (eq_attr "type" "fpdivdbl")
282 (eq_attr "cpu" "700"))
285 (define_insn_reservation "W5" 14
286 (and (eq_attr "type" "fpsqrtsgl")
287 (eq_attr "cpu" "700"))
290 (define_insn_reservation "W6" 18
291 (and (eq_attr "type" "fpsqrtdbl")
292 (eq_attr "cpu" "700"))
295 (define_insn_reservation "W7" 2
296 (and (eq_attr "type" "load")
297 (eq_attr "cpu" "700"))
300 (define_insn_reservation "W8" 2
301 (and (eq_attr "type" "fpload")
302 (eq_attr "cpu" "700"))
305 (define_insn_reservation "W9" 3
306 (and (eq_attr "type" "store")
307 (eq_attr "cpu" "700"))
310 (define_insn_reservation "W10" 3
311 (and (eq_attr "type" "fpstore")
312 (eq_attr "cpu" "700"))
315 (define_insn_reservation "W11" 5
316 (and (eq_attr "type" "fpstore_load")
317 (eq_attr "cpu" "700"))
320 (define_insn_reservation "W12" 6
321 (and (eq_attr "type" "store_fpload")
322 (eq_attr "cpu" "700"))
325 (define_insn_reservation "W13" 1
326 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
327 (eq_attr "cpu" "700"))
330 ;; We have a bypass for all computations in the FP unit which feed an
331 ;; FP store as long as the sizes are the same.
332 (define_bypass 2 "W1,W2" "W10,W11" "pa_fpstore_bypass_p")
333 (define_bypass 9 "W3" "W10,W11" "pa_fpstore_bypass_p")
334 (define_bypass 11 "W4" "W10,W11" "pa_fpstore_bypass_p")
335 (define_bypass 13 "W5" "W10,W11" "pa_fpstore_bypass_p")
336 (define_bypass 17 "W6" "W10,W11" "pa_fpstore_bypass_p")
338 ;; We have an "anti-bypass" for FP loads which feed an FP store.
339 (define_bypass 4 "W8,W12" "W10,W11" "pa_fpstore_bypass_p")
341 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
342 ;; floating point computations with non-floating point computations (fp loads
343 ;; and stores are not fp computations).
345 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
346 ;; take two cycles, during which no Dcache operations should be scheduled.
347 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
348 ;; all have the same memory characteristics if one disregards cache misses.
350 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
351 ;; There's no value in modeling the ALU and MUL separately though
352 ;; since there can never be a functional unit conflict given the
353 ;; latency and issue rates for those units.
356 ;; Instruction Time Unit Minimum Distance (unit contention)
363 ;; fmpyadd 2 ALU,MPY 1
364 ;; fmpysub 2 ALU,MPY 1
365 ;; fmpycfxt 2 ALU,MPY 1
369 ;; fdiv,dbl 15 DIV 15
371 ;; fsqrt,dbl 15 DIV 15
373 (define_automaton "pa7100")
374 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
376 (define_insn_reservation "X0" 2
377 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
378 (eq_attr "cpu" "7100"))
381 (define_insn_reservation "X1" 8
382 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
383 (eq_attr "cpu" "7100"))
384 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
386 (define_insn_reservation "X2" 15
387 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
388 (eq_attr "cpu" "7100"))
389 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
391 (define_insn_reservation "X3" 2
392 (and (eq_attr "type" "load")
393 (eq_attr "cpu" "7100"))
396 (define_insn_reservation "X4" 2
397 (and (eq_attr "type" "fpload")
398 (eq_attr "cpu" "7100"))
401 (define_insn_reservation "X5" 2
402 (and (eq_attr "type" "store")
403 (eq_attr "cpu" "7100"))
404 "i_7100+mem_7100,mem_7100")
406 (define_insn_reservation "X6" 2
407 (and (eq_attr "type" "fpstore")
408 (eq_attr "cpu" "7100"))
409 "i_7100+mem_7100,mem_7100")
411 (define_insn_reservation "X7" 4
412 (and (eq_attr "type" "fpstore_load")
413 (eq_attr "cpu" "7100"))
414 "i_7100+mem_7100,mem_7100*3")
416 (define_insn_reservation "X8" 4
417 (and (eq_attr "type" "store_fpload")
418 (eq_attr "cpu" "7100"))
419 "i_7100+mem_7100,mem_7100*3")
421 (define_insn_reservation "X9" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
423 (eq_attr "cpu" "7100"))
426 ;; We have a bypass for all computations in the FP unit which feed an
427 ;; FP store as long as the sizes are the same.
428 (define_bypass 1 "X0" "X6,X7" "pa_fpstore_bypass_p")
429 (define_bypass 7 "X1" "X6,X7" "pa_fpstore_bypass_p")
430 (define_bypass 14 "X2" "X6,X7" "pa_fpstore_bypass_p")
432 ;; We have an "anti-bypass" for FP loads which feed an FP store.
433 (define_bypass 3 "X4,X8" "X6,X7" "pa_fpstore_bypass_p")
435 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
436 ;; There's no value in modeling the ALU and MUL separately though
437 ;; since there can never be a functional unit conflict that
438 ;; can be avoided given the latency, issue rates and mandatory
439 ;; one cycle cpu-wide lock for a double precision fp multiply.
442 ;; Instruction Time Unit Minimum Distance (unit contention)
449 ;; fmpyadd,sgl 2 ALU,MPY 1
450 ;; fmpyadd,dbl 3 ALU,MPY 2
451 ;; fmpysub,sgl 2 ALU,MPY 1
452 ;; fmpysub,dbl 3 ALU,MPY 2
453 ;; fmpycfxt,sgl 2 ALU,MPY 1
454 ;; fmpycfxt,dbl 3 ALU,MPY 2
459 ;; fdiv,dbl 15 DIV 15
461 ;; fsqrt,dbl 15 DIV 15
463 ;; The PA7200 is just like the PA7100LC except that there is
464 ;; no store-store penalty.
466 ;; The PA7300 is just like the PA7200 except that there is
467 ;; no store-load penalty.
469 ;; Note there are some aspects of the 7100LC we are not modeling
470 ;; at the moment. I'll be reviewing the 7100LC scheduling info
471 ;; shortly and updating this description.
475 ;; other issue modeling
477 (define_automaton "pa7100lc")
478 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
479 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
480 (define_cpu_unit "mem_7100lc" "pa7100lc")
482 ;; Double precision multiplies lock the entire CPU for one
483 ;; cycle. There is no way to avoid this lock and trying to
484 ;; schedule around the lock is pointless and thus there is no
485 ;; value in trying to model this lock.
487 ;; Not modeling the lock allows us to treat fp multiplies just
488 ;; like any other FP alu instruction. It allows for a smaller
489 ;; DFA and may reduce register pressure.
490 (define_insn_reservation "Y0" 2
491 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
492 (eq_attr "cpu" "7100LC,7200,7300"))
493 "f_7100lc,fpmac_7100lc")
495 ;; fp division and sqrt instructions lock the entire CPU for
496 ;; 7 cycles (single precision) or 14 cycles (double precision).
497 ;; There is no way to avoid this lock and trying to schedule
498 ;; around the lock is pointless and thus there is no value in
499 ;; trying to model this lock. Not modeling the lock allows
500 ;; for a smaller DFA and may reduce register pressure.
501 (define_insn_reservation "Y1" 1
502 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
503 (eq_attr "cpu" "7100LC,7200,7300"))
506 (define_insn_reservation "Y2" 2
507 (and (eq_attr "type" "load")
508 (eq_attr "cpu" "7100LC,7200,7300"))
509 "i1_7100lc+mem_7100lc")
511 (define_insn_reservation "Y3" 2
512 (and (eq_attr "type" "fpload")
513 (eq_attr "cpu" "7100LC,7200,7300"))
514 "i1_7100lc+mem_7100lc")
516 (define_insn_reservation "Y4" 2
517 (and (eq_attr "type" "store")
518 (eq_attr "cpu" "7100LC"))
519 "i1_7100lc+mem_7100lc,mem_7100lc")
521 (define_insn_reservation "Y5" 2
522 (and (eq_attr "type" "fpstore")
523 (eq_attr "cpu" "7100LC"))
524 "i1_7100lc+mem_7100lc,mem_7100lc")
526 (define_insn_reservation "Y6" 4
527 (and (eq_attr "type" "fpstore_load")
528 (eq_attr "cpu" "7100LC"))
529 "i1_7100lc+mem_7100lc,mem_7100lc*3")
531 (define_insn_reservation "Y7" 4
532 (and (eq_attr "type" "store_fpload")
533 (eq_attr "cpu" "7100LC"))
534 "i1_7100lc+mem_7100lc,mem_7100lc*3")
536 (define_insn_reservation "Y8" 1
537 (and (eq_attr "type" "shift,nullshift")
538 (eq_attr "cpu" "7100LC,7200,7300"))
541 (define_insn_reservation "Y9" 1
542 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
543 (eq_attr "cpu" "7100LC,7200,7300"))
544 "(i0_7100lc|i1_7100lc)")
546 ;; The 7200 has a store-load penalty
547 (define_insn_reservation "Y10" 2
548 (and (eq_attr "type" "store")
549 (eq_attr "cpu" "7200"))
550 "i1_7100lc,mem_7100lc")
552 (define_insn_reservation "Y11" 2
553 (and (eq_attr "type" "fpstore")
554 (eq_attr "cpu" "7200"))
555 "i1_7100lc,mem_7100lc")
557 (define_insn_reservation "Y12" 4
558 (and (eq_attr "type" "fpstore_load")
559 (eq_attr "cpu" "7200"))
560 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
562 (define_insn_reservation "Y13" 4
563 (and (eq_attr "type" "store_fpload")
564 (eq_attr "cpu" "7200"))
565 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
567 ;; The 7300 has no penalty for store-store or store-load
568 (define_insn_reservation "Y14" 2
569 (and (eq_attr "type" "store")
570 (eq_attr "cpu" "7300"))
573 (define_insn_reservation "Y15" 2
574 (and (eq_attr "type" "fpstore")
575 (eq_attr "cpu" "7300"))
578 (define_insn_reservation "Y16" 4
579 (and (eq_attr "type" "fpstore_load")
580 (eq_attr "cpu" "7300"))
581 "i1_7100lc,i1_7100lc+mem_7100lc")
583 (define_insn_reservation "Y17" 4
584 (and (eq_attr "type" "store_fpload")
585 (eq_attr "cpu" "7300"))
586 "i1_7100lc,i1_7100lc+mem_7100lc")
588 ;; We have an "anti-bypass" for FP loads which feed an FP store.
589 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "pa_fpstore_bypass_p")
591 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
592 ;; traditional architecture.
594 ;; The PA8000 has a large (56) entry reorder buffer that is split between
595 ;; memory and non-memory operations.
597 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
598 ;; the function units, with the exception of branches and multi-output
599 ;; instructions. The PA8000 can retire two non-memory operations per cycle
600 ;; and two memory operations per cycle, only one of which may be a store.
602 ;; Given the large reorder buffer, the processor can hide most latencies.
603 ;; According to HP, they've got the best results by scheduling for retirement
604 ;; bandwidth with limited latency scheduling for floating point operations.
605 ;; Latency for integer operations and memory references is ignored.
608 ;; We claim floating point operations have a 2 cycle latency and are
609 ;; fully pipelined, except for div and sqrt which are not pipelined and
610 ;; take from 17 to 31 cycles to complete.
612 ;; It's worth noting that there is no way to saturate all the functional
613 ;; units on the PA8000 as there is not enough issue bandwidth.
615 (define_automaton "pa8000")
616 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
617 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
618 (define_cpu_unit "store_8000" "pa8000")
619 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
620 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
621 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
622 (define_reservation "im_8000" "im0_8000 | im1_8000")
623 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
624 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
625 (define_reservation "f_8000" "f0_8000 | f1_8000")
626 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
628 ;; We can issue any two memops per cycle, but we can only retire
629 ;; one memory store per cycle. We assume that the reorder buffer
630 ;; will hide any memory latencies per HP's recommendation.
631 (define_insn_reservation "Z0" 0
633 (eq_attr "type" "load,fpload")
634 (eq_attr "cpu" "8000"))
637 (define_insn_reservation "Z1" 0
639 (eq_attr "type" "store,fpstore")
640 (eq_attr "cpu" "8000"))
641 "im_8000,rm_8000+store_8000")
643 (define_insn_reservation "Z2" 0
644 (and (eq_attr "type" "fpstore_load,store_fpload")
645 (eq_attr "cpu" "8000"))
646 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
648 ;; We can issue and retire two non-memory operations per cycle with
649 ;; a few exceptions (branches). This group catches those we want
650 ;; to assume have zero latency.
651 (define_insn_reservation "Z3" 0
653 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
654 (eq_attr "cpu" "8000"))
657 ;; Branches use both slots in the non-memory issue and
659 (define_insn_reservation "Z4" 0
661 (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
662 (eq_attr "cpu" "8000"))
663 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
665 ;; We partial latency schedule the floating point units.
666 ;; They can issue/retire two at a time in the non-memory
667 ;; units. We fix their latency at 2 cycles and they
668 ;; are fully pipelined.
669 (define_insn_reservation "Z5" 1
671 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
672 (eq_attr "cpu" "8000"))
673 "inm_8000,f_8000,rnm_8000")
675 ;; The fdivsqrt units are not pipelined and have a very long latency.
676 ;; To keep the DFA from exploding, we do not show all the
677 ;; reservations for the divsqrt unit.
678 (define_insn_reservation "Z6" 17
680 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
681 (eq_attr "cpu" "8000"))
682 "inm_8000,fdivsqrt_8000*6,rnm_8000")
684 (define_insn_reservation "Z7" 31
686 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
687 (eq_attr "cpu" "8000"))
688 "inm_8000,fdivsqrt_8000*6,rnm_8000")
690 ;; Operand and operator predicates and constraints
692 (include "predicates.md")
693 (include "constraints.md")
695 ;; Compare instructions.
696 ;; This controls RTL generation and register allocation.
700 (match_operator:CCFP 2 "comparison_operator"
701 [(match_operand:SF 0 "reg_or_0_operand" "fG")
702 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
703 "! TARGET_SOFT_FLOAT"
704 "fcmp,sgl,%Y2 %f0,%f1"
705 [(set_attr "length" "4")
706 (set_attr "type" "fpcc")])
710 (match_operator:CCFP 2 "comparison_operator"
711 [(match_operand:DF 0 "reg_or_0_operand" "fG")
712 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
713 "! TARGET_SOFT_FLOAT"
714 "fcmp,dbl,%Y2 %f0,%f1"
715 [(set_attr "length" "4")
716 (set_attr "type" "fpcc")])
718 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
719 ;; placeholders. This is necessary in rare situations when a
720 ;; placeholder is re-emitted (see PR 8705).
722 (define_expand "movccfp"
724 (match_operand 0 "const_int_operand" ""))]
725 "! TARGET_SOFT_FLOAT"
728 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
732 ;; The following patterns are optimization placeholders. In almost
733 ;; all cases, the user of the condition code will be simplified and the
734 ;; original condition code setting insn should be eliminated.
736 (define_insn "*movccfp0"
739 "! TARGET_SOFT_FLOAT"
740 "fcmp,dbl,= %%fr0,%%fr0"
741 [(set_attr "length" "4")
742 (set_attr "type" "fpcc")])
744 (define_insn "*movccfp1"
747 "! TARGET_SOFT_FLOAT"
748 "fcmp,dbl,!= %%fr0,%%fr0"
749 [(set_attr "length" "4")
750 (set_attr "type" "fpcc")])
754 (define_expand "cstoresi4"
755 [(set (match_operand:SI 0 "register_operand")
756 (match_operator:SI 1 "ordered_comparison_operator"
757 [(match_operand:SI 2 "reg_or_0_operand" "")
758 (match_operand:SI 3 "arith5_operand" "")]))]
762 ;; Instruction canonicalization puts immediate operands second, which
763 ;; is the reverse of what we want.
766 [(set (match_operand:SI 0 "register_operand" "=r")
767 (match_operator:SI 3 "comparison_operator"
768 [(match_operand:SI 1 "reg_or_0_operand" "rM")
769 (match_operand:SI 2 "arith11_operand" "rI")]))]
771 "{com%I2clr|cmp%I2clr},%B3 %2,%r1,%0\;ldi 1,%0"
772 [(set_attr "type" "binary")
773 (set_attr "length" "8")])
776 [(set (match_operand:DI 0 "register_operand" "=r")
777 (match_operator:DI 3 "comparison_operator"
778 [(match_operand:DI 1 "reg_or_0_operand" "rM")
779 (match_operand:DI 2 "arith11_operand" "rI")]))]
781 "cmp%I2clr,*%B3 %2,%r1,%0\;ldi 1,%0"
782 [(set_attr "type" "binary")
783 (set_attr "length" "8")])
785 (define_insn "iorscc"
786 [(set (match_operand:SI 0 "register_operand" "=r")
787 (ior:SI (match_operator:SI 3 "comparison_operator"
788 [(match_operand:SI 1 "reg_or_0_operand" "rM")
789 (match_operand:SI 2 "arith11_operand" "rI")])
790 (match_operator:SI 6 "comparison_operator"
791 [(match_operand:SI 4 "reg_or_0_operand" "rM")
792 (match_operand:SI 5 "arith11_operand" "rI")])))]
794 "{com%I2clr|cmp%I2clr},%S3 %2,%r1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%r4,%0\;ldi 1,%0"
795 [(set_attr "type" "binary")
796 (set_attr "length" "12")])
799 [(set (match_operand:DI 0 "register_operand" "=r")
800 (ior:DI (match_operator:DI 3 "comparison_operator"
801 [(match_operand:DI 1 "reg_or_0_operand" "rM")
802 (match_operand:DI 2 "arith11_operand" "rI")])
803 (match_operator:DI 6 "comparison_operator"
804 [(match_operand:DI 4 "reg_or_0_operand" "rM")
805 (match_operand:DI 5 "arith11_operand" "rI")])))]
807 "cmp%I2clr,*%S3 %2,%r1,%%r0\;cmp%I5clr,*%B6 %5,%r4,%0\;ldi 1,%0"
808 [(set_attr "type" "binary")
809 (set_attr "length" "12")])
811 ;; Combiner patterns for common operations performed with the output
812 ;; from an scc insn (negscc and incscc).
813 (define_insn "negscc"
814 [(set (match_operand:SI 0 "register_operand" "=r")
815 (neg:SI (match_operator:SI 3 "comparison_operator"
816 [(match_operand:SI 1 "reg_or_0_operand" "rM")
817 (match_operand:SI 2 "arith11_operand" "rI")])))]
819 "{com%I2clr|cmp%I2clr},%B3 %2,%r1,%0\;ldi -1,%0"
820 [(set_attr "type" "binary")
821 (set_attr "length" "8")])
824 [(set (match_operand:DI 0 "register_operand" "=r")
825 (neg:DI (match_operator:DI 3 "comparison_operator"
826 [(match_operand:DI 1 "reg_or_0_operand" "rM")
827 (match_operand:DI 2 "arith11_operand" "rI")])))]
829 "cmp%I2clr,*%B3 %2,%r1,%0\;ldi -1,%0"
830 [(set_attr "type" "binary")
831 (set_attr "length" "8")])
833 ;; Patterns for adding/subtracting the result of a boolean expression from
834 ;; a register. First we have special patterns that make use of the carry
835 ;; bit, and output only two instructions. For the cases we can't in
836 ;; general do in two instructions, the incscc pattern at the end outputs
837 ;; two or three instructions.
840 [(set (match_operand:SI 0 "register_operand" "=r")
841 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
842 (match_operand:SI 3 "arith11_operand" "rI"))
843 (match_operand:SI 1 "register_operand" "r")))]
845 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
846 [(set_attr "type" "binary")
847 (set_attr "length" "8")])
850 [(set (match_operand:DI 0 "register_operand" "=r")
851 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
852 (match_operand:DI 3 "arith11_operand" "rI"))
853 (match_operand:DI 1 "register_operand" "r")))]
855 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
856 [(set_attr "type" "binary")
857 (set_attr "length" "8")])
859 ; This need only accept registers for op3, since canonicalization
860 ; replaces geu with gtu when op3 is an integer.
862 [(set (match_operand:SI 0 "register_operand" "=r")
863 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
864 (match_operand:SI 3 "register_operand" "r"))
865 (match_operand:SI 1 "register_operand" "r")))]
867 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
868 [(set_attr "type" "binary")
869 (set_attr "length" "8")])
872 [(set (match_operand:DI 0 "register_operand" "=r")
873 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
874 (match_operand:DI 3 "register_operand" "r"))
875 (match_operand:DI 1 "register_operand" "r")))]
877 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
878 [(set_attr "type" "binary")
879 (set_attr "length" "8")])
881 ; Match only integers for op3 here. This is used as canonical form of the
882 ; geu pattern when op3 is an integer. Don't match registers since we can't
883 ; make better code than the general incscc pattern.
885 [(set (match_operand:SI 0 "register_operand" "=r")
886 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
887 (match_operand:SI 3 "int11_operand" "I"))
888 (match_operand:SI 1 "register_operand" "r")))]
890 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
891 [(set_attr "type" "binary")
892 (set_attr "length" "8")])
895 [(set (match_operand:DI 0 "register_operand" "=r")
896 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
897 (match_operand:DI 3 "int11_operand" "I"))
898 (match_operand:DI 1 "register_operand" "r")))]
900 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
901 [(set_attr "type" "binary")
902 (set_attr "length" "8")])
904 (define_insn "incscc"
905 [(set (match_operand:SI 0 "register_operand" "=r,r")
906 (plus:SI (match_operator:SI 4 "comparison_operator"
907 [(match_operand:SI 2 "register_operand" "r,r")
908 (match_operand:SI 3 "arith11_operand" "rI,rI")])
909 (match_operand:SI 1 "register_operand" "0,?r")))]
912 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
913 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
914 [(set_attr "type" "binary,binary")
915 (set_attr "length" "8,12")])
918 [(set (match_operand:DI 0 "register_operand" "=r,r")
919 (plus:DI (match_operator:DI 4 "comparison_operator"
920 [(match_operand:DI 2 "register_operand" "r,r")
921 (match_operand:DI 3 "arith11_operand" "rI,rI")])
922 (match_operand:DI 1 "register_operand" "0,?r")))]
925 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
926 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
927 [(set_attr "type" "binary,binary")
928 (set_attr "length" "8,12")])
931 [(set (match_operand:SI 0 "register_operand" "=r")
932 (minus:SI (match_operand:SI 1 "register_operand" "r")
933 (gtu:SI (match_operand:SI 2 "register_operand" "r")
934 (match_operand:SI 3 "arith11_operand" "rI"))))]
936 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
937 [(set_attr "type" "binary")
938 (set_attr "length" "8")])
941 [(set (match_operand:DI 0 "register_operand" "=r")
942 (minus:DI (match_operand:DI 1 "register_operand" "r")
943 (gtu:DI (match_operand:DI 2 "register_operand" "r")
944 (match_operand:DI 3 "arith11_operand" "rI"))))]
946 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
947 [(set_attr "type" "binary")
948 (set_attr "length" "8")])
951 [(set (match_operand:SI 0 "register_operand" "=r")
952 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
953 (gtu:SI (match_operand:SI 2 "register_operand" "r")
954 (match_operand:SI 3 "arith11_operand" "rI")))
955 (match_operand:SI 4 "register_operand" "r")))]
957 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
958 [(set_attr "type" "binary")
959 (set_attr "length" "8")])
962 [(set (match_operand:DI 0 "register_operand" "=r")
963 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
964 (gtu:DI (match_operand:DI 2 "register_operand" "r")
965 (match_operand:DI 3 "arith11_operand" "rI")))
966 (match_operand:DI 4 "register_operand" "r")))]
968 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
969 [(set_attr "type" "binary")
970 (set_attr "length" "8")])
972 ; This need only accept registers for op3, since canonicalization
973 ; replaces ltu with leu when op3 is an integer.
975 [(set (match_operand:SI 0 "register_operand" "=r")
976 (minus:SI (match_operand:SI 1 "register_operand" "r")
977 (ltu:SI (match_operand:SI 2 "register_operand" "r")
978 (match_operand:SI 3 "register_operand" "r"))))]
980 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
981 [(set_attr "type" "binary")
982 (set_attr "length" "8")])
985 [(set (match_operand:DI 0 "register_operand" "=r")
986 (minus:DI (match_operand:DI 1 "register_operand" "r")
987 (ltu:DI (match_operand:DI 2 "register_operand" "r")
988 (match_operand:DI 3 "register_operand" "r"))))]
990 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
991 [(set_attr "type" "binary")
992 (set_attr "length" "8")])
995 [(set (match_operand:SI 0 "register_operand" "=r")
996 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
997 (ltu:SI (match_operand:SI 2 "register_operand" "r")
998 (match_operand:SI 3 "register_operand" "r")))
999 (match_operand:SI 4 "register_operand" "r")))]
1001 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1002 [(set_attr "type" "binary")
1003 (set_attr "length" "8")])
1006 [(set (match_operand:DI 0 "register_operand" "=r")
1007 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1008 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1009 (match_operand:DI 3 "register_operand" "r")))
1010 (match_operand:DI 4 "register_operand" "r")))]
1012 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1013 [(set_attr "type" "binary")
1014 (set_attr "length" "8")])
1016 ; Match only integers for op3 here. This is used as canonical form of the
1017 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1018 ; make better code than the general incscc pattern.
1020 [(set (match_operand:SI 0 "register_operand" "=r")
1021 (minus:SI (match_operand:SI 1 "register_operand" "r")
1022 (leu:SI (match_operand:SI 2 "register_operand" "r")
1023 (match_operand:SI 3 "int11_operand" "I"))))]
1025 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1026 [(set_attr "type" "binary")
1027 (set_attr "length" "8")])
1030 [(set (match_operand:DI 0 "register_operand" "=r")
1031 (minus:DI (match_operand:DI 1 "register_operand" "r")
1032 (leu:DI (match_operand:DI 2 "register_operand" "r")
1033 (match_operand:DI 3 "int11_operand" "I"))))]
1035 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1036 [(set_attr "type" "binary")
1037 (set_attr "length" "8")])
1040 [(set (match_operand:SI 0 "register_operand" "=r")
1041 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1042 (leu:SI (match_operand:SI 2 "register_operand" "r")
1043 (match_operand:SI 3 "int11_operand" "I")))
1044 (match_operand:SI 4 "register_operand" "r")))]
1046 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1047 [(set_attr "type" "binary")
1048 (set_attr "length" "8")])
1051 [(set (match_operand:DI 0 "register_operand" "=r")
1052 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1053 (leu:DI (match_operand:DI 2 "register_operand" "r")
1054 (match_operand:DI 3 "int11_operand" "I")))
1055 (match_operand:DI 4 "register_operand" "r")))]
1057 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1058 [(set_attr "type" "binary")
1059 (set_attr "length" "8")])
1061 (define_insn "decscc"
1062 [(set (match_operand:SI 0 "register_operand" "=r,r")
1063 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1064 (match_operator:SI 4 "comparison_operator"
1065 [(match_operand:SI 2 "register_operand" "r,r")
1066 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1069 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1070 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1071 [(set_attr "type" "binary,binary")
1072 (set_attr "length" "8,12")])
1075 [(set (match_operand:DI 0 "register_operand" "=r,r")
1076 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1077 (match_operator:DI 4 "comparison_operator"
1078 [(match_operand:DI 2 "register_operand" "r,r")
1079 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1082 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1083 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1084 [(set_attr "type" "binary,binary")
1085 (set_attr "length" "8,12")])
1087 ; Patterns for max and min. (There is no need for an earlyclobber in the
1088 ; last alternative since the middle alternative will match if op0 == op1.)
1090 (define_insn "sminsi3"
1091 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1092 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1093 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1096 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1097 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1098 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1099 [(set_attr "type" "multi,multi,multi")
1100 (set_attr "length" "8,8,8")])
1102 (define_insn "smindi3"
1103 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1104 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1105 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1108 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1109 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1110 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1111 [(set_attr "type" "multi,multi,multi")
1112 (set_attr "length" "8,8,8")])
1114 (define_insn "uminsi3"
1115 [(set (match_operand:SI 0 "register_operand" "=r,r")
1116 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1117 (match_operand:SI 2 "arith11_operand" "r,I")))]
1120 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1121 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1122 [(set_attr "type" "multi,multi")
1123 (set_attr "length" "8,8")])
1125 (define_insn "umindi3"
1126 [(set (match_operand:DI 0 "register_operand" "=r,r")
1127 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1128 (match_operand:DI 2 "arith11_operand" "r,I")))]
1131 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1132 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1133 [(set_attr "type" "multi,multi")
1134 (set_attr "length" "8,8")])
1136 (define_insn "smaxsi3"
1137 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1138 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1139 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1142 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1143 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1144 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1145 [(set_attr "type" "multi,multi,multi")
1146 (set_attr "length" "8,8,8")])
1148 (define_insn "smaxdi3"
1149 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1150 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1151 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1154 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1155 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1156 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1157 [(set_attr "type" "multi,multi,multi")
1158 (set_attr "length" "8,8,8")])
1160 (define_insn "umaxsi3"
1161 [(set (match_operand:SI 0 "register_operand" "=r,r")
1162 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1163 (match_operand:SI 2 "arith11_operand" "r,I")))]
1166 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1167 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1168 [(set_attr "type" "multi,multi")
1169 (set_attr "length" "8,8")])
1171 (define_insn "umaxdi3"
1172 [(set (match_operand:DI 0 "register_operand" "=r,r")
1173 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1174 (match_operand:DI 2 "arith11_operand" "r,I")))]
1177 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1178 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1179 [(set_attr "type" "multi,multi")
1180 (set_attr "length" "8,8")])
1182 (define_insn "absqi2"
1183 [(set (match_operand:QI 0 "register_operand" "=r")
1184 (abs:QI (match_operand:QI 1 "register_operand" "r")))]
1186 "{extrs|extrw,s},>= %1,31,8,%0\;subi 0,%0,%0"
1187 [(set_attr "type" "multi")
1188 (set_attr "length" "8")])
1190 (define_insn "abshi2"
1191 [(set (match_operand:HI 0 "register_operand" "=r")
1192 (abs:HI (match_operand:HI 1 "register_operand" "r")))]
1194 "{extrs|extrw,s},>= %1,31,16,%0\;subi 0,%0,%0"
1195 [(set_attr "type" "multi")
1196 (set_attr "length" "8")])
1198 (define_insn "abssi2"
1199 [(set (match_operand:SI 0 "register_operand" "=r")
1200 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1202 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1203 [(set_attr "type" "multi")
1204 (set_attr "length" "8")])
1206 (define_insn "absdi2"
1207 [(set (match_operand:DI 0 "register_operand" "=r")
1208 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1210 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1211 [(set_attr "type" "multi")
1212 (set_attr "length" "8")])
1214 (define_insn "bswaphi2"
1215 [(set (match_operand:HI 0 "register_operand" "=&r")
1216 (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
1218 "{extru|extrw,u} %1,23,8,%0\;{dep|depw} %1,23,8,%0"
1219 [(set_attr "type" "multi")
1220 (set_attr "length" "8")])
1222 (define_insn "bswapsi2"
1223 [(set (match_operand:SI 0 "register_operand" "=&r")
1224 (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "{shd|shrpw} %1,%1,16,%0\;{dep|depw} %0,15,8,%0\;{shd|shrpw} %1,%0,8,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "12")])
1230 (define_insn "bswapdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=&r")
1232 (bswap:DI (match_operand:DI 1 "register_operand" "r")))
1233 (clobber (match_scratch:DI 2 "=r"))]
1235 "permh,3210 %1,%2\;hshl %2,8,%0\;hshr,u %2,8,%2\;or %0,%2,%0"
1236 [(set_attr "type" "multi")
1237 (set_attr "length" "16")])
1239 ;;; Experimental conditional move patterns
1241 (define_expand "movsicc"
1242 [(set (match_operand:SI 0 "register_operand" "")
1244 (match_operand 1 "comparison_operator" "")
1245 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1246 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1250 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1251 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1255 ;; We used to accept any register for op1.
1257 ;; However, it loses sometimes because the compiler will end up using
1258 ;; different registers for op0 and op1 in some critical cases. local-alloc
1259 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1261 ;; If/when global register allocation supports tying we should allow any
1262 ;; register for op1 again.
1264 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1266 (match_operator 2 "comparison_operator"
1267 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1268 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1269 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1273 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1274 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1275 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1276 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1277 [(set_attr "type" "multi,multi,multi,nullshift")
1278 (set_attr "length" "8,8,8,8")])
1281 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1283 (match_operator 5 "comparison_operator"
1284 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1285 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1286 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1287 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1290 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1291 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1292 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1293 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1294 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1295 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1296 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1297 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1298 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1299 (set_attr "length" "8,8,8,8,8,8,8,8")])
1301 (define_expand "movdicc"
1302 [(set (match_operand:DI 0 "register_operand" "")
1304 (match_operand 1 "comparison_operator" "")
1305 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1306 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1310 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1311 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1315 ; We need the first constraint alternative in order to avoid
1316 ; earlyclobbers on all other alternatives.
1318 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1320 (match_operator 2 "comparison_operator"
1321 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1322 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1323 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1327 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1328 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1329 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1330 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1331 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1332 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1333 (set_attr "length" "8,8,8,8,8")])
1336 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1338 (match_operator 5 "comparison_operator"
1339 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1340 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1341 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1342 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1345 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1346 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1347 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1348 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1349 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1350 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1351 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1352 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1353 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1354 (set_attr "length" "8,8,8,8,8,8,8,8")])
1356 ;; Conditional Branches
1358 (define_expand "cbranchdi4"
1360 (if_then_else (match_operator 0 "ordered_comparison_operator"
1361 [(match_operand:DI 1 "reg_or_0_operand" "")
1362 (match_operand:DI 2 "register_operand" "")])
1363 (label_ref (match_operand 3 "" ""))
1368 (define_expand "cbranchsi4"
1370 (if_then_else (match_operator 0 "ordered_comparison_operator"
1371 [(match_operand:SI 1 "reg_or_0_operand" "")
1372 (match_operand:SI 2 "arith5_operand" "")])
1373 (label_ref (match_operand 3 "" ""))
1378 (define_expand "cbranchsf4"
1380 (if_then_else (match_operator 0 "comparison_operator"
1381 [(match_operand:SF 1 "reg_or_0_operand" "")
1382 (match_operand:SF 2 "reg_or_0_operand" "")])
1383 (label_ref (match_operand 3 "" ""))
1388 pa_emit_bcond_fp (operands);
1393 (define_expand "cbranchdf4"
1395 (if_then_else (match_operator 0 "comparison_operator"
1396 [(match_operand:DF 1 "reg_or_0_operand" "")
1397 (match_operand:DF 2 "reg_or_0_operand" "")])
1398 (label_ref (match_operand 3 "" ""))
1403 pa_emit_bcond_fp (operands);
1407 ;; Match the branch patterns.
1410 ;; Note a long backward conditional branch with an annulled delay slot
1411 ;; has a length of 12.
1415 (match_operator 3 "comparison_operator"
1416 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1417 (match_operand:SI 2 "arith5_operand" "rL")])
1418 (label_ref (match_operand 0 "" ""))
1423 return pa_output_cbranch (operands, 0, insn);
1425 [(set_attr "type" "cbranch")
1426 (set (attr "length")
1427 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1428 (const_int MAX_12BIT_OFFSET))
1430 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1431 (const_int MAX_17BIT_OFFSET))
1433 (match_test "TARGET_PORTABLE_RUNTIME")
1435 (not (match_test "flag_pic"))
1439 ;; Match the negated branch.
1444 (match_operator 3 "comparison_operator"
1445 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1446 (match_operand:SI 2 "arith5_operand" "rL")])
1448 (label_ref (match_operand 0 "" ""))))]
1452 return pa_output_cbranch (operands, 1, insn);
1454 [(set_attr "type" "cbranch")
1455 (set (attr "length")
1456 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1457 (const_int MAX_12BIT_OFFSET))
1459 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1460 (const_int MAX_17BIT_OFFSET))
1462 (match_test "TARGET_PORTABLE_RUNTIME")
1464 (not (match_test "flag_pic"))
1471 (match_operator 3 "comparison_operator"
1472 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1473 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1474 (label_ref (match_operand 0 "" ""))
1479 return pa_output_cbranch (operands, 0, insn);
1481 [(set_attr "type" "cbranch")
1482 (set (attr "length")
1483 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1484 (const_int MAX_12BIT_OFFSET))
1486 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1487 (const_int MAX_17BIT_OFFSET))
1489 (match_test "TARGET_PORTABLE_RUNTIME")
1491 (not (match_test "flag_pic"))
1495 ;; Match the negated branch.
1500 (match_operator 3 "comparison_operator"
1501 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1502 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1504 (label_ref (match_operand 0 "" ""))))]
1508 return pa_output_cbranch (operands, 1, insn);
1510 [(set_attr "type" "cbranch")
1511 (set (attr "length")
1512 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1513 (const_int MAX_12BIT_OFFSET))
1515 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1516 (const_int MAX_17BIT_OFFSET))
1518 (match_test "TARGET_PORTABLE_RUNTIME")
1520 (not (match_test "flag_pic"))
1526 (match_operator 3 "cmpib_comparison_operator"
1527 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1528 (match_operand:DI 2 "arith5_operand" "rL")])
1529 (label_ref (match_operand 0 "" ""))
1534 return pa_output_cbranch (operands, 0, insn);
1536 [(set_attr "type" "cbranch")
1537 (set (attr "length")
1538 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1539 (const_int MAX_12BIT_OFFSET))
1541 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1542 (const_int MAX_17BIT_OFFSET))
1544 (match_test "TARGET_PORTABLE_RUNTIME")
1546 (not (match_test "flag_pic"))
1550 ;; Match the negated branch.
1555 (match_operator 3 "cmpib_comparison_operator"
1556 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1557 (match_operand:DI 2 "arith5_operand" "rL")])
1559 (label_ref (match_operand 0 "" ""))))]
1563 return pa_output_cbranch (operands, 1, insn);
1565 [(set_attr "type" "cbranch")
1566 (set (attr "length")
1567 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1568 (const_int MAX_12BIT_OFFSET))
1570 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1571 (const_int MAX_17BIT_OFFSET))
1573 (match_test "TARGET_PORTABLE_RUNTIME")
1575 (not (match_test "flag_pic"))
1579 ;; Branch on Bit patterns.
1583 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1585 (match_operand:SI 1 "uint5_operand" ""))
1587 (label_ref (match_operand 2 "" ""))
1592 return pa_output_bb (operands, 0, insn, 0);
1594 [(set_attr "type" "cbranch")
1595 (set (attr "length")
1596 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1597 (const_int MAX_12BIT_OFFSET))
1599 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1600 (const_int MAX_17BIT_OFFSET))
1602 (match_test "TARGET_PORTABLE_RUNTIME")
1604 (not (match_test "flag_pic"))
1611 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1613 (match_operand:DI 1 "uint32_operand" ""))
1615 (label_ref (match_operand 2 "" ""))
1620 return pa_output_bb (operands, 0, insn, 0);
1622 [(set_attr "type" "cbranch")
1623 (set (attr "length")
1624 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1625 (const_int MAX_12BIT_OFFSET))
1627 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1628 (const_int MAX_17BIT_OFFSET))
1630 (match_test "TARGET_PORTABLE_RUNTIME")
1632 (not (match_test "flag_pic"))
1639 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1641 (match_operand:SI 1 "uint5_operand" ""))
1644 (label_ref (match_operand 2 "" ""))))]
1648 return pa_output_bb (operands, 1, insn, 0);
1650 [(set_attr "type" "cbranch")
1651 (set (attr "length")
1652 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1653 (const_int MAX_12BIT_OFFSET))
1655 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1656 (const_int MAX_17BIT_OFFSET))
1658 (match_test "TARGET_PORTABLE_RUNTIME")
1660 (not (match_test "flag_pic"))
1667 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1669 (match_operand:DI 1 "uint32_operand" ""))
1672 (label_ref (match_operand 2 "" ""))))]
1676 return pa_output_bb (operands, 1, insn, 0);
1678 [(set_attr "type" "cbranch")
1679 (set (attr "length")
1680 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1681 (const_int MAX_12BIT_OFFSET))
1683 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1684 (const_int MAX_17BIT_OFFSET))
1686 (match_test "TARGET_PORTABLE_RUNTIME")
1688 (not (match_test "flag_pic"))
1695 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1697 (match_operand:SI 1 "uint5_operand" ""))
1699 (label_ref (match_operand 2 "" ""))
1704 return pa_output_bb (operands, 0, insn, 1);
1706 [(set_attr "type" "cbranch")
1707 (set (attr "length")
1708 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1709 (const_int MAX_12BIT_OFFSET))
1711 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1712 (const_int MAX_17BIT_OFFSET))
1714 (match_test "TARGET_PORTABLE_RUNTIME")
1716 (not (match_test "flag_pic"))
1723 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1725 (match_operand:DI 1 "uint32_operand" ""))
1727 (label_ref (match_operand 2 "" ""))
1732 return pa_output_bb (operands, 0, insn, 1);
1734 [(set_attr "type" "cbranch")
1735 (set (attr "length")
1736 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1737 (const_int MAX_12BIT_OFFSET))
1739 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1740 (const_int MAX_17BIT_OFFSET))
1742 (match_test "TARGET_PORTABLE_RUNTIME")
1744 (not (match_test "flag_pic"))
1751 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1753 (match_operand:SI 1 "uint5_operand" ""))
1756 (label_ref (match_operand 2 "" ""))))]
1760 return pa_output_bb (operands, 1, insn, 1);
1762 [(set_attr "type" "cbranch")
1763 (set (attr "length")
1764 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1765 (const_int MAX_12BIT_OFFSET))
1767 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1768 (const_int MAX_17BIT_OFFSET))
1770 (match_test "TARGET_PORTABLE_RUNTIME")
1772 (not (match_test "flag_pic"))
1779 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1781 (match_operand:DI 1 "uint32_operand" ""))
1784 (label_ref (match_operand 2 "" ""))))]
1788 return pa_output_bb (operands, 1, insn, 1);
1790 [(set_attr "type" "cbranch")
1791 (set (attr "length")
1792 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1793 (const_int MAX_12BIT_OFFSET))
1795 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1796 (const_int MAX_17BIT_OFFSET))
1798 (match_test "TARGET_PORTABLE_RUNTIME")
1800 (not (match_test "flag_pic"))
1804 ;; Branch on Variable Bit patterns.
1808 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1810 (match_operand:SI 1 "register_operand" "q"))
1812 (label_ref (match_operand 2 "" ""))
1817 return pa_output_bvb (operands, 0, insn, 0);
1819 [(set_attr "type" "cbranch")
1820 (set (attr "length")
1821 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1822 (const_int MAX_12BIT_OFFSET))
1824 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1825 (const_int MAX_17BIT_OFFSET))
1827 (match_test "TARGET_PORTABLE_RUNTIME")
1829 (not (match_test "flag_pic"))
1836 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1838 (match_operand:DI 1 "register_operand" "q"))
1840 (label_ref (match_operand 2 "" ""))
1845 return pa_output_bvb (operands, 0, insn, 0);
1847 [(set_attr "type" "cbranch")
1848 (set (attr "length")
1849 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1850 (const_int MAX_12BIT_OFFSET))
1852 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1853 (const_int MAX_17BIT_OFFSET))
1855 (match_test "TARGET_PORTABLE_RUNTIME")
1857 (not (match_test "flag_pic"))
1864 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1866 (match_operand:SI 1 "register_operand" "q"))
1869 (label_ref (match_operand 2 "" ""))))]
1873 return pa_output_bvb (operands, 1, insn, 0);
1875 [(set_attr "type" "cbranch")
1876 (set (attr "length")
1877 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1878 (const_int MAX_12BIT_OFFSET))
1880 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1881 (const_int MAX_17BIT_OFFSET))
1883 (match_test "TARGET_PORTABLE_RUNTIME")
1885 (not (match_test "flag_pic"))
1892 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1894 (match_operand:DI 1 "register_operand" "q"))
1897 (label_ref (match_operand 2 "" ""))))]
1901 return pa_output_bvb (operands, 1, insn, 0);
1903 [(set_attr "type" "cbranch")
1904 (set (attr "length")
1905 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1906 (const_int MAX_12BIT_OFFSET))
1908 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1909 (const_int MAX_17BIT_OFFSET))
1911 (match_test "TARGET_PORTABLE_RUNTIME")
1913 (not (match_test "flag_pic"))
1920 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1922 (match_operand:SI 1 "register_operand" "q"))
1924 (label_ref (match_operand 2 "" ""))
1929 return pa_output_bvb (operands, 0, insn, 1);
1931 [(set_attr "type" "cbranch")
1932 (set (attr "length")
1933 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1934 (const_int MAX_12BIT_OFFSET))
1936 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1937 (const_int MAX_17BIT_OFFSET))
1939 (match_test "TARGET_PORTABLE_RUNTIME")
1941 (not (match_test "flag_pic"))
1948 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1950 (match_operand:DI 1 "register_operand" "q"))
1952 (label_ref (match_operand 2 "" ""))
1957 return pa_output_bvb (operands, 0, insn, 1);
1959 [(set_attr "type" "cbranch")
1960 (set (attr "length")
1961 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1962 (const_int MAX_12BIT_OFFSET))
1964 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1965 (const_int MAX_17BIT_OFFSET))
1967 (match_test "TARGET_PORTABLE_RUNTIME")
1969 (not (match_test "flag_pic"))
1976 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1978 (match_operand:SI 1 "register_operand" "q"))
1981 (label_ref (match_operand 2 "" ""))))]
1985 return pa_output_bvb (operands, 1, insn, 1);
1987 [(set_attr "type" "cbranch")
1988 (set (attr "length")
1989 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1990 (const_int MAX_12BIT_OFFSET))
1992 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (const_int MAX_17BIT_OFFSET))
1995 (match_test "TARGET_PORTABLE_RUNTIME")
1997 (not (match_test "flag_pic"))
2004 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2006 (match_operand:DI 1 "register_operand" "q"))
2009 (label_ref (match_operand 2 "" ""))))]
2013 return pa_output_bvb (operands, 1, insn, 1);
2015 [(set_attr "type" "cbranch")
2016 (set (attr "length")
2017 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2018 (const_int MAX_12BIT_OFFSET))
2020 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2021 (const_int MAX_17BIT_OFFSET))
2023 (match_test "TARGET_PORTABLE_RUNTIME")
2025 (not (match_test "flag_pic"))
2029 ;; Floating point branches
2031 ;; ??? Nullification is handled differently from other branches.
2032 ;; If nullification is specified, the delay slot is nullified on any
2033 ;; taken branch regardless of branch direction.
2035 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2036 (label_ref (match_operand 0 "" ""))
2038 "!TARGET_SOFT_FLOAT"
2041 int length = get_attr_length (insn);
2043 int nullify, xdelay;
2046 return \"ftest\;b%* %l0\";
2048 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2052 xoperands[0] = GEN_INT (length - 8);
2058 xoperands[0] = GEN_INT (length - 4);
2062 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2064 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2065 return pa_output_lbranch (operands[0], insn, xdelay);
2067 [(set_attr "type" "fbranch")
2068 (set (attr "length")
2069 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2070 (const_int MAX_17BIT_OFFSET))
2072 (match_test "TARGET_PORTABLE_RUNTIME")
2074 (not (match_test "flag_pic"))
2079 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2081 (label_ref (match_operand 0 "" ""))))]
2082 "!TARGET_SOFT_FLOAT"
2085 int length = get_attr_length (insn);
2087 int nullify, xdelay;
2090 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2092 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2096 xoperands[0] = GEN_INT (length - 4);
2102 xoperands[0] = GEN_INT (length);
2106 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2108 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2109 return pa_output_lbranch (operands[0], insn, xdelay);
2111 [(set_attr "type" "fbranch")
2112 (set (attr "length")
2113 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2114 (const_int MAX_17BIT_OFFSET))
2116 (match_test "TARGET_PORTABLE_RUNTIME")
2118 (not (match_test "flag_pic"))
2122 ;; Move instructions
2124 (define_expand "movsi"
2125 [(set (match_operand:SI 0 "general_operand" "")
2126 (match_operand:SI 1 "general_operand" ""))]
2130 if (pa_emit_move_sequence (operands, SImode, 0))
2134 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2135 (define_expand "reload_insi_r1"
2136 [(set (match_operand:SI 0 "register_operand" "=Z")
2137 (match_operand:SI 1 "non_hard_reg_operand" ""))
2138 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2142 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2145 /* We don't want the clobber emitted, so handle this ourselves. */
2146 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2150 ;; Handle SImode input reloads requiring a general register as a
2151 ;; scratch register.
2152 (define_expand "reload_insi"
2153 [(set (match_operand:SI 0 "register_operand" "=Z")
2154 (match_operand:SI 1 "non_hard_reg_operand" ""))
2155 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2159 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2162 /* We don't want the clobber emitted, so handle this ourselves. */
2163 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2167 ;; Handle SImode output reloads requiring a general register as a
2168 ;; scratch register.
2169 (define_expand "reload_outsi"
2170 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2171 (match_operand:SI 1 "register_operand" "Z"))
2172 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2176 if (pa_emit_move_sequence (operands, SImode, operands[2]))
2179 /* We don't want the clobber emitted, so handle this ourselves. */
2180 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2185 [(set (match_operand:SI 0 "move_dest_operand"
2186 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2187 (match_operand:SI 1 "move_src_operand"
2188 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2189 "(register_operand (operands[0], SImode)
2190 || reg_or_0_operand (operands[1], SImode))
2191 && !TARGET_SOFT_FLOAT
2198 {zdepi|depwi,z} %Z1,%0
2202 {mfctl|mfctl,w} %%sar,%0
2206 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2207 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2208 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2209 (set_attr "pa_combine_type" "addmove")
2210 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2213 [(set (match_operand:SI 0 "move_dest_operand"
2214 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2215 (match_operand:SI 1 "move_src_operand"
2216 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2217 "(register_operand (operands[0], SImode)
2218 || reg_or_0_operand (operands[1], SImode))
2219 && !TARGET_SOFT_FLOAT
2226 {zdepi|depwi,z} %Z1,%0
2230 {mfctl|mfctl,w} %%sar,%0
2234 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2235 (set_attr "pa_combine_type" "addmove")
2236 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2239 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2240 (match_operand:SI 1 "register_operand" "f"))]
2242 && !TARGET_DISABLE_INDEXING
2243 && reload_completed"
2245 [(set_attr "type" "fpstore")
2246 (set_attr "pa_combine_type" "addmove")
2247 (set_attr "length" "4")])
2249 ; Rewrite RTL using an indexed store. This will allow the insn that
2250 ; computes the address to be deleted if the register it sets is dead.
2252 [(set (match_operand:SI 0 "register_operand" "")
2253 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
2255 (match_operand:SI 2 "register_operand" "")))
2256 (set (mem:SI (match_dup 0))
2257 (match_operand:SI 3 "register_operand" ""))]
2259 && !TARGET_DISABLE_INDEXING
2260 && REG_OK_FOR_BASE_P (operands[2])
2261 && FP_REGNO_P (REGNO (operands[3]))"
2262 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2264 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 2))
2269 [(set (match_operand:DI 0 "register_operand" "")
2270 (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
2272 (match_operand:DI 2 "register_operand" "")))
2273 (set (mem:SI (match_dup 0))
2274 (match_operand:SI 3 "register_operand" ""))]
2276 && !TARGET_DISABLE_INDEXING
2278 && REG_OK_FOR_BASE_P (operands[2])
2279 && FP_REGNO_P (REGNO (operands[3]))"
2280 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2282 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 2))
2287 [(set (match_operand:SI 0 "register_operand" "")
2288 (plus:SI (match_operand:SI 1 "register_operand" "")
2289 (match_operand:SI 2 "register_operand" "")))
2290 (set (mem:SI (match_dup 0))
2291 (match_operand:SI 3 "register_operand" ""))]
2293 && !TARGET_DISABLE_INDEXING
2294 && TARGET_NO_SPACE_REGS
2295 && REG_OK_FOR_INDEX_P (operands[1])
2296 && REG_OK_FOR_BASE_P (operands[2])
2297 && FP_REGNO_P (REGNO (operands[3]))"
2298 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2300 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2304 [(set (match_operand:SI 0 "register_operand" "")
2305 (plus:SI (match_operand:SI 1 "register_operand" "")
2306 (match_operand:SI 2 "register_operand" "")))
2307 (set (mem:SI (match_dup 0))
2308 (match_operand:SI 3 "register_operand" ""))]
2310 && !TARGET_DISABLE_INDEXING
2311 && TARGET_NO_SPACE_REGS
2312 && REG_OK_FOR_BASE_P (operands[1])
2313 && REG_OK_FOR_INDEX_P (operands[2])
2314 && FP_REGNO_P (REGNO (operands[3]))"
2315 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2317 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2321 [(set (match_operand:DI 0 "register_operand" "")
2322 (plus:DI (match_operand:DI 1 "register_operand" "")
2323 (match_operand:DI 2 "register_operand" "")))
2324 (set (mem:SI (match_dup 0))
2325 (match_operand:SI 3 "register_operand" ""))]
2327 && !TARGET_DISABLE_INDEXING
2329 && TARGET_NO_SPACE_REGS
2330 && REG_OK_FOR_INDEX_P (operands[1])
2331 && REG_OK_FOR_BASE_P (operands[2])
2332 && FP_REGNO_P (REGNO (operands[3]))"
2333 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2335 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2339 [(set (match_operand:DI 0 "register_operand" "")
2340 (plus:DI (match_operand:DI 1 "register_operand" "")
2341 (match_operand:DI 2 "register_operand" "")))
2342 (set (mem:SI (match_dup 0))
2343 (match_operand:SI 3 "register_operand" ""))]
2345 && !TARGET_DISABLE_INDEXING
2347 && TARGET_NO_SPACE_REGS
2348 && REG_OK_FOR_BASE_P (operands[1])
2349 && REG_OK_FOR_INDEX_P (operands[2])
2350 && FP_REGNO_P (REGNO (operands[3]))"
2351 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2353 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2357 [(set (match_operand:SI 0 "move_dest_operand"
2358 "=r,r,r,r,r,r,Q,!*q,!r")
2359 (match_operand:SI 1 "move_src_operand"
2360 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2361 "(register_operand (operands[0], SImode)
2362 || reg_or_0_operand (operands[1], SImode))
2363 && TARGET_SOFT_FLOAT"
2369 {zdepi|depwi,z} %Z1,%0
2373 {mfctl|mfctl,w} %%sar,%0"
2374 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2375 (set_attr "pa_combine_type" "addmove")
2376 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2378 ;; Load or store with base-register modification.
2380 [(set (match_operand:SI 0 "register_operand" "=r")
2381 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2382 (match_operand:DI 2 "int5_operand" "L"))))
2384 (plus:DI (match_dup 1) (match_dup 2)))]
2387 [(set_attr "type" "load")
2388 (set_attr "length" "4")])
2390 ; And a zero extended variant.
2392 [(set (match_operand:DI 0 "register_operand" "=r")
2393 (zero_extend:DI (mem:SI
2395 (match_operand:DI 1 "register_operand" "+r")
2396 (match_operand:DI 2 "int5_operand" "L")))))
2398 (plus:DI (match_dup 1) (match_dup 2)))]
2401 [(set_attr "type" "load")
2402 (set_attr "length" "4")])
2404 (define_expand "pre_load"
2405 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2406 (mem (plus (match_operand 1 "register_operand" "")
2407 (match_operand 2 "pre_cint_operand" ""))))
2409 (plus (match_dup 1) (match_dup 2)))])]
2415 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2418 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2422 (define_insn "pre_ldw"
2423 [(set (match_operand:SI 0 "register_operand" "=r")
2424 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2425 (match_operand:SI 2 "pre_cint_operand" ""))))
2427 (plus:SI (match_dup 1) (match_dup 2)))]
2431 if (INTVAL (operands[2]) < 0)
2432 return \"{ldwm|ldw,mb} %2(%1),%0\";
2433 return \"{ldws|ldw},mb %2(%1),%0\";
2435 [(set_attr "type" "load")
2436 (set_attr "length" "4")])
2438 (define_insn "pre_ldd"
2439 [(set (match_operand:DI 0 "register_operand" "=r")
2440 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2441 (match_operand:DI 2 "pre_cint_operand" ""))))
2443 (plus:DI (match_dup 1) (match_dup 2)))]
2446 [(set_attr "type" "load")
2447 (set_attr "length" "4")])
2450 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2451 (match_operand:SI 1 "pre_cint_operand" "")))
2452 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2454 (plus:SI (match_dup 0) (match_dup 1)))]
2458 if (INTVAL (operands[1]) < 0)
2459 return \"{stwm|stw,mb} %r2,%1(%0)\";
2460 return \"{stws|stw},mb %r2,%1(%0)\";
2462 [(set_attr "type" "store")
2463 (set_attr "length" "4")])
2466 [(set (match_operand:SI 0 "register_operand" "=r")
2467 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2469 (plus:SI (match_dup 1)
2470 (match_operand:SI 2 "post_cint_operand" "")))]
2474 if (INTVAL (operands[2]) > 0)
2475 return \"{ldwm|ldw,ma} %2(%1),%0\";
2476 return \"{ldws|ldw},ma %2(%1),%0\";
2478 [(set_attr "type" "load")
2479 (set_attr "length" "4")])
2481 (define_expand "post_store"
2482 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2483 (match_operand 1 "reg_or_0_operand" ""))
2486 (match_operand 2 "post_cint_operand" "")))])]
2492 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2495 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2499 (define_insn "post_stw"
2500 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2501 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2503 (plus:SI (match_dup 0)
2504 (match_operand:SI 2 "post_cint_operand" "")))]
2508 if (INTVAL (operands[2]) > 0)
2509 return \"{stwm|stw,ma} %r1,%2(%0)\";
2510 return \"{stws|stw},ma %r1,%2(%0)\";
2512 [(set_attr "type" "store")
2513 (set_attr "length" "4")])
2515 (define_insn "post_std"
2516 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2517 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2519 (plus:DI (match_dup 0)
2520 (match_operand:DI 2 "post_cint_operand" "")))]
2523 [(set_attr "type" "store")
2524 (set_attr "length" "4")])
2526 ;; For loading the address of a label while generating PIC code.
2527 ;; Note since this pattern can be created at reload time (via movsi), all
2528 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2530 [(set (match_operand 0 "pmode_register_operand" "=a")
2531 (match_operand 1 "pic_label_operand" ""))]
2537 xoperands[0] = operands[0];
2538 xoperands[1] = operands[1];
2539 xoperands[2] = gen_label_rtx ();
2541 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2542 CODE_LABEL_NUMBER (xoperands[2]));
2543 output_asm_insn (\"mfia %0\", xoperands);
2545 /* If we're trying to load the address of a label that happens to be
2546 close, then we can use a shorter sequence. */
2547 if (GET_CODE (operands[1]) == LABEL_REF
2548 && !LABEL_REF_NONLOCAL_P (operands[1])
2549 && INSN_ADDRESSES_SET_P ()
2550 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2551 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2552 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2555 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2556 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2560 [(set_attr "type" "multi")
2561 (set_attr "length" "12")]) ; 8 or 12
2564 [(set (match_operand 0 "pmode_register_operand" "=a")
2565 (match_operand 1 "pic_label_operand" ""))]
2571 xoperands[0] = operands[0];
2572 xoperands[1] = operands[1];
2573 xoperands[2] = gen_label_rtx ();
2575 output_asm_insn (\"bl .+8,%0\", xoperands);
2576 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2577 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2578 CODE_LABEL_NUMBER (xoperands[2]));
2580 /* If we're trying to load the address of a label that happens to be
2581 close, then we can use a shorter sequence. */
2582 if (GET_CODE (operands[1]) == LABEL_REF
2583 && !LABEL_REF_NONLOCAL_P (operands[1])
2584 && INSN_ADDRESSES_SET_P ()
2585 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2586 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2587 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2590 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2591 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2595 [(set_attr "type" "multi")
2596 (set_attr "length" "16")]) ; 12 or 16
2599 [(set (match_operand:SI 0 "register_operand" "=a")
2600 (plus:SI (match_operand:SI 1 "register_operand" "r")
2601 (high:SI (match_operand 2 "" ""))))]
2602 "symbolic_operand (operands[2], Pmode)
2603 && ! function_label_operand (operands[2], Pmode)
2606 [(set_attr "type" "binary")
2607 (set_attr "length" "4")])
2610 [(set (match_operand:DI 0 "register_operand" "=a")
2611 (plus:DI (match_operand:DI 1 "register_operand" "r")
2612 (high:DI (match_operand 2 "" ""))))]
2613 "symbolic_operand (operands[2], Pmode)
2614 && ! function_label_operand (operands[2], Pmode)
2618 [(set_attr "type" "binary")
2619 (set_attr "length" "4")])
2622 [(set (match_operand:SI 0 "register_operand" "=r")
2623 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2624 (unspec:SI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))]
2625 "symbolic_operand (operands[2], Pmode)
2626 && ! function_label_operand (operands[2], Pmode)
2629 [(set_attr "type" "binary")
2630 (set_attr "length" "4")])
2633 [(set (match_operand:DI 0 "register_operand" "=r")
2634 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2635 (unspec:DI [(match_operand 2 "" "")] UNSPEC_DLTIND14R)))]
2636 "symbolic_operand (operands[2], Pmode)
2637 && ! function_label_operand (operands[2], Pmode)
2641 [(set_attr "type" "binary")
2642 (set_attr "length" "4")])
2644 ;; Always use addil rather than ldil;add sequences. This allows the
2645 ;; HP linker to eliminate the dp relocation if the symbolic operand
2646 ;; lives in the TEXT space.
2648 [(set (match_operand:SI 0 "register_operand" "=a")
2649 (high:SI (match_operand 1 "" "")))]
2650 "symbolic_operand (operands[1], Pmode)
2651 && ! function_label_operand (operands[1], Pmode)
2652 && ! read_only_operand (operands[1], Pmode)
2656 if (TARGET_LONG_LOAD_STORE)
2657 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2659 return \"addil LR'%H1,%%r27\";
2661 [(set_attr "type" "binary")
2662 (set (attr "length")
2663 (if_then_else (not (match_test "TARGET_LONG_LOAD_STORE"))
2668 ;; This is for use in the prologue/epilogue code. We need it
2669 ;; to add large constants to a stack pointer or frame pointer.
2670 ;; Because of the additional %r1 pressure, we probably do not
2671 ;; want to use this in general code, so make it available
2672 ;; only after reload.
2674 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2675 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2676 (high:SI (match_operand 2 "const_int_operand" ""))))]
2680 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2681 [(set_attr "type" "binary,binary")
2682 (set_attr "length" "4,8")])
2685 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2686 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2687 (high:DI (match_operand 2 "const_int_operand" ""))))]
2688 "reload_completed && TARGET_64BIT"
2691 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2692 [(set_attr "type" "binary,binary")
2693 (set_attr "length" "4,8")])
2696 [(set (match_operand:SI 0 "register_operand" "=r")
2697 (high:SI (match_operand 1 "" "")))]
2698 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2699 && !pa_is_function_label_plus_const (operands[1])"
2702 if (symbolic_operand (operands[1], Pmode))
2703 return \"ldil LR'%H1,%0\";
2705 return \"ldil L'%G1,%0\";
2707 [(set_attr "type" "move")
2708 (set_attr "length" "4")])
2711 [(set (match_operand:DI 0 "register_operand" "=r")
2712 (high:DI (match_operand 1 "const_int_operand" "")))]
2715 [(set_attr "type" "move")
2716 (set_attr "length" "4")])
2719 [(set (match_operand:DI 0 "register_operand" "=r")
2720 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2721 (match_operand:DI 2 "const_int_operand" "i")))]
2724 [(set_attr "type" "move")
2725 (set_attr "length" "4")])
2728 [(set (match_operand:SI 0 "register_operand" "=r")
2729 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2730 (match_operand:SI 2 "immediate_operand" "i")))]
2731 "!pa_is_function_label_plus_const (operands[2])"
2734 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
2736 if (symbolic_operand (operands[2], Pmode))
2737 return \"ldo RR'%G2(%1),%0\";
2739 return \"ldo R'%G2(%1),%0\";
2741 [(set_attr "type" "move")
2742 (set_attr "length" "4")])
2744 ;; Now that a symbolic_address plus a constant is broken up early
2745 ;; in the compilation phase (for better CSE) we need a special
2746 ;; combiner pattern to load the symbolic address plus the constant
2747 ;; in only 2 instructions. (For cases where the symbolic address
2748 ;; was not a common subexpression.)
2750 [(set (match_operand:SI 0 "register_operand" "")
2751 (match_operand:SI 1 "symbolic_operand" ""))
2752 (clobber (match_operand:SI 2 "register_operand" ""))]
2753 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2754 [(set (match_dup 2) (high:SI (match_dup 1)))
2755 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2758 ;; hppa_legitimize_address goes to a great deal of trouble to
2759 ;; create addresses which use indexing. In some cases, this
2760 ;; is a lose because there isn't any store instructions which
2761 ;; allow indexed addresses (with integer register source).
2763 ;; These define_splits try to turn a 3 insn store into
2764 ;; a 2 insn store with some creative RTL rewriting.
2766 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2767 (match_operand:SI 1 "mem_shadd_operand" ""))
2768 (plus:SI (match_operand:SI 2 "register_operand" "")
2769 (match_operand:SI 3 "const_int_operand" ""))))
2770 (match_operand:SI 4 "register_operand" ""))
2771 (clobber (match_operand:SI 5 "register_operand" ""))]
2773 [(set (match_dup 5) (plus:SI (ashift:SI (match_dup 0) (match_dup 1))
2775 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2778 operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
2783 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2784 (match_operand:SI 1 "mem_shadd_operand" ""))
2785 (plus:SI (match_operand:SI 2 "register_operand" "")
2786 (match_operand:SI 3 "const_int_operand" ""))))
2787 (match_operand:HI 4 "register_operand" ""))
2788 (clobber (match_operand:SI 5 "register_operand" ""))]
2790 [(set (match_dup 5) (plus:SI (ashift:SI (match_dup 0) (match_dup 1))
2792 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2795 operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
2800 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2801 (match_operand:SI 1 "mem_shadd_operand" ""))
2802 (plus:SI (match_operand:SI 2 "register_operand" "")
2803 (match_operand:SI 3 "const_int_operand" ""))))
2804 (match_operand:QI 4 "register_operand" ""))
2805 (clobber (match_operand:SI 5 "register_operand" ""))]
2807 [(set (match_dup 5) (plus:SI (ashift:SI (match_dup 0) (match_dup 1))
2809 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2812 operands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
2816 (define_expand "movhi"
2817 [(set (match_operand:HI 0 "general_operand" "")
2818 (match_operand:HI 1 "general_operand" ""))]
2822 if (pa_emit_move_sequence (operands, HImode, 0))
2826 ;; Handle HImode input reloads requiring a general register as a
2827 ;; scratch register.
2828 (define_expand "reload_inhi"
2829 [(set (match_operand:HI 0 "register_operand" "=Z")
2830 (match_operand:HI 1 "non_hard_reg_operand" ""))
2831 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2835 if (pa_emit_move_sequence (operands, HImode, operands[2]))
2838 /* We don't want the clobber emitted, so handle this ourselves. */
2839 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2843 ;; Handle HImode output reloads requiring a general register as a
2844 ;; scratch register.
2845 (define_expand "reload_outhi"
2846 [(set (match_operand:HI 0 "non_hard_reg_operand" "")
2847 (match_operand:HI 1 "register_operand" "Z"))
2848 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2852 if (pa_emit_move_sequence (operands, HImode, operands[2]))
2855 /* We don't want the clobber emitted, so handle this ourselves. */
2856 emit_insn (gen_rtx_SET (operands[0], operands[1]));
2861 [(set (match_operand:HI 0 "move_dest_operand"
2862 "=r,r,r,r,r,Q,!*q,!r")
2863 (match_operand:HI 1 "move_src_operand"
2864 "r,J,N,K,RQ,rM,!rM,!*q"))]
2865 "(register_operand (operands[0], HImode)
2866 || reg_or_0_operand (operands[1], HImode))"
2871 {zdepi|depwi,z} %Z1,%0
2875 {mfctl|mfctl,w} %sar,%0"
2876 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2877 (set_attr "pa_combine_type" "addmove")
2878 (set_attr "length" "4,4,4,4,4,4,4,4")])
2881 [(set (match_operand:HI 0 "register_operand" "=r")
2882 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2883 (match_operand:SI 2 "int5_operand" "L"))))
2885 (plus:SI (match_dup 1) (match_dup 2)))]
2887 "{ldhs|ldh},mb %2(%1),%0"
2888 [(set_attr "type" "load")
2889 (set_attr "length" "4")])
2892 [(set (match_operand:HI 0 "register_operand" "=r")
2893 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2894 (match_operand:DI 2 "int5_operand" "L"))))
2896 (plus:DI (match_dup 1) (match_dup 2)))]
2899 [(set_attr "type" "load")
2900 (set_attr "length" "4")])
2902 ; And a zero extended variant.
2904 [(set (match_operand:DI 0 "register_operand" "=r")
2905 (zero_extend:DI (mem:HI
2907 (match_operand:DI 1 "register_operand" "+r")
2908 (match_operand:DI 2 "int5_operand" "L")))))
2910 (plus:DI (match_dup 1) (match_dup 2)))]
2913 [(set_attr "type" "load")
2914 (set_attr "length" "4")])
2917 [(set (match_operand:SI 0 "register_operand" "=r")
2918 (zero_extend:SI (mem:HI
2920 (match_operand:SI 1 "register_operand" "+r")
2921 (match_operand:SI 2 "int5_operand" "L")))))
2923 (plus:SI (match_dup 1) (match_dup 2)))]
2925 "{ldhs|ldh},mb %2(%1),%0"
2926 [(set_attr "type" "load")
2927 (set_attr "length" "4")])
2930 [(set (match_operand:SI 0 "register_operand" "=r")
2931 (zero_extend:SI (mem:HI
2933 (match_operand:DI 1 "register_operand" "+r")
2934 (match_operand:DI 2 "int5_operand" "L")))))
2936 (plus:DI (match_dup 1) (match_dup 2)))]
2939 [(set_attr "type" "load")
2940 (set_attr "length" "4")])
2943 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2944 (match_operand:SI 1 "int5_operand" "L")))
2945 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2947 (plus:SI (match_dup 0) (match_dup 1)))]
2949 "{sths|sth},mb %r2,%1(%0)"
2950 [(set_attr "type" "store")
2951 (set_attr "length" "4")])
2954 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2955 (match_operand:DI 1 "int5_operand" "L")))
2956 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2958 (plus:DI (match_dup 0) (match_dup 1)))]
2961 [(set_attr "type" "store")
2962 (set_attr "length" "4")])
2964 (define_insn "addhi3"
2965 [(set (match_operand:HI 0 "register_operand" "=r,r")
2966 (plus:HI (match_operand:HI 1 "register_operand" "%r,r")
2967 (match_operand:HI 2 "arith14_operand" "r,J")))]
2970 {addl|add,l} %1,%2,%0
2972 [(set_attr "type" "binary,binary")
2973 (set_attr "pa_combine_type" "addmove")
2974 (set_attr "length" "4,4")])
2976 (define_expand "movqi"
2977 [(set (match_operand:QI 0 "general_operand" "")
2978 (match_operand:QI 1 "general_operand" ""))]
2982 if (pa_emit_move_sequence (operands, QImode, 0))
2986 ;; Handle QImode input reloads requiring a general register as a
2987 ;; scratch register.
2988 (define_expand "reload_inqi"
2989 [(set (match_operand:QI 0 "register_operand" "=Z")
2990 (match_operand:QI 1 "non_hard_reg_operand" ""))
2991 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2995 if (pa_emit_move_sequence (operands, QImode, operands[2]))
2998 /* We don't want the clobber emitted, so handle this ourselves. */
2999 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3003 ;; Handle QImode output reloads requiring a general register as a
3004 ;; scratch register.
3005 (define_expand "reload_outqi"
3006 [(set (match_operand:QI 0 "non_hard_reg_operand" "")
3007 (match_operand:QI 1 "register_operand" "Z"))
3008 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
3012 if (pa_emit_move_sequence (operands, QImode, operands[2]))
3015 /* We don't want the clobber emitted, so handle this ourselves. */
3016 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3021 [(set (match_operand:QI 0 "move_dest_operand"
3022 "=r,r,r,r,r,Q,!*q,!r")
3023 (match_operand:QI 1 "move_src_operand"
3024 "r,J,N,K,RQ,rM,!rM,!*q"))]
3025 "(register_operand (operands[0], QImode)
3026 || reg_or_0_operand (operands[1], QImode))"
3031 {zdepi|depwi,z} %Z1,%0
3035 {mfctl|mfctl,w} %%sar,%0"
3036 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3037 (set_attr "pa_combine_type" "addmove")
3038 (set_attr "length" "4,4,4,4,4,4,4,4")])
3041 [(set (match_operand:QI 0 "register_operand" "=r")
3042 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3043 (match_operand:SI 2 "int5_operand" "L"))))
3044 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3046 "{ldbs|ldb},mb %2(%1),%0"
3047 [(set_attr "type" "load")
3048 (set_attr "length" "4")])
3051 [(set (match_operand:QI 0 "register_operand" "=r")
3052 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3053 (match_operand:DI 2 "int5_operand" "L"))))
3054 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3057 [(set_attr "type" "load")
3058 (set_attr "length" "4")])
3060 ; Now the same thing with zero extensions.
3062 [(set (match_operand:DI 0 "register_operand" "=r")
3063 (zero_extend:DI (mem:QI (plus:DI
3064 (match_operand:DI 1 "register_operand" "+r")
3065 (match_operand:DI 2 "int5_operand" "L")))))
3066 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3069 [(set_attr "type" "load")
3070 (set_attr "length" "4")])
3073 [(set (match_operand:SI 0 "register_operand" "=r")
3074 (zero_extend:SI (mem:QI (plus:SI
3075 (match_operand:SI 1 "register_operand" "+r")
3076 (match_operand:SI 2 "int5_operand" "L")))))
3077 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3079 "{ldbs|ldb},mb %2(%1),%0"
3080 [(set_attr "type" "load")
3081 (set_attr "length" "4")])
3084 [(set (match_operand:SI 0 "register_operand" "=r")
3085 (zero_extend:SI (mem:QI (plus:DI
3086 (match_operand:DI 1 "register_operand" "+r")
3087 (match_operand:DI 2 "int5_operand" "L")))))
3088 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3091 [(set_attr "type" "load")
3092 (set_attr "length" "4")])
3095 [(set (match_operand:HI 0 "register_operand" "=r")
3096 (zero_extend:HI (mem:QI (plus:SI
3097 (match_operand:SI 1 "register_operand" "+r")
3098 (match_operand:SI 2 "int5_operand" "L")))))
3099 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3101 "{ldbs|ldb},mb %2(%1),%0"
3102 [(set_attr "type" "load")
3103 (set_attr "length" "4")])
3106 [(set (match_operand:HI 0 "register_operand" "=r")
3107 (zero_extend:HI (mem:QI (plus:DI
3108 (match_operand:DI 1 "register_operand" "+r")
3109 (match_operand:DI 2 "int5_operand" "L")))))
3110 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3113 [(set_attr "type" "load")
3114 (set_attr "length" "4")])
3117 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3118 (match_operand:SI 1 "int5_operand" "L")))
3119 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3121 (plus:SI (match_dup 0) (match_dup 1)))]
3123 "{stbs|stb},mb %r2,%1(%0)"
3124 [(set_attr "type" "store")
3125 (set_attr "length" "4")])
3128 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3129 (match_operand:DI 1 "int5_operand" "L")))
3130 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3132 (plus:DI (match_dup 0) (match_dup 1)))]
3135 [(set_attr "type" "store")
3136 (set_attr "length" "4")])
3138 ;; The definition of this insn does not really explain what it does,
3139 ;; but it should suffice that anything generated as this insn will be
3140 ;; recognized as a movmemsi operation, and that it will not successfully
3141 ;; combine with anything.
3142 (define_expand "movmemsi"
3143 [(parallel [(set (match_operand:BLK 0 "" "")
3144 (match_operand:BLK 1 "" ""))
3145 (clobber (match_dup 4))
3146 (clobber (match_dup 5))
3147 (clobber (match_dup 6))
3148 (clobber (match_dup 7))
3149 (clobber (match_dup 8))
3150 (use (match_operand:SI 2 "arith14_operand" ""))
3151 (use (match_operand:SI 3 "const_int_operand" ""))])]
3152 "!TARGET_64BIT && optimize > 0"
3157 /* HP provides very fast block move library routine for the PA;
3158 this routine includes:
3160 4x4 byte at a time block moves,
3161 1x4 byte at a time with alignment checked at runtime with
3162 attempts to align the source and destination as needed
3165 With that in mind, here's the heuristics to try and guess when
3166 the inlined block move will be better than the library block
3169 If the size isn't constant, then always use the library routines.
3171 If the size is large in respect to the known alignment, then use
3172 the library routines.
3174 If the size is small in respect to the known alignment, then open
3175 code the copy (since that will lead to better scheduling).
3177 Else use the block move pattern. */
3179 /* Undetermined size, use the library routine. */
3180 if (GET_CODE (operands[2]) != CONST_INT)
3183 size = INTVAL (operands[2]);
3184 align = INTVAL (operands[3]);
3185 align = align > 4 ? 4 : (align ? align : 1);
3187 /* If size/alignment is large, then use the library routines. */
3188 if (size / align > 16)
3191 /* This does happen, but not often enough to worry much about. */
3192 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3195 /* Fall through means we're going to use our block move pattern. */
3197 = replace_equiv_address (operands[0],
3198 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3200 = replace_equiv_address (operands[1],
3201 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3202 operands[4] = gen_reg_rtx (SImode);
3203 operands[5] = gen_reg_rtx (SImode);
3204 operands[6] = gen_reg_rtx (SImode);
3205 operands[7] = gen_reg_rtx (SImode);
3206 operands[8] = gen_reg_rtx (SImode);
3209 ;; The operand constraints are written like this to support both compile-time
3210 ;; and run-time determined byte counts. The expander and pa_output_block_move
3211 ;; only support compile-time determined counts at this time.
3213 ;; If the count is run-time determined, the register with the byte count
3214 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3216 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3217 ;; broke this semantic for pseudo registers. We can't use match_scratch
3218 ;; as this requires two registers in the class R1_REGS when the MEMs for
3219 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3220 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3221 ;; respectively. We then split or peephole optimize after reload.
3222 (define_insn "movmemsi_prereload"
3223 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3224 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3225 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3226 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3227 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3228 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3229 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3230 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3231 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3234 [(set_attr "type" "multi,multi")])
3237 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3238 (match_operand:BLK 1 "memory_operand" ""))
3239 (clobber (match_operand:SI 2 "register_operand" ""))
3240 (clobber (match_operand:SI 3 "register_operand" ""))
3241 (clobber (match_operand:SI 6 "register_operand" ""))
3242 (clobber (match_operand:SI 7 "register_operand" ""))
3243 (clobber (match_operand:SI 8 "register_operand" ""))
3244 (use (match_operand:SI 4 "arith14_operand" ""))
3245 (use (match_operand:SI 5 "const_int_operand" ""))])]
3246 "!TARGET_64BIT && reload_completed && !flag_peephole2
3247 && GET_CODE (operands[0]) == MEM
3248 && register_operand (XEXP (operands[0], 0), SImode)
3249 && GET_CODE (operands[1]) == MEM
3250 && register_operand (XEXP (operands[1], 0), SImode)"
3251 [(set (match_dup 7) (match_dup 9))
3252 (set (match_dup 8) (match_dup 10))
3253 (parallel [(set (match_dup 0) (match_dup 1))
3254 (clobber (match_dup 2))
3255 (clobber (match_dup 3))
3256 (clobber (match_dup 6))
3257 (clobber (match_dup 7))
3258 (clobber (match_dup 8))
3264 operands[9] = XEXP (operands[0], 0);
3265 operands[10] = XEXP (operands[1], 0);
3266 operands[0] = replace_equiv_address (operands[0], operands[7]);
3267 operands[1] = replace_equiv_address (operands[1], operands[8]);
3271 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3272 (match_operand:BLK 1 "memory_operand" ""))
3273 (clobber (match_operand:SI 2 "register_operand" ""))
3274 (clobber (match_operand:SI 3 "register_operand" ""))
3275 (clobber (match_operand:SI 6 "register_operand" ""))
3276 (clobber (match_operand:SI 7 "register_operand" ""))
3277 (clobber (match_operand:SI 8 "register_operand" ""))
3278 (use (match_operand:SI 4 "arith14_operand" ""))
3279 (use (match_operand:SI 5 "const_int_operand" ""))])]
3281 && GET_CODE (operands[0]) == MEM
3282 && register_operand (XEXP (operands[0], 0), SImode)
3283 && GET_CODE (operands[1]) == MEM
3284 && register_operand (XEXP (operands[1], 0), SImode)"
3285 [(parallel [(set (match_dup 0) (match_dup 1))
3286 (clobber (match_dup 2))
3287 (clobber (match_dup 3))
3288 (clobber (match_dup 6))
3289 (clobber (match_dup 7))
3290 (clobber (match_dup 8))
3296 rtx addr = XEXP (operands[0], 0);
3297 if (dead_or_set_p (curr_insn, addr))
3301 emit_insn (gen_rtx_SET (operands[7], addr));
3302 operands[0] = replace_equiv_address (operands[0], operands[7]);
3305 addr = XEXP (operands[1], 0);
3306 if (dead_or_set_p (curr_insn, addr))
3310 emit_insn (gen_rtx_SET (operands[8], addr));
3311 operands[1] = replace_equiv_address (operands[1], operands[8]);
3315 (define_insn "movmemsi_postreload"
3316 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3317 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3318 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3319 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3320 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3321 (clobber (match_dup 0))
3322 (clobber (match_dup 1))
3323 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3324 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3326 "!TARGET_64BIT && reload_completed"
3327 "* return pa_output_block_move (operands, !which_alternative);"
3328 [(set_attr "type" "multi,multi")])
3330 (define_expand "movmemdi"
3331 [(parallel [(set (match_operand:BLK 0 "" "")
3332 (match_operand:BLK 1 "" ""))
3333 (clobber (match_dup 4))
3334 (clobber (match_dup 5))
3335 (clobber (match_dup 6))
3336 (clobber (match_dup 7))
3337 (clobber (match_dup 8))
3338 (use (match_operand:DI 2 "arith14_operand" ""))
3339 (use (match_operand:DI 3 "const_int_operand" ""))])]
3340 "TARGET_64BIT && optimize > 0"
3345 /* HP provides very fast block move library routine for the PA;
3346 this routine includes:
3348 4x4 byte at a time block moves,
3349 1x4 byte at a time with alignment checked at runtime with
3350 attempts to align the source and destination as needed
3353 With that in mind, here's the heuristics to try and guess when
3354 the inlined block move will be better than the library block
3357 If the size isn't constant, then always use the library routines.
3359 If the size is large in respect to the known alignment, then use
3360 the library routines.
3362 If the size is small in respect to the known alignment, then open
3363 code the copy (since that will lead to better scheduling).
3365 Else use the block move pattern. */
3367 /* Undetermined size, use the library routine. */
3368 if (GET_CODE (operands[2]) != CONST_INT)
3371 size = INTVAL (operands[2]);
3372 align = INTVAL (operands[3]);
3373 align = align > 8 ? 8 : (align ? align : 1);
3375 /* If size/alignment is large, then use the library routines. */
3376 if (size / align > 16)
3379 /* This does happen, but not often enough to worry much about. */
3380 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3383 /* Fall through means we're going to use our block move pattern. */
3385 = replace_equiv_address (operands[0],
3386 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3388 = replace_equiv_address (operands[1],
3389 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3390 operands[4] = gen_reg_rtx (DImode);
3391 operands[5] = gen_reg_rtx (DImode);
3392 operands[6] = gen_reg_rtx (DImode);
3393 operands[7] = gen_reg_rtx (DImode);
3394 operands[8] = gen_reg_rtx (DImode);
3397 ;; The operand constraints are written like this to support both compile-time
3398 ;; and run-time determined byte counts. The expander and pa_output_block_move
3399 ;; only support compile-time determined counts at this time.
3401 ;; If the count is run-time determined, the register with the byte count
3402 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3404 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3405 ;; broke this semantic for pseudo registers. We can't use match_scratch
3406 ;; as this requires two registers in the class R1_REGS when the MEMs for
3407 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3408 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3409 ;; respectively. We then split or peephole optimize after reload.
3410 (define_insn "movmemdi_prereload"
3411 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3412 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3413 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3414 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3415 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3416 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3417 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3418 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3419 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3422 [(set_attr "type" "multi,multi")])
3425 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3426 (match_operand:BLK 1 "memory_operand" ""))
3427 (clobber (match_operand:DI 2 "register_operand" ""))
3428 (clobber (match_operand:DI 3 "register_operand" ""))
3429 (clobber (match_operand:DI 6 "register_operand" ""))
3430 (clobber (match_operand:DI 7 "register_operand" ""))
3431 (clobber (match_operand:DI 8 "register_operand" ""))
3432 (use (match_operand:DI 4 "arith14_operand" ""))
3433 (use (match_operand:DI 5 "const_int_operand" ""))])]
3434 "TARGET_64BIT && reload_completed && !flag_peephole2
3435 && GET_CODE (operands[0]) == MEM
3436 && register_operand (XEXP (operands[0], 0), DImode)
3437 && GET_CODE (operands[1]) == MEM
3438 && register_operand (XEXP (operands[1], 0), DImode)"
3439 [(set (match_dup 7) (match_dup 9))
3440 (set (match_dup 8) (match_dup 10))
3441 (parallel [(set (match_dup 0) (match_dup 1))
3442 (clobber (match_dup 2))
3443 (clobber (match_dup 3))
3444 (clobber (match_dup 6))
3445 (clobber (match_dup 7))
3446 (clobber (match_dup 8))
3452 operands[9] = XEXP (operands[0], 0);
3453 operands[10] = XEXP (operands[1], 0);
3454 operands[0] = replace_equiv_address (operands[0], operands[7]);
3455 operands[1] = replace_equiv_address (operands[1], operands[8]);
3459 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3460 (match_operand:BLK 1 "memory_operand" ""))
3461 (clobber (match_operand:DI 2 "register_operand" ""))
3462 (clobber (match_operand:DI 3 "register_operand" ""))
3463 (clobber (match_operand:DI 6 "register_operand" ""))
3464 (clobber (match_operand:DI 7 "register_operand" ""))
3465 (clobber (match_operand:DI 8 "register_operand" ""))
3466 (use (match_operand:DI 4 "arith14_operand" ""))
3467 (use (match_operand:DI 5 "const_int_operand" ""))])]
3469 && GET_CODE (operands[0]) == MEM
3470 && register_operand (XEXP (operands[0], 0), DImode)
3471 && GET_CODE (operands[1]) == MEM
3472 && register_operand (XEXP (operands[1], 0), DImode)"
3473 [(parallel [(set (match_dup 0) (match_dup 1))
3474 (clobber (match_dup 2))
3475 (clobber (match_dup 3))
3476 (clobber (match_dup 6))
3477 (clobber (match_dup 7))
3478 (clobber (match_dup 8))
3484 rtx addr = XEXP (operands[0], 0);
3485 if (dead_or_set_p (curr_insn, addr))
3489 emit_insn (gen_rtx_SET (operands[7], addr));
3490 operands[0] = replace_equiv_address (operands[0], operands[7]);
3493 addr = XEXP (operands[1], 0);
3494 if (dead_or_set_p (curr_insn, addr))
3498 emit_insn (gen_rtx_SET (operands[8], addr));
3499 operands[1] = replace_equiv_address (operands[1], operands[8]);
3503 (define_insn "movmemdi_postreload"
3504 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3505 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3506 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3507 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3508 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3509 (clobber (match_dup 0))
3510 (clobber (match_dup 1))
3511 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3512 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3514 "TARGET_64BIT && reload_completed"
3515 "* return pa_output_block_move (operands, !which_alternative);"
3516 [(set_attr "type" "multi,multi")])
3518 (define_expand "setmemsi"
3519 [(parallel [(set (match_operand:BLK 0 "" "")
3520 (match_operand 2 "const_int_operand" ""))
3521 (clobber (match_dup 4))
3522 (clobber (match_dup 5))
3523 (use (match_operand:SI 1 "arith14_operand" ""))
3524 (use (match_operand:SI 3 "const_int_operand" ""))])]
3525 "!TARGET_64BIT && optimize > 0"
3530 /* If value to set is not zero, use the library routine. */
3531 if (operands[2] != const0_rtx)
3534 /* Undetermined size, use the library routine. */
3535 if (GET_CODE (operands[1]) != CONST_INT)
3538 size = INTVAL (operands[1]);
3539 align = INTVAL (operands[3]);
3540 align = align > 4 ? 4 : align;
3542 /* If size/alignment is large, then use the library routines. */
3543 if (size / align > 16)
3546 /* This does happen, but not often enough to worry much about. */
3547 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3550 /* Fall through means we're going to use our block clear pattern. */
3552 = replace_equiv_address (operands[0],
3553 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3554 operands[4] = gen_reg_rtx (SImode);
3555 operands[5] = gen_reg_rtx (SImode);
3558 (define_insn "clrmemsi_prereload"
3559 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3561 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3562 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3563 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3564 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3567 [(set_attr "type" "multi,multi")])
3570 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3572 (clobber (match_operand:SI 1 "register_operand" ""))
3573 (clobber (match_operand:SI 4 "register_operand" ""))
3574 (use (match_operand:SI 2 "arith14_operand" ""))
3575 (use (match_operand:SI 3 "const_int_operand" ""))])]
3576 "!TARGET_64BIT && reload_completed && !flag_peephole2
3577 && GET_CODE (operands[0]) == MEM
3578 && register_operand (XEXP (operands[0], 0), SImode)"
3579 [(set (match_dup 4) (match_dup 5))
3580 (parallel [(set (match_dup 0) (const_int 0))
3581 (clobber (match_dup 1))
3582 (clobber (match_dup 4))
3588 operands[5] = XEXP (operands[0], 0);
3589 operands[0] = replace_equiv_address (operands[0], operands[4]);
3593 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3595 (clobber (match_operand:SI 1 "register_operand" ""))
3596 (clobber (match_operand:SI 4 "register_operand" ""))
3597 (use (match_operand:SI 2 "arith14_operand" ""))
3598 (use (match_operand:SI 3 "const_int_operand" ""))])]
3600 && GET_CODE (operands[0]) == MEM
3601 && register_operand (XEXP (operands[0], 0), SImode)"
3602 [(parallel [(set (match_dup 0) (const_int 0))
3603 (clobber (match_dup 1))
3604 (clobber (match_dup 4))
3610 rtx addr = XEXP (operands[0], 0);
3611 if (dead_or_set_p (curr_insn, addr))
3615 emit_insn (gen_rtx_SET (operands[4], addr));
3616 operands[0] = replace_equiv_address (operands[0], operands[4]);
3620 (define_insn "clrmemsi_postreload"
3621 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3623 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3624 (clobber (match_dup 0))
3625 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3626 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3628 "!TARGET_64BIT && reload_completed"
3629 "* return pa_output_block_clear (operands, !which_alternative);"
3630 [(set_attr "type" "multi,multi")])
3632 (define_expand "setmemdi"
3633 [(parallel [(set (match_operand:BLK 0 "" "")
3634 (match_operand 2 "const_int_operand" ""))
3635 (clobber (match_dup 4))
3636 (clobber (match_dup 5))
3637 (use (match_operand:DI 1 "arith14_operand" ""))
3638 (use (match_operand:DI 3 "const_int_operand" ""))])]
3639 "TARGET_64BIT && optimize > 0"
3644 /* If value to set is not zero, use the library routine. */
3645 if (operands[2] != const0_rtx)
3648 /* Undetermined size, use the library routine. */
3649 if (GET_CODE (operands[1]) != CONST_INT)
3652 size = INTVAL (operands[1]);
3653 align = INTVAL (operands[3]);
3654 align = align > 8 ? 8 : align;
3656 /* If size/alignment is large, then use the library routines. */
3657 if (size / align > 16)
3660 /* This does happen, but not often enough to worry much about. */
3661 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3664 /* Fall through means we're going to use our block clear pattern. */
3666 = replace_equiv_address (operands[0],
3667 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3668 operands[4] = gen_reg_rtx (DImode);
3669 operands[5] = gen_reg_rtx (DImode);
3672 (define_insn "clrmemdi_prereload"
3673 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3675 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3676 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3677 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3678 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3681 [(set_attr "type" "multi,multi")])
3684 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3686 (clobber (match_operand:DI 1 "register_operand" ""))
3687 (clobber (match_operand:DI 4 "register_operand" ""))
3688 (use (match_operand:DI 2 "arith14_operand" ""))
3689 (use (match_operand:DI 3 "const_int_operand" ""))])]
3690 "TARGET_64BIT && reload_completed && !flag_peephole2
3691 && GET_CODE (operands[0]) == MEM
3692 && register_operand (XEXP (operands[0], 0), DImode)"
3693 [(set (match_dup 4) (match_dup 5))
3694 (parallel [(set (match_dup 0) (const_int 0))
3695 (clobber (match_dup 1))
3696 (clobber (match_dup 4))
3702 operands[5] = XEXP (operands[0], 0);
3703 operands[0] = replace_equiv_address (operands[0], operands[4]);
3707 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3709 (clobber (match_operand:DI 1 "register_operand" ""))
3710 (clobber (match_operand:DI 4 "register_operand" ""))
3711 (use (match_operand:DI 2 "arith14_operand" ""))
3712 (use (match_operand:DI 3 "const_int_operand" ""))])]
3714 && GET_CODE (operands[0]) == MEM
3715 && register_operand (XEXP (operands[0], 0), DImode)"
3716 [(parallel [(set (match_dup 0) (const_int 0))
3717 (clobber (match_dup 1))
3718 (clobber (match_dup 4))
3724 rtx addr = XEXP (operands[0], 0);
3725 if (dead_or_set_p (curr_insn, addr))
3729 emit_insn (gen_rtx_SET (operands[4], addr));
3730 operands[0] = replace_equiv_address (operands[0], operands[4]);
3734 (define_insn "clrmemdi_postreload"
3735 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3737 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3738 (clobber (match_dup 0))
3739 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3740 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3742 "TARGET_64BIT && reload_completed"
3743 "* return pa_output_block_clear (operands, !which_alternative);"
3744 [(set_attr "type" "multi,multi")])
3746 ;; Floating point move insns
3748 (define_expand "movdf"
3749 [(set (match_operand:DF 0 "general_operand" "")
3750 (match_operand:DF 1 "general_operand" ""))]
3754 if (pa_emit_move_sequence (operands, DFmode, 0))
3758 ;; Handle DFmode input reloads requiring %r1 as a scratch register.
3759 (define_expand "reload_indf_r1"
3760 [(set (match_operand:DF 0 "register_operand" "=Z")
3761 (match_operand:DF 1 "non_hard_reg_operand" ""))
3762 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
3766 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3769 /* We don't want the clobber emitted, so handle this ourselves. */
3770 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3774 ;; Handle DFmode input reloads requiring a general register as a
3775 ;; scratch register.
3776 (define_expand "reload_indf"
3777 [(set (match_operand:DF 0 "register_operand" "=Z")
3778 (match_operand:DF 1 "non_hard_reg_operand" ""))
3779 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3783 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3786 /* We don't want the clobber emitted, so handle this ourselves. */
3787 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3791 ;; Handle DFmode output reloads requiring a general register as a
3792 ;; scratch register.
3793 (define_expand "reload_outdf"
3794 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3795 (match_operand:DF 1 "register_operand" "Z"))
3796 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3800 if (pa_emit_move_sequence (operands, DFmode, operands[2]))
3803 /* We don't want the clobber emitted, so handle this ourselves. */
3804 emit_insn (gen_rtx_SET (operands[0], operands[1]));
3809 [(set (match_operand:DF 0 "move_dest_operand"
3810 "=f,*r,T,?o,?Q,f,*r,*r,?*r,?f")
3811 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3812 "fG,*rG,f,*r,*r,RT,o,RQ,f,*r"))]
3813 "(register_operand (operands[0], DFmode)
3814 || reg_or_0_operand (operands[1], DFmode))
3815 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3816 && GET_CODE (operands[0]) == MEM)
3818 && !TARGET_SOFT_FLOAT"
3821 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3822 || operands[1] == CONST0_RTX (DFmode))
3823 && !(REG_P (operands[0]) && REG_P (operands[1])
3824 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
3825 return pa_output_fp_move_double (operands);
3826 return pa_output_move_double (operands);
3828 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
3829 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
3832 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3833 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3835 && !TARGET_DISABLE_INDEXING
3836 && reload_completed"
3838 [(set_attr "type" "fpstore")
3839 (set_attr "pa_combine_type" "addmove")
3840 (set_attr "length" "4")])
3843 [(set (match_operand:SI 0 "register_operand" "")
3844 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3846 (match_operand:SI 2 "register_operand" "")))
3847 (set (mem:DF (match_dup 0))
3848 (match_operand:DF 3 "register_operand" ""))]
3850 && !TARGET_DISABLE_INDEXING
3851 && REG_OK_FOR_BASE_P (operands[2])
3852 && FP_REGNO_P (REGNO (operands[3]))"
3853 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3855 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 3))
3860 [(set (match_operand:SI 0 "register_operand" "")
3861 (plus:SI (match_operand:SI 2 "register_operand" "")
3862 (ashift:SI (match_operand:SI 1 "register_operand" "")
3864 (set (mem:DF (match_dup 0))
3865 (match_operand:DF 3 "register_operand" ""))]
3867 && !TARGET_DISABLE_INDEXING
3868 && REG_OK_FOR_BASE_P (operands[2])
3869 && FP_REGNO_P (REGNO (operands[3]))"
3870 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3872 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 3))
3877 [(set (match_operand:DI 0 "register_operand" "")
3878 (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
3880 (match_operand:DI 2 "register_operand" "")))
3881 (set (mem:DF (match_dup 0))
3882 (match_operand:DF 3 "register_operand" ""))]
3884 && !TARGET_DISABLE_INDEXING
3886 && REG_OK_FOR_BASE_P (operands[2])
3887 && FP_REGNO_P (REGNO (operands[3]))"
3888 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3890 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
3895 [(set (match_operand:DI 0 "register_operand" "")
3896 (plus:DI (match_operand:DI 2 "register_operand" "")
3897 (ashift:DI (match_operand:DI 1 "register_operand" "")
3899 (set (mem:DF (match_dup 0))
3900 (match_operand:DF 3 "register_operand" ""))]
3902 && !TARGET_DISABLE_INDEXING
3904 && REG_OK_FOR_BASE_P (operands[2])
3905 && FP_REGNO_P (REGNO (operands[3]))"
3906 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3908 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
3913 [(set (match_operand:SI 0 "register_operand" "")
3914 (plus:SI (match_operand:SI 1 "register_operand" "")
3915 (match_operand:SI 2 "register_operand" "")))
3916 (set (mem:DF (match_dup 0))
3917 (match_operand:DF 3 "register_operand" ""))]
3919 && !TARGET_DISABLE_INDEXING
3920 && TARGET_NO_SPACE_REGS
3921 && REG_OK_FOR_INDEX_P (operands[1])
3922 && REG_OK_FOR_BASE_P (operands[2])
3923 && FP_REGNO_P (REGNO (operands[3]))"
3924 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3926 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3930 [(set (match_operand:SI 0 "register_operand" "")
3931 (plus:SI (match_operand:SI 1 "register_operand" "")
3932 (match_operand:SI 2 "register_operand" "")))
3933 (set (mem:DF (match_dup 0))
3934 (match_operand:DF 3 "register_operand" ""))]
3936 && !TARGET_DISABLE_INDEXING
3937 && TARGET_NO_SPACE_REGS
3938 && REG_OK_FOR_BASE_P (operands[1])
3939 && REG_OK_FOR_INDEX_P (operands[2])
3940 && FP_REGNO_P (REGNO (operands[3]))"
3941 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3943 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3947 [(set (match_operand:DI 0 "register_operand" "")
3948 (plus:DI (match_operand:DI 1 "register_operand" "")
3949 (match_operand:DI 2 "register_operand" "")))
3950 (set (mem:DF (match_dup 0))
3951 (match_operand:DF 3 "register_operand" ""))]
3953 && !TARGET_DISABLE_INDEXING
3955 && TARGET_NO_SPACE_REGS
3956 && REG_OK_FOR_INDEX_P (operands[1])
3957 && REG_OK_FOR_BASE_P (operands[2])
3958 && FP_REGNO_P (REGNO (operands[3]))"
3959 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3961 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3965 [(set (match_operand:DI 0 "register_operand" "")
3966 (plus:DI (match_operand:DI 1 "register_operand" "")
3967 (match_operand:DI 2 "register_operand" "")))
3968 (set (mem:DF (match_dup 0))
3969 (match_operand:DF 3 "register_operand" ""))]
3971 && !TARGET_DISABLE_INDEXING
3973 && TARGET_NO_SPACE_REGS
3974 && REG_OK_FOR_BASE_P (operands[1])
3975 && REG_OK_FOR_INDEX_P (operands[2])
3976 && FP_REGNO_P (REGNO (operands[3]))"
3977 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3979 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3983 [(set (match_operand:DF 0 "move_dest_operand"
3985 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3987 "(register_operand (operands[0], DFmode)
3988 || reg_or_0_operand (operands[1], DFmode))
3990 && TARGET_SOFT_FLOAT"
3993 return pa_output_move_double (operands);
3995 [(set_attr "type" "move,store,store,load,load")
3996 (set_attr "length" "8,8,16,8,16")])
3999 [(set (match_operand:DF 0 "move_dest_operand"
4000 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4001 (match_operand:DF 1 "move_src_operand"
4002 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
4003 "(register_operand (operands[0], DFmode)
4004 || reg_or_0_operand (operands[1], DFmode))
4005 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4016 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4017 (set_attr "pa_combine_type" "addmove")
4018 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4021 (define_expand "movdi"
4022 [(set (match_operand:DI 0 "general_operand" "")
4023 (match_operand:DI 1 "general_operand" ""))]
4027 if (pa_emit_move_sequence (operands, DImode, 0))
4031 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4032 (define_expand "reload_indi_r1"
4033 [(set (match_operand:DI 0 "register_operand" "=Z")
4034 (match_operand:DI 1 "non_hard_reg_operand" ""))
4035 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4039 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4042 /* We don't want the clobber emitted, so handle this ourselves. */
4043 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4047 ;; Handle DImode input reloads requiring a general register as a
4048 ;; scratch register.
4049 (define_expand "reload_indi"
4050 [(set (match_operand:DI 0 "register_operand" "=Z")
4051 (match_operand:DI 1 "non_hard_reg_operand" ""))
4052 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4056 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4059 /* We don't want the clobber emitted, so handle this ourselves. */
4060 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4064 ;; Handle DImode output reloads requiring a general register as a
4065 ;; scratch register.
4066 (define_expand "reload_outdi"
4067 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4068 (match_operand:DI 1 "register_operand" "Z"))
4069 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4073 if (pa_emit_move_sequence (operands, DImode, operands[2]))
4076 /* We don't want the clobber emitted, so handle this ourselves. */
4077 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4082 [(set (match_operand:DI 0 "register_operand" "=r")
4083 (high:DI (match_operand 1 "" "")))]
4087 rtx op0 = operands[0];
4088 rtx op1 = operands[1];
4090 switch (GET_CODE (op1))
4093 #if HOST_BITS_PER_WIDE_INT <= 32
4094 operands[0] = operand_subword (op0, 1, 0, DImode);
4095 output_asm_insn (\"ldil L'%1,%0\", operands);
4097 operands[0] = operand_subword (op0, 0, 0, DImode);
4098 if (INTVAL (op1) < 0)
4099 output_asm_insn (\"ldi -1,%0\", operands);
4101 output_asm_insn (\"ldi 0,%0\", operands);
4103 operands[0] = operand_subword (op0, 1, 0, DImode);
4104 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4105 output_asm_insn (\"ldil L'%1,%0\", operands);
4107 operands[0] = operand_subword (op0, 0, 0, DImode);
4108 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4109 output_asm_insn (pa_singlemove_string (operands), operands);
4114 operands[0] = operand_subword (op0, 1, 0, DImode);
4115 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4116 output_asm_insn (\"ldil L'%1,%0\", operands);
4118 operands[0] = operand_subword (op0, 0, 0, DImode);
4119 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4120 output_asm_insn (pa_singlemove_string (operands), operands);
4128 [(set_attr "type" "move")
4129 (set_attr "length" "12")])
4132 [(set (match_operand:DI 0 "move_dest_operand"
4133 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4134 (match_operand:DI 1 "move_src_operand"
4135 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4136 "(register_operand (operands[0], DImode)
4137 || reg_or_0_operand (operands[1], DImode))
4139 && !TARGET_SOFT_FLOAT"
4142 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4143 || operands[1] == CONST0_RTX (DFmode))
4144 && !(REG_P (operands[0]) && REG_P (operands[1])
4145 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4146 return pa_output_fp_move_double (operands);
4147 return pa_output_move_double (operands);
4150 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4151 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4154 [(set (match_operand:DI 0 "move_dest_operand"
4155 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4156 (match_operand:DI 1 "move_src_operand"
4157 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4158 "(register_operand (operands[0], DImode)
4159 || reg_or_0_operand (operands[1], DImode))
4160 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4170 {mfctl|mfctl,w} %%sar,%0
4174 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4175 (set_attr "pa_combine_type" "addmove")
4176 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4179 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4180 (match_operand:DI 1 "register_operand" "f"))]
4183 && !TARGET_DISABLE_INDEXING
4184 && reload_completed"
4186 [(set_attr "type" "fpstore")
4187 (set_attr "pa_combine_type" "addmove")
4188 (set_attr "length" "4")])
4191 [(set (match_operand:DI 0 "register_operand" "")
4192 (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
4194 (match_operand:DI 2 "register_operand" "")))
4195 (set (mem:DI (match_dup 0))
4196 (match_operand:DI 3 "register_operand" ""))]
4198 && !TARGET_DISABLE_INDEXING
4200 && REG_OK_FOR_BASE_P (operands[2])
4201 && FP_REGNO_P (REGNO (operands[3]))"
4202 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4204 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 3))
4209 [(set (match_operand:DI 0 "register_operand" "")
4210 (plus:DI (match_operand:DI 1 "register_operand" "")
4211 (match_operand:DI 2 "register_operand" "")))
4212 (set (mem:DI (match_dup 0))
4213 (match_operand:DI 3 "register_operand" ""))]
4215 && !TARGET_DISABLE_INDEXING
4217 && TARGET_NO_SPACE_REGS
4218 && REG_OK_FOR_INDEX_P (operands[1])
4219 && REG_OK_FOR_BASE_P (operands[2])
4220 && FP_REGNO_P (REGNO (operands[3]))"
4221 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4223 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4227 [(set (match_operand:DI 0 "register_operand" "")
4228 (plus:DI (match_operand:DI 1 "register_operand" "")
4229 (match_operand:DI 2 "register_operand" "")))
4230 (set (mem:DI (match_dup 0))
4231 (match_operand:DI 3 "register_operand" ""))]
4233 && !TARGET_DISABLE_INDEXING
4235 && TARGET_NO_SPACE_REGS
4236 && REG_OK_FOR_BASE_P (operands[1])
4237 && REG_OK_FOR_INDEX_P (operands[2])
4238 && FP_REGNO_P (REGNO (operands[3]))"
4239 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4241 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4245 [(set (match_operand:DI 0 "move_dest_operand"
4247 (match_operand:DI 1 "general_operand"
4249 "(register_operand (operands[0], DImode)
4250 || reg_or_0_operand (operands[1], DImode))
4252 && TARGET_SOFT_FLOAT"
4255 return pa_output_move_double (operands);
4257 [(set_attr "type" "move,store,store,load,load,multi")
4258 (set_attr "length" "8,8,16,8,16,16")])
4261 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4262 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4263 (match_operand:DI 2 "immediate_operand" "i,i")))]
4267 /* Don't output a 64-bit constant, since we can't trust the assembler to
4268 handle it correctly. */
4269 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4270 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4271 else if (HOST_BITS_PER_WIDE_INT > 32
4272 && GET_CODE (operands[2]) == CONST_INT)
4273 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4274 if (which_alternative == 1)
4275 output_asm_insn (\"copy %1,%0\", operands);
4276 return \"ldo R'%G2(%R1),%R0\";
4278 [(set_attr "type" "move,move")
4279 (set_attr "length" "4,8")])
4281 (define_expand "movsf"
4282 [(set (match_operand:SF 0 "general_operand" "")
4283 (match_operand:SF 1 "general_operand" ""))]
4287 if (pa_emit_move_sequence (operands, SFmode, 0))
4291 ;; Handle SFmode input reloads requiring %r1 as a scratch register.
4292 (define_expand "reload_insf_r1"
4293 [(set (match_operand:SF 0 "register_operand" "=Z")
4294 (match_operand:SF 1 "non_hard_reg_operand" ""))
4295 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4299 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4302 /* We don't want the clobber emitted, so handle this ourselves. */
4303 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4307 ;; Handle SFmode input reloads requiring a general register as a
4308 ;; scratch register.
4309 (define_expand "reload_insf"
4310 [(set (match_operand:SF 0 "register_operand" "=Z")
4311 (match_operand:SF 1 "non_hard_reg_operand" ""))
4312 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4316 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4319 /* We don't want the clobber emitted, so handle this ourselves. */
4320 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4324 ;; Handle SFmode output reloads requiring a general register as a
4325 ;; scratch register.
4326 (define_expand "reload_outsf"
4327 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4328 (match_operand:SF 1 "register_operand" "Z"))
4329 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4333 if (pa_emit_move_sequence (operands, SFmode, operands[2]))
4336 /* We don't want the clobber emitted, so handle this ourselves. */
4337 emit_insn (gen_rtx_SET (operands[0], operands[1]));
4342 [(set (match_operand:SF 0 "move_dest_operand"
4343 "=f,!*r,f,*r,T,Q,?*r,?f")
4344 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4345 "fG,!*rG,RT,RQ,f,*rG,f,*r"))]
4346 "(register_operand (operands[0], SFmode)
4347 || reg_or_0_operand (operands[1], SFmode))
4348 && !TARGET_SOFT_FLOAT
4357 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4358 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4359 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4360 (set_attr "pa_combine_type" "addmove")
4361 (set_attr "length" "4,4,4,4,4,4,8,8")])
4364 [(set (match_operand:SF 0 "move_dest_operand"
4366 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4367 "fG,!*rG,RT,RQ,f,*rG"))]
4368 "(register_operand (operands[0], SFmode)
4369 || reg_or_0_operand (operands[1], SFmode))
4370 && !TARGET_SOFT_FLOAT
4379 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4380 (set_attr "pa_combine_type" "addmove")
4381 (set_attr "length" "4,4,4,4,4,4")])
4384 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4385 (match_operand:SF 1 "register_operand" "f"))]
4387 && !TARGET_DISABLE_INDEXING
4388 && reload_completed"
4390 [(set_attr "type" "fpstore")
4391 (set_attr "pa_combine_type" "addmove")
4392 (set_attr "length" "4")])
4395 [(set (match_operand:SI 0 "register_operand" "")
4396 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4398 (match_operand:SI 2 "register_operand" "")))
4399 (set (mem:SF (match_dup 0))
4400 (match_operand:SF 3 "register_operand" ""))]
4402 && !TARGET_DISABLE_INDEXING
4403 && REG_OK_FOR_BASE_P (operands[2])
4404 && FP_REGNO_P (REGNO (operands[3]))"
4405 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4407 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 1) (const_int 2))
4412 [(set (match_operand:DI 0 "register_operand" "")
4413 (plus:DI (ashift:DI (match_operand:DI 1 "register_operand" "")
4415 (match_operand:DI 2 "register_operand" "")))
4416 (set (mem:SF (match_dup 0))
4417 (match_operand:SF 3 "register_operand" ""))]
4419 && !TARGET_DISABLE_INDEXING
4421 && REG_OK_FOR_BASE_P (operands[2])
4422 && FP_REGNO_P (REGNO (operands[3]))"
4423 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4425 (set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (const_int 2))
4430 [(set (match_operand:SI 0 "register_operand" "")
4431 (plus:SI (match_operand:SI 1 "register_operand" "")
4432 (match_operand:SI 2 "register_operand" "")))
4433 (set (mem:SF (match_dup 0))
4434 (match_operand:SF 3 "register_operand" ""))]
4436 && !TARGET_DISABLE_INDEXING
4437 && TARGET_NO_SPACE_REGS
4438 && REG_OK_FOR_INDEX_P (operands[1])
4439 && REG_OK_FOR_BASE_P (operands[2])
4440 && FP_REGNO_P (REGNO (operands[3]))"
4441 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4443 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4447 [(set (match_operand:SI 0 "register_operand" "")
4448 (plus:SI (match_operand:SI 1 "register_operand" "")
4449 (match_operand:SI 2 "register_operand" "")))
4450 (set (mem:SF (match_dup 0))
4451 (match_operand:SF 3 "register_operand" ""))]
4453 && !TARGET_DISABLE_INDEXING
4454 && TARGET_NO_SPACE_REGS
4455 && REG_OK_FOR_BASE_P (operands[1])
4456 && REG_OK_FOR_INDEX_P (operands[2])
4457 && FP_REGNO_P (REGNO (operands[3]))"
4458 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4460 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4464 [(set (match_operand:DI 0 "register_operand" "")
4465 (plus:DI (match_operand:DI 1 "register_operand" "")
4466 (match_operand:DI 2 "register_operand" "")))
4467 (set (mem:SF (match_dup 0))
4468 (match_operand:SF 3 "register_operand" ""))]
4470 && !TARGET_DISABLE_INDEXING
4472 && TARGET_NO_SPACE_REGS
4473 && REG_OK_FOR_INDEX_P (operands[1])
4474 && REG_OK_FOR_BASE_P (operands[2])
4475 && FP_REGNO_P (REGNO (operands[3]))"
4476 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4478 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4482 [(set (match_operand:DI 0 "register_operand" "")
4483 (plus:DI (match_operand:DI 1 "register_operand" "")
4484 (match_operand:DI 2 "register_operand" "")))
4485 (set (mem:SF (match_dup 0))
4486 (match_operand:SF 3 "register_operand" ""))]
4488 && !TARGET_DISABLE_INDEXING
4490 && TARGET_NO_SPACE_REGS
4491 && REG_OK_FOR_BASE_P (operands[1])
4492 && REG_OK_FOR_INDEX_P (operands[2])
4493 && FP_REGNO_P (REGNO (operands[3]))"
4494 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4496 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4500 [(set (match_operand:SF 0 "move_dest_operand"
4502 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4504 "(register_operand (operands[0], SFmode)
4505 || reg_or_0_operand (operands[1], SFmode))
4506 && TARGET_SOFT_FLOAT"
4511 [(set_attr "type" "move,load,store")
4512 (set_attr "pa_combine_type" "addmove")
4513 (set_attr "length" "4,4,4")])
4517 ;;- zero extension instructions
4518 ;; We have define_expand for zero extension patterns to make sure the
4519 ;; operands get loaded into registers. The define_insns accept
4520 ;; memory operands. This gives us better overall code than just
4521 ;; having a pattern that does or does not accept memory operands.
4523 (define_expand "zero_extendqihi2"
4524 [(set (match_operand:HI 0 "register_operand" "")
4526 (match_operand:QI 1 "register_operand" "")))]
4531 [(set (match_operand:HI 0 "register_operand" "=r,r")
4533 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4534 "GET_CODE (operands[1]) != CONST_INT"
4536 {extru|extrw,u} %1,31,8,%0
4538 [(set_attr "type" "shift,load")
4539 (set_attr "length" "4,4")])
4541 (define_expand "zero_extendqisi2"
4542 [(set (match_operand:SI 0 "register_operand" "")
4544 (match_operand:QI 1 "register_operand" "")))]
4549 [(set (match_operand:SI 0 "register_operand" "=r,r")
4551 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4552 "GET_CODE (operands[1]) != CONST_INT"
4554 {extru|extrw,u} %1,31,8,%0
4556 [(set_attr "type" "shift,load")
4557 (set_attr "length" "4,4")])
4559 (define_expand "zero_extendhisi2"
4560 [(set (match_operand:SI 0 "register_operand" "")
4562 (match_operand:HI 1 "register_operand" "")))]
4567 [(set (match_operand:SI 0 "register_operand" "=r,r")
4569 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4570 "GET_CODE (operands[1]) != CONST_INT"
4572 {extru|extrw,u} %1,31,16,%0
4574 [(set_attr "type" "shift,load")
4575 (set_attr "length" "4,4")])
4577 (define_expand "zero_extendqidi2"
4578 [(set (match_operand:DI 0 "register_operand" "")
4580 (match_operand:QI 1 "register_operand" "")))]
4585 [(set (match_operand:DI 0 "register_operand" "=r,r")
4587 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4588 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4592 [(set_attr "type" "shift,load")
4593 (set_attr "length" "4,4")])
4595 (define_expand "zero_extendhidi2"
4596 [(set (match_operand:DI 0 "register_operand" "")
4598 (match_operand:HI 1 "register_operand" "")))]
4603 [(set (match_operand:DI 0 "register_operand" "=r,r")
4605 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4606 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4610 [(set_attr "type" "shift,load")
4611 (set_attr "length" "4,4")])
4613 (define_expand "zero_extendsidi2"
4614 [(set (match_operand:DI 0 "register_operand" "")
4616 (match_operand:SI 1 "register_operand" "")))]
4621 [(set (match_operand:DI 0 "register_operand" "=r,r")
4623 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4624 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4628 [(set_attr "type" "shift,load")
4629 (set_attr "length" "4,4")])
4631 ;;- sign extension instructions
4633 (define_insn "extendhisi2"
4634 [(set (match_operand:SI 0 "register_operand" "=r")
4635 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4637 "{extrs|extrw,s} %1,31,16,%0"
4638 [(set_attr "type" "shift")
4639 (set_attr "length" "4")])
4641 (define_insn "extendqihi2"
4642 [(set (match_operand:HI 0 "register_operand" "=r")
4643 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4645 "{extrs|extrw,s} %1,31,8,%0"
4646 [(set_attr "type" "shift")
4647 (set_attr "length" "4")])
4649 (define_insn "extendqisi2"
4650 [(set (match_operand:SI 0 "register_operand" "=r")
4651 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4653 "{extrs|extrw,s} %1,31,8,%0"
4654 [(set_attr "type" "shift")
4655 (set_attr "length" "4")])
4657 (define_insn "extendqidi2"
4658 [(set (match_operand:DI 0 "register_operand" "=r")
4659 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4661 "extrd,s %1,63,8,%0"
4662 [(set_attr "type" "shift")
4663 (set_attr "length" "4")])
4665 (define_insn "extendhidi2"
4666 [(set (match_operand:DI 0 "register_operand" "=r")
4667 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4669 "extrd,s %1,63,16,%0"
4670 [(set_attr "type" "shift")
4671 (set_attr "length" "4")])
4673 (define_insn "extendsidi2"
4674 [(set (match_operand:DI 0 "register_operand" "=r")
4675 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4677 "extrd,s %1,63,32,%0"
4678 [(set_attr "type" "shift")
4679 (set_attr "length" "4")])
4682 ;; Conversions between float and double.
4684 (define_insn "extendsfdf2"
4685 [(set (match_operand:DF 0 "register_operand" "=f")
4687 (match_operand:SF 1 "register_operand" "f")))]
4688 "! TARGET_SOFT_FLOAT"
4689 "{fcnvff|fcnv},sgl,dbl %1,%0"
4690 [(set_attr "type" "fpalu")
4691 (set_attr "length" "4")])
4693 (define_insn "truncdfsf2"
4694 [(set (match_operand:SF 0 "register_operand" "=f")
4696 (match_operand:DF 1 "register_operand" "f")))]
4697 "! TARGET_SOFT_FLOAT"
4698 "{fcnvff|fcnv},dbl,sgl %1,%0"
4699 [(set_attr "type" "fpalu")
4700 (set_attr "length" "4")])
4702 ;; Conversion between fixed point and floating point.
4703 ;; Note that among the fix-to-float insns
4704 ;; the ones that start with SImode come first.
4705 ;; That is so that an operand that is a CONST_INT
4706 ;; (and therefore lacks a specific machine mode).
4707 ;; will be recognized as SImode (which is always valid)
4708 ;; rather than as QImode or HImode.
4710 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4711 ;; to be reloaded by putting the constant into memory.
4712 ;; It must come before the more general floatsisf2 pattern.
4714 [(set (match_operand:SF 0 "register_operand" "=f")
4715 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4716 "! TARGET_SOFT_FLOAT"
4717 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4718 [(set_attr "type" "fpalu")
4719 (set_attr "length" "8")])
4721 (define_insn "floatsisf2"
4722 [(set (match_operand:SF 0 "register_operand" "=f")
4723 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4724 "! TARGET_SOFT_FLOAT"
4725 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4726 [(set_attr "type" "fpalu")
4727 (set_attr "length" "4")])
4729 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4730 ;; to be reloaded by putting the constant into memory.
4731 ;; It must come before the more general floatsidf2 pattern.
4733 [(set (match_operand:DF 0 "register_operand" "=f")
4734 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4735 "! TARGET_SOFT_FLOAT"
4736 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4737 [(set_attr "type" "fpalu")
4738 (set_attr "length" "8")])
4740 (define_insn "floatsidf2"
4741 [(set (match_operand:DF 0 "register_operand" "=f")
4742 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4743 "! TARGET_SOFT_FLOAT"
4744 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4745 [(set_attr "type" "fpalu")
4746 (set_attr "length" "4")])
4748 (define_expand "floatunssisf2"
4749 [(set (subreg:SI (match_dup 2) 4)
4750 (match_operand:SI 1 "register_operand" ""))
4751 (set (subreg:SI (match_dup 2) 0)
4753 (set (match_operand:SF 0 "register_operand" "")
4754 (float:SF (match_dup 2)))]
4755 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4760 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4763 operands[2] = gen_reg_rtx (DImode);
4766 (define_expand "floatunssidf2"
4767 [(set (subreg:SI (match_dup 2) 4)
4768 (match_operand:SI 1 "register_operand" ""))
4769 (set (subreg:SI (match_dup 2) 0)
4771 (set (match_operand:DF 0 "register_operand" "")
4772 (float:DF (match_dup 2)))]
4773 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4778 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4781 operands[2] = gen_reg_rtx (DImode);
4784 (define_insn "floatdisf2"
4785 [(set (match_operand:SF 0 "register_operand" "=f")
4786 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4787 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4788 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4789 [(set_attr "type" "fpalu")
4790 (set_attr "length" "4")])
4792 (define_insn "floatdidf2"
4793 [(set (match_operand:DF 0 "register_operand" "=f")
4794 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4795 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4796 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4797 [(set_attr "type" "fpalu")
4798 (set_attr "length" "4")])
4800 ;; Convert a float to an actual integer.
4801 ;; Truncation is performed as part of the conversion.
4803 (define_insn "fix_truncsfsi2"
4804 [(set (match_operand:SI 0 "register_operand" "=f")
4805 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4806 "! TARGET_SOFT_FLOAT"
4807 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4808 [(set_attr "type" "fpalu")
4809 (set_attr "length" "4")])
4811 (define_insn "fix_truncdfsi2"
4812 [(set (match_operand:SI 0 "register_operand" "=f")
4813 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4814 "! TARGET_SOFT_FLOAT"
4815 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4816 [(set_attr "type" "fpalu")
4817 (set_attr "length" "4")])
4819 (define_insn "fix_truncsfdi2"
4820 [(set (match_operand:DI 0 "register_operand" "=f")
4821 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4822 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4823 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4824 [(set_attr "type" "fpalu")
4825 (set_attr "length" "4")])
4827 (define_insn "fix_truncdfdi2"
4828 [(set (match_operand:DI 0 "register_operand" "=f")
4829 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4830 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4831 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4832 [(set_attr "type" "fpalu")
4833 (set_attr "length" "4")])
4835 (define_insn "floatunssidf2_pa20"
4836 [(set (match_operand:DF 0 "register_operand" "=f")
4837 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4838 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4840 [(set_attr "type" "fpalu")
4841 (set_attr "length" "4")])
4843 (define_insn "floatunssisf2_pa20"
4844 [(set (match_operand:SF 0 "register_operand" "=f")
4845 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4846 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4848 [(set_attr "type" "fpalu")
4849 (set_attr "length" "4")])
4851 (define_insn "floatunsdisf2"
4852 [(set (match_operand:SF 0 "register_operand" "=f")
4853 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4854 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4855 "fcnv,udw,sgl %1,%0"
4856 [(set_attr "type" "fpalu")
4857 (set_attr "length" "4")])
4859 (define_insn "floatunsdidf2"
4860 [(set (match_operand:DF 0 "register_operand" "=f")
4861 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4862 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4863 "fcnv,udw,dbl %1,%0"
4864 [(set_attr "type" "fpalu")
4865 (set_attr "length" "4")])
4867 (define_insn "fixuns_truncsfsi2"
4868 [(set (match_operand:SI 0 "register_operand" "=f")
4869 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4870 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4871 "fcnv,t,sgl,uw %1,%0"
4872 [(set_attr "type" "fpalu")
4873 (set_attr "length" "4")])
4875 (define_insn "fixuns_truncdfsi2"
4876 [(set (match_operand:SI 0 "register_operand" "=f")
4877 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4878 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4879 "fcnv,t,dbl,uw %1,%0"
4880 [(set_attr "type" "fpalu")
4881 (set_attr "length" "4")])
4883 (define_insn "fixuns_truncsfdi2"
4884 [(set (match_operand:DI 0 "register_operand" "=f")
4885 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4886 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4887 "fcnv,t,sgl,udw %1,%0"
4888 [(set_attr "type" "fpalu")
4889 (set_attr "length" "4")])
4891 (define_insn "fixuns_truncdfdi2"
4892 [(set (match_operand:DI 0 "register_operand" "=f")
4893 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4894 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4895 "fcnv,t,dbl,udw %1,%0"
4896 [(set_attr "type" "fpalu")
4897 (set_attr "length" "4")])
4899 ;;- arithmetic instructions
4901 (define_expand "adddi3"
4902 [(set (match_operand:DI 0 "register_operand" "")
4903 (plus:DI (match_operand:DI 1 "register_operand" "")
4904 (match_operand:DI 2 "adddi3_operand" "")))]
4909 [(set (match_operand:DI 0 "register_operand" "=r")
4910 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4911 (match_operand:DI 2 "arith11_operand" "rI")))]
4915 if (GET_CODE (operands[2]) == CONST_INT)
4917 if (INTVAL (operands[2]) >= 0)
4918 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4920 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4923 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4925 [(set_attr "type" "binary")
4926 (set_attr "length" "8")])
4929 [(set (match_operand:DI 0 "register_operand" "=r,r")
4930 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4931 (match_operand:DI 2 "arith14_operand" "r,J")))]
4936 [(set_attr "type" "binary,binary")
4937 (set_attr "pa_combine_type" "addmove")
4938 (set_attr "length" "4,4")])
4941 [(set (match_operand:DI 0 "register_operand" "=r")
4942 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4943 (match_operand:DI 2 "register_operand" "r")))]
4946 [(set_attr "type" "binary")
4947 (set_attr "length" "4")])
4950 [(set (match_operand:SI 0 "register_operand" "=r")
4951 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4952 (match_operand:SI 2 "register_operand" "r")))]
4955 [(set_attr "type" "binary")
4956 (set_attr "length" "4")])
4958 (define_expand "addvdi3"
4959 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4960 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
4961 (match_operand:DI 2 "arith11_operand" "")))
4962 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4963 (sign_extend:TI (match_dup 2)))
4964 (sign_extend:TI (plus:DI (match_dup 1)
4971 [(set (match_operand:DI 0 "register_operand" "=r,r")
4972 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
4973 (match_operand:DI 2 "arith11_operand" "r,I")))
4974 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4975 (sign_extend:TI (match_dup 2)))
4976 (sign_extend:TI (plus:DI (match_dup 1)
4982 addi,tsv,* %2,%1,%0"
4983 [(set_attr "type" "binary,binary")
4984 (set_attr "length" "4,4")])
4987 [(set (match_operand:DI 0 "register_operand" "=r")
4988 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
4989 (match_operand:DI 2 "arith11_operand" "rI")))
4990 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4991 (sign_extend:TI (match_dup 2)))
4992 (sign_extend:TI (plus:DI (match_dup 1)
4998 if (GET_CODE (operands[2]) == CONST_INT)
5000 if (INTVAL (operands[2]) >= 0)
5001 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5003 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5006 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5008 [(set_attr "type" "binary")
5009 (set_attr "length" "8")])
5011 ;; define_splits to optimize cases of adding a constant integer
5012 ;; to a register when the constant does not fit in 14 bits. */
5014 [(set (match_operand:SI 0 "register_operand" "")
5015 (plus:SI (match_operand:SI 1 "register_operand" "")
5016 (match_operand:SI 2 "const_int_operand" "")))
5017 (clobber (match_operand:SI 4 "register_operand" ""))]
5018 "! pa_cint_ok_for_move (UINTVAL (operands[2]))
5019 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5020 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5021 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5024 int val = INTVAL (operands[2]);
5025 int low = (val < 0) ? -0x2000 : 0x1fff;
5026 int rest = val - low;
5028 operands[2] = GEN_INT (rest);
5029 operands[3] = GEN_INT (low);
5033 [(set (match_operand:SI 0 "register_operand" "")
5034 (plus:SI (match_operand:SI 1 "register_operand" "")
5035 (match_operand:SI 2 "const_int_operand" "")))
5036 (clobber (match_operand:SI 4 "register_operand" ""))]
5037 "! pa_cint_ok_for_move (UINTVAL (operands[2]))"
5038 [(set (match_dup 4) (match_dup 2))
5039 (set (match_dup 0) (plus:SI (ashift:SI (match_dup 4) (match_dup 3))
5043 unsigned HOST_WIDE_INT intval = UINTVAL (operands[2]);
5045 /* Try dividing the constant by 2, then 4, and finally 8 to see
5046 if we can get a constant which can be loaded into a register
5047 in a single instruction (pa_cint_ok_for_move).
5049 If that fails, try to negate the constant and subtract it
5050 from our input operand. */
5051 if (intval % 2 == 0 && pa_cint_ok_for_move (intval / 2))
5053 operands[2] = GEN_INT (intval / 2);
5054 operands[3] = const1_rtx;
5056 else if (intval % 4 == 0 && pa_cint_ok_for_move (intval / 4))
5058 operands[2] = GEN_INT (intval / 4);
5059 operands[3] = const2_rtx;
5061 else if (intval % 8 == 0 && pa_cint_ok_for_move (intval / 8))
5063 operands[2] = GEN_INT (intval / 8);
5064 operands[3] = GEN_INT (3);
5066 else if (pa_cint_ok_for_move (-intval))
5068 emit_insn (gen_rtx_SET (operands[4], GEN_INT (-intval)));
5069 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5076 (define_insn "addsi3"
5077 [(set (match_operand:SI 0 "register_operand" "=r,r")
5078 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5079 (match_operand:SI 2 "arith14_operand" "r,J")))]
5082 {addl|add,l} %1,%2,%0
5084 [(set_attr "type" "binary,binary")
5085 (set_attr "pa_combine_type" "addmove")
5086 (set_attr "length" "4,4")])
5088 (define_insn "addvsi3"
5089 [(set (match_operand:SI 0 "register_operand" "=r,r")
5090 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5091 (match_operand:SI 2 "arith11_operand" "r,I")))
5092 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5093 (sign_extend:DI (match_dup 2)))
5094 (sign_extend:DI (plus:SI (match_dup 1)
5099 {addo|add,tsv} %2,%1,%0
5100 {addio|addi,tsv} %2,%1,%0"
5101 [(set_attr "type" "binary,binary")
5102 (set_attr "length" "4,4")])
5104 (define_expand "subdi3"
5105 [(set (match_operand:DI 0 "register_operand" "")
5106 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5107 (match_operand:DI 2 "reg_or_0_operand" "")))]
5112 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5113 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5114 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5120 [(set_attr "type" "binary,binary,move")
5121 (set_attr "length" "4,4,4")])
5124 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5125 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5126 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5130 if (GET_CODE (operands[1]) == CONST_INT)
5132 if (INTVAL (operands[1]) >= 0)
5133 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5135 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5138 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5140 [(set_attr "type" "binary")
5141 (set (attr "length")
5142 (if_then_else (eq_attr "alternative" "0")
5144 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5149 (define_expand "subvdi3"
5150 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5151 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5152 (match_operand:DI 2 "reg_or_0_operand" "")))
5153 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5154 (sign_extend:TI (match_dup 2)))
5155 (sign_extend:TI (minus:DI (match_dup 1)
5162 [(set (match_operand:DI 0 "register_operand" "=r,r")
5163 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5164 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5165 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5166 (sign_extend:TI (match_dup 2)))
5167 (sign_extend:TI (minus:DI (match_dup 1)
5172 {subo|sub,tsv} %1,%2,%0
5173 {subio|subi,tsv} %1,%2,%0"
5174 [(set_attr "type" "binary,binary")
5175 (set_attr "length" "4,4")])
5178 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5179 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5180 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5181 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5182 (sign_extend:TI (match_dup 2)))
5183 (sign_extend:TI (minus:DI (match_dup 1)
5189 if (GET_CODE (operands[1]) == CONST_INT)
5191 if (INTVAL (operands[1]) >= 0)
5192 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5194 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5197 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5199 [(set_attr "type" "binary,binary")
5200 (set (attr "length")
5201 (if_then_else (eq_attr "alternative" "0")
5203 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5208 (define_expand "subsi3"
5209 [(set (match_operand:SI 0 "register_operand" "")
5210 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5211 (match_operand:SI 2 "register_operand" "")))]
5216 [(set (match_operand:SI 0 "register_operand" "=r,r")
5217 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5218 (match_operand:SI 2 "register_operand" "r,r")))]
5223 [(set_attr "type" "binary,binary")
5224 (set_attr "length" "4,4")])
5227 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5228 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5229 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5235 [(set_attr "type" "binary,binary,move")
5236 (set_attr "length" "4,4,4")])
5238 (define_insn "subvsi3"
5239 [(set (match_operand:SI 0 "register_operand" "=r,r")
5240 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5241 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5242 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5243 (sign_extend:DI (match_dup 2)))
5244 (sign_extend:DI (minus:SI (match_dup 1)
5249 {subo|sub,tsv} %1,%2,%0
5250 {subio|subi,tsv} %1,%2,%0"
5251 [(set_attr "type" "binary,binary")
5252 (set_attr "length" "4,4")])
5254 ;; Trap instructions.
5257 [(trap_if (const_int 1) (const_int 0))]
5259 "{addit|addi,tc},<> 1,%%r0,%%r0"
5260 [(set_attr "type" "trap")
5261 (set_attr "length" "4")])
5263 ;; Clobbering a "register_operand" instead of a match_scratch
5264 ;; in operand3 of millicode calls avoids spilling %r1 and
5265 ;; produces better code.
5267 ;; The mulsi3 insns set up registers for the millicode call.
5268 (define_expand "mulsi3"
5269 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5270 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5271 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5272 (clobber (match_dup 3))
5273 (clobber (reg:SI 26))
5274 (clobber (reg:SI 25))
5275 (clobber (match_dup 4))])
5276 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5280 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5281 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5283 rtx scratch = gen_reg_rtx (DImode);
5284 operands[1] = force_reg (SImode, operands[1]);
5285 operands[2] = force_reg (SImode, operands[2]);
5286 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5287 emit_insn (gen_movsi (operands[0],
5288 gen_rtx_SUBREG (SImode, scratch,
5289 GET_MODE_SIZE (SImode))));
5292 operands[3] = gen_reg_rtx (SImode);
5295 (define_insn "umulsidi3"
5296 [(set (match_operand:DI 0 "register_operand" "=f")
5297 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5298 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5299 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5301 [(set_attr "type" "fpmuldbl")
5302 (set_attr "length" "4")])
5305 [(set (match_operand:DI 0 "register_operand" "=f")
5306 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5307 (match_operand:DI 2 "uint32_operand" "f")))]
5308 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5310 [(set_attr "type" "fpmuldbl")
5311 (set_attr "length" "4")])
5314 [(set (match_operand:DI 0 "register_operand" "=f")
5315 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5316 (match_operand:DI 2 "uint32_operand" "f")))]
5317 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5319 [(set_attr "type" "fpmuldbl")
5320 (set_attr "length" "4")])
5323 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5324 (clobber (match_operand:SI 0 "register_operand" "=a"))
5325 (clobber (reg:SI 26))
5326 (clobber (reg:SI 25))
5327 (clobber (reg:SI 31))]
5329 "* return pa_output_mul_insn (0, insn);"
5330 [(set_attr "type" "milli")
5331 (set (attr "length")
5332 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5333 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5336 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5337 (clobber (match_operand:SI 0 "register_operand" "=a"))
5338 (clobber (reg:SI 26))
5339 (clobber (reg:SI 25))
5340 (clobber (reg:SI 2))]
5342 "* return pa_output_mul_insn (0, insn);"
5343 [(set_attr "type" "milli")
5344 (set (attr "length")
5345 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5346 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5348 (define_expand "muldi3"
5349 [(set (match_operand:DI 0 "register_operand" "")
5350 (mult:DI (match_operand:DI 1 "register_operand" "")
5351 (match_operand:DI 2 "register_operand" "")))]
5352 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5355 rtx low_product = gen_reg_rtx (DImode);
5356 rtx cross_product1 = gen_reg_rtx (DImode);
5357 rtx cross_product2 = gen_reg_rtx (DImode);
5358 rtx cross_scratch = gen_reg_rtx (DImode);
5359 rtx cross_product = gen_reg_rtx (DImode);
5360 rtx op1l, op1r, op2l, op2r;
5361 rtx op1shifted, op2shifted;
5363 op1shifted = gen_reg_rtx (DImode);
5364 op2shifted = gen_reg_rtx (DImode);
5365 op1l = gen_reg_rtx (SImode);
5366 op1r = gen_reg_rtx (SImode);
5367 op2l = gen_reg_rtx (SImode);
5368 op2r = gen_reg_rtx (SImode);
5370 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5372 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5374 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5375 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5376 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5377 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5379 /* Emit multiplies for the cross products. */
5380 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5381 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5383 /* Emit a multiply for the low sub-word. */
5384 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5386 /* Sum the cross products and shift them into proper position. */
5387 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5388 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5390 /* Add the cross product to the low product and store the result
5391 into the output operand . */
5392 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5396 ;;; Division and mod.
5397 (define_expand "divsi3"
5398 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5399 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5400 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5401 (clobber (match_dup 3))
5402 (clobber (match_dup 4))
5403 (clobber (reg:SI 26))
5404 (clobber (reg:SI 25))
5405 (clobber (match_dup 5))])
5406 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5410 operands[3] = gen_reg_rtx (SImode);
5413 operands[5] = gen_rtx_REG (SImode, 2);
5414 operands[4] = operands[5];
5418 operands[5] = gen_rtx_REG (SImode, 31);
5419 operands[4] = gen_reg_rtx (SImode);
5421 if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
5427 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5428 (clobber (match_operand:SI 1 "register_operand" "=a"))
5429 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5430 (clobber (reg:SI 26))
5431 (clobber (reg:SI 25))
5432 (clobber (reg:SI 31))]
5435 return pa_output_div_insn (operands, 0, insn);"
5436 [(set_attr "type" "milli")
5437 (set (attr "length")
5438 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5439 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5443 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5444 (clobber (match_operand:SI 1 "register_operand" "=a"))
5445 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5446 (clobber (reg:SI 26))
5447 (clobber (reg:SI 25))
5448 (clobber (reg:SI 2))]
5451 return pa_output_div_insn (operands, 0, insn);"
5452 [(set_attr "type" "milli")
5453 (set (attr "length")
5454 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5455 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5457 (define_expand "udivsi3"
5458 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5459 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5460 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5461 (clobber (match_dup 3))
5462 (clobber (match_dup 4))
5463 (clobber (reg:SI 26))
5464 (clobber (reg:SI 25))
5465 (clobber (match_dup 5))])
5466 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5470 operands[3] = gen_reg_rtx (SImode);
5474 operands[5] = gen_rtx_REG (SImode, 2);
5475 operands[4] = operands[5];
5479 operands[5] = gen_rtx_REG (SImode, 31);
5480 operands[4] = gen_reg_rtx (SImode);
5482 if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
5488 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5489 (clobber (match_operand:SI 1 "register_operand" "=a"))
5490 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5491 (clobber (reg:SI 26))
5492 (clobber (reg:SI 25))
5493 (clobber (reg:SI 31))]
5496 return pa_output_div_insn (operands, 1, insn);"
5497 [(set_attr "type" "milli")
5498 (set (attr "length")
5499 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5500 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5504 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5505 (clobber (match_operand:SI 1 "register_operand" "=a"))
5506 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5507 (clobber (reg:SI 26))
5508 (clobber (reg:SI 25))
5509 (clobber (reg:SI 2))]
5512 return pa_output_div_insn (operands, 1, insn);"
5513 [(set_attr "type" "milli")
5514 (set (attr "length")
5515 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5516 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5518 (define_expand "modsi3"
5519 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5520 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5521 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5522 (clobber (match_dup 3))
5523 (clobber (match_dup 4))
5524 (clobber (reg:SI 26))
5525 (clobber (reg:SI 25))
5526 (clobber (match_dup 5))])
5527 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5533 operands[5] = gen_rtx_REG (SImode, 2);
5534 operands[4] = operands[5];
5538 operands[5] = gen_rtx_REG (SImode, 31);
5539 operands[4] = gen_reg_rtx (SImode);
5541 operands[3] = gen_reg_rtx (SImode);
5545 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5546 (clobber (match_operand:SI 0 "register_operand" "=a"))
5547 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5548 (clobber (reg:SI 26))
5549 (clobber (reg:SI 25))
5550 (clobber (reg:SI 31))]
5553 return pa_output_mod_insn (0, insn);"
5554 [(set_attr "type" "milli")
5555 (set (attr "length")
5556 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5557 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5560 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5561 (clobber (match_operand:SI 0 "register_operand" "=a"))
5562 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5563 (clobber (reg:SI 26))
5564 (clobber (reg:SI 25))
5565 (clobber (reg:SI 2))]
5568 return pa_output_mod_insn (0, insn);"
5569 [(set_attr "type" "milli")
5570 (set (attr "length")
5571 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5572 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5574 (define_expand "umodsi3"
5575 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5576 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5577 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5578 (clobber (match_dup 3))
5579 (clobber (match_dup 4))
5580 (clobber (reg:SI 26))
5581 (clobber (reg:SI 25))
5582 (clobber (match_dup 5))])
5583 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5589 operands[5] = gen_rtx_REG (SImode, 2);
5590 operands[4] = operands[5];
5594 operands[5] = gen_rtx_REG (SImode, 31);
5595 operands[4] = gen_reg_rtx (SImode);
5597 operands[3] = gen_reg_rtx (SImode);
5601 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5602 (clobber (match_operand:SI 0 "register_operand" "=a"))
5603 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5604 (clobber (reg:SI 26))
5605 (clobber (reg:SI 25))
5606 (clobber (reg:SI 31))]
5609 return pa_output_mod_insn (1, insn);"
5610 [(set_attr "type" "milli")
5611 (set (attr "length")
5612 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5613 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5616 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5617 (clobber (match_operand:SI 0 "register_operand" "=a"))
5618 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5619 (clobber (reg:SI 26))
5620 (clobber (reg:SI 25))
5621 (clobber (reg:SI 2))]
5624 return pa_output_mod_insn (1, insn);"
5625 [(set_attr "type" "milli")
5626 (set (attr "length")
5627 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
5628 (symbol_ref "pa_attr_length_millicode_call (insn)")))])
5630 ;;- and instructions
5631 ;; We define DImode `and` so with DImode `not` we can get
5632 ;; DImode `andn`. Other combinations are possible.
5634 (define_expand "anddi3"
5635 [(set (match_operand:DI 0 "register_operand" "")
5636 (and:DI (match_operand:DI 1 "register_operand" "")
5637 (match_operand:DI 2 "and_operand" "")))]
5642 [(set (match_operand:DI 0 "register_operand" "=r,r")
5643 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5644 (match_operand:DI 2 "and_operand" "rO,P")))]
5646 "* return pa_output_64bit_and (operands); "
5647 [(set_attr "type" "binary")
5648 (set_attr "length" "4")])
5650 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5651 ; constant with ldil;ldo.
5652 (define_insn "andsi3"
5653 [(set (match_operand:SI 0 "register_operand" "=r,r")
5654 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5655 (match_operand:SI 2 "and_operand" "rO,P")))]
5657 "* return pa_output_and (operands); "
5658 [(set_attr "type" "binary,shift")
5659 (set_attr "length" "4,4")])
5662 [(set (match_operand:DI 0 "register_operand" "=r")
5663 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5664 (match_operand:DI 2 "register_operand" "r")))]
5667 [(set_attr "type" "binary")
5668 (set_attr "length" "4")])
5671 [(set (match_operand:SI 0 "register_operand" "=r")
5672 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5673 (match_operand:SI 2 "register_operand" "r")))]
5676 [(set_attr "type" "binary")
5677 (set_attr "length" "4")])
5679 (define_expand "iordi3"
5680 [(set (match_operand:DI 0 "register_operand" "")
5681 (ior:DI (match_operand:DI 1 "register_operand" "")
5682 (match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
5687 [(set (match_operand:DI 0 "register_operand" "=r,r")
5688 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5689 (match_operand:DI 2 "cint_ior_operand" "M,i")))]
5691 "* return pa_output_64bit_ior (operands); "
5692 [(set_attr "type" "binary,shift")
5693 (set_attr "length" "4,4")])
5696 [(set (match_operand:DI 0 "register_operand" "=r")
5697 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5698 (match_operand:DI 2 "register_operand" "r")))]
5701 [(set_attr "type" "binary")
5702 (set_attr "length" "4")])
5704 ;; Need a define_expand because we've run out of CONST_OK... characters.
5705 (define_expand "iorsi3"
5706 [(set (match_operand:SI 0 "register_operand" "")
5707 (ior:SI (match_operand:SI 1 "register_operand" "")
5708 (match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
5713 [(set (match_operand:SI 0 "register_operand" "=r,r")
5714 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5715 (match_operand:SI 2 "cint_ior_operand" "M,i")))]
5717 "* return pa_output_ior (operands); "
5718 [(set_attr "type" "binary,shift")
5719 (set_attr "length" "4,4")])
5722 [(set (match_operand:SI 0 "register_operand" "=r")
5723 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5724 (match_operand:SI 2 "register_operand" "r")))]
5727 [(set_attr "type" "binary")
5728 (set_attr "length" "4")])
5730 (define_expand "xordi3"
5731 [(set (match_operand:DI 0 "register_operand" "")
5732 (xor:DI (match_operand:DI 1 "register_operand" "")
5733 (match_operand:DI 2 "register_operand" "")))]
5738 [(set (match_operand:DI 0 "register_operand" "=r")
5739 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5740 (match_operand:DI 2 "register_operand" "r")))]
5743 [(set_attr "type" "binary")
5744 (set_attr "length" "4")])
5746 (define_insn "xorsi3"
5747 [(set (match_operand:SI 0 "register_operand" "=r")
5748 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5749 (match_operand:SI 2 "register_operand" "r")))]
5752 [(set_attr "type" "binary")
5753 (set_attr "length" "4")])
5755 (define_expand "negdi2"
5756 [(set (match_operand:DI 0 "register_operand" "")
5757 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5762 [(set (match_operand:DI 0 "register_operand" "=r")
5763 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5765 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5766 [(set_attr "type" "unary")
5767 (set_attr "length" "8")])
5770 [(set (match_operand:DI 0 "register_operand" "=r")
5771 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5774 [(set_attr "type" "unary")
5775 (set_attr "length" "4")])
5777 (define_expand "negvdi2"
5778 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5779 (neg:DI (match_operand:DI 1 "register_operand" "")))
5780 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5781 (sign_extend:TI (neg:DI (match_dup 1))))
5787 [(set (match_operand:DI 0 "register_operand" "=r")
5788 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5789 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5790 (sign_extend:TI (neg:DI (match_dup 1))))
5793 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
5794 [(set_attr "type" "unary")
5795 (set_attr "length" "8")])
5798 [(set (match_operand:DI 0 "register_operand" "=r")
5799 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5800 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5801 (sign_extend:TI (neg:DI (match_dup 1))))
5804 "sub,tsv %%r0,%1,%0"
5805 [(set_attr "type" "unary")
5806 (set_attr "length" "4")])
5808 (define_insn "negsi2"
5809 [(set (match_operand:SI 0 "register_operand" "=r")
5810 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5813 [(set_attr "type" "unary")
5814 (set_attr "length" "4")])
5816 (define_insn "negvsi2"
5817 [(set (match_operand:SI 0 "register_operand" "=r")
5818 (neg:SI (match_operand:SI 1 "register_operand" "r")))
5819 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
5820 (sign_extend:DI (neg:SI (match_dup 1))))
5823 "{subo|sub,tsv} %%r0,%1,%0"
5824 [(set_attr "type" "unary")
5825 (set_attr "length" "4")])
5827 (define_expand "one_cmpldi2"
5828 [(set (match_operand:DI 0 "register_operand" "")
5829 (not:DI (match_operand:DI 1 "register_operand" "")))]
5836 [(set (match_operand:DI 0 "register_operand" "=r")
5837 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5839 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5840 [(set_attr "type" "unary")
5841 (set_attr "length" "8")])
5844 [(set (match_operand:DI 0 "register_operand" "=r")
5845 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5848 [(set_attr "type" "unary")
5849 (set_attr "length" "4")])
5851 (define_insn "one_cmplsi2"
5852 [(set (match_operand:SI 0 "register_operand" "=r")
5853 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5856 [(set_attr "type" "unary")
5857 (set_attr "length" "4")])
5859 ;; Floating point arithmetic instructions.
5861 (define_insn "adddf3"
5862 [(set (match_operand:DF 0 "register_operand" "=f")
5863 (plus:DF (match_operand:DF 1 "register_operand" "f")
5864 (match_operand:DF 2 "register_operand" "f")))]
5865 "! TARGET_SOFT_FLOAT"
5867 [(set_attr "type" "fpalu")
5868 (set_attr "pa_combine_type" "faddsub")
5869 (set_attr "length" "4")])
5871 (define_insn "addsf3"
5872 [(set (match_operand:SF 0 "register_operand" "=f")
5873 (plus:SF (match_operand:SF 1 "register_operand" "f")
5874 (match_operand:SF 2 "register_operand" "f")))]
5875 "! TARGET_SOFT_FLOAT"
5877 [(set_attr "type" "fpalu")
5878 (set_attr "pa_combine_type" "faddsub")
5879 (set_attr "length" "4")])
5881 (define_insn "subdf3"
5882 [(set (match_operand:DF 0 "register_operand" "=f")
5883 (minus:DF (match_operand:DF 1 "register_operand" "f")
5884 (match_operand:DF 2 "register_operand" "f")))]
5885 "! TARGET_SOFT_FLOAT"
5887 [(set_attr "type" "fpalu")
5888 (set_attr "pa_combine_type" "faddsub")
5889 (set_attr "length" "4")])
5891 (define_insn "subsf3"
5892 [(set (match_operand:SF 0 "register_operand" "=f")
5893 (minus:SF (match_operand:SF 1 "register_operand" "f")
5894 (match_operand:SF 2 "register_operand" "f")))]
5895 "! TARGET_SOFT_FLOAT"
5897 [(set_attr "type" "fpalu")
5898 (set_attr "pa_combine_type" "faddsub")
5899 (set_attr "length" "4")])
5901 (define_insn "muldf3"
5902 [(set (match_operand:DF 0 "register_operand" "=f")
5903 (mult:DF (match_operand:DF 1 "register_operand" "f")
5904 (match_operand:DF 2 "register_operand" "f")))]
5905 "! TARGET_SOFT_FLOAT"
5907 [(set_attr "type" "fpmuldbl")
5908 (set_attr "pa_combine_type" "fmpy")
5909 (set_attr "length" "4")])
5911 (define_insn "mulsf3"
5912 [(set (match_operand:SF 0 "register_operand" "=f")
5913 (mult:SF (match_operand:SF 1 "register_operand" "f")
5914 (match_operand:SF 2 "register_operand" "f")))]
5915 "! TARGET_SOFT_FLOAT"
5917 [(set_attr "type" "fpmulsgl")
5918 (set_attr "pa_combine_type" "fmpy")
5919 (set_attr "length" "4")])
5921 (define_insn "divdf3"
5922 [(set (match_operand:DF 0 "register_operand" "=f")
5923 (div:DF (match_operand:DF 1 "register_operand" "f")
5924 (match_operand:DF 2 "register_operand" "f")))]
5925 "! TARGET_SOFT_FLOAT"
5927 [(set_attr "type" "fpdivdbl")
5928 (set_attr "length" "4")])
5930 (define_insn "divsf3"
5931 [(set (match_operand:SF 0 "register_operand" "=f")
5932 (div:SF (match_operand:SF 1 "register_operand" "f")
5933 (match_operand:SF 2 "register_operand" "f")))]
5934 "! TARGET_SOFT_FLOAT"
5936 [(set_attr "type" "fpdivsgl")
5937 (set_attr "length" "4")])
5939 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5940 ;; negation can be done by subtracting from plus zero. However, this
5941 ;; violates the IEEE standard when negating plus and minus zero.
5942 ;; The slow path toggles the sign bit in the general registers.
5943 (define_expand "negdf2"
5944 [(set (match_operand:DF 0 "register_operand" "")
5945 (neg:DF (match_operand:DF 1 "register_operand" "")))]
5946 "!TARGET_SOFT_FLOAT"
5948 if (TARGET_PA_20 || !flag_signed_zeros)
5949 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5951 emit_insn (gen_negdf2_slow (operands[0], operands[1]));
5955 (define_insn "negdf2_slow"
5956 [(set (match_operand:DF 0 "register_operand" "=r")
5957 (neg:DF (match_operand:DF 1 "register_operand" "r")))]
5958 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
5961 if (rtx_equal_p (operands[0], operands[1]))
5962 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\";
5964 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\;copy %R1,%R0\";
5966 [(set_attr "type" "multi")
5967 (set (attr "length")
5968 (if_then_else (match_test "rtx_equal_p (operands[0], operands[1])")
5972 (define_insn "negdf2_fast"
5973 [(set (match_operand:DF 0 "register_operand" "=f")
5974 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5975 "!TARGET_SOFT_FLOAT"
5979 return \"fneg,dbl %1,%0\";
5981 return \"fsub,dbl %%fr0,%1,%0\";
5983 [(set_attr "type" "fpalu")
5984 (set_attr "length" "4")])
5986 (define_expand "negsf2"
5987 [(set (match_operand:SF 0 "register_operand" "")
5988 (neg:SF (match_operand:SF 1 "register_operand" "")))]
5989 "!TARGET_SOFT_FLOAT"
5991 if (TARGET_PA_20 || !flag_signed_zeros)
5992 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5994 emit_insn (gen_negsf2_slow (operands[0], operands[1]));
5998 (define_insn "negsf2_slow"
5999 [(set (match_operand:SF 0 "register_operand" "=r")
6000 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
6001 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
6002 "and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0"
6003 [(set_attr "type" "multi")
6004 (set_attr "length" "12")])
6006 (define_insn "negsf2_fast"
6007 [(set (match_operand:SF 0 "register_operand" "=f")
6008 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6009 "!TARGET_SOFT_FLOAT"
6013 return \"fneg,sgl %1,%0\";
6015 return \"fsub,sgl %%fr0,%1,%0\";
6017 [(set_attr "type" "fpalu")
6018 (set_attr "length" "4")])
6020 (define_insn "absdf2"
6021 [(set (match_operand:DF 0 "register_operand" "=f")
6022 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6023 "! TARGET_SOFT_FLOAT"
6025 [(set_attr "type" "fpalu")
6026 (set_attr "length" "4")])
6028 (define_insn "abssf2"
6029 [(set (match_operand:SF 0 "register_operand" "=f")
6030 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6031 "! TARGET_SOFT_FLOAT"
6033 [(set_attr "type" "fpalu")
6034 (set_attr "length" "4")])
6036 (define_insn "sqrtdf2"
6037 [(set (match_operand:DF 0 "register_operand" "=f")
6038 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6039 "! TARGET_SOFT_FLOAT"
6041 [(set_attr "type" "fpsqrtdbl")
6042 (set_attr "length" "4")])
6044 (define_insn "sqrtsf2"
6045 [(set (match_operand:SF 0 "register_operand" "=f")
6046 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6047 "! TARGET_SOFT_FLOAT"
6049 [(set_attr "type" "fpsqrtsgl")
6050 (set_attr "length" "4")])
6052 ;; PA 2.0 floating point instructions
6055 (define_insn "fmadf4"
6056 [(set (match_operand:DF 0 "register_operand" "=f")
6057 (fma:DF (match_operand:DF 1 "register_operand" "f")
6058 (match_operand:DF 2 "register_operand" "f")
6059 (match_operand:DF 3 "register_operand" "f")))]
6060 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6061 "fmpyfadd,dbl %1,%2,%3,%0"
6062 [(set_attr "type" "fpmuldbl")
6063 (set_attr "length" "4")])
6065 (define_insn "fmasf4"
6066 [(set (match_operand:SF 0 "register_operand" "=f")
6067 (fma:SF (match_operand:SF 1 "register_operand" "f")
6068 (match_operand:SF 2 "register_operand" "f")
6069 (match_operand:SF 3 "register_operand" "f")))]
6070 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6071 "fmpyfadd,sgl %1,%2,%3,%0"
6072 [(set_attr "type" "fpmulsgl")
6073 (set_attr "length" "4")])
6075 ; fmpynfadd patterns
6076 (define_insn "fnmadf4"
6077 [(set (match_operand:DF 0 "register_operand" "=f")
6078 (fma:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
6079 (match_operand:DF 2 "register_operand" "f")
6080 (match_operand:DF 3 "register_operand" "f")))]
6081 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6082 "fmpynfadd,dbl %1,%2,%3,%0"
6083 [(set_attr "type" "fpmuldbl")
6084 (set_attr "length" "4")])
6086 (define_insn "fnmasf4"
6087 [(set (match_operand:SF 0 "register_operand" "=f")
6088 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
6089 (match_operand:SF 2 "register_operand" "f")
6090 (match_operand:SF 3 "register_operand" "f")))]
6091 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6092 "fmpynfadd,sgl %1,%2,%3,%0"
6093 [(set_attr "type" "fpmulsgl")
6094 (set_attr "length" "4")])
6098 [(set (match_operand:DF 0 "register_operand" "=f")
6099 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6100 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6102 [(set_attr "type" "fpalu")
6103 (set_attr "length" "4")])
6106 [(set (match_operand:SF 0 "register_operand" "=f")
6107 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6108 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6110 [(set_attr "type" "fpalu")
6111 (set_attr "length" "4")])
6114 [(set (match_operand:DF 0 "register_operand" "=f")
6115 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6116 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6117 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6118 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6120 [(set_attr "type" "fpalu")
6121 (set_attr "length" "8")])
6124 [(set (match_operand:DF 0 "register_operand" "")
6125 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6126 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6127 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6128 [(set (match_dup 2) (abs:DF (match_dup 1)))
6129 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6133 [(set (match_operand:SF 0 "register_operand" "=f")
6134 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6135 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6136 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6137 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6139 [(set_attr "type" "fpalu")
6140 (set_attr "length" "8")])
6143 [(set (match_operand:SF 0 "register_operand" "")
6144 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6145 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6146 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6147 [(set (match_dup 2) (abs:SF (match_dup 1)))
6148 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6151 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6152 ;; instruction if we can ignore the sign of zero.
6154 [(set (match_operand:DF 0 "register_operand" "=f")
6155 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6156 (match_operand:DF 2 "register_operand" "f"))))]
6157 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6158 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6159 [(set_attr "type" "fpmuldbl")
6160 (set_attr "length" "4")])
6163 [(set (match_operand:SF 0 "register_operand" "=f")
6164 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6165 (match_operand:SF 2 "register_operand" "f"))))]
6166 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6167 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6168 [(set_attr "type" "fpmuldbl")
6169 (set_attr "length" "4")])
6172 [(set (match_operand:DF 0 "register_operand" "=f")
6173 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6174 (match_operand:DF 2 "register_operand" "f"))))
6175 (set (match_operand:DF 3 "register_operand" "=&f")
6176 (mult:DF (match_dup 1) (match_dup 2)))]
6177 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6178 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6179 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6181 [(set_attr "type" "fpmuldbl")
6182 (set_attr "length" "8")])
6185 [(set (match_operand:DF 0 "register_operand" "")
6186 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6187 (match_operand:DF 2 "register_operand" ""))))
6188 (set (match_operand:DF 3 "register_operand" "")
6189 (mult:DF (match_dup 1) (match_dup 2)))]
6190 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6191 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6192 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6196 [(set (match_operand:SF 0 "register_operand" "=f")
6197 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6198 (match_operand:SF 2 "register_operand" "f"))))
6199 (set (match_operand:SF 3 "register_operand" "=&f")
6200 (mult:SF (match_dup 1) (match_dup 2)))]
6201 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6202 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6203 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6205 [(set_attr "type" "fpmuldbl")
6206 (set_attr "length" "8")])
6209 [(set (match_operand:SF 0 "register_operand" "")
6210 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6211 (match_operand:SF 2 "register_operand" ""))))
6212 (set (match_operand:SF 3 "register_operand" "")
6213 (mult:SF (match_dup 1) (match_dup 2)))]
6214 "!TARGET_SOFT_FLOAT && TARGET_PA_20&& !flag_signed_zeros"
6215 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6216 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6219 ;;- Shift instructions
6221 ;; Optimized special case of shifting.
6224 [(set (match_operand:SI 0 "register_operand" "=r")
6225 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6229 [(set_attr "type" "load")
6230 (set_attr "length" "4")])
6233 [(set (match_operand:SI 0 "register_operand" "=r")
6234 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6238 [(set_attr "type" "load")
6239 (set_attr "length" "4")])
6242 [(set (match_operand:SI 0 "register_operand" "=r")
6243 (plus:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
6244 (match_operand:SI 3 "shadd_operand" ""))
6245 (match_operand:SI 1 "register_operand" "r")))]
6247 "{sh%o3addl %2,%1,%0|shladd,l %2,%o3,%1,%0} "
6248 [(set_attr "type" "binary")
6249 (set_attr "length" "4")])
6252 [(set (match_operand:SI 0 "register_operand" "=r")
6253 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6254 (match_operand:SI 3 "mem_shadd_operand" ""))
6255 (match_operand:SI 1 "register_operand" "r")))]
6259 int shift_val = exact_log2 (INTVAL (operands[3]));
6260 operands[3] = GEN_INT (shift_val);
6261 return \"{sh%o3addl %2,%1,%0|shladd,l %2,%o3,%1,%0}\";
6263 [(set_attr "type" "binary")
6264 (set_attr "length" "4")])
6267 [(set (match_operand:DI 0 "register_operand" "=r")
6268 (plus:DI (ashift:DI (match_operand:DI 2 "register_operand" "r")
6269 (match_operand:DI 3 "shadd_operand" ""))
6270 (match_operand:DI 1 "register_operand" "r")))]
6272 "shladd,l %2,%o3,%1,%0"
6273 [(set_attr "type" "binary")
6274 (set_attr "length" "4")])
6277 [(set (match_operand:DI 0 "register_operand" "=r")
6278 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6279 (match_operand:DI 3 "mem_shadd_operand" ""))
6280 (match_operand:DI 1 "register_operand" "r")))]
6284 int shift_val = exact_log2 (INTVAL (operands[3]));
6285 operands[3] = GEN_INT (shift_val);
6286 return \"shladd,l %2,%o3,%1,%0\";
6288 [(set_attr "type" "binary")
6289 (set_attr "length" "4")])
6291 (define_expand "ashlsi3"
6292 [(set (match_operand:SI 0 "register_operand" "")
6293 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6294 (match_operand:SI 2 "arith32_operand" "")))]
6298 if (GET_CODE (operands[2]) != CONST_INT)
6300 rtx temp = gen_reg_rtx (SImode);
6301 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6302 if (GET_CODE (operands[1]) == CONST_INT)
6303 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6305 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6308 /* Make sure both inputs are not constants,
6309 there are no patterns for that. */
6310 operands[1] = force_reg (SImode, operands[1]);
6314 [(set (match_operand:SI 0 "register_operand" "=r")
6315 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6316 (match_operand:SI 2 "const_int_operand" "n")))]
6318 "{zdep|depw,z} %1,%P2,%L2,%0"
6319 [(set_attr "type" "shift")
6320 (set_attr "length" "4")])
6322 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6323 ; Doing it like this makes slightly better code since reload can
6324 ; replace a register with a known value in range -16..15 with a
6325 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6326 ; but since we have no more CONST_OK... characters, that is not
6328 (define_insn "zvdep32"
6329 [(set (match_operand:SI 0 "register_operand" "=r,r")
6330 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6331 (minus:SI (const_int 31)
6332 (match_operand:SI 2 "register_operand" "q,q"))))]
6335 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6336 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6337 [(set_attr "type" "shift,shift")
6338 (set_attr "length" "4,4")])
6340 (define_insn "zvdep_imm32"
6341 [(set (match_operand:SI 0 "register_operand" "=r")
6342 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6343 (minus:SI (const_int 31)
6344 (match_operand:SI 2 "register_operand" "q"))))]
6348 unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
6349 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6350 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6351 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6353 [(set_attr "type" "shift")
6354 (set_attr "length" "4")])
6356 (define_insn "vdepi_ior"
6357 [(set (match_operand:SI 0 "register_operand" "=r")
6358 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6359 (minus:SI (const_int 31)
6360 (match_operand:SI 2 "register_operand" "q")))
6361 (match_operand:SI 3 "register_operand" "0")))]
6362 ; accept ...0001...1, can this be generalized?
6363 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6366 HOST_WIDE_INT x = INTVAL (operands[1]);
6367 operands[2] = GEN_INT (exact_log2 (x + 1));
6368 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6370 [(set_attr "type" "shift")
6371 (set_attr "length" "4")])
6373 (define_insn "vdepi_and"
6374 [(set (match_operand:SI 0 "register_operand" "=r")
6375 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6376 (minus:SI (const_int 31)
6377 (match_operand:SI 2 "register_operand" "q")))
6378 (match_operand:SI 3 "register_operand" "0")))]
6379 ; this can be generalized...!
6380 "INTVAL (operands[1]) == -2"
6383 HOST_WIDE_INT x = INTVAL (operands[1]);
6384 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6385 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6387 [(set_attr "type" "shift")
6388 (set_attr "length" "4")])
6390 (define_expand "ashldi3"
6391 [(set (match_operand:DI 0 "register_operand" "")
6392 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6393 (match_operand:DI 2 "arith32_operand" "")))]
6397 if (GET_CODE (operands[2]) != CONST_INT)
6399 rtx temp = gen_reg_rtx (DImode);
6400 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6401 if (GET_CODE (operands[1]) == CONST_INT)
6402 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6404 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6407 /* Make sure both inputs are not constants,
6408 there are no patterns for that. */
6409 operands[1] = force_reg (DImode, operands[1]);
6413 [(set (match_operand:DI 0 "register_operand" "=r")
6414 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6415 (match_operand:DI 2 "const_int_operand" "n")))]
6417 "depd,z %1,%p2,%Q2,%0"
6418 [(set_attr "type" "shift")
6419 (set_attr "length" "4")])
6421 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6422 ; Doing it like this makes slightly better code since reload can
6423 ; replace a register with a known value in range -16..15 with a
6424 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6425 ; but since we have no more CONST_OK... characters, that is not
6427 (define_insn "zvdep64"
6428 [(set (match_operand:DI 0 "register_operand" "=r,r")
6429 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6430 (minus:DI (const_int 63)
6431 (match_operand:DI 2 "register_operand" "q,q"))))]
6434 depd,z %1,%%sar,64,%0
6435 depdi,z %1,%%sar,64,%0"
6436 [(set_attr "type" "shift,shift")
6437 (set_attr "length" "4,4")])
6439 (define_insn "zvdep_imm64"
6440 [(set (match_operand:DI 0 "register_operand" "=r")
6441 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6442 (minus:DI (const_int 63)
6443 (match_operand:DI 2 "register_operand" "q"))))]
6447 unsigned HOST_WIDE_INT x = UINTVAL (operands[1]);
6448 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6449 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6450 return \"depdi,z %1,%%sar,%2,%0\";
6452 [(set_attr "type" "shift")
6453 (set_attr "length" "4")])
6456 [(set (match_operand:DI 0 "register_operand" "=r")
6457 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6458 (minus:DI (const_int 63)
6459 (match_operand:DI 2 "register_operand" "q")))
6460 (match_operand:DI 3 "register_operand" "0")))]
6461 ; accept ...0001...1, can this be generalized?
6462 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
6465 HOST_WIDE_INT x = INTVAL (operands[1]);
6466 operands[2] = GEN_INT (exact_log2 (x + 1));
6467 return \"depdi -1,%%sar,%2,%0\";
6469 [(set_attr "type" "shift")
6470 (set_attr "length" "4")])
6473 [(set (match_operand:DI 0 "register_operand" "=r")
6474 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6475 (minus:DI (const_int 63)
6476 (match_operand:DI 2 "register_operand" "q")))
6477 (match_operand:DI 3 "register_operand" "0")))]
6478 ; this can be generalized...!
6479 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6482 HOST_WIDE_INT x = INTVAL (operands[1]);
6483 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6484 return \"depdi 0,%%sar,%2,%0\";
6486 [(set_attr "type" "shift")
6487 (set_attr "length" "4")])
6489 (define_expand "ashrsi3"
6490 [(set (match_operand:SI 0 "register_operand" "")
6491 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6492 (match_operand:SI 2 "arith32_operand" "")))]
6496 if (GET_CODE (operands[2]) != CONST_INT)
6498 rtx temp = gen_reg_rtx (SImode);
6499 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6500 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6506 [(set (match_operand:SI 0 "register_operand" "=r")
6507 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6508 (match_operand:SI 2 "const_int_operand" "n")))]
6510 "{extrs|extrw,s} %1,%P2,%L2,%0"
6511 [(set_attr "type" "shift")
6512 (set_attr "length" "4")])
6514 (define_insn "vextrs32"
6515 [(set (match_operand:SI 0 "register_operand" "=r")
6516 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6517 (minus:SI (const_int 31)
6518 (match_operand:SI 2 "register_operand" "q"))))]
6520 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6521 [(set_attr "type" "shift")
6522 (set_attr "length" "4")])
6524 (define_expand "ashrdi3"
6525 [(set (match_operand:DI 0 "register_operand" "")
6526 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6527 (match_operand:DI 2 "arith32_operand" "")))]
6531 if (GET_CODE (operands[2]) != CONST_INT)
6533 rtx temp = gen_reg_rtx (DImode);
6534 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6535 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6541 [(set (match_operand:DI 0 "register_operand" "=r")
6542 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6543 (match_operand:DI 2 "const_int_operand" "n")))]
6545 "extrd,s %1,%p2,%Q2,%0"
6546 [(set_attr "type" "shift")
6547 (set_attr "length" "4")])
6549 (define_insn "vextrs64"
6550 [(set (match_operand:DI 0 "register_operand" "=r")
6551 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6552 (minus:DI (const_int 63)
6553 (match_operand:DI 2 "register_operand" "q"))))]
6555 "extrd,s %1,%%sar,64,%0"
6556 [(set_attr "type" "shift")
6557 (set_attr "length" "4")])
6559 (define_insn "lshrsi3"
6560 [(set (match_operand:SI 0 "register_operand" "=r,r")
6561 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6562 (match_operand:SI 2 "shift5_operand" "q,n")))]
6565 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6566 {extru|extrw,u} %1,%P2,%L2,%0"
6567 [(set_attr "type" "shift")
6568 (set_attr "length" "4")])
6570 (define_insn "lshrdi3"
6571 [(set (match_operand:DI 0 "register_operand" "=r,r")
6572 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6573 (match_operand:DI 2 "shift6_operand" "q,n")))]
6576 shrpd %%r0,%1,%%sar,%0
6577 extrd,u %1,%p2,%Q2,%0"
6578 [(set_attr "type" "shift")
6579 (set_attr "length" "4")])
6581 ; Shift right pair word 0 to 31 bits.
6582 (define_insn "shrpsi4"
6583 [(set (match_operand:SI 0 "register_operand" "=r,r")
6584 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
6585 (minus:SI (const_int 32)
6586 (match_operand:SI 3 "shift5_operand" "q,n")))
6587 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r,r")
6591 {vshd %1,%2,%0|shrpw %1,%2,%%sar,%0}
6592 {shd|shrpw} %1,%2,%3,%0"
6593 [(set_attr "type" "shift")
6594 (set_attr "length" "4")])
6596 ; Shift right pair doubleword 0 to 63 bits.
6597 (define_insn "shrpdi4"
6598 [(set (match_operand:DI 0 "register_operand" "=r,r")
6599 (ior:DI (ashift:DI (match_operand:SI 1 "register_operand" "r,r")
6600 (minus:DI (const_int 64)
6601 (match_operand:DI 3 "shift6_operand" "q,n")))
6602 (lshiftrt:DI (match_operand:DI 2 "register_operand" "r,r")
6606 shrpd %1,%2,%%sar,%0
6608 [(set_attr "type" "shift")
6609 (set_attr "length" "4")])
6611 (define_insn "rotrsi3"
6612 [(set (match_operand:SI 0 "register_operand" "=r,r")
6613 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6614 (match_operand:SI 2 "shift5_operand" "q,n")))]
6618 if (GET_CODE (operands[2]) == CONST_INT)
6620 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6621 return \"{shd|shrpw} %1,%1,%2,%0\";
6624 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6626 [(set_attr "type" "shift")
6627 (set_attr "length" "4")])
6629 (define_expand "rotlsi3"
6630 [(set (match_operand:SI 0 "register_operand" "")
6631 (rotate:SI (match_operand:SI 1 "register_operand" "")
6632 (match_operand:SI 2 "arith32_operand" "")))]
6636 if (GET_CODE (operands[2]) != CONST_INT)
6638 rtx temp = gen_reg_rtx (SImode);
6639 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6640 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6643 /* Else expand normally. */
6647 [(set (match_operand:SI 0 "register_operand" "=r")
6648 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6649 (match_operand:SI 2 "const_int_operand" "n")))]
6653 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6654 return \"{shd|shrpw} %1,%1,%2,%0\";
6656 [(set_attr "type" "shift")
6657 (set_attr "length" "4")])
6660 [(set (match_operand:SI 0 "register_operand" "=r")
6661 (match_operator:SI 5 "plus_xor_ior_operator"
6662 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6663 (match_operand:SI 3 "const_int_operand" "n"))
6664 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6665 (match_operand:SI 4 "const_int_operand" "n"))]))]
6666 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6667 "{shd|shrpw} %1,%2,%4,%0"
6668 [(set_attr "type" "shift")
6669 (set_attr "length" "4")])
6672 [(set (match_operand:SI 0 "register_operand" "=r")
6673 (match_operator:SI 5 "plus_xor_ior_operator"
6674 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6675 (match_operand:SI 4 "const_int_operand" "n"))
6676 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6677 (match_operand:SI 3 "const_int_operand" "n"))]))]
6678 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6679 "{shd|shrpw} %1,%2,%4,%0"
6680 [(set_attr "type" "shift")
6681 (set_attr "length" "4")])
6684 [(set (match_operand:SI 0 "register_operand" "=r")
6685 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6686 (match_operand:SI 2 "const_int_operand" ""))
6687 (match_operand:SI 3 "const_int_operand" "")))]
6688 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
6691 int cnt = INTVAL (operands[2]) & 31;
6692 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6693 operands[2] = GEN_INT (31 - cnt);
6694 return \"{zdep|depw,z} %1,%2,%3,%0\";
6696 [(set_attr "type" "shift")
6697 (set_attr "length" "4")])
6699 ;; Unconditional and other jump instructions.
6701 ;; Trivial return used when no epilogue is needed.
6702 (define_insn "return"
6705 "pa_can_use_return_insn ()"
6709 return \"bve%* (%%r2)\";
6710 return \"bv%* %%r0(%%r2)\";
6712 [(set_attr "type" "branch")
6713 (set_attr "length" "4")])
6715 ;; This is used for most returns.
6716 (define_insn "return_internal"
6723 return \"bve%* (%%r2)\";
6724 return \"bv%* %%r0(%%r2)\";
6726 [(set_attr "type" "branch")
6727 (set_attr "length" "4")])
6729 ;; This is used for eh returns which bypass the return stub.
6730 (define_insn "return_external_pic"
6732 (clobber (reg:SI 1))
6734 "!TARGET_NO_SPACE_REGS
6736 && flag_pic && crtl->calls_eh_return"
6737 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6738 [(set_attr "type" "branch")
6739 (set_attr "length" "12")])
6741 (define_expand "prologue"
6744 "pa_expand_prologue ();DONE;")
6746 (define_expand "sibcall_epilogue"
6751 pa_expand_epilogue ();
6755 (define_expand "epilogue"
6762 /* Try to use the trivial return first. Else use the full epilogue. */
6763 if (pa_can_use_return_insn ())
6767 pa_expand_epilogue ();
6769 /* EH returns bypass the normal return stub. Thus, we must do an
6770 interspace branch to return from functions that call eh_return.
6771 This is only a problem for returns from shared code on ports
6772 using space registers. */
6773 if (!TARGET_NO_SPACE_REGS
6775 && flag_pic && crtl->calls_eh_return)
6776 x = gen_return_external_pic ();
6778 x = gen_return_internal ();
6784 ; Used by hppa_profile_hook to load the starting address of the current
6785 ; function; operand 1 contains the address of the label in operand 3
6786 (define_insn "load_offset_label_address"
6787 [(set (match_operand:SI 0 "register_operand" "=r")
6788 (plus:SI (match_operand:SI 1 "register_operand" "r")
6789 (minus:SI (match_operand:SI 2 "" "")
6790 (label_ref:SI (match_operand 3 "" "")))))]
6793 [(set_attr "type" "multi")
6794 (set_attr "length" "4")])
6796 ; Output a code label and load its address.
6797 (define_insn "lcla1"
6798 [(set (match_operand:SI 0 "register_operand" "=r")
6799 (label_ref:SI (match_operand 1 "" "")))
6804 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6805 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6806 CODE_LABEL_NUMBER (operands[1]));
6809 [(set_attr "type" "multi")
6810 (set_attr "length" "8")])
6812 (define_insn "lcla2"
6813 [(set (match_operand:SI 0 "register_operand" "=r")
6814 (label_ref:SI (match_operand 1 "" "")))
6819 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6820 CODE_LABEL_NUMBER (operands[1]));
6823 [(set_attr "type" "move")
6824 (set_attr "length" "4")])
6826 (define_insn "blockage"
6827 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6830 [(set_attr "length" "0")])
6833 [(set (pc) (label_ref (match_operand 0 "" "")))]
6837 /* An unconditional branch which can reach its target. */
6838 if (get_attr_length (insn) < 16)
6841 return pa_output_lbranch (operands[0], insn, 1);
6843 [(set_attr "type" "uncond_branch")
6844 (set_attr "pa_combine_type" "uncond_branch")
6845 (set (attr "length")
6846 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6847 (const_int MAX_17BIT_OFFSET))
6849 (match_test "TARGET_PORTABLE_RUNTIME")
6851 (not (match_test "flag_pic"))
6855 ;;; Hope this is only within a function...
6856 (define_insn "indirect_jump"
6857 [(set (pc) (match_operand 0 "pmode_register_operand" "r"))]
6860 [(set_attr "type" "branch")
6861 (set_attr "length" "4")])
6863 ;;; An indirect jump can be optimized to a direct jump. GAS for the
6864 ;;; SOM target doesn't allow branching to a label inside a function.
6865 ;;; We also don't correctly compute branch distances for labels
6866 ;;; outside the current function. Thus, we use an indirect jump can't
6867 ;;; be optimized to a direct jump for all targets. We assume that
6868 ;;; the branch target is in the same space (i.e., nested function
6869 ;;; jumping to a label in an outer function in the same translation
6871 (define_expand "nonlocal_goto"
6872 [(use (match_operand 0 "general_operand" ""))
6873 (use (match_operand 1 "general_operand" ""))
6874 (use (match_operand 2 "general_operand" ""))
6875 (use (match_operand 3 "general_operand" ""))]
6878 rtx lab = operands[1];
6879 rtx stack = operands[2];
6880 rtx fp = operands[3];
6882 lab = copy_to_reg (lab);
6884 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
6885 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
6887 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
6888 instead of the hard_frame_pointer_rtx in the save area. As a
6889 result, an extra instruction is needed to adjust for the offset
6890 of the virtual stack variables and the hard frame pointer. */
6891 if (GET_CODE (fp) != REG)
6892 fp = force_reg (Pmode, fp);
6893 emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8));
6895 emit_stack_restore (SAVE_NONLOCAL, stack);
6897 emit_use (hard_frame_pointer_rtx);
6898 emit_use (stack_pointer_rtx);
6900 /* Nonlocal goto jumps are only used between functions in the same
6901 translation unit. Thus, we can avoid the extra overhead of an
6903 emit_jump_insn (gen_indirect_goto (lab));
6908 (define_insn "indirect_goto"
6909 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
6910 "GET_MODE (operands[0]) == word_mode"
6912 [(set_attr "type" "branch")
6913 (set_attr "length" "4")])
6915 ;; Subroutines of "casesi".
6916 ;; operand 0 is index
6917 ;; operand 1 is the minimum bound
6918 ;; operand 2 is the maximum bound - minimum bound + 1
6919 ;; operand 3 is CODE_LABEL for the table;
6920 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6922 (define_expand "casesi"
6923 [(match_operand:SI 0 "general_operand" "")
6924 (match_operand:SI 1 "const_int_operand" "")
6925 (match_operand:SI 2 "const_int_operand" "")
6926 (match_operand 3 "" "")
6927 (match_operand 4 "" "")]
6931 if (GET_CODE (operands[0]) != REG)
6932 operands[0] = force_reg (SImode, operands[0]);
6934 if (operands[1] != const0_rtx)
6936 rtx index = gen_reg_rtx (SImode);
6938 operands[1] = gen_int_mode (-INTVAL (operands[1]), SImode);
6939 if (!INT_14_BITS (operands[1]))
6940 operands[1] = force_reg (SImode, operands[1]);
6941 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6942 operands[0] = index;
6945 if (!INT_5_BITS (operands[2]))
6946 operands[2] = force_reg (SImode, operands[2]);
6948 /* This branch prevents us finding an insn for the delay slot of the
6949 following vectored branch. It might be possible to use the delay
6950 slot if an index value of -1 was used to transfer to the out-of-range
6951 label. In order to do this, we would have to output the -1 vector
6952 element after the delay insn. The casesi output code would have to
6953 check if the casesi insn is in a delay branch sequence and output
6954 the delay insn if one is found. If this was done, then it might
6955 then be worthwhile to split the casesi patterns to improve scheduling.
6956 However, it's not clear that all this extra complexity is worth
6959 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
6960 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
6963 /* In 64bit mode we must make sure to wipe the upper bits of the register
6964 just in case the addition overflowed or we had random bits in the
6965 high part of the register. */
6968 rtx index = gen_reg_rtx (DImode);
6970 emit_insn (gen_extendsidi2 (index, operands[0]));
6971 operands[0] = index;
6975 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
6977 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
6979 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
6983 ;;; 32-bit code, absolute branch table.
6984 (define_insn "casesi32"
6985 [(set (pc) (mem:SI (plus:SI
6986 (mult:SI (match_operand:SI 0 "register_operand" "r")
6988 (label_ref (match_operand 1 "" "")))))
6989 (clobber (match_scratch:SI 2 "=&r"))]
6991 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6992 [(set_attr "type" "multi")
6993 (set_attr "length" "16")])
6995 ;;; 32-bit code, relative branch table.
6996 (define_insn "casesi32p"
6997 [(set (pc) (mem:SI (plus:SI
6998 (mult:SI (match_operand:SI 0 "register_operand" "r")
7000 (label_ref (match_operand 1 "" "")))))
7001 (clobber (match_scratch:SI 2 "=&r"))
7002 (clobber (match_scratch:SI 3 "=&r"))]
7004 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
7005 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7006 [(set_attr "type" "multi")
7007 (set (attr "length")
7008 (if_then_else (match_test "TARGET_PA_20")
7012 ;;; 64-bit code, 32-bit relative branch table.
7013 (define_insn "casesi64p"
7014 [(set (pc) (mem:DI (plus:DI
7015 (mult:DI (match_operand:DI 0 "register_operand" "r")
7017 (label_ref (match_operand 1 "" "")))))
7018 (clobber (match_scratch:DI 2 "=&r"))
7019 (clobber (match_scratch:DI 3 "=&r"))]
7021 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7022 add,l %2,%3,%3\;bv,n %%r0(%3)"
7023 [(set_attr "type" "multi")
7024 (set_attr "length" "24")])
7028 ;;- jump to subroutine
7030 (define_expand "call"
7031 [(parallel [(call (match_operand:SI 0 "" "")
7032 (match_operand 1 "" ""))
7033 (clobber (reg:SI 2))])]
7038 rtx nb = operands[1];
7040 if (TARGET_PORTABLE_RUNTIME)
7041 op = force_reg (SImode, XEXP (operands[0], 0));
7044 op = XEXP (operands[0], 0);
7046 /* Generate indirect long calls to non-local functions. */
7047 if (TARGET_LONG_CALLS && GET_CODE (op) == SYMBOL_REF)
7049 tree call_decl = SYMBOL_REF_DECL (op);
7050 if (!(call_decl && targetm.binds_local_p (call_decl)))
7051 op = force_reg (word_mode, op);
7057 if (!virtuals_instantiated)
7058 emit_move_insn (arg_pointer_rtx,
7059 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7063 /* The loop pass can generate new libcalls after the virtual
7064 registers are instantiated when fpregs are disabled because
7065 the only method that we have for doing DImode multiplication
7066 is with a libcall. This could be trouble if we haven't
7067 allocated enough space for the outgoing arguments. */
7068 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7070 emit_move_insn (arg_pointer_rtx,
7071 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7072 GEN_INT (STACK_POINTER_OFFSET + 64)));
7076 /* Use two different patterns for calls to explicitly named functions
7077 and calls through function pointers. This is necessary as these two
7078 types of calls use different calling conventions, and CSE might try
7079 to change the named call into an indirect call in some cases (using
7080 two patterns keeps CSE from performing this optimization).
7082 We now use even more call patterns as there was a subtle bug in
7083 attempting to restore the pic register after a call using a simple
7084 move insn. During reload, a instruction involving a pseudo register
7085 with no explicit dependence on the PIC register can be converted
7086 to an equivalent load from memory using the PIC register. If we
7087 emit a simple move to restore the PIC register in the initial rtl
7088 generation, then it can potentially be repositioned during scheduling.
7089 and an instruction that eventually uses the PIC register may end up
7090 between the call and the PIC register restore.
7092 This only worked because there is a post call group of instructions
7093 that are scheduled with the call. These instructions are included
7094 in the same basic block as the call. However, calls can throw in
7095 C++ code and a basic block has to terminate at the call if the call
7096 can throw. This results in the PIC register restore being scheduled
7097 independently from the call. So, we now hide the save and restore
7098 of the PIC register in the call pattern until after reload. Then,
7099 we split the moves out. A small side benefit is that we now don't
7100 need to have a use of the PIC register in the return pattern and
7101 the final save/restore operation is not needed.
7103 I elected to just use register %r4 in the PIC patterns instead
7104 of trying to force hppa_pic_save_rtx () to a callee saved register.
7105 This might have required a new register class and constraint. It
7106 was also simpler to just handle the restore from a register than a
7110 rtx r4 = gen_rtx_REG (word_mode, 4);
7111 if (GET_CODE (op) == SYMBOL_REF)
7112 emit_call_insn (gen_call_symref_64bit (op, nb, r4));
7115 op = force_reg (word_mode, op);
7116 emit_call_insn (gen_call_reg_64bit (op, nb, r4));
7121 if (GET_CODE (op) == SYMBOL_REF)
7125 rtx r4 = gen_rtx_REG (word_mode, 4);
7126 emit_call_insn (gen_call_symref_pic (op, nb, r4));
7129 emit_call_insn (gen_call_symref (op, nb));
7133 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7134 emit_move_insn (tmpreg, force_reg (word_mode, op));
7137 rtx r4 = gen_rtx_REG (word_mode, 4);
7138 emit_call_insn (gen_call_reg_pic (nb, r4));
7141 emit_call_insn (gen_call_reg (nb));
7148 ;; We use function calls to set the attribute length of calls and millicode
7149 ;; calls. This is necessary because of the large variety of call sequences.
7150 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7151 ;; we need the same calculation in several places, maintenance becomes a
7154 ;; However, this has a subtle impact on branch shortening. When the
7155 ;; expression used to set the length attribute of an instruction depends
7156 ;; on a relative address (e.g., pc or a branch address), genattrtab
7157 ;; notes that the insn's length is variable, and attempts to determine a
7158 ;; worst-case default length and code to compute an insn's current length.
7160 ;; The use of a function call hides the variable dependence of our calls
7161 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7162 ;; as variable and it only generates code for the default case using our
7163 ;; function call. Because of this, calls and millicode calls have a fixed
7164 ;; length in the branch shortening pass, and some branches will use a longer
7165 ;; code sequence than necessary. However, the length of any given call
7166 ;; will still reflect its final code location and it may be shorter than
7167 ;; the initial length estimate.
7169 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7170 ;; in the set. However, when genattrtab hits a function call in its attempt
7171 ;; to compute the default length, it marks the result as unknown and sets
7172 ;; the default result to MAX_INT ;-( One possible fix that would allow
7173 ;; calls to participate in branch shortening would be to make the call to
7174 ;; insn_default_length a target option. Then, we could massage unknown
7175 ;; results. Another fix might be to change genattrtab so that it just does
7176 ;; the call in the variable case as it already does for the fixed case.
7178 (define_insn "call_symref"
7179 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7180 (match_operand 1 "" "i"))
7181 (clobber (reg:SI 1))
7182 (clobber (reg:SI 2))
7183 (use (const_int 0))]
7184 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7187 pa_output_arg_descriptor (insn);
7188 return pa_output_call (insn, operands[0], 0);
7190 [(set_attr "type" "call")
7191 (set (attr "length")
7192 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7193 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7195 (define_insn "call_symref_pic"
7196 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7197 (match_operand 1 "" "i"))
7198 (clobber (reg:SI 1))
7199 (clobber (reg:SI 2))
7200 (clobber (match_operand 2))
7202 (use (const_int 0))]
7203 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7206 ;; Split out the PIC register save and restore after reload. As the
7207 ;; split is done after reload, there are some situations in which we
7208 ;; unnecessarily save and restore %r4. This happens when there is a
7209 ;; single call and the PIC register is not used after the call.
7211 ;; The split has to be done since call_from_call_insn () can't handle
7212 ;; the pattern as is. Noreturn calls are special because they have to
7213 ;; terminate the basic block. The split has to contain more than one
7216 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7217 (match_operand 1 "" ""))
7218 (clobber (reg:SI 1))
7219 (clobber (reg:SI 2))
7220 (clobber (match_operand 2))
7222 (use (const_int 0))])]
7223 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7224 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7225 [(set (match_dup 2) (reg:SI 19))
7226 (parallel [(call (mem:SI (match_dup 0))
7228 (clobber (reg:SI 1))
7229 (clobber (reg:SI 2))
7231 (use (const_int 0))])]
7235 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7236 (match_operand 1 "" ""))
7237 (clobber (reg:SI 1))
7238 (clobber (reg:SI 2))
7239 (clobber (match_operand 2))
7241 (use (const_int 0))])]
7242 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7243 [(set (match_dup 2) (reg:SI 19))
7244 (parallel [(call (mem:SI (match_dup 0))
7246 (clobber (reg:SI 1))
7247 (clobber (reg:SI 2))
7249 (use (const_int 0))])
7250 (set (reg:SI 19) (match_dup 2))]
7253 (define_insn "*call_symref_pic_post_reload"
7254 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7255 (match_operand 1 "" "i"))
7256 (clobber (reg:SI 1))
7257 (clobber (reg:SI 2))
7259 (use (const_int 0))]
7260 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7263 pa_output_arg_descriptor (insn);
7264 return pa_output_call (insn, operands[0], 0);
7266 [(set_attr "type" "call")
7267 (set (attr "length")
7268 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7269 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7271 ;; This pattern is split if it is necessary to save and restore the
7273 (define_insn "call_symref_64bit"
7274 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7275 (match_operand 1 "" "i"))
7276 (clobber (reg:DI 1))
7277 (clobber (reg:DI 2))
7278 (clobber (match_operand 2))
7281 (use (const_int 0))]
7285 ;; Split out the PIC register save and restore after reload. As the
7286 ;; split is done after reload, there are some situations in which we
7287 ;; unnecessarily save and restore %r4. This happens when there is a
7288 ;; single call and the PIC register is not used after the call.
7290 ;; The split has to be done since call_from_call_insn () can't handle
7291 ;; the pattern as is. Noreturn calls are special because they have to
7292 ;; terminate the basic block. The split has to contain more than one
7295 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7296 (match_operand 1 "" ""))
7297 (clobber (reg:DI 1))
7298 (clobber (reg:DI 2))
7299 (clobber (match_operand 2))
7302 (use (const_int 0))])]
7303 "TARGET_64BIT && reload_completed
7304 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7305 [(set (match_dup 2) (reg:DI 27))
7306 (parallel [(call (mem:SI (match_dup 0))
7308 (clobber (reg:DI 1))
7309 (clobber (reg:DI 2))
7312 (use (const_int 0))])]
7316 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7317 (match_operand 1 "" ""))
7318 (clobber (reg:DI 1))
7319 (clobber (reg:DI 2))
7320 (clobber (match_operand 2))
7323 (use (const_int 0))])]
7324 "TARGET_64BIT && reload_completed"
7325 [(set (match_dup 2) (reg:DI 27))
7326 (parallel [(call (mem:SI (match_dup 0))
7328 (clobber (reg:DI 1))
7329 (clobber (reg:DI 2))
7332 (use (const_int 0))])
7333 (set (reg:DI 27) (match_dup 2))]
7336 (define_insn "*call_symref_64bit_post_reload"
7337 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7338 (match_operand 1 "" "i"))
7339 (clobber (reg:DI 1))
7340 (clobber (reg:DI 2))
7343 (use (const_int 0))]
7347 return pa_output_call (insn, operands[0], 0);
7349 [(set_attr "type" "call")
7350 (set (attr "length")
7351 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7352 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7354 (define_insn "call_reg"
7355 [(call (mem:SI (reg:SI 22))
7356 (match_operand 0 "" "i"))
7357 (clobber (reg:SI 1))
7358 (clobber (reg:SI 2))
7359 (use (const_int 1))]
7363 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7365 [(set_attr "type" "dyncall")
7366 (set (attr "length")
7367 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7368 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7370 ;; This pattern is split if it is necessary to save and restore the
7372 (define_insn "call_reg_pic"
7373 [(call (mem:SI (reg:SI 22))
7374 (match_operand 0 "" "i"))
7375 (clobber (reg:SI 1))
7376 (clobber (reg:SI 2))
7377 (clobber (match_operand 1))
7379 (use (const_int 1))]
7383 ;; Split out the PIC register save and restore after reload. As the
7384 ;; split is done after reload, there are some situations in which we
7385 ;; unnecessarily save and restore %r4. This happens when there is a
7386 ;; single call and the PIC register is not used after the call.
7388 ;; The split has to be done since call_from_call_insn () can't handle
7389 ;; the pattern as is. Noreturn calls are special because they have to
7390 ;; terminate the basic block. The split has to contain more than one
7393 [(parallel [(call (mem:SI (reg:SI 22))
7394 (match_operand 0 "" ""))
7395 (clobber (reg:SI 1))
7396 (clobber (reg:SI 2))
7397 (clobber (match_operand 1))
7399 (use (const_int 1))])]
7400 "!TARGET_64BIT && reload_completed
7401 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7402 [(set (match_dup 1) (reg:SI 19))
7403 (parallel [(call (mem:SI (reg:SI 22))
7405 (clobber (reg:SI 1))
7406 (clobber (reg:SI 2))
7408 (use (const_int 1))])]
7412 [(parallel [(call (mem:SI (reg:SI 22))
7413 (match_operand 0 "" ""))
7414 (clobber (reg:SI 1))
7415 (clobber (reg:SI 2))
7416 (clobber (match_operand 1))
7418 (use (const_int 1))])]
7419 "!TARGET_64BIT && reload_completed"
7420 [(set (match_dup 1) (reg:SI 19))
7421 (parallel [(call (mem:SI (reg:SI 22))
7423 (clobber (reg:SI 1))
7424 (clobber (reg:SI 2))
7426 (use (const_int 1))])
7427 (set (reg:SI 19) (match_dup 1))]
7430 (define_insn "*call_reg_pic_post_reload"
7431 [(call (mem:SI (reg:SI 22))
7432 (match_operand 0 "" "i"))
7433 (clobber (reg:SI 1))
7434 (clobber (reg:SI 2))
7436 (use (const_int 1))]
7440 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7442 [(set_attr "type" "dyncall")
7443 (set (attr "length")
7444 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7445 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7447 ;; This pattern is split if it is necessary to save and restore the
7449 (define_insn "call_reg_64bit"
7450 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7451 (match_operand 1 "" "i"))
7452 (clobber (reg:DI 2))
7453 (clobber (match_operand 2))
7456 (use (const_int 1))]
7460 ;; Split out the PIC register save and restore after reload. As the
7461 ;; split is done after reload, there are some situations in which we
7462 ;; unnecessarily save and restore %r4. This happens when there is a
7463 ;; single call and the PIC register is not used after the call.
7465 ;; The split has to be done since call_from_call_insn () can't handle
7466 ;; the pattern as is. Noreturn calls are special because they have to
7467 ;; terminate the basic block. The split has to contain more than one
7470 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7471 (match_operand 1 "" ""))
7472 (clobber (reg:DI 2))
7473 (clobber (match_operand 2))
7476 (use (const_int 1))])]
7477 "TARGET_64BIT && reload_completed
7478 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7479 [(set (match_dup 2) (reg:DI 27))
7480 (parallel [(call (mem:SI (match_dup 0))
7482 (clobber (reg:DI 2))
7485 (use (const_int 1))])]
7489 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7490 (match_operand 1 "" ""))
7491 (clobber (reg:DI 2))
7492 (clobber (match_operand 2))
7495 (use (const_int 1))])]
7496 "TARGET_64BIT && reload_completed"
7497 [(set (match_dup 2) (reg:DI 27))
7498 (parallel [(call (mem:SI (match_dup 0))
7500 (clobber (reg:DI 2))
7503 (use (const_int 1))])
7504 (set (reg:DI 27) (match_dup 2))]
7507 (define_insn "*call_reg_64bit_post_reload"
7508 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7509 (match_operand 1 "" "i"))
7510 (clobber (reg:DI 2))
7513 (use (const_int 1))]
7517 return pa_output_indirect_call (insn, operands[0]);
7519 [(set_attr "type" "dyncall")
7520 (set (attr "length")
7521 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 12)]
7522 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
7524 (define_expand "call_value"
7525 [(parallel [(set (match_operand 0 "" "")
7526 (call (match_operand:SI 1 "" "")
7527 (match_operand 2 "" "")))
7528 (clobber (reg:SI 2))])]
7532 rtx dst = operands[0];
7533 rtx nb = operands[2];
7534 bool call_powf = false;
7536 if (TARGET_PORTABLE_RUNTIME)
7537 op = force_reg (SImode, XEXP (operands[1], 0));
7540 op = XEXP (operands[1], 0);
7541 if (GET_CODE (op) == SYMBOL_REF)
7543 /* Handle special call to buggy powf function. */
7544 if (TARGET_HPUX && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT
7545 && !strcmp (targetm.strip_name_encoding (XSTR (op, 0)), "powf"))
7548 /* Generate indirect long calls to non-local functions. */
7549 else if (TARGET_LONG_CALLS)
7551 tree call_decl = SYMBOL_REF_DECL (op);
7552 if (!(call_decl && targetm.binds_local_p (call_decl)))
7553 op = force_reg (word_mode, op);
7560 if (!virtuals_instantiated)
7561 emit_move_insn (arg_pointer_rtx,
7562 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7566 /* The loop pass can generate new libcalls after the virtual
7567 registers are instantiated when fpregs are disabled because
7568 the only method that we have for doing DImode multiplication
7569 is with a libcall. This could be trouble if we haven't
7570 allocated enough space for the outgoing arguments. */
7571 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7573 emit_move_insn (arg_pointer_rtx,
7574 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7575 GEN_INT (STACK_POINTER_OFFSET + 64)));
7579 /* Use two different patterns for calls to explicitly named functions
7580 and calls through function pointers. This is necessary as these two
7581 types of calls use different calling conventions, and CSE might try
7582 to change the named call into an indirect call in some cases (using
7583 two patterns keeps CSE from performing this optimization).
7585 We now use even more call patterns as there was a subtle bug in
7586 attempting to restore the pic register after a call using a simple
7587 move insn. During reload, a instruction involving a pseudo register
7588 with no explicit dependence on the PIC register can be converted
7589 to an equivalent load from memory using the PIC register. If we
7590 emit a simple move to restore the PIC register in the initial rtl
7591 generation, then it can potentially be repositioned during scheduling.
7592 and an instruction that eventually uses the PIC register may end up
7593 between the call and the PIC register restore.
7595 This only worked because there is a post call group of instructions
7596 that are scheduled with the call. These instructions are included
7597 in the same basic block as the call. However, calls can throw in
7598 C++ code and a basic block has to terminate at the call if the call
7599 can throw. This results in the PIC register restore being scheduled
7600 independently from the call. So, we now hide the save and restore
7601 of the PIC register in the call pattern until after reload. Then,
7602 we split the moves out. A small side benefit is that we now don't
7603 need to have a use of the PIC register in the return pattern and
7604 the final save/restore operation is not needed.
7606 I elected to just use register %r4 in the PIC patterns instead
7607 of trying to force hppa_pic_save_rtx () to a callee saved register.
7608 This might have required a new register class and constraint. It
7609 was also simpler to just handle the restore from a register than a
7613 rtx r4 = gen_rtx_REG (word_mode, 4);
7614 if (GET_CODE (op) == SYMBOL_REF)
7617 emit_call_insn (gen_call_val_powf_64bit (dst, op, nb, r4));
7619 emit_call_insn (gen_call_val_symref_64bit (dst, op, nb, r4));
7623 op = force_reg (word_mode, op);
7624 emit_call_insn (gen_call_val_reg_64bit (dst, op, nb, r4));
7629 if (GET_CODE (op) == SYMBOL_REF)
7633 rtx r4 = gen_rtx_REG (word_mode, 4);
7636 emit_call_insn (gen_call_val_powf_pic (dst, op, nb, r4));
7638 emit_call_insn (gen_call_val_symref_pic (dst, op, nb, r4));
7643 emit_call_insn (gen_call_val_powf (dst, op, nb));
7645 emit_call_insn (gen_call_val_symref (dst, op, nb));
7650 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7651 emit_move_insn (tmpreg, force_reg (word_mode, op));
7654 rtx r4 = gen_rtx_REG (word_mode, 4);
7655 emit_call_insn (gen_call_val_reg_pic (dst, nb, r4));
7658 emit_call_insn (gen_call_val_reg (dst, nb));
7665 (define_insn "call_val_symref"
7666 [(set (match_operand 0 "" "")
7667 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7668 (match_operand 2 "" "i")))
7669 (clobber (reg:SI 1))
7670 (clobber (reg:SI 2))
7671 (use (const_int 0))]
7672 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7675 pa_output_arg_descriptor (insn);
7676 return pa_output_call (insn, operands[1], 0);
7678 [(set_attr "type" "call")
7679 (set (attr "length")
7680 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7681 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7683 ;; powf function clobbers %fr12
7684 (define_insn "call_val_powf"
7685 [(set (match_operand 0 "" "")
7686 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7687 (match_operand 2 "" "i")))
7688 (clobber (reg:SI 1))
7689 (clobber (reg:SI 2))
7690 (clobber (reg:DF 48))
7691 (use (const_int 1))]
7692 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7695 pa_output_arg_descriptor (insn);
7696 return pa_output_call (insn, operands[1], 0);
7698 [(set_attr "type" "call")
7699 (set (attr "length")
7700 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7701 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7703 (define_insn "call_val_symref_pic"
7704 [(set (match_operand 0 "" "")
7705 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7706 (match_operand 2 "" "i")))
7707 (clobber (reg:SI 1))
7708 (clobber (reg:SI 2))
7709 (clobber (match_operand 3))
7711 (use (const_int 0))]
7712 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7715 ;; Split out the PIC register save and restore after reload. As the
7716 ;; split is done after reload, there are some situations in which we
7717 ;; unnecessarily save and restore %r4. This happens when there is a
7718 ;; single call and the PIC register is not used after the call.
7720 ;; The split has to be done since call_from_call_insn () can't handle
7721 ;; the pattern as is. Noreturn calls are special because they have to
7722 ;; terminate the basic block. The split has to contain more than one
7725 [(parallel [(set (match_operand 0 "" "")
7726 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7727 (match_operand 2 "" "")))
7728 (clobber (reg:SI 1))
7729 (clobber (reg:SI 2))
7730 (clobber (match_operand 3))
7732 (use (const_int 0))])]
7733 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7734 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7735 [(set (match_dup 3) (reg:SI 19))
7736 (parallel [(set (match_dup 0)
7737 (call (mem:SI (match_dup 1))
7739 (clobber (reg:SI 1))
7740 (clobber (reg:SI 2))
7742 (use (const_int 0))])]
7746 [(parallel [(set (match_operand 0 "" "")
7747 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7748 (match_operand 2 "" "")))
7749 (clobber (reg:SI 1))
7750 (clobber (reg:SI 2))
7751 (clobber (match_operand 3))
7753 (use (const_int 0))])]
7754 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7755 [(set (match_dup 3) (reg:SI 19))
7756 (parallel [(set (match_dup 0)
7757 (call (mem:SI (match_dup 1))
7759 (clobber (reg:SI 1))
7760 (clobber (reg:SI 2))
7762 (use (const_int 0))])
7763 (set (reg:SI 19) (match_dup 3))]
7766 (define_insn "*call_val_symref_pic_post_reload"
7767 [(set (match_operand 0 "" "")
7768 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7769 (match_operand 2 "" "i")))
7770 (clobber (reg:SI 1))
7771 (clobber (reg:SI 2))
7773 (use (const_int 0))]
7774 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7777 pa_output_arg_descriptor (insn);
7778 return pa_output_call (insn, operands[1], 0);
7780 [(set_attr "type" "call")
7781 (set (attr "length")
7782 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7783 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7785 ;; powf function clobbers %fr12
7786 (define_insn "call_val_powf_pic"
7787 [(set (match_operand 0 "" "")
7788 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7789 (match_operand 2 "" "i")))
7790 (clobber (reg:SI 1))
7791 (clobber (reg:SI 2))
7792 (clobber (reg:DF 48))
7793 (clobber (match_operand 3))
7795 (use (const_int 1))]
7796 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7799 ;; Split out the PIC register save and restore after reload. As the
7800 ;; split is done after reload, there are some situations in which we
7801 ;; unnecessarily save and restore %r4. This happens when there is a
7802 ;; single call and the PIC register is not used after the call.
7804 ;; The split has to be done since call_from_call_insn () can't handle
7805 ;; the pattern as is. Noreturn calls are special because they have to
7806 ;; terminate the basic block. The split has to contain more than one
7809 [(parallel [(set (match_operand 0 "" "")
7810 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7811 (match_operand 2 "" "")))
7812 (clobber (reg:SI 1))
7813 (clobber (reg:SI 2))
7814 (clobber (reg:DF 48))
7815 (clobber (match_operand 3))
7817 (use (const_int 1))])]
7818 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7819 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7820 [(set (match_dup 3) (reg:SI 19))
7821 (parallel [(set (match_dup 0)
7822 (call (mem:SI (match_dup 1))
7824 (clobber (reg:SI 1))
7825 (clobber (reg:SI 2))
7826 (clobber (reg:DF 48))
7828 (use (const_int 1))])]
7832 [(parallel [(set (match_operand 0 "" "")
7833 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7834 (match_operand 2 "" "")))
7835 (clobber (reg:SI 1))
7836 (clobber (reg:SI 2))
7837 (clobber (reg:DF 48))
7838 (clobber (match_operand 3))
7840 (use (const_int 1))])]
7841 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7842 [(set (match_dup 3) (reg:SI 19))
7843 (parallel [(set (match_dup 0)
7844 (call (mem:SI (match_dup 1))
7846 (clobber (reg:SI 1))
7847 (clobber (reg:SI 2))
7848 (clobber (reg:DF 48))
7850 (use (const_int 1))])
7851 (set (reg:SI 19) (match_dup 3))]
7854 (define_insn "*call_val_powf_pic_post_reload"
7855 [(set (match_operand 0 "" "")
7856 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7857 (match_operand 2 "" "i")))
7858 (clobber (reg:SI 1))
7859 (clobber (reg:SI 2))
7860 (clobber (reg:DF 48))
7862 (use (const_int 1))]
7863 "TARGET_HPUX && !TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7866 pa_output_arg_descriptor (insn);
7867 return pa_output_call (insn, operands[1], 0);
7869 [(set_attr "type" "call")
7870 (set (attr "length")
7871 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7872 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7874 ;; This pattern is split if it is necessary to save and restore the
7876 (define_insn "call_val_symref_64bit"
7877 [(set (match_operand 0 "" "")
7878 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7879 (match_operand 2 "" "i")))
7880 (clobber (reg:DI 1))
7881 (clobber (reg:DI 2))
7882 (clobber (match_operand 3))
7885 (use (const_int 0))]
7889 ;; Split out the PIC register save and restore after reload. As the
7890 ;; split is done after reload, there are some situations in which we
7891 ;; unnecessarily save and restore %r4. This happens when there is a
7892 ;; single call and the PIC register is not used after the call.
7894 ;; The split has to be done since call_from_call_insn () can't handle
7895 ;; the pattern as is. Noreturn calls are special because they have to
7896 ;; terminate the basic block. The split has to contain more than one
7899 [(parallel [(set (match_operand 0 "" "")
7900 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7901 (match_operand 2 "" "")))
7902 (clobber (reg:DI 1))
7903 (clobber (reg:DI 2))
7904 (clobber (match_operand 3))
7907 (use (const_int 0))])]
7908 "TARGET_64BIT && reload_completed
7909 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7910 [(set (match_dup 3) (reg:DI 27))
7911 (parallel [(set (match_dup 0)
7912 (call (mem:SI (match_dup 1))
7914 (clobber (reg:DI 1))
7915 (clobber (reg:DI 2))
7918 (use (const_int 0))])]
7922 [(parallel [(set (match_operand 0 "" "")
7923 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7924 (match_operand 2 "" "")))
7925 (clobber (reg:DI 1))
7926 (clobber (reg:DI 2))
7927 (clobber (match_operand 3))
7930 (use (const_int 0))])]
7931 "TARGET_64BIT && reload_completed"
7932 [(set (match_dup 3) (reg:DI 27))
7933 (parallel [(set (match_dup 0)
7934 (call (mem:SI (match_dup 1))
7936 (clobber (reg:DI 1))
7937 (clobber (reg:DI 2))
7940 (use (const_int 0))])
7941 (set (reg:DI 27) (match_dup 3))]
7944 (define_insn "*call_val_symref_64bit_post_reload"
7945 [(set (match_operand 0 "" "")
7946 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7947 (match_operand 2 "" "i")))
7948 (clobber (reg:DI 1))
7949 (clobber (reg:DI 2))
7952 (use (const_int 0))]
7956 return pa_output_call (insn, operands[1], 0);
7958 [(set_attr "type" "call")
7959 (set (attr "length")
7960 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
7961 (symbol_ref "pa_attr_length_call (insn, 0)")))])
7963 ;; powf function clobbers %fr12
7964 (define_insn "call_val_powf_64bit"
7965 [(set (match_operand 0 "" "")
7966 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7967 (match_operand 2 "" "i")))
7968 (clobber (reg:DI 1))
7969 (clobber (reg:DI 2))
7970 (clobber (reg:DF 40))
7971 (clobber (match_operand 3))
7974 (use (const_int 1))]
7975 "TARGET_64BIT && TARGET_HPUX"
7978 ;; Split out the PIC register save and restore after reload. As the
7979 ;; split is done after reload, there are some situations in which we
7980 ;; unnecessarily save and restore %r4. This happens when there is a
7981 ;; single call and the PIC register is not used after the call.
7983 ;; The split has to be done since call_from_call_insn () can't handle
7984 ;; the pattern as is. Noreturn calls are special because they have to
7985 ;; terminate the basic block. The split has to contain more than one
7988 [(parallel [(set (match_operand 0 "" "")
7989 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7990 (match_operand 2 "" "")))
7991 (clobber (reg:DI 1))
7992 (clobber (reg:DI 2))
7993 (clobber (reg:DF 40))
7994 (clobber (match_operand 3))
7997 (use (const_int 1))])]
7998 "TARGET_64BIT && TARGET_HPUX && reload_completed
7999 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8000 [(set (match_dup 3) (reg:DI 27))
8001 (parallel [(set (match_dup 0)
8002 (call (mem:SI (match_dup 1))
8004 (clobber (reg:DI 1))
8005 (clobber (reg:DI 2))
8006 (clobber (reg:DF 40))
8009 (use (const_int 1))])]
8013 [(parallel [(set (match_operand 0 "" "")
8014 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8015 (match_operand 2 "" "")))
8016 (clobber (reg:DI 1))
8017 (clobber (reg:DI 2))
8018 (clobber (reg:DF 40))
8019 (clobber (match_operand 3))
8022 (use (const_int 1))])]
8023 "TARGET_64BIT && TARGET_HPUX && reload_completed"
8024 [(set (match_dup 3) (reg:DI 27))
8025 (parallel [(set (match_dup 0)
8026 (call (mem:SI (match_dup 1))
8028 (clobber (reg:DI 1))
8029 (clobber (reg:DI 2))
8030 (clobber (reg:DF 40))
8033 (use (const_int 1))])
8034 (set (reg:DI 27) (match_dup 3))]
8037 (define_insn "*call_val_powf_64bit_post_reload"
8038 [(set (match_operand 0 "" "")
8039 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8040 (match_operand 2 "" "i")))
8041 (clobber (reg:DI 1))
8042 (clobber (reg:DI 2))
8043 (clobber (reg:DF 40))
8046 (use (const_int 1))]
8047 "TARGET_64BIT && TARGET_HPUX"
8050 return pa_output_call (insn, operands[1], 0);
8052 [(set_attr "type" "call")
8053 (set (attr "length")
8054 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8055 (symbol_ref "pa_attr_length_call (insn, 0)")))])
8057 (define_insn "call_val_reg"
8058 [(set (match_operand 0 "" "")
8059 (call (mem:SI (reg:SI 22))
8060 (match_operand 1 "" "i")))
8061 (clobber (reg:SI 1))
8062 (clobber (reg:SI 2))
8063 (use (const_int 1))]
8067 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8069 [(set_attr "type" "dyncall")
8070 (set (attr "length")
8071 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8072 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8074 ;; This pattern is split if it is necessary to save and restore the
8076 (define_insn "call_val_reg_pic"
8077 [(set (match_operand 0 "" "")
8078 (call (mem:SI (reg:SI 22))
8079 (match_operand 1 "" "i")))
8080 (clobber (reg:SI 1))
8081 (clobber (reg:SI 2))
8082 (clobber (match_operand 2))
8084 (use (const_int 1))]
8088 ;; Split out the PIC register save and restore after reload. As the
8089 ;; split is done after reload, there are some situations in which we
8090 ;; unnecessarily save and restore %r4. This happens when there is a
8091 ;; single call and the PIC register is not used after the call.
8093 ;; The split has to be done since call_from_call_insn () can't handle
8094 ;; the pattern as is. Noreturn calls are special because they have to
8095 ;; terminate the basic block. The split has to contain more than one
8098 [(parallel [(set (match_operand 0 "" "")
8099 (call (mem:SI (reg:SI 22))
8100 (match_operand 1 "" "")))
8101 (clobber (reg:SI 1))
8102 (clobber (reg:SI 2))
8103 (clobber (match_operand 2))
8105 (use (const_int 1))])]
8106 "!TARGET_64BIT && reload_completed
8107 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8108 [(set (match_dup 2) (reg:SI 19))
8109 (parallel [(set (match_dup 0)
8110 (call (mem:SI (reg:SI 22))
8112 (clobber (reg:SI 1))
8113 (clobber (reg:SI 2))
8115 (use (const_int 1))])]
8119 [(parallel [(set (match_operand 0 "" "")
8120 (call (mem:SI (reg:SI 22))
8121 (match_operand 1 "" "")))
8122 (clobber (reg:SI 1))
8123 (clobber (reg:SI 2))
8124 (clobber (match_operand 2))
8126 (use (const_int 1))])]
8127 "!TARGET_64BIT && reload_completed"
8128 [(set (match_dup 2) (reg:SI 19))
8129 (parallel [(set (match_dup 0)
8130 (call (mem:SI (reg:SI 22))
8132 (clobber (reg:SI 1))
8133 (clobber (reg:SI 2))
8135 (use (const_int 1))])
8136 (set (reg:SI 19) (match_dup 2))]
8139 (define_insn "*call_val_reg_pic_post_reload"
8140 [(set (match_operand 0 "" "")
8141 (call (mem:SI (reg:SI 22))
8142 (match_operand 1 "" "i")))
8143 (clobber (reg:SI 1))
8144 (clobber (reg:SI 2))
8146 (use (const_int 1))]
8150 return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8152 [(set_attr "type" "dyncall")
8153 (set (attr "length")
8154 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8155 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8157 ;; This pattern is split if it is necessary to save and restore the
8159 (define_insn "call_val_reg_64bit"
8160 [(set (match_operand 0 "" "")
8161 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8162 (match_operand 2 "" "i")))
8163 (clobber (reg:DI 2))
8164 (clobber (match_operand 3))
8167 (use (const_int 1))]
8171 ;; Split out the PIC register save and restore after reload. As the
8172 ;; split is done after reload, there are some situations in which we
8173 ;; unnecessarily save and restore %r4. This happens when there is a
8174 ;; single call and the PIC register is not used after the call.
8176 ;; The split has to be done since call_from_call_insn () can't handle
8177 ;; the pattern as is. Noreturn calls are special because they have to
8178 ;; terminate the basic block. The split has to contain more than one
8181 [(parallel [(set (match_operand 0 "" "")
8182 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8183 (match_operand 2 "" "")))
8184 (clobber (reg:DI 2))
8185 (clobber (match_operand 3))
8188 (use (const_int 1))])]
8189 "TARGET_64BIT && reload_completed
8190 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8191 [(set (match_dup 3) (reg:DI 27))
8192 (parallel [(set (match_dup 0)
8193 (call (mem:SI (match_dup 1))
8195 (clobber (reg:DI 2))
8198 (use (const_int 1))])]
8202 [(parallel [(set (match_operand 0 "" "")
8203 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8204 (match_operand 2 "" "")))
8205 (clobber (reg:DI 2))
8206 (clobber (match_operand 3))
8209 (use (const_int 1))])]
8210 "TARGET_64BIT && reload_completed"
8211 [(set (match_dup 3) (reg:DI 27))
8212 (parallel [(set (match_dup 0)
8213 (call (mem:SI (match_dup 1))
8215 (clobber (reg:DI 2))
8218 (use (const_int 1))])
8219 (set (reg:DI 27) (match_dup 3))]
8222 (define_insn "*call_val_reg_64bit_post_reload"
8223 [(set (match_operand 0 "" "")
8224 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8225 (match_operand 2 "" "i")))
8226 (clobber (reg:DI 2))
8229 (use (const_int 1))]
8233 return pa_output_indirect_call (insn, operands[1]);
8235 [(set_attr "type" "dyncall")
8236 (set (attr "length")
8237 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 12)]
8238 (symbol_ref "pa_attr_length_indirect_call (insn)")))])
8240 /* Expand special pc-relative call to _mcount. */
8242 (define_expand "call_mcount"
8243 [(parallel [(call (match_operand:SI 0 "" "")
8244 (match_operand 1 "" ""))
8247 (minus:SI (match_operand 2 "" "")
8248 (plus:SI (pc) (const_int 4)))))
8249 (clobber (reg:SI 2))])]
8250 "!TARGET_PORTABLE_RUNTIME"
8253 rtx op = XEXP (operands[0], 0);
8254 rtx nb = operands[1];
8255 rtx lab = operands[2];
8259 rtx r4 = gen_rtx_REG (word_mode, 4);
8260 emit_move_insn (arg_pointer_rtx,
8261 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8263 emit_call_insn (gen_call_mcount_64bit (op, nb, lab, r4));
8269 rtx r4 = gen_rtx_REG (word_mode, 4);
8270 emit_call_insn (gen_call_mcount_pic (op, nb, lab, r4));
8273 emit_call_insn (gen_call_mcount_nonpic (op, nb, lab));
8279 (define_insn "call_mcount_nonpic"
8280 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8281 (match_operand 1 "" "i"))
8284 (minus:SI (match_operand 2 "" "")
8285 (plus:SI (pc) (const_int 4)))))
8286 (clobber (reg:SI 2))]
8287 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8290 pa_output_arg_descriptor (insn);
8291 return \"{bl|b,l} %0,%%r2\;ldo %2-.-4(%%r2),%%r25\";
8293 [(set_attr "type" "multi")
8294 (set_attr "length" "8")])
8296 (define_insn "call_mcount_pic"
8297 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8298 (match_operand 1 "" "i"))
8301 (minus:SI (match_operand 2 "" "")
8302 (plus:SI (pc) (const_int 4)))))
8303 (clobber (reg:SI 2))
8304 (clobber (match_operand 3))
8306 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8310 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8311 (match_operand 1 "" ""))
8314 (minus:SI (match_operand 2 "" "")
8315 (plus:SI (pc) (const_int 4)))))
8316 (clobber (reg:SI 2))
8317 (clobber (match_operand 3))
8318 (use (reg:SI 19))])]
8319 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8320 [(set (match_dup 3) (reg:SI 19))
8321 (parallel [(call (mem:SI (match_dup 0))
8325 (minus:SI (match_dup 2)
8326 (plus:SI (pc) (const_int 4)))))
8327 (clobber (reg:SI 2))
8329 (set (reg:SI 19) (match_dup 3))]
8332 (define_insn "*call_mcount_pic_post_reload"
8333 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8334 (match_operand 1 "" "i"))
8337 (minus:SI (match_operand 2 "" "")
8338 (plus:SI (pc) (const_int 4)))))
8339 (clobber (reg:SI 2))
8341 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8344 pa_output_arg_descriptor (insn);
8345 return \"{bl|b,l} %0,%%r2\;ldo %2-.-4(%%r2),%%r25\";
8347 [(set_attr "type" "multi")
8348 (set_attr "length" "8")])
8350 (define_insn "call_mcount_64bit"
8351 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8352 (match_operand 1 "" "i"))
8355 (minus:SI (match_operand 2 "" "")
8356 (plus:SI (pc) (const_int 4)))))
8357 (clobber (reg:DI 2))
8358 (clobber (match_operand 3))
8365 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8366 (match_operand 1 "" ""))
8369 (minus:SI (match_operand 2 "" "")
8370 (plus:SI (pc) (const_int 4)))))
8371 (clobber (reg:DI 2))
8372 (clobber (match_operand 3))
8374 (use (reg:DI 29))])]
8375 "TARGET_64BIT && reload_completed"
8376 [(set (match_dup 3) (reg:DI 27))
8377 (parallel [(call (mem:SI (match_dup 0))
8381 (minus:SI (match_dup 2)
8382 (plus:SI (pc) (const_int 4)))))
8383 (clobber (reg:DI 2))
8386 (set (reg:DI 27) (match_dup 3))]
8389 (define_insn "*call_mcount_64bit_post_reload"
8390 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8391 (match_operand 1 "" "i"))
8394 (minus:SI (match_operand 2 "" "")
8395 (plus:SI (pc) (const_int 4)))))
8396 (clobber (reg:DI 2))
8400 "{bl|b,l} %0,%%r2\;ldo %2-.-4(%%r2),%%r25"
8401 [(set_attr "type" "multi")
8402 (set_attr "length" "8")])
8404 ;; Call subroutine returning any type.
8406 (define_expand "untyped_call"
8407 [(parallel [(call (match_operand 0 "" "")
8409 (match_operand 1 "" "")
8410 (match_operand 2 "" "")])]
8416 emit_call_insn (gen_call (operands[0], const0_rtx));
8418 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8420 rtx set = XVECEXP (operands[2], 0, i);
8421 emit_move_insn (SET_DEST (set), SET_SRC (set));
8424 /* The optimizer does not know that the call sets the function value
8425 registers we stored in the result block. We avoid problems by
8426 claiming that all hard registers are used and clobbered at this
8428 emit_insn (gen_blockage ());
8433 (define_expand "sibcall"
8434 [(call (match_operand:SI 0 "" "")
8435 (match_operand 1 "" ""))]
8436 "!TARGET_PORTABLE_RUNTIME"
8440 rtx nb = operands[1];
8442 op = XEXP (operands[0], 0);
8446 if (!virtuals_instantiated)
8447 emit_move_insn (arg_pointer_rtx,
8448 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8452 /* The loop pass can generate new libcalls after the virtual
8453 registers are instantiated when fpregs are disabled because
8454 the only method that we have for doing DImode multiplication
8455 is with a libcall. This could be trouble if we haven't
8456 allocated enough space for the outgoing arguments. */
8457 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8459 emit_move_insn (arg_pointer_rtx,
8460 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8461 GEN_INT (STACK_POINTER_OFFSET + 64)));
8465 /* Indirect sibling calls are not allowed. */
8467 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8469 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8471 call_insn = emit_call_insn (call_insn);
8474 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8476 /* We don't have to restore the PIC register. */
8478 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8483 (define_insn "sibcall_internal_symref"
8484 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8485 (match_operand 1 "" "i"))
8486 (clobber (reg:SI 1))
8488 (use (const_int 0))]
8489 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8492 pa_output_arg_descriptor (insn);
8493 return pa_output_call (insn, operands[0], 1);
8495 [(set_attr "type" "sibcall")
8496 (set (attr "length")
8497 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8498 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8500 (define_insn "sibcall_internal_symref_64bit"
8501 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8502 (match_operand 1 "" "i"))
8503 (clobber (reg:DI 1))
8505 (use (const_int 0))]
8509 return pa_output_call (insn, operands[0], 1);
8511 [(set_attr "type" "sibcall")
8512 (set (attr "length")
8513 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8514 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8516 (define_expand "sibcall_value"
8517 [(set (match_operand 0 "" "")
8518 (call (match_operand:SI 1 "" "")
8519 (match_operand 2 "" "")))]
8520 "!TARGET_PORTABLE_RUNTIME"
8524 rtx nb = operands[1];
8526 op = XEXP (operands[1], 0);
8530 if (!virtuals_instantiated)
8531 emit_move_insn (arg_pointer_rtx,
8532 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8536 /* The loop pass can generate new libcalls after the virtual
8537 registers are instantiated when fpregs are disabled because
8538 the only method that we have for doing DImode multiplication
8539 is with a libcall. This could be trouble if we haven't
8540 allocated enough space for the outgoing arguments. */
8541 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8543 emit_move_insn (arg_pointer_rtx,
8544 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8545 GEN_INT (STACK_POINTER_OFFSET + 64)));
8549 /* Indirect sibling calls are not allowed. */
8552 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8555 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8557 call_insn = emit_call_insn (call_insn);
8560 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8562 /* We don't have to restore the PIC register. */
8564 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8569 (define_insn "sibcall_value_internal_symref"
8570 [(set (match_operand 0 "" "")
8571 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8572 (match_operand 2 "" "i")))
8573 (clobber (reg:SI 1))
8575 (use (const_int 0))]
8576 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8579 pa_output_arg_descriptor (insn);
8580 return pa_output_call (insn, operands[1], 1);
8582 [(set_attr "type" "sibcall")
8583 (set (attr "length")
8584 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8585 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8587 (define_insn "sibcall_value_internal_symref_64bit"
8588 [(set (match_operand 0 "" "")
8589 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8590 (match_operand 2 "" "i")))
8591 (clobber (reg:DI 1))
8593 (use (const_int 0))]
8597 return pa_output_call (insn, operands[1], 1);
8599 [(set_attr "type" "sibcall")
8600 (set (attr "length")
8601 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 8)]
8602 (symbol_ref "pa_attr_length_call (insn, 1)")))])
8608 [(set_attr "type" "move")
8609 (set_attr "length" "4")])
8611 ;;; EH does longjmp's from and within the data section. Thus,
8612 ;;; an interspace branch is required for the longjmp implementation.
8613 ;;; Registers r1 and r2 are used as scratch registers for the jump
8615 (define_expand "interspace_jump"
8617 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8618 (clobber (match_dup 1))])]
8622 operands[1] = gen_rtx_REG (word_mode, 2);
8626 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8627 (clobber (reg:SI 2))]
8628 "TARGET_PA_20 && !TARGET_64BIT"
8630 [(set_attr "type" "branch")
8631 (set_attr "length" "4")])
8634 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8635 (clobber (reg:SI 2))]
8636 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8638 [(set_attr "type" "branch")
8639 (set_attr "length" "4")])
8642 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8643 (clobber (reg:SI 2))]
8645 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8646 [(set_attr "type" "branch")
8647 (set_attr "length" "12")])
8650 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8651 (clobber (reg:DI 2))]
8654 [(set_attr "type" "branch")
8655 (set_attr "length" "4")])
8657 (define_expand "builtin_longjmp"
8658 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8662 /* The elements of the buffer are, in order: */
8663 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8664 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
8665 POINTER_SIZE / BITS_PER_UNIT));
8666 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0],
8667 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8668 rtx pv = gen_rtx_REG (Pmode, 1);
8670 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
8671 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
8673 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8674 instead of the hard_frame_pointer_rtx in the save area. We need
8675 to adjust for the offset between these two values. */
8676 if (GET_CODE (fp) != REG)
8677 fp = force_reg (Pmode, fp);
8678 emit_move_insn (hard_frame_pointer_rtx, plus_constant (Pmode, fp, -8));
8680 /* This bit is the same as expand_builtin_longjmp. */
8681 emit_stack_restore (SAVE_NONLOCAL, stack);
8682 emit_use (hard_frame_pointer_rtx);
8683 emit_use (stack_pointer_rtx);
8685 /* Load the label we are jumping through into r1 so that we know
8686 where to look for it when we get back to setjmp's function for
8687 restoring the gp. */
8688 emit_move_insn (pv, lab);
8690 /* Prevent the insns above from being scheduled into the delay slot
8691 of the interspace jump because the space register could change. */
8692 emit_insn (gen_blockage ());
8694 emit_jump_insn (gen_interspace_jump (pv));
8699 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8700 (define_expand "extzvsi"
8701 [(set (match_operand:SI 0 "register_operand" "")
8702 (zero_extract:SI (match_operand:SI 1 "register_operand" "")
8703 (match_operand:SI 2 "uint5_operand" "")
8704 (match_operand:SI 3 "uint5_operand" "")))]
8708 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8709 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8711 /* PA extraction insns don't support zero length bitfields or fields
8712 extending beyond the left or right-most bits. Also, the predicate
8713 rejects lengths equal to a word as they are better handled by
8714 the move patterns. */
8715 if (len == 0 || pos + len > 32)
8718 /* From mips.md: extract_bit_field doesn't verify that our source
8719 matches the predicate, so check it again here. */
8720 if (!register_operand (operands[1], VOIDmode))
8723 emit_insn (gen_extzv_32 (operands[0], operands[1],
8724 operands[2], operands[3]));
8728 (define_insn "extzv_32"
8729 [(set (match_operand:SI 0 "register_operand" "=r")
8730 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8731 (match_operand:SI 2 "uint5_operand" "")
8732 (match_operand:SI 3 "uint5_operand" "")))]
8733 "UINTVAL (operands[2]) > 0
8734 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 32"
8735 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8736 [(set_attr "type" "shift")
8737 (set_attr "length" "4")])
8740 [(set (match_operand:SI 0 "register_operand" "=r")
8741 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8743 (match_operand:SI 2 "register_operand" "q")))]
8745 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8746 [(set_attr "type" "shift")
8747 (set_attr "length" "4")])
8749 (define_expand "extzvdi"
8750 [(set (match_operand:DI 0 "register_operand" "")
8751 (zero_extract:DI (match_operand:DI 1 "register_operand" "")
8752 (match_operand:DI 2 "uint6_operand" "")
8753 (match_operand:DI 3 "uint6_operand" "")))]
8757 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8758 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8760 /* PA extraction insns don't support zero length bitfields or fields
8761 extending beyond the left or right-most bits. Also, the predicate
8762 rejects lengths equal to a doubleword as they are better handled by
8763 the move patterns. */
8764 if (len == 0 || pos + len > 64)
8767 /* From mips.md: extract_bit_field doesn't verify that our source
8768 matches the predicate, so check it again here. */
8769 if (!register_operand (operands[1], VOIDmode))
8772 emit_insn (gen_extzv_64 (operands[0], operands[1],
8773 operands[2], operands[3]));
8777 (define_insn "extzv_64"
8778 [(set (match_operand:DI 0 "register_operand" "=r")
8779 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8780 (match_operand:DI 2 "uint6_operand" "")
8781 (match_operand:DI 3 "uint6_operand" "")))]
8783 && UINTVAL (operands[2]) > 0
8784 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 64"
8785 "extrd,u %1,%3+%2-1,%2,%0"
8786 [(set_attr "type" "shift")
8787 (set_attr "length" "4")])
8790 [(set (match_operand:DI 0 "register_operand" "=r")
8791 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8793 (match_operand:DI 2 "register_operand" "q")))]
8795 "extrd,u %1,%%sar,1,%0"
8796 [(set_attr "type" "shift")
8797 (set_attr "length" "4")])
8799 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8800 (define_expand "extvsi"
8801 [(set (match_operand:SI 0 "register_operand" "")
8802 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
8803 (match_operand:SI 2 "uint5_operand" "")
8804 (match_operand:SI 3 "uint5_operand" "")))]
8808 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8809 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8811 /* PA extraction insns don't support zero length bitfields or fields
8812 extending beyond the left or right-most bits. Also, the predicate
8813 rejects lengths equal to a word as they are better handled by
8814 the move patterns. */
8815 if (len == 0 || pos + len > 32)
8818 /* From mips.md: extract_bit_field doesn't verify that our source
8819 matches the predicate, so check it again here. */
8820 if (!register_operand (operands[1], VOIDmode))
8823 emit_insn (gen_extv_32 (operands[0], operands[1],
8824 operands[2], operands[3]));
8828 (define_insn "extv_32"
8829 [(set (match_operand:SI 0 "register_operand" "=r")
8830 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8831 (match_operand:SI 2 "uint5_operand" "")
8832 (match_operand:SI 3 "uint5_operand" "")))]
8833 "UINTVAL (operands[2]) > 0
8834 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 32"
8835 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8836 [(set_attr "type" "shift")
8837 (set_attr "length" "4")])
8840 [(set (match_operand:SI 0 "register_operand" "=r")
8841 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8843 (match_operand:SI 2 "register_operand" "q")))]
8845 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8846 [(set_attr "type" "shift")
8847 (set_attr "length" "4")])
8849 (define_expand "extvdi"
8850 [(set (match_operand:DI 0 "register_operand" "")
8851 (sign_extract:DI (match_operand:DI 1 "register_operand" "")
8852 (match_operand:DI 2 "uint6_operand" "")
8853 (match_operand:DI 3 "uint6_operand" "")))]
8857 unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
8858 unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
8860 /* PA extraction insns don't support zero length bitfields or fields
8861 extending beyond the left or right-most bits. Also, the predicate
8862 rejects lengths equal to a doubleword as they are better handled by
8863 the move patterns. */
8864 if (len == 0 || pos + len > 64)
8867 /* From mips.md: extract_bit_field doesn't verify that our source
8868 matches the predicate, so check it again here. */
8869 if (!register_operand (operands[1], VOIDmode))
8872 emit_insn (gen_extv_64 (operands[0], operands[1],
8873 operands[2], operands[3]));
8877 (define_insn "extv_64"
8878 [(set (match_operand:DI 0 "register_operand" "=r")
8879 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8880 (match_operand:DI 2 "uint6_operand" "")
8881 (match_operand:DI 3 "uint6_operand" "")))]
8883 && UINTVAL (operands[2]) > 0
8884 && UINTVAL (operands[2]) + UINTVAL (operands[3]) <= 64"
8885 "extrd,s %1,%3+%2-1,%2,%0"
8886 [(set_attr "type" "shift")
8887 (set_attr "length" "4")])
8890 [(set (match_operand:DI 0 "register_operand" "=r")
8891 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8893 (match_operand:DI 2 "register_operand" "q")))]
8895 "extrd,s %1,%%sar,1,%0"
8896 [(set_attr "type" "shift")
8897 (set_attr "length" "4")])
8899 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8900 (define_expand "insvsi"
8901 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
8902 (match_operand:SI 1 "uint5_operand" "")
8903 (match_operand:SI 2 "uint5_operand" ""))
8904 (match_operand:SI 3 "arith5_operand" ""))]
8908 unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
8909 unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
8911 /* PA insertion insns don't support zero length bitfields or fields
8912 extending beyond the left or right-most bits. Also, the predicate
8913 rejects lengths equal to a word as they are better handled by
8914 the move patterns. */
8915 if (len <= 0 || pos + len > 32)
8918 /* From mips.md: insert_bit_field doesn't verify that our destination
8919 matches the predicate, so check it again here. */
8920 if (!register_operand (operands[0], VOIDmode))
8923 emit_insn (gen_insv_32 (operands[0], operands[1],
8924 operands[2], operands[3]));
8928 (define_insn "insv_32"
8929 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8930 (match_operand:SI 1 "uint5_operand" "")
8931 (match_operand:SI 2 "uint5_operand" ""))
8932 (match_operand:SI 3 "arith5_operand" "r,L"))]
8933 "UINTVAL (operands[1]) > 0
8934 && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
8936 {dep|depw} %3,%2+%1-1,%1,%0
8937 {depi|depwi} %3,%2+%1-1,%1,%0"
8938 [(set_attr "type" "shift,shift")
8939 (set_attr "length" "4,4")])
8941 ;; Optimize insertion of const_int values of type 1...1xxxx.
8943 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8944 (match_operand:SI 1 "uint5_operand" "")
8945 (match_operand:SI 2 "uint5_operand" ""))
8946 (match_operand:SI 3 "const_int_operand" ""))]
8947 "(INTVAL (operands[3]) & 0x10) != 0 &&
8948 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8951 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8952 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8954 [(set_attr "type" "shift")
8955 (set_attr "length" "4")])
8957 (define_expand "insvdi"
8958 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
8959 (match_operand:DI 1 "uint6_operand" "")
8960 (match_operand:DI 2 "uint6_operand" ""))
8961 (match_operand:DI 3 "arith5_operand" ""))]
8965 unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
8966 unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
8968 /* PA insertion insns don't support zero length bitfields or fields
8969 extending beyond the left or right-most bits. Also, the predicate
8970 rejects lengths equal to a doubleword as they are better handled by
8971 the move patterns. */
8972 if (len <= 0 || pos + len > 64)
8975 /* From mips.md: insert_bit_field doesn't verify that our destination
8976 matches the predicate, so check it again here. */
8977 if (!register_operand (operands[0], VOIDmode))
8980 emit_insn (gen_insv_64 (operands[0], operands[1],
8981 operands[2], operands[3]));
8985 (define_insn "insv_64"
8986 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8987 (match_operand:DI 1 "uint6_operand" "")
8988 (match_operand:DI 2 "uint6_operand" ""))
8989 (match_operand:DI 3 "arith5_operand" "r,L"))]
8991 && UINTVAL (operands[1]) > 0
8992 && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 64"
8994 depd %3,%2+%1-1,%1,%0
8995 depdi %3,%2+%1-1,%1,%0"
8996 [(set_attr "type" "shift,shift")
8997 (set_attr "length" "4,4")])
8999 ;; Optimize insertion of const_int values of type 1...1xxxx.
9001 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
9002 (match_operand:DI 1 "uint6_operand" "")
9003 (match_operand:DI 2 "uint6_operand" ""))
9004 (match_operand:DI 3 "const_int_operand" ""))]
9005 "(INTVAL (operands[3]) & 0x10) != 0
9007 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9010 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9011 return \"depdi %3,%2+%1-1,%1,%0\";
9013 [(set_attr "type" "shift")
9014 (set_attr "length" "4")])
9017 [(set (match_operand:DI 0 "register_operand" "=r")
9018 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
9021 "depd,z %1,31,32,%0"
9022 [(set_attr "type" "shift")
9023 (set_attr "length" "4")])
9025 ;; This insn is used for some loop tests, typically loops reversed when
9026 ;; strength reduction is used. It is actually created when the instruction
9027 ;; combination phase combines the special loop test. Since this insn
9028 ;; is both a jump insn and has an output, it must deal with its own
9029 ;; reloads, hence the `Q' constraints. The `!' constraints direct reload
9030 ;; to not choose the register alternatives in the event a reload is needed.
9031 (define_insn "decrement_and_branch_until_zero"
9034 (match_operator 2 "comparison_operator"
9036 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*Q")
9037 (match_operand:SI 1 "int5_operand" "L,L,L"))
9039 (label_ref (match_operand 3 "" ""))
9042 (plus:SI (match_dup 0) (match_dup 1)))
9043 (clobber (match_scratch:SI 4 "=X,r,r"))]
9045 "* return pa_output_dbra (operands, insn, which_alternative); "
9046 ;; Do not expect to understand this the first time through.
9047 [(set_attr "type" "cbranch,multi,multi")
9048 (set (attr "length")
9049 (if_then_else (eq_attr "alternative" "0")
9050 ;; Loop counter in register case
9051 ;; Short branch has length of 4
9052 ;; Long branch has length of 8, 20, 24 or 28
9053 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9054 (const_int MAX_12BIT_OFFSET))
9056 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9057 (const_int MAX_17BIT_OFFSET))
9059 (match_test "TARGET_PORTABLE_RUNTIME")
9061 (not (match_test "flag_pic"))
9065 ;; Loop counter in FP reg case.
9066 ;; Extra goo to deal with additional reload insns.
9067 (if_then_else (eq_attr "alternative" "1")
9068 (if_then_else (lt (match_dup 3) (pc))
9069 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9070 (const_int MAX_12BIT_OFFSET))
9072 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9073 (const_int MAX_17BIT_OFFSET))
9075 (match_test "TARGET_PORTABLE_RUNTIME")
9077 (not (match_test "flag_pic"))
9080 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9081 (const_int MAX_12BIT_OFFSET))
9083 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9084 (const_int MAX_17BIT_OFFSET))
9086 (match_test "TARGET_PORTABLE_RUNTIME")
9088 (not (match_test "flag_pic"))
9092 ;; Loop counter in memory case.
9093 ;; Extra goo to deal with additional reload insns.
9094 (if_then_else (lt (match_dup 3) (pc))
9095 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9096 (const_int MAX_12BIT_OFFSET))
9098 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9099 (const_int MAX_17BIT_OFFSET))
9101 (match_test "TARGET_PORTABLE_RUNTIME")
9103 (not (match_test "flag_pic"))
9106 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9107 (const_int MAX_12BIT_OFFSET))
9109 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9110 (const_int MAX_17BIT_OFFSET))
9112 (match_test "TARGET_PORTABLE_RUNTIME")
9114 (not (match_test "flag_pic"))
9116 (const_int 36))))))])
9121 (match_operator 2 "movb_comparison_operator"
9122 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9123 (label_ref (match_operand 3 "" ""))
9125 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*Q,!*q")
9128 "* return pa_output_movb (operands, insn, which_alternative, 0); "
9129 ;; Do not expect to understand this the first time through.
9130 [(set_attr "type" "cbranch,multi,multi,multi")
9131 (set (attr "length")
9132 (if_then_else (eq_attr "alternative" "0")
9133 ;; Loop counter in register case
9134 ;; Short branch has length of 4
9135 ;; Long branch has length of 8, 20, 24 or 28
9136 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9137 (const_int MAX_12BIT_OFFSET))
9139 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9140 (const_int MAX_17BIT_OFFSET))
9142 (match_test "TARGET_PORTABLE_RUNTIME")
9144 (not (match_test "flag_pic"))
9148 ;; Loop counter in FP reg case.
9149 ;; Extra goo to deal with additional reload insns.
9150 (if_then_else (eq_attr "alternative" "1")
9151 (if_then_else (lt (match_dup 3) (pc))
9152 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9153 (const_int MAX_12BIT_OFFSET))
9155 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9156 (const_int MAX_17BIT_OFFSET))
9158 (match_test "TARGET_PORTABLE_RUNTIME")
9160 (not (match_test "flag_pic"))
9163 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9164 (const_int MAX_12BIT_OFFSET))
9166 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9167 (const_int MAX_17BIT_OFFSET))
9169 (match_test "TARGET_PORTABLE_RUNTIME")
9171 (not (match_test "flag_pic"))
9175 ;; Loop counter in memory or sar case.
9176 ;; Extra goo to deal with additional reload insns.
9177 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9178 (const_int MAX_12BIT_OFFSET))
9180 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9181 (const_int MAX_17BIT_OFFSET))
9183 (match_test "TARGET_PORTABLE_RUNTIME")
9185 (not (match_test "flag_pic"))
9187 (const_int 32)))))])
9189 ;; Handle negated branch.
9193 (match_operator 2 "movb_comparison_operator"
9194 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9196 (label_ref (match_operand 3 "" ""))))
9197 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*Q,!*q")
9200 "* return pa_output_movb (operands, insn, which_alternative, 1); "
9201 ;; Do not expect to understand this the first time through.
9202 [(set_attr "type" "cbranch,multi,multi,multi")
9203 (set (attr "length")
9204 (if_then_else (eq_attr "alternative" "0")
9205 ;; Loop counter in register case
9206 ;; Short branch has length of 4
9207 ;; Long branch has length of 8
9208 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9209 (const_int MAX_12BIT_OFFSET))
9211 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9212 (const_int MAX_17BIT_OFFSET))
9214 (match_test "TARGET_PORTABLE_RUNTIME")
9216 (not (match_test "flag_pic"))
9220 ;; Loop counter in FP reg case.
9221 ;; Extra goo to deal with additional reload insns.
9222 (if_then_else (eq_attr "alternative" "1")
9223 (if_then_else (lt (match_dup 3) (pc))
9224 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9225 (const_int MAX_12BIT_OFFSET))
9227 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9228 (const_int MAX_17BIT_OFFSET))
9230 (match_test "TARGET_PORTABLE_RUNTIME")
9232 (not (match_test "flag_pic"))
9235 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9236 (const_int MAX_12BIT_OFFSET))
9238 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9239 (const_int MAX_17BIT_OFFSET))
9241 (match_test "TARGET_PORTABLE_RUNTIME")
9243 (not (match_test "flag_pic"))
9247 ;; Loop counter in memory or SAR case.
9248 ;; Extra goo to deal with additional reload insns.
9249 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9250 (const_int MAX_12BIT_OFFSET))
9252 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9253 (const_int MAX_17BIT_OFFSET))
9255 (match_test "TARGET_PORTABLE_RUNTIME")
9257 (not (match_test "flag_pic"))
9259 (const_int 32)))))])
9262 [(set (pc) (label_ref (match_operand 3 "" "" )))
9263 (set (match_operand:SI 0 "ireg_operand" "=r")
9264 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9265 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9266 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9269 return pa_output_parallel_addb (operands, insn);
9271 [(set_attr "type" "parallel_branch")
9272 (set (attr "length")
9273 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9274 (const_int MAX_12BIT_OFFSET))
9276 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9277 (const_int MAX_17BIT_OFFSET))
9279 (match_test "TARGET_PORTABLE_RUNTIME")
9281 (not (match_test "flag_pic"))
9286 [(set (pc) (label_ref (match_operand 2 "" "" )))
9287 (set (match_operand:SF 0 "ireg_operand" "=r")
9288 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9292 return pa_output_parallel_movb (operands, insn);
9294 [(set_attr "type" "parallel_branch")
9295 (set (attr "length")
9296 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9297 (const_int MAX_12BIT_OFFSET))
9299 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9300 (const_int MAX_17BIT_OFFSET))
9302 (match_test "TARGET_PORTABLE_RUNTIME")
9304 (not (match_test "flag_pic"))
9309 [(set (pc) (label_ref (match_operand 2 "" "" )))
9310 (set (match_operand:SI 0 "ireg_operand" "=r")
9311 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9315 return pa_output_parallel_movb (operands, insn);
9317 [(set_attr "type" "parallel_branch")
9318 (set (attr "length")
9319 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9320 (const_int MAX_12BIT_OFFSET))
9322 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9323 (const_int MAX_17BIT_OFFSET))
9325 (match_test "TARGET_PORTABLE_RUNTIME")
9327 (not (match_test "flag_pic"))
9332 [(set (pc) (label_ref (match_operand 2 "" "" )))
9333 (set (match_operand:HI 0 "ireg_operand" "=r")
9334 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9338 return pa_output_parallel_movb (operands, insn);
9340 [(set_attr "type" "parallel_branch")
9341 (set (attr "length")
9342 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9343 (const_int MAX_12BIT_OFFSET))
9345 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9346 (const_int MAX_17BIT_OFFSET))
9348 (match_test "TARGET_PORTABLE_RUNTIME")
9350 (not (match_test "flag_pic"))
9355 [(set (pc) (label_ref (match_operand 2 "" "" )))
9356 (set (match_operand:QI 0 "ireg_operand" "=r")
9357 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9361 return pa_output_parallel_movb (operands, insn);
9363 [(set_attr "type" "parallel_branch")
9364 (set (attr "length")
9365 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9366 (const_int MAX_12BIT_OFFSET))
9368 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9369 (const_int MAX_17BIT_OFFSET))
9371 (match_test "TARGET_PORTABLE_RUNTIME")
9373 (not (match_test "flag_pic"))
9378 [(set (match_operand 0 "register_operand" "=f")
9379 (mult (match_operand 1 "register_operand" "f")
9380 (match_operand 2 "register_operand" "f")))
9381 (set (match_operand 3 "register_operand" "+f")
9382 (plus (match_operand 4 "register_operand" "f")
9383 (match_operand 5 "register_operand" "f")))]
9384 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9385 && reload_completed && pa_fmpyaddoperands (operands)"
9388 if (GET_MODE (operands[0]) == DFmode)
9390 if (rtx_equal_p (operands[3], operands[5]))
9391 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9393 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9397 if (rtx_equal_p (operands[3], operands[5]))
9398 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9400 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9403 [(set_attr "type" "fpalu")
9404 (set_attr "length" "4")])
9407 [(set (match_operand 3 "register_operand" "+f")
9408 (plus (match_operand 4 "register_operand" "f")
9409 (match_operand 5 "register_operand" "f")))
9410 (set (match_operand 0 "register_operand" "=f")
9411 (mult (match_operand 1 "register_operand" "f")
9412 (match_operand 2 "register_operand" "f")))]
9413 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9414 && reload_completed && pa_fmpyaddoperands (operands)"
9417 if (GET_MODE (operands[0]) == DFmode)
9419 if (rtx_equal_p (operands[3], operands[5]))
9420 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9422 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9426 if (rtx_equal_p (operands[3], operands[5]))
9427 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9429 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9432 [(set_attr "type" "fpalu")
9433 (set_attr "length" "4")])
9436 [(set (match_operand 0 "register_operand" "=f")
9437 (mult (match_operand 1 "register_operand" "f")
9438 (match_operand 2 "register_operand" "f")))
9439 (set (match_operand 3 "register_operand" "+f")
9440 (minus (match_operand 4 "register_operand" "f")
9441 (match_operand 5 "register_operand" "f")))]
9442 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9443 && reload_completed && pa_fmpysuboperands (operands)"
9446 if (GET_MODE (operands[0]) == DFmode)
9447 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9449 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9451 [(set_attr "type" "fpalu")
9452 (set_attr "length" "4")])
9455 [(set (match_operand 3 "register_operand" "+f")
9456 (minus (match_operand 4 "register_operand" "f")
9457 (match_operand 5 "register_operand" "f")))
9458 (set (match_operand 0 "register_operand" "=f")
9459 (mult (match_operand 1 "register_operand" "f")
9460 (match_operand 2 "register_operand" "f")))]
9461 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9462 && reload_completed && pa_fmpysuboperands (operands)"
9465 if (GET_MODE (operands[0]) == DFmode)
9466 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9468 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9470 [(set_attr "type" "fpalu")
9471 (set_attr "length" "4")])
9473 ;; The following two patterns are used by the trampoline code for nested
9474 ;; functions. They flush the I and D cache lines from the start address
9475 ;; (operand0) to the end address (operand1). No lines are flushed if the
9476 ;; end address is less than the start address (unsigned).
9478 ;; Because the range of memory flushed is variable and the size of a MEM
9479 ;; can only be a CONST_INT, the patterns specify that they perform an
9480 ;; unspecified volatile operation on all memory.
9482 ;; The address range for an icache flush must lie within a single
9483 ;; space on targets with non-equivalent space registers.
9485 ;; Operand 0 contains the start address.
9486 ;; Operand 1 contains the end address.
9487 ;; Operand 2 contains the line length to use.
9488 (define_insn "dcacheflush<P:mode>"
9490 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9491 (use (match_operand 0 "pmode_register_operand" "r"))
9492 (use (match_operand 1 "pmode_register_operand" "r"))
9493 (use (match_operand 2 "pmode_register_operand" "r"))
9494 (clobber (match_scratch:P 3 "=&0"))]
9496 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
9497 [(set_attr "type" "multi")
9498 (set_attr "length" "12")])
9500 (define_insn "icacheflush<P:mode>"
9502 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9503 (use (match_operand 0 "pmode_register_operand" "r"))
9504 (use (match_operand 1 "pmode_register_operand" "r"))
9505 (use (match_operand 2 "pmode_register_operand" "r"))
9506 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9507 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9508 (clobber (match_scratch:P 5 "=&0"))]
9510 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
9511 [(set_attr "type" "multi")
9512 (set_attr "length" "52")])
9514 ;; An out-of-line prologue.
9515 (define_insn "outline_prologue_call"
9516 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9517 (clobber (reg:SI 31))
9518 (clobber (reg:SI 22))
9519 (clobber (reg:SI 21))
9520 (clobber (reg:SI 20))
9521 (clobber (reg:SI 19))
9522 (clobber (reg:SI 1))]
9527 /* We need two different versions depending on whether or not we
9528 need a frame pointer. Also note that we return to the instruction
9529 immediately after the branch rather than two instructions after the
9530 break as normally is the case. */
9531 if (frame_pointer_needed)
9533 /* Must import the magic millicode routine(s). */
9534 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9536 if (TARGET_PORTABLE_RUNTIME)
9538 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9539 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9543 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9547 /* Must import the magic millicode routine(s). */
9548 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9550 if (TARGET_PORTABLE_RUNTIME)
9552 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9553 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9556 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9560 [(set_attr "type" "multi")
9561 (set_attr "length" "8")])
9563 ;; An out-of-line epilogue.
9564 (define_insn "outline_epilogue_call"
9565 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9568 (clobber (reg:SI 31))
9569 (clobber (reg:SI 22))
9570 (clobber (reg:SI 21))
9571 (clobber (reg:SI 20))
9572 (clobber (reg:SI 19))
9573 (clobber (reg:SI 2))
9574 (clobber (reg:SI 1))]
9579 /* We need two different versions depending on whether or not we
9580 need a frame pointer. Also note that we return to the instruction
9581 immediately after the branch rather than two instructions after the
9582 break as normally is the case. */
9583 if (frame_pointer_needed)
9585 /* Must import the magic millicode routine. */
9586 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9588 /* The out-of-line prologue will make sure we return to the right
9590 if (TARGET_PORTABLE_RUNTIME)
9592 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9593 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9597 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9601 /* Must import the magic millicode routine. */
9602 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9604 /* The out-of-line prologue will make sure we return to the right
9606 if (TARGET_PORTABLE_RUNTIME)
9608 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9609 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9612 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9616 [(set_attr "type" "multi")
9617 (set_attr "length" "8")])
9619 ;; Given a function pointer, canonicalize it so it can be
9620 ;; reliably compared to another function pointer. */
9621 (define_expand "canonicalize_funcptr_for_compare"
9622 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9623 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9624 (clobber (match_dup 2))
9625 (clobber (reg:SI 26))
9626 (clobber (reg:SI 22))
9627 (clobber (reg:SI 31))])
9628 (set (match_operand:SI 0 "register_operand" "")
9630 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9635 rtx canonicalize_funcptr_for_compare_libfunc
9636 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9638 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9639 operands[0], LCT_NORMAL, Pmode,
9640 1, operands[1], Pmode);
9644 operands[2] = gen_reg_rtx (SImode);
9645 if (GET_CODE (operands[1]) != REG)
9647 rtx tmp = gen_reg_rtx (Pmode);
9648 emit_move_insn (tmp, operands[1]);
9653 (define_insn "*$$sh_func_adrs"
9654 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9655 (clobber (match_operand:SI 0 "register_operand" "=a"))
9656 (clobber (reg:SI 26))
9657 (clobber (reg:SI 22))
9658 (clobber (reg:SI 31))]
9662 int length = get_attr_length (insn);
9665 xoperands[0] = GEN_INT (length - 8);
9666 xoperands[1] = GEN_INT (length - 16);
9668 /* Must import the magic millicode routine. */
9669 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9671 /* This is absolutely amazing.
9673 First, copy our input parameter into %r29 just in case we don't
9674 need to call $$sh_func_adrs. */
9675 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9676 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9678 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9679 we use %r26 unchanged. */
9680 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9681 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9683 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9684 4096, then again we use %r26 unchanged. */
9685 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9687 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9688 return pa_output_millicode_call (insn,
9689 gen_rtx_SYMBOL_REF (SImode,
9690 \"$$sh_func_adrs\"));
9692 [(set_attr "type" "sh_func_adrs")
9693 (set (attr "length")
9694 (cond [(and (const_int 0) (eq (const_int 0) (pc))) (const_int 28)]
9695 (plus (symbol_ref "pa_attr_length_millicode_call (insn)")
9698 ;; On the PA, the PIC register is call clobbered, so it must
9699 ;; be saved & restored around calls by the caller. If the call
9700 ;; doesn't return normally (nonlocal goto, or an exception is
9701 ;; thrown), then the code at the exception handler label must
9702 ;; restore the PIC register.
9703 (define_expand "exception_receiver"
9708 /* On the 64-bit port, we need a blockage because there is
9709 confusion regarding the dependence of the restore on the
9710 frame pointer. As a result, the frame pointer and pic
9711 register restores sometimes are interchanged erroneously. */
9713 emit_insn (gen_blockage ());
9714 /* Restore the PIC register using hppa_pic_save_rtx (). The
9715 PIC register is not saved in the frame in 64-bit ABI. */
9716 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9717 emit_insn (gen_blockage ());
9721 (define_expand "builtin_setjmp_receiver"
9722 [(label_ref (match_operand 0 "" ""))]
9727 emit_insn (gen_blockage ());
9728 /* Restore the PIC register. Hopefully, this will always be from
9729 a stack slot. The only registers that are valid after a
9730 builtin_longjmp are the stack and frame pointers. */
9731 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9732 emit_insn (gen_blockage ());
9736 ;; Allocate new stack space and update the saved stack pointer in the
9737 ;; frame marker. The HP C compilers also copy additional words in the
9738 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9739 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9740 ;; currently don't copy these values.
9742 ;; Since the copy of the frame marker can't be done atomically, I
9743 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9744 ;; The HP compilers appear to raise the stack and copy the frame
9745 ;; marker in a strict instruction sequence. This suggests that the
9746 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9747 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9748 ;; as GAS doesn't support it, or try to keep the instructions emitted
9749 ;; here in strict sequence.
9750 (define_expand "allocate_stack"
9751 [(match_operand 0 "" "")
9752 (match_operand 1 "" "")]
9758 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9759 in operand 0 before adjusting the stack. */
9760 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9761 anti_adjust_stack (operands[1]);
9762 if (TARGET_HPUX_UNWIND_LIBRARY)
9764 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9765 GEN_INT (TARGET_64BIT ? -8 : -4));
9766 emit_move_insn (gen_rtx_MEM (word_mode, addr), hard_frame_pointer_rtx);
9768 if (!TARGET_64BIT && flag_pic)
9770 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9771 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9776 (define_expand "prefetch"
9777 [(match_operand 0 "address_operand" "")
9778 (match_operand 1 "const_int_operand" "")
9779 (match_operand 2 "const_int_operand" "")]
9782 operands[0] = copy_addr_to_reg (operands[0]);
9783 emit_insn (gen_prefetch_20 (operands[0], operands[1], operands[2]));
9787 (define_insn "prefetch_20"
9788 [(prefetch (match_operand 0 "pmode_register_operand" "r")
9789 (match_operand:SI 1 "const_int_operand" "n")
9790 (match_operand:SI 2 "const_int_operand" "n"))]
9793 /* The SL cache-control completer indicates good spatial locality but
9794 poor temporal locality. The ldw instruction with a target of general
9795 register 0 prefetches a cache line for a read. The ldd instruction
9796 prefetches a cache line for a write. */
9797 static const char * const instr[2][2] = {
9799 "ldw,sl 0(%0),%%r0",
9807 int read_or_write = INTVAL (operands[1]) == 0 ? 0 : 1;
9808 int locality = INTVAL (operands[2]) == 0 ? 0 : 1;
9810 return instr [locality][read_or_write];
9812 [(set_attr "type" "load")
9813 (set_attr "length" "4")])
9816 (define_insn "tgd_load"
9817 [(set (match_operand:SI 0 "register_operand" "=r")
9818 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9819 (clobber (reg:SI 1))
9824 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9826 [(set_attr "type" "multi")
9827 (set_attr "length" "8")])
9829 (define_insn "tgd_load_pic"
9830 [(set (match_operand:SI 0 "register_operand" "=r")
9831 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
9832 (clobber (reg:SI 1))
9837 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9839 [(set_attr "type" "multi")
9840 (set_attr "length" "8")])
9842 (define_insn "tld_load"
9843 [(set (match_operand:SI 0 "register_operand" "=r")
9844 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
9845 (clobber (reg:SI 1))
9850 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
9852 [(set_attr "type" "multi")
9853 (set_attr "length" "8")])
9855 (define_insn "tld_load_pic"
9856 [(set (match_operand:SI 0 "register_operand" "=r")
9857 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
9858 (clobber (reg:SI 1))
9863 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
9865 [(set_attr "type" "multi")
9866 (set_attr "length" "8")])
9868 (define_insn "tld_offset_load"
9869 [(set (match_operand:SI 0 "register_operand" "=r")
9870 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
9872 (match_operand:SI 2 "register_operand" "r")))
9873 (clobber (reg:SI 1))]
9877 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
9879 [(set_attr "type" "multi")
9880 (set_attr "length" "8")])
9882 (define_insn "tp_load"
9883 [(set (match_operand:SI 0 "register_operand" "=r")
9884 (unspec:SI [(const_int 0)] UNSPEC_TP))]
9887 [(set_attr "type" "multi")
9888 (set_attr "length" "4")])
9890 (define_insn "tie_load"
9891 [(set (match_operand:SI 0 "register_operand" "=r")
9892 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
9893 (clobber (reg:SI 1))
9898 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
9900 [(set_attr "type" "multi")
9901 (set_attr "length" "8")])
9903 (define_insn "tie_load_pic"
9904 [(set (match_operand:SI 0 "register_operand" "=r")
9905 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
9906 (clobber (reg:SI 1))
9911 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
9913 [(set_attr "type" "multi")
9914 (set_attr "length" "8")])
9916 (define_insn "tle_load"
9917 [(set (match_operand:SI 0 "register_operand" "=r")
9918 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
9920 (match_operand:SI 2 "register_operand" "r")))
9921 (clobber (reg:SI 1))]
9923 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
9924 [(set_attr "type" "multi")
9925 (set_attr "length" "8")])
9927 ;; Atomic instructions
9929 ;; All memory loads and stores access storage atomically except
9930 ;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and
9931 ;; doubleword loads and stores are not guaranteed to be atomic
9932 ;; when referencing the I/O address space.
9934 ;; The kernel cmpxchg operation on linux is not atomic with respect to
9935 ;; memory stores on SMP machines, so we must do stores using a cmpxchg
9938 ;; These patterns are at the bottom so the non atomic versions are preferred.
9940 ;; Implement atomic QImode store using exchange.
9942 (define_expand "atomic_storeqi"
9943 [(match_operand:QI 0 "memory_operand") ;; memory
9944 (match_operand:QI 1 "register_operand") ;; val out
9945 (match_operand:SI 2 "const_int_operand")] ;; model
9948 if (TARGET_SYNC_LIBCALL)
9950 rtx mem = operands[0];
9951 rtx val = operands[1];
9952 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
9958 ;; Implement atomic HImode stores using exchange.
9960 (define_expand "atomic_storehi"
9961 [(match_operand:HI 0 "memory_operand") ;; memory
9962 (match_operand:HI 1 "register_operand") ;; val out
9963 (match_operand:SI 2 "const_int_operand")] ;; model
9966 if (TARGET_SYNC_LIBCALL)
9968 rtx mem = operands[0];
9969 rtx val = operands[1];
9970 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
9976 ;; Implement atomic SImode store using exchange.
9978 (define_expand "atomic_storesi"
9979 [(match_operand:SI 0 "memory_operand") ;; memory
9980 (match_operand:SI 1 "register_operand") ;; val out
9981 (match_operand:SI 2 "const_int_operand")] ;; model
9984 if (TARGET_SYNC_LIBCALL)
9986 rtx mem = operands[0];
9987 rtx val = operands[1];
9988 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
9994 ;; Implement atomic SFmode store using exchange.
9996 (define_expand "atomic_storesf"
9997 [(match_operand:SF 0 "memory_operand") ;; memory
9998 (match_operand:SF 1 "register_operand") ;; val out
9999 (match_operand:SI 2 "const_int_operand")] ;; model
10002 if (TARGET_SYNC_LIBCALL)
10004 rtx mem = operands[0];
10005 rtx val = operands[1];
10006 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
10012 ;; Implement atomic DImode load using 64-bit floating point load.
10014 (define_expand "atomic_loaddi"
10015 [(match_operand:DI 0 "register_operand") ;; val out
10016 (match_operand:DI 1 "memory_operand") ;; memory
10017 (match_operand:SI 2 "const_int_operand")] ;; model
10020 enum memmodel model;
10022 if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10025 model = memmodel_from_int (INTVAL (operands[2]));
10026 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
10027 expand_mem_thread_fence (model);
10028 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
10029 if (is_mm_seq_cst (model))
10030 expand_mem_thread_fence (model);
10034 (define_insn "atomic_loaddi_1"
10035 [(set (match_operand:DI 0 "register_operand" "=f,r")
10036 (mem:DI (match_operand:SI 1 "register_operand" "r,r")))
10037 (clobber (match_scratch:DI 2 "=X,f"))]
10038 "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
10040 {fldds|fldd} 0(%1),%0
10041 {fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
10042 [(set_attr "type" "move,move")
10043 (set_attr "length" "4,16")])
10045 ;; Implement atomic DImode store.
10047 (define_expand "atomic_storedi"
10048 [(match_operand:DI 0 "memory_operand") ;; memory
10049 (match_operand:DI 1 "register_operand") ;; val out
10050 (match_operand:SI 2 "const_int_operand")] ;; model
10053 enum memmodel model;
10055 if (TARGET_SYNC_LIBCALL)
10057 rtx mem = operands[0];
10058 rtx val = operands[1];
10059 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
10063 if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10066 model = memmodel_from_int (INTVAL (operands[2]));
10067 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
10068 expand_mem_thread_fence (model);
10069 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
10070 if (is_mm_seq_cst (model))
10071 expand_mem_thread_fence (model);
10075 (define_insn "atomic_storedi_1"
10076 [(set (mem:DI (match_operand:SI 0 "register_operand" "r,r"))
10077 (match_operand:DI 1 "register_operand" "f,r"))
10078 (clobber (match_scratch:DI 2 "=X,f"))]
10079 "!TARGET_64BIT && !TARGET_DISABLE_FPREGS
10080 && !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL"
10082 {fstds|fstd} %1,0(%0)
10083 {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
10084 [(set_attr "type" "move,move")
10085 (set_attr "length" "4,16")])
10087 ;; Implement atomic DFmode load using 64-bit floating point load.
10089 (define_expand "atomic_loaddf"
10090 [(match_operand:DF 0 "register_operand") ;; val out
10091 (match_operand:DF 1 "memory_operand") ;; memory
10092 (match_operand:SI 2 "const_int_operand")] ;; model
10095 enum memmodel model;
10097 if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10100 model = memmodel_from_int (INTVAL (operands[2]));
10101 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
10102 expand_mem_thread_fence (model);
10103 emit_insn (gen_atomic_loaddf_1 (operands[0], operands[1]));
10104 if (is_mm_seq_cst (model))
10105 expand_mem_thread_fence (model);
10109 (define_insn "atomic_loaddf_1"
10110 [(set (match_operand:DF 0 "register_operand" "=f,r")
10111 (mem:DF (match_operand:SI 1 "register_operand" "r,r")))
10112 (clobber (match_scratch:DF 2 "=X,f"))]
10113 "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
10115 {fldds|fldd} 0(%1),%0
10116 {fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
10117 [(set_attr "type" "move,move")
10118 (set_attr "length" "4,16")])
10120 ;; Implement atomic DFmode store using 64-bit floating point store.
10122 (define_expand "atomic_storedf"
10123 [(match_operand:DF 0 "memory_operand") ;; memory
10124 (match_operand:DF 1 "register_operand") ;; val out
10125 (match_operand:SI 2 "const_int_operand")] ;; model
10128 enum memmodel model;
10130 if (TARGET_SYNC_LIBCALL)
10132 rtx mem = operands[0];
10133 rtx val = operands[1];
10134 if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val))
10138 if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10141 model = memmodel_from_int (INTVAL (operands[2]));
10142 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
10143 expand_mem_thread_fence (model);
10144 emit_insn (gen_atomic_storedf_1 (operands[0], operands[1]));
10145 if (is_mm_seq_cst (model))
10146 expand_mem_thread_fence (model);
10150 (define_insn "atomic_storedf_1"
10151 [(set (mem:DF (match_operand:SI 0 "register_operand" "r,r"))
10152 (match_operand:DF 1 "register_operand" "f,r"))
10153 (clobber (match_scratch:DF 2 "=X,f"))]
10154 "!TARGET_64BIT && !TARGET_DISABLE_FPREGS
10155 && !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL"
10157 {fstds|fstd} %1,0(%0)
10158 {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
10159 [(set_attr "type" "move,move")
10160 (set_attr "length" "4,16")])