| blob | 272768398b4ab58ca6842cba120855c4bba7f5ca |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
97 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
107 #ifndef LOAD_EXTEND_OP
108 #define LOAD_EXTEND_OP(M) UNKNOWN
109 #endif
111 /* Number of attempts to combine instructions in this function. */
115 /* Number of attempts that got as far as substitution in this function. */
119 /* Number of instructions combined with added SETs in this function. */
123 /* Number of instructions combined in this function. */
127 /* Totals over entire compilation. */
131 /* combine_instructions may try to replace the right hand side of the
132 second instruction with the value of an associated REG_EQUAL note
133 before throwing it at try_combine. That is problematic when there
134 is a REG_DEAD note for a register used in the old right hand side
135 and can cause distribute_notes to do wrong things. This is the
136 second instruction if it has been so modified, null otherwise. */
140 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
144 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
147 \f
149 /* Record last point of death of (hard or pseudo) register n. */
152 /* Record last point of modification of (hard or pseudo) register n. */
155 /* The next group of fields allows the recording of the last value assigned
156 to (hard or pseudo) register n. We use this information to see if an
157 operation being processed is redundant given a prior operation performed
158 on the register. For example, an `and' with a constant is redundant if
159 all the zero bits are already known to be turned off.
161 We use an approach similar to that used by cse, but change it in the
162 following ways:
164 (1) We do not want to reinitialize at each label.
165 (2) It is useful, but not critical, to know the actual value assigned
166 to a register. Often just its form is helpful.
168 Therefore, we maintain the following fields:
170 last_set_value the last value assigned
171 last_set_label records the value of label_tick when the
172 register was assigned
173 last_set_table_tick records the value of label_tick when a
174 value using the register is assigned
175 last_set_invalid set to nonzero when it is not valid
176 to use the value of this register in some
177 register's value
179 To understand the usage of these tables, it is important to understand
180 the distinction between the value in last_set_value being valid and
181 the register being validly contained in some other expression in the
182 table.
184 (The next two parameters are out of date).
186 reg_stat[i].last_set_value is valid if it is nonzero, and either
187 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
189 Register I may validly appear in any expression returned for the value
190 of another register if reg_n_sets[i] is 1. It may also appear in the
191 value for register J if reg_stat[j].last_set_invalid is zero, or
192 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
194 If an expression is found in the table containing a register which may
195 not validly appear in an expression, the register is replaced by
196 something that won't match, (clobber (const_int 0)). */
198 /* Record last value assigned to (hard or pseudo) register n. */
200 rtx last_set_value;
202 /* Record the value of label_tick when an expression involving register n
203 is placed in last_set_value. */
207 /* Record the value of label_tick when the value for register n is placed in
208 last_set_value. */
212 /* These fields are maintained in parallel with last_set_value and are
213 used to store the mode in which the register was last set, the bits
214 that were known to be zero when it was last set, and the number of
215 sign bits copies it was known to have when it was last set. */
221 /* Set nonzero if references to register n in expressions should not be
222 used. last_set_invalid is set nonzero when this register is being
223 assigned to and last_set_table_tick == label_tick. */
227 /* Some registers that are set more than once and used in more than one
228 basic block are nevertheless always set in similar ways. For example,
229 a QImode register may be loaded from memory in two places on a machine
230 where byte loads zero extend.
232 We record in the following fields if a register has some leading bits
233 that are always equal to the sign bit, and what we know about the
234 nonzero bits of a register, specifically which bits are known to be
235 zero.
237 If an entry is zero, it means that we don't know anything special. */
243 /* Record the value of the label_tick when the last truncation
244 happened. The field truncated_to_mode is only valid if
245 truncation_label == label_tick. */
249 /* Record the last truncation seen for this register. If truncation
250 is not a nop to this mode we might be able to save an explicit
251 truncation if we know that value already contains a truncated
252 value. */
255 };
260 /* One plus the highest pseudo for which we track REG_N_SETS.
261 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
262 but during combine_split_insns new pseudos can be created. As we don't have
263 updated DF information in that case, it is hard to initialize the array
264 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
265 so instead of growing the arrays, just assume all newly created pseudos
266 during combine might be set multiple times. */
270 /* Record the luid of the last insn that invalidated memory
271 (anything that writes memory, and subroutine calls, but not pushes). */
275 /* Record the luid of the last CALL_INSN
276 so we can tell whether a potential combination crosses any calls. */
280 /* When `subst' is called, this is the insn that is being modified
281 (by combining in a previous insn). The PATTERN of this insn
282 is still the old pattern partially modified and it should not be
283 looked at, but this may be used to examine the successors of the insn
284 to judge whether a simplification is valid. */
288 /* This is the lowest LUID that `subst' is currently dealing with.
289 get_last_value will not return a value if the register was set at or
290 after this LUID. If not for this mechanism, we could get confused if
291 I2 or I1 in try_combine were an insn that used the old value of a register
292 to obtain a new value. In that case, we might erroneously get the
293 new value of the register when we wanted the old one. */
297 /* This contains any hard registers that are used in newpat; reg_dead_at_p
298 must consider all these registers to be always live. */
302 /* This is an insn to which a LOG_LINKS entry has been added. If this
303 insn is the earlier than I2 or I3, combine should rescan starting at
304 that location. */
308 /* Basic block in which we are performing combines. */
312 \f
313 /* Length of the currently allocated uid_insn_cost array. */
317 /* The following array records the insn_rtx_cost for every insn
318 in the instruction stream. */
322 /* The following array records the LOG_LINKS for every insn in the
323 instruction stream as struct insn_link pointers. */
329 };
333 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
334 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
336 #define FOR_EACH_LOG_LINK(L, INSN) \
337 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
339 /* Links for LOG_LINKS are allocated from this obstack. */
343 /* Allocate a link. */
347 {
355 }
357 /* Incremented for each basic block. */
361 /* Reset to label_tick for each extended basic block in scanning order. */
365 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
366 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
370 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
371 be safely used. It is zero while computing them and after combine has
372 completed. This former test prevents propagating values based on
373 previously set values, which can be incorrect if a variable is modified
374 in a loop. */
378 \f
379 /* Record one modification to rtl structure
380 to be undone by storing old_contents into *where. */
384 struct undo
385 {
390 };
392 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
393 num_undo says how many are currently recorded.
395 other_insn is nonzero if we have modified some other insn in the process
396 of working on subst_insn. It must be verified too. */
398 struct undobuf
399 {
403 };
407 /* Number of times the pseudo being substituted for
408 was found and replaced. */
413 machine_mode,
417 machine_mode,
489 \f
491 /* It is not safe to use ordinary gen_lowpart in combine.
492 See comments in gen_lowpart_for_combine. */
493 #undef RTL_HOOKS_GEN_LOWPART
494 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
496 /* Our implementation of gen_lowpart never emits a new pseudo. */
497 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
498 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
500 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
501 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
503 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
504 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
506 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
507 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
511 \f
512 /* Convenience wrapper for the canonicalize_comparison target hook.
513 Target hooks cannot use enum rtx_code. */
517 {
521 }
523 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
524 PATTERN can not be split. Otherwise, it returns an insn sequence.
525 This is a wrapper around split_insns which ensures that the
526 reg_stat vector is made larger if the splitter creates a new
527 register. */
531 {
540 }
542 /* This is used by find_single_use to locate an rtx in LOC that
543 contains exactly one use of DEST, which is typically either a REG
544 or CC0. It returns a pointer to the innermost rtx expression
545 containing DEST. Appearances of DEST that are being used to
546 totally replace it are not counted. */
550 {
559 {
563 CASE_CONST_ANY:
568 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
569 of a REG that occupies all of the REG, the insn uses DEST if
570 it is mentioned in the destination or the source. Otherwise, we
571 need just check the source. */
591 }
593 /* If it wasn't one of the common cases above, check each expression and
594 vector of this code. Look for a unique usage of DEST. */
598 {
600 {
605 else
611 /* Duplicate usage. */
613 }
615 {
619 {
625 else
632 }
633 }
634 }
637 }
640 /* See if DEST, produced in INSN, is used only a single time in the
641 sequel. If so, return a pointer to the innermost rtx expression in which
642 it is used.
644 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
646 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
647 care about REG_DEAD notes or LOG_LINKS.
649 Otherwise, we find the single use by finding an insn that has a
650 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
651 only referenced once in that insn, we know that it must be the first
652 and last insn referencing DEST. */
656 {
657 basic_block bb;
663 {
673 }
683 {
689 {
694 }
695 }
698 }
699 \f
700 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
701 insn. The substitution can be undone by undo_all. If INTO is already
702 set to NEWVAL, do not record this change. Because computing NEWVAL might
703 also call SUBST, we have to compute it before we put anything into
704 the undo table. */
706 static void
708 {
715 /* We'd like to catch as many invalid transformations here as
716 possible. Unfortunately, there are way too many mode changes
717 that are perfectly valid, so we'd waste too much effort for
718 little gain doing the checks here. Focus on catching invalid
719 transformations involving integer constants. */
722 {
723 /* Sanity check that we're replacing oldval with a CONST_INT
724 that is a valid sign-extension for the original mode. */
728 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
729 CONST_INT is not valid, because after the replacement, the
730 original mode would be gone. Unfortunately, we can't tell
731 when do_SUBST is called to replace the operand thereof, so we
732 perform this test on oldval instead, checking whether an
733 invalid replacement took place before we got here. */
738 }
742 else
751 }
753 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
755 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
756 for the value of a HOST_WIDE_INT value (including CONST_INT) is
757 not safe. */
759 static void
761 {
770 else
779 }
781 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
783 /* Similar to SUBST, but just substitute the mode. This is used when
784 changing the mode of a pseudo-register, so that any other
785 references to the entry in the regno_reg_rtx array will change as
786 well. */
788 static void
790 {
799 else
808 }
810 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
812 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
814 static void
816 {
825 else
834 }
836 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
837 \f
838 /* Subroutine of try_combine. Determine whether the replacement patterns
839 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
840 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
841 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
842 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
843 of all the instructions can be estimated and the replacements are more
844 expensive than the original sequence. */
846 static bool
849 {
854 /* Lookup the original insn_rtx_costs. */
859 {
862 {
866 }
867 else
868 {
872 }
873 }
874 else
875 {
878 }
880 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
881 correct that. */
886 /* Calculate the replacement insn_rtx_costs. */
889 {
893 }
894 else
895 {
898 }
901 {
907 {
910 }
911 else
913 }
915 /* Disallow this combination if both new_cost and old_cost are greater than
916 zero, and new_cost is greater than old cost. */
920 {
939 else
941 }
946 /* Update the uid_insn_cost array with the replacement costs. */
950 {
954 }
957 }
960 /* Delete any insns that copy a register to itself. */
962 static void
964 {
966 basic_block bb;
969 {
971 {
974 {
979 }
980 }
981 }
982 }
984 \f
985 /* Return false if we do not want to (or cannot) combine DEF. */
986 static bool
988 {
989 /* Do not consider if it is pre/post modification in MEM. */
995 /* Do not combine frame pointer adjustments. */
998 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1006 }
1008 /* Return false if we do not want to (or cannot) combine USE. */
1009 static bool
1011 {
1012 /* Do not consider the usage of the stack pointer by function call. */
1017 }
1019 /* Fill in log links field for all insns. */
1021 static void
1023 {
1024 basic_block bb;
1031 /* Pass through each block from the end, recording the uses of each
1032 register and establishing log links when def is encountered.
1033 Note that we do not clear next_use array in order to save time,
1034 so we have to test whether the use is in the same basic block as def.
1036 There are a few cases below when we do not consider the definition or
1037 usage -- these are taken from original flow.c did. Don't ask me why it is
1038 done this way; I don't know and if it works, I don't want to know. */
1041 {
1043 {
1047 /* Log links are created only once. */
1051 {
1067 /* flow.c claimed:
1069 We don't build a LOG_LINK for hard registers contained
1070 in ASM_OPERANDs. If these registers get replaced,
1071 we might wind up changing the semantics of the insn,
1072 even if reload can make what appear to be valid
1073 assignments later. */
1078 /* Don't add duplicate links between instructions. */
1087 }
1092 }
1093 }
1096 }
1098 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1099 true if we found a LOG_LINK that proves that A feeds B. This only works
1100 if there are no instructions between A and B which could have a link
1101 depending on A, since in that case we would not record a link for B.
1102 We also check the implicit dependency created by a cc0 setter/user
1103 pair. */
1105 static bool
1107 {
1115 }
1116 \f
1117 /* Main entry point for combiner. F is the first insn of the function.
1118 NREGS is the first unused pseudo-reg number.
1120 Return nonzero if the combiner has turned an indirect jump
1121 instruction into a direct jump. */
1122 static int
1124 {
1129 basic_block last_bb;
1149 /* Allocate array for insn info. */
1157 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1158 problems when, for example, we have j <<= 1 in a loop. */
1163 /* Scan all SETs and see if we can deduce anything about what
1164 bits are known to be zero for some registers and how many copies
1165 of the sign bit are known to exist for those registers.
1167 Also set any known values so that we can use it while searching
1168 for what bits are known to be set. */
1171 /* Allow the entry block and the first block to fall into the same EBB.
1172 Conceptually the incoming promotions are assigned to the entry block. */
1177 {
1182 label_tick++;
1190 {
1191 rtx links;
1197 insn);
1204 insn);
1206 /* Record the current insn_rtx_cost of this instruction. */
1209 optimize_this_for_speed_p);
1213 }
1214 }
1218 /* Now scan all the insns in forward order. */
1226 {
1232 label_tick++;
1242 {
1256 /* See if we know about function return values before this
1257 insn based upon SUBREG flags. */
1260 /* See if we can find hardregs and subreg of pseudos in
1261 narrower modes. This could help turning TRUNCATEs
1262 into SUBREGs. */
1265 /* Try this insn with each insn it links back to. */
1271 {
1274 }
1276 /* Try each sequence of three linked insns ending with this one. */
1280 {
1283 /* If the linked insn has been replaced by a note, then there
1284 is no point in pursuing this chain any further. */
1292 {
1295 }
1296 }
1298 /* Try to combine a jump insn that uses CC0
1299 with a preceding insn that sets CC0, and maybe with its
1300 logical predecessor as well.
1301 This is how we make decrement-and-branch insns.
1302 We need this special code because data flow connections
1303 via CC0 do not get entered in LOG_LINKS. */
1310 {
1321 }
1323 /* Do the same for an insn that explicitly references CC0. */
1330 {
1341 }
1343 /* Finally, see if any of the insns that this insn links to
1344 explicitly references CC0. If so, try this insn, that insn,
1345 and its predecessor if it sets CC0. */
1347 {
1359 }
1361 /* Try combining an insn with two different insns whose results it
1362 uses. */
1372 {
1375 }
1377 /* Try four-instruction combinations. */
1380 {
1384 /* If the linked insn has been replaced by a note, then there
1385 is no point in pursuing this chain any further. */
1390 {
1394 /* I0 -> I1 -> I2 -> I3. */
1400 {
1403 }
1404 /* I0, I1 -> I2, I2 -> I3. */
1411 {
1414 }
1415 }
1418 {
1422 /* I0 -> I2; I1, I2 -> I3. */
1428 {
1431 }
1432 /* I0 -> I1; I1, I2 -> I3. */
1438 {
1441 }
1442 }
1443 }
1445 /* Try this insn with each REG_EQUAL note it links back to. */
1447 {
1453 /* Avoid using a register that may already been marked
1454 dead by an earlier instruction. */
1462 {
1463 /* Temporarily replace the set's source with the
1464 contents of the REG_EQUAL note. The insn will
1465 be deleted or recognized by try_combine. */
1476 last_combined_insn);
1479 {
1482 }
1485 }
1486 }
1491 retry:
1492 ;
1493 }
1494 }
1501 /* Clean up. */
1507 {
1510 {
1513 }
1515 }
1525 /* Make recognizer allow volatile MEMs again. */
1529 }
1531 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1533 static void
1535 {
1541 }
1542 \f
1543 /* Set up any promoted values for incoming argument registers. */
1545 static void
1547 {
1548 tree arg;
1553 {
1558 /* Only continue if the incoming argument is in a register. */
1562 /* Determine, if possible, whether all call sites of the current
1563 function lie within the current compilation unit. (This does
1564 take into account the exporting of a function via taking its
1565 address, and so forth.) */
1568 /* The mode and signedness of the argument before any promotions happen
1569 (equal to the mode of the pseudo holding it at that stage). */
1573 /* The mode and signedness of the argument after any source language and
1574 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1578 /* The mode and signedness of the argument as it is actually passed,
1579 see assign_parm_setup_reg in function.c. */
1583 /* The mode of the register in which the argument is being passed. */
1586 /* Eliminate sign extensions in the callee when:
1587 (a) A mode promotion has occurred; */
1590 /* (b) The mode of the register is the same as the mode of
1591 the argument as it is passed; */
1594 /* (c) There's no language level extension; */
1596 ;
1597 /* (c.1) All callers are from the current compilation unit. If that's
1598 the case we don't have to rely on an ABI, we only have to know
1599 what we're generating right now, and we know that we will do the
1600 mode1 to mode2 promotion with the given sign. */
1603 /* (c.2) The combination of the two promotions is useful. This is
1604 true when the signs match, or if the first promotion is unsigned.
1605 In the later case, (sign_extend (zero_extend x)) is the same as
1606 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1612 /* Record that the value was promoted from mode1 to mode3,
1613 so that any sign extension at the head of the current
1614 function may be eliminated. */
1618 }
1619 }
1621 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1622 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1623 because some machines (maybe most) will actually do the sign-extension and
1624 this is the conservative approach.
1626 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1627 kludge. */
1629 static rtx
1631 {
1639 }
1641 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1642 and SET. */
1644 static void
1646 rtx x)
1647 {
1657 {
1661 }
1663 /* Don't call nonzero_bits if it cannot change anything. */
1665 {
1670 }
1672 /* Don't call num_sign_bit_copies if it cannot change anything. */
1674 {
1677 {
1681 }
1684 }
1685 }
1687 /* Called via note_stores. If X is a pseudo that is narrower than
1688 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1690 If we are setting only a portion of X and we can't figure out what
1691 portion, assume all bits will be used since we don't know what will
1692 be happening.
1694 Similarly, set how many bits of X are known to be copies of the sign bit
1695 at all locations in the function. This is the smallest number implied
1696 by any set of X. */
1698 static void
1700 {
1705 /* If this register is undefined at the start of the file, we can't
1706 say what its contents were. */
1707 && ! REGNO_REG_SET_P
1710 {
1714 {
1718 }
1720 /* If this register is being initialized using itself, and the
1721 register is uninitialized in this basic block, and there are
1722 no LOG_LINKS which set the register, then part of the
1723 register is uninitialized. In that case we can't assume
1724 anything about the number of nonzero bits.
1726 ??? We could do better if we checked this in
1727 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1728 could avoid making assumptions about the insn which initially
1729 sets the register, while still using the information in other
1730 insns. We would have to be careful to check every insn
1731 involved in the combination. */
1737 {
1744 {
1748 }
1749 }
1751 /* If this is a complex assignment, see if we can convert it into a
1752 simple assignment. */
1755 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1756 set what we know about X. */
1762 else
1763 {
1766 }
1767 }
1768 }
1769 \f
1770 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1771 optionally insns that were previously combined into I3 or that will be
1772 combined into the merger of INSN and I3. The order is PRED, PRED2,
1773 INSN, SUCC, SUCC2, I3.
1775 Return 0 if the combination is not allowed for any reason.
1777 If the combination is allowed, *PDEST will be set to the single
1778 destination of INSN and *PSRC to the single source, and this function
1779 will return 1. */
1781 static int
1785 {
1790 rtx link;
1795 {
1797 {
1802 }
1807 }
1811 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1812 or a PARALLEL consisting of such a SET and CLOBBERs.
1814 If INSN has CLOBBER parallel parts, ignore them for our processing.
1815 By definition, these happen during the execution of the insn. When it
1816 is merged with another insn, all bets are off. If they are, in fact,
1817 needed and aren't also supplied in I3, they may be added by
1818 recog_for_combine. Otherwise, it won't match.
1820 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1821 note.
1823 Get the source and destination of INSN. If more than one, can't
1824 combine. */
1830 {
1832 {
1836 {
1837 /* This is important to combine floating point insns
1838 for the SH4 port. */
1840 /* Combining an isolated USE doesn't make sense.
1841 We depend here on combinable_i3pat to reject them. */
1842 /* The code below this loop only verifies that the inputs of
1843 the SET in INSN do not change. We call reg_set_between_p
1844 to verify that the REG in the USE does not change between
1845 I3 and INSN.
1846 If the USE in INSN was for a pseudo register, the matching
1847 insn pattern will likely match any register; combining this
1848 with any other USE would only be safe if we knew that the
1849 used registers have identical values, or if there was
1850 something to tell them apart, e.g. different modes. For
1851 now, we forgo such complicated tests and simply disallow
1852 combining of USES of pseudo registers with any other USE. */
1855 {
1860 do
1861 {
1871 }
1873 }
1876 /* We can ignore CLOBBERs. */
1881 /* Ignore SETs whose result isn't used but not those that
1882 have side-effects. */
1888 /* If we have already found a SET, this is a second one and
1889 so we cannot combine with this insn. */
1897 /* Anything else means we can't combine. */
1899 }
1900 }
1903 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1904 so don't do anything with it. */
1907 }
1908 else
1914 /* The simplification in expand_field_assignment may call back to
1915 get_last_value, so set safe guard here. */
1921 /* Do not eliminate user-specified register if it is in an
1922 asm input because we may break the register asm usage defined
1923 in GCC manual if allow to do so.
1924 Be aware that this may cover more cases than we expect but this
1925 should be harmless. */
1930 /* Don't eliminate a store in the stack pointer. */
1932 /* Don't combine with an insn that sets a register to itself if it has
1933 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1935 /* Can't merge an ASM_OPERANDS. */
1937 /* Can't merge a function call. */
1939 /* Don't eliminate a function call argument. */
1945 /* Don't substitute into an incremented register. */
1949 /* Don't substitute into a non-local goto, this confuses CFG. */
1951 /* Make sure that DEST is not used after SUCC but before I3. */
1952 || (!all_adjacent
1953 && ((succ2
1957 /* Make sure that the value that is to be substituted for the register
1958 does not use any registers whose values alter in between. However,
1959 If the insns are adjacent, a use can't cross a set even though we
1960 think it might (this can happen for a sequence of insns each setting
1961 the same destination; last_set of that register might point to
1962 a NOTE). If INSN has a REG_EQUIV note, the register is always
1963 equivalent to the memory so the substitution is valid even if there
1964 are intervening stores. Also, don't move a volatile asm or
1965 UNSPEC_VOLATILE across any other insns. */
1966 || (! all_adjacent
1972 /* Don't combine across a CALL_INSN, because that would possibly
1973 change whether the life span of some REGs crosses calls or not,
1974 and it is a pain to update that information.
1975 Exception: if source is a constant, moving it later can't hurt.
1976 Accept that as a special case. */
1980 /* DEST must either be a REG or CC0. */
1982 {
1983 /* If register alignment is being enforced for multi-word items in all
1984 cases except for parameters, it is possible to have a register copy
1985 insn referencing a hard register that is not allowed to contain the
1986 mode being copied and which would not be valid as an operand of most
1987 insns. Eliminate this problem by not combining with such an insn.
1989 Also, on some machines we don't want to extend the life of a hard
1990 register. */
1995 /* Don't extend the life of a hard register unless it is
1996 user variable (if we have few registers) or it can't
1997 fit into the desired register (meaning something special
1998 is going on).
1999 Also avoid substituting a return register into I3, because
2000 reload can't handle a conflict with constraints of other
2001 inputs. */
2005 }
2013 {
2016 /* If the clobber represents an earlyclobber operand, we must not
2017 substitute an expression containing the clobbered register.
2018 As we do not analyze the constraint strings here, we have to
2019 make the conservative assumption. However, if the register is
2020 a fixed hard reg, the clobber cannot represent any operand;
2021 we leave it up to the machine description to either accept or
2022 reject use-and-clobber patterns. */
2028 }
2030 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2031 or not), reject, unless nothing volatile comes between it and I3 */
2034 {
2035 /* Make sure neither succ nor succ2 contains a volatile reference. */
2040 /* We'll check insns between INSN and I3 below. */
2041 }
2043 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2044 to be an explicit register variable, and was chosen for a reason. */
2050 /* If INSN contains volatile references (specifically volatile MEMs),
2051 we cannot combine across any other volatile references.
2052 Even if INSN doesn't contain volatile references, any intervening
2053 volatile insn might affect machine state. */
2056 ? volatile_refs_p
2063 /* If INSN contains an autoincrement or autodecrement, make sure that
2064 register is not used between there and I3, and not already used in
2065 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2066 Also insist that I3 not be a jump; if it were one
2067 and the incremented register were spilled, we would lose. */
2085 /* Don't combine an insn that follows a CC0-setting insn.
2086 An insn that uses CC0 must not be separated from the one that sets it.
2087 We do, however, allow I2 to follow a CC0-setting insn if that insn
2088 is passed as I1; in that case it will be deleted also.
2089 We also allow combining in this case if all the insns are adjacent
2090 because that would leave the two CC0 insns adjacent as well.
2091 It would be more logical to test whether CC0 occurs inside I1 or I2,
2092 but that would be much slower, and this ought to be equivalent. */
2095 {
2100 }
2102 /* If we get here, we have passed all the tests and the combination is
2103 to be allowed. */
2109 }
2110 \f
2111 /* LOC is the location within I3 that contains its pattern or the component
2112 of a PARALLEL of the pattern. We validate that it is valid for combining.
2114 One problem is if I3 modifies its output, as opposed to replacing it
2115 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2116 doing so would produce an insn that is not equivalent to the original insns.
2118 Consider:
2120 (set (reg:DI 101) (reg:DI 100))
2121 (set (subreg:SI (reg:DI 101) 0) <foo>)
2123 This is NOT equivalent to:
2125 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2126 (set (reg:DI 101) (reg:DI 100))])
2128 Not only does this modify 100 (in which case it might still be valid
2129 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2131 We can also run into a problem if I2 sets a register that I1
2132 uses and I1 gets directly substituted into I3 (not via I2). In that
2133 case, we would be getting the wrong value of I2DEST into I3, so we
2134 must reject the combination. This case occurs when I2 and I1 both
2135 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2136 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2137 of a SET must prevent combination from occurring. The same situation
2138 can occur for I0, in which case I0_NOT_IN_SRC is set.
2140 Before doing the above check, we first try to expand a field assignment
2141 into a set of logical operations.
2143 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2144 we place a register that is both set and used within I3. If more than one
2145 such register is detected, we fail.
2147 Return 1 if the combination is valid, zero otherwise. */
2149 static int
2152 {
2156 {
2161 rtx subdest;
2168 /* Check for the case where I3 modifies its output, as discussed
2169 above. We don't want to prevent pseudos from being combined
2170 into the address of a MEM, so only prevent the combination if
2171 i1 or i2 set the same MEM. */
2181 /* This is the same test done in can_combine_p except we can't test
2182 all_adjacent; we don't have to, since this instruction will stay
2183 in place, thus we are not considering increasing the lifetime of
2184 INNER_DEST.
2186 Also, if this insn sets a function argument, combining it with
2187 something that might need a spill could clobber a previous
2188 function argument; the all_adjacent test in can_combine_p also
2189 checks this; here, we do a more specific test for this case. */
2199 /* If DEST is used in I3, it is being killed in this insn, so
2200 record that for later. We have to consider paradoxical
2201 subregs here, since they kill the whole register, but we
2202 ignore partial subregs, STRICT_LOW_PART, etc.
2203 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2204 STACK_POINTER_REGNUM, since these are always considered to be
2205 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2215 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2221 {
2226 }
2227 }
2230 {
2237 }
2240 }
2241 \f
2242 /* Return 1 if X is an arithmetic expression that contains a multiplication
2243 and division. We don't count multiplications by powers of two here. */
2245 static int
2247 {
2249 {
2265 }
2266 }
2267 \f
2268 /* Determine whether INSN can be used in a combination. Return nonzero if
2269 not. This is used in try_combine to detect early some cases where we
2270 can't perform combinations. */
2272 static int
2274 {
2275 rtx set;
2278 /* If this isn't really an insn, we can't do anything.
2279 This can occur when flow deletes an insn that it has merged into an
2280 auto-increment address. */
2284 /* Never combine loads and stores involving hard regs that are likely
2285 to be spilled. The register allocator can usually handle such
2286 reg-reg moves by tying. If we allow the combiner to make
2287 substitutions of likely-spilled regs, reload might die.
2288 As an exception, we allow combinations involving fixed regs; these are
2289 not available to the register allocator so there's no risk involved. */
2310 }
2312 struct likely_spilled_retval_info
2313 {
2316 };
2318 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2319 hard registers that are known to be written to / clobbered in full. */
2320 static void
2322 {
2339 else
2342 }
2344 /* Return nonzero iff part of the return value is live during INSN, and
2345 it is likely spilled. This can happen when more than one insn is needed
2346 to copy the return value, e.g. when we consider to combine into the
2347 second copy insn for a complex value. */
2349 static int
2351 {
2353 rtx reg;
2356 /* We assume here that no machine mode needs more than
2357 32 hard registers when the value overlaps with a register
2358 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2373 /* Disregard parts of the return value that are set later. */
2382 /* Check if any of the (probably) live return value registers is
2383 likely spilled. */
2384 nregs --;
2385 do
2386 {
2392 }
2394 /* Adjust INSN after we made a change to its destination.
2396 Changing the destination can invalidate notes that say something about
2397 the results of the insn and a LOG_LINK pointing to the insn. */
2399 static void
2401 {
2402 /* For notes, be conservative and simply remove them. */
2405 /* The new insn will have a destination that was previously the destination
2406 of an insn just above it. Call distribute_links to make a LOG_LINK from
2407 the next use of that destination. */
2423 }
2425 /* Return TRUE if combine can reuse reg X in mode MODE.
2426 ADDED_SETS is nonzero if the original set is still required. */
2427 static bool
2429 {
2436 /* Allow hard registers if the new mode is legal, and occupies no more
2437 registers than the old mode. */
2442 /* Or a pseudo that is only used once. */
2445 && !added_sets
2447 }
2450 /* Check whether X, the destination of a set, refers to part of
2451 the register specified by REG. */
2453 static bool
2455 {
2456 /* Check that reg is an integer mode register. */
2467 }
2469 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2470 Note that the INSN should be deleted *after* removing dead edges, so
2471 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2472 but not for a (set (pc) (label_ref FOO)). */
2474 static void
2476 {
2484 {
2489 /* Remove barriers from the footer if there are any. */
2492 {
2495 else
2499 }
2502 }
2503 }
2505 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2506 by an arbitrary number of CLOBBERs. */
2507 static bool
2509 {
2528 }
2530 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2531 CLOBBERs), can be split into individual SETs in that order, without
2532 changing semantics. */
2533 static bool
2535 {
2543 {
2552 }
2555 }
2557 /* Try to combine the insns I0, I1 and I2 into I3.
2558 Here I0, I1 and I2 appear earlier than I3.
2559 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2560 I3.
2562 If we are combining more than two insns and the resulting insn is not
2563 recognized, try splitting it into two insns. If that happens, I2 and I3
2564 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2565 Otherwise, I0, I1 and I2 are pseudo-deleted.
2567 Return 0 if the combination does not work. Then nothing is changed.
2568 If we did the combination, return the insn at which combine should
2569 resume scanning.
2571 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2572 new direct jump instruction.
2574 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2575 been I3 passed to an earlier try_combine within the same basic
2576 block. */
2581 {
2582 /* New patterns for I3 and I2, respectively. */
2586 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2587 dead. */
2589 /* Total number of SETs to put into I3. */
2591 /* Nonzero if I2's or I1's body now appears in I3. */
2593 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2595 /* Contains I3 if the destination of I3 is used in its source, which means
2596 that the old life of I3 is being killed. If that usage is placed into
2597 I2 and not in I3, a REG_DEAD note must be made. */
2599 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2601 /* Copy of SET_SRC of I1 and I0, if needed. */
2603 /* Set if I2DEST was reused as a scratch register. */
2605 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2607 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2612 /* Notes that must be added to REG_NOTES in I3 and I2. */
2614 /* Notes that we substituted I3 into I2 instead of the normal case. */
2616 /* Notes that I1, I2 or I3 is a MULT operation. */
2623 rtx temp_expr;
2626 rtx new_other_notes;
2629 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2630 never be). */
2634 /* Only try four-insn combinations when there's high likelihood of
2635 success. Look for simple insns, such as loads of constants or
2636 binary operations involving a constant. */
2638 {
2648 {
2651 rtx src;
2656 {
2659 }
2661 ngood++;
2664 nshift++;
2665 }
2667 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2668 are likely manipulating its value. Ideally we'll be able to combine
2669 all four insns into a bitfield insertion of some kind.
2671 Note the source in I0 might be inside a sign/zero extension and the
2672 memory modes in I0 and I3 might be different. So extract the address
2673 from the destination of I3 and search for it in the source of I0.
2675 In the event that there's a match but the source/dest do not actually
2676 refer to the same memory, the worst that happens is we try some
2677 combinations that we wouldn't have otherwise. */
2679 /* Ensure the source of SET0 is a MEM, possibly buried inside
2680 an extension. */
2686 /* Ensure the destination of SET3 is a MEM. */
2688 /* Would it be better to extract the base address for the MEM
2689 in SET3 and look for that? I don't have cases where it matters
2690 but I could envision such cases. */
2696 }
2698 /* Exit early if one of the insns involved can't be used for
2699 combinations. */
2710 combine_attempts++;
2713 /* Reset the hard register usage information. */
2717 {
2724 else
2727 }
2729 /* If multiple insns feed into one of I2 or I3, they can be in any
2730 order. To simplify the code below, reorder them in sequence. */
2740 /* First check for one important special case that the code below will
2741 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2742 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2743 we may be able to replace that destination with the destination of I3.
2744 This occurs in the common code where we compute both a quotient and
2745 remainder into a structure, in which case we want to do the computation
2746 directly into the structure to avoid register-register copies.
2748 Note that this case handles both multiple sets in I2 and also cases
2749 where I2 has a number of CLOBBERs inside the PARALLEL.
2751 We make very conservative checks below and only try to handle the
2752 most common cases of this. For example, we only handle the case
2753 where I2 and I3 are adjacent to avoid making difficult register
2754 usage tests. */
2762 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2763 below would need to check what is inside (and reg_overlap_mentioned_p
2764 doesn't support those codes anyway). Don't allow those destinations;
2765 the resulting insn isn't likely to be recognized anyway. */
2771 {
2774 /* Make sure that the destination of I3,
2775 which we are going to substitute into one output of I2,
2776 is not used within another output of I2. We must avoid making this:
2777 (parallel [(set (mem (reg 69)) ...)
2778 (set (reg 69) ...)])
2779 which is not well-defined as to order of actions.
2780 (Besides, reload can't handle output reloads for this.)
2782 The problem can also happen if the dest of I3 is a memory ref,
2783 if another dest in I2 is an indirect memory ref. */
2791 /* Make sure this PARALLEL is not an asm. We do not allow combining
2792 that usually (see can_combine_p), so do not here either. */
2802 {
2803 combine_merges++;
2813 /* Replace the dest in I2 with our dest and make the resulting
2814 insn the new pattern for I3. Then skip to where we validate
2815 the pattern. Everything was set up above. */
2820 }
2821 }
2823 /* If I2 is setting a pseudo to a constant and I3 is setting some
2824 sub-part of it to another constant, merge them by making a new
2825 constant. */
2832 {
2838 {
2841 {
2847 }
2848 }
2849 else
2850 {
2855 }
2858 {
2859 /* If this is the low part, we're done. */
2861 ;
2862 /* Handle the case where inner is twice the size of outer. */
2866 /* Otherwise give up for now. */
2867 else
2869 }
2872 {
2876 wide_int o
2881 combine_merges++;
2888 /* Replace the source in I2 with the new constant and make the
2889 resulting insn the new pattern for I3. Then skip to where we
2890 validate the pattern. Everything was set up above. */
2896 /* The dest of I3 has been replaced with the dest of I2. */
2899 }
2900 }
2902 /* If we have no I1 and I2 looks like:
2903 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2904 (set Y OP)])
2905 make up a dummy I1 that is
2906 (set Y OP)
2907 and change I2 to be
2908 (set (reg:CC X) (compare:CC Y (const_int 0)))
2910 (We can ignore any trailing CLOBBERs.)
2912 This undoes a previous combination and allows us to match a branch-and-
2913 decrement insn. */
2925 {
2926 /* We make I1 with the same INSN_UID as I2. This gives it
2927 the same DF_INSN_LUID for value tracking. Our fake I1 will
2928 never appear in the insn stream so giving it the same INSN_UID
2929 as I2 will not cause a problem. */
2942 }
2944 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2945 make those two SETs separate I1 and I2 insns, and make an I0 that is
2946 the original I1. */
2952 {
2953 /* If there is no I1, there is no I0 either. */
2956 /* We make I1 with the same INSN_UID as I2. This gives it
2957 the same DF_INSN_LUID for value tracking. Our fake I1 will
2958 never appear in the insn stream so giving it the same INSN_UID
2959 as I2 will not cause a problem. */
2967 }
2969 /* Verify that I2 and I1 are valid for combining. */
2975 {
2978 }
2980 /* Record whether I2DEST is used in I2SRC and similarly for the other
2981 cases. Knowing this will help in register status updating below. */
2992 /* For the earlier insns, determine which of the subsequent ones they
2993 feed. */
3000 /* Ensure that I3's pattern can be the destination of combines. */
3006 {
3009 }
3011 /* See if any of the insns is a MULT operation. Unless one is, we will
3012 reject a combination that is, since it must be slower. Be conservative
3013 here. */
3021 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3022 We used to do this EXCEPT in one case: I3 has a post-inc in an
3023 output operand. However, that exception can give rise to insns like
3024 mov r3,(r3)+
3025 which is a famous insn on the PDP-11 where the value of r3 used as the
3026 source was model-dependent. Avoid this sort of thing. */
3028 #if 0
3034 /* It's not the exception. */
3035 #endif
3037 {
3038 rtx link;
3044 {
3047 }
3048 }
3050 /* See if the SETs in I1 or I2 need to be kept around in the merged
3051 instruction: whenever the value set there is still needed past I3.
3052 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3054 For the SET in I1, we have two cases: if I1 and I2 independently feed
3055 into I3, the set in I1 needs to be kept around unless I1DEST dies
3056 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3057 in I1 needs to be kept around unless I1DEST dies or is set in either
3058 I2 or I3. The same considerations apply to I0. */
3065 else
3073 else
3076 /* We are about to copy insns for the case where they need to be kept
3077 around. Check that they can be copied in the merged instruction. */
3083 {
3086 }
3088 /* If the set in I2 needs to be kept around, we must make a copy of
3089 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3090 PATTERN (I2), we are only substituting for the original I1DEST, not into
3091 an already-substituted copy. This also prevents making self-referential
3092 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3093 I2DEST. */
3096 {
3099 else
3101 }
3104 {
3107 else
3109 }
3112 {
3115 else
3117 }
3119 combine_merges++;
3121 /* Substitute in the latest insn for the regs set by the earlier ones. */
3127 /* Many machines that don't use CC0 have insns that can both perform an
3128 arithmetic operation and set the condition code. These operations will
3129 be represented as a PARALLEL with the first element of the vector
3130 being a COMPARE of an arithmetic operation with the constant zero.
3131 The second element of the vector will set some pseudo to the result
3132 of the same arithmetic operation. If we simplify the COMPARE, we won't
3133 match such a pattern and so will generate an extra insn. Here we test
3134 for this case, where both the comparison and the operation result are
3135 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3136 I2SRC. Later we will make the PARALLEL that contains I2. */
3142 {
3143 rtx newpat_dest;
3157 {
3162 }
3164 /* Do the rest only if op1 is const0_rtx, which may be the
3165 result of simplification. */
3167 {
3168 /* If a single use of the CC is found, prepare to modify it
3169 when SELECT_CC_MODE returns a new CC-class mode, or when
3170 the above simplify_compare_const() returned a new comparison
3171 operator. undobuf.other_insn is assigned the CC use insn
3172 when modifying it. */
3174 {
3175 #ifdef SELECT_CC_MODE
3176 machine_mode new_mode
3181 {
3186 else
3187 {
3190 }
3191 }
3192 #endif
3193 /* Cases for modifying the CC-using comparison. */
3195 /* ??? Do we need to verify the zero rtx? */
3197 {
3198 /* Replace cc_use_loc with entire new RTX. */
3203 }
3205 {
3206 /* Just replace the CC reg with a new mode. */
3209 }
3210 }
3212 /* Now we modify the current newpat:
3213 First, SET_DEST(newpat) is updated if the CC mode has been
3214 altered. For targets without SELECT_CC_MODE, this should be
3215 optimized away. */
3218 /* This is always done to propagate i2src into newpat. */
3221 /* Create new version of i2pat if needed; the below PARALLEL
3222 creation needs this to work correctly. */
3226 }
3227 }
3230 {
3231 /* It is possible that the source of I2 or I1 may be performing
3232 an unneeded operation, such as a ZERO_EXTEND of something
3233 that is known to have the high part zero. Handle that case
3234 by letting subst look at the inner insns.
3236 Another way to do this would be to have a function that tries
3237 to simplify a single insn instead of merging two or more
3238 insns. We don't do this because of the potential of infinite
3239 loops and because of the potential extra memory required.
3240 However, doing it the way we are is a bit of a kludge and
3241 doesn't catch all cases.
3243 But only do this if -fexpensive-optimizations since it slows
3244 things down and doesn't usually win.
3246 This is not done in the COMPARE case above because the
3247 unmodified I2PAT is used in the PARALLEL and so a pattern
3248 with a modified I2SRC would not match. */
3251 {
3252 /* Pass pc_rtx so no substitutions are done, just
3253 simplifications. */
3255 {
3258 }
3262 }
3267 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3268 copy of I2SRC each time we substitute it, in order to avoid creating
3269 self-referential RTL when we will be substituting I1SRC for I1DEST
3270 later. Likewise if I0 feeds into I2, either directly or indirectly
3271 through I1, and I0DEST is in I0SRC. */
3278 /* Record whether I2's body now appears within I3's body. */
3280 }
3282 /* If we already got a failure, don't try to do more. Otherwise, try to
3283 substitute I1 if we have it. */
3286 {
3287 /* Check that an autoincrement side-effect on I1 has not been lost.
3288 This happens if I1DEST is mentioned in I2 and dies there, and
3289 has disappeared from the new pattern. */
3291 && i1_feeds_i2_n
3294 /* Before we can do this substitution, we must redo the test done
3295 above (see detailed comments there) that ensures I1DEST isn't
3296 mentioned in any SETs in NEWPAT that are field assignments. */
3299 {
3302 }
3307 /* If the following substitution will modify I1SRC, make a copy of it
3308 for the case where it is substituted for I1DEST in I2PAT later. */
3312 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3313 copy of I1SRC each time we substitute it, in order to avoid creating
3314 self-referential RTL when we will be substituting I0SRC for I0DEST
3315 later. */
3320 /* Record whether I1's body now appears within I3's body. */
3322 }
3324 /* Likewise for I0 if we have it. */
3327 {
3334 {
3337 }
3339 /* If the following substitution will modify I0SRC, make a copy of it
3340 for the case where it is substituted for I0DEST in I1PAT later. */
3343 /* And a copy for I0DEST in I2PAT substitution. */
3352 }
3354 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3355 to count all the ways that I2SRC and I1SRC can be used. */
3366 /* Fail if we tried to make a new register. */
3368 /* Fail if we couldn't do something and have a CLOBBER. */
3370 /* Fail if this new pattern is a MULT and we didn't have one before
3371 at the outer level. */
3374 {
3377 }
3379 /* If the actions of the earlier insns must be kept
3380 in addition to substituting them into the latest one,
3381 we must make a new PARALLEL for the latest insn
3382 to hold additional the SETs. */
3385 {
3387 combine_extras++;
3390 {
3396 }
3397 else
3398 {
3403 }
3409 {
3415 }
3417 {
3426 }
3427 }
3429 validate_replacement:
3431 /* Note which hard regs this insn has as inputs. */
3434 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3435 consider splitting this pattern, we might need these clobbers. */
3438 {
3444 }
3446 /* We have recognized nothing yet. */
3449 /* See if this is a PARALLEL of two SETs where one SET's destination is
3450 a register that is unused and this isn't marked as an instruction that
3451 might trap in an EH region. In that case, we just need the other SET.
3452 We prefer this over the PARALLEL.
3454 This can occur when simplifying a divmod insn. We *must* test for this
3455 case here because the code below that splits two independent SETs doesn't
3456 handle this case correctly when it updates the register status.
3458 It's pointless doing this if we originally had two sets, one from
3459 i3, and one from i2. Combining then splitting the parallel results
3460 in the original i2 again plus an invalid insn (which we delete).
3461 The net effect is only to move instructions around, which makes
3462 debug info less accurate. */
3467 {
3478 {
3481 }
3490 {
3496 }
3500 }
3502 /* Is the result of combination a valid instruction? */
3506 /* If we were combining three insns and the result is a simple SET
3507 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3508 insns. There are two ways to do this. It can be split using a
3509 machine-specific method (like when you have an addition of a large
3510 constant) or by combine in the function find_split_point. */
3514 {
3518 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3519 use I2DEST as a scratch register will help. In the latter case,
3520 convert I2DEST to the mode of the source of NEWPAT if we can. */
3524 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3525 inputs of NEWPAT. */
3527 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3528 possible to try that as a scratch reg. This would require adding
3529 more code to make it work though. */
3532 {
3535 /* First try to split using the original register as a
3536 scratch register. */
3540 i2dest)));
3543 /* If that didn't work, try changing the mode of I2DEST if
3544 we can. */
3549 {
3551 rtx ni2dest;
3555 else
3556 {
3559 }
3561 parallel = (gen_rtx_PARALLEL
3565 ni2dest))));
3570 {
3578 }
3579 }
3582 }
3584 /* If recog_for_combine has discarded clobbers, try to use them
3585 again for the split. */
3587 {
3590 }
3593 {
3598 }
3602 {
3612 /* If I2 or I3 has multiple SETs, we won't know how to track
3613 register status, so don't use these insns. If I2's destination
3614 is used between I2 and I3, we also can't use these insns. */
3624 /* It is possible that both insns now set the destination of I3.
3625 If so, we must show an extra use of it. */
3628 {
3647 }
3648 }
3650 /* If we can split it and use I2DEST, go ahead and see if that
3651 helps things be recognized. Verify that none of the registers
3652 are set between I2 and I3. */
3656 /* We need I2DEST in the proper mode. If it is a hard register
3657 or the only use of a pseudo, we can change its mode.
3658 Make sure we don't change a hard register to have a mode that
3659 isn't valid for it, or change the number of registers. */
3666 /* We can't overwrite I2DEST if its value is still used by
3667 NEWPAT. */
3669 {
3678 /* *SPLIT may be part of I2SRC, so make sure we have the
3679 original expression around for later debug processing.
3680 We should not need I2SRC any more in other cases. */
3683 else
3686 /* Get NEWDEST as a register in the proper mode. We have already
3687 validated that we can do this. */
3689 {
3692 else
3693 {
3696 }
3697 }
3699 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3700 an ASHIFT. This can occur if it was inside a PLUS and hence
3701 appeared to be a memory address. This is a kludge. */
3706 {
3709 /* Update split_code because we may not have a multiply
3710 anymore. */
3712 }
3714 /* Similarly for (plus (mult FOO (const_int pow2))). */
3720 {
3724 /* Update split_code because we may not have a multiply
3725 anymore. */
3727 }
3729 #ifdef INSN_SCHEDULING
3730 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3731 be written as a ZERO_EXTEND. */
3733 {
3734 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3735 what it really is. */
3740 else
3743 }
3744 #endif
3746 /* Attempt to split binary operators using arithmetic identities. */
3750 {
3757 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3759 {
3764 }
3765 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3772 {
3778 /* Split both "((X op Y) op X) op Y" and
3779 "((X op Y) op Y) op X" as "T op T" where T is
3780 "X op Y". */
3783 {
3788 }
3789 /* Split "((X op X) op Y) op Y)" as "T op T" where
3790 T is "X op Y". */
3792 {
3798 }
3799 }
3800 }
3803 {
3806 }
3810 /* recog_for_combine might have added CLOBBERs to newi2pat.
3811 Make sure NEWPAT does not depend on the clobbered regs. */
3815 {
3818 {
3821 }
3822 }
3824 /* If the split point was a MULT and we didn't have one before,
3825 don't use one now. */
3828 }
3829 }
3831 /* Check for a case where we loaded from memory in a narrow mode and
3832 then sign extended it, but we need both registers. In that case,
3833 we have a PARALLEL with both loads from the same memory location.
3834 We can split this into a load from memory followed by a register-register
3835 copy. This saves at least one insn, more if register allocation can
3836 eliminate the copy.
3838 We cannot do this if the destination of the first assignment is a
3839 condition code register or cc0. We eliminate this case by making sure
3840 the SET_DEST and SET_SRC have the same mode.
3842 We cannot do this if the destination of the second assignment is
3843 a register that we have already assumed is zero-extended. Similarly
3844 for a SUBREG of such a register. */
3879 {
3880 rtx ni2dest;
3894 }
3896 /* Similarly, check for a case where we have a PARALLEL of two independent
3897 SETs but we started with three insns. In this case, we can do the sets
3898 as two separate insns. This case occurs when some SET allows two
3899 other insns to combine, but the destination of that SET is still live.
3901 Also do this if we started with two insns and (at least) one of the
3902 resulting sets is a noop; this noop will be deleted later. */
3921 {
3925 /* Normally, it doesn't matter which of the two is done first,
3926 but the one that references cc0 can't be the second, and
3927 one which uses any regs/memory set in between i2 and i3 can't
3928 be first. The PARALLEL might also have been pre-existing in i3,
3929 so we need to make sure that we won't wrongly hoist a SET to i2
3930 that would conflict with a death note present in there. */
3938 /* If I3 is a jump, ensure that set0 is a jump so that
3939 we do not create invalid RTL. */
3941 )
3942 {
3945 }
3953 /* If I3 is a jump, ensure that set1 is a jump so that
3954 we do not create invalid RTL. */
3956 )
3957 {
3960 }
3961 else
3962 {
3965 }
3970 {
3971 /* recog_for_combine might have added CLOBBERs to newi2pat.
3972 Make sure NEWPAT does not depend on the clobbered regs. */
3974 {
3977 {
3980 {
3983 }
3984 }
3985 }
3988 }
3989 }
3991 /* If it still isn't recognized, fail and change things back the way they
3992 were. */
3994 /* Is the result a reasonable ASM_OPERANDS? */
3996 {
3999 }
4001 /* If we had to change another insn, make sure it is valid also. */
4003 {
4011 {
4014 }
4015 }
4017 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4018 they are adjacent to each other or not. */
4020 {
4024 {
4027 }
4028 }
4030 /* Only allow this combination if insn_rtx_costs reports that the
4031 replacement instructions are cheaper than the originals. */
4033 {
4036 }
4039 {
4044 {
4049 /* Temporarily revert mode back. */
4053 {
4054 /* If we used i2dest as a scratch register with a
4055 different mode, substitute it for the original
4056 i2src while its original mode is temporarily
4057 restored, and then clear i2scratch so that we don't
4058 do it again later. */
4060 this_basic_block);
4062 /* Put back the new mode. */
4064 }
4065 else
4066 {
4071 {
4074 }
4075 else
4076 {
4083 }
4085 /* We're dealing with a reg that changed mode but not
4086 meaning, so we want to turn it into a subreg for
4087 the new mode. However, because of REG sharing and
4088 because its mode had already changed, we have to do
4089 it in two steps. First, replace any debug uses of
4090 reg, with its original mode temporarily restored,
4091 with this copy we have created; then, replace the
4092 copy with the SUBREG of the original shared reg,
4093 once again changed to the new mode. */
4095 this_basic_block);
4099 this_basic_block);
4100 }
4101 }
4102 }
4104 /* If we will be able to accept this, we have made a
4105 change to the destination of I3. This requires us to
4106 do a few adjustments. */
4109 {
4112 }
4114 /* We now know that we can do this combination. Merge the insns and
4115 update the status of registers and LOG_LINKS. */
4118 {
4123 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4124 ensure that they are still valid. Then add any non-duplicate
4125 notes added by recog_for_combine. */
4127 {
4137 }
4141 NULL_RTX);
4142 }
4145 {
4148 rtx ni2dest;
4150 /* I3 now uses what used to be its destination and which is now
4151 I2's destination. This requires us to do a few adjustments. */
4155 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4156 so we still will.
4158 However, some later insn might be using I2's dest and have
4159 a LOG_LINK pointing at I3. We must remove this link.
4160 The simplest way to remove the link is to point it at I1,
4161 which we know will be a NOTE. */
4163 /* newi2pat is usually a SET here; however, recog_for_combine might
4164 have added some clobbers. */
4167 else
4174 {
4176 {
4182 }
4183 }
4184 }
4186 {
4191 /* Compute which registers we expect to eliminate. newi2pat may be setting
4192 either i3dest or i2dest, so we must check it. */
4195 || !i2dest_killed
4197 /* For i1, we need to compute both local elimination and global
4198 elimination information with respect to newi2pat because i1dest
4199 may be the same as i3dest, in which case newi2pat may be setting
4200 i1dest. Global information is used when distributing REG_DEAD
4201 note for i2 and i3, in which case it does matter if newi2pat sets
4202 i1dest or not.
4204 Local information is used when distributing REG_DEAD note for i1,
4205 in which case it doesn't matter if newi2pat sets i1dest or not.
4206 See PR62151, if we have four insns combination:
4207 i0: r0 <- i0src
4208 i1: r1 <- i1src (using r0)
4209 REG_DEAD (r0)
4210 i2: r0 <- i2src (using r1)
4211 i3: r3 <- i3src (using r0)
4212 ix: using r0
4213 From i1's point of view, r0 is eliminated, no matter if it is set
4214 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4215 should be discarded.
4217 Note local information only affects cases in forms like "I1->I2->I3",
4218 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4219 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4220 i0dest anyway. */
4222 || !i1dest_killed
4227 /* Same case as i1. */
4234 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4235 clear them. */
4243 /* Ensure that we do not have something that should not be shared but
4244 occurs multiple times in the new insns. Check this by first
4245 resetting all the `used' flags and then copying anything is shared. */
4269 {
4276 {
4277 /* I2SRC must still be meaningful at this point. Some splitting
4278 operations can invalidate I2SRC, but those operations do not
4279 apply to calls. */
4282 }
4290 }
4295 /* We had one special case above where I2 had more than one set and
4296 we replaced a destination of one of those sets with the destination
4297 of I3. In that case, we have to update LOG_LINKS of insns later
4298 in this basic block. Note that this (expensive) case is rare.
4300 Also, in this case, we must pretend that all REG_NOTEs for I2
4301 actually came from I3, so that REG_UNUSED notes from I2 will be
4302 properly handled. */
4305 {
4314 temp_insn
4324 {
4329 }
4330 else
4333 }
4341 {
4344 this_basic_block);
4347 }
4348 else
4349 {
4352 this_basic_block);
4354 }
4357 {
4362 this_basic_block);
4364 }
4367 {
4372 this_basic_block);
4374 }
4376 /* Get death notes for everything that is now used in either I3 or
4377 I2 and used to die in a previous insn. If we built two new
4378 patterns, move from I1 to I2 then I2 to I3 so that we get the
4379 proper movement on registers that I2 modifies. */
4385 else
4391 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4408 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4409 know these are REG_UNUSED and want them to go to the desired insn,
4410 so we always pass it as i3. */
4414 NULL_RTX);
4418 NULL_RTX);
4420 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4421 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4422 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4423 in that case, it might delete I2. Similarly for I2 and I1.
4424 Show an additional death due to the REG_DEAD note we make here. If
4425 we discard it in distribute_notes, we will decrement it again. */
4428 {
4433 else
4436 }
4439 {
4444 else
4447 }
4450 {
4455 else
4458 }
4461 {
4466 else
4469 }
4477 {
4482 /* The insn that used to set this register doesn't exist, and
4483 this life of the register may not exist either. See if one of
4484 I3's links points to an insn that sets I2DEST. If it does,
4485 that is now the last known value for I2DEST. If we don't update
4486 this and I2 set the register to a value that depended on its old
4487 contents, we will get confused. If this insn is used, thing
4488 will be set correctly in combine_instructions. */
4496 /* If the reg formerly set in I2 died only once and that was in I3,
4497 zero its use count so it won't make `reload' do any work. */
4500 && ! i2dest_in_i2src
4503 }
4506 {
4519 && ! i1dest_in_i1src
4522 }
4525 {
4538 && ! i0dest_in_i0src
4541 }
4543 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4544 been made to this insn. The order is important, because newi2pat
4545 can affect nonzero_bits of newpat. */
4549 }
4552 {
4554 {
4557 }
4559 }
4562 {
4564 {
4567 }
4569 }
4572 {
4574 {
4577 }
4579 }
4582 {
4584 {
4587 }
4589 }
4592 {
4594 {
4597 }
4599 }
4601 /* Set new_direct_jump_p if a new return or simple jump instruction
4602 has been created. Adjust the CFG accordingly. */
4604 {
4608 }
4613 {
4616 }
4618 /* A noop might also need cleaning up of CFG, if it comes from the
4619 simplification of a jump. */
4624 {
4627 }
4634 {
4637 }
4639 combine_successes++;
4646 else
4648 }
4649 \f
4650 /* Get a marker for undoing to the current state. */
4654 {
4656 }
4658 /* Undo the modifications up to the marker. */
4660 static void
4662 {
4666 {
4671 {
4686 }
4690 }
4693 }
4695 /* Undo all the modifications recorded in undobuf. */
4697 static void
4699 {
4701 }
4703 /* We've committed to accepting the changes we made. Move all
4704 of the undos to the free list. */
4706 static void
4708 {
4712 {
4716 }
4718 }
4719 \f
4720 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4721 where we have an arithmetic expression and return that point. LOC will
4722 be inside INSN.
4724 try_combine will call this function to see if an insn can be split into
4725 two insns. */
4729 {
4738 /* First special-case some codes. */
4740 {
4742 #ifdef INSN_SCHEDULING
4743 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4744 point. */
4747 #endif
4751 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4752 using LO_SUM and HIGH. */
4755 {
4763 }
4765 /* If we have a PLUS whose second operand is a constant and the
4766 address is not valid, perhaps will can split it up using
4767 the machine-specific way to split large constants. We use
4768 the first pseudo-reg (one of the virtual regs) as a placeholder;
4769 it will not remain in the result. */
4774 {
4777 subst_insn);
4779 /* This should have produced two insns, each of which sets our
4780 placeholder. If the source of the second is a valid address,
4781 we can make put both sources together and make a split point
4782 in the middle. */
4795 && memory_address_addr_space_p
4798 {
4802 /* Replace the placeholder in SRC2 with SRC1. If we can
4803 find where in SRC2 it was placed, that can become our
4804 split point and we can replace this address with SRC2.
4805 Just try two obvious places. */
4816 {
4819 }
4820 }
4822 /* If that didn't work, perhaps the first operand is complex and
4823 needs to be computed separately, so make a split point there.
4824 This will occur on machines that just support REG + CONST
4825 and have a constant moved through some previous computation. */
4831 }
4833 /* If we have a PLUS whose first operand is complex, try computing it
4834 separately by making a split there. */
4845 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4846 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4847 we need to put the operand into a register. So split at that
4848 point. */
4858 /* See if we can split SET_SRC as it stands. */
4863 /* See if we can split SET_DEST as it stands. */
4868 /* See if this is a bitfield assignment with everything constant. If
4869 so, this is an IOR of an AND, so split it into that. */
4879 {
4885 unsigned HOST_WIDE_INT mask
4887 rtx or_mask;
4896 else
4897 {
4903 or_mask));
4904 }
4911 }
4913 /* Otherwise, see if this is an operation that we can split into two.
4914 If so, try to split that. */
4918 {
4920 /* If we are AND'ing with a large constant that is only a single
4921 bit and the result is only being used in a context where we
4922 need to know if it is zero or nonzero, replace it with a bit
4923 extraction. This will avoid the large constant, which might
4924 have taken more than one insn to make. If the constant were
4925 not a valid argument to the AND but took only one insn to make,
4926 this is no worse, but if it took more than one insn, it will
4927 be better. */
4937 {
4942 {
4945 }
4946 }
4950 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4951 is known to be on, this can be converted into a NEG of a shift. */
4957 {
4969 }
4975 /* We can't optimize if either mode is a partial integer
4976 mode as we don't know how many bits are significant
4977 in those modes. */
4991 {
4999 }
5004 }
5008 {
5011 /* For unsigned, we have a choice of a shift followed by an
5012 AND or two shifts. Use two shifts for field sizes where the
5013 constant might be too large. We assume here that we can
5014 always at least get 8-bit constants in an AND insn, which is
5015 true for every current RISC. */
5018 {
5019 unsigned HOST_WIDE_INT mask
5023 gen_rtx_LSHIFTRT
5031 }
5032 else
5033 {
5035 gen_rtx_fmt_ee
5046 }
5047 }
5049 /* See if this is a simple operation with a constant as the second
5050 operand. It might be that this constant is out of range and hence
5051 could be used as a split point. */
5059 /* Finally, see if this is a simple operation with its first operand
5060 not in a register. The operation might require this operand in a
5061 register, so return it as a split point. We can always do this
5062 because if the first operand were another operation, we would have
5063 already found it as a split point. */
5072 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5073 it is better to write this as (not (ior A B)) so we can split it.
5074 Similarly for IOR. */
5076 {
5084 }
5086 /* Many RISC machines have a large set of logical insns. If the
5087 second operand is a NOT, put it first so we will try to split the
5088 other operand first. */
5090 {
5094 }
5099 /* Canonicalization can produce (minus A (mult B C)), where C is a
5100 constant. It may be better to try splitting (plus (mult B -C) A)
5101 instead if this isn't a multiply by a power of two. */
5105 {
5113 mode)),
5116 }
5118 /* Split at a multiply-accumulate instruction. However if this is
5119 the SET_SRC, we likely do not have such an instruction and it's
5120 worthless to try this split. */
5129 }
5131 /* Otherwise, select our actions depending on our rtx class. */
5133 {
5139 /* fall through */
5147 /* fall through */
5149 /* Some machines have (and (shift ...) ...) insns. If X is not
5150 an AND, but XEXP (X, 0) is, use it as our split point. */
5160 /* Otherwise, we don't have a split point. */
5162 }
5163 }
5164 \f
5165 /* Throughout X, replace FROM with TO, and return the result.
5166 The result is TO if X is FROM;
5167 otherwise the result is X, but its contents may have been modified.
5168 If they were modified, a record was made in undobuf so that
5169 undo_all will (among other things) return X to its original state.
5171 If the number of changes necessary is too much to record to undo,
5172 the excess changes are not made, so the result is invalid.
5173 The changes already made can still be undone.
5174 undobuf.num_undo is incremented for such changes, so by testing that
5175 the caller can tell whether the result is valid.
5177 `n_occurrences' is incremented each time FROM is replaced.
5179 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5181 IN_COND is nonzero if we are at the top level of a condition.
5183 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5184 by copying if `n_occurrences' is nonzero. */
5186 static rtx
5188 {
5193 rtx new_rtx;
5195 /* Two expressions are equal if they are identical copies of a shared
5196 RTX or if they are both registers with the same register number
5197 and mode. */
5199 #define COMBINE_RTX_EQUAL_P(X,Y) \
5200 ((X) == (Y) \
5201 || (REG_P (X) && REG_P (Y) \
5202 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5204 /* Do not substitute into clobbers of regs -- this will never result in
5205 valid RTL. */
5210 {
5211 n_occurrences++;
5213 }
5215 /* If X and FROM are the same register but different modes, they
5216 will not have been seen as equal above. However, the log links code
5217 will make a LOG_LINKS entry for that case. If we do nothing, we
5218 will try to rerecognize our original insn and, when it succeeds,
5219 we will delete the feeding insn, which is incorrect.
5221 So force this insn not to match in this (rare) case. */
5226 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5227 of which may contain things that can be combined. */
5231 /* It is possible to have a subexpression appear twice in the insn.
5232 Suppose that FROM is a register that appears within TO.
5233 Then, after that subexpression has been scanned once by `subst',
5234 the second time it is scanned, TO may be found. If we were
5235 to scan TO here, we would find FROM within it and create a
5236 self-referent rtl structure which is completely wrong. */
5240 /* Parallel asm_operands need special attention because all of the
5241 inputs are shared across the arms. Furthermore, unsharing the
5242 rtl results in recognition failures. Failure to handle this case
5243 specially can result in circular rtl.
5245 Solve this by doing a normal pass across the first entry of the
5246 parallel, and only processing the SET_DESTs of the subsequent
5247 entries. Ug. */
5252 {
5255 /* If this substitution failed, this whole thing fails. */
5263 {
5269 {
5272 /* If this substitution failed, this whole thing fails. */
5278 }
5279 }
5280 }
5281 else
5282 {
5286 /* We don't need to process a SET_DEST that is a register, CC0,
5287 or PC, so set up to skip this common case. All other cases
5288 where we want to suppress replacing something inside a
5289 SET_SRC are handled via the IN_DEST operand. */
5296 /* Trying to simplify the operands of a widening MULT is not likely
5297 to create RTL matching a machine insn. */
5309 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5310 constant. */
5315 {
5317 {
5320 {
5322 {
5325 n_occurrences++;
5326 }
5327 else
5328 {
5330 unique_copy);
5332 /* If this substitution failed, this whole thing
5333 fails. */
5337 }
5340 }
5341 }
5343 {
5344 /* If this is a register being set, ignore it. */
5351 ;
5354 {
5355 /* In general, don't install a subreg involving two
5356 modes not tieable. It can worsen register
5357 allocation, and can even make invalid reload
5358 insns, since the reg inside may need to be copied
5359 from in the outside mode, and that may be invalid
5360 if it is an fp reg copied in integer mode.
5362 We allow two exceptions to this: It is valid if
5363 it is inside another SUBREG and the mode of that
5364 SUBREG and the mode of the inside of TO is
5365 tieable and it is valid if X is a SET that copies
5366 FROM to CC0. */
5374 && (!HAVE_cc0
5389 n_occurrences++;
5390 }
5391 else
5392 /* If we are in a SET_DEST, suppress most cases unless we
5393 have gone inside a MEM, in which case we want to
5394 simplify the address. We assume here that things that
5395 are actually part of the destination have their inner
5396 parts in the first expression. This is true for SUBREG,
5397 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5398 things aside from REG and MEM that should appear in a
5399 SET_DEST. */
5401 (((in_dest
5407 unique_copy);
5409 /* If we found that we will have to reject this combination,
5410 indicate that by returning the CLOBBER ourselves, rather than
5411 an expression containing it. This will speed things up as
5412 well as prevent accidents where two CLOBBERs are considered
5413 to be equal, thus producing an incorrect simplification. */
5419 {
5427 }
5430 {
5434 }
5435 else
5437 }
5438 }
5439 }
5441 /* Check if we are loading something from the constant pool via float
5442 extension; in this case we would undo compress_float_constant
5443 optimization and degenerate constant load to an immediate value. */
5447 {
5451 }
5453 /* Try to simplify X. If the simplification changed the code, it is likely
5454 that further simplification will help, so loop, but limit the number
5455 of repetitions that will be performed. */
5458 {
5459 /* If X is sufficiently simple, don't bother trying to do anything
5460 with it. */
5469 /* We no longer know the original mode of operand 0 since we
5470 have changed the form of X) */
5472 }
5475 }
5476 \f
5477 /* Simplify X, a piece of RTL. We just operate on the expression at the
5478 outer level; call `subst' to simplify recursively. Return the new
5479 expression.
5481 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5482 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5483 of a condition. */
5485 static rtx
5488 {
5491 rtx temp;
5494 /* If this is a commutative operation, put a constant last and a complex
5495 expression first. We don't need to do this for comparisons here. */
5498 {
5502 }
5504 /* Try to fold this expression in case we have constants that weren't
5505 present before. */
5508 {
5516 {
5519 {
5523 }
5526 }
5539 }
5542 {
5547 }
5549 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5550 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5551 things. Check for cases where both arms are testing the same
5552 condition.
5554 Don't do anything if all operands are very simple. */
5567 {
5572 /* If everything is a comparison, what we have is highly unlikely
5573 to be simpler, so don't use it. */
5576 {
5583 /* Simplify the alternative arms; this may collapse the true and
5584 false arms to store-flag values. Be careful to use copy_rtx
5585 here since true_rtx or false_rtx might share RTL with x as a
5586 result of the if_then_else_cond call above. */
5590 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5591 is unlikely to be simpler. */
5594 {
5597 /* Restarting if we generate a store-flag expression will cause
5598 us to loop. Just drop through in this case. */
5600 /* If the result values are STORE_FLAG_VALUE and zero, we can
5601 just make the comparison operation. */
5612 /* Likewise, we can make the negate of a comparison operation
5613 if the result values are - STORE_FLAG_VALUE and zero. */
5621 mode);
5632 mode);
5633 else
5636 mode,
5637 VOIDmode,
5638 cond,
5639 cop1),
5644 }
5645 }
5646 }
5648 /* First see if we can apply the inverse distributive law. */
5651 {
5655 }
5657 /* If CODE is an associative operation not otherwise handled, see if we
5658 can associate some operands. This can win if they are constants or
5659 if they are logically related (i.e. (a & b) & a). */
5665 {
5667 {
5671 rtx inner;
5673 /* Make sure we pass the constant operand if any as the second
5674 one if this is a commutative operation. */
5682 /* For commutative operations, try the other pair if that one
5683 didn't simplify. */
5685 {
5690 }
5694 }
5695 }
5697 /* A little bit of algebraic simplification here. */
5699 {
5701 /* Ensure that our address has any ASHIFTs converted to MULT in case
5702 address-recognizing predicates are called later. */
5711 /* See if this can be moved to simplify_subreg. */
5714 /* Don't call gen_lowpart if the inner mode
5715 is VOIDmode and we cannot simplify it, as SUBREG without
5716 inner mode is invalid. */
5723 {
5724 rtx temp;
5730 /* If op is known to have all lower bits zero, the result is zero. */
5740 }
5742 /* Don't change the mode of the MEM if that would change the meaning
5743 of the address. */
5750 /* Note that we cannot do any narrowing for non-constants since
5751 we might have been counting on using the fact that some bits were
5752 zero. We now do this in the SET. */
5759 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5760 replaced by (lshiftrt X C). This will convert
5761 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5769 /* If X has only a single bit that might be nonzero, say, bit I, convert
5770 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5771 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5772 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5773 or a SUBREG of one since we'd be making the expression more
5774 complex if it was just a register. */
5780 {
5781 rtx temp1 = simplify_shift_const
5787 /* If all we did was surround TEMP with the two shifts, we
5788 haven't improved anything, so don't use it. Otherwise,
5789 we are better off with TEMP1. */
5794 }
5798 /* We can't handle truncation to a partial integer mode here
5799 because we don't know the real bitsize of the partial
5800 integer mode. */
5809 /* We can truncate a constant value and return it. */
5813 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5814 whose value is a comparison can be replaced with a subreg if
5815 STORE_FLAG_VALUE permits. */
5824 /* (const (const X)) can become (const X). Do it this way rather than
5825 returning the inner CONST since CONST can be shared with a
5826 REG_EQUAL note. */
5832 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5833 can add in an offset. find_split_point will split this address up
5834 again if it doesn't match. */
5841 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5842 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5843 bit-field and can be replaced by either a sign_extend or a
5844 sign_extract. The `and' may be a zero_extend and the two
5845 <c>, -<c> constants may be reversed. */
5860 return simplify_shift_const
5867 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5868 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5869 the bitsize of the mode - 1. This allows simplification of
5870 "a = (b & 8) == 0;" */
5882 /* If we are adding two things that have no bits in common, convert
5883 the addition into an IOR. This will often be further simplified,
5884 for example in cases like ((a & 1) + (a & 2)), which can
5885 become a & 3. */
5890 {
5891 /* Try to simplify the expression further. */
5895 /* If we could, great. If not, do not go ahead with the IOR
5896 replacement, since PLUS appears in many special purpose
5897 address arithmetic instructions. */
5905 }
5907 /* Canonicalize x + x into x << 1. */
5916 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5917 (and <foo> (const_int pow2-1)) */
5927 /* If we have (mult (plus A B) C), apply the distributive law and then
5928 the inverse distributive law to see if things simplify. This
5929 occurs mostly in addresses, often when unrolling loops. */
5932 {
5936 }
5938 /* Try simplify a*(b/c) as (a*b)/c. */
5941 {
5947 }
5951 /* If this is a divide by a power of two, treat it as a shift if
5952 its first operand is a shift. */
5970 /* If the first operand is a condition code, we can't do anything
5971 with it. */
5975 {
5983 /* Simplify our comparison, if possible. */
5986 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5987 if only the low-order bit is possibly nonzero in X (such as when
5988 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5989 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5990 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5991 (plus X 1).
5993 Remove any ZERO_EXTRACT we made when thinking this was a
5994 comparison. It may now be simpler to use, e.g., an AND. If a
5995 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5996 the call to make_compound_operation in the SET case.
5998 Don't apply these optimizations if the caller would
5999 prefer a comparison rather than a value.
6000 E.g., for the condition in an IF_THEN_ELSE most targets need
6001 an explicit comparison. */
6004 ;
6020 {
6024 mode);
6025 }
6032 {
6036 const1_rtx);
6037 }
6045 {
6048 }
6050 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6051 those above. */
6053 ;
6069 {
6073 mode);
6074 }
6082 {
6086 mode);
6087 }
6089 /* If X is 0/1, (eq X 0) is X-1. */
6095 {
6098 }
6100 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6101 one bit that might be nonzero, we can convert (ne x 0) to
6102 (ashift x c) where C puts the bit in the sign bit. Remove any
6103 AND with STORE_FLAG_VALUE when we are done, since we are only
6104 going to test the sign bit. */
6111 {
6117 else
6119 }
6121 /* If the code changed, return a whole new comparison.
6122 We also need to avoid using SUBST in cases where
6123 simplify_comparison has widened a comparison with a CONST_INT,
6124 since in that case the wider CONST_INT may fail the sanity
6125 checks in do_SUBST. */
6132 /* Otherwise, keep this operation, but maybe change its operands.
6133 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6136 }
6146 /* If we are processing SET_DEST, we are done. */
6164 /* If this is a shift by a constant amount, simplify it. */
6172 (HOST_WIDE_INT_1U
6180 }
6183 }
6184 \f
6185 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6187 static rtx
6189 {
6196 rtx temp;
6199 rtx reversed;
6201 /* Simplify storing of the truth value. */
6206 /* Also when the truth value has to be reversed. */
6212 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6213 in it is being compared against certain values. Get the true and false
6214 comparisons and see if that says anything about the value of each arm. */
6220 {
6221 HOST_WIDE_INT nzb;
6227 /* If FALSE_CODE is EQ, swap the codes and arms. */
6230 {
6233 }
6235 /* If we are comparing against zero and the expression being tested has
6236 only a single bit that might be nonzero, that is its value when it is
6237 not equal to zero. Similarly if it is known to be -1 or 0. */
6241 {
6244 }
6248 {
6251 }
6253 /* Now simplify an arm if we know the value of the register in the
6254 branch and it is used in the arm. Be careful due to the potential
6255 of locally-shared RTL. */
6272 }
6274 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6275 reversed, do so to avoid needing two sets of patterns for
6276 subtract-and-branch insns. Similarly if we have a constant in the true
6277 arm, the false arm is the same as the first operand of the comparison, or
6278 the false arm is more complicated than the true arm. */
6291 {
6300 /* It is possible that the conditional has been simplified out. */
6303 }
6305 /* If the two arms are identical, we don't need the comparison. */
6310 /* Convert a == b ? b : a to "a". */
6322 /* Look for cases where we have (abs x) or (neg (abs X)). */
6325 && comparison_p
6332 {
6338 return
6341 mode);
6344 }
6346 /* Look for MIN or MAX. */
6349 && comparison_p
6354 {
6369 }
6371 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6372 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6373 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6374 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6375 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6376 neither 1 or -1, but it isn't worth checking for. */
6379 && comparison_p
6382 {
6398 /* If an identity-zero op is commutative, check whether there
6399 would be a match if we swapped the operands. */
6419 {
6423 }
6435 {
6439 }
6455 {
6459 }
6471 {
6475 }
6478 {
6484 const_true_rtx));
6492 }
6493 }
6495 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6496 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6497 negation of a single bit, we can convert this operation to a shift. We
6498 can actually do this more generally, but it doesn't seem worth it. */
6507 return
6511 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6521 }
6522 \f
6523 /* Simplify X, a SET expression. Return the new expression. */
6525 static rtx
6527 {
6530 machine_mode mode
6535 /* (set (pc) (return)) gets written as (return). */
6539 /* Now that we know for sure which bits of SRC we are using, see if we can
6540 simplify the expression for the object knowing that we only need the
6541 low-order bits. */
6544 {
6547 }
6549 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6550 the comparison result and try to simplify it unless we already have used
6551 undobuf.other_insn. */
6559 {
6568 {
6571 {
6574 }
6575 }
6576 else
6584 {
6588 }
6589 else
6590 {
6595 /* Attempt to simplify CC user. */
6597 {
6601 }
6603 /* Convert X into a no-op move. */
6607 }
6609 /* Simplify our comparison, if possible. */
6612 #ifdef SELECT_CC_MODE
6613 /* If this machine has CC modes other than CCmode, check to see if we
6614 need to use a different CC mode here. */
6623 else
6626 /* If the mode changed, we have to change SET_DEST, the mode in the
6627 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6628 a hard register, just build new versions with the proper mode. If it
6629 is a pseudo, we lose unless it is only time we set the pseudo, in
6630 which case we can safely change its mode. */
6632 {
6634 {
6636 rtx new_dest;
6640 else
6641 {
6644 }
6651 }
6652 }
6655 /* If the code changed, we have to build a new comparison in
6656 undobuf.other_insn. */
6658 {
6667 /* If the only change we made was to change an EQ into an NE or
6668 vice versa, OP0 has only one bit that might be nonzero, and OP1
6669 is zero, check if changing the user of the condition code will
6670 produce a valid insn. If it won't, we can keep the original code
6671 in that insn by surrounding our operation with an XOR. */
6678 {
6683 {
6690 }
6691 }
6692 }
6697 /* Don't generate a compare of a CC with 0, just use that CC. */
6699 {
6702 }
6703 /* Otherwise, if we didn't previously have the same COMPARE we
6704 want, create it from scratch. */
6707 {
6710 }
6711 }
6712 else
6713 {
6714 /* Get SET_SRC in a form where we have placed back any
6715 compound expressions. Then do the checks below. */
6718 }
6720 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6721 and X being a REG or (subreg (reg)), we may be able to convert this to
6722 (set (subreg:m2 x) (op)).
6724 We can always do this if M1 is narrower than M2 because that means that
6725 we only care about the low bits of the result.
6727 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6728 perform a narrower operation than requested since the high-order bits will
6729 be undefined. On machine where it is defined, this transformation is safe
6730 as long as M1 and M2 have the same number of words. */
6738 && (WORD_REGISTER_OPERATIONS
6741 #ifdef CANNOT_CHANGE_MODE_CLASS
6746 #endif
6750 {
6753 dest));
6757 }
6759 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6760 in SRC. */
6766 {
6770 /* Here we make sure that we don't have a sign bit on. */
6773 {
6776 }
6777 }
6779 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6780 would require a paradoxical subreg. Replace the subreg with a
6781 zero_extend to avoid the reload that would otherwise be required. */
6789 {
6795 }
6797 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6798 are comparing an item known to be 0 or -1 against 0, use a logical
6799 operation instead. Check for one of the arms being an IOR of the other
6800 arm with some value. We compute three terms to be IOR'ed together. In
6801 practice, at most two will be nonzero. Then we do the IOR's. */
6809 && (!HAVE_conditional_move
6815 {
6841 false_rtx);
6847 term3));
6850 }
6852 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6853 whole thing fail. */
6858 else
6859 /* Convert this into a field assignment operation, if possible. */
6861 }
6862 \f
6863 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6864 result. */
6866 static rtx
6868 {
6874 {
6876 /* We can call simplify_and_const_int only if we don't lose
6877 any (sign) bits when converting INTVAL (op1) to
6878 "unsigned HOST_WIDE_INT". */
6882 {
6889 }
6891 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6892 apply the distributive law and then the inverse distributive
6893 law to see if things simplify. */
6895 {
6899 }
6901 {
6905 }
6909 /* If we have (ior (and A B) C), apply the distributive law and then
6910 the inverse distributive law to see if things simplify. */
6913 {
6917 }
6920 {
6924 }
6929 }
6932 }
6933 \f
6934 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6935 operations" because they can be replaced with two more basic operations.
6936 ZERO_EXTEND is also considered "compound" because it can be replaced with
6937 an AND operation, which is simpler, though only one operation.
6939 The function expand_compound_operation is called with an rtx expression
6940 and will convert it to the appropriate shifts and AND operations,
6941 simplifying at each stage.
6943 The function make_compound_operation is called to convert an expression
6944 consisting of shifts and ANDs into the equivalent compound expression.
6945 It is the inverse of this function, loosely speaking. */
6947 static rtx
6949 {
6953 rtx tem;
6956 {
6959 /* FALLTHRU */
6961 /* We can't necessarily use a const_int for a multiword mode;
6962 it depends on implicitly extending the value.
6963 Since we don't know the right way to extend it,
6964 we can't tell whether the implicit way is right.
6966 Even for a mode that is no wider than a const_int,
6967 we can't win, because we need to sign extend one of its bits through
6968 the rest of it, and we don't know which bit. */
6972 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6973 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6974 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6975 reloaded. If not for that, MEM's would very rarely be safe.
6977 Reject MODEs bigger than a word, because we might not be able
6978 to reference a two-register group starting with an arbitrary register
6979 (and currently gen_lowpart might crash for a SUBREG). */
6984 /* Reject MODEs that aren't scalar integers because turning vector
6985 or complex modes into shifts causes problems. */
6991 /* If the inner object has VOIDmode (the only way this can happen
6992 is if it is an ASM_OPERANDS), we can't do anything since we don't
6993 know how much masking to do. */
7002 /* fall through */
7005 /* If the operand is a CLOBBER, just return it. */
7014 /* Reject MODEs that aren't scalar integers because turning vector
7015 or complex modes into shifts causes problems. */
7023 /* This should stay within the object being extracted, fail otherwise. */
7034 }
7035 /* Convert sign extension to zero extension, if we know that the high
7036 bit is not set, as this is easier to optimize. It will be converted
7037 back to cheaper alternative in make_extraction. */
7045 {
7050 /* Make sure this is a profitable operation. */
7057 else
7059 }
7061 /* We can optimize some special cases of ZERO_EXTEND. */
7063 {
7064 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7065 know that the last value didn't have any inappropriate bits
7066 set. */
7074 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7083 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7084 is a comparison and STORE_FLAG_VALUE permits. This is like
7085 the first case, but it works even when GET_MODE (x) is larger
7086 than HOST_WIDE_INT. */
7095 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7105 }
7107 /* If we reach here, we want to return a pair of shifts. The inner
7108 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7109 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7110 logical depending on the value of UNSIGNEDP.
7112 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7113 converted into an AND of a shift.
7115 We must check for the case where the left shift would have a negative
7116 count. This can happen in a case like (x >> 31) & 255 on machines
7117 that can't shift by a constant. On those machines, we would first
7118 combine the shift with the AND to produce a variable-position
7119 extraction. Then the constant of 31 would be substituted in
7120 to produce such a position. */
7124 {
7133 }
7140 else
7141 /* Any other cases we can't handle. */
7144 /* If we couldn't do this for some reason, return the original
7145 expression. */
7150 }
7151 \f
7152 /* X is a SET which contains an assignment of one object into
7153 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7154 or certain SUBREGS). If possible, convert it into a series of
7155 logical operations.
7157 We half-heartedly support variable positions, but do not at all
7158 support variable lengths. */
7160 static const_rtx
7162 {
7163 rtx inner;
7167 machine_mode compute_mode;
7169 /* Loop until we find something we can't simplify. */
7171 {
7174 {
7178 }
7181 {
7186 /* A constant position should stay within the width of INNER. */
7192 {
7200 /* If position is ADJUST - X, new position is X. */
7202 else
7203 {
7208 pos);
7209 }
7210 }
7211 }
7213 /* A SUBREG between two modes that occupy the same numbers of words
7214 can be done by moving the SUBREG to the source. */
7216 /* We need SUBREGs to compute nonzero_bits properly. */
7217 && nonzero_sign_valid
7222 {
7224 gen_lowpart
7228 }
7229 else
7237 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7239 {
7240 machine_mode imode;
7242 /* Don't do anything for vector or complex integral types. */
7246 /* Try to find an integral mode to pun with. */
7253 }
7255 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7259 /* Don't try to compute in too wide unsupported modes. */
7263 /* Now compute the equivalent expression. Make a copy of INNER
7264 for the SET_DEST in case it is a MEM into which we will substitute;
7265 we don't want shared RTL in that case. */
7267 compute_mode);
7271 compute_mode,
7273 compute_mode),
7274 inner);
7279 mask),
7280 pos);
7285 }
7288 }
7289 \f
7290 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7291 it is an RTX that represents the (variable) starting position; otherwise,
7292 POS is the (constant) starting bit position. Both are counted from the LSB.
7294 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7296 IN_DEST is nonzero if this is a reference in the destination of a SET.
7297 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7298 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7299 be used.
7301 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7302 ZERO_EXTRACT should be built even for bits starting at bit 0.
7304 MODE is the desired mode of the result (if IN_DEST == 0).
7306 The result is an RTX for the extraction or NULL_RTX if the target
7307 can't handle it. */
7309 static rtx
7313 {
7314 /* This mode describes the size of the storage area
7315 to fetch the overall value from. Within that, we
7316 ignore the POS lowest bits, etc. */
7318 machine_mode inner_mode;
7319 machine_mode wanted_inner_mode;
7326 HOST_WIDE_INT orig_pos;
7332 {
7333 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7334 consider just the QI as the memory to extract from.
7335 The subreg adds or removes high bits; its mode is
7336 irrelevant to the meaning of this extraction,
7337 since POS and LEN count from the lsb. */
7341 }
7346 {
7347 /* We're extracting the least significant bits of an rtx
7348 (ashift X (const_int C)), where LEN > C. Extract the
7349 least significant (LEN - C) bits of X, giving an rtx
7350 whose mode is MODE, then shift it left C times. */
7356 }
7362 /* See if this can be done without an extraction. We never can if the
7363 width of the field is not the same as that of some integer mode. For
7364 registers, we can only avoid the extraction if the position is at the
7365 low-order bit and this is either not in the destination or we have the
7366 appropriate STRICT_LOW_PART operation available.
7368 For MEM, we can avoid an extract if the field starts on an appropriate
7369 boundary and we can change the mode of the memory reference. */
7378 && (! in_dest
7382 && (pos
7385 /* We can't do this if we are widening INNER_MODE (it
7386 may not be aligned, for one thing). */
7392 {
7393 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7394 field. If the original and current mode are the same, we need not
7395 adjust the offset. Otherwise, we do if bytes big endian.
7397 If INNER is not a MEM, get a piece consisting of just the field
7398 of interest (in this case POS % BITS_PER_WORD must be 0). */
7401 {
7402 HOST_WIDE_INT offset;
7404 /* POS counts from lsb, but make OFFSET count in memory order. */
7407 else
7411 }
7413 {
7415 {
7416 /* We can't call gen_lowpart in a DEST since we
7417 always want a SUBREG (see below) and it would sometimes
7418 return a new hard register. */
7420 {
7435 /* Avoid creating invalid subregs, for example when
7436 simplifying (x>>32)&255. */
7441 }
7442 else
7444 }
7445 else
7447 }
7448 else
7450 len >= HOST_BITS_PER_WIDE_INT
7451 ? HOST_WIDE_INT_M1U
7455 /* If this extraction is going into the destination of a SET,
7456 make a STRICT_LOW_PART unless we made a MEM. */
7471 /* If we know that no extraneous bits are set, and that the high
7472 bit is not set, convert the extraction to the cheaper of
7473 sign and zero extension, that are equivalent in these cases. */
7479 {
7483 /* Prefer ZERO_EXTENSION, since it gives more information to
7484 backends. */
7489 }
7491 /* Otherwise, sign- or zero-extend unless we already are in the
7492 proper mode. */
7496 }
7498 /* Unless this is a COMPARE or we have a funny memory reference,
7499 don't do anything with zero-extending field extracts starting at
7500 the low-order bit since they are simple AND operations. */
7505 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7506 if the position is not a constant and the length is not 1. In all
7507 other cases, we would only be going outside our object in cases when
7508 an original shift would have been undefined. */
7517 /* If INNER is not from memory, we want it to have the mode of a register
7518 extraction pattern's structure operand, or word_mode if there is no
7519 such pattern. The same applies to extraction_mode and pos_mode
7520 and their respective operands.
7522 For memory, assume that the desired extraction_mode and pos_mode
7523 are the same as for a register operation, since at present we don't
7524 have named patterns for aligned memory structures. */
7528 {
7532 }
7534 /* Never narrow an object, since that might not be safe. */
7542 else
7543 {
7544 /* Be careful not to go beyond the extracted object and maintain the
7545 natural alignment of the memory. */
7549 {
7552 }
7553 }
7558 {
7559 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7560 BITS_BIG_ENDIAN style. If position is constant, compute new
7561 position. Otherwise, build subtraction.
7562 Note that POS is relative to the mode of the original argument.
7563 If it's a MEM we need to recompute POS relative to that.
7564 However, if we're extracting from (or inserting into) a register,
7565 we want to recompute POS relative to wanted_inner_mode. */
7572 else
7573 pos_rtx
7576 pos_rtx);
7577 /* POS may be less than 0 now, but we check for that below.
7578 Note that it can only be less than 0 if !MEM_P (inner). */
7579 }
7581 /* If INNER has a wider mode, and this is a constant extraction, try to
7582 make it smaller and adjust the byte to point to the byte containing
7583 the value. */
7586 && ! pos_rtx
7591 {
7594 /* The computations below will be correct if the machine is big
7595 endian in both bits and bytes or little endian in bits and bytes.
7596 If it is mixed, we must adjust. */
7598 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7599 adjust OFFSET to compensate. */
7604 /* We can now move to the desired byte. */
7615 }
7617 /* If INNER is not memory, get it into the proper mode. If we are changing
7618 its mode, POS must be a constant and smaller than the size of the new
7619 mode. */
7621 {
7622 /* On the LHS, don't create paradoxical subregs implicitely truncating
7623 the register unless TRULY_NOOP_TRUNCATION. */
7626 wanted_inner_mode))
7638 pos_rtx
7640 ? HOST_WIDE_INT_M1U
7644 }
7646 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7647 have to zero extend. Otherwise, we can just use a SUBREG. */
7650 {
7654 /* If we know that no extraneous bits are set, and that the high
7655 bit is not set, convert extraction to cheaper one - either
7656 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7657 cases. */
7665 {
7669 /* Prefer ZERO_EXTENSION, since it gives more information to
7670 backends. */
7674 }
7676 }
7678 /* Make POS_RTX unless we already have it and it is correct. If we don't
7679 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7680 be a CONST_INT. */
7687 /* Make the required operation. See if we can use existing rtx. */
7694 }
7695 \f
7696 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7697 with any other operations in X. Return X without that shift if so. */
7699 static rtx
7701 {
7704 rtx tem;
7707 {
7709 /* This is the shift itself. If it is wide enough, we will return
7710 either the value being shifted if the shift count is equal to
7711 COUNT or a shift for the difference. */
7725 /* If we can safely shift this constant and we find the inner shift,
7726 make a new operation. */
7731 {
7735 }
7740 }
7743 }
7744 \f
7745 /* Look at the expression rooted at X. Look for expressions
7746 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7747 Form these expressions.
7749 Return the new rtx, usually just X.
7751 Also, for machines like the VAX that don't have logical shift insns,
7752 try to convert logical to arithmetic shift operations in cases where
7753 they are equivalent. This undoes the canonicalizations to logical
7754 shifts done elsewhere.
7756 We try, as much as possible, to re-use rtl expressions to save memory.
7758 IN_CODE says what kind of expression we are processing. Normally, it is
7759 SET. In a memory address it is MEM. When processing the arguments of
7760 a comparison or a COMPARE against zero, it is COMPARE. */
7762 rtx
7764 {
7772 rtx tem;
7775 /* PR rtl-optimization/70944. */
7779 /* Select the code to be used in recursive calls. Once we are inside an
7780 address, we stay there. If we have a comparison, set to COMPARE,
7781 but once inside, go back to our default of SET. */
7788 /* Process depending on the code of this operation. If NEW is set
7789 nonzero, it will be returned. */
7792 {
7794 /* Convert shifts by constants into multiplications if inside
7795 an address. */
7800 {
7806 {
7809 }
7812 }
7822 {
7826 }
7829 {
7833 mode));
7835 }
7836 else
7837 {
7841 }
7852 {
7856 }
7859 {
7863 mode));
7865 }
7866 else
7867 {
7871 }
7875 /* If the second operand is not a constant, we can't do anything
7876 with it. */
7880 /* If the constant is a power of two minus one and the first operand
7881 is a logical right shift, make an extraction. */
7884 {
7888 }
7890 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7895 {
7904 {
7905 /* If we narrowed the mode when dropping the subreg, then
7906 we must zero-extend to keep the semantics of the AND. */
7908 ;
7912 else
7914 }
7916 /* If that didn't give anything, see if the AND simplifies on
7917 its own. */
7919 {
7923 }
7924 }
7925 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7931 {
7932 /* Apply the distributive law, and then try to make extractions. */
7939 }
7941 /* If we are have (and (rotate X C) M) and C is larger than the number
7942 of bits in M, this is an extraction. */
7948 {
7954 }
7956 /* On machines without logical shifts, if the operand of the AND is
7957 a logical shift and our mask turns off all the propagated sign
7958 bits, we can replace the logical shift with an arithmetic shift. */
7966 {
7973 make_compound_operation
7976 }
7978 /* If the constant is one less than a power of two, this might be
7979 representable by an extraction even if no shift is present.
7980 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7981 we are in a COMPARE. */
7985 next_code),
7988 /* If we are in a comparison and this is an AND with a power of two,
7989 convert this into the appropriate bit extract. */
7994 next_code),
7997 /* If the one operand is a paradoxical subreg of a register or memory and
7998 the constant (limited to the smaller mode) has only zero bits where
7999 the sub expression has known zero bits, this can be expressed as
8000 a zero_extend. */
8002 {
8003 rtx sub;
8009 {
8013 /* original AND constant with all the known zero bits set */
8016 {
8021 }
8022 }
8023 }
8028 /* If the sign bit is known to be zero, replace this with an
8029 arithmetic shift. */
8034 {
8037 next_code),
8040 }
8042 /* fall through */
8048 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8049 this is a SIGN_EXTRACT. */
8056 {
8063 }
8065 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8066 If so, try to merge the shifts into a SIGN_EXTEND. We could
8067 also do this for some cases of SIGN_EXTRACT, but it doesn't
8068 seem worth the effort; the case checked for occurs on Alpha. */
8085 /* Call ourselves recursively on the inner expression. If we are
8086 narrowing the object and it has a different RTL code from
8087 what it originally did, do this SUBREG as a force_to_mode. */
8088 {
8092 /* If in_code is COMPARE, it isn't always safe to pass it through
8093 to the recursive make_compound_operation call. */
8097 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8098 is (const_int 0), rather than
8099 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8109 simplified
8117 {
8118 rtx newer
8121 /* If we have something other than a SUBREG, we might have
8122 done an expansion, so rerun ourselves. */
8126 /* force_to_mode can expand compounds. If it just re-expanded the
8127 compound, use gen_lowpart to convert to the desired mode. */
8129 /* Likewise if it re-expanded the compound only partially.
8130 This happens for SUBREG of ZERO_EXTRACT if they extract
8131 the same number of bits. */
8140 }
8144 }
8149 }
8152 {
8155 }
8157 /* Now recursively process each operand of this operation. We need to
8158 handle ZERO_EXTEND specially so that we don't lose track of the
8159 inner mode. */
8161 {
8169 }
8174 {
8177 }
8180 {
8183 }
8185 maybe_swap:
8186 /* If this is a commutative operation, the changes to the operands
8187 may have made it noncanonical. */
8190 {
8194 }
8197 }
8198 \f
8199 /* Given M see if it is a value that would select a field of bits
8200 within an item, but not the entire word. Return -1 if not.
8201 Otherwise, return the starting position of the field, where 0 is the
8202 low-order bit.
8204 *PLEN is set to the length of the field. */
8206 static int
8208 {
8209 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8214 /* Now shift off the low-order zero bits and see if we have a
8215 power of two minus 1. */
8223 }
8224 \f
8225 /* If X refers to a register that equals REG in value, replace these
8226 references with REG. */
8227 static rtx
8229 {
8237 {
8270 /* FALLTHRU */
8274 {
8278 else
8280 }
8282 /* fall through */
8289 {
8292 {
8294 {
8297 }
8299 }
8300 }
8302 {
8305 {
8308 {
8310 {
8313 }
8315 }
8316 }
8317 }
8320 }
8323 }
8325 /* Return X converted to MODE. If the value is already truncated to
8326 MODE we can just return a subreg even though in the general case we
8327 would need an explicit truncation. */
8329 static rtx
8331 {
8336 {
8337 /* Bit-cast X into an integer mode. */
8342 }
8345 }
8347 /* See if X can be simplified knowing that we will only refer to it in
8348 MODE and will only refer to those bits that are nonzero in MASK.
8349 If other bits are being computed or if masking operations are done
8350 that select a superset of the bits in MASK, they can sometimes be
8351 ignored.
8353 Return a possibly simplified expression, but always convert X to
8354 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8356 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8357 are all off in X. This is used when X will be complemented, by either
8358 NOT, NEG, or XOR. */
8360 static rtx
8363 {
8366 machine_mode op_mode;
8370 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8371 code below will do the wrong thing since the mode of such an
8372 expression is VOIDmode.
8374 Also do nothing if X is a CLOBBER; this can happen if X was
8375 the return value from a call to gen_lowpart. */
8379 /* We want to perform the operation in its present mode unless we know
8380 that the operation is valid in MODE, in which case we do the operation
8381 in MODE. */
8386 /* It is not valid to do a right-shift in a narrower mode
8387 than the one it came in with. */
8392 /* Truncate MASK to fit OP_MODE. */
8396 /* When we have an arithmetic operation, or a shift whose count we
8397 do not know, we need to assume that all bits up to the highest-order
8398 bit in MASK will be needed. This is how we form such a mask. */
8401 else
8405 /* Determine what bits of X are guaranteed to be (non)zero. */
8408 /* If none of the bits in X are needed, return a zero. */
8412 /* If X is a CONST_INT, return a new one. Do this here since the
8413 test below will fail. */
8415 {
8418 else
8419 {
8422 }
8423 }
8425 /* If X is narrower than MODE and we want all the bits in X's mode, just
8426 get X in the proper mode. */
8431 /* We can ignore the effect of a SUBREG if it narrows the mode or
8432 if the constant masks to zero all the bits the mode doesn't have. */
8442 /* The arithmetic simplifications here only work for scalar integer modes. */
8447 {
8449 /* If X is a (clobber (const_int)), return it since we know we are
8450 generating something that won't match. */
8463 /* Similarly for a truncate. */
8467 /* If this is an AND with a constant, convert it into an AND
8468 whose constant is the AND of that constant with MASK. If it
8469 remains an AND of MASK, delete it since it is redundant. */
8472 {
8476 /* If X is still an AND, see if it is an AND with a mask that
8477 is just some low-order bits. If so, and it is MASK, we don't
8478 need it. */
8485 /* If it remains an AND, try making another AND with the bits
8486 in the mode mask that aren't in MASK turned on. If the
8487 constant in the AND is wide enough, this might make a
8488 cheaper constant. */
8493 {
8494 unsigned HOST_WIDE_INT cval
8497 rtx y;
8504 }
8507 }
8512 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8513 low-order bits (as in an alignment operation) and FOO is already
8514 aligned to that boundary, mask C1 to that boundary as well.
8515 This may eliminate that PLUS and, later, the AND. */
8517 {
8521 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8522 number, sign extend it. */
8535 }
8537 /* fall through */
8540 /* Substituting into the operands of a widening MULT is not likely to
8541 create RTL matching a machine insn. */
8551 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8552 most significant bit in MASK since carries from those bits will
8553 affect the bits we are interested in. */
8558 /* If X is (minus C Y) where C's least set bit is larger than any bit
8559 in the mask, then we may replace with (neg Y). */
8562 {
8566 }
8568 /* Similarly, if C contains every bit in the fuller_mask, then we may
8569 replace with (not Y). */
8572 {
8576 }
8583 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8584 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8585 operation which may be a bitfield extraction. Ensure that the
8586 constant we form is not wider than the mode of X. */
8598 {
8607 }
8609 binop:
8610 /* For most binary operations, just propagate into the operation and
8611 change the mode if we have an operation of that mode. */
8616 /* If we ended up truncating both operands, truncate the result of the
8617 operation instead. */
8620 {
8623 }
8633 /* For left shifts, do the same, but just for the first operand.
8634 However, we cannot do anything with shifts where we cannot
8635 guarantee that the counts are smaller than the size of the mode
8636 because such a count will have a different meaning in a
8637 wider mode. */
8647 /* If the shift count is a constant and we can do arithmetic in
8648 the mode of the shift, refine which bits we need. Otherwise, use the
8649 conservative form of the mask. */
8655 else
8667 /* Here we can only do something if the shift count is a constant,
8668 this shift constant is valid for the host, and we can do arithmetic
8669 in OP_MODE. */
8675 {
8679 /* Select the mask of the bits we need for the shift operand. */
8682 /* We can only change the mode of the shift if we can do arithmetic
8683 in the mode of the shift and INNER_MASK is no wider than the
8684 width of X's mode. */
8692 }
8694 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8695 shift and AND produces only copies of the sign bit (C2 is one less
8696 than a power of two), we can do this with just a shift. */
8700 /* The shift puts one of the sign bit copies in the least significant
8701 bit. */
8706 /* Number of bits left after the shift must be more than the mask
8707 needs. */
8710 /* Must be more sign bit copies than the mask needs. */
8720 /* If we are just looking for the sign bit, we don't need this shift at
8721 all, even if it has a variable count. */
8725 /* If this is a shift by a constant, get a mask that contains those bits
8726 that are not copies of the sign bit. We then have two cases: If
8727 MASK only includes those bits, this can be a logical shift, which may
8728 allow simplifications. If MASK is a single-bit field not within
8729 those bits, we are requesting a copy of the sign bit and hence can
8730 shift the sign bit to the appropriate location. */
8734 {
8737 /* If the considered data is wider than HOST_WIDE_INT, we can't
8738 represent a mask for all its bits in a single scalar.
8739 But we only care about the lower bits, so calculate these. */
8742 {
8745 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8746 is the number of bits a full-width mask would have set.
8747 We need only shift if these are fewer than nonzero can
8748 hold. If not, we must keep all bits set in nonzero. */
8753 + HOST_BITS_PER_WIDE_INT
8755 }
8756 else
8757 {
8760 }
8763 {
8768 }
8771 {
8772 x = simplify_shift_const
8778 }
8779 }
8781 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8782 even if the shift count isn't a constant. */
8787 shiftrt:
8789 /* If this is a zero- or sign-extension operation that just affects bits
8790 we don't care about, remove it. Be sure the call above returned
8791 something that is still a shift. */
8801 next_select);
8807 /* If the shift count is constant and we can do computations
8808 in the mode of X, compute where the bits we care about are.
8809 Otherwise, we can't do anything. Don't change the mode of
8810 the shift or propagate MODE into the shift, though. */
8813 {
8823 }
8827 /* If we just want the low-order bit, the NEG isn't needed since it
8828 won't change the low-order bit. */
8832 /* We need any bits less significant than the most significant bit in
8833 MASK since carries from those bits will affect the bits we are
8834 interested in. */
8839 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8840 same as the XOR case above. Ensure that the constant we form is not
8841 wider than the mode of X. */
8849 {
8858 }
8860 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8861 use the full mask inside the NOT. */
8864 unop:
8867 next_select));
8873 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8874 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8875 which is equal to STORE_FLAG_VALUE. */
8887 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8888 written in a narrower mode. We play it safe and do not do so. */
8904 }
8906 /* Ensure we return a value of the proper mode. */
8908 }
8909 \f
8910 /* Return nonzero if X is an expression that has one of two values depending on
8911 whether some other value is zero or nonzero. In that case, we return the
8912 value that is being tested, *PTRUE is set to the value if the rtx being
8913 returned has a nonzero value, and *PFALSE is set to the other alternative.
8915 If we return zero, we set *PTRUE and *PFALSE to X. */
8917 static rtx
8919 {
8925 /* If we are comparing a value against zero, we are done. */
8928 {
8932 }
8934 /* If this is a unary operation whose operand has one of two values, apply
8935 our opcode to compute those values. */
8938 {
8943 }
8945 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8946 make can't possibly match and would suppress other optimizations. */
8948 ;
8950 /* If this is a binary operation, see if either side has only one of two
8951 values. If either one does or if both do and they are conditional on
8952 the same value, compute the new true and false values. */
8954 {
8960 {
8961 /* If if_then_else_cond returned zero, then true/false are the
8962 same rtl. We must copy one of them to prevent invalid rtl
8963 sharing. */
8970 {
8975 }
8976 else
8977 {
8980 }
8983 }
8985 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8986 operands is zero when the other is nonzero, and vice-versa,
8987 and STORE_FLAG_VALUE is 1 or -1. */
8993 {
9010 {
9017 const_true_rtx);
9019 }
9020 }
9022 /* Similarly for MULT, AND and UMIN, except that for these the result
9023 is always zero. */
9027 {
9041 {
9044 }
9045 }
9046 }
9049 {
9050 /* If we have IF_THEN_ELSE already, extract the condition and
9051 canonicalize it if it is NE or EQ. */
9057 {
9060 }
9061 else
9063 }
9065 /* If X is a SUBREG, we can narrow both the true and false values
9066 if the inner expression, if there is a condition. */
9070 {
9076 {
9080 }
9081 }
9083 /* If X is a constant, this isn't special and will cause confusions
9084 if we treat it as such. Likewise if it is equivalent to a constant. */
9087 ;
9089 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9090 will be least confusing to the rest of the compiler. */
9092 {
9095 }
9097 /* If X is known to be either 0 or -1, those are the true and
9098 false values when testing X. */
9102 {
9105 }
9107 /* Likewise for 0 or a single bit. */
9110 {
9113 }
9115 /* Otherwise fail; show no condition with true and false values the same. */
9118 }
9119 \f
9120 /* Return the value of expression X given the fact that condition COND
9121 is known to be true when applied to REG as its first operand and VAL
9122 as its second. X is known to not be shared and so can be modified in
9123 place.
9125 We only handle the simplest cases, and specifically those cases that
9126 arise with IF_THEN_ELSE expressions. */
9128 static rtx
9130 {
9138 /* If either operand of the condition is a floating point value,
9139 then we have to avoid collapsing an EQ comparison. */
9149 /* If X is (abs REG) and we know something about REG's relationship
9150 with zero, we may be able to simplify this. */
9154 {
9163 }
9165 /* The only other cases we handle are MIN, MAX, and comparisons if the
9166 operands are the same as REG and VAL. */
9169 {
9171 {
9174 }
9177 {
9179 {
9187 else
9189 }
9192 {
9195 /* Do not reverse the condition when it is NE or EQ.
9196 This is because we cannot conclude anything about
9197 the value of 'SMAX (x, y)' when x is not equal to y,
9198 but we can when x equals y. */
9204 {
9215 }
9216 }
9217 }
9218 }
9220 {
9225 {
9226 /* We must simplify subreg here, before we lose track of the
9227 original inner_mode. */
9232 else
9234 }
9237 }
9238 /* We don't have to handle SIGN_EXTEND here, because even in the
9239 case of replacing something with a modeless CONST_INT, a
9240 CONST_INT is already (supposed to be) a valid sign extension for
9241 its narrower mode, which implies it's already properly
9242 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9243 story is different. */
9245 {
9250 {
9251 /* We must simplify the zero_extend here, before we lose
9252 track of the original inner_mode. */
9257 else
9259 }
9262 }
9266 {
9273 }
9276 }
9277 \f
9278 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9279 assignment as a field assignment. */
9281 static int
9283 {
9285 {
9290 /* For big endian, adjust the memory offset. */
9295 else
9297 }
9305 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9306 Note that all SUBREGs of MEM are paradoxical; otherwise they
9307 would have been rewritten. */
9320 /* We used to see if get_last_value of X and Y were the same but that's
9321 not correct. In one direction, we'll cause the assignment to have
9322 the wrong destination and in the case, we'll import a register into this
9323 insn that might have already have been dead. So fail if none of the
9324 above cases are true. */
9326 }
9327 \f
9328 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9329 Return that assignment if so.
9331 We only handle the most common cases. */
9333 static rtx
9335 {
9338 rtx assign;
9340 HOST_WIDE_INT c1;
9341 HOST_WIDE_INT pos;
9343 rtx other;
9344 machine_mode mode;
9346 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9347 a clear of a one-bit field. We will have changed it to
9348 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9349 for a SUBREG. */
9355 {
9361 }
9371 {
9378 }
9380 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9381 one-bit field. */
9385 {
9391 }
9393 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9394 SRC is an AND with all bits of that field set, then we can discard
9395 the AND. */
9400 {
9407 else
9410 /* Complete overlap. We can remove the source AND. */
9414 /* Partial overlap. We can reduce the source AND. */
9416 {
9421 }
9422 }
9424 /* The other case we handle is assignments into a constant-position
9425 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9426 a mask that has all one bits except for a group of zero bits and
9427 OTHER is known to have zeros where C1 has ones, this is such an
9428 assignment. Compute the position and length from C1. Shift OTHER
9429 to the appropriate position, force it to the required mode, and
9430 make the extraction. Check for the AND in both operands. */
9432 /* One or more SUBREGs might obscure the constant-position field
9433 assignment. The first one we are likely to encounter is an outer
9434 narrowing SUBREG, which we can just strip for the purposes of
9435 identifying the constant-field assignment. */
9449 /* The second SUBREG that might get in the way is a paradoxical
9450 SUBREG around the first operand of the AND. We want to
9451 pretend the operand is as wide as the destination here. We
9452 do this by adjusting the MEM to wider mode for the sole
9453 purpose of the call to rtx_equal_for_field_assignment_p. Also
9454 note this trick only works for MEMs. */
9466 /* The second SUBREG that might get in the way is a paradoxical
9467 SUBREG around the first operand of the AND. We want to
9468 pretend the operand is as wide as the destination here. We
9469 do this by adjusting the MEM to wider mode for the sole
9470 purpose of the call to rtx_equal_for_field_assignment_p. Also
9471 note this trick only works for MEMs. */
9479 else
9492 /* The mode to use for the source is the mode of the assignment, or of
9493 what is inside a possible STRICT_LOW_PART. */
9497 /* Shift OTHER right POS places and make it the source, restricting it
9498 to the proper length and mode. */
9503 dest);
9506 ? HOST_WIDE_INT_M1U
9510 /* If SRC is masked by an AND that does not make a difference in
9511 the value being stored, strip it. */
9522 }
9523 \f
9524 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9525 if so. */
9527 static rtx
9529 {
9533 rtx tem;
9535 /* Distributivity is not true for floating point as it can change the
9536 value. So we don't do it unless -funsafe-math-optimizations. */
9541 /* The outer operation can only be one of the following: */
9549 /* If either operand is a primitive we can't do anything, so get out
9550 fast. */
9560 /* See if the inner and outer operations distribute. */
9562 {
9567 /* These all distribute except over PLUS. */
9578 /* This is also a multiply, so it distributes over everything. */
9581 /* This used to handle SUBREG, but this turned out to be counter-
9582 productive, since (subreg (op ...)) usually is not handled by
9583 insn patterns, and this "optimization" therefore transformed
9584 recognizable patterns into unrecognizable ones. Therefore the
9585 SUBREG case was removed from here.
9587 It is possible that distributing SUBREG over arithmetic operations
9588 leads to an intermediate result than can then be optimized further,
9589 e.g. by moving the outer SUBREG to the other side of a SET as done
9590 in simplify_set. This seems to have been the original intent of
9591 handling SUBREGs here.
9593 However, with current GCC this does not appear to actually happen,
9594 at least on major platforms. If some case is found where removing
9595 the SUBREG case here prevents follow-on optimizations, distributing
9596 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9600 }
9602 /* Set LHS and RHS to the inner operands (A and B in the example
9603 above) and set OTHER to the common operand (C in the example).
9604 There is only one way to do this unless the inner operation is
9605 commutative. */
9617 else
9620 /* Form the new inner operation, seeing if it simplifies first. */
9623 /* There is one exception to the general way of distributing:
9624 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9626 {
9629 }
9631 /* We may be able to continuing distributing the result, so call
9632 ourselves recursively on the inner operation before forming the
9633 outer operation, which we return. */
9636 }
9638 /* See if X is of the form (* (+ A B) C), and if so convert to
9639 (+ (* A C) (* B C)) and try to simplify.
9641 Most of the time, this results in no change. However, if some of
9642 the operands are the same or inverses of each other, simplifications
9643 will result.
9645 For example, (and (ior A B) (not B)) can occur as the result of
9646 expanding a bit field assignment. When we apply the distributive
9647 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9648 which then simplifies to (and (A (not B))).
9650 Note that no checks happen on the validity of applying the inverse
9651 distributive law. This is pointless since we can do it in the
9652 few places where this routine is called.
9654 N is the index of the term that is decomposed (the arithmetic operation,
9655 i.e. (+ A B) in the first example above). !N is the index of the term that
9656 is distributed, i.e. of C in the first example above. */
9657 static rtx
9659 {
9660 machine_mode mode;
9664 /* Distributivity is not true for floating point as it can change the
9665 value. So we don't do it unless -funsafe-math-optimizations. */
9682 /* Special case (and (xor B C) (not A)), which is equivalent to
9683 (xor (ior A B) (ior A C)) */
9685 {
9688 }
9691 {
9692 /* Distribute the second term. */
9695 }
9696 else
9697 {
9698 /* Distribute the first term. */
9701 }
9711 }
9712 \f
9713 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9714 in MODE. Return an equivalent form, if different from (and VAROP
9715 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9717 static rtx
9720 {
9723 rtx orig_varop;
9731 /* Simplify VAROP knowing that we will be only looking at some of the
9732 bits in it.
9734 Note by passing in CONSTOP, we guarantee that the bits not set in
9735 CONSTOP are not significant and will never be examined. We must
9736 ensure that is the case by explicitly masking out those bits
9737 before returning. */
9740 /* If VAROP is a CLOBBER, we will fail so return it. */
9744 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9745 to VAROP and return the new constant. */
9749 /* See what bits may be nonzero in VAROP. Unlike the general case of
9750 a call to nonzero_bits, here we don't care about bits outside
9751 MODE. */
9755 /* Turn off all bits in the constant that are known to already be zero.
9756 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9757 which is tested below. */
9761 /* If we don't have any bits left, return zero. */
9765 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9766 a power of two, we can replace this with an ASHIFT. */
9771 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9772 or XOR, then try to apply the distributive law. This may eliminate
9773 operations if either branch can be simplified because of the AND.
9774 It may also make some cases more complex, but those cases probably
9775 won't match a pattern either with or without this. */
9778 return
9779 gen_lowpart
9781 apply_distributive_law
9786 constop),
9790 constop))));
9792 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9793 the AND and see if one of the operands simplifies to zero. If so, we
9794 may eliminate it. */
9798 {
9807 }
9809 /* Make a SUBREG if necessary. If we can't make it, fail. */
9814 /* If we are only masking insignificant bits, return VAROP. */
9821 /* Otherwise, return an AND. */
9823 }
9826 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9827 in MODE.
9829 Return an equivalent form, if different from X. Otherwise, return X. If
9830 X is zero, we are to always construct the equivalent form. */
9832 static rtx
9835 {
9846 }
9847 \f
9848 /* Given a REG, X, compute which bits in X can be nonzero.
9849 We don't care about bits outside of those defined in MODE.
9851 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9852 a shift, AND, or zero_extract, we can do better. */
9854 static rtx
9856 const_rtx known_x ATTRIBUTE_UNUSED,
9857 machine_mode known_mode ATTRIBUTE_UNUSED,
9860 {
9861 rtx tem;
9864 /* If X is a register whose nonzero bits value is current, use it.
9865 Otherwise, if X is a register whose value we can find, use that
9866 value. Otherwise, use the previously-computed global nonzero bits
9867 for this register. */
9881 && !REGNO_REG_SET_P
9884 {
9888 /* We don't know anything about the upper bits. */
9893 }
9898 {
9904 }
9906 {
9910 /* We don't know anything about the upper bits. */
9914 }
9917 }
9919 /* Return the number of bits at the high-order end of X that are known to
9920 be equal to the sign bit. X will be used in mode MODE; if MODE is
9921 VOIDmode, X will be used in its own mode. The returned value will always
9922 be between 1 and the number of bits in MODE. */
9924 static rtx
9926 const_rtx known_x ATTRIBUTE_UNUSED,
9927 machine_mode known_mode
9928 ATTRIBUTE_UNUSED,
9931 {
9932 rtx tem;
9945 && !REGNO_REG_SET_P
9948 {
9951 }
9962 }
9963 \f
9964 /* Return the number of "extended" bits there are in X, when interpreted
9965 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9966 unsigned quantities, this is the number of high-order zero bits.
9967 For signed quantities, this is the number of copies of the sign bit
9968 minus 1. In both case, this function returns the number of "spare"
9969 bits. For example, if two quantities for which this function returns
9970 at least 1 are added, the addition is known not to overflow.
9972 This function will always return 0 unless called during combine, which
9973 implies that it must be called from a define_split. */
9975 unsigned int
9977 {
9987 }
9989 /* This function is called from `simplify_shift_const' to merge two
9990 outer operations. Specifically, we have already found that we need
9991 to perform operation *POP0 with constant *PCONST0 at the outermost
9992 position. We would now like to also perform OP1 with constant CONST1
9993 (with *POP0 being done last).
9995 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9996 the resulting operation. *PCOMP_P is set to 1 if we would need to
9997 complement the innermost operand, otherwise it is unchanged.
9999 MODE is the mode in which the operation will be done. No bits outside
10000 the width of this mode matter. It is assumed that the width of this mode
10001 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10003 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10004 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10005 result is simply *PCONST0.
10007 If the resulting operation cannot be expressed as one operation, we
10008 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10010 static int
10011 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10012 {
10019 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10023 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10024 if OP0 is SET. */
10033 {
10035 {
10053 }
10054 }
10056 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10060 /* If the two constants aren't the same, we can't do anything. The
10061 remaining six cases can all be done. */
10065 else
10067 {
10070 /* (a & b) | b == b */
10073 /* (a ^ b) | b == a | b */
10074 {;}
10079 /* (a & b) ^ b == (~a) & b */
10082 /* (a | b) ^ b == a & ~b */
10088 /* (a | b) & b == b */
10091 /* (a ^ b) & b) == (~a) & b */
10096 }
10098 /* Check for NO-OP cases. */
10111 /* ??? Slightly redundant with the above mask, but not entirely.
10112 Moving this above means we'd have to sign-extend the mode mask
10113 for the final test. */
10118 }
10119 \f
10120 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10121 the shift in. The original shift operation CODE is performed on OP in
10122 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10123 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10124 result of the shift is subject to operation OUTER_CODE with operand
10125 OUTER_CONST. */
10127 static machine_mode
10131 {
10136 /* In general we can't perform in wider mode for right shift and rotate. */
10138 {
10140 /* We can still widen if the bits brought in from the left are identical
10141 to the sign bit of ORIG_MODE. */
10149 /* Similarly here but with zero bits. */
10154 /* We can also widen if the bits brought in will be masked off. This
10155 operation is performed in ORIG_MODE. */
10157 {
10163 }
10164 /* fall through */
10174 }
10175 }
10177 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10178 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10179 if we cannot simplify it. Otherwise, return a simplified value.
10181 The shift is normally computed in the widest mode we find in VAROP, as
10182 long as it isn't a different number of words than RESULT_MODE. Exceptions
10183 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10185 static rtx
10188 {
10194 unsigned int mode_words
10196 /* We form (outer_op (code varop count) (outer_const)). */
10202 /* Make sure and truncate the "natural" shift on the way in. We don't
10203 want to do this inside the loop as it makes it more difficult to
10204 combine shifts. */
10208 /* If we were given an invalid count, don't do anything except exactly
10209 what was requested. */
10216 /* Unless one of the branches of the `if' in this loop does a `continue',
10217 we will `break' the loop after the `if'. */
10220 {
10221 /* If we have an operand of (clobber (const_int 0)), fail. */
10225 /* Convert ROTATERT to ROTATE. */
10227 {
10232 else
10234 }
10239 /* Handle cases where the count is greater than the size of the mode
10240 minus 1. For ASHIFT, use the size minus one as the count (this can
10241 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10242 take the count modulo the size. For other shifts, the result is
10243 zero.
10245 Since these shifts are being produced by the compiler by combining
10246 multiple operations, each of which are defined, we know what the
10247 result is supposed to be. */
10250 {
10255 else
10256 {
10257 /* We can't simply return zero because there may be an
10258 outer op. */
10262 }
10263 }
10265 /* If we discovered we had to complement VAROP, leave. Making a NOT
10266 here would cause an infinite loop. */
10270 /* An arithmetic right shift of a quantity known to be -1 or 0
10271 is a no-op. */
10275 {
10278 }
10280 /* If we are doing an arithmetic right shift and discarding all but
10281 the sign bit copies, this is equivalent to doing a shift by the
10282 bitsize minus one. Convert it into that shift because it will often
10283 allow other simplifications. */
10290 /* We simplify the tests below and elsewhere by converting
10291 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10292 `make_compound_operation' will convert it to an ASHIFTRT for
10293 those machines (such as VAX) that don't have an LSHIFTRT. */
10310 {
10317 {
10320 }
10324 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10325 minus the width of a smaller mode, we can do this with a
10326 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10333 {
10342 }
10346 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10347 the same number of words as what we've seen so far. Then store
10348 the widest mode in MODE. */
10354 == mode_words
10357 {
10362 }
10366 /* Some machines use MULT instead of ASHIFT because MULT
10367 is cheaper. But it is still better on those machines to
10368 merge two shifts into one. */
10371 {
10372 varop
10378 }
10382 /* Similar, for when divides are cheaper. */
10385 {
10386 varop
10392 }
10396 /* If we are extracting just the sign bit of an arithmetic
10397 right shift, that shift is not needed. However, the sign
10398 bit of a wider mode may be different from what would be
10399 interpreted as the sign bit in a narrower mode, so, if
10400 the result is narrower, don't discard the shift. */
10405 {
10408 }
10410 /* fall through */
10415 /* Here we have two nested shifts. The result is usually the
10416 AND of a new shift with a mask. We compute the result below. */
10423 {
10427 rtx mask_rtx;
10429 /* We have one common special case. We can't do any merging if
10430 the inner code is an ASHIFTRT of a smaller mode. However, if
10431 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10432 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10433 we can convert it to
10434 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10435 This simplifies certain SIGN_EXTEND operations. */
10439 {
10440 /* C3 has the low-order C1 bits zero. */
10452 }
10454 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10455 than C1 high-order bits equal to the sign bit, we can convert
10456 this to either an ASHIFT or an ASHIFTRT depending on the
10457 two counts.
10459 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10465 {
10469 {
10472 }
10475 }
10477 /* There are some cases we can't do. If CODE is ASHIFTRT,
10478 we can only do this if FIRST_CODE is also ASHIFTRT.
10480 We can't do the case when CODE is ROTATE and FIRST_CODE is
10481 ASHIFTRT.
10483 If the mode of this shift is not the mode of the outer shift,
10484 we can't do this if either shift is a right shift or ROTATE.
10486 Finally, we can't do any of these if the mode is too wide
10487 unless the codes are the same.
10489 Handle the case where the shift codes are the same
10490 first. */
10493 {
10502 }
10513 /* To compute the mask to apply after the shift, shift the
10514 nonzero bits of the inner shift the same way the
10515 outer shift will. */
10518 result_mode);
10520 mask_rtx
10524 /* Give up if we can't compute an outer operation to use. */
10532 /* If the shifts are in the same direction, we add the
10533 counts. Otherwise, we subtract them. */
10537 else
10540 /* If COUNT is positive, the new shift is usually CODE,
10541 except for the two exceptions below, in which case it is
10542 FIRST_CODE. If the count is negative, FIRST_CODE should
10543 always be used */
10553 }
10555 /* If we have (A << B << C) for any shift, we can convert this to
10556 (A << C << B). This wins if A is a constant. Only try this if
10557 B is not a constant. */
10562 {
10563 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10564 sure the result will be masked. See PR70222. */
10572 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10573 up outer sign extension (often left and right shift) is
10574 hardly more efficient than the original. See PR70429. */
10584 }
10591 /* Make this fit the case below. */
10598 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10599 with C the size of VAROP - 1 and the shift is logical if
10600 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10601 we have an (le X 0) operation. If we have an arithmetic shift
10602 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10603 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10611 {
10614 const0_rtx);
10620 }
10622 /* If we have (shift (logical)), move the logical to the outside
10623 to allow it to possibly combine with another logical and the
10624 shift to combine with another shift. This also canonicalizes to
10625 what a ZERO_EXTRACT looks like. Also, some machines have
10626 (and (shift)) insns. */
10629 /* We can't do this if we have (ashiftrt (xor)) and the
10630 constant has its sign bit set in shift_mode with shift_mode
10631 wider than result_mode. */
10635 shift_mode))
10643 {
10646 }
10648 /* If we can't do that, try to simplify the shift in each arm of the
10649 logical expression, make a new logical expression, and apply
10650 the inverse distributive law. This also can't be done for
10651 (ashiftrt (xor)) where we've widened the shift and the constant
10652 changes the sign bit. */
10657 shift_mode)))
10658 {
10670 }
10674 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10675 says that the sign bit can be tested, FOO has mode MODE, C is
10676 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10677 that may be nonzero. */
10687 {
10691 }
10695 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10696 than the number of bits in the mode is equivalent to A. */
10700 {
10704 }
10706 /* NEG commutes with ASHIFT since it is multiplication. Move the
10707 NEG outside to allow shifts to combine. */
10711 {
10714 }
10718 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10719 is one less than the number of bits in the mode is
10720 equivalent to (xor A 1). */
10727 {
10731 }
10733 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10734 that might be nonzero in BAR are those being shifted out and those
10735 bits are known zero in FOO, we can replace the PLUS with FOO.
10736 Similarly in the other operand order. This code occurs when
10737 we are computing the size of a variable-size array. */
10744 {
10747 }
10755 result_mode)))
10756 {
10759 }
10761 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10771 {
10774 }
10776 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10777 signbit', and attempt to change the PLUS to an XOR and move it to
10778 the outer operation as is done above in the AND/IOR/XOR case
10779 leg for shift(logical). See details in logical handling above
10780 for reasoning in doing so. */
10791 {
10794 }
10799 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10800 with C the size of VAROP - 1 and the shift is logical if
10801 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10802 we have a (gt X 0) operation. If the shift is arithmetic with
10803 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10804 we have a (neg (gt X 0)) operation. */
10813 {
10816 const0_rtx);
10822 }
10826 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10827 if the truncate does not affect the value. */
10834 {
10837 varop_inner
10840 GEN_INT
10845 }
10850 }
10853 }
10858 /* We have now finished analyzing the shift. The result should be
10859 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10860 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10861 to the result of the shift. OUTER_CONST is the relevant constant,
10862 but we must turn off all bits turned off in the shift. */
10870 /* Make a SUBREG if necessary. If we can't make it, fail. */
10875 /* If we have an outer operation and we just made a shift, it is
10876 possible that we could have simplified the shift were it not
10877 for the outer operation. So try to do the simplification
10878 recursively. */
10882 else
10888 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10889 turn off all the bits that the shift would have turned off. */
10894 /* Do the remainder of the processing in RESULT_MODE. */
10897 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10898 operation. */
10903 {
10911 {
10912 /* This means that we have determined that the result is
10913 equivalent to a constant. This should be rare. */
10916 }
10919 else
10922 }
10925 }
10927 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10928 The result of the shift is RESULT_MODE. If we cannot simplify it,
10929 return X or, if it is NULL, synthesize the expression with
10930 simplify_gen_binary. Otherwise, return a simplified value.
10932 The shift is normally computed in the widest mode we find in VAROP, as
10933 long as it isn't a different number of words than RESULT_MODE. Exceptions
10934 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10936 static rtx
10939 {
10949 }
10951 \f
10952 /* A subroutine of recog_for_combine. See there for arguments and
10953 return value. */
10955 static int
10957 {
10959 rtx pat_without_clobbers;
10967 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10968 we use to indicate that something didn't match. If we find such a
10969 thing, force rejection. */
10983 {
10986 else
10989 }
10991 /* If it isn't, there is the possibility that we previously had an insn
10992 that clobbered some register as a side effect, but the combined
10993 insn doesn't need to do that. So try once more without the clobbers
10994 unless this represents an ASM insn. */
10998 {
11003 {
11006 pos++;
11007 }
11017 {
11020 else
11023 }
11024 }
11031 /* Recognize all noop sets, these will be killed by followup pass. */
11035 /* If we had any clobbers to add, make a new pattern than contains
11036 them. Then check to make sure that all of them are dead. */
11038 {
11048 else
11055 {
11060 {
11064 }
11065 }
11067 }
11071 {
11078 /* Allow targets to reject combined insn. */
11080 {
11083 dump_file);
11085 /* Callers expect recog_for_combine to strip
11086 clobbers from the pattern on failure. */
11091 }
11096 }
11102 }
11104 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11105 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11106 Return whether anything was so changed. */
11108 static bool
11110 {
11115 {
11124 {
11133 }
11139 {
11142 }
11143 else
11151 }
11154 }
11156 /* Like recog, but we receive the address of a pointer to a new pattern.
11157 We try to match the rtx that the pointer points to.
11158 If that fails, we may try to modify or replace the pattern,
11159 storing the replacement into the same pointer object.
11161 Modifications include deletion or addition of CLOBBERs. If the
11162 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11163 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11164 (and undo if that fails).
11166 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11167 the CLOBBERs are placed.
11169 The value is the final insn code from the pattern ultimately matched,
11170 or -1. */
11172 static int
11174 {
11186 {
11189 {
11193 }
11194 }
11197 {
11202 }
11205 }
11206 \f
11207 /* Like gen_lowpart_general but for use by combine. In combine it
11208 is not possible to create any new pseudoregs. However, it is
11209 safe to create invalid memory addresses, because combine will
11210 try to recognize them and all they will do is make the combine
11211 attempt fail.
11213 If for some reason this cannot do its job, an rtx
11214 (clobber (const_int 0)) is returned.
11215 An insn containing that will not be recognized. */
11217 static rtx
11219 {
11223 rtx result;
11228 /* We can only support MODE being wider than a word if X is a
11229 constant integer or has a mode the same size. */
11234 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11235 won't know what to do. So we will strip off the SUBREG here and
11236 process normally. */
11238 {
11241 /* For use in case we fall down into the address adjustments
11242 further below, we need to adjust the known mode and size of
11243 x; imode and isize, since we just adjusted x. */
11250 }
11258 {
11261 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11262 address. */
11267 /* If we want to refer to something bigger than the original memref,
11268 generate a paradoxical subreg instead. That will force a reload
11269 of the original memref X. */
11276 /* Adjust the address so that the address-after-the-data is
11277 unchanged. */
11282 }
11284 /* If X is a comparison operator, rewrite it in a new mode. This
11285 probably won't match, but may allow further simplifications. */
11289 /* If we couldn't simplify X any other way, just enclose it in a
11290 SUBREG. Normally, this SUBREG won't match, but some patterns may
11291 include an explicit SUBREG or we may simplify it further in combine. */
11292 else
11293 {
11294 rtx res;
11297 {
11302 }
11306 }
11308 fail:
11310 }
11311 \f
11312 /* Try to simplify a comparison between OP0 and a constant OP1,
11313 where CODE is the comparison code that will be tested, into a
11314 (CODE OP0 const0_rtx) form.
11316 The result is a possibly different comparison code to use.
11317 *POP1 may be updated. */
11319 static enum rtx_code
11322 {
11326 /* Get the constant we are comparing against and turn off all bits
11327 not on in our mode. */
11331 /* If we are comparing against a constant power of two and the value
11332 being compared can only have that single bit nonzero (e.g., it was
11333 `and'ed with that bit), we can replace this with a comparison
11334 with zero. */
11342 {
11345 }
11347 /* Similarly, if we are comparing a value known to be either -1 or
11348 0 with -1, change it to the opposite comparison against zero. */
11353 {
11356 }
11358 /* Do some canonicalizations based on the comparison code. We prefer
11359 comparisons against zero and then prefer equality comparisons.
11360 If we can reduce the size of a constant, we will do that too. */
11362 {
11364 /* < C is equivalent to <= (C - 1) */
11366 {
11369 /* ... fall through to LE case below. */
11370 }
11371 else
11375 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11377 {
11380 }
11382 /* If we are doing a <= 0 comparison on a value known to have
11383 a zero sign bit, we can replace this with == 0. */
11393 /* >= C is equivalent to > (C - 1). */
11395 {
11398 /* ... fall through to GT below. */
11399 }
11400 else
11404 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11406 {
11409 }
11411 /* If we are doing a > 0 comparison on a value known to have
11412 a zero sign bit, we can replace this with != 0. */
11422 /* < C is equivalent to <= (C - 1). */
11424 {
11427 /* ... fall through ... */
11428 }
11429 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11433 {
11437 }
11438 else
11442 /* unsigned <= 0 is equivalent to == 0 */
11445 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11449 {
11452 }
11456 /* >= C is equivalent to > (C - 1). */
11458 {
11461 /* ... fall through ... */
11462 }
11464 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11468 {
11472 }
11473 else
11477 /* unsigned > 0 is equivalent to != 0 */
11480 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11484 {
11487 }
11492 }
11496 }
11497 \f
11498 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11499 comparison code that will be tested.
11501 The result is a possibly different comparison code to use. *POP0 and
11502 *POP1 may be updated.
11504 It is possible that we might detect that a comparison is either always
11505 true or always false. However, we do not perform general constant
11506 folding in combine, so this knowledge isn't useful. Such tautologies
11507 should have been detected earlier. Hence we ignore all such cases. */
11509 static enum rtx_code
11511 {
11518 /* Try a few ways of applying the same transformation to both operands. */
11520 {
11521 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11522 so check specially. */
11538 - (GET_MODE_PRECISION
11540 {
11543 }
11545 /* If both operands are the same constant shift, see if we can ignore the
11546 shift. We can if the shift is a rotate or if the bits shifted out of
11547 this shift are known to be zero for both inputs and if the type of
11548 comparison is compatible with the shift. */
11561 {
11574 else
11576 }
11578 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11579 SUBREGs are of the same mode, and, in both cases, the AND would
11580 be redundant if the comparison was done in the narrower mode,
11581 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11582 and the operand's possibly nonzero bits are 0xffffff01; in that case
11583 if we only care about QImode, we don't need the AND). This case
11584 occurs if the output mode of an scc insn is not SImode and
11585 STORE_FLAG_VALUE == 1 (e.g., the 386).
11587 Similarly, check for a case where the AND's are ZERO_EXTEND
11588 operations from some narrower mode even though a SUBREG is not
11589 present. */
11594 {
11611 {
11615 /* The resulting comparison is always unsigned since we masked
11616 off the original sign bit. */
11620 }
11627 {
11633 }
11637 }
11639 /* If both operands are NOT, we can strip off the outer operation
11640 and adjust the comparison code for swapped operands; similarly for
11641 NEG, except that this must be an equality comparison. */
11647 else
11649 }
11651 /* If the first operand is a constant, swap the operands and adjust the
11652 comparison code appropriately, but don't do this if the second operand
11653 is already a constant integer. */
11655 {
11658 }
11660 /* We now enter a loop during which we will try to simplify the comparison.
11661 For the most part, we only are concerned with comparisons with zero,
11662 but some things may really be comparisons with zero but not start
11663 out looking that way. */
11666 {
11673 HOST_WIDE_INT const_op;
11675 /* We only want to handle integral modes. This catches VOIDmode,
11676 CCmode, and the floating-point modes. An exception is that we
11677 can handle VOIDmode if OP0 is a COMPARE or a comparison
11678 operation. */
11685 /* Try to simplify the compare to constant, possibly changing the
11686 comparison op, and/or changing op1 to zero. */
11690 /* Compute some predicates to simplify code below. */
11697 /* If this is a sign bit comparison and we can do arithmetic in
11698 MODE, say that we will only be needing the sign bit of OP0. */
11701 HOST_WIDE_INT_1U
11705 /* Now try cases based on the opcode of OP0. If none of the cases
11706 does a "continue", we exit this loop immediately after the
11707 switch. */
11710 {
11712 /* If we are extracting a single bit from a variable position in
11713 a constant that has only a single bit set and are comparing it
11714 with zero, we can convert this into an equality comparison
11715 between the position and the location of the single bit. */
11716 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11717 have already reduced the shift count modulo the word size. */
11723 {
11731 /* Result is nonzero iff shift count is equal to I. */
11734 }
11736 /* fall through */
11741 {
11744 }
11748 /* If testing for equality, we can take the NOT of the constant. */
11751 {
11755 }
11757 /* If just looking at the sign bit, reverse the sense of the
11758 comparison. */
11760 {
11764 }
11768 /* If testing for equality, we can take the NEG of the constant. */
11771 {
11775 }
11777 /* The remaining cases only apply to comparisons with zero. */
11781 /* When X is ABS or is known positive,
11782 (neg X) is < 0 if and only if X != 0. */
11790 {
11794 }
11796 /* If we have NEG of something whose two high-order bits are the
11797 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11799 {
11803 }
11807 /* If we are testing equality and our count is a constant, we
11808 can perform the inverse operation on our RHS. */
11812 {
11816 }
11818 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11819 a particular bit. Convert it to an AND of a constant of that
11820 bit. This will be converted into a ZERO_EXTRACT. */
11824 {
11826 (HOST_WIDE_INT_1U
11831 }
11833 /* Fall through. */
11836 /* ABS is ignorable inside an equality comparison with zero. */
11838 {
11841 }
11845 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11846 (compare FOO CONST) if CONST fits in FOO's mode and we
11847 are either testing inequality or have an unsigned
11848 comparison with ZERO_EXTEND or a signed comparison with
11849 SIGN_EXTEND. But don't do it if we don't have a compare
11850 insn of the given mode, since we'd have to revert it
11851 later on, and then we wouldn't know whether to sign- or
11852 zero-extend. */
11855 && ! unsigned_comparison_p
11859 {
11862 }
11866 /* Check for the case where we are comparing A - C1 with C2, that is
11868 (subreg:MODE (plus (A) (-C1))) op (C2)
11870 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11871 comparison in the wider mode. One of the following two conditions
11872 must be true in order for this to be valid:
11874 1. The mode extension results in the same bit pattern being added
11875 on both sides and the comparison is equality or unsigned. As
11876 C2 has been truncated to fit in MODE, the pattern can only be
11877 all 0s or all 1s.
11879 2. The mode extension results in the sign bit being copied on
11880 each side.
11882 The difficulty here is that we have predicates for A but not for
11883 (A - C1) so we need to check that C1 is within proper bounds so
11884 as to perturbate A as little as possible. */
11891 {
11900 /* (A - C1) zero-extends if it is positive and sign-extends
11901 if it is negative, C2 both zero- and sign-extends. */
11905 /* (A - C1) sign-extends if it is positive and 1-extends
11906 if it is negative, C2 both sign- and 1-extends. */
11913 /* (A - C1) always sign-extends, like C2. */
11917 {
11920 }
11921 }
11923 /* If the inner mode is narrower and we are extracting the low part,
11924 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11927 ;
11928 else
11931 /* FALLTHROUGH */
11941 {
11944 }
11948 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11949 this for equality comparisons due to pathological cases involving
11950 overflows. */
11954 {
11958 }
11960 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11963 {
11967 }
11971 /* We used to optimize signed comparisons against zero, but that
11972 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11973 arrive here as equality comparisons, or (GEU, LTU) are
11974 optimized away. No need to special-case them. */
11976 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11977 (eq B (minus A C)), whichever simplifies. We can only do
11978 this for equality comparisons due to pathological cases involving
11979 overflows. */
11983 {
11987 }
11992 {
11996 }
11998 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11999 of bits in X minus 1, is one iff X > 0. */
12004 {
12008 }
12012 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12013 if C is zero or B is a constant. */
12017 {
12021 }
12029 /* We can't do anything if OP0 is a condition code value, rather
12030 than an actual data value. */
12036 /* Get the two operands being compared. */
12039 else
12042 /* Check for the cases where we simply want the result of the
12043 earlier test or the opposite of that result. */
12047 {
12051 else
12055 {
12060 }
12061 }
12065 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12066 iff X <= 0. */
12070 {
12074 }
12078 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12079 will be converted to a ZERO_EXTRACT later. */
12083 {
12088 }
12090 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12091 zero and X is a comparison and C1 and C2 describe only bits set
12092 in STORE_FLAG_VALUE, we can compare with X. */
12100 {
12107 {
12110 }
12111 }
12113 /* If we are doing an equality comparison of an AND of a bit equal
12114 to the sign bit, replace this with a LT or GE comparison of
12115 the underlying value. */
12122 {
12126 }
12128 /* If this AND operation is really a ZERO_EXTEND from a narrower
12129 mode, the constant fits within that mode, and this is either an
12130 equality or unsigned comparison, try to do this comparison in
12131 the narrower mode.
12133 Note that in:
12135 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12136 -> (ne:DI (reg:SI 4) (const_int 0))
12138 unless TRULY_NOOP_TRUNCATION allows it or the register is
12139 known to hold a value of the required mode the
12140 transformation is invalid. */
12148 {
12151 }
12153 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12154 fits in both M1 and M2 and the SUBREG is either paradoxical
12155 or represents the low part, permute the SUBREG and the AND
12156 and try again. */
12159 {
12162 /* Require an integral mode, to avoid creating something like
12163 (AND:SF ...). */
12165 /* It is unsafe to commute the AND into the SUBREG if the
12166 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12167 not defined. As originally written the upper bits
12168 have a defined value due to the AND operation.
12169 However, if we commute the AND inside the SUBREG then
12170 they no longer have defined values and the meaning of
12171 the code has been changed.
12172 Also C1 should not change value in the smaller mode,
12173 see PR67028 (a positive C1 can become negative in the
12174 smaller mode, so that the AND does no longer mask the
12175 upper bits). */
12176 && ((WORD_REGISTER_OPERATIONS
12188 {
12194 }
12195 }
12197 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12201 {
12206 }
12208 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12209 (eq (and (lshiftrt X) 1) 0).
12210 Also handle the case where (not X) is expressed using xor. */
12214 {
12224 == HOST_WIDE_INT_1U
12226 {
12227 op0
12232 }
12233 }
12237 /* If we have (compare (ashift FOO N) (const_int C)) and
12238 the high order N bits of FOO (N+1 if an inequality comparison)
12239 are known to be zero, we can do this by comparing FOO with C
12240 shifted right N bits so long as the low-order N bits of C are
12241 zero. */
12253 {
12254 /* We must perform a logical shift, not an arithmetic one,
12255 as we want the top N bits of C to be zero. */
12262 }
12264 /* If we are doing a sign bit comparison, it means we are testing
12265 a particular bit. Convert it to the appropriate AND. */
12268 {
12270 (HOST_WIDE_INT_1U
12275 }
12277 /* If this an equality comparison with zero and we are shifting
12278 the low bit to the sign bit, we can convert this to an AND of the
12279 low-order bit. */
12283 {
12286 }
12290 /* If this is an equality comparison with zero, we can do this
12291 as a logical shift, which might be much simpler. */
12294 {
12299 }
12301 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12302 do the comparison in a narrower mode. */
12312 {
12315 }
12317 /* Likewise if OP0 is a PLUS of a sign extension with a
12318 constant, which is usually represented with the PLUS
12319 between the shifts. */
12331 {
12339 new_const);
12341 }
12343 /* FALLTHROUGH */
12345 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12346 the low order N bits of FOO are known to be zero, we can do this
12347 by comparing FOO with C shifted left N bits so long as no
12348 overflow occurs. Even if the low order N bits of FOO aren't known
12349 to be zero, if the comparison is >= or < we can use the same
12350 optimization and for > or <= by setting all the low
12351 order N bits in the comparison constant. */
12362 {
12363 unsigned HOST_WIDE_INT low_bits
12365 & ((HOST_WIDE_INT_1U
12368 {
12369 /* If the shift was logical, then we must make the condition
12370 unsigned. */
12378 const_op
12383 }
12384 }
12386 /* If we are using this shift to extract just the sign bit, we
12387 can replace this with an LT or GE comparison. */
12392 {
12396 }
12401 }
12404 }
12406 /* Now make any compound operations involved in this comparison. Then,
12407 check for an outmost SUBREG on OP0 that is not doing anything or is
12408 paradoxical. The latter transformation must only be performed when
12409 it is known that the "extra" bits will be the same in op0 and op1 or
12410 that they don't matter. There are three cases to consider:
12412 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12413 care bits and we can assume they have any convenient value. So
12414 making the transformation is safe.
12416 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12417 In this case the upper bits of op0 are undefined. We should not make
12418 the simplification in that case as we do not know the contents of
12419 those bits.
12421 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12422 UNKNOWN. In that case we know those bits are zeros or ones. We must
12423 also be sure that they are the same as the upper bits of op1.
12425 We can never remove a SUBREG for a non-equality comparison because
12426 the sign bit is in a different place in the underlying object. */
12435 {
12437 {
12438 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12439 implemented. */
12441 {
12444 }
12445 }
12451 {
12457 }
12458 }
12460 /* We now do the opposite procedure: Some machines don't have compare
12461 insns in all modes. If OP0's mode is an integer mode smaller than a
12462 word and we can't do a compare in that mode, see if there is a larger
12463 mode for which we can do the compare. There are a number of cases in
12464 which we can use the wider mode. */
12474 {
12477 /* If this is a test for negative, we can make an explicit
12478 test of the sign bit. Test this first so we can use
12479 a paradoxical subreg to extend OP0. */
12483 {
12484 unsigned HOST_WIDE_INT sign
12491 }
12493 /* If the only nonzero bits in OP0 and OP1 are those in the
12494 narrower mode and this is an equality or unsigned comparison,
12495 we can use the wider mode. Similarly for sign-extended
12496 values, in which case it is true for all comparisons. */
12513 {
12514 /* If OP0 is an AND and we don't have an AND in MODE either,
12515 make a new AND in the proper mode. */
12523 else
12524 {
12526 {
12529 }
12530 else
12531 {
12534 }
12536 }
12537 }
12538 }
12540 /* We may have changed the comparison operands. Re-canonicalize. */
12542 {
12545 }
12547 /* If this machine only supports a subset of valid comparisons, see if we
12548 can convert an unsupported one into a supported one. */
12555 }
12556 \f
12557 /* Utility function for record_value_for_reg. Count number of
12558 rtxs in X. */
12559 static int
12561 {
12568 {
12588 }
12599 }
12600 \f
12601 /* Utility function for following routine. Called when X is part of a value
12602 being stored into last_set_value. Sets last_set_table_tick
12603 for each register mentioned. Similar to mention_regs in cse.c */
12605 static void
12607 {
12613 {
12619 {
12622 }
12625 }
12629 {
12630 /* Check for identical subexpressions. If x contains
12631 identical subexpression we only have to traverse one of
12632 them. */
12634 {
12635 /* Note that at this point x1 has already been
12636 processed. */
12640 /* If x0 and x1 are identical then there is no need to
12641 process x0. */
12645 /* If x0 is identical to a subexpression of x1 then while
12646 processing x1, x0 has already been processed. Thus we
12647 are done with x. */
12652 /* If x1 is identical to a subexpression of x0 then we
12653 still have to process the rest of x0. */
12656 {
12659 }
12660 }
12663 }
12667 }
12669 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12670 are saying that the register is clobbered and we no longer know its
12671 value. If INSN is zero, don't update reg_stat[].last_set; this is
12672 only permitted with VALUE also zero and is used to invalidate the
12673 register. */
12675 static void
12677 {
12683 /* If VALUE contains REG and we have a previous value for REG, substitute
12684 the previous value. */
12686 {
12687 rtx tem;
12689 /* Set things up so get_last_value is allowed to see anything set up to
12690 our insn. */
12694 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12695 it isn't going to be useful and will take a lot of time to process,
12696 so just use the CLOBBER. */
12699 {
12705 {
12706 /* If there are two or more occurrences of REG in VALUE,
12707 prevent the value from growing too much. */
12710 }
12713 }
12714 }
12716 /* For each register modified, show we don't know its value, that
12717 we don't know about its bitwise content, that its value has been
12718 updated, and that we don't know the location of the death of the
12719 register. */
12721 {
12733 }
12735 /* Mark registers that are being referenced in this value. */
12739 /* Now update the status of each register being set.
12740 If someone is using this register in this block, set this register
12741 to invalid since we will get confused between the two lives in this
12742 basic block. This makes using this register always invalid. In cse, we
12743 scan the table to invalidate all entries using this register, but this
12744 is too much work for us. */
12747 {
12753 else
12755 }
12757 /* The value being assigned might refer to X (like in "x++;"). In that
12758 case, we must replace it with (clobber (const_int 0)) to prevent
12759 infinite loops. */
12762 {
12766 }
12768 /* For the main register being modified, update the value, the mode, the
12769 nonzero bits, and the number of sign bit copies. */
12774 {
12782 rsp->last_set_sign_bit_copies
12784 }
12785 }
12787 /* Called via note_stores from record_dead_and_set_regs to handle one
12788 SET or CLOBBER in an insn. DATA is the instruction in which the
12789 set is occurring. */
12791 static void
12793 {
12800 {
12804 }
12807 {
12808 /* If we are setting the whole register, we know its value. Otherwise
12809 show that we don't know the value. We can handle SUBREG in
12810 some cases. */
12821 else
12823 }
12825 /* Ignore pushes, they clobber nothing. */
12828 }
12830 /* Update the records of when each REG was most recently set or killed
12831 for the things done by INSN. This is the last thing done in processing
12832 INSN in the combiner loop.
12834 We update reg_stat[], in particular fields last_set, last_set_value,
12835 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12836 last_death, and also the similar information mem_last_set (which insn
12837 most recently modified memory) and last_call_luid (which insn was the
12838 most recent subroutine call). */
12840 static void
12842 {
12843 rtx link;
12847 {
12850 {
12855 {
12860 }
12861 }
12864 }
12867 {
12868 hard_reg_set_iterator hrsi;
12870 {
12882 }
12886 /* We can't combine into a call pattern. Remember, though, that
12887 the return value register is set at this LUID. We could
12888 still replace a register with the return value from the
12889 wrong subroutine call! */
12891 }
12892 else
12894 }
12896 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12897 register present in the SUBREG, so for each such SUBREG go back and
12898 adjust nonzero and sign bit information of the registers that are
12899 known to have some zero/sign bits set.
12901 This is needed because when combine blows the SUBREGs away, the
12902 information on zero/sign bits is lost and further combines can be
12903 missed because of that. */
12905 static void
12907 {
12909 rtx set;
12917 {
12926 {
12929 }
12933 {
12936 }
12939 {
12942 }
12943 else
12945 }
12946 }
12948 /* Check if X, a register, is known to contain a value already
12949 truncated to MODE. In this case we can use a subreg to refer to
12950 the truncated value even though in the generic case we would need
12951 an explicit truncation. */
12953 static bool
12955 {
12967 }
12969 /* If X is a hard reg or a subreg record the mode that the register is
12970 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12971 to turn a truncate into a subreg using this information. Return true
12972 if traversing X is complete. */
12974 static bool
12976 {
12977 machine_mode truncated_mode;
12981 {
12992 }
12993 /* ??? For hard-regs we now record everything. We might be able to
12994 optimize this using last_set_mode. */
12997 else
13005 {
13008 }
13011 }
13013 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13014 the modes they are used in. This can help truning TRUNCATEs into
13015 SUBREGs. */
13017 static void
13019 {
13024 }
13026 /* Scan X for promoted SUBREGs. For each one found,
13027 note what it implies to the registers used in it. */
13029 static void
13031 {
13036 else
13037 {
13043 {
13053 }
13054 }
13055 }
13056 \f
13057 /* Verify that all the registers and memory references mentioned in *LOC are
13058 still valid. *LOC was part of a value set in INSN when label_tick was
13059 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13060 the invalid references with (clobber (const_int 0)) and return 1. This
13061 replacement is useful because we often can get useful information about
13062 the form of a value (e.g., if it was produced by a shift that always
13063 produces -1 or 0) even though we don't know exactly what registers it
13064 was produced from. */
13066 static int
13068 {
13075 {
13081 {
13084 /* If this is a pseudo-register that was only set once and not
13085 live at the beginning of the function, it is always valid. */
13089 && (!REGNO_REG_SET_P
13091 regno)))
13093 {
13097 }
13098 }
13101 }
13102 /* If this is a memory reference, make sure that there were no stores after
13103 it that might have clobbered the value. We don't have alias info, so we
13104 assume any store invalidates it. Moreover, we only have local UIDs, so
13105 we also assume that there were stores in the intervening basic blocks. */
13108 {
13112 }
13115 {
13117 {
13118 /* Check for identical subexpressions. If x contains
13119 identical subexpression we only have to traverse one of
13120 them. */
13122 {
13123 /* Note that at this point x0 has already been checked
13124 and found valid. */
13128 /* If x0 and x1 are identical then x is also valid. */
13132 /* If x1 is identical to a subexpression of x0 then
13133 while checking x0, x1 has already been checked. Thus
13134 it is valid and so as x. */
13139 /* If x0 is identical to a subexpression of x1 then x is
13140 valid iff the rest of x1 is valid. */
13143 return
13147 }
13152 }
13158 }
13160 /* If we haven't found a reason for it to be invalid, it is valid. */
13162 }
13164 /* Get the last value assigned to X, if known. Some registers
13165 in the value may be replaced with (clobber (const_int 0)) if their value
13166 is known longer known reliably. */
13168 static rtx
13170 {
13172 rtx value;
13175 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13176 then convert it to the desired mode. If this is a paradoxical SUBREG,
13177 we cannot predict what values the "extra" bits might have. */
13191 /* If we don't have a value, or if it isn't for this basic block and
13192 it's either a hard register, set more than once, or it's a live
13193 at the beginning of the function, return 0.
13195 Because if it's not live at the beginning of the function then the reg
13196 is always set before being used (is never used without being set).
13197 And, if it's set only once, and it's always set before use, then all
13198 uses must have the same last value, even if it's not from this basic
13199 block. */
13206 || REGNO_REG_SET_P
13210 /* If the value was set in a later insn than the ones we are processing,
13211 we can't use it even if the register was only set once. */
13216 /* If fewer bits were set than what we are asked for now, we cannot use
13217 the value. */
13222 /* If the value has all its registers valid, return it. */
13226 /* Otherwise, make a copy and replace any invalid register with
13227 (clobber (const_int 0)). If that fails for some reason, return 0. */
13234 }
13235 \f
13236 /* Return nonzero if expression X refers to a REG or to memory
13237 that is set in an instruction more recent than FROM_LUID. */
13239 static int
13241 {
13247 {
13251 #ifdef PUSH_ROUNDING
13252 /* Don't allow uses of the stack pointer to be moved,
13253 because we don't know whether the move crosses a push insn. */
13256 #endif
13258 {
13264 }
13266 }
13274 {
13276 {
13281 }
13285 }
13287 }
13288 \f
13289 /* Define three variables used for communication between the following
13290 routines. */
13295 /* Function called via note_stores from reg_dead_at_p.
13297 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13298 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13300 static void
13302 {
13312 }
13314 /* Return nonzero if REG is known to be dead at INSN.
13316 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13317 referencing REG, it is dead. If we hit a SET referencing REG, it is
13318 live. Otherwise, see if it is live or dead at the start of the basic
13319 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13320 must be assumed to be always live. */
13322 static int
13324 {
13325 basic_block block;
13328 /* Set variables for reg_dead_at_p_1. */
13334 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13335 we allow the machine description to decide whether use-and-clobber
13336 patterns are OK. */
13338 {
13342 }
13344 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13345 beginning of basic block. */
13348 {
13350 {
13360 }
13366 }
13368 /* Look at live-in sets for the basic block that we were in. */
13374 }
13375 \f
13376 /* Note hard registers in X that are used. */
13378 static void
13380 {
13386 {
13390 CASE_CONST_ANY:
13395 /* CC0 must die in the insn after it is set, so we don't need to take
13396 special note of it here. */
13401 /* If we are clobbering a MEM, mark any hard registers inside the
13402 address as used. */
13409 /* A hard reg in a wide mode may really be multiple registers.
13410 If so, mark all of them just like the first. */
13412 {
13413 /* None of this applies to the stack, frame or arg pointers. */
13415 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13423 }
13427 {
13428 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13429 the address. */
13441 }
13446 }
13448 /* Recursively scan the operands of this expression. */
13450 {
13454 {
13458 {
13463 }
13464 }
13465 }
13466 }
13467 \f
13468 /* Remove register number REGNO from the dead registers list of INSN.
13470 Return the note used to record the death, if there was one. */
13472 rtx
13474 {
13481 }
13483 /* For each register (hardware or pseudo) used within expression X, if its
13484 death is in an instruction with luid between FROM_LUID (inclusive) and
13485 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13486 list headed by PNOTES.
13488 That said, don't move registers killed by maybe_kill_insn.
13490 This is done when X is being merged by combination into TO_INSN. These
13491 notes will then be distributed as needed. */
13493 static void
13496 {
13502 {
13506 /* Don't move the register if it gets killed in between from and to. */
13515 {
13518 /* It is possible for the call above to return 0. This can occur
13519 when last_death points to I2 or I1 that we combined with.
13520 In that case make a new note.
13522 We must also check for the case where X is a hard register
13523 and NOTE is a death note for a range of hard registers
13524 including X. In that case, we must put REG_DEAD notes for
13525 the remaining registers in place of NOTE. */
13530 {
13539 }
13541 /* If we didn't find any note, or if we found a REG_DEAD note that
13542 covers only part of the given reg, and we have a multi-reg hard
13543 register, then to be safe we must check for REG_DEAD notes
13544 for each register other than the first. They could have
13545 their own REG_DEAD notes lying around. */
13552 {
13559 else
13565 }
13568 {
13571 }
13572 else
13574 }
13577 }
13580 {
13585 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13586 that accesses one word of a multi-word item, some
13587 piece of everything register in the expression is used by
13588 this insn, so remove any old death. */
13589 /* ??? So why do we test for equality of the sizes? */
13598 {
13601 }
13603 /* If this is some other SUBREG, we know it replaces the entire
13604 value, so use that as the destination. */
13608 /* If this is a MEM, adjust deaths of anything used in the address.
13609 For a REG (the only other possibility), the entire value is
13610 being replaced so the old value is not used in this insn. */
13616 }
13625 {
13627 {
13632 }
13635 }
13636 }
13637 \f
13638 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13639 pattern of an insn. X must be a REG. */
13641 static int
13643 {
13647 {
13649 rtx target;
13656 else
13673 }
13681 }
13682 \f
13683 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13684 as appropriate. I3 and I2 are the insns resulting from the combination
13685 insns including FROM (I2 may be zero).
13687 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13688 not need REG_DEAD notes because they are being substituted for. This
13689 saves searching in the most common cases.
13691 Each note in the list is either ignored or placed on some insns, depending
13692 on the type of note. */
13694 static void
13697 {
13699 rtx tem_note;
13703 {
13708 {
13711 /* Doesn't matter much where we put this, as long as it's somewhere.
13712 It is preferable to keep these notes on branches, which is most
13713 likely to be i3. */
13720 else
13721 {
13724 }
13728 /* These notes must remain with the call or trapping instruction. */
13733 else
13734 {
13740 /* ??? Otherwise assume we've combined things such that we
13741 can now prove that the instructions can't trap. Drop the
13742 note in this case. */
13743 }
13747 /* ??? How to distribute between i3-i1. Assume i3 contains the
13748 entire adjustment. Assert i3 contains at least some adjust. */
13750 {
13752 /* fixup_args_size_notes looks at REG_NORETURN note,
13753 so ensure the note is placed there first. */
13755 {
13759 {
13765 }
13766 }
13768 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13769 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13772 && !ACCUMULATE_OUTGOING_ARGS
13774 }
13781 /* These notes must remain with the call. It should not be
13782 possible for both I2 and I3 to be a call. */
13785 else
13786 {
13789 }
13793 /* Any clobbers for i3 may still exist, and so we must process
13794 REG_UNUSED notes from that insn.
13796 Any clobbers from i2 or i1 can only exist if they were added by
13797 recog_for_combine. In that case, recog_for_combine created the
13798 necessary REG_UNUSED notes. Trying to keep any original
13799 REG_UNUSED notes from these insns can cause incorrect output
13800 if it is for the same register as the original i3 dest.
13801 In that case, we will notice that the register is set in i3,
13802 and then add a REG_UNUSED note for the destination of i3, which
13803 is wrong. However, it is possible to have REG_UNUSED notes from
13804 i2 or i1 for register which were both used and clobbered, so
13805 we keep notes from i2 or i1 if they will turn into REG_DEAD
13806 notes. */
13808 /* If this register is set or clobbered in I3, put the note there
13809 unless there is one already. */
13811 {
13819 }
13820 /* Otherwise, if this register is used by I3, then this register
13821 now dies here, so we must put a REG_DEAD note here unless there
13822 is one already. */
13828 {
13831 }
13837 /* These notes say something about results of an insn. We can
13838 only support them if they used to be on I3 in which case they
13839 remain on I3. Otherwise they are ignored.
13841 If the note refers to an expression that is not a constant, we
13842 must also ignore the note since we cannot tell whether the
13843 equivalence is still true. It might be possible to do
13844 slightly better than this (we only have a problem if I2DEST
13845 or I1DEST is present in the expression), but it doesn't
13846 seem worth the trouble. */
13854 /* These notes say something about how a register is used. They must
13855 be present on any use of the register in I2 or I3. */
13860 {
13863 else
13865 }
13870 /* This can show up in several ways -- either directly in the
13871 pattern, or hidden off in the constant pool with (or without?)
13872 a REG_EQUAL note. */
13873 /* ??? Ignore the without-reg_equal-note problem for now. */
13885 {
13888 else
13890 }
13892 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13893 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13894 there. */
13899 {
13906 }
13912 {
13920 }
13924 /* This note says something about the value of a register prior
13925 to the execution of an insn. It is too much trouble to see
13926 if the note is still correct in all situations. It is better
13927 to simply delete it. */
13931 /* If we replaced the right hand side of FROM_INSN with a
13932 REG_EQUAL note, the original use of the dying register
13933 will not have been combined into I3 and I2. In such cases,
13934 FROM_INSN is guaranteed to be the first of the combined
13935 instructions, so we simply need to search back before
13936 FROM_INSN for the previous use or set of this register,
13937 then alter the notes there appropriately.
13939 If the register is used as an input in I3, it dies there.
13940 Similarly for I2, if it is nonzero and adjacent to I3.
13942 If the register is not used as an input in either I3 or I2
13943 and it is not one of the registers we were supposed to eliminate,
13944 there are two possibilities. We might have a non-adjacent I2
13945 or we might have somehow eliminated an additional register
13946 from a computation. For example, we might have had A & B where
13947 we discover that B will always be zero. In this case we will
13948 eliminate the reference to A.
13950 In both cases, we must search to see if we can find a previous
13951 use of A and put the death note there. */
13957 else
13958 {
13969 && !(i2mod
13971 i2mod_old_rhs)))
13976 /* If the new I2 sets the same register that is marked dead
13977 in the note, we do not know where to put the note.
13978 Give up. */
13981 }
13984 {
13988 {
13990 {
13994 }
13996 /* If the register is being set at TEM_INSN, see if that is all
13997 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13998 into a REG_UNUSED note instead. Don't delete sets to
13999 global register vars. */
14003 {
14014 ;
14016 /* Verify that it was the set, and not a clobber that
14017 modified the register.
14019 CC0 targets must be careful to maintain setter/user
14020 pairs. If we cannot delete the setter due to side
14021 effects, mark the user with an UNUSED note instead
14022 of deleting it. */
14026 && (!HAVE_cc0
14030 {
14031 /* Move the notes and links of TEM_INSN elsewhere.
14032 This might delete other dead insns recursively.
14033 First set the pattern to something that won't use
14034 any register. */
14048 /* Delete the setter too. */
14050 {
14063 }
14064 }
14065 else
14066 {
14069 /* If there isn't already a REG_UNUSED note, put one
14070 here. Do not place a REG_DEAD note, even if
14071 the register is also used here; that would not
14072 match the algorithm used in lifetime analysis
14073 and can cause the consistency check in the
14074 scheduler to fail. */
14079 }
14080 }
14084 {
14087 /* If we are doing a 3->2 combination, and we have a
14088 register which formerly died in i3 and was not used
14089 by i2, which now no longer dies in i3 and is used in
14090 i2 but does not die in i2, and place is between i2
14091 and i3, then we may need to move a link from place to
14092 i2. */
14094 && from_insn
14097 {
14101 }
14103 }
14107 }
14109 }
14111 /* If the register is set or already dead at PLACE, we needn't do
14112 anything with this note if it is still a REG_DEAD note.
14113 We check here if it is set at all, not if is it totally replaced,
14114 which is what `dead_or_set_p' checks, so also check for it being
14115 set partially. */
14118 {
14124 {
14125 /* Unless the register previously died in PLACE, clear
14126 last_death. [I no longer understand why this is
14127 being done.] */
14131 }
14132 else
14135 /* If this is a death note for a hard reg that is occupying
14136 multiple registers, ensure that we are still using all
14137 parts of the object. If we find a piece of the object
14138 that is unused, we must arrange for an appropriate REG_DEAD
14139 note to be added for it. However, we can't just emit a USE
14140 and tag the note to it, since the register might actually
14141 be dead; so we recourse, and the recursive call then finds
14142 the previous insn that used this register. */
14145 {
14154 {
14157 }
14160 {
14161 /* Put only REG_DEAD notes for pieces that are
14162 not already dead or set. */
14166 {
14173 {
14175 NULL_RTX);
14179 NULL_RTX);
14180 }
14185 {
14187 {
14191 }
14195 {
14198 }
14199 }
14200 }
14203 }
14204 }
14205 }
14209 /* Any other notes should not be present at this point in the
14210 compilation. */
14212 }
14215 {
14218 }
14222 }
14223 }
14224 \f
14225 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14226 I3, I2, and I1 to new locations. This is also called to add a link
14227 pointing at I3 when I3's destination is changed. */
14229 static void
14231 {
14235 {
14242 /* If the insn that this link points to is a NOTE, ignore it. */
14251 {
14254 {
14270 }
14273 }
14274 else
14284 /* A LOG_LINK is defined as being placed on the first insn that uses
14285 a register and points to the insn that sets the register. Start
14286 searching at the next insn after the target of the link and stop
14287 when we reach a set of the register or the end of the basic block.
14289 Note that this correctly handles the link that used to point from
14290 I3 to I2. Also note that not much searching is typically done here
14291 since most links don't point very far away. */
14300 {
14304 }
14307 {
14310 }
14314 /* If we found a place to put the link, place it there unless there
14315 is already a link to the same insn as LINK at that point. */
14318 {
14326 {
14330 /* Set added_links_insn to the earliest insn we added a
14331 link to. */
14335 }
14336 }
14337 }
14338 }
14339 \f
14340 /* Check for any register or memory mentioned in EQUIV that is not
14341 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14342 of EXPR where some registers may have been replaced by constants. */
14344 static bool
14346 {
14349 {
14354 }
14356 }
14357 \f
14358 DEBUG_FUNCTION void
14360 {
14361 fprintf
14363 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14365 }
14367 void
14369 {
14370 fprintf
14372 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14374 }
14375 \f
14376 /* Try combining insns through substitution. */
14377 static unsigned int
14379 {
14389 rebuild_jump_labels_after_combine
14392 /* Combining insns may have turned an indirect jump into a
14393 direct jump. Rebuild the JUMP_LABEL fields of jumping
14394 instructions. */
14396 {
14403 }
14407 }
14412 {
14422 };
14425 {
14429 {}
14431 /* opt_pass methods: */
14434 {
14436 }
14442 rtl_opt_pass *
14444 {
14446 }