1 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
2 /* { dg-options "-O2 -ftree-vectorize --save-temps" } */
11 void __attribute__ ((noinline
, noclone
))
12 f2 (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
, ITYPE n
)
14 for (ITYPE i
= 0; i
< n
; ++i
)
21 void __attribute__ ((noinline
, noclone
))
22 f3 (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
,
23 TYPE
*__restrict d
, ITYPE n
)
25 for (ITYPE i
= 0; i
< n
; ++i
)
33 void __attribute__ ((noinline
, noclone
))
34 f4 (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
,
35 TYPE
*__restrict d
, TYPE
*__restrict e
, ITYPE n
)
37 for (ITYPE i
= 0; i
< n
; ++i
)
46 void __attribute__ ((noinline
, noclone
))
47 g2 (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
, ITYPE n
)
49 for (ITYPE i
= 0; i
< n
; ++i
)
56 void __attribute__ ((noinline
, noclone
))
57 g3 (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
,
58 TYPE
*__restrict d
, ITYPE n
)
60 for (ITYPE i
= 0; i
< n
; ++i
)
68 void __attribute__ ((noinline
, noclone
))
69 g4 (TYPE
*__restrict a
, TYPE
*__restrict b
, TYPE
*__restrict c
,
70 TYPE
*__restrict d
, TYPE
*__restrict e
, ITYPE n
)
72 for (ITYPE i
= 0; i
< n
; ++i
)
81 /* { dg-final { scan-assembler {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */
82 /* { dg-final { scan-assembler {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */
83 /* { dg-final { scan-assembler {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */
84 /* { dg-final { scan-assembler {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */
85 /* { dg-final { scan-assembler {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */
86 /* { dg-final { scan-assembler {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */