[AArch64] Fix SVE testsuite failures for ILP32 (PR 83846)
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / spill_6.c
blobae9c338f5696a9f743696b58f3d8e1dd991de501
1 /* { dg-do compile } */
2 /* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=scalable" } */
4 #include <stdint.h>
6 void consumer (void *);
8 #define TEST_LOOP(TYPE, VAL) \
9 void \
10 multi_loop_##TYPE (TYPE *x1, TYPE *x2, TYPE *x3, TYPE *x4, int which) \
11 { \
12 if (which) \
13 { \
14 for (int i = 0; i < 7; ++i) \
15 x1[i] += VAL; \
16 consumer (x1); \
17 for (int i = 0; i < 7; ++i) \
18 x2[i] -= VAL; \
19 consumer (x2); \
20 } \
21 else \
22 { \
23 for (int i = 0; i < 7; ++i) \
24 x3[i] &= VAL; \
25 consumer (x3); \
26 } \
27 for (int i = 0; i < 7; ++i) \
28 x4[i] |= VAL; \
29 consumer (x4); \
32 TEST_LOOP (uint8_t, 0x12);
33 TEST_LOOP (uint16_t, 0x1234);
34 TEST_LOOP (uint32_t, 0x12345);
35 TEST_LOOP (uint64_t, 0x123456);
37 /* { dg-final { scan-assembler {\tld1b\tz[0-9]+\.b,} } } */
38 /* { dg-final { scan-assembler {\tld1h\tz[0-9]+\.h,} } } */
39 /* { dg-final { scan-assembler {\tld1w\tz[0-9]+\.s,} } } */
40 /* { dg-final { scan-assembler {\tld1d\tz[0-9]+\.d,} } } */
41 /* { dg-final { scan-assembler-not {\tldr\tz[0-9]} } } */
42 /* { dg-final { scan-assembler-not {\tstr\tz[0-9]} } } */
43 /* { dg-final { scan-assembler-not {\tldr\tp[0-9]} } } */
44 /* { dg-final { scan-assembler-not {\tstr\tp[0-9]} } } */