gcc/reload1.c

   1 /* Reload pseudo regs into hard regs for insns that require hard regs.
   2    Copyright (C) 1987-2015 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 #include "hard-reg-set.h"
  26 #include "rtl-error.h"
  27 #include "tm_p.h"
  28 #include "obstack.h"
  29 #include "insn-config.h"
  30 #include "flags.h"
  31 #include "input.h"
  32 #include "function.h"
  33 #include "symtab.h"
  34 #include "rtl.h"
  35 #include "alias.h"
  36 #include "tree.h"
  37 #include "expmed.h"
  38 #include "dojump.h"
  39 #include "explow.h"
  40 #include "calls.h"
  41 #include "emit-rtl.h"
  42 #include "varasm.h"
  43 #include "stmt.h"
  44 #include "expr.h"
  45 #include "insn-codes.h"
  46 #include "optabs.h"
  47 #include "regs.h"
  48 #include "addresses.h"
  49 #include "predict.h"
  50 #include "dominance.h"
  51 #include "cfg.h"
  52 #include "cfgrtl.h"
  53 #include "cfgbuild.h"
  54 #include "basic-block.h"
  55 #include "df.h"
  56 #include "reload.h"
  57 #include "recog.h"
  58 #include "except.h"
  59 #include "ira.h"
  60 #include "target.h"
  61 #include "dumpfile.h"
  62 #include "rtl-iter.h"
  63
  64 /* This file contains the reload pass of the compiler, which is
  65    run after register allocation has been done.  It checks that
  66    each insn is valid (operands required to be in registers really
  67    are in registers of the proper class) and fixes up invalid ones
  68    by copying values temporarily into registers for the insns
  69    that need them.
  70
  71    The results of register allocation are described by the vector
  72    reg_renumber; the insns still contain pseudo regs, but reg_renumber
  73    can be used to find which hard reg, if any, a pseudo reg is in.
  74
  75    The technique we always use is to free up a few hard regs that are
  76    called ``reload regs'', and for each place where a pseudo reg
  77    must be in a hard reg, copy it temporarily into one of the reload regs.
  78
  79    Reload regs are allocated locally for every instruction that needs
  80    reloads.  When there are pseudos which are allocated to a register that
  81    has been chosen as a reload reg, such pseudos must be ``spilled''.
  82    This means that they go to other hard regs, or to stack slots if no other
  83    available hard regs can be found.  Spilling can invalidate more
  84    insns, requiring additional need for reloads, so we must keep checking
  85    until the process stabilizes.
  86
  87    For machines with different classes of registers, we must keep track
  88    of the register class needed for each reload, and make sure that
  89    we allocate enough reload registers of each class.
  90
  91    The file reload.c contains the code that checks one insn for
  92    validity and reports the reloads that it needs.  This file
  93    is in charge of scanning the entire rtl code, accumulating the
  94    reload needs, spilling, assigning reload registers to use for
  95    fixing up each insn, and generating the new insns to copy values
  96    into the reload registers.  */
  97 \f
  98 struct target_reload default_target_reload;
  99 #if SWITCHABLE_TARGET
 100 struct target_reload *this_target_reload = &default_target_reload;
 101 #endif
 102
 103 #define spill_indirect_levels                   \
 104   (this_target_reload->x_spill_indirect_levels)
 105
 106 /* During reload_as_needed, element N contains a REG rtx for the hard reg
 107    into which reg N has been reloaded (perhaps for a previous insn).  */
 108 static rtx *reg_last_reload_reg;
 109
 110 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
 111    for an output reload that stores into reg N.  */
 112 static regset_head reg_has_output_reload;
 113
 114 /* Indicates which hard regs are reload-registers for an output reload
 115    in the current insn.  */
 116 static HARD_REG_SET reg_is_output_reload;
 117
 118 /* Widest width in which each pseudo reg is referred to (via subreg).  */
 119 static unsigned int *reg_max_ref_width;
 120
 121 /* Vector to remember old contents of reg_renumber before spilling.  */
 122 static short *reg_old_renumber;
 123
 124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
 125    into hard register N.  If that pseudo reg occupied more than one register,
 126    reg_reloaded_contents points to that pseudo for each spill register in
 127    use; all of these must remain set for an inheritance to occur.  */
 128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
 129
 130 /* During reload_as_needed, element N contains the insn for which
 131    hard register N was last used.   Its contents are significant only
 132    when reg_reloaded_valid is set for this register.  */
 133 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
 134
 135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid.  */
 136 static HARD_REG_SET reg_reloaded_valid;
 137 /* Indicate if the register was dead at the end of the reload.
 138    This is only valid if reg_reloaded_contents is set and valid.  */
 139 static HARD_REG_SET reg_reloaded_dead;
 140
 141 /* Indicate whether the register's current value is one that is not
 142    safe to retain across a call, even for registers that are normally
 143    call-saved.  This is only meaningful for members of reg_reloaded_valid.  */
 144 static HARD_REG_SET reg_reloaded_call_part_clobbered;
 145
 146 /* Number of spill-regs so far; number of valid elements of spill_regs.  */
 147 static int n_spills;
 148
 149 /* In parallel with spill_regs, contains REG rtx's for those regs.
 150    Holds the last rtx used for any given reg, or 0 if it has never
 151    been used for spilling yet.  This rtx is reused, provided it has
 152    the proper mode.  */
 153 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
 154
 155 /* In parallel with spill_regs, contains nonzero for a spill reg
 156    that was stored after the last time it was used.
 157    The precise value is the insn generated to do the store.  */
 158 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
 159
 160 /* This is the register that was stored with spill_reg_store.  This is a
 161    copy of reload_out / reload_out_reg when the value was stored; if
 162    reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg.  */
 163 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
 164
 165 /* This table is the inverse mapping of spill_regs:
 166    indexed by hard reg number,
 167    it contains the position of that reg in spill_regs,
 168    or -1 for something that is not in spill_regs.
 169
 170    ?!?  This is no longer accurate.  */
 171 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
 172
 173 /* This reg set indicates registers that can't be used as spill registers for
 174    the currently processed insn.  These are the hard registers which are live
 175    during the insn, but not allocated to pseudos, as well as fixed
 176    registers.  */
 177 static HARD_REG_SET bad_spill_regs;
 178
 179 /* These are the hard registers that can't be used as spill register for any
 180    insn.  This includes registers used for user variables and registers that
 181    we can't eliminate.  A register that appears in this set also can't be used
 182    to retry register allocation.  */
 183 static HARD_REG_SET bad_spill_regs_global;
 184
 185 /* Describes order of use of registers for reloading
 186    of spilled pseudo-registers.  `n_spills' is the number of
 187    elements that are actually valid; new ones are added at the end.
 188
 189    Both spill_regs and spill_reg_order are used on two occasions:
 190    once during find_reload_regs, where they keep track of the spill registers
 191    for a single insn, but also during reload_as_needed where they show all
 192    the registers ever used by reload.  For the latter case, the information
 193    is calculated during finish_spills.  */
 194 static short spill_regs[FIRST_PSEUDO_REGISTER];
 195
 196 /* This vector of reg sets indicates, for each pseudo, which hard registers
 197    may not be used for retrying global allocation because the register was
 198    formerly spilled from one of them.  If we allowed reallocating a pseudo to
 199    a register that it was already allocated to, reload might not
 200    terminate.  */
 201 static HARD_REG_SET *pseudo_previous_regs;
 202
 203 /* This vector of reg sets indicates, for each pseudo, which hard
 204    registers may not be used for retrying global allocation because they
 205    are used as spill registers during one of the insns in which the
 206    pseudo is live.  */
 207 static HARD_REG_SET *pseudo_forbidden_regs;
 208
 209 /* All hard regs that have been used as spill registers for any insn are
 210    marked in this set.  */
 211 static HARD_REG_SET used_spill_regs;
 212
 213 /* Index of last register assigned as a spill register.  We allocate in
 214    a round-robin fashion.  */
 215 static int last_spill_reg;
 216
 217 /* Record the stack slot for each spilled hard register.  */
 218 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
 219
 220 /* Width allocated so far for that stack slot.  */
 221 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
 222
 223 /* Record which pseudos needed to be spilled.  */
 224 static regset_head spilled_pseudos;
 225
 226 /* Record which pseudos changed their allocation in finish_spills.  */
 227 static regset_head changed_allocation_pseudos;
 228
 229 /* Used for communication between order_regs_for_reload and count_pseudo.
 230    Used to avoid counting one pseudo twice.  */
 231 static regset_head pseudos_counted;
 232
 233 /* First uid used by insns created by reload in this function.
 234    Used in find_equiv_reg.  */
 235 int reload_first_uid;
 236
 237 /* Flag set by local-alloc or global-alloc if anything is live in
 238    a call-clobbered reg across calls.  */
 239 int caller_save_needed;
 240
 241 /* Set to 1 while reload_as_needed is operating.
 242    Required by some machines to handle any generated moves differently.  */
 243 int reload_in_progress = 0;
 244
 245 /* This obstack is used for allocation of rtl during register elimination.
 246    The allocated storage can be freed once find_reloads has processed the
 247    insn.  */
 248 static struct obstack reload_obstack;
 249
 250 /* Points to the beginning of the reload_obstack.  All insn_chain structures
 251    are allocated first.  */
 252 static char *reload_startobj;
 253
 254 /* The point after all insn_chain structures.  Used to quickly deallocate
 255    memory allocated in copy_reloads during calculate_needs_all_insns.  */
 256 static char *reload_firstobj;
 257
 258 /* This points before all local rtl generated by register elimination.
 259    Used to quickly free all memory after processing one insn.  */
 260 static char *reload_insn_firstobj;
 261
 262 /* List of insn_chain instructions, one for every insn that reload needs to
 263    examine.  */
 264 struct insn_chain *reload_insn_chain;
 265
 266 /* TRUE if we potentially left dead insns in the insn stream and want to
 267    run DCE immediately after reload, FALSE otherwise.  */
 268 static bool need_dce;
 269
 270 /* List of all insns needing reloads.  */
 271 static struct insn_chain *insns_need_reload;
 272 \f
 273 /* This structure is used to record information about register eliminations.
 274    Each array entry describes one possible way of eliminating a register
 275    in favor of another.   If there is more than one way of eliminating a
 276    particular register, the most preferred should be specified first.  */
 277
 278 struct elim_table
 279 {
 280   int from;                     /* Register number to be eliminated.  */
 281   int to;                       /* Register number used as replacement.  */
 282   HOST_WIDE_INT initial_offset; /* Initial difference between values.  */
 283   int can_eliminate;            /* Nonzero if this elimination can be done.  */
 284   int can_eliminate_previous;   /* Value returned by TARGET_CAN_ELIMINATE
 285                                    target hook in previous scan over insns
 286                                    made by reload.  */
 287   HOST_WIDE_INT offset;         /* Current offset between the two regs.  */
 288   HOST_WIDE_INT previous_offset;/* Offset at end of previous insn.  */
 289   int ref_outside_mem;          /* "to" has been referenced outside a MEM.  */
 290   rtx from_rtx;                 /* REG rtx for the register to be eliminated.
 291                                    We cannot simply compare the number since
 292                                    we might then spuriously replace a hard
 293                                    register corresponding to a pseudo
 294                                    assigned to the reg to be eliminated.  */
 295   rtx to_rtx;                   /* REG rtx for the replacement.  */
 296 };
 297
 298 static struct elim_table *reg_eliminate = 0;
 299
 300 /* This is an intermediate structure to initialize the table.  It has
 301    exactly the members provided by ELIMINABLE_REGS.  */
 302 static const struct elim_table_1
 303 {
 304   const int from;
 305   const int to;
 306 } reg_eliminate_1[] =
 307
 308 /* If a set of eliminable registers was specified, define the table from it.
 309    Otherwise, default to the normal case of the frame pointer being
 310    replaced by the stack pointer.  */
 311
 312 #ifdef ELIMINABLE_REGS
 313   ELIMINABLE_REGS;
 314 #else
 315   {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
 316 #endif
 317
 318 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
 319
 320 /* Record the number of pending eliminations that have an offset not equal
 321    to their initial offset.  If nonzero, we use a new copy of each
 322    replacement result in any insns encountered.  */
 323 int num_not_at_initial_offset;
 324
 325 /* Count the number of registers that we may be able to eliminate.  */
 326 static int num_eliminable;
 327 /* And the number of registers that are equivalent to a constant that
 328    can be eliminated to frame_pointer / arg_pointer + constant.  */
 329 static int num_eliminable_invariants;
 330
 331 /* For each label, we record the offset of each elimination.  If we reach
 332    a label by more than one path and an offset differs, we cannot do the
 333    elimination.  This information is indexed by the difference of the
 334    number of the label and the first label number.  We can't offset the
 335    pointer itself as this can cause problems on machines with segmented
 336    memory.  The first table is an array of flags that records whether we
 337    have yet encountered a label and the second table is an array of arrays,
 338    one entry in the latter array for each elimination.  */
 339
 340 static int first_label_num;
 341 static char *offsets_known_at;
 342 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
 343
 344 vec<reg_equivs_t, va_gc> *reg_equivs;
 345
 346 /* Stack of addresses where an rtx has been changed.  We can undo the
 347    changes by popping items off the stack and restoring the original
 348    value at each location.
 349
 350    We use this simplistic undo capability rather than copy_rtx as copy_rtx
 351    will not make a deep copy of a normally sharable rtx, such as
 352    (const (plus (symbol_ref) (const_int))).  If such an expression appears
 353    as R1 in gen_reload_chain_without_interm_reg_p, then a shared
 354    rtx expression would be changed.  See PR 42431.  */
 355
 356 typedef rtx *rtx_p;
 357 static vec<rtx_p> substitute_stack;
 358
 359 /* Number of labels in the current function.  */
 360
 361 static int num_labels;
 362 \f
 363 static void replace_pseudos_in (rtx *, machine_mode, rtx);
 364 static void maybe_fix_stack_asms (void);
 365 static void copy_reloads (struct insn_chain *);
 366 static void calculate_needs_all_insns (int);
 367 static int find_reg (struct insn_chain *, int);
 368 static void find_reload_regs (struct insn_chain *);
 369 static void select_reload_regs (void);
 370 static void delete_caller_save_insns (void);
 371
 372 static void spill_failure (rtx_insn *, enum reg_class);
 373 static void count_spilled_pseudo (int, int, int);
 374 static void delete_dead_insn (rtx_insn *);
 375 static void alter_reg (int, int, bool);
 376 static void set_label_offsets (rtx, rtx_insn *, int);
 377 static void check_eliminable_occurrences (rtx);
 378 static void elimination_effects (rtx, machine_mode);
 379 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
 380 static int eliminate_regs_in_insn (rtx_insn *, int);
 381 static void update_eliminable_offsets (void);
 382 static void mark_not_eliminable (rtx, const_rtx, void *);
 383 static void set_initial_elim_offsets (void);
 384 static bool verify_initial_elim_offsets (void);
 385 static void set_initial_label_offsets (void);
 386 static void set_offsets_for_label (rtx_insn *);
 387 static void init_eliminable_invariants (rtx_insn *, bool);
 388 static void init_elim_table (void);
 389 static void free_reg_equiv (void);
 390 static void update_eliminables (HARD_REG_SET *);
 391 static bool update_eliminables_and_spill (void);
 392 static void elimination_costs_in_insn (rtx_insn *);
 393 static void spill_hard_reg (unsigned int, int);
 394 static int finish_spills (int);
 395 static void scan_paradoxical_subregs (rtx);
 396 static void count_pseudo (int);
 397 static void order_regs_for_reload (struct insn_chain *);
 398 static void reload_as_needed (int);
 399 static void forget_old_reloads_1 (rtx, const_rtx, void *);
 400 static void forget_marked_reloads (regset);
 401 static int reload_reg_class_lower (const void *, const void *);
 402 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
 403                                     machine_mode);
 404 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
 405                                      machine_mode);
 406 static int reload_reg_free_p (unsigned int, int, enum reload_type);
 407 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
 408                                         rtx, rtx, int, int);
 409 static int free_for_value_p (int, machine_mode, int, enum reload_type,
 410                              rtx, rtx, int, int);
 411 static int allocate_reload_reg (struct insn_chain *, int, int);
 412 static int conflicts_with_override (rtx);
 413 static void failed_reload (rtx_insn *, int);
 414 static int set_reload_reg (int, int);
 415 static void choose_reload_regs_init (struct insn_chain *, rtx *);
 416 static void choose_reload_regs (struct insn_chain *);
 417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
 418                                      rtx, int);
 419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
 420                                       int);
 421 static void do_input_reload (struct insn_chain *, struct reload *, int);
 422 static void do_output_reload (struct insn_chain *, struct reload *, int);
 423 static void emit_reload_insns (struct insn_chain *);
 424 static void delete_output_reload (rtx_insn *, int, int, rtx);
 425 static void delete_address_reloads (rtx_insn *, rtx_insn *);
 426 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
 427 static void inc_for_reload (rtx, rtx, rtx, int);
 428 #ifdef AUTO_INC_DEC
 429 static void add_auto_inc_notes (rtx_insn *, rtx);
 430 #endif
 431 static void substitute (rtx *, const_rtx, rtx);
 432 static bool gen_reload_chain_without_interm_reg_p (int, int);
 433 static int reloads_conflict (int, int);
 434 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
 435 static rtx_insn *emit_insn_if_valid_for_reload (rtx);
 436 \f
 437 /* Initialize the reload pass.  This is called at the beginning of compilation
 438    and may be called again if the target is reinitialized.  */
 439
 440 void
 441 init_reload (void)
 442 {
 443   int i;
 444
 445   /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
 446      Set spill_indirect_levels to the number of levels such addressing is
 447      permitted, zero if it is not permitted at all.  */
 448
 449   rtx tem
 450     = gen_rtx_MEM (Pmode,
 451                    gen_rtx_PLUS (Pmode,
 452                                  gen_rtx_REG (Pmode,
 453                                               LAST_VIRTUAL_REGISTER + 1),
 454                                  gen_int_mode (4, Pmode)));
 455   spill_indirect_levels = 0;
 456
 457   while (memory_address_p (QImode, tem))
 458     {
 459       spill_indirect_levels++;
 460       tem = gen_rtx_MEM (Pmode, tem);
 461     }
 462
 463   /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)).  */
 464
 465   tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
 466   indirect_symref_ok = memory_address_p (QImode, tem);
 467
 468   /* See if reg+reg is a valid (and offsettable) address.  */
 469
 470   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 471     {
 472       tem = gen_rtx_PLUS (Pmode,
 473                           gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
 474                           gen_rtx_REG (Pmode, i));
 475
 476       /* This way, we make sure that reg+reg is an offsettable address.  */
 477       tem = plus_constant (Pmode, tem, 4);
 478
 479       if (memory_address_p (QImode, tem))
 480         {
 481           double_reg_address_ok = 1;
 482           break;
 483         }
 484     }
 485
 486   /* Initialize obstack for our rtl allocation.  */
 487   if (reload_startobj == NULL)
 488     {
 489       gcc_obstack_init (&reload_obstack);
 490       reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
 491     }
 492
 493   INIT_REG_SET (&spilled_pseudos);
 494   INIT_REG_SET (&changed_allocation_pseudos);
 495   INIT_REG_SET (&pseudos_counted);
 496 }
 497
 498 /* List of insn chains that are currently unused.  */
 499 static struct insn_chain *unused_insn_chains = 0;
 500
 501 /* Allocate an empty insn_chain structure.  */
 502 struct insn_chain *
 503 new_insn_chain (void)
 504 {
 505   struct insn_chain *c;
 506
 507   if (unused_insn_chains == 0)
 508     {
 509       c = XOBNEW (&reload_obstack, struct insn_chain);
 510       INIT_REG_SET (&c->live_throughout);
 511       INIT_REG_SET (&c->dead_or_set);
 512     }
 513   else
 514     {
 515       c = unused_insn_chains;
 516       unused_insn_chains = c->next;
 517     }
 518   c->is_caller_save_insn = 0;
 519   c->need_operand_change = 0;
 520   c->need_reload = 0;
 521   c->need_elim = 0;
 522   return c;
 523 }
 524
 525 /* Small utility function to set all regs in hard reg set TO which are
 526    allocated to pseudos in regset FROM.  */
 527
 528 void
 529 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
 530 {
 531   unsigned int regno;
 532   reg_set_iterator rsi;
 533
 534   EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
 535     {
 536       int r = reg_renumber[regno];
 537
 538       if (r < 0)
 539         {
 540           /* reload_combine uses the information from DF_LIVE_IN,
 541              which might still contain registers that have not
 542              actually been allocated since they have an
 543              equivalence.  */
 544           gcc_assert (ira_conflicts_p || reload_completed);
 545         }
 546       else
 547         add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
 548     }
 549 }
 550
 551 /* Replace all pseudos found in LOC with their corresponding
 552    equivalences.  */
 553
 554 static void
 555 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
 556 {
 557   rtx x = *loc;
 558   enum rtx_code code;
 559   const char *fmt;
 560   int i, j;
 561
 562   if (! x)
 563     return;
 564
 565   code = GET_CODE (x);
 566   if (code == REG)
 567     {
 568       unsigned int regno = REGNO (x);
 569
 570       if (regno < FIRST_PSEUDO_REGISTER)
 571         return;
 572
 573       x = eliminate_regs_1 (x, mem_mode, usage, true, false);
 574       if (x != *loc)
 575         {
 576           *loc = x;
 577           replace_pseudos_in (loc, mem_mode, usage);
 578           return;
 579         }
 580
 581       if (reg_equiv_constant (regno))
 582         *loc = reg_equiv_constant (regno);
 583       else if (reg_equiv_invariant (regno))
 584         *loc = reg_equiv_invariant (regno);
 585       else if (reg_equiv_mem (regno))
 586         *loc = reg_equiv_mem (regno);
 587       else if (reg_equiv_address (regno))
 588         *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
 589       else
 590         {
 591           gcc_assert (!REG_P (regno_reg_rtx[regno])
 592                       || REGNO (regno_reg_rtx[regno]) != regno);
 593           *loc = regno_reg_rtx[regno];
 594         }
 595
 596       return;
 597     }
 598   else if (code == MEM)
 599     {
 600       replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
 601       return;
 602     }
 603
 604   /* Process each of our operands recursively.  */
 605   fmt = GET_RTX_FORMAT (code);
 606   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
 607     if (*fmt == 'e')
 608       replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
 609     else if (*fmt == 'E')
 610       for (j = 0; j < XVECLEN (x, i); j++)
 611         replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
 612 }
 613
 614 /* Determine if the current function has an exception receiver block
 615    that reaches the exit block via non-exceptional edges  */
 616
 617 static bool
 618 has_nonexceptional_receiver (void)
 619 {
 620   edge e;
 621   edge_iterator ei;
 622   basic_block *tos, *worklist, bb;
 623
 624   /* If we're not optimizing, then just err on the safe side.  */
 625   if (!optimize)
 626     return true;
 627
 628   /* First determine which blocks can reach exit via normal paths.  */
 629   tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
 630
 631   FOR_EACH_BB_FN (bb, cfun)
 632     bb->flags &= ~BB_REACHABLE;
 633
 634   /* Place the exit block on our worklist.  */
 635   EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
 636   *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
 637
 638   /* Iterate: find everything reachable from what we've already seen.  */
 639   while (tos != worklist)
 640     {
 641       bb = *--tos;
 642
 643       FOR_EACH_EDGE (e, ei, bb->preds)
 644         if (!(e->flags & EDGE_ABNORMAL))
 645           {
 646             basic_block src = e->src;
 647
 648             if (!(src->flags & BB_REACHABLE))
 649               {
 650                 src->flags |= BB_REACHABLE;
 651                 *tos++ = src;
 652               }
 653           }
 654     }
 655   free (worklist);
 656
 657   /* Now see if there's a reachable block with an exceptional incoming
 658      edge.  */
 659   FOR_EACH_BB_FN (bb, cfun)
 660     if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
 661       return true;
 662
 663   /* No exceptional block reached exit unexceptionally.  */
 664   return false;
 665 }
 666
 667 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
 668    zero elements) to MAX_REG_NUM elements.
 669
 670    Initialize all new fields to NULL and update REG_EQUIVS_SIZE.  */
 671 void
 672 grow_reg_equivs (void)
 673 {
 674   int old_size = vec_safe_length (reg_equivs);
 675   int max_regno = max_reg_num ();
 676   int i;
 677   reg_equivs_t ze;
 678
 679   memset (&ze, 0, sizeof (reg_equivs_t));
 680   vec_safe_reserve (reg_equivs, max_regno);
 681   for (i = old_size; i < max_regno; i++)
 682     reg_equivs->quick_insert (i, ze);
 683 }
 684
 685 \f
 686 /* Global variables used by reload and its subroutines.  */
 687
 688 /* The current basic block while in calculate_elim_costs_all_insns.  */
 689 static basic_block elim_bb;
 690
 691 /* Set during calculate_needs if an insn needs register elimination.  */
 692 static int something_needs_elimination;
 693 /* Set during calculate_needs if an insn needs an operand changed.  */
 694 static int something_needs_operands_changed;
 695 /* Set by alter_regs if we spilled a register to the stack.  */
 696 static bool something_was_spilled;
 697
 698 /* Nonzero means we couldn't get enough spill regs.  */
 699 static int failure;
 700
 701 /* Temporary array of pseudo-register number.  */
 702 static int *temp_pseudo_reg_arr;
 703
 704 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
 705    If that insn didn't set the register (i.e., it copied the register to
 706    memory), just delete that insn instead of the equivalencing insn plus
 707    anything now dead.  If we call delete_dead_insn on that insn, we may
 708    delete the insn that actually sets the register if the register dies
 709    there and that is incorrect.  */
 710 static void
 711 remove_init_insns ()
 712 {
 713   for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 714     {
 715       if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
 716         {
 717           rtx list;
 718           for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
 719             {
 720               rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
 721
 722               /* If we already deleted the insn or if it may trap, we can't
 723                  delete it.  The latter case shouldn't happen, but can
 724                  if an insn has a variable address, gets a REG_EH_REGION
 725                  note added to it, and then gets converted into a load
 726                  from a constant address.  */
 727               if (NOTE_P (equiv_insn)
 728                   || can_throw_internal (equiv_insn))
 729                 ;
 730               else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
 731                 delete_dead_insn (equiv_insn);
 732               else
 733                 SET_INSN_DELETED (equiv_insn);
 734             }
 735         }
 736     }
 737 }
 738
 739 /* Return true if remove_init_insns will delete INSN.  */
 740 static bool
 741 will_delete_init_insn_p (rtx_insn *insn)
 742 {
 743   rtx set = single_set (insn);
 744   if (!set || !REG_P (SET_DEST (set)))
 745     return false;
 746   unsigned regno = REGNO (SET_DEST (set));
 747
 748   if (can_throw_internal (insn))
 749     return false;
 750
 751   if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
 752     return false;
 753
 754   for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
 755     {
 756       rtx equiv_insn = XEXP (list, 0);
 757       if (equiv_insn == insn)
 758         return true;
 759     }
 760   return false;
 761 }
 762
 763 /* Main entry point for the reload pass.
 764
 765    FIRST is the first insn of the function being compiled.
 766
 767    GLOBAL nonzero means we were called from global_alloc
 768    and should attempt to reallocate any pseudoregs that we
 769    displace from hard regs we will use for reloads.
 770    If GLOBAL is zero, we do not have enough information to do that,
 771    so any pseudo reg that is spilled must go to the stack.
 772
 773    Return value is TRUE if reload likely left dead insns in the
 774    stream and a DCE pass should be run to elimiante them.  Else the
 775    return value is FALSE.  */
 776
 777 bool
 778 reload (rtx_insn *first, int global)
 779 {
 780   int i, n;
 781   rtx_insn *insn;
 782   struct elim_table *ep;
 783   basic_block bb;
 784   bool inserted;
 785
 786   /* Make sure even insns with volatile mem refs are recognizable.  */
 787   init_recog ();
 788
 789   failure = 0;
 790
 791   reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
 792
 793   /* Make sure that the last insn in the chain
 794      is not something that needs reloading.  */
 795   emit_note (NOTE_INSN_DELETED);
 796
 797   /* Enable find_equiv_reg to distinguish insns made by reload.  */
 798   reload_first_uid = get_max_uid ();
 799
 800 #ifdef SECONDARY_MEMORY_NEEDED
 801   /* Initialize the secondary memory table.  */
 802   clear_secondary_mem ();
 803 #endif
 804
 805   /* We don't have a stack slot for any spill reg yet.  */
 806   memset (spill_stack_slot, 0, sizeof spill_stack_slot);
 807   memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
 808
 809   /* Initialize the save area information for caller-save, in case some
 810      are needed.  */
 811   init_save_areas ();
 812
 813   /* Compute which hard registers are now in use
 814      as homes for pseudo registers.
 815      This is done here rather than (eg) in global_alloc
 816      because this point is reached even if not optimizing.  */
 817   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 818     mark_home_live (i);
 819
 820   /* A function that has a nonlocal label that can reach the exit
 821      block via non-exceptional paths must save all call-saved
 822      registers.  */
 823   if (cfun->has_nonlocal_label
 824       && has_nonexceptional_receiver ())
 825     crtl->saves_all_registers = 1;
 826
 827   if (crtl->saves_all_registers)
 828     for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 829       if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
 830         df_set_regs_ever_live (i, true);
 831
 832   /* Find all the pseudo registers that didn't get hard regs
 833      but do have known equivalent constants or memory slots.
 834      These include parameters (known equivalent to parameter slots)
 835      and cse'd or loop-moved constant memory addresses.
 836
 837      Record constant equivalents in reg_equiv_constant
 838      so they will be substituted by find_reloads.
 839      Record memory equivalents in reg_mem_equiv so they can
 840      be substituted eventually by altering the REG-rtx's.  */
 841
 842   grow_reg_equivs ();
 843   reg_old_renumber = XCNEWVEC (short, max_regno);
 844   memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
 845   pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
 846   pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
 847
 848   CLEAR_HARD_REG_SET (bad_spill_regs_global);
 849
 850   init_eliminable_invariants (first, true);
 851   init_elim_table ();
 852
 853   /* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
 854      stack slots to the pseudos that lack hard regs or equivalents.
 855      Do not touch virtual registers.  */
 856
 857   temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
 858   for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
 859     temp_pseudo_reg_arr[n++] = i;
 860
 861   if (ira_conflicts_p)
 862     /* Ask IRA to order pseudo-registers for better stack slot
 863        sharing.  */
 864     ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
 865
 866   for (i = 0; i < n; i++)
 867     alter_reg (temp_pseudo_reg_arr[i], -1, false);
 868
 869   /* If we have some registers we think can be eliminated, scan all insns to
 870      see if there is an insn that sets one of these registers to something
 871      other than itself plus a constant.  If so, the register cannot be
 872      eliminated.  Doing this scan here eliminates an extra pass through the
 873      main reload loop in the most common case where register elimination
 874      cannot be done.  */
 875   for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
 876     if (INSN_P (insn))
 877       note_stores (PATTERN (insn), mark_not_eliminable, NULL);
 878
 879   maybe_fix_stack_asms ();
 880
 881   insns_need_reload = 0;
 882   something_needs_elimination = 0;
 883
 884   /* Initialize to -1, which means take the first spill register.  */
 885   last_spill_reg = -1;
 886
 887   /* Spill any hard regs that we know we can't eliminate.  */
 888   CLEAR_HARD_REG_SET (used_spill_regs);
 889   /* There can be multiple ways to eliminate a register;
 890      they should be listed adjacently.
 891      Elimination for any register fails only if all possible ways fail.  */
 892   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
 893     {
 894       int from = ep->from;
 895       int can_eliminate = 0;
 896       do
 897         {
 898           can_eliminate |= ep->can_eliminate;
 899           ep++;
 900         }
 901       while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
 902       if (! can_eliminate)
 903         spill_hard_reg (from, 1);
 904     }
 905
 906   if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
 907     spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
 908
 909   finish_spills (global);
 910
 911   /* From now on, we may need to generate moves differently.  We may also
 912      allow modifications of insns which cause them to not be recognized.
 913      Any such modifications will be cleaned up during reload itself.  */
 914   reload_in_progress = 1;
 915
 916   /* This loop scans the entire function each go-round
 917      and repeats until one repetition spills no additional hard regs.  */
 918   for (;;)
 919     {
 920       int something_changed;
 921       int did_spill;
 922       HOST_WIDE_INT starting_frame_size;
 923
 924       starting_frame_size = get_frame_size ();
 925       something_was_spilled = false;
 926
 927       set_initial_elim_offsets ();
 928       set_initial_label_offsets ();
 929
 930       /* For each pseudo register that has an equivalent location defined,
 931          try to eliminate any eliminable registers (such as the frame pointer)
 932          assuming initial offsets for the replacement register, which
 933          is the normal case.
 934
 935          If the resulting location is directly addressable, substitute
 936          the MEM we just got directly for the old REG.
 937
 938          If it is not addressable but is a constant or the sum of a hard reg
 939          and constant, it is probably not addressable because the constant is
 940          out of range, in that case record the address; we will generate
 941          hairy code to compute the address in a register each time it is
 942          needed.  Similarly if it is a hard register, but one that is not
 943          valid as an address register.
 944
 945          If the location is not addressable, but does not have one of the
 946          above forms, assign a stack slot.  We have to do this to avoid the
 947          potential of producing lots of reloads if, e.g., a location involves
 948          a pseudo that didn't get a hard register and has an equivalent memory
 949          location that also involves a pseudo that didn't get a hard register.
 950
 951          Perhaps at some point we will improve reload_when_needed handling
 952          so this problem goes away.  But that's very hairy.  */
 953
 954       for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
 955         if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
 956           {
 957             rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
 958                                     NULL_RTX);
 959
 960             if (strict_memory_address_addr_space_p
 961                   (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
 962                    MEM_ADDR_SPACE (x)))
 963               reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
 964             else if (CONSTANT_P (XEXP (x, 0))
 965                      || (REG_P (XEXP (x, 0))
 966                          && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
 967                      || (GET_CODE (XEXP (x, 0)) == PLUS
 968                          && REG_P (XEXP (XEXP (x, 0), 0))
 969                          && (REGNO (XEXP (XEXP (x, 0), 0))
 970                              < FIRST_PSEUDO_REGISTER)
 971                          && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
 972               reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
 973             else
 974               {
 975                 /* Make a new stack slot.  Then indicate that something
 976                    changed so we go back and recompute offsets for
 977                    eliminable registers because the allocation of memory
 978                    below might change some offset.  reg_equiv_{mem,address}
 979                    will be set up for this pseudo on the next pass around
 980                    the loop.  */
 981                 reg_equiv_memory_loc (i) = 0;
 982                 reg_equiv_init (i) = 0;
 983                 alter_reg (i, -1, true);
 984               }
 985           }
 986
 987       if (caller_save_needed)
 988         setup_save_areas ();
 989
 990       if (starting_frame_size && crtl->stack_alignment_needed)
 991         {
 992           /* If we have a stack frame, we must align it now.  The
 993              stack size may be a part of the offset computation for
 994              register elimination.  So if this changes the stack size,
 995              then repeat the elimination bookkeeping.  We don't
 996              realign when there is no stack, as that will cause a
 997              stack frame when none is needed should
 998              STARTING_FRAME_OFFSET not be already aligned to
 999              STACK_BOUNDARY.  */
1000           assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1001         }
1002       /* If we allocated another stack slot, redo elimination bookkeeping.  */
1003       if (something_was_spilled || starting_frame_size != get_frame_size ())
1004         {
1005           update_eliminables_and_spill ();
1006           continue;
1007         }
1008
1009       if (caller_save_needed)
1010         {
1011           save_call_clobbered_regs ();
1012           /* That might have allocated new insn_chain structures.  */
1013           reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1014         }
1015
1016       calculate_needs_all_insns (global);
1017
1018       if (! ira_conflicts_p)
1019         /* Don't do it for IRA.  We need this info because we don't
1020            change live_throughout and dead_or_set for chains when IRA
1021            is used.  */
1022         CLEAR_REG_SET (&spilled_pseudos);
1023
1024       did_spill = 0;
1025
1026       something_changed = 0;
1027
1028       /* If we allocated any new memory locations, make another pass
1029          since it might have changed elimination offsets.  */
1030       if (something_was_spilled || starting_frame_size != get_frame_size ())
1031         something_changed = 1;
1032
1033       /* Even if the frame size remained the same, we might still have
1034          changed elimination offsets, e.g. if find_reloads called
1035          force_const_mem requiring the back end to allocate a constant
1036          pool base register that needs to be saved on the stack.  */
1037       else if (!verify_initial_elim_offsets ())
1038         something_changed = 1;
1039
1040       if (update_eliminables_and_spill ())
1041         {
1042           did_spill = 1;
1043           something_changed = 1;
1044         }
1045
1046       select_reload_regs ();
1047       if (failure)
1048         goto failed;
1049
1050       if (insns_need_reload != 0 || did_spill)
1051         something_changed |= finish_spills (global);
1052
1053       if (! something_changed)
1054         break;
1055
1056       if (caller_save_needed)
1057         delete_caller_save_insns ();
1058
1059       obstack_free (&reload_obstack, reload_firstobj);
1060     }
1061
1062   /* If global-alloc was run, notify it of any register eliminations we have
1063      done.  */
1064   if (global)
1065     for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1066       if (ep->can_eliminate)
1067         mark_elimination (ep->from, ep->to);
1068
1069   remove_init_insns ();
1070
1071   /* Use the reload registers where necessary
1072      by generating move instructions to move the must-be-register
1073      values into or out of the reload registers.  */
1074
1075   if (insns_need_reload != 0 || something_needs_elimination
1076       || something_needs_operands_changed)
1077     {
1078       HOST_WIDE_INT old_frame_size = get_frame_size ();
1079
1080       reload_as_needed (global);
1081
1082       gcc_assert (old_frame_size == get_frame_size ());
1083
1084       gcc_assert (verify_initial_elim_offsets ());
1085     }
1086
1087   /* If we were able to eliminate the frame pointer, show that it is no
1088      longer live at the start of any basic block.  If it ls live by
1089      virtue of being in a pseudo, that pseudo will be marked live
1090      and hence the frame pointer will be known to be live via that
1091      pseudo.  */
1092
1093   if (! frame_pointer_needed)
1094     FOR_EACH_BB_FN (bb, cfun)
1095       bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1096
1097   /* Come here (with failure set nonzero) if we can't get enough spill
1098      regs.  */
1099  failed:
1100
1101   CLEAR_REG_SET (&changed_allocation_pseudos);
1102   CLEAR_REG_SET (&spilled_pseudos);
1103   reload_in_progress = 0;
1104
1105   /* Now eliminate all pseudo regs by modifying them into
1106      their equivalent memory references.
1107      The REG-rtx's for the pseudos are modified in place,
1108      so all insns that used to refer to them now refer to memory.
1109
1110      For a reg that has a reg_equiv_address, all those insns
1111      were changed by reloading so that no insns refer to it any longer;
1112      but the DECL_RTL of a variable decl may refer to it,
1113      and if so this causes the debugging info to mention the variable.  */
1114
1115   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1116     {
1117       rtx addr = 0;
1118
1119       if (reg_equiv_mem (i))
1120         addr = XEXP (reg_equiv_mem (i), 0);
1121
1122       if (reg_equiv_address (i))
1123         addr = reg_equiv_address (i);
1124
1125       if (addr)
1126         {
1127           if (reg_renumber[i] < 0)
1128             {
1129               rtx reg = regno_reg_rtx[i];
1130
1131               REG_USERVAR_P (reg) = 0;
1132               PUT_CODE (reg, MEM);
1133               XEXP (reg, 0) = addr;
1134               if (reg_equiv_memory_loc (i))
1135                 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1136               else
1137                 MEM_ATTRS (reg) = 0;
1138               MEM_NOTRAP_P (reg) = 1;
1139             }
1140           else if (reg_equiv_mem (i))
1141             XEXP (reg_equiv_mem (i), 0) = addr;
1142         }
1143
1144       /* We don't want complex addressing modes in debug insns
1145          if simpler ones will do, so delegitimize equivalences
1146          in debug insns.  */
1147       if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1148         {
1149           rtx reg = regno_reg_rtx[i];
1150           rtx equiv = 0;
1151           df_ref use, next;
1152
1153           if (reg_equiv_constant (i))
1154             equiv = reg_equiv_constant (i);
1155           else if (reg_equiv_invariant (i))
1156             equiv = reg_equiv_invariant (i);
1157           else if (reg && MEM_P (reg))
1158             equiv = targetm.delegitimize_address (reg);
1159           else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1160             equiv = reg;
1161
1162           if (equiv == reg)
1163             continue;
1164
1165           for (use = DF_REG_USE_CHAIN (i); use; use = next)
1166             {
1167               insn = DF_REF_INSN (use);
1168
1169               /* Make sure the next ref is for a different instruction,
1170                  so that we're not affected by the rescan.  */
1171               next = DF_REF_NEXT_REG (use);
1172               while (next && DF_REF_INSN (next) == insn)
1173                 next = DF_REF_NEXT_REG (next);
1174
1175               if (DEBUG_INSN_P (insn))
1176                 {
1177                   if (!equiv)
1178                     {
1179                       INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1180                       df_insn_rescan_debug_internal (insn);
1181                     }
1182                   else
1183                     INSN_VAR_LOCATION_LOC (insn)
1184                       = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1185                                               reg, equiv);
1186                 }
1187             }
1188         }
1189     }
1190
1191   /* We must set reload_completed now since the cleanup_subreg_operands call
1192      below will re-recognize each insn and reload may have generated insns
1193      which are only valid during and after reload.  */
1194   reload_completed = 1;
1195
1196   /* Make a pass over all the insns and delete all USEs which we inserted
1197      only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
1198      notes.  Delete all CLOBBER insns, except those that refer to the return
1199      value and the special mem:BLK CLOBBERs added to prevent the scheduler
1200      from misarranging variable-array code, and simplify (subreg (reg))
1201      operands.  Strip and regenerate REG_INC notes that may have been moved
1202      around.  */
1203
1204   for (insn = first; insn; insn = NEXT_INSN (insn))
1205     if (INSN_P (insn))
1206       {
1207         rtx *pnote;
1208
1209         if (CALL_P (insn))
1210           replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1211                               VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1212
1213         if ((GET_CODE (PATTERN (insn)) == USE
1214              /* We mark with QImode USEs introduced by reload itself.  */
1215              && (GET_MODE (insn) == QImode
1216                  || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1217             || (GET_CODE (PATTERN (insn)) == CLOBBER
1218                 && (!MEM_P (XEXP (PATTERN (insn), 0))
1219                     || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1220                     || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1221                         && XEXP (XEXP (PATTERN (insn), 0), 0)
1222                                 != stack_pointer_rtx))
1223                 && (!REG_P (XEXP (PATTERN (insn), 0))
1224                     || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1225           {
1226             delete_insn (insn);
1227             continue;
1228           }
1229
1230         /* Some CLOBBERs may survive until here and still reference unassigned
1231            pseudos with const equivalent, which may in turn cause ICE in later
1232            passes if the reference remains in place.  */
1233         if (GET_CODE (PATTERN (insn)) == CLOBBER)
1234           replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1235                               VOIDmode, PATTERN (insn));
1236
1237         /* Discard obvious no-ops, even without -O.  This optimization
1238            is fast and doesn't interfere with debugging.  */
1239         if (NONJUMP_INSN_P (insn)
1240             && GET_CODE (PATTERN (insn)) == SET
1241             && REG_P (SET_SRC (PATTERN (insn)))
1242             && REG_P (SET_DEST (PATTERN (insn)))
1243             && (REGNO (SET_SRC (PATTERN (insn)))
1244                 == REGNO (SET_DEST (PATTERN (insn)))))
1245           {
1246             delete_insn (insn);
1247             continue;
1248           }
1249
1250         pnote = &REG_NOTES (insn);
1251         while (*pnote != 0)
1252           {
1253             if (REG_NOTE_KIND (*pnote) == REG_DEAD
1254                 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1255                 || REG_NOTE_KIND (*pnote) == REG_INC)
1256               *pnote = XEXP (*pnote, 1);
1257             else
1258               pnote = &XEXP (*pnote, 1);
1259           }
1260
1261 #ifdef AUTO_INC_DEC
1262         add_auto_inc_notes (insn, PATTERN (insn));
1263 #endif
1264
1265         /* Simplify (subreg (reg)) if it appears as an operand.  */
1266         cleanup_subreg_operands (insn);
1267
1268         /* Clean up invalid ASMs so that they don't confuse later passes.
1269            See PR 21299.  */
1270         if (asm_noperands (PATTERN (insn)) >= 0)
1271           {
1272             extract_insn (insn);
1273             if (!constrain_operands (1, get_enabled_alternatives (insn)))
1274               {
1275                 error_for_asm (insn,
1276                                "%<asm%> operand has impossible constraints");
1277                 delete_insn (insn);
1278                 continue;
1279               }
1280           }
1281       }
1282
1283   /* If we are doing generic stack checking, give a warning if this
1284      function's frame size is larger than we expect.  */
1285   if (flag_stack_check == GENERIC_STACK_CHECK)
1286     {
1287       HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1288       static int verbose_warned = 0;
1289
1290       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1291         if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1292           size += UNITS_PER_WORD;
1293
1294       if (size > STACK_CHECK_MAX_FRAME_SIZE)
1295         {
1296           warning (0, "frame size too large for reliable stack checking");
1297           if (! verbose_warned)
1298             {
1299               warning (0, "try reducing the number of local variables");
1300               verbose_warned = 1;
1301             }
1302         }
1303     }
1304
1305   free (temp_pseudo_reg_arr);
1306
1307   /* Indicate that we no longer have known memory locations or constants.  */
1308   free_reg_equiv ();
1309
1310   free (reg_max_ref_width);
1311   free (reg_old_renumber);
1312   free (pseudo_previous_regs);
1313   free (pseudo_forbidden_regs);
1314
1315   CLEAR_HARD_REG_SET (used_spill_regs);
1316   for (i = 0; i < n_spills; i++)
1317     SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1318
1319   /* Free all the insn_chain structures at once.  */
1320   obstack_free (&reload_obstack, reload_startobj);
1321   unused_insn_chains = 0;
1322
1323   inserted = fixup_abnormal_edges ();
1324
1325   /* We've possibly turned single trapping insn into multiple ones.  */
1326   if (cfun->can_throw_non_call_exceptions)
1327     {
1328       sbitmap blocks;
1329       blocks = sbitmap_alloc (last_basic_block_for_fn (cfun));
1330       bitmap_ones (blocks);
1331       find_many_sub_basic_blocks (blocks);
1332       sbitmap_free (blocks);
1333     }
1334
1335   if (inserted)
1336     commit_edge_insertions ();
1337
1338   /* Replacing pseudos with their memory equivalents might have
1339      created shared rtx.  Subsequent passes would get confused
1340      by this, so unshare everything here.  */
1341   unshare_all_rtl_again (first);
1342
1343 #ifdef STACK_BOUNDARY
1344   /* init_emit has set the alignment of the hard frame pointer
1345      to STACK_BOUNDARY.  It is very likely no longer valid if
1346      the hard frame pointer was used for register allocation.  */
1347   if (!frame_pointer_needed)
1348     REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1349 #endif
1350
1351   substitute_stack.release ();
1352
1353   gcc_assert (bitmap_empty_p (&spilled_pseudos));
1354
1355   reload_completed = !failure;
1356
1357   return need_dce;
1358 }
1359
1360 /* Yet another special case.  Unfortunately, reg-stack forces people to
1361    write incorrect clobbers in asm statements.  These clobbers must not
1362    cause the register to appear in bad_spill_regs, otherwise we'll call
1363    fatal_insn later.  We clear the corresponding regnos in the live
1364    register sets to avoid this.
1365    The whole thing is rather sick, I'm afraid.  */
1366
1367 static void
1368 maybe_fix_stack_asms (void)
1369 {
1370 #ifdef STACK_REGS
1371   const char *constraints[MAX_RECOG_OPERANDS];
1372   machine_mode operand_mode[MAX_RECOG_OPERANDS];
1373   struct insn_chain *chain;
1374
1375   for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1376     {
1377       int i, noperands;
1378       HARD_REG_SET clobbered, allowed;
1379       rtx pat;
1380
1381       if (! INSN_P (chain->insn)
1382           || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1383         continue;
1384       pat = PATTERN (chain->insn);
1385       if (GET_CODE (pat) != PARALLEL)
1386         continue;
1387
1388       CLEAR_HARD_REG_SET (clobbered);
1389       CLEAR_HARD_REG_SET (allowed);
1390
1391       /* First, make a mask of all stack regs that are clobbered.  */
1392       for (i = 0; i < XVECLEN (pat, 0); i++)
1393         {
1394           rtx t = XVECEXP (pat, 0, i);
1395           if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1396             SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1397         }
1398
1399       /* Get the operand values and constraints out of the insn.  */
1400       decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1401                            constraints, operand_mode, NULL);
1402
1403       /* For every operand, see what registers are allowed.  */
1404       for (i = 0; i < noperands; i++)
1405         {
1406           const char *p = constraints[i];
1407           /* For every alternative, we compute the class of registers allowed
1408              for reloading in CLS, and merge its contents into the reg set
1409              ALLOWED.  */
1410           int cls = (int) NO_REGS;
1411
1412           for (;;)
1413             {
1414               char c = *p;
1415
1416               if (c == '\0' || c == ',' || c == '#')
1417                 {
1418                   /* End of one alternative - mark the regs in the current
1419                      class, and reset the class.  */
1420                   IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1421                   cls = NO_REGS;
1422                   p++;
1423                   if (c == '#')
1424                     do {
1425                       c = *p++;
1426                     } while (c != '\0' && c != ',');
1427                   if (c == '\0')
1428                     break;
1429                   continue;
1430                 }
1431
1432               switch (c)
1433                 {
1434                 case 'g':
1435                   cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1436                   break;
1437
1438                 default:
1439                   enum constraint_num cn = lookup_constraint (p);
1440                   if (insn_extra_address_constraint (cn))
1441                     cls = (int) reg_class_subunion[cls]
1442                       [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1443                                              ADDRESS, SCRATCH)];
1444                   else
1445                     cls = (int) reg_class_subunion[cls]
1446                       [reg_class_for_constraint (cn)];
1447                   break;
1448                 }
1449               p += CONSTRAINT_LEN (c, p);
1450             }
1451         }
1452       /* Those of the registers which are clobbered, but allowed by the
1453          constraints, must be usable as reload registers.  So clear them
1454          out of the life information.  */
1455       AND_HARD_REG_SET (allowed, clobbered);
1456       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1457         if (TEST_HARD_REG_BIT (allowed, i))
1458           {
1459             CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1460             CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1461           }
1462     }
1463
1464 #endif
1465 }
1466 \f
1467 /* Copy the global variables n_reloads and rld into the corresponding elts
1468    of CHAIN.  */
1469 static void
1470 copy_reloads (struct insn_chain *chain)
1471 {
1472   chain->n_reloads = n_reloads;
1473   chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1474   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1475   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1476 }
1477
1478 /* Walk the chain of insns, and determine for each whether it needs reloads
1479    and/or eliminations.  Build the corresponding insns_need_reload list, and
1480    set something_needs_elimination as appropriate.  */
1481 static void
1482 calculate_needs_all_insns (int global)
1483 {
1484   struct insn_chain **pprev_reload = &insns_need_reload;
1485   struct insn_chain *chain, *next = 0;
1486
1487   something_needs_elimination = 0;
1488
1489   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1490   for (chain = reload_insn_chain; chain != 0; chain = next)
1491     {
1492       rtx_insn *insn = chain->insn;
1493
1494       next = chain->next;
1495
1496       /* Clear out the shortcuts.  */
1497       chain->n_reloads = 0;
1498       chain->need_elim = 0;
1499       chain->need_reload = 0;
1500       chain->need_operand_change = 0;
1501
1502       /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1503          include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1504          what effects this has on the known offsets at labels.  */
1505
1506       if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1507           || (INSN_P (insn) && REG_NOTES (insn) != 0))
1508         set_label_offsets (insn, insn, 0);
1509
1510       if (INSN_P (insn))
1511         {
1512           rtx old_body = PATTERN (insn);
1513           int old_code = INSN_CODE (insn);
1514           rtx old_notes = REG_NOTES (insn);
1515           int did_elimination = 0;
1516           int operands_changed = 0;
1517
1518           /* Skip insns that only set an equivalence.  */
1519           if (will_delete_init_insn_p (insn))
1520             continue;
1521
1522           /* If needed, eliminate any eliminable registers.  */
1523           if (num_eliminable || num_eliminable_invariants)
1524             did_elimination = eliminate_regs_in_insn (insn, 0);
1525
1526           /* Analyze the instruction.  */
1527           operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1528                                            global, spill_reg_order);
1529
1530           /* If a no-op set needs more than one reload, this is likely
1531              to be something that needs input address reloads.  We
1532              can't get rid of this cleanly later, and it is of no use
1533              anyway, so discard it now.
1534              We only do this when expensive_optimizations is enabled,
1535              since this complements reload inheritance / output
1536              reload deletion, and it can make debugging harder.  */
1537           if (flag_expensive_optimizations && n_reloads > 1)
1538             {
1539               rtx set = single_set (insn);
1540               if (set
1541                   &&
1542                   ((SET_SRC (set) == SET_DEST (set)
1543                     && REG_P (SET_SRC (set))
1544                     && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1545                    || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1546                        && reg_renumber[REGNO (SET_SRC (set))] < 0
1547                        && reg_renumber[REGNO (SET_DEST (set))] < 0
1548                        && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1549                        && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1550                        && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1551                                        reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1552                 {
1553                   if (ira_conflicts_p)
1554                     /* Inform IRA about the insn deletion.  */
1555                     ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1556                                                    REGNO (SET_SRC (set)));
1557                   delete_insn (insn);
1558                   /* Delete it from the reload chain.  */
1559                   if (chain->prev)
1560                     chain->prev->next = next;
1561                   else
1562                     reload_insn_chain = next;
1563                   if (next)
1564                     next->prev = chain->prev;
1565                   chain->next = unused_insn_chains;
1566                   unused_insn_chains = chain;
1567                   continue;
1568                 }
1569             }
1570           if (num_eliminable)
1571             update_eliminable_offsets ();
1572
1573           /* Remember for later shortcuts which insns had any reloads or
1574              register eliminations.  */
1575           chain->need_elim = did_elimination;
1576           chain->need_reload = n_reloads > 0;
1577           chain->need_operand_change = operands_changed;
1578
1579           /* Discard any register replacements done.  */
1580           if (did_elimination)
1581             {
1582               obstack_free (&reload_obstack, reload_insn_firstobj);
1583               PATTERN (insn) = old_body;
1584               INSN_CODE (insn) = old_code;
1585               REG_NOTES (insn) = old_notes;
1586               something_needs_elimination = 1;
1587             }
1588
1589           something_needs_operands_changed |= operands_changed;
1590
1591           if (n_reloads != 0)
1592             {
1593               copy_reloads (chain);
1594               *pprev_reload = chain;
1595               pprev_reload = &chain->next_need_reload;
1596             }
1597         }
1598     }
1599   *pprev_reload = 0;
1600 }
1601 \f
1602 /* This function is called from the register allocator to set up estimates
1603    for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1604    an invariant.  The structure is similar to calculate_needs_all_insns.  */
1605
1606 void
1607 calculate_elim_costs_all_insns (void)
1608 {
1609   int *reg_equiv_init_cost;
1610   basic_block bb;
1611   int i;
1612
1613   reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1614   init_elim_table ();
1615   init_eliminable_invariants (get_insns (), false);
1616
1617   set_initial_elim_offsets ();
1618   set_initial_label_offsets ();
1619
1620   FOR_EACH_BB_FN (bb, cfun)
1621     {
1622       rtx_insn *insn;
1623       elim_bb = bb;
1624
1625       FOR_BB_INSNS (bb, insn)
1626         {
1627           /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1628              include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1629              what effects this has on the known offsets at labels.  */
1630
1631           if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1632               || (INSN_P (insn) && REG_NOTES (insn) != 0))
1633             set_label_offsets (insn, insn, 0);
1634
1635           if (INSN_P (insn))
1636             {
1637               rtx set = single_set (insn);
1638
1639               /* Skip insns that only set an equivalence.  */
1640               if (set && REG_P (SET_DEST (set))
1641                   && reg_renumber[REGNO (SET_DEST (set))] < 0
1642                   && (reg_equiv_constant (REGNO (SET_DEST (set)))
1643                       || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1644                 {
1645                   unsigned regno = REGNO (SET_DEST (set));
1646                   rtx_insn_list *init = reg_equiv_init (regno);
1647                   if (init)
1648                     {
1649                       rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1650                                                 false, true);
1651                       int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1652                       int freq = REG_FREQ_FROM_BB (bb);
1653
1654                       reg_equiv_init_cost[regno] = cost * freq;
1655                       continue;
1656                     }
1657                 }
1658               /* If needed, eliminate any eliminable registers.  */
1659               if (num_eliminable || num_eliminable_invariants)
1660                 elimination_costs_in_insn (insn);
1661
1662               if (num_eliminable)
1663                 update_eliminable_offsets ();
1664             }
1665         }
1666     }
1667   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1668     {
1669       if (reg_equiv_invariant (i))
1670         {
1671           if (reg_equiv_init (i))
1672             {
1673               int cost = reg_equiv_init_cost[i];
1674               if (dump_file)
1675                 fprintf (dump_file,
1676                          "Reg %d has equivalence, initial gains %d\n", i, cost);
1677               if (cost != 0)
1678                 ira_adjust_equiv_reg_cost (i, cost);
1679             }
1680           else
1681             {
1682               if (dump_file)
1683                 fprintf (dump_file,
1684                          "Reg %d had equivalence, but can't be eliminated\n",
1685                          i);
1686               ira_adjust_equiv_reg_cost (i, 0);
1687             }
1688         }
1689     }
1690
1691   free (reg_equiv_init_cost);
1692   free (offsets_known_at);
1693   free (offsets_at);
1694   offsets_at = NULL;
1695   offsets_known_at = NULL;
1696 }
1697 \f
1698 /* Comparison function for qsort to decide which of two reloads
1699    should be handled first.  *P1 and *P2 are the reload numbers.  */
1700
1701 static int
1702 reload_reg_class_lower (const void *r1p, const void *r2p)
1703 {
1704   int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1705   int t;
1706
1707   /* Consider required reloads before optional ones.  */
1708   t = rld[r1].optional - rld[r2].optional;
1709   if (t != 0)
1710     return t;
1711
1712   /* Count all solitary classes before non-solitary ones.  */
1713   t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1714        - (reg_class_size[(int) rld[r1].rclass] == 1));
1715   if (t != 0)
1716     return t;
1717
1718   /* Aside from solitaires, consider all multi-reg groups first.  */
1719   t = rld[r2].nregs - rld[r1].nregs;
1720   if (t != 0)
1721     return t;
1722
1723   /* Consider reloads in order of increasing reg-class number.  */
1724   t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1725   if (t != 0)
1726     return t;
1727
1728   /* If reloads are equally urgent, sort by reload number,
1729      so that the results of qsort leave nothing to chance.  */
1730   return r1 - r2;
1731 }
1732 \f
1733 /* The cost of spilling each hard reg.  */
1734 static int spill_cost[FIRST_PSEUDO_REGISTER];
1735
1736 /* When spilling multiple hard registers, we use SPILL_COST for the first
1737    spilled hard reg and SPILL_ADD_COST for subsequent regs.  SPILL_ADD_COST
1738    only the first hard reg for a multi-reg pseudo.  */
1739 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1740
1741 /* Map of hard regno to pseudo regno currently occupying the hard
1742    reg.  */
1743 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1744
1745 /* Update the spill cost arrays, considering that pseudo REG is live.  */
1746
1747 static void
1748 count_pseudo (int reg)
1749 {
1750   int freq = REG_FREQ (reg);
1751   int r = reg_renumber[reg];
1752   int nregs;
1753
1754   /* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
1755   if (ira_conflicts_p && r < 0)
1756     return;
1757
1758   if (REGNO_REG_SET_P (&pseudos_counted, reg)
1759       || REGNO_REG_SET_P (&spilled_pseudos, reg))
1760     return;
1761
1762   SET_REGNO_REG_SET (&pseudos_counted, reg);
1763
1764   gcc_assert (r >= 0);
1765
1766   spill_add_cost[r] += freq;
1767   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1768   while (nregs-- > 0)
1769     {
1770       hard_regno_to_pseudo_regno[r + nregs] = reg;
1771       spill_cost[r + nregs] += freq;
1772     }
1773 }
1774
1775 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1776    contents of BAD_SPILL_REGS for the insn described by CHAIN.  */
1777
1778 static void
1779 order_regs_for_reload (struct insn_chain *chain)
1780 {
1781   unsigned i;
1782   HARD_REG_SET used_by_pseudos;
1783   HARD_REG_SET used_by_pseudos2;
1784   reg_set_iterator rsi;
1785
1786   COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1787
1788   memset (spill_cost, 0, sizeof spill_cost);
1789   memset (spill_add_cost, 0, sizeof spill_add_cost);
1790   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1791     hard_regno_to_pseudo_regno[i] = -1;
1792
1793   /* Count number of uses of each hard reg by pseudo regs allocated to it
1794      and then order them by decreasing use.  First exclude hard registers
1795      that are live in or across this insn.  */
1796
1797   REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1798   REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1799   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1800   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1801
1802   /* Now find out which pseudos are allocated to it, and update
1803      hard_reg_n_uses.  */
1804   CLEAR_REG_SET (&pseudos_counted);
1805
1806   EXECUTE_IF_SET_IN_REG_SET
1807     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1808     {
1809       count_pseudo (i);
1810     }
1811   EXECUTE_IF_SET_IN_REG_SET
1812     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1813     {
1814       count_pseudo (i);
1815     }
1816   CLEAR_REG_SET (&pseudos_counted);
1817 }
1818 \f
1819 /* Vector of reload-numbers showing the order in which the reloads should
1820    be processed.  */
1821 static short reload_order[MAX_RELOADS];
1822
1823 /* This is used to keep track of the spill regs used in one insn.  */
1824 static HARD_REG_SET used_spill_regs_local;
1825
1826 /* We decided to spill hard register SPILLED, which has a size of
1827    SPILLED_NREGS.  Determine how pseudo REG, which is live during the insn,
1828    is affected.  We will add it to SPILLED_PSEUDOS if necessary, and we will
1829    update SPILL_COST/SPILL_ADD_COST.  */
1830
1831 static void
1832 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1833 {
1834   int freq = REG_FREQ (reg);
1835   int r = reg_renumber[reg];
1836   int nregs;
1837
1838   /* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
1839   if (ira_conflicts_p && r < 0)
1840     return;
1841
1842   gcc_assert (r >= 0);
1843
1844   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1845
1846   if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1847       || spilled + spilled_nregs <= r || r + nregs <= spilled)
1848     return;
1849
1850   SET_REGNO_REG_SET (&spilled_pseudos, reg);
1851
1852   spill_add_cost[r] -= freq;
1853   while (nregs-- > 0)
1854     {
1855       hard_regno_to_pseudo_regno[r + nregs] = -1;
1856       spill_cost[r + nregs] -= freq;
1857     }
1858 }
1859
1860 /* Find reload register to use for reload number ORDER.  */
1861
1862 static int
1863 find_reg (struct insn_chain *chain, int order)
1864 {
1865   int rnum = reload_order[order];
1866   struct reload *rl = rld + rnum;
1867   int best_cost = INT_MAX;
1868   int best_reg = -1;
1869   unsigned int i, j, n;
1870   int k;
1871   HARD_REG_SET not_usable;
1872   HARD_REG_SET used_by_other_reload;
1873   reg_set_iterator rsi;
1874   static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1875   static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1876
1877   COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1878   IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1879   IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1880
1881   CLEAR_HARD_REG_SET (used_by_other_reload);
1882   for (k = 0; k < order; k++)
1883     {
1884       int other = reload_order[k];
1885
1886       if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1887         for (j = 0; j < rld[other].nregs; j++)
1888           SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1889     }
1890
1891   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1892     {
1893 #ifdef REG_ALLOC_ORDER
1894       unsigned int regno = reg_alloc_order[i];
1895 #else
1896       unsigned int regno = i;
1897 #endif
1898
1899       if (! TEST_HARD_REG_BIT (not_usable, regno)
1900           && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1901           && HARD_REGNO_MODE_OK (regno, rl->mode))
1902         {
1903           int this_cost = spill_cost[regno];
1904           int ok = 1;
1905           unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1906
1907           for (j = 1; j < this_nregs; j++)
1908             {
1909               this_cost += spill_add_cost[regno + j];
1910               if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1911                   || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1912                 ok = 0;
1913             }
1914           if (! ok)
1915             continue;
1916
1917           if (ira_conflicts_p)
1918             {
1919               /* Ask IRA to find a better pseudo-register for
1920                  spilling.  */
1921               for (n = j = 0; j < this_nregs; j++)
1922                 {
1923                   int r = hard_regno_to_pseudo_regno[regno + j];
1924
1925                   if (r < 0)
1926                     continue;
1927                   if (n == 0 || regno_pseudo_regs[n - 1] != r)
1928                     regno_pseudo_regs[n++] = r;
1929                 }
1930               regno_pseudo_regs[n++] = -1;
1931               if (best_reg < 0
1932                   || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1933                                                       best_regno_pseudo_regs,
1934                                                       rl->in, rl->out,
1935                                                       chain->insn))
1936                 {
1937                   best_reg = regno;
1938                   for (j = 0;; j++)
1939                     {
1940                       best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1941                       if (regno_pseudo_regs[j] < 0)
1942                         break;
1943                     }
1944                 }
1945               continue;
1946             }
1947
1948           if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1949             this_cost--;
1950           if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1951             this_cost--;
1952           if (this_cost < best_cost
1953               /* Among registers with equal cost, prefer caller-saved ones, or
1954                  use REG_ALLOC_ORDER if it is defined.  */
1955               || (this_cost == best_cost
1956 #ifdef REG_ALLOC_ORDER
1957                   && (inv_reg_alloc_order[regno]
1958                       < inv_reg_alloc_order[best_reg])
1959 #else
1960                   && call_used_regs[regno]
1961                   && ! call_used_regs[best_reg]
1962 #endif
1963                   ))
1964             {
1965               best_reg = regno;
1966               best_cost = this_cost;
1967             }
1968         }
1969     }
1970   if (best_reg == -1)
1971     return 0;
1972
1973   if (dump_file)
1974     fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1975
1976   rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1977   rl->regno = best_reg;
1978
1979   EXECUTE_IF_SET_IN_REG_SET
1980     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1981     {
1982       count_spilled_pseudo (best_reg, rl->nregs, j);
1983     }
1984
1985   EXECUTE_IF_SET_IN_REG_SET
1986     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1987     {
1988       count_spilled_pseudo (best_reg, rl->nregs, j);
1989     }
1990
1991   for (i = 0; i < rl->nregs; i++)
1992     {
1993       gcc_assert (spill_cost[best_reg + i] == 0);
1994       gcc_assert (spill_add_cost[best_reg + i] == 0);
1995       gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1996       SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1997     }
1998   return 1;
1999 }
2000
2001 /* Find more reload regs to satisfy the remaining need of an insn, which
2002    is given by CHAIN.
2003    Do it by ascending class number, since otherwise a reg
2004    might be spilled for a big class and might fail to count
2005    for a smaller class even though it belongs to that class.  */
2006
2007 static void
2008 find_reload_regs (struct insn_chain *chain)
2009 {
2010   int i;
2011
2012   /* In order to be certain of getting the registers we need,
2013      we must sort the reloads into order of increasing register class.
2014      Then our grabbing of reload registers will parallel the process
2015      that provided the reload registers.  */
2016   for (i = 0; i < chain->n_reloads; i++)
2017     {
2018       /* Show whether this reload already has a hard reg.  */
2019       if (chain->rld[i].reg_rtx)
2020         {
2021           int regno = REGNO (chain->rld[i].reg_rtx);
2022           chain->rld[i].regno = regno;
2023           chain->rld[i].nregs
2024             = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2025         }
2026       else
2027         chain->rld[i].regno = -1;
2028       reload_order[i] = i;
2029     }
2030
2031   n_reloads = chain->n_reloads;
2032   memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2033
2034   CLEAR_HARD_REG_SET (used_spill_regs_local);
2035
2036   if (dump_file)
2037     fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2038
2039   qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2040
2041   /* Compute the order of preference for hard registers to spill.  */
2042
2043   order_regs_for_reload (chain);
2044
2045   for (i = 0; i < n_reloads; i++)
2046     {
2047       int r = reload_order[i];
2048
2049       /* Ignore reloads that got marked inoperative.  */
2050       if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2051           && ! rld[r].optional
2052           && rld[r].regno == -1)
2053         if (! find_reg (chain, i))
2054           {
2055             if (dump_file)
2056               fprintf (dump_file, "reload failure for reload %d\n", r);
2057             spill_failure (chain->insn, rld[r].rclass);
2058             failure = 1;
2059             return;
2060           }
2061     }
2062
2063   COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2064   IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2065
2066   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2067 }
2068
2069 static void
2070 select_reload_regs (void)
2071 {
2072   struct insn_chain *chain;
2073
2074   /* Try to satisfy the needs for each insn.  */
2075   for (chain = insns_need_reload; chain != 0;
2076        chain = chain->next_need_reload)
2077     find_reload_regs (chain);
2078 }
2079 \f
2080 /* Delete all insns that were inserted by emit_caller_save_insns during
2081    this iteration.  */
2082 static void
2083 delete_caller_save_insns (void)
2084 {
2085   struct insn_chain *c = reload_insn_chain;
2086
2087   while (c != 0)
2088     {
2089       while (c != 0 && c->is_caller_save_insn)
2090         {
2091           struct insn_chain *next = c->next;
2092           rtx_insn *insn = c->insn;
2093
2094           if (c == reload_insn_chain)
2095             reload_insn_chain = next;
2096           delete_insn (insn);
2097
2098           if (next)
2099             next->prev = c->prev;
2100           if (c->prev)
2101             c->prev->next = next;
2102           c->next = unused_insn_chains;
2103           unused_insn_chains = c;
2104           c = next;
2105         }
2106       if (c != 0)
2107         c = c->next;
2108     }
2109 }
2110 \f
2111 /* Handle the failure to find a register to spill.
2112    INSN should be one of the insns which needed this particular spill reg.  */
2113
2114 static void
2115 spill_failure (rtx_insn *insn, enum reg_class rclass)
2116 {
2117   if (asm_noperands (PATTERN (insn)) >= 0)
2118     error_for_asm (insn, "can%'t find a register in class %qs while "
2119                    "reloading %<asm%>",
2120                    reg_class_names[rclass]);
2121   else
2122     {
2123       error ("unable to find a register to spill in class %qs",
2124              reg_class_names[rclass]);
2125
2126       if (dump_file)
2127         {
2128           fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2129           debug_reload_to_stream (dump_file);
2130         }
2131       fatal_insn ("this is the insn:", insn);
2132     }
2133 }
2134 \f
2135 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2136    data that is dead in INSN.  */
2137
2138 static void
2139 delete_dead_insn (rtx_insn *insn)
2140 {
2141   rtx_insn *prev = prev_active_insn (insn);
2142   rtx prev_dest;
2143
2144   /* If the previous insn sets a register that dies in our insn make
2145      a note that we want to run DCE immediately after reload.
2146
2147      We used to delete the previous insn & recurse, but that's wrong for
2148      block local equivalences.  Instead of trying to figure out the exact
2149      circumstances where we can delete the potentially dead insns, just
2150      let DCE do the job.  */
2151   if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2152       && GET_CODE (PATTERN (prev)) == SET
2153       && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2154       && reg_mentioned_p (prev_dest, PATTERN (insn))
2155       && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2156       && ! side_effects_p (SET_SRC (PATTERN (prev))))
2157     need_dce = 1;
2158
2159   SET_INSN_DELETED (insn);
2160 }
2161
2162 /* Modify the home of pseudo-reg I.
2163    The new home is present in reg_renumber[I].
2164
2165    FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2166    or it may be -1, meaning there is none or it is not relevant.
2167    This is used so that all pseudos spilled from a given hard reg
2168    can share one stack slot.  */
2169
2170 static void
2171 alter_reg (int i, int from_reg, bool dont_share_p)
2172 {
2173   /* When outputting an inline function, this can happen
2174      for a reg that isn't actually used.  */
2175   if (regno_reg_rtx[i] == 0)
2176     return;
2177
2178   /* If the reg got changed to a MEM at rtl-generation time,
2179      ignore it.  */
2180   if (!REG_P (regno_reg_rtx[i]))
2181     return;
2182
2183   /* Modify the reg-rtx to contain the new hard reg
2184      number or else to contain its pseudo reg number.  */
2185   SET_REGNO (regno_reg_rtx[i],
2186              reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2187
2188   /* If we have a pseudo that is needed but has no hard reg or equivalent,
2189      allocate a stack slot for it.  */
2190
2191   if (reg_renumber[i] < 0
2192       && REG_N_REFS (i) > 0
2193       && reg_equiv_constant (i) == 0
2194       && (reg_equiv_invariant (i) == 0
2195           || reg_equiv_init (i) == 0)
2196       && reg_equiv_memory_loc (i) == 0)
2197     {
2198       rtx x = NULL_RTX;
2199       machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2200       unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2201       unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2202       unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2203       unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2204       int adjust = 0;
2205
2206       something_was_spilled = true;
2207
2208       if (ira_conflicts_p)
2209         {
2210           /* Mark the spill for IRA.  */
2211           SET_REGNO_REG_SET (&spilled_pseudos, i);
2212           if (!dont_share_p)
2213             x = ira_reuse_stack_slot (i, inherent_size, total_size);
2214         }
2215
2216       if (x)
2217         ;
2218
2219       /* Each pseudo reg has an inherent size which comes from its own mode,
2220          and a total size which provides room for paradoxical subregs
2221          which refer to the pseudo reg in wider modes.
2222
2223          We can use a slot already allocated if it provides both
2224          enough inherent space and enough total space.
2225          Otherwise, we allocate a new slot, making sure that it has no less
2226          inherent space, and no less total space, then the previous slot.  */
2227       else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2228         {
2229           rtx stack_slot;
2230
2231           /* No known place to spill from => no slot to reuse.  */
2232           x = assign_stack_local (mode, total_size,
2233                                   min_align > inherent_align
2234                                   || total_size > inherent_size ? -1 : 0);
2235
2236           stack_slot = x;
2237
2238           /* Cancel the big-endian correction done in assign_stack_local.
2239              Get the address of the beginning of the slot.  This is so we
2240              can do a big-endian correction unconditionally below.  */
2241           if (BYTES_BIG_ENDIAN)
2242             {
2243               adjust = inherent_size - total_size;
2244               if (adjust)
2245                 stack_slot
2246                   = adjust_address_nv (x, mode_for_size (total_size
2247                                                          * BITS_PER_UNIT,
2248                                                          MODE_INT, 1),
2249                                        adjust);
2250             }
2251
2252           if (! dont_share_p && ira_conflicts_p)
2253             /* Inform IRA about allocation a new stack slot.  */
2254             ira_mark_new_stack_slot (stack_slot, i, total_size);
2255         }
2256
2257       /* Reuse a stack slot if possible.  */
2258       else if (spill_stack_slot[from_reg] != 0
2259                && spill_stack_slot_width[from_reg] >= total_size
2260                && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2261                    >= inherent_size)
2262                && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2263         x = spill_stack_slot[from_reg];
2264
2265       /* Allocate a bigger slot.  */
2266       else
2267         {
2268           /* Compute maximum size needed, both for inherent size
2269              and for total size.  */
2270           rtx stack_slot;
2271
2272           if (spill_stack_slot[from_reg])
2273             {
2274               if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2275                   > inherent_size)
2276                 mode = GET_MODE (spill_stack_slot[from_reg]);
2277               if (spill_stack_slot_width[from_reg] > total_size)
2278                 total_size = spill_stack_slot_width[from_reg];
2279               if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2280                 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2281             }
2282
2283           /* Make a slot with that size.  */
2284           x = assign_stack_local (mode, total_size,
2285                                   min_align > inherent_align
2286                                   || total_size > inherent_size ? -1 : 0);
2287           stack_slot = x;
2288
2289           /* Cancel the  big-endian correction done in assign_stack_local.
2290              Get the address of the beginning of the slot.  This is so we
2291              can do a big-endian correction unconditionally below.  */
2292           if (BYTES_BIG_ENDIAN)
2293             {
2294               adjust = GET_MODE_SIZE (mode) - total_size;
2295               if (adjust)
2296                 stack_slot
2297                   = adjust_address_nv (x, mode_for_size (total_size
2298                                                          * BITS_PER_UNIT,
2299                                                          MODE_INT, 1),
2300                                        adjust);
2301             }
2302
2303           spill_stack_slot[from_reg] = stack_slot;
2304           spill_stack_slot_width[from_reg] = total_size;
2305         }
2306
2307       /* On a big endian machine, the "address" of the slot
2308          is the address of the low part that fits its inherent mode.  */
2309       if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2310         adjust += (total_size - inherent_size);
2311
2312       /* If we have any adjustment to make, or if the stack slot is the
2313          wrong mode, make a new stack slot.  */
2314       x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2315
2316       /* Set all of the memory attributes as appropriate for a spill.  */
2317       set_mem_attrs_for_spill (x);
2318
2319       /* Save the stack slot for later.  */
2320       reg_equiv_memory_loc (i) = x;
2321     }
2322 }
2323
2324 /* Mark the slots in regs_ever_live for the hard regs used by
2325    pseudo-reg number REGNO, accessed in MODE.  */
2326
2327 static void
2328 mark_home_live_1 (int regno, machine_mode mode)
2329 {
2330   int i, lim;
2331
2332   i = reg_renumber[regno];
2333   if (i < 0)
2334     return;
2335   lim = end_hard_regno (mode, i);
2336   while (i < lim)
2337     df_set_regs_ever_live (i++, true);
2338 }
2339
2340 /* Mark the slots in regs_ever_live for the hard regs
2341    used by pseudo-reg number REGNO.  */
2342
2343 void
2344 mark_home_live (int regno)
2345 {
2346   if (reg_renumber[regno] >= 0)
2347     mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2348 }
2349 \f
2350 /* This function handles the tracking of elimination offsets around branches.
2351
2352    X is a piece of RTL being scanned.
2353
2354    INSN is the insn that it came from, if any.
2355
2356    INITIAL_P is nonzero if we are to set the offset to be the initial
2357    offset and zero if we are setting the offset of the label to be the
2358    current offset.  */
2359
2360 static void
2361 set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2362 {
2363   enum rtx_code code = GET_CODE (x);
2364   rtx tem;
2365   unsigned int i;
2366   struct elim_table *p;
2367
2368   switch (code)
2369     {
2370     case LABEL_REF:
2371       if (LABEL_REF_NONLOCAL_P (x))
2372         return;
2373
2374       x = LABEL_REF_LABEL (x);
2375
2376       /* ... fall through ...  */
2377
2378     case CODE_LABEL:
2379       /* If we know nothing about this label, set the desired offsets.  Note
2380          that this sets the offset at a label to be the offset before a label
2381          if we don't know anything about the label.  This is not correct for
2382          the label after a BARRIER, but is the best guess we can make.  If
2383          we guessed wrong, we will suppress an elimination that might have
2384          been possible had we been able to guess correctly.  */
2385
2386       if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2387         {
2388           for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2389             offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2390               = (initial_p ? reg_eliminate[i].initial_offset
2391                  : reg_eliminate[i].offset);
2392           offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2393         }
2394
2395       /* Otherwise, if this is the definition of a label and it is
2396          preceded by a BARRIER, set our offsets to the known offset of
2397          that label.  */
2398
2399       else if (x == insn
2400                && (tem = prev_nonnote_insn (insn)) != 0
2401                && BARRIER_P (tem))
2402         set_offsets_for_label (insn);
2403       else
2404         /* If neither of the above cases is true, compare each offset
2405            with those previously recorded and suppress any eliminations
2406            where the offsets disagree.  */
2407
2408         for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2409           if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2410               != (initial_p ? reg_eliminate[i].initial_offset
2411                   : reg_eliminate[i].offset))
2412             reg_eliminate[i].can_eliminate = 0;
2413
2414       return;
2415
2416     case JUMP_TABLE_DATA:
2417       set_label_offsets (PATTERN (insn), insn, initial_p);
2418       return;
2419
2420     case JUMP_INSN:
2421       set_label_offsets (PATTERN (insn), insn, initial_p);
2422
2423       /* ... fall through ...  */
2424
2425     case INSN:
2426     case CALL_INSN:
2427       /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2428          to indirectly and hence must have all eliminations at their
2429          initial offsets.  */
2430       for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2431         if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2432           set_label_offsets (XEXP (tem, 0), insn, 1);
2433       return;
2434
2435     case PARALLEL:
2436     case ADDR_VEC:
2437     case ADDR_DIFF_VEC:
2438       /* Each of the labels in the parallel or address vector must be
2439          at their initial offsets.  We want the first field for PARALLEL
2440          and ADDR_VEC and the second field for ADDR_DIFF_VEC.  */
2441
2442       for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2443         set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2444                            insn, initial_p);
2445       return;
2446
2447     case SET:
2448       /* We only care about setting PC.  If the source is not RETURN,
2449          IF_THEN_ELSE, or a label, disable any eliminations not at
2450          their initial offsets.  Similarly if any arm of the IF_THEN_ELSE
2451          isn't one of those possibilities.  For branches to a label,
2452          call ourselves recursively.
2453
2454          Note that this can disable elimination unnecessarily when we have
2455          a non-local goto since it will look like a non-constant jump to
2456          someplace in the current function.  This isn't a significant
2457          problem since such jumps will normally be when all elimination
2458          pairs are back to their initial offsets.  */
2459
2460       if (SET_DEST (x) != pc_rtx)
2461         return;
2462
2463       switch (GET_CODE (SET_SRC (x)))
2464         {
2465         case PC:
2466         case RETURN:
2467           return;
2468
2469         case LABEL_REF:
2470           set_label_offsets (SET_SRC (x), insn, initial_p);
2471           return;
2472
2473         case IF_THEN_ELSE:
2474           tem = XEXP (SET_SRC (x), 1);
2475           if (GET_CODE (tem) == LABEL_REF)
2476             set_label_offsets (LABEL_REF_LABEL (tem), insn, initial_p);
2477           else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2478             break;
2479
2480           tem = XEXP (SET_SRC (x), 2);
2481           if (GET_CODE (tem) == LABEL_REF)
2482             set_label_offsets (LABEL_REF_LABEL (tem), insn, initial_p);
2483           else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2484             break;
2485           return;
2486
2487         default:
2488           break;
2489         }
2490
2491       /* If we reach here, all eliminations must be at their initial
2492          offset because we are doing a jump to a variable address.  */
2493       for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
2494         if (p->offset != p->initial_offset)
2495           p->can_eliminate = 0;
2496       break;
2497
2498     default:
2499       break;
2500     }
2501 }
2502 \f
2503 /* This function examines every reg that occurs in X and adjusts the
2504    costs for its elimination which are gathered by IRA.  INSN is the
2505    insn in which X occurs.  We do not recurse into MEM expressions.  */
2506
2507 static void
2508 note_reg_elim_costly (const_rtx x, rtx insn)
2509 {
2510   subrtx_iterator::array_type array;
2511   FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2512     {
2513       const_rtx x = *iter;
2514       if (MEM_P (x))
2515         iter.skip_subrtxes ();
2516       else if (REG_P (x)
2517                && REGNO (x) >= FIRST_PSEUDO_REGISTER
2518                && reg_equiv_init (REGNO (x))
2519                && reg_equiv_invariant (REGNO (x)))
2520         {
2521           rtx t = reg_equiv_invariant (REGNO (x));
2522           rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2523           int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2524           int freq = REG_FREQ_FROM_BB (elim_bb);
2525
2526           if (cost != 0)
2527             ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2528         }
2529     }
2530 }
2531
2532 /* Scan X and replace any eliminable registers (such as fp) with a
2533    replacement (such as sp), plus an offset.
2534
2535    MEM_MODE is the mode of an enclosing MEM.  We need this to know how
2536    much to adjust a register for, e.g., PRE_DEC.  Also, if we are inside a
2537    MEM, we are allowed to replace a sum of a register and the constant zero
2538    with the register, which we cannot do outside a MEM.  In addition, we need
2539    to record the fact that a register is referenced outside a MEM.
2540
2541    If INSN is an insn, it is the insn containing X.  If we replace a REG
2542    in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2543    CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2544    the REG is being modified.
2545
2546    Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2547    That's used when we eliminate in expressions stored in notes.
2548    This means, do not set ref_outside_mem even if the reference
2549    is outside of MEMs.
2550
2551    If FOR_COSTS is true, we are being called before reload in order to
2552    estimate the costs of keeping registers with an equivalence unallocated.
2553
2554    REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2555    replacements done assuming all offsets are at their initial values.  If
2556    they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2557    encounter, return the actual location so that find_reloads will do
2558    the proper thing.  */
2559
2560 static rtx
2561 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2562                   bool may_use_invariant, bool for_costs)
2563 {
2564   enum rtx_code code = GET_CODE (x);
2565   struct elim_table *ep;
2566   int regno;
2567   rtx new_rtx;
2568   int i, j;
2569   const char *fmt;
2570   int copied = 0;
2571
2572   if (! current_function_decl)
2573     return x;
2574
2575   switch (code)
2576     {
2577     CASE_CONST_ANY:
2578     case CONST:
2579     case SYMBOL_REF:
2580     case CODE_LABEL:
2581     case PC:
2582     case CC0:
2583     case ASM_INPUT:
2584     case ADDR_VEC:
2585     case ADDR_DIFF_VEC:
2586     case RETURN:
2587       return x;
2588
2589     case REG:
2590       regno = REGNO (x);
2591
2592       /* First handle the case where we encounter a bare register that
2593          is eliminable.  Replace it with a PLUS.  */
2594       if (regno < FIRST_PSEUDO_REGISTER)
2595         {
2596           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2597                ep++)
2598             if (ep->from_rtx == x && ep->can_eliminate)
2599               return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2600
2601         }
2602       else if (reg_renumber && reg_renumber[regno] < 0
2603                && reg_equivs
2604                && reg_equiv_invariant (regno))
2605         {
2606           if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2607             return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2608                                      mem_mode, insn, true, for_costs);
2609           /* There exists at least one use of REGNO that cannot be
2610              eliminated.  Prevent the defining insn from being deleted.  */
2611           reg_equiv_init (regno) = NULL;
2612           if (!for_costs)
2613             alter_reg (regno, -1, true);
2614         }
2615       return x;
2616
2617     /* You might think handling MINUS in a manner similar to PLUS is a
2618        good idea.  It is not.  It has been tried multiple times and every
2619        time the change has had to have been reverted.
2620
2621        Other parts of reload know a PLUS is special (gen_reload for example)
2622        and require special code to handle code a reloaded PLUS operand.
2623
2624        Also consider backends where the flags register is clobbered by a
2625        MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2626        lea instruction comes to mind).  If we try to reload a MINUS, we
2627        may kill the flags register that was holding a useful value.
2628
2629        So, please before trying to handle MINUS, consider reload as a
2630        whole instead of this little section as well as the backend issues.  */
2631     case PLUS:
2632       /* If this is the sum of an eliminable register and a constant, rework
2633          the sum.  */
2634       if (REG_P (XEXP (x, 0))
2635           && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2636           && CONSTANT_P (XEXP (x, 1)))
2637         {
2638           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2639                ep++)
2640             if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2641               {
2642                 /* The only time we want to replace a PLUS with a REG (this
2643                    occurs when the constant operand of the PLUS is the negative
2644                    of the offset) is when we are inside a MEM.  We won't want
2645                    to do so at other times because that would change the
2646                    structure of the insn in a way that reload can't handle.
2647                    We special-case the commonest situation in
2648                    eliminate_regs_in_insn, so just replace a PLUS with a
2649                    PLUS here, unless inside a MEM.  */
2650                 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2651                     && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2652                   return ep->to_rtx;
2653                 else
2654                   return gen_rtx_PLUS (Pmode, ep->to_rtx,
2655                                        plus_constant (Pmode, XEXP (x, 1),
2656                                                       ep->previous_offset));
2657               }
2658
2659           /* If the register is not eliminable, we are done since the other
2660              operand is a constant.  */
2661           return x;
2662         }
2663
2664       /* If this is part of an address, we want to bring any constant to the
2665          outermost PLUS.  We will do this by doing register replacement in
2666          our operands and seeing if a constant shows up in one of them.
2667
2668          Note that there is no risk of modifying the structure of the insn,
2669          since we only get called for its operands, thus we are either
2670          modifying the address inside a MEM, or something like an address
2671          operand of a load-address insn.  */
2672
2673       {
2674         rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2675                                      for_costs);
2676         rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2677                                      for_costs);
2678
2679         if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2680           {
2681             /* If one side is a PLUS and the other side is a pseudo that
2682                didn't get a hard register but has a reg_equiv_constant,
2683                we must replace the constant here since it may no longer
2684                be in the position of any operand.  */
2685             if (GET_CODE (new0) == PLUS && REG_P (new1)
2686                 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2687                 && reg_renumber[REGNO (new1)] < 0
2688                 && reg_equivs
2689                 && reg_equiv_constant (REGNO (new1)) != 0)
2690               new1 = reg_equiv_constant (REGNO (new1));
2691             else if (GET_CODE (new1) == PLUS && REG_P (new0)
2692                      && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2693                      && reg_renumber[REGNO (new0)] < 0
2694                      && reg_equiv_constant (REGNO (new0)) != 0)
2695               new0 = reg_equiv_constant (REGNO (new0));
2696
2697             new_rtx = form_sum (GET_MODE (x), new0, new1);
2698
2699             /* As above, if we are not inside a MEM we do not want to
2700                turn a PLUS into something else.  We might try to do so here
2701                for an addition of 0 if we aren't optimizing.  */
2702             if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2703               return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2704             else
2705               return new_rtx;
2706           }
2707       }
2708       return x;
2709
2710     case MULT:
2711       /* If this is the product of an eliminable register and a
2712          constant, apply the distribute law and move the constant out
2713          so that we have (plus (mult ..) ..).  This is needed in order
2714          to keep load-address insns valid.   This case is pathological.
2715          We ignore the possibility of overflow here.  */
2716       if (REG_P (XEXP (x, 0))
2717           && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2718           && CONST_INT_P (XEXP (x, 1)))
2719         for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2720              ep++)
2721           if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2722             {
2723               if (! mem_mode
2724                   /* Refs inside notes or in DEBUG_INSNs don't count for
2725                      this purpose.  */
2726                   && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2727                                       || GET_CODE (insn) == INSN_LIST
2728                                       || DEBUG_INSN_P (insn))))
2729                 ep->ref_outside_mem = 1;
2730
2731               return
2732                 plus_constant (Pmode,
2733                                gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2734                                ep->previous_offset * INTVAL (XEXP (x, 1)));
2735             }
2736
2737       /* ... fall through ...  */
2738
2739     case CALL:
2740     case COMPARE:
2741     /* See comments before PLUS about handling MINUS.  */
2742     case MINUS:
2743     case DIV:      case UDIV:
2744     case MOD:      case UMOD:
2745     case AND:      case IOR:      case XOR:
2746     case ROTATERT: case ROTATE:
2747     case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2748     case NE:       case EQ:
2749     case GE:       case GT:       case GEU:    case GTU:
2750     case LE:       case LT:       case LEU:    case LTU:
2751       {
2752         rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2753                                      for_costs);
2754         rtx new1 = XEXP (x, 1)
2755           ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2756                               for_costs) : 0;
2757
2758         if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2759           return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2760       }
2761       return x;
2762
2763     case EXPR_LIST:
2764       /* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
2765       if (XEXP (x, 0))
2766         {
2767           new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2768                                       for_costs);
2769           if (new_rtx != XEXP (x, 0))
2770             {
2771               /* If this is a REG_DEAD note, it is not valid anymore.
2772                  Using the eliminated version could result in creating a
2773                  REG_DEAD note for the stack or frame pointer.  */
2774               if (REG_NOTE_KIND (x) == REG_DEAD)
2775                 return (XEXP (x, 1)
2776                         ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2777                                             for_costs)
2778                         : NULL_RTX);
2779
2780               x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2781             }
2782         }
2783
2784       /* ... fall through ...  */
2785
2786     case INSN_LIST:
2787     case INT_LIST:
2788       /* Now do eliminations in the rest of the chain.  If this was
2789          an EXPR_LIST, this might result in allocating more memory than is
2790          strictly needed, but it simplifies the code.  */
2791       if (XEXP (x, 1))
2792         {
2793           new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2794                                       for_costs);
2795           if (new_rtx != XEXP (x, 1))
2796             return
2797               gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2798         }
2799       return x;
2800
2801     case PRE_INC:
2802     case POST_INC:
2803     case PRE_DEC:
2804     case POST_DEC:
2805       /* We do not support elimination of a register that is modified.
2806          elimination_effects has already make sure that this does not
2807          happen.  */
2808       return x;
2809
2810     case PRE_MODIFY:
2811     case POST_MODIFY:
2812       /* We do not support elimination of a register that is modified.
2813          elimination_effects has already make sure that this does not
2814          happen.  The only remaining case we need to consider here is
2815          that the increment value may be an eliminable register.  */
2816       if (GET_CODE (XEXP (x, 1)) == PLUS
2817           && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2818         {
2819           rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2820                                           insn, true, for_costs);
2821
2822           if (new_rtx != XEXP (XEXP (x, 1), 1))
2823             return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2824                                    gen_rtx_PLUS (GET_MODE (x),
2825                                                  XEXP (x, 0), new_rtx));
2826         }
2827       return x;
2828
2829     case STRICT_LOW_PART:
2830     case NEG:          case NOT:
2831     case SIGN_EXTEND:  case ZERO_EXTEND:
2832     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2833     case FLOAT:        case FIX:
2834     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2835     case ABS:
2836     case SQRT:
2837     case FFS:
2838     case CLZ:
2839     case CTZ:
2840     case POPCOUNT:
2841     case PARITY:
2842     case BSWAP:
2843       new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2844                                   for_costs);
2845       if (new_rtx != XEXP (x, 0))
2846         return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2847       return x;
2848
2849     case SUBREG:
2850       /* Similar to above processing, but preserve SUBREG_BYTE.
2851          Convert (subreg (mem)) to (mem) if not paradoxical.
2852          Also, if we have a non-paradoxical (subreg (pseudo)) and the
2853          pseudo didn't get a hard reg, we must replace this with the
2854          eliminated version of the memory location because push_reload
2855          may do the replacement in certain circumstances.  */
2856       if (REG_P (SUBREG_REG (x))
2857           && !paradoxical_subreg_p (x)
2858           && reg_equivs
2859           && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2860         {
2861           new_rtx = SUBREG_REG (x);
2862         }
2863       else
2864         new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2865
2866       if (new_rtx != SUBREG_REG (x))
2867         {
2868           int x_size = GET_MODE_SIZE (GET_MODE (x));
2869           int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2870
2871           if (MEM_P (new_rtx)
2872               && ((x_size < new_size
2873 #ifdef WORD_REGISTER_OPERATIONS
2874                    /* On these machines, combine can create rtl of the form
2875                       (set (subreg:m1 (reg:m2 R) 0) ...)
2876                       where m1 < m2, and expects something interesting to
2877                       happen to the entire word.  Moreover, it will use the
2878                       (reg:m2 R) later, expecting all bits to be preserved.
2879                       So if the number of words is the same, preserve the
2880                       subreg so that push_reload can see it.  */
2881                    && ! ((x_size - 1) / UNITS_PER_WORD
2882                          == (new_size -1 ) / UNITS_PER_WORD)
2883 #endif
2884                    )
2885                   || x_size == new_size)
2886               )
2887             return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2888           else
2889             return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2890         }
2891
2892       return x;
2893
2894     case MEM:
2895       /* Our only special processing is to pass the mode of the MEM to our
2896          recursive call and copy the flags.  While we are here, handle this
2897          case more efficiently.  */
2898
2899       new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2900                                   for_costs);
2901       if (for_costs
2902           && memory_address_p (GET_MODE (x), XEXP (x, 0))
2903           && !memory_address_p (GET_MODE (x), new_rtx))
2904         note_reg_elim_costly (XEXP (x, 0), insn);
2905
2906       return replace_equiv_address_nv (x, new_rtx);
2907
2908     case USE:
2909       /* Handle insn_list USE that a call to a pure function may generate.  */
2910       new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2911                                   for_costs);
2912       if (new_rtx != XEXP (x, 0))
2913         return gen_rtx_USE (GET_MODE (x), new_rtx);
2914       return x;
2915
2916     case CLOBBER:
2917     case ASM_OPERANDS:
2918       gcc_assert (insn && DEBUG_INSN_P (insn));
2919       break;
2920
2921     case SET:
2922       gcc_unreachable ();
2923
2924     default:
2925       break;
2926     }
2927
2928   /* Process each of our operands recursively.  If any have changed, make a
2929      copy of the rtx.  */
2930   fmt = GET_RTX_FORMAT (code);
2931   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2932     {
2933       if (*fmt == 'e')
2934         {
2935           new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2936                                       for_costs);
2937           if (new_rtx != XEXP (x, i) && ! copied)
2938             {
2939               x = shallow_copy_rtx (x);
2940               copied = 1;
2941             }
2942           XEXP (x, i) = new_rtx;
2943         }
2944       else if (*fmt == 'E')
2945         {
2946           int copied_vec = 0;
2947           for (j = 0; j < XVECLEN (x, i); j++)
2948             {
2949               new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2950                                           for_costs);
2951               if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2952                 {
2953                   rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2954                                              XVEC (x, i)->elem);
2955                   if (! copied)
2956                     {
2957                       x = shallow_copy_rtx (x);
2958                       copied = 1;
2959                     }
2960                   XVEC (x, i) = new_v;
2961                   copied_vec = 1;
2962                 }
2963               XVECEXP (x, i, j) = new_rtx;
2964             }
2965         }
2966     }
2967
2968   return x;
2969 }
2970
2971 rtx
2972 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2973 {
2974   if (reg_eliminate == NULL)
2975     {
2976       gcc_assert (targetm.no_register_allocation);
2977       return x;
2978     }
2979   return eliminate_regs_1 (x, mem_mode, insn, false, false);
2980 }
2981
2982 /* Scan rtx X for modifications of elimination target registers.  Update
2983    the table of eliminables to reflect the changed state.  MEM_MODE is
2984    the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM.  */
2985
2986 static void
2987 elimination_effects (rtx x, machine_mode mem_mode)
2988 {
2989   enum rtx_code code = GET_CODE (x);
2990   struct elim_table *ep;
2991   int regno;
2992   int i, j;
2993   const char *fmt;
2994
2995   switch (code)
2996     {
2997     CASE_CONST_ANY:
2998     case CONST:
2999     case SYMBOL_REF:
3000     case CODE_LABEL:
3001     case PC:
3002     case CC0:
3003     case ASM_INPUT:
3004     case ADDR_VEC:
3005     case ADDR_DIFF_VEC:
3006     case RETURN:
3007       return;
3008
3009     case REG:
3010       regno = REGNO (x);
3011
3012       /* First handle the case where we encounter a bare register that
3013          is eliminable.  Replace it with a PLUS.  */
3014       if (regno < FIRST_PSEUDO_REGISTER)
3015         {
3016           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3017                ep++)
3018             if (ep->from_rtx == x && ep->can_eliminate)
3019               {
3020                 if (! mem_mode)
3021                   ep->ref_outside_mem = 1;
3022                 return;
3023               }
3024
3025         }
3026       else if (reg_renumber[regno] < 0
3027                && reg_equivs
3028                && reg_equiv_constant (regno)
3029                && ! function_invariant_p (reg_equiv_constant (regno)))
3030         elimination_effects (reg_equiv_constant (regno), mem_mode);
3031       return;
3032
3033     case PRE_INC:
3034     case POST_INC:
3035     case PRE_DEC:
3036     case POST_DEC:
3037     case POST_MODIFY:
3038     case PRE_MODIFY:
3039       /* If we modify the source of an elimination rule, disable it.  */
3040       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3041         if (ep->from_rtx == XEXP (x, 0))
3042           ep->can_eliminate = 0;
3043
3044       /* If we modify the target of an elimination rule by adding a constant,
3045          update its offset.  If we modify the target in any other way, we'll
3046          have to disable the rule as well.  */
3047       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3048         if (ep->to_rtx == XEXP (x, 0))
3049           {
3050             int size = GET_MODE_SIZE (mem_mode);
3051
3052             /* If more bytes than MEM_MODE are pushed, account for them.  */
3053 #ifdef PUSH_ROUNDING
3054             if (ep->to_rtx == stack_pointer_rtx)
3055               size = PUSH_ROUNDING (size);
3056 #endif
3057             if (code == PRE_DEC || code == POST_DEC)
3058               ep->offset += size;
3059             else if (code == PRE_INC || code == POST_INC)
3060               ep->offset -= size;
3061             else if (code == PRE_MODIFY || code == POST_MODIFY)
3062               {
3063                 if (GET_CODE (XEXP (x, 1)) == PLUS
3064                     && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3065                     && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3066                   ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3067                 else
3068                   ep->can_eliminate = 0;
3069               }
3070           }
3071
3072       /* These two aren't unary operators.  */
3073       if (code == POST_MODIFY || code == PRE_MODIFY)
3074         break;
3075
3076       /* Fall through to generic unary operation case.  */
3077     case STRICT_LOW_PART:
3078     case NEG:          case NOT:
3079     case SIGN_EXTEND:  case ZERO_EXTEND:
3080     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3081     case FLOAT:        case FIX:
3082     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3083     case ABS:
3084     case SQRT:
3085     case FFS:
3086     case CLZ:
3087     case CTZ:
3088     case POPCOUNT:
3089     case PARITY:
3090     case BSWAP:
3091       elimination_effects (XEXP (x, 0), mem_mode);
3092       return;
3093
3094     case SUBREG:
3095       if (REG_P (SUBREG_REG (x))
3096           && (GET_MODE_SIZE (GET_MODE (x))
3097               <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3098           && reg_equivs
3099           && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3100         return;
3101
3102       elimination_effects (SUBREG_REG (x), mem_mode);
3103       return;
3104
3105     case USE:
3106       /* If using a register that is the source of an eliminate we still
3107          think can be performed, note it cannot be performed since we don't
3108          know how this register is used.  */
3109       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3110         if (ep->from_rtx == XEXP (x, 0))
3111           ep->can_eliminate = 0;
3112
3113       elimination_effects (XEXP (x, 0), mem_mode);
3114       return;
3115
3116     case CLOBBER:
3117       /* If clobbering a register that is the replacement register for an
3118          elimination we still think can be performed, note that it cannot
3119          be performed.  Otherwise, we need not be concerned about it.  */
3120       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3121         if (ep->to_rtx == XEXP (x, 0))
3122           ep->can_eliminate = 0;
3123
3124       elimination_effects (XEXP (x, 0), mem_mode);
3125       return;
3126
3127     case SET:
3128       /* Check for setting a register that we know about.  */
3129       if (REG_P (SET_DEST (x)))
3130         {
3131           /* See if this is setting the replacement register for an
3132              elimination.
3133
3134              If DEST is the hard frame pointer, we do nothing because we
3135              assume that all assignments to the frame pointer are for
3136              non-local gotos and are being done at a time when they are valid
3137              and do not disturb anything else.  Some machines want to
3138              eliminate a fake argument pointer (or even a fake frame pointer)
3139              with either the real frame or the stack pointer.  Assignments to
3140              the hard frame pointer must not prevent this elimination.  */
3141
3142           for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3143                ep++)
3144             if (ep->to_rtx == SET_DEST (x)
3145                 && SET_DEST (x) != hard_frame_pointer_rtx)
3146               {
3147                 /* If it is being incremented, adjust the offset.  Otherwise,
3148                    this elimination can't be done.  */
3149                 rtx src = SET_SRC (x);
3150
3151                 if (GET_CODE (src) == PLUS
3152                     && XEXP (src, 0) == SET_DEST (x)
3153                     && CONST_INT_P (XEXP (src, 1)))
3154                   ep->offset -= INTVAL (XEXP (src, 1));
3155                 else
3156                   ep->can_eliminate = 0;
3157               }
3158         }
3159
3160       elimination_effects (SET_DEST (x), VOIDmode);
3161       elimination_effects (SET_SRC (x), VOIDmode);
3162       return;
3163
3164     case MEM:
3165       /* Our only special processing is to pass the mode of the MEM to our
3166          recursive call.  */
3167       elimination_effects (XEXP (x, 0), GET_MODE (x));
3168       return;
3169
3170     default:
3171       break;
3172     }
3173
3174   fmt = GET_RTX_FORMAT (code);
3175   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3176     {
3177       if (*fmt == 'e')
3178         elimination_effects (XEXP (x, i), mem_mode);
3179       else if (*fmt == 'E')
3180         for (j = 0; j < XVECLEN (x, i); j++)
3181           elimination_effects (XVECEXP (x, i, j), mem_mode);
3182     }
3183 }
3184
3185 /* Descend through rtx X and verify that no references to eliminable registers
3186    remain.  If any do remain, mark the involved register as not
3187    eliminable.  */
3188
3189 static void
3190 check_eliminable_occurrences (rtx x)
3191 {
3192   const char *fmt;
3193   int i;
3194   enum rtx_code code;
3195
3196   if (x == 0)
3197     return;
3198
3199   code = GET_CODE (x);
3200
3201   if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3202     {
3203       struct elim_table *ep;
3204
3205       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3206         if (ep->from_rtx == x)
3207           ep->can_eliminate = 0;
3208       return;
3209     }
3210
3211   fmt = GET_RTX_FORMAT (code);
3212   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3213     {
3214       if (*fmt == 'e')
3215         check_eliminable_occurrences (XEXP (x, i));
3216       else if (*fmt == 'E')
3217         {
3218           int j;
3219           for (j = 0; j < XVECLEN (x, i); j++)
3220             check_eliminable_occurrences (XVECEXP (x, i, j));
3221         }
3222     }
3223 }
3224 \f
3225 /* Scan INSN and eliminate all eliminable registers in it.
3226
3227    If REPLACE is nonzero, do the replacement destructively.  Also
3228    delete the insn as dead it if it is setting an eliminable register.
3229
3230    If REPLACE is zero, do all our allocations in reload_obstack.
3231
3232    If no eliminations were done and this insn doesn't require any elimination
3233    processing (these are not identical conditions: it might be updating sp,
3234    but not referencing fp; this needs to be seen during reload_as_needed so
3235    that the offset between fp and sp can be taken into consideration), zero
3236    is returned.  Otherwise, 1 is returned.  */
3237
3238 static int
3239 eliminate_regs_in_insn (rtx_insn *insn, int replace)
3240 {
3241   int icode = recog_memoized (insn);
3242   rtx old_body = PATTERN (insn);
3243   int insn_is_asm = asm_noperands (old_body) >= 0;
3244   rtx old_set = single_set (insn);
3245   rtx new_body;
3246   int val = 0;
3247   int i;
3248   rtx substed_operand[MAX_RECOG_OPERANDS];
3249   rtx orig_operand[MAX_RECOG_OPERANDS];
3250   struct elim_table *ep;
3251   rtx plus_src, plus_cst_src;
3252
3253   if (! insn_is_asm && icode < 0)
3254     {
3255       gcc_assert (DEBUG_INSN_P (insn)
3256                   || GET_CODE (PATTERN (insn)) == USE
3257                   || GET_CODE (PATTERN (insn)) == CLOBBER
3258                   || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3259       if (DEBUG_INSN_P (insn))
3260         INSN_VAR_LOCATION_LOC (insn)
3261           = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3262       return 0;
3263     }
3264
3265   if (old_set != 0 && REG_P (SET_DEST (old_set))
3266       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3267     {
3268       /* Check for setting an eliminable register.  */
3269       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3270         if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3271           {
3272             /* If this is setting the frame pointer register to the
3273                hardware frame pointer register and this is an elimination
3274                that will be done (tested above), this insn is really
3275                adjusting the frame pointer downward to compensate for
3276                the adjustment done before a nonlocal goto.  */
3277             if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3278                 && ep->from == FRAME_POINTER_REGNUM
3279                 && ep->to == HARD_FRAME_POINTER_REGNUM)
3280               {
3281                 rtx base = SET_SRC (old_set);
3282                 rtx_insn *base_insn = insn;
3283                 HOST_WIDE_INT offset = 0;
3284
3285                 while (base != ep->to_rtx)
3286                   {
3287                     rtx_insn *prev_insn;
3288                     rtx prev_set;
3289
3290                     if (GET_CODE (base) == PLUS
3291                         && CONST_INT_P (XEXP (base, 1)))
3292                       {
3293                         offset += INTVAL (XEXP (base, 1));
3294                         base = XEXP (base, 0);
3295                       }
3296                     else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3297                              && (prev_set = single_set (prev_insn)) != 0
3298                              && rtx_equal_p (SET_DEST (prev_set), base))
3299                       {
3300                         base = SET_SRC (prev_set);
3301                         base_insn = prev_insn;
3302                       }
3303                     else
3304                       break;
3305                   }
3306
3307                 if (base == ep->to_rtx)
3308                   {
3309                     rtx src = plus_constant (Pmode, ep->to_rtx,
3310                                              offset - ep->offset);
3311
3312                     new_body = old_body;
3313                     if (! replace)
3314                       {
3315                         new_body = copy_insn (old_body);
3316                         if (REG_NOTES (insn))
3317                           REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3318                       }
3319                     PATTERN (insn) = new_body;
3320                     old_set = single_set (insn);
3321
3322                     /* First see if this insn remains valid when we
3323                        make the change.  If not, keep the INSN_CODE
3324                        the same and let reload fit it up.  */
3325                     validate_change (insn, &SET_SRC (old_set), src, 1);
3326                     validate_change (insn, &SET_DEST (old_set),
3327                                      ep->to_rtx, 1);
3328                     if (! apply_change_group ())
3329                       {
3330                         SET_SRC (old_set) = src;
3331                         SET_DEST (old_set) = ep->to_rtx;
3332                       }
3333
3334                     val = 1;
3335                     goto done;
3336                   }
3337               }
3338
3339             /* In this case this insn isn't serving a useful purpose.  We
3340                will delete it in reload_as_needed once we know that this
3341                elimination is, in fact, being done.
3342
3343                If REPLACE isn't set, we can't delete this insn, but needn't
3344                process it since it won't be used unless something changes.  */
3345             if (replace)
3346               {
3347                 delete_dead_insn (insn);
3348                 return 1;
3349               }
3350             val = 1;
3351             goto done;
3352           }
3353     }
3354
3355   /* We allow one special case which happens to work on all machines we
3356      currently support: a single set with the source or a REG_EQUAL
3357      note being a PLUS of an eliminable register and a constant.  */
3358   plus_src = plus_cst_src = 0;
3359   if (old_set && REG_P (SET_DEST (old_set)))
3360     {
3361       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3362         plus_src = SET_SRC (old_set);
3363       /* First see if the source is of the form (plus (...) CST).  */
3364       if (plus_src
3365           && CONST_INT_P (XEXP (plus_src, 1)))
3366         plus_cst_src = plus_src;
3367       else if (REG_P (SET_SRC (old_set))
3368                || plus_src)
3369         {
3370           /* Otherwise, see if we have a REG_EQUAL note of the form
3371              (plus (...) CST).  */
3372           rtx links;
3373           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3374             {
3375               if ((REG_NOTE_KIND (links) == REG_EQUAL
3376                    || REG_NOTE_KIND (links) == REG_EQUIV)
3377                   && GET_CODE (XEXP (links, 0)) == PLUS
3378                   && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3379                 {
3380                   plus_cst_src = XEXP (links, 0);
3381                   break;
3382                 }
3383             }
3384         }
3385
3386       /* Check that the first operand of the PLUS is a hard reg or
3387          the lowpart subreg of one.  */
3388       if (plus_cst_src)
3389         {
3390           rtx reg = XEXP (plus_cst_src, 0);
3391           if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3392             reg = SUBREG_REG (reg);
3393
3394           if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3395             plus_cst_src = 0;
3396         }
3397     }
3398   if (plus_cst_src)
3399     {
3400       rtx reg = XEXP (plus_cst_src, 0);
3401       HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3402
3403       if (GET_CODE (reg) == SUBREG)
3404         reg = SUBREG_REG (reg);
3405
3406       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3407         if (ep->from_rtx == reg && ep->can_eliminate)
3408           {
3409             rtx to_rtx = ep->to_rtx;
3410             offset += ep->offset;
3411             offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3412
3413             if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3414               to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3415                                     to_rtx);
3416             /* If we have a nonzero offset, and the source is already
3417                a simple REG, the following transformation would
3418                increase the cost of the insn by replacing a simple REG
3419                with (plus (reg sp) CST).  So try only when we already
3420                had a PLUS before.  */
3421             if (offset == 0 || plus_src)
3422               {
3423                 rtx new_src = plus_constant (GET_MODE (to_rtx),
3424                                              to_rtx, offset);
3425
3426                 new_body = old_body;
3427                 if (! replace)
3428                   {
3429                     new_body = copy_insn (old_body);
3430                     if (REG_NOTES (insn))
3431                       REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3432                   }
3433                 PATTERN (insn) = new_body;
3434                 old_set = single_set (insn);
3435
3436                 /* First see if this insn remains valid when we make the
3437                    change.  If not, try to replace the whole pattern with
3438                    a simple set (this may help if the original insn was a
3439                    PARALLEL that was only recognized as single_set due to
3440                    REG_UNUSED notes).  If this isn't valid either, keep
3441                    the INSN_CODE the same and let reload fix it up.  */
3442                 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3443                   {
3444                     rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3445
3446                     if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3447                       SET_SRC (old_set) = new_src;
3448                   }
3449               }
3450             else
3451               break;
3452
3453             val = 1;
3454             /* This can't have an effect on elimination offsets, so skip right
3455                to the end.  */
3456             goto done;
3457           }
3458     }
3459
3460   /* Determine the effects of this insn on elimination offsets.  */
3461   elimination_effects (old_body, VOIDmode);
3462
3463   /* Eliminate all eliminable registers occurring in operands that
3464      can be handled by reload.  */
3465   extract_insn (insn);
3466   for (i = 0; i < recog_data.n_operands; i++)
3467     {
3468       orig_operand[i] = recog_data.operand[i];
3469       substed_operand[i] = recog_data.operand[i];
3470
3471       /* For an asm statement, every operand is eliminable.  */
3472       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3473         {
3474           bool is_set_src, in_plus;
3475
3476           /* Check for setting a register that we know about.  */
3477           if (recog_data.operand_type[i] != OP_IN
3478               && REG_P (orig_operand[i]))
3479             {
3480               /* If we are assigning to a register that can be eliminated, it
3481                  must be as part of a PARALLEL, since the code above handles
3482                  single SETs.  We must indicate that we can no longer
3483                  eliminate this reg.  */
3484               for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3485                    ep++)
3486                 if (ep->from_rtx == orig_operand[i])
3487                   ep->can_eliminate = 0;
3488             }
3489
3490           /* Companion to the above plus substitution, we can allow
3491              invariants as the source of a plain move.  */
3492           is_set_src = false;
3493           if (old_set
3494               && recog_data.operand_loc[i] == &SET_SRC (old_set))
3495             is_set_src = true;
3496           in_plus = false;
3497           if (plus_src
3498               && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3499                   || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3500             in_plus = true;
3501
3502           substed_operand[i]
3503             = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3504                                 replace ? insn : NULL_RTX,
3505                                 is_set_src || in_plus, false);
3506           if (substed_operand[i] != orig_operand[i])
3507             val = 1;
3508           /* Terminate the search in check_eliminable_occurrences at
3509              this point.  */
3510           *recog_data.operand_loc[i] = 0;
3511
3512           /* If an output operand changed from a REG to a MEM and INSN is an
3513              insn, write a CLOBBER insn.  */
3514           if (recog_data.operand_type[i] != OP_IN
3515               && REG_P (orig_operand[i])
3516               && MEM_P (substed_operand[i])
3517               && replace)
3518             emit_insn_after (gen_clobber (orig_operand[i]), insn);
3519         }
3520     }
3521
3522   for (i = 0; i < recog_data.n_dups; i++)
3523     *recog_data.dup_loc[i]
3524       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3525
3526   /* If any eliminable remain, they aren't eliminable anymore.  */
3527   check_eliminable_occurrences (old_body);
3528
3529   /* Substitute the operands; the new values are in the substed_operand
3530      array.  */
3531   for (i = 0; i < recog_data.n_operands; i++)
3532     *recog_data.operand_loc[i] = substed_operand[i];
3533   for (i = 0; i < recog_data.n_dups; i++)
3534     *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3535
3536   /* If we are replacing a body that was a (set X (plus Y Z)), try to
3537      re-recognize the insn.  We do this in case we had a simple addition
3538      but now can do this as a load-address.  This saves an insn in this
3539      common case.
3540      If re-recognition fails, the old insn code number will still be used,
3541      and some register operands may have changed into PLUS expressions.
3542      These will be handled by find_reloads by loading them into a register
3543      again.  */
3544
3545   if (val)
3546     {
3547       /* If we aren't replacing things permanently and we changed something,
3548          make another copy to ensure that all the RTL is new.  Otherwise
3549          things can go wrong if find_reload swaps commutative operands
3550          and one is inside RTL that has been copied while the other is not.  */
3551       new_body = old_body;
3552       if (! replace)
3553         {
3554           new_body = copy_insn (old_body);
3555           if (REG_NOTES (insn))
3556             REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3557         }
3558       PATTERN (insn) = new_body;
3559
3560       /* If we had a move insn but now we don't, rerecognize it.  This will
3561          cause spurious re-recognition if the old move had a PARALLEL since
3562          the new one still will, but we can't call single_set without
3563          having put NEW_BODY into the insn and the re-recognition won't
3564          hurt in this rare case.  */
3565       /* ??? Why this huge if statement - why don't we just rerecognize the
3566          thing always?  */
3567       if (! insn_is_asm
3568           && old_set != 0
3569           && ((REG_P (SET_SRC (old_set))
3570                && (GET_CODE (new_body) != SET
3571                    || !REG_P (SET_SRC (new_body))))
3572               /* If this was a load from or store to memory, compare
3573                  the MEM in recog_data.operand to the one in the insn.
3574                  If they are not equal, then rerecognize the insn.  */
3575               || (old_set != 0
3576                   && ((MEM_P (SET_SRC (old_set))
3577                        && SET_SRC (old_set) != recog_data.operand[1])
3578                       || (MEM_P (SET_DEST (old_set))
3579                           && SET_DEST (old_set) != recog_data.operand[0])))
3580               /* If this was an add insn before, rerecognize.  */
3581               || GET_CODE (SET_SRC (old_set)) == PLUS))
3582         {
3583           int new_icode = recog (PATTERN (insn), insn, 0);
3584           if (new_icode >= 0)
3585             INSN_CODE (insn) = new_icode;
3586         }
3587     }
3588
3589   /* Restore the old body.  If there were any changes to it, we made a copy
3590      of it while the changes were still in place, so we'll correctly return
3591      a modified insn below.  */
3592   if (! replace)
3593     {
3594       /* Restore the old body.  */
3595       for (i = 0; i < recog_data.n_operands; i++)
3596         /* Restoring a top-level match_parallel would clobber the new_body
3597            we installed in the insn.  */
3598         if (recog_data.operand_loc[i] != &PATTERN (insn))
3599           *recog_data.operand_loc[i] = orig_operand[i];
3600       for (i = 0; i < recog_data.n_dups; i++)
3601         *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3602     }
3603
3604   /* Update all elimination pairs to reflect the status after the current
3605      insn.  The changes we make were determined by the earlier call to
3606      elimination_effects.
3607
3608      We also detect cases where register elimination cannot be done,
3609      namely, if a register would be both changed and referenced outside a MEM
3610      in the resulting insn since such an insn is often undefined and, even if
3611      not, we cannot know what meaning will be given to it.  Note that it is
3612      valid to have a register used in an address in an insn that changes it
3613      (presumably with a pre- or post-increment or decrement).
3614
3615      If anything changes, return nonzero.  */
3616
3617   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3618     {
3619       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3620         ep->can_eliminate = 0;
3621
3622       ep->ref_outside_mem = 0;
3623
3624       if (ep->previous_offset != ep->offset)
3625         val = 1;
3626     }
3627
3628  done:
3629   /* If we changed something, perform elimination in REG_NOTES.  This is
3630      needed even when REPLACE is zero because a REG_DEAD note might refer
3631      to a register that we eliminate and could cause a different number
3632      of spill registers to be needed in the final reload pass than in
3633      the pre-passes.  */
3634   if (val && REG_NOTES (insn) != 0)
3635     REG_NOTES (insn)
3636       = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3637                           false);
3638
3639   return val;
3640 }
3641
3642 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3643    register allocator.  INSN is the instruction we need to examine, we perform
3644    eliminations in its operands and record cases where eliminating a reg with
3645    an invariant equivalence would add extra cost.  */
3646
3647 static void
3648 elimination_costs_in_insn (rtx_insn *insn)
3649 {
3650   int icode = recog_memoized (insn);
3651   rtx old_body = PATTERN (insn);
3652   int insn_is_asm = asm_noperands (old_body) >= 0;
3653   rtx old_set = single_set (insn);
3654   int i;
3655   rtx orig_operand[MAX_RECOG_OPERANDS];
3656   rtx orig_dup[MAX_RECOG_OPERANDS];
3657   struct elim_table *ep;
3658   rtx plus_src, plus_cst_src;
3659   bool sets_reg_p;
3660
3661   if (! insn_is_asm && icode < 0)
3662     {
3663       gcc_assert (DEBUG_INSN_P (insn)
3664                   || GET_CODE (PATTERN (insn)) == USE
3665                   || GET_CODE (PATTERN (insn)) == CLOBBER
3666                   || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3667       return;
3668     }
3669
3670   if (old_set != 0 && REG_P (SET_DEST (old_set))
3671       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3672     {
3673       /* Check for setting an eliminable register.  */
3674       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3675         if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3676           return;
3677     }
3678
3679   /* We allow one special case which happens to work on all machines we
3680      currently support: a single set with the source or a REG_EQUAL
3681      note being a PLUS of an eliminable register and a constant.  */
3682   plus_src = plus_cst_src = 0;
3683   sets_reg_p = false;
3684   if (old_set && REG_P (SET_DEST (old_set)))
3685     {
3686       sets_reg_p = true;
3687       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3688         plus_src = SET_SRC (old_set);
3689       /* First see if the source is of the form (plus (...) CST).  */
3690       if (plus_src
3691           && CONST_INT_P (XEXP (plus_src, 1)))
3692         plus_cst_src = plus_src;
3693       else if (REG_P (SET_SRC (old_set))
3694                || plus_src)
3695         {
3696           /* Otherwise, see if we have a REG_EQUAL note of the form
3697              (plus (...) CST).  */
3698           rtx links;
3699           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3700             {
3701               if ((REG_NOTE_KIND (links) == REG_EQUAL
3702                    || REG_NOTE_KIND (links) == REG_EQUIV)
3703                   && GET_CODE (XEXP (links, 0)) == PLUS
3704                   && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3705                 {
3706                   plus_cst_src = XEXP (links, 0);
3707                   break;
3708                 }
3709             }
3710         }
3711     }
3712
3713   /* Determine the effects of this insn on elimination offsets.  */
3714   elimination_effects (old_body, VOIDmode);
3715
3716   /* Eliminate all eliminable registers occurring in operands that
3717      can be handled by reload.  */
3718   extract_insn (insn);
3719   for (i = 0; i < recog_data.n_dups; i++)
3720     orig_dup[i] = *recog_data.dup_loc[i];
3721
3722   for (i = 0; i < recog_data.n_operands; i++)
3723     {
3724       orig_operand[i] = recog_data.operand[i];
3725
3726       /* For an asm statement, every operand is eliminable.  */
3727       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3728         {
3729           bool is_set_src, in_plus;
3730
3731           /* Check for setting a register that we know about.  */
3732           if (recog_data.operand_type[i] != OP_IN
3733               && REG_P (orig_operand[i]))
3734             {
3735               /* If we are assigning to a register that can be eliminated, it
3736                  must be as part of a PARALLEL, since the code above handles
3737                  single SETs.  We must indicate that we can no longer
3738                  eliminate this reg.  */
3739               for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3740                    ep++)
3741                 if (ep->from_rtx == orig_operand[i])
3742                   ep->can_eliminate = 0;
3743             }
3744
3745           /* Companion to the above plus substitution, we can allow
3746              invariants as the source of a plain move.  */
3747           is_set_src = false;
3748           if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3749             is_set_src = true;
3750           if (is_set_src && !sets_reg_p)
3751             note_reg_elim_costly (SET_SRC (old_set), insn);
3752           in_plus = false;
3753           if (plus_src && sets_reg_p
3754               && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3755                   || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3756             in_plus = true;
3757
3758           eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3759                             NULL_RTX,
3760                             is_set_src || in_plus, true);
3761           /* Terminate the search in check_eliminable_occurrences at
3762              this point.  */
3763           *recog_data.operand_loc[i] = 0;
3764         }
3765     }
3766
3767   for (i = 0; i < recog_data.n_dups; i++)
3768     *recog_data.dup_loc[i]
3769       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3770
3771   /* If any eliminable remain, they aren't eliminable anymore.  */
3772   check_eliminable_occurrences (old_body);
3773
3774   /* Restore the old body.  */
3775   for (i = 0; i < recog_data.n_operands; i++)
3776     *recog_data.operand_loc[i] = orig_operand[i];
3777   for (i = 0; i < recog_data.n_dups; i++)
3778     *recog_data.dup_loc[i] = orig_dup[i];
3779
3780   /* Update all elimination pairs to reflect the status after the current
3781      insn.  The changes we make were determined by the earlier call to
3782      elimination_effects.  */
3783
3784   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3785     {
3786       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3787         ep->can_eliminate = 0;
3788
3789       ep->ref_outside_mem = 0;
3790     }
3791
3792   return;
3793 }
3794
3795 /* Loop through all elimination pairs.
3796    Recalculate the number not at initial offset.
3797
3798    Compute the maximum offset (minimum offset if the stack does not
3799    grow downward) for each elimination pair.  */
3800
3801 static void
3802 update_eliminable_offsets (void)
3803 {
3804   struct elim_table *ep;
3805
3806   num_not_at_initial_offset = 0;
3807   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3808     {
3809       ep->previous_offset = ep->offset;
3810       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3811         num_not_at_initial_offset++;
3812     }
3813 }
3814
3815 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3816    replacement we currently believe is valid, mark it as not eliminable if X
3817    modifies DEST in any way other than by adding a constant integer to it.
3818
3819    If DEST is the frame pointer, we do nothing because we assume that
3820    all assignments to the hard frame pointer are nonlocal gotos and are being
3821    done at a time when they are valid and do not disturb anything else.
3822    Some machines want to eliminate a fake argument pointer with either the
3823    frame or stack pointer.  Assignments to the hard frame pointer must not
3824    prevent this elimination.
3825
3826    Called via note_stores from reload before starting its passes to scan
3827    the insns of the function.  */
3828
3829 static void
3830 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3831 {
3832   unsigned int i;
3833
3834   /* A SUBREG of a hard register here is just changing its mode.  We should
3835      not see a SUBREG of an eliminable hard register, but check just in
3836      case.  */
3837   if (GET_CODE (dest) == SUBREG)
3838     dest = SUBREG_REG (dest);
3839
3840   if (dest == hard_frame_pointer_rtx)
3841     return;
3842
3843   for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3844     if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3845         && (GET_CODE (x) != SET
3846             || GET_CODE (SET_SRC (x)) != PLUS
3847             || XEXP (SET_SRC (x), 0) != dest
3848             || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3849       {
3850         reg_eliminate[i].can_eliminate_previous
3851           = reg_eliminate[i].can_eliminate = 0;
3852         num_eliminable--;
3853       }
3854 }
3855
3856 /* Verify that the initial elimination offsets did not change since the
3857    last call to set_initial_elim_offsets.  This is used to catch cases
3858    where something illegal happened during reload_as_needed that could
3859    cause incorrect code to be generated if we did not check for it.  */
3860
3861 static bool
3862 verify_initial_elim_offsets (void)
3863 {
3864   HOST_WIDE_INT t;
3865
3866   if (!num_eliminable)
3867     return true;
3868
3869 #ifdef ELIMINABLE_REGS
3870   {
3871    struct elim_table *ep;
3872
3873    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3874      {
3875        INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3876        if (t != ep->initial_offset)
3877          return false;
3878      }
3879   }
3880 #else
3881   INITIAL_FRAME_POINTER_OFFSET (t);
3882   if (t != reg_eliminate[0].initial_offset)
3883     return false;
3884 #endif
3885
3886   return true;
3887 }
3888
3889 /* Reset all offsets on eliminable registers to their initial values.  */
3890
3891 static void
3892 set_initial_elim_offsets (void)
3893 {
3894   struct elim_table *ep = reg_eliminate;
3895
3896 #ifdef ELIMINABLE_REGS
3897   for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3898     {
3899       INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3900       ep->previous_offset = ep->offset = ep->initial_offset;
3901     }
3902 #else
3903   INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3904   ep->previous_offset = ep->offset = ep->initial_offset;
3905 #endif
3906
3907   num_not_at_initial_offset = 0;
3908 }
3909
3910 /* Subroutine of set_initial_label_offsets called via for_each_eh_label.  */
3911
3912 static void
3913 set_initial_eh_label_offset (rtx label)
3914 {
3915   set_label_offsets (label, NULL, 1);
3916 }
3917
3918 /* Initialize the known label offsets.
3919    Set a known offset for each forced label to be at the initial offset
3920    of each elimination.  We do this because we assume that all
3921    computed jumps occur from a location where each elimination is
3922    at its initial offset.
3923    For all other labels, show that we don't know the offsets.  */
3924
3925 static void
3926 set_initial_label_offsets (void)
3927 {
3928   memset (offsets_known_at, 0, num_labels);
3929
3930   for (rtx_insn_list *x = forced_labels; x; x = x->next ())
3931     if (x->insn ())
3932       set_label_offsets (x->insn (), NULL, 1);
3933
3934   for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3935     if (x->insn ())
3936       set_label_offsets (x->insn (), NULL, 1);
3937
3938   for_each_eh_label (set_initial_eh_label_offset);
3939 }
3940
3941 /* Set all elimination offsets to the known values for the code label given
3942    by INSN.  */
3943
3944 static void
3945 set_offsets_for_label (rtx_insn *insn)
3946 {
3947   unsigned int i;
3948   int label_nr = CODE_LABEL_NUMBER (insn);
3949   struct elim_table *ep;
3950
3951   num_not_at_initial_offset = 0;
3952   for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3953     {
3954       ep->offset = ep->previous_offset
3955                  = offsets_at[label_nr - first_label_num][i];
3956       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3957         num_not_at_initial_offset++;
3958     }
3959 }
3960
3961 /* See if anything that happened changes which eliminations are valid.
3962    For example, on the SPARC, whether or not the frame pointer can
3963    be eliminated can depend on what registers have been used.  We need
3964    not check some conditions again (such as flag_omit_frame_pointer)
3965    since they can't have changed.  */
3966
3967 static void
3968 update_eliminables (HARD_REG_SET *pset)
3969 {
3970   int previous_frame_pointer_needed = frame_pointer_needed;
3971   struct elim_table *ep;
3972
3973   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3974     if ((ep->from == HARD_FRAME_POINTER_REGNUM
3975          && targetm.frame_pointer_required ())
3976 #ifdef ELIMINABLE_REGS
3977         || ! targetm.can_eliminate (ep->from, ep->to)
3978 #endif
3979         )
3980       ep->can_eliminate = 0;
3981
3982   /* Look for the case where we have discovered that we can't replace
3983      register A with register B and that means that we will now be
3984      trying to replace register A with register C.  This means we can
3985      no longer replace register C with register B and we need to disable
3986      such an elimination, if it exists.  This occurs often with A == ap,
3987      B == sp, and C == fp.  */
3988
3989   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3990     {
3991       struct elim_table *op;
3992       int new_to = -1;
3993
3994       if (! ep->can_eliminate && ep->can_eliminate_previous)
3995         {
3996           /* Find the current elimination for ep->from, if there is a
3997              new one.  */
3998           for (op = reg_eliminate;
3999                op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
4000             if (op->from == ep->from && op->can_eliminate)
4001               {
4002                 new_to = op->to;
4003                 break;
4004               }
4005
4006           /* See if there is an elimination of NEW_TO -> EP->TO.  If so,
4007              disable it.  */
4008           for (op = reg_eliminate;
4009                op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
4010             if (op->from == new_to && op->to == ep->to)
4011               op->can_eliminate = 0;
4012         }
4013     }
4014
4015   /* See if any registers that we thought we could eliminate the previous
4016      time are no longer eliminable.  If so, something has changed and we
4017      must spill the register.  Also, recompute the number of eliminable
4018      registers and see if the frame pointer is needed; it is if there is
4019      no elimination of the frame pointer that we can perform.  */
4020
4021   frame_pointer_needed = 1;
4022   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4023     {
4024       if (ep->can_eliminate
4025           && ep->from == FRAME_POINTER_REGNUM
4026           && ep->to != HARD_FRAME_POINTER_REGNUM
4027           && (! SUPPORTS_STACK_ALIGNMENT
4028               || ! crtl->stack_realign_needed))
4029         frame_pointer_needed = 0;
4030
4031       if (! ep->can_eliminate && ep->can_eliminate_previous)
4032         {
4033           ep->can_eliminate_previous = 0;
4034           SET_HARD_REG_BIT (*pset, ep->from);
4035           num_eliminable--;
4036         }
4037     }
4038
4039   /* If we didn't need a frame pointer last time, but we do now, spill
4040      the hard frame pointer.  */
4041   if (frame_pointer_needed && ! previous_frame_pointer_needed)
4042     SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4043 }
4044
4045 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4046    Return true iff a register was spilled.  */
4047
4048 static bool
4049 update_eliminables_and_spill (void)
4050 {
4051   int i;
4052   bool did_spill = false;
4053   HARD_REG_SET to_spill;
4054   CLEAR_HARD_REG_SET (to_spill);
4055   update_eliminables (&to_spill);
4056   AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
4057
4058   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4059     if (TEST_HARD_REG_BIT (to_spill, i))
4060       {
4061         spill_hard_reg (i, 1);
4062         did_spill = true;
4063
4064         /* Regardless of the state of spills, if we previously had
4065            a register that we thought we could eliminate, but now can
4066            not eliminate, we must run another pass.
4067
4068            Consider pseudos which have an entry in reg_equiv_* which
4069            reference an eliminable register.  We must make another pass
4070            to update reg_equiv_* so that we do not substitute in the
4071            old value from when we thought the elimination could be
4072            performed.  */
4073       }
4074   return did_spill;
4075 }
4076
4077 /* Return true if X is used as the target register of an elimination.  */
4078
4079 bool
4080 elimination_target_reg_p (rtx x)
4081 {
4082   struct elim_table *ep;
4083
4084   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4085     if (ep->to_rtx == x && ep->can_eliminate)
4086       return true;
4087
4088   return false;
4089 }
4090
4091 /* Initialize the table of registers to eliminate.
4092    Pre-condition: global flag frame_pointer_needed has been set before
4093    calling this function.  */
4094
4095 static void
4096 init_elim_table (void)
4097 {
4098   struct elim_table *ep;
4099 #ifdef ELIMINABLE_REGS
4100   const struct elim_table_1 *ep1;
4101 #endif
4102
4103   if (!reg_eliminate)
4104     reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4105
4106   num_eliminable = 0;
4107
4108 #ifdef ELIMINABLE_REGS
4109   for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4110        ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4111     {
4112       ep->from = ep1->from;
4113       ep->to = ep1->to;
4114       ep->can_eliminate = ep->can_eliminate_previous
4115         = (targetm.can_eliminate (ep->from, ep->to)
4116            && ! (ep->to == STACK_POINTER_REGNUM
4117                  && frame_pointer_needed
4118                  && (! SUPPORTS_STACK_ALIGNMENT
4119                      || ! stack_realign_fp)));
4120     }
4121 #else
4122   reg_eliminate[0].from = reg_eliminate_1[0].from;
4123   reg_eliminate[0].to = reg_eliminate_1[0].to;
4124   reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4125     = ! frame_pointer_needed;
4126 #endif
4127
4128   /* Count the number of eliminable registers and build the FROM and TO
4129      REG rtx's.  Note that code in gen_rtx_REG will cause, e.g.,
4130      gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4131      We depend on this.  */
4132   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4133     {
4134       num_eliminable += ep->can_eliminate;
4135       ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4136       ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4137     }
4138 }
4139
4140 /* Find all the pseudo registers that didn't get hard regs
4141    but do have known equivalent constants or memory slots.
4142    These include parameters (known equivalent to parameter slots)
4143    and cse'd or loop-moved constant memory addresses.
4144
4145    Record constant equivalents in reg_equiv_constant
4146    so they will be substituted by find_reloads.
4147    Record memory equivalents in reg_mem_equiv so they can
4148    be substituted eventually by altering the REG-rtx's.  */
4149
4150 static void
4151 init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4152 {
4153   int i;
4154   rtx_insn *insn;
4155
4156   grow_reg_equivs ();
4157   if (do_subregs)
4158     reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4159   else
4160     reg_max_ref_width = NULL;
4161
4162   num_eliminable_invariants = 0;
4163
4164   first_label_num = get_first_label_num ();
4165   num_labels = max_label_num () - first_label_num;
4166
4167   /* Allocate the tables used to store offset information at labels.  */
4168   offsets_known_at = XNEWVEC (char, num_labels);
4169   offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4170
4171 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4172    to.  If DO_SUBREGS is true, also find all paradoxical subregs and
4173    find largest such for each pseudo.  FIRST is the head of the insn
4174    list.  */
4175
4176   for (insn = first; insn; insn = NEXT_INSN (insn))
4177     {
4178       rtx set = single_set (insn);
4179
4180       /* We may introduce USEs that we want to remove at the end, so
4181          we'll mark them with QImode.  Make sure there are no
4182          previously-marked insns left by say regmove.  */
4183       if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4184           && GET_MODE (insn) != VOIDmode)
4185         PUT_MODE (insn, VOIDmode);
4186
4187       if (do_subregs && NONDEBUG_INSN_P (insn))
4188         scan_paradoxical_subregs (PATTERN (insn));
4189
4190       if (set != 0 && REG_P (SET_DEST (set)))
4191         {
4192           rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4193           rtx x;
4194
4195           if (! note)
4196             continue;
4197
4198           i = REGNO (SET_DEST (set));
4199           x = XEXP (note, 0);
4200
4201           if (i <= LAST_VIRTUAL_REGISTER)
4202             continue;
4203
4204           /* If flag_pic and we have constant, verify it's legitimate.  */
4205           if (!CONSTANT_P (x)
4206               || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4207             {
4208               /* It can happen that a REG_EQUIV note contains a MEM
4209                  that is not a legitimate memory operand.  As later
4210                  stages of reload assume that all addresses found
4211                  in the reg_equiv_* arrays were originally legitimate,
4212                  we ignore such REG_EQUIV notes.  */
4213               if (memory_operand (x, VOIDmode))
4214                 {
4215                   /* Always unshare the equivalence, so we can
4216                      substitute into this insn without touching the
4217                        equivalence.  */
4218                   reg_equiv_memory_loc (i) = copy_rtx (x);
4219                 }
4220               else if (function_invariant_p (x))
4221                 {
4222                   machine_mode mode;
4223
4224                   mode = GET_MODE (SET_DEST (set));
4225                   if (GET_CODE (x) == PLUS)
4226                     {
4227                       /* This is PLUS of frame pointer and a constant,
4228                          and might be shared.  Unshare it.  */
4229                       reg_equiv_invariant (i) = copy_rtx (x);
4230                       num_eliminable_invariants++;
4231                     }
4232                   else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4233                     {
4234                       reg_equiv_invariant (i) = x;
4235                       num_eliminable_invariants++;
4236                     }
4237                   else if (targetm.legitimate_constant_p (mode, x))
4238                     reg_equiv_constant (i) = x;
4239                   else
4240                     {
4241                       reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4242                       if (! reg_equiv_memory_loc (i))
4243                         reg_equiv_init (i) = NULL;
4244                     }
4245                 }
4246               else
4247                 {
4248                   reg_equiv_init (i) = NULL;
4249                   continue;
4250                 }
4251             }
4252           else
4253             reg_equiv_init (i) = NULL;
4254         }
4255     }
4256
4257   if (dump_file)
4258     for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4259       if (reg_equiv_init (i))
4260         {
4261           fprintf (dump_file, "init_insns for %u: ", i);
4262           print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4263           fprintf (dump_file, "\n");
4264         }
4265 }
4266
4267 /* Indicate that we no longer have known memory locations or constants.
4268    Free all data involved in tracking these.  */
4269
4270 static void
4271 free_reg_equiv (void)
4272 {
4273   int i;
4274
4275   free (offsets_known_at);
4276   free (offsets_at);
4277   offsets_at = 0;
4278   offsets_known_at = 0;
4279
4280   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4281     if (reg_equiv_alt_mem_list (i))
4282       free_EXPR_LIST_list (&reg_equiv_alt_mem_list (i));
4283   vec_free (reg_equivs);
4284 }
4285 \f
4286 /* Kick all pseudos out of hard register REGNO.
4287
4288    If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4289    because we found we can't eliminate some register.  In the case, no pseudos
4290    are allowed to be in the register, even if they are only in a block that
4291    doesn't require spill registers, unlike the case when we are spilling this
4292    hard reg to produce another spill register.
4293
4294    Return nonzero if any pseudos needed to be kicked out.  */
4295
4296 static void
4297 spill_hard_reg (unsigned int regno, int cant_eliminate)
4298 {
4299   int i;
4300
4301   if (cant_eliminate)
4302     {
4303       SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4304       df_set_regs_ever_live (regno, true);
4305     }
4306
4307   /* Spill every pseudo reg that was allocated to this reg
4308      or to something that overlaps this reg.  */
4309
4310   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4311     if (reg_renumber[i] >= 0
4312         && (unsigned int) reg_renumber[i] <= regno
4313         && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4314       SET_REGNO_REG_SET (&spilled_pseudos, i);
4315 }
4316
4317 /* After find_reload_regs has been run for all insn that need reloads,
4318    and/or spill_hard_regs was called, this function is used to actually
4319    spill pseudo registers and try to reallocate them.  It also sets up the
4320    spill_regs array for use by choose_reload_regs.  */
4321
4322 static int
4323 finish_spills (int global)
4324 {
4325   struct insn_chain *chain;
4326   int something_changed = 0;
4327   unsigned i;
4328   reg_set_iterator rsi;
4329
4330   /* Build the spill_regs array for the function.  */
4331   /* If there are some registers still to eliminate and one of the spill regs
4332      wasn't ever used before, additional stack space may have to be
4333      allocated to store this register.  Thus, we may have changed the offset
4334      between the stack and frame pointers, so mark that something has changed.
4335
4336      One might think that we need only set VAL to 1 if this is a call-used
4337      register.  However, the set of registers that must be saved by the
4338      prologue is not identical to the call-used set.  For example, the
4339      register used by the call insn for the return PC is a call-used register,
4340      but must be saved by the prologue.  */
4341
4342   n_spills = 0;
4343   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4344     if (TEST_HARD_REG_BIT (used_spill_regs, i))
4345       {
4346         spill_reg_order[i] = n_spills;
4347         spill_regs[n_spills++] = i;
4348         if (num_eliminable && ! df_regs_ever_live_p (i))
4349           something_changed = 1;
4350         df_set_regs_ever_live (i, true);
4351       }
4352     else
4353       spill_reg_order[i] = -1;
4354
4355   EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4356     if (! ira_conflicts_p || reg_renumber[i] >= 0)
4357       {
4358         /* Record the current hard register the pseudo is allocated to
4359            in pseudo_previous_regs so we avoid reallocating it to the
4360            same hard reg in a later pass.  */
4361         gcc_assert (reg_renumber[i] >= 0);
4362
4363         SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4364         /* Mark it as no longer having a hard register home.  */
4365         reg_renumber[i] = -1;
4366         if (ira_conflicts_p)
4367           /* Inform IRA about the change.  */
4368           ira_mark_allocation_change (i);
4369         /* We will need to scan everything again.  */
4370         something_changed = 1;
4371       }
4372
4373   /* Retry global register allocation if possible.  */
4374   if (global && ira_conflicts_p)
4375     {
4376       unsigned int n;
4377
4378       memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4379       /* For every insn that needs reloads, set the registers used as spill
4380          regs in pseudo_forbidden_regs for every pseudo live across the
4381          insn.  */
4382       for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4383         {
4384           EXECUTE_IF_SET_IN_REG_SET
4385             (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4386             {
4387               IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4388                                 chain->used_spill_regs);
4389             }
4390           EXECUTE_IF_SET_IN_REG_SET
4391             (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4392             {
4393               IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4394                                 chain->used_spill_regs);
4395             }
4396         }
4397
4398       /* Retry allocating the pseudos spilled in IRA and the
4399          reload.  For each reg, merge the various reg sets that
4400          indicate which hard regs can't be used, and call
4401          ira_reassign_pseudos.  */
4402       for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4403         if (reg_old_renumber[i] != reg_renumber[i])
4404           {
4405             if (reg_renumber[i] < 0)
4406               temp_pseudo_reg_arr[n++] = i;
4407             else
4408               CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4409           }
4410       if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4411                                 bad_spill_regs_global,
4412                                 pseudo_forbidden_regs, pseudo_previous_regs,
4413                                 &spilled_pseudos))
4414         something_changed = 1;
4415     }
4416   /* Fix up the register information in the insn chain.
4417      This involves deleting those of the spilled pseudos which did not get
4418      a new hard register home from the live_{before,after} sets.  */
4419   for (chain = reload_insn_chain; chain; chain = chain->next)
4420     {
4421       HARD_REG_SET used_by_pseudos;
4422       HARD_REG_SET used_by_pseudos2;
4423
4424       if (! ira_conflicts_p)
4425         {
4426           /* Don't do it for IRA because IRA and the reload still can
4427              assign hard registers to the spilled pseudos on next
4428              reload iterations.  */
4429           AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4430           AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4431         }
4432       /* Mark any unallocated hard regs as available for spills.  That
4433          makes inheritance work somewhat better.  */
4434       if (chain->need_reload)
4435         {
4436           REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4437           REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4438           IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4439
4440           compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4441           compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4442           /* Value of chain->used_spill_regs from previous iteration
4443              may be not included in the value calculated here because
4444              of possible removing caller-saves insns (see function
4445              delete_caller_save_insns.  */
4446           COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4447           AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4448         }
4449     }
4450
4451   CLEAR_REG_SET (&changed_allocation_pseudos);
4452   /* Let alter_reg modify the reg rtx's for the modified pseudos.  */
4453   for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4454     {
4455       int regno = reg_renumber[i];
4456       if (reg_old_renumber[i] == regno)
4457         continue;
4458
4459       SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4460
4461       alter_reg (i, reg_old_renumber[i], false);
4462       reg_old_renumber[i] = regno;
4463       if (dump_file)
4464         {
4465           if (regno == -1)
4466             fprintf (dump_file, " Register %d now on stack.\n\n", i);
4467           else
4468             fprintf (dump_file, " Register %d now in %d.\n\n",
4469                      i, reg_renumber[i]);
4470         }
4471     }
4472
4473   return something_changed;
4474 }
4475 \f
4476 /* Find all paradoxical subregs within X and update reg_max_ref_width.  */
4477
4478 static void
4479 scan_paradoxical_subregs (rtx x)
4480 {
4481   int i;
4482   const char *fmt;
4483   enum rtx_code code = GET_CODE (x);
4484
4485   switch (code)
4486     {
4487     case REG:
4488     case CONST:
4489     case SYMBOL_REF:
4490     case LABEL_REF:
4491     CASE_CONST_ANY:
4492     case CC0:
4493     case PC:
4494     case USE:
4495     case CLOBBER:
4496       return;
4497
4498     case SUBREG:
4499       if (REG_P (SUBREG_REG (x))
4500           && (GET_MODE_SIZE (GET_MODE (x))
4501               > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4502         {
4503           reg_max_ref_width[REGNO (SUBREG_REG (x))]
4504             = GET_MODE_SIZE (GET_MODE (x));
4505           mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4506         }
4507       return;
4508
4509     default:
4510       break;
4511     }
4512
4513   fmt = GET_RTX_FORMAT (code);
4514   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4515     {
4516       if (fmt[i] == 'e')
4517         scan_paradoxical_subregs (XEXP (x, i));
4518       else if (fmt[i] == 'E')
4519         {
4520           int j;
4521           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4522             scan_paradoxical_subregs (XVECEXP (x, i, j));
4523         }
4524     }
4525 }
4526
4527 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4528    If *OP_PTR is a paradoxical subreg, try to remove that subreg
4529    and apply the corresponding narrowing subreg to *OTHER_PTR.
4530    Return true if the operands were changed, false otherwise.  */
4531
4532 static bool
4533 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4534 {
4535   rtx op, inner, other, tem;
4536
4537   op = *op_ptr;
4538   if (!paradoxical_subreg_p (op))
4539     return false;
4540   inner = SUBREG_REG (op);
4541
4542   other = *other_ptr;
4543   tem = gen_lowpart_common (GET_MODE (inner), other);
4544   if (!tem)
4545     return false;
4546
4547   /* If the lowpart operation turned a hard register into a subreg,
4548      rather than simplifying it to another hard register, then the
4549      mode change cannot be properly represented.  For example, OTHER
4550      might be valid in its current mode, but not in the new one.  */
4551   if (GET_CODE (tem) == SUBREG
4552       && REG_P (other)
4553       && HARD_REGISTER_P (other))
4554     return false;
4555
4556   *op_ptr = inner;
4557   *other_ptr = tem;
4558   return true;
4559 }
4560 \f
4561 /* A subroutine of reload_as_needed.  If INSN has a REG_EH_REGION note,
4562    examine all of the reload insns between PREV and NEXT exclusive, and
4563    annotate all that may trap.  */
4564
4565 static void
4566 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4567 {
4568   rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4569   if (note == NULL)
4570     return;
4571   if (!insn_could_throw_p (insn))
4572     remove_note (insn, note);
4573   copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4574 }
4575
4576 /* Reload pseudo-registers into hard regs around each insn as needed.
4577    Additional register load insns are output before the insn that needs it
4578    and perhaps store insns after insns that modify the reloaded pseudo reg.
4579
4580    reg_last_reload_reg and reg_reloaded_contents keep track of
4581    which registers are already available in reload registers.
4582    We update these for the reloads that we perform,
4583    as the insns are scanned.  */
4584
4585 static void
4586 reload_as_needed (int live_known)
4587 {
4588   struct insn_chain *chain;
4589 #if defined (AUTO_INC_DEC)
4590   int i;
4591 #endif
4592   rtx_note *marker;
4593
4594   memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4595   memset (spill_reg_store, 0, sizeof spill_reg_store);
4596   reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4597   INIT_REG_SET (&reg_has_output_reload);
4598   CLEAR_HARD_REG_SET (reg_reloaded_valid);
4599   CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4600
4601   set_initial_elim_offsets ();
4602
4603   /* Generate a marker insn that we will move around.  */
4604   marker = emit_note (NOTE_INSN_DELETED);
4605   unlink_insn_chain (marker, marker);
4606
4607   for (chain = reload_insn_chain; chain; chain = chain->next)
4608     {
4609       rtx_insn *prev = 0;
4610       rtx_insn *insn = chain->insn;
4611       rtx_insn *old_next = NEXT_INSN (insn);
4612 #ifdef AUTO_INC_DEC
4613       rtx_insn *old_prev = PREV_INSN (insn);
4614 #endif
4615
4616       if (will_delete_init_insn_p (insn))
4617         continue;
4618
4619       /* If we pass a label, copy the offsets from the label information
4620          into the current offsets of each elimination.  */
4621       if (LABEL_P (insn))
4622         set_offsets_for_label (insn);
4623
4624       else if (INSN_P (insn))
4625         {
4626           regset_head regs_to_forget;
4627           INIT_REG_SET (&regs_to_forget);
4628           note_stores (PATTERN (insn), forget_old_reloads_1, &regs_to_forget);
4629
4630           /* If this is a USE and CLOBBER of a MEM, ensure that any
4631              references to eliminable registers have been removed.  */
4632
4633           if ((GET_CODE (PATTERN (insn)) == USE
4634                || GET_CODE (PATTERN (insn)) == CLOBBER)
4635               && MEM_P (XEXP (PATTERN (insn), 0)))
4636             XEXP (XEXP (PATTERN (insn), 0), 0)
4637               = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4638                                 GET_MODE (XEXP (PATTERN (insn), 0)),
4639                                 NULL_RTX);
4640
4641           /* If we need to do register elimination processing, do so.
4642              This might delete the insn, in which case we are done.  */
4643           if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4644             {
4645               eliminate_regs_in_insn (insn, 1);
4646               if (NOTE_P (insn))
4647                 {
4648                   update_eliminable_offsets ();
4649                   CLEAR_REG_SET (&regs_to_forget);
4650                   continue;
4651                 }
4652             }
4653
4654           /* If need_elim is nonzero but need_reload is zero, one might think
4655              that we could simply set n_reloads to 0.  However, find_reloads
4656              could have done some manipulation of the insn (such as swapping
4657              commutative operands), and these manipulations are lost during
4658              the first pass for every insn that needs register elimination.
4659              So the actions of find_reloads must be redone here.  */
4660
4661           if (! chain->need_elim && ! chain->need_reload
4662               && ! chain->need_operand_change)
4663             n_reloads = 0;
4664           /* First find the pseudo regs that must be reloaded for this insn.
4665              This info is returned in the tables reload_... (see reload.h).
4666              Also modify the body of INSN by substituting RELOAD
4667              rtx's for those pseudo regs.  */
4668           else
4669             {
4670               CLEAR_REG_SET (&reg_has_output_reload);
4671               CLEAR_HARD_REG_SET (reg_is_output_reload);
4672
4673               find_reloads (insn, 1, spill_indirect_levels, live_known,
4674                             spill_reg_order);
4675             }
4676
4677           if (n_reloads > 0)
4678             {
4679               rtx_insn *next = NEXT_INSN (insn);
4680
4681               /* ??? PREV can get deleted by reload inheritance.
4682                  Work around this by emitting a marker note.  */
4683               prev = PREV_INSN (insn);
4684               reorder_insns_nobb (marker, marker, prev);
4685
4686               /* Now compute which reload regs to reload them into.  Perhaps
4687                  reusing reload regs from previous insns, or else output
4688                  load insns to reload them.  Maybe output store insns too.
4689                  Record the choices of reload reg in reload_reg_rtx.  */
4690               choose_reload_regs (chain);
4691
4692               /* Generate the insns to reload operands into or out of
4693                  their reload regs.  */
4694               emit_reload_insns (chain);
4695
4696               /* Substitute the chosen reload regs from reload_reg_rtx
4697                  into the insn's body (or perhaps into the bodies of other
4698                  load and store insn that we just made for reloading
4699                  and that we moved the structure into).  */
4700               subst_reloads (insn);
4701
4702               prev = PREV_INSN (marker);
4703               unlink_insn_chain (marker, marker);
4704
4705               /* Adjust the exception region notes for loads and stores.  */
4706               if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4707                 fixup_eh_region_note (insn, prev, next);
4708
4709               /* Adjust the location of REG_ARGS_SIZE.  */
4710               rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4711               if (p)
4712                 {
4713                   remove_note (insn, p);
4714                   fixup_args_size_notes (prev, PREV_INSN (next),
4715                                          INTVAL (XEXP (p, 0)));
4716                 }
4717
4718               /* If this was an ASM, make sure that all the reload insns
4719                  we have generated are valid.  If not, give an error
4720                  and delete them.  */
4721               if (asm_noperands (PATTERN (insn)) >= 0)
4722                 for (rtx_insn *p = NEXT_INSN (prev);
4723                      p != next;
4724                      p = NEXT_INSN (p))
4725                   if (p != insn && INSN_P (p)
4726                       && GET_CODE (PATTERN (p)) != USE
4727                       && (recog_memoized (p) < 0
4728                           || (extract_insn (p),
4729                               !(constrain_operands (1,
4730                                   get_enabled_alternatives (p))))))
4731                     {
4732                       error_for_asm (insn,
4733                                      "%<asm%> operand requires "
4734                                      "impossible reload");
4735                       delete_insn (p);
4736                     }
4737             }
4738
4739           if (num_eliminable && chain->need_elim)
4740             update_eliminable_offsets ();
4741
4742           /* Any previously reloaded spilled pseudo reg, stored in this insn,
4743              is no longer validly lying around to save a future reload.
4744              Note that this does not detect pseudos that were reloaded
4745              for this insn in order to be stored in
4746              (obeying register constraints).  That is correct; such reload
4747              registers ARE still valid.  */
4748           forget_marked_reloads (&regs_to_forget);
4749           CLEAR_REG_SET (&regs_to_forget);
4750
4751           /* There may have been CLOBBER insns placed after INSN.  So scan
4752              between INSN and NEXT and use them to forget old reloads.  */
4753           for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4754             if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4755               note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4756
4757 #ifdef AUTO_INC_DEC
4758           /* Likewise for regs altered by auto-increment in this insn.
4759              REG_INC notes have been changed by reloading:
4760              find_reloads_address_1 records substitutions for them,
4761              which have been performed by subst_reloads above.  */
4762           for (i = n_reloads - 1; i >= 0; i--)
4763             {
4764               rtx in_reg = rld[i].in_reg;
4765               if (in_reg)
4766                 {
4767                   enum rtx_code code = GET_CODE (in_reg);
4768                   /* PRE_INC / PRE_DEC will have the reload register ending up
4769                      with the same value as the stack slot, but that doesn't
4770                      hold true for POST_INC / POST_DEC.  Either we have to
4771                      convert the memory access to a true POST_INC / POST_DEC,
4772                      or we can't use the reload register for inheritance.  */
4773                   if ((code == POST_INC || code == POST_DEC)
4774                       && TEST_HARD_REG_BIT (reg_reloaded_valid,
4775                                             REGNO (rld[i].reg_rtx))
4776                       /* Make sure it is the inc/dec pseudo, and not
4777                          some other (e.g. output operand) pseudo.  */
4778                       && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4779                           == REGNO (XEXP (in_reg, 0))))
4780
4781                     {
4782                       rtx reload_reg = rld[i].reg_rtx;
4783                       machine_mode mode = GET_MODE (reload_reg);
4784                       int n = 0;
4785                       rtx_insn *p;
4786
4787                       for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4788                         {
4789                           /* We really want to ignore REG_INC notes here, so
4790                              use PATTERN (p) as argument to reg_set_p .  */
4791                           if (reg_set_p (reload_reg, PATTERN (p)))
4792                             break;
4793                           n = count_occurrences (PATTERN (p), reload_reg, 0);
4794                           if (! n)
4795                             continue;
4796                           if (n == 1)
4797                             {
4798                               rtx replace_reg
4799                                 = gen_rtx_fmt_e (code, mode, reload_reg);
4800
4801                               validate_replace_rtx_group (reload_reg,
4802                                                           replace_reg, p);
4803                               n = verify_changes (0);
4804
4805                               /* We must also verify that the constraints
4806                                  are met after the replacement.  Make sure
4807                                  extract_insn is only called for an insn
4808                                  where the replacements were found to be
4809                                  valid so far. */
4810                               if (n)
4811                                 {
4812                                   extract_insn (p);
4813                                   n = constrain_operands (1,
4814                                     get_enabled_alternatives (p));
4815                                 }
4816
4817                               /* If the constraints were not met, then
4818                                  undo the replacement, else confirm it.  */
4819                               if (!n)
4820                                 cancel_changes (0);
4821                               else
4822                                 confirm_change_group ();
4823                             }
4824                           break;
4825                         }
4826                       if (n == 1)
4827                         {
4828                           add_reg_note (p, REG_INC, reload_reg);
4829                           /* Mark this as having an output reload so that the
4830                              REG_INC processing code below won't invalidate
4831                              the reload for inheritance.  */
4832                           SET_HARD_REG_BIT (reg_is_output_reload,
4833                                             REGNO (reload_reg));
4834                           SET_REGNO_REG_SET (&reg_has_output_reload,
4835                                              REGNO (XEXP (in_reg, 0)));
4836                         }
4837                       else
4838                         forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4839                                               NULL);
4840                     }
4841                   else if ((code == PRE_INC || code == PRE_DEC)
4842                            && TEST_HARD_REG_BIT (reg_reloaded_valid,
4843                                                  REGNO (rld[i].reg_rtx))
4844                            /* Make sure it is the inc/dec pseudo, and not
4845                               some other (e.g. output operand) pseudo.  */
4846                            && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4847                                == REGNO (XEXP (in_reg, 0))))
4848                     {
4849                       SET_HARD_REG_BIT (reg_is_output_reload,
4850                                         REGNO (rld[i].reg_rtx));
4851                       SET_REGNO_REG_SET (&reg_has_output_reload,
4852                                          REGNO (XEXP (in_reg, 0)));
4853                     }
4854                   else if (code == PRE_INC || code == PRE_DEC
4855                            || code == POST_INC || code == POST_DEC)
4856                     {
4857                       int in_regno = REGNO (XEXP (in_reg, 0));
4858
4859                       if (reg_last_reload_reg[in_regno] != NULL_RTX)
4860                         {
4861                           int in_hard_regno;
4862                           bool forget_p = true;
4863
4864                           in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4865                           if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4866                                                  in_hard_regno))
4867                             {
4868                               for (rtx_insn *x = (old_prev ?
4869                                                   NEXT_INSN (old_prev) : insn);
4870                                    x != old_next;
4871                                    x = NEXT_INSN (x))
4872                                 if (x == reg_reloaded_insn[in_hard_regno])
4873                                   {
4874                                     forget_p = false;
4875                                     break;
4876                                   }
4877                             }
4878                           /* If for some reasons, we didn't set up
4879                              reg_last_reload_reg in this insn,
4880                              invalidate inheritance from previous
4881                              insns for the incremented/decremented
4882                              register.  Such registers will be not in
4883                              reg_has_output_reload.  Invalidate it
4884                              also if the corresponding element in
4885                              reg_reloaded_insn is also
4886                              invalidated.  */
4887                           if (forget_p)
4888                             forget_old_reloads_1 (XEXP (in_reg, 0),
4889                                                   NULL_RTX, NULL);
4890                         }
4891                     }
4892                 }
4893             }
4894           /* If a pseudo that got a hard register is auto-incremented,
4895              we must purge records of copying it into pseudos without
4896              hard registers.  */
4897           for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4898             if (REG_NOTE_KIND (x) == REG_INC)
4899               {
4900                 /* See if this pseudo reg was reloaded in this insn.
4901                    If so, its last-reload info is still valid
4902                    because it is based on this insn's reload.  */
4903                 for (i = 0; i < n_reloads; i++)
4904                   if (rld[i].out == XEXP (x, 0))
4905                     break;
4906
4907                 if (i == n_reloads)
4908                   forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4909               }
4910 #endif
4911         }
4912       /* A reload reg's contents are unknown after a label.  */
4913       if (LABEL_P (insn))
4914         CLEAR_HARD_REG_SET (reg_reloaded_valid);
4915
4916       /* Don't assume a reload reg is still good after a call insn
4917          if it is a call-used reg, or if it contains a value that will
4918          be partially clobbered by the call.  */
4919       else if (CALL_P (insn))
4920         {
4921           AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4922           AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4923
4924           /* If this is a call to a setjmp-type function, we must not
4925              reuse any reload reg contents across the call; that will
4926              just be clobbered by other uses of the register in later
4927              code, before the longjmp.  */
4928           if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4929             CLEAR_HARD_REG_SET (reg_reloaded_valid);
4930         }
4931     }
4932
4933   /* Clean up.  */
4934   free (reg_last_reload_reg);
4935   CLEAR_REG_SET (&reg_has_output_reload);
4936 }
4937
4938 /* Discard all record of any value reloaded from X,
4939    or reloaded in X from someplace else;
4940    unless X is an output reload reg of the current insn.
4941
4942    X may be a hard reg (the reload reg)
4943    or it may be a pseudo reg that was reloaded from.
4944
4945    When DATA is non-NULL just mark the registers in regset
4946    to be forgotten later.  */
4947
4948 static void
4949 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4950                       void *data)
4951 {
4952   unsigned int regno;
4953   unsigned int nr;
4954   regset regs = (regset) data;
4955
4956   /* note_stores does give us subregs of hard regs,
4957      subreg_regno_offset requires a hard reg.  */
4958   while (GET_CODE (x) == SUBREG)
4959     {
4960       /* We ignore the subreg offset when calculating the regno,
4961          because we are using the entire underlying hard register
4962          below.  */
4963       x = SUBREG_REG (x);
4964     }
4965
4966   if (!REG_P (x))
4967     return;
4968
4969   regno = REGNO (x);
4970
4971   if (regno >= FIRST_PSEUDO_REGISTER)
4972     nr = 1;
4973   else
4974     {
4975       unsigned int i;
4976
4977       nr = hard_regno_nregs[regno][GET_MODE (x)];
4978       /* Storing into a spilled-reg invalidates its contents.
4979          This can happen if a block-local pseudo is allocated to that reg
4980          and it wasn't spilled because this block's total need is 0.
4981          Then some insn might have an optional reload and use this reg.  */
4982       if (!regs)
4983         for (i = 0; i < nr; i++)
4984           /* But don't do this if the reg actually serves as an output
4985              reload reg in the current instruction.  */
4986           if (n_reloads == 0
4987               || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4988             {
4989               CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4990               spill_reg_store[regno + i] = 0;
4991             }
4992     }
4993
4994   if (regs)
4995     while (nr-- > 0)
4996       SET_REGNO_REG_SET (regs, regno + nr);
4997   else
4998     {
4999       /* Since value of X has changed,
5000          forget any value previously copied from it.  */
5001
5002       while (nr-- > 0)
5003         /* But don't forget a copy if this is the output reload
5004            that establishes the copy's validity.  */
5005         if (n_reloads == 0
5006             || !REGNO_REG_SET_P (&reg_has_output_reload, regno + nr))
5007           reg_last_reload_reg[regno + nr] = 0;
5008      }
5009 }
5010
5011 /* Forget the reloads marked in regset by previous function.  */
5012 static void
5013 forget_marked_reloads (regset regs)
5014 {
5015   unsigned int reg;
5016   reg_set_iterator rsi;
5017   EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
5018     {
5019       if (reg < FIRST_PSEUDO_REGISTER
5020           /* But don't do this if the reg actually serves as an output
5021              reload reg in the current instruction.  */
5022           && (n_reloads == 0
5023               || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
5024           {
5025             CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
5026             spill_reg_store[reg] = 0;
5027           }
5028       if (n_reloads == 0
5029           || !REGNO_REG_SET_P (&reg_has_output_reload, reg))
5030         reg_last_reload_reg[reg] = 0;
5031     }
5032 }
5033 \f
5034 /* The following HARD_REG_SETs indicate when each hard register is
5035    used for a reload of various parts of the current insn.  */
5036
5037 /* If reg is unavailable for all reloads.  */
5038 static HARD_REG_SET reload_reg_unavailable;
5039 /* If reg is in use as a reload reg for a RELOAD_OTHER reload.  */
5040 static HARD_REG_SET reload_reg_used;
5041 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I.  */
5042 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5043 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I.  */
5044 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5045 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I.  */
5046 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5047 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I.  */
5048 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5049 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I.  */
5050 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5051 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I.  */
5052 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5053 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload.  */
5054 static HARD_REG_SET reload_reg_used_in_op_addr;
5055 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload.  */
5056 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5057 /* If reg is in use for a RELOAD_FOR_INSN reload.  */
5058 static HARD_REG_SET reload_reg_used_in_insn;
5059 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload.  */
5060 static HARD_REG_SET reload_reg_used_in_other_addr;
5061
5062 /* If reg is in use as a reload reg for any sort of reload.  */
5063 static HARD_REG_SET reload_reg_used_at_all;
5064
5065 /* If reg is use as an inherited reload.  We just mark the first register
5066    in the group.  */
5067 static HARD_REG_SET reload_reg_used_for_inherit;
5068
5069 /* Records which hard regs are used in any way, either as explicit use or
5070    by being allocated to a pseudo during any point of the current insn.  */
5071 static HARD_REG_SET reg_used_in_insn;
5072
5073 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5074    TYPE. MODE is used to indicate how many consecutive regs are
5075    actually used.  */
5076
5077 static void
5078 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5079                         machine_mode mode)
5080 {
5081   switch (type)
5082     {
5083     case RELOAD_OTHER:
5084       add_to_hard_reg_set (&reload_reg_used, mode, regno);
5085       break;
5086
5087     case RELOAD_FOR_INPUT_ADDRESS:
5088       add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5089       break;
5090
5091     case RELOAD_FOR_INPADDR_ADDRESS:
5092       add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5093       break;
5094
5095     case RELOAD_FOR_OUTPUT_ADDRESS:
5096       add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5097       break;
5098
5099     case RELOAD_FOR_OUTADDR_ADDRESS:
5100       add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5101       break;
5102
5103     case RELOAD_FOR_OPERAND_ADDRESS:
5104       add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5105       break;
5106
5107     case RELOAD_FOR_OPADDR_ADDR:
5108       add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5109       break;
5110
5111     case RELOAD_FOR_OTHER_ADDRESS:
5112       add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5113       break;
5114
5115     case RELOAD_FOR_INPUT:
5116       add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5117       break;
5118
5119     case RELOAD_FOR_OUTPUT:
5120       add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5121       break;
5122
5123     case RELOAD_FOR_INSN:
5124       add_to_hard_reg_set (&reload_reg_used_in_insn,  mode, regno);
5125       break;
5126     }
5127
5128   add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5129 }
5130
5131 /* Similarly, but show REGNO is no longer in use for a reload.  */
5132
5133 static void
5134 clear_reload_reg_in_use (unsigned int regno, int opnum,
5135                          enum reload_type type, machine_mode mode)
5136 {
5137   unsigned int nregs = hard_regno_nregs[regno][mode];
5138   unsigned int start_regno, end_regno, r;
5139   int i;
5140   /* A complication is that for some reload types, inheritance might
5141      allow multiple reloads of the same types to share a reload register.
5142      We set check_opnum if we have to check only reloads with the same
5143      operand number, and check_any if we have to check all reloads.  */
5144   int check_opnum = 0;
5145   int check_any = 0;
5146   HARD_REG_SET *used_in_set;
5147
5148   switch (type)
5149     {
5150     case RELOAD_OTHER:
5151       used_in_set = &reload_reg_used;
5152       break;
5153
5154     case RELOAD_FOR_INPUT_ADDRESS:
5155       used_in_set = &reload_reg_used_in_input_addr[opnum];
5156       break;
5157
5158     case RELOAD_FOR_INPADDR_ADDRESS:
5159       check_opnum = 1;
5160       used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5161       break;
5162
5163     case RELOAD_FOR_OUTPUT_ADDRESS:
5164       used_in_set = &reload_reg_used_in_output_addr[opnum];
5165       break;
5166
5167     case RELOAD_FOR_OUTADDR_ADDRESS:
5168       check_opnum = 1;
5169       used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5170       break;
5171
5172     case RELOAD_FOR_OPERAND_ADDRESS:
5173       used_in_set = &reload_reg_used_in_op_addr;
5174       break;
5175
5176     case RELOAD_FOR_OPADDR_ADDR:
5177       check_any = 1;
5178       used_in_set = &reload_reg_used_in_op_addr_reload;
5179       break;
5180
5181     case RELOAD_FOR_OTHER_ADDRESS:
5182       used_in_set = &reload_reg_used_in_other_addr;
5183       check_any = 1;
5184       break;
5185
5186     case RELOAD_FOR_INPUT:
5187       used_in_set = &reload_reg_used_in_input[opnum];
5188       break;
5189
5190     case RELOAD_FOR_OUTPUT:
5191       used_in_set = &reload_reg_used_in_output[opnum];
5192       break;
5193
5194     case RELOAD_FOR_INSN:
5195       used_in_set = &reload_reg_used_in_insn;
5196       break;
5197     default:
5198       gcc_unreachable ();
5199     }
5200   /* We resolve conflicts with remaining reloads of the same type by
5201      excluding the intervals of reload registers by them from the
5202      interval of freed reload registers.  Since we only keep track of
5203      one set of interval bounds, we might have to exclude somewhat
5204      more than what would be necessary if we used a HARD_REG_SET here.
5205      But this should only happen very infrequently, so there should
5206      be no reason to worry about it.  */
5207
5208   start_regno = regno;
5209   end_regno = regno + nregs;
5210   if (check_opnum || check_any)
5211     {
5212       for (i = n_reloads - 1; i >= 0; i--)
5213         {
5214           if (rld[i].when_needed == type
5215               && (check_any || rld[i].opnum == opnum)
5216               && rld[i].reg_rtx)
5217             {
5218               unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5219               unsigned int conflict_end
5220                 = end_hard_regno (rld[i].mode, conflict_start);
5221
5222               /* If there is an overlap with the first to-be-freed register,
5223                  adjust the interval start.  */
5224               if (conflict_start <= start_regno && conflict_end > start_regno)
5225                 start_regno = conflict_end;
5226               /* Otherwise, if there is a conflict with one of the other
5227                  to-be-freed registers, adjust the interval end.  */
5228               if (conflict_start > start_regno && conflict_start < end_regno)
5229                 end_regno = conflict_start;
5230             }
5231         }
5232     }
5233
5234   for (r = start_regno; r < end_regno; r++)
5235     CLEAR_HARD_REG_BIT (*used_in_set, r);
5236 }
5237
5238 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5239    specified by OPNUM and TYPE.  */
5240
5241 static int
5242 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5243 {
5244   int i;
5245
5246   /* In use for a RELOAD_OTHER means it's not available for anything.  */
5247   if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5248       || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5249     return 0;
5250
5251   switch (type)
5252     {
5253     case RELOAD_OTHER:
5254       /* In use for anything means we can't use it for RELOAD_OTHER.  */
5255       if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5256           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5257           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5258           || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5259         return 0;
5260
5261       for (i = 0; i < reload_n_operands; i++)
5262         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5263             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5264             || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5265             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5266             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5267             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5268           return 0;
5269
5270       return 1;
5271
5272     case RELOAD_FOR_INPUT:
5273       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5274           || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5275         return 0;
5276
5277       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5278         return 0;
5279
5280       /* If it is used for some other input, can't use it.  */
5281       for (i = 0; i < reload_n_operands; i++)
5282         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5283           return 0;
5284
5285       /* If it is used in a later operand's address, can't use it.  */
5286       for (i = opnum + 1; i < reload_n_operands; i++)
5287         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5288             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5289           return 0;
5290
5291       return 1;
5292
5293     case RELOAD_FOR_INPUT_ADDRESS:
5294       /* Can't use a register if it is used for an input address for this
5295          operand or used as an input in an earlier one.  */
5296       if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5297           || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5298         return 0;
5299
5300       for (i = 0; i < opnum; i++)
5301         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5302           return 0;
5303
5304       return 1;
5305
5306     case RELOAD_FOR_INPADDR_ADDRESS:
5307       /* Can't use a register if it is used for an input address
5308          for this operand or used as an input in an earlier
5309          one.  */
5310       if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5311         return 0;
5312
5313       for (i = 0; i < opnum; i++)
5314         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5315           return 0;
5316
5317       return 1;
5318
5319     case RELOAD_FOR_OUTPUT_ADDRESS:
5320       /* Can't use a register if it is used for an output address for this
5321          operand or used as an output in this or a later operand.  Note
5322          that multiple output operands are emitted in reverse order, so
5323          the conflicting ones are those with lower indices.  */
5324       if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5325         return 0;
5326
5327       for (i = 0; i <= opnum; i++)
5328         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5329           return 0;
5330
5331       return 1;
5332
5333     case RELOAD_FOR_OUTADDR_ADDRESS:
5334       /* Can't use a register if it is used for an output address
5335          for this operand or used as an output in this or a
5336          later operand.  Note that multiple output operands are
5337          emitted in reverse order, so the conflicting ones are
5338          those with lower indices.  */
5339       if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5340         return 0;
5341
5342       for (i = 0; i <= opnum; i++)
5343         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5344           return 0;
5345
5346       return 1;
5347
5348     case RELOAD_FOR_OPERAND_ADDRESS:
5349       for (i = 0; i < reload_n_operands; i++)
5350         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5351           return 0;
5352
5353       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5354               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5355
5356     case RELOAD_FOR_OPADDR_ADDR:
5357       for (i = 0; i < reload_n_operands; i++)
5358         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5359           return 0;
5360
5361       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5362
5363     case RELOAD_FOR_OUTPUT:
5364       /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5365          outputs, or an operand address for this or an earlier output.
5366          Note that multiple output operands are emitted in reverse order,
5367          so the conflicting ones are those with higher indices.  */
5368       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5369         return 0;
5370
5371       for (i = 0; i < reload_n_operands; i++)
5372         if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5373           return 0;
5374
5375       for (i = opnum; i < reload_n_operands; i++)
5376         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5377             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5378           return 0;
5379
5380       return 1;
5381
5382     case RELOAD_FOR_INSN:
5383       for (i = 0; i < reload_n_operands; i++)
5384         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5385             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5386           return 0;
5387
5388       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5389               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5390
5391     case RELOAD_FOR_OTHER_ADDRESS:
5392       return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5393
5394     default:
5395       gcc_unreachable ();
5396     }
5397 }
5398
5399 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5400    the number RELOADNUM, is still available in REGNO at the end of the insn.
5401
5402    We can assume that the reload reg was already tested for availability
5403    at the time it is needed, and we should not check this again,
5404    in case the reg has already been marked in use.  */
5405
5406 static int
5407 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5408 {
5409   int opnum = rld[reloadnum].opnum;
5410   enum reload_type type = rld[reloadnum].when_needed;
5411   int i;
5412
5413   /* See if there is a reload with the same type for this operand, using
5414      the same register. This case is not handled by the code below.  */
5415   for (i = reloadnum + 1; i < n_reloads; i++)
5416     {
5417       rtx reg;
5418       int nregs;
5419
5420       if (rld[i].opnum != opnum || rld[i].when_needed != type)
5421         continue;
5422       reg = rld[i].reg_rtx;
5423       if (reg == NULL_RTX)
5424         continue;
5425       nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5426       if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5427         return 0;
5428     }
5429
5430   switch (type)
5431     {
5432     case RELOAD_OTHER:
5433       /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5434          its value must reach the end.  */
5435       return 1;
5436
5437       /* If this use is for part of the insn,
5438          its value reaches if no subsequent part uses the same register.
5439          Just like the above function, don't try to do this with lots
5440          of fallthroughs.  */
5441
5442     case RELOAD_FOR_OTHER_ADDRESS:
5443       /* Here we check for everything else, since these don't conflict
5444          with anything else and everything comes later.  */
5445
5446       for (i = 0; i < reload_n_operands; i++)
5447         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5448             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5449             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5450             || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5451             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5452             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5453           return 0;
5454
5455       return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5456               && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5457               && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5458               && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5459
5460     case RELOAD_FOR_INPUT_ADDRESS:
5461     case RELOAD_FOR_INPADDR_ADDRESS:
5462       /* Similar, except that we check only for this and subsequent inputs
5463          and the address of only subsequent inputs and we do not need
5464          to check for RELOAD_OTHER objects since they are known not to
5465          conflict.  */
5466
5467       for (i = opnum; i < reload_n_operands; i++)
5468         if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5469           return 0;
5470
5471       /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5472          could be killed if the register is also used by reload with type
5473          RELOAD_FOR_INPUT_ADDRESS, so check it.  */
5474       if (type == RELOAD_FOR_INPADDR_ADDRESS
5475           && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5476         return 0;
5477
5478       for (i = opnum + 1; i < reload_n_operands; i++)
5479         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5480             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5481           return 0;
5482
5483       for (i = 0; i < reload_n_operands; i++)
5484         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5485             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5486             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5487           return 0;
5488
5489       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5490         return 0;
5491
5492       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5493               && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5494               && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5495
5496     case RELOAD_FOR_INPUT:
5497       /* Similar to input address, except we start at the next operand for
5498          both input and input address and we do not check for
5499          RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5500          would conflict.  */
5501
5502       for (i = opnum + 1; i < reload_n_operands; i++)
5503         if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5504             || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5505             || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5506           return 0;
5507
5508       /* ... fall through ...  */
5509
5510     case RELOAD_FOR_OPERAND_ADDRESS:
5511       /* Check outputs and their addresses.  */
5512
5513       for (i = 0; i < reload_n_operands; i++)
5514         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5515             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5516             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5517           return 0;
5518
5519       return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5520
5521     case RELOAD_FOR_OPADDR_ADDR:
5522       for (i = 0; i < reload_n_operands; i++)
5523         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5524             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5525             || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5526           return 0;
5527
5528       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5529               && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5530               && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5531
5532     case RELOAD_FOR_INSN:
5533       /* These conflict with other outputs with RELOAD_OTHER.  So
5534          we need only check for output addresses.  */
5535
5536       opnum = reload_n_operands;
5537
5538       /* ... fall through ...  */
5539
5540     case RELOAD_FOR_OUTPUT:
5541     case RELOAD_FOR_OUTPUT_ADDRESS:
5542     case RELOAD_FOR_OUTADDR_ADDRESS:
5543       /* We already know these can't conflict with a later output.  So the
5544          only thing to check are later output addresses.
5545          Note that multiple output operands are emitted in reverse order,
5546          so the conflicting ones are those with lower indices.  */
5547       for (i = 0; i < opnum; i++)
5548         if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5549             || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5550           return 0;
5551
5552       /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5553          could be killed if the register is also used by reload with type
5554          RELOAD_FOR_OUTPUT_ADDRESS, so check it.  */
5555       if (type == RELOAD_FOR_OUTADDR_ADDRESS
5556           && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5557         return 0;
5558
5559       return 1;
5560
5561     default:
5562       gcc_unreachable ();
5563     }
5564 }
5565
5566 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5567    every register in REG.  */
5568
5569 static bool
5570 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5571 {
5572   unsigned int i;
5573
5574   for (i = REGNO (reg); i < END_REGNO (reg); i++)
5575     if (!reload_reg_reaches_end_p (i, reloadnum))
5576       return false;
5577   return true;
5578 }
5579 \f
5580
5581 /*  Returns whether R1 and R2 are uniquely chained: the value of one
5582     is used by the other, and that value is not used by any other
5583     reload for this insn.  This is used to partially undo the decision
5584     made in find_reloads when in the case of multiple
5585     RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5586     RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5587     reloads.  This code tries to avoid the conflict created by that
5588     change.  It might be cleaner to explicitly keep track of which
5589     RELOAD_FOR_OPADDR_ADDR reload is associated with which
5590     RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5591     this after the fact. */
5592 static bool
5593 reloads_unique_chain_p (int r1, int r2)
5594 {
5595   int i;
5596
5597   /* We only check input reloads.  */
5598   if (! rld[r1].in || ! rld[r2].in)
5599     return false;
5600
5601   /* Avoid anything with output reloads.  */
5602   if (rld[r1].out || rld[r2].out)
5603     return false;
5604
5605   /* "chained" means one reload is a component of the other reload,
5606      not the same as the other reload.  */
5607   if (rld[r1].opnum != rld[r2].opnum
5608       || rtx_equal_p (rld[r1].in, rld[r2].in)
5609       || rld[r1].optional || rld[r2].optional
5610       || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5611             || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5612     return false;
5613
5614   /* The following loop assumes that r1 is the reload that feeds r2.  */
5615   if (r1 > r2)
5616     {
5617       int tmp = r2;
5618       r2 = r1;
5619       r1 = tmp;
5620     }
5621
5622   for (i = 0; i < n_reloads; i ++)
5623     /* Look for input reloads that aren't our two */
5624     if (i != r1 && i != r2 && rld[i].in)
5625       {
5626         /* If our reload is mentioned at all, it isn't a simple chain.  */
5627         if (reg_mentioned_p (rld[r1].in, rld[i].in))
5628           return false;
5629       }
5630   return true;
5631 }
5632
5633 /* The recursive function change all occurrences of WHAT in *WHERE
5634    to REPL.  */
5635 static void
5636 substitute (rtx *where, const_rtx what, rtx repl)
5637 {
5638   const char *fmt;
5639   int i;
5640   enum rtx_code code;
5641
5642   if (*where == 0)
5643     return;
5644
5645   if (*where == what || rtx_equal_p (*where, what))
5646     {
5647       /* Record the location of the changed rtx.  */
5648       substitute_stack.safe_push (where);
5649       *where = repl;
5650       return;
5651     }
5652
5653   code = GET_CODE (*where);
5654   fmt = GET_RTX_FORMAT (code);
5655   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5656     {
5657       if (fmt[i] == 'E')
5658         {
5659           int j;
5660
5661           for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5662             substitute (&XVECEXP (*where, i, j), what, repl);
5663         }
5664       else if (fmt[i] == 'e')
5665         substitute (&XEXP (*where, i), what, repl);
5666     }
5667 }
5668
5669 /* The function returns TRUE if chain of reload R1 and R2 (in any
5670    order) can be evaluated without usage of intermediate register for
5671    the reload containing another reload.  It is important to see
5672    gen_reload to understand what the function is trying to do.  As an
5673    example, let us have reload chain
5674
5675       r2: const
5676       r1: <something> + const
5677
5678    and reload R2 got reload reg HR.  The function returns true if
5679    there is a correct insn HR = HR + <something>.  Otherwise,
5680    gen_reload will use intermediate register (and this is the reload
5681    reg for R1) to reload <something>.
5682
5683    We need this function to find a conflict for chain reloads.  In our
5684    example, if HR = HR + <something> is incorrect insn, then we cannot
5685    use HR as a reload register for R2.  If we do use it then we get a
5686    wrong code:
5687
5688       HR = const
5689       HR = <something>
5690       HR = HR + HR
5691
5692 */
5693 static bool
5694 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5695 {
5696   /* Assume other cases in gen_reload are not possible for
5697      chain reloads or do need an intermediate hard registers.  */
5698   bool result = true;
5699   int regno, code;
5700   rtx out, in;
5701   rtx_insn *insn;
5702   rtx_insn *last = get_last_insn ();
5703
5704   /* Make r2 a component of r1.  */
5705   if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5706     std::swap (r1, r2);
5707
5708   gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5709   regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5710   gcc_assert (regno >= 0);
5711   out = gen_rtx_REG (rld[r1].mode, regno);
5712   in = rld[r1].in;
5713   substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5714
5715   /* If IN is a paradoxical SUBREG, remove it and try to put the
5716      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
5717   strip_paradoxical_subreg (&in, &out);
5718
5719   if (GET_CODE (in) == PLUS
5720       && (REG_P (XEXP (in, 0))
5721           || GET_CODE (XEXP (in, 0)) == SUBREG
5722           || MEM_P (XEXP (in, 0)))
5723       && (REG_P (XEXP (in, 1))
5724           || GET_CODE (XEXP (in, 1)) == SUBREG
5725           || CONSTANT_P (XEXP (in, 1))
5726           || MEM_P (XEXP (in, 1))))
5727     {
5728       insn = emit_insn (gen_rtx_SET (out, in));
5729       code = recog_memoized (insn);
5730       result = false;
5731
5732       if (code >= 0)
5733         {
5734           extract_insn (insn);
5735           /* We want constrain operands to treat this insn strictly in
5736              its validity determination, i.e., the way it would after
5737              reload has completed.  */
5738           result = constrain_operands (1, get_enabled_alternatives (insn));
5739         }
5740
5741       delete_insns_since (last);
5742     }
5743
5744   /* Restore the original value at each changed address within R1.  */
5745   while (!substitute_stack.is_empty ())
5746     {
5747       rtx *where = substitute_stack.pop ();
5748       *where = rld[r2].in;
5749     }
5750
5751   return result;
5752 }
5753
5754 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5755    Return 0 otherwise.
5756
5757    This function uses the same algorithm as reload_reg_free_p above.  */
5758
5759 static int
5760 reloads_conflict (int r1, int r2)
5761 {
5762   enum reload_type r1_type = rld[r1].when_needed;
5763   enum reload_type r2_type = rld[r2].when_needed;
5764   int r1_opnum = rld[r1].opnum;
5765   int r2_opnum = rld[r2].opnum;
5766
5767   /* RELOAD_OTHER conflicts with everything.  */
5768   if (r2_type == RELOAD_OTHER)
5769     return 1;
5770
5771   /* Otherwise, check conflicts differently for each type.  */
5772
5773   switch (r1_type)
5774     {
5775     case RELOAD_FOR_INPUT:
5776       return (r2_type == RELOAD_FOR_INSN
5777               || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5778               || r2_type == RELOAD_FOR_OPADDR_ADDR
5779               || r2_type == RELOAD_FOR_INPUT
5780               || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5781                    || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5782                   && r2_opnum > r1_opnum));
5783
5784     case RELOAD_FOR_INPUT_ADDRESS:
5785       return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5786               || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5787
5788     case RELOAD_FOR_INPADDR_ADDRESS:
5789       return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5790               || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5791
5792     case RELOAD_FOR_OUTPUT_ADDRESS:
5793       return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5794               || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5795
5796     case RELOAD_FOR_OUTADDR_ADDRESS:
5797       return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5798               || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5799
5800     case RELOAD_FOR_OPERAND_ADDRESS:
5801       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5802               || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5803                   && (!reloads_unique_chain_p (r1, r2)
5804                       || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5805
5806     case RELOAD_FOR_OPADDR_ADDR:
5807       return (r2_type == RELOAD_FOR_INPUT
5808               || r2_type == RELOAD_FOR_OPADDR_ADDR);
5809
5810     case RELOAD_FOR_OUTPUT:
5811       return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5812               || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5813                    || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5814                   && r2_opnum >= r1_opnum));
5815
5816     case RELOAD_FOR_INSN:
5817       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5818               || r2_type == RELOAD_FOR_INSN
5819               || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5820
5821     case RELOAD_FOR_OTHER_ADDRESS:
5822       return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5823
5824     case RELOAD_OTHER:
5825       return 1;
5826
5827     default:
5828       gcc_unreachable ();
5829     }
5830 }
5831 \f
5832 /* Indexed by reload number, 1 if incoming value
5833    inherited from previous insns.  */
5834 static char reload_inherited[MAX_RELOADS];
5835
5836 /* For an inherited reload, this is the insn the reload was inherited from,
5837    if we know it.  Otherwise, this is 0.  */
5838 static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5839
5840 /* If nonzero, this is a place to get the value of the reload,
5841    rather than using reload_in.  */
5842 static rtx reload_override_in[MAX_RELOADS];
5843
5844 /* For each reload, the hard register number of the register used,
5845    or -1 if we did not need a register for this reload.  */
5846 static int reload_spill_index[MAX_RELOADS];
5847
5848 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode.  */
5849 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5850
5851 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode.  */
5852 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5853
5854 /* Subroutine of free_for_value_p, used to check a single register.
5855    START_REGNO is the starting regno of the full reload register
5856    (possibly comprising multiple hard registers) that we are considering.  */
5857
5858 static int
5859 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5860                              enum reload_type type, rtx value, rtx out,
5861                              int reloadnum, int ignore_address_reloads)
5862 {
5863   int time1;
5864   /* Set if we see an input reload that must not share its reload register
5865      with any new earlyclobber, but might otherwise share the reload
5866      register with an output or input-output reload.  */
5867   int check_earlyclobber = 0;
5868   int i;
5869   int copy = 0;
5870
5871   if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5872     return 0;
5873
5874   if (out == const0_rtx)
5875     {
5876       copy = 1;
5877       out = NULL_RTX;
5878     }
5879
5880   /* We use some pseudo 'time' value to check if the lifetimes of the
5881      new register use would overlap with the one of a previous reload
5882      that is not read-only or uses a different value.
5883      The 'time' used doesn't have to be linear in any shape or form, just
5884      monotonic.
5885      Some reload types use different 'buckets' for each operand.
5886      So there are MAX_RECOG_OPERANDS different time values for each
5887      such reload type.
5888      We compute TIME1 as the time when the register for the prospective
5889      new reload ceases to be live, and TIME2 for each existing
5890      reload as the time when that the reload register of that reload
5891      becomes live.
5892      Where there is little to be gained by exact lifetime calculations,
5893      we just make conservative assumptions, i.e. a longer lifetime;
5894      this is done in the 'default:' cases.  */
5895   switch (type)
5896     {
5897     case RELOAD_FOR_OTHER_ADDRESS:
5898       /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads.  */
5899       time1 = copy ? 0 : 1;
5900       break;
5901     case RELOAD_OTHER:
5902       time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5903       break;
5904       /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5905          RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT.  By adding 0 / 1 / 2 ,
5906          respectively, to the time values for these, we get distinct time
5907          values.  To get distinct time values for each operand, we have to
5908          multiply opnum by at least three.  We round that up to four because
5909          multiply by four is often cheaper.  */
5910     case RELOAD_FOR_INPADDR_ADDRESS:
5911       time1 = opnum * 4 + 2;
5912       break;
5913     case RELOAD_FOR_INPUT_ADDRESS:
5914       time1 = opnum * 4 + 3;
5915       break;
5916     case RELOAD_FOR_INPUT:
5917       /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5918          executes (inclusive).  */
5919       time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5920       break;
5921     case RELOAD_FOR_OPADDR_ADDR:
5922       /* opnum * 4 + 4
5923          <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5924       time1 = MAX_RECOG_OPERANDS * 4 + 1;
5925       break;
5926     case RELOAD_FOR_OPERAND_ADDRESS:
5927       /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5928          is executed.  */
5929       time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5930       break;
5931     case RELOAD_FOR_OUTADDR_ADDRESS:
5932       time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5933       break;
5934     case RELOAD_FOR_OUTPUT_ADDRESS:
5935       time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5936       break;
5937     default:
5938       time1 = MAX_RECOG_OPERANDS * 5 + 5;
5939     }
5940
5941   for (i = 0; i < n_reloads; i++)
5942     {
5943       rtx reg = rld[i].reg_rtx;
5944       if (reg && REG_P (reg)
5945           && ((unsigned) regno - true_regnum (reg)
5946               <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5947           && i != reloadnum)
5948         {
5949           rtx other_input = rld[i].in;
5950
5951           /* If the other reload loads the same input value, that
5952              will not cause a conflict only if it's loading it into
5953              the same register.  */
5954           if (true_regnum (reg) != start_regno)
5955             other_input = NULL_RTX;
5956           if (! other_input || ! rtx_equal_p (other_input, value)
5957               || rld[i].out || out)
5958             {
5959               int time2;
5960               switch (rld[i].when_needed)
5961                 {
5962                 case RELOAD_FOR_OTHER_ADDRESS:
5963                   time2 = 0;
5964                   break;
5965                 case RELOAD_FOR_INPADDR_ADDRESS:
5966                   /* find_reloads makes sure that a
5967                      RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5968                      by at most one - the first -
5969                      RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS .  If the
5970                      address reload is inherited, the address address reload
5971                      goes away, so we can ignore this conflict.  */
5972                   if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5973                       && ignore_address_reloads
5974                       /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5975                          Then the address address is still needed to store
5976                          back the new address.  */
5977                       && ! rld[reloadnum].out)
5978                     continue;
5979                   /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5980                      RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5981                      reloads go away.  */
5982                   if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5983                       && ignore_address_reloads
5984                       /* Unless we are reloading an auto_inc expression.  */
5985                       && ! rld[reloadnum].out)
5986                     continue;
5987                   time2 = rld[i].opnum * 4 + 2;
5988                   break;
5989                 case RELOAD_FOR_INPUT_ADDRESS:
5990                   if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5991                       && ignore_address_reloads
5992                       && ! rld[reloadnum].out)
5993                     continue;
5994                   time2 = rld[i].opnum * 4 + 3;
5995                   break;
5996                 case RELOAD_FOR_INPUT:
5997                   time2 = rld[i].opnum * 4 + 4;
5998                   check_earlyclobber = 1;
5999                   break;
6000                   /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
6001                      == MAX_RECOG_OPERAND * 4  */
6002                 case RELOAD_FOR_OPADDR_ADDR:
6003                   if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
6004                       && ignore_address_reloads
6005                       && ! rld[reloadnum].out)
6006                     continue;
6007                   time2 = MAX_RECOG_OPERANDS * 4 + 1;
6008                   break;
6009                 case RELOAD_FOR_OPERAND_ADDRESS:
6010                   time2 = MAX_RECOG_OPERANDS * 4 + 2;
6011                   check_earlyclobber = 1;
6012                   break;
6013                 case RELOAD_FOR_INSN:
6014                   time2 = MAX_RECOG_OPERANDS * 4 + 3;
6015                   break;
6016                 case RELOAD_FOR_OUTPUT:
6017                   /* All RELOAD_FOR_OUTPUT reloads become live just after the
6018                      instruction is executed.  */
6019                   time2 = MAX_RECOG_OPERANDS * 4 + 4;
6020                   break;
6021                   /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
6022                      the RELOAD_FOR_OUTPUT reloads, so assign it the same time
6023                      value.  */
6024                 case RELOAD_FOR_OUTADDR_ADDRESS:
6025                   if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
6026                       && ignore_address_reloads
6027                       && ! rld[reloadnum].out)
6028                     continue;
6029                   time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
6030                   break;
6031                 case RELOAD_FOR_OUTPUT_ADDRESS:
6032                   time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
6033                   break;
6034                 case RELOAD_OTHER:
6035                   /* If there is no conflict in the input part, handle this
6036                      like an output reload.  */
6037                   if (! rld[i].in || rtx_equal_p (other_input, value))
6038                     {
6039                       time2 = MAX_RECOG_OPERANDS * 4 + 4;
6040                       /* Earlyclobbered outputs must conflict with inputs.  */
6041                       if (earlyclobber_operand_p (rld[i].out))
6042                         time2 = MAX_RECOG_OPERANDS * 4 + 3;
6043
6044                       break;
6045                     }
6046                   time2 = 1;
6047                   /* RELOAD_OTHER might be live beyond instruction execution,
6048                      but this is not obvious when we set time2 = 1.  So check
6049                      here if there might be a problem with the new reload
6050                      clobbering the register used by the RELOAD_OTHER.  */
6051                   if (out)
6052                     return 0;
6053                   break;
6054                 default:
6055                   return 0;
6056                 }
6057               if ((time1 >= time2
6058                    && (! rld[i].in || rld[i].out
6059                        || ! rtx_equal_p (other_input, value)))
6060                   || (out && rld[reloadnum].out_reg
6061                       && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6062                 return 0;
6063             }
6064         }
6065     }
6066
6067   /* Earlyclobbered outputs must conflict with inputs.  */
6068   if (check_earlyclobber && out && earlyclobber_operand_p (out))
6069     return 0;
6070
6071   return 1;
6072 }
6073
6074 /* Return 1 if the value in reload reg REGNO, as used by a reload
6075    needed for the part of the insn specified by OPNUM and TYPE,
6076    may be used to load VALUE into it.
6077
6078    MODE is the mode in which the register is used, this is needed to
6079    determine how many hard regs to test.
6080
6081    Other read-only reloads with the same value do not conflict
6082    unless OUT is nonzero and these other reloads have to live while
6083    output reloads live.
6084    If OUT is CONST0_RTX, this is a special case: it means that the
6085    test should not be for using register REGNO as reload register, but
6086    for copying from register REGNO into the reload register.
6087
6088    RELOADNUM is the number of the reload we want to load this value for;
6089    a reload does not conflict with itself.
6090
6091    When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6092    reloads that load an address for the very reload we are considering.
6093
6094    The caller has to make sure that there is no conflict with the return
6095    register.  */
6096
6097 static int
6098 free_for_value_p (int regno, machine_mode mode, int opnum,
6099                   enum reload_type type, rtx value, rtx out, int reloadnum,
6100                   int ignore_address_reloads)
6101 {
6102   int nregs = hard_regno_nregs[regno][mode];
6103   while (nregs-- > 0)
6104     if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6105                                        value, out, reloadnum,
6106                                        ignore_address_reloads))
6107       return 0;
6108   return 1;
6109 }
6110
6111 /* Return nonzero if the rtx X is invariant over the current function.  */
6112 /* ??? Actually, the places where we use this expect exactly what is
6113    tested here, and not everything that is function invariant.  In
6114    particular, the frame pointer and arg pointer are special cased;
6115    pic_offset_table_rtx is not, and we must not spill these things to
6116    memory.  */
6117
6118 int
6119 function_invariant_p (const_rtx x)
6120 {
6121   if (CONSTANT_P (x))
6122     return 1;
6123   if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6124     return 1;
6125   if (GET_CODE (x) == PLUS
6126       && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6127       && GET_CODE (XEXP (x, 1)) == CONST_INT)
6128     return 1;
6129   return 0;
6130 }
6131
6132 /* Determine whether the reload reg X overlaps any rtx'es used for
6133    overriding inheritance.  Return nonzero if so.  */
6134
6135 static int
6136 conflicts_with_override (rtx x)
6137 {
6138   int i;
6139   for (i = 0; i < n_reloads; i++)
6140     if (reload_override_in[i]
6141         && reg_overlap_mentioned_p (x, reload_override_in[i]))
6142       return 1;
6143   return 0;
6144 }
6145 \f
6146 /* Give an error message saying we failed to find a reload for INSN,
6147    and clear out reload R.  */
6148 static void
6149 failed_reload (rtx_insn *insn, int r)
6150 {
6151   if (asm_noperands (PATTERN (insn)) < 0)
6152     /* It's the compiler's fault.  */
6153     fatal_insn ("could not find a spill register", insn);
6154
6155   /* It's the user's fault; the operand's mode and constraint
6156      don't match.  Disable this reload so we don't crash in final.  */
6157   error_for_asm (insn,
6158                  "%<asm%> operand constraint incompatible with operand size");
6159   rld[r].in = 0;
6160   rld[r].out = 0;
6161   rld[r].reg_rtx = 0;
6162   rld[r].optional = 1;
6163   rld[r].secondary_p = 1;
6164 }
6165
6166 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6167    for reload R.  If it's valid, get an rtx for it.  Return nonzero if
6168    successful.  */
6169 static int
6170 set_reload_reg (int i, int r)
6171 {
6172   /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6173      parameter.  */
6174   int regno ATTRIBUTE_UNUSED;
6175   rtx reg = spill_reg_rtx[i];
6176
6177   if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6178     spill_reg_rtx[i] = reg
6179       = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6180
6181   regno = true_regnum (reg);
6182
6183   /* Detect when the reload reg can't hold the reload mode.
6184      This used to be one `if', but Sequent compiler can't handle that.  */
6185   if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6186     {
6187       machine_mode test_mode = VOIDmode;
6188       if (rld[r].in)
6189         test_mode = GET_MODE (rld[r].in);
6190       /* If rld[r].in has VOIDmode, it means we will load it
6191          in whatever mode the reload reg has: to wit, rld[r].mode.
6192          We have already tested that for validity.  */
6193       /* Aside from that, we need to test that the expressions
6194          to reload from or into have modes which are valid for this
6195          reload register.  Otherwise the reload insns would be invalid.  */
6196       if (! (rld[r].in != 0 && test_mode != VOIDmode
6197              && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6198         if (! (rld[r].out != 0
6199                && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6200           {
6201             /* The reg is OK.  */
6202             last_spill_reg = i;
6203
6204             /* Mark as in use for this insn the reload regs we use
6205                for this.  */
6206             mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6207                                     rld[r].when_needed, rld[r].mode);
6208
6209             rld[r].reg_rtx = reg;
6210             reload_spill_index[r] = spill_regs[i];
6211             return 1;
6212           }
6213     }
6214   return 0;
6215 }
6216
6217 /* Find a spill register to use as a reload register for reload R.
6218    LAST_RELOAD is nonzero if this is the last reload for the insn being
6219    processed.
6220
6221    Set rld[R].reg_rtx to the register allocated.
6222
6223    We return 1 if successful, or 0 if we couldn't find a spill reg and
6224    we didn't change anything.  */
6225
6226 static int
6227 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6228                      int last_reload)
6229 {
6230   int i, pass, count;
6231
6232   /* If we put this reload ahead, thinking it is a group,
6233      then insist on finding a group.  Otherwise we can grab a
6234      reg that some other reload needs.
6235      (That can happen when we have a 68000 DATA_OR_FP_REG
6236      which is a group of data regs or one fp reg.)
6237      We need not be so restrictive if there are no more reloads
6238      for this insn.
6239
6240      ??? Really it would be nicer to have smarter handling
6241      for that kind of reg class, where a problem like this is normal.
6242      Perhaps those classes should be avoided for reloading
6243      by use of more alternatives.  */
6244
6245   int force_group = rld[r].nregs > 1 && ! last_reload;
6246
6247   /* If we want a single register and haven't yet found one,
6248      take any reg in the right class and not in use.
6249      If we want a consecutive group, here is where we look for it.
6250
6251      We use three passes so we can first look for reload regs to
6252      reuse, which are already in use for other reloads in this insn,
6253      and only then use additional registers which are not "bad", then
6254      finally any register.
6255
6256      I think that maximizing reuse is needed to make sure we don't
6257      run out of reload regs.  Suppose we have three reloads, and
6258      reloads A and B can share regs.  These need two regs.
6259      Suppose A and B are given different regs.
6260      That leaves none for C.  */
6261   for (pass = 0; pass < 3; pass++)
6262     {
6263       /* I is the index in spill_regs.
6264          We advance it round-robin between insns to use all spill regs
6265          equally, so that inherited reloads have a chance
6266          of leapfrogging each other.  */
6267
6268       i = last_spill_reg;
6269
6270       for (count = 0; count < n_spills; count++)
6271         {
6272           int rclass = (int) rld[r].rclass;
6273           int regnum;
6274
6275           i++;
6276           if (i >= n_spills)
6277             i -= n_spills;
6278           regnum = spill_regs[i];
6279
6280           if ((reload_reg_free_p (regnum, rld[r].opnum,
6281                                   rld[r].when_needed)
6282                || (rld[r].in
6283                    /* We check reload_reg_used to make sure we
6284                       don't clobber the return register.  */
6285                    && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6286                    && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6287                                         rld[r].when_needed, rld[r].in,
6288                                         rld[r].out, r, 1)))
6289               && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6290               && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6291               /* Look first for regs to share, then for unshared.  But
6292                  don't share regs used for inherited reloads; they are
6293                  the ones we want to preserve.  */
6294               && (pass
6295                   || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6296                                          regnum)
6297                       && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6298                                               regnum))))
6299             {
6300               int nr = hard_regno_nregs[regnum][rld[r].mode];
6301
6302               /* During the second pass we want to avoid reload registers
6303                  which are "bad" for this reload.  */
6304               if (pass == 1
6305                   && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6306                 continue;
6307
6308               /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6309                  (on 68000) got us two FP regs.  If NR is 1,
6310                  we would reject both of them.  */
6311               if (force_group)
6312                 nr = rld[r].nregs;
6313               /* If we need only one reg, we have already won.  */
6314               if (nr == 1)
6315                 {
6316                   /* But reject a single reg if we demand a group.  */
6317                   if (force_group)
6318                     continue;
6319                   break;
6320                 }
6321               /* Otherwise check that as many consecutive regs as we need
6322                  are available here.  */
6323               while (nr > 1)
6324                 {
6325                   int regno = regnum + nr - 1;
6326                   if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6327                         && spill_reg_order[regno] >= 0
6328                         && reload_reg_free_p (regno, rld[r].opnum,
6329                                               rld[r].when_needed)))
6330                     break;
6331                   nr--;
6332                 }
6333               if (nr == 1)
6334                 break;
6335             }
6336         }
6337
6338       /* If we found something on the current pass, omit later passes.  */
6339       if (count < n_spills)
6340         break;
6341     }
6342
6343   /* We should have found a spill register by now.  */
6344   if (count >= n_spills)
6345     return 0;
6346
6347   /* I is the index in SPILL_REG_RTX of the reload register we are to
6348      allocate.  Get an rtx for it and find its register number.  */
6349
6350   return set_reload_reg (i, r);
6351 }
6352 \f
6353 /* Initialize all the tables needed to allocate reload registers.
6354    CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6355    is the array we use to restore the reg_rtx field for every reload.  */
6356
6357 static void
6358 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6359 {
6360   int i;
6361
6362   for (i = 0; i < n_reloads; i++)
6363     rld[i].reg_rtx = save_reload_reg_rtx[i];
6364
6365   memset (reload_inherited, 0, MAX_RELOADS);
6366   memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6367   memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6368
6369   CLEAR_HARD_REG_SET (reload_reg_used);
6370   CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6371   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6372   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6373   CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6374   CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6375
6376   CLEAR_HARD_REG_SET (reg_used_in_insn);
6377   {
6378     HARD_REG_SET tmp;
6379     REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6380     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6381     REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6382     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6383     compute_use_by_pseudos (&reg_used_in_insn, &chain->live_throughout);
6384     compute_use_by_pseudos (&reg_used_in_insn, &chain->dead_or_set);
6385   }
6386
6387   for (i = 0; i < reload_n_operands; i++)
6388     {
6389       CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6390       CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6391       CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6392       CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6393       CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6394       CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6395     }
6396
6397   COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6398
6399   CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6400
6401   for (i = 0; i < n_reloads; i++)
6402     /* If we have already decided to use a certain register,
6403        don't use it in another way.  */
6404     if (rld[i].reg_rtx)
6405       mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6406                               rld[i].when_needed, rld[i].mode);
6407 }
6408
6409 #ifdef SECONDARY_MEMORY_NEEDED
6410 /* If X is not a subreg, return it unmodified.  If it is a subreg,
6411    look up whether we made a replacement for the SUBREG_REG.  Return
6412    either the replacement or the SUBREG_REG.  */
6413
6414 static rtx
6415 replaced_subreg (rtx x)
6416 {
6417   if (GET_CODE (x) == SUBREG)
6418     return find_replacement (&SUBREG_REG (x));
6419   return x;
6420 }
6421 #endif
6422
6423 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6424    mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6425    SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6426    otherwise it is NULL.  */
6427
6428 static int
6429 compute_reload_subreg_offset (machine_mode outermode,
6430                               rtx subreg,
6431                               machine_mode innermode)
6432 {
6433   int outer_offset;
6434   machine_mode middlemode;
6435
6436   if (!subreg)
6437     return subreg_lowpart_offset (outermode, innermode);
6438
6439   outer_offset = SUBREG_BYTE (subreg);
6440   middlemode = GET_MODE (SUBREG_REG (subreg));
6441
6442   /* If SUBREG is paradoxical then return the normal lowpart offset
6443      for OUTERMODE and INNERMODE.  Our caller has already checked
6444      that OUTERMODE fits in INNERMODE.  */
6445   if (outer_offset == 0
6446       && GET_MODE_SIZE (outermode) > GET_MODE_SIZE (middlemode))
6447     return subreg_lowpart_offset (outermode, innermode);
6448
6449   /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6450      plus the normal lowpart offset for MIDDLEMODE and INNERMODE.  */
6451   return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6452 }
6453
6454 /* Assign hard reg targets for the pseudo-registers we must reload
6455    into hard regs for this insn.
6456    Also output the instructions to copy them in and out of the hard regs.
6457
6458    For machines with register classes, we are responsible for
6459    finding a reload reg in the proper class.  */
6460
6461 static void
6462 choose_reload_regs (struct insn_chain *chain)
6463 {
6464   rtx_insn *insn = chain->insn;
6465   int i, j;
6466   unsigned int max_group_size = 1;
6467   enum reg_class group_class = NO_REGS;
6468   int pass, win, inheritance;
6469
6470   rtx save_reload_reg_rtx[MAX_RELOADS];
6471
6472   /* In order to be certain of getting the registers we need,
6473      we must sort the reloads into order of increasing register class.
6474      Then our grabbing of reload registers will parallel the process
6475      that provided the reload registers.
6476
6477      Also note whether any of the reloads wants a consecutive group of regs.
6478      If so, record the maximum size of the group desired and what
6479      register class contains all the groups needed by this insn.  */
6480
6481   for (j = 0; j < n_reloads; j++)
6482     {
6483       reload_order[j] = j;
6484       if (rld[j].reg_rtx != NULL_RTX)
6485         {
6486           gcc_assert (REG_P (rld[j].reg_rtx)
6487                       && HARD_REGISTER_P (rld[j].reg_rtx));
6488           reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6489         }
6490       else
6491         reload_spill_index[j] = -1;
6492
6493       if (rld[j].nregs > 1)
6494         {
6495           max_group_size = MAX (rld[j].nregs, max_group_size);
6496           group_class
6497             = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6498         }
6499
6500       save_reload_reg_rtx[j] = rld[j].reg_rtx;
6501     }
6502
6503   if (n_reloads > 1)
6504     qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6505
6506   /* If -O, try first with inheritance, then turning it off.
6507      If not -O, don't do inheritance.
6508      Using inheritance when not optimizing leads to paradoxes
6509      with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6510      because one side of the comparison might be inherited.  */
6511   win = 0;
6512   for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6513     {
6514       choose_reload_regs_init (chain, save_reload_reg_rtx);
6515
6516       /* Process the reloads in order of preference just found.
6517          Beyond this point, subregs can be found in reload_reg_rtx.
6518
6519          This used to look for an existing reloaded home for all of the
6520          reloads, and only then perform any new reloads.  But that could lose
6521          if the reloads were done out of reg-class order because a later
6522          reload with a looser constraint might have an old home in a register
6523          needed by an earlier reload with a tighter constraint.
6524
6525          To solve this, we make two passes over the reloads, in the order
6526          described above.  In the first pass we try to inherit a reload
6527          from a previous insn.  If there is a later reload that needs a
6528          class that is a proper subset of the class being processed, we must
6529          also allocate a spill register during the first pass.
6530
6531          Then make a second pass over the reloads to allocate any reloads
6532          that haven't been given registers yet.  */
6533
6534       for (j = 0; j < n_reloads; j++)
6535         {
6536           int r = reload_order[j];
6537           rtx search_equiv = NULL_RTX;
6538
6539           /* Ignore reloads that got marked inoperative.  */
6540           if (rld[r].out == 0 && rld[r].in == 0
6541               && ! rld[r].secondary_p)
6542             continue;
6543
6544           /* If find_reloads chose to use reload_in or reload_out as a reload
6545              register, we don't need to chose one.  Otherwise, try even if it
6546              found one since we might save an insn if we find the value lying
6547              around.
6548              Try also when reload_in is a pseudo without a hard reg.  */
6549           if (rld[r].in != 0 && rld[r].reg_rtx != 0
6550               && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6551                   || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6552                       && !MEM_P (rld[r].in)
6553                       && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6554             continue;
6555
6556 #if 0 /* No longer needed for correct operation.
6557          It might give better code, or might not; worth an experiment?  */
6558           /* If this is an optional reload, we can't inherit from earlier insns
6559              until we are sure that any non-optional reloads have been allocated.
6560              The following code takes advantage of the fact that optional reloads
6561              are at the end of reload_order.  */
6562           if (rld[r].optional != 0)
6563             for (i = 0; i < j; i++)
6564               if ((rld[reload_order[i]].out != 0
6565                    || rld[reload_order[i]].in != 0
6566                    || rld[reload_order[i]].secondary_p)
6567                   && ! rld[reload_order[i]].optional
6568                   && rld[reload_order[i]].reg_rtx == 0)
6569                 allocate_reload_reg (chain, reload_order[i], 0);
6570 #endif
6571
6572           /* First see if this pseudo is already available as reloaded
6573              for a previous insn.  We cannot try to inherit for reloads
6574              that are smaller than the maximum number of registers needed
6575              for groups unless the register we would allocate cannot be used
6576              for the groups.
6577
6578              We could check here to see if this is a secondary reload for
6579              an object that is already in a register of the desired class.
6580              This would avoid the need for the secondary reload register.
6581              But this is complex because we can't easily determine what
6582              objects might want to be loaded via this reload.  So let a
6583              register be allocated here.  In `emit_reload_insns' we suppress
6584              one of the loads in the case described above.  */
6585
6586           if (inheritance)
6587             {
6588               int byte = 0;
6589               int regno = -1;
6590               machine_mode mode = VOIDmode;
6591               rtx subreg = NULL_RTX;
6592
6593               if (rld[r].in == 0)
6594                 ;
6595               else if (REG_P (rld[r].in))
6596                 {
6597                   regno = REGNO (rld[r].in);
6598                   mode = GET_MODE (rld[r].in);
6599                 }
6600               else if (REG_P (rld[r].in_reg))
6601                 {
6602                   regno = REGNO (rld[r].in_reg);
6603                   mode = GET_MODE (rld[r].in_reg);
6604                 }
6605               else if (GET_CODE (rld[r].in_reg) == SUBREG
6606                        && REG_P (SUBREG_REG (rld[r].in_reg)))
6607                 {
6608                   regno = REGNO (SUBREG_REG (rld[r].in_reg));
6609                   if (regno < FIRST_PSEUDO_REGISTER)
6610                     regno = subreg_regno (rld[r].in_reg);
6611                   else
6612                     {
6613                       subreg = rld[r].in_reg;
6614                       byte = SUBREG_BYTE (subreg);
6615                     }
6616                   mode = GET_MODE (rld[r].in_reg);
6617                 }
6618 #ifdef AUTO_INC_DEC
6619               else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6620                        && REG_P (XEXP (rld[r].in_reg, 0)))
6621                 {
6622                   regno = REGNO (XEXP (rld[r].in_reg, 0));
6623                   mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6624                   rld[r].out = rld[r].in;
6625                 }
6626 #endif
6627 #if 0
6628               /* This won't work, since REGNO can be a pseudo reg number.
6629                  Also, it takes much more hair to keep track of all the things
6630                  that can invalidate an inherited reload of part of a pseudoreg.  */
6631               else if (GET_CODE (rld[r].in) == SUBREG
6632                        && REG_P (SUBREG_REG (rld[r].in)))
6633                 regno = subreg_regno (rld[r].in);
6634 #endif
6635
6636               if (regno >= 0
6637                   && reg_last_reload_reg[regno] != 0
6638                   && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6639                       >= GET_MODE_SIZE (mode) + byte)
6640 #ifdef CANNOT_CHANGE_MODE_CLASS
6641                   /* Verify that the register it's in can be used in
6642                      mode MODE.  */
6643                   && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6644                                                 GET_MODE (reg_last_reload_reg[regno]),
6645                                                 mode)
6646 #endif
6647                   )
6648                 {
6649                   enum reg_class rclass = rld[r].rclass, last_class;
6650                   rtx last_reg = reg_last_reload_reg[regno];
6651
6652                   i = REGNO (last_reg);
6653                   byte = compute_reload_subreg_offset (mode,
6654                                                        subreg,
6655                                                        GET_MODE (last_reg));
6656                   i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6657                   last_class = REGNO_REG_CLASS (i);
6658
6659                   if (reg_reloaded_contents[i] == regno
6660                       && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6661                       && HARD_REGNO_MODE_OK (i, rld[r].mode)
6662                       && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6663                           /* Even if we can't use this register as a reload
6664                              register, we might use it for reload_override_in,
6665                              if copying it to the desired class is cheap
6666                              enough.  */
6667                           || ((register_move_cost (mode, last_class, rclass)
6668                                < memory_move_cost (mode, rclass, true))
6669                               && (secondary_reload_class (1, rclass, mode,
6670                                                           last_reg)
6671                                   == NO_REGS)
6672 #ifdef SECONDARY_MEMORY_NEEDED
6673                               && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6674                                                             mode)
6675 #endif
6676                               ))
6677
6678                       && (rld[r].nregs == max_group_size
6679                           || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6680                                                   i))
6681                       && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6682                                            rld[r].when_needed, rld[r].in,
6683                                            const0_rtx, r, 1))
6684                     {
6685                       /* If a group is needed, verify that all the subsequent
6686                          registers still have their values intact.  */
6687                       int nr = hard_regno_nregs[i][rld[r].mode];
6688                       int k;
6689
6690                       for (k = 1; k < nr; k++)
6691                         if (reg_reloaded_contents[i + k] != regno
6692                             || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6693                           break;
6694
6695                       if (k == nr)
6696                         {
6697                           int i1;
6698                           int bad_for_class;
6699
6700                           last_reg = (GET_MODE (last_reg) == mode
6701                                       ? last_reg : gen_rtx_REG (mode, i));
6702
6703                           bad_for_class = 0;
6704                           for (k = 0; k < nr; k++)
6705                             bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6706                                                                   i+k);
6707
6708                           /* We found a register that contains the
6709                              value we need.  If this register is the
6710                              same as an `earlyclobber' operand of the
6711                              current insn, just mark it as a place to
6712                              reload from since we can't use it as the
6713                              reload register itself.  */
6714
6715                           for (i1 = 0; i1 < n_earlyclobbers; i1++)
6716                             if (reg_overlap_mentioned_for_reload_p
6717                                 (reg_last_reload_reg[regno],
6718                                  reload_earlyclobbers[i1]))
6719                               break;
6720
6721                           if (i1 != n_earlyclobbers
6722                               || ! (free_for_value_p (i, rld[r].mode,
6723                                                       rld[r].opnum,
6724                                                       rld[r].when_needed, rld[r].in,
6725                                                       rld[r].out, r, 1))
6726                               /* Don't use it if we'd clobber a pseudo reg.  */
6727                               || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6728                                   && rld[r].out
6729                                   && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6730                               /* Don't clobber the frame pointer.  */
6731                               || (i == HARD_FRAME_POINTER_REGNUM
6732                                   && frame_pointer_needed
6733                                   && rld[r].out)
6734                               /* Don't really use the inherited spill reg
6735                                  if we need it wider than we've got it.  */
6736                               || (GET_MODE_SIZE (rld[r].mode)
6737                                   > GET_MODE_SIZE (mode))
6738                               || bad_for_class
6739
6740                               /* If find_reloads chose reload_out as reload
6741                                  register, stay with it - that leaves the
6742                                  inherited register for subsequent reloads.  */
6743                               || (rld[r].out && rld[r].reg_rtx
6744                                   && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6745                             {
6746                               if (! rld[r].optional)
6747                                 {
6748                                   reload_override_in[r] = last_reg;
6749                                   reload_inheritance_insn[r]
6750                                     = reg_reloaded_insn[i];
6751                                 }
6752                             }
6753                           else
6754                             {
6755                               int k;
6756                               /* We can use this as a reload reg.  */
6757                               /* Mark the register as in use for this part of
6758                                  the insn.  */
6759                               mark_reload_reg_in_use (i,
6760                                                       rld[r].opnum,
6761                                                       rld[r].when_needed,
6762                                                       rld[r].mode);
6763                               rld[r].reg_rtx = last_reg;
6764                               reload_inherited[r] = 1;
6765                               reload_inheritance_insn[r]
6766                                 = reg_reloaded_insn[i];
6767                               reload_spill_index[r] = i;
6768                               for (k = 0; k < nr; k++)
6769                                 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6770                                                   i + k);
6771                             }
6772                         }
6773                     }
6774                 }
6775             }
6776
6777           /* Here's another way to see if the value is already lying around.  */
6778           if (inheritance
6779               && rld[r].in != 0
6780               && ! reload_inherited[r]
6781               && rld[r].out == 0
6782               && (CONSTANT_P (rld[r].in)
6783                   || GET_CODE (rld[r].in) == PLUS
6784                   || REG_P (rld[r].in)
6785                   || MEM_P (rld[r].in))
6786               && (rld[r].nregs == max_group_size
6787                   || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6788             search_equiv = rld[r].in;
6789
6790           if (search_equiv)
6791             {
6792               rtx equiv
6793                 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6794                                   -1, NULL, 0, rld[r].mode);
6795               int regno = 0;
6796
6797               if (equiv != 0)
6798                 {
6799                   if (REG_P (equiv))
6800                     regno = REGNO (equiv);
6801                   else
6802                     {
6803                       /* This must be a SUBREG of a hard register.
6804                          Make a new REG since this might be used in an
6805                          address and not all machines support SUBREGs
6806                          there.  */
6807                       gcc_assert (GET_CODE (equiv) == SUBREG);
6808                       regno = subreg_regno (equiv);
6809                       equiv = gen_rtx_REG (rld[r].mode, regno);
6810                       /* If we choose EQUIV as the reload register, but the
6811                          loop below decides to cancel the inheritance, we'll
6812                          end up reloading EQUIV in rld[r].mode, not the mode
6813                          it had originally.  That isn't safe when EQUIV isn't
6814                          available as a spill register since its value might
6815                          still be live at this point.  */
6816                       for (i = regno; i < regno + (int) rld[r].nregs; i++)
6817                         if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6818                           equiv = 0;
6819                     }
6820                 }
6821
6822               /* If we found a spill reg, reject it unless it is free
6823                  and of the desired class.  */
6824               if (equiv != 0)
6825                 {
6826                   int regs_used = 0;
6827                   int bad_for_class = 0;
6828                   int max_regno = regno + rld[r].nregs;
6829
6830                   for (i = regno; i < max_regno; i++)
6831                     {
6832                       regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6833                                                       i);
6834                       bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6835                                                            i);
6836                     }
6837
6838                   if ((regs_used
6839                        && ! free_for_value_p (regno, rld[r].mode,
6840                                               rld[r].opnum, rld[r].when_needed,
6841                                               rld[r].in, rld[r].out, r, 1))
6842                       || bad_for_class)
6843                     equiv = 0;
6844                 }
6845
6846               if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6847                 equiv = 0;
6848
6849               /* We found a register that contains the value we need.
6850                  If this register is the same as an `earlyclobber' operand
6851                  of the current insn, just mark it as a place to reload from
6852                  since we can't use it as the reload register itself.  */
6853
6854               if (equiv != 0)
6855                 for (i = 0; i < n_earlyclobbers; i++)
6856                   if (reg_overlap_mentioned_for_reload_p (equiv,
6857                                                           reload_earlyclobbers[i]))
6858                     {
6859                       if (! rld[r].optional)
6860                         reload_override_in[r] = equiv;
6861                       equiv = 0;
6862                       break;
6863                     }
6864
6865               /* If the equiv register we have found is explicitly clobbered
6866                  in the current insn, it depends on the reload type if we
6867                  can use it, use it for reload_override_in, or not at all.
6868                  In particular, we then can't use EQUIV for a
6869                  RELOAD_FOR_OUTPUT_ADDRESS reload.  */
6870
6871               if (equiv != 0)
6872                 {
6873                   if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6874                     switch (rld[r].when_needed)
6875                       {
6876                       case RELOAD_FOR_OTHER_ADDRESS:
6877                       case RELOAD_FOR_INPADDR_ADDRESS:
6878                       case RELOAD_FOR_INPUT_ADDRESS:
6879                       case RELOAD_FOR_OPADDR_ADDR:
6880                         break;
6881                       case RELOAD_OTHER:
6882                       case RELOAD_FOR_INPUT:
6883                       case RELOAD_FOR_OPERAND_ADDRESS:
6884                         if (! rld[r].optional)
6885                           reload_override_in[r] = equiv;
6886                         /* Fall through.  */
6887                       default:
6888                         equiv = 0;
6889                         break;
6890                       }
6891                   else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6892                     switch (rld[r].when_needed)
6893                       {
6894                       case RELOAD_FOR_OTHER_ADDRESS:
6895                       case RELOAD_FOR_INPADDR_ADDRESS:
6896                       case RELOAD_FOR_INPUT_ADDRESS:
6897                       case RELOAD_FOR_OPADDR_ADDR:
6898                       case RELOAD_FOR_OPERAND_ADDRESS:
6899                       case RELOAD_FOR_INPUT:
6900                         break;
6901                       case RELOAD_OTHER:
6902                         if (! rld[r].optional)
6903                           reload_override_in[r] = equiv;
6904                         /* Fall through.  */
6905                       default:
6906                         equiv = 0;
6907                         break;
6908                       }
6909                 }
6910
6911               /* If we found an equivalent reg, say no code need be generated
6912                  to load it, and use it as our reload reg.  */
6913               if (equiv != 0
6914                   && (regno != HARD_FRAME_POINTER_REGNUM
6915                       || !frame_pointer_needed))
6916                 {
6917                   int nr = hard_regno_nregs[regno][rld[r].mode];
6918                   int k;
6919                   rld[r].reg_rtx = equiv;
6920                   reload_spill_index[r] = regno;
6921                   reload_inherited[r] = 1;
6922
6923                   /* If reg_reloaded_valid is not set for this register,
6924                      there might be a stale spill_reg_store lying around.
6925                      We must clear it, since otherwise emit_reload_insns
6926                      might delete the store.  */
6927                   if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6928                     spill_reg_store[regno] = NULL;
6929                   /* If any of the hard registers in EQUIV are spill
6930                      registers, mark them as in use for this insn.  */
6931                   for (k = 0; k < nr; k++)
6932                     {
6933                       i = spill_reg_order[regno + k];
6934                       if (i >= 0)
6935                         {
6936                           mark_reload_reg_in_use (regno, rld[r].opnum,
6937                                                   rld[r].when_needed,
6938                                                   rld[r].mode);
6939                           SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6940                                             regno + k);
6941                         }
6942                     }
6943                 }
6944             }
6945
6946           /* If we found a register to use already, or if this is an optional
6947              reload, we are done.  */
6948           if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6949             continue;
6950
6951 #if 0
6952           /* No longer needed for correct operation.  Might or might
6953              not give better code on the average.  Want to experiment?  */
6954
6955           /* See if there is a later reload that has a class different from our
6956              class that intersects our class or that requires less register
6957              than our reload.  If so, we must allocate a register to this
6958              reload now, since that reload might inherit a previous reload
6959              and take the only available register in our class.  Don't do this
6960              for optional reloads since they will force all previous reloads
6961              to be allocated.  Also don't do this for reloads that have been
6962              turned off.  */
6963
6964           for (i = j + 1; i < n_reloads; i++)
6965             {
6966               int s = reload_order[i];
6967
6968               if ((rld[s].in == 0 && rld[s].out == 0
6969                    && ! rld[s].secondary_p)
6970                   || rld[s].optional)
6971                 continue;
6972
6973               if ((rld[s].rclass != rld[r].rclass
6974                    && reg_classes_intersect_p (rld[r].rclass,
6975                                                rld[s].rclass))
6976                   || rld[s].nregs < rld[r].nregs)
6977                 break;
6978             }
6979
6980           if (i == n_reloads)
6981             continue;
6982
6983           allocate_reload_reg (chain, r, j == n_reloads - 1);
6984 #endif
6985         }
6986
6987       /* Now allocate reload registers for anything non-optional that
6988          didn't get one yet.  */
6989       for (j = 0; j < n_reloads; j++)
6990         {
6991           int r = reload_order[j];
6992
6993           /* Ignore reloads that got marked inoperative.  */
6994           if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6995             continue;
6996
6997           /* Skip reloads that already have a register allocated or are
6998              optional.  */
6999           if (rld[r].reg_rtx != 0 || rld[r].optional)
7000             continue;
7001
7002           if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
7003             break;
7004         }
7005
7006       /* If that loop got all the way, we have won.  */
7007       if (j == n_reloads)
7008         {
7009           win = 1;
7010           break;
7011         }
7012
7013       /* Loop around and try without any inheritance.  */
7014     }
7015
7016   if (! win)
7017     {
7018       /* First undo everything done by the failed attempt
7019          to allocate with inheritance.  */
7020       choose_reload_regs_init (chain, save_reload_reg_rtx);
7021
7022       /* Some sanity tests to verify that the reloads found in the first
7023          pass are identical to the ones we have now.  */
7024       gcc_assert (chain->n_reloads == n_reloads);
7025
7026       for (i = 0; i < n_reloads; i++)
7027         {
7028           if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
7029             continue;
7030           gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
7031           for (j = 0; j < n_spills; j++)
7032             if (spill_regs[j] == chain->rld[i].regno)
7033               if (! set_reload_reg (j, i))
7034                 failed_reload (chain->insn, i);
7035         }
7036     }
7037
7038   /* If we thought we could inherit a reload, because it seemed that
7039      nothing else wanted the same reload register earlier in the insn,
7040      verify that assumption, now that all reloads have been assigned.
7041      Likewise for reloads where reload_override_in has been set.  */
7042
7043   /* If doing expensive optimizations, do one preliminary pass that doesn't
7044      cancel any inheritance, but removes reloads that have been needed only
7045      for reloads that we know can be inherited.  */
7046   for (pass = flag_expensive_optimizations; pass >= 0; pass--)
7047     {
7048       for (j = 0; j < n_reloads; j++)
7049         {
7050           int r = reload_order[j];
7051           rtx check_reg;
7052 #ifdef SECONDARY_MEMORY_NEEDED
7053           rtx tem;
7054 #endif
7055           if (reload_inherited[r] && rld[r].reg_rtx)
7056             check_reg = rld[r].reg_rtx;
7057           else if (reload_override_in[r]
7058                    && (REG_P (reload_override_in[r])
7059                        || GET_CODE (reload_override_in[r]) == SUBREG))
7060             check_reg = reload_override_in[r];
7061           else
7062             continue;
7063           if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
7064                                   rld[r].opnum, rld[r].when_needed, rld[r].in,
7065                                   (reload_inherited[r]
7066                                    ? rld[r].out : const0_rtx),
7067                                   r, 1))
7068             {
7069               if (pass)
7070                 continue;
7071               reload_inherited[r] = 0;
7072               reload_override_in[r] = 0;
7073             }
7074           /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7075              reload_override_in, then we do not need its related
7076              RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7077              likewise for other reload types.
7078              We handle this by removing a reload when its only replacement
7079              is mentioned in reload_in of the reload we are going to inherit.
7080              A special case are auto_inc expressions; even if the input is
7081              inherited, we still need the address for the output.  We can
7082              recognize them because they have RELOAD_OUT set to RELOAD_IN.
7083              If we succeeded removing some reload and we are doing a preliminary
7084              pass just to remove such reloads, make another pass, since the
7085              removal of one reload might allow us to inherit another one.  */
7086           else if (rld[r].in
7087                    && rld[r].out != rld[r].in
7088                    && remove_address_replacements (rld[r].in))
7089             {
7090               if (pass)
7091                 pass = 2;
7092             }
7093 #ifdef SECONDARY_MEMORY_NEEDED
7094           /* If we needed a memory location for the reload, we also have to
7095              remove its related reloads.  */
7096           else if (rld[r].in
7097                    && rld[r].out != rld[r].in
7098                    && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7099                    && REGNO (tem) < FIRST_PSEUDO_REGISTER
7100                    && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem)),
7101                                                rld[r].rclass, rld[r].inmode)
7102                    && remove_address_replacements
7103                       (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7104                                           rld[r].when_needed)))
7105             {
7106               if (pass)
7107                 pass = 2;
7108             }
7109 #endif
7110         }
7111     }
7112
7113   /* Now that reload_override_in is known valid,
7114      actually override reload_in.  */
7115   for (j = 0; j < n_reloads; j++)
7116     if (reload_override_in[j])
7117       rld[j].in = reload_override_in[j];
7118
7119   /* If this reload won't be done because it has been canceled or is
7120      optional and not inherited, clear reload_reg_rtx so other
7121      routines (such as subst_reloads) don't get confused.  */
7122   for (j = 0; j < n_reloads; j++)
7123     if (rld[j].reg_rtx != 0
7124         && ((rld[j].optional && ! reload_inherited[j])
7125             || (rld[j].in == 0 && rld[j].out == 0
7126                 && ! rld[j].secondary_p)))
7127       {
7128         int regno = true_regnum (rld[j].reg_rtx);
7129
7130         if (spill_reg_order[regno] >= 0)
7131           clear_reload_reg_in_use (regno, rld[j].opnum,
7132                                    rld[j].when_needed, rld[j].mode);
7133         rld[j].reg_rtx = 0;
7134         reload_spill_index[j] = -1;
7135       }
7136
7137   /* Record which pseudos and which spill regs have output reloads.  */
7138   for (j = 0; j < n_reloads; j++)
7139     {
7140       int r = reload_order[j];
7141
7142       i = reload_spill_index[r];
7143
7144       /* I is nonneg if this reload uses a register.
7145          If rld[r].reg_rtx is 0, this is an optional reload
7146          that we opted to ignore.  */
7147       if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7148           && rld[r].reg_rtx != 0)
7149         {
7150           int nregno = REGNO (rld[r].out_reg);
7151           int nr = 1;
7152
7153           if (nregno < FIRST_PSEUDO_REGISTER)
7154             nr = hard_regno_nregs[nregno][rld[r].mode];
7155
7156           while (--nr >= 0)
7157             SET_REGNO_REG_SET (&reg_has_output_reload,
7158                                nregno + nr);
7159
7160           if (i >= 0)
7161             add_to_hard_reg_set (&reg_is_output_reload, rld[r].mode, i);
7162
7163           gcc_assert (rld[r].when_needed == RELOAD_OTHER
7164                       || rld[r].when_needed == RELOAD_FOR_OUTPUT
7165                       || rld[r].when_needed == RELOAD_FOR_INSN);
7166         }
7167     }
7168 }
7169
7170 /* Deallocate the reload register for reload R.  This is called from
7171    remove_address_replacements.  */
7172
7173 void
7174 deallocate_reload_reg (int r)
7175 {
7176   int regno;
7177
7178   if (! rld[r].reg_rtx)
7179     return;
7180   regno = true_regnum (rld[r].reg_rtx);
7181   rld[r].reg_rtx = 0;
7182   if (spill_reg_order[regno] >= 0)
7183     clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7184                              rld[r].mode);
7185   reload_spill_index[r] = -1;
7186 }
7187 \f
7188 /* These arrays are filled by emit_reload_insns and its subroutines.  */
7189 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7190 static rtx_insn *other_input_address_reload_insns = 0;
7191 static rtx_insn *other_input_reload_insns = 0;
7192 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7193 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7194 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7195 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7196 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7197 static rtx_insn *operand_reload_insns = 0;
7198 static rtx_insn *other_operand_reload_insns = 0;
7199 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7200
7201 /* Values to be put in spill_reg_store are put here first.  Instructions
7202    must only be placed here if the associated reload register reaches
7203    the end of the instruction's reload sequence.  */
7204 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7205 static HARD_REG_SET reg_reloaded_died;
7206
7207 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7208    of class NEW_CLASS with mode NEW_MODE.  Or alternatively, if alt_reload_reg
7209    is nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7210    adjusted register, and return true.  Otherwise, return false.  */
7211 static bool
7212 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7213                             enum reg_class new_class,
7214                             machine_mode new_mode)
7215
7216 {
7217   rtx reg;
7218
7219   for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7220     {
7221       unsigned regno = REGNO (reg);
7222
7223       if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7224         continue;
7225       if (GET_MODE (reg) != new_mode)
7226         {
7227           if (!HARD_REGNO_MODE_OK (regno, new_mode))
7228             continue;
7229           if (hard_regno_nregs[regno][new_mode]
7230               > hard_regno_nregs[regno][GET_MODE (reg)])
7231             continue;
7232           reg = reload_adjust_reg_for_mode (reg, new_mode);
7233         }
7234       *reload_reg = reg;
7235       return true;
7236     }
7237   return false;
7238 }
7239
7240 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7241    pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7242    nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7243    adjusted register, and return true.  Otherwise, return false.  */
7244 static bool
7245 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7246                              enum insn_code icode)
7247
7248 {
7249   enum reg_class new_class = scratch_reload_class (icode);
7250   machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7251
7252   return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7253                                      new_class, new_mode);
7254 }
7255
7256 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7257    has the number J.  OLD contains the value to be used as input.  */
7258
7259 static void
7260 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7261                          rtx old, int j)
7262 {
7263   rtx_insn *insn = chain->insn;
7264   rtx reloadreg;
7265   rtx oldequiv_reg = 0;
7266   rtx oldequiv = 0;
7267   int special = 0;
7268   machine_mode mode;
7269   rtx_insn **where;
7270
7271   /* delete_output_reload is only invoked properly if old contains
7272      the original pseudo register.  Since this is replaced with a
7273      hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7274      find the pseudo in RELOAD_IN_REG.  This is also used to
7275      determine whether a secondary reload is needed.  */
7276   if (reload_override_in[j]
7277       && (REG_P (rl->in_reg)
7278           || (GET_CODE (rl->in_reg) == SUBREG
7279               && REG_P (SUBREG_REG (rl->in_reg)))))
7280     {
7281       oldequiv = old;
7282       old = rl->in_reg;
7283     }
7284   if (oldequiv == 0)
7285     oldequiv = old;
7286   else if (REG_P (oldequiv))
7287     oldequiv_reg = oldequiv;
7288   else if (GET_CODE (oldequiv) == SUBREG)
7289     oldequiv_reg = SUBREG_REG (oldequiv);
7290
7291   reloadreg = reload_reg_rtx_for_input[j];
7292   mode = GET_MODE (reloadreg);
7293
7294   /* If we are reloading from a register that was recently stored in
7295      with an output-reload, see if we can prove there was
7296      actually no need to store the old value in it.  */
7297
7298   if (optimize && REG_P (oldequiv)
7299       && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7300       && spill_reg_store[REGNO (oldequiv)]
7301       && REG_P (old)
7302       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7303           || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7304                           rl->out_reg)))
7305     delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7306
7307   /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7308      OLDEQUIV.  */
7309
7310   while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7311     oldequiv = SUBREG_REG (oldequiv);
7312   if (GET_MODE (oldequiv) != VOIDmode
7313       && mode != GET_MODE (oldequiv))
7314     oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7315
7316   /* Switch to the right place to emit the reload insns.  */
7317   switch (rl->when_needed)
7318     {
7319     case RELOAD_OTHER:
7320       where = &other_input_reload_insns;
7321       break;
7322     case RELOAD_FOR_INPUT:
7323       where = &input_reload_insns[rl->opnum];
7324       break;
7325     case RELOAD_FOR_INPUT_ADDRESS:
7326       where = &input_address_reload_insns[rl->opnum];
7327       break;
7328     case RELOAD_FOR_INPADDR_ADDRESS:
7329       where = &inpaddr_address_reload_insns[rl->opnum];
7330       break;
7331     case RELOAD_FOR_OUTPUT_ADDRESS:
7332       where = &output_address_reload_insns[rl->opnum];
7333       break;
7334     case RELOAD_FOR_OUTADDR_ADDRESS:
7335       where = &outaddr_address_reload_insns[rl->opnum];
7336       break;
7337     case RELOAD_FOR_OPERAND_ADDRESS:
7338       where = &operand_reload_insns;
7339       break;
7340     case RELOAD_FOR_OPADDR_ADDR:
7341       where = &other_operand_reload_insns;
7342       break;
7343     case RELOAD_FOR_OTHER_ADDRESS:
7344       where = &other_input_address_reload_insns;
7345       break;
7346     default:
7347       gcc_unreachable ();
7348     }
7349
7350   push_to_sequence (*where);
7351
7352   /* Auto-increment addresses must be reloaded in a special way.  */
7353   if (rl->out && ! rl->out_reg)
7354     {
7355       /* We are not going to bother supporting the case where a
7356          incremented register can't be copied directly from
7357          OLDEQUIV since this seems highly unlikely.  */
7358       gcc_assert (rl->secondary_in_reload < 0);
7359
7360       if (reload_inherited[j])
7361         oldequiv = reloadreg;
7362
7363       old = XEXP (rl->in_reg, 0);
7364
7365       /* Prevent normal processing of this reload.  */
7366       special = 1;
7367       /* Output a special code sequence for this case.  */
7368       inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7369     }
7370
7371   /* If we are reloading a pseudo-register that was set by the previous
7372      insn, see if we can get rid of that pseudo-register entirely
7373      by redirecting the previous insn into our reload register.  */
7374
7375   else if (optimize && REG_P (old)
7376            && REGNO (old) >= FIRST_PSEUDO_REGISTER
7377            && dead_or_set_p (insn, old)
7378            /* This is unsafe if some other reload
7379               uses the same reg first.  */
7380            && ! conflicts_with_override (reloadreg)
7381            && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7382                                 rl->when_needed, old, rl->out, j, 0))
7383     {
7384       rtx_insn *temp = PREV_INSN (insn);
7385       while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7386         temp = PREV_INSN (temp);
7387       if (temp
7388           && NONJUMP_INSN_P (temp)
7389           && GET_CODE (PATTERN (temp)) == SET
7390           && SET_DEST (PATTERN (temp)) == old
7391           /* Make sure we can access insn_operand_constraint.  */
7392           && asm_noperands (PATTERN (temp)) < 0
7393           /* This is unsafe if operand occurs more than once in current
7394              insn.  Perhaps some occurrences aren't reloaded.  */
7395           && count_occurrences (PATTERN (insn), old, 0) == 1)
7396         {
7397           rtx old = SET_DEST (PATTERN (temp));
7398           /* Store into the reload register instead of the pseudo.  */
7399           SET_DEST (PATTERN (temp)) = reloadreg;
7400
7401           /* Verify that resulting insn is valid.
7402
7403              Note that we have replaced the destination of TEMP with
7404              RELOADREG.  If TEMP references RELOADREG within an
7405              autoincrement addressing mode, then the resulting insn
7406              is ill-formed and we must reject this optimization.  */
7407           extract_insn (temp);
7408           if (constrain_operands (1, get_enabled_alternatives (temp))
7409 #ifdef AUTO_INC_DEC
7410               && ! find_reg_note (temp, REG_INC, reloadreg)
7411 #endif
7412               )
7413             {
7414               /* If the previous insn is an output reload, the source is
7415                  a reload register, and its spill_reg_store entry will
7416                  contain the previous destination.  This is now
7417                  invalid.  */
7418               if (REG_P (SET_SRC (PATTERN (temp)))
7419                   && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7420                 {
7421                   spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7422                   spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7423                 }
7424
7425               /* If these are the only uses of the pseudo reg,
7426                  pretend for GDB it lives in the reload reg we used.  */
7427               if (REG_N_DEATHS (REGNO (old)) == 1
7428                   && REG_N_SETS (REGNO (old)) == 1)
7429                 {
7430                   reg_renumber[REGNO (old)] = REGNO (reloadreg);
7431                   if (ira_conflicts_p)
7432                     /* Inform IRA about the change.  */
7433                     ira_mark_allocation_change (REGNO (old));
7434                   alter_reg (REGNO (old), -1, false);
7435                 }
7436               special = 1;
7437
7438               /* Adjust any debug insns between temp and insn.  */
7439               while ((temp = NEXT_INSN (temp)) != insn)
7440                 if (DEBUG_INSN_P (temp))
7441                   replace_rtx (PATTERN (temp), old, reloadreg);
7442                 else
7443                   gcc_assert (NOTE_P (temp));
7444             }
7445           else
7446             {
7447               SET_DEST (PATTERN (temp)) = old;
7448             }
7449         }
7450     }
7451
7452   /* We can't do that, so output an insn to load RELOADREG.  */
7453
7454   /* If we have a secondary reload, pick up the secondary register
7455      and icode, if any.  If OLDEQUIV and OLD are different or
7456      if this is an in-out reload, recompute whether or not we
7457      still need a secondary register and what the icode should
7458      be.  If we still need a secondary register and the class or
7459      icode is different, go back to reloading from OLD if using
7460      OLDEQUIV means that we got the wrong type of register.  We
7461      cannot have different class or icode due to an in-out reload
7462      because we don't make such reloads when both the input and
7463      output need secondary reload registers.  */
7464
7465   if (! special && rl->secondary_in_reload >= 0)
7466     {
7467       rtx second_reload_reg = 0;
7468       rtx third_reload_reg = 0;
7469       int secondary_reload = rl->secondary_in_reload;
7470       rtx real_oldequiv = oldequiv;
7471       rtx real_old = old;
7472       rtx tmp;
7473       enum insn_code icode;
7474       enum insn_code tertiary_icode = CODE_FOR_nothing;
7475
7476       /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7477          and similarly for OLD.
7478          See comments in get_secondary_reload in reload.c.  */
7479       /* If it is a pseudo that cannot be replaced with its
7480          equivalent MEM, we must fall back to reload_in, which
7481          will have all the necessary substitutions registered.
7482          Likewise for a pseudo that can't be replaced with its
7483          equivalent constant.
7484
7485          Take extra care for subregs of such pseudos.  Note that
7486          we cannot use reg_equiv_mem in this case because it is
7487          not in the right mode.  */
7488
7489       tmp = oldequiv;
7490       if (GET_CODE (tmp) == SUBREG)
7491         tmp = SUBREG_REG (tmp);
7492       if (REG_P (tmp)
7493           && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7494           && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7495               || reg_equiv_constant (REGNO (tmp)) != 0))
7496         {
7497           if (! reg_equiv_mem (REGNO (tmp))
7498               || num_not_at_initial_offset
7499               || GET_CODE (oldequiv) == SUBREG)
7500             real_oldequiv = rl->in;
7501           else
7502             real_oldequiv = reg_equiv_mem (REGNO (tmp));
7503         }
7504
7505       tmp = old;
7506       if (GET_CODE (tmp) == SUBREG)
7507         tmp = SUBREG_REG (tmp);
7508       if (REG_P (tmp)
7509           && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7510           && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7511               || reg_equiv_constant (REGNO (tmp)) != 0))
7512         {
7513           if (! reg_equiv_mem (REGNO (tmp))
7514               || num_not_at_initial_offset
7515               || GET_CODE (old) == SUBREG)
7516             real_old = rl->in;
7517           else
7518             real_old = reg_equiv_mem (REGNO (tmp));
7519         }
7520
7521       second_reload_reg = rld[secondary_reload].reg_rtx;
7522       if (rld[secondary_reload].secondary_in_reload >= 0)
7523         {
7524           int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7525
7526           third_reload_reg = rld[tertiary_reload].reg_rtx;
7527           tertiary_icode = rld[secondary_reload].secondary_in_icode;
7528           /* We'd have to add more code for quartary reloads.  */
7529           gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7530         }
7531       icode = rl->secondary_in_icode;
7532
7533       if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7534           || (rl->in != 0 && rl->out != 0))
7535         {
7536           secondary_reload_info sri, sri2;
7537           enum reg_class new_class, new_t_class;
7538
7539           sri.icode = CODE_FOR_nothing;
7540           sri.prev_sri = NULL;
7541           new_class
7542             = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7543                                                          rl->rclass, mode,
7544                                                          &sri);
7545
7546           if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7547             second_reload_reg = 0;
7548           else if (new_class == NO_REGS)
7549             {
7550               if (reload_adjust_reg_for_icode (&second_reload_reg,
7551                                                third_reload_reg,
7552                                                (enum insn_code) sri.icode))
7553                 {
7554                   icode = (enum insn_code) sri.icode;
7555                   third_reload_reg = 0;
7556                 }
7557               else
7558                 {
7559                   oldequiv = old;
7560                   real_oldequiv = real_old;
7561                 }
7562             }
7563           else if (sri.icode != CODE_FOR_nothing)
7564             /* We currently lack a way to express this in reloads.  */
7565             gcc_unreachable ();
7566           else
7567             {
7568               sri2.icode = CODE_FOR_nothing;
7569               sri2.prev_sri = &sri;
7570               new_t_class
7571                 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7572                                                              new_class, mode,
7573                                                              &sri);
7574               if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7575                 {
7576                   if (reload_adjust_reg_for_temp (&second_reload_reg,
7577                                                   third_reload_reg,
7578                                                   new_class, mode))
7579                     {
7580                       third_reload_reg = 0;
7581                       tertiary_icode = (enum insn_code) sri2.icode;
7582                     }
7583                   else
7584                     {
7585                       oldequiv = old;
7586                       real_oldequiv = real_old;
7587                     }
7588                 }
7589               else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7590                 {
7591                   rtx intermediate = second_reload_reg;
7592
7593                   if (reload_adjust_reg_for_temp (&intermediate, NULL,
7594                                                   new_class, mode)
7595                       && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7596                                                       ((enum insn_code)
7597                                                        sri2.icode)))
7598                     {
7599                       second_reload_reg = intermediate;
7600                       tertiary_icode = (enum insn_code) sri2.icode;
7601                     }
7602                   else
7603                     {
7604                       oldequiv = old;
7605                       real_oldequiv = real_old;
7606                     }
7607                 }
7608               else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7609                 {
7610                   rtx intermediate = second_reload_reg;
7611
7612                   if (reload_adjust_reg_for_temp (&intermediate, NULL,
7613                                                   new_class, mode)
7614                       && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7615                                                       new_t_class, mode))
7616                     {
7617                       second_reload_reg = intermediate;
7618                       tertiary_icode = (enum insn_code) sri2.icode;
7619                     }
7620                   else
7621                     {
7622                       oldequiv = old;
7623                       real_oldequiv = real_old;
7624                     }
7625                 }
7626               else
7627                 {
7628                   /* This could be handled more intelligently too.  */
7629                   oldequiv = old;
7630                   real_oldequiv = real_old;
7631                 }
7632             }
7633         }
7634
7635       /* If we still need a secondary reload register, check
7636          to see if it is being used as a scratch or intermediate
7637          register and generate code appropriately.  If we need
7638          a scratch register, use REAL_OLDEQUIV since the form of
7639          the insn may depend on the actual address if it is
7640          a MEM.  */
7641
7642       if (second_reload_reg)
7643         {
7644           if (icode != CODE_FOR_nothing)
7645             {
7646               /* We'd have to add extra code to handle this case.  */
7647               gcc_assert (!third_reload_reg);
7648
7649               emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7650                                           second_reload_reg));
7651               special = 1;
7652             }
7653           else
7654             {
7655               /* See if we need a scratch register to load the
7656                  intermediate register (a tertiary reload).  */
7657               if (tertiary_icode != CODE_FOR_nothing)
7658                 {
7659                   emit_insn ((GEN_FCN (tertiary_icode)
7660                               (second_reload_reg, real_oldequiv,
7661                                third_reload_reg)));
7662                 }
7663               else if (third_reload_reg)
7664                 {
7665                   gen_reload (third_reload_reg, real_oldequiv,
7666                               rl->opnum,
7667                               rl->when_needed);
7668                   gen_reload (second_reload_reg, third_reload_reg,
7669                               rl->opnum,
7670                               rl->when_needed);
7671                 }
7672               else
7673                 gen_reload (second_reload_reg, real_oldequiv,
7674                             rl->opnum,
7675                             rl->when_needed);
7676
7677               oldequiv = second_reload_reg;
7678             }
7679         }
7680     }
7681
7682   if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7683     {
7684       rtx real_oldequiv = oldequiv;
7685
7686       if ((REG_P (oldequiv)
7687            && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7688            && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7689                || reg_equiv_constant (REGNO (oldequiv)) != 0))
7690           || (GET_CODE (oldequiv) == SUBREG
7691               && REG_P (SUBREG_REG (oldequiv))
7692               && (REGNO (SUBREG_REG (oldequiv))
7693                   >= FIRST_PSEUDO_REGISTER)
7694               && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7695                   || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7696           || (CONSTANT_P (oldequiv)
7697               && (targetm.preferred_reload_class (oldequiv,
7698                                                   REGNO_REG_CLASS (REGNO (reloadreg)))
7699                   == NO_REGS)))
7700         real_oldequiv = rl->in;
7701       gen_reload (reloadreg, real_oldequiv, rl->opnum,
7702                   rl->when_needed);
7703     }
7704
7705   if (cfun->can_throw_non_call_exceptions)
7706     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7707
7708   /* End this sequence.  */
7709   *where = get_insns ();
7710   end_sequence ();
7711
7712   /* Update reload_override_in so that delete_address_reloads_1
7713      can see the actual register usage.  */
7714   if (oldequiv_reg)
7715     reload_override_in[j] = oldequiv;
7716 }
7717
7718 /* Generate insns to for the output reload RL, which is for the insn described
7719    by CHAIN and has the number J.  */
7720 static void
7721 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7722                           int j)
7723 {
7724   rtx reloadreg;
7725   rtx_insn *insn = chain->insn;
7726   int special = 0;
7727   rtx old = rl->out;
7728   machine_mode mode;
7729   rtx_insn *p;
7730   rtx rl_reg_rtx;
7731
7732   if (rl->when_needed == RELOAD_OTHER)
7733     start_sequence ();
7734   else
7735     push_to_sequence (output_reload_insns[rl->opnum]);
7736
7737   rl_reg_rtx = reload_reg_rtx_for_output[j];
7738   mode = GET_MODE (rl_reg_rtx);
7739
7740   reloadreg = rl_reg_rtx;
7741
7742   /* If we need two reload regs, set RELOADREG to the intermediate
7743      one, since it will be stored into OLD.  We might need a secondary
7744      register only for an input reload, so check again here.  */
7745
7746   if (rl->secondary_out_reload >= 0)
7747     {
7748       rtx real_old = old;
7749       int secondary_reload = rl->secondary_out_reload;
7750       int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7751
7752       if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7753           && reg_equiv_mem (REGNO (old)) != 0)
7754         real_old = reg_equiv_mem (REGNO (old));
7755
7756       if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7757         {
7758           rtx second_reloadreg = reloadreg;
7759           reloadreg = rld[secondary_reload].reg_rtx;
7760
7761           /* See if RELOADREG is to be used as a scratch register
7762              or as an intermediate register.  */
7763           if (rl->secondary_out_icode != CODE_FOR_nothing)
7764             {
7765               /* We'd have to add extra code to handle this case.  */
7766               gcc_assert (tertiary_reload < 0);
7767
7768               emit_insn ((GEN_FCN (rl->secondary_out_icode)
7769                           (real_old, second_reloadreg, reloadreg)));
7770               special = 1;
7771             }
7772           else
7773             {
7774               /* See if we need both a scratch and intermediate reload
7775                  register.  */
7776
7777               enum insn_code tertiary_icode
7778                 = rld[secondary_reload].secondary_out_icode;
7779
7780               /* We'd have to add more code for quartary reloads.  */
7781               gcc_assert (tertiary_reload < 0
7782                           || rld[tertiary_reload].secondary_out_reload < 0);
7783
7784               if (GET_MODE (reloadreg) != mode)
7785                 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7786
7787               if (tertiary_icode != CODE_FOR_nothing)
7788                 {
7789                   rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7790
7791                   /* Copy primary reload reg to secondary reload reg.
7792                      (Note that these have been swapped above, then
7793                      secondary reload reg to OLD using our insn.)  */
7794
7795                   /* If REAL_OLD is a paradoxical SUBREG, remove it
7796                      and try to put the opposite SUBREG on
7797                      RELOADREG.  */
7798                   strip_paradoxical_subreg (&real_old, &reloadreg);
7799
7800                   gen_reload (reloadreg, second_reloadreg,
7801                               rl->opnum, rl->when_needed);
7802                   emit_insn ((GEN_FCN (tertiary_icode)
7803                               (real_old, reloadreg, third_reloadreg)));
7804                   special = 1;
7805                 }
7806
7807               else
7808                 {
7809                   /* Copy between the reload regs here and then to
7810                      OUT later.  */
7811
7812                   gen_reload (reloadreg, second_reloadreg,
7813                               rl->opnum, rl->when_needed);
7814                   if (tertiary_reload >= 0)
7815                     {
7816                       rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7817
7818                       gen_reload (third_reloadreg, reloadreg,
7819                                   rl->opnum, rl->when_needed);
7820                       reloadreg = third_reloadreg;
7821                     }
7822                 }
7823             }
7824         }
7825     }
7826
7827   /* Output the last reload insn.  */
7828   if (! special)
7829     {
7830       rtx set;
7831
7832       /* Don't output the last reload if OLD is not the dest of
7833          INSN and is in the src and is clobbered by INSN.  */
7834       if (! flag_expensive_optimizations
7835           || !REG_P (old)
7836           || !(set = single_set (insn))
7837           || rtx_equal_p (old, SET_DEST (set))
7838           || !reg_mentioned_p (old, SET_SRC (set))
7839           || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7840                && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7841         gen_reload (old, reloadreg, rl->opnum,
7842                     rl->when_needed);
7843     }
7844
7845   /* Look at all insns we emitted, just to be safe.  */
7846   for (p = get_insns (); p; p = NEXT_INSN (p))
7847     if (INSN_P (p))
7848       {
7849         rtx pat = PATTERN (p);
7850
7851         /* If this output reload doesn't come from a spill reg,
7852            clear any memory of reloaded copies of the pseudo reg.
7853            If this output reload comes from a spill reg,
7854            reg_has_output_reload will make this do nothing.  */
7855         note_stores (pat, forget_old_reloads_1, NULL);
7856
7857         if (reg_mentioned_p (rl_reg_rtx, pat))
7858           {
7859             rtx set = single_set (insn);
7860             if (reload_spill_index[j] < 0
7861                 && set
7862                 && SET_SRC (set) == rl_reg_rtx)
7863               {
7864                 int src = REGNO (SET_SRC (set));
7865
7866                 reload_spill_index[j] = src;
7867                 SET_HARD_REG_BIT (reg_is_output_reload, src);
7868                 if (find_regno_note (insn, REG_DEAD, src))
7869                   SET_HARD_REG_BIT (reg_reloaded_died, src);
7870               }
7871             if (HARD_REGISTER_P (rl_reg_rtx))
7872               {
7873                 int s = rl->secondary_out_reload;
7874                 set = single_set (p);
7875                 /* If this reload copies only to the secondary reload
7876                    register, the secondary reload does the actual
7877                    store.  */
7878                 if (s >= 0 && set == NULL_RTX)
7879                   /* We can't tell what function the secondary reload
7880                      has and where the actual store to the pseudo is
7881                      made; leave new_spill_reg_store alone.  */
7882                   ;
7883                 else if (s >= 0
7884                          && SET_SRC (set) == rl_reg_rtx
7885                          && SET_DEST (set) == rld[s].reg_rtx)
7886                   {
7887                     /* Usually the next instruction will be the
7888                        secondary reload insn;  if we can confirm
7889                        that it is, setting new_spill_reg_store to
7890                        that insn will allow an extra optimization.  */
7891                     rtx s_reg = rld[s].reg_rtx;
7892                     rtx_insn *next = NEXT_INSN (p);
7893                     rld[s].out = rl->out;
7894                     rld[s].out_reg = rl->out_reg;
7895                     set = single_set (next);
7896                     if (set && SET_SRC (set) == s_reg
7897                         && reload_reg_rtx_reaches_end_p (s_reg, s))
7898                       {
7899                         SET_HARD_REG_BIT (reg_is_output_reload,
7900                                           REGNO (s_reg));
7901                         new_spill_reg_store[REGNO (s_reg)] = next;
7902                       }
7903                   }
7904                 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7905                   new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7906               }
7907           }
7908       }
7909
7910   if (rl->when_needed == RELOAD_OTHER)
7911     {
7912       emit_insn (other_output_reload_insns[rl->opnum]);
7913       other_output_reload_insns[rl->opnum] = get_insns ();
7914     }
7915   else
7916     output_reload_insns[rl->opnum] = get_insns ();
7917
7918   if (cfun->can_throw_non_call_exceptions)
7919     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7920
7921   end_sequence ();
7922 }
7923
7924 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7925    and has the number J.  */
7926 static void
7927 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7928 {
7929   rtx_insn *insn = chain->insn;
7930   rtx old = (rl->in && MEM_P (rl->in)
7931              ? rl->in_reg : rl->in);
7932   rtx reg_rtx = rl->reg_rtx;
7933
7934   if (old && reg_rtx)
7935     {
7936       machine_mode mode;
7937
7938       /* Determine the mode to reload in.
7939          This is very tricky because we have three to choose from.
7940          There is the mode the insn operand wants (rl->inmode).
7941          There is the mode of the reload register RELOADREG.
7942          There is the intrinsic mode of the operand, which we could find
7943          by stripping some SUBREGs.
7944          It turns out that RELOADREG's mode is irrelevant:
7945          we can change that arbitrarily.
7946
7947          Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7948          then the reload reg may not support QImode moves, so use SImode.
7949          If foo is in memory due to spilling a pseudo reg, this is safe,
7950          because the QImode value is in the least significant part of a
7951          slot big enough for a SImode.  If foo is some other sort of
7952          memory reference, then it is impossible to reload this case,
7953          so previous passes had better make sure this never happens.
7954
7955          Then consider a one-word union which has SImode and one of its
7956          members is a float, being fetched as (SUBREG:SF union:SI).
7957          We must fetch that as SFmode because we could be loading into
7958          a float-only register.  In this case OLD's mode is correct.
7959
7960          Consider an immediate integer: it has VOIDmode.  Here we need
7961          to get a mode from something else.
7962
7963          In some cases, there is a fourth mode, the operand's
7964          containing mode.  If the insn specifies a containing mode for
7965          this operand, it overrides all others.
7966
7967          I am not sure whether the algorithm here is always right,
7968          but it does the right things in those cases.  */
7969
7970       mode = GET_MODE (old);
7971       if (mode == VOIDmode)
7972         mode = rl->inmode;
7973
7974       /* We cannot use gen_lowpart_common since it can do the wrong thing
7975          when REG_RTX has a multi-word mode.  Note that REG_RTX must
7976          always be a REG here.  */
7977       if (GET_MODE (reg_rtx) != mode)
7978         reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7979     }
7980   reload_reg_rtx_for_input[j] = reg_rtx;
7981
7982   if (old != 0
7983       /* AUTO_INC reloads need to be handled even if inherited.  We got an
7984          AUTO_INC reload if reload_out is set but reload_out_reg isn't.  */
7985       && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7986       && ! rtx_equal_p (reg_rtx, old)
7987       && reg_rtx != 0)
7988     emit_input_reload_insns (chain, rld + j, old, j);
7989
7990   /* When inheriting a wider reload, we have a MEM in rl->in,
7991      e.g. inheriting a SImode output reload for
7992      (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10)))  */
7993   if (optimize && reload_inherited[j] && rl->in
7994       && MEM_P (rl->in)
7995       && MEM_P (rl->in_reg)
7996       && reload_spill_index[j] >= 0
7997       && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7998     rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7999
8000   /* If we are reloading a register that was recently stored in with an
8001      output-reload, see if we can prove there was
8002      actually no need to store the old value in it.  */
8003
8004   if (optimize
8005       && (reload_inherited[j] || reload_override_in[j])
8006       && reg_rtx
8007       && REG_P (reg_rtx)
8008       && spill_reg_store[REGNO (reg_rtx)] != 0
8009 #if 0
8010       /* There doesn't seem to be any reason to restrict this to pseudos
8011          and doing so loses in the case where we are copying from a
8012          register of the wrong class.  */
8013       && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
8014 #endif
8015       /* The insn might have already some references to stackslots
8016          replaced by MEMs, while reload_out_reg still names the
8017          original pseudo.  */
8018       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
8019           || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
8020     delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
8021 }
8022
8023 /* Do output reloading for reload RL, which is for the insn described by
8024    CHAIN and has the number J.
8025    ??? At some point we need to support handling output reloads of
8026    JUMP_INSNs or insns that set cc0.  */
8027 static void
8028 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
8029 {
8030   rtx note, old;
8031   rtx_insn *insn = chain->insn;
8032   /* If this is an output reload that stores something that is
8033      not loaded in this same reload, see if we can eliminate a previous
8034      store.  */
8035   rtx pseudo = rl->out_reg;
8036   rtx reg_rtx = rl->reg_rtx;
8037
8038   if (rl->out && reg_rtx)
8039     {
8040       machine_mode mode;
8041
8042       /* Determine the mode to reload in.
8043          See comments above (for input reloading).  */
8044       mode = GET_MODE (rl->out);
8045       if (mode == VOIDmode)
8046         {
8047           /* VOIDmode should never happen for an output.  */
8048           if (asm_noperands (PATTERN (insn)) < 0)
8049             /* It's the compiler's fault.  */
8050             fatal_insn ("VOIDmode on an output", insn);
8051           error_for_asm (insn, "output operand is constant in %<asm%>");
8052           /* Prevent crash--use something we know is valid.  */
8053           mode = word_mode;
8054           rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
8055         }
8056       if (GET_MODE (reg_rtx) != mode)
8057         reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
8058     }
8059   reload_reg_rtx_for_output[j] = reg_rtx;
8060
8061   if (pseudo
8062       && optimize
8063       && REG_P (pseudo)
8064       && ! rtx_equal_p (rl->in_reg, pseudo)
8065       && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
8066       && reg_last_reload_reg[REGNO (pseudo)])
8067     {
8068       int pseudo_no = REGNO (pseudo);
8069       int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
8070
8071       /* We don't need to test full validity of last_regno for
8072          inherit here; we only want to know if the store actually
8073          matches the pseudo.  */
8074       if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
8075           && reg_reloaded_contents[last_regno] == pseudo_no
8076           && spill_reg_store[last_regno]
8077           && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
8078         delete_output_reload (insn, j, last_regno, reg_rtx);
8079     }
8080
8081   old = rl->out_reg;
8082   if (old == 0
8083       || reg_rtx == 0
8084       || rtx_equal_p (old, reg_rtx))
8085     return;
8086
8087   /* An output operand that dies right away does need a reload,
8088      but need not be copied from it.  Show the new location in the
8089      REG_UNUSED note.  */
8090   if ((REG_P (old) || GET_CODE (old) == SCRATCH)
8091       && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
8092     {
8093       XEXP (note, 0) = reg_rtx;
8094       return;
8095     }
8096   /* Likewise for a SUBREG of an operand that dies.  */
8097   else if (GET_CODE (old) == SUBREG
8098            && REG_P (SUBREG_REG (old))
8099            && 0 != (note = find_reg_note (insn, REG_UNUSED,
8100                                           SUBREG_REG (old))))
8101     {
8102       XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
8103       return;
8104     }
8105   else if (GET_CODE (old) == SCRATCH)
8106     /* If we aren't optimizing, there won't be a REG_UNUSED note,
8107        but we don't want to make an output reload.  */
8108     return;
8109
8110   /* If is a JUMP_INSN, we can't support output reloads yet.  */
8111   gcc_assert (NONJUMP_INSN_P (insn));
8112
8113   emit_output_reload_insns (chain, rld + j, j);
8114 }
8115
8116 /* A reload copies values of MODE from register SRC to register DEST.
8117    Return true if it can be treated for inheritance purposes like a
8118    group of reloads, each one reloading a single hard register.  The
8119    caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8120    occupy the same number of hard registers.  */
8121
8122 static bool
8123 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8124                      int src ATTRIBUTE_UNUSED,
8125                      machine_mode mode ATTRIBUTE_UNUSED)
8126 {
8127 #ifdef CANNOT_CHANGE_MODE_CLASS
8128   return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8129           && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8130 #else
8131   return true;
8132 #endif
8133 }
8134
8135 /* Output insns to reload values in and out of the chosen reload regs.  */
8136
8137 static void
8138 emit_reload_insns (struct insn_chain *chain)
8139 {
8140   rtx_insn *insn = chain->insn;
8141
8142   int j;
8143
8144   CLEAR_HARD_REG_SET (reg_reloaded_died);
8145
8146   for (j = 0; j < reload_n_operands; j++)
8147     input_reload_insns[j] = input_address_reload_insns[j]
8148       = inpaddr_address_reload_insns[j]
8149       = output_reload_insns[j] = output_address_reload_insns[j]
8150       = outaddr_address_reload_insns[j]
8151       = other_output_reload_insns[j] = 0;
8152   other_input_address_reload_insns = 0;
8153   other_input_reload_insns = 0;
8154   operand_reload_insns = 0;
8155   other_operand_reload_insns = 0;
8156
8157   /* Dump reloads into the dump file.  */
8158   if (dump_file)
8159     {
8160       fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8161       debug_reload_to_stream (dump_file);
8162     }
8163
8164   for (j = 0; j < n_reloads; j++)
8165     if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8166       {
8167         unsigned int i;
8168
8169         for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8170           new_spill_reg_store[i] = 0;
8171       }
8172
8173   /* Now output the instructions to copy the data into and out of the
8174      reload registers.  Do these in the order that the reloads were reported,
8175      since reloads of base and index registers precede reloads of operands
8176      and the operands may need the base and index registers reloaded.  */
8177
8178   for (j = 0; j < n_reloads; j++)
8179     {
8180       do_input_reload (chain, rld + j, j);
8181       do_output_reload (chain, rld + j, j);
8182     }
8183
8184   /* Now write all the insns we made for reloads in the order expected by
8185      the allocation functions.  Prior to the insn being reloaded, we write
8186      the following reloads:
8187
8188      RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8189
8190      RELOAD_OTHER reloads.
8191
8192      For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8193      by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8194      RELOAD_FOR_INPUT reload for the operand.
8195
8196      RELOAD_FOR_OPADDR_ADDRS reloads.
8197
8198      RELOAD_FOR_OPERAND_ADDRESS reloads.
8199
8200      After the insn being reloaded, we write the following:
8201
8202      For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8203      by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8204      RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8205      reloads for the operand.  The RELOAD_OTHER output reloads are
8206      output in descending order by reload number.  */
8207
8208   emit_insn_before (other_input_address_reload_insns, insn);
8209   emit_insn_before (other_input_reload_insns, insn);
8210
8211   for (j = 0; j < reload_n_operands; j++)
8212     {
8213       emit_insn_before (inpaddr_address_reload_insns[j], insn);
8214       emit_insn_before (input_address_reload_insns[j], insn);
8215       emit_insn_before (input_reload_insns[j], insn);
8216     }
8217
8218   emit_insn_before (other_operand_reload_insns, insn);
8219   emit_insn_before (operand_reload_insns, insn);
8220
8221   for (j = 0; j < reload_n_operands; j++)
8222     {
8223       rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8224       x = emit_insn_after (output_address_reload_insns[j], x);
8225       x = emit_insn_after (output_reload_insns[j], x);
8226       emit_insn_after (other_output_reload_insns[j], x);
8227     }
8228
8229   /* For all the spill regs newly reloaded in this instruction,
8230      record what they were reloaded from, so subsequent instructions
8231      can inherit the reloads.
8232
8233      Update spill_reg_store for the reloads of this insn.
8234      Copy the elements that were updated in the loop above.  */
8235
8236   for (j = 0; j < n_reloads; j++)
8237     {
8238       int r = reload_order[j];
8239       int i = reload_spill_index[r];
8240
8241       /* If this is a non-inherited input reload from a pseudo, we must
8242          clear any memory of a previous store to the same pseudo.  Only do
8243          something if there will not be an output reload for the pseudo
8244          being reloaded.  */
8245       if (rld[r].in_reg != 0
8246           && ! (reload_inherited[r] || reload_override_in[r]))
8247         {
8248           rtx reg = rld[r].in_reg;
8249
8250           if (GET_CODE (reg) == SUBREG)
8251             reg = SUBREG_REG (reg);
8252
8253           if (REG_P (reg)
8254               && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8255               && !REGNO_REG_SET_P (&reg_has_output_reload, REGNO (reg)))
8256             {
8257               int nregno = REGNO (reg);
8258
8259               if (reg_last_reload_reg[nregno])
8260                 {
8261                   int last_regno = REGNO (reg_last_reload_reg[nregno]);
8262
8263                   if (reg_reloaded_contents[last_regno] == nregno)
8264                     spill_reg_store[last_regno] = 0;
8265                 }
8266             }
8267         }
8268
8269       /* I is nonneg if this reload used a register.
8270          If rld[r].reg_rtx is 0, this is an optional reload
8271          that we opted to ignore.  */
8272
8273       if (i >= 0 && rld[r].reg_rtx != 0)
8274         {
8275           int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8276           int k;
8277
8278           /* For a multi register reload, we need to check if all or part
8279              of the value lives to the end.  */
8280           for (k = 0; k < nr; k++)
8281             if (reload_reg_reaches_end_p (i + k, r))
8282               CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8283
8284           /* Maybe the spill reg contains a copy of reload_out.  */
8285           if (rld[r].out != 0
8286               && (REG_P (rld[r].out)
8287                   || (rld[r].out_reg
8288                       ? REG_P (rld[r].out_reg)
8289                       /* The reload value is an auto-modification of
8290                          some kind.  For PRE_INC, POST_INC, PRE_DEC
8291                          and POST_DEC, we record an equivalence
8292                          between the reload register and the operand
8293                          on the optimistic assumption that we can make
8294                          the equivalence hold.  reload_as_needed must
8295                          then either make it hold or invalidate the
8296                          equivalence.
8297
8298                          PRE_MODIFY and POST_MODIFY addresses are reloaded
8299                          somewhat differently, and allowing them here leads
8300                          to problems.  */
8301                       : (GET_CODE (rld[r].out) != POST_MODIFY
8302                          && GET_CODE (rld[r].out) != PRE_MODIFY))))
8303             {
8304               rtx reg;
8305
8306               reg = reload_reg_rtx_for_output[r];
8307               if (reload_reg_rtx_reaches_end_p (reg, r))
8308                 {
8309                   machine_mode mode = GET_MODE (reg);
8310                   int regno = REGNO (reg);
8311                   int nregs = hard_regno_nregs[regno][mode];
8312                   rtx out = (REG_P (rld[r].out)
8313                              ? rld[r].out
8314                              : rld[r].out_reg
8315                              ? rld[r].out_reg
8316 /* AUTO_INC */               : XEXP (rld[r].in_reg, 0));
8317                   int out_regno = REGNO (out);
8318                   int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8319                                    : hard_regno_nregs[out_regno][mode]);
8320                   bool piecemeal;
8321
8322                   spill_reg_store[regno] = new_spill_reg_store[regno];
8323                   spill_reg_stored_to[regno] = out;
8324                   reg_last_reload_reg[out_regno] = reg;
8325
8326                   piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8327                                && nregs == out_nregs
8328                                && inherit_piecemeal_p (out_regno, regno, mode));
8329
8330                   /* If OUT_REGNO is a hard register, it may occupy more than
8331                      one register.  If it does, say what is in the
8332                      rest of the registers assuming that both registers
8333                      agree on how many words the object takes.  If not,
8334                      invalidate the subsequent registers.  */
8335
8336                   if (HARD_REGISTER_NUM_P (out_regno))
8337                     for (k = 1; k < out_nregs; k++)
8338                       reg_last_reload_reg[out_regno + k]
8339                         = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8340
8341                   /* Now do the inverse operation.  */
8342                   for (k = 0; k < nregs; k++)
8343                     {
8344                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8345                       reg_reloaded_contents[regno + k]
8346                         = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8347                            ? out_regno
8348                            : out_regno + k);
8349                       reg_reloaded_insn[regno + k] = insn;
8350                       SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8351                       if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8352                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8353                                           regno + k);
8354                       else
8355                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8356                                             regno + k);
8357                     }
8358                 }
8359             }
8360           /* Maybe the spill reg contains a copy of reload_in.  Only do
8361              something if there will not be an output reload for
8362              the register being reloaded.  */
8363           else if (rld[r].out_reg == 0
8364                    && rld[r].in != 0
8365                    && ((REG_P (rld[r].in)
8366                         && !HARD_REGISTER_P (rld[r].in)
8367                         && !REGNO_REG_SET_P (&reg_has_output_reload,
8368                                              REGNO (rld[r].in)))
8369                        || (REG_P (rld[r].in_reg)
8370                            && !REGNO_REG_SET_P (&reg_has_output_reload,
8371                                                 REGNO (rld[r].in_reg))))
8372                    && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8373             {
8374               rtx reg;
8375
8376               reg = reload_reg_rtx_for_input[r];
8377               if (reload_reg_rtx_reaches_end_p (reg, r))
8378                 {
8379                   machine_mode mode;
8380                   int regno;
8381                   int nregs;
8382                   int in_regno;
8383                   int in_nregs;
8384                   rtx in;
8385                   bool piecemeal;
8386
8387                   mode = GET_MODE (reg);
8388                   regno = REGNO (reg);
8389                   nregs = hard_regno_nregs[regno][mode];
8390                   if (REG_P (rld[r].in)
8391                       && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8392                     in = rld[r].in;
8393                   else if (REG_P (rld[r].in_reg))
8394                     in = rld[r].in_reg;
8395                   else
8396                     in = XEXP (rld[r].in_reg, 0);
8397                   in_regno = REGNO (in);
8398
8399                   in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8400                               : hard_regno_nregs[in_regno][mode]);
8401
8402                   reg_last_reload_reg[in_regno] = reg;
8403
8404                   piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8405                                && nregs == in_nregs
8406                                && inherit_piecemeal_p (regno, in_regno, mode));
8407
8408                   if (HARD_REGISTER_NUM_P (in_regno))
8409                     for (k = 1; k < in_nregs; k++)
8410                       reg_last_reload_reg[in_regno + k]
8411                         = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8412
8413                   /* Unless we inherited this reload, show we haven't
8414                      recently done a store.
8415                      Previous stores of inherited auto_inc expressions
8416                      also have to be discarded.  */
8417                   if (! reload_inherited[r]
8418                       || (rld[r].out && ! rld[r].out_reg))
8419                     spill_reg_store[regno] = 0;
8420
8421                   for (k = 0; k < nregs; k++)
8422                     {
8423                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8424                       reg_reloaded_contents[regno + k]
8425                         = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8426                            ? in_regno
8427                            : in_regno + k);
8428                       reg_reloaded_insn[regno + k] = insn;
8429                       SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8430                       if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8431                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8432                                           regno + k);
8433                       else
8434                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8435                                             regno + k);
8436                     }
8437                 }
8438             }
8439         }
8440
8441       /* The following if-statement was #if 0'd in 1.34 (or before...).
8442          It's reenabled in 1.35 because supposedly nothing else
8443          deals with this problem.  */
8444
8445       /* If a register gets output-reloaded from a non-spill register,
8446          that invalidates any previous reloaded copy of it.
8447          But forget_old_reloads_1 won't get to see it, because
8448          it thinks only about the original insn.  So invalidate it here.
8449          Also do the same thing for RELOAD_OTHER constraints where the
8450          output is discarded.  */
8451       if (i < 0
8452           && ((rld[r].out != 0
8453                && (REG_P (rld[r].out)
8454                    || (MEM_P (rld[r].out)
8455                        && REG_P (rld[r].out_reg))))
8456               || (rld[r].out == 0 && rld[r].out_reg
8457                   && REG_P (rld[r].out_reg))))
8458         {
8459           rtx out = ((rld[r].out && REG_P (rld[r].out))
8460                      ? rld[r].out : rld[r].out_reg);
8461           int out_regno = REGNO (out);
8462           machine_mode mode = GET_MODE (out);
8463
8464           /* REG_RTX is now set or clobbered by the main instruction.
8465              As the comment above explains, forget_old_reloads_1 only
8466              sees the original instruction, and there is no guarantee
8467              that the original instruction also clobbered REG_RTX.
8468              For example, if find_reloads sees that the input side of
8469              a matched operand pair dies in this instruction, it may
8470              use the input register as the reload register.
8471
8472              Calling forget_old_reloads_1 is a waste of effort if
8473              REG_RTX is also the output register.
8474
8475              If we know that REG_RTX holds the value of a pseudo
8476              register, the code after the call will record that fact.  */
8477           if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8478             forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8479
8480           if (!HARD_REGISTER_NUM_P (out_regno))
8481             {
8482               rtx src_reg;
8483               rtx_insn *store_insn = NULL;
8484
8485               reg_last_reload_reg[out_regno] = 0;
8486
8487               /* If we can find a hard register that is stored, record
8488                  the storing insn so that we may delete this insn with
8489                  delete_output_reload.  */
8490               src_reg = reload_reg_rtx_for_output[r];
8491
8492               if (src_reg)
8493                 {
8494                   if (reload_reg_rtx_reaches_end_p (src_reg, r))
8495                     store_insn = new_spill_reg_store[REGNO (src_reg)];
8496                   else
8497                     src_reg = NULL_RTX;
8498                 }
8499               else
8500                 {
8501                   /* If this is an optional reload, try to find the
8502                      source reg from an input reload.  */
8503                   rtx set = single_set (insn);
8504                   if (set && SET_DEST (set) == rld[r].out)
8505                     {
8506                       int k;
8507
8508                       src_reg = SET_SRC (set);
8509                       store_insn = insn;
8510                       for (k = 0; k < n_reloads; k++)
8511                         {
8512                           if (rld[k].in == src_reg)
8513                             {
8514                               src_reg = reload_reg_rtx_for_input[k];
8515                               break;
8516                             }
8517                         }
8518                     }
8519                 }
8520               if (src_reg && REG_P (src_reg)
8521                   && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8522                 {
8523                   int src_regno, src_nregs, k;
8524                   rtx note;
8525
8526                   gcc_assert (GET_MODE (src_reg) == mode);
8527                   src_regno = REGNO (src_reg);
8528                   src_nregs = hard_regno_nregs[src_regno][mode];
8529                   /* The place where to find a death note varies with
8530                      PRESERVE_DEATH_INFO_REGNO_P .  The condition is not
8531                      necessarily checked exactly in the code that moves
8532                      notes, so just check both locations.  */
8533                   note = find_regno_note (insn, REG_DEAD, src_regno);
8534                   if (! note && store_insn)
8535                     note = find_regno_note (store_insn, REG_DEAD, src_regno);
8536                   for (k = 0; k < src_nregs; k++)
8537                     {
8538                       spill_reg_store[src_regno + k] = store_insn;
8539                       spill_reg_stored_to[src_regno + k] = out;
8540                       reg_reloaded_contents[src_regno + k] = out_regno;
8541                       reg_reloaded_insn[src_regno + k] = store_insn;
8542                       CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8543                       SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8544                       if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8545                                                           mode))
8546                         SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8547                                           src_regno + k);
8548                       else
8549                         CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8550                                             src_regno + k);
8551                       SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8552                       if (note)
8553                         SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8554                       else
8555                         CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8556                     }
8557                   reg_last_reload_reg[out_regno] = src_reg;
8558                   /* We have to set reg_has_output_reload here, or else
8559                      forget_old_reloads_1 will clear reg_last_reload_reg
8560                      right away.  */
8561                   SET_REGNO_REG_SET (&reg_has_output_reload,
8562                                      out_regno);
8563                 }
8564             }
8565           else
8566             {
8567               int k, out_nregs = hard_regno_nregs[out_regno][mode];
8568
8569               for (k = 0; k < out_nregs; k++)
8570                 reg_last_reload_reg[out_regno + k] = 0;
8571             }
8572         }
8573     }
8574   IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8575 }
8576 \f
8577 /* Go through the motions to emit INSN and test if it is strictly valid.
8578    Return the emitted insn if valid, else return NULL.  */
8579
8580 static rtx_insn *
8581 emit_insn_if_valid_for_reload (rtx pat)
8582 {
8583   rtx_insn *last = get_last_insn ();
8584   int code;
8585
8586   rtx_insn *insn = emit_insn (pat);
8587   code = recog_memoized (insn);
8588
8589   if (code >= 0)
8590     {
8591       extract_insn (insn);
8592       /* We want constrain operands to treat this insn strictly in its
8593          validity determination, i.e., the way it would after reload has
8594          completed.  */
8595       if (constrain_operands (1, get_enabled_alternatives (insn)))
8596         return insn;
8597     }
8598
8599   delete_insns_since (last);
8600   return NULL;
8601 }
8602
8603 /* Emit code to perform a reload from IN (which may be a reload register) to
8604    OUT (which may also be a reload register).  IN or OUT is from operand
8605    OPNUM with reload type TYPE.
8606
8607    Returns first insn emitted.  */
8608
8609 static rtx_insn *
8610 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8611 {
8612   rtx_insn *last = get_last_insn ();
8613   rtx_insn *tem;
8614 #ifdef SECONDARY_MEMORY_NEEDED
8615   rtx tem1, tem2;
8616 #endif
8617
8618   /* If IN is a paradoxical SUBREG, remove it and try to put the
8619      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
8620   if (!strip_paradoxical_subreg (&in, &out))
8621     strip_paradoxical_subreg (&out, &in);
8622
8623   /* How to do this reload can get quite tricky.  Normally, we are being
8624      asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8625      register that didn't get a hard register.  In that case we can just
8626      call emit_move_insn.
8627
8628      We can also be asked to reload a PLUS that adds a register or a MEM to
8629      another register, constant or MEM.  This can occur during frame pointer
8630      elimination and while reloading addresses.  This case is handled by
8631      trying to emit a single insn to perform the add.  If it is not valid,
8632      we use a two insn sequence.
8633
8634      Or we can be asked to reload an unary operand that was a fragment of
8635      an addressing mode, into a register.  If it isn't recognized as-is,
8636      we try making the unop operand and the reload-register the same:
8637      (set reg:X (unop:X expr:Y))
8638      -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8639
8640      Finally, we could be called to handle an 'o' constraint by putting
8641      an address into a register.  In that case, we first try to do this
8642      with a named pattern of "reload_load_address".  If no such pattern
8643      exists, we just emit a SET insn and hope for the best (it will normally
8644      be valid on machines that use 'o').
8645
8646      This entire process is made complex because reload will never
8647      process the insns we generate here and so we must ensure that
8648      they will fit their constraints and also by the fact that parts of
8649      IN might be being reloaded separately and replaced with spill registers.
8650      Because of this, we are, in some sense, just guessing the right approach
8651      here.  The one listed above seems to work.
8652
8653      ??? At some point, this whole thing needs to be rethought.  */
8654
8655   if (GET_CODE (in) == PLUS
8656       && (REG_P (XEXP (in, 0))
8657           || GET_CODE (XEXP (in, 0)) == SUBREG
8658           || MEM_P (XEXP (in, 0)))
8659       && (REG_P (XEXP (in, 1))
8660           || GET_CODE (XEXP (in, 1)) == SUBREG
8661           || CONSTANT_P (XEXP (in, 1))
8662           || MEM_P (XEXP (in, 1))))
8663     {
8664       /* We need to compute the sum of a register or a MEM and another
8665          register, constant, or MEM, and put it into the reload
8666          register.  The best possible way of doing this is if the machine
8667          has a three-operand ADD insn that accepts the required operands.
8668
8669          The simplest approach is to try to generate such an insn and see if it
8670          is recognized and matches its constraints.  If so, it can be used.
8671
8672          It might be better not to actually emit the insn unless it is valid,
8673          but we need to pass the insn as an operand to `recog' and
8674          `extract_insn' and it is simpler to emit and then delete the insn if
8675          not valid than to dummy things up.  */
8676
8677       rtx op0, op1, tem;
8678       rtx_insn *insn;
8679       enum insn_code code;
8680
8681       op0 = find_replacement (&XEXP (in, 0));
8682       op1 = find_replacement (&XEXP (in, 1));
8683
8684       /* Since constraint checking is strict, commutativity won't be
8685          checked, so we need to do that here to avoid spurious failure
8686          if the add instruction is two-address and the second operand
8687          of the add is the same as the reload reg, which is frequently
8688          the case.  If the insn would be A = B + A, rearrange it so
8689          it will be A = A + B as constrain_operands expects.  */
8690
8691       if (REG_P (XEXP (in, 1))
8692           && REGNO (out) == REGNO (XEXP (in, 1)))
8693         tem = op0, op0 = op1, op1 = tem;
8694
8695       if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8696         in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8697
8698       insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8699       if (insn)
8700         return insn;
8701
8702       /* If that failed, we must use a conservative two-insn sequence.
8703
8704          Use a move to copy one operand into the reload register.  Prefer
8705          to reload a constant, MEM or pseudo since the move patterns can
8706          handle an arbitrary operand.  If OP1 is not a constant, MEM or
8707          pseudo and OP1 is not a valid operand for an add instruction, then
8708          reload OP1.
8709
8710          After reloading one of the operands into the reload register, add
8711          the reload register to the output register.
8712
8713          If there is another way to do this for a specific machine, a
8714          DEFINE_PEEPHOLE should be specified that recognizes the sequence
8715          we emit below.  */
8716
8717       code = optab_handler (add_optab, GET_MODE (out));
8718
8719       if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8720           || (REG_P (op1)
8721               && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8722           || (code != CODE_FOR_nothing
8723               && !insn_operand_matches (code, 2, op1)))
8724         tem = op0, op0 = op1, op1 = tem;
8725
8726       gen_reload (out, op0, opnum, type);
8727
8728       /* If OP0 and OP1 are the same, we can use OUT for OP1.
8729          This fixes a problem on the 32K where the stack pointer cannot
8730          be used as an operand of an add insn.  */
8731
8732       if (rtx_equal_p (op0, op1))
8733         op1 = out;
8734
8735       insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8736       if (insn)
8737         {
8738           /* Add a REG_EQUIV note so that find_equiv_reg can find it.  */
8739           set_dst_reg_note (insn, REG_EQUIV, in, out);
8740           return insn;
8741         }
8742
8743       /* If that failed, copy the address register to the reload register.
8744          Then add the constant to the reload register.  */
8745
8746       gcc_assert (!reg_overlap_mentioned_p (out, op0));
8747       gen_reload (out, op1, opnum, type);
8748       insn = emit_insn (gen_add2_insn (out, op0));
8749       set_dst_reg_note (insn, REG_EQUIV, in, out);
8750     }
8751
8752 #ifdef SECONDARY_MEMORY_NEEDED
8753   /* If we need a memory location to do the move, do it that way.  */
8754   else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8755             (REG_P (tem1) && REG_P (tem2)))
8756            && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8757            && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8758            && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1)),
8759                                        REGNO_REG_CLASS (REGNO (tem2)),
8760                                        GET_MODE (out)))
8761     {
8762       /* Get the memory to use and rewrite both registers to its mode.  */
8763       rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8764
8765       if (GET_MODE (loc) != GET_MODE (out))
8766         out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8767
8768       if (GET_MODE (loc) != GET_MODE (in))
8769         in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8770
8771       gen_reload (loc, in, opnum, type);
8772       gen_reload (out, loc, opnum, type);
8773     }
8774 #endif
8775   else if (REG_P (out) && UNARY_P (in))
8776     {
8777       rtx insn;
8778       rtx op1;
8779       rtx out_moded;
8780       rtx_insn *set;
8781
8782       op1 = find_replacement (&XEXP (in, 0));
8783       if (op1 != XEXP (in, 0))
8784         in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8785
8786       /* First, try a plain SET.  */
8787       set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8788       if (set)
8789         return set;
8790
8791       /* If that failed, move the inner operand to the reload
8792          register, and try the same unop with the inner expression
8793          replaced with the reload register.  */
8794
8795       if (GET_MODE (op1) != GET_MODE (out))
8796         out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8797       else
8798         out_moded = out;
8799
8800       gen_reload (out_moded, op1, opnum, type);
8801
8802       insn = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8803                                               out_moded));
8804       insn = emit_insn_if_valid_for_reload (insn);
8805       if (insn)
8806         {
8807           set_unique_reg_note (insn, REG_EQUIV, in);
8808           return as_a <rtx_insn *> (insn);
8809         }
8810
8811       fatal_insn ("failure trying to reload:", set);
8812     }
8813   /* If IN is a simple operand, use gen_move_insn.  */
8814   else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8815     {
8816       tem = emit_insn (gen_move_insn (out, in));
8817       /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note.  */
8818       mark_jump_label (in, tem, 0);
8819     }
8820
8821 #ifdef HAVE_reload_load_address
8822   else if (HAVE_reload_load_address)
8823     emit_insn (gen_reload_load_address (out, in));
8824 #endif
8825
8826   /* Otherwise, just write (set OUT IN) and hope for the best.  */
8827   else
8828     emit_insn (gen_rtx_SET (out, in));
8829
8830   /* Return the first insn emitted.
8831      We can not just return get_last_insn, because there may have
8832      been multiple instructions emitted.  Also note that gen_move_insn may
8833      emit more than one insn itself, so we can not assume that there is one
8834      insn emitted per emit_insn_before call.  */
8835
8836   return last ? NEXT_INSN (last) : get_insns ();
8837 }
8838 \f
8839 /* Delete a previously made output-reload whose result we now believe
8840    is not needed.  First we double-check.
8841
8842    INSN is the insn now being processed.
8843    LAST_RELOAD_REG is the hard register number for which we want to delete
8844    the last output reload.
8845    J is the reload-number that originally used REG.  The caller has made
8846    certain that reload J doesn't use REG any longer for input.
8847    NEW_RELOAD_REG is reload register that reload J is using for REG.  */
8848
8849 static void
8850 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8851                       rtx new_reload_reg)
8852 {
8853   rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8854   rtx reg = spill_reg_stored_to[last_reload_reg];
8855   int k;
8856   int n_occurrences;
8857   int n_inherited = 0;
8858   rtx substed;
8859   unsigned regno;
8860   int nregs;
8861
8862   /* It is possible that this reload has been only used to set another reload
8863      we eliminated earlier and thus deleted this instruction too.  */
8864   if (output_reload_insn->deleted ())
8865     return;
8866
8867   /* Get the raw pseudo-register referred to.  */
8868
8869   while (GET_CODE (reg) == SUBREG)
8870     reg = SUBREG_REG (reg);
8871   substed = reg_equiv_memory_loc (REGNO (reg));
8872
8873   /* This is unsafe if the operand occurs more often in the current
8874      insn than it is inherited.  */
8875   for (k = n_reloads - 1; k >= 0; k--)
8876     {
8877       rtx reg2 = rld[k].in;
8878       if (! reg2)
8879         continue;
8880       if (MEM_P (reg2) || reload_override_in[k])
8881         reg2 = rld[k].in_reg;
8882 #ifdef AUTO_INC_DEC
8883       if (rld[k].out && ! rld[k].out_reg)
8884         reg2 = XEXP (rld[k].in_reg, 0);
8885 #endif
8886       while (GET_CODE (reg2) == SUBREG)
8887         reg2 = SUBREG_REG (reg2);
8888       if (rtx_equal_p (reg2, reg))
8889         {
8890           if (reload_inherited[k] || reload_override_in[k] || k == j)
8891             n_inherited++;
8892           else
8893             return;
8894         }
8895     }
8896   n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8897   if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8898     n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8899                                         reg, 0);
8900   if (substed)
8901     n_occurrences += count_occurrences (PATTERN (insn),
8902                                         eliminate_regs (substed, VOIDmode,
8903                                                         NULL_RTX), 0);
8904   for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8905     {
8906       gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8907       n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8908     }
8909   if (n_occurrences > n_inherited)
8910     return;
8911
8912   regno = REGNO (reg);
8913   if (regno >= FIRST_PSEUDO_REGISTER)
8914     nregs = 1;
8915   else
8916     nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8917
8918   /* If the pseudo-reg we are reloading is no longer referenced
8919      anywhere between the store into it and here,
8920      and we're within the same basic block, then the value can only
8921      pass through the reload reg and end up here.
8922      Otherwise, give up--return.  */
8923   for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8924        i1 != insn; i1 = NEXT_INSN (i1))
8925     {
8926       if (NOTE_INSN_BASIC_BLOCK_P (i1))
8927         return;
8928       if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8929           && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8930         {
8931           /* If this is USE in front of INSN, we only have to check that
8932              there are no more references than accounted for by inheritance.  */
8933           while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8934             {
8935               n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8936               i1 = NEXT_INSN (i1);
8937             }
8938           if (n_occurrences <= n_inherited && i1 == insn)
8939             break;
8940           return;
8941         }
8942     }
8943
8944   /* We will be deleting the insn.  Remove the spill reg information.  */
8945   for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8946     {
8947       spill_reg_store[last_reload_reg + k] = 0;
8948       spill_reg_stored_to[last_reload_reg + k] = 0;
8949     }
8950
8951   /* The caller has already checked that REG dies or is set in INSN.
8952      It has also checked that we are optimizing, and thus some
8953      inaccuracies in the debugging information are acceptable.
8954      So we could just delete output_reload_insn.  But in some cases
8955      we can improve the debugging information without sacrificing
8956      optimization - maybe even improving the code: See if the pseudo
8957      reg has been completely replaced with reload regs.  If so, delete
8958      the store insn and forget we had a stack slot for the pseudo.  */
8959   if (rld[j].out != rld[j].in
8960       && REG_N_DEATHS (REGNO (reg)) == 1
8961       && REG_N_SETS (REGNO (reg)) == 1
8962       && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8963       && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8964     {
8965       rtx_insn *i2;
8966
8967       /* We know that it was used only between here and the beginning of
8968          the current basic block.  (We also know that the last use before
8969          INSN was the output reload we are thinking of deleting, but never
8970          mind that.)  Search that range; see if any ref remains.  */
8971       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8972         {
8973           rtx set = single_set (i2);
8974
8975           /* Uses which just store in the pseudo don't count,
8976              since if they are the only uses, they are dead.  */
8977           if (set != 0 && SET_DEST (set) == reg)
8978             continue;
8979           if (LABEL_P (i2) || JUMP_P (i2))
8980             break;
8981           if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8982               && reg_mentioned_p (reg, PATTERN (i2)))
8983             {
8984               /* Some other ref remains; just delete the output reload we
8985                  know to be dead.  */
8986               delete_address_reloads (output_reload_insn, insn);
8987               delete_insn (output_reload_insn);
8988               return;
8989             }
8990         }
8991
8992       /* Delete the now-dead stores into this pseudo.  Note that this
8993          loop also takes care of deleting output_reload_insn.  */
8994       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8995         {
8996           rtx set = single_set (i2);
8997
8998           if (set != 0 && SET_DEST (set) == reg)
8999             {
9000               delete_address_reloads (i2, insn);
9001               delete_insn (i2);
9002             }
9003           if (LABEL_P (i2) || JUMP_P (i2))
9004             break;
9005         }
9006
9007       /* For the debugging info, say the pseudo lives in this reload reg.  */
9008       reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
9009       if (ira_conflicts_p)
9010         /* Inform IRA about the change.  */
9011         ira_mark_allocation_change (REGNO (reg));
9012       alter_reg (REGNO (reg), -1, false);
9013     }
9014   else
9015     {
9016       delete_address_reloads (output_reload_insn, insn);
9017       delete_insn (output_reload_insn);
9018     }
9019 }
9020
9021 /* We are going to delete DEAD_INSN.  Recursively delete loads of
9022    reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
9023    CURRENT_INSN is being reloaded, so we have to check its reloads too.  */
9024 static void
9025 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
9026 {
9027   rtx set = single_set (dead_insn);
9028   rtx set2, dst;
9029   rtx_insn *prev, *next;
9030   if (set)
9031     {
9032       rtx dst = SET_DEST (set);
9033       if (MEM_P (dst))
9034         delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
9035     }
9036   /* If we deleted the store from a reloaded post_{in,de}c expression,
9037      we can delete the matching adds.  */
9038   prev = PREV_INSN (dead_insn);
9039   next = NEXT_INSN (dead_insn);
9040   if (! prev || ! next)
9041     return;
9042   set = single_set (next);
9043   set2 = single_set (prev);
9044   if (! set || ! set2
9045       || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
9046       || !CONST_INT_P (XEXP (SET_SRC (set), 1))
9047       || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
9048     return;
9049   dst = SET_DEST (set);
9050   if (! rtx_equal_p (dst, SET_DEST (set2))
9051       || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
9052       || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
9053       || (INTVAL (XEXP (SET_SRC (set), 1))
9054           != -INTVAL (XEXP (SET_SRC (set2), 1))))
9055     return;
9056   delete_related_insns (prev);
9057   delete_related_insns (next);
9058 }
9059
9060 /* Subfunction of delete_address_reloads: process registers found in X.  */
9061 static void
9062 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
9063 {
9064   rtx_insn *prev, *i2;
9065   rtx set, dst;
9066   int i, j;
9067   enum rtx_code code = GET_CODE (x);
9068
9069   if (code != REG)
9070     {
9071       const char *fmt = GET_RTX_FORMAT (code);
9072       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9073         {
9074           if (fmt[i] == 'e')
9075             delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
9076           else if (fmt[i] == 'E')
9077             {
9078               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9079                 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
9080                                           current_insn);
9081             }
9082         }
9083       return;
9084     }
9085
9086   if (spill_reg_order[REGNO (x)] < 0)
9087     return;
9088
9089   /* Scan backwards for the insn that sets x.  This might be a way back due
9090      to inheritance.  */
9091   for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
9092     {
9093       code = GET_CODE (prev);
9094       if (code == CODE_LABEL || code == JUMP_INSN)
9095         return;
9096       if (!INSN_P (prev))
9097         continue;
9098       if (reg_set_p (x, PATTERN (prev)))
9099         break;
9100       if (reg_referenced_p (x, PATTERN (prev)))
9101         return;
9102     }
9103   if (! prev || INSN_UID (prev) < reload_first_uid)
9104     return;
9105   /* Check that PREV only sets the reload register.  */
9106   set = single_set (prev);
9107   if (! set)
9108     return;
9109   dst = SET_DEST (set);
9110   if (!REG_P (dst)
9111       || ! rtx_equal_p (dst, x))
9112     return;
9113   if (! reg_set_p (dst, PATTERN (dead_insn)))
9114     {
9115       /* Check if DST was used in a later insn -
9116          it might have been inherited.  */
9117       for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9118         {
9119           if (LABEL_P (i2))
9120             break;
9121           if (! INSN_P (i2))
9122             continue;
9123           if (reg_referenced_p (dst, PATTERN (i2)))
9124             {
9125               /* If there is a reference to the register in the current insn,
9126                  it might be loaded in a non-inherited reload.  If no other
9127                  reload uses it, that means the register is set before
9128                  referenced.  */
9129               if (i2 == current_insn)
9130                 {
9131                   for (j = n_reloads - 1; j >= 0; j--)
9132                     if ((rld[j].reg_rtx == dst && reload_inherited[j])
9133                         || reload_override_in[j] == dst)
9134                       return;
9135                   for (j = n_reloads - 1; j >= 0; j--)
9136                     if (rld[j].in && rld[j].reg_rtx == dst)
9137                       break;
9138                   if (j >= 0)
9139                     break;
9140                 }
9141               return;
9142             }
9143           if (JUMP_P (i2))
9144             break;
9145           /* If DST is still live at CURRENT_INSN, check if it is used for
9146              any reload.  Note that even if CURRENT_INSN sets DST, we still
9147              have to check the reloads.  */
9148           if (i2 == current_insn)
9149             {
9150               for (j = n_reloads - 1; j >= 0; j--)
9151                 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9152                     || reload_override_in[j] == dst)
9153                   return;
9154               /* ??? We can't finish the loop here, because dst might be
9155                  allocated to a pseudo in this block if no reload in this
9156                  block needs any of the classes containing DST - see
9157                  spill_hard_reg.  There is no easy way to tell this, so we
9158                  have to scan till the end of the basic block.  */
9159             }
9160           if (reg_set_p (dst, PATTERN (i2)))
9161             break;
9162         }
9163     }
9164   delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9165   reg_reloaded_contents[REGNO (dst)] = -1;
9166   delete_insn (prev);
9167 }
9168 \f
9169 /* Output reload-insns to reload VALUE into RELOADREG.
9170    VALUE is an autoincrement or autodecrement RTX whose operand
9171    is a register or memory location;
9172    so reloading involves incrementing that location.
9173    IN is either identical to VALUE, or some cheaper place to reload from.
9174
9175    INC_AMOUNT is the number to increment or decrement by (always positive).
9176    This cannot be deduced from VALUE.  */
9177
9178 static void
9179 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9180 {
9181   /* REG or MEM to be copied and incremented.  */
9182   rtx incloc = find_replacement (&XEXP (value, 0));
9183   /* Nonzero if increment after copying.  */
9184   int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9185               || GET_CODE (value) == POST_MODIFY);
9186   rtx_insn *last;
9187   rtx inc;
9188   rtx_insn *add_insn;
9189   int code;
9190   rtx real_in = in == value ? incloc : in;
9191
9192   /* No hard register is equivalent to this register after
9193      inc/dec operation.  If REG_LAST_RELOAD_REG were nonzero,
9194      we could inc/dec that register as well (maybe even using it for
9195      the source), but I'm not sure it's worth worrying about.  */
9196   if (REG_P (incloc))
9197     reg_last_reload_reg[REGNO (incloc)] = 0;
9198
9199   if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9200     {
9201       gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9202       inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9203     }
9204   else
9205     {
9206       if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9207         inc_amount = -inc_amount;
9208
9209       inc = GEN_INT (inc_amount);
9210     }
9211
9212   /* If this is post-increment, first copy the location to the reload reg.  */
9213   if (post && real_in != reloadreg)
9214     emit_insn (gen_move_insn (reloadreg, real_in));
9215
9216   if (in == value)
9217     {
9218       /* See if we can directly increment INCLOC.  Use a method similar to
9219          that in gen_reload.  */
9220
9221       last = get_last_insn ();
9222       add_insn = emit_insn (gen_rtx_SET (incloc,
9223                                          gen_rtx_PLUS (GET_MODE (incloc),
9224                                                        incloc, inc)));
9225
9226       code = recog_memoized (add_insn);
9227       if (code >= 0)
9228         {
9229           extract_insn (add_insn);
9230           if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9231             {
9232               /* If this is a pre-increment and we have incremented the value
9233                  where it lives, copy the incremented value to RELOADREG to
9234                  be used as an address.  */
9235
9236               if (! post)
9237                 emit_insn (gen_move_insn (reloadreg, incloc));
9238               return;
9239             }
9240         }
9241       delete_insns_since (last);
9242     }
9243
9244   /* If couldn't do the increment directly, must increment in RELOADREG.
9245      The way we do this depends on whether this is pre- or post-increment.
9246      For pre-increment, copy INCLOC to the reload register, increment it
9247      there, then save back.  */
9248
9249   if (! post)
9250     {
9251       if (in != reloadreg)
9252         emit_insn (gen_move_insn (reloadreg, real_in));
9253       emit_insn (gen_add2_insn (reloadreg, inc));
9254       emit_insn (gen_move_insn (incloc, reloadreg));
9255     }
9256   else
9257     {
9258       /* Postincrement.
9259          Because this might be a jump insn or a compare, and because RELOADREG
9260          may not be available after the insn in an input reload, we must do
9261          the incrementation before the insn being reloaded for.
9262
9263          We have already copied IN to RELOADREG.  Increment the copy in
9264          RELOADREG, save that back, then decrement RELOADREG so it has
9265          the original value.  */
9266
9267       emit_insn (gen_add2_insn (reloadreg, inc));
9268       emit_insn (gen_move_insn (incloc, reloadreg));
9269       if (CONST_INT_P (inc))
9270         emit_insn (gen_add2_insn (reloadreg,
9271                                   gen_int_mode (-INTVAL (inc),
9272                                                 GET_MODE (reloadreg))));
9273       else
9274         emit_insn (gen_sub2_insn (reloadreg, inc));
9275     }
9276 }
9277 \f
9278 #ifdef AUTO_INC_DEC
9279 static void
9280 add_auto_inc_notes (rtx_insn *insn, rtx x)
9281 {
9282   enum rtx_code code = GET_CODE (x);
9283   const char *fmt;
9284   int i, j;
9285
9286   if (code == MEM && auto_inc_p (XEXP (x, 0)))
9287     {
9288       add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9289       return;
9290     }
9291
9292   /* Scan all the operand sub-expressions.  */
9293   fmt = GET_RTX_FORMAT (code);
9294   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9295     {
9296       if (fmt[i] == 'e')
9297         add_auto_inc_notes (insn, XEXP (x, i));
9298       else if (fmt[i] == 'E')
9299         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9300           add_auto_inc_notes (insn, XVECEXP (x, i, j));
9301     }
9302 }
9303 #endif