1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "hard-reg-set.h"
33 #include "insn-config.h"
44 #include "dominance.h"
46 #include "basic-block.h"
48 #include "addresses.h"
51 #include "diagnostic-core.h"
56 /* The flags is set up every time when we calculate pseudo register
57 classes through function ira_set_pseudo_classes. */
58 static bool pseudo_classes_defined_p
= false;
60 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
61 static bool allocno_p
;
63 /* Number of elements in array `costs'. */
64 static int cost_elements_num
;
66 /* The `costs' struct records the cost of using hard registers of each
67 class considered for the calculation and of using memory for each
72 /* Costs for register classes start here. We process only some
77 #define max_struct_costs_size \
78 (this_target_ira_int->x_max_struct_costs_size)
80 (this_target_ira_int->x_init_cost)
82 (this_target_ira_int->x_temp_costs)
84 (this_target_ira_int->x_op_costs)
85 #define this_op_costs \
86 (this_target_ira_int->x_this_op_costs)
88 /* Costs of each class for each allocno or pseudo. */
89 static struct costs
*costs
;
91 /* Accumulated costs of each class for each allocno. */
92 static struct costs
*total_allocno_costs
;
94 /* It is the current size of struct costs. */
95 static int struct_costs_size
;
97 /* Return pointer to structure containing costs of allocno or pseudo
98 with given NUM in array ARR. */
99 #define COSTS(arr, num) \
100 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
102 /* Return index in COSTS when processing reg with REGNO. */
103 #define COST_INDEX(regno) (allocno_p \
104 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
107 /* Record register class preferences of each allocno or pseudo. Null
108 value means no preferences. It happens on the 1st iteration of the
110 static enum reg_class
*pref
;
112 /* Allocated buffers for pref. */
113 static enum reg_class
*pref_buffer
;
115 /* Record allocno class of each allocno with the same regno. */
116 static enum reg_class
*regno_aclass
;
118 /* Record cost gains for not allocating a register with an invariant
120 static int *regno_equiv_gains
;
122 /* Execution frequency of the current insn. */
123 static int frequency
;
127 /* Info about reg classes whose costs are calculated for a pseudo. */
130 /* Number of the cost classes in the subsequent array. */
132 /* Container of the cost classes. */
133 enum reg_class classes
[N_REG_CLASSES
];
134 /* Map reg class -> index of the reg class in the previous array.
135 -1 if it is not a cost class. */
136 int index
[N_REG_CLASSES
];
137 /* Map hard regno index of first class in array CLASSES containing
138 the hard regno, -1 otherwise. */
139 int hard_regno_index
[FIRST_PSEUDO_REGISTER
];
142 /* Types of pointers to the structure above. */
143 typedef struct cost_classes
*cost_classes_t
;
144 typedef const struct cost_classes
*const_cost_classes_t
;
146 /* Info about cost classes for each pseudo. */
147 static cost_classes_t
*regno_cost_classes
;
149 /* Helper for cost_classes hashing. */
151 struct cost_classes_hasher
153 typedef cost_classes
*value_type
;
154 typedef cost_classes
*compare_type
;
155 static inline hashval_t
hash (const cost_classes
*);
156 static inline bool equal (const cost_classes
*, const cost_classes
*);
157 static inline void remove (cost_classes
*);
160 /* Returns hash value for cost classes info HV. */
162 cost_classes_hasher::hash (const cost_classes
*hv
)
164 return iterative_hash (&hv
->classes
, sizeof (enum reg_class
) * hv
->num
, 0);
167 /* Compares cost classes info HV1 and HV2. */
169 cost_classes_hasher::equal (const cost_classes
*hv1
, const cost_classes
*hv2
)
171 return (hv1
->num
== hv2
->num
172 && memcmp (hv1
->classes
, hv2
->classes
,
173 sizeof (enum reg_class
) * hv1
->num
) == 0);
176 /* Delete cost classes info V from the hash table. */
178 cost_classes_hasher::remove (cost_classes
*v
)
183 /* Hash table of unique cost classes. */
184 static hash_table
<cost_classes_hasher
> *cost_classes_htab
;
186 /* Map allocno class -> cost classes for pseudo of given allocno
188 static cost_classes_t cost_classes_aclass_cache
[N_REG_CLASSES
];
190 /* Map mode -> cost classes for pseudo of give mode. */
191 static cost_classes_t cost_classes_mode_cache
[MAX_MACHINE_MODE
];
193 /* Cost classes that include all classes in ira_important_classes. */
194 static cost_classes all_cost_classes
;
196 /* Use the array of classes in CLASSES_PTR to fill out the rest of
199 complete_cost_classes (cost_classes_t classes_ptr
)
201 for (int i
= 0; i
< N_REG_CLASSES
; i
++)
202 classes_ptr
->index
[i
] = -1;
203 for (int i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
204 classes_ptr
->hard_regno_index
[i
] = -1;
205 for (int i
= 0; i
< classes_ptr
->num
; i
++)
207 enum reg_class cl
= classes_ptr
->classes
[i
];
208 classes_ptr
->index
[cl
] = i
;
209 for (int j
= ira_class_hard_regs_num
[cl
] - 1; j
>= 0; j
--)
211 unsigned int hard_regno
= ira_class_hard_regs
[cl
][j
];
212 if (classes_ptr
->hard_regno_index
[hard_regno
] < 0)
213 classes_ptr
->hard_regno_index
[hard_regno
] = i
;
218 /* Initialize info about the cost classes for each pseudo. */
220 initiate_regno_cost_classes (void)
222 int size
= sizeof (cost_classes_t
) * max_reg_num ();
224 regno_cost_classes
= (cost_classes_t
*) ira_allocate (size
);
225 memset (regno_cost_classes
, 0, size
);
226 memset (cost_classes_aclass_cache
, 0,
227 sizeof (cost_classes_t
) * N_REG_CLASSES
);
228 memset (cost_classes_mode_cache
, 0,
229 sizeof (cost_classes_t
) * MAX_MACHINE_MODE
);
230 cost_classes_htab
= new hash_table
<cost_classes_hasher
> (200);
231 all_cost_classes
.num
= ira_important_classes_num
;
232 for (int i
= 0; i
< ira_important_classes_num
; i
++)
233 all_cost_classes
.classes
[i
] = ira_important_classes
[i
];
234 complete_cost_classes (&all_cost_classes
);
237 /* Create new cost classes from cost classes FROM and set up members
238 index and hard_regno_index. Return the new classes. The function
239 implements some common code of two functions
240 setup_regno_cost_classes_by_aclass and
241 setup_regno_cost_classes_by_mode. */
242 static cost_classes_t
243 setup_cost_classes (cost_classes_t from
)
245 cost_classes_t classes_ptr
;
247 classes_ptr
= (cost_classes_t
) ira_allocate (sizeof (struct cost_classes
));
248 classes_ptr
->num
= from
->num
;
249 for (int i
= 0; i
< from
->num
; i
++)
250 classes_ptr
->classes
[i
] = from
->classes
[i
];
251 complete_cost_classes (classes_ptr
);
255 /* Return a version of FULL that only considers registers in REGS that are
256 valid for mode MODE. Both FULL and the returned class are globally
258 static cost_classes_t
259 restrict_cost_classes (cost_classes_t full
, machine_mode mode
,
260 const HARD_REG_SET
®s
)
262 static struct cost_classes narrow
;
263 int map
[N_REG_CLASSES
];
265 for (int i
= 0; i
< full
->num
; i
++)
267 /* Assume that we'll drop the class. */
270 /* Ignore classes that are too small for the mode. */
271 enum reg_class cl
= full
->classes
[i
];
272 if (!contains_reg_of_mode
[cl
][mode
])
275 /* Calculate the set of registers in CL that belong to REGS and
276 are valid for MODE. */
277 HARD_REG_SET valid_for_cl
;
278 COPY_HARD_REG_SET (valid_for_cl
, reg_class_contents
[cl
]);
279 AND_HARD_REG_SET (valid_for_cl
, regs
);
280 AND_COMPL_HARD_REG_SET (valid_for_cl
,
281 ira_prohibited_class_mode_regs
[cl
][mode
]);
282 AND_COMPL_HARD_REG_SET (valid_for_cl
, ira_no_alloc_regs
);
283 if (hard_reg_set_empty_p (valid_for_cl
))
286 /* Don't use this class if the set of valid registers is a subset
287 of an existing class. For example, suppose we have two classes
288 GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose
289 that the mode changes allowed by FR_REGS are not as general as
290 the mode changes allowed by GR_REGS.
292 In this situation, the mode changes for GR_AND_FR_REGS could
293 either be seen as the union or the intersection of the mode
294 changes allowed by the two subclasses. The justification for
295 the union-based definition would be that, if you want a mode
296 change that's only allowed by GR_REGS, you can pick a register
297 from the GR_REGS subclass. The justification for the
298 intersection-based definition would be that every register
299 from the class would allow the mode change.
301 However, if we have a register that needs to be in GR_REGS,
302 using GR_AND_FR_REGS with the intersection-based definition
303 would be too pessimistic, since it would bring in restrictions
304 that only apply to FR_REGS. Conversely, if we have a register
305 that needs to be in FR_REGS, using GR_AND_FR_REGS with the
306 union-based definition would lose the extra restrictions
307 placed on FR_REGS. GR_AND_FR_REGS is therefore only useful
308 for cases where GR_REGS and FP_REGS are both valid. */
310 for (pos
= 0; pos
< narrow
.num
; ++pos
)
312 enum reg_class cl2
= narrow
.classes
[pos
];
313 if (hard_reg_set_subset_p (valid_for_cl
, reg_class_contents
[cl2
]))
317 if (pos
== narrow
.num
)
319 /* If several classes are equivalent, prefer to use the one
320 that was chosen as the allocno class. */
321 enum reg_class cl2
= ira_allocno_class_translate
[cl
];
322 if (ira_class_hard_regs_num
[cl
] == ira_class_hard_regs_num
[cl2
])
324 narrow
.classes
[narrow
.num
++] = cl
;
327 if (narrow
.num
== full
->num
)
330 cost_classes
**slot
= cost_classes_htab
->find_slot (&narrow
, INSERT
);
333 cost_classes_t classes
= setup_cost_classes (&narrow
);
334 /* Map equivalent classes to the representative that we chose above. */
335 for (int i
= 0; i
< ira_important_classes_num
; i
++)
337 enum reg_class cl
= ira_important_classes
[i
];
338 int index
= full
->index
[cl
];
340 classes
->index
[cl
] = map
[index
];
347 /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
348 This function is used when we know an initial approximation of
349 allocno class of the pseudo already, e.g. on the second iteration
350 of class cost calculation or after class cost calculation in
351 register-pressure sensitive insn scheduling or register-pressure
352 sensitive loop-invariant motion. */
354 setup_regno_cost_classes_by_aclass (int regno
, enum reg_class aclass
)
356 static struct cost_classes classes
;
357 cost_classes_t classes_ptr
;
361 HARD_REG_SET temp
, temp2
;
364 if ((classes_ptr
= cost_classes_aclass_cache
[aclass
]) == NULL
)
366 COPY_HARD_REG_SET (temp
, reg_class_contents
[aclass
]);
367 AND_COMPL_HARD_REG_SET (temp
, ira_no_alloc_regs
);
368 /* We exclude classes from consideration which are subsets of
369 ACLASS only if ACLASS is an uniform class. */
370 exclude_p
= ira_uniform_class_p
[aclass
];
372 for (i
= 0; i
< ira_important_classes_num
; i
++)
374 cl
= ira_important_classes
[i
];
377 /* Exclude non-uniform classes which are subsets of
379 COPY_HARD_REG_SET (temp2
, reg_class_contents
[cl
]);
380 AND_COMPL_HARD_REG_SET (temp2
, ira_no_alloc_regs
);
381 if (hard_reg_set_subset_p (temp2
, temp
) && cl
!= aclass
)
384 classes
.classes
[classes
.num
++] = cl
;
386 slot
= cost_classes_htab
->find_slot (&classes
, INSERT
);
389 classes_ptr
= setup_cost_classes (&classes
);
392 classes_ptr
= cost_classes_aclass_cache
[aclass
] = (cost_classes_t
) *slot
;
394 if (regno_reg_rtx
[regno
] != NULL_RTX
)
396 /* Restrict the classes to those that are valid for REGNO's mode
397 (which might for example exclude singleton classes if the mode
398 requires two registers). Also restrict the classes to those that
399 are valid for subregs of REGNO. */
400 const HARD_REG_SET
*valid_regs
= valid_mode_changes_for_regno (regno
);
402 valid_regs
= ®_class_contents
[ALL_REGS
];
403 classes_ptr
= restrict_cost_classes (classes_ptr
,
404 PSEUDO_REGNO_MODE (regno
),
407 regno_cost_classes
[regno
] = classes_ptr
;
410 /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
411 decrease number of cost classes for the pseudo, if hard registers
412 of some important classes can not hold a value of MODE. So the
413 pseudo can not get hard register of some important classes and cost
414 calculation for such important classes is only wasting CPU
417 setup_regno_cost_classes_by_mode (int regno
, machine_mode mode
)
419 if (const HARD_REG_SET
*valid_regs
= valid_mode_changes_for_regno (regno
))
420 regno_cost_classes
[regno
] = restrict_cost_classes (&all_cost_classes
,
424 if (cost_classes_mode_cache
[mode
] == NULL
)
425 cost_classes_mode_cache
[mode
]
426 = restrict_cost_classes (&all_cost_classes
, mode
,
427 reg_class_contents
[ALL_REGS
]);
428 regno_cost_classes
[regno
] = cost_classes_mode_cache
[mode
];
432 /* Finalize info about the cost classes for each pseudo. */
434 finish_regno_cost_classes (void)
436 ira_free (regno_cost_classes
);
437 delete cost_classes_htab
;
438 cost_classes_htab
= NULL
;
443 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
444 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
445 be a pseudo register. */
447 copy_cost (rtx x
, machine_mode mode
, reg_class_t rclass
, bool to_p
,
448 secondary_reload_info
*prev_sri
)
450 secondary_reload_info sri
;
451 reg_class_t secondary_class
= NO_REGS
;
453 /* If X is a SCRATCH, there is actually nothing to move since we are
454 assuming optimal allocation. */
455 if (GET_CODE (x
) == SCRATCH
)
458 /* Get the class we will actually use for a reload. */
459 rclass
= targetm
.preferred_reload_class (x
, rclass
);
461 /* If we need a secondary reload for an intermediate, the cost is
462 that to load the input into the intermediate register, then to
464 sri
.prev_sri
= prev_sri
;
466 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
468 if (secondary_class
!= NO_REGS
)
470 ira_init_register_move_cost_if_necessary (mode
);
471 return (ira_register_move_cost
[mode
][(int) secondary_class
][(int) rclass
]
473 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
476 /* For memory, use the memory move cost, for (hard) registers, use
477 the cost to move between the register classes, and use 2 for
478 everything else (constants). */
479 if (MEM_P (x
) || rclass
== NO_REGS
)
480 return sri
.extra_cost
481 + ira_memory_move_cost
[mode
][(int) rclass
][to_p
!= 0];
484 reg_class_t x_class
= REGNO_REG_CLASS (REGNO (x
));
486 ira_init_register_move_cost_if_necessary (mode
);
487 return (sri
.extra_cost
488 + ira_register_move_cost
[mode
][(int) x_class
][(int) rclass
]);
491 /* If this is a constant, we may eventually want to call rtx_cost
493 return sri
.extra_cost
+ COSTS_N_INSNS (1);
498 /* Record the cost of using memory or hard registers of various
499 classes for the operands in INSN.
501 N_ALTS is the number of alternatives.
502 N_OPS is the number of operands.
503 OPS is an array of the operands.
504 MODES are the modes of the operands, in case any are VOIDmode.
505 CONSTRAINTS are the constraints to use for the operands. This array
506 is modified by this procedure.
508 This procedure works alternative by alternative. For each
509 alternative we assume that we will be able to allocate all allocnos
510 to their ideal register class and calculate the cost of using that
511 alternative. Then we compute, for each operand that is a
512 pseudo-register, the cost of having the allocno allocated to each
513 register class and using it in that alternative. To this cost is
514 added the cost of the alternative.
516 The cost of each class for this insn is its lowest cost among all
519 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
520 machine_mode
*modes
, const char **constraints
,
521 rtx_insn
*insn
, enum reg_class
*pref
)
525 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
526 move_table
*move_in_cost
, *move_out_cost
;
527 short (*mem_cost
)[2];
529 for (i
= 0; i
< n_ops
; i
++)
530 insn_allows_mem
[i
] = 0;
532 /* Process each alternative, each time minimizing an operand's cost
533 with the cost for each operand in that alternative. */
534 alternative_mask preferred
= get_preferred_alternatives (insn
);
535 for (alt
= 0; alt
< n_alts
; alt
++)
537 enum reg_class classes
[MAX_RECOG_OPERANDS
];
538 int allows_mem
[MAX_RECOG_OPERANDS
];
539 enum reg_class rclass
;
541 int alt_cost
= 0, op_cost_add
;
543 if (!TEST_BIT (preferred
, alt
))
545 for (i
= 0; i
< recog_data
.n_operands
; i
++)
546 constraints
[i
] = skip_alternative (constraints
[i
]);
551 for (i
= 0; i
< n_ops
; i
++)
554 const char *p
= constraints
[i
];
556 machine_mode mode
= modes
[i
];
560 /* Initially show we know nothing about the register class. */
561 classes
[i
] = NO_REGS
;
564 /* If this operand has no constraints at all, we can
565 conclude nothing about it since anything is valid. */
568 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
569 memset (this_op_costs
[i
], 0, struct_costs_size
);
573 /* If this alternative is only relevant when this operand
574 matches a previous operand, we do different things
575 depending on whether this operand is a allocno-reg or not.
576 We must process any modifiers for the operand before we
577 can make this test. */
578 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
581 if (p
[0] >= '0' && p
[0] <= '0' + i
)
583 /* Copy class and whether memory is allowed from the
584 matching alternative. Then perform any needed cost
585 computations and/or adjustments. */
587 classes
[i
] = classes
[j
];
588 allows_mem
[i
] = allows_mem
[j
];
590 insn_allows_mem
[i
] = 1;
592 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
594 /* If this matches the other operand, we have no
595 added cost and we win. */
596 if (rtx_equal_p (ops
[j
], op
))
598 /* If we can put the other operand into a register,
599 add to the cost of this alternative the cost to
600 copy this operand to the register used for the
602 else if (classes
[j
] != NO_REGS
)
604 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
608 else if (! REG_P (ops
[j
])
609 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
611 /* This op is an allocno but the one it matches is
614 /* If we can't put the other operand into a
615 register, this alternative can't be used. */
617 if (classes
[j
] == NO_REGS
)
619 /* Otherwise, add to the cost of this alternative
620 the cost to copy the other operand to the hard
621 register used for this operand. */
623 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
627 /* The costs of this operand are not the same as the
628 other operand since move costs are not symmetric.
629 Moreover, if we cannot tie them, this alternative
630 needs to do a copy, which is one insn. */
631 struct costs
*pp
= this_op_costs
[i
];
632 int *pp_costs
= pp
->cost
;
633 cost_classes_t cost_classes_ptr
634 = regno_cost_classes
[REGNO (op
)];
635 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
636 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
637 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
638 enum reg_class op_class
= classes
[i
];
640 ira_init_register_move_cost_if_necessary (mode
);
644 if (op_class
== NO_REGS
)
646 mem_cost
= ira_memory_move_cost
[mode
];
647 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
649 rclass
= cost_classes
[k
];
650 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
655 move_out_cost
= ira_may_move_out_cost
[mode
];
656 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
658 rclass
= cost_classes
[k
];
660 = move_out_cost
[op_class
][rclass
] * frequency
;
667 if (op_class
== NO_REGS
)
669 mem_cost
= ira_memory_move_cost
[mode
];
670 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
672 rclass
= cost_classes
[k
];
673 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
678 move_in_cost
= ira_may_move_in_cost
[mode
];
679 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
681 rclass
= cost_classes
[k
];
683 = move_in_cost
[rclass
][op_class
] * frequency
;
689 if (op_class
== NO_REGS
)
691 mem_cost
= ira_memory_move_cost
[mode
];
692 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
694 rclass
= cost_classes
[k
];
695 pp_costs
[k
] = ((mem_cost
[rclass
][0]
696 + mem_cost
[rclass
][1])
702 move_in_cost
= ira_may_move_in_cost
[mode
];
703 move_out_cost
= ira_may_move_out_cost
[mode
];
704 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
706 rclass
= cost_classes
[k
];
707 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
708 + move_out_cost
[op_class
][rclass
])
714 /* If the alternative actually allows memory, make
715 things a bit cheaper since we won't need an extra
718 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
719 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
720 - allows_mem
[i
]) * frequency
;
722 /* If we have assigned a class to this allocno in
723 our first pass, add a cost to this alternative
724 corresponding to what we would add if this
725 allocno were not in the appropriate class. */
728 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
730 if (pref_class
== NO_REGS
)
733 ? ira_memory_move_cost
[mode
][op_class
][0] : 0)
735 ? ira_memory_move_cost
[mode
][op_class
][1]
737 else if (ira_reg_class_intersect
738 [pref_class
][op_class
] == NO_REGS
)
740 += ira_register_move_cost
[mode
][pref_class
][op_class
];
742 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
743 && ! find_reg_note (insn
, REG_DEAD
, op
))
750 /* Scan all the constraint letters. See if the operand
751 matches any of the constraints. Collect the valid
752 register classes and see if this operand accepts
759 /* Ignore the next letter for this pass. */
774 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
776 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
777 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][GENERAL_REGS
];
781 enum constraint_num cn
= lookup_constraint (p
);
783 switch (get_constraint_type (cn
))
786 cl
= reg_class_for_constraint (cn
);
788 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][cl
];
793 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
798 /* Every MEM can be reloaded to fit. */
799 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
805 /* Every address can be reloaded to fit. */
807 if (address_operand (op
, GET_MODE (op
))
808 || constraint_satisfied_p (op
, cn
))
810 /* We know this operand is an address, so we
811 want it to be allocated to a hard register
812 that can be the base of an address,
813 i.e. BASE_REG_CLASS. */
815 = ira_reg_class_subunion
[classes
[i
]]
816 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
821 if (constraint_satisfied_p (op
, cn
))
827 p
+= CONSTRAINT_LEN (c
, p
);
834 /* How we account for this operand now depends on whether it
835 is a pseudo register or not. If it is, we first check if
836 any register classes are valid. If not, we ignore this
837 alternative, since we want to assume that all allocnos get
838 allocated for register preferencing. If some register
839 class is valid, compute the costs of moving the allocno
841 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
843 if (classes
[i
] == NO_REGS
&& ! allows_mem
[i
])
845 /* We must always fail if the operand is a REG, but
846 we did not find a suitable class and memory is
849 Otherwise we may perform an uninitialized read
850 from this_op_costs after the `continue' statement
856 unsigned int regno
= REGNO (op
);
857 struct costs
*pp
= this_op_costs
[i
];
858 int *pp_costs
= pp
->cost
;
859 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
860 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
861 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
862 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
863 enum reg_class op_class
= classes
[i
];
865 ira_init_register_move_cost_if_necessary (mode
);
869 if (op_class
== NO_REGS
)
871 mem_cost
= ira_memory_move_cost
[mode
];
872 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
874 rclass
= cost_classes
[k
];
875 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
880 move_out_cost
= ira_may_move_out_cost
[mode
];
881 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
883 rclass
= cost_classes
[k
];
885 = move_out_cost
[op_class
][rclass
] * frequency
;
892 if (op_class
== NO_REGS
)
894 mem_cost
= ira_memory_move_cost
[mode
];
895 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
897 rclass
= cost_classes
[k
];
898 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
903 move_in_cost
= ira_may_move_in_cost
[mode
];
904 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
906 rclass
= cost_classes
[k
];
908 = move_in_cost
[rclass
][op_class
] * frequency
;
914 if (op_class
== NO_REGS
)
916 mem_cost
= ira_memory_move_cost
[mode
];
917 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
919 rclass
= cost_classes
[k
];
920 pp_costs
[k
] = ((mem_cost
[rclass
][0]
921 + mem_cost
[rclass
][1])
927 move_in_cost
= ira_may_move_in_cost
[mode
];
928 move_out_cost
= ira_may_move_out_cost
[mode
];
929 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
931 rclass
= cost_classes
[k
];
932 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
933 + move_out_cost
[op_class
][rclass
])
939 if (op_class
== NO_REGS
)
940 /* Although we don't need insn to reload from
941 memory, still accessing memory is usually more
942 expensive than a register. */
943 pp
->mem_cost
= frequency
;
945 /* If the alternative actually allows memory, make
946 things a bit cheaper since we won't need an
947 extra insn to load it. */
949 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
950 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
951 - allows_mem
[i
]) * frequency
;
952 /* If we have assigned a class to this allocno in
953 our first pass, add a cost to this alternative
954 corresponding to what we would add if this
955 allocno were not in the appropriate class. */
958 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
960 if (pref_class
== NO_REGS
)
962 if (op_class
!= NO_REGS
)
965 ? ira_memory_move_cost
[mode
][op_class
][0]
968 ? ira_memory_move_cost
[mode
][op_class
][1]
971 else if (op_class
== NO_REGS
)
974 ? ira_memory_move_cost
[mode
][pref_class
][1]
977 ? ira_memory_move_cost
[mode
][pref_class
][0]
979 else if (ira_reg_class_intersect
[pref_class
][op_class
]
981 alt_cost
+= (ira_register_move_cost
982 [mode
][pref_class
][op_class
]);
987 /* Otherwise, if this alternative wins, either because we
988 have already determined that or if we have a hard
989 register of the proper class, there is no cost for this
991 else if (win
|| (REG_P (op
)
992 && reg_fits_class_p (op
, classes
[i
],
996 /* If registers are valid, the cost of this alternative
997 includes copying the object to and/or from a
999 else if (classes
[i
] != NO_REGS
)
1001 if (recog_data
.operand_type
[i
] != OP_OUT
)
1002 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
1004 if (recog_data
.operand_type
[i
] != OP_IN
)
1005 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
1007 /* The only other way this alternative can be used is if
1008 this is a constant that could be placed into memory. */
1009 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1010 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
1018 op_cost_add
= alt_cost
* frequency
;
1019 /* Finally, update the costs with the information we've
1020 calculated about this alternative. */
1021 for (i
= 0; i
< n_ops
; i
++)
1022 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1024 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
1025 int *pp_costs
= pp
->cost
, *qq_costs
= qq
->cost
;
1026 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1027 cost_classes_t cost_classes_ptr
1028 = regno_cost_classes
[REGNO (ops
[i
])];
1030 pp
->mem_cost
= MIN (pp
->mem_cost
,
1031 (qq
->mem_cost
+ op_cost_add
) * scale
);
1033 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1035 = MIN (pp_costs
[k
], (qq_costs
[k
] + op_cost_add
) * scale
);
1040 for (i
= 0; i
< n_ops
; i
++)
1045 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1047 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
1048 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
1049 ALLOCNO_BAD_SPILL_P (a
) = true;
1056 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
1058 ok_for_index_p_nonstrict (rtx reg
)
1060 unsigned regno
= REGNO (reg
);
1062 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
1065 /* A version of regno_ok_for_base_p for use here, when all
1066 pseudo-registers should count as OK. Arguments as for
1067 regno_ok_for_base_p. */
1069 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
1070 enum rtx_code outer_code
, enum rtx_code index_code
)
1072 unsigned regno
= REGNO (reg
);
1074 if (regno
>= FIRST_PSEUDO_REGISTER
)
1076 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
1079 /* Record the pseudo registers we must reload into hard registers in a
1080 subexpression of a memory address, X.
1082 If CONTEXT is 0, we are looking at the base part of an address,
1083 otherwise we are looking at the index part.
1085 MODE and AS are the mode and address space of the memory reference;
1086 OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1087 These four arguments are passed down to base_reg_class.
1089 SCALE is twice the amount to multiply the cost by (it is twice so
1090 we can represent half-cost adjustments). */
1092 record_address_regs (machine_mode mode
, addr_space_t as
, rtx x
,
1093 int context
, enum rtx_code outer_code
,
1094 enum rtx_code index_code
, int scale
)
1096 enum rtx_code code
= GET_CODE (x
);
1097 enum reg_class rclass
;
1100 rclass
= INDEX_REG_CLASS
;
1102 rclass
= base_reg_class (mode
, as
, outer_code
, index_code
);
1115 /* When we have an address that is a sum, we must determine
1116 whether registers are "base" or "index" regs. If there is a
1117 sum of two registers, we must choose one to be the "base".
1118 Luckily, we can use the REG_POINTER to make a good choice
1119 most of the time. We only need to do this on machines that
1120 can have two registers in an address and where the base and
1121 index register classes are different.
1123 ??? This code used to set REGNO_POINTER_FLAG in some cases,
1124 but that seems bogus since it should only be set when we are
1125 sure the register is being used as a pointer. */
1127 rtx arg0
= XEXP (x
, 0);
1128 rtx arg1
= XEXP (x
, 1);
1129 enum rtx_code code0
= GET_CODE (arg0
);
1130 enum rtx_code code1
= GET_CODE (arg1
);
1132 /* Look inside subregs. */
1133 if (code0
== SUBREG
)
1134 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1135 if (code1
== SUBREG
)
1136 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1138 /* If this machine only allows one register per address, it
1139 must be in the first operand. */
1140 if (MAX_REGS_PER_ADDRESS
== 1)
1141 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1143 /* If index and base registers are the same on this machine,
1144 just record registers in any non-constant operands. We
1145 assume here, as well as in the tests below, that all
1146 addresses are in canonical form. */
1147 else if (INDEX_REG_CLASS
1148 == base_reg_class (VOIDmode
, as
, PLUS
, SCRATCH
))
1150 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1151 if (! CONSTANT_P (arg1
))
1152 record_address_regs (mode
, as
, arg1
, context
, PLUS
, code0
, scale
);
1155 /* If the second operand is a constant integer, it doesn't
1156 change what class the first operand must be. */
1157 else if (CONST_SCALAR_INT_P (arg1
))
1158 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1159 /* If the second operand is a symbolic constant, the first
1160 operand must be an index register. */
1161 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1162 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1163 /* If both operands are registers but one is already a hard
1164 register of index or reg-base class, give the other the
1165 class that the hard register is not. */
1166 else if (code0
== REG
&& code1
== REG
1167 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1168 && (ok_for_base_p_nonstrict (arg0
, mode
, as
, PLUS
, REG
)
1169 || ok_for_index_p_nonstrict (arg0
)))
1170 record_address_regs (mode
, as
, arg1
,
1171 ok_for_base_p_nonstrict (arg0
, mode
, as
,
1174 else if (code0
== REG
&& code1
== REG
1175 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1176 && (ok_for_base_p_nonstrict (arg1
, mode
, as
, PLUS
, REG
)
1177 || ok_for_index_p_nonstrict (arg1
)))
1178 record_address_regs (mode
, as
, arg0
,
1179 ok_for_base_p_nonstrict (arg1
, mode
, as
,
1182 /* If one operand is known to be a pointer, it must be the
1183 base with the other operand the index. Likewise if the
1184 other operand is a MULT. */
1185 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
1187 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1188 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
);
1190 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
1192 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1193 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
);
1195 /* Otherwise, count equal chances that each might be a base or
1196 index register. This case should be rare. */
1199 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
/ 2);
1200 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
/ 2);
1201 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
/ 2);
1202 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
/ 2);
1207 /* Double the importance of an allocno that is incremented or
1208 decremented, since it would take two extra insns if it ends
1209 up in the wrong place. */
1212 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
,
1213 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
1214 if (REG_P (XEXP (XEXP (x
, 1), 1)))
1215 record_address_regs (mode
, as
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
1223 /* Double the importance of an allocno that is incremented or
1224 decremented, since it would take two extra insns if it ends
1225 up in the wrong place. */
1226 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
1234 int k
, regno
, add_cost
;
1235 cost_classes_t cost_classes_ptr
;
1236 enum reg_class
*cost_classes
;
1237 move_table
*move_in_cost
;
1239 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1244 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[regno
]) = true;
1245 pp
= COSTS (costs
, COST_INDEX (regno
));
1246 add_cost
= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
1247 if (INT_MAX
- add_cost
< pp
->mem_cost
)
1248 pp
->mem_cost
= INT_MAX
;
1250 pp
->mem_cost
+= add_cost
;
1251 cost_classes_ptr
= regno_cost_classes
[regno
];
1252 cost_classes
= cost_classes_ptr
->classes
;
1253 pp_costs
= pp
->cost
;
1254 ira_init_register_move_cost_if_necessary (Pmode
);
1255 move_in_cost
= ira_may_move_in_cost
[Pmode
];
1256 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1258 i
= cost_classes
[k
];
1259 add_cost
= (move_in_cost
[i
][rclass
] * scale
) / 2;
1260 if (INT_MAX
- add_cost
< pp_costs
[k
])
1261 pp_costs
[k
] = INT_MAX
;
1263 pp_costs
[k
] += add_cost
;
1270 const char *fmt
= GET_RTX_FORMAT (code
);
1272 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1274 record_address_regs (mode
, as
, XEXP (x
, i
), context
, code
, SCRATCH
,
1282 /* Calculate the costs of insn operands. */
1284 record_operand_costs (rtx_insn
*insn
, enum reg_class
*pref
)
1286 const char *constraints
[MAX_RECOG_OPERANDS
];
1287 machine_mode modes
[MAX_RECOG_OPERANDS
];
1288 rtx ops
[MAX_RECOG_OPERANDS
];
1292 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1294 constraints
[i
] = recog_data
.constraints
[i
];
1295 modes
[i
] = recog_data
.operand_mode
[i
];
1298 /* If we get here, we are set up to record the costs of all the
1299 operands for this insn. Start by initializing the costs. Then
1300 handle any address registers. Finally record the desired classes
1301 for any allocnos, doing it twice if some pair of operands are
1303 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1305 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
1307 ops
[i
] = recog_data
.operand
[i
];
1308 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1309 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1311 if (MEM_P (recog_data
.operand
[i
]))
1312 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1313 MEM_ADDR_SPACE (recog_data
.operand
[i
]),
1314 XEXP (recog_data
.operand
[i
], 0),
1315 0, MEM
, SCRATCH
, frequency
* 2);
1316 else if (constraints
[i
][0] == 'p'
1317 || (insn_extra_address_constraint
1318 (lookup_constraint (constraints
[i
]))))
1319 record_address_regs (VOIDmode
, ADDR_SPACE_GENERIC
,
1320 recog_data
.operand
[i
], 0, ADDRESS
, SCRATCH
,
1324 /* Check for commutative in a separate loop so everything will have
1325 been initialized. We must do this even if one operand is a
1326 constant--see addsi3 in m68k.md. */
1327 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1328 if (constraints
[i
][0] == '%')
1330 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1333 /* Handle commutative operands by swapping the constraints.
1334 We assume the modes are the same. */
1335 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1336 xconstraints
[j
] = constraints
[j
];
1338 xconstraints
[i
] = constraints
[i
+1];
1339 xconstraints
[i
+1] = constraints
[i
];
1340 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1341 recog_data
.operand
, modes
,
1342 xconstraints
, insn
, pref
);
1344 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1345 recog_data
.operand
, modes
,
1346 constraints
, insn
, pref
);
1348 /* If this insn is a single set copying operand 1 to operand 0 and
1349 one operand is an allocno with the other a hard reg or an allocno
1350 that prefers a hard register that is in its own register class
1351 then we may want to adjust the cost of that register class to -1.
1353 Avoid the adjustment if the source does not die to avoid
1354 stressing of register allocator by preferencing two colliding
1355 registers into single class.
1357 Also avoid the adjustment if a copy between hard registers of the
1358 class is expensive (ten times the cost of a default copy is
1359 considered arbitrarily expensive). This avoids losing when the
1360 preferred class is very expensive as the source of a copy
1362 if ((set
= single_set (insn
)) != NULL_RTX
1363 /* In rare cases the single set insn might have less 2 operands
1364 as the source can be a fixed special reg. */
1365 && recog_data
.n_operands
> 1
1366 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
))
1368 int regno
, other_regno
;
1369 rtx dest
= SET_DEST (set
);
1370 rtx src
= SET_SRC (set
);
1372 if (GET_CODE (dest
) == SUBREG
1373 && (GET_MODE_SIZE (GET_MODE (dest
))
1374 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))))
1375 dest
= SUBREG_REG (dest
);
1376 if (GET_CODE (src
) == SUBREG
1377 && (GET_MODE_SIZE (GET_MODE (src
))
1378 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
1379 src
= SUBREG_REG (src
);
1380 if (REG_P (src
) && REG_P (dest
)
1381 && find_regno_note (insn
, REG_DEAD
, REGNO (src
))
1382 && (((regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
1383 && (other_regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
)
1384 || ((regno
= REGNO (dest
)) >= FIRST_PSEUDO_REGISTER
1385 && (other_regno
= REGNO (src
)) < FIRST_PSEUDO_REGISTER
)))
1387 machine_mode mode
= GET_MODE (src
);
1388 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1389 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1393 i
= regno
== (int) REGNO (src
) ? 1 : 0;
1394 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1396 rclass
= cost_classes
[k
];
1397 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], other_regno
)
1398 && (reg_class_size
[(int) rclass
]
1399 == ira_reg_class_max_nregs
[(int) rclass
][(int) mode
]))
1401 if (reg_class_size
[rclass
] == 1)
1402 op_costs
[i
]->cost
[k
] = -frequency
;
1406 nr
< hard_regno_nregs
[other_regno
][mode
];
1408 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
1412 if (nr
== hard_regno_nregs
[other_regno
][mode
])
1413 op_costs
[i
]->cost
[k
] = -frequency
;
1423 /* Process one insn INSN. Scan it and record each time it would save
1424 code to put a certain allocnos in a certain class. Return the last
1425 insn processed, so that the scan can be continued from there. */
1427 scan_one_insn (rtx_insn
*insn
)
1429 enum rtx_code pat_code
;
1434 if (!NONDEBUG_INSN_P (insn
))
1437 pat_code
= GET_CODE (PATTERN (insn
));
1438 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
)
1441 counted_mem
= false;
1442 set
= single_set (insn
);
1443 extract_insn (insn
);
1445 /* If this insn loads a parameter from its stack slot, then it
1446 represents a savings, rather than a cost, if the parameter is
1447 stored in memory. Record this fact.
1449 Similarly if we're loading other constants from memory (constant
1450 pool, TOC references, small data areas, etc) and this is the only
1451 assignment to the destination pseudo.
1453 Don't do this if SET_SRC (set) isn't a general operand, if it is
1454 a memory requiring special instructions to load it, decreasing
1455 mem_cost might result in it being loaded using the specialized
1456 instruction into a register, then stored into stack and loaded
1457 again from the stack. See PR52208.
1459 Don't do this if SET_SRC (set) has side effect. See PR56124. */
1460 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1461 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1462 && ((MEM_P (XEXP (note
, 0))
1463 && !side_effects_p (SET_SRC (set
)))
1464 || (CONSTANT_P (XEXP (note
, 0))
1465 && targetm
.legitimate_constant_p (GET_MODE (SET_DEST (set
)),
1467 && REG_N_SETS (REGNO (SET_DEST (set
))) == 1))
1468 && general_operand (SET_SRC (set
), GET_MODE (SET_SRC (set
))))
1470 enum reg_class cl
= GENERAL_REGS
;
1471 rtx reg
= SET_DEST (set
);
1472 int num
= COST_INDEX (REGNO (reg
));
1474 COSTS (costs
, num
)->mem_cost
1475 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1476 record_address_regs (GET_MODE (SET_SRC (set
)),
1477 MEM_ADDR_SPACE (SET_SRC (set
)),
1478 XEXP (SET_SRC (set
), 0), 0, MEM
, SCRATCH
,
1483 record_operand_costs (insn
, pref
);
1485 /* Now add the cost for each operand to the total costs for its
1487 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1488 if (REG_P (recog_data
.operand
[i
])
1489 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1491 int regno
= REGNO (recog_data
.operand
[i
]);
1492 struct costs
*p
= COSTS (costs
, COST_INDEX (regno
));
1493 struct costs
*q
= op_costs
[i
];
1494 int *p_costs
= p
->cost
, *q_costs
= q
->cost
;
1495 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1498 /* If the already accounted for the memory "cost" above, don't
1502 add_cost
= q
->mem_cost
;
1503 if (add_cost
> 0 && INT_MAX
- add_cost
< p
->mem_cost
)
1504 p
->mem_cost
= INT_MAX
;
1506 p
->mem_cost
+= add_cost
;
1508 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1510 add_cost
= q_costs
[k
];
1511 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1512 p_costs
[k
] = INT_MAX
;
1514 p_costs
[k
] += add_cost
;
1523 /* Print allocnos costs to file F. */
1525 print_allocno_costs (FILE *f
)
1529 ira_allocno_iterator ai
;
1531 ira_assert (allocno_p
);
1533 FOR_EACH_ALLOCNO (a
, ai
)
1537 int regno
= ALLOCNO_REGNO (a
);
1538 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1539 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1541 i
= ALLOCNO_NUM (a
);
1542 fprintf (f
, " a%d(r%d,", i
, regno
);
1543 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1544 fprintf (f
, "b%d", bb
->index
);
1546 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1547 fprintf (f
, ") costs:");
1548 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1550 rclass
= cost_classes
[k
];
1551 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1552 COSTS (costs
, i
)->cost
[k
]);
1553 if (flag_ira_region
== IRA_REGION_ALL
1554 || flag_ira_region
== IRA_REGION_MIXED
)
1555 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->cost
[k
]);
1557 fprintf (f
, " MEM:%i", COSTS (costs
, i
)->mem_cost
);
1558 if (flag_ira_region
== IRA_REGION_ALL
1559 || flag_ira_region
== IRA_REGION_MIXED
)
1560 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->mem_cost
);
1565 /* Print pseudo costs to file F. */
1567 print_pseudo_costs (FILE *f
)
1571 cost_classes_t cost_classes_ptr
;
1572 enum reg_class
*cost_classes
;
1574 ira_assert (! allocno_p
);
1576 for (regno
= max_reg_num () - 1; regno
>= FIRST_PSEUDO_REGISTER
; regno
--)
1578 if (REG_N_REFS (regno
) <= 0)
1580 cost_classes_ptr
= regno_cost_classes
[regno
];
1581 cost_classes
= cost_classes_ptr
->classes
;
1582 fprintf (f
, " r%d costs:", regno
);
1583 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1585 rclass
= cost_classes
[k
];
1586 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1587 COSTS (costs
, regno
)->cost
[k
]);
1589 fprintf (f
, " MEM:%i\n", COSTS (costs
, regno
)->mem_cost
);
1593 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1596 process_bb_for_costs (basic_block bb
)
1600 frequency
= REG_FREQ_FROM_BB (bb
);
1603 FOR_BB_INSNS (bb
, insn
)
1604 insn
= scan_one_insn (insn
);
1607 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1610 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1614 bb
= loop_tree_node
->bb
;
1616 process_bb_for_costs (bb
);
1619 /* Find costs of register classes and memory for allocnos or pseudos
1620 and their best costs. Set up preferred, alternative and allocno
1621 classes for pseudos. */
1623 find_costs_and_classes (FILE *dump_file
)
1625 int i
, k
, start
, max_cost_classes_num
;
1628 enum reg_class
*regno_best_class
, new_class
;
1632 = (enum reg_class
*) ira_allocate (max_reg_num ()
1633 * sizeof (enum reg_class
));
1634 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1635 regno_best_class
[i
] = NO_REGS
;
1636 if (!resize_reg_info () && allocno_p
1637 && pseudo_classes_defined_p
&& flag_expensive_optimizations
)
1640 ira_allocno_iterator ai
;
1643 max_cost_classes_num
= 1;
1644 FOR_EACH_ALLOCNO (a
, ai
)
1646 pref
[ALLOCNO_NUM (a
)] = reg_preferred_class (ALLOCNO_REGNO (a
));
1647 setup_regno_cost_classes_by_aclass
1648 (ALLOCNO_REGNO (a
), pref
[ALLOCNO_NUM (a
)]);
1649 max_cost_classes_num
1650 = MAX (max_cost_classes_num
,
1651 regno_cost_classes
[ALLOCNO_REGNO (a
)]->num
);
1658 max_cost_classes_num
= ira_important_classes_num
;
1659 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1660 if (regno_reg_rtx
[i
] != NULL_RTX
)
1661 setup_regno_cost_classes_by_mode (i
, PSEUDO_REGNO_MODE (i
));
1663 setup_regno_cost_classes_by_aclass (i
, ALL_REGS
);
1667 /* Clear the flag for the next compiled function. */
1668 pseudo_classes_defined_p
= false;
1669 /* Normally we scan the insns once and determine the best class to
1670 use for each allocno. However, if -fexpensive-optimizations are
1671 on, we do so twice, the second time using the tentative best
1672 classes to guide the selection. */
1673 for (pass
= start
; pass
<= flag_expensive_optimizations
; pass
++)
1675 if ((!allocno_p
|| internal_flag_ira_verbose
> 0) && dump_file
)
1677 "\nPass %i for finding pseudo/allocno costs\n\n", pass
);
1681 max_cost_classes_num
= 1;
1682 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1684 setup_regno_cost_classes_by_aclass (i
, regno_best_class
[i
]);
1685 max_cost_classes_num
1686 = MAX (max_cost_classes_num
, regno_cost_classes
[i
]->num
);
1691 = sizeof (struct costs
) + sizeof (int) * (max_cost_classes_num
- 1);
1692 /* Zero out our accumulation of the cost of each class for each
1694 memset (costs
, 0, cost_elements_num
* struct_costs_size
);
1698 /* Scan the instructions and record each time it would save code
1699 to put a certain allocno in a certain class. */
1700 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1701 process_bb_node_for_costs
, NULL
);
1703 memcpy (total_allocno_costs
, costs
,
1704 max_struct_costs_size
* ira_allocnos_num
);
1710 FOR_EACH_BB_FN (bb
, cfun
)
1711 process_bb_for_costs (bb
);
1717 /* Now for each allocno look at how desirable each class is and
1718 find which class is preferred. */
1719 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1721 ira_allocno_t a
, parent_a
;
1722 int rclass
, a_num
, parent_a_num
, add_cost
;
1723 ira_loop_tree_node_t parent
;
1724 int best_cost
, allocno_cost
;
1725 enum reg_class best
, alt_class
;
1726 cost_classes_t cost_classes_ptr
= regno_cost_classes
[i
];
1727 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1728 int *i_costs
= temp_costs
->cost
;
1730 int equiv_savings
= regno_equiv_gains
[i
];
1734 if (regno_reg_rtx
[i
] == NULL_RTX
)
1736 memcpy (temp_costs
, COSTS (costs
, i
), struct_costs_size
);
1737 i_mem_cost
= temp_costs
->mem_cost
;
1741 if (ira_regno_allocno_map
[i
] == NULL
)
1743 memset (temp_costs
, 0, struct_costs_size
);
1745 /* Find cost of all allocnos with the same regno. */
1746 for (a
= ira_regno_allocno_map
[i
];
1748 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1750 int *a_costs
, *p_costs
;
1752 a_num
= ALLOCNO_NUM (a
);
1753 if ((flag_ira_region
== IRA_REGION_ALL
1754 || flag_ira_region
== IRA_REGION_MIXED
)
1755 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1756 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1757 /* There are no caps yet. */
1758 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1759 (a
)->border_allocnos
,
1762 /* Propagate costs to upper levels in the region
1764 parent_a_num
= ALLOCNO_NUM (parent_a
);
1765 a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1766 p_costs
= COSTS (total_allocno_costs
, parent_a_num
)->cost
;
1767 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1769 add_cost
= a_costs
[k
];
1770 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1771 p_costs
[k
] = INT_MAX
;
1773 p_costs
[k
] += add_cost
;
1775 add_cost
= COSTS (total_allocno_costs
, a_num
)->mem_cost
;
1777 && (INT_MAX
- add_cost
1778 < COSTS (total_allocno_costs
,
1779 parent_a_num
)->mem_cost
))
1780 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1783 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1786 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1787 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
= 0;
1789 a_costs
= COSTS (costs
, a_num
)->cost
;
1790 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1792 add_cost
= a_costs
[k
];
1793 if (add_cost
> 0 && INT_MAX
- add_cost
< i_costs
[k
])
1794 i_costs
[k
] = INT_MAX
;
1796 i_costs
[k
] += add_cost
;
1798 add_cost
= COSTS (costs
, a_num
)->mem_cost
;
1799 if (add_cost
> 0 && INT_MAX
- add_cost
< i_mem_cost
)
1800 i_mem_cost
= INT_MAX
;
1802 i_mem_cost
+= add_cost
;
1805 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1807 else if (equiv_savings
< 0)
1808 i_mem_cost
= -equiv_savings
;
1809 else if (equiv_savings
> 0)
1812 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1813 i_costs
[k
] += equiv_savings
;
1816 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1818 alt_class
= NO_REGS
;
1819 /* Find best common class for all allocnos with the same
1821 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1823 rclass
= cost_classes
[k
];
1824 if (i_costs
[k
] < best_cost
)
1826 best_cost
= i_costs
[k
];
1827 best
= (enum reg_class
) rclass
;
1829 else if (i_costs
[k
] == best_cost
)
1830 best
= ira_reg_class_subunion
[best
][rclass
];
1831 if (pass
== flag_expensive_optimizations
1832 /* We still prefer registers to memory even at this
1833 stage if their costs are the same. We will make
1834 a final decision during assigning hard registers
1835 when we have all info including more accurate
1836 costs which might be affected by assigning hard
1837 registers to other pseudos because the pseudos
1838 involved in moves can be coalesced. */
1839 && i_costs
[k
] <= i_mem_cost
1840 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1841 > reg_class_size
[alt_class
]))
1842 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1844 alt_class
= ira_allocno_class_translate
[alt_class
];
1845 if (best_cost
> i_mem_cost
)
1846 regno_aclass
[i
] = NO_REGS
;
1847 else if (!optimize
&& !targetm
.class_likely_spilled_p (best
))
1848 /* Registers in the alternative class are likely to need
1849 longer or slower sequences than registers in the best class.
1850 When optimizing we make some effort to use the best class
1851 over the alternative class where possible, but at -O0 we
1852 effectively give the alternative class equal weight.
1853 We then run the risk of using slower alternative registers
1854 when plenty of registers from the best class are still free.
1855 This is especially true because live ranges tend to be very
1856 short in -O0 code and so register pressure tends to be low.
1858 Avoid that by ignoring the alternative class if the best
1859 class has plenty of registers. */
1860 regno_aclass
[i
] = best
;
1863 /* Make the common class the biggest class of best and
1866 = ira_reg_class_superunion
[best
][alt_class
];
1867 ira_assert (regno_aclass
[i
] != NO_REGS
1868 && ira_reg_allocno_class_p
[regno_aclass
[i
]]);
1871 = (reg_class
) (targetm
.ira_change_pseudo_allocno_class
1872 (i
, regno_aclass
[i
]))) != regno_aclass
[i
])
1874 regno_aclass
[i
] = new_class
;
1875 if (hard_reg_set_subset_p (reg_class_contents
[new_class
],
1876 reg_class_contents
[best
]))
1878 if (hard_reg_set_subset_p (reg_class_contents
[new_class
],
1879 reg_class_contents
[alt_class
]))
1880 alt_class
= new_class
;
1882 if (pass
== flag_expensive_optimizations
)
1884 if (best_cost
> i_mem_cost
)
1885 best
= alt_class
= NO_REGS
;
1886 else if (best
== alt_class
)
1887 alt_class
= NO_REGS
;
1888 setup_reg_classes (i
, best
, alt_class
, regno_aclass
[i
]);
1889 if ((!allocno_p
|| internal_flag_ira_verbose
> 2)
1890 && dump_file
!= NULL
)
1892 " r%d: preferred %s, alternative %s, allocno %s\n",
1893 i
, reg_class_names
[best
], reg_class_names
[alt_class
],
1894 reg_class_names
[regno_aclass
[i
]]);
1896 regno_best_class
[i
] = best
;
1899 pref
[i
] = best_cost
> i_mem_cost
? NO_REGS
: best
;
1902 for (a
= ira_regno_allocno_map
[i
];
1904 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1906 enum reg_class aclass
= regno_aclass
[i
];
1907 int a_num
= ALLOCNO_NUM (a
);
1908 int *total_a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1909 int *a_costs
= COSTS (costs
, a_num
)->cost
;
1911 if (aclass
== NO_REGS
)
1915 /* Finding best class which is subset of the common
1917 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1918 allocno_cost
= best_cost
;
1920 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1922 rclass
= cost_classes
[k
];
1923 if (! ira_class_subset_p
[rclass
][aclass
])
1925 if (total_a_costs
[k
] < best_cost
)
1927 best_cost
= total_a_costs
[k
];
1928 allocno_cost
= a_costs
[k
];
1929 best
= (enum reg_class
) rclass
;
1931 else if (total_a_costs
[k
] == best_cost
)
1933 best
= ira_reg_class_subunion
[best
][rclass
];
1934 allocno_cost
= MAX (allocno_cost
, a_costs
[k
]);
1937 ALLOCNO_CLASS_COST (a
) = allocno_cost
;
1939 if (internal_flag_ira_verbose
> 2 && dump_file
!= NULL
1940 && (pass
== 0 || pref
[a_num
] != best
))
1942 fprintf (dump_file
, " a%d (r%d,", a_num
, i
);
1943 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1944 fprintf (dump_file
, "b%d", bb
->index
);
1946 fprintf (dump_file
, "l%d",
1947 ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1948 fprintf (dump_file
, ") best %s, allocno %s\n",
1949 reg_class_names
[best
],
1950 reg_class_names
[aclass
]);
1953 if (pass
== flag_expensive_optimizations
&& best
!= aclass
1954 && ira_class_hard_regs_num
[best
] > 0
1955 && (ira_reg_class_max_nregs
[best
][ALLOCNO_MODE (a
)]
1956 >= ira_class_hard_regs_num
[best
]))
1958 int ind
= cost_classes_ptr
->index
[aclass
];
1960 ira_assert (ind
>= 0);
1961 ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a
));
1962 ira_add_allocno_pref (a
, ira_class_hard_regs
[best
][0],
1963 (a_costs
[ind
] - ALLOCNO_CLASS_COST (a
))
1964 / (ira_register_move_cost
1965 [ALLOCNO_MODE (a
)][best
][aclass
]));
1966 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1967 if (ira_class_subset_p
[cost_classes
[k
]][best
])
1968 a_costs
[k
] = a_costs
[ind
];
1973 if (internal_flag_ira_verbose
> 4 && dump_file
)
1976 print_allocno_costs (dump_file
);
1978 print_pseudo_costs (dump_file
);
1979 fprintf (dump_file
,"\n");
1982 ira_free (regno_best_class
);
1987 /* Process moves involving hard regs to modify allocno hard register
1988 costs. We can do this only after determining allocno class. If a
1989 hard register forms a register class, then moves with the hard
1990 register are already taken into account in class costs for the
1993 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1995 int i
, freq
, src_regno
, dst_regno
, hard_regno
, a_regno
;
1997 ira_allocno_t a
, curr_a
;
1998 ira_loop_tree_node_t curr_loop_tree_node
;
1999 enum reg_class rclass
;
2004 bb
= loop_tree_node
->bb
;
2007 freq
= REG_FREQ_FROM_BB (bb
);
2010 FOR_BB_INSNS (bb
, insn
)
2012 if (!NONDEBUG_INSN_P (insn
))
2014 set
= single_set (insn
);
2015 if (set
== NULL_RTX
)
2017 dst
= SET_DEST (set
);
2018 src
= SET_SRC (set
);
2019 if (! REG_P (dst
) || ! REG_P (src
))
2021 dst_regno
= REGNO (dst
);
2022 src_regno
= REGNO (src
);
2023 if (dst_regno
>= FIRST_PSEUDO_REGISTER
2024 && src_regno
< FIRST_PSEUDO_REGISTER
)
2026 hard_regno
= src_regno
;
2027 a
= ira_curr_regno_allocno_map
[dst_regno
];
2030 else if (src_regno
>= FIRST_PSEUDO_REGISTER
2031 && dst_regno
< FIRST_PSEUDO_REGISTER
)
2033 hard_regno
= dst_regno
;
2034 a
= ira_curr_regno_allocno_map
[src_regno
];
2039 rclass
= ALLOCNO_CLASS (a
);
2040 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
2042 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
2045 a_regno
= ALLOCNO_REGNO (a
);
2046 for (curr_loop_tree_node
= ALLOCNO_LOOP_TREE_NODE (a
);
2047 curr_loop_tree_node
!= NULL
;
2048 curr_loop_tree_node
= curr_loop_tree_node
->parent
)
2049 if ((curr_a
= curr_loop_tree_node
->regno_allocno_map
[a_regno
]) != NULL
)
2050 ira_add_allocno_pref (curr_a
, hard_regno
, freq
);
2053 enum reg_class hard_reg_class
;
2056 mode
= ALLOCNO_MODE (a
);
2057 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
2058 ira_init_register_move_cost_if_necessary (mode
);
2059 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][rclass
]
2060 : ira_register_move_cost
[mode
][rclass
][hard_reg_class
]) * freq
;
2061 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
2062 ALLOCNO_CLASS_COST (a
));
2063 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
2065 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
2066 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
2067 ALLOCNO_CLASS_COST (a
) = MIN (ALLOCNO_CLASS_COST (a
),
2068 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
2073 /* After we find hard register and memory costs for allocnos, define
2074 its class and modify hard register cost because insns moving
2075 allocno to/from hard registers. */
2077 setup_allocno_class_and_costs (void)
2079 int i
, j
, n
, regno
, hard_regno
, num
;
2081 enum reg_class aclass
, rclass
;
2083 ira_allocno_iterator ai
;
2084 cost_classes_t cost_classes_ptr
;
2086 ira_assert (allocno_p
);
2087 FOR_EACH_ALLOCNO (a
, ai
)
2089 i
= ALLOCNO_NUM (a
);
2090 regno
= ALLOCNO_REGNO (a
);
2091 aclass
= regno_aclass
[regno
];
2092 cost_classes_ptr
= regno_cost_classes
[regno
];
2093 ira_assert (pref
[i
] == NO_REGS
|| aclass
!= NO_REGS
);
2094 ALLOCNO_MEMORY_COST (a
) = COSTS (costs
, i
)->mem_cost
;
2095 ira_set_allocno_class (a
, aclass
);
2096 if (aclass
== NO_REGS
)
2098 if (optimize
&& ALLOCNO_CLASS (a
) != pref
[i
])
2100 n
= ira_class_hard_regs_num
[aclass
];
2101 ALLOCNO_HARD_REG_COSTS (a
)
2102 = reg_costs
= ira_allocate_cost_vector (aclass
);
2103 for (j
= n
- 1; j
>= 0; j
--)
2105 hard_regno
= ira_class_hard_regs
[aclass
][j
];
2106 if (TEST_HARD_REG_BIT (reg_class_contents
[pref
[i
]], hard_regno
))
2107 reg_costs
[j
] = ALLOCNO_CLASS_COST (a
);
2110 rclass
= REGNO_REG_CLASS (hard_regno
);
2111 num
= cost_classes_ptr
->index
[rclass
];
2114 num
= cost_classes_ptr
->hard_regno_index
[hard_regno
];
2115 ira_assert (num
>= 0);
2117 reg_costs
[j
] = COSTS (costs
, i
)->cost
[num
];
2123 ira_traverse_loop_tree (true, ira_loop_tree_root
,
2124 process_bb_node_for_hard_reg_moves
, NULL
);
2129 /* Function called once during compiler work. */
2131 ira_init_costs_once (void)
2136 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2139 this_op_costs
[i
] = NULL
;
2144 /* Free allocated temporary cost vectors. */
2146 target_ira_int::free_ira_costs ()
2152 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2154 free (x_op_costs
[i
]);
2155 free (x_this_op_costs
[i
]);
2156 x_op_costs
[i
] = x_this_op_costs
[i
] = NULL
;
2158 free (x_temp_costs
);
2159 x_temp_costs
= NULL
;
2162 /* This is called each time register related information is
2165 ira_init_costs (void)
2169 this_target_ira_int
->free_ira_costs ();
2170 max_struct_costs_size
2171 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
2172 /* Don't use ira_allocate because vectors live through several IRA
2174 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
2175 init_cost
->mem_cost
= 1000000;
2176 for (i
= 0; i
< ira_important_classes_num
; i
++)
2177 init_cost
->cost
[i
] = 1000000;
2178 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2180 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2181 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2183 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
2188 /* Common initialization function for ira_costs and
2189 ira_set_pseudo_classes. */
2193 init_subregs_of_mode ();
2194 costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2195 * cost_elements_num
);
2196 pref_buffer
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2197 * cost_elements_num
);
2198 regno_aclass
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2200 regno_equiv_gains
= (int *) ira_allocate (sizeof (int) * max_reg_num ());
2201 memset (regno_equiv_gains
, 0, sizeof (int) * max_reg_num ());
2204 /* Common finalization function for ira_costs and
2205 ira_set_pseudo_classes. */
2209 finish_subregs_of_mode ();
2210 ira_free (regno_equiv_gains
);
2211 ira_free (regno_aclass
);
2212 ira_free (pref_buffer
);
2216 /* Entry function which defines register class, memory and hard
2217 register costs for each allocno. */
2222 cost_elements_num
= ira_allocnos_num
;
2224 total_allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2225 * ira_allocnos_num
);
2226 initiate_regno_cost_classes ();
2227 calculate_elim_costs_all_insns ();
2228 find_costs_and_classes (ira_dump_file
);
2229 setup_allocno_class_and_costs ();
2230 finish_regno_cost_classes ();
2232 ira_free (total_allocno_costs
);
2235 /* Entry function which defines classes for pseudos.
2236 Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2238 ira_set_pseudo_classes (bool define_pseudo_classes
, FILE *dump_file
)
2241 internal_flag_ira_verbose
= flag_ira_verbose
;
2242 cost_elements_num
= max_reg_num ();
2244 initiate_regno_cost_classes ();
2245 find_costs_and_classes (dump_file
);
2246 finish_regno_cost_classes ();
2247 if (define_pseudo_classes
)
2248 pseudo_classes_defined_p
= true;
2255 /* Change hard register costs for allocnos which lives through
2256 function calls. This is called only when we found all intersected
2257 calls during building allocno live ranges. */
2259 ira_tune_allocno_costs (void)
2262 int cost
, min_cost
, *reg_costs
;
2263 enum reg_class aclass
, rclass
;
2266 ira_allocno_iterator ai
;
2267 ira_allocno_object_iterator oi
;
2270 HARD_REG_SET
*crossed_calls_clobber_regs
;
2272 FOR_EACH_ALLOCNO (a
, ai
)
2274 aclass
= ALLOCNO_CLASS (a
);
2275 if (aclass
== NO_REGS
)
2277 mode
= ALLOCNO_MODE (a
);
2278 n
= ira_class_hard_regs_num
[aclass
];
2280 if (ALLOCNO_CALLS_CROSSED_NUM (a
)
2281 != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2283 ira_allocate_and_set_costs
2284 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
,
2285 ALLOCNO_CLASS_COST (a
));
2286 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2287 for (j
= n
- 1; j
>= 0; j
--)
2289 regno
= ira_class_hard_regs
[aclass
][j
];
2291 FOR_EACH_ALLOCNO_OBJECT (a
, obj
, oi
)
2293 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2294 OBJECT_CONFLICT_HARD_REGS
2303 rclass
= REGNO_REG_CLASS (regno
);
2305 crossed_calls_clobber_regs
2306 = &(ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
));
2307 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2308 *crossed_calls_clobber_regs
)
2309 && (ira_hard_reg_set_intersection_p (regno
, mode
,
2311 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2312 cost
+= (ALLOCNO_CALL_FREQ (a
)
2313 * (ira_memory_move_cost
[mode
][rclass
][0]
2314 + ira_memory_move_cost
[mode
][rclass
][1]));
2315 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2316 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
2317 + ira_memory_move_cost
[mode
][rclass
][1])
2319 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
2321 if (INT_MAX
- cost
< reg_costs
[j
])
2322 reg_costs
[j
] = INT_MAX
;
2324 reg_costs
[j
] += cost
;
2325 if (min_cost
> reg_costs
[j
])
2326 min_cost
= reg_costs
[j
];
2329 if (min_cost
!= INT_MAX
)
2330 ALLOCNO_CLASS_COST (a
) = min_cost
;
2332 /* Some targets allow pseudos to be allocated to unaligned sequences
2333 of hard registers. However, selecting an unaligned sequence can
2334 unnecessarily restrict later allocations. So increase the cost of
2335 unaligned hard regs to encourage the use of aligned hard regs. */
2337 const int nregs
= ira_reg_class_max_nregs
[aclass
][ALLOCNO_MODE (a
)];
2341 ira_allocate_and_set_costs
2342 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
, ALLOCNO_CLASS_COST (a
));
2343 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2344 for (j
= n
- 1; j
>= 0; j
--)
2346 regno
= ira_non_ordered_class_hard_regs
[aclass
][j
];
2347 if ((regno
% nregs
) != 0)
2349 int index
= ira_class_hard_reg_index
[aclass
][regno
];
2350 ira_assert (index
!= -1);
2351 reg_costs
[index
] += ALLOCNO_FREQ (a
);
2359 /* Add COST to the estimated gain for eliminating REGNO with its
2360 equivalence. If COST is zero, record that no such elimination is
2364 ira_adjust_equiv_reg_cost (unsigned regno
, int cost
)
2367 regno_equiv_gains
[regno
] = 0;
2369 regno_equiv_gains
[regno
] += cost
;
2373 ira_costs_c_finalize (void)
2375 this_target_ira_int
->free_ira_costs ();