| blob | bce843031f4dadd7dc74cc9512b39682d60ff6b3 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
100 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
127 /* Number of attempts to combine instructions in this function. */
131 /* Number of attempts that got as far as substitution in this function. */
135 /* Number of instructions combined with added SETs in this function. */
139 /* Number of instructions combined in this function. */
143 /* Totals over entire compilation. */
147 /* combine_instructions may try to replace the right hand side of the
148 second instruction with the value of an associated REG_EQUAL note
149 before throwing it at try_combine. That is problematic when there
150 is a REG_DEAD note for a register used in the old right hand side
151 and can cause distribute_notes to do wrong things. This is the
152 second instruction if it has been so modified, null otherwise. */
156 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
160 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
163 \f
165 /* Record last point of death of (hard or pseudo) register n. */
168 /* Record last point of modification of (hard or pseudo) register n. */
171 /* The next group of fields allows the recording of the last value assigned
172 to (hard or pseudo) register n. We use this information to see if an
173 operation being processed is redundant given a prior operation performed
174 on the register. For example, an `and' with a constant is redundant if
175 all the zero bits are already known to be turned off.
177 We use an approach similar to that used by cse, but change it in the
178 following ways:
180 (1) We do not want to reinitialize at each label.
181 (2) It is useful, but not critical, to know the actual value assigned
182 to a register. Often just its form is helpful.
184 Therefore, we maintain the following fields:
186 last_set_value the last value assigned
187 last_set_label records the value of label_tick when the
188 register was assigned
189 last_set_table_tick records the value of label_tick when a
190 value using the register is assigned
191 last_set_invalid set to nonzero when it is not valid
192 to use the value of this register in some
193 register's value
195 To understand the usage of these tables, it is important to understand
196 the distinction between the value in last_set_value being valid and
197 the register being validly contained in some other expression in the
198 table.
200 (The next two parameters are out of date).
202 reg_stat[i].last_set_value is valid if it is nonzero, and either
203 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
205 Register I may validly appear in any expression returned for the value
206 of another register if reg_n_sets[i] is 1. It may also appear in the
207 value for register J if reg_stat[j].last_set_invalid is zero, or
208 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
210 If an expression is found in the table containing a register which may
211 not validly appear in an expression, the register is replaced by
212 something that won't match, (clobber (const_int 0)). */
214 /* Record last value assigned to (hard or pseudo) register n. */
216 rtx last_set_value;
218 /* Record the value of label_tick when an expression involving register n
219 is placed in last_set_value. */
223 /* Record the value of label_tick when the value for register n is placed in
224 last_set_value. */
228 /* These fields are maintained in parallel with last_set_value and are
229 used to store the mode in which the register was last set, the bits
230 that were known to be zero when it was last set, and the number of
231 sign bits copies it was known to have when it was last set. */
237 /* Set nonzero if references to register n in expressions should not be
238 used. last_set_invalid is set nonzero when this register is being
239 assigned to and last_set_table_tick == label_tick. */
243 /* Some registers that are set more than once and used in more than one
244 basic block are nevertheless always set in similar ways. For example,
245 a QImode register may be loaded from memory in two places on a machine
246 where byte loads zero extend.
248 We record in the following fields if a register has some leading bits
249 that are always equal to the sign bit, and what we know about the
250 nonzero bits of a register, specifically which bits are known to be
251 zero.
253 If an entry is zero, it means that we don't know anything special. */
259 /* Record the value of the label_tick when the last truncation
260 happened. The field truncated_to_mode is only valid if
261 truncation_label == label_tick. */
265 /* Record the last truncation seen for this register. If truncation
266 is not a nop to this mode we might be able to save an explicit
267 truncation if we know that value already contains a truncated
268 value. */
276 /* One plus the highest pseudo for which we track REG_N_SETS.
277 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
278 but during combine_split_insns new pseudos can be created. As we don't have
279 updated DF information in that case, it is hard to initialize the array
280 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
281 so instead of growing the arrays, just assume all newly created pseudos
282 during combine might be set multiple times. */
286 /* Record the luid of the last insn that invalidated memory
287 (anything that writes memory, and subroutine calls, but not pushes). */
291 /* Record the luid of the last CALL_INSN
292 so we can tell whether a potential combination crosses any calls. */
296 /* When `subst' is called, this is the insn that is being modified
297 (by combining in a previous insn). The PATTERN of this insn
298 is still the old pattern partially modified and it should not be
299 looked at, but this may be used to examine the successors of the insn
300 to judge whether a simplification is valid. */
304 /* This is the lowest LUID that `subst' is currently dealing with.
305 get_last_value will not return a value if the register was set at or
306 after this LUID. If not for this mechanism, we could get confused if
307 I2 or I1 in try_combine were an insn that used the old value of a register
308 to obtain a new value. In that case, we might erroneously get the
309 new value of the register when we wanted the old one. */
313 /* This contains any hard registers that are used in newpat; reg_dead_at_p
314 must consider all these registers to be always live. */
318 /* This is an insn to which a LOG_LINKS entry has been added. If this
319 insn is the earlier than I2 or I3, combine should rescan starting at
320 that location. */
324 /* Basic block in which we are performing combines. */
328 \f
329 /* Length of the currently allocated uid_insn_cost array. */
333 /* The following array records the insn_rtx_cost for every insn
334 in the instruction stream. */
338 /* The following array records the LOG_LINKS for every insn in the
339 instruction stream as struct insn_link pointers. */
345 };
349 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
350 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
352 #define FOR_EACH_LOG_LINK(L, INSN) \
353 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
355 /* Links for LOG_LINKS are allocated from this obstack. */
359 /* Allocate a link. */
363 {
371 }
373 /* Incremented for each basic block. */
377 /* Reset to label_tick for each extended basic block in scanning order. */
381 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
382 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
386 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
387 be safely used. It is zero while computing them and after combine has
388 completed. This former test prevents propagating values based on
389 previously set values, which can be incorrect if a variable is modified
390 in a loop. */
394 \f
395 /* Record one modification to rtl structure
396 to be undone by storing old_contents into *where. */
400 struct undo
401 {
406 };
408 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
409 num_undo says how many are currently recorded.
411 other_insn is nonzero if we have modified some other insn in the process
412 of working on subst_insn. It must be verified too. */
414 struct undobuf
415 {
419 };
423 /* Number of times the pseudo being substituted for
424 was found and replaced. */
429 machine_mode,
433 machine_mode,
505 \f
507 /* It is not safe to use ordinary gen_lowpart in combine.
508 See comments in gen_lowpart_for_combine. */
509 #undef RTL_HOOKS_GEN_LOWPART
510 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
512 /* Our implementation of gen_lowpart never emits a new pseudo. */
513 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
514 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
516 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
517 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
519 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
520 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
522 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
523 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
527 \f
528 /* Convenience wrapper for the canonicalize_comparison target hook.
529 Target hooks cannot use enum rtx_code. */
533 {
537 }
539 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
540 PATTERN can not be split. Otherwise, it returns an insn sequence.
541 This is a wrapper around split_insns which ensures that the
542 reg_stat vector is made larger if the splitter creates a new
543 register. */
547 {
556 }
558 /* This is used by find_single_use to locate an rtx in LOC that
559 contains exactly one use of DEST, which is typically either a REG
560 or CC0. It returns a pointer to the innermost rtx expression
561 containing DEST. Appearances of DEST that are being used to
562 totally replace it are not counted. */
566 {
575 {
579 CASE_CONST_ANY:
584 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
585 of a REG that occupies all of the REG, the insn uses DEST if
586 it is mentioned in the destination or the source. Otherwise, we
587 need just check the source. */
607 }
609 /* If it wasn't one of the common cases above, check each expression and
610 vector of this code. Look for a unique usage of DEST. */
614 {
616 {
621 else
627 /* Duplicate usage. */
629 }
631 {
635 {
641 else
648 }
649 }
650 }
653 }
656 /* See if DEST, produced in INSN, is used only a single time in the
657 sequel. If so, return a pointer to the innermost rtx expression in which
658 it is used.
660 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
662 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
663 care about REG_DEAD notes or LOG_LINKS.
665 Otherwise, we find the single use by finding an insn that has a
666 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
667 only referenced once in that insn, we know that it must be the first
668 and last insn referencing DEST. */
672 {
673 basic_block bb;
679 {
689 }
699 {
705 {
710 }
711 }
714 }
715 \f
716 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
717 insn. The substitution can be undone by undo_all. If INTO is already
718 set to NEWVAL, do not record this change. Because computing NEWVAL might
719 also call SUBST, we have to compute it before we put anything into
720 the undo table. */
722 static void
724 {
731 /* We'd like to catch as many invalid transformations here as
732 possible. Unfortunately, there are way too many mode changes
733 that are perfectly valid, so we'd waste too much effort for
734 little gain doing the checks here. Focus on catching invalid
735 transformations involving integer constants. */
738 {
739 /* Sanity check that we're replacing oldval with a CONST_INT
740 that is a valid sign-extension for the original mode. */
744 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
745 CONST_INT is not valid, because after the replacement, the
746 original mode would be gone. Unfortunately, we can't tell
747 when do_SUBST is called to replace the operand thereof, so we
748 perform this test on oldval instead, checking whether an
749 invalid replacement took place before we got here. */
754 }
758 else
767 }
769 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
771 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
772 for the value of a HOST_WIDE_INT value (including CONST_INT) is
773 not safe. */
775 static void
777 {
786 else
795 }
797 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
799 /* Similar to SUBST, but just substitute the mode. This is used when
800 changing the mode of a pseudo-register, so that any other
801 references to the entry in the regno_reg_rtx array will change as
802 well. */
804 static void
806 {
815 else
824 }
826 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
828 #if !HAVE_cc0
829 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
831 static void
833 {
842 else
851 }
853 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
854 #endif
855 \f
856 /* Subroutine of try_combine. Determine whether the replacement patterns
857 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
858 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
859 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
860 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
861 of all the instructions can be estimated and the replacements are more
862 expensive than the original sequence. */
864 static bool
867 {
872 /* Lookup the original insn_rtx_costs. */
877 {
880 {
884 }
885 else
886 {
890 }
891 }
892 else
893 {
896 }
898 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
899 correct that. */
904 /* Calculate the replacement insn_rtx_costs. */
907 {
911 }
912 else
913 {
916 }
919 {
925 {
928 }
929 else
931 }
933 /* Disallow this combination if both new_cost and old_cost are greater than
934 zero, and new_cost is greater than old cost. */
938 {
957 else
959 }
964 /* Update the uid_insn_cost array with the replacement costs. */
968 {
972 }
975 }
978 /* Delete any insns that copy a register to itself. */
980 static void
982 {
984 basic_block bb;
987 {
989 {
992 {
997 }
998 }
999 }
1000 }
1002 \f
1003 /* Return false if we do not want to (or cannot) combine DEF. */
1004 static bool
1006 {
1007 /* Do not consider if it is pre/post modification in MEM. */
1013 /* Do not combine frame pointer adjustments. */
1016 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1019 #endif
1025 }
1027 /* Return false if we do not want to (or cannot) combine USE. */
1028 static bool
1030 {
1031 /* Do not consider the usage of the stack pointer by function call. */
1036 }
1038 /* Fill in log links field for all insns. */
1040 static void
1042 {
1043 basic_block bb;
1050 /* Pass through each block from the end, recording the uses of each
1051 register and establishing log links when def is encountered.
1052 Note that we do not clear next_use array in order to save time,
1053 so we have to test whether the use is in the same basic block as def.
1055 There are a few cases below when we do not consider the definition or
1056 usage -- these are taken from original flow.c did. Don't ask me why it is
1057 done this way; I don't know and if it works, I don't want to know. */
1060 {
1062 {
1066 /* Log links are created only once. */
1070 {
1086 /* flow.c claimed:
1088 We don't build a LOG_LINK for hard registers contained
1089 in ASM_OPERANDs. If these registers get replaced,
1090 we might wind up changing the semantics of the insn,
1091 even if reload can make what appear to be valid
1092 assignments later. */
1097 /* Don't add duplicate links between instructions. */
1106 }
1111 }
1112 }
1115 }
1117 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1118 true if we found a LOG_LINK that proves that A feeds B. This only works
1119 if there are no instructions between A and B which could have a link
1120 depending on A, since in that case we would not record a link for B.
1121 We also check the implicit dependency created by a cc0 setter/user
1122 pair. */
1124 static bool
1126 {
1134 }
1135 \f
1136 /* Main entry point for combiner. F is the first insn of the function.
1137 NREGS is the first unused pseudo-reg number.
1139 Return nonzero if the combiner has turned an indirect jump
1140 instruction into a direct jump. */
1141 static int
1143 {
1145 #if HAVE_cc0
1147 #endif
1150 basic_block last_bb;
1170 /* Allocate array for insn info. */
1178 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1179 problems when, for example, we have j <<= 1 in a loop. */
1184 /* Scan all SETs and see if we can deduce anything about what
1185 bits are known to be zero for some registers and how many copies
1186 of the sign bit are known to exist for those registers.
1188 Also set any known values so that we can use it while searching
1189 for what bits are known to be set. */
1192 /* Allow the entry block and the first block to fall into the same EBB.
1193 Conceptually the incoming promotions are assigned to the entry block. */
1198 {
1203 label_tick++;
1211 {
1212 #ifdef AUTO_INC_DEC
1213 rtx links;
1214 #endif
1220 insn);
1223 #ifdef AUTO_INC_DEC
1227 insn);
1228 #endif
1230 /* Record the current insn_rtx_cost of this instruction. */
1233 optimize_this_for_speed_p);
1237 }
1238 }
1242 /* Now scan all the insns in forward order. */
1250 {
1256 label_tick++;
1266 {
1280 /* See if we know about function return values before this
1281 insn based upon SUBREG flags. */
1284 /* See if we can find hardregs and subreg of pseudos in
1285 narrower modes. This could help turning TRUNCATEs
1286 into SUBREGs. */
1289 /* Try this insn with each insn it links back to. */
1295 {
1298 }
1300 /* Try each sequence of three linked insns ending with this one. */
1304 {
1307 /* If the linked insn has been replaced by a note, then there
1308 is no point in pursuing this chain any further. */
1316 {
1319 }
1320 }
1322 #if HAVE_cc0
1323 /* Try to combine a jump insn that uses CC0
1324 with a preceding insn that sets CC0, and maybe with its
1325 logical predecessor as well.
1326 This is how we make decrement-and-branch insns.
1327 We need this special code because data flow connections
1328 via CC0 do not get entered in LOG_LINKS. */
1334 {
1345 }
1347 /* Do the same for an insn that explicitly references CC0. */
1354 {
1365 }
1367 /* Finally, see if any of the insns that this insn links to
1368 explicitly references CC0. If so, try this insn, that insn,
1369 and its predecessor if it sets CC0. */
1381 #endif
1383 /* Try combining an insn with two different insns whose results it
1384 uses. */
1394 {
1397 }
1399 /* Try four-instruction combinations. */
1402 {
1406 /* If the linked insn has been replaced by a note, then there
1407 is no point in pursuing this chain any further. */
1412 {
1416 /* I0 -> I1 -> I2 -> I3. */
1422 {
1425 }
1426 /* I0, I1 -> I2, I2 -> I3. */
1433 {
1436 }
1437 }
1440 {
1444 /* I0 -> I2; I1, I2 -> I3. */
1450 {
1453 }
1454 /* I0 -> I1; I1, I2 -> I3. */
1460 {
1463 }
1464 }
1465 }
1467 /* Try this insn with each REG_EQUAL note it links back to. */
1469 {
1475 /* Avoid using a register that may already been marked
1476 dead by an earlier instruction. */
1481 {
1482 /* Temporarily replace the set's source with the
1483 contents of the REG_EQUAL note. The insn will
1484 be deleted or recognized by try_combine. */
1492 last_combined_insn);
1495 {
1498 }
1500 }
1501 }
1506 retry:
1507 ;
1508 }
1509 }
1516 /* Clean up. */
1522 {
1525 {
1528 }
1530 }
1540 /* Make recognizer allow volatile MEMs again. */
1544 }
1546 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1548 static void
1550 {
1556 }
1557 \f
1558 /* Set up any promoted values for incoming argument registers. */
1560 static void
1562 {
1563 tree arg;
1568 {
1573 /* Only continue if the incoming argument is in a register. */
1577 /* Determine, if possible, whether all call sites of the current
1578 function lie within the current compilation unit. (This does
1579 take into account the exporting of a function via taking its
1580 address, and so forth.) */
1583 /* The mode and signedness of the argument before any promotions happen
1584 (equal to the mode of the pseudo holding it at that stage). */
1588 /* The mode and signedness of the argument after any source language and
1589 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1593 /* The mode and signedness of the argument as it is actually passed,
1594 see assign_parm_setup_reg in function.c. */
1598 /* The mode of the register in which the argument is being passed. */
1601 /* Eliminate sign extensions in the callee when:
1602 (a) A mode promotion has occurred; */
1605 /* (b) The mode of the register is the same as the mode of
1606 the argument as it is passed; */
1609 /* (c) There's no language level extension; */
1611 ;
1612 /* (c.1) All callers are from the current compilation unit. If that's
1613 the case we don't have to rely on an ABI, we only have to know
1614 what we're generating right now, and we know that we will do the
1615 mode1 to mode2 promotion with the given sign. */
1618 /* (c.2) The combination of the two promotions is useful. This is
1619 true when the signs match, or if the first promotion is unsigned.
1620 In the later case, (sign_extend (zero_extend x)) is the same as
1621 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1627 /* Record that the value was promoted from mode1 to mode3,
1628 so that any sign extension at the head of the current
1629 function may be eliminated. */
1633 }
1634 }
1636 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1637 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1638 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1639 because some machines (maybe most) will actually do the sign-extension and
1640 this is the conservative approach.
1642 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1643 kludge. */
1645 static rtx
1647 {
1655 }
1656 #endif
1658 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1659 and SET. */
1661 static void
1663 rtx x)
1664 {
1673 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1677 #endif
1679 /* Don't call nonzero_bits if it cannot change anything. */
1681 {
1686 }
1688 /* Don't call num_sign_bit_copies if it cannot change anything. */
1690 {
1693 {
1697 }
1700 }
1701 }
1703 /* Called via note_stores. If X is a pseudo that is narrower than
1704 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1706 If we are setting only a portion of X and we can't figure out what
1707 portion, assume all bits will be used since we don't know what will
1708 be happening.
1710 Similarly, set how many bits of X are known to be copies of the sign bit
1711 at all locations in the function. This is the smallest number implied
1712 by any set of X. */
1714 static void
1716 {
1721 /* If this register is undefined at the start of the file, we can't
1722 say what its contents were. */
1723 && ! REGNO_REG_SET_P
1726 {
1730 {
1734 }
1736 /* If this register is being initialized using itself, and the
1737 register is uninitialized in this basic block, and there are
1738 no LOG_LINKS which set the register, then part of the
1739 register is uninitialized. In that case we can't assume
1740 anything about the number of nonzero bits.
1742 ??? We could do better if we checked this in
1743 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1744 could avoid making assumptions about the insn which initially
1745 sets the register, while still using the information in other
1746 insns. We would have to be careful to check every insn
1747 involved in the combination. */
1753 {
1760 {
1764 }
1765 }
1767 /* If this is a complex assignment, see if we can convert it into a
1768 simple assignment. */
1771 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1772 set what we know about X. */
1778 else
1779 {
1782 }
1783 }
1784 }
1785 \f
1786 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1787 optionally insns that were previously combined into I3 or that will be
1788 combined into the merger of INSN and I3. The order is PRED, PRED2,
1789 INSN, SUCC, SUCC2, I3.
1791 Return 0 if the combination is not allowed for any reason.
1793 If the combination is allowed, *PDEST will be set to the single
1794 destination of INSN and *PSRC to the single source, and this function
1795 will return 1. */
1797 static int
1801 {
1806 #ifdef AUTO_INC_DEC
1807 rtx link;
1808 #endif
1813 {
1815 {
1820 }
1825 }
1829 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1830 or a PARALLEL consisting of such a SET and CLOBBERs.
1832 If INSN has CLOBBER parallel parts, ignore them for our processing.
1833 By definition, these happen during the execution of the insn. When it
1834 is merged with another insn, all bets are off. If they are, in fact,
1835 needed and aren't also supplied in I3, they may be added by
1836 recog_for_combine. Otherwise, it won't match.
1838 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1839 note.
1841 Get the source and destination of INSN. If more than one, can't
1842 combine. */
1848 {
1850 {
1854 {
1855 /* This is important to combine floating point insns
1856 for the SH4 port. */
1858 /* Combining an isolated USE doesn't make sense.
1859 We depend here on combinable_i3pat to reject them. */
1860 /* The code below this loop only verifies that the inputs of
1861 the SET in INSN do not change. We call reg_set_between_p
1862 to verify that the REG in the USE does not change between
1863 I3 and INSN.
1864 If the USE in INSN was for a pseudo register, the matching
1865 insn pattern will likely match any register; combining this
1866 with any other USE would only be safe if we knew that the
1867 used registers have identical values, or if there was
1868 something to tell them apart, e.g. different modes. For
1869 now, we forgo such complicated tests and simply disallow
1870 combining of USES of pseudo registers with any other USE. */
1873 {
1878 do
1879 {
1889 }
1891 }
1894 /* We can ignore CLOBBERs. */
1899 /* Ignore SETs whose result isn't used but not those that
1900 have side-effects. */
1906 /* If we have already found a SET, this is a second one and
1907 so we cannot combine with this insn. */
1915 /* Anything else means we can't combine. */
1917 }
1918 }
1921 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1922 so don't do anything with it. */
1925 }
1926 else
1932 /* The simplification in expand_field_assignment may call back to
1933 get_last_value, so set safe guard here. */
1939 /* Do not eliminate user-specified register if it is in an
1940 asm input because we may break the register asm usage defined
1941 in GCC manual if allow to do so.
1942 Be aware that this may cover more cases than we expect but this
1943 should be harmless. */
1948 /* Don't eliminate a store in the stack pointer. */
1950 /* Don't combine with an insn that sets a register to itself if it has
1951 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1953 /* Can't merge an ASM_OPERANDS. */
1955 /* Can't merge a function call. */
1957 /* Don't eliminate a function call argument. */
1963 /* Don't substitute into an incremented register. */
1967 /* Don't substitute into a non-local goto, this confuses CFG. */
1969 /* Make sure that DEST is not used after SUCC but before I3. */
1970 || (!all_adjacent
1971 && ((succ2
1975 /* Make sure that the value that is to be substituted for the register
1976 does not use any registers whose values alter in between. However,
1977 If the insns are adjacent, a use can't cross a set even though we
1978 think it might (this can happen for a sequence of insns each setting
1979 the same destination; last_set of that register might point to
1980 a NOTE). If INSN has a REG_EQUIV note, the register is always
1981 equivalent to the memory so the substitution is valid even if there
1982 are intervening stores. Also, don't move a volatile asm or
1983 UNSPEC_VOLATILE across any other insns. */
1984 || (! all_adjacent
1990 /* Don't combine across a CALL_INSN, because that would possibly
1991 change whether the life span of some REGs crosses calls or not,
1992 and it is a pain to update that information.
1993 Exception: if source is a constant, moving it later can't hurt.
1994 Accept that as a special case. */
1998 /* DEST must either be a REG or CC0. */
2000 {
2001 /* If register alignment is being enforced for multi-word items in all
2002 cases except for parameters, it is possible to have a register copy
2003 insn referencing a hard register that is not allowed to contain the
2004 mode being copied and which would not be valid as an operand of most
2005 insns. Eliminate this problem by not combining with such an insn.
2007 Also, on some machines we don't want to extend the life of a hard
2008 register. */
2013 /* Don't extend the life of a hard register unless it is
2014 user variable (if we have few registers) or it can't
2015 fit into the desired register (meaning something special
2016 is going on).
2017 Also avoid substituting a return register into I3, because
2018 reload can't handle a conflict with constraints of other
2019 inputs. */
2023 }
2031 {
2034 /* If the clobber represents an earlyclobber operand, we must not
2035 substitute an expression containing the clobbered register.
2036 As we do not analyze the constraint strings here, we have to
2037 make the conservative assumption. However, if the register is
2038 a fixed hard reg, the clobber cannot represent any operand;
2039 we leave it up to the machine description to either accept or
2040 reject use-and-clobber patterns. */
2046 }
2048 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2049 or not), reject, unless nothing volatile comes between it and I3 */
2052 {
2053 /* Make sure neither succ nor succ2 contains a volatile reference. */
2058 /* We'll check insns between INSN and I3 below. */
2059 }
2061 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2062 to be an explicit register variable, and was chosen for a reason. */
2068 /* If INSN contains volatile references (specifically volatile MEMs),
2069 we cannot combine across any other volatile references.
2070 Even if INSN doesn't contain volatile references, any intervening
2071 volatile insn might affect machine state. */
2074 ? volatile_refs_p
2081 /* If INSN contains an autoincrement or autodecrement, make sure that
2082 register is not used between there and I3, and not already used in
2083 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2084 Also insist that I3 not be a jump; if it were one
2085 and the incremented register were spilled, we would lose. */
2087 #ifdef AUTO_INC_DEC
2102 #endif
2104 /* Don't combine an insn that follows a CC0-setting insn.
2105 An insn that uses CC0 must not be separated from the one that sets it.
2106 We do, however, allow I2 to follow a CC0-setting insn if that insn
2107 is passed as I1; in that case it will be deleted also.
2108 We also allow combining in this case if all the insns are adjacent
2109 because that would leave the two CC0 insns adjacent as well.
2110 It would be more logical to test whether CC0 occurs inside I1 or I2,
2111 but that would be much slower, and this ought to be equivalent. */
2114 {
2119 }
2121 /* If we get here, we have passed all the tests and the combination is
2122 to be allowed. */
2128 }
2129 \f
2130 /* LOC is the location within I3 that contains its pattern or the component
2131 of a PARALLEL of the pattern. We validate that it is valid for combining.
2133 One problem is if I3 modifies its output, as opposed to replacing it
2134 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2135 doing so would produce an insn that is not equivalent to the original insns.
2137 Consider:
2139 (set (reg:DI 101) (reg:DI 100))
2140 (set (subreg:SI (reg:DI 101) 0) <foo>)
2142 This is NOT equivalent to:
2144 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2145 (set (reg:DI 101) (reg:DI 100))])
2147 Not only does this modify 100 (in which case it might still be valid
2148 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2150 We can also run into a problem if I2 sets a register that I1
2151 uses and I1 gets directly substituted into I3 (not via I2). In that
2152 case, we would be getting the wrong value of I2DEST into I3, so we
2153 must reject the combination. This case occurs when I2 and I1 both
2154 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2155 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2156 of a SET must prevent combination from occurring. The same situation
2157 can occur for I0, in which case I0_NOT_IN_SRC is set.
2159 Before doing the above check, we first try to expand a field assignment
2160 into a set of logical operations.
2162 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2163 we place a register that is both set and used within I3. If more than one
2164 such register is detected, we fail.
2166 Return 1 if the combination is valid, zero otherwise. */
2168 static int
2171 {
2175 {
2180 rtx subdest;
2187 /* Check for the case where I3 modifies its output, as discussed
2188 above. We don't want to prevent pseudos from being combined
2189 into the address of a MEM, so only prevent the combination if
2190 i1 or i2 set the same MEM. */
2200 /* This is the same test done in can_combine_p except we can't test
2201 all_adjacent; we don't have to, since this instruction will stay
2202 in place, thus we are not considering increasing the lifetime of
2203 INNER_DEST.
2205 Also, if this insn sets a function argument, combining it with
2206 something that might need a spill could clobber a previous
2207 function argument; the all_adjacent test in can_combine_p also
2208 checks this; here, we do a more specific test for this case. */
2218 /* If DEST is used in I3, it is being killed in this insn, so
2219 record that for later. We have to consider paradoxical
2220 subregs here, since they kill the whole register, but we
2221 ignore partial subregs, STRICT_LOW_PART, etc.
2222 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2223 STACK_POINTER_REGNUM, since these are always considered to be
2224 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2234 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2236 #endif
2241 {
2246 }
2247 }
2250 {
2257 }
2260 }
2261 \f
2262 /* Return 1 if X is an arithmetic expression that contains a multiplication
2263 and division. We don't count multiplications by powers of two here. */
2265 static int
2267 {
2269 {
2285 }
2286 }
2287 \f
2288 /* Determine whether INSN can be used in a combination. Return nonzero if
2289 not. This is used in try_combine to detect early some cases where we
2290 can't perform combinations. */
2292 static int
2294 {
2295 rtx set;
2298 /* If this isn't really an insn, we can't do anything.
2299 This can occur when flow deletes an insn that it has merged into an
2300 auto-increment address. */
2304 /* Never combine loads and stores involving hard regs that are likely
2305 to be spilled. The register allocator can usually handle such
2306 reg-reg moves by tying. If we allow the combiner to make
2307 substitutions of likely-spilled regs, reload might die.
2308 As an exception, we allow combinations involving fixed regs; these are
2309 not available to the register allocator so there's no risk involved. */
2330 }
2332 struct likely_spilled_retval_info
2333 {
2336 };
2338 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2339 hard registers that are known to be written to / clobbered in full. */
2340 static void
2342 {
2359 else
2362 }
2364 /* Return nonzero iff part of the return value is live during INSN, and
2365 it is likely spilled. This can happen when more than one insn is needed
2366 to copy the return value, e.g. when we consider to combine into the
2367 second copy insn for a complex value. */
2369 static int
2371 {
2373 rtx reg;
2376 /* We assume here that no machine mode needs more than
2377 32 hard registers when the value overlaps with a register
2378 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2393 /* Disregard parts of the return value that are set later. */
2402 /* Check if any of the (probably) live return value registers is
2403 likely spilled. */
2404 nregs --;
2405 do
2406 {
2412 }
2414 /* Adjust INSN after we made a change to its destination.
2416 Changing the destination can invalidate notes that say something about
2417 the results of the insn and a LOG_LINK pointing to the insn. */
2419 static void
2421 {
2422 /* For notes, be conservative and simply remove them. */
2425 /* The new insn will have a destination that was previously the destination
2426 of an insn just above it. Call distribute_links to make a LOG_LINK from
2427 the next use of that destination. */
2443 }
2445 /* Return TRUE if combine can reuse reg X in mode MODE.
2446 ADDED_SETS is nonzero if the original set is still required. */
2447 static bool
2449 {
2456 /* Allow hard registers if the new mode is legal, and occupies no more
2457 registers than the old mode. */
2462 /* Or a pseudo that is only used once. */
2465 && !added_sets
2467 }
2470 /* Check whether X, the destination of a set, refers to part of
2471 the register specified by REG. */
2473 static bool
2475 {
2476 /* Check that reg is an integer mode register. */
2487 }
2489 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2490 Note that the INSN should be deleted *after* removing dead edges, so
2491 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2492 but not for a (set (pc) (label_ref FOO)). */
2494 static void
2496 {
2504 {
2509 /* Remove barriers from the footer if there are any. */
2512 {
2515 else
2519 }
2522 }
2523 }
2525 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2526 by an arbitrary number of CLOBBERs. */
2527 static bool
2529 {
2547 }
2549 #if !HAVE_cc0
2550 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2551 CLOBBERs), can be split into individual SETs in that order, without
2552 changing semantics. */
2553 static bool
2555 {
2563 {
2572 }
2575 }
2576 #endif
2578 /* Try to combine the insns I0, I1 and I2 into I3.
2579 Here I0, I1 and I2 appear earlier than I3.
2580 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2581 I3.
2583 If we are combining more than two insns and the resulting insn is not
2584 recognized, try splitting it into two insns. If that happens, I2 and I3
2585 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2586 Otherwise, I0, I1 and I2 are pseudo-deleted.
2588 Return 0 if the combination does not work. Then nothing is changed.
2589 If we did the combination, return the insn at which combine should
2590 resume scanning.
2592 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2593 new direct jump instruction.
2595 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2596 been I3 passed to an earlier try_combine within the same basic
2597 block. */
2602 {
2603 /* New patterns for I3 and I2, respectively. */
2607 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2608 dead. */
2610 /* Total number of SETs to put into I3. */
2612 /* Nonzero if I2's or I1's body now appears in I3. */
2614 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2616 /* Contains I3 if the destination of I3 is used in its source, which means
2617 that the old life of I3 is being killed. If that usage is placed into
2618 I2 and not in I3, a REG_DEAD note must be made. */
2620 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2622 /* Copy of SET_SRC of I1 and I0, if needed. */
2624 /* Set if I2DEST was reused as a scratch register. */
2626 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2628 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2633 /* Notes that must be added to REG_NOTES in I3 and I2. */
2635 /* Notes that we substituted I3 into I2 instead of the normal case. */
2637 /* Notes that I1, I2 or I3 is a MULT operation. */
2644 rtx temp_expr;
2647 rtx new_other_notes;
2650 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2651 never be). */
2655 /* Only try four-insn combinations when there's high likelihood of
2656 success. Look for simple insns, such as loads of constants or
2657 binary operations involving a constant. */
2659 {
2669 {
2672 rtx src;
2677 {
2680 }
2682 ngood++;
2685 nshift++;
2686 }
2688 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2689 are likely manipulating its value. Ideally we'll be able to combine
2690 all four insns into a bitfield insertion of some kind.
2692 Note the source in I0 might be inside a sign/zero extension and the
2693 memory modes in I0 and I3 might be different. So extract the address
2694 from the destination of I3 and search for it in the source of I0.
2696 In the event that there's a match but the source/dest do not actually
2697 refer to the same memory, the worst that happens is we try some
2698 combinations that we wouldn't have otherwise. */
2700 /* Ensure the source of SET0 is a MEM, possibly buried inside
2701 an extension. */
2707 /* Ensure the destination of SET3 is a MEM. */
2709 /* Would it be better to extract the base address for the MEM
2710 in SET3 and look for that? I don't have cases where it matters
2711 but I could envision such cases. */
2717 }
2719 /* Exit early if one of the insns involved can't be used for
2720 combinations. */
2731 combine_attempts++;
2734 /* Reset the hard register usage information. */
2738 {
2745 else
2748 }
2750 /* If multiple insns feed into one of I2 or I3, they can be in any
2751 order. To simplify the code below, reorder them in sequence. */
2761 /* First check for one important special case that the code below will
2762 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2763 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2764 we may be able to replace that destination with the destination of I3.
2765 This occurs in the common code where we compute both a quotient and
2766 remainder into a structure, in which case we want to do the computation
2767 directly into the structure to avoid register-register copies.
2769 Note that this case handles both multiple sets in I2 and also cases
2770 where I2 has a number of CLOBBERs inside the PARALLEL.
2772 We make very conservative checks below and only try to handle the
2773 most common cases of this. For example, we only handle the case
2774 where I2 and I3 are adjacent to avoid making difficult register
2775 usage tests. */
2783 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2784 below would need to check what is inside (and reg_overlap_mentioned_p
2785 doesn't support those codes anyway). Don't allow those destinations;
2786 the resulting insn isn't likely to be recognized anyway. */
2792 {
2795 /* Make sure that the destination of I3,
2796 which we are going to substitute into one output of I2,
2797 is not used within another output of I2. We must avoid making this:
2798 (parallel [(set (mem (reg 69)) ...)
2799 (set (reg 69) ...)])
2800 which is not well-defined as to order of actions.
2801 (Besides, reload can't handle output reloads for this.)
2803 The problem can also happen if the dest of I3 is a memory ref,
2804 if another dest in I2 is an indirect memory ref. */
2812 /* Make sure this PARALLEL is not an asm. We do not allow combining
2813 that usually (see can_combine_p), so do not here either. */
2823 {
2824 combine_merges++;
2834 /* Replace the dest in I2 with our dest and make the resulting
2835 insn the new pattern for I3. Then skip to where we validate
2836 the pattern. Everything was set up above. */
2841 }
2842 }
2844 /* If I2 is setting a pseudo to a constant and I3 is setting some
2845 sub-part of it to another constant, merge them by making a new
2846 constant. */
2853 {
2859 {
2862 {
2868 }
2869 }
2870 else
2871 {
2876 }
2879 {
2880 /* If this is the low part, we're done. */
2882 ;
2883 /* Handle the case where inner is twice the size of outer. */
2887 /* Otherwise give up for now. */
2888 else
2890 }
2893 {
2897 wide_int o
2902 combine_merges++;
2909 /* Replace the source in I2 with the new constant and make the
2910 resulting insn the new pattern for I3. Then skip to where we
2911 validate the pattern. Everything was set up above. */
2917 /* The dest of I3 has been replaced with the dest of I2. */
2920 }
2921 }
2923 #if !HAVE_cc0
2924 /* If we have no I1 and I2 looks like:
2925 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2926 (set Y OP)])
2927 make up a dummy I1 that is
2928 (set Y OP)
2929 and change I2 to be
2930 (set (reg:CC X) (compare:CC Y (const_int 0)))
2932 (We can ignore any trailing CLOBBERs.)
2934 This undoes a previous combination and allows us to match a branch-and-
2935 decrement insn. */
2947 {
2948 /* We make I1 with the same INSN_UID as I2. This gives it
2949 the same DF_INSN_LUID for value tracking. Our fake I1 will
2950 never appear in the insn stream so giving it the same INSN_UID
2951 as I2 will not cause a problem. */
2964 }
2966 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2967 make those two SETs separate I1 and I2 insns, and make an I0 that is
2968 the original I1. */
2974 {
2975 /* If there is no I1, there is no I0 either. */
2978 /* We make I1 with the same INSN_UID as I2. This gives it
2979 the same DF_INSN_LUID for value tracking. Our fake I1 will
2980 never appear in the insn stream so giving it the same INSN_UID
2981 as I2 will not cause a problem. */
2989 }
2990 #endif
2992 /* Verify that I2 and I1 are valid for combining. */
2998 {
3001 }
3003 /* Record whether I2DEST is used in I2SRC and similarly for the other
3004 cases. Knowing this will help in register status updating below. */
3015 /* For the earlier insns, determine which of the subsequent ones they
3016 feed. */
3023 /* Ensure that I3's pattern can be the destination of combines. */
3029 {
3032 }
3034 /* See if any of the insns is a MULT operation. Unless one is, we will
3035 reject a combination that is, since it must be slower. Be conservative
3036 here. */
3044 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3045 We used to do this EXCEPT in one case: I3 has a post-inc in an
3046 output operand. However, that exception can give rise to insns like
3047 mov r3,(r3)+
3048 which is a famous insn on the PDP-11 where the value of r3 used as the
3049 source was model-dependent. Avoid this sort of thing. */
3051 #if 0
3057 /* It's not the exception. */
3058 #endif
3059 #ifdef AUTO_INC_DEC
3060 {
3061 rtx link;
3067 {
3070 }
3071 }
3072 #endif
3074 /* See if the SETs in I1 or I2 need to be kept around in the merged
3075 instruction: whenever the value set there is still needed past I3.
3076 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3078 For the SET in I1, we have two cases: if I1 and I2 independently feed
3079 into I3, the set in I1 needs to be kept around unless I1DEST dies
3080 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3081 in I1 needs to be kept around unless I1DEST dies or is set in either
3082 I2 or I3. The same considerations apply to I0. */
3089 else
3097 else
3100 /* We are about to copy insns for the case where they need to be kept
3101 around. Check that they can be copied in the merged instruction. */
3107 {
3110 }
3112 /* If the set in I2 needs to be kept around, we must make a copy of
3113 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3114 PATTERN (I2), we are only substituting for the original I1DEST, not into
3115 an already-substituted copy. This also prevents making self-referential
3116 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3117 I2DEST. */
3120 {
3123 else
3125 }
3128 {
3131 else
3133 }
3136 {
3139 else
3141 }
3143 combine_merges++;
3145 /* Substitute in the latest insn for the regs set by the earlier ones. */
3151 /* Many machines that don't use CC0 have insns that can both perform an
3152 arithmetic operation and set the condition code. These operations will
3153 be represented as a PARALLEL with the first element of the vector
3154 being a COMPARE of an arithmetic operation with the constant zero.
3155 The second element of the vector will set some pseudo to the result
3156 of the same arithmetic operation. If we simplify the COMPARE, we won't
3157 match such a pattern and so will generate an extra insn. Here we test
3158 for this case, where both the comparison and the operation result are
3159 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3160 I2SRC. Later we will make the PARALLEL that contains I2. */
3166 {
3167 rtx newpat_dest;
3181 {
3186 }
3188 /* Do the rest only if op1 is const0_rtx, which may be the
3189 result of simplification. */
3191 {
3192 /* If a single use of the CC is found, prepare to modify it
3193 when SELECT_CC_MODE returns a new CC-class mode, or when
3194 the above simplify_compare_const() returned a new comparison
3195 operator. undobuf.other_insn is assigned the CC use insn
3196 when modifying it. */
3198 {
3199 #ifdef SELECT_CC_MODE
3200 machine_mode new_mode
3205 {
3210 else
3211 {
3214 }
3215 }
3216 #endif
3217 /* Cases for modifying the CC-using comparison. */
3219 /* ??? Do we need to verify the zero rtx? */
3221 {
3222 /* Replace cc_use_loc with entire new RTX. */
3227 }
3229 {
3230 /* Just replace the CC reg with a new mode. */
3233 }
3234 }
3236 /* Now we modify the current newpat:
3237 First, SET_DEST(newpat) is updated if the CC mode has been
3238 altered. For targets without SELECT_CC_MODE, this should be
3239 optimized away. */
3242 /* This is always done to propagate i2src into newpat. */
3245 /* Create new version of i2pat if needed; the below PARALLEL
3246 creation needs this to work correctly. */
3250 }
3251 }
3254 {
3255 /* It is possible that the source of I2 or I1 may be performing
3256 an unneeded operation, such as a ZERO_EXTEND of something
3257 that is known to have the high part zero. Handle that case
3258 by letting subst look at the inner insns.
3260 Another way to do this would be to have a function that tries
3261 to simplify a single insn instead of merging two or more
3262 insns. We don't do this because of the potential of infinite
3263 loops and because of the potential extra memory required.
3264 However, doing it the way we are is a bit of a kludge and
3265 doesn't catch all cases.
3267 But only do this if -fexpensive-optimizations since it slows
3268 things down and doesn't usually win.
3270 This is not done in the COMPARE case above because the
3271 unmodified I2PAT is used in the PARALLEL and so a pattern
3272 with a modified I2SRC would not match. */
3275 {
3276 /* Pass pc_rtx so no substitutions are done, just
3277 simplifications. */
3279 {
3282 }
3286 }
3291 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3292 copy of I2SRC each time we substitute it, in order to avoid creating
3293 self-referential RTL when we will be substituting I1SRC for I1DEST
3294 later. Likewise if I0 feeds into I2, either directly or indirectly
3295 through I1, and I0DEST is in I0SRC. */
3302 /* Record whether I2's body now appears within I3's body. */
3304 }
3306 /* If we already got a failure, don't try to do more. Otherwise, try to
3307 substitute I1 if we have it. */
3310 {
3311 /* Check that an autoincrement side-effect on I1 has not been lost.
3312 This happens if I1DEST is mentioned in I2 and dies there, and
3313 has disappeared from the new pattern. */
3315 && i1_feeds_i2_n
3318 /* Before we can do this substitution, we must redo the test done
3319 above (see detailed comments there) that ensures I1DEST isn't
3320 mentioned in any SETs in NEWPAT that are field assignments. */
3323 {
3326 }
3331 /* If the following substitution will modify I1SRC, make a copy of it
3332 for the case where it is substituted for I1DEST in I2PAT later. */
3336 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3337 copy of I1SRC each time we substitute it, in order to avoid creating
3338 self-referential RTL when we will be substituting I0SRC for I0DEST
3339 later. */
3344 /* Record whether I1's body now appears within I3's body. */
3346 }
3348 /* Likewise for I0 if we have it. */
3351 {
3358 {
3361 }
3363 /* If the following substitution will modify I0SRC, make a copy of it
3364 for the case where it is substituted for I0DEST in I1PAT later. */
3367 /* And a copy for I0DEST in I2PAT substitution. */
3376 }
3378 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3379 to count all the ways that I2SRC and I1SRC can be used. */
3390 /* Fail if we tried to make a new register. */
3392 /* Fail if we couldn't do something and have a CLOBBER. */
3394 /* Fail if this new pattern is a MULT and we didn't have one before
3395 at the outer level. */
3398 {
3401 }
3403 /* If the actions of the earlier insns must be kept
3404 in addition to substituting them into the latest one,
3405 we must make a new PARALLEL for the latest insn
3406 to hold additional the SETs. */
3409 {
3411 combine_extras++;
3414 {
3420 }
3421 else
3422 {
3427 }
3433 {
3439 }
3441 {
3450 }
3451 }
3453 validate_replacement:
3455 /* Note which hard regs this insn has as inputs. */
3458 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3459 consider splitting this pattern, we might need these clobbers. */
3462 {
3468 }
3470 /* We have recognized nothing yet. */
3473 /* See if this is a PARALLEL of two SETs where one SET's destination is
3474 a register that is unused and this isn't marked as an instruction that
3475 might trap in an EH region. In that case, we just need the other SET.
3476 We prefer this over the PARALLEL.
3478 This can occur when simplifying a divmod insn. We *must* test for this
3479 case here because the code below that splits two independent SETs doesn't
3480 handle this case correctly when it updates the register status.
3482 It's pointless doing this if we originally had two sets, one from
3483 i3, and one from i2. Combining then splitting the parallel results
3484 in the original i2 again plus an invalid insn (which we delete).
3485 The net effect is only to move instructions around, which makes
3486 debug info less accurate. */
3491 {
3502 {
3505 }
3514 {
3520 }
3524 }
3526 /* Is the result of combination a valid instruction? */
3530 /* If we were combining three insns and the result is a simple SET
3531 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3532 insns. There are two ways to do this. It can be split using a
3533 machine-specific method (like when you have an addition of a large
3534 constant) or by combine in the function find_split_point. */
3538 {
3542 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3543 use I2DEST as a scratch register will help. In the latter case,
3544 convert I2DEST to the mode of the source of NEWPAT if we can. */
3548 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3549 inputs of NEWPAT. */
3551 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3552 possible to try that as a scratch reg. This would require adding
3553 more code to make it work though. */
3556 {
3559 /* First try to split using the original register as a
3560 scratch register. */
3564 i2dest)));
3567 /* If that didn't work, try changing the mode of I2DEST if
3568 we can. */
3573 {
3575 rtx ni2dest;
3579 else
3580 {
3583 }
3585 parallel = (gen_rtx_PARALLEL
3589 ni2dest))));
3594 {
3602 }
3603 }
3606 }
3608 /* If recog_for_combine has discarded clobbers, try to use them
3609 again for the split. */
3611 {
3614 }
3617 {
3622 }
3626 {
3636 /* If I2 or I3 has multiple SETs, we won't know how to track
3637 register status, so don't use these insns. If I2's destination
3638 is used between I2 and I3, we also can't use these insns. */
3648 /* It is possible that both insns now set the destination of I3.
3649 If so, we must show an extra use of it. */
3652 {
3671 }
3672 }
3674 /* If we can split it and use I2DEST, go ahead and see if that
3675 helps things be recognized. Verify that none of the registers
3676 are set between I2 and I3. */
3680 /* We need I2DEST in the proper mode. If it is a hard register
3681 or the only use of a pseudo, we can change its mode.
3682 Make sure we don't change a hard register to have a mode that
3683 isn't valid for it, or change the number of registers. */
3690 /* We can't overwrite I2DEST if its value is still used by
3691 NEWPAT. */
3693 {
3702 /* *SPLIT may be part of I2SRC, so make sure we have the
3703 original expression around for later debug processing.
3704 We should not need I2SRC any more in other cases. */
3707 else
3710 /* Get NEWDEST as a register in the proper mode. We have already
3711 validated that we can do this. */
3713 {
3716 else
3717 {
3720 }
3721 }
3723 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3724 an ASHIFT. This can occur if it was inside a PLUS and hence
3725 appeared to be a memory address. This is a kludge. */
3730 {
3733 /* Update split_code because we may not have a multiply
3734 anymore. */
3736 }
3738 /* Similarly for (plus (mult FOO (const_int pow2))). */
3744 {
3748 /* Update split_code because we may not have a multiply
3749 anymore. */
3751 }
3753 #ifdef INSN_SCHEDULING
3754 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3755 be written as a ZERO_EXTEND. */
3757 {
3758 #ifdef LOAD_EXTEND_OP
3759 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3760 what it really is. */
3765 else
3766 #endif
3769 }
3770 #endif
3772 /* Attempt to split binary operators using arithmetic identities. */
3776 {
3783 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3785 {
3790 }
3791 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3798 {
3804 /* Split both "((X op Y) op X) op Y" and
3805 "((X op Y) op Y) op X" as "T op T" where T is
3806 "X op Y". */
3809 {
3814 }
3815 /* Split "((X op X) op Y) op Y)" as "T op T" where
3816 T is "X op Y". */
3818 {
3824 }
3825 }
3826 }
3829 {
3832 }
3836 /* recog_for_combine might have added CLOBBERs to newi2pat.
3837 Make sure NEWPAT does not depend on the clobbered regs. */
3841 {
3844 {
3847 }
3848 }
3850 /* If the split point was a MULT and we didn't have one before,
3851 don't use one now. */
3854 }
3855 }
3857 /* Check for a case where we loaded from memory in a narrow mode and
3858 then sign extended it, but we need both registers. In that case,
3859 we have a PARALLEL with both loads from the same memory location.
3860 We can split this into a load from memory followed by a register-register
3861 copy. This saves at least one insn, more if register allocation can
3862 eliminate the copy.
3864 We cannot do this if the destination of the first assignment is a
3865 condition code register or cc0. We eliminate this case by making sure
3866 the SET_DEST and SET_SRC have the same mode.
3868 We cannot do this if the destination of the second assignment is
3869 a register that we have already assumed is zero-extended. Similarly
3870 for a SUBREG of such a register. */
3905 {
3906 rtx ni2dest;
3920 }
3922 /* Similarly, check for a case where we have a PARALLEL of two independent
3923 SETs but we started with three insns. In this case, we can do the sets
3924 as two separate insns. This case occurs when some SET allows two
3925 other insns to combine, but the destination of that SET is still live.
3927 Also do this if we started with two insns and (at least) one of the
3928 resulting sets is a noop; this noop will be deleted later. */
3947 {
3951 /* Normally, it doesn't matter which of the two is done first,
3952 but the one that references cc0 can't be the second, and
3953 one which uses any regs/memory set in between i2 and i3 can't
3954 be first. The PARALLEL might also have been pre-existing in i3,
3955 so we need to make sure that we won't wrongly hoist a SET to i2
3956 that would conflict with a death note present in there. */
3964 /* If I3 is a jump, ensure that set0 is a jump so that
3965 we do not create invalid RTL. */
3967 )
3968 {
3971 }
3979 /* If I3 is a jump, ensure that set1 is a jump so that
3980 we do not create invalid RTL. */
3982 )
3983 {
3986 }
3987 else
3988 {
3991 }
3996 {
3997 /* recog_for_combine might have added CLOBBERs to newi2pat.
3998 Make sure NEWPAT does not depend on the clobbered regs. */
4000 {
4003 {
4006 {
4009 }
4010 }
4011 }
4014 }
4015 }
4017 /* If it still isn't recognized, fail and change things back the way they
4018 were. */
4020 /* Is the result a reasonable ASM_OPERANDS? */
4022 {
4025 }
4027 /* If we had to change another insn, make sure it is valid also. */
4029 {
4037 {
4040 }
4041 }
4043 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4044 they are adjacent to each other or not. */
4046 {
4050 {
4053 }
4054 }
4056 /* Only allow this combination if insn_rtx_costs reports that the
4057 replacement instructions are cheaper than the originals. */
4059 {
4062 }
4065 {
4070 {
4075 /* Temporarily revert mode back. */
4079 {
4080 /* If we used i2dest as a scratch register with a
4081 different mode, substitute it for the original
4082 i2src while its original mode is temporarily
4083 restored, and then clear i2scratch so that we don't
4084 do it again later. */
4086 this_basic_block);
4088 /* Put back the new mode. */
4090 }
4091 else
4092 {
4097 {
4100 }
4101 else
4102 {
4109 }
4111 /* We're dealing with a reg that changed mode but not
4112 meaning, so we want to turn it into a subreg for
4113 the new mode. However, because of REG sharing and
4114 because its mode had already changed, we have to do
4115 it in two steps. First, replace any debug uses of
4116 reg, with its original mode temporarily restored,
4117 with this copy we have created; then, replace the
4118 copy with the SUBREG of the original shared reg,
4119 once again changed to the new mode. */
4121 this_basic_block);
4125 this_basic_block);
4126 }
4127 }
4128 }
4130 /* If we will be able to accept this, we have made a
4131 change to the destination of I3. This requires us to
4132 do a few adjustments. */
4135 {
4138 }
4140 /* We now know that we can do this combination. Merge the insns and
4141 update the status of registers and LOG_LINKS. */
4144 {
4149 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4150 ensure that they are still valid. Then add any non-duplicate
4151 notes added by recog_for_combine. */
4153 {
4163 }
4167 NULL_RTX);
4168 }
4171 {
4174 rtx ni2dest;
4176 /* I3 now uses what used to be its destination and which is now
4177 I2's destination. This requires us to do a few adjustments. */
4181 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4182 so we still will.
4184 However, some later insn might be using I2's dest and have
4185 a LOG_LINK pointing at I3. We must remove this link.
4186 The simplest way to remove the link is to point it at I1,
4187 which we know will be a NOTE. */
4189 /* newi2pat is usually a SET here; however, recog_for_combine might
4190 have added some clobbers. */
4193 else
4200 {
4202 {
4208 }
4209 }
4210 }
4212 {
4217 /* Compute which registers we expect to eliminate. newi2pat may be setting
4218 either i3dest or i2dest, so we must check it. */
4221 || !i2dest_killed
4223 /* For i1, we need to compute both local elimination and global
4224 elimination information with respect to newi2pat because i1dest
4225 may be the same as i3dest, in which case newi2pat may be setting
4226 i1dest. Global information is used when distributing REG_DEAD
4227 note for i2 and i3, in which case it does matter if newi2pat sets
4228 i1dest or not.
4230 Local information is used when distributing REG_DEAD note for i1,
4231 in which case it doesn't matter if newi2pat sets i1dest or not.
4232 See PR62151, if we have four insns combination:
4233 i0: r0 <- i0src
4234 i1: r1 <- i1src (using r0)
4235 REG_DEAD (r0)
4236 i2: r0 <- i2src (using r1)
4237 i3: r3 <- i3src (using r0)
4238 ix: using r0
4239 From i1's point of view, r0 is eliminated, no matter if it is set
4240 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4241 should be discarded.
4243 Note local information only affects cases in forms like "I1->I2->I3",
4244 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4245 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4246 i0dest anyway. */
4248 || !i1dest_killed
4253 /* Same case as i1. */
4260 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4261 clear them. */
4269 /* Ensure that we do not have something that should not be shared but
4270 occurs multiple times in the new insns. Check this by first
4271 resetting all the `used' flags and then copying anything is shared. */
4295 {
4302 {
4303 /* I2SRC must still be meaningful at this point. Some splitting
4304 operations can invalidate I2SRC, but those operations do not
4305 apply to calls. */
4308 }
4316 }
4321 /* We had one special case above where I2 had more than one set and
4322 we replaced a destination of one of those sets with the destination
4323 of I3. In that case, we have to update LOG_LINKS of insns later
4324 in this basic block. Note that this (expensive) case is rare.
4326 Also, in this case, we must pretend that all REG_NOTEs for I2
4327 actually came from I3, so that REG_UNUSED notes from I2 will be
4328 properly handled. */
4331 {
4340 temp_insn
4350 {
4355 }
4356 else
4359 }
4367 {
4370 this_basic_block);
4373 }
4374 else
4375 {
4378 this_basic_block);
4380 }
4383 {
4388 this_basic_block);
4390 }
4393 {
4398 this_basic_block);
4400 }
4402 /* Get death notes for everything that is now used in either I3 or
4403 I2 and used to die in a previous insn. If we built two new
4404 patterns, move from I1 to I2 then I2 to I3 so that we get the
4405 proper movement on registers that I2 modifies. */
4411 else
4417 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4434 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4435 know these are REG_UNUSED and want them to go to the desired insn,
4436 so we always pass it as i3. */
4440 NULL_RTX);
4444 NULL_RTX);
4446 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4447 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4448 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4449 in that case, it might delete I2. Similarly for I2 and I1.
4450 Show an additional death due to the REG_DEAD note we make here. If
4451 we discard it in distribute_notes, we will decrement it again. */
4454 {
4459 else
4462 }
4465 {
4470 else
4473 }
4476 {
4481 else
4484 }
4487 {
4492 else
4495 }
4503 {
4508 /* The insn that used to set this register doesn't exist, and
4509 this life of the register may not exist either. See if one of
4510 I3's links points to an insn that sets I2DEST. If it does,
4511 that is now the last known value for I2DEST. If we don't update
4512 this and I2 set the register to a value that depended on its old
4513 contents, we will get confused. If this insn is used, thing
4514 will be set correctly in combine_instructions. */
4522 /* If the reg formerly set in I2 died only once and that was in I3,
4523 zero its use count so it won't make `reload' do any work. */
4526 && ! i2dest_in_i2src
4529 }
4532 {
4545 && ! i1dest_in_i1src
4548 }
4551 {
4564 && ! i0dest_in_i0src
4567 }
4569 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4570 been made to this insn. The order is important, because newi2pat
4571 can affect nonzero_bits of newpat. */
4575 }
4578 {
4580 {
4583 }
4585 }
4588 {
4590 {
4593 }
4595 }
4598 {
4600 {
4603 }
4605 }
4608 {
4610 {
4613 }
4615 }
4618 {
4620 {
4623 }
4625 }
4627 /* Set new_direct_jump_p if a new return or simple jump instruction
4628 has been created. Adjust the CFG accordingly. */
4630 {
4634 }
4639 {
4642 }
4644 /* A noop might also need cleaning up of CFG, if it comes from the
4645 simplification of a jump. */
4650 {
4653 }
4660 {
4663 }
4665 combine_successes++;
4672 else
4674 }
4675 \f
4676 /* Get a marker for undoing to the current state. */
4680 {
4682 }
4684 /* Undo the modifications up to the marker. */
4686 static void
4688 {
4692 {
4697 {
4712 }
4716 }
4719 }
4721 /* Undo all the modifications recorded in undobuf. */
4723 static void
4725 {
4727 }
4729 /* We've committed to accepting the changes we made. Move all
4730 of the undos to the free list. */
4732 static void
4734 {
4738 {
4742 }
4744 }
4745 \f
4746 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4747 where we have an arithmetic expression and return that point. LOC will
4748 be inside INSN.
4750 try_combine will call this function to see if an insn can be split into
4751 two insns. */
4755 {
4764 /* First special-case some codes. */
4766 {
4768 #ifdef INSN_SCHEDULING
4769 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4770 point. */
4773 #endif
4777 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4778 using LO_SUM and HIGH. */
4781 {
4789 }
4791 /* If we have a PLUS whose second operand is a constant and the
4792 address is not valid, perhaps will can split it up using
4793 the machine-specific way to split large constants. We use
4794 the first pseudo-reg (one of the virtual regs) as a placeholder;
4795 it will not remain in the result. */
4800 {
4803 subst_insn);
4805 /* This should have produced two insns, each of which sets our
4806 placeholder. If the source of the second is a valid address,
4807 we can make put both sources together and make a split point
4808 in the middle. */
4821 && memory_address_addr_space_p
4824 {
4828 /* Replace the placeholder in SRC2 with SRC1. If we can
4829 find where in SRC2 it was placed, that can become our
4830 split point and we can replace this address with SRC2.
4831 Just try two obvious places. */
4842 {
4845 }
4846 }
4848 /* If that didn't work, perhaps the first operand is complex and
4849 needs to be computed separately, so make a split point there.
4850 This will occur on machines that just support REG + CONST
4851 and have a constant moved through some previous computation. */
4857 }
4859 /* If we have a PLUS whose first operand is complex, try computing it
4860 separately by making a split there. */
4871 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4872 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4873 we need to put the operand into a register. So split at that
4874 point. */
4884 /* See if we can split SET_SRC as it stands. */
4889 /* See if we can split SET_DEST as it stands. */
4894 /* See if this is a bitfield assignment with everything constant. If
4895 so, this is an IOR of an AND, so split it into that. */
4905 {
4911 unsigned HOST_WIDE_INT mask
4913 rtx or_mask;
4922 else
4923 {
4929 or_mask));
4930 }
4937 }
4939 /* Otherwise, see if this is an operation that we can split into two.
4940 If so, try to split that. */
4944 {
4946 /* If we are AND'ing with a large constant that is only a single
4947 bit and the result is only being used in a context where we
4948 need to know if it is zero or nonzero, replace it with a bit
4949 extraction. This will avoid the large constant, which might
4950 have taken more than one insn to make. If the constant were
4951 not a valid argument to the AND but took only one insn to make,
4952 this is no worse, but if it took more than one insn, it will
4953 be better. */
4963 {
4968 {
4971 }
4972 }
4976 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4977 is known to be on, this can be converted into a NEG of a shift. */
4983 {
4995 }
5001 /* We can't optimize if either mode is a partial integer
5002 mode as we don't know how many bits are significant
5003 in those modes. */
5017 {
5025 }
5030 }
5034 {
5037 /* For unsigned, we have a choice of a shift followed by an
5038 AND or two shifts. Use two shifts for field sizes where the
5039 constant might be too large. We assume here that we can
5040 always at least get 8-bit constants in an AND insn, which is
5041 true for every current RISC. */
5044 {
5045 unsigned HOST_WIDE_INT mask
5049 gen_rtx_LSHIFTRT
5057 }
5058 else
5059 {
5061 gen_rtx_fmt_ee
5072 }
5073 }
5075 /* See if this is a simple operation with a constant as the second
5076 operand. It might be that this constant is out of range and hence
5077 could be used as a split point. */
5085 /* Finally, see if this is a simple operation with its first operand
5086 not in a register. The operation might require this operand in a
5087 register, so return it as a split point. We can always do this
5088 because if the first operand were another operation, we would have
5089 already found it as a split point. */
5098 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5099 it is better to write this as (not (ior A B)) so we can split it.
5100 Similarly for IOR. */
5102 {
5110 }
5112 /* Many RISC machines have a large set of logical insns. If the
5113 second operand is a NOT, put it first so we will try to split the
5114 other operand first. */
5116 {
5120 }
5125 /* Canonicalization can produce (minus A (mult B C)), where C is a
5126 constant. It may be better to try splitting (plus (mult B -C) A)
5127 instead if this isn't a multiply by a power of two. */
5131 {
5139 mode)),
5142 }
5144 /* Split at a multiply-accumulate instruction. However if this is
5145 the SET_SRC, we likely do not have such an instruction and it's
5146 worthless to try this split. */
5155 }
5157 /* Otherwise, select our actions depending on our rtx class. */
5159 {
5165 /* ... fall through ... */
5173 /* ... fall through ... */
5175 /* Some machines have (and (shift ...) ...) insns. If X is not
5176 an AND, but XEXP (X, 0) is, use it as our split point. */
5186 /* Otherwise, we don't have a split point. */
5188 }
5189 }
5190 \f
5191 /* Throughout X, replace FROM with TO, and return the result.
5192 The result is TO if X is FROM;
5193 otherwise the result is X, but its contents may have been modified.
5194 If they were modified, a record was made in undobuf so that
5195 undo_all will (among other things) return X to its original state.
5197 If the number of changes necessary is too much to record to undo,
5198 the excess changes are not made, so the result is invalid.
5199 The changes already made can still be undone.
5200 undobuf.num_undo is incremented for such changes, so by testing that
5201 the caller can tell whether the result is valid.
5203 `n_occurrences' is incremented each time FROM is replaced.
5205 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5207 IN_COND is nonzero if we are at the top level of a condition.
5209 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5210 by copying if `n_occurrences' is nonzero. */
5212 static rtx
5214 {
5219 rtx new_rtx;
5221 /* Two expressions are equal if they are identical copies of a shared
5222 RTX or if they are both registers with the same register number
5223 and mode. */
5225 #define COMBINE_RTX_EQUAL_P(X,Y) \
5226 ((X) == (Y) \
5227 || (REG_P (X) && REG_P (Y) \
5228 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5230 /* Do not substitute into clobbers of regs -- this will never result in
5231 valid RTL. */
5236 {
5237 n_occurrences++;
5239 }
5241 /* If X and FROM are the same register but different modes, they
5242 will not have been seen as equal above. However, the log links code
5243 will make a LOG_LINKS entry for that case. If we do nothing, we
5244 will try to rerecognize our original insn and, when it succeeds,
5245 we will delete the feeding insn, which is incorrect.
5247 So force this insn not to match in this (rare) case. */
5252 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5253 of which may contain things that can be combined. */
5257 /* It is possible to have a subexpression appear twice in the insn.
5258 Suppose that FROM is a register that appears within TO.
5259 Then, after that subexpression has been scanned once by `subst',
5260 the second time it is scanned, TO may be found. If we were
5261 to scan TO here, we would find FROM within it and create a
5262 self-referent rtl structure which is completely wrong. */
5266 /* Parallel asm_operands need special attention because all of the
5267 inputs are shared across the arms. Furthermore, unsharing the
5268 rtl results in recognition failures. Failure to handle this case
5269 specially can result in circular rtl.
5271 Solve this by doing a normal pass across the first entry of the
5272 parallel, and only processing the SET_DESTs of the subsequent
5273 entries. Ug. */
5278 {
5281 /* If this substitution failed, this whole thing fails. */
5289 {
5295 {
5298 /* If this substitution failed, this whole thing fails. */
5304 }
5305 }
5306 }
5307 else
5308 {
5312 /* We don't need to process a SET_DEST that is a register, CC0,
5313 or PC, so set up to skip this common case. All other cases
5314 where we want to suppress replacing something inside a
5315 SET_SRC are handled via the IN_DEST operand. */
5322 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5323 constant. */
5328 {
5330 {
5333 {
5335 {
5338 n_occurrences++;
5339 }
5340 else
5341 {
5343 unique_copy);
5345 /* If this substitution failed, this whole thing
5346 fails. */
5350 }
5353 }
5354 }
5356 {
5357 /* If this is a register being set, ignore it. */
5364 ;
5367 {
5368 /* In general, don't install a subreg involving two
5369 modes not tieable. It can worsen register
5370 allocation, and can even make invalid reload
5371 insns, since the reg inside may need to be copied
5372 from in the outside mode, and that may be invalid
5373 if it is an fp reg copied in integer mode.
5375 We allow two exceptions to this: It is valid if
5376 it is inside another SUBREG and the mode of that
5377 SUBREG and the mode of the inside of TO is
5378 tieable and it is valid if X is a SET that copies
5379 FROM to CC0. */
5387 #if HAVE_cc0
5389 #endif
5390 )
5402 n_occurrences++;
5403 }
5404 else
5405 /* If we are in a SET_DEST, suppress most cases unless we
5406 have gone inside a MEM, in which case we want to
5407 simplify the address. We assume here that things that
5408 are actually part of the destination have their inner
5409 parts in the first expression. This is true for SUBREG,
5410 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5411 things aside from REG and MEM that should appear in a
5412 SET_DEST. */
5414 (((in_dest
5420 unique_copy);
5422 /* If we found that we will have to reject this combination,
5423 indicate that by returning the CLOBBER ourselves, rather than
5424 an expression containing it. This will speed things up as
5425 well as prevent accidents where two CLOBBERs are considered
5426 to be equal, thus producing an incorrect simplification. */
5432 {
5440 }
5443 {
5447 }
5448 else
5450 }
5451 }
5452 }
5454 /* Check if we are loading something from the constant pool via float
5455 extension; in this case we would undo compress_float_constant
5456 optimization and degenerate constant load to an immediate value. */
5460 {
5464 }
5466 /* Try to simplify X. If the simplification changed the code, it is likely
5467 that further simplification will help, so loop, but limit the number
5468 of repetitions that will be performed. */
5471 {
5472 /* If X is sufficiently simple, don't bother trying to do anything
5473 with it. */
5482 /* We no longer know the original mode of operand 0 since we
5483 have changed the form of X) */
5485 }
5488 }
5489 \f
5490 /* Simplify X, a piece of RTL. We just operate on the expression at the
5491 outer level; call `subst' to simplify recursively. Return the new
5492 expression.
5494 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5495 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5496 of a condition. */
5498 static rtx
5501 {
5504 rtx temp;
5507 /* If this is a commutative operation, put a constant last and a complex
5508 expression first. We don't need to do this for comparisons here. */
5511 {
5515 }
5517 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5518 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5519 things. Check for cases where both arms are testing the same
5520 condition.
5522 Don't do anything if all operands are very simple. */
5535 {
5540 /* If everything is a comparison, what we have is highly unlikely
5541 to be simpler, so don't use it. */
5544 {
5551 /* Simplify the alternative arms; this may collapse the true and
5552 false arms to store-flag values. Be careful to use copy_rtx
5553 here since true_rtx or false_rtx might share RTL with x as a
5554 result of the if_then_else_cond call above. */
5558 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5559 is unlikely to be simpler. */
5562 {
5565 /* Restarting if we generate a store-flag expression will cause
5566 us to loop. Just drop through in this case. */
5568 /* If the result values are STORE_FLAG_VALUE and zero, we can
5569 just make the comparison operation. */
5580 /* Likewise, we can make the negate of a comparison operation
5581 if the result values are - STORE_FLAG_VALUE and zero. */
5589 mode);
5600 mode);
5601 else
5604 mode,
5605 VOIDmode,
5606 cond,
5607 cop1),
5612 }
5613 }
5614 }
5616 /* Try to fold this expression in case we have constants that weren't
5617 present before. */
5620 {
5628 {
5631 {
5635 }
5638 }
5651 }
5654 {
5659 }
5661 /* First see if we can apply the inverse distributive law. */
5664 {
5668 }
5670 /* If CODE is an associative operation not otherwise handled, see if we
5671 can associate some operands. This can win if they are constants or
5672 if they are logically related (i.e. (a & b) & a). */
5678 {
5680 {
5684 rtx inner;
5686 /* Make sure we pass the constant operand if any as the second
5687 one if this is a commutative operation. */
5689 {
5693 }
5699 /* For commutative operations, try the other pair if that one
5700 didn't simplify. */
5702 {
5707 }
5711 }
5712 }
5714 /* A little bit of algebraic simplification here. */
5716 {
5718 /* Ensure that our address has any ASHIFTs converted to MULT in case
5719 address-recognizing predicates are called later. */
5728 /* See if this can be moved to simplify_subreg. */
5731 /* Don't call gen_lowpart if the inner mode
5732 is VOIDmode and we cannot simplify it, as SUBREG without
5733 inner mode is invalid. */
5740 {
5741 rtx temp;
5747 /* If op is known to have all lower bits zero, the result is zero. */
5757 }
5759 /* Don't change the mode of the MEM if that would change the meaning
5760 of the address. */
5767 /* Note that we cannot do any narrowing for non-constants since
5768 we might have been counting on using the fact that some bits were
5769 zero. We now do this in the SET. */
5776 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5777 replaced by (lshiftrt X C). This will convert
5778 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5786 /* If X has only a single bit that might be nonzero, say, bit I, convert
5787 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5788 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5789 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5790 or a SUBREG of one since we'd be making the expression more
5791 complex if it was just a register. */
5797 {
5798 rtx temp1 = simplify_shift_const
5804 /* If all we did was surround TEMP with the two shifts, we
5805 haven't improved anything, so don't use it. Otherwise,
5806 we are better off with TEMP1. */
5811 }
5815 /* We can't handle truncation to a partial integer mode here
5816 because we don't know the real bitsize of the partial
5817 integer mode. */
5826 /* We can truncate a constant value and return it. */
5830 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5831 whose value is a comparison can be replaced with a subreg if
5832 STORE_FLAG_VALUE permits. */
5841 /* (const (const X)) can become (const X). Do it this way rather than
5842 returning the inner CONST since CONST can be shared with a
5843 REG_EQUAL note. */
5849 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5850 can add in an offset. find_split_point will split this address up
5851 again if it doesn't match. */
5858 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5859 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5860 bit-field and can be replaced by either a sign_extend or a
5861 sign_extract. The `and' may be a zero_extend and the two
5862 <c>, -<c> constants may be reversed. */
5877 return simplify_shift_const
5884 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5885 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5886 the bitsize of the mode - 1. This allows simplification of
5887 "a = (b & 8) == 0;" */
5899 /* If we are adding two things that have no bits in common, convert
5900 the addition into an IOR. This will often be further simplified,
5901 for example in cases like ((a & 1) + (a & 2)), which can
5902 become a & 3. */
5907 {
5908 /* Try to simplify the expression further. */
5912 /* If we could, great. If not, do not go ahead with the IOR
5913 replacement, since PLUS appears in many special purpose
5914 address arithmetic instructions. */
5922 }
5926 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5927 (and <foo> (const_int pow2-1)) */
5937 /* If we have (mult (plus A B) C), apply the distributive law and then
5938 the inverse distributive law to see if things simplify. This
5939 occurs mostly in addresses, often when unrolling loops. */
5942 {
5946 }
5948 /* Try simplify a*(b/c) as (a*b)/c. */
5951 {
5957 }
5961 /* If this is a divide by a power of two, treat it as a shift if
5962 its first operand is a shift. */
5980 /* If the first operand is a condition code, we can't do anything
5981 with it. */
5985 {
5993 /* Simplify our comparison, if possible. */
5996 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5997 if only the low-order bit is possibly nonzero in X (such as when
5998 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5999 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6000 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6001 (plus X 1).
6003 Remove any ZERO_EXTRACT we made when thinking this was a
6004 comparison. It may now be simpler to use, e.g., an AND. If a
6005 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6006 the call to make_compound_operation in the SET case.
6008 Don't apply these optimizations if the caller would
6009 prefer a comparison rather than a value.
6010 E.g., for the condition in an IF_THEN_ELSE most targets need
6011 an explicit comparison. */
6014 ;
6030 {
6034 mode);
6035 }
6042 {
6046 const1_rtx);
6047 }
6055 {
6058 }
6060 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6061 those above. */
6063 ;
6079 {
6083 mode);
6084 }
6092 {
6096 mode);
6097 }
6099 /* If X is 0/1, (eq X 0) is X-1. */
6105 {
6108 }
6110 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6111 one bit that might be nonzero, we can convert (ne x 0) to
6112 (ashift x c) where C puts the bit in the sign bit. Remove any
6113 AND with STORE_FLAG_VALUE when we are done, since we are only
6114 going to test the sign bit. */
6121 {
6127 else
6129 }
6131 /* If the code changed, return a whole new comparison.
6132 We also need to avoid using SUBST in cases where
6133 simplify_comparison has widened a comparison with a CONST_INT,
6134 since in that case the wider CONST_INT may fail the sanity
6135 checks in do_SUBST. */
6142 /* Otherwise, keep this operation, but maybe change its operands.
6143 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6146 }
6156 /* If we are processing SET_DEST, we are done. */
6174 /* If this is a shift by a constant amount, simplify it. */
6190 }
6193 }
6194 \f
6195 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6197 static rtx
6199 {
6206 rtx temp;
6209 rtx reversed;
6211 /* Simplify storing of the truth value. */
6216 /* Also when the truth value has to be reversed. */
6222 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6223 in it is being compared against certain values. Get the true and false
6224 comparisons and see if that says anything about the value of each arm. */
6230 {
6231 HOST_WIDE_INT nzb;
6237 /* If FALSE_CODE is EQ, swap the codes and arms. */
6240 {
6243 }
6245 /* If we are comparing against zero and the expression being tested has
6246 only a single bit that might be nonzero, that is its value when it is
6247 not equal to zero. Similarly if it is known to be -1 or 0. */
6251 {
6254 }
6258 {
6261 }
6263 /* Now simplify an arm if we know the value of the register in the
6264 branch and it is used in the arm. Be careful due to the potential
6265 of locally-shared RTL. */
6282 }
6284 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6285 reversed, do so to avoid needing two sets of patterns for
6286 subtract-and-branch insns. Similarly if we have a constant in the true
6287 arm, the false arm is the same as the first operand of the comparison, or
6288 the false arm is more complicated than the true arm. */
6301 {
6310 /* It is possible that the conditional has been simplified out. */
6313 }
6315 /* If the two arms are identical, we don't need the comparison. */
6320 /* Convert a == b ? b : a to "a". */
6332 /* Look for cases where we have (abs x) or (neg (abs X)). */
6335 && comparison_p
6342 {
6348 return
6351 mode);
6354 }
6356 /* Look for MIN or MAX. */
6359 && comparison_p
6364 {
6379 }
6381 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6382 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6383 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6384 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6385 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6386 neither 1 or -1, but it isn't worth checking for. */
6389 && comparison_p
6392 {
6408 /* If an identity-zero op is commutative, check whether there
6409 would be a match if we swapped the operands. */
6429 {
6433 }
6445 {
6449 }
6465 {
6469 }
6481 {
6485 }
6488 {
6494 const_true_rtx));
6502 }
6503 }
6505 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6506 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6507 negation of a single bit, we can convert this operation to a shift. We
6508 can actually do this more generally, but it doesn't seem worth it. */
6517 return
6521 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6531 }
6532 \f
6533 /* Simplify X, a SET expression. Return the new expression. */
6535 static rtx
6537 {
6540 machine_mode mode
6545 /* (set (pc) (return)) gets written as (return). */
6549 /* Now that we know for sure which bits of SRC we are using, see if we can
6550 simplify the expression for the object knowing that we only need the
6551 low-order bits. */
6554 {
6557 }
6559 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6560 the comparison result and try to simplify it unless we already have used
6561 undobuf.other_insn. */
6569 {
6578 {
6581 {
6584 }
6585 }
6586 else
6594 {
6598 }
6599 else
6600 {
6605 /* Attempt to simplify CC user. */
6607 {
6611 }
6613 /* Convert X into a no-op move. */
6617 }
6619 /* Simplify our comparison, if possible. */
6622 #ifdef SELECT_CC_MODE
6623 /* If this machine has CC modes other than CCmode, check to see if we
6624 need to use a different CC mode here. */
6633 else
6636 /* If the mode changed, we have to change SET_DEST, the mode in the
6637 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6638 a hard register, just build new versions with the proper mode. If it
6639 is a pseudo, we lose unless it is only time we set the pseudo, in
6640 which case we can safely change its mode. */
6642 {
6644 {
6646 rtx new_dest;
6650 else
6651 {
6654 }
6661 }
6662 }
6665 /* If the code changed, we have to build a new comparison in
6666 undobuf.other_insn. */
6668 {
6677 /* If the only change we made was to change an EQ into an NE or
6678 vice versa, OP0 has only one bit that might be nonzero, and OP1
6679 is zero, check if changing the user of the condition code will
6680 produce a valid insn. If it won't, we can keep the original code
6681 in that insn by surrounding our operation with an XOR. */
6688 {
6693 {
6700 }
6701 }
6702 }
6707 /* Don't generate a compare of a CC with 0, just use that CC. */
6709 {
6712 }
6713 /* Otherwise, if we didn't previously have the same COMPARE we
6714 want, create it from scratch. */
6717 {
6720 }
6721 }
6722 else
6723 {
6724 /* Get SET_SRC in a form where we have placed back any
6725 compound expressions. Then do the checks below. */
6728 }
6730 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6731 and X being a REG or (subreg (reg)), we may be able to convert this to
6732 (set (subreg:m2 x) (op)).
6734 We can always do this if M1 is narrower than M2 because that means that
6735 we only care about the low bits of the result.
6737 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6738 perform a narrower operation than requested since the high-order bits will
6739 be undefined. On machine where it is defined, this transformation is safe
6740 as long as M1 and M2 have the same number of words. */
6748 #ifndef WORD_REGISTER_OPERATIONS
6751 #endif
6752 #ifdef CANNOT_CHANGE_MODE_CLASS
6757 #endif
6761 {
6764 dest));
6768 }
6770 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6771 in SRC. */
6777 {
6781 /* Here we make sure that we don't have a sign bit on. */
6784 {
6787 }
6788 }
6790 #ifdef LOAD_EXTEND_OP
6791 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6792 would require a paradoxical subreg. Replace the subreg with a
6793 zero_extend to avoid the reload that would otherwise be required. */
6801 {
6807 }
6808 #endif
6810 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6811 are comparing an item known to be 0 or -1 against 0, use a logical
6812 operation instead. Check for one of the arms being an IOR of the other
6813 arm with some value. We compute three terms to be IOR'ed together. In
6814 practice, at most two will be nonzero. Then we do the IOR's. */
6822 && (!HAVE_conditional_move
6828 {
6854 false_rtx);
6860 term3));
6863 }
6865 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6866 whole thing fail. */
6871 else
6872 /* Convert this into a field assignment operation, if possible. */
6874 }
6875 \f
6876 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6877 result. */
6879 static rtx
6881 {
6887 {
6889 /* We can call simplify_and_const_int only if we don't lose
6890 any (sign) bits when converting INTVAL (op1) to
6891 "unsigned HOST_WIDE_INT". */
6895 {
6902 }
6904 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6905 apply the distributive law and then the inverse distributive
6906 law to see if things simplify. */
6908 {
6912 }
6914 {
6918 }
6922 /* If we have (ior (and A B) C), apply the distributive law and then
6923 the inverse distributive law to see if things simplify. */
6926 {
6930 }
6933 {
6937 }
6942 }
6945 }
6946 \f
6947 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6948 operations" because they can be replaced with two more basic operations.
6949 ZERO_EXTEND is also considered "compound" because it can be replaced with
6950 an AND operation, which is simpler, though only one operation.
6952 The function expand_compound_operation is called with an rtx expression
6953 and will convert it to the appropriate shifts and AND operations,
6954 simplifying at each stage.
6956 The function make_compound_operation is called to convert an expression
6957 consisting of shifts and ANDs into the equivalent compound expression.
6958 It is the inverse of this function, loosely speaking. */
6960 static rtx
6962 {
6966 rtx tem;
6969 {
6973 /* We can't necessarily use a const_int for a multiword mode;
6974 it depends on implicitly extending the value.
6975 Since we don't know the right way to extend it,
6976 we can't tell whether the implicit way is right.
6978 Even for a mode that is no wider than a const_int,
6979 we can't win, because we need to sign extend one of its bits through
6980 the rest of it, and we don't know which bit. */
6984 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6985 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6986 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6987 reloaded. If not for that, MEM's would very rarely be safe.
6989 Reject MODEs bigger than a word, because we might not be able
6990 to reference a two-register group starting with an arbitrary register
6991 (and currently gen_lowpart might crash for a SUBREG). */
6996 /* Reject MODEs that aren't scalar integers because turning vector
6997 or complex modes into shifts causes problems. */
7003 /* If the inner object has VOIDmode (the only way this can happen
7004 is if it is an ASM_OPERANDS), we can't do anything since we don't
7005 know how much masking to do. */
7014 /* ... fall through ... */
7017 /* If the operand is a CLOBBER, just return it. */
7026 /* Reject MODEs that aren't scalar integers because turning vector
7027 or complex modes into shifts causes problems. */
7035 /* This should stay within the object being extracted, fail otherwise. */
7046 }
7047 /* Convert sign extension to zero extension, if we know that the high
7048 bit is not set, as this is easier to optimize. It will be converted
7049 back to cheaper alternative in make_extraction. */
7057 {
7061 /* Make sure this is a profitable operation. */
7068 else
7070 }
7072 /* We can optimize some special cases of ZERO_EXTEND. */
7074 {
7075 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7076 know that the last value didn't have any inappropriate bits
7077 set. */
7085 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7094 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7095 is a comparison and STORE_FLAG_VALUE permits. This is like
7096 the first case, but it works even when GET_MODE (x) is larger
7097 than HOST_WIDE_INT. */
7106 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7116 }
7118 /* If we reach here, we want to return a pair of shifts. The inner
7119 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7120 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7121 logical depending on the value of UNSIGNEDP.
7123 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7124 converted into an AND of a shift.
7126 We must check for the case where the left shift would have a negative
7127 count. This can happen in a case like (x >> 31) & 255 on machines
7128 that can't shift by a constant. On those machines, we would first
7129 combine the shift with the AND to produce a variable-position
7130 extraction. Then the constant of 31 would be substituted in
7131 to produce such a position. */
7135 {
7144 }
7151 else
7152 /* Any other cases we can't handle. */
7155 /* If we couldn't do this for some reason, return the original
7156 expression. */
7161 }
7162 \f
7163 /* X is a SET which contains an assignment of one object into
7164 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7165 or certain SUBREGS). If possible, convert it into a series of
7166 logical operations.
7168 We half-heartedly support variable positions, but do not at all
7169 support variable lengths. */
7171 static const_rtx
7173 {
7174 rtx inner;
7178 machine_mode compute_mode;
7180 /* Loop until we find something we can't simplify. */
7182 {
7185 {
7189 }
7192 {
7197 /* A constant position should stay within the width of INNER. */
7203 {
7211 /* If position is ADJUST - X, new position is X. */
7213 else
7214 {
7219 pos);
7220 }
7221 }
7222 }
7224 /* A SUBREG between two modes that occupy the same numbers of words
7225 can be done by moving the SUBREG to the source. */
7227 /* We need SUBREGs to compute nonzero_bits properly. */
7228 && nonzero_sign_valid
7233 {
7235 gen_lowpart
7239 }
7240 else
7248 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7250 {
7251 machine_mode imode;
7253 /* Don't do anything for vector or complex integral types. */
7257 /* Try to find an integral mode to pun with. */
7264 }
7266 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7270 /* Now compute the equivalent expression. Make a copy of INNER
7271 for the SET_DEST in case it is a MEM into which we will substitute;
7272 we don't want shared RTL in that case. */
7274 compute_mode);
7278 compute_mode,
7280 compute_mode),
7281 inner);
7286 mask),
7287 pos);
7292 }
7295 }
7296 \f
7297 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7298 it is an RTX that represents the (variable) starting position; otherwise,
7299 POS is the (constant) starting bit position. Both are counted from the LSB.
7301 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7303 IN_DEST is nonzero if this is a reference in the destination of a SET.
7304 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7305 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7306 be used.
7308 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7309 ZERO_EXTRACT should be built even for bits starting at bit 0.
7311 MODE is the desired mode of the result (if IN_DEST == 0).
7313 The result is an RTX for the extraction or NULL_RTX if the target
7314 can't handle it. */
7316 static rtx
7320 {
7321 /* This mode describes the size of the storage area
7322 to fetch the overall value from. Within that, we
7323 ignore the POS lowest bits, etc. */
7325 machine_mode inner_mode;
7326 machine_mode wanted_inner_mode;
7333 HOST_WIDE_INT orig_pos;
7339 {
7340 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7341 consider just the QI as the memory to extract from.
7342 The subreg adds or removes high bits; its mode is
7343 irrelevant to the meaning of this extraction,
7344 since POS and LEN count from the lsb. */
7348 }
7353 {
7354 /* We're extracting the least significant bits of an rtx
7355 (ashift X (const_int C)), where LEN > C. Extract the
7356 least significant (LEN - C) bits of X, giving an rtx
7357 whose mode is MODE, then shift it left C times. */
7363 }
7369 /* See if this can be done without an extraction. We never can if the
7370 width of the field is not the same as that of some integer mode. For
7371 registers, we can only avoid the extraction if the position is at the
7372 low-order bit and this is either not in the destination or we have the
7373 appropriate STRICT_LOW_PART operation available.
7375 For MEM, we can avoid an extract if the field starts on an appropriate
7376 boundary and we can change the mode of the memory reference. */
7385 && (! in_dest
7389 && (pos
7392 /* We can't do this if we are widening INNER_MODE (it
7393 may not be aligned, for one thing). */
7399 {
7400 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7401 field. If the original and current mode are the same, we need not
7402 adjust the offset. Otherwise, we do if bytes big endian.
7404 If INNER is not a MEM, get a piece consisting of just the field
7405 of interest (in this case POS % BITS_PER_WORD must be 0). */
7408 {
7409 HOST_WIDE_INT offset;
7411 /* POS counts from lsb, but make OFFSET count in memory order. */
7414 else
7418 }
7420 {
7422 {
7423 /* We can't call gen_lowpart in a DEST since we
7424 always want a SUBREG (see below) and it would sometimes
7425 return a new hard register. */
7427 {
7442 /* Avoid creating invalid subregs, for example when
7443 simplifying (x>>32)&255. */
7448 }
7449 else
7451 }
7452 else
7454 }
7455 else
7457 len >= HOST_BITS_PER_WIDE_INT
7462 /* If this extraction is going into the destination of a SET,
7463 make a STRICT_LOW_PART unless we made a MEM. */
7478 /* If we know that no extraneous bits are set, and that the high
7479 bit is not set, convert the extraction to the cheaper of
7480 sign and zero extension, that are equivalent in these cases. */
7486 {
7490 /* Prefer ZERO_EXTENSION, since it gives more information to
7491 backends. */
7496 }
7498 /* Otherwise, sign- or zero-extend unless we already are in the
7499 proper mode. */
7503 }
7505 /* Unless this is a COMPARE or we have a funny memory reference,
7506 don't do anything with zero-extending field extracts starting at
7507 the low-order bit since they are simple AND operations. */
7512 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7513 if the position is not a constant and the length is not 1. In all
7514 other cases, we would only be going outside our object in cases when
7515 an original shift would have been undefined. */
7524 /* If INNER is not from memory, we want it to have the mode of a register
7525 extraction pattern's structure operand, or word_mode if there is no
7526 such pattern. The same applies to extraction_mode and pos_mode
7527 and their respective operands.
7529 For memory, assume that the desired extraction_mode and pos_mode
7530 are the same as for a register operation, since at present we don't
7531 have named patterns for aligned memory structures. */
7535 {
7539 }
7541 /* Never narrow an object, since that might not be safe. */
7549 else
7550 {
7551 /* Be careful not to go beyond the extracted object and maintain the
7552 natural alignment of the memory. */
7556 {
7559 }
7560 }
7565 {
7566 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7567 BITS_BIG_ENDIAN style. If position is constant, compute new
7568 position. Otherwise, build subtraction.
7569 Note that POS is relative to the mode of the original argument.
7570 If it's a MEM we need to recompute POS relative to that.
7571 However, if we're extracting from (or inserting into) a register,
7572 we want to recompute POS relative to wanted_inner_mode. */
7579 else
7580 pos_rtx
7583 pos_rtx);
7584 /* POS may be less than 0 now, but we check for that below.
7585 Note that it can only be less than 0 if !MEM_P (inner). */
7586 }
7588 /* If INNER has a wider mode, and this is a constant extraction, try to
7589 make it smaller and adjust the byte to point to the byte containing
7590 the value. */
7593 && ! pos_rtx
7598 {
7601 /* The computations below will be correct if the machine is big
7602 endian in both bits and bytes or little endian in bits and bytes.
7603 If it is mixed, we must adjust. */
7605 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7606 adjust OFFSET to compensate. */
7611 /* We can now move to the desired byte. */
7622 }
7624 /* If INNER is not memory, get it into the proper mode. If we are changing
7625 its mode, POS must be a constant and smaller than the size of the new
7626 mode. */
7628 {
7629 /* On the LHS, don't create paradoxical subregs implicitely truncating
7630 the register unless TRULY_NOOP_TRUNCATION. */
7633 wanted_inner_mode))
7645 pos_rtx
7651 }
7653 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7654 have to zero extend. Otherwise, we can just use a SUBREG. */
7657 {
7661 /* If we know that no extraneous bits are set, and that the high
7662 bit is not set, convert extraction to cheaper one - either
7663 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7664 cases. */
7672 {
7676 /* Prefer ZERO_EXTENSION, since it gives more information to
7677 backends. */
7681 }
7683 }
7685 /* Make POS_RTX unless we already have it and it is correct. If we don't
7686 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7687 be a CONST_INT. */
7694 /* Make the required operation. See if we can use existing rtx. */
7701 }
7702 \f
7703 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7704 with any other operations in X. Return X without that shift if so. */
7706 static rtx
7708 {
7711 rtx tem;
7714 {
7716 /* This is the shift itself. If it is wide enough, we will return
7717 either the value being shifted if the shift count is equal to
7718 COUNT or a shift for the difference. */
7732 /* If we can safely shift this constant and we find the inner shift,
7733 make a new operation. */
7738 {
7742 }
7747 }
7750 }
7751 \f
7752 /* Look at the expression rooted at X. Look for expressions
7753 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7754 Form these expressions.
7756 Return the new rtx, usually just X.
7758 Also, for machines like the VAX that don't have logical shift insns,
7759 try to convert logical to arithmetic shift operations in cases where
7760 they are equivalent. This undoes the canonicalizations to logical
7761 shifts done elsewhere.
7763 We try, as much as possible, to re-use rtl expressions to save memory.
7765 IN_CODE says what kind of expression we are processing. Normally, it is
7766 SET. In a memory address it is MEM. When processing the arguments of
7767 a comparison or a COMPARE against zero, it is COMPARE. */
7769 rtx
7771 {
7779 rtx tem;
7782 /* Select the code to be used in recursive calls. Once we are inside an
7783 address, we stay there. If we have a comparison, set to COMPARE,
7784 but once inside, go back to our default of SET. */
7791 /* Process depending on the code of this operation. If NEW is set
7792 nonzero, it will be returned. */
7795 {
7797 /* Convert shifts by constants into multiplications if inside
7798 an address. */
7803 {
7809 {
7812 }
7815 }
7825 {
7829 }
7832 {
7836 mode));
7838 }
7839 else
7840 {
7844 }
7855 {
7859 }
7862 {
7866 mode));
7868 }
7869 else
7870 {
7874 }
7878 /* If the second operand is not a constant, we can't do anything
7879 with it. */
7883 /* If the constant is a power of two minus one and the first operand
7884 is a logical right shift, make an extraction. */
7887 {
7891 }
7893 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7898 {
7900 next_code);
7904 }
7905 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7911 {
7912 /* Apply the distributive law, and then try to make extractions. */
7919 }
7921 /* If we are have (and (rotate X C) M) and C is larger than the number
7922 of bits in M, this is an extraction. */
7928 {
7934 }
7936 /* On machines without logical shifts, if the operand of the AND is
7937 a logical shift and our mask turns off all the propagated sign
7938 bits, we can replace the logical shift with an arithmetic shift. */
7946 {
7953 make_compound_operation
7956 }
7958 /* If the constant is one less than a power of two, this might be
7959 representable by an extraction even if no shift is present.
7960 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7961 we are in a COMPARE. */
7965 next_code),
7968 /* If we are in a comparison and this is an AND with a power of two,
7969 convert this into the appropriate bit extract. */
7974 next_code),
7980 /* If the sign bit is known to be zero, replace this with an
7981 arithmetic shift. */
7986 {
7989 next_code),
7992 }
7994 /* ... fall through ... */
8000 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8001 this is a SIGN_EXTRACT. */
8008 {
8015 }
8017 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8018 If so, try to merge the shifts into a SIGN_EXTEND. We could
8019 also do this for some cases of SIGN_EXTRACT, but it doesn't
8020 seem worth the effort; the case checked for occurs on Alpha. */
8036 /* Call ourselves recursively on the inner expression. If we are
8037 narrowing the object and it has a different RTL code from
8038 what it originally did, do this SUBREG as a force_to_mode. */
8039 {
8043 /* If in_code is COMPARE, it isn't always safe to pass it through
8044 to the recursive make_compound_operation call. */
8048 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8049 is (const_int 0), rather than
8050 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8060 simplified
8068 {
8069 rtx newer
8072 /* If we have something other than a SUBREG, we might have
8073 done an expansion, so rerun ourselves. */
8077 /* force_to_mode can expand compounds. If it just re-expanded the
8078 compound, use gen_lowpart to convert to the desired mode. */
8080 /* Likewise if it re-expanded the compound only partially.
8081 This happens for SUBREG of ZERO_EXTRACT if they extract
8082 the same number of bits. */
8091 }
8095 }
8100 }
8103 {
8106 }
8108 /* Now recursively process each operand of this operation. We need to
8109 handle ZERO_EXTEND specially so that we don't lose track of the
8110 inner mode. */
8112 {
8120 }
8125 {
8128 }
8131 {
8134 }
8136 maybe_swap:
8137 /* If this is a commutative operation, the changes to the operands
8138 may have made it noncanonical. */
8141 {
8145 }
8148 }
8149 \f
8150 /* Given M see if it is a value that would select a field of bits
8151 within an item, but not the entire word. Return -1 if not.
8152 Otherwise, return the starting position of the field, where 0 is the
8153 low-order bit.
8155 *PLEN is set to the length of the field. */
8157 static int
8159 {
8160 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8165 /* Now shift off the low-order zero bits and see if we have a
8166 power of two minus 1. */
8174 }
8175 \f
8176 /* If X refers to a register that equals REG in value, replace these
8177 references with REG. */
8178 static rtx
8180 {
8188 {
8224 {
8228 else
8230 }
8232 /* fall through */
8239 {
8242 {
8244 {
8247 }
8249 }
8250 }
8252 {
8255 {
8258 {
8260 {
8263 }
8265 }
8266 }
8267 }
8270 }
8273 }
8275 /* Return X converted to MODE. If the value is already truncated to
8276 MODE we can just return a subreg even though in the general case we
8277 would need an explicit truncation. */
8279 static rtx
8281 {
8286 {
8287 /* Bit-cast X into an integer mode. */
8292 }
8295 }
8297 /* See if X can be simplified knowing that we will only refer to it in
8298 MODE and will only refer to those bits that are nonzero in MASK.
8299 If other bits are being computed or if masking operations are done
8300 that select a superset of the bits in MASK, they can sometimes be
8301 ignored.
8303 Return a possibly simplified expression, but always convert X to
8304 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8306 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8307 are all off in X. This is used when X will be complemented, by either
8308 NOT, NEG, or XOR. */
8310 static rtx
8313 {
8316 machine_mode op_mode;
8320 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8321 code below will do the wrong thing since the mode of such an
8322 expression is VOIDmode.
8324 Also do nothing if X is a CLOBBER; this can happen if X was
8325 the return value from a call to gen_lowpart. */
8329 /* We want to perform the operation in its present mode unless we know
8330 that the operation is valid in MODE, in which case we do the operation
8331 in MODE. */
8336 /* It is not valid to do a right-shift in a narrower mode
8337 than the one it came in with. */
8342 /* Truncate MASK to fit OP_MODE. */
8346 /* When we have an arithmetic operation, or a shift whose count we
8347 do not know, we need to assume that all bits up to the highest-order
8348 bit in MASK will be needed. This is how we form such a mask. */
8351 else
8355 /* Determine what bits of X are guaranteed to be (non)zero. */
8358 /* If none of the bits in X are needed, return a zero. */
8362 /* If X is a CONST_INT, return a new one. Do this here since the
8363 test below will fail. */
8365 {
8368 else
8369 {
8372 }
8373 }
8375 /* If X is narrower than MODE and we want all the bits in X's mode, just
8376 get X in the proper mode. */
8381 /* We can ignore the effect of a SUBREG if it narrows the mode or
8382 if the constant masks to zero all the bits the mode doesn't have. */
8392 /* The arithmetic simplifications here only work for scalar integer modes. */
8397 {
8399 /* If X is a (clobber (const_int)), return it since we know we are
8400 generating something that won't match. */
8413 /* Similarly for a truncate. */
8417 /* If this is an AND with a constant, convert it into an AND
8418 whose constant is the AND of that constant with MASK. If it
8419 remains an AND of MASK, delete it since it is redundant. */
8422 {
8426 /* If X is still an AND, see if it is an AND with a mask that
8427 is just some low-order bits. If so, and it is MASK, we don't
8428 need it. */
8435 /* If it remains an AND, try making another AND with the bits
8436 in the mode mask that aren't in MASK turned on. If the
8437 constant in the AND is wide enough, this might make a
8438 cheaper constant. */
8443 {
8444 unsigned HOST_WIDE_INT cval
8447 rtx y;
8454 }
8457 }
8462 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8463 low-order bits (as in an alignment operation) and FOO is already
8464 aligned to that boundary, mask C1 to that boundary as well.
8465 This may eliminate that PLUS and, later, the AND. */
8467 {
8471 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8472 number, sign extend it. */
8485 }
8487 /* ... fall through ... */
8490 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8491 most significant bit in MASK since carries from those bits will
8492 affect the bits we are interested in. */
8497 /* If X is (minus C Y) where C's least set bit is larger than any bit
8498 in the mask, then we may replace with (neg Y). */
8501 {
8505 }
8507 /* Similarly, if C contains every bit in the fuller_mask, then we may
8508 replace with (not Y). */
8511 {
8515 }
8522 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8523 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8524 operation which may be a bitfield extraction. Ensure that the
8525 constant we form is not wider than the mode of X. */
8537 {
8546 }
8548 binop:
8549 /* For most binary operations, just propagate into the operation and
8550 change the mode if we have an operation of that mode. */
8555 /* If we ended up truncating both operands, truncate the result of the
8556 operation instead. */
8559 {
8562 }
8572 /* For left shifts, do the same, but just for the first operand.
8573 However, we cannot do anything with shifts where we cannot
8574 guarantee that the counts are smaller than the size of the mode
8575 because such a count will have a different meaning in a
8576 wider mode. */
8586 /* If the shift count is a constant and we can do arithmetic in
8587 the mode of the shift, refine which bits we need. Otherwise, use the
8588 conservative form of the mask. */
8594 else
8606 /* Here we can only do something if the shift count is a constant,
8607 this shift constant is valid for the host, and we can do arithmetic
8608 in OP_MODE. */
8614 {
8618 /* Select the mask of the bits we need for the shift operand. */
8621 /* We can only change the mode of the shift if we can do arithmetic
8622 in the mode of the shift and INNER_MASK is no wider than the
8623 width of X's mode. */
8631 }
8633 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8634 shift and AND produces only copies of the sign bit (C2 is one less
8635 than a power of two), we can do this with just a shift. */
8639 /* The shift puts one of the sign bit copies in the least significant
8640 bit. */
8645 /* Number of bits left after the shift must be more than the mask
8646 needs. */
8649 /* Must be more sign bit copies than the mask needs. */
8659 /* If we are just looking for the sign bit, we don't need this shift at
8660 all, even if it has a variable count. */
8664 /* If this is a shift by a constant, get a mask that contains those bits
8665 that are not copies of the sign bit. We then have two cases: If
8666 MASK only includes those bits, this can be a logical shift, which may
8667 allow simplifications. If MASK is a single-bit field not within
8668 those bits, we are requesting a copy of the sign bit and hence can
8669 shift the sign bit to the appropriate location. */
8673 {
8676 /* If the considered data is wider than HOST_WIDE_INT, we can't
8677 represent a mask for all its bits in a single scalar.
8678 But we only care about the lower bits, so calculate these. */
8681 {
8684 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8685 is the number of bits a full-width mask would have set.
8686 We need only shift if these are fewer than nonzero can
8687 hold. If not, we must keep all bits set in nonzero. */
8692 + HOST_BITS_PER_WIDE_INT
8694 }
8695 else
8696 {
8699 }
8702 {
8707 }
8710 {
8711 x = simplify_shift_const
8717 }
8718 }
8720 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8721 even if the shift count isn't a constant. */
8726 shiftrt:
8728 /* If this is a zero- or sign-extension operation that just affects bits
8729 we don't care about, remove it. Be sure the call above returned
8730 something that is still a shift. */
8740 next_select);
8746 /* If the shift count is constant and we can do computations
8747 in the mode of X, compute where the bits we care about are.
8748 Otherwise, we can't do anything. Don't change the mode of
8749 the shift or propagate MODE into the shift, though. */
8752 {
8762 }
8766 /* If we just want the low-order bit, the NEG isn't needed since it
8767 won't change the low-order bit. */
8771 /* We need any bits less significant than the most significant bit in
8772 MASK since carries from those bits will affect the bits we are
8773 interested in. */
8778 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8779 same as the XOR case above. Ensure that the constant we form is not
8780 wider than the mode of X. */
8788 {
8797 }
8799 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8800 use the full mask inside the NOT. */
8803 unop:
8806 next_select));
8812 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8813 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8814 which is equal to STORE_FLAG_VALUE. */
8826 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8827 written in a narrower mode. We play it safe and do not do so. */
8843 }
8845 /* Ensure we return a value of the proper mode. */
8847 }
8848 \f
8849 /* Return nonzero if X is an expression that has one of two values depending on
8850 whether some other value is zero or nonzero. In that case, we return the
8851 value that is being tested, *PTRUE is set to the value if the rtx being
8852 returned has a nonzero value, and *PFALSE is set to the other alternative.
8854 If we return zero, we set *PTRUE and *PFALSE to X. */
8856 static rtx
8858 {
8864 /* If we are comparing a value against zero, we are done. */
8867 {
8871 }
8873 /* If this is a unary operation whose operand has one of two values, apply
8874 our opcode to compute those values. */
8877 {
8882 }
8884 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8885 make can't possibly match and would suppress other optimizations. */
8887 ;
8889 /* If this is a binary operation, see if either side has only one of two
8890 values. If either one does or if both do and they are conditional on
8891 the same value, compute the new true and false values. */
8893 {
8899 {
8900 /* If if_then_else_cond returned zero, then true/false are the
8901 same rtl. We must copy one of them to prevent invalid rtl
8902 sharing. */
8909 {
8914 }
8915 else
8916 {
8919 }
8922 }
8924 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8925 operands is zero when the other is nonzero, and vice-versa,
8926 and STORE_FLAG_VALUE is 1 or -1. */
8932 {
8949 {
8956 const_true_rtx);
8958 }
8959 }
8961 /* Similarly for MULT, AND and UMIN, except that for these the result
8962 is always zero. */
8966 {
8980 {
8983 }
8984 }
8985 }
8988 {
8989 /* If we have IF_THEN_ELSE already, extract the condition and
8990 canonicalize it if it is NE or EQ. */
8996 {
8999 }
9000 else
9002 }
9004 /* If X is a SUBREG, we can narrow both the true and false values
9005 if the inner expression, if there is a condition. */
9009 {
9015 {
9019 }
9020 }
9022 /* If X is a constant, this isn't special and will cause confusions
9023 if we treat it as such. Likewise if it is equivalent to a constant. */
9026 ;
9028 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9029 will be least confusing to the rest of the compiler. */
9031 {
9034 }
9036 /* If X is known to be either 0 or -1, those are the true and
9037 false values when testing X. */
9041 {
9044 }
9046 /* Likewise for 0 or a single bit. */
9049 {
9052 }
9054 /* Otherwise fail; show no condition with true and false values the same. */
9057 }
9058 \f
9059 /* Return the value of expression X given the fact that condition COND
9060 is known to be true when applied to REG as its first operand and VAL
9061 as its second. X is known to not be shared and so can be modified in
9062 place.
9064 We only handle the simplest cases, and specifically those cases that
9065 arise with IF_THEN_ELSE expressions. */
9067 static rtx
9069 {
9077 /* If either operand of the condition is a floating point value,
9078 then we have to avoid collapsing an EQ comparison. */
9088 /* If X is (abs REG) and we know something about REG's relationship
9089 with zero, we may be able to simplify this. */
9093 {
9102 }
9104 /* The only other cases we handle are MIN, MAX, and comparisons if the
9105 operands are the same as REG and VAL. */
9108 {
9110 {
9113 }
9116 {
9118 {
9126 else
9128 }
9131 {
9134 /* Do not reverse the condition when it is NE or EQ.
9135 This is because we cannot conclude anything about
9136 the value of 'SMAX (x, y)' when x is not equal to y,
9137 but we can when x equals y. */
9143 {
9154 }
9155 }
9156 }
9157 }
9159 {
9164 {
9165 /* We must simplify subreg here, before we lose track of the
9166 original inner_mode. */
9171 else
9173 }
9176 }
9177 /* We don't have to handle SIGN_EXTEND here, because even in the
9178 case of replacing something with a modeless CONST_INT, a
9179 CONST_INT is already (supposed to be) a valid sign extension for
9180 its narrower mode, which implies it's already properly
9181 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9182 story is different. */
9184 {
9189 {
9190 /* We must simplify the zero_extend here, before we lose
9191 track of the original inner_mode. */
9196 else
9198 }
9201 }
9205 {
9212 }
9215 }
9216 \f
9217 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9218 assignment as a field assignment. */
9220 static int
9222 {
9224 {
9229 /* For big endian, adjust the memory offset. */
9234 else
9236 }
9244 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9245 Note that all SUBREGs of MEM are paradoxical; otherwise they
9246 would have been rewritten. */
9259 /* We used to see if get_last_value of X and Y were the same but that's
9260 not correct. In one direction, we'll cause the assignment to have
9261 the wrong destination and in the case, we'll import a register into this
9262 insn that might have already have been dead. So fail if none of the
9263 above cases are true. */
9265 }
9266 \f
9267 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9268 Return that assignment if so.
9270 We only handle the most common cases. */
9272 static rtx
9274 {
9277 rtx assign;
9279 HOST_WIDE_INT c1;
9280 HOST_WIDE_INT pos;
9282 rtx other;
9283 machine_mode mode;
9285 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9286 a clear of a one-bit field. We will have changed it to
9287 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9288 for a SUBREG. */
9294 {
9300 }
9310 {
9317 }
9319 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9320 one-bit field. */
9324 {
9330 }
9332 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9333 SRC is an AND with all bits of that field set, then we can discard
9334 the AND. */
9339 {
9346 else
9349 /* Complete overlap. We can remove the source AND. */
9353 /* Partial overlap. We can reduce the source AND. */
9355 {
9360 }
9361 }
9363 /* The other case we handle is assignments into a constant-position
9364 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9365 a mask that has all one bits except for a group of zero bits and
9366 OTHER is known to have zeros where C1 has ones, this is such an
9367 assignment. Compute the position and length from C1. Shift OTHER
9368 to the appropriate position, force it to the required mode, and
9369 make the extraction. Check for the AND in both operands. */
9371 /* One or more SUBREGs might obscure the constant-position field
9372 assignment. The first one we are likely to encounter is an outer
9373 narrowing SUBREG, which we can just strip for the purposes of
9374 identifying the constant-field assignment. */
9388 /* The second SUBREG that might get in the way is a paradoxical
9389 SUBREG around the first operand of the AND. We want to
9390 pretend the operand is as wide as the destination here. We
9391 do this by adjusting the MEM to wider mode for the sole
9392 purpose of the call to rtx_equal_for_field_assignment_p. Also
9393 note this trick only works for MEMs. */
9405 /* The second SUBREG that might get in the way is a paradoxical
9406 SUBREG around the first operand of the AND. We want to
9407 pretend the operand is as wide as the destination here. We
9408 do this by adjusting the MEM to wider mode for the sole
9409 purpose of the call to rtx_equal_for_field_assignment_p. Also
9410 note this trick only works for MEMs. */
9418 else
9431 /* The mode to use for the source is the mode of the assignment, or of
9432 what is inside a possible STRICT_LOW_PART. */
9436 /* Shift OTHER right POS places and make it the source, restricting it
9437 to the proper length and mode. */
9442 dest);
9449 /* If SRC is masked by an AND that does not make a difference in
9450 the value being stored, strip it. */
9461 }
9462 \f
9463 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9464 if so. */
9466 static rtx
9468 {
9472 rtx tem;
9474 /* Distributivity is not true for floating point as it can change the
9475 value. So we don't do it unless -funsafe-math-optimizations. */
9480 /* The outer operation can only be one of the following: */
9488 /* If either operand is a primitive we can't do anything, so get out
9489 fast. */
9499 /* See if the inner and outer operations distribute. */
9501 {
9506 /* These all distribute except over PLUS. */
9517 /* This is also a multiply, so it distributes over everything. */
9520 /* This used to handle SUBREG, but this turned out to be counter-
9521 productive, since (subreg (op ...)) usually is not handled by
9522 insn patterns, and this "optimization" therefore transformed
9523 recognizable patterns into unrecognizable ones. Therefore the
9524 SUBREG case was removed from here.
9526 It is possible that distributing SUBREG over arithmetic operations
9527 leads to an intermediate result than can then be optimized further,
9528 e.g. by moving the outer SUBREG to the other side of a SET as done
9529 in simplify_set. This seems to have been the original intent of
9530 handling SUBREGs here.
9532 However, with current GCC this does not appear to actually happen,
9533 at least on major platforms. If some case is found where removing
9534 the SUBREG case here prevents follow-on optimizations, distributing
9535 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9539 }
9541 /* Set LHS and RHS to the inner operands (A and B in the example
9542 above) and set OTHER to the common operand (C in the example).
9543 There is only one way to do this unless the inner operation is
9544 commutative. */
9556 else
9559 /* Form the new inner operation, seeing if it simplifies first. */
9562 /* There is one exception to the general way of distributing:
9563 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9565 {
9568 }
9570 /* We may be able to continuing distributing the result, so call
9571 ourselves recursively on the inner operation before forming the
9572 outer operation, which we return. */
9575 }
9577 /* See if X is of the form (* (+ A B) C), and if so convert to
9578 (+ (* A C) (* B C)) and try to simplify.
9580 Most of the time, this results in no change. However, if some of
9581 the operands are the same or inverses of each other, simplifications
9582 will result.
9584 For example, (and (ior A B) (not B)) can occur as the result of
9585 expanding a bit field assignment. When we apply the distributive
9586 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9587 which then simplifies to (and (A (not B))).
9589 Note that no checks happen on the validity of applying the inverse
9590 distributive law. This is pointless since we can do it in the
9591 few places where this routine is called.
9593 N is the index of the term that is decomposed (the arithmetic operation,
9594 i.e. (+ A B) in the first example above). !N is the index of the term that
9595 is distributed, i.e. of C in the first example above. */
9596 static rtx
9598 {
9599 machine_mode mode;
9603 /* Distributivity is not true for floating point as it can change the
9604 value. So we don't do it unless -funsafe-math-optimizations. */
9621 /* Special case (and (xor B C) (not A)), which is equivalent to
9622 (xor (ior A B) (ior A C)) */
9624 {
9627 }
9630 {
9631 /* Distribute the second term. */
9634 }
9635 else
9636 {
9637 /* Distribute the first term. */
9640 }
9650 }
9651 \f
9652 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9653 in MODE. Return an equivalent form, if different from (and VAROP
9654 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9656 static rtx
9659 {
9662 rtx orig_varop;
9670 /* Simplify VAROP knowing that we will be only looking at some of the
9671 bits in it.
9673 Note by passing in CONSTOP, we guarantee that the bits not set in
9674 CONSTOP are not significant and will never be examined. We must
9675 ensure that is the case by explicitly masking out those bits
9676 before returning. */
9679 /* If VAROP is a CLOBBER, we will fail so return it. */
9683 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9684 to VAROP and return the new constant. */
9688 /* See what bits may be nonzero in VAROP. Unlike the general case of
9689 a call to nonzero_bits, here we don't care about bits outside
9690 MODE. */
9694 /* Turn off all bits in the constant that are known to already be zero.
9695 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9696 which is tested below. */
9700 /* If we don't have any bits left, return zero. */
9704 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9705 a power of two, we can replace this with an ASHIFT. */
9710 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9711 or XOR, then try to apply the distributive law. This may eliminate
9712 operations if either branch can be simplified because of the AND.
9713 It may also make some cases more complex, but those cases probably
9714 won't match a pattern either with or without this. */
9717 return
9718 gen_lowpart
9720 apply_distributive_law
9725 constop),
9729 constop))));
9731 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9732 the AND and see if one of the operands simplifies to zero. If so, we
9733 may eliminate it. */
9737 {
9746 }
9748 /* Make a SUBREG if necessary. If we can't make it, fail. */
9753 /* If we are only masking insignificant bits, return VAROP. */
9760 /* Otherwise, return an AND. */
9762 }
9765 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9766 in MODE.
9768 Return an equivalent form, if different from X. Otherwise, return X. If
9769 X is zero, we are to always construct the equivalent form. */
9771 static rtx
9774 {
9785 }
9786 \f
9787 /* Given a REG, X, compute which bits in X can be nonzero.
9788 We don't care about bits outside of those defined in MODE.
9790 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9791 a shift, AND, or zero_extract, we can do better. */
9793 static rtx
9795 const_rtx known_x ATTRIBUTE_UNUSED,
9796 machine_mode known_mode ATTRIBUTE_UNUSED,
9799 {
9800 rtx tem;
9803 /* If X is a register whose nonzero bits value is current, use it.
9804 Otherwise, if X is a register whose value we can find, use that
9805 value. Otherwise, use the previously-computed global nonzero bits
9806 for this register. */
9820 && !REGNO_REG_SET_P
9823 {
9827 /* We don't know anything about the upper bits. */
9832 }
9837 {
9838 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9841 #endif
9843 }
9845 {
9849 /* We don't know anything about the upper bits. */
9853 }
9856 }
9858 /* Return the number of bits at the high-order end of X that are known to
9859 be equal to the sign bit. X will be used in mode MODE; if MODE is
9860 VOIDmode, X will be used in its own mode. The returned value will always
9861 be between 1 and the number of bits in MODE. */
9863 static rtx
9865 const_rtx known_x ATTRIBUTE_UNUSED,
9866 machine_mode known_mode
9867 ATTRIBUTE_UNUSED,
9870 {
9871 rtx tem;
9884 && !REGNO_REG_SET_P
9887 {
9890 }
9901 }
9902 \f
9903 /* Return the number of "extended" bits there are in X, when interpreted
9904 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9905 unsigned quantities, this is the number of high-order zero bits.
9906 For signed quantities, this is the number of copies of the sign bit
9907 minus 1. In both case, this function returns the number of "spare"
9908 bits. For example, if two quantities for which this function returns
9909 at least 1 are added, the addition is known not to overflow.
9911 This function will always return 0 unless called during combine, which
9912 implies that it must be called from a define_split. */
9914 unsigned int
9916 {
9926 }
9928 /* This function is called from `simplify_shift_const' to merge two
9929 outer operations. Specifically, we have already found that we need
9930 to perform operation *POP0 with constant *PCONST0 at the outermost
9931 position. We would now like to also perform OP1 with constant CONST1
9932 (with *POP0 being done last).
9934 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9935 the resulting operation. *PCOMP_P is set to 1 if we would need to
9936 complement the innermost operand, otherwise it is unchanged.
9938 MODE is the mode in which the operation will be done. No bits outside
9939 the width of this mode matter. It is assumed that the width of this mode
9940 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9942 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9943 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9944 result is simply *PCONST0.
9946 If the resulting operation cannot be expressed as one operation, we
9947 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9949 static int
9950 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9951 {
9958 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9962 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9963 if OP0 is SET. */
9972 {
9974 {
9992 }
9993 }
9995 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9999 /* If the two constants aren't the same, we can't do anything. The
10000 remaining six cases can all be done. */
10004 else
10006 {
10009 /* (a & b) | b == b */
10012 /* (a ^ b) | b == a | b */
10013 {;}
10018 /* (a & b) ^ b == (~a) & b */
10021 /* (a | b) ^ b == a & ~b */
10027 /* (a | b) & b == b */
10030 /* (a ^ b) & b) == (~a) & b */
10035 }
10037 /* Check for NO-OP cases. */
10050 /* ??? Slightly redundant with the above mask, but not entirely.
10051 Moving this above means we'd have to sign-extend the mode mask
10052 for the final test. */
10057 }
10058 \f
10059 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10060 the shift in. The original shift operation CODE is performed on OP in
10061 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10062 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10063 result of the shift is subject to operation OUTER_CODE with operand
10064 OUTER_CONST. */
10066 static machine_mode
10070 {
10075 /* In general we can't perform in wider mode for right shift and rotate. */
10077 {
10079 /* We can still widen if the bits brought in from the left are identical
10080 to the sign bit of ORIG_MODE. */
10088 /* Similarly here but with zero bits. */
10093 /* We can also widen if the bits brought in will be masked off. This
10094 operation is performed in ORIG_MODE. */
10096 {
10102 }
10103 /* fall through */
10113 }
10114 }
10116 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10117 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10118 if we cannot simplify it. Otherwise, return a simplified value.
10120 The shift is normally computed in the widest mode we find in VAROP, as
10121 long as it isn't a different number of words than RESULT_MODE. Exceptions
10122 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10124 static rtx
10127 {
10133 unsigned int mode_words
10135 /* We form (outer_op (code varop count) (outer_const)). */
10141 /* Make sure and truncate the "natural" shift on the way in. We don't
10142 want to do this inside the loop as it makes it more difficult to
10143 combine shifts. */
10147 /* If we were given an invalid count, don't do anything except exactly
10148 what was requested. */
10155 /* Unless one of the branches of the `if' in this loop does a `continue',
10156 we will `break' the loop after the `if'. */
10159 {
10160 /* If we have an operand of (clobber (const_int 0)), fail. */
10164 /* Convert ROTATERT to ROTATE. */
10166 {
10171 else
10173 }
10178 /* Handle cases where the count is greater than the size of the mode
10179 minus 1. For ASHIFT, use the size minus one as the count (this can
10180 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10181 take the count modulo the size. For other shifts, the result is
10182 zero.
10184 Since these shifts are being produced by the compiler by combining
10185 multiple operations, each of which are defined, we know what the
10186 result is supposed to be. */
10189 {
10194 else
10195 {
10196 /* We can't simply return zero because there may be an
10197 outer op. */
10201 }
10202 }
10204 /* If we discovered we had to complement VAROP, leave. Making a NOT
10205 here would cause an infinite loop. */
10209 /* An arithmetic right shift of a quantity known to be -1 or 0
10210 is a no-op. */
10214 {
10217 }
10219 /* If we are doing an arithmetic right shift and discarding all but
10220 the sign bit copies, this is equivalent to doing a shift by the
10221 bitsize minus one. Convert it into that shift because it will often
10222 allow other simplifications. */
10229 /* We simplify the tests below and elsewhere by converting
10230 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10231 `make_compound_operation' will convert it to an ASHIFTRT for
10232 those machines (such as VAX) that don't have an LSHIFTRT. */
10249 {
10256 {
10259 }
10263 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10264 minus the width of a smaller mode, we can do this with a
10265 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10272 {
10281 }
10285 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10286 the same number of words as what we've seen so far. Then store
10287 the widest mode in MODE. */
10293 == mode_words
10296 {
10301 }
10305 /* Some machines use MULT instead of ASHIFT because MULT
10306 is cheaper. But it is still better on those machines to
10307 merge two shifts into one. */
10310 {
10311 varop
10317 }
10321 /* Similar, for when divides are cheaper. */
10324 {
10325 varop
10331 }
10335 /* If we are extracting just the sign bit of an arithmetic
10336 right shift, that shift is not needed. However, the sign
10337 bit of a wider mode may be different from what would be
10338 interpreted as the sign bit in a narrower mode, so, if
10339 the result is narrower, don't discard the shift. */
10344 {
10347 }
10349 /* ... fall through ... */
10354 /* Here we have two nested shifts. The result is usually the
10355 AND of a new shift with a mask. We compute the result below. */
10362 {
10366 rtx mask_rtx;
10368 /* We have one common special case. We can't do any merging if
10369 the inner code is an ASHIFTRT of a smaller mode. However, if
10370 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10371 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10372 we can convert it to
10373 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10374 This simplifies certain SIGN_EXTEND operations. */
10378 {
10379 /* C3 has the low-order C1 bits zero. */
10391 }
10393 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10394 than C1 high-order bits equal to the sign bit, we can convert
10395 this to either an ASHIFT or an ASHIFTRT depending on the
10396 two counts.
10398 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10404 {
10408 {
10411 }
10414 }
10416 /* There are some cases we can't do. If CODE is ASHIFTRT,
10417 we can only do this if FIRST_CODE is also ASHIFTRT.
10419 We can't do the case when CODE is ROTATE and FIRST_CODE is
10420 ASHIFTRT.
10422 If the mode of this shift is not the mode of the outer shift,
10423 we can't do this if either shift is a right shift or ROTATE.
10425 Finally, we can't do any of these if the mode is too wide
10426 unless the codes are the same.
10428 Handle the case where the shift codes are the same
10429 first. */
10432 {
10441 }
10452 /* To compute the mask to apply after the shift, shift the
10453 nonzero bits of the inner shift the same way the
10454 outer shift will. */
10457 result_mode);
10459 mask_rtx
10463 /* Give up if we can't compute an outer operation to use. */
10471 /* If the shifts are in the same direction, we add the
10472 counts. Otherwise, we subtract them. */
10476 else
10479 /* If COUNT is positive, the new shift is usually CODE,
10480 except for the two exceptions below, in which case it is
10481 FIRST_CODE. If the count is negative, FIRST_CODE should
10482 always be used */
10492 }
10494 /* If we have (A << B << C) for any shift, we can convert this to
10495 (A << C << B). This wins if A is a constant. Only try this if
10496 B is not a constant. */
10501 {
10508 }
10515 /* Make this fit the case below. */
10522 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10523 with C the size of VAROP - 1 and the shift is logical if
10524 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10525 we have an (le X 0) operation. If we have an arithmetic shift
10526 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10527 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10535 {
10538 const0_rtx);
10544 }
10546 /* If we have (shift (logical)), move the logical to the outside
10547 to allow it to possibly combine with another logical and the
10548 shift to combine with another shift. This also canonicalizes to
10549 what a ZERO_EXTRACT looks like. Also, some machines have
10550 (and (shift)) insns. */
10553 /* We can't do this if we have (ashiftrt (xor)) and the
10554 constant has its sign bit set in shift_mode with shift_mode
10555 wider than result_mode. */
10559 shift_mode))
10567 {
10570 }
10572 /* If we can't do that, try to simplify the shift in each arm of the
10573 logical expression, make a new logical expression, and apply
10574 the inverse distributive law. This also can't be done for
10575 (ashiftrt (xor)) where we've widened the shift and the constant
10576 changes the sign bit. */
10581 shift_mode)))
10582 {
10594 }
10598 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10599 says that the sign bit can be tested, FOO has mode MODE, C is
10600 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10601 that may be nonzero. */
10611 {
10615 }
10619 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10620 than the number of bits in the mode is equivalent to A. */
10624 {
10628 }
10630 /* NEG commutes with ASHIFT since it is multiplication. Move the
10631 NEG outside to allow shifts to combine. */
10635 {
10638 }
10642 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10643 is one less than the number of bits in the mode is
10644 equivalent to (xor A 1). */
10651 {
10655 }
10657 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10658 that might be nonzero in BAR are those being shifted out and those
10659 bits are known zero in FOO, we can replace the PLUS with FOO.
10660 Similarly in the other operand order. This code occurs when
10661 we are computing the size of a variable-size array. */
10668 {
10671 }
10679 result_mode)))
10680 {
10683 }
10685 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10695 {
10698 }
10700 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10701 signbit', and attempt to change the PLUS to an XOR and move it to
10702 the outer operation as is done above in the AND/IOR/XOR case
10703 leg for shift(logical). See details in logical handling above
10704 for reasoning in doing so. */
10715 {
10718 }
10723 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10724 with C the size of VAROP - 1 and the shift is logical if
10725 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10726 we have a (gt X 0) operation. If the shift is arithmetic with
10727 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10728 we have a (neg (gt X 0)) operation. */
10737 {
10740 const0_rtx);
10746 }
10750 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10751 if the truncate does not affect the value. */
10758 {
10761 varop_inner
10764 GEN_INT
10769 }
10774 }
10777 }
10782 /* We have now finished analyzing the shift. The result should be
10783 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10784 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10785 to the result of the shift. OUTER_CONST is the relevant constant,
10786 but we must turn off all bits turned off in the shift. */
10794 /* Make a SUBREG if necessary. If we can't make it, fail. */
10799 /* If we have an outer operation and we just made a shift, it is
10800 possible that we could have simplified the shift were it not
10801 for the outer operation. So try to do the simplification
10802 recursively. */
10806 else
10812 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10813 turn off all the bits that the shift would have turned off. */
10818 /* Do the remainder of the processing in RESULT_MODE. */
10821 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10822 operation. */
10827 {
10835 {
10836 /* This means that we have determined that the result is
10837 equivalent to a constant. This should be rare. */
10840 }
10843 else
10846 }
10849 }
10851 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10852 The result of the shift is RESULT_MODE. If we cannot simplify it,
10853 return X or, if it is NULL, synthesize the expression with
10854 simplify_gen_binary. Otherwise, return a simplified value.
10856 The shift is normally computed in the widest mode we find in VAROP, as
10857 long as it isn't a different number of words than RESULT_MODE. Exceptions
10858 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10860 static rtx
10863 {
10873 }
10875 \f
10876 /* A subroutine of recog_for_combine. See there for arguments and
10877 return value. */
10879 static int
10881 {
10883 rtx pat_without_clobbers;
10891 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10892 we use to indicate that something didn't match. If we find such a
10893 thing, force rejection. */
10907 {
10910 else
10913 }
10915 /* If it isn't, there is the possibility that we previously had an insn
10916 that clobbered some register as a side effect, but the combined
10917 insn doesn't need to do that. So try once more without the clobbers
10918 unless this represents an ASM insn. */
10922 {
10927 {
10930 pos++;
10931 }
10941 {
10944 else
10947 }
10948 }
10955 /* Recognize all noop sets, these will be killed by followup pass. */
10959 /* If we had any clobbers to add, make a new pattern than contains
10960 them. Then check to make sure that all of them are dead. */
10962 {
10972 else
10979 {
10984 {
10988 }
10989 }
10991 }
10995 {
11002 /* Allow targets to reject combined insn. */
11004 {
11007 dump_file);
11009 /* Callers expect recog_for_combine to strip
11010 clobbers from the pattern on failure. */
11015 }
11020 }
11026 }
11028 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11029 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11030 Return whether anything was so changed. */
11032 static bool
11034 {
11039 {
11048 {
11056 }
11061 {
11064 }
11065 else
11070 mask--;
11076 }
11079 }
11081 /* Like recog, but we receive the address of a pointer to a new pattern.
11082 We try to match the rtx that the pointer points to.
11083 If that fails, we may try to modify or replace the pattern,
11084 storing the replacement into the same pointer object.
11086 Modifications include deletion or addition of CLOBBERs. If the
11087 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11088 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11089 (and undo if that fails).
11091 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11092 the CLOBBERs are placed.
11094 The value is the final insn code from the pattern ultimately matched,
11095 or -1. */
11097 static int
11099 {
11111 {
11114 {
11118 }
11119 }
11122 {
11127 }
11130 }
11131 \f
11132 /* Like gen_lowpart_general but for use by combine. In combine it
11133 is not possible to create any new pseudoregs. However, it is
11134 safe to create invalid memory addresses, because combine will
11135 try to recognize them and all they will do is make the combine
11136 attempt fail.
11138 If for some reason this cannot do its job, an rtx
11139 (clobber (const_int 0)) is returned.
11140 An insn containing that will not be recognized. */
11142 static rtx
11144 {
11148 rtx result;
11153 /* We can only support MODE being wider than a word if X is a
11154 constant integer or has a mode the same size. */
11159 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11160 won't know what to do. So we will strip off the SUBREG here and
11161 process normally. */
11163 {
11166 /* For use in case we fall down into the address adjustments
11167 further below, we need to adjust the known mode and size of
11168 x; imode and isize, since we just adjusted x. */
11175 }
11183 {
11186 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11187 address. */
11192 /* If we want to refer to something bigger than the original memref,
11193 generate a paradoxical subreg instead. That will force a reload
11194 of the original memref X. */
11201 /* Adjust the address so that the address-after-the-data is
11202 unchanged. */
11207 }
11209 /* If X is a comparison operator, rewrite it in a new mode. This
11210 probably won't match, but may allow further simplifications. */
11214 /* If we couldn't simplify X any other way, just enclose it in a
11215 SUBREG. Normally, this SUBREG won't match, but some patterns may
11216 include an explicit SUBREG or we may simplify it further in combine. */
11217 else
11218 {
11220 rtx res;
11224 {
11229 }
11233 }
11235 fail:
11237 }
11238 \f
11239 /* Try to simplify a comparison between OP0 and a constant OP1,
11240 where CODE is the comparison code that will be tested, into a
11241 (CODE OP0 const0_rtx) form.
11243 The result is a possibly different comparison code to use.
11244 *POP1 may be updated. */
11246 static enum rtx_code
11249 {
11253 /* Get the constant we are comparing against and turn off all bits
11254 not on in our mode. */
11258 /* If we are comparing against a constant power of two and the value
11259 being compared can only have that single bit nonzero (e.g., it was
11260 `and'ed with that bit), we can replace this with a comparison
11261 with zero. */
11269 {
11272 }
11274 /* Similarly, if we are comparing a value known to be either -1 or
11275 0 with -1, change it to the opposite comparison against zero. */
11280 {
11283 }
11285 /* Do some canonicalizations based on the comparison code. We prefer
11286 comparisons against zero and then prefer equality comparisons.
11287 If we can reduce the size of a constant, we will do that too. */
11289 {
11291 /* < C is equivalent to <= (C - 1) */
11293 {
11296 /* ... fall through to LE case below. */
11297 }
11298 else
11302 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11304 {
11307 }
11309 /* If we are doing a <= 0 comparison on a value known to have
11310 a zero sign bit, we can replace this with == 0. */
11320 /* >= C is equivalent to > (C - 1). */
11322 {
11325 /* ... fall through to GT below. */
11326 }
11327 else
11331 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11333 {
11336 }
11338 /* If we are doing a > 0 comparison on a value known to have
11339 a zero sign bit, we can replace this with != 0. */
11349 /* < C is equivalent to <= (C - 1). */
11351 {
11354 /* ... fall through ... */
11355 }
11356 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11360 {
11364 }
11365 else
11369 /* unsigned <= 0 is equivalent to == 0 */
11372 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11376 {
11379 }
11383 /* >= C is equivalent to > (C - 1). */
11385 {
11388 /* ... fall through ... */
11389 }
11391 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11395 {
11399 }
11400 else
11404 /* unsigned > 0 is equivalent to != 0 */
11407 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11411 {
11414 }
11419 }
11423 }
11424 \f
11425 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11426 comparison code that will be tested.
11428 The result is a possibly different comparison code to use. *POP0 and
11429 *POP1 may be updated.
11431 It is possible that we might detect that a comparison is either always
11432 true or always false. However, we do not perform general constant
11433 folding in combine, so this knowledge isn't useful. Such tautologies
11434 should have been detected earlier. Hence we ignore all such cases. */
11436 static enum rtx_code
11438 {
11445 /* Try a few ways of applying the same transformation to both operands. */
11447 {
11448 #ifndef WORD_REGISTER_OPERATIONS
11449 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11450 so check specially. */
11465 - (GET_MODE_PRECISION
11467 {
11470 }
11471 #endif
11473 /* If both operands are the same constant shift, see if we can ignore the
11474 shift. We can if the shift is a rotate or if the bits shifted out of
11475 this shift are known to be zero for both inputs and if the type of
11476 comparison is compatible with the shift. */
11489 {
11502 else
11504 }
11506 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11507 SUBREGs are of the same mode, and, in both cases, the AND would
11508 be redundant if the comparison was done in the narrower mode,
11509 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11510 and the operand's possibly nonzero bits are 0xffffff01; in that case
11511 if we only care about QImode, we don't need the AND). This case
11512 occurs if the output mode of an scc insn is not SImode and
11513 STORE_FLAG_VALUE == 1 (e.g., the 386).
11515 Similarly, check for a case where the AND's are ZERO_EXTEND
11516 operations from some narrower mode even though a SUBREG is not
11517 present. */
11522 {
11539 {
11543 /* The resulting comparison is always unsigned since we masked
11544 off the original sign bit. */
11548 }
11555 {
11561 }
11565 }
11567 /* If both operands are NOT, we can strip off the outer operation
11568 and adjust the comparison code for swapped operands; similarly for
11569 NEG, except that this must be an equality comparison. */
11575 else
11577 }
11579 /* If the first operand is a constant, swap the operands and adjust the
11580 comparison code appropriately, but don't do this if the second operand
11581 is already a constant integer. */
11583 {
11586 }
11588 /* We now enter a loop during which we will try to simplify the comparison.
11589 For the most part, we only are concerned with comparisons with zero,
11590 but some things may really be comparisons with zero but not start
11591 out looking that way. */
11594 {
11601 HOST_WIDE_INT const_op;
11603 /* We only want to handle integral modes. This catches VOIDmode,
11604 CCmode, and the floating-point modes. An exception is that we
11605 can handle VOIDmode if OP0 is a COMPARE or a comparison
11606 operation. */
11613 /* Try to simplify the compare to constant, possibly changing the
11614 comparison op, and/or changing op1 to zero. */
11618 /* Compute some predicates to simplify code below. */
11625 /* If this is a sign bit comparison and we can do arithmetic in
11626 MODE, say that we will only be needing the sign bit of OP0. */
11633 /* Now try cases based on the opcode of OP0. If none of the cases
11634 does a "continue", we exit this loop immediately after the
11635 switch. */
11638 {
11640 /* If we are extracting a single bit from a variable position in
11641 a constant that has only a single bit set and are comparing it
11642 with zero, we can convert this into an equality comparison
11643 between the position and the location of the single bit. */
11644 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11645 have already reduced the shift count modulo the word size. */
11651 {
11659 /* Result is nonzero iff shift count is equal to I. */
11662 }
11664 /* ... fall through ... */
11669 {
11672 }
11676 /* If testing for equality, we can take the NOT of the constant. */
11679 {
11683 }
11685 /* If just looking at the sign bit, reverse the sense of the
11686 comparison. */
11688 {
11692 }
11696 /* If testing for equality, we can take the NEG of the constant. */
11699 {
11703 }
11705 /* The remaining cases only apply to comparisons with zero. */
11709 /* When X is ABS or is known positive,
11710 (neg X) is < 0 if and only if X != 0. */
11718 {
11722 }
11724 /* If we have NEG of something whose two high-order bits are the
11725 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11727 {
11731 }
11735 /* If we are testing equality and our count is a constant, we
11736 can perform the inverse operation on our RHS. */
11740 {
11744 }
11746 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11747 a particular bit. Convert it to an AND of a constant of that
11748 bit. This will be converted into a ZERO_EXTRACT. */
11752 {
11759 }
11761 /* Fall through. */
11764 /* ABS is ignorable inside an equality comparison with zero. */
11766 {
11769 }
11773 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11774 (compare FOO CONST) if CONST fits in FOO's mode and we
11775 are either testing inequality or have an unsigned
11776 comparison with ZERO_EXTEND or a signed comparison with
11777 SIGN_EXTEND. But don't do it if we don't have a compare
11778 insn of the given mode, since we'd have to revert it
11779 later on, and then we wouldn't know whether to sign- or
11780 zero-extend. */
11783 && ! unsigned_comparison_p
11787 {
11790 }
11794 /* Check for the case where we are comparing A - C1 with C2, that is
11796 (subreg:MODE (plus (A) (-C1))) op (C2)
11798 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11799 comparison in the wider mode. One of the following two conditions
11800 must be true in order for this to be valid:
11802 1. The mode extension results in the same bit pattern being added
11803 on both sides and the comparison is equality or unsigned. As
11804 C2 has been truncated to fit in MODE, the pattern can only be
11805 all 0s or all 1s.
11807 2. The mode extension results in the sign bit being copied on
11808 each side.
11810 The difficulty here is that we have predicates for A but not for
11811 (A - C1) so we need to check that C1 is within proper bounds so
11812 as to perturbate A as little as possible. */
11819 {
11828 /* (A - C1) zero-extends if it is positive and sign-extends
11829 if it is negative, C2 both zero- and sign-extends. */
11833 /* (A - C1) sign-extends if it is positive and 1-extends
11834 if it is negative, C2 both sign- and 1-extends. */
11841 /* (A - C1) always sign-extends, like C2. */
11845 {
11848 }
11849 }
11851 /* If the inner mode is narrower and we are extracting the low part,
11852 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11856 else
11859 /* ... fall through ... */
11869 {
11872 }
11876 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11877 this for equality comparisons due to pathological cases involving
11878 overflows. */
11882 {
11886 }
11888 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11891 {
11895 }
11899 /* We used to optimize signed comparisons against zero, but that
11900 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11901 arrive here as equality comparisons, or (GEU, LTU) are
11902 optimized away. No need to special-case them. */
11904 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11905 (eq B (minus A C)), whichever simplifies. We can only do
11906 this for equality comparisons due to pathological cases involving
11907 overflows. */
11911 {
11915 }
11920 {
11924 }
11926 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11927 of bits in X minus 1, is one iff X > 0. */
11932 {
11936 }
11940 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11941 if C is zero or B is a constant. */
11945 {
11949 }
11957 /* We can't do anything if OP0 is a condition code value, rather
11958 than an actual data value. */
11964 /* Get the two operands being compared. */
11967 else
11970 /* Check for the cases where we simply want the result of the
11971 earlier test or the opposite of that result. */
11975 {
11979 else
11983 {
11988 }
11989 }
11993 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11994 iff X <= 0. */
11998 {
12002 }
12006 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12007 will be converted to a ZERO_EXTRACT later. */
12011 {
12016 }
12018 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12019 zero and X is a comparison and C1 and C2 describe only bits set
12020 in STORE_FLAG_VALUE, we can compare with X. */
12028 {
12035 {
12038 }
12039 }
12041 /* If we are doing an equality comparison of an AND of a bit equal
12042 to the sign bit, replace this with a LT or GE comparison of
12043 the underlying value. */
12050 {
12054 }
12056 /* If this AND operation is really a ZERO_EXTEND from a narrower
12057 mode, the constant fits within that mode, and this is either an
12058 equality or unsigned comparison, try to do this comparison in
12059 the narrower mode.
12061 Note that in:
12063 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12064 -> (ne:DI (reg:SI 4) (const_int 0))
12066 unless TRULY_NOOP_TRUNCATION allows it or the register is
12067 known to hold a value of the required mode the
12068 transformation is invalid. */
12079 {
12082 }
12084 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12085 fits in both M1 and M2 and the SUBREG is either paradoxical
12086 or represents the low part, permute the SUBREG and the AND
12087 and try again. */
12089 {
12092 /* Require an integral mode, to avoid creating something like
12093 (AND:SF ...). */
12095 /* It is unsafe to commute the AND into the SUBREG if the
12096 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12097 not defined. As originally written the upper bits
12098 have a defined value due to the AND operation.
12099 However, if we commute the AND inside the SUBREG then
12100 they no longer have defined values and the meaning of
12101 the code has been changed. */
12103 #ifdef WORD_REGISTER_OPERATIONS
12106 #endif
12116 {
12122 }
12123 }
12125 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12129 {
12134 }
12136 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12137 (eq (and (lshiftrt X) 1) 0).
12138 Also handle the case where (not X) is expressed using xor. */
12142 {
12154 {
12155 op0
12160 }
12161 }
12165 /* If we have (compare (ashift FOO N) (const_int C)) and
12166 the high order N bits of FOO (N+1 if an inequality comparison)
12167 are known to be zero, we can do this by comparing FOO with C
12168 shifted right N bits so long as the low-order N bits of C are
12169 zero. */
12181 {
12182 /* We must perform a logical shift, not an arithmetic one,
12183 as we want the top N bits of C to be zero. */
12190 }
12192 /* If we are doing a sign bit comparison, it means we are testing
12193 a particular bit. Convert it to the appropriate AND. */
12196 {
12203 }
12205 /* If this an equality comparison with zero and we are shifting
12206 the low bit to the sign bit, we can convert this to an AND of the
12207 low-order bit. */
12211 {
12214 }
12218 /* If this is an equality comparison with zero, we can do this
12219 as a logical shift, which might be much simpler. */
12222 {
12227 }
12229 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12230 do the comparison in a narrower mode. */
12240 {
12243 }
12245 /* Likewise if OP0 is a PLUS of a sign extension with a
12246 constant, which is usually represented with the PLUS
12247 between the shifts. */
12259 {
12267 new_const);
12269 }
12271 /* ... fall through ... */
12273 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12274 the low order N bits of FOO are known to be zero, we can do this
12275 by comparing FOO with C shifted left N bits so long as no
12276 overflow occurs. Even if the low order N bits of FOO aren't known
12277 to be zero, if the comparison is >= or < we can use the same
12278 optimization and for > or <= by setting all the low
12279 order N bits in the comparison constant. */
12290 {
12291 unsigned HOST_WIDE_INT low_bits
12296 {
12297 /* If the shift was logical, then we must make the condition
12298 unsigned. */
12306 const_op
12311 }
12312 }
12314 /* If we are using this shift to extract just the sign bit, we
12315 can replace this with an LT or GE comparison. */
12320 {
12324 }
12329 }
12332 }
12334 /* Now make any compound operations involved in this comparison. Then,
12335 check for an outmost SUBREG on OP0 that is not doing anything or is
12336 paradoxical. The latter transformation must only be performed when
12337 it is known that the "extra" bits will be the same in op0 and op1 or
12338 that they don't matter. There are three cases to consider:
12340 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12341 care bits and we can assume they have any convenient value. So
12342 making the transformation is safe.
12344 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12345 In this case the upper bits of op0 are undefined. We should not make
12346 the simplification in that case as we do not know the contents of
12347 those bits.
12349 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12350 UNKNOWN. In that case we know those bits are zeros or ones. We must
12351 also be sure that they are the same as the upper bits of op1.
12353 We can never remove a SUBREG for a non-equality comparison because
12354 the sign bit is in a different place in the underlying object. */
12363 {
12365 {
12366 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12367 implemented. */
12369 {
12372 }
12373 }
12379 {
12385 }
12386 }
12388 /* We now do the opposite procedure: Some machines don't have compare
12389 insns in all modes. If OP0's mode is an integer mode smaller than a
12390 word and we can't do a compare in that mode, see if there is a larger
12391 mode for which we can do the compare. There are a number of cases in
12392 which we can use the wider mode. */
12402 {
12405 /* If this is a test for negative, we can make an explicit
12406 test of the sign bit. Test this first so we can use
12407 a paradoxical subreg to extend OP0. */
12411 {
12412 unsigned HOST_WIDE_INT sign
12419 }
12421 /* If the only nonzero bits in OP0 and OP1 are those in the
12422 narrower mode and this is an equality or unsigned comparison,
12423 we can use the wider mode. Similarly for sign-extended
12424 values, in which case it is true for all comparisons. */
12441 {
12442 /* If OP0 is an AND and we don't have an AND in MODE either,
12443 make a new AND in the proper mode. */
12451 else
12452 {
12454 {
12457 }
12458 else
12459 {
12462 }
12464 }
12465 }
12466 }
12468 /* We may have changed the comparison operands. Re-canonicalize. */
12470 {
12473 }
12475 /* If this machine only supports a subset of valid comparisons, see if we
12476 can convert an unsupported one into a supported one. */
12483 }
12484 \f
12485 /* Utility function for record_value_for_reg. Count number of
12486 rtxs in X. */
12487 static int
12489 {
12496 {
12516 }
12527 }
12528 \f
12529 /* Utility function for following routine. Called when X is part of a value
12530 being stored into last_set_value. Sets last_set_table_tick
12531 for each register mentioned. Similar to mention_regs in cse.c */
12533 static void
12535 {
12541 {
12547 {
12550 }
12553 }
12557 {
12558 /* Check for identical subexpressions. If x contains
12559 identical subexpression we only have to traverse one of
12560 them. */
12562 {
12563 /* Note that at this point x1 has already been
12564 processed. */
12568 /* If x0 and x1 are identical then there is no need to
12569 process x0. */
12573 /* If x0 is identical to a subexpression of x1 then while
12574 processing x1, x0 has already been processed. Thus we
12575 are done with x. */
12580 /* If x1 is identical to a subexpression of x0 then we
12581 still have to process the rest of x0. */
12584 {
12587 }
12588 }
12591 }
12595 }
12597 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12598 are saying that the register is clobbered and we no longer know its
12599 value. If INSN is zero, don't update reg_stat[].last_set; this is
12600 only permitted with VALUE also zero and is used to invalidate the
12601 register. */
12603 static void
12605 {
12611 /* If VALUE contains REG and we have a previous value for REG, substitute
12612 the previous value. */
12614 {
12615 rtx tem;
12617 /* Set things up so get_last_value is allowed to see anything set up to
12618 our insn. */
12622 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12623 it isn't going to be useful and will take a lot of time to process,
12624 so just use the CLOBBER. */
12627 {
12633 {
12634 /* If there are two or more occurrences of REG in VALUE,
12635 prevent the value from growing too much. */
12638 }
12641 }
12642 }
12644 /* For each register modified, show we don't know its value, that
12645 we don't know about its bitwise content, that its value has been
12646 updated, and that we don't know the location of the death of the
12647 register. */
12649 {
12661 }
12663 /* Mark registers that are being referenced in this value. */
12667 /* Now update the status of each register being set.
12668 If someone is using this register in this block, set this register
12669 to invalid since we will get confused between the two lives in this
12670 basic block. This makes using this register always invalid. In cse, we
12671 scan the table to invalidate all entries using this register, but this
12672 is too much work for us. */
12675 {
12681 else
12683 }
12685 /* The value being assigned might refer to X (like in "x++;"). In that
12686 case, we must replace it with (clobber (const_int 0)) to prevent
12687 infinite loops. */
12690 {
12694 }
12696 /* For the main register being modified, update the value, the mode, the
12697 nonzero bits, and the number of sign bit copies. */
12702 {
12710 rsp->last_set_sign_bit_copies
12712 }
12713 }
12715 /* Called via note_stores from record_dead_and_set_regs to handle one
12716 SET or CLOBBER in an insn. DATA is the instruction in which the
12717 set is occurring. */
12719 static void
12721 {
12728 {
12732 }
12735 {
12736 /* If we are setting the whole register, we know its value. Otherwise
12737 show that we don't know the value. We can handle SUBREG in
12738 some cases. */
12749 else
12751 }
12753 /* Ignore pushes, they clobber nothing. */
12756 }
12758 /* Update the records of when each REG was most recently set or killed
12759 for the things done by INSN. This is the last thing done in processing
12760 INSN in the combiner loop.
12762 We update reg_stat[], in particular fields last_set, last_set_value,
12763 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12764 last_death, and also the similar information mem_last_set (which insn
12765 most recently modified memory) and last_call_luid (which insn was the
12766 most recent subroutine call). */
12768 static void
12770 {
12771 rtx link;
12775 {
12778 {
12783 {
12788 }
12789 }
12792 }
12795 {
12796 hard_reg_set_iterator hrsi;
12798 {
12810 }
12814 /* We can't combine into a call pattern. Remember, though, that
12815 the return value register is set at this LUID. We could
12816 still replace a register with the return value from the
12817 wrong subroutine call! */
12819 }
12820 else
12822 }
12824 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12825 register present in the SUBREG, so for each such SUBREG go back and
12826 adjust nonzero and sign bit information of the registers that are
12827 known to have some zero/sign bits set.
12829 This is needed because when combine blows the SUBREGs away, the
12830 information on zero/sign bits is lost and further combines can be
12831 missed because of that. */
12833 static void
12835 {
12837 rtx set;
12845 {
12854 {
12857 }
12861 {
12864 }
12867 {
12870 }
12871 else
12873 }
12874 }
12876 /* Check if X, a register, is known to contain a value already
12877 truncated to MODE. In this case we can use a subreg to refer to
12878 the truncated value even though in the generic case we would need
12879 an explicit truncation. */
12881 static bool
12883 {
12895 }
12897 /* If X is a hard reg or a subreg record the mode that the register is
12898 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12899 to turn a truncate into a subreg using this information. Return true
12900 if traversing X is complete. */
12902 static bool
12904 {
12905 machine_mode truncated_mode;
12909 {
12920 }
12921 /* ??? For hard-regs we now record everything. We might be able to
12922 optimize this using last_set_mode. */
12925 else
12933 {
12936 }
12939 }
12941 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12942 the modes they are used in. This can help truning TRUNCATEs into
12943 SUBREGs. */
12945 static void
12947 {
12952 }
12954 /* Scan X for promoted SUBREGs. For each one found,
12955 note what it implies to the registers used in it. */
12957 static void
12959 {
12964 else
12965 {
12971 {
12981 }
12982 }
12983 }
12984 \f
12985 /* Verify that all the registers and memory references mentioned in *LOC are
12986 still valid. *LOC was part of a value set in INSN when label_tick was
12987 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12988 the invalid references with (clobber (const_int 0)) and return 1. This
12989 replacement is useful because we often can get useful information about
12990 the form of a value (e.g., if it was produced by a shift that always
12991 produces -1 or 0) even though we don't know exactly what registers it
12992 was produced from. */
12994 static int
12996 {
13003 {
13009 {
13012 /* If this is a pseudo-register that was only set once and not
13013 live at the beginning of the function, it is always valid. */
13017 && (!REGNO_REG_SET_P
13019 regno)))
13021 {
13025 }
13026 }
13029 }
13030 /* If this is a memory reference, make sure that there were no stores after
13031 it that might have clobbered the value. We don't have alias info, so we
13032 assume any store invalidates it. Moreover, we only have local UIDs, so
13033 we also assume that there were stores in the intervening basic blocks. */
13036 {
13040 }
13043 {
13045 {
13046 /* Check for identical subexpressions. If x contains
13047 identical subexpression we only have to traverse one of
13048 them. */
13050 {
13051 /* Note that at this point x0 has already been checked
13052 and found valid. */
13056 /* If x0 and x1 are identical then x is also valid. */
13060 /* If x1 is identical to a subexpression of x0 then
13061 while checking x0, x1 has already been checked. Thus
13062 it is valid and so as x. */
13067 /* If x0 is identical to a subexpression of x1 then x is
13068 valid iff the rest of x1 is valid. */
13071 return
13075 }
13080 }
13086 }
13088 /* If we haven't found a reason for it to be invalid, it is valid. */
13090 }
13092 /* Get the last value assigned to X, if known. Some registers
13093 in the value may be replaced with (clobber (const_int 0)) if their value
13094 is known longer known reliably. */
13096 static rtx
13098 {
13100 rtx value;
13103 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13104 then convert it to the desired mode. If this is a paradoxical SUBREG,
13105 we cannot predict what values the "extra" bits might have. */
13119 /* If we don't have a value, or if it isn't for this basic block and
13120 it's either a hard register, set more than once, or it's a live
13121 at the beginning of the function, return 0.
13123 Because if it's not live at the beginning of the function then the reg
13124 is always set before being used (is never used without being set).
13125 And, if it's set only once, and it's always set before use, then all
13126 uses must have the same last value, even if it's not from this basic
13127 block. */
13134 || REGNO_REG_SET_P
13138 /* If the value was set in a later insn than the ones we are processing,
13139 we can't use it even if the register was only set once. */
13144 /* If the value has all its registers valid, return it. */
13148 /* Otherwise, make a copy and replace any invalid register with
13149 (clobber (const_int 0)). If that fails for some reason, return 0. */
13156 }
13157 \f
13158 /* Return nonzero if expression X refers to a REG or to memory
13159 that is set in an instruction more recent than FROM_LUID. */
13161 static int
13163 {
13169 {
13173 #ifdef PUSH_ROUNDING
13174 /* Don't allow uses of the stack pointer to be moved,
13175 because we don't know whether the move crosses a push insn. */
13178 #endif
13180 {
13186 }
13188 }
13196 {
13198 {
13203 }
13207 }
13209 }
13210 \f
13211 /* Define three variables used for communication between the following
13212 routines. */
13217 /* Function called via note_stores from reg_dead_at_p.
13219 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13220 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13222 static void
13224 {
13234 }
13236 /* Return nonzero if REG is known to be dead at INSN.
13238 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13239 referencing REG, it is dead. If we hit a SET referencing REG, it is
13240 live. Otherwise, see if it is live or dead at the start of the basic
13241 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13242 must be assumed to be always live. */
13244 static int
13246 {
13247 basic_block block;
13250 /* Set variables for reg_dead_at_p_1. */
13256 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13257 we allow the machine description to decide whether use-and-clobber
13258 patterns are OK. */
13260 {
13264 }
13266 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13267 beginning of basic block. */
13270 {
13272 {
13282 }
13288 }
13290 /* Look at live-in sets for the basic block that we were in. */
13296 }
13297 \f
13298 /* Note hard registers in X that are used. */
13300 static void
13302 {
13308 {
13312 CASE_CONST_ANY:
13317 /* CC0 must die in the insn after it is set, so we don't need to take
13318 special note of it here. */
13323 /* If we are clobbering a MEM, mark any hard registers inside the
13324 address as used. */
13331 /* A hard reg in a wide mode may really be multiple registers.
13332 If so, mark all of them just like the first. */
13334 {
13335 /* None of this applies to the stack, frame or arg pointers. */
13337 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13339 #endif
13346 }
13350 {
13351 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13352 the address. */
13364 }
13369 }
13371 /* Recursively scan the operands of this expression. */
13373 {
13377 {
13381 {
13386 }
13387 }
13388 }
13389 }
13390 \f
13391 /* Remove register number REGNO from the dead registers list of INSN.
13393 Return the note used to record the death, if there was one. */
13395 rtx
13397 {
13404 }
13406 /* For each register (hardware or pseudo) used within expression X, if its
13407 death is in an instruction with luid between FROM_LUID (inclusive) and
13408 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13409 list headed by PNOTES.
13411 That said, don't move registers killed by maybe_kill_insn.
13413 This is done when X is being merged by combination into TO_INSN. These
13414 notes will then be distributed as needed. */
13416 static void
13419 {
13425 {
13429 /* Don't move the register if it gets killed in between from and to. */
13438 {
13441 /* It is possible for the call above to return 0. This can occur
13442 when last_death points to I2 or I1 that we combined with.
13443 In that case make a new note.
13445 We must also check for the case where X is a hard register
13446 and NOTE is a death note for a range of hard registers
13447 including X. In that case, we must put REG_DEAD notes for
13448 the remaining registers in place of NOTE. */
13453 {
13462 }
13464 /* If we didn't find any note, or if we found a REG_DEAD note that
13465 covers only part of the given reg, and we have a multi-reg hard
13466 register, then to be safe we must check for REG_DEAD notes
13467 for each register other than the first. They could have
13468 their own REG_DEAD notes lying around. */
13475 {
13482 else
13488 }
13491 {
13494 }
13495 else
13497 }
13500 }
13503 {
13508 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13509 that accesses one word of a multi-word item, some
13510 piece of everything register in the expression is used by
13511 this insn, so remove any old death. */
13512 /* ??? So why do we test for equality of the sizes? */
13521 {
13524 }
13526 /* If this is some other SUBREG, we know it replaces the entire
13527 value, so use that as the destination. */
13531 /* If this is a MEM, adjust deaths of anything used in the address.
13532 For a REG (the only other possibility), the entire value is
13533 being replaced so the old value is not used in this insn. */
13539 }
13548 {
13550 {
13555 }
13558 }
13559 }
13560 \f
13561 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13562 pattern of an insn. X must be a REG. */
13564 static int
13566 {
13570 {
13572 rtx target;
13579 else
13596 }
13604 }
13605 \f
13606 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13607 as appropriate. I3 and I2 are the insns resulting from the combination
13608 insns including FROM (I2 may be zero).
13610 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13611 not need REG_DEAD notes because they are being substituted for. This
13612 saves searching in the most common cases.
13614 Each note in the list is either ignored or placed on some insns, depending
13615 on the type of note. */
13617 static void
13620 {
13622 rtx tem_note;
13626 {
13631 {
13634 /* Doesn't matter much where we put this, as long as it's somewhere.
13635 It is preferable to keep these notes on branches, which is most
13636 likely to be i3. */
13643 else
13644 {
13647 }
13651 /* These notes must remain with the call or trapping instruction. */
13656 else
13657 {
13663 /* ??? Otherwise assume we've combined things such that we
13664 can now prove that the instructions can't trap. Drop the
13665 note in this case. */
13666 }
13670 /* ??? How to distribute between i3-i1. Assume i3 contains the
13671 entire adjustment. Assert i3 contains at least some adjust. */
13673 {
13675 /* fixup_args_size_notes looks at REG_NORETURN note,
13676 so ensure the note is placed there first. */
13678 {
13682 {
13688 }
13689 }
13691 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13692 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13695 && !ACCUMULATE_OUTGOING_ARGS
13697 }
13704 /* These notes must remain with the call. It should not be
13705 possible for both I2 and I3 to be a call. */
13708 else
13709 {
13712 }
13716 /* Any clobbers for i3 may still exist, and so we must process
13717 REG_UNUSED notes from that insn.
13719 Any clobbers from i2 or i1 can only exist if they were added by
13720 recog_for_combine. In that case, recog_for_combine created the
13721 necessary REG_UNUSED notes. Trying to keep any original
13722 REG_UNUSED notes from these insns can cause incorrect output
13723 if it is for the same register as the original i3 dest.
13724 In that case, we will notice that the register is set in i3,
13725 and then add a REG_UNUSED note for the destination of i3, which
13726 is wrong. However, it is possible to have REG_UNUSED notes from
13727 i2 or i1 for register which were both used and clobbered, so
13728 we keep notes from i2 or i1 if they will turn into REG_DEAD
13729 notes. */
13731 /* If this register is set or clobbered in I3, put the note there
13732 unless there is one already. */
13734 {
13742 }
13743 /* Otherwise, if this register is used by I3, then this register
13744 now dies here, so we must put a REG_DEAD note here unless there
13745 is one already. */
13751 {
13754 }
13760 /* These notes say something about results of an insn. We can
13761 only support them if they used to be on I3 in which case they
13762 remain on I3. Otherwise they are ignored.
13764 If the note refers to an expression that is not a constant, we
13765 must also ignore the note since we cannot tell whether the
13766 equivalence is still true. It might be possible to do
13767 slightly better than this (we only have a problem if I2DEST
13768 or I1DEST is present in the expression), but it doesn't
13769 seem worth the trouble. */
13777 /* These notes say something about how a register is used. They must
13778 be present on any use of the register in I2 or I3. */
13783 {
13786 else
13788 }
13793 /* This can show up in several ways -- either directly in the
13794 pattern, or hidden off in the constant pool with (or without?)
13795 a REG_EQUAL note. */
13796 /* ??? Ignore the without-reg_equal-note problem for now. */
13808 {
13811 else
13813 }
13815 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13816 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13817 there. */
13822 {
13829 }
13835 {
13843 }
13847 /* This note says something about the value of a register prior
13848 to the execution of an insn. It is too much trouble to see
13849 if the note is still correct in all situations. It is better
13850 to simply delete it. */
13854 /* If we replaced the right hand side of FROM_INSN with a
13855 REG_EQUAL note, the original use of the dying register
13856 will not have been combined into I3 and I2. In such cases,
13857 FROM_INSN is guaranteed to be the first of the combined
13858 instructions, so we simply need to search back before
13859 FROM_INSN for the previous use or set of this register,
13860 then alter the notes there appropriately.
13862 If the register is used as an input in I3, it dies there.
13863 Similarly for I2, if it is nonzero and adjacent to I3.
13865 If the register is not used as an input in either I3 or I2
13866 and it is not one of the registers we were supposed to eliminate,
13867 there are two possibilities. We might have a non-adjacent I2
13868 or we might have somehow eliminated an additional register
13869 from a computation. For example, we might have had A & B where
13870 we discover that B will always be zero. In this case we will
13871 eliminate the reference to A.
13873 In both cases, we must search to see if we can find a previous
13874 use of A and put the death note there. */
13880 else
13881 {
13892 && !(i2mod
13894 i2mod_old_rhs)))
13899 /* If the new I2 sets the same register that is marked dead
13900 in the note, the note now should not be put on I2, as the
13901 note refers to a previous incarnation of the reg. */
13904 }
13907 {
13911 {
13913 {
13917 }
13919 /* If the register is being set at TEM_INSN, see if that is all
13920 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13921 into a REG_UNUSED note instead. Don't delete sets to
13922 global register vars. */
13926 {
13937 ;
13939 /* Verify that it was the set, and not a clobber that
13940 modified the register.
13942 CC0 targets must be careful to maintain setter/user
13943 pairs. If we cannot delete the setter due to side
13944 effects, mark the user with an UNUSED note instead
13945 of deleting it. */
13949 #if HAVE_cc0
13953 #endif
13954 )
13955 {
13956 /* Move the notes and links of TEM_INSN elsewhere.
13957 This might delete other dead insns recursively.
13958 First set the pattern to something that won't use
13959 any register. */
13973 /* Delete the setter too. */
13975 {
13988 }
13989 }
13990 else
13991 {
13994 /* If there isn't already a REG_UNUSED note, put one
13995 here. Do not place a REG_DEAD note, even if
13996 the register is also used here; that would not
13997 match the algorithm used in lifetime analysis
13998 and can cause the consistency check in the
13999 scheduler to fail. */
14004 }
14005 }
14009 {
14012 /* If we are doing a 3->2 combination, and we have a
14013 register which formerly died in i3 and was not used
14014 by i2, which now no longer dies in i3 and is used in
14015 i2 but does not die in i2, and place is between i2
14016 and i3, then we may need to move a link from place to
14017 i2. */
14019 && from_insn
14022 {
14026 }
14028 }
14032 }
14034 }
14036 /* If the register is set or already dead at PLACE, we needn't do
14037 anything with this note if it is still a REG_DEAD note.
14038 We check here if it is set at all, not if is it totally replaced,
14039 which is what `dead_or_set_p' checks, so also check for it being
14040 set partially. */
14043 {
14049 {
14050 /* Unless the register previously died in PLACE, clear
14051 last_death. [I no longer understand why this is
14052 being done.] */
14056 }
14057 else
14060 /* If this is a death note for a hard reg that is occupying
14061 multiple registers, ensure that we are still using all
14062 parts of the object. If we find a piece of the object
14063 that is unused, we must arrange for an appropriate REG_DEAD
14064 note to be added for it. However, we can't just emit a USE
14065 and tag the note to it, since the register might actually
14066 be dead; so we recourse, and the recursive call then finds
14067 the previous insn that used this register. */
14070 {
14079 {
14082 }
14085 {
14086 /* Put only REG_DEAD notes for pieces that are
14087 not already dead or set. */
14091 {
14098 {
14100 NULL_RTX);
14104 NULL_RTX);
14105 }
14110 {
14112 {
14116 }
14120 {
14123 }
14124 }
14125 }
14128 }
14129 }
14130 }
14134 /* Any other notes should not be present at this point in the
14135 compilation. */
14137 }
14140 {
14143 }
14147 }
14148 }
14149 \f
14150 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14151 I3, I2, and I1 to new locations. This is also called to add a link
14152 pointing at I3 when I3's destination is changed. */
14154 static void
14156 {
14160 {
14167 /* If the insn that this link points to is a NOTE, ignore it. */
14176 {
14179 {
14195 }
14198 }
14199 else
14209 /* A LOG_LINK is defined as being placed on the first insn that uses
14210 a register and points to the insn that sets the register. Start
14211 searching at the next insn after the target of the link and stop
14212 when we reach a set of the register or the end of the basic block.
14214 Note that this correctly handles the link that used to point from
14215 I3 to I2. Also note that not much searching is typically done here
14216 since most links don't point very far away. */
14225 {
14229 }
14232 {
14235 }
14239 /* If we found a place to put the link, place it there unless there
14240 is already a link to the same insn as LINK at that point. */
14243 {
14251 {
14255 /* Set added_links_insn to the earliest insn we added a
14256 link to. */
14260 }
14261 }
14262 }
14263 }
14264 \f
14265 /* Check for any register or memory mentioned in EQUIV that is not
14266 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14267 of EXPR where some registers may have been replaced by constants. */
14269 static bool
14271 {
14274 {
14279 }
14281 }
14282 \f
14283 DEBUG_FUNCTION void
14285 {
14286 fprintf
14288 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14290 }
14292 void
14294 {
14295 fprintf
14297 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14299 }
14300 \f
14301 /* Try combining insns through substitution. */
14302 static unsigned int
14304 {
14314 rebuild_jump_labels_after_combine
14317 /* Combining insns may have turned an indirect jump into a
14318 direct jump. Rebuild the JUMP_LABEL fields of jumping
14319 instructions. */
14321 {
14326 }
14330 }
14335 {
14345 };
14348 {
14352 {}
14354 /* opt_pass methods: */
14357 {
14359 }
14365 rtl_opt_pass *
14367 {
14369 }