2 /* Perform branch target register load optimizations.
3 Copyright (C) 2001-2015 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "hard-reg-set.h"
35 #include "insn-config.h"
44 #include "insn-attr.h"
47 #include "diagnostic-core.h"
48 #include "tree-pass.h"
50 #include "dominance.h"
54 #include "cfgcleanup.h"
56 #include "basic-block.h"
60 #include "fibonacci_heap.h"
62 /* Target register optimizations - these are performed after reload. */
64 typedef struct btr_def_group_s
66 struct btr_def_group_s
*next
;
68 struct btr_def_s
*members
;
71 typedef struct btr_user_s
73 struct btr_user_s
*next
;
77 /* If INSN has a single use of a single branch register, then
78 USE points to it within INSN. If there is more than
79 one branch register use, or the use is in some way ambiguous,
83 int first_reaching_def
;
84 char other_use_this_block
;
87 /* btr_def structs appear on three lists:
88 1. A list of all btr_def structures (head is
89 ALL_BTR_DEFS, linked by the NEXT field).
90 2. A list of branch reg definitions per basic block (head is
91 BB_BTR_DEFS[i], linked by the NEXT_THIS_BB field).
92 3. A list of all branch reg definitions belonging to the same
93 group (head is in a BTR_DEF_GROUP struct, linked by
94 NEXT_THIS_GROUP field). */
96 typedef struct btr_def_s
98 struct btr_def_s
*next_this_bb
;
99 struct btr_def_s
*next_this_group
;
105 /* For a branch register setting insn that has a constant
106 source (i.e. a label), group links together all the
107 insns with the same source. For other branch register
108 setting insns, group is NULL. */
111 /* If this def has a reaching use which is not a simple use
112 in a branch instruction, then has_ambiguous_use will be true,
113 and we will not attempt to migrate this definition. */
114 char has_ambiguous_use
;
115 /* live_range is an approximation to the true live range for this
116 def/use web, because it records the set of blocks that contain
117 the live range. There could be other live ranges for the same
118 branch register in that set of blocks, either in the block
119 containing the def (before the def), or in a block containing
120 a use (after the use). If there are such other live ranges, then
121 other_btr_uses_before_def or other_btr_uses_after_use must be set true
123 char other_btr_uses_before_def
;
124 char other_btr_uses_after_use
;
125 /* We set own_end when we have moved a definition into a dominator.
126 Thus, when a later combination removes this definition again, we know
127 to clear out trs_live_at_end again. */
132 typedef fibonacci_heap
<long, btr_def_s
> btr_heap_t
;
133 typedef fibonacci_node
<long, btr_def_s
> btr_heap_node_t
;
135 static int issue_rate
;
137 static int basic_block_freq (const_basic_block
);
138 static int insn_sets_btr_p (const rtx_insn
*, int, int *);
139 static void find_btr_def_group (btr_def_group
*, btr_def
);
140 static btr_def
add_btr_def (btr_heap_t
*, basic_block
, int, rtx_insn
*,
141 unsigned int, int, btr_def_group
*);
142 static btr_user
new_btr_user (basic_block
, int, rtx_insn
*);
143 static void dump_hard_reg_set (HARD_REG_SET
);
144 static void dump_btrs_live (int);
145 static void note_other_use_this_block (unsigned int, btr_user
);
146 static void compute_defs_uses_and_gen (btr_heap_t
*, btr_def
*,btr_user
*,
147 sbitmap
*, sbitmap
*, HARD_REG_SET
*);
148 static void compute_kill (sbitmap
*, sbitmap
*, HARD_REG_SET
*);
149 static void compute_out (sbitmap
*bb_out
, sbitmap
*, sbitmap
*, int);
150 static void link_btr_uses (btr_def
*, btr_user
*, sbitmap
*, sbitmap
*, int);
151 static void build_btr_def_use_webs (btr_heap_t
*);
152 static int block_at_edge_of_live_range_p (int, btr_def
);
153 static void clear_btr_from_live_range (btr_def def
);
154 static void add_btr_to_live_range (btr_def
, int);
155 static void augment_live_range (bitmap
, HARD_REG_SET
*, basic_block
,
157 static int choose_btr (HARD_REG_SET
);
158 static void combine_btr_defs (btr_def
, HARD_REG_SET
*);
159 static void btr_def_live_range (btr_def
, HARD_REG_SET
*);
160 static void move_btr_def (basic_block
, int, btr_def
, bitmap
, HARD_REG_SET
*);
161 static int migrate_btr_def (btr_def
, int);
162 static void migrate_btr_defs (enum reg_class
, int);
163 static int can_move_up (const_basic_block
, const rtx_insn
*, int);
164 static void note_btr_set (rtx
, const_rtx
, void *);
166 /* The following code performs code motion of target load instructions
167 (instructions that set branch target registers), to move them
168 forward away from the branch instructions and out of loops (or,
169 more generally, from a more frequently executed place to a less
170 frequently executed place).
171 Moving target load instructions further in front of the branch
172 instruction that uses the target register value means that the hardware
173 has a better chance of preloading the instructions at the branch
174 target by the time the branch is reached. This avoids bubbles
175 when a taken branch needs to flush out the pipeline.
176 Moving target load instructions out of loops means they are executed
179 /* An obstack to hold the def-use web data structures built up for
180 migrating branch target load instructions. */
181 static struct obstack migrate_btrl_obstack
;
183 /* Array indexed by basic block number, giving the set of registers
184 live in that block. */
185 static HARD_REG_SET
*btrs_live
;
187 /* Array indexed by basic block number, giving the set of registers live at
188 the end of that block, including any uses by a final jump insn, if any. */
189 static HARD_REG_SET
*btrs_live_at_end
;
191 /* Set of all target registers that we are willing to allocate. */
192 static HARD_REG_SET all_btrs
;
194 /* Provide lower and upper bounds for target register numbers, so that
195 we don't need to search through all the hard registers all the time. */
196 static int first_btr
, last_btr
;
200 /* Return an estimate of the frequency of execution of block bb. */
202 basic_block_freq (const_basic_block bb
)
204 return bb
->frequency
;
207 /* If X references (sets or reads) any branch target register, return one
208 such register. If EXCLUDEP is set, disregard any references within
211 find_btr_use (rtx x
, rtx
*excludep
= 0)
213 subrtx_ptr_iterator::array_type array
;
214 FOR_EACH_SUBRTX_PTR (iter
, array
, &x
, NONCONST
)
218 iter
.skip_subrtxes ();
223 && overlaps_hard_reg_set_p (all_btrs
, GET_MODE (x
), REGNO (x
)))
230 /* Return true if insn is an instruction that sets a target register.
231 if CHECK_CONST is true, only return true if the source is constant.
232 If such a set is found and REGNO is nonzero, assign the register number
233 of the destination register to *REGNO. */
235 insn_sets_btr_p (const rtx_insn
*insn
, int check_const
, int *regno
)
239 if (NONJUMP_INSN_P (insn
)
240 && (set
= single_set (insn
)))
242 rtx dest
= SET_DEST (set
);
243 rtx src
= SET_SRC (set
);
245 if (GET_CODE (dest
) == SUBREG
)
246 dest
= XEXP (dest
, 0);
249 && TEST_HARD_REG_BIT (all_btrs
, REGNO (dest
)))
251 gcc_assert (!find_btr_use (src
));
253 if (!check_const
|| CONSTANT_P (src
))
256 *regno
= REGNO (dest
);
264 /* Find the group that the target register definition DEF belongs
265 to in the list starting with *ALL_BTR_DEF_GROUPS. If no such
266 group exists, create one. Add def to the group. */
268 find_btr_def_group (btr_def_group
*all_btr_def_groups
, btr_def def
)
270 if (insn_sets_btr_p (def
->insn
, 1, NULL
))
272 btr_def_group this_group
;
273 rtx def_src
= SET_SRC (single_set (def
->insn
));
275 /* ?? This linear search is an efficiency concern, particularly
276 as the search will almost always fail to find a match. */
277 for (this_group
= *all_btr_def_groups
;
279 this_group
= this_group
->next
)
280 if (rtx_equal_p (def_src
, this_group
->src
))
285 this_group
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_group_s
);
286 this_group
->src
= def_src
;
287 this_group
->members
= NULL
;
288 this_group
->next
= *all_btr_def_groups
;
289 *all_btr_def_groups
= this_group
;
291 def
->group
= this_group
;
292 def
->next_this_group
= this_group
->members
;
293 this_group
->members
= def
;
299 /* Create a new target register definition structure, for a definition in
300 block BB, instruction INSN, and insert it into ALL_BTR_DEFS. Return
301 the new definition. */
303 add_btr_def (btr_heap_t
*all_btr_defs
, basic_block bb
, int insn_luid
,
305 unsigned int dest_reg
, int other_btr_uses_before_def
,
306 btr_def_group
*all_btr_def_groups
)
308 btr_def this_def
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_s
);
310 this_def
->luid
= insn_luid
;
311 this_def
->insn
= insn
;
312 this_def
->btr
= dest_reg
;
313 this_def
->cost
= basic_block_freq (bb
);
314 this_def
->has_ambiguous_use
= 0;
315 this_def
->other_btr_uses_before_def
= other_btr_uses_before_def
;
316 this_def
->other_btr_uses_after_use
= 0;
317 this_def
->next_this_bb
= NULL
;
318 this_def
->next_this_group
= NULL
;
319 this_def
->uses
= NULL
;
320 this_def
->live_range
= NULL
;
321 find_btr_def_group (all_btr_def_groups
, this_def
);
323 all_btr_defs
->insert (-this_def
->cost
, this_def
);
327 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
328 dest_reg
, bb
->index
, INSN_UID (insn
),
329 (this_def
->group
? "" : ":not const"), this_def
->cost
);
334 /* Create a new target register user structure, for a use in block BB,
335 instruction INSN. Return the new user. */
337 new_btr_user (basic_block bb
, int insn_luid
, rtx_insn
*insn
)
339 /* This instruction reads target registers. We need
340 to decide whether we can replace all target register
343 rtx
*usep
= find_btr_use (PATTERN (insn
));
345 btr_user user
= NULL
;
349 int unambiguous_single_use
;
351 /* We want to ensure that USE is the only use of a target
352 register in INSN, so that we know that to rewrite INSN to use
353 a different target register, all we have to do is replace USE. */
354 unambiguous_single_use
= !find_btr_use (PATTERN (insn
), usep
);
355 if (!unambiguous_single_use
)
358 use
= usep
? *usep
: NULL_RTX
;
359 user
= XOBNEW (&migrate_btrl_obstack
, struct btr_user_s
);
361 user
->luid
= insn_luid
;
364 user
->other_use_this_block
= 0;
366 user
->n_reaching_defs
= 0;
367 user
->first_reaching_def
= -1;
371 fprintf (dump_file
, "Uses target reg: { bb %d, insn %d }",
372 bb
->index
, INSN_UID (insn
));
375 fprintf (dump_file
, ": unambiguous use of reg %d\n",
382 /* Write the contents of S to the dump file. */
384 dump_hard_reg_set (HARD_REG_SET s
)
387 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
388 if (TEST_HARD_REG_BIT (s
, reg
))
389 fprintf (dump_file
, " %d", reg
);
392 /* Write the set of target regs live in block BB to the dump file. */
394 dump_btrs_live (int bb
)
396 fprintf (dump_file
, "BB%d live:", bb
);
397 dump_hard_reg_set (btrs_live
[bb
]);
398 fprintf (dump_file
, "\n");
401 /* REGNO is the number of a branch target register that is being used or
402 set. USERS_THIS_BB is a list of preceding branch target register users;
403 If any of them use the same register, set their other_use_this_block
406 note_other_use_this_block (unsigned int regno
, btr_user users_this_bb
)
410 for (user
= users_this_bb
; user
!= NULL
; user
= user
->next
)
411 if (user
->use
&& REGNO (user
->use
) == regno
)
412 user
->other_use_this_block
= 1;
416 btr_user users_this_bb
;
417 HARD_REG_SET btrs_written_in_block
;
418 HARD_REG_SET btrs_live_in_block
;
423 /* Called via note_stores or directly to register stores into /
424 clobbers of a branch target register DEST that are not recognized as
425 straightforward definitions. DATA points to information about the
426 current basic block that needs updating. */
428 note_btr_set (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
, void *data
)
430 defs_uses_info
*info
= (defs_uses_info
*) data
;
431 int regno
, end_regno
;
435 regno
= REGNO (dest
);
436 end_regno
= END_REGNO (dest
);
437 for (; regno
< end_regno
; regno
++)
438 if (TEST_HARD_REG_BIT (all_btrs
, regno
))
440 note_other_use_this_block (regno
, info
->users_this_bb
);
441 SET_HARD_REG_BIT (info
->btrs_written_in_block
, regno
);
442 SET_HARD_REG_BIT (info
->btrs_live_in_block
, regno
);
443 bitmap_and_compl (info
->bb_gen
, info
->bb_gen
,
444 info
->btr_defset
[regno
- first_btr
]);
449 compute_defs_uses_and_gen (btr_heap_t
*all_btr_defs
, btr_def
*def_array
,
450 btr_user
*use_array
, sbitmap
*btr_defset
,
451 sbitmap
*bb_gen
, HARD_REG_SET
*btrs_written
)
453 /* Scan the code building up the set of all defs and all uses.
454 For each target register, build the set of defs of that register.
455 For each block, calculate the set of target registers
456 written in that block.
457 Also calculate the set of btrs ever live in that block.
461 btr_def_group all_btr_def_groups
= NULL
;
464 bitmap_vector_clear (bb_gen
, last_basic_block_for_fn (cfun
));
465 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
467 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
469 btr_def defs_this_bb
= NULL
;
474 info
.users_this_bb
= NULL
;
475 info
.bb_gen
= bb_gen
[i
];
476 info
.btr_defset
= btr_defset
;
478 CLEAR_HARD_REG_SET (info
.btrs_live_in_block
);
479 CLEAR_HARD_REG_SET (info
.btrs_written_in_block
);
480 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
481 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
482 && REGNO_REG_SET_P (df_get_live_in (bb
), reg
))
483 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
485 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
487 insn
= NEXT_INSN (insn
), insn_luid
++)
492 int insn_uid
= INSN_UID (insn
);
494 if (insn_sets_btr_p (insn
, 0, ®no
))
496 btr_def def
= add_btr_def (
497 all_btr_defs
, bb
, insn_luid
, insn
, regno
,
498 TEST_HARD_REG_BIT (info
.btrs_live_in_block
, regno
),
499 &all_btr_def_groups
);
501 def_array
[insn_uid
] = def
;
502 SET_HARD_REG_BIT (info
.btrs_written_in_block
, regno
);
503 SET_HARD_REG_BIT (info
.btrs_live_in_block
, regno
);
504 bitmap_and_compl (bb_gen
[i
], bb_gen
[i
],
505 btr_defset
[regno
- first_btr
]);
506 bitmap_set_bit (bb_gen
[i
], insn_uid
);
507 def
->next_this_bb
= defs_this_bb
;
509 bitmap_set_bit (btr_defset
[regno
- first_btr
], insn_uid
);
510 note_other_use_this_block (regno
, info
.users_this_bb
);
512 /* Check for the blockage emitted by expand_nl_goto_receiver. */
513 else if (cfun
->has_nonlocal_label
514 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
)
518 /* Do the equivalent of calling note_other_use_this_block
519 for every target register. */
520 for (user
= info
.users_this_bb
; user
!= NULL
;
523 user
->other_use_this_block
= 1;
524 IOR_HARD_REG_SET (info
.btrs_written_in_block
, all_btrs
);
525 IOR_HARD_REG_SET (info
.btrs_live_in_block
, all_btrs
);
526 bitmap_clear (info
.bb_gen
);
530 if (find_btr_use (PATTERN (insn
)))
532 btr_user user
= new_btr_user (bb
, insn_luid
, insn
);
534 use_array
[insn_uid
] = user
;
536 SET_HARD_REG_BIT (info
.btrs_live_in_block
,
541 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
542 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
543 && refers_to_regno_p (reg
, user
->insn
))
545 note_other_use_this_block (reg
,
547 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
549 note_stores (PATTERN (insn
), note_btr_set
, &info
);
551 user
->next
= info
.users_this_bb
;
552 info
.users_this_bb
= user
;
556 HARD_REG_SET
*clobbered
= &call_used_reg_set
;
557 HARD_REG_SET call_saved
;
558 rtx pat
= PATTERN (insn
);
561 /* Check for sibcall. */
562 if (GET_CODE (pat
) == PARALLEL
)
563 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
564 if (ANY_RETURN_P (XVECEXP (pat
, 0, i
)))
566 COMPL_HARD_REG_SET (call_saved
,
568 clobbered
= &call_saved
;
571 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
572 if (TEST_HARD_REG_BIT (*clobbered
, regno
))
573 note_btr_set (regno_reg_rtx
[regno
], NULL_RTX
, &info
);
579 COPY_HARD_REG_SET (btrs_live
[i
], info
.btrs_live_in_block
);
580 COPY_HARD_REG_SET (btrs_written
[i
], info
.btrs_written_in_block
);
582 REG_SET_TO_HARD_REG_SET (btrs_live_at_end
[i
], df_get_live_out (bb
));
583 /* If this block ends in a jump insn, add any uses or even clobbers
584 of branch target registers that it might have. */
585 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
) && ! INSN_P (insn
); )
586 insn
= PREV_INSN (insn
);
587 /* ??? for the fall-through edge, it would make sense to insert the
588 btr set on the edge, but that would require to split the block
589 early on so that we can distinguish between dominance from the fall
590 through edge - which can use the call-clobbered registers - from
591 dominance by the throw edge. */
592 if (can_throw_internal (insn
))
596 COPY_HARD_REG_SET (tmp
, call_used_reg_set
);
597 AND_HARD_REG_SET (tmp
, all_btrs
);
598 IOR_HARD_REG_SET (btrs_live_at_end
[i
], tmp
);
601 if (can_throw
|| JUMP_P (insn
))
605 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
606 if (refers_to_regno_p (regno
, insn
))
607 SET_HARD_REG_BIT (btrs_live_at_end
[i
], regno
);
616 compute_kill (sbitmap
*bb_kill
, sbitmap
*btr_defset
,
617 HARD_REG_SET
*btrs_written
)
622 /* For each basic block, form the set BB_KILL - the set
623 of definitions that the block kills. */
624 bitmap_vector_clear (bb_kill
, last_basic_block_for_fn (cfun
));
625 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
627 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
628 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
629 && TEST_HARD_REG_BIT (btrs_written
[i
], regno
))
630 bitmap_ior (bb_kill
[i
], bb_kill
[i
],
631 btr_defset
[regno
- first_btr
]);
636 compute_out (sbitmap
*bb_out
, sbitmap
*bb_gen
, sbitmap
*bb_kill
, int max_uid
)
638 /* Perform iterative dataflow:
639 Initially, for all blocks, BB_OUT = BB_GEN.
641 BB_IN = union over predecessors of BB_OUT(pred)
642 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
643 Iterate until the bb_out sets stop growing. */
646 sbitmap bb_in
= sbitmap_alloc (max_uid
);
648 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
649 bitmap_copy (bb_out
[i
], bb_gen
[i
]);
655 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
657 bitmap_union_of_preds (bb_in
, bb_out
, BASIC_BLOCK_FOR_FN (cfun
, i
));
658 changed
|= bitmap_ior_and_compl (bb_out
[i
], bb_gen
[i
],
662 sbitmap_free (bb_in
);
666 link_btr_uses (btr_def
*def_array
, btr_user
*use_array
, sbitmap
*bb_out
,
667 sbitmap
*btr_defset
, int max_uid
)
670 sbitmap reaching_defs
= sbitmap_alloc (max_uid
);
672 /* Link uses to the uses lists of all of their reaching defs.
673 Count up the number of reaching defs of each use. */
674 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
676 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
680 bitmap_union_of_preds (reaching_defs
, bb_out
, BASIC_BLOCK_FOR_FN (cfun
, i
));
681 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
683 insn
= NEXT_INSN (insn
))
687 int insn_uid
= INSN_UID (insn
);
689 btr_def def
= def_array
[insn_uid
];
690 btr_user user
= use_array
[insn_uid
];
693 /* Remove all reaching defs of regno except
695 bitmap_and_compl (reaching_defs
, reaching_defs
,
696 btr_defset
[def
->btr
- first_btr
]);
697 bitmap_set_bit (reaching_defs
, insn_uid
);
702 /* Find all the reaching defs for this use. */
703 sbitmap reaching_defs_of_reg
= sbitmap_alloc (max_uid
);
704 unsigned int uid
= 0;
705 sbitmap_iterator sbi
;
709 reaching_defs_of_reg
,
711 btr_defset
[REGNO (user
->use
) - first_btr
]);
716 bitmap_clear (reaching_defs_of_reg
);
717 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
718 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
719 && refers_to_regno_p (reg
, user
->insn
))
720 bitmap_or_and (reaching_defs_of_reg
,
721 reaching_defs_of_reg
,
723 btr_defset
[reg
- first_btr
]);
725 EXECUTE_IF_SET_IN_BITMAP (reaching_defs_of_reg
, 0, uid
, sbi
)
727 btr_def def
= def_array
[uid
];
729 /* We now know that def reaches user. */
733 "Def in insn %d reaches use in insn %d\n",
736 user
->n_reaching_defs
++;
738 def
->has_ambiguous_use
= 1;
739 if (user
->first_reaching_def
!= -1)
740 { /* There is more than one reaching def. This is
741 a rare case, so just give up on this def/use
742 web when it occurs. */
743 def
->has_ambiguous_use
= 1;
744 def_array
[user
->first_reaching_def
]
745 ->has_ambiguous_use
= 1;
748 "(use %d has multiple reaching defs)\n",
752 user
->first_reaching_def
= uid
;
753 if (user
->other_use_this_block
)
754 def
->other_btr_uses_after_use
= 1;
755 user
->next
= def
->uses
;
758 sbitmap_free (reaching_defs_of_reg
);
765 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
766 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
767 && TEST_HARD_REG_BIT (call_used_reg_set
, regno
))
768 bitmap_and_compl (reaching_defs
, reaching_defs
,
769 btr_defset
[regno
- first_btr
]);
774 sbitmap_free (reaching_defs
);
778 build_btr_def_use_webs (btr_heap_t
*all_btr_defs
)
780 const int max_uid
= get_max_uid ();
781 btr_def
*def_array
= XCNEWVEC (btr_def
, max_uid
);
782 btr_user
*use_array
= XCNEWVEC (btr_user
, max_uid
);
783 sbitmap
*btr_defset
= sbitmap_vector_alloc (
784 (last_btr
- first_btr
) + 1, max_uid
);
785 sbitmap
*bb_gen
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
),
787 HARD_REG_SET
*btrs_written
= XCNEWVEC (HARD_REG_SET
,
788 last_basic_block_for_fn (cfun
));
792 bitmap_vector_clear (btr_defset
, (last_btr
- first_btr
) + 1);
794 compute_defs_uses_and_gen (all_btr_defs
, def_array
, use_array
, btr_defset
,
795 bb_gen
, btrs_written
);
797 bb_kill
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
), max_uid
);
798 compute_kill (bb_kill
, btr_defset
, btrs_written
);
801 bb_out
= sbitmap_vector_alloc (last_basic_block_for_fn (cfun
), max_uid
);
802 compute_out (bb_out
, bb_gen
, bb_kill
, max_uid
);
804 sbitmap_vector_free (bb_gen
);
805 sbitmap_vector_free (bb_kill
);
807 link_btr_uses (def_array
, use_array
, bb_out
, btr_defset
, max_uid
);
809 sbitmap_vector_free (bb_out
);
810 sbitmap_vector_free (btr_defset
);
815 /* Return true if basic block BB contains the start or end of the
816 live range of the definition DEF, AND there are other live
817 ranges of the same target register that include BB. */
819 block_at_edge_of_live_range_p (int bb
, btr_def def
)
821 if (def
->other_btr_uses_before_def
822 && BASIC_BLOCK_FOR_FN (cfun
, bb
) == def
->bb
)
824 else if (def
->other_btr_uses_after_use
)
827 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
828 if (BASIC_BLOCK_FOR_FN (cfun
, bb
) == user
->bb
)
834 /* We are removing the def/use web DEF. The target register
835 used in this web is therefore no longer live in the live range
836 of this web, so remove it from the live set of all basic blocks
837 in the live range of the web.
838 Blocks at the boundary of the live range may contain other live
839 ranges for the same target register, so we have to be careful
840 to remove the target register from the live set of these blocks
841 only if they do not contain other live ranges for the same register. */
843 clear_btr_from_live_range (btr_def def
)
848 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
850 if ((!def
->other_btr_uses_before_def
851 && !def
->other_btr_uses_after_use
)
852 || !block_at_edge_of_live_range_p (bb
, def
))
854 CLEAR_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
855 CLEAR_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
861 CLEAR_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
865 /* We are adding the def/use web DEF. Add the target register used
866 in this web to the live set of all of the basic blocks that contain
867 the live range of the web.
868 If OWN_END is set, also show that the register is live from our
869 definitions at the end of the basic block where it is defined. */
871 add_btr_to_live_range (btr_def def
, int own_end
)
876 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
878 SET_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
879 SET_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
885 SET_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
890 /* Update a live range to contain the basic block NEW_BLOCK, and all
891 blocks on paths between the existing live range and NEW_BLOCK.
892 HEAD is a block contained in the existing live range that dominates
893 all other blocks in the existing live range.
894 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
895 are live in the blocks that we add to the live range.
896 If FULL_RANGE is set, include the full live range of NEW_BB;
897 otherwise, if NEW_BB dominates HEAD_BB, only add registers that
898 are life at the end of NEW_BB for NEW_BB itself.
899 It is a precondition that either NEW_BLOCK dominates HEAD,or
900 HEAD dom NEW_BLOCK. This is used to speed up the
901 implementation of this function. */
903 augment_live_range (bitmap live_range
, HARD_REG_SET
*btrs_live_in_range
,
904 basic_block head_bb
, basic_block new_bb
, int full_range
)
906 basic_block
*worklist
, *tos
;
908 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
910 if (dominated_by_p (CDI_DOMINATORS
, new_bb
, head_bb
))
912 if (new_bb
== head_bb
)
915 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_bb
->index
]);
925 int new_block
= new_bb
->index
;
927 gcc_assert (dominated_by_p (CDI_DOMINATORS
, head_bb
, new_bb
));
929 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[head_bb
->index
]);
930 bitmap_set_bit (live_range
, new_block
);
931 /* A previous btr migration could have caused a register to be
932 live just at the end of new_block which we need in full, so
933 use trs_live_at_end even if full_range is set. */
934 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live_at_end
[new_block
]);
936 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_block
]);
940 "Adding end of block %d and rest of %d to live range\n",
941 new_block
, head_bb
->index
);
942 fprintf (dump_file
,"Now live btrs are ");
943 dump_hard_reg_set (*btrs_live_in_range
);
944 fprintf (dump_file
, "\n");
946 FOR_EACH_EDGE (e
, ei
, head_bb
->preds
)
950 while (tos
!= worklist
)
952 basic_block bb
= *--tos
;
953 if (!bitmap_bit_p (live_range
, bb
->index
))
958 bitmap_set_bit (live_range
, bb
->index
);
959 IOR_HARD_REG_SET (*btrs_live_in_range
,
960 btrs_live
[bb
->index
]);
961 /* A previous btr migration could have caused a register to be
962 live just at the end of a block which we need in full. */
963 IOR_HARD_REG_SET (*btrs_live_in_range
,
964 btrs_live_at_end
[bb
->index
]);
968 "Adding block %d to live range\n", bb
->index
);
969 fprintf (dump_file
,"Now live btrs are ");
970 dump_hard_reg_set (*btrs_live_in_range
);
971 fprintf (dump_file
, "\n");
974 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
976 basic_block pred
= e
->src
;
977 if (!bitmap_bit_p (live_range
, pred
->index
))
986 /* Return the most desirable target register that is not in
987 the set USED_BTRS. */
989 choose_btr (HARD_REG_SET used_btrs
)
993 if (!hard_reg_set_subset_p (all_btrs
, used_btrs
))
994 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
996 #ifdef REG_ALLOC_ORDER
997 int regno
= reg_alloc_order
[i
];
1001 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
1002 && !TEST_HARD_REG_BIT (used_btrs
, regno
))
1008 /* Calculate the set of basic blocks that contain the live range of
1009 the def/use web DEF.
1010 Also calculate the set of target registers that are live at time
1011 in this live range, but ignore the live range represented by DEF
1012 when calculating this set. */
1014 btr_def_live_range (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1016 if (!def
->live_range
)
1020 def
->live_range
= BITMAP_ALLOC (NULL
);
1022 bitmap_set_bit (def
->live_range
, def
->bb
->index
);
1023 COPY_HARD_REG_SET (*btrs_live_in_range
,
1024 (flag_btr_bb_exclusive
1025 ? btrs_live
: btrs_live_at_end
)[def
->bb
->index
]);
1027 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1028 augment_live_range (def
->live_range
, btrs_live_in_range
,
1030 (flag_btr_bb_exclusive
1031 || user
->insn
!= BB_END (def
->bb
)
1032 || !JUMP_P (user
->insn
)));
1036 /* def->live_range is accurate, but we need to recompute
1037 the set of target registers live over it, because migration
1038 of other PT instructions may have affected it.
1041 unsigned def_bb
= flag_btr_bb_exclusive
? -1 : def
->bb
->index
;
1044 CLEAR_HARD_REG_SET (*btrs_live_in_range
);
1045 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
1047 IOR_HARD_REG_SET (*btrs_live_in_range
,
1049 ? btrs_live_at_end
: btrs_live
) [bb
]);
1052 if (!def
->other_btr_uses_before_def
&&
1053 !def
->other_btr_uses_after_use
)
1054 CLEAR_HARD_REG_BIT (*btrs_live_in_range
, def
->btr
);
1057 /* Merge into the def/use web DEF any other def/use webs in the same
1058 group that are dominated by DEF, provided that there is a target
1059 register available to allocate to the merged web. */
1061 combine_btr_defs (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1065 for (other_def
= def
->group
->members
;
1067 other_def
= other_def
->next_this_group
)
1069 if (other_def
!= def
1070 && other_def
->uses
!= NULL
1071 && ! other_def
->has_ambiguous_use
1072 && dominated_by_p (CDI_DOMINATORS
, other_def
->bb
, def
->bb
))
1074 /* def->bb dominates the other def, so def and other_def could
1076 /* Merge their live ranges, and get the set of
1077 target registers live over the merged range. */
1079 HARD_REG_SET combined_btrs_live
;
1080 bitmap combined_live_range
= BITMAP_ALLOC (NULL
);
1083 if (other_def
->live_range
== NULL
)
1085 HARD_REG_SET dummy_btrs_live_in_range
;
1086 btr_def_live_range (other_def
, &dummy_btrs_live_in_range
);
1088 COPY_HARD_REG_SET (combined_btrs_live
, *btrs_live_in_range
);
1089 bitmap_copy (combined_live_range
, def
->live_range
);
1091 for (user
= other_def
->uses
; user
!= NULL
; user
= user
->next
)
1092 augment_live_range (combined_live_range
, &combined_btrs_live
,
1094 (flag_btr_bb_exclusive
1095 || user
->insn
!= BB_END (def
->bb
)
1096 || !JUMP_P (user
->insn
)));
1098 btr
= choose_btr (combined_btrs_live
);
1101 /* We can combine them. */
1104 "Combining def in insn %d with def in insn %d\n",
1105 INSN_UID (other_def
->insn
), INSN_UID (def
->insn
));
1108 user
= other_def
->uses
;
1109 while (user
!= NULL
)
1111 btr_user next
= user
->next
;
1113 user
->next
= def
->uses
;
1117 /* Combining def/use webs can make target registers live
1118 after uses where they previously were not. This means
1119 some REG_DEAD notes may no longer be correct. We could
1120 be more precise about this if we looked at the combined
1121 live range, but here I just delete any REG_DEAD notes
1122 in case they are no longer correct. */
1123 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1124 remove_note (user
->insn
,
1125 find_regno_note (user
->insn
, REG_DEAD
,
1126 REGNO (user
->use
)));
1127 clear_btr_from_live_range (other_def
);
1128 other_def
->uses
= NULL
;
1129 bitmap_copy (def
->live_range
, combined_live_range
);
1130 if (other_def
->btr
== btr
&& other_def
->other_btr_uses_after_use
)
1131 def
->other_btr_uses_after_use
= 1;
1132 COPY_HARD_REG_SET (*btrs_live_in_range
, combined_btrs_live
);
1134 /* Delete the old target register initialization. */
1135 delete_insn (other_def
->insn
);
1138 BITMAP_FREE (combined_live_range
);
1143 /* Move the definition DEF from its current position to basic
1144 block NEW_DEF_BB, and modify it to use branch target register BTR.
1145 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1146 Update all reaching uses of DEF in the RTL to use BTR.
1147 If this new position means that other defs in the
1148 same group can be combined with DEF then combine them. */
1150 move_btr_def (basic_block new_def_bb
, int btr
, btr_def def
, bitmap live_range
,
1151 HARD_REG_SET
*btrs_live_in_range
)
1153 /* We can move the instruction.
1154 Set a target register in block NEW_DEF_BB to the value
1155 needed for this target register definition.
1156 Replace all uses of the old target register definition by
1157 uses of the new definition. Delete the old definition. */
1158 basic_block b
= new_def_bb
;
1159 rtx_insn
*insp
= BB_HEAD (b
);
1160 rtx_insn
*old_insn
= def
->insn
;
1164 machine_mode btr_mode
;
1169 fprintf(dump_file
, "migrating to basic block %d, using reg %d\n",
1170 new_def_bb
->index
, btr
);
1172 clear_btr_from_live_range (def
);
1174 def
->bb
= new_def_bb
;
1176 def
->cost
= basic_block_freq (new_def_bb
);
1177 bitmap_copy (def
->live_range
, live_range
);
1178 combine_btr_defs (def
, btrs_live_in_range
);
1180 def
->other_btr_uses_before_def
1181 = TEST_HARD_REG_BIT (btrs_live
[b
->index
], btr
) ? 1 : 0;
1182 add_btr_to_live_range (def
, 1);
1184 insp
= NEXT_INSN (insp
);
1185 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1186 optimizations can result in insp being both first and last insn of
1188 /* ?? some assertions to check that insp is sensible? */
1190 if (def
->other_btr_uses_before_def
)
1193 for (insp
= BB_END (b
); ! INSN_P (insp
); insp
= PREV_INSN (insp
))
1194 gcc_assert (insp
!= BB_HEAD (b
));
1196 if (JUMP_P (insp
) || can_throw_internal (insp
))
1197 insp
= PREV_INSN (insp
);
1200 set
= single_set (old_insn
);
1201 src
= SET_SRC (set
);
1202 btr_mode
= GET_MODE (SET_DEST (set
));
1203 btr_rtx
= gen_rtx_REG (btr_mode
, btr
);
1205 new_insn
= gen_move_insn (btr_rtx
, src
);
1207 /* Insert target register initialization at head of basic block. */
1208 def
->insn
= emit_insn_after (new_insn
, insp
);
1210 df_set_regs_ever_live (btr
, true);
1213 fprintf (dump_file
, "New pt is insn %d, inserted after insn %d\n",
1214 INSN_UID (def
->insn
), INSN_UID (insp
));
1216 /* Delete the old target register initialization. */
1217 delete_insn (old_insn
);
1219 /* Replace each use of the old target register by a use of the new target
1221 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1223 /* Some extra work here to ensure consistent modes, because
1224 it seems that a target register REG rtx can be given a different
1225 mode depending on the context (surely that should not be
1227 rtx replacement_rtx
;
1228 if (GET_MODE (user
->use
) == GET_MODE (btr_rtx
)
1229 || GET_MODE (user
->use
) == VOIDmode
)
1230 replacement_rtx
= btr_rtx
;
1232 replacement_rtx
= gen_rtx_REG (GET_MODE (user
->use
), btr
);
1233 validate_replace_rtx (user
->use
, replacement_rtx
, user
->insn
);
1234 user
->use
= replacement_rtx
;
1238 /* We anticipate intra-block scheduling to be done. See if INSN could move
1239 up within BB by N_INSNS. */
1241 can_move_up (const_basic_block bb
, const rtx_insn
*insn
, int n_insns
)
1243 while (insn
!= BB_HEAD (bb
) && n_insns
> 0)
1245 insn
= PREV_INSN (insn
);
1246 /* ??? What if we have an anti-dependency that actually prevents the
1247 scheduler from doing the move? We'd like to re-allocate the register,
1248 but not necessarily put the load into another basic block. */
1252 return n_insns
<= 0;
1255 /* Attempt to migrate the target register definition DEF to an
1256 earlier point in the flowgraph.
1258 It is a precondition of this function that DEF is migratable:
1259 i.e. it has a constant source, and all uses are unambiguous.
1261 Only migrations that reduce the cost of DEF will be made.
1262 MIN_COST is the lower bound on the cost of the DEF after migration.
1263 If we migrate DEF so that its cost falls below MIN_COST,
1264 then we do not attempt to migrate further. The idea is that
1265 we migrate definitions in a priority order based on their cost,
1266 when the cost of this definition falls below MIN_COST, then
1267 there is another definition with cost == MIN_COST which now
1268 has a higher priority than this definition.
1270 Return nonzero if there may be benefit from attempting to
1271 migrate this DEF further (i.e. we have reduced the cost below
1272 MIN_COST, but we may be able to reduce it further).
1273 Return zero if no further migration is possible. */
1275 migrate_btr_def (btr_def def
, int min_cost
)
1278 HARD_REG_SET btrs_live_in_range
;
1279 int btr_used_near_def
= 0;
1280 int def_basic_block_freq
;
1281 basic_block attempt
;
1289 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1290 INSN_UID (def
->insn
), def
->cost
, min_cost
);
1292 if (!def
->group
|| def
->has_ambiguous_use
)
1293 /* These defs are not migratable. */
1296 fprintf (dump_file
, "it's not migratable\n");
1301 /* We have combined this def with another in the same group, so
1302 no need to consider it further.
1306 fprintf (dump_file
, "it's already combined with another pt\n");
1310 btr_def_live_range (def
, &btrs_live_in_range
);
1311 live_range
= BITMAP_ALLOC (NULL
);
1312 bitmap_copy (live_range
, def
->live_range
);
1314 #ifdef INSN_SCHEDULING
1315 def_latency
= insn_default_latency (def
->insn
) * issue_rate
;
1317 def_latency
= issue_rate
;
1320 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1322 if (user
->bb
== def
->bb
1323 && user
->luid
> def
->luid
1324 && (def
->luid
+ def_latency
) > user
->luid
1325 && ! can_move_up (def
->bb
, def
->insn
,
1326 (def
->luid
+ def_latency
) - user
->luid
))
1328 btr_used_near_def
= 1;
1333 def_basic_block_freq
= basic_block_freq (def
->bb
);
1335 for (attempt
= get_immediate_dominator (CDI_DOMINATORS
, def
->bb
);
1336 !give_up
&& attempt
&& attempt
!= ENTRY_BLOCK_PTR_FOR_FN (cfun
)
1337 && def
->cost
>= min_cost
;
1338 attempt
= get_immediate_dominator (CDI_DOMINATORS
, attempt
))
1340 /* Try to move the instruction that sets the target register into
1341 basic block ATTEMPT. */
1342 int try_freq
= basic_block_freq (attempt
);
1346 /* If ATTEMPT has abnormal edges, skip it. */
1347 FOR_EACH_EDGE (e
, ei
, attempt
->succs
)
1348 if (e
->flags
& EDGE_COMPLEX
)
1354 fprintf (dump_file
, "trying block %d ...", attempt
->index
);
1356 if (try_freq
< def_basic_block_freq
1357 || (try_freq
== def_basic_block_freq
&& btr_used_near_def
))
1360 augment_live_range (live_range
, &btrs_live_in_range
, def
->bb
, attempt
,
1361 flag_btr_bb_exclusive
);
1364 fprintf (dump_file
, "Now btrs live in range are: ");
1365 dump_hard_reg_set (btrs_live_in_range
);
1366 fprintf (dump_file
, "\n");
1368 btr
= choose_btr (btrs_live_in_range
);
1371 move_btr_def (attempt
, btr
, def
, live_range
, &btrs_live_in_range
);
1372 bitmap_copy (live_range
, def
->live_range
);
1373 btr_used_near_def
= 0;
1375 def_basic_block_freq
= basic_block_freq (def
->bb
);
1379 /* There are no free target registers available to move
1380 this far forward, so give up */
1384 "giving up because there are no free target registers\n");
1393 fprintf (dump_file
, "failed to move\n");
1395 BITMAP_FREE (live_range
);
1399 /* Attempt to move instructions that set target registers earlier
1400 in the flowgraph, away from their corresponding uses. */
1402 migrate_btr_defs (enum reg_class btr_class
, int allow_callee_save
)
1404 btr_heap_t
all_btr_defs (LONG_MIN
);
1407 gcc_obstack_init (&migrate_btrl_obstack
);
1412 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block_for_fn (cfun
); i
++)
1414 basic_block bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
1416 "Basic block %d: count = %" PRId64
1417 " loop-depth = %d idom = %d\n",
1418 i
, (int64_t) bb
->count
, bb_loop_depth (bb
),
1419 get_immediate_dominator (CDI_DOMINATORS
, bb
)->index
);
1423 CLEAR_HARD_REG_SET (all_btrs
);
1424 for (first_btr
= -1, reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
1425 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) btr_class
], reg
)
1426 && (allow_callee_save
|| call_used_regs
[reg
]
1427 || df_regs_ever_live_p (reg
)))
1429 SET_HARD_REG_BIT (all_btrs
, reg
);
1435 btrs_live
= XCNEWVEC (HARD_REG_SET
, last_basic_block_for_fn (cfun
));
1436 btrs_live_at_end
= XCNEWVEC (HARD_REG_SET
, last_basic_block_for_fn (cfun
));
1438 build_btr_def_use_webs (&all_btr_defs
);
1440 while (!all_btr_defs
.empty ())
1442 int min_cost
= -all_btr_defs
.min_key ();
1443 btr_def def
= all_btr_defs
.extract_min ();
1444 if (migrate_btr_def (def
, min_cost
))
1446 all_btr_defs
.insert (-def
->cost
, def
);
1450 "Putting insn %d back on queue with priority %d\n",
1451 INSN_UID (def
->insn
), def
->cost
);
1455 BITMAP_FREE (def
->live_range
);
1459 free (btrs_live_at_end
);
1460 obstack_free (&migrate_btrl_obstack
, NULL
);
1464 branch_target_load_optimize (bool after_prologue_epilogue_gen
)
1466 enum reg_class klass
1467 = (enum reg_class
) targetm
.branch_target_register_class ();
1468 if (klass
!= NO_REGS
)
1470 /* Initialize issue_rate. */
1471 if (targetm
.sched
.issue_rate
)
1472 issue_rate
= targetm
.sched
.issue_rate ();
1476 if (!after_prologue_epilogue_gen
)
1478 /* Build the CFG for migrate_btr_defs. */
1480 /* This may or may not be needed, depending on where we
1482 cleanup_cfg (optimize
? CLEANUP_EXPENSIVE
: 0);
1488 /* Dominator info is also needed for migrate_btr_def. */
1489 calculate_dominance_info (CDI_DOMINATORS
);
1490 migrate_btr_defs (klass
,
1491 (targetm
.branch_target_register_callee_saved
1492 (after_prologue_epilogue_gen
)));
1494 free_dominance_info (CDI_DOMINATORS
);
1500 const pass_data pass_data_branch_target_load_optimize1
=
1502 RTL_PASS
, /* type */
1504 OPTGROUP_NONE
, /* optinfo_flags */
1505 TV_NONE
, /* tv_id */
1506 0, /* properties_required */
1507 0, /* properties_provided */
1508 0, /* properties_destroyed */
1509 0, /* todo_flags_start */
1510 0, /* todo_flags_finish */
1513 class pass_branch_target_load_optimize1
: public rtl_opt_pass
1516 pass_branch_target_load_optimize1 (gcc::context
*ctxt
)
1517 : rtl_opt_pass (pass_data_branch_target_load_optimize1
, ctxt
)
1520 /* opt_pass methods: */
1521 virtual bool gate (function
*) { return flag_branch_target_load_optimize
; }
1522 virtual unsigned int execute (function
*)
1524 branch_target_load_optimize (epilogue_completed
);
1528 }; // class pass_branch_target_load_optimize1
1533 make_pass_branch_target_load_optimize1 (gcc::context
*ctxt
)
1535 return new pass_branch_target_load_optimize1 (ctxt
);
1541 const pass_data pass_data_branch_target_load_optimize2
=
1543 RTL_PASS
, /* type */
1545 OPTGROUP_NONE
, /* optinfo_flags */
1546 TV_NONE
, /* tv_id */
1547 0, /* properties_required */
1548 0, /* properties_provided */
1549 0, /* properties_destroyed */
1550 0, /* todo_flags_start */
1551 0, /* todo_flags_finish */
1554 class pass_branch_target_load_optimize2
: public rtl_opt_pass
1557 pass_branch_target_load_optimize2 (gcc::context
*ctxt
)
1558 : rtl_opt_pass (pass_data_branch_target_load_optimize2
, ctxt
)
1561 /* opt_pass methods: */
1562 virtual bool gate (function
*)
1564 return (optimize
> 0 && flag_branch_target_load_optimize2
);
1567 virtual unsigned int execute (function
*);
1569 }; // class pass_branch_target_load_optimize2
1572 pass_branch_target_load_optimize2::execute (function
*)
1574 static int warned
= 0;
1576 /* Leave this a warning for now so that it is possible to experiment
1577 with running this pass twice. In 3.6, we should either make this
1578 an error, or use separate dump files. */
1579 if (flag_branch_target_load_optimize
1580 && flag_branch_target_load_optimize2
1583 warning (0, "branch target register load optimization is not intended "
1589 branch_target_load_optimize (epilogue_completed
);
1596 make_pass_branch_target_load_optimize2 (gcc::context
*ctxt
)
1598 return new pass_branch_target_load_optimize2 (ctxt
);