1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; Q -- Memory reference without index register and with short displacement.
51 ;; R -- Memory reference with index register and short displacement.
52 ;; S -- Memory reference without index register but with long displacement.
53 ;; T -- Memory reference with index register and long displacement.
54 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
55 ;; Offsettable memory reference of type specified by second letter.
56 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
57 ;; Memory reference of the type specified by second letter that
58 ;; does *not* refer to a literal pool entry.
59 ;; U -- Pointer with short displacement.
60 ;; W -- Pointer with long displacement.
61 ;; Y -- Shift count operand.
63 ;; Special formats used for outputting 390 instructions.
65 ;; %C: print opcode suffix for branch condition.
66 ;; %D: print opcode suffix for inverse branch condition.
67 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
68 ;; %O: print only the displacement of a memory reference.
69 ;; %R: print only the base register of a memory reference.
70 ;; %S: print S-type memory reference (base+displacement).
71 ;; %N: print the second word of a DImode operand.
72 ;; %M: print the second word of a TImode operand.
74 ;; %b: print integer X as if it's an unsigned byte.
75 ;; %x: print integer X as if it's an unsigned word.
76 ;; %h: print integer X as if it's a signed word.
77 ;; %i: print the first nonzero HImode part of X
78 ;; %j: print the first HImode part unequal to 0xffff of X
81 ;; We have a special constraint for pattern matching.
83 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
96 ; GOT/PLT and lt-relative accesses
97 (UNSPEC_LTREL_OFFSET 100)
98 (UNSPEC_LTREL_BASE 101)
106 (UNSPEC_RELOAD_BASE 210)
107 (UNSPEC_MAIN_BASE 211)
112 ; TLS relocation specifiers
117 (UNSPEC_GOTNTPOFF 504)
118 (UNSPEC_INDNTPOFF 505)
121 (UNSPEC_TLSLDM_NTPOFF 511)
122 (UNSPEC_TLS_LOAD 512)
129 ;; UNSPEC_VOLATILE usage
137 (UNSPECV_TPF_PROLOGUE 20)
138 (UNSPECV_TPF_EPILOGUE 21)
142 (UNSPECV_POOL_SECTION 201)
143 (UNSPECV_POOL_ALIGN 202)
144 (UNSPECV_POOL_ENTRY 203)
145 (UNSPECV_MAIN_POOL 300)
157 ; Sibling call register.
159 ; Literal pool base register.
161 ; Return address register.
163 ; Condition code register.
165 ; Thread local storage pointer register.
170 ;; Instruction operand type as used in the Principles of Operation.
171 ;; Used to determine defaults for length and other attribute values.
173 (define_attr "op_type"
174 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
177 ;; Instruction type attribute used for scheduling.
179 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
181 imulhi,imulsi,imuldi,
182 branch,jsr,fsimpdf,fsimpsf,
183 floaddf,floadsf,fstoredf,fstoresf,
184 fmuldf,fmulsf,fdivdf,fdivsf,
185 ftoi,itof,fsqrtdf,fsqrtsf,
187 (cond [(eq_attr "op_type" "NN") (const_string "other")
188 (eq_attr "op_type" "SS") (const_string "cs")]
189 (const_string "integer")))
191 ;; Another attribute used for scheduling purposes:
192 ;; agen: Instruction uses the address generation unit
193 ;; reg: Instruction does not use the agen unit
195 (define_attr "atype" "agen,reg"
196 (cond [(eq_attr "op_type" "E") (const_string "reg")
197 (eq_attr "op_type" "RR") (const_string "reg")
198 (eq_attr "op_type" "RX") (const_string "agen")
199 (eq_attr "op_type" "RI") (const_string "reg")
200 (eq_attr "op_type" "RRE") (const_string "reg")
201 (eq_attr "op_type" "RS") (const_string "agen")
202 (eq_attr "op_type" "RSI") (const_string "agen")
203 (eq_attr "op_type" "S") (const_string "agen")
204 (eq_attr "op_type" "SI") (const_string "agen")
205 (eq_attr "op_type" "SS") (const_string "agen")
206 (eq_attr "op_type" "SSE") (const_string "agen")
207 (eq_attr "op_type" "RXE") (const_string "agen")
208 (eq_attr "op_type" "RSE") (const_string "agen")
209 (eq_attr "op_type" "RIL") (const_string "agen")
210 (eq_attr "op_type" "RXY") (const_string "agen")
211 (eq_attr "op_type" "RSY") (const_string "agen")
212 (eq_attr "op_type" "SIY") (const_string "agen")]
213 (const_string "agen")))
217 (define_attr "length" ""
218 (cond [(eq_attr "op_type" "E") (const_int 2)
219 (eq_attr "op_type" "RR") (const_int 2)
220 (eq_attr "op_type" "RX") (const_int 4)
221 (eq_attr "op_type" "RI") (const_int 4)
222 (eq_attr "op_type" "RRE") (const_int 4)
223 (eq_attr "op_type" "RS") (const_int 4)
224 (eq_attr "op_type" "RSI") (const_int 4)
225 (eq_attr "op_type" "S") (const_int 4)
226 (eq_attr "op_type" "SI") (const_int 4)
227 (eq_attr "op_type" "SS") (const_int 6)
228 (eq_attr "op_type" "SSE") (const_int 6)
229 (eq_attr "op_type" "RXE") (const_int 6)
230 (eq_attr "op_type" "RSE") (const_int 6)
231 (eq_attr "op_type" "RIL") (const_int 6)
232 (eq_attr "op_type" "RXY") (const_int 6)
233 (eq_attr "op_type" "RSY") (const_int 6)
234 (eq_attr "op_type" "SIY") (const_int 6)]
238 ;; Processor type. This attribute must exactly match the processor_type
239 ;; enumeration in s390.h. The current machine description does not
240 ;; distinguish between g5 and g6, but there are differences between the two
241 ;; CPUs could in theory be modeled.
243 (define_attr "cpu" "g5,g6,z900,z990"
244 (const (symbol_ref "s390_tune")))
246 ;; Pipeline description for z900. For lack of anything better,
247 ;; this description is also used for the g5 and g6.
250 ;; Pipeline description for z990.
254 (include "predicates.md")
259 ;; This mode macro allows DF and SF patterns to be generated from the
261 (define_mode_macro FPR [DF SF])
263 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
264 ;; from the same template.
265 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
266 (define_mode_macro DSI [DI SI])
268 ;; This mode macro allows :P to be used for patterns that operate on
269 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
270 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
272 ;; This mode macro allows the QI and HI patterns to be defined from
273 ;; the same template.
274 (define_mode_macro HQI [HI QI])
276 ;; This mode macro allows the integer patterns to be defined from the
278 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
280 ;; This macro allows to unify all 'bCOND' expander patterns.
281 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
282 ordered uneq unlt ungt unle unge ltgt])
284 ;; This macro allows to unify all 'sCOND' patterns.
285 (define_code_macro SCOND [ltu gtu leu geu])
287 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
288 ;; the same template.
289 (define_code_macro SHIFT [ashift lshiftrt])
292 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
293 ;; and "ltebr" in SFmode.
294 (define_mode_attr de [(DF "d") (SF "e")])
296 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
297 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
298 (define_mode_attr dee [(DF "d") (SF "ee")])
300 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
301 ;; 'ashift' and "srdl" in 'lshiftrt'.
302 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
304 ;; In SHIFT templates, this attribute holds the correct standard name for the
305 ;; pattern itself and the corresponding function calls.
306 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
308 ;; This attribute handles differences in the instruction 'type' and will result
309 ;; in "RRE" for DImode and "RR" for SImode.
310 (define_mode_attr E [(DI "E") (SI "")])
312 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
313 ;; and "lcr" in SImode.
314 (define_mode_attr g [(DI "g") (SI "")])
316 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
317 ;; and "cfdbr" in SImode.
318 (define_mode_attr gf [(DI "g") (SI "f")])
320 ;; ICM mask required to load MODE value into the highest subreg
321 ;; of a SImode register.
322 (define_mode_attr icm_hi [(HI "12") (QI "8")])
324 ;; ICM mask required to load MODE value into the lowest subreg
325 ;; of a SImode register.
326 (define_mode_attr icm_lo [(HI "3") (QI "1")])
328 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
329 ;; HImode and "llgc" in QImode.
330 (define_mode_attr hc [(HI "h") (QI "c")])
332 ;; Maximum unsigned integer that fits in MODE.
333 (define_mode_attr max_uint [(HI "65535") (QI "255")])
337 ;;- Compare instructions.
340 (define_expand "cmp<mode>"
341 [(set (reg:CC CC_REGNUM)
342 (compare:CC (match_operand:GPR 0 "register_operand" "")
343 (match_operand:GPR 1 "general_operand" "")))]
346 s390_compare_op0 = operands[0];
347 s390_compare_op1 = operands[1];
351 (define_expand "cmp<mode>"
352 [(set (reg:CC CC_REGNUM)
353 (compare:CC (match_operand:FPR 0 "register_operand" "")
354 (match_operand:FPR 1 "general_operand" "")))]
357 s390_compare_op0 = operands[0];
358 s390_compare_op1 = operands[1];
363 ; Test-under-Mask instructions
365 (define_insn "*tmqi_mem"
366 [(set (reg CC_REGNUM)
367 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
368 (match_operand:QI 1 "immediate_operand" "n,n"))
369 (match_operand:QI 2 "immediate_operand" "n,n")))]
370 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
374 [(set_attr "op_type" "SI,SIY")])
376 (define_insn "*tmdi_reg"
377 [(set (reg CC_REGNUM)
378 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
379 (match_operand:DI 1 "immediate_operand"
380 "N0HD0,N1HD0,N2HD0,N3HD0"))
381 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
383 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
384 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
390 [(set_attr "op_type" "RI")])
392 (define_insn "*tmsi_reg"
393 [(set (reg CC_REGNUM)
394 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
395 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
396 (match_operand:SI 2 "immediate_operand" "n,n")))]
397 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
398 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
402 [(set_attr "op_type" "RI")])
404 (define_insn "*tm<mode>_full"
405 [(set (reg CC_REGNUM)
406 (compare (match_operand:HQI 0 "register_operand" "d")
407 (match_operand:HQI 1 "immediate_operand" "n")))]
408 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
410 [(set_attr "op_type" "RI")])
413 ; Load-and-Test instructions
415 (define_insn "*tstdi_sign"
416 [(set (reg CC_REGNUM)
417 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
418 (const_int 32)) (const_int 32))
419 (match_operand:DI 1 "const0_operand" "")))
420 (set (match_operand:DI 2 "register_operand" "=d")
421 (sign_extend:DI (match_dup 0)))]
422 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
424 [(set_attr "op_type" "RRE")])
426 (define_insn "*tstdi"
427 [(set (reg CC_REGNUM)
428 (compare (match_operand:DI 0 "register_operand" "d")
429 (match_operand:DI 1 "const0_operand" "")))
430 (set (match_operand:DI 2 "register_operand" "=d")
432 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
434 [(set_attr "op_type" "RRE")])
436 (define_insn "*tstdi_cconly"
437 [(set (reg CC_REGNUM)
438 (compare (match_operand:DI 0 "register_operand" "d")
439 (match_operand:DI 1 "const0_operand" "")))]
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
442 [(set_attr "op_type" "RRE")])
444 (define_insn "*tstdi_cconly_31"
445 [(set (reg CC_REGNUM)
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))]
448 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
450 [(set_attr "op_type" "RS")
451 (set_attr "atype" "reg")])
454 (define_insn "*tstsi"
455 [(set (reg CC_REGNUM)
456 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
457 (match_operand:SI 1 "const0_operand" "")))
458 (set (match_operand:SI 2 "register_operand" "=d,d,d")
460 "s390_match_ccmode(insn, CCSmode)"
465 [(set_attr "op_type" "RR,RS,RSY")])
467 (define_insn "*tstsi_cconly"
468 [(set (reg CC_REGNUM)
469 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
470 (match_operand:SI 1 "const0_operand" "")))
471 (clobber (match_scratch:SI 2 "=X,d,d"))]
472 "s390_match_ccmode(insn, CCSmode)"
477 [(set_attr "op_type" "RR,RS,RSY")])
479 (define_insn "*tstsi_cconly2"
480 [(set (reg CC_REGNUM)
481 (compare (match_operand:SI 0 "register_operand" "d")
482 (match_operand:SI 1 "const0_operand" "")))]
483 "s390_match_ccmode(insn, CCSmode)"
485 [(set_attr "op_type" "RR")])
487 (define_insn "*tst<mode>CCT"
488 [(set (reg CC_REGNUM)
489 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
490 (match_operand:HQI 1 "const0_operand" "")))
491 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
493 "s390_match_ccmode(insn, CCTmode)"
496 icmy\t%2,<icm_lo>,%S0
498 [(set_attr "op_type" "RS,RSY,RI")])
500 (define_insn "*tsthiCCT_cconly"
501 [(set (reg CC_REGNUM)
502 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
503 (match_operand:HI 1 "const0_operand" "")))
504 (clobber (match_scratch:HI 2 "=d,d,X"))]
505 "s390_match_ccmode(insn, CCTmode)"
510 [(set_attr "op_type" "RS,RSY,RI")])
512 (define_insn "*tstqiCCT_cconly"
513 [(set (reg CC_REGNUM)
514 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
515 (match_operand:QI 1 "const0_operand" "")))]
516 "s390_match_ccmode(insn, CCTmode)"
521 [(set_attr "op_type" "SI,SIY,RI")])
523 (define_insn "*tst<mode>"
524 [(set (reg CC_REGNUM)
525 (compare (match_operand:HQI 0 "s_operand" "Q,S")
526 (match_operand:HQI 1 "const0_operand" "")))
527 (set (match_operand:HQI 2 "register_operand" "=d,d")
529 "s390_match_ccmode(insn, CCSmode)"
532 icmy\t%2,<icm_lo>,%S0"
533 [(set_attr "op_type" "RS,RSY")])
535 (define_insn "*tst<mode>_cconly"
536 [(set (reg CC_REGNUM)
537 (compare (match_operand:HQI 0 "s_operand" "Q,S")
538 (match_operand:HQI 1 "const0_operand" "")))
539 (clobber (match_scratch:HQI 2 "=d,d"))]
540 "s390_match_ccmode(insn, CCSmode)"
543 icmy\t%2,<icm_lo>,%S0"
544 [(set_attr "op_type" "RS,RSY")])
547 ; Compare (equality) instructions
549 (define_insn "*cmpdi_cct"
550 [(set (reg CC_REGNUM)
551 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
552 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
553 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
559 [(set_attr "op_type" "RRE,RI,RXY,SS")])
561 (define_insn "*cmpsi_cct"
562 [(set (reg CC_REGNUM)
563 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
564 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
565 "s390_match_ccmode (insn, CCTmode)"
572 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
575 ; Compare (signed) instructions
577 (define_insn "*cmpdi_ccs_sign"
578 [(set (reg CC_REGNUM)
579 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
580 (match_operand:DI 0 "register_operand" "d,d")))]
581 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
585 [(set_attr "op_type" "RRE,RXY")])
587 (define_insn "*cmpdi_ccs"
588 [(set (reg CC_REGNUM)
589 (compare (match_operand:DI 0 "register_operand" "d,d,d")
590 (match_operand:DI 1 "general_operand" "d,K,m")))]
591 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
596 [(set_attr "op_type" "RRE,RI,RXY")])
598 (define_insn "*cmpsi_ccs_sign"
599 [(set (reg CC_REGNUM)
600 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
601 (match_operand:SI 0 "register_operand" "d,d")))]
602 "s390_match_ccmode(insn, CCSRmode)"
606 [(set_attr "op_type" "RX,RXY")])
608 (define_insn "*cmpsi_ccs"
609 [(set (reg CC_REGNUM)
610 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
611 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
612 "s390_match_ccmode(insn, CCSmode)"
618 [(set_attr "op_type" "RR,RI,RX,RXY")])
621 ; Compare (unsigned) instructions
623 (define_insn "*cmpdi_ccu_zero"
624 [(set (reg CC_REGNUM)
625 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
626 (match_operand:DI 0 "register_operand" "d,d")))]
627 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
631 [(set_attr "op_type" "RRE,RXY")])
633 (define_insn "*cmpdi_ccu"
634 [(set (reg CC_REGNUM)
635 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
636 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
637 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
643 [(set_attr "op_type" "RRE,RXY,SS,SS")])
645 (define_insn "*cmpsi_ccu"
646 [(set (reg CC_REGNUM)
647 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
648 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
649 "s390_match_ccmode (insn, CCUmode)"
656 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
658 (define_insn "*cmphi_ccu"
659 [(set (reg CC_REGNUM)
660 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
661 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
662 "s390_match_ccmode (insn, CCUmode)
663 && !register_operand (operands[1], HImode)"
669 [(set_attr "op_type" "RS,RSY,SS,SS")])
671 (define_insn "*cmpqi_ccu"
672 [(set (reg CC_REGNUM)
673 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
674 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
675 "s390_match_ccmode (insn, CCUmode)
676 && !register_operand (operands[1], QImode)"
684 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
687 ; Block compare (CLC) instruction patterns.
690 [(set (reg CC_REGNUM)
691 (compare (match_operand:BLK 0 "memory_operand" "Q")
692 (match_operand:BLK 1 "memory_operand" "Q")))
693 (use (match_operand 2 "const_int_operand" "n"))]
694 "s390_match_ccmode (insn, CCUmode)
695 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
696 "clc\t%O0(%2,%R0),%S1"
697 [(set_attr "op_type" "SS")])
700 [(set (reg CC_REGNUM)
701 (compare (match_operand 0 "memory_operand" "")
702 (match_operand 1 "memory_operand" "")))]
704 && s390_match_ccmode (insn, CCUmode)
705 && GET_MODE (operands[0]) == GET_MODE (operands[1])
706 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
708 [(set (match_dup 0) (match_dup 1))
709 (use (match_dup 2))])]
711 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
712 operands[0] = adjust_address (operands[0], BLKmode, 0);
713 operands[1] = adjust_address (operands[1], BLKmode, 0);
715 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
716 operands[0], operands[1]);
717 operands[0] = SET_DEST (PATTERN (curr_insn));
721 ; (DF|SF) instructions
723 (define_insn "*cmp<mode>_ccs_0"
724 [(set (reg CC_REGNUM)
725 (compare (match_operand:FPR 0 "register_operand" "f")
726 (match_operand:FPR 1 "const0_operand" "")))]
727 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
729 [(set_attr "op_type" "RRE")
730 (set_attr "type" "fsimp<mode>")])
732 (define_insn "*cmp<mode>_ccs_0_ibm"
733 [(set (reg CC_REGNUM)
734 (compare (match_operand:FPR 0 "register_operand" "f")
735 (match_operand:FPR 1 "const0_operand" "")))]
736 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
738 [(set_attr "op_type" "RR")
739 (set_attr "type" "fsimp<mode>")])
741 (define_insn "*cmp<mode>_ccs"
742 [(set (reg CC_REGNUM)
743 (compare (match_operand:FPR 0 "register_operand" "f,f")
744 (match_operand:FPR 1 "general_operand" "f,R")))]
745 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
749 [(set_attr "op_type" "RRE,RXE")
750 (set_attr "type" "fsimp<mode>")])
752 (define_insn "*cmp<mode>_ccs_ibm"
753 [(set (reg CC_REGNUM)
754 (compare (match_operand:FPR 0 "register_operand" "f,f")
755 (match_operand:FPR 1 "general_operand" "f,R")))]
756 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
760 [(set_attr "op_type" "RR,RX")
761 (set_attr "type" "fsimp<mode>")])
765 ;;- Move instructions.
769 ; movti instruction pattern(s).
773 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
774 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
782 [(set_attr "op_type" "RSY,RSY,*,*,SS")
783 (set_attr "type" "lm,stm,*,*,*")])
786 [(set (match_operand:TI 0 "nonimmediate_operand" "")
787 (match_operand:TI 1 "general_operand" ""))]
788 "TARGET_64BIT && reload_completed
789 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
790 [(set (match_dup 2) (match_dup 4))
791 (set (match_dup 3) (match_dup 5))]
793 operands[2] = operand_subword (operands[0], 0, 0, TImode);
794 operands[3] = operand_subword (operands[0], 1, 0, TImode);
795 operands[4] = operand_subword (operands[1], 0, 0, TImode);
796 operands[5] = operand_subword (operands[1], 1, 0, TImode);
800 [(set (match_operand:TI 0 "nonimmediate_operand" "")
801 (match_operand:TI 1 "general_operand" ""))]
802 "TARGET_64BIT && reload_completed
803 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
804 [(set (match_dup 2) (match_dup 4))
805 (set (match_dup 3) (match_dup 5))]
807 operands[2] = operand_subword (operands[0], 1, 0, TImode);
808 operands[3] = operand_subword (operands[0], 0, 0, TImode);
809 operands[4] = operand_subword (operands[1], 1, 0, TImode);
810 operands[5] = operand_subword (operands[1], 0, 0, TImode);
814 [(set (match_operand:TI 0 "register_operand" "")
815 (match_operand:TI 1 "memory_operand" ""))]
816 "TARGET_64BIT && reload_completed
817 && !s_operand (operands[1], VOIDmode)"
818 [(set (match_dup 0) (match_dup 1))]
820 rtx addr = operand_subword (operands[0], 1, 0, TImode);
821 s390_load_address (addr, XEXP (operands[1], 0));
822 operands[1] = replace_equiv_address (operands[1], addr);
825 (define_expand "reload_outti"
826 [(parallel [(match_operand:TI 0 "" "")
827 (match_operand:TI 1 "register_operand" "d")
828 (match_operand:DI 2 "register_operand" "=&a")])]
831 gcc_assert (MEM_P (operands[0]));
832 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
833 operands[0] = replace_equiv_address (operands[0], operands[2]);
834 emit_move_insn (operands[0], operands[1]);
839 ; movdi instruction pattern(s).
842 (define_expand "movdi"
843 [(set (match_operand:DI 0 "general_operand" "")
844 (match_operand:DI 1 "general_operand" ""))]
847 /* Handle symbolic constants. */
848 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
849 emit_symbolic_move (operands);
852 (define_insn "*movdi_larl"
853 [(set (match_operand:DI 0 "register_operand" "=d")
854 (match_operand:DI 1 "larl_operand" "X"))]
856 && !FP_REG_P (operands[0])"
858 [(set_attr "op_type" "RIL")
859 (set_attr "type" "larl")])
861 (define_insn "*movdi_64"
862 [(set (match_operand:DI 0 "nonimmediate_operand"
863 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
864 (match_operand:DI 1 "general_operand"
865 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
887 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
888 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
889 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
890 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
893 [(set (match_operand:DI 0 "register_operand" "")
894 (match_operand:DI 1 "register_operand" ""))]
895 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
896 [(set (match_dup 2) (match_dup 3))
897 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
898 (set (strict_low_part (match_dup 2)) (match_dup 4))]
899 "operands[2] = gen_lowpart (SImode, operands[0]);
900 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
903 [(set (match_operand:DI 0 "register_operand" "")
904 (match_operand:DI 1 "register_operand" ""))]
905 "TARGET_64BIT && ACCESS_REG_P (operands[0])
906 && dead_or_set_p (insn, operands[1])"
907 [(set (match_dup 3) (match_dup 2))
908 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
909 (set (match_dup 4) (match_dup 2))]
910 "operands[2] = gen_lowpart (SImode, operands[1]);
911 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
914 [(set (match_operand:DI 0 "register_operand" "")
915 (match_operand:DI 1 "register_operand" ""))]
916 "TARGET_64BIT && ACCESS_REG_P (operands[0])
917 && !dead_or_set_p (insn, operands[1])"
918 [(set (match_dup 3) (match_dup 2))
919 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
920 (set (match_dup 4) (match_dup 2))
921 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
922 "operands[2] = gen_lowpart (SImode, operands[1]);
923 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
925 (define_insn "*movdi_31"
926 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
927 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
940 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
941 (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
944 [(set (match_operand:DI 0 "nonimmediate_operand" "")
945 (match_operand:DI 1 "general_operand" ""))]
946 "!TARGET_64BIT && reload_completed
947 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
948 [(set (match_dup 2) (match_dup 4))
949 (set (match_dup 3) (match_dup 5))]
951 operands[2] = operand_subword (operands[0], 0, 0, DImode);
952 operands[3] = operand_subword (operands[0], 1, 0, DImode);
953 operands[4] = operand_subword (operands[1], 0, 0, DImode);
954 operands[5] = operand_subword (operands[1], 1, 0, DImode);
958 [(set (match_operand:DI 0 "nonimmediate_operand" "")
959 (match_operand:DI 1 "general_operand" ""))]
960 "!TARGET_64BIT && reload_completed
961 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
962 [(set (match_dup 2) (match_dup 4))
963 (set (match_dup 3) (match_dup 5))]
965 operands[2] = operand_subword (operands[0], 1, 0, DImode);
966 operands[3] = operand_subword (operands[0], 0, 0, DImode);
967 operands[4] = operand_subword (operands[1], 1, 0, DImode);
968 operands[5] = operand_subword (operands[1], 0, 0, DImode);
972 [(set (match_operand:DI 0 "register_operand" "")
973 (match_operand:DI 1 "memory_operand" ""))]
974 "!TARGET_64BIT && reload_completed
975 && !FP_REG_P (operands[0])
976 && !s_operand (operands[1], VOIDmode)"
977 [(set (match_dup 0) (match_dup 1))]
979 rtx addr = operand_subword (operands[0], 1, 0, DImode);
980 s390_load_address (addr, XEXP (operands[1], 0));
981 operands[1] = replace_equiv_address (operands[1], addr);
984 (define_expand "reload_outdi"
985 [(parallel [(match_operand:DI 0 "" "")
986 (match_operand:DI 1 "register_operand" "d")
987 (match_operand:SI 2 "register_operand" "=&a")])]
990 gcc_assert (MEM_P (operands[0]));
991 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
992 operands[0] = replace_equiv_address (operands[0], operands[2]);
993 emit_move_insn (operands[0], operands[1]);
998 [(set (match_operand:DI 0 "register_operand" "")
999 (mem:DI (match_operand 1 "address_operand" "")))]
1001 && !FP_REG_P (operands[0])
1002 && GET_CODE (operands[1]) == SYMBOL_REF
1003 && CONSTANT_POOL_ADDRESS_P (operands[1])
1004 && get_pool_mode (operands[1]) == DImode
1005 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1006 [(set (match_dup 0) (match_dup 2))]
1007 "operands[2] = get_pool_constant (operands[1]);")
1009 (define_insn "*la_64"
1010 [(set (match_operand:DI 0 "register_operand" "=d,d")
1011 (match_operand:QI 1 "address_operand" "U,W"))]
1016 [(set_attr "op_type" "RX,RXY")
1017 (set_attr "type" "la")])
1021 [(set (match_operand:DI 0 "register_operand" "")
1022 (match_operand:QI 1 "address_operand" ""))
1023 (clobber (reg:CC CC_REGNUM))])]
1025 && preferred_la_operand_p (operands[1], const0_rtx)"
1026 [(set (match_dup 0) (match_dup 1))]
1030 [(set (match_operand:DI 0 "register_operand" "")
1031 (match_operand:DI 1 "register_operand" ""))
1034 (plus:DI (match_dup 0)
1035 (match_operand:DI 2 "nonmemory_operand" "")))
1036 (clobber (reg:CC CC_REGNUM))])]
1038 && !reg_overlap_mentioned_p (operands[0], operands[2])
1039 && preferred_la_operand_p (operands[1], operands[2])"
1040 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1043 (define_expand "reload_indi"
1044 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1045 (match_operand:DI 1 "s390_plus_operand" "")
1046 (match_operand:DI 2 "register_operand" "=&a")])]
1049 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1054 ; movsi instruction pattern(s).
1057 (define_expand "movsi"
1058 [(set (match_operand:SI 0 "general_operand" "")
1059 (match_operand:SI 1 "general_operand" ""))]
1062 /* Handle symbolic constants. */
1063 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1064 emit_symbolic_move (operands);
1067 (define_insn "*movsi_larl"
1068 [(set (match_operand:SI 0 "register_operand" "=d")
1069 (match_operand:SI 1 "larl_operand" "X"))]
1070 "!TARGET_64BIT && TARGET_CPU_ZARCH
1071 && !FP_REG_P (operands[0])"
1073 [(set_attr "op_type" "RIL")
1074 (set_attr "type" "larl")])
1076 (define_insn "*movsi_zarch"
1077 [(set (match_operand:SI 0 "nonimmediate_operand"
1078 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1079 (match_operand:SI 1 "general_operand"
1080 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1102 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1103 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1104 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1105 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1107 (define_insn "*movsi_esa"
1108 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1109 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1124 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1125 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1128 [(set (match_operand:SI 0 "register_operand" "")
1129 (mem:SI (match_operand 1 "address_operand" "")))]
1130 "!FP_REG_P (operands[0])
1131 && GET_CODE (operands[1]) == SYMBOL_REF
1132 && CONSTANT_POOL_ADDRESS_P (operands[1])
1133 && get_pool_mode (operands[1]) == SImode
1134 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1135 [(set (match_dup 0) (match_dup 2))]
1136 "operands[2] = get_pool_constant (operands[1]);")
1138 (define_insn "*la_31"
1139 [(set (match_operand:SI 0 "register_operand" "=d,d")
1140 (match_operand:QI 1 "address_operand" "U,W"))]
1141 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1145 [(set_attr "op_type" "RX,RXY")
1146 (set_attr "type" "la")])
1150 [(set (match_operand:SI 0 "register_operand" "")
1151 (match_operand:QI 1 "address_operand" ""))
1152 (clobber (reg:CC CC_REGNUM))])]
1154 && preferred_la_operand_p (operands[1], const0_rtx)"
1155 [(set (match_dup 0) (match_dup 1))]
1159 [(set (match_operand:SI 0 "register_operand" "")
1160 (match_operand:SI 1 "register_operand" ""))
1163 (plus:SI (match_dup 0)
1164 (match_operand:SI 2 "nonmemory_operand" "")))
1165 (clobber (reg:CC CC_REGNUM))])]
1167 && !reg_overlap_mentioned_p (operands[0], operands[2])
1168 && preferred_la_operand_p (operands[1], operands[2])"
1169 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1172 (define_insn "*la_31_and"
1173 [(set (match_operand:SI 0 "register_operand" "=d,d")
1174 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1175 (const_int 2147483647)))]
1180 [(set_attr "op_type" "RX,RXY")
1181 (set_attr "type" "la")])
1183 (define_insn_and_split "*la_31_and_cc"
1184 [(set (match_operand:SI 0 "register_operand" "=d")
1185 (and:SI (match_operand:QI 1 "address_operand" "p")
1186 (const_int 2147483647)))
1187 (clobber (reg:CC CC_REGNUM))]
1190 "&& reload_completed"
1192 (and:SI (match_dup 1) (const_int 2147483647)))]
1194 [(set_attr "op_type" "RX")
1195 (set_attr "type" "la")])
1197 (define_insn "force_la_31"
1198 [(set (match_operand:SI 0 "register_operand" "=d,d")
1199 (match_operand:QI 1 "address_operand" "U,W"))
1200 (use (const_int 0))]
1205 [(set_attr "op_type" "RX")
1206 (set_attr "type" "la")])
1208 (define_expand "reload_insi"
1209 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1210 (match_operand:SI 1 "s390_plus_operand" "")
1211 (match_operand:SI 2 "register_operand" "=&a")])]
1214 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1219 ; movhi instruction pattern(s).
1222 (define_expand "movhi"
1223 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1224 (match_operand:HI 1 "general_operand" ""))]
1227 /* Make it explicit that loading a register from memory
1228 always sign-extends (at least) to SImode. */
1229 if (optimize && !no_new_pseudos
1230 && register_operand (operands[0], VOIDmode)
1231 && GET_CODE (operands[1]) == MEM)
1233 rtx tmp = gen_reg_rtx (SImode);
1234 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1235 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1236 operands[1] = gen_lowpart (HImode, tmp);
1240 (define_insn "*movhi"
1241 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1242 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1252 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1253 (set_attr "type" "lr,*,*,*,store,store,*")])
1256 [(set (match_operand:HI 0 "register_operand" "")
1257 (mem:HI (match_operand 1 "address_operand" "")))]
1258 "GET_CODE (operands[1]) == SYMBOL_REF
1259 && CONSTANT_POOL_ADDRESS_P (operands[1])
1260 && get_pool_mode (operands[1]) == HImode
1261 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1262 [(set (match_dup 0) (match_dup 2))]
1263 "operands[2] = get_pool_constant (operands[1]);")
1266 ; movqi instruction pattern(s).
1269 (define_expand "movqi"
1270 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1271 (match_operand:QI 1 "general_operand" ""))]
1274 /* On z/Architecture, zero-extending from memory to register
1275 is just as fast as a QImode load. */
1276 if (TARGET_ZARCH && optimize && !no_new_pseudos
1277 && register_operand (operands[0], VOIDmode)
1278 && GET_CODE (operands[1]) == MEM)
1280 rtx tmp = gen_reg_rtx (word_mode);
1281 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1282 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1283 operands[1] = gen_lowpart (QImode, tmp);
1287 (define_insn "*movqi"
1288 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1289 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1301 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1302 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1305 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1306 (mem:QI (match_operand 1 "address_operand" "")))]
1307 "GET_CODE (operands[1]) == SYMBOL_REF
1308 && CONSTANT_POOL_ADDRESS_P (operands[1])
1309 && get_pool_mode (operands[1]) == QImode
1310 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1311 [(set (match_dup 0) (match_dup 2))]
1312 "operands[2] = get_pool_constant (operands[1]);")
1315 ; movstrictqi instruction pattern(s).
1318 (define_insn "*movstrictqi"
1319 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1320 (match_operand:QI 1 "memory_operand" "R,T"))]
1325 [(set_attr "op_type" "RX,RXY")])
1328 ; movstricthi instruction pattern(s).
1331 (define_insn "*movstricthi"
1332 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1333 (match_operand:HI 1 "memory_operand" "Q,S"))
1334 (clobber (reg:CC CC_REGNUM))]
1339 [(set_attr "op_type" "RS,RSY")])
1342 ; movstrictsi instruction pattern(s).
1345 (define_insn "movstrictsi"
1346 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1347 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1354 [(set_attr "op_type" "RR,RX,RXY,RRE")
1355 (set_attr "type" "lr,load,load,*")])
1358 ; movdf instruction pattern(s).
1361 (define_expand "movdf"
1362 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1363 (match_operand:DF 1 "general_operand" ""))]
1367 (define_insn "*movdf_64"
1368 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1369 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1382 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1383 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1385 (define_insn "*movdf_31"
1386 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,Q,d,o,Q")
1387 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,d,dKm,d,Q"))]
1401 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1402 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
1405 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1406 (match_operand:DF 1 "general_operand" ""))]
1407 "!TARGET_64BIT && reload_completed
1408 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1409 [(set (match_dup 2) (match_dup 4))
1410 (set (match_dup 3) (match_dup 5))]
1412 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1413 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1414 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1415 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1419 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1420 (match_operand:DF 1 "general_operand" ""))]
1421 "!TARGET_64BIT && reload_completed
1422 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1423 [(set (match_dup 2) (match_dup 4))
1424 (set (match_dup 3) (match_dup 5))]
1426 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1427 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1428 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1429 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1433 [(set (match_operand:DF 0 "register_operand" "")
1434 (match_operand:DF 1 "memory_operand" ""))]
1435 "!TARGET_64BIT && reload_completed
1436 && !FP_REG_P (operands[0])
1437 && !s_operand (operands[1], VOIDmode)"
1438 [(set (match_dup 0) (match_dup 1))]
1440 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1441 s390_load_address (addr, XEXP (operands[1], 0));
1442 operands[1] = replace_equiv_address (operands[1], addr);
1445 (define_expand "reload_outdf"
1446 [(parallel [(match_operand:DF 0 "" "")
1447 (match_operand:DF 1 "register_operand" "d")
1448 (match_operand:SI 2 "register_operand" "=&a")])]
1451 gcc_assert (MEM_P (operands[0]));
1452 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1453 operands[0] = replace_equiv_address (operands[0], operands[2]);
1454 emit_move_insn (operands[0], operands[1]);
1459 ; movsf instruction pattern(s).
1462 (define_insn "movsf"
1463 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1464 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1479 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1480 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1481 lr,load,load,store,store,*")])
1484 ; movcc instruction pattern
1487 (define_insn "movcc"
1488 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1489 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1499 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1500 (set_attr "type" "lr,*,*,store,store,load,load")])
1503 ; Block move (MVC) patterns.
1507 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1508 (match_operand:BLK 1 "memory_operand" "Q"))
1509 (use (match_operand 2 "const_int_operand" "n"))]
1510 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1511 "mvc\t%O0(%2,%R0),%S1"
1512 [(set_attr "op_type" "SS")])
1515 [(set (match_operand 0 "memory_operand" "")
1516 (match_operand 1 "memory_operand" ""))]
1518 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1519 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1521 [(set (match_dup 0) (match_dup 1))
1522 (use (match_dup 2))])]
1524 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1525 operands[0] = adjust_address (operands[0], BLKmode, 0);
1526 operands[1] = adjust_address (operands[1], BLKmode, 0);
1531 [(set (match_operand:BLK 0 "memory_operand" "")
1532 (match_operand:BLK 1 "memory_operand" ""))
1533 (use (match_operand 2 "const_int_operand" ""))])
1535 [(set (match_operand:BLK 3 "memory_operand" "")
1536 (match_operand:BLK 4 "memory_operand" ""))
1537 (use (match_operand 5 "const_int_operand" ""))])]
1538 "s390_offset_p (operands[0], operands[3], operands[2])
1539 && s390_offset_p (operands[1], operands[4], operands[2])
1540 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1542 [(set (match_dup 6) (match_dup 7))
1543 (use (match_dup 8))])]
1544 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1545 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1546 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1550 ; load_multiple pattern(s).
1552 ; ??? Due to reload problems with replacing registers inside match_parallel
1553 ; we currently support load_multiple/store_multiple only after reload.
1556 (define_expand "load_multiple"
1557 [(match_par_dup 3 [(set (match_operand 0 "" "")
1558 (match_operand 1 "" ""))
1559 (use (match_operand 2 "" ""))])]
1562 enum machine_mode mode;
1568 /* Support only loading a constant number of fixed-point registers from
1569 memory and only bother with this if more than two */
1570 if (GET_CODE (operands[2]) != CONST_INT
1571 || INTVAL (operands[2]) < 2
1572 || INTVAL (operands[2]) > 16
1573 || GET_CODE (operands[1]) != MEM
1574 || GET_CODE (operands[0]) != REG
1575 || REGNO (operands[0]) >= 16)
1578 count = INTVAL (operands[2]);
1579 regno = REGNO (operands[0]);
1580 mode = GET_MODE (operands[0]);
1581 if (mode != SImode && mode != word_mode)
1584 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1587 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1589 from = XEXP (operands[1], 0);
1592 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1593 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1594 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1596 from = XEXP (XEXP (operands[1], 0), 0);
1597 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1604 from = force_reg (Pmode, XEXP (operands[1], 0));
1608 for (i = 0; i < count; i++)
1609 XVECEXP (operands[3], 0, i)
1610 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1611 change_address (operands[1], mode,
1612 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1615 (define_insn "*load_multiple_di"
1616 [(match_parallel 0 "load_multiple_operation"
1617 [(set (match_operand:DI 1 "register_operand" "=r")
1618 (match_operand:DI 2 "s_operand" "QS"))])]
1619 "reload_completed && word_mode == DImode"
1621 int words = XVECLEN (operands[0], 0);
1622 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1623 return "lmg\t%1,%0,%S2";
1625 [(set_attr "op_type" "RSY")
1626 (set_attr "type" "lm")])
1628 (define_insn "*load_multiple_si"
1629 [(match_parallel 0 "load_multiple_operation"
1630 [(set (match_operand:SI 1 "register_operand" "=r,r")
1631 (match_operand:SI 2 "s_operand" "Q,S"))])]
1634 int words = XVECLEN (operands[0], 0);
1635 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1636 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1638 [(set_attr "op_type" "RS,RSY")
1639 (set_attr "type" "lm")])
1642 ; store multiple pattern(s).
1645 (define_expand "store_multiple"
1646 [(match_par_dup 3 [(set (match_operand 0 "" "")
1647 (match_operand 1 "" ""))
1648 (use (match_operand 2 "" ""))])]
1651 enum machine_mode mode;
1657 /* Support only storing a constant number of fixed-point registers to
1658 memory and only bother with this if more than two. */
1659 if (GET_CODE (operands[2]) != CONST_INT
1660 || INTVAL (operands[2]) < 2
1661 || INTVAL (operands[2]) > 16
1662 || GET_CODE (operands[0]) != MEM
1663 || GET_CODE (operands[1]) != REG
1664 || REGNO (operands[1]) >= 16)
1667 count = INTVAL (operands[2]);
1668 regno = REGNO (operands[1]);
1669 mode = GET_MODE (operands[1]);
1670 if (mode != SImode && mode != word_mode)
1673 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1677 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1679 to = XEXP (operands[0], 0);
1682 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1683 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1684 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1686 to = XEXP (XEXP (operands[0], 0), 0);
1687 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1694 to = force_reg (Pmode, XEXP (operands[0], 0));
1698 for (i = 0; i < count; i++)
1699 XVECEXP (operands[3], 0, i)
1700 = gen_rtx_SET (VOIDmode,
1701 change_address (operands[0], mode,
1702 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1703 gen_rtx_REG (mode, regno + i));
1706 (define_insn "*store_multiple_di"
1707 [(match_parallel 0 "store_multiple_operation"
1708 [(set (match_operand:DI 1 "s_operand" "=QS")
1709 (match_operand:DI 2 "register_operand" "r"))])]
1710 "reload_completed && word_mode == DImode"
1712 int words = XVECLEN (operands[0], 0);
1713 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1714 return "stmg\t%2,%0,%S1";
1716 [(set_attr "op_type" "RSY")
1717 (set_attr "type" "stm")])
1720 (define_insn "*store_multiple_si"
1721 [(match_parallel 0 "store_multiple_operation"
1722 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1723 (match_operand:SI 2 "register_operand" "r,r"))])]
1726 int words = XVECLEN (operands[0], 0);
1727 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1728 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1730 [(set_attr "op_type" "RS,RSY")
1731 (set_attr "type" "stm")])
1734 ;; String instructions.
1737 (define_insn "*execute"
1738 [(match_parallel 0 ""
1739 [(unspec [(match_operand 1 "register_operand" "a")
1740 (match_operand:BLK 2 "memory_operand" "R")
1741 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1742 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1743 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1745 [(set_attr "op_type" "RX")
1746 (set_attr "type" "cs")])
1750 ; strlenM instruction pattern(s).
1753 (define_expand "strlen<mode>"
1754 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1757 (unspec:P [(const_int 0)
1758 (match_operand:BLK 1 "memory_operand" "")
1760 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1761 (clobber (scratch:P))
1762 (clobber (reg:CC CC_REGNUM))])
1764 [(set (match_operand:P 0 "register_operand" "")
1765 (minus:P (match_dup 4) (match_dup 5)))
1766 (clobber (reg:CC CC_REGNUM))])]
1769 operands[4] = gen_reg_rtx (Pmode);
1770 operands[5] = gen_reg_rtx (Pmode);
1771 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1772 operands[1] = replace_equiv_address (operands[1], operands[5]);
1775 (define_insn "*strlen<mode>"
1776 [(set (match_operand:P 0 "register_operand" "=a")
1777 (unspec:P [(match_operand:P 2 "general_operand" "0")
1778 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1780 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1781 (clobber (match_scratch:P 1 "=a"))
1782 (clobber (reg:CC CC_REGNUM))]
1784 "srst\t%0,%1\;jo\t.-4"
1785 [(set_attr "length" "8")
1786 (set_attr "type" "vs")])
1789 ; movmemM instruction pattern(s).
1792 (define_expand "movmem<mode>"
1793 [(set (match_operand:BLK 0 "memory_operand" "")
1794 (match_operand:BLK 1 "memory_operand" ""))
1795 (use (match_operand:GPR 2 "general_operand" ""))
1796 (match_operand 3 "" "")]
1798 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1800 ; Move a block that is up to 256 bytes in length.
1801 ; The block length is taken as (operands[2] % 256) + 1.
1803 (define_expand "movmem_short"
1805 [(set (match_operand:BLK 0 "memory_operand" "")
1806 (match_operand:BLK 1 "memory_operand" ""))
1807 (use (match_operand 2 "nonmemory_operand" ""))
1808 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1809 (clobber (match_dup 3))])]
1811 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1813 (define_insn "*movmem_short"
1814 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1815 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1816 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1817 (use (match_operand 3 "immediate_operand" "X,R,X"))
1818 (clobber (match_scratch 4 "=X,X,&a"))]
1819 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1820 && GET_MODE (operands[4]) == Pmode"
1822 [(set_attr "type" "cs")])
1825 [(set (match_operand:BLK 0 "memory_operand" "")
1826 (match_operand:BLK 1 "memory_operand" ""))
1827 (use (match_operand 2 "const_int_operand" ""))
1828 (use (match_operand 3 "immediate_operand" ""))
1829 (clobber (scratch))]
1832 [(set (match_dup 0) (match_dup 1))
1833 (use (match_dup 2))])]
1834 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1837 [(set (match_operand:BLK 0 "memory_operand" "")
1838 (match_operand:BLK 1 "memory_operand" ""))
1839 (use (match_operand 2 "register_operand" ""))
1840 (use (match_operand 3 "memory_operand" ""))
1841 (clobber (scratch))]
1844 [(unspec [(match_dup 2) (match_dup 3)
1845 (const_int 0)] UNSPEC_EXECUTE)
1846 (set (match_dup 0) (match_dup 1))
1847 (use (const_int 1))])]
1851 [(set (match_operand:BLK 0 "memory_operand" "")
1852 (match_operand:BLK 1 "memory_operand" ""))
1853 (use (match_operand 2 "register_operand" ""))
1854 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1855 (clobber (match_operand 3 "register_operand" ""))]
1856 "reload_completed && TARGET_CPU_ZARCH"
1857 [(set (match_dup 3) (label_ref (match_dup 4)))
1859 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1860 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1861 (set (match_dup 0) (match_dup 1))
1862 (use (const_int 1))])]
1863 "operands[4] = gen_label_rtx ();")
1865 ; Move a block of arbitrary length.
1867 (define_expand "movmem_long"
1869 [(clobber (match_dup 2))
1870 (clobber (match_dup 3))
1871 (set (match_operand:BLK 0 "memory_operand" "")
1872 (match_operand:BLK 1 "memory_operand" ""))
1873 (use (match_operand 2 "general_operand" ""))
1875 (clobber (reg:CC CC_REGNUM))])]
1878 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1879 rtx reg0 = gen_reg_rtx (dword_mode);
1880 rtx reg1 = gen_reg_rtx (dword_mode);
1881 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1882 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1883 rtx len0 = gen_lowpart (Pmode, reg0);
1884 rtx len1 = gen_lowpart (Pmode, reg1);
1886 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1887 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1888 emit_move_insn (len0, operands[2]);
1890 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1891 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1892 emit_move_insn (len1, operands[2]);
1894 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1895 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1900 (define_insn "*movmem_long_64"
1901 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1902 (clobber (match_operand:TI 1 "register_operand" "=d"))
1903 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1904 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1907 (clobber (reg:CC CC_REGNUM))]
1909 "mvcle\t%0,%1,0\;jo\t.-4"
1910 [(set_attr "length" "8")
1911 (set_attr "type" "vs")])
1913 (define_insn "*movmem_long_31"
1914 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1915 (clobber (match_operand:DI 1 "register_operand" "=d"))
1916 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1917 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1920 (clobber (reg:CC CC_REGNUM))]
1922 "mvcle\t%0,%1,0\;jo\t.-4"
1923 [(set_attr "length" "8")
1924 (set_attr "type" "vs")])
1927 ; clrmemM instruction pattern(s).
1930 (define_expand "clrmem<mode>"
1931 [(set (match_operand:BLK 0 "memory_operand" "")
1933 (use (match_operand:GPR 1 "general_operand" ""))
1934 (match_operand 2 "" "")]
1936 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1938 ; Clear a block that is up to 256 bytes in length.
1939 ; The block length is taken as (operands[1] % 256) + 1.
1941 (define_expand "clrmem_short"
1943 [(set (match_operand:BLK 0 "memory_operand" "")
1945 (use (match_operand 1 "nonmemory_operand" ""))
1946 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1947 (clobber (match_dup 2))
1948 (clobber (reg:CC CC_REGNUM))])]
1950 "operands[2] = gen_rtx_SCRATCH (Pmode);")
1952 (define_insn "*clrmem_short"
1953 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1955 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
1956 (use (match_operand 2 "immediate_operand" "X,R,X"))
1957 (clobber (match_scratch 3 "=X,X,&a"))
1958 (clobber (reg:CC CC_REGNUM))]
1959 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
1960 && GET_MODE (operands[3]) == Pmode"
1962 [(set_attr "type" "cs")])
1965 [(set (match_operand:BLK 0 "memory_operand" "")
1967 (use (match_operand 1 "const_int_operand" ""))
1968 (use (match_operand 2 "immediate_operand" ""))
1970 (clobber (reg:CC CC_REGNUM))]
1973 [(set (match_dup 0) (const_int 0))
1975 (clobber (reg:CC CC_REGNUM))])]
1976 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
1979 [(set (match_operand:BLK 0 "memory_operand" "")
1981 (use (match_operand 1 "register_operand" ""))
1982 (use (match_operand 2 "memory_operand" ""))
1984 (clobber (reg:CC CC_REGNUM))]
1987 [(unspec [(match_dup 1) (match_dup 2)
1988 (const_int 0)] UNSPEC_EXECUTE)
1989 (set (match_dup 0) (const_int 0))
1991 (clobber (reg:CC CC_REGNUM))])]
1995 [(set (match_operand:BLK 0 "memory_operand" "")
1997 (use (match_operand 1 "register_operand" ""))
1998 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1999 (clobber (match_operand 2 "register_operand" ""))
2000 (clobber (reg:CC CC_REGNUM))]
2001 "reload_completed && TARGET_CPU_ZARCH"
2002 [(set (match_dup 2) (label_ref (match_dup 3)))
2004 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2005 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2006 (set (match_dup 0) (const_int 0))
2008 (clobber (reg:CC CC_REGNUM))])]
2009 "operands[3] = gen_label_rtx ();")
2011 ; Clear a block of arbitrary length.
2013 (define_expand "clrmem_long"
2015 [(clobber (match_dup 1))
2016 (set (match_operand:BLK 0 "memory_operand" "")
2018 (use (match_operand 1 "general_operand" ""))
2020 (clobber (reg:CC CC_REGNUM))])]
2023 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2024 rtx reg0 = gen_reg_rtx (dword_mode);
2025 rtx reg1 = gen_reg_rtx (dword_mode);
2026 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2027 rtx len0 = gen_lowpart (Pmode, reg0);
2029 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2030 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2031 emit_move_insn (len0, operands[1]);
2033 emit_move_insn (reg1, const0_rtx);
2035 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2040 (define_insn "*clrmem_long_64"
2041 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2042 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2045 (use (match_operand:TI 1 "register_operand" "d"))
2046 (clobber (reg:CC CC_REGNUM))]
2048 "mvcle\t%0,%1,0\;jo\t.-4"
2049 [(set_attr "length" "8")
2050 (set_attr "type" "vs")])
2052 (define_insn "*clrmem_long_31"
2053 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2054 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2057 (use (match_operand:DI 1 "register_operand" "d"))
2058 (clobber (reg:CC CC_REGNUM))]
2060 "mvcle\t%0,%1,0\;jo\t.-4"
2061 [(set_attr "length" "8")
2062 (set_attr "type" "vs")])
2065 ; cmpmemM instruction pattern(s).
2068 (define_expand "cmpmemsi"
2069 [(set (match_operand:SI 0 "register_operand" "")
2070 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2071 (match_operand:BLK 2 "memory_operand" "") ) )
2072 (use (match_operand:SI 3 "general_operand" ""))
2073 (use (match_operand:SI 4 "" ""))]
2075 "s390_expand_cmpmem (operands[0], operands[1],
2076 operands[2], operands[3]); DONE;")
2078 ; Compare a block that is up to 256 bytes in length.
2079 ; The block length is taken as (operands[2] % 256) + 1.
2081 (define_expand "cmpmem_short"
2083 [(set (reg:CCU CC_REGNUM)
2084 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2085 (match_operand:BLK 1 "memory_operand" "")))
2086 (use (match_operand 2 "nonmemory_operand" ""))
2087 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2088 (clobber (match_dup 3))])]
2090 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2092 (define_insn "*cmpmem_short"
2093 [(set (reg:CCU CC_REGNUM)
2094 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2095 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2096 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2097 (use (match_operand 3 "immediate_operand" "X,R,X"))
2098 (clobber (match_scratch 4 "=X,X,&a"))]
2099 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2100 && GET_MODE (operands[4]) == Pmode"
2102 [(set_attr "type" "cs")])
2105 [(set (reg:CCU CC_REGNUM)
2106 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2107 (match_operand:BLK 1 "memory_operand" "")))
2108 (use (match_operand 2 "const_int_operand" ""))
2109 (use (match_operand 3 "immediate_operand" ""))
2110 (clobber (scratch))]
2113 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2114 (use (match_dup 2))])]
2115 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2118 [(set (reg:CCU CC_REGNUM)
2119 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2120 (match_operand:BLK 1 "memory_operand" "")))
2121 (use (match_operand 2 "register_operand" ""))
2122 (use (match_operand 3 "memory_operand" ""))
2123 (clobber (scratch))]
2126 [(unspec [(match_dup 2) (match_dup 3)
2127 (const_int 0)] UNSPEC_EXECUTE)
2128 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2129 (use (const_int 1))])]
2133 [(set (reg:CCU CC_REGNUM)
2134 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2135 (match_operand:BLK 1 "memory_operand" "")))
2136 (use (match_operand 2 "register_operand" ""))
2137 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2138 (clobber (match_operand 3 "register_operand" ""))]
2139 "reload_completed && TARGET_CPU_ZARCH"
2140 [(set (match_dup 3) (label_ref (match_dup 4)))
2142 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2143 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2144 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2145 (use (const_int 1))])]
2146 "operands[4] = gen_label_rtx ();")
2148 ; Compare a block of arbitrary length.
2150 (define_expand "cmpmem_long"
2152 [(clobber (match_dup 2))
2153 (clobber (match_dup 3))
2154 (set (reg:CCU CC_REGNUM)
2155 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2156 (match_operand:BLK 1 "memory_operand" "")))
2157 (use (match_operand 2 "general_operand" ""))
2158 (use (match_dup 3))])]
2161 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2162 rtx reg0 = gen_reg_rtx (dword_mode);
2163 rtx reg1 = gen_reg_rtx (dword_mode);
2164 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2165 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2166 rtx len0 = gen_lowpart (Pmode, reg0);
2167 rtx len1 = gen_lowpart (Pmode, reg1);
2169 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2170 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2171 emit_move_insn (len0, operands[2]);
2173 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2174 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2175 emit_move_insn (len1, operands[2]);
2177 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2178 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2183 (define_insn "*cmpmem_long_64"
2184 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2185 (clobber (match_operand:TI 1 "register_operand" "=d"))
2186 (set (reg:CCU CC_REGNUM)
2187 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2188 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2190 (use (match_dup 3))]
2192 "clcle\t%0,%1,0\;jo\t.-4"
2193 [(set_attr "length" "8")
2194 (set_attr "type" "vs")])
2196 (define_insn "*cmpmem_long_31"
2197 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2198 (clobber (match_operand:DI 1 "register_operand" "=d"))
2199 (set (reg:CCU CC_REGNUM)
2200 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2201 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2203 (use (match_dup 3))]
2205 "clcle\t%0,%1,0\;jo\t.-4"
2206 [(set_attr "length" "8")
2207 (set_attr "type" "vs")])
2209 ; Convert CCUmode condition code to integer.
2210 ; Result is zero if EQ, positive if LTU, negative if GTU.
2212 (define_insn_and_split "cmpint"
2213 [(set (match_operand:SI 0 "register_operand" "=d")
2214 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2216 (clobber (reg:CC CC_REGNUM))]
2220 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2222 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2223 (clobber (reg:CC CC_REGNUM))])])
2225 (define_insn_and_split "*cmpint_cc"
2226 [(set (reg CC_REGNUM)
2227 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2230 (set (match_operand:SI 0 "register_operand" "=d")
2231 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2232 "s390_match_ccmode (insn, CCSmode)"
2234 "&& reload_completed"
2235 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2237 [(set (match_dup 2) (match_dup 3))
2238 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2240 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2241 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2242 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2245 (define_insn_and_split "*cmpint_sign"
2246 [(set (match_operand:DI 0 "register_operand" "=d")
2247 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2249 (clobber (reg:CC CC_REGNUM))]
2252 "&& reload_completed"
2253 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2255 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2256 (clobber (reg:CC CC_REGNUM))])])
2258 (define_insn_and_split "*cmpint_sign_cc"
2259 [(set (reg CC_REGNUM)
2260 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2261 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2263 (const_int 32)) (const_int 32))
2265 (set (match_operand:DI 0 "register_operand" "=d")
2266 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2267 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2269 "&& reload_completed"
2270 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2272 [(set (match_dup 2) (match_dup 3))
2273 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2275 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2276 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2277 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2282 ;;- Conversion instructions.
2286 (define_insn "*sethigh<mode>si"
2287 [(set (match_operand:SI 0 "register_operand" "=d,d")
2288 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2289 (clobber (reg:CC CC_REGNUM))]
2292 icm\t%0,<icm_hi>,%S1
2293 icmy\t%0,<icm_hi>,%S1"
2294 [(set_attr "op_type" "RS,RSY")])
2296 (define_insn "*sethighqidi_64"
2297 [(set (match_operand:DI 0 "register_operand" "=d")
2298 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2299 (clobber (reg:CC CC_REGNUM))]
2302 [(set_attr "op_type" "RSY")])
2304 (define_insn "*sethighqidi_31"
2305 [(set (match_operand:DI 0 "register_operand" "=d,d")
2306 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2307 (clobber (reg:CC CC_REGNUM))]
2312 [(set_attr "op_type" "RS,RSY")])
2314 (define_insn_and_split "*extractqi"
2315 [(set (match_operand:SI 0 "register_operand" "=d")
2316 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2317 (match_operand 2 "const_int_operand" "n")
2319 (clobber (reg:CC CC_REGNUM))]
2321 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2323 "&& reload_completed"
2325 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2326 (clobber (reg:CC CC_REGNUM))])
2327 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2329 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2330 operands[1] = change_address (operands[1], QImode, 0);
2333 (define_insn_and_split "*extracthi"
2334 [(set (match_operand:SI 0 "register_operand" "=d")
2335 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2336 (match_operand 2 "const_int_operand" "n")
2338 (clobber (reg:CC CC_REGNUM))]
2340 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2342 "&& reload_completed"
2344 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2345 (clobber (reg:CC CC_REGNUM))])
2346 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2348 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2349 operands[1] = change_address (operands[1], HImode, 0);
2353 ; extendsidi2 instruction pattern(s).
2356 (define_expand "extendsidi2"
2357 [(set (match_operand:DI 0 "register_operand" "")
2358 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2364 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2365 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2366 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2367 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2373 (define_insn "*extendsidi2"
2374 [(set (match_operand:DI 0 "register_operand" "=d,d")
2375 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2380 [(set_attr "op_type" "RRE,RXY")])
2383 ; extend(hi|qi)di2 instruction pattern(s).
2386 (define_expand "extend<mode>di2"
2387 [(set (match_operand:DI 0 "register_operand" "")
2388 (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2394 rtx tmp = gen_reg_rtx (SImode);
2395 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2396 emit_insn (gen_extendsidi2 (operands[0], tmp));
2401 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2402 GET_MODE_BITSIZE (<MODE>mode));
2403 operands[1] = gen_lowpart (DImode, operands[1]);
2404 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2405 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2411 (define_insn "*extendhidi2"
2412 [(set (match_operand:DI 0 "register_operand" "=d")
2413 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2416 [(set_attr "op_type" "RXY")])
2418 (define_insn "*extendqidi2"
2419 [(set (match_operand:DI 0 "register_operand" "=d")
2420 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2421 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2423 [(set_attr "op_type" "RXY")])
2425 (define_insn_and_split "*extendqidi2_short_displ"
2426 [(set (match_operand:DI 0 "register_operand" "=d")
2427 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2428 (clobber (reg:CC CC_REGNUM))]
2429 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2431 "&& reload_completed"
2433 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2434 (clobber (reg:CC CC_REGNUM))])
2436 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2437 (clobber (reg:CC CC_REGNUM))])]
2441 ; extend(hi|qi)si2 instruction pattern(s).
2444 (define_expand "extend<mode>si2"
2445 [(set (match_operand:SI 0 "register_operand" "")
2446 (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2450 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2451 GET_MODE_BITSIZE(<MODE>mode));
2452 operands[1] = gen_lowpart (SImode, operands[1]);
2453 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2454 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2459 (define_insn "*extendhisi2"
2460 [(set (match_operand:SI 0 "register_operand" "=d,d")
2461 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2466 [(set_attr "op_type" "RX,RXY")])
2468 (define_insn "*extendqisi2"
2469 [(set (match_operand:SI 0 "register_operand" "=d")
2470 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2471 "TARGET_LONG_DISPLACEMENT"
2473 [(set_attr "op_type" "RXY")])
2475 (define_insn_and_split "*extendqisi2_short_displ"
2476 [(set (match_operand:SI 0 "register_operand" "=d")
2477 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2478 (clobber (reg:CC CC_REGNUM))]
2479 "!TARGET_LONG_DISPLACEMENT"
2481 "&& reload_completed"
2483 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2484 (clobber (reg:CC CC_REGNUM))])
2486 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2487 (clobber (reg:CC CC_REGNUM))])]
2491 ; extendqihi2 instruction pattern(s).
2496 ; zero_extendsidi2 instruction pattern(s).
2499 (define_expand "zero_extendsidi2"
2500 [(set (match_operand:DI 0 "register_operand" "")
2501 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2507 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2508 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2509 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2515 (define_insn "*zero_extendsidi2"
2516 [(set (match_operand:DI 0 "register_operand" "=d,d")
2517 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2522 [(set_attr "op_type" "RRE,RXY")])
2525 ; zero_extend(hi|qi)di2 instruction pattern(s).
2528 (define_expand "zero_extend<mode>di2"
2529 [(set (match_operand:DI 0 "register_operand" "")
2530 (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))]
2536 rtx tmp = gen_reg_rtx (SImode);
2537 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2538 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2543 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2544 GET_MODE_BITSIZE(<MODE>mode));
2545 operands[1] = gen_lowpart (DImode, operands[1]);
2546 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2547 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2553 (define_insn "*zero_extend<mode>di2"
2554 [(set (match_operand:DI 0 "register_operand" "=d")
2555 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2558 [(set_attr "op_type" "RXY")])
2561 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2564 (define_insn "*llgt_sidi"
2565 [(set (match_operand:DI 0 "register_operand" "=d")
2566 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2567 (const_int 2147483647)))]
2570 [(set_attr "op_type" "RXE")])
2572 (define_insn_and_split "*llgt_sidi_split"
2573 [(set (match_operand:DI 0 "register_operand" "=d")
2574 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2575 (const_int 2147483647)))
2576 (clobber (reg:CC CC_REGNUM))]
2579 "&& reload_completed"
2581 (and:DI (subreg:DI (match_dup 1) 0)
2582 (const_int 2147483647)))]
2585 (define_insn "*llgt_sisi"
2586 [(set (match_operand:SI 0 "register_operand" "=d,d")
2587 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2588 (const_int 2147483647)))]
2593 [(set_attr "op_type" "RRE,RXE")])
2595 (define_insn "*llgt_didi"
2596 [(set (match_operand:DI 0 "register_operand" "=d,d")
2597 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2598 (const_int 2147483647)))]
2603 [(set_attr "op_type" "RRE,RXE")])
2606 [(set (match_operand:GPR 0 "register_operand" "")
2607 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2608 (const_int 2147483647)))
2609 (clobber (reg:CC CC_REGNUM))]
2610 "TARGET_64BIT && reload_completed"
2612 (and:GPR (match_dup 1)
2613 (const_int 2147483647)))]
2617 ; zero_extend(hi|qi)si2 instruction pattern(s).
2620 (define_expand "zero_extend<mode>si2"
2621 [(set (match_operand:SI 0 "register_operand" "")
2622 (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))]
2626 operands[1] = gen_lowpart (SImode, operands[1]);
2627 emit_insn (gen_andsi3 (operands[0], operands[1],
2628 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2633 (define_insn "*zero_extend<mode>si2_64"
2634 [(set (match_operand:SI 0 "register_operand" "=d")
2635 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2638 [(set_attr "op_type" "RXY")])
2640 (define_insn_and_split "*zero_extendhisi2_31"
2641 [(set (match_operand:SI 0 "register_operand" "=&d")
2642 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2643 (clobber (reg:CC CC_REGNUM))]
2646 "&& reload_completed"
2647 [(set (match_dup 0) (const_int 0))
2649 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2650 (clobber (reg:CC CC_REGNUM))])]
2651 "operands[2] = gen_lowpart (HImode, operands[0]);")
2653 (define_insn_and_split "*zero_extendqisi2_31"
2654 [(set (match_operand:SI 0 "register_operand" "=&d")
2655 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2658 "&& reload_completed"
2659 [(set (match_dup 0) (const_int 0))
2660 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2661 "operands[2] = gen_lowpart (QImode, operands[0]);")
2664 ; zero_extendqihi2 instruction pattern(s).
2667 (define_expand "zero_extendqihi2"
2668 [(set (match_operand:HI 0 "register_operand" "")
2669 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2673 operands[1] = gen_lowpart (HImode, operands[1]);
2674 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2679 (define_insn "*zero_extendqihi2_64"
2680 [(set (match_operand:HI 0 "register_operand" "=d")
2681 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2684 [(set_attr "op_type" "RXY")])
2686 (define_insn_and_split "*zero_extendqihi2_31"
2687 [(set (match_operand:HI 0 "register_operand" "=&d")
2688 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2691 "&& reload_completed"
2692 [(set (match_dup 0) (const_int 0))
2693 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2694 "operands[2] = gen_lowpart (QImode, operands[0]);")
2698 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2701 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2702 [(set (match_operand:GPR 0 "register_operand" "")
2703 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2704 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2706 rtx label1 = gen_label_rtx ();
2707 rtx label2 = gen_label_rtx ();
2708 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2709 REAL_VALUE_TYPE cmp, sub;
2711 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2712 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2713 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2715 emit_insn (gen_cmp<FPR:mode> (operands[1],
2716 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2717 emit_jump_insn (gen_blt (label1));
2718 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2719 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2720 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2724 emit_label (label1);
2725 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2726 operands[1], GEN_INT(5)));
2727 emit_label (label2);
2731 (define_expand "fix_trunc<FPR:mode>di2"
2732 [(set (match_operand:DI 0 "register_operand" "")
2733 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2734 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2736 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2737 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2742 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2743 [(set (match_operand:GPR 0 "register_operand" "=d")
2744 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2745 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2746 (clobber (reg:CC CC_REGNUM))]
2747 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2748 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2749 [(set_attr "op_type" "RRE")
2750 (set_attr "type" "ftoi")])
2753 ; fix_truncdfsi2 instruction pattern(s).
2756 (define_expand "fix_truncdfsi2"
2757 [(set (match_operand:SI 0 "register_operand" "")
2758 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2761 if (TARGET_IBM_FLOAT)
2763 /* This is the algorithm from POP chapter A.5.7.2. */
2765 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2766 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2767 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2769 operands[1] = force_reg (DFmode, operands[1]);
2770 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2771 two31r, two32, temp));
2775 operands[1] = force_reg (DFmode, operands[1]);
2776 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2782 (define_insn "fix_truncdfsi2_ibm"
2783 [(set (match_operand:SI 0 "register_operand" "=d")
2784 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2785 (use (match_operand:DI 2 "immediate_operand" "m"))
2786 (use (match_operand:DI 3 "immediate_operand" "m"))
2787 (use (match_operand:BLK 4 "memory_operand" "m"))
2788 (clobber (reg:CC CC_REGNUM))]
2789 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2791 output_asm_insn ("sd\t%1,%2", operands);
2792 output_asm_insn ("aw\t%1,%3", operands);
2793 output_asm_insn ("std\t%1,%4", operands);
2794 output_asm_insn ("xi\t%N4,128", operands);
2797 [(set_attr "length" "20")])
2800 ; fix_truncsfsi2 instruction pattern(s).
2803 (define_expand "fix_truncsfsi2"
2804 [(set (match_operand:SI 0 "register_operand" "")
2805 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2808 if (TARGET_IBM_FLOAT)
2810 /* Convert to DFmode and then use the POP algorithm. */
2811 rtx temp = gen_reg_rtx (DFmode);
2812 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2813 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2817 operands[1] = force_reg (SFmode, operands[1]);
2818 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2825 ; floatdi(df|sf)2 instruction pattern(s).
2828 (define_insn "floatdi<mode>2"
2829 [(set (match_operand:FPR 0 "register_operand" "=f")
2830 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
2831 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2833 [(set_attr "op_type" "RRE")
2834 (set_attr "type" "itof" )])
2837 ; floatsidf2 instruction pattern(s).
2840 (define_expand "floatsidf2"
2841 [(set (match_operand:DF 0 "register_operand" "")
2842 (float:DF (match_operand:SI 1 "register_operand" "")))]
2845 if (TARGET_IBM_FLOAT)
2847 /* This is the algorithm from POP chapter A.5.7.1. */
2849 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2850 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2852 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2857 (define_insn "floatsidf2_ieee"
2858 [(set (match_operand:DF 0 "register_operand" "=f")
2859 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2860 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2862 [(set_attr "op_type" "RRE")
2863 (set_attr "type" "itof" )])
2865 (define_insn "floatsidf2_ibm"
2866 [(set (match_operand:DF 0 "register_operand" "=f")
2867 (float:DF (match_operand:SI 1 "register_operand" "d")))
2868 (use (match_operand:DI 2 "immediate_operand" "m"))
2869 (use (match_operand:BLK 3 "memory_operand" "m"))
2870 (clobber (reg:CC CC_REGNUM))]
2871 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2873 output_asm_insn ("st\t%1,%N3", operands);
2874 output_asm_insn ("xi\t%N3,128", operands);
2875 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
2876 output_asm_insn ("ld\t%0,%3", operands);
2879 [(set_attr "length" "20")])
2882 ; floatsisf2 instruction pattern(s).
2885 (define_expand "floatsisf2"
2886 [(set (match_operand:SF 0 "register_operand" "")
2887 (float:SF (match_operand:SI 1 "register_operand" "")))]
2890 if (TARGET_IBM_FLOAT)
2892 /* Use the POP algorithm to convert to DFmode and then truncate. */
2893 rtx temp = gen_reg_rtx (DFmode);
2894 emit_insn (gen_floatsidf2 (temp, operands[1]));
2895 emit_insn (gen_truncdfsf2 (operands[0], temp));
2900 (define_insn "floatsisf2_ieee"
2901 [(set (match_operand:SF 0 "register_operand" "=f")
2902 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2903 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2905 [(set_attr "op_type" "RRE")
2906 (set_attr "type" "itof" )])
2909 ; truncdfsf2 instruction pattern(s).
2912 (define_expand "truncdfsf2"
2913 [(set (match_operand:SF 0 "register_operand" "")
2914 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
2918 (define_insn "truncdfsf2_ieee"
2919 [(set (match_operand:SF 0 "register_operand" "=f")
2920 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2921 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2923 [(set_attr "op_type" "RRE")])
2925 (define_insn "truncdfsf2_ibm"
2926 [(set (match_operand:SF 0 "register_operand" "=f,f")
2927 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
2928 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2932 [(set_attr "op_type" "RR,RX")
2933 (set_attr "type" "floadsf")])
2936 ; extendsfdf2 instruction pattern(s).
2939 (define_expand "extendsfdf2"
2940 [(set (match_operand:DF 0 "register_operand" "")
2941 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2944 if (TARGET_IBM_FLOAT)
2946 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2951 (define_insn "extendsfdf2_ieee"
2952 [(set (match_operand:DF 0 "register_operand" "=f,f")
2953 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
2954 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2958 [(set_attr "op_type" "RRE,RXE")
2959 (set_attr "type" "floadsf")])
2961 (define_insn "extendsfdf2_ibm"
2962 [(set (match_operand:DF 0 "register_operand" "=f,f")
2963 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
2964 (clobber (reg:CC CC_REGNUM))]
2965 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2967 sdr\t%0,%0\;ler\t%0,%1
2968 sdr\t%0,%0\;le\t%0,%1"
2969 [(set_attr "length" "4,6")
2970 (set_attr "type" "floadsf")])
2974 ;; ARITHMETIC OPERATIONS
2976 ; arithmetic operations set the ConditionCode,
2977 ; because of unpredictable Bits in Register for Halfword and Byte
2978 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2981 ;;- Add instructions.
2985 ; addti3 instruction pattern(s).
2988 (define_insn_and_split "addti3"
2989 [(set (match_operand:TI 0 "register_operand" "=&d")
2990 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
2991 (match_operand:TI 2 "general_operand" "do") ) )
2992 (clobber (reg:CC CC_REGNUM))]
2995 "&& reload_completed"
2997 [(set (reg:CCL1 CC_REGNUM)
2998 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3000 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3002 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3003 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3004 (clobber (reg:CC CC_REGNUM))])]
3005 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3006 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3007 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3008 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3009 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3010 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3013 ; adddi3 instruction pattern(s).
3016 (define_insn "*adddi3_sign"
3017 [(set (match_operand:DI 0 "register_operand" "=d,d")
3018 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3019 (match_operand:DI 1 "register_operand" "0,0")))
3020 (clobber (reg:CC CC_REGNUM))]
3025 [(set_attr "op_type" "RRE,RXY")])
3027 (define_insn "*adddi3_zero_cc"
3028 [(set (reg CC_REGNUM)
3029 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3030 (match_operand:DI 1 "register_operand" "0,0"))
3032 (set (match_operand:DI 0 "register_operand" "=d,d")
3033 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3034 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3038 [(set_attr "op_type" "RRE,RXY")])
3040 (define_insn "*adddi3_zero_cconly"
3041 [(set (reg CC_REGNUM)
3042 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3043 (match_operand:DI 1 "register_operand" "0,0"))
3045 (clobber (match_scratch:DI 0 "=d,d"))]
3046 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3050 [(set_attr "op_type" "RRE,RXY")])
3052 (define_insn "*adddi3_zero"
3053 [(set (match_operand:DI 0 "register_operand" "=d,d")
3054 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3055 (match_operand:DI 1 "register_operand" "0,0")))
3056 (clobber (reg:CC CC_REGNUM))]
3061 [(set_attr "op_type" "RRE,RXY")])
3063 (define_insn "*adddi3_imm_cc"
3064 [(set (reg CC_REGNUM)
3065 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3066 (match_operand:DI 2 "const_int_operand" "K"))
3068 (set (match_operand:DI 0 "register_operand" "=d")
3069 (plus:DI (match_dup 1) (match_dup 2)))]
3071 && s390_match_ccmode (insn, CCAmode)
3072 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3074 [(set_attr "op_type" "RI")])
3076 (define_insn "*adddi3_carry1_cc"
3077 [(set (reg CC_REGNUM)
3078 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3079 (match_operand:DI 2 "general_operand" "d,m"))
3081 (set (match_operand:DI 0 "register_operand" "=d,d")
3082 (plus:DI (match_dup 1) (match_dup 2)))]
3083 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3087 [(set_attr "op_type" "RRE,RXY")])
3089 (define_insn "*adddi3_carry1_cconly"
3090 [(set (reg CC_REGNUM)
3091 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3092 (match_operand:DI 2 "general_operand" "d,m"))
3094 (clobber (match_scratch:DI 0 "=d,d"))]
3095 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3099 [(set_attr "op_type" "RRE,RXY")])
3101 (define_insn "*adddi3_carry2_cc"
3102 [(set (reg CC_REGNUM)
3103 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3104 (match_operand:DI 2 "general_operand" "d,m"))
3106 (set (match_operand:DI 0 "register_operand" "=d,d")
3107 (plus:DI (match_dup 1) (match_dup 2)))]
3108 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3112 [(set_attr "op_type" "RRE,RXY")])
3114 (define_insn "*adddi3_carry2_cconly"
3115 [(set (reg CC_REGNUM)
3116 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3117 (match_operand:DI 2 "general_operand" "d,m"))
3119 (clobber (match_scratch:DI 0 "=d,d"))]
3120 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3124 [(set_attr "op_type" "RRE,RXY")])
3126 (define_insn "*adddi3_cc"
3127 [(set (reg CC_REGNUM)
3128 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3129 (match_operand:DI 2 "general_operand" "d,m"))
3131 (set (match_operand:DI 0 "register_operand" "=d,d")
3132 (plus:DI (match_dup 1) (match_dup 2)))]
3133 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3137 [(set_attr "op_type" "RRE,RXY")])
3139 (define_insn "*adddi3_cconly"
3140 [(set (reg CC_REGNUM)
3141 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3142 (match_operand:DI 2 "general_operand" "d,m"))
3144 (clobber (match_scratch:DI 0 "=d,d"))]
3145 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3149 [(set_attr "op_type" "RRE,RXY")])
3151 (define_insn "*adddi3_cconly2"
3152 [(set (reg CC_REGNUM)
3153 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3154 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3155 (clobber (match_scratch:DI 0 "=d,d"))]
3156 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3160 [(set_attr "op_type" "RRE,RXY")])
3162 (define_insn "*adddi3_64"
3163 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3164 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3165 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3166 (clobber (reg:CC CC_REGNUM))]
3172 [(set_attr "op_type" "RRE,RI,RXY")])
3174 (define_insn_and_split "*adddi3_31z"
3175 [(set (match_operand:DI 0 "register_operand" "=&d")
3176 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3177 (match_operand:DI 2 "general_operand" "do") ) )
3178 (clobber (reg:CC CC_REGNUM))]
3179 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3181 "&& reload_completed"
3183 [(set (reg:CCL1 CC_REGNUM)
3184 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3186 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3188 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3189 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3190 (clobber (reg:CC CC_REGNUM))])]
3191 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3192 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3193 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3194 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3195 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3196 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3198 (define_insn_and_split "*adddi3_31"
3199 [(set (match_operand:DI 0 "register_operand" "=&d")
3200 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3201 (match_operand:DI 2 "general_operand" "do") ) )
3202 (clobber (reg:CC CC_REGNUM))]
3205 "&& reload_completed"
3207 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3208 (clobber (reg:CC CC_REGNUM))])
3210 [(set (reg:CCL1 CC_REGNUM)
3211 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3213 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3215 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3217 (label_ref (match_dup 9))))
3219 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3220 (clobber (reg:CC CC_REGNUM))])
3222 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3223 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3224 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3225 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3226 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3227 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3228 operands[9] = gen_label_rtx ();")
3230 (define_expand "adddi3"
3232 [(set (match_operand:DI 0 "register_operand" "")
3233 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3234 (match_operand:DI 2 "general_operand" "")))
3235 (clobber (reg:CC CC_REGNUM))])]
3240 ; addsi3 instruction pattern(s).
3243 (define_insn "*addsi3_imm_cc"
3244 [(set (reg CC_REGNUM)
3245 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3246 (match_operand:SI 2 "const_int_operand" "K"))
3248 (set (match_operand:SI 0 "register_operand" "=d")
3249 (plus:SI (match_dup 1) (match_dup 2)))]
3250 "s390_match_ccmode (insn, CCAmode)
3251 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3253 [(set_attr "op_type" "RI")])
3255 (define_insn "*addsi3_carry1_cc"
3256 [(set (reg CC_REGNUM)
3257 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3258 (match_operand:SI 2 "general_operand" "d,R,T"))
3260 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3261 (plus:SI (match_dup 1) (match_dup 2)))]
3262 "s390_match_ccmode (insn, CCL1mode)"
3267 [(set_attr "op_type" "RR,RX,RXY")])
3269 (define_insn "*addsi3_carry1_cconly"
3270 [(set (reg CC_REGNUM)
3271 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3272 (match_operand:SI 2 "general_operand" "d,R,T"))
3274 (clobber (match_scratch:SI 0 "=d,d,d"))]
3275 "s390_match_ccmode (insn, CCL1mode)"
3280 [(set_attr "op_type" "RR,RX,RXY")])
3282 (define_insn "*addsi3_carry2_cc"
3283 [(set (reg CC_REGNUM)
3284 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3285 (match_operand:SI 2 "general_operand" "d,R,T"))
3287 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3288 (plus:SI (match_dup 1) (match_dup 2)))]
3289 "s390_match_ccmode (insn, CCL1mode)"
3294 [(set_attr "op_type" "RR,RX,RXY")])
3296 (define_insn "*addsi3_carry2_cconly"
3297 [(set (reg CC_REGNUM)
3298 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3299 (match_operand:SI 2 "general_operand" "d,R,T"))
3301 (clobber (match_scratch:SI 0 "=d,d,d"))]
3302 "s390_match_ccmode (insn, CCL1mode)"
3307 [(set_attr "op_type" "RR,RX,RXY")])
3309 (define_insn "*addsi3_cc"
3310 [(set (reg CC_REGNUM)
3311 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3312 (match_operand:SI 2 "general_operand" "d,R,T"))
3314 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3315 (plus:SI (match_dup 1) (match_dup 2)))]
3316 "s390_match_ccmode (insn, CCLmode)"
3321 [(set_attr "op_type" "RR,RX,RXY")])
3323 (define_insn "*addsi3_cconly"
3324 [(set (reg CC_REGNUM)
3325 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3326 (match_operand:SI 2 "general_operand" "d,R,T"))
3328 (clobber (match_scratch:SI 0 "=d,d,d"))]
3329 "s390_match_ccmode (insn, CCLmode)"
3334 [(set_attr "op_type" "RR,RX,RXY")])
3336 (define_insn "*addsi3_cconly2"
3337 [(set (reg CC_REGNUM)
3338 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3339 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3340 (clobber (match_scratch:SI 0 "=d,d,d"))]
3341 "s390_match_ccmode (insn, CCLmode)"
3346 [(set_attr "op_type" "RR,RX,RXY")])
3348 (define_insn "*addsi3_sign"
3349 [(set (match_operand:SI 0 "register_operand" "=d,d")
3350 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3351 (match_operand:SI 1 "register_operand" "0,0")))
3352 (clobber (reg:CC CC_REGNUM))]
3357 [(set_attr "op_type" "RX,RXY")])
3359 (define_insn "addsi3"
3360 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3361 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3362 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3363 (clobber (reg:CC CC_REGNUM))]
3370 [(set_attr "op_type" "RR,RI,RX,RXY")])
3373 ; add(df|sf)3 instruction pattern(s).
3376 (define_expand "add<mode>3"
3378 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3379 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3380 (match_operand:FPR 2 "general_operand" "f,R")))
3381 (clobber (reg:CC CC_REGNUM))])]
3385 (define_insn "*add<mode>3"
3386 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3387 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3388 (match_operand:FPR 2 "general_operand" "f,R")))
3389 (clobber (reg:CC CC_REGNUM))]
3390 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3394 [(set_attr "op_type" "RRE,RXE")
3395 (set_attr "type" "fsimp<mode>")])
3397 (define_insn "*add<mode>3_cc"
3398 [(set (reg CC_REGNUM)
3399 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3400 (match_operand:FPR 2 "general_operand" "f,R"))
3401 (match_operand:FPR 3 "const0_operand" "")))
3402 (set (match_operand:FPR 0 "register_operand" "=f,f")
3403 (plus:FPR (match_dup 1) (match_dup 2)))]
3404 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3408 [(set_attr "op_type" "RRE,RXE")
3409 (set_attr "type" "fsimp<mode>")])
3411 (define_insn "*add<mode>3_cconly"
3412 [(set (reg CC_REGNUM)
3413 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3414 (match_operand:FPR 2 "general_operand" "f,R"))
3415 (match_operand:FPR 3 "const0_operand" "")))
3416 (clobber (match_scratch:FPR 0 "=f,f"))]
3417 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3421 [(set_attr "op_type" "RRE,RXE")
3422 (set_attr "type" "fsimp<mode>")])
3424 (define_insn "*add<mode>3_ibm"
3425 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3426 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3427 (match_operand:FPR 2 "general_operand" "f,R")))
3428 (clobber (reg:CC CC_REGNUM))]
3429 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3433 [(set_attr "op_type" "RR,RX")
3434 (set_attr "type" "fsimp<mode>")])
3438 ;;- Subtract instructions.
3442 ; subti3 instruction pattern(s).
3445 (define_insn_and_split "subti3"
3446 [(set (match_operand:TI 0 "register_operand" "=&d")
3447 (minus:TI (match_operand:TI 1 "register_operand" "0")
3448 (match_operand:TI 2 "general_operand" "do") ) )
3449 (clobber (reg:CC CC_REGNUM))]
3452 "&& reload_completed"
3454 [(set (reg:CCL2 CC_REGNUM)
3455 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3457 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3459 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3460 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3461 (clobber (reg:CC CC_REGNUM))])]
3462 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3463 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3464 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3465 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3466 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3467 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3470 ; subdi3 instruction pattern(s).
3473 (define_insn "*subdi3_sign"
3474 [(set (match_operand:DI 0 "register_operand" "=d,d")
3475 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3476 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3477 (clobber (reg:CC CC_REGNUM))]
3482 [(set_attr "op_type" "RRE,RXY")])
3484 (define_insn "*subdi3_zero_cc"
3485 [(set (reg CC_REGNUM)
3486 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3487 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3489 (set (match_operand:DI 0 "register_operand" "=d,d")
3490 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3491 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3495 [(set_attr "op_type" "RRE,RXY")])
3497 (define_insn "*subdi3_zero_cconly"
3498 [(set (reg CC_REGNUM)
3499 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3500 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3502 (clobber (match_scratch:DI 0 "=d,d"))]
3503 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3507 [(set_attr "op_type" "RRE,RXY")])
3509 (define_insn "*subdi3_zero"
3510 [(set (match_operand:DI 0 "register_operand" "=d,d")
3511 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3512 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3513 (clobber (reg:CC CC_REGNUM))]
3518 [(set_attr "op_type" "RRE,RXY")])
3520 (define_insn "*subdi3_borrow_cc"
3521 [(set (reg CC_REGNUM)
3522 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3523 (match_operand:DI 2 "general_operand" "d,m"))
3525 (set (match_operand:DI 0 "register_operand" "=d,d")
3526 (minus:DI (match_dup 1) (match_dup 2)))]
3527 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3531 [(set_attr "op_type" "RRE,RXY")])
3533 (define_insn "*subdi3_borrow_cconly"
3534 [(set (reg CC_REGNUM)
3535 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3536 (match_operand:DI 2 "general_operand" "d,m"))
3538 (clobber (match_scratch:DI 0 "=d,d"))]
3539 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3543 [(set_attr "op_type" "RRE,RXY")])
3545 (define_insn "*subdi3_cc"
3546 [(set (reg CC_REGNUM)
3547 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3548 (match_operand:DI 2 "general_operand" "d,m"))
3550 (set (match_operand:DI 0 "register_operand" "=d,d")
3551 (minus:DI (match_dup 1) (match_dup 2)))]
3552 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3556 [(set_attr "op_type" "RRE,RXY")])
3558 (define_insn "*subdi3_cc2"
3559 [(set (reg CC_REGNUM)
3560 (compare (match_operand:DI 1 "register_operand" "0,0")
3561 (match_operand:DI 2 "general_operand" "d,m")))
3562 (set (match_operand:DI 0 "register_operand" "=d,d")
3563 (minus:DI (match_dup 1) (match_dup 2)))]
3564 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3568 [(set_attr "op_type" "RRE,RXY")])
3570 (define_insn "*subdi3_cconly"
3571 [(set (reg CC_REGNUM)
3572 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3573 (match_operand:DI 2 "general_operand" "d,m"))
3575 (clobber (match_scratch:DI 0 "=d,d"))]
3576 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3580 [(set_attr "op_type" "RRE,RXY")])
3582 (define_insn "*subdi3_cconly2"
3583 [(set (reg CC_REGNUM)
3584 (compare (match_operand:DI 1 "register_operand" "0,0")
3585 (match_operand:DI 2 "general_operand" "d,m")))
3586 (clobber (match_scratch:DI 0 "=d,d"))]
3587 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3591 [(set_attr "op_type" "RRE,RXY")])
3593 (define_insn "*subdi3_64"
3594 [(set (match_operand:DI 0 "register_operand" "=d,d")
3595 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3596 (match_operand:DI 2 "general_operand" "d,m") ) )
3597 (clobber (reg:CC CC_REGNUM))]
3602 [(set_attr "op_type" "RRE,RRE")])
3604 (define_insn_and_split "*subdi3_31z"
3605 [(set (match_operand:DI 0 "register_operand" "=&d")
3606 (minus:DI (match_operand:DI 1 "register_operand" "0")
3607 (match_operand:DI 2 "general_operand" "do") ) )
3608 (clobber (reg:CC CC_REGNUM))]
3609 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3611 "&& reload_completed"
3613 [(set (reg:CCL2 CC_REGNUM)
3614 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3616 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3618 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3619 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3620 (clobber (reg:CC CC_REGNUM))])]
3621 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3622 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3623 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3624 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3625 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3626 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3628 (define_insn_and_split "*subdi3_31"
3629 [(set (match_operand:DI 0 "register_operand" "=&d")
3630 (minus:DI (match_operand:DI 1 "register_operand" "0")
3631 (match_operand:DI 2 "general_operand" "do") ) )
3632 (clobber (reg:CC CC_REGNUM))]
3635 "&& reload_completed"
3637 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3638 (clobber (reg:CC CC_REGNUM))])
3640 [(set (reg:CCL2 CC_REGNUM)
3641 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3643 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3645 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3647 (label_ref (match_dup 9))))
3649 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3650 (clobber (reg:CC CC_REGNUM))])
3652 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3653 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3654 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3655 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3656 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3657 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3658 operands[9] = gen_label_rtx ();")
3660 (define_expand "subdi3"
3662 [(set (match_operand:DI 0 "register_operand" "")
3663 (minus:DI (match_operand:DI 1 "register_operand" "")
3664 (match_operand:DI 2 "general_operand" "")))
3665 (clobber (reg:CC CC_REGNUM))])]
3670 ; subsi3 instruction pattern(s).
3673 (define_insn "*subsi3_borrow_cc"
3674 [(set (reg CC_REGNUM)
3675 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3676 (match_operand:SI 2 "general_operand" "d,R,T"))
3678 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3679 (minus:SI (match_dup 1) (match_dup 2)))]
3680 "s390_match_ccmode (insn, CCL2mode)"
3685 [(set_attr "op_type" "RR,RX,RXY")])
3687 (define_insn "*subsi3_borrow_cconly"
3688 [(set (reg CC_REGNUM)
3689 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3690 (match_operand:SI 2 "general_operand" "d,R,T"))
3692 (clobber (match_scratch:SI 0 "=d,d,d"))]
3693 "s390_match_ccmode (insn, CCL2mode)"
3698 [(set_attr "op_type" "RR,RX,RXY")])
3700 (define_insn "*subsi3_cc"
3701 [(set (reg CC_REGNUM)
3702 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3703 (match_operand:SI 2 "general_operand" "d,R,T"))
3705 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3706 (minus:SI (match_dup 1) (match_dup 2)))]
3707 "s390_match_ccmode (insn, CCLmode)"
3712 [(set_attr "op_type" "RR,RX,RXY")])
3714 (define_insn "*subsi3_cc2"
3715 [(set (reg CC_REGNUM)
3716 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3717 (match_operand:SI 2 "general_operand" "d,R,T")))
3718 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3719 (minus:SI (match_dup 1) (match_dup 2)))]
3720 "s390_match_ccmode (insn, CCL3mode)"
3725 [(set_attr "op_type" "RR,RX,RXY")])
3727 (define_insn "*subsi3_cconly"
3728 [(set (reg CC_REGNUM)
3729 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3730 (match_operand:SI 2 "general_operand" "d,R,T"))
3732 (clobber (match_scratch:SI 0 "=d,d,d"))]
3733 "s390_match_ccmode (insn, CCLmode)"
3738 [(set_attr "op_type" "RR,RX,RXY")])
3740 (define_insn "*subsi3_cconly2"
3741 [(set (reg CC_REGNUM)
3742 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3743 (match_operand:SI 2 "general_operand" "d,R,T")))
3744 (clobber (match_scratch:SI 0 "=d,d,d"))]
3745 "s390_match_ccmode (insn, CCL3mode)"
3750 [(set_attr "op_type" "RR,RX,RXY")])
3752 (define_insn "*subsi3_sign"
3753 [(set (match_operand:SI 0 "register_operand" "=d,d")
3754 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3755 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3756 (clobber (reg:CC CC_REGNUM))]
3761 [(set_attr "op_type" "RX,RXY")])
3763 (define_insn "subsi3"
3764 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3765 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3766 (match_operand:SI 2 "general_operand" "d,R,T")))
3767 (clobber (reg:CC CC_REGNUM))]
3773 [(set_attr "op_type" "RR,RX,RXY")])
3777 ; sub(df|sf)3 instruction pattern(s).
3780 (define_expand "sub<mode>3"
3782 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3783 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3784 (match_operand:FPR 2 "general_operand" "f,R")))
3785 (clobber (reg:CC CC_REGNUM))])]
3789 (define_insn "*sub<mode>3"
3790 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3791 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3792 (match_operand:FPR 2 "general_operand" "f,R")))
3793 (clobber (reg:CC CC_REGNUM))]
3794 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3798 [(set_attr "op_type" "RRE,RXE")
3799 (set_attr "type" "fsimp<mode>")])
3801 (define_insn "*sub<mode>3_cc"
3802 [(set (reg CC_REGNUM)
3803 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3804 (match_operand:FPR 2 "general_operand" "f,R"))
3805 (match_operand:FPR 3 "const0_operand" "")))
3806 (set (match_operand:FPR 0 "register_operand" "=f,f")
3807 (minus:FPR (match_dup 1) (match_dup 2)))]
3808 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3812 [(set_attr "op_type" "RRE,RXE")
3813 (set_attr "type" "fsimp<mode>")])
3815 (define_insn "*sub<mode>3_cconly"
3816 [(set (reg CC_REGNUM)
3817 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
3818 (match_operand:FPR 2 "general_operand" "f,R"))
3819 (match_operand:FPR 3 "const0_operand" "")))
3820 (clobber (match_scratch:FPR 0 "=f,f"))]
3821 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3825 [(set_attr "op_type" "RRE,RXE")
3826 (set_attr "type" "fsimp<mode>")])
3828 (define_insn "*sub<mode>3_ibm"
3829 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3830 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
3831 (match_operand:FPR 2 "general_operand" "f,R")))
3832 (clobber (reg:CC CC_REGNUM))]
3833 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3837 [(set_attr "op_type" "RR,RX")
3838 (set_attr "type" "fsimp<mode>")])
3842 ;;- Conditional add/subtract instructions.
3846 ; add(di|si)cc instruction pattern(s).
3849 (define_insn "*add<mode>3_alc_cc"
3850 [(set (reg CC_REGNUM)
3852 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3853 (match_operand:GPR 2 "general_operand" "d,m"))
3854 (match_operand:GPR 3 "s390_alc_comparison" ""))
3856 (set (match_operand:GPR 0 "register_operand" "=d,d")
3857 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3858 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3862 [(set_attr "op_type" "RRE,RXY")])
3864 (define_insn "*add<mode>3_alc"
3865 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3866 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
3867 (match_operand:GPR 2 "general_operand" "d,m"))
3868 (match_operand:GPR 3 "s390_alc_comparison" "")))
3869 (clobber (reg:CC CC_REGNUM))]
3874 [(set_attr "op_type" "RRE,RXY")])
3876 (define_insn "*sub<mode>3_slb_cc"
3877 [(set (reg CC_REGNUM)
3879 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3880 (match_operand:GPR 2 "general_operand" "d,m"))
3881 (match_operand:GPR 3 "s390_slb_comparison" ""))
3883 (set (match_operand:GPR 0 "register_operand" "=d,d")
3884 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
3885 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
3889 [(set_attr "op_type" "RRE,RXY")])
3891 (define_insn "*sub<mode>3_slb"
3892 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3893 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3894 (match_operand:GPR 2 "general_operand" "d,m"))
3895 (match_operand:GPR 3 "s390_slb_comparison" "")))
3896 (clobber (reg:CC CC_REGNUM))]
3901 [(set_attr "op_type" "RRE,RXY")])
3903 (define_expand "add<mode>cc"
3904 [(match_operand:GPR 0 "register_operand" "")
3905 (match_operand 1 "comparison_operator" "")
3906 (match_operand:GPR 2 "register_operand" "")
3907 (match_operand:GPR 3 "const_int_operand" "")]
3909 "if (!s390_expand_addcc (GET_CODE (operands[1]),
3910 s390_compare_op0, s390_compare_op1,
3911 operands[0], operands[2],
3912 operands[3])) FAIL; DONE;")
3915 ; scond instruction pattern(s).
3918 (define_insn_and_split "*scond<mode>"
3919 [(set (match_operand:GPR 0 "register_operand" "=&d")
3920 (match_operand:GPR 1 "s390_alc_comparison" ""))
3921 (clobber (reg:CC CC_REGNUM))]
3924 "&& reload_completed"
3925 [(set (match_dup 0) (const_int 0))
3927 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
3929 (clobber (reg:CC CC_REGNUM))])]
3932 (define_insn_and_split "*scond<mode>_neg"
3933 [(set (match_operand:GPR 0 "register_operand" "=&d")
3934 (match_operand:GPR 1 "s390_slb_comparison" ""))
3935 (clobber (reg:CC CC_REGNUM))]
3938 "&& reload_completed"
3939 [(set (match_dup 0) (const_int 0))
3941 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
3943 (clobber (reg:CC CC_REGNUM))])
3945 [(set (match_dup 0) (neg:GPR (match_dup 0)))
3946 (clobber (reg:CC CC_REGNUM))])]
3950 (define_expand "s<code>"
3951 [(set (match_operand:SI 0 "register_operand" "")
3952 (SCOND (match_dup 0)
3955 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
3956 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
3960 ;;- Multiply instructions.
3964 ; muldi3 instruction pattern(s).
3967 (define_insn "*muldi3_sign"
3968 [(set (match_operand:DI 0 "register_operand" "=d,d")
3969 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3970 (match_operand:DI 1 "register_operand" "0,0")))]
3975 [(set_attr "op_type" "RRE,RXY")
3976 (set_attr "type" "imuldi")])
3978 (define_insn "muldi3"
3979 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3980 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3981 (match_operand:DI 2 "general_operand" "d,K,m")))]
3987 [(set_attr "op_type" "RRE,RI,RXY")
3988 (set_attr "type" "imuldi")])
3991 ; mulsi3 instruction pattern(s).
3994 (define_insn "*mulsi3_sign"
3995 [(set (match_operand:SI 0 "register_operand" "=d")
3996 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
3997 (match_operand:SI 1 "register_operand" "0")))]
4000 [(set_attr "op_type" "RX")
4001 (set_attr "type" "imulhi")])
4003 (define_insn "mulsi3"
4004 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4005 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4006 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4013 [(set_attr "op_type" "RRE,RI,RX,RXY")
4014 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4017 ; mulsidi3 instruction pattern(s).
4020 (define_insn "mulsidi3"
4021 [(set (match_operand:DI 0 "register_operand" "=d,d")
4022 (mult:DI (sign_extend:DI
4023 (match_operand:SI 1 "register_operand" "%0,0"))
4025 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4030 [(set_attr "op_type" "RR,RX")
4031 (set_attr "type" "imulsi")])
4034 ; umulsidi3 instruction pattern(s).
4037 (define_insn "umulsidi3"
4038 [(set (match_operand:DI 0 "register_operand" "=d,d")
4039 (mult:DI (zero_extend:DI
4040 (match_operand:SI 1 "register_operand" "%0,0"))
4042 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4043 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4047 [(set_attr "op_type" "RRE,RXY")
4048 (set_attr "type" "imulsi")])
4051 ; mul(df|sf)3 instruction pattern(s).
4054 (define_expand "mul<mode>3"
4055 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4056 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4057 (match_operand:FPR 2 "general_operand" "f,R")))]
4061 (define_insn "*mul<mode>3"
4062 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4063 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4064 (match_operand:FPR 2 "general_operand" "f,R")))]
4065 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4069 [(set_attr "op_type" "RRE,RXE")
4070 (set_attr "type" "fmul<mode>")])
4072 (define_insn "*mul<mode>3_ibm"
4073 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4074 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4075 (match_operand:FPR 2 "general_operand" "f,R")))]
4076 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4080 [(set_attr "op_type" "RR,RX")
4081 (set_attr "type" "fmul<mode>")])
4083 (define_insn "*fmadd<mode>"
4084 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4085 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4086 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4087 (match_operand:FPR 3 "register_operand" "0,0")))]
4088 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4092 [(set_attr "op_type" "RRE,RXE")
4093 (set_attr "type" "fmul<mode>")])
4095 (define_insn "*fmsub<mode>"
4096 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4097 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4098 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4099 (match_operand:FPR 3 "register_operand" "0,0")))]
4100 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4104 [(set_attr "op_type" "RRE,RXE")
4105 (set_attr "type" "fmul<mode>")])
4108 ;;- Divide and modulo instructions.
4112 ; divmoddi4 instruction pattern(s).
4115 (define_expand "divmoddi4"
4116 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4117 (div:DI (match_operand:DI 1 "register_operand" "")
4118 (match_operand:DI 2 "general_operand" "")))
4119 (set (match_operand:DI 3 "general_operand" "")
4120 (mod:DI (match_dup 1) (match_dup 2)))])
4121 (clobber (match_dup 4))]
4124 rtx insn, div_equal, mod_equal;
4126 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4127 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4129 operands[4] = gen_reg_rtx(TImode);
4130 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4132 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4134 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4136 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4138 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4143 (define_insn "divmodtidi3"
4144 [(set (match_operand:TI 0 "register_operand" "=d,d")
4148 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4149 (match_operand:DI 2 "general_operand" "d,m")))
4151 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4156 [(set_attr "op_type" "RRE,RXY")
4157 (set_attr "type" "idiv")])
4159 (define_insn "divmodtisi3"
4160 [(set (match_operand:TI 0 "register_operand" "=d,d")
4164 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4166 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4169 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4174 [(set_attr "op_type" "RRE,RXY")
4175 (set_attr "type" "idiv")])
4178 ; udivmoddi4 instruction pattern(s).
4181 (define_expand "udivmoddi4"
4182 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4183 (udiv:DI (match_operand:DI 1 "general_operand" "")
4184 (match_operand:DI 2 "nonimmediate_operand" "")))
4185 (set (match_operand:DI 3 "general_operand" "")
4186 (umod:DI (match_dup 1) (match_dup 2)))])
4187 (clobber (match_dup 4))]
4190 rtx insn, div_equal, mod_equal, equal;
4192 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4193 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4194 equal = gen_rtx_IOR (TImode,
4195 gen_rtx_ASHIFT (TImode,
4196 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4198 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4200 operands[4] = gen_reg_rtx(TImode);
4201 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4202 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4203 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4204 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4206 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4208 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4210 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4212 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4214 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4219 (define_insn "udivmodtidi3"
4220 [(set (match_operand:TI 0 "register_operand" "=d,d")
4225 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4227 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4231 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4236 [(set_attr "op_type" "RRE,RXY")
4237 (set_attr "type" "idiv")])
4240 ; divmodsi4 instruction pattern(s).
4243 (define_expand "divmodsi4"
4244 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4245 (div:SI (match_operand:SI 1 "general_operand" "")
4246 (match_operand:SI 2 "nonimmediate_operand" "")))
4247 (set (match_operand:SI 3 "general_operand" "")
4248 (mod:SI (match_dup 1) (match_dup 2)))])
4249 (clobber (match_dup 4))]
4252 rtx insn, div_equal, mod_equal, equal;
4254 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4255 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4256 equal = gen_rtx_IOR (DImode,
4257 gen_rtx_ASHIFT (DImode,
4258 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4260 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4262 operands[4] = gen_reg_rtx(DImode);
4263 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4264 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4266 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4268 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4270 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4272 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4274 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4279 (define_insn "divmoddisi3"
4280 [(set (match_operand:DI 0 "register_operand" "=d,d")
4285 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4287 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4291 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4296 [(set_attr "op_type" "RR,RX")
4297 (set_attr "type" "idiv")])
4300 ; udivsi3 and umodsi3 instruction pattern(s).
4303 (define_expand "udivmodsi4"
4304 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4305 (udiv:SI (match_operand:SI 1 "general_operand" "")
4306 (match_operand:SI 2 "nonimmediate_operand" "")))
4307 (set (match_operand:SI 3 "general_operand" "")
4308 (umod:SI (match_dup 1) (match_dup 2)))])
4309 (clobber (match_dup 4))]
4310 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4312 rtx insn, div_equal, mod_equal, equal;
4314 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4315 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4316 equal = gen_rtx_IOR (DImode,
4317 gen_rtx_ASHIFT (DImode,
4318 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4320 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4322 operands[4] = gen_reg_rtx(DImode);
4323 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4324 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4325 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4326 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4328 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4330 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4332 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4334 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4336 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4341 (define_insn "udivmoddisi3"
4342 [(set (match_operand:DI 0 "register_operand" "=d,d")
4347 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4349 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4353 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4354 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4358 [(set_attr "op_type" "RRE,RXY")
4359 (set_attr "type" "idiv")])
4361 (define_expand "udivsi3"
4362 [(set (match_operand:SI 0 "register_operand" "=d")
4363 (udiv:SI (match_operand:SI 1 "general_operand" "")
4364 (match_operand:SI 2 "general_operand" "")))
4365 (clobber (match_dup 3))]
4366 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4368 rtx insn, udiv_equal, umod_equal, equal;
4370 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4371 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4372 equal = gen_rtx_IOR (DImode,
4373 gen_rtx_ASHIFT (DImode,
4374 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4376 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4378 operands[3] = gen_reg_rtx (DImode);
4380 if (CONSTANT_P (operands[2]))
4382 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4384 rtx label1 = gen_label_rtx ();
4386 operands[1] = make_safe_from (operands[1], operands[0]);
4387 emit_move_insn (operands[0], const0_rtx);
4388 emit_insn (gen_cmpsi (operands[1], operands[2]));
4389 emit_jump_insn (gen_bltu (label1));
4390 emit_move_insn (operands[0], const1_rtx);
4391 emit_label (label1);
4395 operands[2] = force_reg (SImode, operands[2]);
4396 operands[2] = make_safe_from (operands[2], operands[0]);
4398 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4399 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4402 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4404 insn = emit_move_insn (operands[0],
4405 gen_lowpart (SImode, operands[3]));
4407 gen_rtx_EXPR_LIST (REG_EQUAL,
4408 udiv_equal, REG_NOTES (insn));
4413 rtx label1 = gen_label_rtx ();
4414 rtx label2 = gen_label_rtx ();
4415 rtx label3 = gen_label_rtx ();
4417 operands[1] = force_reg (SImode, operands[1]);
4418 operands[1] = make_safe_from (operands[1], operands[0]);
4419 operands[2] = force_reg (SImode, operands[2]);
4420 operands[2] = make_safe_from (operands[2], operands[0]);
4422 emit_move_insn (operands[0], const0_rtx);
4423 emit_insn (gen_cmpsi (operands[2], operands[1]));
4424 emit_jump_insn (gen_bgtu (label3));
4425 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4426 emit_jump_insn (gen_blt (label2));
4427 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4428 emit_jump_insn (gen_beq (label1));
4429 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4430 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4433 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4435 insn = emit_move_insn (operands[0],
4436 gen_lowpart (SImode, operands[3]));
4438 gen_rtx_EXPR_LIST (REG_EQUAL,
4439 udiv_equal, REG_NOTES (insn));
4441 emit_label (label1);
4442 emit_move_insn (operands[0], operands[1]);
4444 emit_label (label2);
4445 emit_move_insn (operands[0], const1_rtx);
4446 emit_label (label3);
4448 emit_move_insn (operands[0], operands[0]);
4452 (define_expand "umodsi3"
4453 [(set (match_operand:SI 0 "register_operand" "=d")
4454 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4455 (match_operand:SI 2 "nonimmediate_operand" "")))
4456 (clobber (match_dup 3))]
4457 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4459 rtx insn, udiv_equal, umod_equal, equal;
4461 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4462 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4463 equal = gen_rtx_IOR (DImode,
4464 gen_rtx_ASHIFT (DImode,
4465 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4467 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4469 operands[3] = gen_reg_rtx (DImode);
4471 if (CONSTANT_P (operands[2]))
4473 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4475 rtx label1 = gen_label_rtx ();
4477 operands[1] = make_safe_from (operands[1], operands[0]);
4478 emit_move_insn (operands[0], operands[1]);
4479 emit_insn (gen_cmpsi (operands[0], operands[2]));
4480 emit_jump_insn (gen_bltu (label1));
4481 emit_insn (gen_abssi2 (operands[0], operands[2]));
4482 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4483 emit_label (label1);
4487 operands[2] = force_reg (SImode, operands[2]);
4488 operands[2] = make_safe_from (operands[2], operands[0]);
4490 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4491 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4494 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4496 insn = emit_move_insn (operands[0],
4497 gen_highpart (SImode, operands[3]));
4499 gen_rtx_EXPR_LIST (REG_EQUAL,
4500 umod_equal, REG_NOTES (insn));
4505 rtx label1 = gen_label_rtx ();
4506 rtx label2 = gen_label_rtx ();
4507 rtx label3 = gen_label_rtx ();
4509 operands[1] = force_reg (SImode, operands[1]);
4510 operands[1] = make_safe_from (operands[1], operands[0]);
4511 operands[2] = force_reg (SImode, operands[2]);
4512 operands[2] = make_safe_from (operands[2], operands[0]);
4514 emit_move_insn(operands[0], operands[1]);
4515 emit_insn (gen_cmpsi (operands[2], operands[1]));
4516 emit_jump_insn (gen_bgtu (label3));
4517 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4518 emit_jump_insn (gen_blt (label2));
4519 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4520 emit_jump_insn (gen_beq (label1));
4521 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4522 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4525 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4527 insn = emit_move_insn (operands[0],
4528 gen_highpart (SImode, operands[3]));
4530 gen_rtx_EXPR_LIST (REG_EQUAL,
4531 umod_equal, REG_NOTES (insn));
4533 emit_label (label1);
4534 emit_move_insn (operands[0], const0_rtx);
4536 emit_label (label2);
4537 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4538 emit_label (label3);
4544 ; div(df|sf)3 instruction pattern(s).
4547 (define_expand "div<mode>3"
4548 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4549 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4550 (match_operand:FPR 2 "general_operand" "f,R")))]
4554 (define_insn "*div<mode>3"
4555 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4556 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4557 (match_operand:FPR 2 "general_operand" "f,R")))]
4558 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4562 [(set_attr "op_type" "RRE,RXE")
4563 (set_attr "type" "fdiv<mode>")])
4565 (define_insn "*div<mode>3_ibm"
4566 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4567 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4568 (match_operand:FPR 2 "general_operand" "f,R")))]
4569 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4573 [(set_attr "op_type" "RR,RX")
4574 (set_attr "type" "fdiv<mode>")])
4578 ;;- And instructions.
4581 (define_expand "and<mode>3"
4582 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4583 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4584 (match_operand:INT 2 "general_operand" "")))
4585 (clobber (reg:CC CC_REGNUM))]
4587 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4590 ; anddi3 instruction pattern(s).
4593 (define_insn "*anddi3_cc"
4594 [(set (reg CC_REGNUM)
4595 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4596 (match_operand:DI 2 "general_operand" "d,m"))
4598 (set (match_operand:DI 0 "register_operand" "=d,d")
4599 (and:DI (match_dup 1) (match_dup 2)))]
4600 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4604 [(set_attr "op_type" "RRE,RXY")])
4606 (define_insn "*anddi3_cconly"
4607 [(set (reg CC_REGNUM)
4608 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4609 (match_operand:DI 2 "general_operand" "d,m"))
4611 (clobber (match_scratch:DI 0 "=d,d"))]
4612 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4613 /* Do not steal TM patterns. */
4614 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4618 [(set_attr "op_type" "RRE,RXY")])
4620 (define_insn "*anddi3"
4621 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4622 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4623 "%d,o,0,0,0,0,0,0,0,0")
4624 (match_operand:DI 2 "general_operand"
4625 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4626 (clobber (reg:CC CC_REGNUM))]
4627 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4639 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4642 [(set (match_operand:DI 0 "s_operand" "")
4643 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4644 (clobber (reg:CC CC_REGNUM))]
4647 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4648 (clobber (reg:CC CC_REGNUM))])]
4649 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4653 ; andsi3 instruction pattern(s).
4656 (define_insn "*andsi3_cc"
4657 [(set (reg CC_REGNUM)
4658 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4659 (match_operand:SI 2 "general_operand" "d,R,T"))
4661 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4662 (and:SI (match_dup 1) (match_dup 2)))]
4663 "s390_match_ccmode(insn, CCTmode)"
4668 [(set_attr "op_type" "RR,RX,RXY")])
4670 (define_insn "*andsi3_cconly"
4671 [(set (reg CC_REGNUM)
4672 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4673 (match_operand:SI 2 "general_operand" "d,R,T"))
4675 (clobber (match_scratch:SI 0 "=d,d,d"))]
4676 "s390_match_ccmode(insn, CCTmode)
4677 /* Do not steal TM patterns. */
4678 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4683 [(set_attr "op_type" "RR,RX,RXY")])
4685 (define_insn "*andsi3_zarch"
4686 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
4687 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4688 "%d,o,0,0,0,0,0,0,0")
4689 (match_operand:SI 2 "general_operand"
4690 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
4691 (clobber (reg:CC CC_REGNUM))]
4692 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4703 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
4705 (define_insn "*andsi3_esa"
4706 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4707 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4708 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4709 (clobber (reg:CC CC_REGNUM))]
4710 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4716 [(set_attr "op_type" "RR,RX,SI,SS")])
4719 [(set (match_operand:SI 0 "s_operand" "")
4720 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4721 (clobber (reg:CC CC_REGNUM))]
4724 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4725 (clobber (reg:CC CC_REGNUM))])]
4726 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4729 ; andhi3 instruction pattern(s).
4732 (define_insn "*andhi3_zarch"
4733 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4734 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
4735 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
4736 (clobber (reg:CC CC_REGNUM))]
4737 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4743 [(set_attr "op_type" "RR,RI,SI,SS")])
4745 (define_insn "*andhi3_esa"
4746 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
4747 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
4748 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
4749 (clobber (reg:CC CC_REGNUM))]
4750 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4755 [(set_attr "op_type" "RR,SI,SS")])
4758 [(set (match_operand:HI 0 "s_operand" "")
4759 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
4760 (clobber (reg:CC CC_REGNUM))]
4763 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4764 (clobber (reg:CC CC_REGNUM))])]
4765 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4768 ; andqi3 instruction pattern(s).
4771 (define_insn "*andqi3_zarch"
4772 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
4773 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
4774 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
4775 (clobber (reg:CC CC_REGNUM))]
4776 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4783 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
4785 (define_insn "*andqi3_esa"
4786 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
4787 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
4788 (match_operand:QI 2 "general_operand" "d,n,Q")))
4789 (clobber (reg:CC CC_REGNUM))]
4790 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4795 [(set_attr "op_type" "RR,SI,SS")])
4798 ; Block and (NC) patterns.
4802 [(set (match_operand:BLK 0 "memory_operand" "=Q")
4803 (and:BLK (match_dup 0)
4804 (match_operand:BLK 1 "memory_operand" "Q")))
4805 (use (match_operand 2 "const_int_operand" "n"))
4806 (clobber (reg:CC CC_REGNUM))]
4807 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
4808 "nc\t%O0(%2,%R0),%S1"
4809 [(set_attr "op_type" "SS")])
4812 [(set (match_operand 0 "memory_operand" "")
4814 (match_operand 1 "memory_operand" "")))
4815 (clobber (reg:CC CC_REGNUM))]
4817 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4818 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
4820 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
4822 (clobber (reg:CC CC_REGNUM))])]
4824 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
4825 operands[0] = adjust_address (operands[0], BLKmode, 0);
4826 operands[1] = adjust_address (operands[1], BLKmode, 0);
4831 [(set (match_operand:BLK 0 "memory_operand" "")
4832 (and:BLK (match_dup 0)
4833 (match_operand:BLK 1 "memory_operand" "")))
4834 (use (match_operand 2 "const_int_operand" ""))
4835 (clobber (reg:CC CC_REGNUM))])
4837 [(set (match_operand:BLK 3 "memory_operand" "")
4838 (and:BLK (match_dup 3)
4839 (match_operand:BLK 4 "memory_operand" "")))
4840 (use (match_operand 5 "const_int_operand" ""))
4841 (clobber (reg:CC CC_REGNUM))])]
4842 "s390_offset_p (operands[0], operands[3], operands[2])
4843 && s390_offset_p (operands[1], operands[4], operands[2])
4844 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
4846 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
4848 (clobber (reg:CC CC_REGNUM))])]
4849 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
4850 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
4851 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
4855 ;;- Bit set (inclusive or) instructions.
4858 (define_expand "ior<mode>3"
4859 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4860 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
4861 (match_operand:INT 2 "general_operand" "")))
4862 (clobber (reg:CC CC_REGNUM))]
4864 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
4867 ; iordi3 instruction pattern(s).
4870 (define_insn "*iordi3_cc"
4871 [(set (reg CC_REGNUM)
4872 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4873 (match_operand:DI 2 "general_operand" "d,m"))
4875 (set (match_operand:DI 0 "register_operand" "=d,d")
4876 (ior:DI (match_dup 1) (match_dup 2)))]
4877 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4881 [(set_attr "op_type" "RRE,RXY")])
4883 (define_insn "*iordi3_cconly"
4884 [(set (reg CC_REGNUM)
4885 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4886 (match_operand:DI 2 "general_operand" "d,m"))
4888 (clobber (match_scratch:DI 0 "=d,d"))]
4889 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4893 [(set_attr "op_type" "RRE,RXY")])
4895 (define_insn "*iordi3"
4896 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
4897 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
4898 (match_operand:DI 2 "general_operand"
4899 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
4900 (clobber (reg:CC CC_REGNUM))]
4901 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
4911 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
4914 [(set (match_operand:DI 0 "s_operand" "")
4915 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4916 (clobber (reg:CC CC_REGNUM))]
4919 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4920 (clobber (reg:CC CC_REGNUM))])]
4921 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4924 ; iorsi3 instruction pattern(s).
4927 (define_insn "*iorsi3_cc"
4928 [(set (reg CC_REGNUM)
4929 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4930 (match_operand:SI 2 "general_operand" "d,R,T"))
4932 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4933 (ior:SI (match_dup 1) (match_dup 2)))]
4934 "s390_match_ccmode(insn, CCTmode)"
4939 [(set_attr "op_type" "RR,RX,RXY")])
4941 (define_insn "*iorsi3_cconly"
4942 [(set (reg CC_REGNUM)
4943 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
4944 (match_operand:SI 2 "general_operand" "d,R,T"))
4946 (clobber (match_scratch:SI 0 "=d,d,d"))]
4947 "s390_match_ccmode(insn, CCTmode)"
4952 [(set_attr "op_type" "RR,RX,RXY")])
4954 (define_insn "*iorsi3_zarch"
4955 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
4956 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4957 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
4958 (clobber (reg:CC CC_REGNUM))]
4959 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4968 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
4970 (define_insn "*iorsi3_esa"
4971 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4972 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4973 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
4974 (clobber (reg:CC CC_REGNUM))]
4975 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4981 [(set_attr "op_type" "RR,RX,SI,SS")])
4984 [(set (match_operand:SI 0 "s_operand" "")
4985 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
4986 (clobber (reg:CC CC_REGNUM))]
4989 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
4990 (clobber (reg:CC CC_REGNUM))])]
4991 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
4994 ; iorhi3 instruction pattern(s).
4997 (define_insn "*iorhi3_zarch"
4998 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4999 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5000 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5001 (clobber (reg:CC CC_REGNUM))]
5002 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5008 [(set_attr "op_type" "RR,RI,SI,SS")])
5010 (define_insn "*iorhi3_esa"
5011 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5012 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5013 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5014 (clobber (reg:CC CC_REGNUM))]
5015 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5020 [(set_attr "op_type" "RR,SI,SS")])
5023 [(set (match_operand:HI 0 "s_operand" "")
5024 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5025 (clobber (reg:CC CC_REGNUM))]
5028 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5029 (clobber (reg:CC CC_REGNUM))])]
5030 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5033 ; iorqi3 instruction pattern(s).
5036 (define_insn "*iorqi3_zarch"
5037 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5038 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5039 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5040 (clobber (reg:CC CC_REGNUM))]
5041 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5048 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5050 (define_insn "*iorqi3_esa"
5051 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5052 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5053 (match_operand:QI 2 "general_operand" "d,n,Q")))
5054 (clobber (reg:CC CC_REGNUM))]
5055 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5060 [(set_attr "op_type" "RR,SI,SS")])
5063 ; Block inclusive or (OC) patterns.
5067 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5068 (ior:BLK (match_dup 0)
5069 (match_operand:BLK 1 "memory_operand" "Q")))
5070 (use (match_operand 2 "const_int_operand" "n"))
5071 (clobber (reg:CC CC_REGNUM))]
5072 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5073 "oc\t%O0(%2,%R0),%S1"
5074 [(set_attr "op_type" "SS")])
5077 [(set (match_operand 0 "memory_operand" "")
5079 (match_operand 1 "memory_operand" "")))
5080 (clobber (reg:CC CC_REGNUM))]
5082 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5083 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5085 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5087 (clobber (reg:CC CC_REGNUM))])]
5089 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5090 operands[0] = adjust_address (operands[0], BLKmode, 0);
5091 operands[1] = adjust_address (operands[1], BLKmode, 0);
5096 [(set (match_operand:BLK 0 "memory_operand" "")
5097 (ior:BLK (match_dup 0)
5098 (match_operand:BLK 1 "memory_operand" "")))
5099 (use (match_operand 2 "const_int_operand" ""))
5100 (clobber (reg:CC CC_REGNUM))])
5102 [(set (match_operand:BLK 3 "memory_operand" "")
5103 (ior:BLK (match_dup 3)
5104 (match_operand:BLK 4 "memory_operand" "")))
5105 (use (match_operand 5 "const_int_operand" ""))
5106 (clobber (reg:CC CC_REGNUM))])]
5107 "s390_offset_p (operands[0], operands[3], operands[2])
5108 && s390_offset_p (operands[1], operands[4], operands[2])
5109 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5111 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5113 (clobber (reg:CC CC_REGNUM))])]
5114 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5115 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5116 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5120 ;;- Xor instructions.
5123 (define_expand "xor<mode>3"
5124 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5125 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5126 (match_operand:INT 2 "general_operand" "")))
5127 (clobber (reg:CC CC_REGNUM))]
5129 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5132 ; xordi3 instruction pattern(s).
5135 (define_insn "*xordi3_cc"
5136 [(set (reg CC_REGNUM)
5137 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5138 (match_operand:DI 2 "general_operand" "d,m"))
5140 (set (match_operand:DI 0 "register_operand" "=d,d")
5141 (xor:DI (match_dup 1) (match_dup 2)))]
5142 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5146 [(set_attr "op_type" "RRE,RXY")])
5148 (define_insn "*xordi3_cconly"
5149 [(set (reg CC_REGNUM)
5150 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5151 (match_operand:DI 2 "general_operand" "d,m"))
5153 (clobber (match_scratch:DI 0 "=d,d"))]
5154 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5158 [(set_attr "op_type" "RRE,RXY")])
5160 (define_insn "*xordi3"
5161 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5162 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5163 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5164 (clobber (reg:CC CC_REGNUM))]
5165 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5171 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5174 [(set (match_operand:DI 0 "s_operand" "")
5175 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5176 (clobber (reg:CC CC_REGNUM))]
5179 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5180 (clobber (reg:CC CC_REGNUM))])]
5181 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5184 ; xorsi3 instruction pattern(s).
5187 (define_insn "*xorsi3_cc"
5188 [(set (reg CC_REGNUM)
5189 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5190 (match_operand:SI 2 "general_operand" "d,R,T"))
5192 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5193 (xor:SI (match_dup 1) (match_dup 2)))]
5194 "s390_match_ccmode(insn, CCTmode)"
5199 [(set_attr "op_type" "RR,RX,RXY")])
5201 (define_insn "*xorsi3_cconly"
5202 [(set (reg CC_REGNUM)
5203 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5204 (match_operand:SI 2 "general_operand" "d,R,T"))
5206 (clobber (match_scratch:SI 0 "=d,d,d"))]
5207 "s390_match_ccmode(insn, CCTmode)"
5212 [(set_attr "op_type" "RR,RX,RXY")])
5214 (define_insn "*xorsi3"
5215 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5216 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5217 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5218 (clobber (reg:CC CC_REGNUM))]
5219 "s390_logical_operator_ok_p (operands)"
5226 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5229 [(set (match_operand:SI 0 "s_operand" "")
5230 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5231 (clobber (reg:CC CC_REGNUM))]
5234 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5235 (clobber (reg:CC CC_REGNUM))])]
5236 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5239 ; xorhi3 instruction pattern(s).
5242 (define_insn "*xorhi3"
5243 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5244 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5245 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5246 (clobber (reg:CC CC_REGNUM))]
5247 "s390_logical_operator_ok_p (operands)"
5252 [(set_attr "op_type" "RR,SI,SS")])
5255 [(set (match_operand:HI 0 "s_operand" "")
5256 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5257 (clobber (reg:CC CC_REGNUM))]
5260 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5261 (clobber (reg:CC CC_REGNUM))])]
5262 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5265 ; xorqi3 instruction pattern(s).
5268 (define_insn "*xorqi3"
5269 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5270 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5271 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5272 (clobber (reg:CC CC_REGNUM))]
5273 "s390_logical_operator_ok_p (operands)"
5279 [(set_attr "op_type" "RR,SI,SIY,SS")])
5282 ; Block exclusive or (XC) patterns.
5286 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5287 (xor:BLK (match_dup 0)
5288 (match_operand:BLK 1 "memory_operand" "Q")))
5289 (use (match_operand 2 "const_int_operand" "n"))
5290 (clobber (reg:CC CC_REGNUM))]
5291 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5292 "xc\t%O0(%2,%R0),%S1"
5293 [(set_attr "op_type" "SS")])
5296 [(set (match_operand 0 "memory_operand" "")
5298 (match_operand 1 "memory_operand" "")))
5299 (clobber (reg:CC CC_REGNUM))]
5301 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5302 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5304 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5306 (clobber (reg:CC CC_REGNUM))])]
5308 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5309 operands[0] = adjust_address (operands[0], BLKmode, 0);
5310 operands[1] = adjust_address (operands[1], BLKmode, 0);
5315 [(set (match_operand:BLK 0 "memory_operand" "")
5316 (xor:BLK (match_dup 0)
5317 (match_operand:BLK 1 "memory_operand" "")))
5318 (use (match_operand 2 "const_int_operand" ""))
5319 (clobber (reg:CC CC_REGNUM))])
5321 [(set (match_operand:BLK 3 "memory_operand" "")
5322 (xor:BLK (match_dup 3)
5323 (match_operand:BLK 4 "memory_operand" "")))
5324 (use (match_operand 5 "const_int_operand" ""))
5325 (clobber (reg:CC CC_REGNUM))])]
5326 "s390_offset_p (operands[0], operands[3], operands[2])
5327 && s390_offset_p (operands[1], operands[4], operands[2])
5328 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5330 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5332 (clobber (reg:CC CC_REGNUM))])]
5333 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5334 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5335 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5338 ; Block xor (XC) patterns with src == dest.
5341 (define_insn "*xc_zero"
5342 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5344 (use (match_operand 1 "const_int_operand" "n"))
5345 (clobber (reg:CC CC_REGNUM))]
5346 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5347 "xc\t%O0(%1,%R0),%S0"
5348 [(set_attr "op_type" "SS")])
5352 [(set (match_operand:BLK 0 "memory_operand" "")
5354 (use (match_operand 1 "const_int_operand" ""))
5355 (clobber (reg:CC CC_REGNUM))])
5357 [(set (match_operand:BLK 2 "memory_operand" "")
5359 (use (match_operand 3 "const_int_operand" ""))
5360 (clobber (reg:CC CC_REGNUM))])]
5361 "s390_offset_p (operands[0], operands[2], operands[1])
5362 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5364 [(set (match_dup 4) (const_int 0))
5366 (clobber (reg:CC CC_REGNUM))])]
5367 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5368 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5372 ;;- Negate instructions.
5376 ; neg(di|si)2 instruction pattern(s).
5379 (define_expand "neg<mode>2"
5381 [(set (match_operand:DSI 0 "register_operand" "=d")
5382 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5383 (clobber (reg:CC CC_REGNUM))])]
5387 (define_insn "*negdi2_sign_cc"
5388 [(set (reg CC_REGNUM)
5389 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5390 (match_operand:SI 1 "register_operand" "d") 0)
5391 (const_int 32)) (const_int 32)))
5393 (set (match_operand:DI 0 "register_operand" "=d")
5394 (neg:DI (sign_extend:DI (match_dup 1))))]
5395 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5397 [(set_attr "op_type" "RRE")])
5399 (define_insn "*negdi2_sign"
5400 [(set (match_operand:DI 0 "register_operand" "=d")
5401 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5402 (clobber (reg:CC CC_REGNUM))]
5405 [(set_attr "op_type" "RRE")])
5407 (define_insn "*neg<mode>2_cc"
5408 [(set (reg CC_REGNUM)
5409 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5411 (set (match_operand:GPR 0 "register_operand" "=d")
5412 (neg:GPR (match_dup 1)))]
5413 "s390_match_ccmode (insn, CCAmode)"
5415 [(set_attr "op_type" "RR<E>")])
5417 (define_insn "*neg<mode>2_cconly"
5418 [(set (reg CC_REGNUM)
5419 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5421 (clobber (match_scratch:GPR 0 "=d"))]
5422 "s390_match_ccmode (insn, CCAmode)"
5424 [(set_attr "op_type" "RR<E>")])
5426 (define_insn "*neg<mode>2"
5427 [(set (match_operand:GPR 0 "register_operand" "=d")
5428 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5429 (clobber (reg:CC CC_REGNUM))]
5432 [(set_attr "op_type" "RR<E>")])
5434 (define_insn_and_split "*negdi2_31"
5435 [(set (match_operand:DI 0 "register_operand" "=d")
5436 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5437 (clobber (reg:CC CC_REGNUM))]
5440 "&& reload_completed"
5442 [(set (match_dup 2) (neg:SI (match_dup 3)))
5443 (clobber (reg:CC CC_REGNUM))])
5445 [(set (reg:CCAP CC_REGNUM)
5446 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5447 (set (match_dup 4) (neg:SI (match_dup 5)))])
5449 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5451 (label_ref (match_dup 6))))
5453 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5454 (clobber (reg:CC CC_REGNUM))])
5456 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5457 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5458 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5459 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5460 operands[6] = gen_label_rtx ();")
5463 ; neg(df|sf)2 instruction pattern(s).
5466 (define_expand "neg<mode>2"
5468 [(set (match_operand:FPR 0 "register_operand" "=f")
5469 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5470 (clobber (reg:CC CC_REGNUM))])]
5474 (define_insn "*neg<mode>2_cc"
5475 [(set (reg CC_REGNUM)
5476 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5477 (match_operand:FPR 2 "const0_operand" "")))
5478 (set (match_operand:FPR 0 "register_operand" "=f")
5479 (neg:FPR (match_dup 1)))]
5480 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5482 [(set_attr "op_type" "RRE")
5483 (set_attr "type" "fsimp<mode>")])
5485 (define_insn "*neg<mode>2_cconly"
5486 [(set (reg CC_REGNUM)
5487 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5488 (match_operand:FPR 2 "const0_operand" "")))
5489 (clobber (match_scratch:FPR 0 "=f"))]
5490 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5492 [(set_attr "op_type" "RRE")
5493 (set_attr "type" "fsimp<mode>")])
5495 (define_insn "*neg<mode>2"
5496 [(set (match_operand:FPR 0 "register_operand" "=f")
5497 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5498 (clobber (reg:CC CC_REGNUM))]
5499 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5501 [(set_attr "op_type" "RRE")
5502 (set_attr "type" "fsimp<mode>")])
5504 (define_insn "*neg<mode>2_ibm"
5505 [(set (match_operand:FPR 0 "register_operand" "=f")
5506 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5507 (clobber (reg:CC CC_REGNUM))]
5508 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5510 [(set_attr "op_type" "RR")
5511 (set_attr "type" "fsimp<mode>")])
5515 ;;- Absolute value instructions.
5519 ; abs(di|si)2 instruction pattern(s).
5522 (define_insn "*absdi2_sign_cc"
5523 [(set (reg CC_REGNUM)
5524 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5525 (match_operand:SI 1 "register_operand" "d") 0)
5526 (const_int 32)) (const_int 32)))
5528 (set (match_operand:DI 0 "register_operand" "=d")
5529 (abs:DI (sign_extend:DI (match_dup 1))))]
5530 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5532 [(set_attr "op_type" "RRE")])
5534 (define_insn "*absdi2_sign"
5535 [(set (match_operand:DI 0 "register_operand" "=d")
5536 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5537 (clobber (reg:CC CC_REGNUM))]
5540 [(set_attr "op_type" "RRE")])
5542 (define_insn "*abs<mode>2_cc"
5543 [(set (reg CC_REGNUM)
5544 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5546 (set (match_operand:GPR 0 "register_operand" "=d")
5547 (abs:GPR (match_dup 1)))]
5548 "s390_match_ccmode (insn, CCAmode)"
5550 [(set_attr "op_type" "RR<E>")])
5552 (define_insn "*abs<mode>2_cconly"
5553 [(set (reg CC_REGNUM)
5554 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5556 (clobber (match_scratch:GPR 0 "=d"))]
5557 "s390_match_ccmode (insn, CCAmode)"
5559 [(set_attr "op_type" "RR<E>")])
5561 (define_insn "abs<mode>2"
5562 [(set (match_operand:GPR 0 "register_operand" "=d")
5563 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5564 (clobber (reg:CC CC_REGNUM))]
5567 [(set_attr "op_type" "RR<E>")])
5570 ; abs(df|sf)2 instruction pattern(s).
5573 (define_expand "abs<mode>2"
5575 [(set (match_operand:FPR 0 "register_operand" "=f")
5576 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5577 (clobber (reg:CC CC_REGNUM))])]
5581 (define_insn "*abs<mode>2_cc"
5582 [(set (reg CC_REGNUM)
5583 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5584 (match_operand:FPR 2 "const0_operand" "")))
5585 (set (match_operand:FPR 0 "register_operand" "=f")
5586 (abs:FPR (match_dup 1)))]
5587 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5589 [(set_attr "op_type" "RRE")
5590 (set_attr "type" "fsimp<mode>")])
5592 (define_insn "*abs<mode>2_cconly"
5593 [(set (reg CC_REGNUM)
5594 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5595 (match_operand:FPR 2 "const0_operand" "")))
5596 (clobber (match_scratch:FPR 0 "=f"))]
5597 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5599 [(set_attr "op_type" "RRE")
5600 (set_attr "type" "fsimp<mode>")])
5602 (define_insn "*abs<mode>2"
5603 [(set (match_operand:FPR 0 "register_operand" "=f")
5604 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5605 (clobber (reg:CC CC_REGNUM))]
5606 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5608 [(set_attr "op_type" "RRE")
5609 (set_attr "type" "fsimp<mode>")])
5611 (define_insn "*abs<mode>2_ibm"
5612 [(set (match_operand:FPR 0 "register_operand" "=f")
5613 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5614 (clobber (reg:CC CC_REGNUM))]
5615 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5617 [(set_attr "op_type" "RR")
5618 (set_attr "type" "fsimp<mode>")])
5621 ;;- Negated absolute value instructions
5628 (define_insn "*negabsdi2_sign_cc"
5629 [(set (reg CC_REGNUM)
5630 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5631 (match_operand:SI 1 "register_operand" "d") 0)
5632 (const_int 32)) (const_int 32))))
5634 (set (match_operand:DI 0 "register_operand" "=d")
5635 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5636 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5638 [(set_attr "op_type" "RRE")])
5640 (define_insn "*negabsdi2_sign"
5641 [(set (match_operand:DI 0 "register_operand" "=d")
5642 (neg:DI (abs:DI (sign_extend:DI
5643 (match_operand:SI 1 "register_operand" "d")))))
5644 (clobber (reg:CC CC_REGNUM))]
5647 [(set_attr "op_type" "RRE")])
5649 (define_insn "*negabs<mode>2_cc"
5650 [(set (reg CC_REGNUM)
5651 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5653 (set (match_operand:GPR 0 "register_operand" "=d")
5654 (neg:GPR (abs:GPR (match_dup 1))))]
5655 "s390_match_ccmode (insn, CCAmode)"
5657 [(set_attr "op_type" "RR<E>")])
5659 (define_insn "*negabs<mode>2_cconly"
5660 [(set (reg CC_REGNUM)
5661 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5663 (clobber (match_scratch:GPR 0 "=d"))]
5664 "s390_match_ccmode (insn, CCAmode)"
5666 [(set_attr "op_type" "RR<E>")])
5668 (define_insn "*negabs<mode>2"
5669 [(set (match_operand:GPR 0 "register_operand" "=d")
5670 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
5671 (clobber (reg:CC CC_REGNUM))]
5674 [(set_attr "op_type" "RR<E>")])
5680 (define_insn "*negabs<mode>2_cc"
5681 [(set (reg CC_REGNUM)
5682 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5683 (match_operand:FPR 2 "const0_operand" "")))
5684 (set (match_operand:FPR 0 "register_operand" "=f")
5685 (neg:FPR (abs:FPR (match_dup 1))))]
5686 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5688 [(set_attr "op_type" "RRE")
5689 (set_attr "type" "fsimp<mode>")])
5691 (define_insn "*negabs<mode>2_cconly"
5692 [(set (reg CC_REGNUM)
5693 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5694 (match_operand:FPR 2 "const0_operand" "")))
5695 (clobber (match_scratch:FPR 0 "=f"))]
5696 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5698 [(set_attr "op_type" "RRE")
5699 (set_attr "type" "fsimp<mode>")])
5701 (define_insn "*negabs<mode>2"
5702 [(set (match_operand:FPR 0 "register_operand" "=f")
5703 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
5704 (clobber (reg:CC CC_REGNUM))]
5705 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5707 [(set_attr "op_type" "RRE")
5708 (set_attr "type" "fsimp<mode>")])
5711 ;;- Square root instructions.
5715 ; sqrt(df|sf)2 instruction pattern(s).
5718 (define_insn "sqrt<mode>2"
5719 [(set (match_operand:FPR 0 "register_operand" "=f,f")
5720 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
5721 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5725 [(set_attr "op_type" "RRE,RXE")
5726 (set_attr "type" "fsqrt<mode>")])
5730 ;;- One complement instructions.
5734 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
5737 (define_expand "one_cmpl<mode>2"
5739 [(set (match_operand:INT 0 "register_operand" "")
5740 (xor:INT (match_operand:INT 1 "register_operand" "")
5742 (clobber (reg:CC CC_REGNUM))])]
5748 ;;- Rotate instructions.
5752 ; rotl(di|si)3 instruction pattern(s).
5755 (define_insn "rotl<mode>3"
5756 [(set (match_operand:GPR 0 "register_operand" "=d")
5757 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
5758 (match_operand:SI 2 "shift_count_operand" "Y")))]
5761 [(set_attr "op_type" "RSE")
5762 (set_attr "atype" "reg")])
5766 ;;- Shift instructions.
5770 ; (ashl|lshr)di3 instruction pattern(s).
5773 (define_expand "<shift>di3"
5774 [(set (match_operand:DI 0 "register_operand" "")
5775 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
5776 (match_operand:SI 2 "shift_count_operand" "")))]
5780 (define_insn "*<shift>di3_31"
5781 [(set (match_operand:DI 0 "register_operand" "=d")
5782 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
5783 (match_operand:SI 2 "shift_count_operand" "Y")))]
5786 [(set_attr "op_type" "RS")
5787 (set_attr "atype" "reg")])
5789 (define_insn "*<shift>di3_64"
5790 [(set (match_operand:DI 0 "register_operand" "=d")
5791 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
5792 (match_operand:SI 2 "shift_count_operand" "Y")))]
5794 "s<lr>lg\t%0,%1,%Y2"
5795 [(set_attr "op_type" "RSE")
5796 (set_attr "atype" "reg")])
5799 ; ashrdi3 instruction pattern(s).
5802 (define_expand "ashrdi3"
5804 [(set (match_operand:DI 0 "register_operand" "")
5805 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5806 (match_operand:SI 2 "shift_count_operand" "")))
5807 (clobber (reg:CC CC_REGNUM))])]
5811 (define_insn "*ashrdi3_cc_31"
5812 [(set (reg CC_REGNUM)
5813 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5814 (match_operand:SI 2 "shift_count_operand" "Y"))
5816 (set (match_operand:DI 0 "register_operand" "=d")
5817 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5818 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5820 [(set_attr "op_type" "RS")
5821 (set_attr "atype" "reg")])
5823 (define_insn "*ashrdi3_cconly_31"
5824 [(set (reg CC_REGNUM)
5825 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5826 (match_operand:SI 2 "shift_count_operand" "Y"))
5828 (clobber (match_scratch:DI 0 "=d"))]
5829 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5831 [(set_attr "op_type" "RS")
5832 (set_attr "atype" "reg")])
5834 (define_insn "*ashrdi3_31"
5835 [(set (match_operand:DI 0 "register_operand" "=d")
5836 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
5837 (match_operand:SI 2 "shift_count_operand" "Y")))
5838 (clobber (reg:CC CC_REGNUM))]
5841 [(set_attr "op_type" "RS")
5842 (set_attr "atype" "reg")])
5844 (define_insn "*ashrdi3_cc_64"
5845 [(set (reg CC_REGNUM)
5846 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5847 (match_operand:SI 2 "shift_count_operand" "Y"))
5849 (set (match_operand:DI 0 "register_operand" "=d")
5850 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5851 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5853 [(set_attr "op_type" "RSE")
5854 (set_attr "atype" "reg")])
5856 (define_insn "*ashrdi3_cconly_64"
5857 [(set (reg CC_REGNUM)
5858 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5859 (match_operand:SI 2 "shift_count_operand" "Y"))
5861 (clobber (match_scratch:DI 0 "=d"))]
5862 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5864 [(set_attr "op_type" "RSE")
5865 (set_attr "atype" "reg")])
5867 (define_insn "*ashrdi3_64"
5868 [(set (match_operand:DI 0 "register_operand" "=d")
5869 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
5870 (match_operand:SI 2 "shift_count_operand" "Y")))
5871 (clobber (reg:CC CC_REGNUM))]
5874 [(set_attr "op_type" "RSE")
5875 (set_attr "atype" "reg")])
5879 ; (ashl|lshr)si3 instruction pattern(s).
5882 (define_insn "<shift>si3"
5883 [(set (match_operand:SI 0 "register_operand" "=d")
5884 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
5885 (match_operand:SI 2 "shift_count_operand" "Y")))]
5888 [(set_attr "op_type" "RS")
5889 (set_attr "atype" "reg")])
5892 ; ashrsi3 instruction pattern(s).
5895 (define_insn "*ashrsi3_cc"
5896 [(set (reg CC_REGNUM)
5897 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5898 (match_operand:SI 2 "shift_count_operand" "Y"))
5900 (set (match_operand:SI 0 "register_operand" "=d")
5901 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5902 "s390_match_ccmode(insn, CCSmode)"
5904 [(set_attr "op_type" "RS")
5905 (set_attr "atype" "reg")])
5908 (define_insn "*ashrsi3_cconly"
5909 [(set (reg CC_REGNUM)
5910 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5911 (match_operand:SI 2 "shift_count_operand" "Y"))
5913 (clobber (match_scratch:SI 0 "=d"))]
5914 "s390_match_ccmode(insn, CCSmode)"
5916 [(set_attr "op_type" "RS")
5917 (set_attr "atype" "reg")])
5919 (define_insn "ashrsi3"
5920 [(set (match_operand:SI 0 "register_operand" "=d")
5921 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5922 (match_operand:SI 2 "shift_count_operand" "Y")))
5923 (clobber (reg:CC CC_REGNUM))]
5926 [(set_attr "op_type" "RS")
5927 (set_attr "atype" "reg")])
5931 ;; Branch instruction patterns.
5934 (define_expand "b<code>"
5936 (if_then_else (COMPARE (match_operand 0 "" "")
5941 "s390_emit_jump (operands[0],
5942 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
5946 ;;- Conditional jump instructions.
5949 (define_insn "*cjump_64"
5952 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5953 (label_ref (match_operand 0 "" ""))
5957 if (get_attr_length (insn) == 4)
5960 return "jg%C1\t%l0";
5962 [(set_attr "op_type" "RI")
5963 (set_attr "type" "branch")
5964 (set (attr "length")
5965 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5966 (const_int 4) (const_int 6)))])
5968 (define_insn "*cjump_31"
5971 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5972 (label_ref (match_operand 0 "" ""))
5976 gcc_assert (get_attr_length (insn) == 4);
5979 [(set_attr "op_type" "RI")
5980 (set_attr "type" "branch")
5981 (set (attr "length")
5982 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5983 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5984 (const_int 4) (const_int 6))
5985 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5986 (const_int 4) (const_int 8))))])
5988 (define_insn "*cjump_long"
5991 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
5992 (match_operand 0 "address_operand" "U")
5996 if (get_attr_op_type (insn) == OP_TYPE_RR)
6001 [(set (attr "op_type")
6002 (if_then_else (match_operand 0 "register_operand" "")
6003 (const_string "RR") (const_string "RX")))
6004 (set_attr "type" "branch")
6005 (set_attr "atype" "agen")])
6009 ;;- Negated conditional jump instructions.
6012 (define_insn "*icjump_64"
6015 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6017 (label_ref (match_operand 0 "" ""))))]
6020 if (get_attr_length (insn) == 4)
6023 return "jg%D1\t%l0";
6025 [(set_attr "op_type" "RI")
6026 (set_attr "type" "branch")
6027 (set (attr "length")
6028 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6029 (const_int 4) (const_int 6)))])
6031 (define_insn "*icjump_31"
6034 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6036 (label_ref (match_operand 0 "" ""))))]
6039 gcc_assert (get_attr_length (insn) == 4);
6042 [(set_attr "op_type" "RI")
6043 (set_attr "type" "branch")
6044 (set (attr "length")
6045 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6046 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6047 (const_int 4) (const_int 6))
6048 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6049 (const_int 4) (const_int 8))))])
6051 (define_insn "*icjump_long"
6054 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6056 (match_operand 0 "address_operand" "U")))]
6059 if (get_attr_op_type (insn) == OP_TYPE_RR)
6064 [(set (attr "op_type")
6065 (if_then_else (match_operand 0 "register_operand" "")
6066 (const_string "RR") (const_string "RX")))
6067 (set_attr "type" "branch")
6068 (set_attr "atype" "agen")])
6071 ;;- Trap instructions.
6075 [(trap_if (const_int 1) (const_int 0))]
6078 [(set_attr "op_type" "RI")
6079 (set_attr "type" "branch")])
6081 (define_expand "conditional_trap"
6082 [(trap_if (match_operand 0 "comparison_operator" "")
6083 (match_operand 1 "general_operand" ""))]
6086 if (operands[1] != const0_rtx) FAIL;
6087 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6088 s390_compare_op0, s390_compare_op1);
6091 (define_insn "*trap"
6092 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6096 [(set_attr "op_type" "RI")
6097 (set_attr "type" "branch")])
6100 ;;- Loop instructions.
6102 ;; This is all complicated by the fact that since this is a jump insn
6103 ;; we must handle our own output reloads.
6105 (define_expand "doloop_end"
6106 [(use (match_operand 0 "" "")) ; loop pseudo
6107 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6108 (use (match_operand 2 "" "")) ; max iterations
6109 (use (match_operand 3 "" "")) ; loop level
6110 (use (match_operand 4 "" ""))] ; label
6113 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6114 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6115 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6116 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6117 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6118 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6125 (define_insn_and_split "doloop_si64"
6128 (ne (match_operand:SI 1 "register_operand" "d,d")
6130 (label_ref (match_operand 0 "" ""))
6132 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6133 (plus:SI (match_dup 1) (const_int -1)))
6134 (clobber (match_scratch:SI 3 "=X,&1"))
6135 (clobber (reg:CC CC_REGNUM))]
6138 if (which_alternative != 0)
6140 else if (get_attr_length (insn) == 4)
6141 return "brct\t%1,%l0";
6143 return "ahi\t%1,-1\;jgne\t%l0";
6145 "&& reload_completed
6146 && (! REG_P (operands[2])
6147 || ! rtx_equal_p (operands[1], operands[2]))"
6148 [(parallel [(set (reg:CCAN CC_REGNUM)
6149 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6151 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6152 (set (match_dup 2) (match_dup 3))
6153 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6154 (label_ref (match_dup 0))
6157 [(set_attr "op_type" "RI")
6158 (set_attr "type" "branch")
6159 (set (attr "length")
6160 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6161 (const_int 4) (const_int 10)))])
6163 (define_insn_and_split "doloop_si31"
6166 (ne (match_operand:SI 1 "register_operand" "d,d")
6168 (label_ref (match_operand 0 "" ""))
6170 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6171 (plus:SI (match_dup 1) (const_int -1)))
6172 (clobber (match_scratch:SI 3 "=X,&1"))
6173 (clobber (reg:CC CC_REGNUM))]
6176 if (which_alternative != 0)
6178 else if (get_attr_length (insn) == 4)
6179 return "brct\t%1,%l0";
6183 "&& reload_completed
6184 && (! REG_P (operands[2])
6185 || ! rtx_equal_p (operands[1], operands[2]))"
6186 [(parallel [(set (reg:CCAN CC_REGNUM)
6187 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6189 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6190 (set (match_dup 2) (match_dup 3))
6191 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6192 (label_ref (match_dup 0))
6195 [(set_attr "op_type" "RI")
6196 (set_attr "type" "branch")
6197 (set (attr "length")
6198 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6199 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6200 (const_int 4) (const_int 6))
6201 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6202 (const_int 4) (const_int 8))))])
6204 (define_insn "*doloop_si_long"
6207 (ne (match_operand:SI 1 "register_operand" "d,d")
6209 (match_operand 0 "address_operand" "U,U")
6211 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6212 (plus:SI (match_dup 1) (const_int -1)))
6213 (clobber (match_scratch:SI 3 "=X,&1"))
6214 (clobber (reg:CC CC_REGNUM))]
6217 if (get_attr_op_type (insn) == OP_TYPE_RR)
6218 return "bctr\t%1,%0";
6220 return "bct\t%1,%a0";
6222 [(set (attr "op_type")
6223 (if_then_else (match_operand 0 "register_operand" "")
6224 (const_string "RR") (const_string "RX")))
6225 (set_attr "type" "branch")
6226 (set_attr "atype" "agen")])
6228 (define_insn_and_split "doloop_di"
6231 (ne (match_operand:DI 1 "register_operand" "d,d")
6233 (label_ref (match_operand 0 "" ""))
6235 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6236 (plus:DI (match_dup 1) (const_int -1)))
6237 (clobber (match_scratch:DI 3 "=X,&1"))
6238 (clobber (reg:CC CC_REGNUM))]
6241 if (which_alternative != 0)
6243 else if (get_attr_length (insn) == 4)
6244 return "brctg\t%1,%l0";
6246 return "aghi\t%1,-1\;jgne\t%l0";
6248 "&& reload_completed
6249 && (! REG_P (operands[2])
6250 || ! rtx_equal_p (operands[1], operands[2]))"
6251 [(parallel [(set (reg:CCAN CC_REGNUM)
6252 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6254 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6255 (set (match_dup 2) (match_dup 3))
6256 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6257 (label_ref (match_dup 0))
6260 [(set_attr "op_type" "RI")
6261 (set_attr "type" "branch")
6262 (set (attr "length")
6263 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6264 (const_int 4) (const_int 10)))])
6267 ;;- Unconditional jump instructions.
6271 ; jump instruction pattern(s).
6274 (define_expand "jump"
6275 [(match_operand 0 "" "")]
6277 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6279 (define_insn "*jump64"
6280 [(set (pc) (label_ref (match_operand 0 "" "")))]
6283 if (get_attr_length (insn) == 4)
6288 [(set_attr "op_type" "RI")
6289 (set_attr "type" "branch")
6290 (set (attr "length")
6291 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6292 (const_int 4) (const_int 6)))])
6294 (define_insn "*jump31"
6295 [(set (pc) (label_ref (match_operand 0 "" "")))]
6298 gcc_assert (get_attr_length (insn) == 4);
6301 [(set_attr "op_type" "RI")
6302 (set_attr "type" "branch")
6303 (set (attr "length")
6304 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6305 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6306 (const_int 4) (const_int 6))
6307 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6308 (const_int 4) (const_int 8))))])
6311 ; indirect-jump instruction pattern(s).
6314 (define_insn "indirect_jump"
6315 [(set (pc) (match_operand 0 "address_operand" "U"))]
6318 if (get_attr_op_type (insn) == OP_TYPE_RR)
6323 [(set (attr "op_type")
6324 (if_then_else (match_operand 0 "register_operand" "")
6325 (const_string "RR") (const_string "RX")))
6326 (set_attr "type" "branch")
6327 (set_attr "atype" "agen")])
6330 ; casesi instruction pattern(s).
6333 (define_insn "casesi_jump"
6334 [(set (pc) (match_operand 0 "address_operand" "U"))
6335 (use (label_ref (match_operand 1 "" "")))]
6338 if (get_attr_op_type (insn) == OP_TYPE_RR)
6343 [(set (attr "op_type")
6344 (if_then_else (match_operand 0 "register_operand" "")
6345 (const_string "RR") (const_string "RX")))
6346 (set_attr "type" "branch")
6347 (set_attr "atype" "agen")])
6349 (define_expand "casesi"
6350 [(match_operand:SI 0 "general_operand" "")
6351 (match_operand:SI 1 "general_operand" "")
6352 (match_operand:SI 2 "general_operand" "")
6353 (label_ref (match_operand 3 "" ""))
6354 (label_ref (match_operand 4 "" ""))]
6357 rtx index = gen_reg_rtx (SImode);
6358 rtx base = gen_reg_rtx (Pmode);
6359 rtx target = gen_reg_rtx (Pmode);
6361 emit_move_insn (index, operands[0]);
6362 emit_insn (gen_subsi3 (index, index, operands[1]));
6363 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6366 if (Pmode != SImode)
6367 index = convert_to_mode (Pmode, index, 1);
6368 if (GET_CODE (index) != REG)
6369 index = copy_to_mode_reg (Pmode, index);
6372 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6374 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6376 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6378 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6379 emit_move_insn (target, index);
6382 target = gen_rtx_PLUS (Pmode, base, target);
6383 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6390 ;;- Jump to subroutine.
6395 ; untyped call instruction pattern(s).
6398 ;; Call subroutine returning any type.
6399 (define_expand "untyped_call"
6400 [(parallel [(call (match_operand 0 "" "")
6402 (match_operand 1 "" "")
6403 (match_operand 2 "" "")])]
6408 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6410 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6412 rtx set = XVECEXP (operands[2], 0, i);
6413 emit_move_insn (SET_DEST (set), SET_SRC (set));
6416 /* The optimizer does not know that the call sets the function value
6417 registers we stored in the result block. We avoid problems by
6418 claiming that all hard registers are used and clobbered at this
6420 emit_insn (gen_blockage ());
6425 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6426 ;; all of memory. This blocks insns from being moved across this point.
6428 (define_insn "blockage"
6429 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6432 [(set_attr "type" "none")
6433 (set_attr "length" "0")])
6439 (define_expand "sibcall"
6440 [(call (match_operand 0 "" "")
6441 (match_operand 1 "" ""))]
6444 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6448 (define_insn "*sibcall_br"
6449 [(call (mem:QI (reg SIBCALL_REGNUM))
6450 (match_operand 0 "const_int_operand" "n"))]
6451 "SIBLING_CALL_P (insn)
6452 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6454 [(set_attr "op_type" "RR")
6455 (set_attr "type" "branch")
6456 (set_attr "atype" "agen")])
6458 (define_insn "*sibcall_brc"
6459 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6460 (match_operand 1 "const_int_operand" "n"))]
6461 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6463 [(set_attr "op_type" "RI")
6464 (set_attr "type" "branch")])
6466 (define_insn "*sibcall_brcl"
6467 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6468 (match_operand 1 "const_int_operand" "n"))]
6469 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6471 [(set_attr "op_type" "RIL")
6472 (set_attr "type" "branch")])
6475 ; sibcall_value patterns
6478 (define_expand "sibcall_value"
6479 [(set (match_operand 0 "" "")
6480 (call (match_operand 1 "" "")
6481 (match_operand 2 "" "")))]
6484 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6488 (define_insn "*sibcall_value_br"
6489 [(set (match_operand 0 "" "")
6490 (call (mem:QI (reg SIBCALL_REGNUM))
6491 (match_operand 1 "const_int_operand" "n")))]
6492 "SIBLING_CALL_P (insn)
6493 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6495 [(set_attr "op_type" "RR")
6496 (set_attr "type" "branch")
6497 (set_attr "atype" "agen")])
6499 (define_insn "*sibcall_value_brc"
6500 [(set (match_operand 0 "" "")
6501 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6502 (match_operand 2 "const_int_operand" "n")))]
6503 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6505 [(set_attr "op_type" "RI")
6506 (set_attr "type" "branch")])
6508 (define_insn "*sibcall_value_brcl"
6509 [(set (match_operand 0 "" "")
6510 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6511 (match_operand 2 "const_int_operand" "n")))]
6512 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6514 [(set_attr "op_type" "RIL")
6515 (set_attr "type" "branch")])
6519 ; call instruction pattern(s).
6522 (define_expand "call"
6523 [(call (match_operand 0 "" "")
6524 (match_operand 1 "" ""))
6525 (use (match_operand 2 "" ""))]
6528 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6529 gen_rtx_REG (Pmode, RETURN_REGNUM));
6533 (define_insn "*bras"
6534 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6535 (match_operand 1 "const_int_operand" "n"))
6536 (clobber (match_operand 2 "register_operand" "=r"))]
6537 "!SIBLING_CALL_P (insn)
6538 && TARGET_SMALL_EXEC
6539 && GET_MODE (operands[2]) == Pmode"
6541 [(set_attr "op_type" "RI")
6542 (set_attr "type" "jsr")])
6544 (define_insn "*brasl"
6545 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6546 (match_operand 1 "const_int_operand" "n"))
6547 (clobber (match_operand 2 "register_operand" "=r"))]
6548 "!SIBLING_CALL_P (insn)
6550 && GET_MODE (operands[2]) == Pmode"
6552 [(set_attr "op_type" "RIL")
6553 (set_attr "type" "jsr")])
6555 (define_insn "*basr"
6556 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6557 (match_operand 1 "const_int_operand" "n"))
6558 (clobber (match_operand 2 "register_operand" "=r"))]
6559 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6561 if (get_attr_op_type (insn) == OP_TYPE_RR)
6562 return "basr\t%2,%0";
6564 return "bas\t%2,%a0";
6566 [(set (attr "op_type")
6567 (if_then_else (match_operand 0 "register_operand" "")
6568 (const_string "RR") (const_string "RX")))
6569 (set_attr "type" "jsr")
6570 (set_attr "atype" "agen")])
6573 ; call_value instruction pattern(s).
6576 (define_expand "call_value"
6577 [(set (match_operand 0 "" "")
6578 (call (match_operand 1 "" "")
6579 (match_operand 2 "" "")))
6580 (use (match_operand 3 "" ""))]
6583 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6584 gen_rtx_REG (Pmode, RETURN_REGNUM));
6588 (define_insn "*bras_r"
6589 [(set (match_operand 0 "" "")
6590 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6591 (match_operand:SI 2 "const_int_operand" "n")))
6592 (clobber (match_operand 3 "register_operand" "=r"))]
6593 "!SIBLING_CALL_P (insn)
6594 && TARGET_SMALL_EXEC
6595 && GET_MODE (operands[3]) == Pmode"
6597 [(set_attr "op_type" "RI")
6598 (set_attr "type" "jsr")])
6600 (define_insn "*brasl_r"
6601 [(set (match_operand 0 "" "")
6602 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6603 (match_operand 2 "const_int_operand" "n")))
6604 (clobber (match_operand 3 "register_operand" "=r"))]
6605 "!SIBLING_CALL_P (insn)
6607 && GET_MODE (operands[3]) == Pmode"
6609 [(set_attr "op_type" "RIL")
6610 (set_attr "type" "jsr")])
6612 (define_insn "*basr_r"
6613 [(set (match_operand 0 "" "")
6614 (call (mem:QI (match_operand 1 "address_operand" "U"))
6615 (match_operand 2 "const_int_operand" "n")))
6616 (clobber (match_operand 3 "register_operand" "=r"))]
6617 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6619 if (get_attr_op_type (insn) == OP_TYPE_RR)
6620 return "basr\t%3,%1";
6622 return "bas\t%3,%a1";
6624 [(set (attr "op_type")
6625 (if_then_else (match_operand 1 "register_operand" "")
6626 (const_string "RR") (const_string "RX")))
6627 (set_attr "type" "jsr")
6628 (set_attr "atype" "agen")])
6631 ;;- Thread-local storage support.
6634 (define_expand "get_tp_64"
6635 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
6639 (define_expand "get_tp_31"
6640 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
6644 (define_expand "set_tp_64"
6645 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
6646 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
6650 (define_expand "set_tp_31"
6651 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
6652 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
6656 (define_insn "*set_tp"
6657 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
6660 [(set_attr "type" "none")
6661 (set_attr "length" "0")])
6663 (define_insn "*tls_load_64"
6664 [(set (match_operand:DI 0 "register_operand" "=d")
6665 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
6666 (match_operand:DI 2 "" "")]
6670 [(set_attr "op_type" "RXE")])
6672 (define_insn "*tls_load_31"
6673 [(set (match_operand:SI 0 "register_operand" "=d,d")
6674 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
6675 (match_operand:SI 2 "" "")]
6681 [(set_attr "op_type" "RX,RXY")])
6683 (define_insn "*bras_tls"
6684 [(set (match_operand 0 "" "")
6685 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6686 (match_operand 2 "const_int_operand" "n")))
6687 (clobber (match_operand 3 "register_operand" "=r"))
6688 (use (match_operand 4 "" ""))]
6689 "!SIBLING_CALL_P (insn)
6690 && TARGET_SMALL_EXEC
6691 && GET_MODE (operands[3]) == Pmode"
6693 [(set_attr "op_type" "RI")
6694 (set_attr "type" "jsr")])
6696 (define_insn "*brasl_tls"
6697 [(set (match_operand 0 "" "")
6698 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6699 (match_operand 2 "const_int_operand" "n")))
6700 (clobber (match_operand 3 "register_operand" "=r"))
6701 (use (match_operand 4 "" ""))]
6702 "!SIBLING_CALL_P (insn)
6704 && GET_MODE (operands[3]) == Pmode"
6706 [(set_attr "op_type" "RIL")
6707 (set_attr "type" "jsr")])
6709 (define_insn "*basr_tls"
6710 [(set (match_operand 0 "" "")
6711 (call (mem:QI (match_operand 1 "address_operand" "U"))
6712 (match_operand 2 "const_int_operand" "n")))
6713 (clobber (match_operand 3 "register_operand" "=r"))
6714 (use (match_operand 4 "" ""))]
6715 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6717 if (get_attr_op_type (insn) == OP_TYPE_RR)
6718 return "basr\t%3,%1%J4";
6720 return "bas\t%3,%a1%J4";
6722 [(set (attr "op_type")
6723 (if_then_else (match_operand 1 "register_operand" "")
6724 (const_string "RR") (const_string "RX")))
6725 (set_attr "type" "jsr")
6726 (set_attr "atype" "agen")])
6729 ;;- Miscellaneous instructions.
6733 ; allocate stack instruction pattern(s).
6736 (define_expand "allocate_stack"
6737 [(match_operand 0 "general_operand" "")
6738 (match_operand 1 "general_operand" "")]
6741 rtx temp = gen_reg_rtx (Pmode);
6743 emit_move_insn (temp, s390_back_chain_rtx ());
6744 anti_adjust_stack (operands[1]);
6745 emit_move_insn (s390_back_chain_rtx (), temp);
6747 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6753 ; setjmp instruction pattern.
6756 (define_expand "builtin_setjmp_receiver"
6757 [(match_operand 0 "" "")]
6760 emit_insn (s390_load_got ());
6761 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
6765 ;; These patterns say how to save and restore the stack pointer. We need not
6766 ;; save the stack pointer at function level since we are careful to
6767 ;; preserve the backchain. At block level, we have to restore the backchain
6768 ;; when we restore the stack pointer.
6770 ;; For nonlocal gotos, we must save both the stack pointer and its
6771 ;; backchain and restore both. Note that in the nonlocal case, the
6772 ;; save area is a memory location.
6774 (define_expand "save_stack_function"
6775 [(match_operand 0 "general_operand" "")
6776 (match_operand 1 "general_operand" "")]
6780 (define_expand "restore_stack_function"
6781 [(match_operand 0 "general_operand" "")
6782 (match_operand 1 "general_operand" "")]
6786 (define_expand "restore_stack_block"
6787 [(match_operand 0 "register_operand" "")
6788 (match_operand 1 "register_operand" "")]
6791 rtx temp = gen_reg_rtx (Pmode);
6793 emit_move_insn (temp, s390_back_chain_rtx ());
6794 emit_move_insn (operands[0], operands[1]);
6795 emit_move_insn (s390_back_chain_rtx (), temp);
6800 (define_expand "save_stack_nonlocal"
6801 [(match_operand 0 "memory_operand" "")
6802 (match_operand 1 "register_operand" "")]
6805 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6806 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6808 /* Copy the backchain to the first word, sp to the second and the
6809 literal pool base to the third. */
6811 if (TARGET_BACKCHAIN)
6813 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
6814 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
6817 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
6818 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
6823 (define_expand "restore_stack_nonlocal"
6824 [(match_operand 0 "register_operand" "")
6825 (match_operand 1 "memory_operand" "")]
6828 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
6829 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
6830 rtx temp = NULL_RTX;
6832 /* Restore the backchain from the first word, sp from the second and the
6833 literal pool base from the third. */
6835 if (TARGET_BACKCHAIN)
6836 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
6838 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
6839 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
6842 emit_move_insn (s390_back_chain_rtx (), temp);
6844 emit_insn (gen_rtx_USE (VOIDmode, base));
6850 ; nop instruction pattern(s).
6857 [(set_attr "op_type" "RR")])
6861 ; Special literal pool access instruction pattern(s).
6864 (define_insn "*pool_entry"
6865 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
6866 UNSPECV_POOL_ENTRY)]
6869 enum machine_mode mode = GET_MODE (PATTERN (insn));
6870 unsigned int align = GET_MODE_BITSIZE (mode);
6871 s390_output_pool_entry (operands[0], mode, align);
6874 [(set (attr "length")
6875 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
6877 (define_insn "pool_align"
6878 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
6879 UNSPECV_POOL_ALIGN)]
6882 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6884 (define_insn "pool_section_start"
6885 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
6888 [(set_attr "length" "0")])
6890 (define_insn "pool_section_end"
6891 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
6894 [(set_attr "length" "0")])
6896 (define_insn "main_base_31_small"
6897 [(set (match_operand 0 "register_operand" "=a")
6898 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
6899 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6901 [(set_attr "op_type" "RR")
6902 (set_attr "type" "la")])
6904 (define_insn "main_base_31_large"
6905 [(set (match_operand 0 "register_operand" "=a")
6906 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
6907 (set (pc) (label_ref (match_operand 2 "" "")))]
6908 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6910 [(set_attr "op_type" "RI")])
6912 (define_insn "main_base_64"
6913 [(set (match_operand 0 "register_operand" "=a")
6914 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
6915 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6917 [(set_attr "op_type" "RIL")
6918 (set_attr "type" "larl")])
6920 (define_insn "main_pool"
6921 [(set (match_operand 0 "register_operand" "=a")
6922 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
6923 "GET_MODE (operands[0]) == Pmode"
6928 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
6929 (const_string "larl") (const_string "la")))])
6931 (define_insn "reload_base_31"
6932 [(set (match_operand 0 "register_operand" "=a")
6933 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
6934 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6935 "basr\t%0,0\;la\t%0,%1-.(%0)"
6936 [(set_attr "length" "6")
6937 (set_attr "type" "la")])
6939 (define_insn "reload_base_64"
6940 [(set (match_operand 0 "register_operand" "=a")
6941 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
6942 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
6944 [(set_attr "op_type" "RIL")
6945 (set_attr "type" "larl")])
6948 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
6953 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6956 ;; Insns related to generating the function prologue and epilogue.
6960 (define_expand "prologue"
6961 [(use (const_int 0))]
6963 "s390_emit_prologue (); DONE;")
6965 (define_insn "prologue_tpf"
6966 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
6967 (clobber (reg:DI 1))]
6968 "TARGET_TPF_PROFILING"
6969 "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064"
6970 [(set_attr "length" "14")])
6972 (define_expand "epilogue"
6973 [(use (const_int 1))]
6975 "s390_emit_epilogue (false); DONE;")
6977 (define_insn "epilogue_tpf"
6978 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
6979 (clobber (reg:DI 1))]
6980 "TARGET_TPF_PROFILING"
6981 "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070"
6982 [(set_attr "length" "14")])
6984 (define_expand "sibcall_epilogue"
6985 [(use (const_int 0))]
6987 "s390_emit_epilogue (true); DONE;")
6989 (define_insn "*return"
6991 (use (match_operand 0 "register_operand" "a"))]
6992 "GET_MODE (operands[0]) == Pmode"
6994 [(set_attr "op_type" "RR")
6995 (set_attr "type" "jsr")
6996 (set_attr "atype" "agen")])
6999 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7000 ;; pointer. This is used for compatibility.
7002 (define_expand "ptr_extend"
7003 [(set (match_operand:DI 0 "register_operand" "=r")
7004 (match_operand:SI 1 "register_operand" "r"))]
7007 emit_insn (gen_anddi3 (operands[0],
7008 gen_lowpart (DImode, operands[1]),
7009 GEN_INT (0x7fffffff)));
7013 ;; Instruction definition to expand eh_return macro to support
7014 ;; swapping in special linkage return addresses.
7016 (define_expand "eh_return"
7017 [(use (match_operand 0 "register_operand" ""))]
7020 s390_emit_tpf_eh_return (operands[0]);