| blob | 93adfc11be749fba7fecc9b06cf72c57553dbdf2 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 scalar_int_mode,
421 scalar_int_mode,
494 \f
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
516 \f
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
522 {
526 }
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
532 register. */
536 {
545 }
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
555 {
564 {
568 CASE_CONST_ANY:
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
593 }
595 /* If it wasn't one of the common cases above, check each expression and
596 vector of this code. Look for a unique usage of DEST. */
600 {
602 {
607 else
613 /* Duplicate usage. */
615 }
617 {
621 {
627 else
634 }
635 }
636 }
639 }
642 /* See if DEST, produced in INSN, is used only a single time in the
643 sequel. If so, return a pointer to the innermost rtx expression in which
644 it is used.
646 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
648 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
649 care about REG_DEAD notes or LOG_LINKS.
651 Otherwise, we find the single use by finding an insn that has a
652 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
653 only referenced once in that insn, we know that it must be the first
654 and last insn referencing DEST. */
658 {
659 basic_block bb;
665 {
675 }
685 {
691 {
696 }
697 }
700 }
701 \f
702 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
703 insn. The substitution can be undone by undo_all. If INTO is already
704 set to NEWVAL, do not record this change. Because computing NEWVAL might
705 also call SUBST, we have to compute it before we put anything into
706 the undo table. */
708 static void
710 {
717 /* We'd like to catch as many invalid transformations here as
718 possible. Unfortunately, there are way too many mode changes
719 that are perfectly valid, so we'd waste too much effort for
720 little gain doing the checks here. Focus on catching invalid
721 transformations involving integer constants. */
724 {
725 /* Sanity check that we're replacing oldval with a CONST_INT
726 that is a valid sign-extension for the original mode. */
730 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
731 CONST_INT is not valid, because after the replacement, the
732 original mode would be gone. Unfortunately, we can't tell
733 when do_SUBST is called to replace the operand thereof, so we
734 perform this test on oldval instead, checking whether an
735 invalid replacement took place before we got here. */
740 }
744 else
753 }
755 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
757 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
758 for the value of a HOST_WIDE_INT value (including CONST_INT) is
759 not safe. */
761 static void
763 {
772 else
781 }
783 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
785 /* Similar to SUBST, but just substitute the mode. This is used when
786 changing the mode of a pseudo-register, so that any other
787 references to the entry in the regno_reg_rtx array will change as
788 well. */
790 static void
792 {
801 else
810 }
812 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
814 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
816 static void
818 {
827 else
836 }
838 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
839 \f
840 /* Subroutine of try_combine. Determine whether the replacement patterns
841 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
842 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
843 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
844 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
845 of all the instructions can be estimated and the replacements are more
846 expensive than the original sequence. */
848 static bool
851 {
856 /* Lookup the original insn_costs. */
861 {
864 {
868 }
869 else
870 {
874 }
875 }
876 else
877 {
880 }
882 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
883 correct that. */
888 /* Calculate the replacement insn_costs. */
897 {
907 }
908 else
909 {
912 }
915 {
924 optimize_this_for_speed_p);
928 {
931 }
932 else
934 }
936 /* Disallow this combination if both new_cost and old_cost are greater than
937 zero, and new_cost is greater than old cost. */
941 {
960 else
962 }
967 /* Update the uid_insn_cost array with the replacement costs. */
971 {
975 }
978 }
981 /* Delete any insns that copy a register to itself. */
983 static void
985 {
987 basic_block bb;
990 {
992 {
995 {
1000 }
1001 }
1002 }
1003 }
1005 \f
1006 /* Return false if we do not want to (or cannot) combine DEF. */
1007 static bool
1009 {
1010 /* Do not consider if it is pre/post modification in MEM. */
1016 /* Do not combine frame pointer adjustments. */
1019 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1027 }
1029 /* Return false if we do not want to (or cannot) combine USE. */
1030 static bool
1032 {
1033 /* Do not consider the usage of the stack pointer by function call. */
1038 }
1040 /* Fill in log links field for all insns. */
1042 static void
1044 {
1045 basic_block bb;
1052 /* Pass through each block from the end, recording the uses of each
1053 register and establishing log links when def is encountered.
1054 Note that we do not clear next_use array in order to save time,
1055 so we have to test whether the use is in the same basic block as def.
1057 There are a few cases below when we do not consider the definition or
1058 usage -- these are taken from original flow.c did. Don't ask me why it is
1059 done this way; I don't know and if it works, I don't want to know. */
1062 {
1064 {
1068 /* Log links are created only once. */
1072 {
1088 /* flow.c claimed:
1090 We don't build a LOG_LINK for hard registers contained
1091 in ASM_OPERANDs. If these registers get replaced,
1092 we might wind up changing the semantics of the insn,
1093 even if reload can make what appear to be valid
1094 assignments later. */
1099 /* Don't add duplicate links between instructions. */
1108 }
1113 }
1114 }
1117 }
1119 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1120 true if we found a LOG_LINK that proves that A feeds B. This only works
1121 if there are no instructions between A and B which could have a link
1122 depending on A, since in that case we would not record a link for B.
1123 We also check the implicit dependency created by a cc0 setter/user
1124 pair. */
1126 static bool
1128 {
1136 }
1137 \f
1138 /* Main entry point for combiner. F is the first insn of the function.
1139 NREGS is the first unused pseudo-reg number.
1141 Return nonzero if the combiner has turned an indirect jump
1142 instruction into a direct jump. */
1143 static int
1145 {
1150 basic_block last_bb;
1170 /* Allocate array for insn info. */
1178 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1179 problems when, for example, we have j <<= 1 in a loop. */
1184 /* Scan all SETs and see if we can deduce anything about what
1185 bits are known to be zero for some registers and how many copies
1186 of the sign bit are known to exist for those registers.
1188 Also set any known values so that we can use it while searching
1189 for what bits are known to be set. */
1192 /* Allow the entry block and the first block to fall into the same EBB.
1193 Conceptually the incoming promotions are assigned to the entry block. */
1198 {
1203 label_tick++;
1211 {
1212 rtx links;
1218 insn);
1225 insn);
1227 /* Record the current insn_cost of this instruction. */
1231 {
1234 }
1235 }
1236 }
1240 /* Now scan all the insns in forward order. */
1248 {
1251 /* Ignore instruction combination in basic blocks that are going to
1252 be removed as unreachable anyway. See PR82386. */
1260 label_tick++;
1270 {
1284 /* See if we know about function return values before this
1285 insn based upon SUBREG flags. */
1288 /* See if we can find hardregs and subreg of pseudos in
1289 narrower modes. This could help turning TRUNCATEs
1290 into SUBREGs. */
1293 /* Try this insn with each insn it links back to. */
1299 {
1302 }
1304 /* Try each sequence of three linked insns ending with this one. */
1308 {
1311 /* If the linked insn has been replaced by a note, then there
1312 is no point in pursuing this chain any further. */
1320 {
1323 }
1324 }
1326 /* Try to combine a jump insn that uses CC0
1327 with a preceding insn that sets CC0, and maybe with its
1328 logical predecessor as well.
1329 This is how we make decrement-and-branch insns.
1330 We need this special code because data flow connections
1331 via CC0 do not get entered in LOG_LINKS. */
1338 {
1349 }
1351 /* Do the same for an insn that explicitly references CC0. */
1358 {
1369 }
1371 /* Finally, see if any of the insns that this insn links to
1372 explicitly references CC0. If so, try this insn, that insn,
1373 and its predecessor if it sets CC0. */
1375 {
1387 }
1389 /* Try combining an insn with two different insns whose results it
1390 uses. */
1400 {
1403 }
1405 /* Try four-instruction combinations. */
1408 {
1412 /* If the linked insn has been replaced by a note, then there
1413 is no point in pursuing this chain any further. */
1418 {
1422 /* I0 -> I1 -> I2 -> I3. */
1428 {
1431 }
1432 /* I0, I1 -> I2, I2 -> I3. */
1439 {
1442 }
1443 }
1446 {
1450 /* I0 -> I2; I1, I2 -> I3. */
1456 {
1459 }
1460 /* I0 -> I1; I1, I2 -> I3. */
1466 {
1469 }
1470 }
1471 }
1473 /* Try this insn with each REG_EQUAL note it links back to. */
1475 {
1481 /* Avoid using a register that may already been marked
1482 dead by an earlier instruction. */
1490 {
1491 /* Temporarily replace the set's source with the
1492 contents of the REG_EQUAL note. The insn will
1493 be deleted or recognized by try_combine. */
1504 last_combined_insn);
1507 {
1510 }
1513 }
1514 }
1519 retry:
1520 ;
1521 }
1522 }
1529 /* Clean up. */
1535 {
1538 {
1541 }
1543 }
1553 /* Make recognizer allow volatile MEMs again. */
1557 }
1559 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1561 static void
1563 {
1569 }
1570 \f
1571 /* Set up any promoted values for incoming argument registers. */
1573 static void
1575 {
1576 tree arg;
1581 {
1586 /* Only continue if the incoming argument is in a register. */
1590 /* Determine, if possible, whether all call sites of the current
1591 function lie within the current compilation unit. (This does
1592 take into account the exporting of a function via taking its
1593 address, and so forth.) */
1596 /* The mode and signedness of the argument before any promotions happen
1597 (equal to the mode of the pseudo holding it at that stage). */
1601 /* The mode and signedness of the argument after any source language and
1602 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1606 /* The mode and signedness of the argument as it is actually passed,
1607 see assign_parm_setup_reg in function.c. */
1611 /* The mode of the register in which the argument is being passed. */
1614 /* Eliminate sign extensions in the callee when:
1615 (a) A mode promotion has occurred; */
1618 /* (b) The mode of the register is the same as the mode of
1619 the argument as it is passed; */
1622 /* (c) There's no language level extension; */
1624 ;
1625 /* (c.1) All callers are from the current compilation unit. If that's
1626 the case we don't have to rely on an ABI, we only have to know
1627 what we're generating right now, and we know that we will do the
1628 mode1 to mode2 promotion with the given sign. */
1631 /* (c.2) The combination of the two promotions is useful. This is
1632 true when the signs match, or if the first promotion is unsigned.
1633 In the later case, (sign_extend (zero_extend x)) is the same as
1634 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1640 /* Record that the value was promoted from mode1 to mode3,
1641 so that any sign extension at the head of the current
1642 function may be eliminated. */
1646 }
1647 }
1649 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1650 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1651 because some machines (maybe most) will actually do the sign-extension and
1652 this is the conservative approach.
1654 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1655 kludge. */
1657 static rtx
1659 {
1660 scalar_int_mode int_mode;
1669 }
1671 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1672 and SET. */
1674 static void
1676 rtx x)
1677 {
1687 {
1691 }
1693 /* Don't call nonzero_bits if it cannot change anything. */
1695 {
1700 }
1702 /* Don't call num_sign_bit_copies if it cannot change anything. */
1704 {
1707 {
1711 }
1714 }
1715 }
1717 /* Called via note_stores. If X is a pseudo that is narrower than
1718 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1720 If we are setting only a portion of X and we can't figure out what
1721 portion, assume all bits will be used since we don't know what will
1722 be happening.
1724 Similarly, set how many bits of X are known to be copies of the sign bit
1725 at all locations in the function. This is the smallest number implied
1726 by any set of X. */
1728 static void
1730 {
1732 scalar_int_mode mode;
1736 /* If this register is undefined at the start of the file, we can't
1737 say what its contents were. */
1738 && ! REGNO_REG_SET_P
1742 {
1746 {
1750 }
1752 /* If this register is being initialized using itself, and the
1753 register is uninitialized in this basic block, and there are
1754 no LOG_LINKS which set the register, then part of the
1755 register is uninitialized. In that case we can't assume
1756 anything about the number of nonzero bits.
1758 ??? We could do better if we checked this in
1759 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1760 could avoid making assumptions about the insn which initially
1761 sets the register, while still using the information in other
1762 insns. We would have to be careful to check every insn
1763 involved in the combination. */
1769 {
1776 {
1780 }
1781 }
1783 /* If this is a complex assignment, see if we can convert it into a
1784 simple assignment. */
1787 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1788 set what we know about X. */
1794 else
1795 {
1798 }
1799 }
1800 }
1801 \f
1802 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1803 optionally insns that were previously combined into I3 or that will be
1804 combined into the merger of INSN and I3. The order is PRED, PRED2,
1805 INSN, SUCC, SUCC2, I3.
1807 Return 0 if the combination is not allowed for any reason.
1809 If the combination is allowed, *PDEST will be set to the single
1810 destination of INSN and *PSRC to the single source, and this function
1811 will return 1. */
1813 static int
1817 {
1822 rtx link;
1827 {
1829 {
1834 }
1839 }
1843 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1844 or a PARALLEL consisting of such a SET and CLOBBERs.
1846 If INSN has CLOBBER parallel parts, ignore them for our processing.
1847 By definition, these happen during the execution of the insn. When it
1848 is merged with another insn, all bets are off. If they are, in fact,
1849 needed and aren't also supplied in I3, they may be added by
1850 recog_for_combine. Otherwise, it won't match.
1852 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1853 note.
1855 Get the source and destination of INSN. If more than one, can't
1856 combine. */
1862 {
1864 {
1868 {
1869 /* This is important to combine floating point insns
1870 for the SH4 port. */
1872 /* Combining an isolated USE doesn't make sense.
1873 We depend here on combinable_i3pat to reject them. */
1874 /* The code below this loop only verifies that the inputs of
1875 the SET in INSN do not change. We call reg_set_between_p
1876 to verify that the REG in the USE does not change between
1877 I3 and INSN.
1878 If the USE in INSN was for a pseudo register, the matching
1879 insn pattern will likely match any register; combining this
1880 with any other USE would only be safe if we knew that the
1881 used registers have identical values, or if there was
1882 something to tell them apart, e.g. different modes. For
1883 now, we forgo such complicated tests and simply disallow
1884 combining of USES of pseudo registers with any other USE. */
1887 {
1892 do
1893 {
1903 }
1905 }
1908 /* We can ignore CLOBBERs. */
1913 /* Ignore SETs whose result isn't used but not those that
1914 have side-effects. */
1920 /* If we have already found a SET, this is a second one and
1921 so we cannot combine with this insn. */
1929 /* Anything else means we can't combine. */
1931 }
1932 }
1935 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1936 so don't do anything with it. */
1939 }
1940 else
1946 /* The simplification in expand_field_assignment may call back to
1947 get_last_value, so set safe guard here. */
1953 /* Do not eliminate user-specified register if it is in an
1954 asm input because we may break the register asm usage defined
1955 in GCC manual if allow to do so.
1956 Be aware that this may cover more cases than we expect but this
1957 should be harmless. */
1962 /* Don't eliminate a store in the stack pointer. */
1964 /* Don't combine with an insn that sets a register to itself if it has
1965 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1967 /* Can't merge an ASM_OPERANDS. */
1969 /* Can't merge a function call. */
1971 /* Don't eliminate a function call argument. */
1977 /* Don't substitute into an incremented register. */
1981 /* Don't substitute into a non-local goto, this confuses CFG. */
1983 /* Make sure that DEST is not used after INSN but before SUCC, or
1984 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1985 || (!all_adjacent
1986 && ((succ2
1990 || (succ
1991 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1992 that case SUCC is not in the insn stream, so use SUCC2
1993 instead for this test. */
1995 succ2
1998 /* Make sure that the value that is to be substituted for the register
1999 does not use any registers whose values alter in between. However,
2000 If the insns are adjacent, a use can't cross a set even though we
2001 think it might (this can happen for a sequence of insns each setting
2002 the same destination; last_set of that register might point to
2003 a NOTE). If INSN has a REG_EQUIV note, the register is always
2004 equivalent to the memory so the substitution is valid even if there
2005 are intervening stores. Also, don't move a volatile asm or
2006 UNSPEC_VOLATILE across any other insns. */
2007 || (! all_adjacent
2013 /* Don't combine across a CALL_INSN, because that would possibly
2014 change whether the life span of some REGs crosses calls or not,
2015 and it is a pain to update that information.
2016 Exception: if source is a constant, moving it later can't hurt.
2017 Accept that as a special case. */
2021 /* DEST must either be a REG or CC0. */
2023 {
2024 /* If register alignment is being enforced for multi-word items in all
2025 cases except for parameters, it is possible to have a register copy
2026 insn referencing a hard register that is not allowed to contain the
2027 mode being copied and which would not be valid as an operand of most
2028 insns. Eliminate this problem by not combining with such an insn.
2030 Also, on some machines we don't want to extend the life of a hard
2031 register. */
2036 /* Don't extend the life of a hard register unless it is
2037 user variable (if we have few registers) or it can't
2038 fit into the desired register (meaning something special
2039 is going on).
2040 Also avoid substituting a return register into I3, because
2041 reload can't handle a conflict with constraints of other
2042 inputs. */
2047 }
2055 {
2058 /* If the clobber represents an earlyclobber operand, we must not
2059 substitute an expression containing the clobbered register.
2060 As we do not analyze the constraint strings here, we have to
2061 make the conservative assumption. However, if the register is
2062 a fixed hard reg, the clobber cannot represent any operand;
2063 we leave it up to the machine description to either accept or
2064 reject use-and-clobber patterns. */
2070 }
2072 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2073 or not), reject, unless nothing volatile comes between it and I3 */
2076 {
2077 /* Make sure neither succ nor succ2 contains a volatile reference. */
2082 /* We'll check insns between INSN and I3 below. */
2083 }
2085 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2086 to be an explicit register variable, and was chosen for a reason. */
2092 /* If INSN contains volatile references (specifically volatile MEMs),
2093 we cannot combine across any other volatile references.
2094 Even if INSN doesn't contain volatile references, any intervening
2095 volatile insn might affect machine state. */
2098 ? volatile_refs_p
2105 /* If INSN contains an autoincrement or autodecrement, make sure that
2106 register is not used between there and I3, and not already used in
2107 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2108 Also insist that I3 not be a jump; if it were one
2109 and the incremented register were spilled, we would lose. */
2127 /* Don't combine an insn that follows a CC0-setting insn.
2128 An insn that uses CC0 must not be separated from the one that sets it.
2129 We do, however, allow I2 to follow a CC0-setting insn if that insn
2130 is passed as I1; in that case it will be deleted also.
2131 We also allow combining in this case if all the insns are adjacent
2132 because that would leave the two CC0 insns adjacent as well.
2133 It would be more logical to test whether CC0 occurs inside I1 or I2,
2134 but that would be much slower, and this ought to be equivalent. */
2137 {
2142 }
2144 /* If we get here, we have passed all the tests and the combination is
2145 to be allowed. */
2151 }
2152 \f
2153 /* LOC is the location within I3 that contains its pattern or the component
2154 of a PARALLEL of the pattern. We validate that it is valid for combining.
2156 One problem is if I3 modifies its output, as opposed to replacing it
2157 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2158 doing so would produce an insn that is not equivalent to the original insns.
2160 Consider:
2162 (set (reg:DI 101) (reg:DI 100))
2163 (set (subreg:SI (reg:DI 101) 0) <foo>)
2165 This is NOT equivalent to:
2167 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2168 (set (reg:DI 101) (reg:DI 100))])
2170 Not only does this modify 100 (in which case it might still be valid
2171 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2173 We can also run into a problem if I2 sets a register that I1
2174 uses and I1 gets directly substituted into I3 (not via I2). In that
2175 case, we would be getting the wrong value of I2DEST into I3, so we
2176 must reject the combination. This case occurs when I2 and I1 both
2177 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2178 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2179 of a SET must prevent combination from occurring. The same situation
2180 can occur for I0, in which case I0_NOT_IN_SRC is set.
2182 Before doing the above check, we first try to expand a field assignment
2183 into a set of logical operations.
2185 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2186 we place a register that is both set and used within I3. If more than one
2187 such register is detected, we fail.
2189 Return 1 if the combination is valid, zero otherwise. */
2191 static int
2194 {
2198 {
2203 rtx subdest;
2210 /* Check for the case where I3 modifies its output, as discussed
2211 above. We don't want to prevent pseudos from being combined
2212 into the address of a MEM, so only prevent the combination if
2213 i1 or i2 set the same MEM. */
2223 /* This is the same test done in can_combine_p except we can't test
2224 all_adjacent; we don't have to, since this instruction will stay
2225 in place, thus we are not considering increasing the lifetime of
2226 INNER_DEST.
2228 Also, if this insn sets a function argument, combining it with
2229 something that might need a spill could clobber a previous
2230 function argument; the all_adjacent test in can_combine_p also
2231 checks this; here, we do a more specific test for this case. */
2241 /* If DEST is used in I3, it is being killed in this insn, so
2242 record that for later. We have to consider paradoxical
2243 subregs here, since they kill the whole register, but we
2244 ignore partial subregs, STRICT_LOW_PART, etc.
2245 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2246 STACK_POINTER_REGNUM, since these are always considered to be
2247 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2255 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2261 {
2266 }
2267 }
2270 {
2277 }
2280 }
2281 \f
2282 /* Return 1 if X is an arithmetic expression that contains a multiplication
2283 and division. We don't count multiplications by powers of two here. */
2285 static int
2287 {
2289 {
2305 }
2306 }
2307 \f
2308 /* Determine whether INSN can be used in a combination. Return nonzero if
2309 not. This is used in try_combine to detect early some cases where we
2310 can't perform combinations. */
2312 static int
2314 {
2315 rtx set;
2318 /* If this isn't really an insn, we can't do anything.
2319 This can occur when flow deletes an insn that it has merged into an
2320 auto-increment address. */
2324 /* Never combine loads and stores involving hard regs that are likely
2325 to be spilled. The register allocator can usually handle such
2326 reg-reg moves by tying. If we allow the combiner to make
2327 substitutions of likely-spilled regs, reload might die.
2328 As an exception, we allow combinations involving fixed regs; these are
2329 not available to the register allocator so there's no risk involved. */
2350 }
2352 struct likely_spilled_retval_info
2353 {
2356 };
2358 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2359 hard registers that are known to be written to / clobbered in full. */
2360 static void
2362 {
2379 else
2382 }
2384 /* Return nonzero iff part of the return value is live during INSN, and
2385 it is likely spilled. This can happen when more than one insn is needed
2386 to copy the return value, e.g. when we consider to combine into the
2387 second copy insn for a complex value. */
2389 static int
2391 {
2393 rtx reg;
2396 /* We assume here that no machine mode needs more than
2397 32 hard registers when the value overlaps with a register
2398 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2413 /* Disregard parts of the return value that are set later. */
2422 /* Check if any of the (probably) live return value registers is
2423 likely spilled. */
2424 nregs --;
2425 do
2426 {
2432 }
2434 /* Adjust INSN after we made a change to its destination.
2436 Changing the destination can invalidate notes that say something about
2437 the results of the insn and a LOG_LINK pointing to the insn. */
2439 static void
2441 {
2442 /* For notes, be conservative and simply remove them. */
2445 /* The new insn will have a destination that was previously the destination
2446 of an insn just above it. Call distribute_links to make a LOG_LINK from
2447 the next use of that destination. */
2463 }
2465 /* Return TRUE if combine can reuse reg X in mode MODE.
2466 ADDED_SETS is nonzero if the original set is still required. */
2467 static bool
2469 {
2475 /* Don't change between modes with different underlying register sizes,
2476 since this could lead to invalid subregs. */
2482 /* Allow hard registers if the new mode is legal, and occupies no more
2483 registers than the old mode. */
2488 /* Or a pseudo that is only used once. */
2491 && !added_sets
2493 }
2496 /* Check whether X, the destination of a set, refers to part of
2497 the register specified by REG. */
2499 static bool
2501 {
2502 /* Check that reg is an integer mode register. */
2513 }
2515 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2516 Note that the INSN should be deleted *after* removing dead edges, so
2517 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2518 but not for a (set (pc) (label_ref FOO)). */
2520 static void
2522 {
2530 {
2535 /* Remove barriers from the footer if there are any. */
2538 {
2541 else
2545 }
2548 }
2549 }
2551 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2552 by an arbitrary number of CLOBBERs. */
2553 static bool
2555 {
2574 }
2576 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2577 CLOBBERs), can be split into individual SETs in that order, without
2578 changing semantics. */
2579 static bool
2581 {
2589 {
2598 }
2601 }
2603 /* Try to combine the insns I0, I1 and I2 into I3.
2604 Here I0, I1 and I2 appear earlier than I3.
2605 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2606 I3.
2608 If we are combining more than two insns and the resulting insn is not
2609 recognized, try splitting it into two insns. If that happens, I2 and I3
2610 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2611 Otherwise, I0, I1 and I2 are pseudo-deleted.
2613 Return 0 if the combination does not work. Then nothing is changed.
2614 If we did the combination, return the insn at which combine should
2615 resume scanning.
2617 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2618 new direct jump instruction.
2620 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2621 been I3 passed to an earlier try_combine within the same basic
2622 block. */
2627 {
2628 /* New patterns for I3 and I2, respectively. */
2632 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2633 dead. */
2635 /* Total number of SETs to put into I3. */
2637 /* Nonzero if I2's or I1's body now appears in I3. */
2639 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2641 /* Contains I3 if the destination of I3 is used in its source, which means
2642 that the old life of I3 is being killed. If that usage is placed into
2643 I2 and not in I3, a REG_DEAD note must be made. */
2645 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2647 /* Copy of SET_SRC of I1 and I0, if needed. */
2649 /* Set if I2DEST was reused as a scratch register. */
2651 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2653 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2658 /* Notes that must be added to REG_NOTES in I3 and I2. */
2660 /* Notes that we substituted I3 into I2 instead of the normal case. */
2662 /* Notes that I1, I2 or I3 is a MULT operation. */
2669 rtx temp_expr;
2672 rtx new_other_notes;
2676 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2677 never be). */
2681 /* Only try four-insn combinations when there's high likelihood of
2682 success. Look for simple insns, such as loads of constants or
2683 binary operations involving a constant. */
2685 {
2695 {
2698 rtx src;
2703 {
2706 }
2708 ngood++;
2711 nshift++;
2712 }
2714 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2715 are likely manipulating its value. Ideally we'll be able to combine
2716 all four insns into a bitfield insertion of some kind.
2718 Note the source in I0 might be inside a sign/zero extension and the
2719 memory modes in I0 and I3 might be different. So extract the address
2720 from the destination of I3 and search for it in the source of I0.
2722 In the event that there's a match but the source/dest do not actually
2723 refer to the same memory, the worst that happens is we try some
2724 combinations that we wouldn't have otherwise. */
2726 /* Ensure the source of SET0 is a MEM, possibly buried inside
2727 an extension. */
2733 /* Ensure the destination of SET3 is a MEM. */
2735 /* Would it be better to extract the base address for the MEM
2736 in SET3 and look for that? I don't have cases where it matters
2737 but I could envision such cases. */
2743 }
2745 /* Exit early if one of the insns involved can't be used for
2746 combinations. */
2757 combine_attempts++;
2760 /* Reset the hard register usage information. */
2764 {
2771 else
2774 }
2776 /* If multiple insns feed into one of I2 or I3, they can be in any
2777 order. To simplify the code below, reorder them in sequence. */
2787 /* First check for one important special case that the code below will
2788 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2789 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2790 we may be able to replace that destination with the destination of I3.
2791 This occurs in the common code where we compute both a quotient and
2792 remainder into a structure, in which case we want to do the computation
2793 directly into the structure to avoid register-register copies.
2795 Note that this case handles both multiple sets in I2 and also cases
2796 where I2 has a number of CLOBBERs inside the PARALLEL.
2798 We make very conservative checks below and only try to handle the
2799 most common cases of this. For example, we only handle the case
2800 where I2 and I3 are adjacent to avoid making difficult register
2801 usage tests. */
2809 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2810 below would need to check what is inside (and reg_overlap_mentioned_p
2811 doesn't support those codes anyway). Don't allow those destinations;
2812 the resulting insn isn't likely to be recognized anyway. */
2818 {
2821 /* Make sure that the destination of I3,
2822 which we are going to substitute into one output of I2,
2823 is not used within another output of I2. We must avoid making this:
2824 (parallel [(set (mem (reg 69)) ...)
2825 (set (reg 69) ...)])
2826 which is not well-defined as to order of actions.
2827 (Besides, reload can't handle output reloads for this.)
2829 The problem can also happen if the dest of I3 is a memory ref,
2830 if another dest in I2 is an indirect memory ref.
2832 Neither can this PARALLEL be an asm. We do not allow combining
2833 that usually (see can_combine_p), so do not here either. */
2836 {
2845 }
2851 {
2852 combine_merges++;
2862 /* Replace the dest in I2 with our dest and make the resulting
2863 insn the new pattern for I3. Then skip to where we validate
2864 the pattern. Everything was set up above. */
2869 }
2870 }
2872 /* If I2 is setting a pseudo to a constant and I3 is setting some
2873 sub-part of it to another constant, merge them by making a new
2874 constant. */
2882 {
2889 {
2894 {
2900 }
2901 }
2902 else
2903 {
2907 {
2910 }
2911 }
2914 {
2915 /* If this is the low part, we're done. */
2917 ;
2918 /* Handle the case where inner is twice the size of outer. */
2922 /* Otherwise give up for now. */
2923 else
2925 }
2928 {
2936 combine_merges++;
2943 /* Replace the source in I2 with the new constant and make the
2944 resulting insn the new pattern for I3. Then skip to where we
2945 validate the pattern. Everything was set up above. */
2951 /* The dest of I3 has been replaced with the dest of I2. */
2954 }
2955 }
2957 /* If we have no I1 and I2 looks like:
2958 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2959 (set Y OP)])
2960 make up a dummy I1 that is
2961 (set Y OP)
2962 and change I2 to be
2963 (set (reg:CC X) (compare:CC Y (const_int 0)))
2965 (We can ignore any trailing CLOBBERs.)
2967 This undoes a previous combination and allows us to match a branch-and-
2968 decrement insn. */
2980 {
2981 /* We make I1 with the same INSN_UID as I2. This gives it
2982 the same DF_INSN_LUID for value tracking. Our fake I1 will
2983 never appear in the insn stream so giving it the same INSN_UID
2984 as I2 will not cause a problem. */
2997 }
2999 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3000 make those two SETs separate I1 and I2 insns, and make an I0 that is
3001 the original I1. */
3007 {
3008 /* If there is no I1, there is no I0 either. */
3011 /* We make I1 with the same INSN_UID as I2. This gives it
3012 the same DF_INSN_LUID for value tracking. Our fake I1 will
3013 never appear in the insn stream so giving it the same INSN_UID
3014 as I2 will not cause a problem. */
3022 }
3024 /* Verify that I2 and I1 are valid for combining. */
3030 {
3033 }
3035 /* Record whether I2DEST is used in I2SRC and similarly for the other
3036 cases. Knowing this will help in register status updating below. */
3047 /* For the earlier insns, determine which of the subsequent ones they
3048 feed. */
3055 /* Ensure that I3's pattern can be the destination of combines. */
3061 {
3064 }
3066 /* See if any of the insns is a MULT operation. Unless one is, we will
3067 reject a combination that is, since it must be slower. Be conservative
3068 here. */
3076 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3077 We used to do this EXCEPT in one case: I3 has a post-inc in an
3078 output operand. However, that exception can give rise to insns like
3079 mov r3,(r3)+
3080 which is a famous insn on the PDP-11 where the value of r3 used as the
3081 source was model-dependent. Avoid this sort of thing. */
3083 #if 0
3089 /* It's not the exception. */
3090 #endif
3092 {
3093 rtx link;
3099 {
3102 }
3103 }
3105 /* See if the SETs in I1 or I2 need to be kept around in the merged
3106 instruction: whenever the value set there is still needed past I3.
3107 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3109 For the SET in I1, we have two cases: if I1 and I2 independently feed
3110 into I3, the set in I1 needs to be kept around unless I1DEST dies
3111 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3112 in I1 needs to be kept around unless I1DEST dies or is set in either
3113 I2 or I3. The same considerations apply to I0. */
3120 else
3128 else
3131 /* We are about to copy insns for the case where they need to be kept
3132 around. Check that they can be copied in the merged instruction. */
3138 {
3141 }
3143 /* If the set in I2 needs to be kept around, we must make a copy of
3144 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3145 PATTERN (I2), we are only substituting for the original I1DEST, not into
3146 an already-substituted copy. This also prevents making self-referential
3147 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3148 I2DEST. */
3151 {
3154 else
3156 }
3159 {
3162 else
3164 }
3167 {
3170 else
3172 }
3174 combine_merges++;
3176 /* Substitute in the latest insn for the regs set by the earlier ones. */
3182 /* Many machines that don't use CC0 have insns that can both perform an
3183 arithmetic operation and set the condition code. These operations will
3184 be represented as a PARALLEL with the first element of the vector
3185 being a COMPARE of an arithmetic operation with the constant zero.
3186 The second element of the vector will set some pseudo to the result
3187 of the same arithmetic operation. If we simplify the COMPARE, we won't
3188 match such a pattern and so will generate an extra insn. Here we test
3189 for this case, where both the comparison and the operation result are
3190 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3191 I2SRC. Later we will make the PARALLEL that contains I2. */
3197 {
3198 rtx newpat_dest;
3204 scalar_int_mode mode;
3213 {
3219 }
3221 /* Do the rest only if op1 is const0_rtx, which may be the
3222 result of simplification. */
3224 {
3225 /* If a single use of the CC is found, prepare to modify it
3226 when SELECT_CC_MODE returns a new CC-class mode, or when
3227 the above simplify_compare_const() returned a new comparison
3228 operator. undobuf.other_insn is assigned the CC use insn
3229 when modifying it. */
3231 {
3232 #ifdef SELECT_CC_MODE
3233 machine_mode new_mode
3238 {
3243 else
3244 {
3247 }
3248 }
3249 #endif
3250 /* Cases for modifying the CC-using comparison. */
3252 /* ??? Do we need to verify the zero rtx? */
3254 {
3255 /* Replace cc_use_loc with entire new RTX. */
3260 }
3262 {
3263 /* Just replace the CC reg with a new mode. */
3266 }
3267 }
3269 /* Now we modify the current newpat:
3270 First, SET_DEST(newpat) is updated if the CC mode has been
3271 altered. For targets without SELECT_CC_MODE, this should be
3272 optimized away. */
3275 /* This is always done to propagate i2src into newpat. */
3278 /* Create new version of i2pat if needed; the below PARALLEL
3279 creation needs this to work correctly. */
3283 }
3284 }
3287 {
3288 /* It is possible that the source of I2 or I1 may be performing
3289 an unneeded operation, such as a ZERO_EXTEND of something
3290 that is known to have the high part zero. Handle that case
3291 by letting subst look at the inner insns.
3293 Another way to do this would be to have a function that tries
3294 to simplify a single insn instead of merging two or more
3295 insns. We don't do this because of the potential of infinite
3296 loops and because of the potential extra memory required.
3297 However, doing it the way we are is a bit of a kludge and
3298 doesn't catch all cases.
3300 But only do this if -fexpensive-optimizations since it slows
3301 things down and doesn't usually win.
3303 This is not done in the COMPARE case above because the
3304 unmodified I2PAT is used in the PARALLEL and so a pattern
3305 with a modified I2SRC would not match. */
3308 {
3309 /* Pass pc_rtx so no substitutions are done, just
3310 simplifications. */
3312 {
3315 }
3319 }
3324 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3325 copy of I2SRC each time we substitute it, in order to avoid creating
3326 self-referential RTL when we will be substituting I1SRC for I1DEST
3327 later. Likewise if I0 feeds into I2, either directly or indirectly
3328 through I1, and I0DEST is in I0SRC. */
3335 /* Record whether I2's body now appears within I3's body. */
3337 }
3339 /* If we already got a failure, don't try to do more. Otherwise, try to
3340 substitute I1 if we have it. */
3343 {
3344 /* Check that an autoincrement side-effect on I1 has not been lost.
3345 This happens if I1DEST is mentioned in I2 and dies there, and
3346 has disappeared from the new pattern. */
3348 && i1_feeds_i2_n
3351 /* Before we can do this substitution, we must redo the test done
3352 above (see detailed comments there) that ensures I1DEST isn't
3353 mentioned in any SETs in NEWPAT that are field assignments. */
3356 {
3359 }
3364 /* If the following substitution will modify I1SRC, make a copy of it
3365 for the case where it is substituted for I1DEST in I2PAT later. */
3369 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3370 copy of I1SRC each time we substitute it, in order to avoid creating
3371 self-referential RTL when we will be substituting I0SRC for I0DEST
3372 later. */
3377 /* Record whether I1's body now appears within I3's body. */
3379 }
3381 /* Likewise for I0 if we have it. */
3384 {
3391 {
3394 }
3396 /* If the following substitution will modify I0SRC, make a copy of it
3397 for the case where it is substituted for I0DEST in I1PAT later. */
3400 /* And a copy for I0DEST in I2PAT substitution. */
3409 }
3411 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3412 to count all the ways that I2SRC and I1SRC can be used. */
3423 /* Fail if we tried to make a new register. */
3425 /* Fail if we couldn't do something and have a CLOBBER. */
3427 /* Fail if this new pattern is a MULT and we didn't have one before
3428 at the outer level. */
3431 {
3434 }
3436 /* If the actions of the earlier insns must be kept
3437 in addition to substituting them into the latest one,
3438 we must make a new PARALLEL for the latest insn
3439 to hold additional the SETs. */
3442 {
3444 combine_extras++;
3447 {
3453 }
3454 else
3455 {
3460 }
3466 {
3472 }
3474 {
3483 }
3484 }
3486 validate_replacement:
3488 /* Note which hard regs this insn has as inputs. */
3491 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3492 consider splitting this pattern, we might need these clobbers. */
3495 {
3501 }
3503 /* We have recognized nothing yet. */
3506 /* See if this is a PARALLEL of two SETs where one SET's destination is
3507 a register that is unused and this isn't marked as an instruction that
3508 might trap in an EH region. In that case, we just need the other SET.
3509 We prefer this over the PARALLEL.
3511 This can occur when simplifying a divmod insn. We *must* test for this
3512 case here because the code below that splits two independent SETs doesn't
3513 handle this case correctly when it updates the register status.
3515 It's pointless doing this if we originally had two sets, one from
3516 i3, and one from i2. Combining then splitting the parallel results
3517 in the original i2 again plus an invalid insn (which we delete).
3518 The net effect is only to move instructions around, which makes
3519 debug info less accurate.
3521 If the remaining SET came from I2 its destination should not be used
3522 between I2 and I3. See PR82024. */
3527 {
3538 {
3541 }
3550 {
3555 {
3561 }
3562 }
3566 }
3568 /* Is the result of combination a valid instruction? */
3572 /* If we were combining three insns and the result is a simple SET
3573 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3574 insns. There are two ways to do this. It can be split using a
3575 machine-specific method (like when you have an addition of a large
3576 constant) or by combine in the function find_split_point. */
3580 {
3584 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3585 use I2DEST as a scratch register will help. In the latter case,
3586 convert I2DEST to the mode of the source of NEWPAT if we can. */
3590 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3591 inputs of NEWPAT. */
3593 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3594 possible to try that as a scratch reg. This would require adding
3595 more code to make it work though. */
3598 {
3601 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3602 (temporarily, until we are committed to this instruction
3603 combination) does not work: for example, any call to nonzero_bits
3604 on the register (from a splitter in the MD file, for example)
3605 will get the old information, which is invalid.
3607 Since nowadays we can create registers during combine just fine,
3608 we should just create a new one here, not reuse i2dest. */
3610 /* First try to split using the original register as a
3611 scratch register. */
3615 i2dest)));
3618 /* If that didn't work, try changing the mode of I2DEST if
3619 we can. */
3624 {
3626 rtx ni2dest;
3630 else
3631 {
3634 }
3636 parallel = (gen_rtx_PARALLEL
3640 ni2dest))));
3645 {
3653 }
3654 }
3657 }
3659 /* If recog_for_combine has discarded clobbers, try to use them
3660 again for the split. */
3662 {
3665 }
3668 {
3673 }
3677 {
3687 /* If I2 or I3 has multiple SETs, we won't know how to track
3688 register status, so don't use these insns. If I2's destination
3689 is used between I2 and I3, we also can't use these insns. */
3699 /* It is possible that both insns now set the destination of I3.
3700 If so, we must show an extra use of it. */
3703 {
3722 }
3723 }
3725 /* If we can split it and use I2DEST, go ahead and see if that
3726 helps things be recognized. Verify that none of the registers
3727 are set between I2 and I3. */
3731 /* We need I2DEST in the proper mode. If it is a hard register
3732 or the only use of a pseudo, we can change its mode.
3733 Make sure we don't change a hard register to have a mode that
3734 isn't valid for it, or change the number of registers. */
3741 /* We can't overwrite I2DEST if its value is still used by
3742 NEWPAT. */
3744 {
3753 /* *SPLIT may be part of I2SRC, so make sure we have the
3754 original expression around for later debug processing.
3755 We should not need I2SRC any more in other cases. */
3758 else
3761 /* Get NEWDEST as a register in the proper mode. We have already
3762 validated that we can do this. */
3764 {
3767 else
3768 {
3771 }
3772 }
3774 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3775 an ASHIFT. This can occur if it was inside a PLUS and hence
3776 appeared to be a memory address. This is a kludge. */
3781 {
3784 /* Update split_code because we may not have a multiply
3785 anymore. */
3787 }
3789 /* Similarly for (plus (mult FOO (const_int pow2))). */
3795 {
3799 /* Update split_code because we may not have a multiply
3800 anymore. */
3802 }
3804 #ifdef INSN_SCHEDULING
3805 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3806 be written as a ZERO_EXTEND. */
3808 {
3809 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3810 what it really is. */
3815 else
3818 }
3819 #endif
3821 /* Attempt to split binary operators using arithmetic identities. */
3825 {
3832 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3834 {
3839 }
3840 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3847 {
3853 /* Split both "((X op Y) op X) op Y" and
3854 "((X op Y) op Y) op X" as "T op T" where T is
3855 "X op Y". */
3858 {
3863 }
3864 /* Split "((X op X) op Y) op Y)" as "T op T" where
3865 T is "X op Y". */
3867 {
3873 }
3874 }
3875 }
3878 {
3881 }
3885 /* recog_for_combine might have added CLOBBERs to newi2pat.
3886 Make sure NEWPAT does not depend on the clobbered regs. */
3890 {
3893 {
3896 }
3897 }
3899 /* If the split point was a MULT and we didn't have one before,
3900 don't use one now. */
3903 }
3904 }
3906 /* Check for a case where we loaded from memory in a narrow mode and
3907 then sign extended it, but we need both registers. In that case,
3908 we have a PARALLEL with both loads from the same memory location.
3909 We can split this into a load from memory followed by a register-register
3910 copy. This saves at least one insn, more if register allocation can
3911 eliminate the copy.
3913 We cannot do this if the destination of the first assignment is a
3914 condition code register or cc0. We eliminate this case by making sure
3915 the SET_DEST and SET_SRC have the same mode.
3917 We cannot do this if the destination of the second assignment is
3918 a register that we have already assumed is zero-extended. Similarly
3919 for a SUBREG of such a register. */
3954 {
3955 rtx ni2dest;
3969 }
3971 /* Similarly, check for a case where we have a PARALLEL of two independent
3972 SETs but we started with three insns. In this case, we can do the sets
3973 as two separate insns. This case occurs when some SET allows two
3974 other insns to combine, but the destination of that SET is still live.
3976 Also do this if we started with two insns and (at least) one of the
3977 resulting sets is a noop; this noop will be deleted later. */
3996 {
4000 /* Normally, it doesn't matter which of the two is done first,
4001 but the one that references cc0 can't be the second, and
4002 one which uses any regs/memory set in between i2 and i3 can't
4003 be first. The PARALLEL might also have been pre-existing in i3,
4004 so we need to make sure that we won't wrongly hoist a SET to i2
4005 that would conflict with a death note present in there. */
4013 /* If I3 is a jump, ensure that set0 is a jump so that
4014 we do not create invalid RTL. */
4016 )
4017 {
4020 }
4028 /* If I3 is a jump, ensure that set1 is a jump so that
4029 we do not create invalid RTL. */
4031 )
4032 {
4035 }
4036 else
4037 {
4040 }
4045 {
4046 /* recog_for_combine might have added CLOBBERs to newi2pat.
4047 Make sure NEWPAT does not depend on the clobbered regs. */
4049 {
4052 {
4055 {
4058 }
4059 }
4060 }
4063 }
4064 }
4066 /* If it still isn't recognized, fail and change things back the way they
4067 were. */
4069 /* Is the result a reasonable ASM_OPERANDS? */
4071 {
4074 }
4076 /* If we had to change another insn, make sure it is valid also. */
4078 {
4086 {
4089 }
4090 }
4092 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4093 they are adjacent to each other or not. */
4095 {
4099 {
4102 }
4103 }
4105 /* Only allow this combination if insn_cost reports that the
4106 replacement instructions are cheaper than the originals. */
4108 {
4111 }
4114 {
4119 {
4124 /* Temporarily revert mode back. */
4128 {
4129 /* If we used i2dest as a scratch register with a
4130 different mode, substitute it for the original
4131 i2src while its original mode is temporarily
4132 restored, and then clear i2scratch so that we don't
4133 do it again later. */
4135 this_basic_block);
4137 /* Put back the new mode. */
4139 }
4140 else
4141 {
4146 {
4149 }
4150 else
4151 {
4158 }
4160 /* We're dealing with a reg that changed mode but not
4161 meaning, so we want to turn it into a subreg for
4162 the new mode. However, because of REG sharing and
4163 because its mode had already changed, we have to do
4164 it in two steps. First, replace any debug uses of
4165 reg, with its original mode temporarily restored,
4166 with this copy we have created; then, replace the
4167 copy with the SUBREG of the original shared reg,
4168 once again changed to the new mode. */
4170 this_basic_block);
4174 this_basic_block);
4175 }
4176 }
4177 }
4179 /* If we will be able to accept this, we have made a
4180 change to the destination of I3. This requires us to
4181 do a few adjustments. */
4184 {
4187 }
4189 /* We now know that we can do this combination. Merge the insns and
4190 update the status of registers and LOG_LINKS. */
4193 {
4198 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4199 ensure that they are still valid. Then add any non-duplicate
4200 notes added by recog_for_combine. */
4202 {
4211 /* Simply drop equal note since it may be no longer valid
4212 for other_insn. It may be possible to record that CC
4213 register is changed and only discard those notes, but
4214 in practice it's unnecessary complication and doesn't
4215 give any meaningful improvement.
4217 See PR78559. */
4221 }
4225 NULL_RTX);
4226 }
4229 {
4232 rtx ni2dest;
4234 /* I3 now uses what used to be its destination and which is now
4235 I2's destination. This requires us to do a few adjustments. */
4239 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4240 so we still will.
4242 However, some later insn might be using I2's dest and have
4243 a LOG_LINK pointing at I3. We must remove this link.
4244 The simplest way to remove the link is to point it at I1,
4245 which we know will be a NOTE. */
4247 /* newi2pat is usually a SET here; however, recog_for_combine might
4248 have added some clobbers. */
4251 else
4258 {
4261 {
4267 }
4268 }
4269 }
4271 {
4276 /* Compute which registers we expect to eliminate. newi2pat may be setting
4277 either i3dest or i2dest, so we must check it. */
4280 || !i2dest_killed
4282 /* For i1, we need to compute both local elimination and global
4283 elimination information with respect to newi2pat because i1dest
4284 may be the same as i3dest, in which case newi2pat may be setting
4285 i1dest. Global information is used when distributing REG_DEAD
4286 note for i2 and i3, in which case it does matter if newi2pat sets
4287 i1dest or not.
4289 Local information is used when distributing REG_DEAD note for i1,
4290 in which case it doesn't matter if newi2pat sets i1dest or not.
4291 See PR62151, if we have four insns combination:
4292 i0: r0 <- i0src
4293 i1: r1 <- i1src (using r0)
4294 REG_DEAD (r0)
4295 i2: r0 <- i2src (using r1)
4296 i3: r3 <- i3src (using r0)
4297 ix: using r0
4298 From i1's point of view, r0 is eliminated, no matter if it is set
4299 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4300 should be discarded.
4302 Note local information only affects cases in forms like "I1->I2->I3",
4303 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4304 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4305 i0dest anyway. */
4307 || !i1dest_killed
4312 /* Same case as i1. */
4319 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4320 clear them. */
4328 /* Ensure that we do not have something that should not be shared but
4329 occurs multiple times in the new insns. Check this by first
4330 resetting all the `used' flags and then copying anything is shared. */
4354 {
4357 {
4359 {
4360 /* I2SRC must still be meaningful at this point. Some
4361 splitting operations can invalidate I2SRC, but those
4362 operations do not apply to calls. */
4366 }
4373 }
4374 }
4379 /* We had one special case above where I2 had more than one set and
4380 we replaced a destination of one of those sets with the destination
4381 of I3. In that case, we have to update LOG_LINKS of insns later
4382 in this basic block. Note that this (expensive) case is rare.
4384 Also, in this case, we must pretend that all REG_NOTEs for I2
4385 actually came from I3, so that REG_UNUSED notes from I2 will be
4386 properly handled. */
4389 {
4398 temp_insn
4408 {
4413 }
4414 else
4417 }
4425 {
4428 this_basic_block);
4431 }
4432 else
4433 {
4436 this_basic_block);
4438 }
4441 {
4446 this_basic_block);
4448 }
4451 {
4456 this_basic_block);
4458 }
4460 /* Get death notes for everything that is now used in either I3 or
4461 I2 and used to die in a previous insn. If we built two new
4462 patterns, move from I1 to I2 then I2 to I3 so that we get the
4463 proper movement on registers that I2 modifies. */
4469 else
4475 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4492 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4493 know these are REG_UNUSED and want them to go to the desired insn,
4494 so we always pass it as i3. */
4498 NULL_RTX);
4502 NULL_RTX);
4504 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4505 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4506 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4507 in that case, it might delete I2. Similarly for I2 and I1.
4508 Show an additional death due to the REG_DEAD note we make here. If
4509 we discard it in distribute_notes, we will decrement it again. */
4512 {
4517 else
4520 }
4523 {
4528 else
4531 }
4534 {
4539 else
4542 }
4545 {
4550 else
4553 }
4561 {
4566 /* The insn that used to set this register doesn't exist, and
4567 this life of the register may not exist either. See if one of
4568 I3's links points to an insn that sets I2DEST. If it does,
4569 that is now the last known value for I2DEST. If we don't update
4570 this and I2 set the register to a value that depended on its old
4571 contents, we will get confused. If this insn is used, thing
4572 will be set correctly in combine_instructions. */
4580 /* If the reg formerly set in I2 died only once and that was in I3,
4581 zero its use count so it won't make `reload' do any work. */
4584 && ! i2dest_in_i2src
4587 }
4590 {
4603 && ! i1dest_in_i1src
4606 }
4609 {
4622 && ! i0dest_in_i0src
4625 }
4627 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4628 been made to this insn. The order is important, because newi2pat
4629 can affect nonzero_bits of newpat. */
4633 }
4636 {
4638 {
4641 }
4643 }
4646 {
4648 {
4651 }
4653 }
4656 {
4658 {
4661 }
4663 }
4666 {
4668 {
4671 }
4673 }
4676 {
4678 {
4681 }
4683 }
4685 /* Set new_direct_jump_p if a new return or simple jump instruction
4686 has been created. Adjust the CFG accordingly. */
4688 {
4692 }
4697 {
4700 }
4704 {
4710 }
4715 {
4721 }
4723 /* A noop might also need cleaning up of CFG, if it comes from the
4724 simplification of a jump. */
4729 {
4732 }
4739 {
4742 }
4744 combine_successes++;
4751 else
4753 }
4754 \f
4755 /* Get a marker for undoing to the current state. */
4759 {
4761 }
4763 /* Undo the modifications up to the marker. */
4765 static void
4767 {
4771 {
4776 {
4791 }
4795 }
4798 }
4800 /* Undo all the modifications recorded in undobuf. */
4802 static void
4804 {
4806 }
4808 /* We've committed to accepting the changes we made. Move all
4809 of the undos to the free list. */
4811 static void
4813 {
4817 {
4821 }
4823 }
4824 \f
4825 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4826 where we have an arithmetic expression and return that point. LOC will
4827 be inside INSN.
4829 try_combine will call this function to see if an insn can be split into
4830 two insns. */
4834 {
4844 /* First special-case some codes. */
4846 {
4848 #ifdef INSN_SCHEDULING
4849 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4850 point. */
4853 #endif
4857 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4858 using LO_SUM and HIGH. */
4861 {
4869 }
4871 /* If we have a PLUS whose second operand is a constant and the
4872 address is not valid, perhaps will can split it up using
4873 the machine-specific way to split large constants. We use
4874 the first pseudo-reg (one of the virtual regs) as a placeholder;
4875 it will not remain in the result. */
4880 {
4883 subst_insn);
4885 /* This should have produced two insns, each of which sets our
4886 placeholder. If the source of the second is a valid address,
4887 we can make put both sources together and make a split point
4888 in the middle. */
4901 && memory_address_addr_space_p
4904 {
4908 /* Replace the placeholder in SRC2 with SRC1. If we can
4909 find where in SRC2 it was placed, that can become our
4910 split point and we can replace this address with SRC2.
4911 Just try two obvious places. */
4922 {
4925 }
4926 }
4928 /* If that didn't work, perhaps the first operand is complex and
4929 needs to be computed separately, so make a split point there.
4930 This will occur on machines that just support REG + CONST
4931 and have a constant moved through some previous computation. */
4937 }
4939 /* If we have a PLUS whose first operand is complex, try computing it
4940 separately by making a split there. */
4951 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4952 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4953 we need to put the operand into a register. So split at that
4954 point. */
4964 /* See if we can split SET_SRC as it stands. */
4969 /* See if we can split SET_DEST as it stands. */
4974 /* See if this is a bitfield assignment with everything constant. If
4975 so, this is an IOR of an AND, so split it into that. */
4987 {
4992 unsigned HOST_WIDE_INT mask
4994 rtx or_mask;
5003 else
5004 {
5010 or_mask));
5011 }
5018 }
5020 /* Otherwise, see if this is an operation that we can split into two.
5021 If so, try to split that. */
5025 {
5027 /* If we are AND'ing with a large constant that is only a single
5028 bit and the result is only being used in a context where we
5029 need to know if it is zero or nonzero, replace it with a bit
5030 extraction. This will avoid the large constant, which might
5031 have taken more than one insn to make. If the constant were
5032 not a valid argument to the AND but took only one insn to make,
5033 this is no worse, but if it took more than one insn, it will
5034 be better. */
5044 {
5049 {
5052 }
5053 }
5057 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5058 is known to be on, this can be converted into a NEG of a shift. */
5064 {
5076 }
5082 /* We can't optimize if either mode is a partial integer
5083 mode as we don't know how many bits are significant
5084 in those modes. */
5100 {
5108 }
5113 }
5118 {
5119 /* For unsigned, we have a choice of a shift followed by an
5120 AND or two shifts. Use two shifts for field sizes where the
5121 constant might be too large. We assume here that we can
5122 always at least get 8-bit constants in an AND insn, which is
5123 true for every current RISC. */
5126 {
5127 unsigned HOST_WIDE_INT mask
5131 gen_rtx_LSHIFTRT
5139 }
5140 else
5141 {
5143 gen_rtx_fmt_ee
5154 }
5155 }
5157 /* See if this is a simple operation with a constant as the second
5158 operand. It might be that this constant is out of range and hence
5159 could be used as a split point. */
5167 /* Finally, see if this is a simple operation with its first operand
5168 not in a register. The operation might require this operand in a
5169 register, so return it as a split point. We can always do this
5170 because if the first operand were another operation, we would have
5171 already found it as a split point. */
5180 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5181 it is better to write this as (not (ior A B)) so we can split it.
5182 Similarly for IOR. */
5184 {
5192 }
5194 /* Many RISC machines have a large set of logical insns. If the
5195 second operand is a NOT, put it first so we will try to split the
5196 other operand first. */
5198 {
5202 }
5207 /* Canonicalization can produce (minus A (mult B C)), where C is a
5208 constant. It may be better to try splitting (plus (mult B -C) A)
5209 instead if this isn't a multiply by a power of two. */
5213 {
5221 mode)),
5224 }
5226 /* Split at a multiply-accumulate instruction. However if this is
5227 the SET_SRC, we likely do not have such an instruction and it's
5228 worthless to try this split. */
5237 }
5239 /* Otherwise, select our actions depending on our rtx class. */
5241 {
5247 /* fall through */
5255 /* fall through */
5257 /* Some machines have (and (shift ...) ...) insns. If X is not
5258 an AND, but XEXP (X, 0) is, use it as our split point. */
5268 /* Otherwise, we don't have a split point. */
5270 }
5271 }
5272 \f
5273 /* Throughout X, replace FROM with TO, and return the result.
5274 The result is TO if X is FROM;
5275 otherwise the result is X, but its contents may have been modified.
5276 If they were modified, a record was made in undobuf so that
5277 undo_all will (among other things) return X to its original state.
5279 If the number of changes necessary is too much to record to undo,
5280 the excess changes are not made, so the result is invalid.
5281 The changes already made can still be undone.
5282 undobuf.num_undo is incremented for such changes, so by testing that
5283 the caller can tell whether the result is valid.
5285 `n_occurrences' is incremented each time FROM is replaced.
5287 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5289 IN_COND is nonzero if we are at the top level of a condition.
5291 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5292 by copying if `n_occurrences' is nonzero. */
5294 static rtx
5296 {
5301 rtx new_rtx;
5303 /* Two expressions are equal if they are identical copies of a shared
5304 RTX or if they are both registers with the same register number
5305 and mode. */
5307 #define COMBINE_RTX_EQUAL_P(X,Y) \
5308 ((X) == (Y) \
5309 || (REG_P (X) && REG_P (Y) \
5310 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5312 /* Do not substitute into clobbers of regs -- this will never result in
5313 valid RTL. */
5318 {
5319 n_occurrences++;
5321 }
5323 /* If X and FROM are the same register but different modes, they
5324 will not have been seen as equal above. However, the log links code
5325 will make a LOG_LINKS entry for that case. If we do nothing, we
5326 will try to rerecognize our original insn and, when it succeeds,
5327 we will delete the feeding insn, which is incorrect.
5329 So force this insn not to match in this (rare) case. */
5334 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5335 of which may contain things that can be combined. */
5339 /* It is possible to have a subexpression appear twice in the insn.
5340 Suppose that FROM is a register that appears within TO.
5341 Then, after that subexpression has been scanned once by `subst',
5342 the second time it is scanned, TO may be found. If we were
5343 to scan TO here, we would find FROM within it and create a
5344 self-referent rtl structure which is completely wrong. */
5348 /* Parallel asm_operands need special attention because all of the
5349 inputs are shared across the arms. Furthermore, unsharing the
5350 rtl results in recognition failures. Failure to handle this case
5351 specially can result in circular rtl.
5353 Solve this by doing a normal pass across the first entry of the
5354 parallel, and only processing the SET_DESTs of the subsequent
5355 entries. Ug. */
5360 {
5363 /* If this substitution failed, this whole thing fails. */
5371 {
5377 {
5380 /* If this substitution failed, this whole thing fails. */
5386 }
5387 }
5388 }
5389 else
5390 {
5394 /* We don't need to process a SET_DEST that is a register, CC0,
5395 or PC, so set up to skip this common case. All other cases
5396 where we want to suppress replacing something inside a
5397 SET_SRC are handled via the IN_DEST operand. */
5404 /* Trying to simplify the operands of a widening MULT is not likely
5405 to create RTL matching a machine insn. */
5417 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5418 constant. */
5423 {
5425 {
5428 {
5430 {
5433 n_occurrences++;
5434 }
5435 else
5436 {
5438 unique_copy);
5440 /* If this substitution failed, this whole thing
5441 fails. */
5445 }
5448 }
5449 }
5451 {
5452 /* If this is a register being set, ignore it. */
5459 ;
5462 {
5463 /* In general, don't install a subreg involving two
5464 modes not tieable. It can worsen register
5465 allocation, and can even make invalid reload
5466 insns, since the reg inside may need to be copied
5467 from in the outside mode, and that may be invalid
5468 if it is an fp reg copied in integer mode.
5470 We allow two exceptions to this: It is valid if
5471 it is inside another SUBREG and the mode of that
5472 SUBREG and the mode of the inside of TO is
5473 tieable and it is valid if X is a SET that copies
5474 FROM to CC0. */
5482 && (!HAVE_cc0
5497 n_occurrences++;
5498 }
5499 else
5500 /* If we are in a SET_DEST, suppress most cases unless we
5501 have gone inside a MEM, in which case we want to
5502 simplify the address. We assume here that things that
5503 are actually part of the destination have their inner
5504 parts in the first expression. This is true for SUBREG,
5505 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5506 things aside from REG and MEM that should appear in a
5507 SET_DEST. */
5509 (((in_dest
5515 unique_copy);
5517 /* If we found that we will have to reject this combination,
5518 indicate that by returning the CLOBBER ourselves, rather than
5519 an expression containing it. This will speed things up as
5520 well as prevent accidents where two CLOBBERs are considered
5521 to be equal, thus producing an incorrect simplification. */
5527 {
5535 }
5538 {
5542 }
5543 else
5545 }
5546 }
5547 }
5549 /* Check if we are loading something from the constant pool via float
5550 extension; in this case we would undo compress_float_constant
5551 optimization and degenerate constant load to an immediate value. */
5555 {
5559 }
5561 /* Try to simplify X. If the simplification changed the code, it is likely
5562 that further simplification will help, so loop, but limit the number
5563 of repetitions that will be performed. */
5566 {
5567 /* If X is sufficiently simple, don't bother trying to do anything
5568 with it. */
5577 /* We no longer know the original mode of operand 0 since we
5578 have changed the form of X) */
5580 }
5583 }
5584 \f
5585 /* If X is a commutative operation whose operands are not in the canonical
5586 order, use substitutions to swap them. */
5588 static void
5590 {
5593 {
5597 }
5598 }
5600 /* Simplify X, a piece of RTL. We just operate on the expression at the
5601 outer level; call `subst' to simplify recursively. Return the new
5602 expression.
5604 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5605 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5606 of a condition. */
5608 static rtx
5611 {
5614 scalar_int_mode int_mode;
5615 rtx temp;
5618 /* If this is a commutative operation, put a constant last and a complex
5619 expression first. We don't need to do this for comparisons here. */
5622 /* Try to fold this expression in case we have constants that weren't
5623 present before. */
5626 {
5634 {
5637 {
5641 }
5644 }
5657 }
5660 {
5665 }
5667 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5668 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5669 things. Check for cases where both arms are testing the same
5670 condition.
5672 Don't do anything if all operands are very simple. */
5685 {
5690 /* If everything is a comparison, what we have is highly unlikely
5691 to be simpler, so don't use it. */
5694 {
5701 /* Simplify the alternative arms; this may collapse the true and
5702 false arms to store-flag values. Be careful to use copy_rtx
5703 here since true_rtx or false_rtx might share RTL with x as a
5704 result of the if_then_else_cond call above. */
5708 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5709 is unlikely to be simpler. */
5712 {
5715 /* Restarting if we generate a store-flag expression will cause
5716 us to loop. Just drop through in this case. */
5718 /* If the result values are STORE_FLAG_VALUE and zero, we can
5719 just make the comparison operation. */
5730 /* Likewise, we can make the negate of a comparison operation
5731 if the result values are - STORE_FLAG_VALUE and zero. */
5739 mode);
5750 mode);
5751 else
5754 mode,
5755 VOIDmode,
5756 cond,
5757 cop1),
5762 }
5763 }
5764 }
5766 /* First see if we can apply the inverse distributive law. */
5769 {
5773 }
5775 /* If CODE is an associative operation not otherwise handled, see if we
5776 can associate some operands. This can win if they are constants or
5777 if they are logically related (i.e. (a & b) & a). */
5783 {
5785 {
5789 rtx inner;
5791 /* Make sure we pass the constant operand if any as the second
5792 one if this is a commutative operation. */
5800 /* For commutative operations, try the other pair if that one
5801 didn't simplify. */
5803 {
5808 }
5812 }
5813 }
5815 /* A little bit of algebraic simplification here. */
5817 {
5819 /* Ensure that our address has any ASHIFTs converted to MULT in case
5820 address-recognizing predicates are called later. */
5829 /* See if this can be moved to simplify_subreg. */
5832 /* Don't call gen_lowpart if the inner mode
5833 is VOIDmode and we cannot simplify it, as SUBREG without
5834 inner mode is invalid. */
5841 {
5842 rtx temp;
5848 /* If op is known to have all lower bits zero, the result is zero. */
5861 }
5863 /* Don't change the mode of the MEM if that would change the meaning
5864 of the address. */
5871 /* Note that we cannot do any narrowing for non-constants since
5872 we might have been counting on using the fact that some bits were
5873 zero. We now do this in the SET. */
5880 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5881 replaced by (lshiftrt X C). This will convert
5882 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5890 /* If X has only a single bit that might be nonzero, say, bit I, convert
5891 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5892 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5893 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5894 or a SUBREG of one since we'd be making the expression more
5895 complex if it was just a register. */
5902 {
5903 rtx temp1 = simplify_shift_const
5909 /* If all we did was surround TEMP with the two shifts, we
5910 haven't improved anything, so don't use it. Otherwise,
5911 we are better off with TEMP1. */
5916 }
5920 /* We can't handle truncation to a partial integer mode here
5921 because we don't know the real bitsize of the partial
5922 integer mode. */
5931 /* We can truncate a constant value and return it. */
5935 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5936 whose value is a comparison can be replaced with a subreg if
5937 STORE_FLAG_VALUE permits. */
5946 /* (const (const X)) can become (const X). Do it this way rather than
5947 returning the inner CONST since CONST can be shared with a
5948 REG_EQUAL note. */
5954 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5955 can add in an offset. find_split_point will split this address up
5956 again if it doesn't match. */
5963 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5964 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5965 bit-field and can be replaced by either a sign_extend or a
5966 sign_extract. The `and' may be a zero_extend and the two
5967 <c>, -<c> constants may be reversed. */
5983 return simplify_shift_const
5990 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5991 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5992 the bitsize of the mode - 1. This allows simplification of
5993 "a = (b & 8) == 0;" */
6000 return simplify_shift_const
6004 const1_rtx),
6008 /* If we are adding two things that have no bits in common, convert
6009 the addition into an IOR. This will often be further simplified,
6010 for example in cases like ((a & 1) + (a & 2)), which can
6011 become a & 3. */
6016 {
6017 /* Try to simplify the expression further. */
6021 /* If we could, great. If not, do not go ahead with the IOR
6022 replacement, since PLUS appears in many special purpose
6023 address arithmetic instructions. */
6031 }
6033 /* Canonicalize x + x into x << 1. */
6042 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6043 (and <foo> (const_int pow2-1)) */
6054 /* If we have (mult (plus A B) C), apply the distributive law and then
6055 the inverse distributive law to see if things simplify. This
6056 occurs mostly in addresses, often when unrolling loops. */
6059 {
6063 }
6065 /* Try simplify a*(b/c) as (a*b)/c. */
6068 {
6074 }
6078 /* If this is a divide by a power of two, treat it as a shift if
6079 its first operand is a shift. */
6099 /* If the first operand is a condition code, we can't do anything
6100 with it. */
6104 {
6112 /* Simplify our comparison, if possible. */
6115 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6116 if only the low-order bit is possibly nonzero in X (such as when
6117 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6118 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6119 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6120 (plus X 1).
6122 Remove any ZERO_EXTRACT we made when thinking this was a
6123 comparison. It may now be simpler to use, e.g., an AND. If a
6124 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6125 the call to make_compound_operation in the SET case.
6127 Don't apply these optimizations if the caller would
6128 prefer a comparison rather than a value.
6129 E.g., for the condition in an IF_THEN_ELSE most targets need
6130 an explicit comparison. */
6133 ;
6151 {
6155 int_mode);
6156 }
6164 {
6168 const1_rtx);
6169 }
6178 {
6181 }
6183 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6184 those above. */
6186 ;
6203 {
6207 int_mode);
6208 }
6217 {
6221 int_mode);
6222 }
6224 /* If X is 0/1, (eq X 0) is X-1. */
6231 {
6234 }
6236 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6237 one bit that might be nonzero, we can convert (ne x 0) to
6238 (ashift x c) where C puts the bit in the sign bit. Remove any
6239 AND with STORE_FLAG_VALUE when we are done, since we are only
6240 going to test the sign bit. */
6248 {
6254 else
6256 }
6258 /* If the code changed, return a whole new comparison.
6259 We also need to avoid using SUBST in cases where
6260 simplify_comparison has widened a comparison with a CONST_INT,
6261 since in that case the wider CONST_INT may fail the sanity
6262 checks in do_SUBST. */
6269 /* Otherwise, keep this operation, but maybe change its operands.
6270 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6273 }
6283 /* If we are processing SET_DEST, we are done. */
6301 /* If this is a shift by a constant amount, simplify it. */
6309 (HOST_WIDE_INT_1U
6318 }
6321 }
6322 \f
6323 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6325 static rtx
6327 {
6334 rtx temp;
6337 rtx reversed;
6340 /* Simplify storing of the truth value. */
6345 /* Also when the truth value has to be reversed. */
6351 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6352 in it is being compared against certain values. Get the true and false
6353 comparisons and see if that says anything about the value of each arm. */
6359 {
6360 HOST_WIDE_INT nzb;
6366 /* If FALSE_CODE is EQ, swap the codes and arms. */
6369 {
6372 }
6374 scalar_int_mode from_mode;
6376 {
6377 /* If we are comparing against zero and the expression being
6378 tested has only a single bit that might be nonzero, that is
6379 its value when it is not equal to zero. Similarly if it is
6380 known to be -1 or 0. */
6384 {
6387 }
6392 {
6395 }
6396 }
6398 /* Now simplify an arm if we know the value of the register in the
6399 branch and it is used in the arm. Be careful due to the potential
6400 of locally-shared RTL. */
6417 }
6419 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6420 reversed, do so to avoid needing two sets of patterns for
6421 subtract-and-branch insns. Similarly if we have a constant in the true
6422 arm, the false arm is the same as the first operand of the comparison, or
6423 the false arm is more complicated than the true arm. */
6436 {
6445 /* It is possible that the conditional has been simplified out. */
6448 }
6450 /* If the two arms are identical, we don't need the comparison. */
6455 /* Convert a == b ? b : a to "a". */
6467 /* Look for cases where we have (abs x) or (neg (abs X)). */
6470 && comparison_p
6477 {
6483 return
6486 mode);
6489 }
6491 /* Look for MIN or MAX. */
6494 && comparison_p
6499 {
6514 }
6516 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6517 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6518 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6519 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6520 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6521 neither 1 or -1, but it isn't worth checking for. */
6524 && comparison_p
6527 {
6543 /* If an identity-zero op is commutative, check whether there
6544 would be a match if we swapped the operands. */
6565 {
6569 }
6582 {
6586 }
6603 {
6607 }
6620 {
6624 }
6627 {
6633 const_true_rtx));
6641 }
6642 }
6644 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6645 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6646 negation of a single bit, we can convert this operation to a shift. We
6647 can actually do this more generally, but it doesn't seem worth it. */
6659 return
6663 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6664 non-zero bit in A is C1. */
6672 {
6678 }
6681 }
6682 \f
6683 /* Simplify X, a SET expression. Return the new expression. */
6685 static rtx
6687 {
6690 machine_mode mode
6694 scalar_int_mode int_mode;
6696 /* (set (pc) (return)) gets written as (return). */
6700 /* Now that we know for sure which bits of SRC we are using, see if we can
6701 simplify the expression for the object knowing that we only need the
6702 low-order bits. */
6705 {
6708 }
6710 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6711 the comparison result and try to simplify it unless we already have used
6712 undobuf.other_insn. */
6720 {
6729 {
6732 {
6735 }
6736 }
6737 else
6745 {
6749 }
6750 else
6751 {
6756 /* Attempt to simplify CC user. */
6758 {
6762 }
6764 /* Convert X into a no-op move. */
6768 }
6770 /* Simplify our comparison, if possible. */
6773 #ifdef SELECT_CC_MODE
6774 /* If this machine has CC modes other than CCmode, check to see if we
6775 need to use a different CC mode here. */
6784 else
6787 /* If the mode changed, we have to change SET_DEST, the mode in the
6788 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6789 a hard register, just build new versions with the proper mode. If it
6790 is a pseudo, we lose unless it is only time we set the pseudo, in
6791 which case we can safely change its mode. */
6793 {
6795 {
6797 rtx new_dest;
6801 else
6802 {
6805 }
6812 }
6813 }
6816 /* If the code changed, we have to build a new comparison in
6817 undobuf.other_insn. */
6819 {
6828 /* If the only change we made was to change an EQ into an NE or
6829 vice versa, OP0 has only one bit that might be nonzero, and OP1
6830 is zero, check if changing the user of the condition code will
6831 produce a valid insn. If it won't, we can keep the original code
6832 in that insn by surrounding our operation with an XOR. */
6839 {
6844 {
6851 }
6852 }
6853 }
6858 /* Don't generate a compare of a CC with 0, just use that CC. */
6860 {
6863 }
6864 /* Otherwise, if we didn't previously have the same COMPARE we
6865 want, create it from scratch. */
6868 {
6871 }
6872 }
6873 else
6874 {
6875 /* Get SET_SRC in a form where we have placed back any
6876 compound expressions. Then do the checks below. */
6879 }
6881 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6882 and X being a REG or (subreg (reg)), we may be able to convert this to
6883 (set (subreg:m2 x) (op)).
6885 We can always do this if M1 is narrower than M2 because that means that
6886 we only care about the low bits of the result.
6888 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6889 perform a narrower operation than requested since the high-order bits will
6890 be undefined. On machine where it is defined, this transformation is safe
6891 as long as M1 and M2 have the same number of words. */
6907 {
6910 dest));
6914 }
6916 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6917 in SRC. */
6921 {
6925 /* Here we make sure that we don't have a sign bit on. */
6928 {
6931 }
6932 }
6934 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6935 would require a paradoxical subreg. Replace the subreg with a
6936 zero_extend to avoid the reload that would otherwise be required. */
6942 {
6947 }
6949 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6950 are comparing an item known to be 0 or -1 against 0, use a logical
6951 operation instead. Check for one of the arms being an IOR of the other
6952 arm with some value. We compute three terms to be IOR'ed together. In
6953 practice, at most two will be nonzero. Then we do the IOR's. */
6961 && (!HAVE_conditional_move
6966 {
6991 int_mode),
6992 false_rtx);
6998 term3));
7001 }
7003 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7004 whole thing fail. */
7009 else
7010 /* Convert this into a field assignment operation, if possible. */
7012 }
7013 \f
7014 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7015 result. */
7017 static rtx
7019 {
7022 scalar_int_mode mode;
7025 {
7027 /* We can call simplify_and_const_int only if we don't lose
7028 any (sign) bits when converting INTVAL (op1) to
7029 "unsigned HOST_WIDE_INT". */
7034 {
7041 }
7043 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7044 apply the distributive law and then the inverse distributive
7045 law to see if things simplify. */
7047 {
7051 }
7053 {
7057 }
7061 /* If we have (ior (and A B) C), apply the distributive law and then
7062 the inverse distributive law to see if things simplify. */
7065 {
7069 }
7072 {
7076 }
7081 }
7084 }
7085 \f
7086 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7087 operations" because they can be replaced with two more basic operations.
7088 ZERO_EXTEND is also considered "compound" because it can be replaced with
7089 an AND operation, which is simpler, though only one operation.
7091 The function expand_compound_operation is called with an rtx expression
7092 and will convert it to the appropriate shifts and AND operations,
7093 simplifying at each stage.
7095 The function make_compound_operation is called to convert an expression
7096 consisting of shifts and ANDs into the equivalent compound expression.
7097 It is the inverse of this function, loosely speaking. */
7099 static rtx
7101 {
7105 rtx tem;
7106 scalar_int_mode inner_mode;
7109 {
7112 /* FALLTHRU */
7114 /* We can't necessarily use a const_int for a multiword mode;
7115 it depends on implicitly extending the value.
7116 Since we don't know the right way to extend it,
7117 we can't tell whether the implicit way is right.
7119 Even for a mode that is no wider than a const_int,
7120 we can't win, because we need to sign extend one of its bits through
7121 the rest of it, and we don't know which bit. */
7125 /* Reject modes that aren't scalar integers because turning vector
7126 or complex modes into shifts causes problems. */
7130 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7131 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7132 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7133 reloaded. If not for that, MEM's would very rarely be safe.
7135 Reject modes bigger than a word, because we might not be able
7136 to reference a two-register group starting with an arbitrary register
7137 (and currently gen_lowpart might crash for a SUBREG). */
7143 /* If the inner object has VOIDmode (the only way this can happen
7144 is if it is an ASM_OPERANDS), we can't do anything since we don't
7145 know how much masking to do. */
7154 /* fall through */
7157 /* If the operand is a CLOBBER, just return it. */
7165 /* Reject modes that aren't scalar integers because turning vector
7166 or complex modes into shifts causes problems. */
7173 /* This should stay within the object being extracted, fail otherwise. */
7184 }
7186 /* We've rejected non-scalar operations by now. */
7189 /* Convert sign extension to zero extension, if we know that the high
7190 bit is not set, as this is easier to optimize. It will be converted
7191 back to cheaper alternative in make_extraction. */
7197 {
7201 /* Make sure this is a profitable operation. */
7208 else
7210 }
7212 /* We can optimize some special cases of ZERO_EXTEND. */
7214 {
7215 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7216 know that the last value didn't have any inappropriate bits
7217 set. */
7225 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7234 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7235 is a comparison and STORE_FLAG_VALUE permits. This is like
7236 the first case, but it works even when MODE is larger
7237 than HOST_WIDE_INT. */
7245 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7254 }
7256 /* If we reach here, we want to return a pair of shifts. The inner
7257 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7258 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7259 logical depending on the value of UNSIGNEDP.
7261 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7262 converted into an AND of a shift.
7264 We must check for the case where the left shift would have a negative
7265 count. This can happen in a case like (x >> 31) & 255 on machines
7266 that can't shift by a constant. On those machines, we would first
7267 combine the shift with the AND to produce a variable-position
7268 extraction. Then the constant of 31 would be substituted in
7269 to produce such a position. */
7273 {
7281 }
7286 pos),
7288 else
7289 /* Any other cases we can't handle. */
7292 /* If we couldn't do this for some reason, return the original
7293 expression. */
7298 }
7299 \f
7300 /* X is a SET which contains an assignment of one object into
7301 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7302 or certain SUBREGS). If possible, convert it into a series of
7303 logical operations.
7305 We half-heartedly support variable positions, but do not at all
7306 support variable lengths. */
7308 static const_rtx
7310 {
7311 rtx inner;
7315 scalar_int_mode compute_mode;
7317 /* Loop until we find something we can't simplify. */
7319 {
7322 {
7326 }
7329 {
7334 /* A constant position should stay within the width of INNER. */
7340 {
7348 /* If position is ADJUST - X, new position is X. */
7350 else
7351 {
7356 pos);
7357 }
7358 }
7359 }
7361 /* If the destination is a subreg that overwrites the whole of the inner
7362 register, we can move the subreg to the source. */
7364 /* We need SUBREGs to compute nonzero_bits properly. */
7365 && nonzero_sign_valid
7367 {
7369 gen_lowpart
7373 }
7374 else
7380 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7382 {
7383 /* Don't do anything for vector or complex integral types. */
7387 /* Try to find an integral mode to pun with. */
7393 }
7395 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7399 /* Don't try to compute in too wide unsupported modes. */
7403 /* Now compute the equivalent expression. Make a copy of INNER
7404 for the SET_DEST in case it is a MEM into which we will substitute;
7405 we don't want shared RTL in that case. */
7407 compute_mode);
7411 compute_mode,
7413 compute_mode),
7414 inner);
7419 mask),
7420 pos);
7425 }
7428 }
7429 \f
7430 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7431 it is an RTX that represents the (variable) starting position; otherwise,
7432 POS is the (constant) starting bit position. Both are counted from the LSB.
7434 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7436 IN_DEST is nonzero if this is a reference in the destination of a SET.
7437 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7438 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7439 be used.
7441 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7442 ZERO_EXTRACT should be built even for bits starting at bit 0.
7444 MODE is the desired mode of the result (if IN_DEST == 0).
7446 The result is an RTX for the extraction or NULL_RTX if the target
7447 can't handle it. */
7449 static rtx
7453 {
7454 /* This mode describes the size of the storage area
7455 to fetch the overall value from. Within that, we
7456 ignore the POS lowest bits, etc. */
7458 machine_mode inner_mode;
7459 scalar_int_mode wanted_inner_mode;
7465 HOST_WIDE_INT orig_pos;
7473 /* If trying or potentionally trying to extract
7474 bits outside of is_mode, don't look through
7475 non-paradoxical SUBREGs. See PR82192. */
7478 {
7479 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7480 consider just the QI as the memory to extract from.
7481 The subreg adds or removes high bits; its mode is
7482 irrelevant to the meaning of this extraction,
7483 since POS and LEN count from the lsb. */
7487 }
7492 {
7493 /* We're extracting the least significant bits of an rtx
7494 (ashift X (const_int C)), where LEN > C. Extract the
7495 least significant (LEN - C) bits of X, giving an rtx
7496 whose mode is MODE, then shift it left C times. */
7502 }
7504 /* If trying or potentionally trying to extract
7505 bits outside of is_mode, don't look through
7506 TRUNCATE. See PR82192. */
7513 /* See if this can be done without an extraction. We never can if the
7514 width of the field is not the same as that of some integer mode. For
7515 registers, we can only avoid the extraction if the position is at the
7516 low-order bit and this is either not in the destination or we have the
7517 appropriate STRICT_LOW_PART operation available.
7519 For MEM, we can avoid an extract if the field starts on an appropriate
7520 boundary and we can change the mode of the memory reference. */
7522 scalar_int_mode tmode;
7531 && (! in_dest
7535 && (pos
7538 /* We can't do this if we are widening INNER_MODE (it
7539 may not be aligned, for one thing). */
7545 {
7546 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7547 field. If the original and current mode are the same, we need not
7548 adjust the offset. Otherwise, we do if bytes big endian.
7550 If INNER is not a MEM, get a piece consisting of just the field
7551 of interest (in this case POS % BITS_PER_WORD must be 0). */
7554 {
7555 HOST_WIDE_INT offset;
7557 /* POS counts from lsb, but make OFFSET count in memory order. */
7560 else
7564 }
7566 {
7568 {
7569 /* We can't call gen_lowpart in a DEST since we
7570 always want a SUBREG (see below) and it would sometimes
7571 return a new hard register. */
7573 {
7574 unsigned int offset
7577 /* Avoid creating invalid subregs, for example when
7578 simplifying (x>>32)&255. */
7583 }
7584 else
7586 }
7587 else
7589 }
7590 else
7592 len >= HOST_BITS_PER_WIDE_INT
7593 ? HOST_WIDE_INT_M1U
7596 /* If this extraction is going into the destination of a SET,
7597 make a STRICT_LOW_PART unless we made a MEM. */
7612 /* If we know that no extraneous bits are set, and that the high
7613 bit is not set, convert the extraction to the cheaper of
7614 sign and zero extension, that are equivalent in these cases. */
7620 {
7624 /* Prefer ZERO_EXTENSION, since it gives more information to
7625 backends. */
7630 }
7632 /* Otherwise, sign- or zero-extend unless we already are in the
7633 proper mode. */
7637 }
7639 /* Unless this is a COMPARE or we have a funny memory reference,
7640 don't do anything with zero-extending field extracts starting at
7641 the low-order bit since they are simple AND operations. */
7646 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7647 if the position is not a constant and the length is not 1. In all
7648 other cases, we would only be going outside our object in cases when
7649 an original shift would have been undefined. */
7658 /* If INNER is not from memory, we want it to have the mode of a register
7659 extraction pattern's structure operand, or word_mode if there is no
7660 such pattern. The same applies to extraction_mode and pos_mode
7661 and their respective operands.
7663 For memory, assume that the desired extraction_mode and pos_mode
7664 are the same as for a register operation, since at present we don't
7665 have named patterns for aligned memory structures. */
7669 {
7673 }
7675 /* Never narrow an object, since that might not be safe. */
7683 else
7684 {
7685 /* Be careful not to go beyond the extracted object and maintain the
7686 natural alignment of the memory. */
7691 }
7696 {
7697 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7698 BITS_BIG_ENDIAN style. If position is constant, compute new
7699 position. Otherwise, build subtraction.
7700 Note that POS is relative to the mode of the original argument.
7701 If it's a MEM we need to recompute POS relative to that.
7702 However, if we're extracting from (or inserting into) a register,
7703 we want to recompute POS relative to wanted_inner_mode. */
7710 else
7711 pos_rtx
7714 pos_rtx);
7715 /* POS may be less than 0 now, but we check for that below.
7716 Note that it can only be less than 0 if !MEM_P (inner). */
7717 }
7719 /* If INNER has a wider mode, and this is a constant extraction, try to
7720 make it smaller and adjust the byte to point to the byte containing
7721 the value. */
7724 && ! pos_rtx
7729 {
7732 /* The computations below will be correct if the machine is big
7733 endian in both bits and bytes or little endian in bits and bytes.
7734 If it is mixed, we must adjust. */
7736 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7737 adjust OFFSET to compensate. */
7742 /* We can now move to the desired byte. */
7753 }
7755 /* If INNER is not memory, get it into the proper mode. If we are changing
7756 its mode, POS must be a constant and smaller than the size of the new
7757 mode. */
7759 {
7760 /* On the LHS, don't create paradoxical subregs implicitely truncating
7761 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7764 wanted_inner_mode))
7776 pos_rtx
7778 ? HOST_WIDE_INT_M1U
7782 }
7784 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7785 have to zero extend. Otherwise, we can just use a SUBREG.
7787 We dealt with constant rtxes earlier, so pos_rtx cannot
7788 have VOIDmode at this point. */
7792 {
7796 /* If we know that no extraneous bits are set, and that the high
7797 bit is not set, convert extraction to cheaper one - either
7798 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7799 cases. */
7807 {
7811 /* Prefer ZERO_EXTENSION, since it gives more information to
7812 backends. */
7816 }
7818 }
7820 /* Make POS_RTX unless we already have it and it is correct. If we don't
7821 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7822 be a CONST_INT. */
7829 /* Make the required operation. See if we can use existing rtx. */
7836 }
7837 \f
7838 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7839 can be commuted with any other operations in X. Return X without
7840 that shift if so. */
7842 static rtx
7844 {
7846 rtx tem;
7849 {
7851 /* This is the shift itself. If it is wide enough, we will return
7852 either the value being shifted if the shift count is equal to
7853 COUNT or a shift for the difference. */
7867 /* If we can safely shift this constant and we find the inner shift,
7868 make a new operation. */
7873 {
7877 }
7882 }
7885 }
7886 \f
7887 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7888 level of the expression and MODE is its mode. IN_CODE is as for
7889 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7890 that should be used when recursing on operands of *X_PTR.
7892 There are two possible actions:
7894 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7895 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7897 - Return a new rtx, which the caller returns directly. */
7899 static rtx
7903 {
7911 rtx tem;
7912 scalar_int_mode inner_mode;
7916 {
7919 }
7921 /* Process depending on the code of this operation. If NEW is set
7922 nonzero, it will be returned. */
7925 {
7927 /* Convert shifts by constants into multiplications if inside
7928 an address. */
7932 {
7938 {
7941 }
7944 }
7953 {
7957 }
7960 {
7964 mode));
7966 }
7967 else
7968 {
7971 }
7981 {
7985 }
7988 {
7992 mode));
7994 }
7995 else
7996 {
8000 }
8003 /* If the second operand is not a constant, we can't do anything
8004 with it. */
8008 /* If the constant is a power of two minus one and the first operand
8009 is a logical right shift, make an extraction. */
8012 {
8016 }
8018 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8025 {
8032 /* If we narrowed the mode when dropping the subreg, then we lose. */
8036 /* If that didn't give anything, see if the AND simplifies on
8037 its own. */
8039 {
8043 }
8044 }
8045 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8051 {
8052 /* Apply the distributive law, and then try to make extractions. */
8059 }
8061 /* If we are have (and (rotate X C) M) and C is larger than the number
8062 of bits in M, this is an extraction. */
8068 {
8074 }
8076 /* On machines without logical shifts, if the operand of the AND is
8077 a logical shift and our mask turns off all the propagated sign
8078 bits, we can replace the logical shift with an arithmetic shift. */
8086 {
8096 next_code),
8098 }
8100 /* If the constant is one less than a power of two, this might be
8101 representable by an extraction even if no shift is present.
8102 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8103 we are in a COMPARE. */
8107 next_code),
8110 /* If we are in a comparison and this is an AND with a power of two,
8111 convert this into the appropriate bit extract. */
8117 next_code),
8120 /* If the one operand is a paradoxical subreg of a register or memory and
8121 the constant (limited to the smaller mode) has only zero bits where
8122 the sub expression has known zero bits, this can be expressed as
8123 a zero_extend. */
8125 {
8126 rtx sub;
8132 {
8136 /* original AND constant with all the known zero bits set */
8139 {
8144 }
8145 }
8146 }
8151 /* If the sign bit is known to be zero, replace this with an
8152 arithmetic shift. */
8157 {
8160 next_code),
8163 }
8165 /* fall through */
8171 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8172 this is a SIGN_EXTRACT. */
8179 {
8186 }
8188 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8189 If so, try to merge the shifts into a SIGN_EXTEND. We could
8190 also do this for some cases of SIGN_EXTRACT, but it doesn't
8191 seem worth the effort; the case checked for occurs on Alpha. */
8202 next_code),
8209 /* Call ourselves recursively on the inner expression. If we are
8210 narrowing the object and it has a different RTL code from
8211 what it originally did, do this SUBREG as a force_to_mode. */
8212 {
8216 /* If the SUBREG is masking of a logical right shift,
8217 make an extraction. */
8224 {
8233 }
8235 /* If in_code is COMPARE, it isn't always safe to pass it through
8236 to the recursive make_compound_operation call. */
8240 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8241 is (const_int 0), rather than
8242 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8243 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8244 for non-equality comparisons against 0 is not equivalent
8245 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8255 simplified
8263 {
8264 rtx newer
8267 /* If we have something other than a SUBREG, we might have
8268 done an expansion, so rerun ourselves. */
8272 /* force_to_mode can expand compounds. If it just re-expanded
8273 the compound, use gen_lowpart to convert to the desired
8274 mode. */
8276 /* Likewise if it re-expanded the compound only partially.
8277 This happens for SUBREG of ZERO_EXTRACT if they extract
8278 the same number of bits. */
8287 }
8291 }
8296 }
8302 }
8304 /* Look at the expression rooted at X. Look for expressions
8305 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8306 Form these expressions.
8308 Return the new rtx, usually just X.
8310 Also, for machines like the VAX that don't have logical shift insns,
8311 try to convert logical to arithmetic shift operations in cases where
8312 they are equivalent. This undoes the canonicalizations to logical
8313 shifts done elsewhere.
8315 We try, as much as possible, to re-use rtl expressions to save memory.
8317 IN_CODE says what kind of expression we are processing. Normally, it is
8318 SET. In a memory address it is MEM. When processing the arguments of
8319 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8320 precisely it is an equality comparison against zero. */
8322 rtx
8324 {
8331 /* Select the code to be used in recursive calls. Once we are inside an
8332 address, we stay there. If we have a comparison, set to COMPARE,
8333 but once inside, go back to our default of SET. */
8340 scalar_int_mode mode;
8342 {
8348 }
8350 /* Now recursively process each operand of this operation. We need to
8351 handle ZERO_EXTEND specially so that we don't lose track of the
8352 inner mode. */
8354 {
8362 }
8367 {
8370 }
8373 {
8376 }
8380 }
8381 \f
8382 /* Given M see if it is a value that would select a field of bits
8383 within an item, but not the entire word. Return -1 if not.
8384 Otherwise, return the starting position of the field, where 0 is the
8385 low-order bit.
8387 *PLEN is set to the length of the field. */
8389 static int
8391 {
8392 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8397 /* Now shift off the low-order zero bits and see if we have a
8398 power of two minus 1. */
8406 }
8407 \f
8408 /* If X refers to a register that equals REG in value, replace these
8409 references with REG. */
8410 static rtx
8412 {
8420 {
8453 /* FALLTHRU */
8457 {
8461 else
8463 }
8465 /* fall through */
8472 {
8475 {
8477 {
8480 }
8482 }
8483 }
8485 {
8488 {
8491 {
8493 {
8496 }
8498 }
8499 }
8500 }
8503 }
8506 }
8508 /* Return X converted to MODE. If the value is already truncated to
8509 MODE we can just return a subreg even though in the general case we
8510 would need an explicit truncation. */
8512 static rtx
8514 {
8519 {
8520 /* Bit-cast X into an integer mode. */
8525 }
8528 }
8530 /* See if X can be simplified knowing that we will only refer to it in
8531 MODE and will only refer to those bits that are nonzero in MASK.
8532 If other bits are being computed or if masking operations are done
8533 that select a superset of the bits in MASK, they can sometimes be
8534 ignored.
8536 Return a possibly simplified expression, but always convert X to
8537 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8539 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8540 are all off in X. This is used when X will be complemented, by either
8541 NOT, NEG, or XOR. */
8543 static rtx
8546 {
8549 machine_mode op_mode;
8552 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8553 code below will do the wrong thing since the mode of such an
8554 expression is VOIDmode.
8556 Also do nothing if X is a CLOBBER; this can happen if X was
8557 the return value from a call to gen_lowpart. */
8561 /* We want to perform the operation in its present mode unless we know
8562 that the operation is valid in MODE, in which case we do the operation
8563 in MODE. */
8568 /* It is not valid to do a right-shift in a narrower mode
8569 than the one it came in with. */
8574 /* Truncate MASK to fit OP_MODE. */
8578 /* Determine what bits of X are guaranteed to be (non)zero. */
8581 /* If none of the bits in X are needed, return a zero. */
8585 /* If X is a CONST_INT, return a new one. Do this here since the
8586 test below will fail. */
8588 {
8591 else
8592 {
8595 }
8596 }
8598 /* If X is narrower than MODE and we want all the bits in X's mode, just
8599 get X in the proper mode. */
8604 /* We can ignore the effect of a SUBREG if it narrows the mode or
8605 if the constant masks to zero all the bits the mode doesn't have. */
8617 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8618 integer too. */
8624 }
8626 /* Subroutine of force_to_mode that handles cases in which both X and
8627 the result are scalar integers. MODE is the mode of the result,
8628 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8629 is preferred for simplified versions of X. The other arguments
8630 are as for force_to_mode. */
8632 static rtx
8636 {
8642 /* When we have an arithmetic operation, or a shift whose count we
8643 do not know, we need to assume that all bits up to the highest-order
8644 bit in MASK will be needed. This is how we form such a mask. */
8647 else
8652 {
8654 /* If X is a (clobber (const_int)), return it since we know we are
8655 generating something that won't match. */
8668 /* Similarly for a truncate. */
8672 /* If this is an AND with a constant, convert it into an AND
8673 whose constant is the AND of that constant with MASK. If it
8674 remains an AND of MASK, delete it since it is redundant. */
8677 {
8682 /* If X is still an AND, see if it is an AND with a mask that
8683 is just some low-order bits. If so, and it is MASK, we don't
8684 need it. */
8690 /* If it remains an AND, try making another AND with the bits
8691 in the mode mask that aren't in MASK turned on. If the
8692 constant in the AND is wide enough, this might make a
8693 cheaper constant. */
8698 {
8699 unsigned HOST_WIDE_INT cval
8701 rtx y;
8708 }
8711 }
8716 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8717 low-order bits (as in an alignment operation) and FOO is already
8718 aligned to that boundary, mask C1 to that boundary as well.
8719 This may eliminate that PLUS and, later, the AND. */
8721 {
8725 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8726 number, sign extend it. */
8739 }
8741 /* fall through */
8744 /* Substituting into the operands of a widening MULT is not likely to
8745 create RTL matching a machine insn. */
8755 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8756 most significant bit in MASK since carries from those bits will
8757 affect the bits we are interested in. */
8762 /* If X is (minus C Y) where C's least set bit is larger than any bit
8763 in the mask, then we may replace with (neg Y). */
8766 {
8769 }
8771 /* Similarly, if C contains every bit in the fuller_mask, then we may
8772 replace with (not Y). */
8775 {
8778 }
8785 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8786 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8787 operation which may be a bitfield extraction. Ensure that the
8788 constant we form is not wider than the mode of X. */
8800 {
8803 xmode);
8809 }
8811 binop:
8812 /* For most binary operations, just propagate into the operation and
8813 change the mode if we have an operation of that mode. */
8818 /* If we ended up truncating both operands, truncate the result of the
8819 operation instead. */
8822 {
8825 }
8831 {
8834 }
8838 /* For left shifts, do the same, but just for the first operand.
8839 However, we cannot do anything with shifts where we cannot
8840 guarantee that the counts are smaller than the size of the mode
8841 because such a count will have a different meaning in a
8842 wider mode. */
8852 /* If the shift count is a constant and we can do arithmetic in
8853 the mode of the shift, refine which bits we need. Otherwise, use the
8854 conservative form of the mask. */
8860 else
8868 {
8871 }
8875 /* Here we can only do something if the shift count is a constant,
8876 this shift constant is valid for the host, and we can do arithmetic
8877 in OP_MODE. */
8883 {
8887 /* Select the mask of the bits we need for the shift operand. */
8890 /* We can only change the mode of the shift if we can do arithmetic
8891 in the mode of the shift and INNER_MASK is no wider than the
8892 width of X's mode. */
8899 {
8902 }
8903 }
8905 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8906 shift and AND produces only copies of the sign bit (C2 is one less
8907 than a power of two), we can do this with just a shift. */
8911 /* The shift puts one of the sign bit copies in the least significant
8912 bit. */
8917 /* Number of bits left after the shift must be more than the mask
8918 needs. */
8921 /* Must be more sign bit copies than the mask needs. */
8931 /* If we are just looking for the sign bit, we don't need this shift at
8932 all, even if it has a variable count. */
8936 /* If this is a shift by a constant, get a mask that contains those bits
8937 that are not copies of the sign bit. We then have two cases: If
8938 MASK only includes those bits, this can be a logical shift, which may
8939 allow simplifications. If MASK is a single-bit field not within
8940 those bits, we are requesting a copy of the sign bit and hence can
8941 shift the sign bit to the appropriate location. */
8945 {
8949 /* If the considered data is wider than HOST_WIDE_INT, we can't
8950 represent a mask for all its bits in a single scalar.
8951 But we only care about the lower bits, so calculate these. */
8954 {
8957 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8958 is the number of bits a full-width mask would have set.
8959 We need only shift if these are fewer than nonzero can
8960 hold. If not, we must keep all bits set in nonzero. */
8965 + HOST_BITS_PER_WIDE_INT
8967 }
8968 else
8969 {
8972 }
8975 {
8980 }
8983 {
8984 x = simplify_shift_const
8990 }
8991 }
8993 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8994 even if the shift count isn't a constant. */
8998 shiftrt:
9000 /* If this is a zero- or sign-extension operation that just affects bits
9001 we don't care about, remove it. Be sure the call above returned
9002 something that is still a shift. */
9012 next_select);
9018 /* If the shift count is constant and we can do computations
9019 in the mode of X, compute where the bits we care about are.
9020 Otherwise, we can't do anything. Don't change the mode of
9021 the shift or propagate MODE into the shift, though. */
9024 {
9033 }
9037 /* If we just want the low-order bit, the NEG isn't needed since it
9038 won't change the low-order bit. */
9042 /* We need any bits less significant than the most significant bit in
9043 MASK since carries from those bits will affect the bits we are
9044 interested in. */
9049 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9050 same as the XOR case above. Ensure that the constant we form is not
9051 wider than the mode of X. */
9059 {
9066 }
9068 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9069 use the full mask inside the NOT. */
9072 unop:
9075 next_select));
9077 {
9080 }
9084 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9085 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9086 which is equal to STORE_FLAG_VALUE. */
9098 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9099 written in a narrower mode. We play it safe and do not do so. */
9115 }
9117 /* Ensure we return a value of the proper mode. */
9119 }
9120 \f
9121 /* Return nonzero if X is an expression that has one of two values depending on
9122 whether some other value is zero or nonzero. In that case, we return the
9123 value that is being tested, *PTRUE is set to the value if the rtx being
9124 returned has a nonzero value, and *PFALSE is set to the other alternative.
9126 If we return zero, we set *PTRUE and *PFALSE to X. */
9128 static rtx
9130 {
9135 scalar_int_mode int_mode;
9137 /* If we are comparing a value against zero, we are done. */
9140 {
9144 }
9146 /* If this is a unary operation whose operand has one of two values, apply
9147 our opcode to compute those values. */
9150 {
9155 }
9157 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9158 make can't possibly match and would suppress other optimizations. */
9160 ;
9162 /* If this is a binary operation, see if either side has only one of two
9163 values. If either one does or if both do and they are conditional on
9164 the same value, compute the new true and false values. */
9166 {
9174 {
9175 /* Try to enable a simplification by undoing work done by
9176 if_then_else_cond if it converted a REG into something more
9177 complex. */
9179 {
9182 }
9183 else
9184 {
9187 }
9188 }
9192 {
9193 /* If if_then_else_cond returned zero, then true/false are the
9194 same rtl. We must copy one of them to prevent invalid rtl
9195 sharing. */
9202 {
9207 }
9208 else
9209 {
9212 }
9215 }
9217 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9218 operands is zero when the other is nonzero, and vice-versa,
9219 and STORE_FLAG_VALUE is 1 or -1. */
9225 {
9242 {
9249 const_true_rtx);
9251 }
9252 }
9254 /* Similarly for MULT, AND and UMIN, except that for these the result
9255 is always zero. */
9259 {
9273 {
9276 }
9277 }
9278 }
9281 {
9282 /* If we have IF_THEN_ELSE already, extract the condition and
9283 canonicalize it if it is NE or EQ. */
9289 {
9292 }
9293 else
9295 }
9297 /* If X is a SUBREG, we can narrow both the true and false values
9298 if the inner expression, if there is a condition. */
9302 {
9308 {
9312 }
9313 }
9315 /* If X is a constant, this isn't special and will cause confusions
9316 if we treat it as such. Likewise if it is equivalent to a constant. */
9319 ;
9321 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9322 will be least confusing to the rest of the compiler. */
9324 {
9327 }
9329 /* If X is known to be either 0 or -1, those are the true and
9330 false values when testing X. */
9335 {
9338 }
9340 /* Likewise for 0 or a single bit. */
9343 {
9346 }
9348 /* Otherwise fail; show no condition with true and false values the same. */
9351 }
9352 \f
9353 /* Return the value of expression X given the fact that condition COND
9354 is known to be true when applied to REG as its first operand and VAL
9355 as its second. X is known to not be shared and so can be modified in
9356 place.
9358 We only handle the simplest cases, and specifically those cases that
9359 arise with IF_THEN_ELSE expressions. */
9361 static rtx
9363 {
9371 /* If either operand of the condition is a floating point value,
9372 then we have to avoid collapsing an EQ comparison. */
9382 /* If X is (abs REG) and we know something about REG's relationship
9383 with zero, we may be able to simplify this. */
9387 {
9396 }
9398 /* The only other cases we handle are MIN, MAX, and comparisons if the
9399 operands are the same as REG and VAL. */
9402 {
9404 {
9407 }
9410 {
9412 {
9420 else
9422 }
9425 {
9428 /* Do not reverse the condition when it is NE or EQ.
9429 This is because we cannot conclude anything about
9430 the value of 'SMAX (x, y)' when x is not equal to y,
9431 but we can when x equals y. */
9437 {
9448 }
9449 }
9450 }
9451 }
9453 {
9458 {
9459 /* We must simplify subreg here, before we lose track of the
9460 original inner_mode. */
9465 else
9467 }
9470 }
9471 /* We don't have to handle SIGN_EXTEND here, because even in the
9472 case of replacing something with a modeless CONST_INT, a
9473 CONST_INT is already (supposed to be) a valid sign extension for
9474 its narrower mode, which implies it's already properly
9475 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9476 story is different. */
9478 {
9483 {
9484 /* We must simplify the zero_extend here, before we lose
9485 track of the original inner_mode. */
9490 else
9492 }
9495 }
9499 {
9506 }
9509 }
9510 \f
9511 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9512 assignment as a field assignment. */
9514 static int
9516 {
9518 {
9526 }
9534 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9535 Note that all SUBREGs of MEM are paradoxical; otherwise they
9536 would have been rewritten. */
9549 /* We used to see if get_last_value of X and Y were the same but that's
9550 not correct. In one direction, we'll cause the assignment to have
9551 the wrong destination and in the case, we'll import a register into this
9552 insn that might have already have been dead. So fail if none of the
9553 above cases are true. */
9555 }
9556 \f
9557 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9558 Return that assignment if so.
9560 We only handle the most common cases. */
9562 static rtx
9564 {
9567 rtx assign;
9569 HOST_WIDE_INT c1;
9570 HOST_WIDE_INT pos;
9572 rtx other;
9574 /* All the rules in this function are specific to scalar integers. */
9575 scalar_int_mode mode;
9579 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9580 a clear of a one-bit field. We will have changed it to
9581 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9582 for a SUBREG. */
9588 {
9594 }
9603 {
9610 }
9612 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9613 one-bit field. */
9617 {
9623 }
9625 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9626 SRC is an AND with all bits of that field set, then we can discard
9627 the AND. */
9632 {
9639 else
9642 /* Complete overlap. We can remove the source AND. */
9646 /* Partial overlap. We can reduce the source AND. */
9648 {
9652 }
9653 }
9655 /* The other case we handle is assignments into a constant-position
9656 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9657 a mask that has all one bits except for a group of zero bits and
9658 OTHER is known to have zeros where C1 has ones, this is such an
9659 assignment. Compute the position and length from C1. Shift OTHER
9660 to the appropriate position, force it to the required mode, and
9661 make the extraction. Check for the AND in both operands. */
9663 /* One or more SUBREGs might obscure the constant-position field
9664 assignment. The first one we are likely to encounter is an outer
9665 narrowing SUBREG, which we can just strip for the purposes of
9666 identifying the constant-field assignment. */
9683 /* The second SUBREG that might get in the way is a paradoxical
9684 SUBREG around the first operand of the AND. We want to
9685 pretend the operand is as wide as the destination here. We
9686 do this by adjusting the MEM to wider mode for the sole
9687 purpose of the call to rtx_equal_for_field_assignment_p. Also
9688 note this trick only works for MEMs. */
9700 /* The second SUBREG that might get in the way is a paradoxical
9701 SUBREG around the first operand of the AND. We want to
9702 pretend the operand is as wide as the destination here. We
9703 do this by adjusting the MEM to wider mode for the sole
9704 purpose of the call to rtx_equal_for_field_assignment_p. Also
9705 note this trick only works for MEMs. */
9713 else
9727 /* The mode to use for the source is the mode of the assignment, or of
9728 what is inside a possible STRICT_LOW_PART. */
9732 /* Shift OTHER right POS places and make it the source, restricting it
9733 to the proper length and mode. */
9737 dest);
9739 len >= HOST_BITS_PER_WIDE_INT
9740 ? HOST_WIDE_INT_M1U
9744 /* If SRC is masked by an AND that does not make a difference in
9745 the value being stored, strip it. */
9756 }
9757 \f
9758 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9759 if so. */
9761 static rtx
9763 {
9767 rtx tem;
9769 /* Distributivity is not true for floating point as it can change the
9770 value. So we don't do it unless -funsafe-math-optimizations. */
9775 /* The outer operation can only be one of the following: */
9783 /* If either operand is a primitive we can't do anything, so get out
9784 fast. */
9794 /* See if the inner and outer operations distribute. */
9796 {
9801 /* These all distribute except over PLUS. */
9812 /* This is also a multiply, so it distributes over everything. */
9815 /* This used to handle SUBREG, but this turned out to be counter-
9816 productive, since (subreg (op ...)) usually is not handled by
9817 insn patterns, and this "optimization" therefore transformed
9818 recognizable patterns into unrecognizable ones. Therefore the
9819 SUBREG case was removed from here.
9821 It is possible that distributing SUBREG over arithmetic operations
9822 leads to an intermediate result than can then be optimized further,
9823 e.g. by moving the outer SUBREG to the other side of a SET as done
9824 in simplify_set. This seems to have been the original intent of
9825 handling SUBREGs here.
9827 However, with current GCC this does not appear to actually happen,
9828 at least on major platforms. If some case is found where removing
9829 the SUBREG case here prevents follow-on optimizations, distributing
9830 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9834 }
9836 /* Set LHS and RHS to the inner operands (A and B in the example
9837 above) and set OTHER to the common operand (C in the example).
9838 There is only one way to do this unless the inner operation is
9839 commutative. */
9851 else
9854 /* Form the new inner operation, seeing if it simplifies first. */
9857 /* There is one exception to the general way of distributing:
9858 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9860 {
9863 }
9865 /* We may be able to continuing distributing the result, so call
9866 ourselves recursively on the inner operation before forming the
9867 outer operation, which we return. */
9870 }
9872 /* See if X is of the form (* (+ A B) C), and if so convert to
9873 (+ (* A C) (* B C)) and try to simplify.
9875 Most of the time, this results in no change. However, if some of
9876 the operands are the same or inverses of each other, simplifications
9877 will result.
9879 For example, (and (ior A B) (not B)) can occur as the result of
9880 expanding a bit field assignment. When we apply the distributive
9881 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9882 which then simplifies to (and (A (not B))).
9884 Note that no checks happen on the validity of applying the inverse
9885 distributive law. This is pointless since we can do it in the
9886 few places where this routine is called.
9888 N is the index of the term that is decomposed (the arithmetic operation,
9889 i.e. (+ A B) in the first example above). !N is the index of the term that
9890 is distributed, i.e. of C in the first example above. */
9891 static rtx
9893 {
9894 machine_mode mode;
9898 /* Distributivity is not true for floating point as it can change the
9899 value. So we don't do it unless -funsafe-math-optimizations. */
9916 /* Special case (and (xor B C) (not A)), which is equivalent to
9917 (xor (ior A B) (ior A C)) */
9919 {
9922 }
9925 {
9926 /* Distribute the second term. */
9929 }
9930 else
9931 {
9932 /* Distribute the first term. */
9935 }
9945 }
9946 \f
9947 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9948 in MODE. Return an equivalent form, if different from (and VAROP
9949 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9951 static rtx
9954 {
9957 rtx orig_varop;
9965 /* Simplify VAROP knowing that we will be only looking at some of the
9966 bits in it.
9968 Note by passing in CONSTOP, we guarantee that the bits not set in
9969 CONSTOP are not significant and will never be examined. We must
9970 ensure that is the case by explicitly masking out those bits
9971 before returning. */
9974 /* If VAROP is a CLOBBER, we will fail so return it. */
9978 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9979 to VAROP and return the new constant. */
9983 /* See what bits may be nonzero in VAROP. Unlike the general case of
9984 a call to nonzero_bits, here we don't care about bits outside
9985 MODE. */
9989 /* Turn off all bits in the constant that are known to already be zero.
9990 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9991 which is tested below. */
9995 /* If we don't have any bits left, return zero. */
9999 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10000 a power of two, we can replace this with an ASHIFT. */
10005 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10006 or XOR, then try to apply the distributive law. This may eliminate
10007 operations if either branch can be simplified because of the AND.
10008 It may also make some cases more complex, but those cases probably
10009 won't match a pattern either with or without this. */
10012 {
10014 return
10015 gen_lowpart
10017 apply_distributive_law
10021 constop),
10024 constop))));
10025 }
10027 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10028 the AND and see if one of the operands simplifies to zero. If so, we
10029 may eliminate it. */
10033 {
10042 }
10044 /* Make a SUBREG if necessary. If we can't make it, fail. */
10049 /* If we are only masking insignificant bits, return VAROP. */
10056 /* Otherwise, return an AND. */
10058 }
10061 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10062 in MODE.
10064 Return an equivalent form, if different from X. Otherwise, return X. If
10065 X is zero, we are to always construct the equivalent form. */
10067 static rtx
10070 {
10081 }
10082 \f
10083 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10084 We don't care about bits outside of those defined in MODE.
10086 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10087 a shift, AND, or zero_extract, we can do better. */
10089 static rtx
10091 scalar_int_mode mode,
10093 {
10094 rtx tem;
10097 /* If X is a register whose nonzero bits value is current, use it.
10098 Otherwise, if X is a register whose value we can find, use that
10099 value. Otherwise, use the previously-computed global nonzero bits
10100 for this register. */
10114 && !REGNO_REG_SET_P
10117 {
10118 /* Note that, even if the precision of last_set_mode is lower than that
10119 of mode, record_value_for_reg invoked nonzero_bits on the register
10120 with nonzero_bits_mode (because last_set_mode is necessarily integral
10121 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10122 are all valid, hence in mode too since nonzero_bits_mode is defined
10123 to the largest HWI_COMPUTABLE_MODE_P mode. */
10126 }
10130 {
10135 }
10138 {
10142 /* We don't know anything about the upper bits. */
10146 }
10149 }
10151 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10152 end of X that are known to be equal to the sign bit. X will be used
10153 in mode MODE; the returned value will always be between 1 and the
10154 number of bits in MODE. */
10156 static rtx
10158 scalar_int_mode mode,
10160 {
10161 rtx tem;
10174 && !REGNO_REG_SET_P
10177 {
10180 }
10191 }
10192 \f
10193 /* Return the number of "extended" bits there are in X, when interpreted
10194 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10195 unsigned quantities, this is the number of high-order zero bits.
10196 For signed quantities, this is the number of copies of the sign bit
10197 minus 1. In both case, this function returns the number of "spare"
10198 bits. For example, if two quantities for which this function returns
10199 at least 1 are added, the addition is known not to overflow.
10201 This function will always return 0 unless called during combine, which
10202 implies that it must be called from a define_split. */
10204 unsigned int
10206 {
10210 scalar_int_mode int_mode;
10218 }
10220 /* This function is called from `simplify_shift_const' to merge two
10221 outer operations. Specifically, we have already found that we need
10222 to perform operation *POP0 with constant *PCONST0 at the outermost
10223 position. We would now like to also perform OP1 with constant CONST1
10224 (with *POP0 being done last).
10226 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10227 the resulting operation. *PCOMP_P is set to 1 if we would need to
10228 complement the innermost operand, otherwise it is unchanged.
10230 MODE is the mode in which the operation will be done. No bits outside
10231 the width of this mode matter. It is assumed that the width of this mode
10232 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10234 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10235 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10236 result is simply *PCONST0.
10238 If the resulting operation cannot be expressed as one operation, we
10239 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10241 static int
10242 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10243 {
10250 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10254 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10255 if OP0 is SET. */
10264 {
10266 {
10284 }
10285 }
10287 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10291 /* If the two constants aren't the same, we can't do anything. The
10292 remaining six cases can all be done. */
10296 else
10298 {
10301 /* (a & b) | b == b */
10304 /* (a ^ b) | b == a | b */
10305 {;}
10310 /* (a & b) ^ b == (~a) & b */
10313 /* (a | b) ^ b == a & ~b */
10319 /* (a | b) & b == b */
10322 /* (a ^ b) & b) == (~a) & b */
10327 }
10329 /* Check for NO-OP cases. */
10342 /* ??? Slightly redundant with the above mask, but not entirely.
10343 Moving this above means we'd have to sign-extend the mode mask
10344 for the final test. */
10349 }
10350 \f
10351 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10352 the shift in. The original shift operation CODE is performed on OP in
10353 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10354 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10355 result of the shift is subject to operation OUTER_CODE with operand
10356 OUTER_CONST. */
10358 static scalar_int_mode
10362 {
10365 /* In general we can't perform in wider mode for right shift and rotate. */
10367 {
10369 /* We can still widen if the bits brought in from the left are identical
10370 to the sign bit of ORIG_MODE. */
10378 /* Similarly here but with zero bits. */
10383 /* We can also widen if the bits brought in will be masked off. This
10384 operation is performed in ORIG_MODE. */
10386 {
10392 }
10393 /* fall through */
10403 }
10404 }
10406 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10407 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10408 if we cannot simplify it. Otherwise, return a simplified value.
10410 The shift is normally computed in the widest mode we find in VAROP, as
10411 long as it isn't a different number of words than RESULT_MODE. Exceptions
10412 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10414 static rtx
10417 {
10422 machine_mode shift_mode;
10424 unsigned int mode_words
10426 /* We form (outer_op (code varop count) (outer_const)). */
10432 /* Make sure and truncate the "natural" shift on the way in. We don't
10433 want to do this inside the loop as it makes it more difficult to
10434 combine shifts. */
10438 /* If we were given an invalid count, don't do anything except exactly
10439 what was requested. */
10446 /* Unless one of the branches of the `if' in this loop does a `continue',
10447 we will `break' the loop after the `if'. */
10450 {
10451 /* If we have an operand of (clobber (const_int 0)), fail. */
10455 /* Convert ROTATERT to ROTATE. */
10457 {
10461 }
10465 {
10466 /* We only change the modes of scalar shifts. */
10472 }
10474 scalar_int_mode shift_unit_mode
10477 /* Handle cases where the count is greater than the size of the mode
10478 minus 1. For ASHIFT, use the size minus one as the count (this can
10479 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10480 take the count modulo the size. For other shifts, the result is
10481 zero.
10483 Since these shifts are being produced by the compiler by combining
10484 multiple operations, each of which are defined, we know what the
10485 result is supposed to be. */
10488 {
10493 else
10494 {
10495 /* We can't simply return zero because there may be an
10496 outer op. */
10500 }
10501 }
10503 /* If we discovered we had to complement VAROP, leave. Making a NOT
10504 here would cause an infinite loop. */
10509 {
10510 /* An arithmetic right shift of a quantity known to be -1 or 0
10511 is a no-op. */
10515 {
10518 }
10520 /* If we are doing an arithmetic right shift and discarding all but
10521 the sign bit copies, this is equivalent to doing a shift by the
10522 bitsize minus one. Convert it into that shift because it will
10523 often allow other simplifications. */
10530 /* We simplify the tests below and elsewhere by converting
10531 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10532 `make_compound_operation' will convert it to an ASHIFTRT for
10533 those machines (such as VAX) that don't have an LSHIFTRT. */
10538 shift_unit_mode)))
10550 }
10553 {
10560 {
10563 }
10567 /* The following rules apply only to scalars. */
10572 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10573 minus the width of a smaller mode, we can do this with a
10574 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10581 {
10590 }
10594 /* The following rules apply only to scalars. */
10600 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10601 the same number of words as what we've seen so far. Then store
10602 the widest mode in MODE. */
10608 == mode_words
10610 {
10615 }
10619 /* Some machines use MULT instead of ASHIFT because MULT
10620 is cheaper. But it is still better on those machines to
10621 merge two shifts into one. */
10624 {
10625 varop
10631 }
10635 /* Similar, for when divides are cheaper. */
10638 {
10639 varop
10645 }
10649 /* If we are extracting just the sign bit of an arithmetic
10650 right shift, that shift is not needed. However, the sign
10651 bit of a wider mode may be different from what would be
10652 interpreted as the sign bit in a narrower mode, so, if
10653 the result is narrower, don't discard the shift. */
10658 {
10661 }
10663 /* fall through */
10668 /* The following rules apply only to scalars. */
10675 /* Here we have two nested shifts. The result is usually the
10676 AND of a new shift with a mask. We compute the result below. */
10682 {
10686 rtx mask_rtx;
10688 /* We have one common special case. We can't do any merging if
10689 the inner code is an ASHIFTRT of a smaller mode. However, if
10690 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10691 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10692 we can convert it to
10693 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10694 This simplifies certain SIGN_EXTEND operations. */
10698 {
10699 /* C3 has the low-order C1 bits zero. */
10711 }
10713 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10714 than C1 high-order bits equal to the sign bit, we can convert
10715 this to either an ASHIFT or an ASHIFTRT depending on the
10716 two counts.
10718 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10724 {
10728 {
10731 }
10734 }
10736 /* There are some cases we can't do. If CODE is ASHIFTRT,
10737 we can only do this if FIRST_CODE is also ASHIFTRT.
10739 We can't do the case when CODE is ROTATE and FIRST_CODE is
10740 ASHIFTRT.
10742 If the mode of this shift is not the mode of the outer shift,
10743 we can't do this if either shift is a right shift or ROTATE.
10745 Finally, we can't do any of these if the mode is too wide
10746 unless the codes are the same.
10748 Handle the case where the shift codes are the same
10749 first. */
10752 {
10761 }
10772 /* To compute the mask to apply after the shift, shift the
10773 nonzero bits of the inner shift the same way the
10774 outer shift will. */
10777 int_result_mode);
10779 mask_rtx
10783 /* Give up if we can't compute an outer operation to use. */
10791 /* If the shifts are in the same direction, we add the
10792 counts. Otherwise, we subtract them. */
10796 else
10799 /* If COUNT is positive, the new shift is usually CODE,
10800 except for the two exceptions below, in which case it is
10801 FIRST_CODE. If the count is negative, FIRST_CODE should
10802 always be used */
10812 }
10814 /* If we have (A << B << C) for any shift, we can convert this to
10815 (A << C << B). This wins if A is a constant. Only try this if
10816 B is not a constant. */
10821 {
10822 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10823 sure the result will be masked. See PR70222. */
10831 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10832 up outer sign extension (often left and right shift) is
10833 hardly more efficient than the original. See PR70429. */
10843 }
10847 /* The following rules apply only to scalars. */
10851 /* Make this fit the case below. */
10858 /* The following rules apply only to scalars. */
10864 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10865 with C the size of VAROP - 1 and the shift is logical if
10866 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10867 we have an (le X 0) operation. If we have an arithmetic shift
10868 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10869 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10877 {
10880 const0_rtx);
10886 }
10888 /* If we have (shift (logical)), move the logical to the outside
10889 to allow it to possibly combine with another logical and the
10890 shift to combine with another shift. This also canonicalizes to
10891 what a ZERO_EXTRACT looks like. Also, some machines have
10892 (and (shift)) insns. */
10895 /* We can't do this if we have (ashiftrt (xor)) and the
10896 constant has its sign bit set in shift_unit_mode with
10897 shift_unit_mode wider than result_mode. */
10901 shift_unit_mode))
10910 {
10913 }
10915 /* If we can't do that, try to simplify the shift in each arm of the
10916 logical expression, make a new logical expression, and apply
10917 the inverse distributive law. This also can't be done for
10918 (ashiftrt (xor)) where we've widened the shift and the constant
10919 changes the sign bit. */
10924 shift_unit_mode)))
10925 {
10937 }
10941 /* The following rules apply only to scalars. */
10946 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10947 says that the sign bit can be tested, FOO has mode MODE, C is
10948 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10949 that may be nonzero. */
10959 {
10963 }
10967 /* The following rules apply only to scalars. */
10972 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10973 than the number of bits in the mode is equivalent to A. */
10977 {
10981 }
10983 /* NEG commutes with ASHIFT since it is multiplication. Move the
10984 NEG outside to allow shifts to combine. */
10988 {
10991 }
10995 /* The following rules apply only to scalars. */
11000 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11001 is one less than the number of bits in the mode is
11002 equivalent to (xor A 1). */
11009 {
11013 }
11015 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11016 that might be nonzero in BAR are those being shifted out and those
11017 bits are known zero in FOO, we can replace the PLUS with FOO.
11018 Similarly in the other operand order. This code occurs when
11019 we are computing the size of a variable-size array. */
11026 {
11029 }
11037 {
11040 }
11042 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11053 {
11056 }
11058 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11059 signbit', and attempt to change the PLUS to an XOR and move it to
11060 the outer operation as is done above in the AND/IOR/XOR case
11061 leg for shift(logical). See details in logical handling above
11062 for reasoning in doing so. */
11074 {
11077 }
11082 /* The following rules apply only to scalars. */
11087 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11088 with C the size of VAROP - 1 and the shift is logical if
11089 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11090 we have a (gt X 0) operation. If the shift is arithmetic with
11091 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11092 we have a (neg (gt X 0)) operation. */
11101 {
11104 const0_rtx);
11110 }
11114 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11115 if the truncate does not affect the value. */
11122 {
11125 varop_inner
11128 GEN_INT
11133 }
11138 }
11141 }
11145 {
11146 /* We only change the modes of scalar shifts. */
11151 }
11153 /* We have now finished analyzing the shift. The result should be
11154 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11155 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11156 to the result of the shift. OUTER_CONST is the relevant constant,
11157 but we must turn off all bits turned off in the shift. */
11165 /* Make a SUBREG if necessary. If we can't make it, fail. */
11170 /* If we have an outer operation and we just made a shift, it is
11171 possible that we could have simplified the shift were it not
11172 for the outer operation. So try to do the simplification
11173 recursively. */
11177 else
11183 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11184 turn off all the bits that the shift would have turned off. */
11186 /* We only change the modes of scalar shifts. */
11190 /* Do the remainder of the processing in RESULT_MODE. */
11193 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11194 operation. */
11199 {
11209 {
11210 /* This means that we have determined that the result is
11211 equivalent to a constant. This should be rare. */
11214 }
11217 else
11220 }
11223 }
11225 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11226 The result of the shift is RESULT_MODE. If we cannot simplify it,
11227 return X or, if it is NULL, synthesize the expression with
11228 simplify_gen_binary. Otherwise, return a simplified value.
11230 The shift is normally computed in the widest mode we find in VAROP, as
11231 long as it isn't a different number of words than RESULT_MODE. Exceptions
11232 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11234 static rtx
11237 {
11247 }
11249 \f
11250 /* A subroutine of recog_for_combine. See there for arguments and
11251 return value. */
11253 static int
11255 {
11257 rtx pat_without_clobbers;
11265 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11266 we use to indicate that something didn't match. If we find such a
11267 thing, force rejection. */
11281 {
11284 else
11287 }
11289 /* If it isn't, there is the possibility that we previously had an insn
11290 that clobbered some register as a side effect, but the combined
11291 insn doesn't need to do that. So try once more without the clobbers
11292 unless this represents an ASM insn. */
11296 {
11301 {
11304 pos++;
11305 }
11315 {
11318 else
11321 }
11322 }
11329 /* Recognize all noop sets, these will be killed by followup pass. */
11333 /* If we had any clobbers to add, make a new pattern than contains
11334 them. Then check to make sure that all of them are dead. */
11336 {
11346 else
11353 {
11358 {
11362 }
11363 }
11365 }
11369 {
11377 /* Allow targets to reject combined insn. */
11379 {
11382 dump_file);
11384 /* Callers expect recog_for_combine to strip
11385 clobbers from the pattern on failure. */
11390 }
11395 }
11401 }
11403 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11404 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11405 Return whether anything was so changed. */
11407 static bool
11409 {
11415 {
11427 {
11436 else
11440 }
11446 {
11452 }
11457 {
11461 }
11462 else
11468 {
11471 }
11475 }
11482 scalar_int_mode mode;
11488 {
11502 else
11510 }
11513 }
11515 /* Like recog, but we receive the address of a pointer to a new pattern.
11516 We try to match the rtx that the pointer points to.
11517 If that fails, we may try to modify or replace the pattern,
11518 storing the replacement into the same pointer object.
11520 Modifications include deletion or addition of CLOBBERs. If the
11521 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11522 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11523 (and undo if that fails).
11525 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11526 the CLOBBERs are placed.
11528 The value is the final insn code from the pattern ultimately matched,
11529 or -1. */
11531 static int
11533 {
11545 {
11548 {
11552 }
11553 }
11556 {
11561 }
11564 }
11565 \f
11566 /* Like gen_lowpart_general but for use by combine. In combine it
11567 is not possible to create any new pseudoregs. However, it is
11568 safe to create invalid memory addresses, because combine will
11569 try to recognize them and all they will do is make the combine
11570 attempt fail.
11572 If for some reason this cannot do its job, an rtx
11573 (clobber (const_int 0)) is returned.
11574 An insn containing that will not be recognized. */
11576 static rtx
11578 {
11582 rtx result;
11587 /* We can only support MODE being wider than a word if X is a
11588 constant integer or has a mode the same size. */
11593 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11594 won't know what to do. So we will strip off the SUBREG here and
11595 process normally. */
11597 {
11600 /* For use in case we fall down into the address adjustments
11601 further below, we need to adjust the known mode and size of
11602 x; imode and isize, since we just adjusted x. */
11609 }
11617 {
11618 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11619 address. */
11624 /* If we want to refer to something bigger than the original memref,
11625 generate a paradoxical subreg instead. That will force a reload
11626 of the original memref X. */
11632 }
11634 /* If X is a comparison operator, rewrite it in a new mode. This
11635 probably won't match, but may allow further simplifications. */
11639 /* If we couldn't simplify X any other way, just enclose it in a
11640 SUBREG. Normally, this SUBREG won't match, but some patterns may
11641 include an explicit SUBREG or we may simplify it further in combine. */
11642 else
11643 {
11644 rtx res;
11647 {
11652 }
11656 }
11658 fail:
11660 }
11661 \f
11662 /* Try to simplify a comparison between OP0 and a constant OP1,
11663 where CODE is the comparison code that will be tested, into a
11664 (CODE OP0 const0_rtx) form.
11666 The result is a possibly different comparison code to use.
11667 *POP1 may be updated. */
11669 static enum rtx_code
11672 {
11673 scalar_int_mode int_mode;
11676 /* Get the constant we are comparing against and turn off all bits
11677 not on in our mode. */
11681 /* If we are comparing against a constant power of two and the value
11682 being compared can only have that single bit nonzero (e.g., it was
11683 `and'ed with that bit), we can replace this with a comparison
11684 with zero. */
11693 {
11696 }
11698 /* Similarly, if we are comparing a value known to be either -1 or
11699 0 with -1, change it to the opposite comparison against zero. */
11705 {
11708 }
11710 /* Do some canonicalizations based on the comparison code. We prefer
11711 comparisons against zero and then prefer equality comparisons.
11712 If we can reduce the size of a constant, we will do that too. */
11714 {
11716 /* < C is equivalent to <= (C - 1) */
11718 {
11721 /* ... fall through to LE case below. */
11723 }
11724 else
11728 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11730 {
11733 }
11735 /* If we are doing a <= 0 comparison on a value known to have
11736 a zero sign bit, we can replace this with == 0. */
11747 /* >= C is equivalent to > (C - 1). */
11749 {
11752 /* ... fall through to GT below. */
11754 }
11755 else
11759 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11761 {
11764 }
11766 /* If we are doing a > 0 comparison on a value known to have
11767 a zero sign bit, we can replace this with != 0. */
11778 /* < C is equivalent to <= (C - 1). */
11780 {
11783 /* ... fall through ... */
11785 }
11786 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11791 {
11795 }
11796 else
11800 /* unsigned <= 0 is equivalent to == 0 */
11803 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11807 == ((HOST_WIDE_INT_1U
11809 {
11812 }
11816 /* >= C is equivalent to > (C - 1). */
11818 {
11821 /* ... fall through ... */
11823 }
11825 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11830 {
11834 }
11835 else
11839 /* unsigned > 0 is equivalent to != 0 */
11842 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11846 == (HOST_WIDE_INT_1U
11848 {
11851 }
11856 }
11860 }
11861 \f
11862 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11863 comparison code that will be tested.
11865 The result is a possibly different comparison code to use. *POP0 and
11866 *POP1 may be updated.
11868 It is possible that we might detect that a comparison is either always
11869 true or always false. However, we do not perform general constant
11870 folding in combine, so this knowledge isn't useful. Such tautologies
11871 should have been detected earlier. Hence we ignore all such cases. */
11873 static enum rtx_code
11875 {
11881 opt_scalar_int_mode tmode_iter;
11883 /* Try a few ways of applying the same transformation to both operands. */
11885 {
11886 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11887 so check specially. */
11906 {
11909 }
11911 /* If both operands are the same constant shift, see if we can ignore the
11912 shift. We can if the shift is a rotate or if the bits shifted out of
11913 this shift are known to be zero for both inputs and if the type of
11914 comparison is compatible with the shift. */
11927 {
11940 else
11942 }
11944 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11945 SUBREGs are of the same mode, and, in both cases, the AND would
11946 be redundant if the comparison was done in the narrower mode,
11947 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11948 and the operand's possibly nonzero bits are 0xffffff01; in that case
11949 if we only care about QImode, we don't need the AND). This case
11950 occurs if the output mode of an scc insn is not SImode and
11951 STORE_FLAG_VALUE == 1 (e.g., the 386).
11953 Similarly, check for a case where the AND's are ZERO_EXTEND
11954 operations from some narrower mode even though a SUBREG is not
11955 present. */
11960 {
11976 {
11980 /* The resulting comparison is always unsigned since we masked
11981 off the original sign bit. */
11985 }
11991 {
11997 }
12001 }
12003 /* If both operands are NOT, we can strip off the outer operation
12004 and adjust the comparison code for swapped operands; similarly for
12005 NEG, except that this must be an equality comparison. */
12011 else
12013 }
12015 /* If the first operand is a constant, swap the operands and adjust the
12016 comparison code appropriately, but don't do this if the second operand
12017 is already a constant integer. */
12019 {
12022 }
12024 /* We now enter a loop during which we will try to simplify the comparison.
12025 For the most part, we only are concerned with comparisons with zero,
12026 but some things may really be comparisons with zero but not start
12027 out looking that way. */
12030 {
12032 scalar_int_mode int_mode;
12036 HOST_WIDE_INT const_op;
12038 /* We only want to handle integral modes. This catches VOIDmode,
12039 CCmode, and the floating-point modes. An exception is that we
12040 can handle VOIDmode if OP0 is a COMPARE or a comparison
12041 operation. */
12048 /* Try to simplify the compare to constant, possibly changing the
12049 comparison op, and/or changing op1 to zero. */
12053 /* Compute some predicates to simplify code below. */
12060 /* If this is a sign bit comparison and we can do arithmetic in
12061 MODE, say that we will only be needing the sign bit of OP0. */
12066 HOST_WIDE_INT_1U
12071 {
12072 /* We can't do anything if OP0 is a condition code value, rather
12073 than an actual data value. */
12079 /* Get the two operands being compared. */
12082 else
12085 /* Check for the cases where we simply want the result of the
12086 earlier test or the opposite of that result. */
12090 {
12094 else
12098 {
12103 }
12104 }
12106 }
12112 /* Now try cases based on the opcode of OP0. If none of the cases
12113 does a "continue", we exit this loop immediately after the
12114 switch. */
12119 {
12121 /* If we are extracting a single bit from a variable position in
12122 a constant that has only a single bit set and are comparing it
12123 with zero, we can convert this into an equality comparison
12124 between the position and the location of the single bit. */
12125 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12126 have already reduced the shift count modulo the word size. */
12132 {
12140 /* Result is nonzero iff shift count is equal to I. */
12143 }
12145 /* fall through */
12150 {
12153 }
12157 /* If testing for equality, we can take the NOT of the constant. */
12160 {
12164 }
12166 /* If just looking at the sign bit, reverse the sense of the
12167 comparison. */
12169 {
12173 }
12177 /* If testing for equality, we can take the NEG of the constant. */
12180 {
12184 }
12186 /* The remaining cases only apply to comparisons with zero. */
12190 /* When X is ABS or is known positive,
12191 (neg X) is < 0 if and only if X != 0. */
12199 {
12203 }
12205 /* If we have NEG of something whose two high-order bits are the
12206 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12208 {
12212 }
12216 /* If we are testing equality and our count is a constant, we
12217 can perform the inverse operation on our RHS. */
12221 {
12225 }
12227 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12228 a particular bit. Convert it to an AND of a constant of that
12229 bit. This will be converted into a ZERO_EXTRACT. */
12233 {
12235 (HOST_WIDE_INT_1U
12240 }
12242 /* Fall through. */
12245 /* ABS is ignorable inside an equality comparison with zero. */
12247 {
12250 }
12254 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12255 (compare FOO CONST) if CONST fits in FOO's mode and we
12256 are either testing inequality or have an unsigned
12257 comparison with ZERO_EXTEND or a signed comparison with
12258 SIGN_EXTEND. But don't do it if we don't have a compare
12259 insn of the given mode, since we'd have to revert it
12260 later on, and then we wouldn't know whether to sign- or
12261 zero-extend. */
12263 && ! unsigned_comparison_p
12267 {
12270 }
12274 /* Check for the case where we are comparing A - C1 with C2, that is
12276 (subreg:MODE (plus (A) (-C1))) op (C2)
12278 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12279 comparison in the wider mode. One of the following two conditions
12280 must be true in order for this to be valid:
12282 1. The mode extension results in the same bit pattern being added
12283 on both sides and the comparison is equality or unsigned. As
12284 C2 has been truncated to fit in MODE, the pattern can only be
12285 all 0s or all 1s.
12287 2. The mode extension results in the sign bit being copied on
12288 each side.
12290 The difficulty here is that we have predicates for A but not for
12291 (A - C1) so we need to check that C1 is within proper bounds so
12292 as to perturbate A as little as possible. */
12301 {
12309 /* (A - C1) zero-extends if it is positive and sign-extends
12310 if it is negative, C2 both zero- and sign-extends. */
12314 /* (A - C1) sign-extends if it is positive and 1-extends
12315 if it is negative, C2 both sign- and 1-extends. */
12322 /* (A - C1) always sign-extends, like C2. */
12326 {
12329 }
12330 }
12332 /* If the inner mode is narrower and we are extracting the low part,
12333 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12335 ;
12344 {
12345 /* Remove outer subregs that don't do anything. */
12350 {
12354 }
12356 }
12357 else
12360 /* FALLTHROUGH */
12369 {
12372 }
12376 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12377 this for equality comparisons due to pathological cases involving
12378 overflows. */
12382 {
12386 }
12388 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12391 {
12395 }
12399 /* We used to optimize signed comparisons against zero, but that
12400 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12401 arrive here as equality comparisons, or (GEU, LTU) are
12402 optimized away. No need to special-case them. */
12404 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12405 (eq B (minus A C)), whichever simplifies. We can only do
12406 this for equality comparisons due to pathological cases involving
12407 overflows. */
12411 {
12415 }
12420 {
12424 }
12426 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12427 of bits in X minus 1, is one iff X > 0. */
12432 {
12436 }
12440 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12441 if C is zero or B is a constant. */
12445 {
12449 }
12454 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12455 iff X <= 0. */
12459 {
12463 }
12467 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12468 will be converted to a ZERO_EXTRACT later. */
12472 {
12477 }
12479 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12480 zero and X is a comparison and C1 and C2 describe only bits set
12481 in STORE_FLAG_VALUE, we can compare with X. */
12489 {
12496 {
12499 }
12500 }
12502 /* If we are doing an equality comparison of an AND of a bit equal
12503 to the sign bit, replace this with a LT or GE comparison of
12504 the underlying value. */
12511 {
12515 }
12517 /* If this AND operation is really a ZERO_EXTEND from a narrower
12518 mode, the constant fits within that mode, and this is either an
12519 equality or unsigned comparison, try to do this comparison in
12520 the narrower mode.
12522 Note that in:
12524 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12525 -> (ne:DI (reg:SI 4) (const_int 0))
12527 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12528 known to hold a value of the required mode the
12529 transformation is invalid. */
12537 {
12540 }
12542 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12543 fits in both M1 and M2 and the SUBREG is either paradoxical
12544 or represents the low part, permute the SUBREG and the AND
12545 and try again. */
12548 {
12550 /* Require an integral mode, to avoid creating something like
12551 (AND:SF ...). */
12554 /* It is unsafe to commute the AND into the SUBREG if the
12555 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12556 not defined. As originally written the upper bits
12557 have a defined value due to the AND operation.
12558 However, if we commute the AND inside the SUBREG then
12559 they no longer have defined values and the meaning of
12560 the code has been changed.
12561 Also C1 should not change value in the smaller mode,
12562 see PR67028 (a positive C1 can become negative in the
12563 smaller mode, so that the AND does no longer mask the
12564 upper bits). */
12565 && ((WORD_REGISTER_OPERATIONS
12577 {
12583 }
12584 }
12586 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12590 {
12595 }
12597 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12598 (eq (and (lshiftrt X) 1) 0).
12599 Also handle the case where (not X) is expressed using xor. */
12603 {
12613 == HOST_WIDE_INT_1U
12615 {
12616 op0
12621 }
12622 }
12626 /* If we have (compare (ashift FOO N) (const_int C)) and
12627 the high order N bits of FOO (N+1 if an inequality comparison)
12628 are known to be zero, we can do this by comparing FOO with C
12629 shifted right N bits so long as the low-order N bits of C are
12630 zero. */
12642 {
12643 /* We must perform a logical shift, not an arithmetic one,
12644 as we want the top N bits of C to be zero. */
12651 }
12653 /* If we are doing a sign bit comparison, it means we are testing
12654 a particular bit. Convert it to the appropriate AND. */
12657 {
12659 (HOST_WIDE_INT_1U
12664 }
12666 /* If this an equality comparison with zero and we are shifting
12667 the low bit to the sign bit, we can convert this to an AND of the
12668 low-order bit. */
12672 {
12675 }
12679 /* If this is an equality comparison with zero, we can do this
12680 as a logical shift, which might be much simpler. */
12683 {
12688 }
12690 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12691 do the comparison in a narrower mode. */
12701 {
12704 }
12706 /* Likewise if OP0 is a PLUS of a sign extension with a
12707 constant, which is usually represented with the PLUS
12708 between the shifts. */
12720 {
12728 new_const);
12730 }
12732 /* FALLTHROUGH */
12734 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12735 the low order N bits of FOO are known to be zero, we can do this
12736 by comparing FOO with C shifted left N bits so long as no
12737 overflow occurs. Even if the low order N bits of FOO aren't known
12738 to be zero, if the comparison is >= or < we can use the same
12739 optimization and for > or <= by setting all the low
12740 order N bits in the comparison constant. */
12751 {
12752 unsigned HOST_WIDE_INT low_bits
12754 & ((HOST_WIDE_INT_1U
12757 {
12758 /* If the shift was logical, then we must make the condition
12759 unsigned. */
12768 const_op
12773 }
12774 }
12776 /* If we are using this shift to extract just the sign bit, we
12777 can replace this with an LT or GE comparison. */
12782 {
12786 }
12791 }
12794 }
12796 /* Now make any compound operations involved in this comparison. Then,
12797 check for an outmost SUBREG on OP0 that is not doing anything or is
12798 paradoxical. The latter transformation must only be performed when
12799 it is known that the "extra" bits will be the same in op0 and op1 or
12800 that they don't matter. There are three cases to consider:
12802 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12803 care bits and we can assume they have any convenient value. So
12804 making the transformation is safe.
12806 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12807 In this case the upper bits of op0 are undefined. We should not make
12808 the simplification in that case as we do not know the contents of
12809 those bits.
12811 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12812 In that case we know those bits are zeros or ones. We must also be
12813 sure that they are the same as the upper bits of op1.
12815 We can never remove a SUBREG for a non-equality comparison because
12816 the sign bit is in a different place in the underlying object. */
12829 {
12831 {
12832 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12833 implemented. */
12835 {
12838 }
12839 }
12843 {
12848 }
12849 }
12851 /* We now do the opposite procedure: Some machines don't have compare
12852 insns in all modes. If OP0's mode is an integer mode smaller than a
12853 word and we can't do a compare in that mode, see if there is a larger
12854 mode for which we can do the compare. There are a number of cases in
12855 which we can use the wider mode. */
12861 {
12866 {
12869 /* If this is a test for negative, we can make an explicit
12870 test of the sign bit. Test this first so we can use
12871 a paradoxical subreg to extend OP0. */
12875 {
12876 unsigned HOST_WIDE_INT sign
12883 }
12885 /* If the only nonzero bits in OP0 and OP1 are those in the
12886 narrower mode and this is an equality or unsigned comparison,
12887 we can use the wider mode. Similarly for sign-extended
12888 values, in which case it is true for all comparisons. */
12905 {
12906 /* If OP0 is an AND and we don't have an AND in MODE either,
12907 make a new AND in the proper mode. */
12915 else
12916 {
12918 {
12923 }
12924 else
12925 {
12930 }
12932 }
12933 }
12934 }
12935 }
12937 /* We may have changed the comparison operands. Re-canonicalize. */
12939 {
12942 }
12944 /* If this machine only supports a subset of valid comparisons, see if we
12945 can convert an unsupported one into a supported one. */
12952 }
12953 \f
12954 /* Utility function for record_value_for_reg. Count number of
12955 rtxs in X. */
12956 static int
12958 {
12965 {
12985 }
12996 }
12997 \f
12998 /* Utility function for following routine. Called when X is part of a value
12999 being stored into last_set_value. Sets last_set_table_tick
13000 for each register mentioned. Similar to mention_regs in cse.c */
13002 static void
13004 {
13010 {
13016 {
13019 }
13022 }
13026 {
13027 /* Check for identical subexpressions. If x contains
13028 identical subexpression we only have to traverse one of
13029 them. */
13031 {
13032 /* Note that at this point x1 has already been
13033 processed. */
13037 /* If x0 and x1 are identical then there is no need to
13038 process x0. */
13042 /* If x0 is identical to a subexpression of x1 then while
13043 processing x1, x0 has already been processed. Thus we
13044 are done with x. */
13049 /* If x1 is identical to a subexpression of x0 then we
13050 still have to process the rest of x0. */
13053 {
13056 }
13057 }
13060 }
13064 }
13066 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13067 are saying that the register is clobbered and we no longer know its
13068 value. If INSN is zero, don't update reg_stat[].last_set; this is
13069 only permitted with VALUE also zero and is used to invalidate the
13070 register. */
13072 static void
13074 {
13080 /* If VALUE contains REG and we have a previous value for REG, substitute
13081 the previous value. */
13083 {
13084 rtx tem;
13086 /* Set things up so get_last_value is allowed to see anything set up to
13087 our insn. */
13091 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13092 it isn't going to be useful and will take a lot of time to process,
13093 so just use the CLOBBER. */
13096 {
13102 {
13103 /* If there are two or more occurrences of REG in VALUE,
13104 prevent the value from growing too much. */
13107 }
13110 }
13111 }
13113 /* For each register modified, show we don't know its value, that
13114 we don't know about its bitwise content, that its value has been
13115 updated, and that we don't know the location of the death of the
13116 register. */
13118 {
13130 }
13132 /* Mark registers that are being referenced in this value. */
13136 /* Now update the status of each register being set.
13137 If someone is using this register in this block, set this register
13138 to invalid since we will get confused between the two lives in this
13139 basic block. This makes using this register always invalid. In cse, we
13140 scan the table to invalidate all entries using this register, but this
13141 is too much work for us. */
13144 {
13150 else
13152 }
13154 /* The value being assigned might refer to X (like in "x++;"). In that
13155 case, we must replace it with (clobber (const_int 0)) to prevent
13156 infinite loops. */
13159 {
13163 }
13165 /* For the main register being modified, update the value, the mode, the
13166 nonzero bits, and the number of sign bit copies. */
13171 {
13179 rsp->last_set_sign_bit_copies
13181 }
13182 }
13184 /* Called via note_stores from record_dead_and_set_regs to handle one
13185 SET or CLOBBER in an insn. DATA is the instruction in which the
13186 set is occurring. */
13188 static void
13190 {
13197 {
13201 }
13204 {
13205 /* If we are setting the whole register, we know its value. Otherwise
13206 show that we don't know the value. We can handle SUBREG in
13207 some cases. */
13218 else
13220 }
13222 /* Ignore pushes, they clobber nothing. */
13225 }
13227 /* Update the records of when each REG was most recently set or killed
13228 for the things done by INSN. This is the last thing done in processing
13229 INSN in the combiner loop.
13231 We update reg_stat[], in particular fields last_set, last_set_value,
13232 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13233 last_death, and also the similar information mem_last_set (which insn
13234 most recently modified memory) and last_call_luid (which insn was the
13235 most recent subroutine call). */
13237 static void
13239 {
13240 rtx link;
13244 {
13247 {
13252 {
13257 }
13258 }
13261 }
13264 {
13265 hard_reg_set_iterator hrsi;
13267 {
13279 }
13283 /* We can't combine into a call pattern. Remember, though, that
13284 the return value register is set at this LUID. We could
13285 still replace a register with the return value from the
13286 wrong subroutine call! */
13288 }
13289 else
13291 }
13293 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13294 register present in the SUBREG, so for each such SUBREG go back and
13295 adjust nonzero and sign bit information of the registers that are
13296 known to have some zero/sign bits set.
13298 This is needed because when combine blows the SUBREGs away, the
13299 information on zero/sign bits is lost and further combines can be
13300 missed because of that. */
13302 static void
13304 {
13306 rtx set;
13314 {
13323 {
13326 }
13330 {
13333 }
13336 {
13339 }
13340 else
13342 }
13343 }
13345 /* Check if X, a register, is known to contain a value already
13346 truncated to MODE. In this case we can use a subreg to refer to
13347 the truncated value even though in the generic case we would need
13348 an explicit truncation. */
13350 static bool
13352 {
13364 }
13366 /* If X is a hard reg or a subreg record the mode that the register is
13367 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13368 able to turn a truncate into a subreg using this information. Return true
13369 if traversing X is complete. */
13371 static bool
13373 {
13374 machine_mode truncated_mode;
13378 {
13390 }
13391 /* ??? For hard-regs we now record everything. We might be able to
13392 optimize this using last_set_mode. */
13395 else
13402 {
13405 }
13408 }
13410 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13411 the modes they are used in. This can help truning TRUNCATEs into
13412 SUBREGs. */
13414 static void
13416 {
13421 }
13423 /* Scan X for promoted SUBREGs. For each one found,
13424 note what it implies to the registers used in it. */
13426 static void
13428 {
13433 else
13434 {
13440 {
13450 }
13451 }
13452 }
13453 \f
13454 /* Verify that all the registers and memory references mentioned in *LOC are
13455 still valid. *LOC was part of a value set in INSN when label_tick was
13456 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13457 the invalid references with (clobber (const_int 0)) and return 1. This
13458 replacement is useful because we often can get useful information about
13459 the form of a value (e.g., if it was produced by a shift that always
13460 produces -1 or 0) even though we don't know exactly what registers it
13461 was produced from. */
13463 static int
13465 {
13472 {
13478 {
13481 /* If this is a pseudo-register that was only set once and not
13482 live at the beginning of the function, it is always valid. */
13486 && (!REGNO_REG_SET_P
13488 regno)))
13490 {
13494 }
13495 }
13498 }
13499 /* If this is a memory reference, make sure that there were no stores after
13500 it that might have clobbered the value. We don't have alias info, so we
13501 assume any store invalidates it. Moreover, we only have local UIDs, so
13502 we also assume that there were stores in the intervening basic blocks. */
13505 {
13509 }
13512 {
13514 {
13515 /* Check for identical subexpressions. If x contains
13516 identical subexpression we only have to traverse one of
13517 them. */
13519 {
13520 /* Note that at this point x0 has already been checked
13521 and found valid. */
13525 /* If x0 and x1 are identical then x is also valid. */
13529 /* If x1 is identical to a subexpression of x0 then
13530 while checking x0, x1 has already been checked. Thus
13531 it is valid and so as x. */
13536 /* If x0 is identical to a subexpression of x1 then x is
13537 valid iff the rest of x1 is valid. */
13540 return
13544 }
13549 }
13555 }
13557 /* If we haven't found a reason for it to be invalid, it is valid. */
13559 }
13561 /* Get the last value assigned to X, if known. Some registers
13562 in the value may be replaced with (clobber (const_int 0)) if their value
13563 is known longer known reliably. */
13565 static rtx
13567 {
13569 rtx value;
13572 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13573 then convert it to the desired mode. If this is a paradoxical SUBREG,
13574 we cannot predict what values the "extra" bits might have. */
13588 /* If we don't have a value, or if it isn't for this basic block and
13589 it's either a hard register, set more than once, or it's a live
13590 at the beginning of the function, return 0.
13592 Because if it's not live at the beginning of the function then the reg
13593 is always set before being used (is never used without being set).
13594 And, if it's set only once, and it's always set before use, then all
13595 uses must have the same last value, even if it's not from this basic
13596 block. */
13603 || REGNO_REG_SET_P
13607 /* If the value was set in a later insn than the ones we are processing,
13608 we can't use it even if the register was only set once. */
13613 /* If fewer bits were set than what we are asked for now, we cannot use
13614 the value. */
13619 /* If the value has all its registers valid, return it. */
13623 /* Otherwise, make a copy and replace any invalid register with
13624 (clobber (const_int 0)). If that fails for some reason, return 0. */
13631 }
13632 \f
13633 /* Return nonzero if expression X refers to a REG or to memory
13634 that is set in an instruction more recent than FROM_LUID. */
13636 static int
13638 {
13644 {
13648 #ifdef PUSH_ROUNDING
13649 /* Don't allow uses of the stack pointer to be moved,
13650 because we don't know whether the move crosses a push insn. */
13653 #endif
13655 {
13661 }
13663 }
13671 {
13673 {
13678 }
13682 }
13684 }
13685 \f
13686 /* Define three variables used for communication between the following
13687 routines. */
13692 /* Function called via note_stores from reg_dead_at_p.
13694 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13695 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13697 static void
13699 {
13709 }
13711 /* Return nonzero if REG is known to be dead at INSN.
13713 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13714 referencing REG, it is dead. If we hit a SET referencing REG, it is
13715 live. Otherwise, see if it is live or dead at the start of the basic
13716 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13717 must be assumed to be always live. */
13719 static int
13721 {
13722 basic_block block;
13725 /* Set variables for reg_dead_at_p_1. */
13731 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13732 we allow the machine description to decide whether use-and-clobber
13733 patterns are OK. */
13735 {
13739 }
13741 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13742 beginning of basic block. */
13745 {
13747 {
13757 }
13763 }
13765 /* Look at live-in sets for the basic block that we were in. */
13771 }
13772 \f
13773 /* Note hard registers in X that are used. */
13775 static void
13777 {
13783 {
13787 CASE_CONST_ANY:
13792 /* CC0 must die in the insn after it is set, so we don't need to take
13793 special note of it here. */
13798 /* If we are clobbering a MEM, mark any hard registers inside the
13799 address as used. */
13806 /* A hard reg in a wide mode may really be multiple registers.
13807 If so, mark all of them just like the first. */
13809 {
13810 /* None of this applies to the stack, frame or arg pointers. */
13812 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13820 }
13824 {
13825 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13826 the address. */
13838 }
13843 }
13845 /* Recursively scan the operands of this expression. */
13847 {
13851 {
13855 {
13860 }
13861 }
13862 }
13863 }
13864 \f
13865 /* Remove register number REGNO from the dead registers list of INSN.
13867 Return the note used to record the death, if there was one. */
13869 rtx
13871 {
13878 }
13880 /* For each register (hardware or pseudo) used within expression X, if its
13881 death is in an instruction with luid between FROM_LUID (inclusive) and
13882 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13883 list headed by PNOTES.
13885 That said, don't move registers killed by maybe_kill_insn.
13887 This is done when X is being merged by combination into TO_INSN. These
13888 notes will then be distributed as needed. */
13890 static void
13893 {
13899 {
13903 /* Don't move the register if it gets killed in between from and to. */
13912 {
13915 /* It is possible for the call above to return 0. This can occur
13916 when last_death points to I2 or I1 that we combined with.
13917 In that case make a new note.
13919 We must also check for the case where X is a hard register
13920 and NOTE is a death note for a range of hard registers
13921 including X. In that case, we must put REG_DEAD notes for
13922 the remaining registers in place of NOTE. */
13926 {
13935 }
13937 /* If we didn't find any note, or if we found a REG_DEAD note that
13938 covers only part of the given reg, and we have a multi-reg hard
13939 register, then to be safe we must check for REG_DEAD notes
13940 for each register other than the first. They could have
13941 their own REG_DEAD notes lying around. */
13948 {
13955 else
13961 }
13964 {
13967 }
13968 else
13970 }
13973 }
13976 {
13981 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13982 that accesses one word of a multi-word item, some
13983 piece of everything register in the expression is used by
13984 this insn, so remove any old death. */
13985 /* ??? So why do we test for equality of the sizes? */
13991 {
13994 }
13996 /* If this is some other SUBREG, we know it replaces the entire
13997 value, so use that as the destination. */
14001 /* If this is a MEM, adjust deaths of anything used in the address.
14002 For a REG (the only other possibility), the entire value is
14003 being replaced so the old value is not used in this insn. */
14009 }
14018 {
14020 {
14025 }
14028 }
14029 }
14030 \f
14031 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14032 pattern of an insn. X must be a REG. */
14034 static int
14036 {
14040 {
14042 rtx target;
14049 else
14066 }
14074 }
14075 \f
14076 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14077 as appropriate. I3 and I2 are the insns resulting from the combination
14078 insns including FROM (I2 may be zero).
14080 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14081 not need REG_DEAD notes because they are being substituted for. This
14082 saves searching in the most common cases.
14084 Each note in the list is either ignored or placed on some insns, depending
14085 on the type of note. */
14087 static void
14090 {
14092 rtx tem_note;
14096 {
14101 {
14104 /* Doesn't matter much where we put this, as long as it's somewhere.
14105 It is preferable to keep these notes on branches, which is most
14106 likely to be i3. */
14113 else
14114 {
14117 }
14121 /* These notes must remain with the call or trapping instruction. */
14126 else
14127 {
14133 /* ??? Otherwise assume we've combined things such that we
14134 can now prove that the instructions can't trap. Drop the
14135 note in this case. */
14136 }
14140 /* ??? How to distribute between i3-i1. Assume i3 contains the
14141 entire adjustment. Assert i3 contains at least some adjust. */
14143 {
14145 /* fixup_args_size_notes looks at REG_NORETURN note,
14146 so ensure the note is placed there first. */
14148 {
14152 {
14158 }
14159 }
14161 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14162 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14165 && !ACCUMULATE_OUTGOING_ARGS
14167 }
14175 /* These notes must remain with the call. It should not be
14176 possible for both I2 and I3 to be a call. */
14179 else
14180 {
14183 }
14187 /* Any clobbers for i3 may still exist, and so we must process
14188 REG_UNUSED notes from that insn.
14190 Any clobbers from i2 or i1 can only exist if they were added by
14191 recog_for_combine. In that case, recog_for_combine created the
14192 necessary REG_UNUSED notes. Trying to keep any original
14193 REG_UNUSED notes from these insns can cause incorrect output
14194 if it is for the same register as the original i3 dest.
14195 In that case, we will notice that the register is set in i3,
14196 and then add a REG_UNUSED note for the destination of i3, which
14197 is wrong. However, it is possible to have REG_UNUSED notes from
14198 i2 or i1 for register which were both used and clobbered, so
14199 we keep notes from i2 or i1 if they will turn into REG_DEAD
14200 notes. */
14202 /* If this register is set or clobbered in I3, put the note there
14203 unless there is one already. */
14205 {
14213 }
14214 /* Otherwise, if this register is used by I3, then this register
14215 now dies here, so we must put a REG_DEAD note here unless there
14216 is one already. */
14222 {
14225 }
14231 /* These notes say something about results of an insn. We can
14232 only support them if they used to be on I3 in which case they
14233 remain on I3. Otherwise they are ignored.
14235 If the note refers to an expression that is not a constant, we
14236 must also ignore the note since we cannot tell whether the
14237 equivalence is still true. It might be possible to do
14238 slightly better than this (we only have a problem if I2DEST
14239 or I1DEST is present in the expression), but it doesn't
14240 seem worth the trouble. */
14248 /* These notes say something about how a register is used. They must
14249 be present on any use of the register in I2 or I3. */
14254 {
14257 else
14259 }
14264 /* This can show up in several ways -- either directly in the
14265 pattern, or hidden off in the constant pool with (or without?)
14266 a REG_EQUAL note. */
14267 /* ??? Ignore the without-reg_equal-note problem for now. */
14279 {
14282 else
14284 }
14286 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14287 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14288 there. */
14293 {
14300 }
14306 {
14314 }
14318 /* This note says something about the value of a register prior
14319 to the execution of an insn. It is too much trouble to see
14320 if the note is still correct in all situations. It is better
14321 to simply delete it. */
14325 /* If we replaced the right hand side of FROM_INSN with a
14326 REG_EQUAL note, the original use of the dying register
14327 will not have been combined into I3 and I2. In such cases,
14328 FROM_INSN is guaranteed to be the first of the combined
14329 instructions, so we simply need to search back before
14330 FROM_INSN for the previous use or set of this register,
14331 then alter the notes there appropriately.
14333 If the register is used as an input in I3, it dies there.
14334 Similarly for I2, if it is nonzero and adjacent to I3.
14336 If the register is not used as an input in either I3 or I2
14337 and it is not one of the registers we were supposed to eliminate,
14338 there are two possibilities. We might have a non-adjacent I2
14339 or we might have somehow eliminated an additional register
14340 from a computation. For example, we might have had A & B where
14341 we discover that B will always be zero. In this case we will
14342 eliminate the reference to A.
14344 In both cases, we must search to see if we can find a previous
14345 use of A and put the death note there. */
14351 else
14352 {
14363 && !(i2mod
14365 i2mod_old_rhs)))
14370 /* If the new I2 sets the same register that is marked dead
14371 in the note, we do not know where to put the note.
14372 Give up. */
14375 }
14378 {
14382 {
14384 {
14388 }
14390 /* If the register is being set at TEM_INSN, see if that is all
14391 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14392 into a REG_UNUSED note instead. Don't delete sets to
14393 global register vars. */
14397 {
14408 ;
14410 /* Verify that it was the set, and not a clobber that
14411 modified the register.
14413 CC0 targets must be careful to maintain setter/user
14414 pairs. If we cannot delete the setter due to side
14415 effects, mark the user with an UNUSED note instead
14416 of deleting it. */
14420 && (!HAVE_cc0
14424 {
14425 /* Move the notes and links of TEM_INSN elsewhere.
14426 This might delete other dead insns recursively.
14427 First set the pattern to something that won't use
14428 any register. */
14447 /* Delete the setter too. */
14449 {
14462 }
14463 }
14464 else
14465 {
14468 /* If there isn't already a REG_UNUSED note, put one
14469 here. Do not place a REG_DEAD note, even if
14470 the register is also used here; that would not
14471 match the algorithm used in lifetime analysis
14472 and can cause the consistency check in the
14473 scheduler to fail. */
14478 }
14479 }
14483 {
14486 /* If we are doing a 3->2 combination, and we have a
14487 register which formerly died in i3 and was not used
14488 by i2, which now no longer dies in i3 and is used in
14489 i2 but does not die in i2, and place is between i2
14490 and i3, then we may need to move a link from place to
14491 i2. */
14493 && from_insn
14496 {
14500 }
14502 }
14506 }
14508 }
14510 /* If the register is set or already dead at PLACE, we needn't do
14511 anything with this note if it is still a REG_DEAD note.
14512 We check here if it is set at all, not if is it totally replaced,
14513 which is what `dead_or_set_p' checks, so also check for it being
14514 set partially. */
14517 {
14523 {
14524 /* Unless the register previously died in PLACE, clear
14525 last_death. [I no longer understand why this is
14526 being done.] */
14530 }
14531 else
14534 /* If this is a death note for a hard reg that is occupying
14535 multiple registers, ensure that we are still using all
14536 parts of the object. If we find a piece of the object
14537 that is unused, we must arrange for an appropriate REG_DEAD
14538 note to be added for it. However, we can't just emit a USE
14539 and tag the note to it, since the register might actually
14540 be dead; so we recourse, and the recursive call then finds
14541 the previous insn that used this register. */
14544 {
14553 {
14556 }
14559 {
14560 /* Put only REG_DEAD notes for pieces that are
14561 not already dead or set. */
14565 {
14572 {
14574 NULL_RTX);
14578 NULL_RTX);
14579 }
14584 {
14586 {
14590 }
14594 {
14597 }
14598 }
14599 }
14602 }
14603 }
14604 }
14608 /* Any other notes should not be present at this point in the
14609 compilation. */
14611 }
14614 {
14617 }
14621 }
14622 }
14623 \f
14624 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14625 I3, I2, and I1 to new locations. This is also called to add a link
14626 pointing at I3 when I3's destination is changed. */
14628 static void
14630 {
14634 {
14641 /* If the insn that this link points to is a NOTE, ignore it. */
14650 {
14653 {
14669 }
14672 }
14673 else
14683 /* A LOG_LINK is defined as being placed on the first insn that uses
14684 a register and points to the insn that sets the register. Start
14685 searching at the next insn after the target of the link and stop
14686 when we reach a set of the register or the end of the basic block.
14688 Note that this correctly handles the link that used to point from
14689 I3 to I2. Also note that not much searching is typically done here
14690 since most links don't point very far away. */
14699 {
14703 }
14706 {
14709 }
14713 /* If we found a place to put the link, place it there unless there
14714 is already a link to the same insn as LINK at that point. */
14717 {
14725 {
14729 /* Set added_links_insn to the earliest insn we added a
14730 link to. */
14734 }
14735 }
14736 }
14737 }
14738 \f
14739 /* Check for any register or memory mentioned in EQUIV that is not
14740 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14741 of EXPR where some registers may have been replaced by constants. */
14743 static bool
14745 {
14748 {
14753 }
14755 }
14756 \f
14757 DEBUG_FUNCTION void
14759 {
14760 fprintf
14762 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14764 }
14766 void
14768 {
14769 fprintf
14771 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14773 }
14774 \f
14775 /* Try combining insns through substitution. */
14776 static unsigned int
14778 {
14788 rebuild_jump_labels_after_combine
14791 /* Combining insns may have turned an indirect jump into a
14792 direct jump. Rebuild the JUMP_LABEL fields of jumping
14793 instructions. */
14795 {
14802 }
14806 }
14811 {
14821 };
14824 {
14828 {}
14830 /* opt_pass methods: */
14833 {
14835 }
14841 rtl_opt_pass *
14843 {
14845 }