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[official-gcc.git] / gcc / longlong.h
blobf03e25b85bbf8250538c3b257177a2e4f483fb98
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2004,
3 2005, 2007 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 3, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; see the file COPYING3. If not see
17 <http://www.gnu.org/licenses/>. */
18
19 /* You have to define the following before including this file:
20
21 UWtype -- An unsigned type, default type for operations (typically a "word")
22 UHWtype -- An unsigned type, at least half the size of UWtype.
23 UDWtype -- An unsigned type, at least twice as large a UWtype
24 W_TYPE_SIZE -- size in bits of UWtype
25
26 UQItype -- Unsigned 8 bit type.
27 SItype, USItype -- Signed and unsigned 32 bit types.
28 DItype, UDItype -- Signed and unsigned 64 bit types.
29
30 On a 32 bit machine UWtype should typically be USItype;
31 on a 64 bit machine, UWtype should typically be UDItype. */
32
33 #define __BITS4 (W_TYPE_SIZE / 4)
34 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
35 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
36 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
37
38 #ifndef W_TYPE_SIZE
39 #define W_TYPE_SIZE 32
40 #define UWtype USItype
41 #define UHWtype USItype
42 #define UDWtype UDItype
43 #endif
44
45 extern const UQItype __clz_tab[256];
46
47 /* Define auxiliary asm macros.
48
49 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
50 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
52
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
55
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
63
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
66 is rounded towards 0.
67
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first nonzero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
72
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
75
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
81
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
87 and is lost.
88
89 If any of these macros are left undefined for a particular CPU,
90 C macros are used. */
91
92 /* The CPUs come in alphabetical order below.
93
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below!
96 (E.g. WE32100, IBM360.) */
97
98 #if defined (__GNUC__) && !defined (NO_ASM)
99
100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
101 understood by gcc1. Use cpp to avoid major code duplication. */
102 #if __GNUC__ < 2
103 #define __CLOBBER_CC
104 #define __AND_CLOBBER_CC
105 #else /* __GNUC__ >= 2 */
106 #define __CLOBBER_CC : "cc"
107 #define __AND_CLOBBER_CC , "cc"
108 #endif /* __GNUC__ < 2 */
109
110 #if defined (__alpha) && W_TYPE_SIZE == 64
111 #define umul_ppmm(ph, pl, m0, m1) \
112 do { \
113 UDItype __m0 = (m0), __m1 = (m1); \
114 (ph) = __builtin_alpha_umulh (__m0, __m1); \
115 (pl) = __m0 * __m1; \
116 } while (0)
117 #define UMUL_TIME 46
118 #ifndef LONGLONG_STANDALONE
119 #define udiv_qrnnd(q, r, n1, n0, d) \
120 do { UDItype __r; \
121 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
122 (r) = __r; \
123 } while (0)
124 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
125 #define UDIV_TIME 220
126 #endif /* LONGLONG_STANDALONE */
127 #ifdef __alpha_cix__
128 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
129 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
130 #define COUNT_LEADING_ZEROS_0 64
131 #else
132 #define count_leading_zeros(COUNT,X) \
133 do { \
134 UDItype __xr = (X), __t, __a; \
135 __t = __builtin_alpha_cmpbge (0, __xr); \
136 __a = __clz_tab[__t ^ 0xff] - 1; \
137 __t = __builtin_alpha_extbl (__xr, __a); \
138 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
139 } while (0)
140 #define count_trailing_zeros(COUNT,X) \
141 do { \
142 UDItype __xr = (X), __t, __a; \
143 __t = __builtin_alpha_cmpbge (0, __xr); \
144 __t = ~__t & -~__t; \
145 __a = ((__t & 0xCC) != 0) * 2; \
146 __a += ((__t & 0xF0) != 0) * 4; \
147 __a += ((__t & 0xAA) != 0); \
148 __t = __builtin_alpha_extbl (__xr, __a); \
149 __a <<= 3; \
150 __t &= -__t; \
151 __a += ((__t & 0xCC) != 0) * 2; \
152 __a += ((__t & 0xF0) != 0) * 4; \
153 __a += ((__t & 0xAA) != 0); \
154 (COUNT) = __a; \
155 } while (0)
156 #endif /* __alpha_cix__ */
157 #endif /* __alpha */
158
159 #if defined (__arc__) && W_TYPE_SIZE == 32
160 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
161 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
162 : "=r" ((USItype) (sh)), \
163 "=&r" ((USItype) (sl)) \
164 : "%r" ((USItype) (ah)), \
165 "rIJ" ((USItype) (bh)), \
166 "%r" ((USItype) (al)), \
167 "rIJ" ((USItype) (bl)))
168 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
169 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
170 : "=r" ((USItype) (sh)), \
171 "=&r" ((USItype) (sl)) \
172 : "r" ((USItype) (ah)), \
173 "rIJ" ((USItype) (bh)), \
174 "r" ((USItype) (al)), \
175 "rIJ" ((USItype) (bl)))
176 /* Call libgcc routine. */
177 #define umul_ppmm(w1, w0, u, v) \
178 do { \
179 DWunion __w; \
180 __w.ll = __umulsidi3 (u, v); \
181 w1 = __w.s.high; \
182 w0 = __w.s.low; \
183 } while (0)
184 #define __umulsidi3 __umulsidi3
185 UDItype __umulsidi3 (USItype, USItype);
186 #endif
187
188 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
189 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
190 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
191 : "=r" ((USItype) (sh)), \
192 "=&r" ((USItype) (sl)) \
193 : "%r" ((USItype) (ah)), \
194 "rI" ((USItype) (bh)), \
195 "%r" ((USItype) (al)), \
196 "rI" ((USItype) (bl)) __CLOBBER_CC)
197 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
198 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
199 : "=r" ((USItype) (sh)), \
200 "=&r" ((USItype) (sl)) \
201 : "r" ((USItype) (ah)), \
202 "rI" ((USItype) (bh)), \
203 "r" ((USItype) (al)), \
204 "rI" ((USItype) (bl)) __CLOBBER_CC)
205 #define umul_ppmm(xh, xl, a, b) \
206 {register USItype __t0, __t1, __t2; \
207 __asm__ ("%@ Inlined umul_ppmm\n" \
208 " mov %2, %5, lsr #16\n" \
209 " mov %0, %6, lsr #16\n" \
210 " bic %3, %5, %2, lsl #16\n" \
211 " bic %4, %6, %0, lsl #16\n" \
212 " mul %1, %3, %4\n" \
213 " mul %4, %2, %4\n" \
214 " mul %3, %0, %3\n" \
215 " mul %0, %2, %0\n" \
216 " adds %3, %4, %3\n" \
217 " addcs %0, %0, #65536\n" \
218 " adds %1, %1, %3, lsl #16\n" \
219 " adc %0, %0, %3, lsr #16" \
220 : "=&r" ((USItype) (xh)), \
221 "=r" ((USItype) (xl)), \
222 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
223 : "r" ((USItype) (a)), \
224 "r" ((USItype) (b)) __CLOBBER_CC );}
225 #define UMUL_TIME 20
226 #define UDIV_TIME 100
227 #endif /* __arm__ */
228
229 #if defined (__hppa) && W_TYPE_SIZE == 32
230 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
231 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
232 : "=r" ((USItype) (sh)), \
233 "=&r" ((USItype) (sl)) \
234 : "%rM" ((USItype) (ah)), \
235 "rM" ((USItype) (bh)), \
236 "%rM" ((USItype) (al)), \
237 "rM" ((USItype) (bl)))
238 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
239 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
240 : "=r" ((USItype) (sh)), \
241 "=&r" ((USItype) (sl)) \
242 : "rM" ((USItype) (ah)), \
243 "rM" ((USItype) (bh)), \
244 "rM" ((USItype) (al)), \
245 "rM" ((USItype) (bl)))
246 #if defined (_PA_RISC1_1)
247 #define umul_ppmm(w1, w0, u, v) \
248 do { \
249 union \
250 { \
251 UDItype __f; \
252 struct {USItype __w1, __w0;} __w1w0; \
253 } __t; \
254 __asm__ ("xmpyu %1,%2,%0" \
255 : "=x" (__t.__f) \
256 : "x" ((USItype) (u)), \
257 "x" ((USItype) (v))); \
258 (w1) = __t.__w1w0.__w1; \
259 (w0) = __t.__w1w0.__w0; \
260 } while (0)
261 #define UMUL_TIME 8
262 #else
263 #define UMUL_TIME 30
264 #endif
265 #define UDIV_TIME 40
266 #define count_leading_zeros(count, x) \
267 do { \
268 USItype __tmp; \
269 __asm__ ( \
270 "ldi 1,%0\n" \
271 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
272 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
273 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
274 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
275 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
276 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
277 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
278 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
279 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
280 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
281 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
282 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
283 " extru %1,30,1,%1 ; Extract bit 1.\n" \
284 " sub %0,%1,%0 ; Subtract it.\n" \
285 : "=r" (count), "=r" (__tmp) : "1" (x)); \
286 } while (0)
287 #endif
288
289 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
290 #define smul_ppmm(xh, xl, m0, m1) \
291 do { \
292 union {DItype __ll; \
293 struct {USItype __h, __l;} __i; \
294 } __x; \
295 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
296 : "=&r" (__x.__ll) \
297 : "r" (m0), "r" (m1)); \
298 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
299 } while (0)
300 #define sdiv_qrnnd(q, r, n1, n0, d) \
301 do { \
302 union {DItype __ll; \
303 struct {USItype __h, __l;} __i; \
304 } __x; \
305 __x.__i.__h = n1; __x.__i.__l = n0; \
306 __asm__ ("dr %0,%2" \
307 : "=r" (__x.__ll) \
308 : "0" (__x.__ll), "r" (d)); \
309 (q) = __x.__i.__l; (r) = __x.__i.__h; \
310 } while (0)
311 #endif
312
313 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
314 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
315 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
316 : "=r" ((USItype) (sh)), \
317 "=&r" ((USItype) (sl)) \
318 : "%0" ((USItype) (ah)), \
319 "g" ((USItype) (bh)), \
320 "%1" ((USItype) (al)), \
321 "g" ((USItype) (bl)))
322 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
323 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
324 : "=r" ((USItype) (sh)), \
325 "=&r" ((USItype) (sl)) \
326 : "0" ((USItype) (ah)), \
327 "g" ((USItype) (bh)), \
328 "1" ((USItype) (al)), \
329 "g" ((USItype) (bl)))
330 #define umul_ppmm(w1, w0, u, v) \
331 __asm__ ("mull %3" \
332 : "=a" ((USItype) (w0)), \
333 "=d" ((USItype) (w1)) \
334 : "%0" ((USItype) (u)), \
335 "rm" ((USItype) (v)))
336 #define udiv_qrnnd(q, r, n1, n0, dv) \
337 __asm__ ("divl %4" \
338 : "=a" ((USItype) (q)), \
339 "=d" ((USItype) (r)) \
340 : "0" ((USItype) (n0)), \
341 "1" ((USItype) (n1)), \
342 "rm" ((USItype) (dv)))
343 #define count_leading_zeros(count, x) \
344 do { \
345 USItype __cbtmp; \
346 __asm__ ("bsrl %1,%0" \
347 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
348 (count) = __cbtmp ^ 31; \
349 } while (0)
350 #define count_trailing_zeros(count, x) \
351 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
352 #define UMUL_TIME 40
353 #define UDIV_TIME 40
354 #endif /* 80x86 */
355
356 #if defined (__i960__) && W_TYPE_SIZE == 32
357 #define umul_ppmm(w1, w0, u, v) \
358 ({union {UDItype __ll; \
359 struct {USItype __l, __h;} __i; \
360 } __xx; \
361 __asm__ ("emul %2,%1,%0" \
362 : "=d" (__xx.__ll) \
363 : "%dI" ((USItype) (u)), \
364 "dI" ((USItype) (v))); \
365 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
366 #define __umulsidi3(u, v) \
367 ({UDItype __w; \
368 __asm__ ("emul %2,%1,%0" \
369 : "=d" (__w) \
370 : "%dI" ((USItype) (u)), \
371 "dI" ((USItype) (v))); \
372 __w; })
373 #endif /* __i960__ */
374
375 #if defined (__M32R__) && W_TYPE_SIZE == 32
376 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
377 /* The cmp clears the condition bit. */ \
378 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
379 : "=r" ((USItype) (sh)), \
380 "=&r" ((USItype) (sl)) \
381 : "0" ((USItype) (ah)), \
382 "r" ((USItype) (bh)), \
383 "1" ((USItype) (al)), \
384 "r" ((USItype) (bl)) \
385 : "cbit")
386 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
387 /* The cmp clears the condition bit. */ \
388 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
389 : "=r" ((USItype) (sh)), \
390 "=&r" ((USItype) (sl)) \
391 : "0" ((USItype) (ah)), \
392 "r" ((USItype) (bh)), \
393 "1" ((USItype) (al)), \
394 "r" ((USItype) (bl)) \
395 : "cbit")
396 #endif /* __M32R__ */
397
398 #if defined (__mc68000__) && W_TYPE_SIZE == 32
399 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
400 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
401 : "=d" ((USItype) (sh)), \
402 "=&d" ((USItype) (sl)) \
403 : "%0" ((USItype) (ah)), \
404 "d" ((USItype) (bh)), \
405 "%1" ((USItype) (al)), \
406 "g" ((USItype) (bl)))
407 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
408 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
409 : "=d" ((USItype) (sh)), \
410 "=&d" ((USItype) (sl)) \
411 : "0" ((USItype) (ah)), \
412 "d" ((USItype) (bh)), \
413 "1" ((USItype) (al)), \
414 "g" ((USItype) (bl)))
415
416 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
417 #if (defined (__mc68020__) && !defined (__mc68060__))
418 #define umul_ppmm(w1, w0, u, v) \
419 __asm__ ("mulu%.l %3,%1:%0" \
420 : "=d" ((USItype) (w0)), \
421 "=d" ((USItype) (w1)) \
422 : "%0" ((USItype) (u)), \
423 "dmi" ((USItype) (v)))
424 #define UMUL_TIME 45
425 #define udiv_qrnnd(q, r, n1, n0, d) \
426 __asm__ ("divu%.l %4,%1:%0" \
427 : "=d" ((USItype) (q)), \
428 "=d" ((USItype) (r)) \
429 : "0" ((USItype) (n0)), \
430 "1" ((USItype) (n1)), \
431 "dmi" ((USItype) (d)))
432 #define UDIV_TIME 90
433 #define sdiv_qrnnd(q, r, n1, n0, d) \
434 __asm__ ("divs%.l %4,%1:%0" \
435 : "=d" ((USItype) (q)), \
436 "=d" ((USItype) (r)) \
437 : "0" ((USItype) (n0)), \
438 "1" ((USItype) (n1)), \
439 "dmi" ((USItype) (d)))
440
441 #elif defined (__mcoldfire__) /* not mc68020 */
442
443 #define umul_ppmm(xh, xl, a, b) \
444 __asm__ ("| Inlined umul_ppmm\n" \
445 " move%.l %2,%/d0\n" \
446 " move%.l %3,%/d1\n" \
447 " move%.l %/d0,%/d2\n" \
448 " swap %/d0\n" \
449 " move%.l %/d1,%/d3\n" \
450 " swap %/d1\n" \
451 " move%.w %/d2,%/d4\n" \
452 " mulu %/d3,%/d4\n" \
453 " mulu %/d1,%/d2\n" \
454 " mulu %/d0,%/d3\n" \
455 " mulu %/d0,%/d1\n" \
456 " move%.l %/d4,%/d0\n" \
457 " clr%.w %/d0\n" \
458 " swap %/d0\n" \
459 " add%.l %/d0,%/d2\n" \
460 " add%.l %/d3,%/d2\n" \
461 " jcc 1f\n" \
462 " add%.l %#65536,%/d1\n" \
463 "1: swap %/d2\n" \
464 " moveq %#0,%/d0\n" \
465 " move%.w %/d2,%/d0\n" \
466 " move%.w %/d4,%/d2\n" \
467 " move%.l %/d2,%1\n" \
468 " add%.l %/d1,%/d0\n" \
469 " move%.l %/d0,%0" \
470 : "=g" ((USItype) (xh)), \
471 "=g" ((USItype) (xl)) \
472 : "g" ((USItype) (a)), \
473 "g" ((USItype) (b)) \
474 : "d0", "d1", "d2", "d3", "d4")
475 #define UMUL_TIME 100
476 #define UDIV_TIME 400
477 #else /* not ColdFire */
478 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
479 #define umul_ppmm(xh, xl, a, b) \
480 __asm__ ("| Inlined umul_ppmm\n" \
481 " move%.l %2,%/d0\n" \
482 " move%.l %3,%/d1\n" \
483 " move%.l %/d0,%/d2\n" \
484 " swap %/d0\n" \
485 " move%.l %/d1,%/d3\n" \
486 " swap %/d1\n" \
487 " move%.w %/d2,%/d4\n" \
488 " mulu %/d3,%/d4\n" \
489 " mulu %/d1,%/d2\n" \
490 " mulu %/d0,%/d3\n" \
491 " mulu %/d0,%/d1\n" \
492 " move%.l %/d4,%/d0\n" \
493 " eor%.w %/d0,%/d0\n" \
494 " swap %/d0\n" \
495 " add%.l %/d0,%/d2\n" \
496 " add%.l %/d3,%/d2\n" \
497 " jcc 1f\n" \
498 " add%.l %#65536,%/d1\n" \
499 "1: swap %/d2\n" \
500 " moveq %#0,%/d0\n" \
501 " move%.w %/d2,%/d0\n" \
502 " move%.w %/d4,%/d2\n" \
503 " move%.l %/d2,%1\n" \
504 " add%.l %/d1,%/d0\n" \
505 " move%.l %/d0,%0" \
506 : "=g" ((USItype) (xh)), \
507 "=g" ((USItype) (xl)) \
508 : "g" ((USItype) (a)), \
509 "g" ((USItype) (b)) \
510 : "d0", "d1", "d2", "d3", "d4")
511 #define UMUL_TIME 100
512 #define UDIV_TIME 400
513
514 #endif /* not mc68020 */
515
516 /* The '020, '030, '040 and '060 have bitfield insns.
517 cpu32 disguises as a 68020, but lacks them. */
518 #if defined (__mc68020__) && !defined (__mcpu32__)
519 #define count_leading_zeros(count, x) \
520 __asm__ ("bfffo %1{%b2:%b2},%0" \
521 : "=d" ((USItype) (count)) \
522 : "od" ((USItype) (x)), "n" (0))
523 #endif
524 #endif /* mc68000 */
525
526 #if defined (__m88000__) && W_TYPE_SIZE == 32
527 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
528 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
529 : "=r" ((USItype) (sh)), \
530 "=&r" ((USItype) (sl)) \
531 : "%rJ" ((USItype) (ah)), \
532 "rJ" ((USItype) (bh)), \
533 "%rJ" ((USItype) (al)), \
534 "rJ" ((USItype) (bl)))
535 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
536 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
537 : "=r" ((USItype) (sh)), \
538 "=&r" ((USItype) (sl)) \
539 : "rJ" ((USItype) (ah)), \
540 "rJ" ((USItype) (bh)), \
541 "rJ" ((USItype) (al)), \
542 "rJ" ((USItype) (bl)))
543 #define count_leading_zeros(count, x) \
544 do { \
545 USItype __cbtmp; \
546 __asm__ ("ff1 %0,%1" \
547 : "=r" (__cbtmp) \
548 : "r" ((USItype) (x))); \
549 (count) = __cbtmp ^ 31; \
550 } while (0)
551 #define COUNT_LEADING_ZEROS_0 63 /* sic */
552 #if defined (__mc88110__)
553 #define umul_ppmm(wh, wl, u, v) \
554 do { \
555 union {UDItype __ll; \
556 struct {USItype __h, __l;} __i; \
557 } __xx; \
558 __asm__ ("mulu.d %0,%1,%2" \
559 : "=r" (__xx.__ll) \
560 : "r" ((USItype) (u)), \
561 "r" ((USItype) (v))); \
562 (wh) = __xx.__i.__h; \
563 (wl) = __xx.__i.__l; \
564 } while (0)
565 #define udiv_qrnnd(q, r, n1, n0, d) \
566 ({union {UDItype __ll; \
567 struct {USItype __h, __l;} __i; \
568 } __xx; \
569 USItype __q; \
570 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
571 __asm__ ("divu.d %0,%1,%2" \
572 : "=r" (__q) \
573 : "r" (__xx.__ll), \
574 "r" ((USItype) (d))); \
575 (r) = (n0) - __q * (d); (q) = __q; })
576 #define UMUL_TIME 5
577 #define UDIV_TIME 25
578 #else
579 #define UMUL_TIME 17
580 #define UDIV_TIME 150
581 #endif /* __mc88110__ */
582 #endif /* __m88000__ */
583
584 #if defined (__mips__) && W_TYPE_SIZE == 32
585 #define umul_ppmm(w1, w0, u, v) \
586 __asm__ ("multu %2,%3" \
587 : "=l" ((USItype) (w0)), \
588 "=h" ((USItype) (w1)) \
589 : "d" ((USItype) (u)), \
590 "d" ((USItype) (v)))
591 #define UMUL_TIME 10
592 #define UDIV_TIME 100
593 #endif /* __mips__ */
594
595 #if defined (__ns32000__) && W_TYPE_SIZE == 32
596 #define umul_ppmm(w1, w0, u, v) \
597 ({union {UDItype __ll; \
598 struct {USItype __l, __h;} __i; \
599 } __xx; \
600 __asm__ ("meid %2,%0" \
601 : "=g" (__xx.__ll) \
602 : "%0" ((USItype) (u)), \
603 "g" ((USItype) (v))); \
604 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
605 #define __umulsidi3(u, v) \
606 ({UDItype __w; \
607 __asm__ ("meid %2,%0" \
608 : "=g" (__w) \
609 : "%0" ((USItype) (u)), \
610 "g" ((USItype) (v))); \
611 __w; })
612 #define udiv_qrnnd(q, r, n1, n0, d) \
613 ({union {UDItype __ll; \
614 struct {USItype __l, __h;} __i; \
615 } __xx; \
616 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
617 __asm__ ("deid %2,%0" \
618 : "=g" (__xx.__ll) \
619 : "0" (__xx.__ll), \
620 "g" ((USItype) (d))); \
621 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
622 #define count_trailing_zeros(count,x) \
623 do { \
624 __asm__ ("ffsd %2,%0" \
625 : "=r" ((USItype) (count)) \
626 : "0" ((USItype) 0), \
627 "r" ((USItype) (x))); \
628 } while (0)
629 #endif /* __ns32000__ */
630
631 /* FIXME: We should test _IBMR2 here when we add assembly support for the
632 system vendor compilers.
633 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
634 enough, since that hits ARM and m68k too. */
635 #if (defined (_ARCH_PPC) /* AIX */ \
636 || defined (_ARCH_PWR) /* AIX */ \
637 || defined (_ARCH_COM) /* AIX */ \
638 || defined (__powerpc__) /* gcc */ \
639 || defined (__POWERPC__) /* BEOS */ \
640 || defined (__ppc__) /* Darwin */ \
641 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
642 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
643 && CPU_FAMILY == PPC) \
644 ) && W_TYPE_SIZE == 32
645 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
646 do { \
647 if (__builtin_constant_p (bh) && (bh) == 0) \
648 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
649 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
650 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
651 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
652 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
653 else \
654 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
655 : "=r" (sh), "=&r" (sl) \
656 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
657 } while (0)
658 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
659 do { \
660 if (__builtin_constant_p (ah) && (ah) == 0) \
661 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
662 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
663 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
664 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
665 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
666 else if (__builtin_constant_p (bh) && (bh) == 0) \
667 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
668 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
669 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
670 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
671 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
672 else \
673 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
674 : "=r" (sh), "=&r" (sl) \
675 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
676 } while (0)
677 #define count_leading_zeros(count, x) \
678 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
679 #define COUNT_LEADING_ZEROS_0 32
680 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
681 || defined (__ppc__) \
682 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
683 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
684 && CPU_FAMILY == PPC)
685 #define umul_ppmm(ph, pl, m0, m1) \
686 do { \
687 USItype __m0 = (m0), __m1 = (m1); \
688 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
689 (pl) = __m0 * __m1; \
690 } while (0)
691 #define UMUL_TIME 15
692 #define smul_ppmm(ph, pl, m0, m1) \
693 do { \
694 SItype __m0 = (m0), __m1 = (m1); \
695 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
696 (pl) = __m0 * __m1; \
697 } while (0)
698 #define SMUL_TIME 14
699 #define UDIV_TIME 120
700 #elif defined (_ARCH_PWR)
701 #define UMUL_TIME 8
702 #define smul_ppmm(xh, xl, m0, m1) \
703 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
704 #define SMUL_TIME 4
705 #define sdiv_qrnnd(q, r, nh, nl, d) \
706 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
707 #define UDIV_TIME 100
708 #endif
709 #endif /* 32-bit POWER architecture variants. */
710
711 /* We should test _IBMR2 here when we add assembly support for the system
712 vendor compilers. */
713 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
714 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
715 do { \
716 if (__builtin_constant_p (bh) && (bh) == 0) \
717 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
718 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
719 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
720 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
721 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
722 else \
723 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
724 : "=r" (sh), "=&r" (sl) \
725 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
726 } while (0)
727 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
728 do { \
729 if (__builtin_constant_p (ah) && (ah) == 0) \
730 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
731 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
732 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
733 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
734 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
735 else if (__builtin_constant_p (bh) && (bh) == 0) \
736 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
737 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
738 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
739 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
740 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
741 else \
742 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
743 : "=r" (sh), "=&r" (sl) \
744 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
745 } while (0)
746 #define count_leading_zeros(count, x) \
747 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
748 #define COUNT_LEADING_ZEROS_0 64
749 #define umul_ppmm(ph, pl, m0, m1) \
750 do { \
751 UDItype __m0 = (m0), __m1 = (m1); \
752 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
753 (pl) = __m0 * __m1; \
754 } while (0)
755 #define UMUL_TIME 15
756 #define smul_ppmm(ph, pl, m0, m1) \
757 do { \
758 DItype __m0 = (m0), __m1 = (m1); \
759 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
760 (pl) = __m0 * __m1; \
761 } while (0)
762 #define SMUL_TIME 14 /* ??? */
763 #define UDIV_TIME 120 /* ??? */
764 #endif /* 64-bit PowerPC. */
765
766 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
767 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
768 __asm__ ("a %1,%5\n\tae %0,%3" \
769 : "=r" ((USItype) (sh)), \
770 "=&r" ((USItype) (sl)) \
771 : "%0" ((USItype) (ah)), \
772 "r" ((USItype) (bh)), \
773 "%1" ((USItype) (al)), \
774 "r" ((USItype) (bl)))
775 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
776 __asm__ ("s %1,%5\n\tse %0,%3" \
777 : "=r" ((USItype) (sh)), \
778 "=&r" ((USItype) (sl)) \
779 : "0" ((USItype) (ah)), \
780 "r" ((USItype) (bh)), \
781 "1" ((USItype) (al)), \
782 "r" ((USItype) (bl)))
783 #define umul_ppmm(ph, pl, m0, m1) \
784 do { \
785 USItype __m0 = (m0), __m1 = (m1); \
786 __asm__ ( \
787 "s r2,r2\n" \
788 " mts r10,%2\n" \
789 " m r2,%3\n" \
790 " m r2,%3\n" \
791 " m r2,%3\n" \
792 " m r2,%3\n" \
793 " m r2,%3\n" \
794 " m r2,%3\n" \
795 " m r2,%3\n" \
796 " m r2,%3\n" \
797 " m r2,%3\n" \
798 " m r2,%3\n" \
799 " m r2,%3\n" \
800 " m r2,%3\n" \
801 " m r2,%3\n" \
802 " m r2,%3\n" \
803 " m r2,%3\n" \
804 " m r2,%3\n" \
805 " cas %0,r2,r0\n" \
806 " mfs r10,%1" \
807 : "=r" ((USItype) (ph)), \
808 "=r" ((USItype) (pl)) \
809 : "%r" (__m0), \
810 "r" (__m1) \
811 : "r2"); \
812 (ph) += ((((SItype) __m0 >> 31) & __m1) \
813 + (((SItype) __m1 >> 31) & __m0)); \
814 } while (0)
815 #define UMUL_TIME 20
816 #define UDIV_TIME 200
817 #define count_leading_zeros(count, x) \
818 do { \
819 if ((x) >= 0x10000) \
820 __asm__ ("clz %0,%1" \
821 : "=r" ((USItype) (count)) \
822 : "r" ((USItype) (x) >> 16)); \
823 else \
824 { \
825 __asm__ ("clz %0,%1" \
826 : "=r" ((USItype) (count)) \
827 : "r" ((USItype) (x))); \
828 (count) += 16; \
829 } \
830 } while (0)
831 #endif
832
833 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
834 #ifndef __sh1__
835 #define umul_ppmm(w1, w0, u, v) \
836 __asm__ ( \
837 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
838 : "=r<" ((USItype)(w1)), \
839 "=r<" ((USItype)(w0)) \
840 : "r" ((USItype)(u)), \
841 "r" ((USItype)(v)) \
842 : "macl", "mach")
843 #define UMUL_TIME 5
844 #endif
845
846 /* This is the same algorithm as __udiv_qrnnd_c. */
847 #define UDIV_NEEDS_NORMALIZATION 1
848
849 #define udiv_qrnnd(q, r, n1, n0, d) \
850 do { \
851 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
852 __attribute__ ((visibility ("hidden"))); \
853 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
854 __asm__ ( \
855 "mov%M4 %4,r5\n" \
856 " swap.w %3,r4\n" \
857 " swap.w r5,r6\n" \
858 " jsr @%5\n" \
859 " shll16 r6\n" \
860 " swap.w r4,r4\n" \
861 " jsr @%5\n" \
862 " swap.w r1,%0\n" \
863 " or r1,%0" \
864 : "=r" (q), "=&z" (r) \
865 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
866 : "r1", "r2", "r4", "r5", "r6", "pr"); \
867 } while (0)
868
869 #define UDIV_TIME 80
870
871 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
872 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
873 : "=r" (sh), "=r" (sl) \
874 : "0" (ah), "1" (al), "r" (bh), "r" (bl))
875
876 #endif /* __sh__ */
877
878 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
879 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
880 #define count_leading_zeros(count, x) \
881 do \
882 { \
883 UDItype x_ = (USItype)(x); \
884 SItype c_; \
885 \
886 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
887 (count) = c_ - 31; \
888 } \
889 while (0)
890 #define COUNT_LEADING_ZEROS_0 32
891 #endif
892
893 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
894 && W_TYPE_SIZE == 32
895 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
896 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
897 : "=r" ((USItype) (sh)), \
898 "=&r" ((USItype) (sl)) \
899 : "%rJ" ((USItype) (ah)), \
900 "rI" ((USItype) (bh)), \
901 "%rJ" ((USItype) (al)), \
902 "rI" ((USItype) (bl)) \
903 __CLOBBER_CC)
904 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
905 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
906 : "=r" ((USItype) (sh)), \
907 "=&r" ((USItype) (sl)) \
908 : "rJ" ((USItype) (ah)), \
909 "rI" ((USItype) (bh)), \
910 "rJ" ((USItype) (al)), \
911 "rI" ((USItype) (bl)) \
912 __CLOBBER_CC)
913 #if defined (__sparc_v8__)
914 #define umul_ppmm(w1, w0, u, v) \
915 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
916 : "=r" ((USItype) (w1)), \
917 "=r" ((USItype) (w0)) \
918 : "r" ((USItype) (u)), \
919 "r" ((USItype) (v)))
920 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
921 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
922 : "=&r" ((USItype) (__q)), \
923 "=&r" ((USItype) (__r)) \
924 : "r" ((USItype) (__n1)), \
925 "r" ((USItype) (__n0)), \
926 "r" ((USItype) (__d)))
927 #else
928 #if defined (__sparclite__)
929 /* This has hardware multiply but not divide. It also has two additional
930 instructions scan (ffs from high bit) and divscc. */
931 #define umul_ppmm(w1, w0, u, v) \
932 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
933 : "=r" ((USItype) (w1)), \
934 "=r" ((USItype) (w0)) \
935 : "r" ((USItype) (u)), \
936 "r" ((USItype) (v)))
937 #define udiv_qrnnd(q, r, n1, n0, d) \
938 __asm__ ("! Inlined udiv_qrnnd\n" \
939 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
940 " tst %%g0\n" \
941 " divscc %3,%4,%%g1\n" \
942 " divscc %%g1,%4,%%g1\n" \
943 " divscc %%g1,%4,%%g1\n" \
944 " divscc %%g1,%4,%%g1\n" \
945 " divscc %%g1,%4,%%g1\n" \
946 " divscc %%g1,%4,%%g1\n" \
947 " divscc %%g1,%4,%%g1\n" \
948 " divscc %%g1,%4,%%g1\n" \
949 " divscc %%g1,%4,%%g1\n" \
950 " divscc %%g1,%4,%%g1\n" \
951 " divscc %%g1,%4,%%g1\n" \
952 " divscc %%g1,%4,%%g1\n" \
953 " divscc %%g1,%4,%%g1\n" \
954 " divscc %%g1,%4,%%g1\n" \
955 " divscc %%g1,%4,%%g1\n" \
956 " divscc %%g1,%4,%%g1\n" \
957 " divscc %%g1,%4,%%g1\n" \
958 " divscc %%g1,%4,%%g1\n" \
959 " divscc %%g1,%4,%%g1\n" \
960 " divscc %%g1,%4,%%g1\n" \
961 " divscc %%g1,%4,%%g1\n" \
962 " divscc %%g1,%4,%%g1\n" \
963 " divscc %%g1,%4,%%g1\n" \
964 " divscc %%g1,%4,%%g1\n" \
965 " divscc %%g1,%4,%%g1\n" \
966 " divscc %%g1,%4,%%g1\n" \
967 " divscc %%g1,%4,%%g1\n" \
968 " divscc %%g1,%4,%%g1\n" \
969 " divscc %%g1,%4,%%g1\n" \
970 " divscc %%g1,%4,%%g1\n" \
971 " divscc %%g1,%4,%%g1\n" \
972 " divscc %%g1,%4,%0\n" \
973 " rd %%y,%1\n" \
974 " bl,a 1f\n" \
975 " add %1,%4,%1\n" \
976 "1: ! End of inline udiv_qrnnd" \
977 : "=r" ((USItype) (q)), \
978 "=r" ((USItype) (r)) \
979 : "r" ((USItype) (n1)), \
980 "r" ((USItype) (n0)), \
981 "rI" ((USItype) (d)) \
982 : "g1" __AND_CLOBBER_CC)
983 #define UDIV_TIME 37
984 #define count_leading_zeros(count, x) \
985 do { \
986 __asm__ ("scan %1,1,%0" \
987 : "=r" ((USItype) (count)) \
988 : "r" ((USItype) (x))); \
989 } while (0)
990 /* Early sparclites return 63 for an argument of 0, but they warn that future
991 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
992 undefined. */
993 #else
994 /* SPARC without integer multiplication and divide instructions.
995 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
996 #define umul_ppmm(w1, w0, u, v) \
997 __asm__ ("! Inlined umul_ppmm\n" \
998 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
999 " sra %3,31,%%o5 ! Don't move this insn\n" \
1000 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1001 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1002 " mulscc %%g1,%3,%%g1\n" \
1003 " mulscc %%g1,%3,%%g1\n" \
1004 " mulscc %%g1,%3,%%g1\n" \
1005 " mulscc %%g1,%3,%%g1\n" \
1006 " mulscc %%g1,%3,%%g1\n" \
1007 " mulscc %%g1,%3,%%g1\n" \
1008 " mulscc %%g1,%3,%%g1\n" \
1009 " mulscc %%g1,%3,%%g1\n" \
1010 " mulscc %%g1,%3,%%g1\n" \
1011 " mulscc %%g1,%3,%%g1\n" \
1012 " mulscc %%g1,%3,%%g1\n" \
1013 " mulscc %%g1,%3,%%g1\n" \
1014 " mulscc %%g1,%3,%%g1\n" \
1015 " mulscc %%g1,%3,%%g1\n" \
1016 " mulscc %%g1,%3,%%g1\n" \
1017 " mulscc %%g1,%3,%%g1\n" \
1018 " mulscc %%g1,%3,%%g1\n" \
1019 " mulscc %%g1,%3,%%g1\n" \
1020 " mulscc %%g1,%3,%%g1\n" \
1021 " mulscc %%g1,%3,%%g1\n" \
1022 " mulscc %%g1,%3,%%g1\n" \
1023 " mulscc %%g1,%3,%%g1\n" \
1024 " mulscc %%g1,%3,%%g1\n" \
1025 " mulscc %%g1,%3,%%g1\n" \
1026 " mulscc %%g1,%3,%%g1\n" \
1027 " mulscc %%g1,%3,%%g1\n" \
1028 " mulscc %%g1,%3,%%g1\n" \
1029 " mulscc %%g1,%3,%%g1\n" \
1030 " mulscc %%g1,%3,%%g1\n" \
1031 " mulscc %%g1,%3,%%g1\n" \
1032 " mulscc %%g1,%3,%%g1\n" \
1033 " mulscc %%g1,%3,%%g1\n" \
1034 " mulscc %%g1,0,%%g1\n" \
1035 " add %%g1,%%o5,%0\n" \
1036 " rd %%y,%1" \
1037 : "=r" ((USItype) (w1)), \
1038 "=r" ((USItype) (w0)) \
1039 : "%rI" ((USItype) (u)), \
1040 "r" ((USItype) (v)) \
1041 : "g1", "o5" __AND_CLOBBER_CC)
1042 #define UMUL_TIME 39 /* 39 instructions */
1043 /* It's quite necessary to add this much assembler for the sparc.
1044 The default udiv_qrnnd (in C) is more than 10 times slower! */
1045 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1046 __asm__ ("! Inlined udiv_qrnnd\n" \
1047 " mov 32,%%g1\n" \
1048 " subcc %1,%2,%%g0\n" \
1049 "1: bcs 5f\n" \
1050 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1051 " sub %1,%2,%1 ! this kills msb of n\n" \
1052 " addx %1,%1,%1 ! so this can't give carry\n" \
1053 " subcc %%g1,1,%%g1\n" \
1054 "2: bne 1b\n" \
1055 " subcc %1,%2,%%g0\n" \
1056 " bcs 3f\n" \
1057 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1058 " b 3f\n" \
1059 " sub %1,%2,%1 ! this kills msb of n\n" \
1060 "4: sub %1,%2,%1\n" \
1061 "5: addxcc %1,%1,%1\n" \
1062 " bcc 2b\n" \
1063 " subcc %%g1,1,%%g1\n" \
1064 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1065 " bne 4b\n" \
1066 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1067 " sub %1,%2,%1\n" \
1068 "3: xnor %0,0,%0\n" \
1069 " ! End of inline udiv_qrnnd" \
1070 : "=&r" ((USItype) (__q)), \
1071 "=&r" ((USItype) (__r)) \
1072 : "r" ((USItype) (__d)), \
1073 "1" ((USItype) (__n1)), \
1074 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1075 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1076 #endif /* __sparclite__ */
1077 #endif /* __sparc_v8__ */
1078 #endif /* sparc32 */
1079
1080 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1081 && W_TYPE_SIZE == 64
1082 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1083 __asm__ ("addcc %r4,%5,%1\n\t" \
1084 "add %r2,%3,%0\n\t" \
1085 "bcs,a,pn %%xcc, 1f\n\t" \
1086 "add %0, 1, %0\n" \
1087 "1:" \
1088 : "=r" ((UDItype)(sh)), \
1089 "=&r" ((UDItype)(sl)) \
1090 : "%rJ" ((UDItype)(ah)), \
1091 "rI" ((UDItype)(bh)), \
1092 "%rJ" ((UDItype)(al)), \
1093 "rI" ((UDItype)(bl)) \
1094 __CLOBBER_CC)
1095
1096 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1097 __asm__ ("subcc %r4,%5,%1\n\t" \
1098 "sub %r2,%3,%0\n\t" \
1099 "bcs,a,pn %%xcc, 1f\n\t" \
1100 "sub %0, 1, %0\n\t" \
1101 "1:" \
1102 : "=r" ((UDItype)(sh)), \
1103 "=&r" ((UDItype)(sl)) \
1104 : "rJ" ((UDItype)(ah)), \
1105 "rI" ((UDItype)(bh)), \
1106 "rJ" ((UDItype)(al)), \
1107 "rI" ((UDItype)(bl)) \
1108 __CLOBBER_CC)
1109
1110 #define umul_ppmm(wh, wl, u, v) \
1111 do { \
1112 UDItype tmp1, tmp2, tmp3, tmp4; \
1113 __asm__ __volatile__ ( \
1114 "srl %7,0,%3\n\t" \
1115 "mulx %3,%6,%1\n\t" \
1116 "srlx %6,32,%2\n\t" \
1117 "mulx %2,%3,%4\n\t" \
1118 "sllx %4,32,%5\n\t" \
1119 "srl %6,0,%3\n\t" \
1120 "sub %1,%5,%5\n\t" \
1121 "srlx %5,32,%5\n\t" \
1122 "addcc %4,%5,%4\n\t" \
1123 "srlx %7,32,%5\n\t" \
1124 "mulx %3,%5,%3\n\t" \
1125 "mulx %2,%5,%5\n\t" \
1126 "sethi %%hi(0x80000000),%2\n\t" \
1127 "addcc %4,%3,%4\n\t" \
1128 "srlx %4,32,%4\n\t" \
1129 "add %2,%2,%2\n\t" \
1130 "movcc %%xcc,%%g0,%2\n\t" \
1131 "addcc %5,%4,%5\n\t" \
1132 "sllx %3,32,%3\n\t" \
1133 "add %1,%3,%1\n\t" \
1134 "add %5,%2,%0" \
1135 : "=r" ((UDItype)(wh)), \
1136 "=&r" ((UDItype)(wl)), \
1137 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1138 : "r" ((UDItype)(u)), \
1139 "r" ((UDItype)(v)) \
1140 __CLOBBER_CC); \
1141 } while (0)
1142 #define UMUL_TIME 96
1143 #define UDIV_TIME 230
1144 #endif /* sparc64 */
1145
1146 #if defined (__vax__) && W_TYPE_SIZE == 32
1147 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1148 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1149 : "=g" ((USItype) (sh)), \
1150 "=&g" ((USItype) (sl)) \
1151 : "%0" ((USItype) (ah)), \
1152 "g" ((USItype) (bh)), \
1153 "%1" ((USItype) (al)), \
1154 "g" ((USItype) (bl)))
1155 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1156 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1157 : "=g" ((USItype) (sh)), \
1158 "=&g" ((USItype) (sl)) \
1159 : "0" ((USItype) (ah)), \
1160 "g" ((USItype) (bh)), \
1161 "1" ((USItype) (al)), \
1162 "g" ((USItype) (bl)))
1163 #define umul_ppmm(xh, xl, m0, m1) \
1164 do { \
1165 union { \
1166 UDItype __ll; \
1167 struct {USItype __l, __h;} __i; \
1168 } __xx; \
1169 USItype __m0 = (m0), __m1 = (m1); \
1170 __asm__ ("emul %1,%2,$0,%0" \
1171 : "=r" (__xx.__ll) \
1172 : "g" (__m0), \
1173 "g" (__m1)); \
1174 (xh) = __xx.__i.__h; \
1175 (xl) = __xx.__i.__l; \
1176 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1177 + (((SItype) __m1 >> 31) & __m0)); \
1178 } while (0)
1179 #define sdiv_qrnnd(q, r, n1, n0, d) \
1180 do { \
1181 union {DItype __ll; \
1182 struct {SItype __l, __h;} __i; \
1183 } __xx; \
1184 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1185 __asm__ ("ediv %3,%2,%0,%1" \
1186 : "=g" (q), "=g" (r) \
1187 : "g" (__xx.__ll), "g" (d)); \
1188 } while (0)
1189 #endif /* __vax__ */
1190
1191 #if defined (__z8000__) && W_TYPE_SIZE == 16
1192 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1193 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1194 : "=r" ((unsigned int)(sh)), \
1195 "=&r" ((unsigned int)(sl)) \
1196 : "%0" ((unsigned int)(ah)), \
1197 "r" ((unsigned int)(bh)), \
1198 "%1" ((unsigned int)(al)), \
1199 "rQR" ((unsigned int)(bl)))
1200 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1201 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1202 : "=r" ((unsigned int)(sh)), \
1203 "=&r" ((unsigned int)(sl)) \
1204 : "0" ((unsigned int)(ah)), \
1205 "r" ((unsigned int)(bh)), \
1206 "1" ((unsigned int)(al)), \
1207 "rQR" ((unsigned int)(bl)))
1208 #define umul_ppmm(xh, xl, m0, m1) \
1209 do { \
1210 union {long int __ll; \
1211 struct {unsigned int __h, __l;} __i; \
1212 } __xx; \
1213 unsigned int __m0 = (m0), __m1 = (m1); \
1214 __asm__ ("mult %S0,%H3" \
1215 : "=r" (__xx.__i.__h), \
1216 "=r" (__xx.__i.__l) \
1217 : "%1" (__m0), \
1218 "rQR" (__m1)); \
1219 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1220 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1221 + (((signed int) __m1 >> 15) & __m0)); \
1222 } while (0)
1223 #endif /* __z8000__ */
1224
1225 #endif /* __GNUC__ */
1226
1227 /* If this machine has no inline assembler, use C macros. */
1228
1229 #if !defined (add_ssaaaa)
1230 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1231 do { \
1232 UWtype __x; \
1233 __x = (al) + (bl); \
1234 (sh) = (ah) + (bh) + (__x < (al)); \
1235 (sl) = __x; \
1236 } while (0)
1237 #endif
1238
1239 #if !defined (sub_ddmmss)
1240 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1241 do { \
1242 UWtype __x; \
1243 __x = (al) - (bl); \
1244 (sh) = (ah) - (bh) - (__x > (al)); \
1245 (sl) = __x; \
1246 } while (0)
1247 #endif
1248
1249 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1250 smul_ppmm. */
1251 #if !defined (umul_ppmm) && defined (smul_ppmm)
1252 #define umul_ppmm(w1, w0, u, v) \
1253 do { \
1254 UWtype __w1; \
1255 UWtype __xm0 = (u), __xm1 = (v); \
1256 smul_ppmm (__w1, w0, __xm0, __xm1); \
1257 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1258 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1259 } while (0)
1260 #endif
1261
1262 /* If we still don't have umul_ppmm, define it using plain C. */
1263 #if !defined (umul_ppmm)
1264 #define umul_ppmm(w1, w0, u, v) \
1265 do { \
1266 UWtype __x0, __x1, __x2, __x3; \
1267 UHWtype __ul, __vl, __uh, __vh; \
1268 \
1269 __ul = __ll_lowpart (u); \
1270 __uh = __ll_highpart (u); \
1271 __vl = __ll_lowpart (v); \
1272 __vh = __ll_highpart (v); \
1273 \
1274 __x0 = (UWtype) __ul * __vl; \
1275 __x1 = (UWtype) __ul * __vh; \
1276 __x2 = (UWtype) __uh * __vl; \
1277 __x3 = (UWtype) __uh * __vh; \
1278 \
1279 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1280 __x1 += __x2; /* but this indeed can */ \
1281 if (__x1 < __x2) /* did we get it? */ \
1282 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1283 \
1284 (w1) = __x3 + __ll_highpart (__x1); \
1285 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1286 } while (0)
1287 #endif
1288
1289 #if !defined (__umulsidi3)
1290 #define __umulsidi3(u, v) \
1291 ({DWunion __w; \
1292 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1293 __w.ll; })
1294 #endif
1295
1296 /* Define this unconditionally, so it can be used for debugging. */
1297 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1298 do { \
1299 UWtype __d1, __d0, __q1, __q0; \
1300 UWtype __r1, __r0, __m; \
1301 __d1 = __ll_highpart (d); \
1302 __d0 = __ll_lowpart (d); \
1303 \
1304 __r1 = (n1) % __d1; \
1305 __q1 = (n1) / __d1; \
1306 __m = (UWtype) __q1 * __d0; \
1307 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1308 if (__r1 < __m) \
1309 { \
1310 __q1--, __r1 += (d); \
1311 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1312 if (__r1 < __m) \
1313 __q1--, __r1 += (d); \
1314 } \
1315 __r1 -= __m; \
1316 \
1317 __r0 = __r1 % __d1; \
1318 __q0 = __r1 / __d1; \
1319 __m = (UWtype) __q0 * __d0; \
1320 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1321 if (__r0 < __m) \
1322 { \
1323 __q0--, __r0 += (d); \
1324 if (__r0 >= (d)) \
1325 if (__r0 < __m) \
1326 __q0--, __r0 += (d); \
1327 } \
1328 __r0 -= __m; \
1329 \
1330 (q) = (UWtype) __q1 * __ll_B | __q0; \
1331 (r) = __r0; \
1332 } while (0)
1333
1334 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1335 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1336 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1337 #define udiv_qrnnd(q, r, nh, nl, d) \
1338 do { \
1339 USItype __r; \
1340 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1341 (r) = __r; \
1342 } while (0)
1343 #endif
1344
1345 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1346 #if !defined (udiv_qrnnd)
1347 #define UDIV_NEEDS_NORMALIZATION 1
1348 #define udiv_qrnnd __udiv_qrnnd_c
1349 #endif
1350
1351 #if !defined (count_leading_zeros)
1352 #define count_leading_zeros(count, x) \
1353 do { \
1354 UWtype __xr = (x); \
1355 UWtype __a; \
1356 \
1357 if (W_TYPE_SIZE <= 32) \
1358 { \
1359 __a = __xr < ((UWtype)1<<2*__BITS4) \
1360 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1361 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1362 } \
1363 else \
1364 { \
1365 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1366 if (((__xr >> __a) & 0xff) != 0) \
1367 break; \
1368 } \
1369 \
1370 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1371 } while (0)
1372 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1373 #endif
1374
1375 #if !defined (count_trailing_zeros)
1376 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1377 defined in asm, but if it is not, the C version above is good enough. */
1378 #define count_trailing_zeros(count, x) \
1379 do { \
1380 UWtype __ctz_x = (x); \
1381 UWtype __ctz_c; \
1382 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1383 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1384 } while (0)
1385 #endif
1386
1387 #ifndef UDIV_NEEDS_NORMALIZATION
1388 #define UDIV_NEEDS_NORMALIZATION 0
1389 #endif
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