1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009, 2010 Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
60 (define_c_enum "unspec" [
68 ; GOT/PLT and lt-relative accesses
89 ; TLS relocation specifiers
105 ; Stack Smashing Protector
109 ; Test Data Class (TDC)
118 ;; UNSPEC_VOLATILE usage
121 (define_c_enum "unspecv" [
148 ; Registers with special meaning
152 ; Sibling call register.
154 ; Literal pool base register.
156 ; Return address register.
158 ; Condition code register.
160 ; Thread local storage pointer register.
164 ; Hardware register names
168 ; General purpose registers
170 ; Floating point registers.
176 ;; PFPO GPR0 argument format
181 ; PFPO operation type
182 (PFPO_CONVERT 0x1000000)
184 (PFPO_OP_TYPE_SF 0x5)
185 (PFPO_OP_TYPE_DF 0x6)
186 (PFPO_OP_TYPE_TF 0x7)
187 (PFPO_OP_TYPE_SD 0x8)
188 (PFPO_OP_TYPE_DD 0x9)
189 (PFPO_OP_TYPE_TD 0xa)
190 ; Bitposition of operand types
191 (PFPO_OP0_TYPE_SHIFT 16)
192 (PFPO_OP1_TYPE_SHIFT 8)
196 ;; Instruction operand type as used in the Principles of Operation.
197 ;; Used to determine defaults for length and other attribute values.
199 (define_attr "op_type"
200 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
203 ;; Instruction type attribute used for scheduling.
205 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
206 cs,vs,store,sem,idiv,
207 imulhi,imulsi,imuldi,
208 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
209 floadtf,floaddf,floadsf,fstoredf,fstoresf,
210 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
211 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
213 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
214 itoftf, itofdf, itofsf, itofdd, itoftd,
215 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
216 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
218 (cond [(eq_attr "op_type" "NN") (const_string "other")
219 (eq_attr "op_type" "SS") (const_string "cs")]
220 (const_string "integer")))
222 ;; Another attribute used for scheduling purposes:
223 ;; agen: Instruction uses the address generation unit
224 ;; reg: Instruction does not use the agen unit
226 (define_attr "atype" "agen,reg"
227 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
229 (const_string "agen")))
231 ;; Properties concerning Z10 execution grouping and value forwarding.
232 ;; z10_super: instruction is superscalar.
233 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
234 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
235 ;; target register. It can forward this value to a second instruction that reads
236 ;; the same register if that second instruction is issued in the same group.
237 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
238 ;; instruction in the S pipe writes to the register, then the T instruction
239 ;; can immediately read the new value.
240 ;; z10_fr: union of Z10_fwd and z10_rec.
241 ;; z10_c: second operand of instruction is a register and read with complemented bits.
243 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
246 (define_attr "z10prop" "none,
247 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
248 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
250 z10_fr, z10_fr_A3, z10_fr_E1,
252 (const_string "none"))
254 ;; Properties concerning Z196 decoding
255 ;; z196_alone: must group alone
256 ;; z196_end: ends a group
257 ;; z196_cracked: instruction is cracked or expanded
258 (define_attr "z196prop" "none,
259 z196_alone, z196_ends,
261 (const_string "none"))
263 (define_attr "mnemonic" "unknown" (const_string "unknown"))
267 (define_attr "length" ""
268 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
269 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
273 ;; Processor type. This attribute must exactly match the processor_type
274 ;; enumeration in s390.h. The current machine description does not
275 ;; distinguish between g5 and g6, but there are differences between the two
276 ;; CPUs could in theory be modeled.
278 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12"
279 (const (symbol_ref "s390_tune_attr")))
281 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196,zEC12"
282 (const_string "standard"))
284 (define_attr "enabled" ""
285 (cond [(eq_attr "cpu_facility" "standard")
288 (and (eq_attr "cpu_facility" "ieee")
289 (match_test "TARGET_CPU_IEEE_FLOAT"))
292 (and (eq_attr "cpu_facility" "zarch")
293 (match_test "TARGET_ZARCH"))
296 (and (eq_attr "cpu_facility" "longdisp")
297 (match_test "TARGET_LONG_DISPLACEMENT"))
300 (and (eq_attr "cpu_facility" "extimm")
301 (match_test "TARGET_EXTIMM"))
304 (and (eq_attr "cpu_facility" "dfp")
305 (match_test "TARGET_DFP"))
308 (and (eq_attr "cpu_facility" "z10")
309 (match_test "TARGET_Z10"))
312 (and (eq_attr "cpu_facility" "z196")
313 (match_test "TARGET_Z196"))
316 (and (eq_attr "cpu_facility" "zEC12")
317 (match_test "TARGET_ZEC12"))
321 ;; Pipeline description for z900. For lack of anything better,
322 ;; this description is also used for the g5 and g6.
325 ;; Pipeline description for z990, z9-109 and z9-ec.
328 ;; Pipeline description for z10
331 ;; Pipeline description for z196
334 ;; Pipeline description for zEC12
338 (include "predicates.md")
340 ;; Constraint definitions
341 (include "constraints.md")
348 ;; These mode iterators allow floating point patterns to be generated from the
350 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
351 (SD "TARGET_HARD_DFP")])
352 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
353 (define_mode_iterator FPALL [TF DF SF TD DD SD])
354 (define_mode_iterator BFP [TF DF SF])
355 (define_mode_iterator DFP [TD DD])
356 (define_mode_iterator DFP_ALL [TD DD SD])
357 (define_mode_iterator DSF [DF SF])
358 (define_mode_iterator SD_SF [SF SD])
359 (define_mode_iterator DD_DF [DF DD])
360 (define_mode_iterator TD_TF [TF TD])
362 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
363 ;; from the same template.
364 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
365 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
366 (define_mode_iterator DSI [DI SI])
367 (define_mode_iterator TDI [TI DI])
369 ;; These mode iterators allow :P to be used for patterns that operate on
370 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
371 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
373 ;; These macros refer to the actual word_mode of the configuration.
374 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
375 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
376 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
378 ;; Used by the umul pattern to express modes having half the size.
379 (define_mode_attr DWH [(TI "DI") (DI "SI")])
380 (define_mode_attr dwh [(TI "di") (DI "si")])
382 ;; This mode iterator allows the QI and HI patterns to be defined from
383 ;; the same template.
384 (define_mode_iterator HQI [HI QI])
386 ;; This mode iterator allows the integer patterns to be defined from the
388 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
389 (define_mode_iterator INTALL [TI DI SI HI QI])
390 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
392 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
393 ;; the same template.
394 (define_code_iterator SHIFT [ashift lshiftrt])
396 ;; This iterator and attribute allow to combine most atomic operations.
397 (define_code_iterator ATOMIC [and ior xor plus minus mult])
398 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
399 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
400 (plus "add") (minus "sub") (mult "nand")])
401 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
403 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
404 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
405 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
407 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
408 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
410 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
412 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
413 ;; Likewise for "<RXe>".
414 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
415 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
417 ;; The decimal floating point variants of add, sub, div and mul support 3
418 ;; fp register operands. The following attributes allow to merge the bfp and
419 ;; dfp variants in a single insn definition.
421 ;; This attribute is used to set op_type accordingly.
422 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
423 (DD "RRR") (SD "RRR")])
425 ;; This attribute is used in the operand constraint list in order to have the
426 ;; first and the second operand match for bfp modes.
427 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
429 ;; This attribute is used in the operand list of the instruction to have an
430 ;; additional operand for the dfp instructions.
431 (define_mode_attr op1 [(TF "") (DF "") (SF "")
432 (TD "%1,") (DD "%1,") (SD "%1,")])
435 ;; This attribute is used in the operand constraint list
436 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
437 ;; TFmode values are represented by a fp register pair. Since the
438 ;; sign bit instructions only handle single source and target fp registers
439 ;; these instructions can only be used for TFmode values if the source and
440 ;; target operand uses the same fp register.
441 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
443 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
444 ;; This is used to disable the memory alternative in TFmode patterns.
445 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
447 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
448 ;; within instruction mnemonics.
449 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
451 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
452 ;; modes and to an empty string for bfp modes.
453 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
455 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
456 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
457 ;; version only operates on one register.
458 (define_mode_attr d0 [(DI "d") (SI "0")])
460 ;; In combination with d0 this allows to combine instructions of which the 31bit
461 ;; version only operates on one register. The DImode version needs an additional
462 ;; register for the assembler output.
463 (define_mode_attr 1 [(DI "%1,") (SI "")])
465 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
466 ;; 'ashift' and "srdl" in 'lshiftrt'.
467 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
469 ;; In SHIFT templates, this attribute holds the correct standard name for the
470 ;; pattern itself and the corresponding function calls.
471 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
473 ;; This attribute handles differences in the instruction 'type' and will result
474 ;; in "RRE" for DImode and "RR" for SImode.
475 (define_mode_attr E [(DI "E") (SI "")])
477 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
478 ;; to result in "RXY" for DImode and "RX" for SImode.
479 (define_mode_attr Y [(DI "Y") (SI "")])
481 ;; This attribute handles differences in the instruction 'type' and will result
482 ;; in "RSE" for TImode and "RS" for DImode.
483 (define_mode_attr TE [(TI "E") (DI "")])
485 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
486 ;; and "lcr" in SImode.
487 (define_mode_attr g [(DI "g") (SI "")])
489 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
490 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
491 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
492 ;; variant for long displacements.
493 (define_mode_attr y [(DI "g") (SI "y")])
495 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
496 ;; and "cds" in DImode.
497 (define_mode_attr tg [(TI "g") (DI "")])
499 ;; In TDI templates, a string like "c<d>sg".
500 (define_mode_attr td [(TI "d") (DI "")])
502 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
503 ;; and "cfdbr" in SImode.
504 (define_mode_attr gf [(DI "g") (SI "f")])
506 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
507 ;; and sllk for SI. This way it is possible to merge the new z196 SI
508 ;; 3 operands shift instructions into the existing patterns.
509 (define_mode_attr gk [(DI "g") (SI "k")])
511 ;; ICM mask required to load MODE value into the lowest subreg
512 ;; of a SImode register.
513 (define_mode_attr icm_lo [(HI "3") (QI "1")])
515 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
516 ;; HImode and "llgc" in QImode.
517 (define_mode_attr hc [(HI "h") (QI "c")])
519 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
521 (define_mode_attr DBL [(DI "TI") (SI "DI")])
523 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
524 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
525 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
527 ;; Maximum unsigned integer that fits in MODE.
528 (define_mode_attr max_uint [(HI "65535") (QI "255")])
531 ;;- Compare instructions.
534 ; Test-under-Mask instructions
536 (define_insn "*tmqi_mem"
537 [(set (reg CC_REGNUM)
538 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
539 (match_operand:QI 1 "immediate_operand" "n,n"))
540 (match_operand:QI 2 "immediate_operand" "n,n")))]
541 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
545 [(set_attr "op_type" "SI,SIY")
546 (set_attr "z10prop" "z10_super,z10_super")])
548 (define_insn "*tmdi_reg"
549 [(set (reg CC_REGNUM)
550 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
551 (match_operand:DI 1 "immediate_operand"
552 "N0HD0,N1HD0,N2HD0,N3HD0"))
553 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
555 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
556 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
562 [(set_attr "op_type" "RI")
563 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
565 (define_insn "*tmsi_reg"
566 [(set (reg CC_REGNUM)
567 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
568 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
569 (match_operand:SI 2 "immediate_operand" "n,n")))]
570 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
571 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
575 [(set_attr "op_type" "RI")
576 (set_attr "z10prop" "z10_super,z10_super")])
578 (define_insn "*tm<mode>_full"
579 [(set (reg CC_REGNUM)
580 (compare (match_operand:HQI 0 "register_operand" "d")
581 (match_operand:HQI 1 "immediate_operand" "n")))]
582 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
584 [(set_attr "op_type" "RI")
585 (set_attr "z10prop" "z10_super")])
589 ; Load-and-Test instructions
592 ; tst(di|si) instruction pattern(s).
594 (define_insn "*tstdi_sign"
595 [(set (reg CC_REGNUM)
599 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
600 (const_int 32)) (const_int 32))
601 (match_operand:DI 1 "const0_operand" "")))
602 (set (match_operand:DI 2 "register_operand" "=d,d")
603 (sign_extend:DI (match_dup 0)))]
604 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
607 [(set_attr "op_type" "RRE,RXY")
608 (set_attr "cpu_facility" "*,z10")
609 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
612 (define_insn "*tst<mode>_extimm"
613 [(set (reg CC_REGNUM)
614 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
615 (match_operand:GPR 1 "const0_operand" "")))
616 (set (match_operand:GPR 2 "register_operand" "=d,d")
618 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
622 [(set_attr "op_type" "RR<E>,RXY")
623 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
626 (define_insn "*tst<mode>_cconly_extimm"
627 [(set (reg CC_REGNUM)
628 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
629 (match_operand:GPR 1 "const0_operand" "")))
630 (clobber (match_scratch:GPR 2 "=X,d"))]
631 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
635 [(set_attr "op_type" "RR<E>,RXY")
636 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
638 (define_insn "*tstdi"
639 [(set (reg CC_REGNUM)
640 (compare (match_operand:DI 0 "register_operand" "d")
641 (match_operand:DI 1 "const0_operand" "")))
642 (set (match_operand:DI 2 "register_operand" "=d")
644 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
646 [(set_attr "op_type" "RRE")
647 (set_attr "z10prop" "z10_fr_E1")])
649 (define_insn "*tstsi"
650 [(set (reg CC_REGNUM)
651 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
652 (match_operand:SI 1 "const0_operand" "")))
653 (set (match_operand:SI 2 "register_operand" "=d,d,d")
655 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
660 [(set_attr "op_type" "RR,RS,RSY")
661 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
663 (define_insn "*tstsi_cconly"
664 [(set (reg CC_REGNUM)
665 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
666 (match_operand:SI 1 "const0_operand" "")))
667 (clobber (match_scratch:SI 2 "=X,d,d"))]
668 "s390_match_ccmode(insn, CCSmode)"
673 [(set_attr "op_type" "RR,RS,RSY")
674 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
676 (define_insn "*tstdi_cconly_31"
677 [(set (reg CC_REGNUM)
678 (compare (match_operand:DI 0 "register_operand" "d")
679 (match_operand:DI 1 "const0_operand" "")))]
680 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
682 [(set_attr "op_type" "RS")
683 (set_attr "atype" "reg")])
686 (define_insn "*tst<mode>_cconly2"
687 [(set (reg CC_REGNUM)
688 (compare (match_operand:GPR 0 "register_operand" "d")
689 (match_operand:GPR 1 "const0_operand" "")))]
690 "s390_match_ccmode(insn, CCSmode)"
692 [(set_attr "op_type" "RR<E>")
693 (set_attr "z10prop" "z10_fr_E1")])
695 ; tst(hi|qi) instruction pattern(s).
697 (define_insn "*tst<mode>CCT"
698 [(set (reg CC_REGNUM)
699 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
700 (match_operand:HQI 1 "const0_operand" "")))
701 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
703 "s390_match_ccmode(insn, CCTmode)"
706 icmy\t%2,<icm_lo>,%S0
708 [(set_attr "op_type" "RS,RSY,RI")
709 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
711 (define_insn "*tsthiCCT_cconly"
712 [(set (reg CC_REGNUM)
713 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
714 (match_operand:HI 1 "const0_operand" "")))
715 (clobber (match_scratch:HI 2 "=d,d,X"))]
716 "s390_match_ccmode(insn, CCTmode)"
721 [(set_attr "op_type" "RS,RSY,RI")
722 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
724 (define_insn "*tstqiCCT_cconly"
725 [(set (reg CC_REGNUM)
726 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
727 (match_operand:QI 1 "const0_operand" "")))]
728 "s390_match_ccmode(insn, CCTmode)"
733 [(set_attr "op_type" "SI,SIY,RI")
734 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
736 (define_insn "*tst<mode>"
737 [(set (reg CC_REGNUM)
738 (compare (match_operand:HQI 0 "s_operand" "Q,S")
739 (match_operand:HQI 1 "const0_operand" "")))
740 (set (match_operand:HQI 2 "register_operand" "=d,d")
742 "s390_match_ccmode(insn, CCSmode)"
745 icmy\t%2,<icm_lo>,%S0"
746 [(set_attr "op_type" "RS,RSY")
747 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
749 (define_insn "*tst<mode>_cconly"
750 [(set (reg CC_REGNUM)
751 (compare (match_operand:HQI 0 "s_operand" "Q,S")
752 (match_operand:HQI 1 "const0_operand" "")))
753 (clobber (match_scratch:HQI 2 "=d,d"))]
754 "s390_match_ccmode(insn, CCSmode)"
757 icmy\t%2,<icm_lo>,%S0"
758 [(set_attr "op_type" "RS,RSY")
759 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
762 ; Compare (equality) instructions
764 (define_insn "*cmpdi_cct"
765 [(set (reg CC_REGNUM)
766 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
767 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
768 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
775 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
776 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
778 (define_insn "*cmpsi_cct"
779 [(set (reg CC_REGNUM)
780 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
781 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
782 "s390_match_ccmode (insn, CCTmode)"
790 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
791 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
793 ; Compare (signed) instructions
795 (define_insn "*cmpdi_ccs_sign"
796 [(set (reg CC_REGNUM)
797 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
799 (match_operand:DI 0 "register_operand" "d, d,d")))]
800 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
805 [(set_attr "op_type" "RRE,RXY,RIL")
806 (set_attr "z10prop" "z10_c,*,*")
807 (set_attr "type" "*,*,larl")])
811 (define_insn "*cmpsi_ccs_sign"
812 [(set (reg CC_REGNUM)
813 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
814 (match_operand:SI 0 "register_operand" "d,d,d")))]
815 "s390_match_ccmode(insn, CCSRmode)"
820 [(set_attr "op_type" "RX,RXY,RIL")
821 (set_attr "cpu_facility" "*,*,z10")
822 (set_attr "type" "*,*,larl")
823 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
825 (define_insn "*cmphi_ccs_z10"
826 [(set (reg CC_REGNUM)
827 (compare (match_operand:HI 0 "s_operand" "Q")
828 (match_operand:HI 1 "immediate_operand" "K")))]
829 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
831 [(set_attr "op_type" "SIL")
832 (set_attr "z196prop" "z196_cracked")])
834 (define_insn "*cmpdi_ccs_signhi_rl"
835 [(set (reg CC_REGNUM)
836 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
837 (match_operand:GPR 0 "register_operand" "d,d")))]
838 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
842 [(set_attr "op_type" "RXY,RIL")
843 (set_attr "type" "*,larl")])
845 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
846 (define_insn "*cmp<mode>_ccs"
847 [(set (reg CC_REGNUM)
848 (compare (match_operand:GPR 0 "nonimmediate_operand"
850 (match_operand:GPR 1 "general_operand"
852 "s390_match_ccmode(insn, CCSmode)"
861 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
862 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
863 (set_attr "type" "*,*,*,*,*,*,larl")
864 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
867 ; Compare (unsigned) instructions
869 (define_insn "*cmpsi_ccu_zerohi_rlsi"
870 [(set (reg CC_REGNUM)
871 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
872 "larl_operand" "X")))
873 (match_operand:SI 0 "register_operand" "d")))]
874 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
876 [(set_attr "op_type" "RIL")
877 (set_attr "type" "larl")
878 (set_attr "z10prop" "z10_super")])
881 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
882 [(set (reg CC_REGNUM)
883 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
884 "larl_operand" "X")))
885 (match_operand:GPR 0 "register_operand" "d")))]
886 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
888 [(set_attr "op_type" "RIL")
889 (set_attr "type" "larl")
890 (set_attr "z10prop" "z10_super")])
892 (define_insn "*cmpdi_ccu_zero"
893 [(set (reg CC_REGNUM)
894 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
896 (match_operand:DI 0 "register_operand" "d, d,d")))]
897 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
902 [(set_attr "op_type" "RRE,RXY,RIL")
903 (set_attr "cpu_facility" "*,*,z10")
904 (set_attr "type" "*,*,larl")
905 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
907 (define_insn "*cmpdi_ccu"
908 [(set (reg CC_REGNUM)
909 (compare (match_operand:DI 0 "nonimmediate_operand"
911 (match_operand:DI 1 "general_operand"
912 "d,Op,b,D,RT,BQ,Q")))]
913 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
922 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
923 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
924 (set_attr "type" "*,*,larl,*,*,*,*")
925 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
927 (define_insn "*cmpsi_ccu"
928 [(set (reg CC_REGNUM)
929 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
930 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
931 "s390_match_ccmode (insn, CCUmode)"
941 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
942 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
943 (set_attr "type" "*,*,larl,*,*,*,*,*")
944 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
946 (define_insn "*cmphi_ccu"
947 [(set (reg CC_REGNUM)
948 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
949 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
950 "s390_match_ccmode (insn, CCUmode)
951 && !register_operand (operands[1], HImode)"
958 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
959 (set_attr "cpu_facility" "*,*,z10,*,*")
960 (set_attr "z10prop" "*,*,z10_super,*,*")])
962 (define_insn "*cmpqi_ccu"
963 [(set (reg CC_REGNUM)
964 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
965 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
966 "s390_match_ccmode (insn, CCUmode)
967 && !register_operand (operands[1], QImode)"
975 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
976 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
979 ; Block compare (CLC) instruction patterns.
982 [(set (reg CC_REGNUM)
983 (compare (match_operand:BLK 0 "memory_operand" "Q")
984 (match_operand:BLK 1 "memory_operand" "Q")))
985 (use (match_operand 2 "const_int_operand" "n"))]
986 "s390_match_ccmode (insn, CCUmode)
987 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
988 "clc\t%O0(%2,%R0),%S1"
989 [(set_attr "op_type" "SS")])
992 [(set (reg CC_REGNUM)
993 (compare (match_operand 0 "memory_operand" "")
994 (match_operand 1 "memory_operand" "")))]
996 && s390_match_ccmode (insn, CCUmode)
997 && GET_MODE (operands[0]) == GET_MODE (operands[1])
998 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1000 [(set (match_dup 0) (match_dup 1))
1001 (use (match_dup 2))])]
1003 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1004 operands[0] = adjust_address (operands[0], BLKmode, 0);
1005 operands[1] = adjust_address (operands[1], BLKmode, 0);
1007 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1008 operands[0], operands[1]);
1009 operands[0] = SET_DEST (PATTERN (curr_insn));
1013 ; (TF|DF|SF|TD|DD|SD) instructions
1015 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1016 (define_insn "*cmp<mode>_ccs_0"
1017 [(set (reg CC_REGNUM)
1018 (compare (match_operand:FP 0 "register_operand" "f")
1019 (match_operand:FP 1 "const0_operand" "")))]
1020 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1021 "lt<xde><bt>r\t%0,%0"
1022 [(set_attr "op_type" "RRE")
1023 (set_attr "type" "fsimp<mode>")])
1025 ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
1026 (define_insn "*cmp<mode>_ccs"
1027 [(set (reg CC_REGNUM)
1028 (compare (match_operand:FP 0 "register_operand" "f,f")
1029 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1030 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1034 [(set_attr "op_type" "RRE,RXE")
1035 (set_attr "type" "fsimp<mode>")])
1038 ; Compare and Branch instructions
1040 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1041 ; The following instructions do a complementary access of their second
1042 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1043 (define_insn "*cmp_and_br_signed_<mode>"
1045 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1046 [(match_operand:GPR 1 "register_operand" "d,d")
1047 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1048 (label_ref (match_operand 3 "" ""))
1050 (clobber (reg:CC CC_REGNUM))]
1051 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1053 if (get_attr_length (insn) == 6)
1054 return which_alternative ?
1055 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1057 return which_alternative ?
1058 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1060 [(set_attr "op_type" "RIE")
1061 (set_attr "type" "branch")
1062 (set_attr "z10prop" "z10_super_c,z10_super")
1063 (set (attr "length")
1064 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1065 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1066 ; 10 byte for cgr/jg
1068 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1069 ; The following instructions do a complementary access of their second
1070 ; operand (z10 only): clrj, clgrj, clr, clgr
1071 (define_insn "*cmp_and_br_unsigned_<mode>"
1073 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1074 [(match_operand:GPR 1 "register_operand" "d,d")
1075 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1076 (label_ref (match_operand 3 "" ""))
1078 (clobber (reg:CC CC_REGNUM))]
1079 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1081 if (get_attr_length (insn) == 6)
1082 return which_alternative ?
1083 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1085 return which_alternative ?
1086 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1088 [(set_attr "op_type" "RIE")
1089 (set_attr "type" "branch")
1090 (set_attr "z10prop" "z10_super_c,z10_super")
1091 (set (attr "length")
1092 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1093 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1094 ; 10 byte for clgr/jg
1096 ; And now the same two patterns as above but with a negated CC mask.
1098 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1099 ; The following instructions do a complementary access of their second
1100 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1101 (define_insn "*icmp_and_br_signed_<mode>"
1103 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1104 [(match_operand:GPR 1 "register_operand" "d,d")
1105 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1107 (label_ref (match_operand 3 "" ""))))
1108 (clobber (reg:CC CC_REGNUM))]
1109 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1111 if (get_attr_length (insn) == 6)
1112 return which_alternative ?
1113 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1115 return which_alternative ?
1116 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1118 [(set_attr "op_type" "RIE")
1119 (set_attr "type" "branch")
1120 (set_attr "z10prop" "z10_super_c,z10_super")
1121 (set (attr "length")
1122 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1123 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1124 ; 10 byte for cgr/jg
1126 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1127 ; The following instructions do a complementary access of their second
1128 ; operand (z10 only): clrj, clgrj, clr, clgr
1129 (define_insn "*icmp_and_br_unsigned_<mode>"
1131 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1132 [(match_operand:GPR 1 "register_operand" "d,d")
1133 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1135 (label_ref (match_operand 3 "" ""))))
1136 (clobber (reg:CC CC_REGNUM))]
1137 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1139 if (get_attr_length (insn) == 6)
1140 return which_alternative ?
1141 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1143 return which_alternative ?
1144 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1146 [(set_attr "op_type" "RIE")
1147 (set_attr "type" "branch")
1148 (set_attr "z10prop" "z10_super_c,z10_super")
1149 (set (attr "length")
1150 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1151 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1152 ; 10 byte for clgr/jg
1155 ;;- Move instructions.
1159 ; movti instruction pattern(s).
1162 (define_insn "movti"
1163 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1164 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1171 [(set_attr "op_type" "RSY,RSY,*,*")
1172 (set_attr "type" "lm,stm,*,*")])
1175 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1176 (match_operand:TI 1 "general_operand" ""))]
1177 "TARGET_ZARCH && reload_completed
1178 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1179 [(set (match_dup 2) (match_dup 4))
1180 (set (match_dup 3) (match_dup 5))]
1182 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1183 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1184 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1185 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1189 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1190 (match_operand:TI 1 "general_operand" ""))]
1191 "TARGET_ZARCH && reload_completed
1192 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1193 [(set (match_dup 2) (match_dup 4))
1194 (set (match_dup 3) (match_dup 5))]
1196 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1197 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1198 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1199 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1203 [(set (match_operand:TI 0 "register_operand" "")
1204 (match_operand:TI 1 "memory_operand" ""))]
1205 "TARGET_ZARCH && reload_completed
1206 && !s_operand (operands[1], VOIDmode)"
1207 [(set (match_dup 0) (match_dup 1))]
1209 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1210 addr = gen_lowpart (Pmode, addr);
1211 s390_load_address (addr, XEXP (operands[1], 0));
1212 operands[1] = replace_equiv_address (operands[1], addr);
1217 ; Patterns used for secondary reloads
1220 ; z10 provides move instructions accepting larl memory operands.
1221 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1222 ; These patterns are also used for unaligned SI and DI accesses.
1224 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1225 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1226 (match_operand:INTALL 1 "register_operand" "=d")
1227 (match_operand:P 2 "register_operand" "=&a")])]
1230 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1234 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1235 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1236 (match_operand:INTALL 1 "memory_operand" "")
1237 (match_operand:P 2 "register_operand" "=a")])]
1240 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1244 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1245 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1246 (match_operand:FPALL 1 "register_operand" "=d")
1247 (match_operand:P 2 "register_operand" "=&a")])]
1250 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1254 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1255 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1256 (match_operand:FPALL 1 "memory_operand" "")
1257 (match_operand:P 2 "register_operand" "=a")])]
1260 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1264 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1265 [(parallel [(match_operand:P 0 "register_operand" "=d")
1266 (match_operand:P 1 "larl_operand" "")
1267 (match_operand:P 2 "register_operand" "=a")])]
1270 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1274 ; Handles loading a PLUS (load address) expression
1276 (define_expand "reload<mode>_plus"
1277 [(parallel [(match_operand:P 0 "register_operand" "=a")
1278 (match_operand:P 1 "s390_plus_operand" "")
1279 (match_operand:P 2 "register_operand" "=&a")])]
1282 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1286 ; Handles assessing a non-offsetable memory address
1288 (define_expand "reload<mode>_nonoffmem_in"
1289 [(parallel [(match_operand 0 "register_operand" "")
1290 (match_operand 1 "" "")
1291 (match_operand:P 2 "register_operand" "=&a")])]
1294 gcc_assert (MEM_P (operands[1]));
1295 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1296 operands[1] = replace_equiv_address (operands[1], operands[2]);
1297 emit_move_insn (operands[0], operands[1]);
1301 (define_expand "reload<mode>_nonoffmem_out"
1302 [(parallel [(match_operand 0 "" "")
1303 (match_operand 1 "register_operand" "")
1304 (match_operand:P 2 "register_operand" "=&a")])]
1307 gcc_assert (MEM_P (operands[0]));
1308 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1309 operands[0] = replace_equiv_address (operands[0], operands[2]);
1310 emit_move_insn (operands[0], operands[1]);
1314 (define_expand "reload<mode>_PIC_addr"
1315 [(parallel [(match_operand 0 "register_operand" "=d")
1316 (match_operand 1 "larl_operand" "")
1317 (match_operand:P 2 "register_operand" "=a")])]
1320 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1321 emit_move_insn (operands[0], new_rtx);
1325 ; movdi instruction pattern(s).
1328 (define_expand "movdi"
1329 [(set (match_operand:DI 0 "general_operand" "")
1330 (match_operand:DI 1 "general_operand" ""))]
1333 /* Handle symbolic constants. */
1335 && (SYMBOLIC_CONST (operands[1])
1336 || (GET_CODE (operands[1]) == PLUS
1337 && XEXP (operands[1], 0) == pic_offset_table_rtx
1338 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1339 emit_symbolic_move (operands);
1342 (define_insn "*movdi_larl"
1343 [(set (match_operand:DI 0 "register_operand" "=d")
1344 (match_operand:DI 1 "larl_operand" "X"))]
1346 && !FP_REG_P (operands[0])"
1348 [(set_attr "op_type" "RIL")
1349 (set_attr "type" "larl")
1350 (set_attr "z10prop" "z10_super_A1")])
1352 (define_insn "*movdi_64"
1353 [(set (match_operand:DI 0 "nonimmediate_operand"
1354 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1355 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1356 (match_operand:DI 1 "general_operand"
1357 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1358 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1387 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1388 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1389 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1390 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1392 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1393 z10,*,*,*,*,*,longdisp,*,longdisp,
1395 (set_attr "z10prop" "z10_fwd_A1,
1424 [(set (match_operand:DI 0 "register_operand" "")
1425 (match_operand:DI 1 "register_operand" ""))]
1426 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1427 [(set (match_dup 2) (match_dup 3))
1428 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1429 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1430 "operands[2] = gen_lowpart (SImode, operands[0]);
1431 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1434 [(set (match_operand:DI 0 "register_operand" "")
1435 (match_operand:DI 1 "register_operand" ""))]
1436 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1437 && dead_or_set_p (insn, operands[1])"
1438 [(set (match_dup 3) (match_dup 2))
1439 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1440 (set (match_dup 4) (match_dup 2))]
1441 "operands[2] = gen_lowpart (SImode, operands[1]);
1442 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1445 [(set (match_operand:DI 0 "register_operand" "")
1446 (match_operand:DI 1 "register_operand" ""))]
1447 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1448 && !dead_or_set_p (insn, operands[1])"
1449 [(set (match_dup 3) (match_dup 2))
1450 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1451 (set (match_dup 4) (match_dup 2))
1452 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1453 "operands[2] = gen_lowpart (SImode, operands[1]);
1454 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1456 (define_insn "*movdi_31"
1457 [(set (match_operand:DI 0 "nonimmediate_operand"
1458 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1459 (match_operand:DI 1 "general_operand"
1460 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1475 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1476 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1477 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1479 ; For a load from a symbol ref we can use one of the target registers
1480 ; together with larl to load the address.
1482 [(set (match_operand:DI 0 "register_operand" "")
1483 (match_operand:DI 1 "memory_operand" ""))]
1484 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1485 && larl_operand (XEXP (operands[1], 0), SImode)"
1486 [(set (match_dup 2) (match_dup 3))
1487 (set (match_dup 0) (match_dup 1))]
1489 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1490 operands[3] = XEXP (operands[1], 0);
1491 operands[1] = replace_equiv_address (operands[1], operands[2]);
1495 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1496 (match_operand:DI 1 "general_operand" ""))]
1497 "!TARGET_ZARCH && reload_completed
1498 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1499 [(set (match_dup 2) (match_dup 4))
1500 (set (match_dup 3) (match_dup 5))]
1502 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1503 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1504 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1505 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1509 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1510 (match_operand:DI 1 "general_operand" ""))]
1511 "!TARGET_ZARCH && reload_completed
1512 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1513 [(set (match_dup 2) (match_dup 4))
1514 (set (match_dup 3) (match_dup 5))]
1516 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1517 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1518 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1519 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1523 [(set (match_operand:DI 0 "register_operand" "")
1524 (match_operand:DI 1 "memory_operand" ""))]
1525 "!TARGET_ZARCH && reload_completed
1526 && !FP_REG_P (operands[0])
1527 && !s_operand (operands[1], VOIDmode)"
1528 [(set (match_dup 0) (match_dup 1))]
1530 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1531 s390_load_address (addr, XEXP (operands[1], 0));
1532 operands[1] = replace_equiv_address (operands[1], addr);
1536 [(set (match_operand:DI 0 "register_operand" "")
1537 (mem:DI (match_operand 1 "address_operand" "")))]
1539 && !FP_REG_P (operands[0])
1540 && GET_CODE (operands[1]) == SYMBOL_REF
1541 && CONSTANT_POOL_ADDRESS_P (operands[1])
1542 && get_pool_mode (operands[1]) == DImode
1543 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1544 [(set (match_dup 0) (match_dup 2))]
1545 "operands[2] = get_pool_constant (operands[1]);")
1547 (define_insn "*la_64"
1548 [(set (match_operand:DI 0 "register_operand" "=d,d")
1549 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1554 [(set_attr "op_type" "RX,RXY")
1555 (set_attr "type" "la")
1556 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1560 [(set (match_operand:DI 0 "register_operand" "")
1561 (match_operand:QI 1 "address_operand" ""))
1562 (clobber (reg:CC CC_REGNUM))])]
1564 && preferred_la_operand_p (operands[1], const0_rtx)"
1565 [(set (match_dup 0) (match_dup 1))]
1569 [(set (match_operand:DI 0 "register_operand" "")
1570 (match_operand:DI 1 "register_operand" ""))
1573 (plus:DI (match_dup 0)
1574 (match_operand:DI 2 "nonmemory_operand" "")))
1575 (clobber (reg:CC CC_REGNUM))])]
1577 && !reg_overlap_mentioned_p (operands[0], operands[2])
1578 && preferred_la_operand_p (operands[1], operands[2])"
1579 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1583 ; movsi instruction pattern(s).
1586 (define_expand "movsi"
1587 [(set (match_operand:SI 0 "general_operand" "")
1588 (match_operand:SI 1 "general_operand" ""))]
1591 /* Handle symbolic constants. */
1593 && (SYMBOLIC_CONST (operands[1])
1594 || (GET_CODE (operands[1]) == PLUS
1595 && XEXP (operands[1], 0) == pic_offset_table_rtx
1596 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1597 emit_symbolic_move (operands);
1600 (define_insn "*movsi_larl"
1601 [(set (match_operand:SI 0 "register_operand" "=d")
1602 (match_operand:SI 1 "larl_operand" "X"))]
1603 "!TARGET_64BIT && TARGET_CPU_ZARCH
1604 && !FP_REG_P (operands[0])"
1606 [(set_attr "op_type" "RIL")
1607 (set_attr "type" "larl")
1608 (set_attr "z10prop" "z10_fwd_A1")])
1610 (define_insn "*movsi_zarch"
1611 [(set (match_operand:SI 0 "nonimmediate_operand"
1612 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1613 (match_operand:SI 1 "general_operand"
1614 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1639 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1640 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1641 (set_attr "type" "*,
1663 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1664 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1665 (set_attr "z10prop" "z10_fwd_A1,
1688 (define_insn "*movsi_esa"
1689 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1690 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1704 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1705 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1706 (set_attr "z10prop" "z10_fwd_A1,
1720 [(set (match_operand:SI 0 "register_operand" "")
1721 (mem:SI (match_operand 1 "address_operand" "")))]
1722 "!FP_REG_P (operands[0])
1723 && GET_CODE (operands[1]) == SYMBOL_REF
1724 && CONSTANT_POOL_ADDRESS_P (operands[1])
1725 && get_pool_mode (operands[1]) == SImode
1726 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1727 [(set (match_dup 0) (match_dup 2))]
1728 "operands[2] = get_pool_constant (operands[1]);")
1730 (define_insn "*la_31"
1731 [(set (match_operand:SI 0 "register_operand" "=d,d")
1732 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
1733 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1737 [(set_attr "op_type" "RX,RXY")
1738 (set_attr "type" "la")
1739 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1743 [(set (match_operand:SI 0 "register_operand" "")
1744 (match_operand:QI 1 "address_operand" ""))
1745 (clobber (reg:CC CC_REGNUM))])]
1747 && preferred_la_operand_p (operands[1], const0_rtx)"
1748 [(set (match_dup 0) (match_dup 1))]
1752 [(set (match_operand:SI 0 "register_operand" "")
1753 (match_operand:SI 1 "register_operand" ""))
1756 (plus:SI (match_dup 0)
1757 (match_operand:SI 2 "nonmemory_operand" "")))
1758 (clobber (reg:CC CC_REGNUM))])]
1760 && !reg_overlap_mentioned_p (operands[0], operands[2])
1761 && preferred_la_operand_p (operands[1], operands[2])"
1762 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1765 (define_insn "*la_31_and"
1766 [(set (match_operand:SI 0 "register_operand" "=d,d")
1767 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
1768 (const_int 2147483647)))]
1773 [(set_attr "op_type" "RX,RXY")
1774 (set_attr "type" "la")
1775 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1777 (define_insn_and_split "*la_31_and_cc"
1778 [(set (match_operand:SI 0 "register_operand" "=d")
1779 (and:SI (match_operand:QI 1 "address_operand" "p")
1780 (const_int 2147483647)))
1781 (clobber (reg:CC CC_REGNUM))]
1784 "&& reload_completed"
1786 (and:SI (match_dup 1) (const_int 2147483647)))]
1788 [(set_attr "op_type" "RX")
1789 (set_attr "type" "la")])
1791 (define_insn "force_la_31"
1792 [(set (match_operand:SI 0 "register_operand" "=d,d")
1793 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
1794 (use (const_int 0))]
1799 [(set_attr "op_type" "RX")
1800 (set_attr "type" "la")
1801 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1804 ; movhi instruction pattern(s).
1807 (define_expand "movhi"
1808 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1809 (match_operand:HI 1 "general_operand" ""))]
1812 /* Make it explicit that loading a register from memory
1813 always sign-extends (at least) to SImode. */
1814 if (optimize && can_create_pseudo_p ()
1815 && register_operand (operands[0], VOIDmode)
1816 && GET_CODE (operands[1]) == MEM)
1818 rtx tmp = gen_reg_rtx (SImode);
1819 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1820 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1821 operands[1] = gen_lowpart (HImode, tmp);
1825 (define_insn "*movhi"
1826 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1827 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1839 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1840 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1841 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1842 (set_attr "z10prop" "z10_fr_E1,
1853 [(set (match_operand:HI 0 "register_operand" "")
1854 (mem:HI (match_operand 1 "address_operand" "")))]
1855 "GET_CODE (operands[1]) == SYMBOL_REF
1856 && CONSTANT_POOL_ADDRESS_P (operands[1])
1857 && get_pool_mode (operands[1]) == HImode
1858 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1859 [(set (match_dup 0) (match_dup 2))]
1860 "operands[2] = get_pool_constant (operands[1]);")
1863 ; movqi instruction pattern(s).
1866 (define_expand "movqi"
1867 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1868 (match_operand:QI 1 "general_operand" ""))]
1871 /* On z/Architecture, zero-extending from memory to register
1872 is just as fast as a QImode load. */
1873 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1874 && register_operand (operands[0], VOIDmode)
1875 && GET_CODE (operands[1]) == MEM)
1877 rtx tmp = gen_reg_rtx (DImode);
1878 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
1879 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1880 operands[1] = gen_lowpart (QImode, tmp);
1884 (define_insn "*movqi"
1885 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1886 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
1898 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1899 (set_attr "type" "lr,*,*,*,store,store,store,store,*")
1900 (set_attr "z10prop" "z10_fr_E1,
1911 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1912 (mem:QI (match_operand 1 "address_operand" "")))]
1913 "GET_CODE (operands[1]) == SYMBOL_REF
1914 && CONSTANT_POOL_ADDRESS_P (operands[1])
1915 && get_pool_mode (operands[1]) == QImode
1916 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1917 [(set (match_dup 0) (match_dup 2))]
1918 "operands[2] = get_pool_constant (operands[1]);")
1921 ; movstrictqi instruction pattern(s).
1924 (define_insn "*movstrictqi"
1925 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1926 (match_operand:QI 1 "memory_operand" "R,T"))]
1931 [(set_attr "op_type" "RX,RXY")
1932 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1935 ; movstricthi instruction pattern(s).
1938 (define_insn "*movstricthi"
1939 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1940 (match_operand:HI 1 "memory_operand" "Q,S"))
1941 (clobber (reg:CC CC_REGNUM))]
1946 [(set_attr "op_type" "RS,RSY")
1947 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1950 ; movstrictsi instruction pattern(s).
1953 (define_insn "movstrictsi"
1954 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1955 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1962 [(set_attr "op_type" "RR,RX,RXY,RRE")
1963 (set_attr "type" "lr,load,load,*")
1964 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1967 ; mov(tf|td) instruction pattern(s).
1970 (define_expand "mov<mode>"
1971 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1972 (match_operand:TD_TF 1 "general_operand" ""))]
1976 (define_insn "*mov<mode>_64"
1977 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1978 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1989 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1990 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
1991 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
1993 (define_insn "*mov<mode>_31"
1994 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1995 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2002 [(set_attr "op_type" "RRE,RRE,*,*")
2003 (set_attr "type" "fsimptf,fsimptf,*,*")
2004 (set_attr "cpu_facility" "z196,*,*,*")])
2006 ; TFmode in GPRs splitters
2009 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2010 (match_operand:TD_TF 1 "general_operand" ""))]
2011 "TARGET_ZARCH && reload_completed
2012 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2013 [(set (match_dup 2) (match_dup 4))
2014 (set (match_dup 3) (match_dup 5))]
2016 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2017 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2018 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2019 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2023 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2024 (match_operand:TD_TF 1 "general_operand" ""))]
2025 "TARGET_ZARCH && reload_completed
2026 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2027 [(set (match_dup 2) (match_dup 4))
2028 (set (match_dup 3) (match_dup 5))]
2030 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2031 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2032 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2033 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2037 [(set (match_operand:TD_TF 0 "register_operand" "")
2038 (match_operand:TD_TF 1 "memory_operand" ""))]
2039 "TARGET_ZARCH && reload_completed
2040 && !FP_REG_P (operands[0])
2041 && !s_operand (operands[1], VOIDmode)"
2042 [(set (match_dup 0) (match_dup 1))]
2044 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2045 addr = gen_lowpart (Pmode, addr);
2046 s390_load_address (addr, XEXP (operands[1], 0));
2047 operands[1] = replace_equiv_address (operands[1], addr);
2050 ; TFmode in BFPs splitters
2053 [(set (match_operand:TD_TF 0 "register_operand" "")
2054 (match_operand:TD_TF 1 "memory_operand" ""))]
2055 "reload_completed && offsettable_memref_p (operands[1])
2056 && FP_REG_P (operands[0])"
2057 [(set (match_dup 2) (match_dup 4))
2058 (set (match_dup 3) (match_dup 5))]
2060 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2062 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2064 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2065 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2069 [(set (match_operand:TD_TF 0 "memory_operand" "")
2070 (match_operand:TD_TF 1 "register_operand" ""))]
2071 "reload_completed && offsettable_memref_p (operands[0])
2072 && FP_REG_P (operands[1])"
2073 [(set (match_dup 2) (match_dup 4))
2074 (set (match_dup 3) (match_dup 5))]
2076 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2077 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2078 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2080 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2085 ; mov(df|dd) instruction pattern(s).
2088 (define_expand "mov<mode>"
2089 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2090 (match_operand:DD_DF 1 "general_operand" ""))]
2094 (define_insn "*mov<mode>_64dfp"
2095 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2096 "=f,f,f,d,f,f,R,T,d,d, d,RT")
2097 (match_operand:DD_DF 1 "general_operand"
2098 " G,f,d,f,R,T,f,f,G,d,RT, d"))]
2113 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2114 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2115 fstoredf,fstoredf,*,lr,load,store")
2116 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2117 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2119 (define_insn "*mov<mode>_64"
2120 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
2121 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
2134 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
2135 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2136 fstore<mode>,fstore<mode>,*,lr,load,store")
2137 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
2138 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
2140 (define_insn "*mov<mode>_31"
2141 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2142 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2143 (match_operand:DD_DF 1 "general_operand"
2144 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2159 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2160 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2161 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2162 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2165 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2166 (match_operand:DD_DF 1 "general_operand" ""))]
2167 "!TARGET_ZARCH && reload_completed
2168 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2169 [(set (match_dup 2) (match_dup 4))
2170 (set (match_dup 3) (match_dup 5))]
2172 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2173 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2174 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2175 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2179 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2180 (match_operand:DD_DF 1 "general_operand" ""))]
2181 "!TARGET_ZARCH && reload_completed
2182 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2183 [(set (match_dup 2) (match_dup 4))
2184 (set (match_dup 3) (match_dup 5))]
2186 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2187 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2188 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2189 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2193 [(set (match_operand:DD_DF 0 "register_operand" "")
2194 (match_operand:DD_DF 1 "memory_operand" ""))]
2195 "!TARGET_ZARCH && reload_completed
2196 && !FP_REG_P (operands[0])
2197 && !s_operand (operands[1], VOIDmode)"
2198 [(set (match_dup 0) (match_dup 1))]
2200 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2201 s390_load_address (addr, XEXP (operands[1], 0));
2202 operands[1] = replace_equiv_address (operands[1], addr);
2206 ; mov(sf|sd) instruction pattern(s).
2209 (define_insn "mov<mode>"
2210 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2211 "=f,f,f,f,R,T,d,d,d,d,R,T")
2212 (match_operand:SD_SF 1 "general_operand"
2213 " G,f,R,T,f,f,G,d,R,T,d,d"))]
2228 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
2229 (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
2230 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2231 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2232 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
2235 ; movcc instruction pattern
2238 (define_insn "movcc"
2239 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2240 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2250 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2251 (set_attr "type" "lr,*,*,store,store,load,load")
2252 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
2253 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2256 ; Block move (MVC) patterns.
2260 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2261 (match_operand:BLK 1 "memory_operand" "Q"))
2262 (use (match_operand 2 "const_int_operand" "n"))]
2263 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2264 "mvc\t%O0(%2,%R0),%S1"
2265 [(set_attr "op_type" "SS")])
2267 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2268 ; order to have it implemented with mvc.
2271 [(set (match_operand:QI 0 "memory_operand" "")
2272 (match_operand:QI 1 "memory_operand" ""))]
2275 [(set (match_dup 0) (match_dup 1))
2276 (use (const_int 1))])]
2278 operands[0] = adjust_address (operands[0], BLKmode, 0);
2279 operands[1] = adjust_address (operands[1], BLKmode, 0);
2285 [(set (match_operand:BLK 0 "memory_operand" "")
2286 (match_operand:BLK 1 "memory_operand" ""))
2287 (use (match_operand 2 "const_int_operand" ""))])
2289 [(set (match_operand:BLK 3 "memory_operand" "")
2290 (match_operand:BLK 4 "memory_operand" ""))
2291 (use (match_operand 5 "const_int_operand" ""))])]
2292 "s390_offset_p (operands[0], operands[3], operands[2])
2293 && s390_offset_p (operands[1], operands[4], operands[2])
2294 && !s390_overlap_p (operands[0], operands[1],
2295 INTVAL (operands[2]) + INTVAL (operands[5]))
2296 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2298 [(set (match_dup 6) (match_dup 7))
2299 (use (match_dup 8))])]
2300 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2301 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2302 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2306 ; load_multiple pattern(s).
2308 ; ??? Due to reload problems with replacing registers inside match_parallel
2309 ; we currently support load_multiple/store_multiple only after reload.
2312 (define_expand "load_multiple"
2313 [(match_par_dup 3 [(set (match_operand 0 "" "")
2314 (match_operand 1 "" ""))
2315 (use (match_operand 2 "" ""))])]
2318 enum machine_mode mode;
2324 /* Support only loading a constant number of fixed-point registers from
2325 memory and only bother with this if more than two */
2326 if (GET_CODE (operands[2]) != CONST_INT
2327 || INTVAL (operands[2]) < 2
2328 || INTVAL (operands[2]) > 16
2329 || GET_CODE (operands[1]) != MEM
2330 || GET_CODE (operands[0]) != REG
2331 || REGNO (operands[0]) >= 16)
2334 count = INTVAL (operands[2]);
2335 regno = REGNO (operands[0]);
2336 mode = GET_MODE (operands[0]);
2337 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2340 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2341 if (!can_create_pseudo_p ())
2343 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2345 from = XEXP (operands[1], 0);
2348 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2349 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2350 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2352 from = XEXP (XEXP (operands[1], 0), 0);
2353 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2360 from = force_reg (Pmode, XEXP (operands[1], 0));
2364 for (i = 0; i < count; i++)
2365 XVECEXP (operands[3], 0, i)
2366 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2367 change_address (operands[1], mode,
2368 plus_constant (Pmode, from,
2369 off + i * GET_MODE_SIZE (mode))));
2372 (define_insn "*load_multiple_di"
2373 [(match_parallel 0 "load_multiple_operation"
2374 [(set (match_operand:DI 1 "register_operand" "=r")
2375 (match_operand:DI 2 "s_operand" "QS"))])]
2376 "reload_completed && TARGET_ZARCH"
2378 int words = XVECLEN (operands[0], 0);
2379 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2380 return "lmg\t%1,%0,%S2";
2382 [(set_attr "op_type" "RSY")
2383 (set_attr "type" "lm")])
2385 (define_insn "*load_multiple_si"
2386 [(match_parallel 0 "load_multiple_operation"
2387 [(set (match_operand:SI 1 "register_operand" "=r,r")
2388 (match_operand:SI 2 "s_operand" "Q,S"))])]
2391 int words = XVECLEN (operands[0], 0);
2392 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2393 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2395 [(set_attr "op_type" "RS,RSY")
2396 (set_attr "type" "lm")])
2399 ; store multiple pattern(s).
2402 (define_expand "store_multiple"
2403 [(match_par_dup 3 [(set (match_operand 0 "" "")
2404 (match_operand 1 "" ""))
2405 (use (match_operand 2 "" ""))])]
2408 enum machine_mode mode;
2414 /* Support only storing a constant number of fixed-point registers to
2415 memory and only bother with this if more than two. */
2416 if (GET_CODE (operands[2]) != CONST_INT
2417 || INTVAL (operands[2]) < 2
2418 || INTVAL (operands[2]) > 16
2419 || GET_CODE (operands[0]) != MEM
2420 || GET_CODE (operands[1]) != REG
2421 || REGNO (operands[1]) >= 16)
2424 count = INTVAL (operands[2]);
2425 regno = REGNO (operands[1]);
2426 mode = GET_MODE (operands[1]);
2427 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2430 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2432 if (!can_create_pseudo_p ())
2434 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2436 to = XEXP (operands[0], 0);
2439 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2440 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2441 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2443 to = XEXP (XEXP (operands[0], 0), 0);
2444 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2451 to = force_reg (Pmode, XEXP (operands[0], 0));
2455 for (i = 0; i < count; i++)
2456 XVECEXP (operands[3], 0, i)
2457 = gen_rtx_SET (VOIDmode,
2458 change_address (operands[0], mode,
2459 plus_constant (Pmode, to,
2460 off + i * GET_MODE_SIZE (mode))),
2461 gen_rtx_REG (mode, regno + i));
2464 (define_insn "*store_multiple_di"
2465 [(match_parallel 0 "store_multiple_operation"
2466 [(set (match_operand:DI 1 "s_operand" "=QS")
2467 (match_operand:DI 2 "register_operand" "r"))])]
2468 "reload_completed && TARGET_ZARCH"
2470 int words = XVECLEN (operands[0], 0);
2471 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2472 return "stmg\t%2,%0,%S1";
2474 [(set_attr "op_type" "RSY")
2475 (set_attr "type" "stm")])
2478 (define_insn "*store_multiple_si"
2479 [(match_parallel 0 "store_multiple_operation"
2480 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2481 (match_operand:SI 2 "register_operand" "r,r"))])]
2484 int words = XVECLEN (operands[0], 0);
2485 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2486 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2488 [(set_attr "op_type" "RS,RSY")
2489 (set_attr "type" "stm")])
2492 ;; String instructions.
2495 (define_insn "*execute_rl"
2496 [(match_parallel 0 "execute_operation"
2497 [(unspec [(match_operand 1 "register_operand" "a")
2498 (match_operand 2 "" "")
2499 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2500 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2501 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2503 [(set_attr "op_type" "RIL")
2504 (set_attr "type" "cs")])
2506 (define_insn "*execute"
2507 [(match_parallel 0 "execute_operation"
2508 [(unspec [(match_operand 1 "register_operand" "a")
2509 (match_operand:BLK 2 "memory_operand" "R")
2510 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2511 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2512 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2514 [(set_attr "op_type" "RX")
2515 (set_attr "type" "cs")])
2519 ; strlenM instruction pattern(s).
2522 (define_expand "strlen<mode>"
2523 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2526 (unspec:P [(const_int 0)
2527 (match_operand:BLK 1 "memory_operand" "")
2529 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2530 (clobber (scratch:P))
2531 (clobber (reg:CC CC_REGNUM))])
2533 [(set (match_operand:P 0 "register_operand" "")
2534 (minus:P (match_dup 4) (match_dup 5)))
2535 (clobber (reg:CC CC_REGNUM))])]
2538 operands[4] = gen_reg_rtx (Pmode);
2539 operands[5] = gen_reg_rtx (Pmode);
2540 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2541 operands[1] = replace_equiv_address (operands[1], operands[5]);
2544 (define_insn "*strlen<mode>"
2545 [(set (match_operand:P 0 "register_operand" "=a")
2546 (unspec:P [(match_operand:P 2 "general_operand" "0")
2547 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2549 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2550 (clobber (match_scratch:P 1 "=a"))
2551 (clobber (reg:CC CC_REGNUM))]
2553 "srst\t%0,%1\;jo\t.-4"
2554 [(set_attr "length" "8")
2555 (set_attr "type" "vs")])
2558 ; cmpstrM instruction pattern(s).
2561 (define_expand "cmpstrsi"
2562 [(set (reg:SI 0) (const_int 0))
2564 [(clobber (match_operand 3 "" ""))
2565 (clobber (match_dup 4))
2566 (set (reg:CCU CC_REGNUM)
2567 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2568 (match_operand:BLK 2 "memory_operand" "")))
2571 [(set (match_operand:SI 0 "register_operand" "=d")
2572 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2573 (clobber (reg:CC CC_REGNUM))])]
2576 /* As the result of CMPINT is inverted compared to what we need,
2577 we have to swap the operands. */
2578 rtx op1 = operands[2];
2579 rtx op2 = operands[1];
2580 rtx addr1 = gen_reg_rtx (Pmode);
2581 rtx addr2 = gen_reg_rtx (Pmode);
2583 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2584 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2585 operands[1] = replace_equiv_address_nv (op1, addr1);
2586 operands[2] = replace_equiv_address_nv (op2, addr2);
2587 operands[3] = addr1;
2588 operands[4] = addr2;
2591 (define_insn "*cmpstr<mode>"
2592 [(clobber (match_operand:P 0 "register_operand" "=d"))
2593 (clobber (match_operand:P 1 "register_operand" "=d"))
2594 (set (reg:CCU CC_REGNUM)
2595 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2596 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2599 "clst\t%0,%1\;jo\t.-4"
2600 [(set_attr "length" "8")
2601 (set_attr "type" "vs")])
2604 ; movstr instruction pattern.
2607 (define_expand "movstr"
2608 [(set (reg:SI 0) (const_int 0))
2610 [(clobber (match_dup 3))
2611 (set (match_operand:BLK 1 "memory_operand" "")
2612 (match_operand:BLK 2 "memory_operand" ""))
2613 (set (match_operand 0 "register_operand" "")
2614 (unspec [(match_dup 1)
2616 (reg:SI 0)] UNSPEC_MVST))
2617 (clobber (reg:CC CC_REGNUM))])]
2620 rtx addr1 = gen_reg_rtx (Pmode);
2621 rtx addr2 = gen_reg_rtx (Pmode);
2623 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2624 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2625 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2626 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2627 operands[3] = addr2;
2630 (define_insn "*movstr"
2631 [(clobber (match_operand:P 2 "register_operand" "=d"))
2632 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2633 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2634 (set (match_operand:P 0 "register_operand" "=d")
2635 (unspec [(mem:BLK (match_dup 1))
2636 (mem:BLK (match_dup 3))
2637 (reg:SI 0)] UNSPEC_MVST))
2638 (clobber (reg:CC CC_REGNUM))]
2640 "mvst\t%1,%2\;jo\t.-4"
2641 [(set_attr "length" "8")
2642 (set_attr "type" "vs")])
2646 ; movmemM instruction pattern(s).
2649 (define_expand "movmem<mode>"
2650 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2651 (match_operand:BLK 1 "memory_operand" "")) ; source
2652 (use (match_operand:GPR 2 "general_operand" "")) ; count
2653 (match_operand 3 "" "")]
2656 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
2662 ; Move a block that is up to 256 bytes in length.
2663 ; The block length is taken as (operands[2] % 256) + 1.
2665 (define_expand "movmem_short"
2667 [(set (match_operand:BLK 0 "memory_operand" "")
2668 (match_operand:BLK 1 "memory_operand" ""))
2669 (use (match_operand 2 "nonmemory_operand" ""))
2670 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2671 (clobber (match_dup 3))])]
2673 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2675 (define_insn "*movmem_short"
2676 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2677 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2678 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2679 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2680 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
2681 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
2683 [(set_attr "type" "cs")
2684 (set_attr "cpu_facility" "*,*,z10,*")])
2687 [(set (match_operand:BLK 0 "memory_operand" "")
2688 (match_operand:BLK 1 "memory_operand" ""))
2689 (use (match_operand 2 "const_int_operand" ""))
2690 (use (match_operand 3 "immediate_operand" ""))
2691 (clobber (scratch))]
2694 [(set (match_dup 0) (match_dup 1))
2695 (use (match_dup 2))])]
2696 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2699 [(set (match_operand:BLK 0 "memory_operand" "")
2700 (match_operand:BLK 1 "memory_operand" ""))
2701 (use (match_operand 2 "register_operand" ""))
2702 (use (match_operand 3 "memory_operand" ""))
2703 (clobber (scratch))]
2706 [(unspec [(match_dup 2) (match_dup 3)
2707 (const_int 0)] UNSPEC_EXECUTE)
2708 (set (match_dup 0) (match_dup 1))
2709 (use (const_int 1))])]
2713 [(set (match_operand:BLK 0 "memory_operand" "")
2714 (match_operand:BLK 1 "memory_operand" ""))
2715 (use (match_operand 2 "register_operand" ""))
2716 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2717 (clobber (scratch))]
2718 "TARGET_Z10 && reload_completed"
2720 [(unspec [(match_dup 2) (const_int 0)
2721 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2722 (set (match_dup 0) (match_dup 1))
2723 (use (const_int 1))])]
2724 "operands[3] = gen_label_rtx ();")
2727 [(set (match_operand:BLK 0 "memory_operand" "")
2728 (match_operand:BLK 1 "memory_operand" ""))
2729 (use (match_operand 2 "register_operand" ""))
2730 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2731 (clobber (match_operand 3 "register_operand" ""))]
2732 "reload_completed && TARGET_CPU_ZARCH"
2733 [(set (match_dup 3) (label_ref (match_dup 4)))
2735 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2736 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2737 (set (match_dup 0) (match_dup 1))
2738 (use (const_int 1))])]
2739 "operands[4] = gen_label_rtx ();")
2741 ; Move a block of arbitrary length.
2743 (define_expand "movmem_long"
2745 [(clobber (match_dup 2))
2746 (clobber (match_dup 3))
2747 (set (match_operand:BLK 0 "memory_operand" "")
2748 (match_operand:BLK 1 "memory_operand" ""))
2749 (use (match_operand 2 "general_operand" ""))
2751 (clobber (reg:CC CC_REGNUM))])]
2754 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2755 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2756 rtx reg0 = gen_reg_rtx (dreg_mode);
2757 rtx reg1 = gen_reg_rtx (dreg_mode);
2758 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2759 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
2760 rtx len0 = gen_lowpart (Pmode, reg0);
2761 rtx len1 = gen_lowpart (Pmode, reg1);
2763 emit_clobber (reg0);
2764 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2765 emit_move_insn (len0, operands[2]);
2767 emit_clobber (reg1);
2768 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2769 emit_move_insn (len1, operands[2]);
2771 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2772 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2777 (define_insn "*movmem_long"
2778 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2779 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2780 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2781 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2784 (clobber (reg:CC CC_REGNUM))]
2785 "TARGET_64BIT || !TARGET_ZARCH"
2786 "mvcle\t%0,%1,0\;jo\t.-4"
2787 [(set_attr "length" "8")
2788 (set_attr "type" "vs")])
2790 (define_insn "*movmem_long_31z"
2791 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2792 (clobber (match_operand:TI 1 "register_operand" "=d"))
2793 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
2794 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
2797 (clobber (reg:CC CC_REGNUM))]
2798 "!TARGET_64BIT && TARGET_ZARCH"
2799 "mvcle\t%0,%1,0\;jo\t.-4"
2800 [(set_attr "length" "8")
2801 (set_attr "type" "vs")])
2808 (define_expand "signbit<mode>2"
2809 [(set (reg:CCZ CC_REGNUM)
2810 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2813 (set (match_operand:SI 0 "register_operand" "=d")
2814 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2817 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2820 (define_expand "isinf<mode>2"
2821 [(set (reg:CCZ CC_REGNUM)
2822 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2825 (set (match_operand:SI 0 "register_operand" "=d")
2826 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2829 operands[2] = GEN_INT (S390_TDC_INFINITY);
2832 ; This insn is used to generate all variants of the Test Data Class
2833 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2834 ; is the register to be tested and the second one is the bit mask
2835 ; specifying the required test(s).
2837 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
2838 (define_insn "*TDC_insn_<mode>"
2839 [(set (reg:CCZ CC_REGNUM)
2840 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2841 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2843 "t<_d>c<xde><bt>\t%0,%1"
2844 [(set_attr "op_type" "RXE")
2845 (set_attr "type" "fsimp<mode>")])
2847 (define_insn_and_split "*ccz_to_int"
2848 [(set (match_operand:SI 0 "register_operand" "=d")
2849 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2850 UNSPEC_CCZ_TO_INT))]
2854 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2858 ; setmemM instruction pattern(s).
2861 (define_expand "setmem<mode>"
2862 [(set (match_operand:BLK 0 "memory_operand" "")
2863 (match_operand:QI 2 "general_operand" ""))
2864 (use (match_operand:GPR 1 "general_operand" ""))
2865 (match_operand 3 "" "")]
2867 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2869 ; Clear a block that is up to 256 bytes in length.
2870 ; The block length is taken as (operands[1] % 256) + 1.
2872 (define_expand "clrmem_short"
2874 [(set (match_operand:BLK 0 "memory_operand" "")
2876 (use (match_operand 1 "nonmemory_operand" ""))
2877 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2878 (clobber (match_dup 2))
2879 (clobber (reg:CC CC_REGNUM))])]
2881 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2883 (define_insn "*clrmem_short"
2884 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2886 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2887 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2888 (clobber (match_scratch:P 3 "=X,X,X,&a"))
2889 (clobber (reg:CC CC_REGNUM))]
2890 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
2892 [(set_attr "type" "cs")
2893 (set_attr "cpu_facility" "*,*,z10,*")])
2896 [(set (match_operand:BLK 0 "memory_operand" "")
2898 (use (match_operand 1 "const_int_operand" ""))
2899 (use (match_operand 2 "immediate_operand" ""))
2901 (clobber (reg:CC CC_REGNUM))]
2904 [(set (match_dup 0) (const_int 0))
2906 (clobber (reg:CC CC_REGNUM))])]
2907 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2910 [(set (match_operand:BLK 0 "memory_operand" "")
2912 (use (match_operand 1 "register_operand" ""))
2913 (use (match_operand 2 "memory_operand" ""))
2915 (clobber (reg:CC CC_REGNUM))]
2918 [(unspec [(match_dup 1) (match_dup 2)
2919 (const_int 0)] UNSPEC_EXECUTE)
2920 (set (match_dup 0) (const_int 0))
2922 (clobber (reg:CC CC_REGNUM))])]
2926 [(set (match_operand:BLK 0 "memory_operand" "")
2928 (use (match_operand 1 "register_operand" ""))
2929 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2931 (clobber (reg:CC CC_REGNUM))]
2932 "TARGET_Z10 && reload_completed"
2934 [(unspec [(match_dup 1) (const_int 0)
2935 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2936 (set (match_dup 0) (const_int 0))
2938 (clobber (reg:CC CC_REGNUM))])]
2939 "operands[3] = gen_label_rtx ();")
2942 [(set (match_operand:BLK 0 "memory_operand" "")
2944 (use (match_operand 1 "register_operand" ""))
2945 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2946 (clobber (match_operand 2 "register_operand" ""))
2947 (clobber (reg:CC CC_REGNUM))]
2948 "reload_completed && TARGET_CPU_ZARCH"
2949 [(set (match_dup 2) (label_ref (match_dup 3)))
2951 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2952 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2953 (set (match_dup 0) (const_int 0))
2955 (clobber (reg:CC CC_REGNUM))])]
2956 "operands[3] = gen_label_rtx ();")
2958 ; Initialize a block of arbitrary length with (operands[2] % 256).
2960 (define_expand "setmem_long"
2962 [(clobber (match_dup 1))
2963 (set (match_operand:BLK 0 "memory_operand" "")
2964 (match_operand 2 "shift_count_or_setmem_operand" ""))
2965 (use (match_operand 1 "general_operand" ""))
2967 (clobber (reg:CC CC_REGNUM))])]
2970 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
2971 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
2972 rtx reg0 = gen_reg_rtx (dreg_mode);
2973 rtx reg1 = gen_reg_rtx (dreg_mode);
2974 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
2975 rtx len0 = gen_lowpart (Pmode, reg0);
2977 emit_clobber (reg0);
2978 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2979 emit_move_insn (len0, operands[1]);
2981 emit_move_insn (reg1, const0_rtx);
2983 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2988 (define_insn "*setmem_long"
2989 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2990 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2991 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2993 (use (match_operand:<DBL> 1 "register_operand" "d"))
2994 (clobber (reg:CC CC_REGNUM))]
2995 "TARGET_64BIT || !TARGET_ZARCH"
2996 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2997 [(set_attr "length" "8")
2998 (set_attr "type" "vs")])
3000 (define_insn "*setmem_long_and"
3001 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3002 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3003 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
3004 (match_operand 4 "const_int_operand" "n")))
3006 (use (match_operand:<DBL> 1 "register_operand" "d"))
3007 (clobber (reg:CC CC_REGNUM))]
3008 "(TARGET_64BIT || !TARGET_ZARCH) &&
3009 (INTVAL (operands[4]) & 255) == 255"
3010 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3011 [(set_attr "length" "8")
3012 (set_attr "type" "vs")])
3014 (define_insn "*setmem_long_31z"
3015 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3016 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3017 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
3019 (use (match_operand:TI 1 "register_operand" "d"))
3020 (clobber (reg:CC CC_REGNUM))]
3021 "!TARGET_64BIT && TARGET_ZARCH"
3022 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3023 [(set_attr "length" "8")
3024 (set_attr "type" "vs")])
3027 ; cmpmemM instruction pattern(s).
3030 (define_expand "cmpmemsi"
3031 [(set (match_operand:SI 0 "register_operand" "")
3032 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3033 (match_operand:BLK 2 "memory_operand" "") ) )
3034 (use (match_operand:SI 3 "general_operand" ""))
3035 (use (match_operand:SI 4 "" ""))]
3038 if (s390_expand_cmpmem (operands[0], operands[1],
3039 operands[2], operands[3]))
3045 ; Compare a block that is up to 256 bytes in length.
3046 ; The block length is taken as (operands[2] % 256) + 1.
3048 (define_expand "cmpmem_short"
3050 [(set (reg:CCU CC_REGNUM)
3051 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3052 (match_operand:BLK 1 "memory_operand" "")))
3053 (use (match_operand 2 "nonmemory_operand" ""))
3054 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3055 (clobber (match_dup 3))])]
3057 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3059 (define_insn "*cmpmem_short"
3060 [(set (reg:CCU CC_REGNUM)
3061 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3062 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3063 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3064 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3065 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3066 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3068 [(set_attr "type" "cs")
3069 (set_attr "cpu_facility" "*,*,z10,*")])
3072 [(set (reg:CCU CC_REGNUM)
3073 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3074 (match_operand:BLK 1 "memory_operand" "")))
3075 (use (match_operand 2 "const_int_operand" ""))
3076 (use (match_operand 3 "immediate_operand" ""))
3077 (clobber (scratch))]
3080 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3081 (use (match_dup 2))])]
3082 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3085 [(set (reg:CCU CC_REGNUM)
3086 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3087 (match_operand:BLK 1 "memory_operand" "")))
3088 (use (match_operand 2 "register_operand" ""))
3089 (use (match_operand 3 "memory_operand" ""))
3090 (clobber (scratch))]
3093 [(unspec [(match_dup 2) (match_dup 3)
3094 (const_int 0)] UNSPEC_EXECUTE)
3095 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3096 (use (const_int 1))])]
3100 [(set (reg:CCU CC_REGNUM)
3101 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3102 (match_operand:BLK 1 "memory_operand" "")))
3103 (use (match_operand 2 "register_operand" ""))
3104 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3105 (clobber (scratch))]
3106 "TARGET_Z10 && reload_completed"
3108 [(unspec [(match_dup 2) (const_int 0)
3109 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3110 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3111 (use (const_int 1))])]
3112 "operands[4] = gen_label_rtx ();")
3115 [(set (reg:CCU CC_REGNUM)
3116 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3117 (match_operand:BLK 1 "memory_operand" "")))
3118 (use (match_operand 2 "register_operand" ""))
3119 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3120 (clobber (match_operand 3 "register_operand" ""))]
3121 "reload_completed && TARGET_CPU_ZARCH"
3122 [(set (match_dup 3) (label_ref (match_dup 4)))
3124 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3125 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3126 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3127 (use (const_int 1))])]
3128 "operands[4] = gen_label_rtx ();")
3130 ; Compare a block of arbitrary length.
3132 (define_expand "cmpmem_long"
3134 [(clobber (match_dup 2))
3135 (clobber (match_dup 3))
3136 (set (reg:CCU CC_REGNUM)
3137 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3138 (match_operand:BLK 1 "memory_operand" "")))
3139 (use (match_operand 2 "general_operand" ""))
3140 (use (match_dup 3))])]
3143 enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3144 enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3145 rtx reg0 = gen_reg_rtx (dreg_mode);
3146 rtx reg1 = gen_reg_rtx (dreg_mode);
3147 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3148 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3149 rtx len0 = gen_lowpart (Pmode, reg0);
3150 rtx len1 = gen_lowpart (Pmode, reg1);
3152 emit_clobber (reg0);
3153 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3154 emit_move_insn (len0, operands[2]);
3156 emit_clobber (reg1);
3157 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3158 emit_move_insn (len1, operands[2]);
3160 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3161 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3166 (define_insn "*cmpmem_long"
3167 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3168 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3169 (set (reg:CCU CC_REGNUM)
3170 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3171 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3173 (use (match_dup 3))]
3174 "TARGET_64BIT || !TARGET_ZARCH"
3175 "clcle\t%0,%1,0\;jo\t.-4"
3176 [(set_attr "length" "8")
3177 (set_attr "type" "vs")])
3179 (define_insn "*cmpmem_long_31z"
3180 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3181 (clobber (match_operand:TI 1 "register_operand" "=d"))
3182 (set (reg:CCU CC_REGNUM)
3183 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3184 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3186 (use (match_dup 3))]
3187 "!TARGET_64BIT && TARGET_ZARCH"
3188 "clcle\t%0,%1,0\;jo\t.-4"
3189 [(set_attr "op_type" "NN")
3190 (set_attr "type" "vs")
3191 (set_attr "length" "8")])
3193 ; Convert CCUmode condition code to integer.
3194 ; Result is zero if EQ, positive if LTU, negative if GTU.
3196 (define_insn_and_split "cmpint"
3197 [(set (match_operand:SI 0 "register_operand" "=d")
3198 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3200 (clobber (reg:CC CC_REGNUM))]
3204 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3206 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3207 (clobber (reg:CC CC_REGNUM))])])
3209 (define_insn_and_split "*cmpint_cc"
3210 [(set (reg CC_REGNUM)
3211 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3214 (set (match_operand:SI 0 "register_operand" "=d")
3215 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3216 "s390_match_ccmode (insn, CCSmode)"
3218 "&& reload_completed"
3219 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3221 [(set (match_dup 2) (match_dup 3))
3222 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3224 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3225 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3226 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3229 (define_insn_and_split "*cmpint_sign"
3230 [(set (match_operand:DI 0 "register_operand" "=d")
3231 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3232 UNSPEC_CCU_TO_INT)))
3233 (clobber (reg:CC CC_REGNUM))]
3236 "&& reload_completed"
3237 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3239 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3240 (clobber (reg:CC CC_REGNUM))])])
3242 (define_insn_and_split "*cmpint_sign_cc"
3243 [(set (reg CC_REGNUM)
3244 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3245 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3246 UNSPEC_CCU_TO_INT) 0)
3247 (const_int 32)) (const_int 32))
3249 (set (match_operand:DI 0 "register_operand" "=d")
3250 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3251 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3253 "&& reload_completed"
3254 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3256 [(set (match_dup 2) (match_dup 3))
3257 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3259 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3260 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3261 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3266 ;;- Conversion instructions.
3269 (define_insn "*sethighpartsi"
3270 [(set (match_operand:SI 0 "register_operand" "=d,d")
3271 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3272 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3273 (clobber (reg:CC CC_REGNUM))]
3278 [(set_attr "op_type" "RS,RSY")
3279 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3281 (define_insn "*sethighpartdi_64"
3282 [(set (match_operand:DI 0 "register_operand" "=d")
3283 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3284 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3285 (clobber (reg:CC CC_REGNUM))]
3288 [(set_attr "op_type" "RSY")
3289 (set_attr "z10prop" "z10_super")])
3291 (define_insn "*sethighpartdi_31"
3292 [(set (match_operand:DI 0 "register_operand" "=d,d")
3293 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3294 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3295 (clobber (reg:CC CC_REGNUM))]
3300 [(set_attr "op_type" "RS,RSY")
3301 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3304 (define_insn_and_split "*extzv<mode>"
3305 [(set (match_operand:GPR 0 "register_operand" "=d")
3306 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3307 (match_operand 2 "const_int_operand" "n")
3309 (clobber (reg:CC CC_REGNUM))]
3310 "INTVAL (operands[2]) > 0
3311 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3313 "&& reload_completed"
3315 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3316 (clobber (reg:CC CC_REGNUM))])
3317 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3319 int bitsize = INTVAL (operands[2]);
3320 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3321 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3323 operands[1] = adjust_address (operands[1], BLKmode, 0);
3324 set_mem_size (operands[1], size);
3325 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3326 operands[3] = GEN_INT (mask);
3329 (define_insn_and_split "*extv<mode>"
3330 [(set (match_operand:GPR 0 "register_operand" "=d")
3331 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3332 (match_operand 2 "const_int_operand" "n")
3334 (clobber (reg:CC CC_REGNUM))]
3335 "INTVAL (operands[2]) > 0
3336 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3338 "&& reload_completed"
3340 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3341 (clobber (reg:CC CC_REGNUM))])
3343 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3344 (clobber (reg:CC CC_REGNUM))])]
3346 int bitsize = INTVAL (operands[2]);
3347 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3348 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3350 operands[1] = adjust_address (operands[1], BLKmode, 0);
3351 set_mem_size (operands[1], size);
3352 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3353 operands[3] = GEN_INT (mask);
3357 ; insv instruction patterns
3360 (define_expand "insv"
3361 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3362 (match_operand 1 "const_int_operand" "")
3363 (match_operand 2 "const_int_operand" ""))
3364 (match_operand 3 "general_operand" ""))]
3367 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3372 (define_insn "*insv<mode>_zEC12"
3373 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3374 (match_operand 1 "const_int_operand" "I")
3375 (match_operand 2 "const_int_operand" "I"))
3376 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3378 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3379 GET_MODE_BITSIZE (<MODE>mode)"
3381 int start = INTVAL (operands[2]);
3382 int size = INTVAL (operands[1]);
3383 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3385 operands[2] = GEN_INT (offset + start); /* start bit position */
3386 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3387 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3388 start - size); /* left shift count */
3390 return "risbgn\t%0,%3,%b2,%b1,%b4";
3392 [(set_attr "op_type" "RIE")])
3394 (define_insn "*insv<mode>_z10"
3395 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3396 (match_operand 1 "const_int_operand" "I")
3397 (match_operand 2 "const_int_operand" "I"))
3398 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3399 (clobber (reg:CC CC_REGNUM))]
3401 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3402 GET_MODE_BITSIZE (<MODE>mode)"
3404 int start = INTVAL (operands[2]);
3405 int size = INTVAL (operands[1]);
3406 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3408 operands[2] = GEN_INT (offset + start); /* start bit position */
3409 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3410 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3411 start - size); /* left shift count */
3413 return "risbg\t%0,%3,%b2,%b1,%b4";
3415 [(set_attr "op_type" "RIE")
3416 (set_attr "z10prop" "z10_super_E1")])
3418 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3419 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3420 (define_insn "*insv<mode>_zEC12_noshift"
3421 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3422 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3423 (match_operand 2 "const_int_operand" "n"))
3424 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3425 (match_operand 4 "const_int_operand" "n"))))]
3427 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3428 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3429 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3435 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3436 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3438 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3439 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3440 operands[7] = const0_rtx; /* left shift count */
3442 return "risbgn\t%0,%1,%b5,%b6,%b7";
3444 [(set_attr "op_type" "RIE")])
3446 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3447 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3448 (define_insn "*insv<mode>_z10_noshift"
3449 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3450 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3451 (match_operand 2 "const_int_operand" "n"))
3452 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3453 (match_operand 4 "const_int_operand" "n"))))
3454 (clobber (reg:CC CC_REGNUM))]
3456 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3457 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3458 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3464 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3465 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3467 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3468 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3469 operands[7] = const0_rtx; /* left shift count */
3471 return "risbg\t%0,%1,%b5,%b6,%b7";
3473 [(set_attr "op_type" "RIE")
3474 (set_attr "z10prop" "z10_super_E1")])
3476 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3477 (define_insn "*insv<mode>_or_z10_noshift"
3478 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3479 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3480 (match_operand 2 "const_int_operand" "n"))
3481 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3482 (clobber (reg:CC CC_REGNUM))]
3484 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3485 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3490 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3491 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3493 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3494 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3495 operands[6] = const0_rtx; /* left shift count */
3497 return "rosbg\t%0,%1,%b4,%b5,%b6";
3499 [(set_attr "op_type" "RIE")])
3501 (define_insn "*insv<mode>_mem_reg"
3502 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
3503 (match_operand 1 "const_int_operand" "n,n")
3505 (match_operand:W 2 "register_operand" "d,d"))]
3506 "INTVAL (operands[1]) > 0
3507 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3508 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3510 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3512 operands[1] = GEN_INT ((1ul << size) - 1);
3513 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3514 : "stcmy\t%2,%1,%S0";
3516 [(set_attr "op_type" "RS,RSY")
3517 (set_attr "z10prop" "z10_super,z10_super")])
3519 (define_insn "*insvdi_mem_reghigh"
3520 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3521 (match_operand 1 "const_int_operand" "n")
3523 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3526 && INTVAL (operands[1]) > 0
3527 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3528 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3530 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3532 operands[1] = GEN_INT ((1ul << size) - 1);
3533 return "stcmh\t%2,%1,%S0";
3535 [(set_attr "op_type" "RSY")
3536 (set_attr "z10prop" "z10_super")])
3538 (define_insn "*insvdi_reg_imm"
3539 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3541 (match_operand 1 "const_int_operand" "n"))
3542 (match_operand:DI 2 "const_int_operand" "n"))]
3544 && INTVAL (operands[1]) >= 0
3545 && INTVAL (operands[1]) < BITS_PER_WORD
3546 && INTVAL (operands[1]) % 16 == 0"
3548 switch (BITS_PER_WORD - INTVAL (operands[1]))
3550 case 64: return "iihh\t%0,%x2"; break;
3551 case 48: return "iihl\t%0,%x2"; break;
3552 case 32: return "iilh\t%0,%x2"; break;
3553 case 16: return "iill\t%0,%x2"; break;
3554 default: gcc_unreachable();
3557 [(set_attr "op_type" "RI")
3558 (set_attr "z10prop" "z10_super_E1")])
3560 ; Update the left-most 32 bit of a DI.
3561 (define_insn "*insv_h_di_reg_extimm"
3562 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3565 (match_operand:DI 1 "const_int_operand" "n"))]
3568 [(set_attr "op_type" "RIL")
3569 (set_attr "z10prop" "z10_fwd_E1")])
3571 ; Update the right-most 32 bit of a DI, or the whole of a SI.
3572 (define_insn "*insv_l<mode>_reg_extimm"
3573 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3575 (match_operand 1 "const_int_operand" "n"))
3576 (match_operand:P 2 "const_int_operand" "n"))]
3578 && BITS_PER_WORD - INTVAL (operands[1]) == 32"
3580 [(set_attr "op_type" "RIL")
3581 (set_attr "z10prop" "z10_fwd_A1")])
3584 ; extendsidi2 instruction pattern(s).
3587 (define_expand "extendsidi2"
3588 [(set (match_operand:DI 0 "register_operand" "")
3589 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3594 emit_clobber (operands[0]);
3595 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3596 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3597 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3602 (define_insn "*extendsidi2"
3603 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3604 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3610 [(set_attr "op_type" "RRE,RXY,RIL")
3611 (set_attr "type" "*,*,larl")
3612 (set_attr "cpu_facility" "*,*,z10")
3613 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3616 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3619 (define_expand "extend<HQI:mode><DSI:mode>2"
3620 [(set (match_operand:DSI 0 "register_operand" "")
3621 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3624 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
3626 rtx tmp = gen_reg_rtx (SImode);
3627 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3628 emit_insn (gen_extendsidi2 (operands[0], tmp));
3631 else if (!TARGET_EXTIMM)
3633 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3634 GET_MODE_BITSIZE (<HQI:MODE>mode));
3636 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3637 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3638 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3644 ; extendhidi2 instruction pattern(s).
3647 (define_insn "*extendhidi2_extimm"
3648 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3649 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3650 "TARGET_ZARCH && TARGET_EXTIMM"
3655 [(set_attr "op_type" "RRE,RXY,RIL")
3656 (set_attr "type" "*,*,larl")
3657 (set_attr "cpu_facility" "extimm,extimm,z10")
3658 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3660 (define_insn "*extendhidi2"
3661 [(set (match_operand:DI 0 "register_operand" "=d")
3662 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3665 [(set_attr "op_type" "RXY")
3666 (set_attr "z10prop" "z10_super_E1")])
3669 ; extendhisi2 instruction pattern(s).
3672 (define_insn "*extendhisi2_extimm"
3673 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3674 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3681 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3682 (set_attr "type" "*,*,*,larl")
3683 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3684 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3686 (define_insn "*extendhisi2"
3687 [(set (match_operand:SI 0 "register_operand" "=d,d")
3688 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3693 [(set_attr "op_type" "RX,RXY")
3694 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3697 ; extendqi(si|di)2 instruction pattern(s).
3700 ; lbr, lgbr, lb, lgb
3701 (define_insn "*extendqi<mode>2_extimm"
3702 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3703 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3708 [(set_attr "op_type" "RRE,RXY")
3709 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3712 (define_insn "*extendqi<mode>2"
3713 [(set (match_operand:GPR 0 "register_operand" "=d")
3714 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3715 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3717 [(set_attr "op_type" "RXY")
3718 (set_attr "z10prop" "z10_super_E1")])
3720 (define_insn_and_split "*extendqi<mode>2_short_displ"
3721 [(set (match_operand:GPR 0 "register_operand" "=d")
3722 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3723 (clobber (reg:CC CC_REGNUM))]
3724 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3726 "&& reload_completed"
3728 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3729 (clobber (reg:CC CC_REGNUM))])
3731 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3732 (clobber (reg:CC CC_REGNUM))])]
3734 operands[1] = adjust_address (operands[1], BLKmode, 0);
3735 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
3736 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3737 - GET_MODE_BITSIZE (QImode));
3741 ; zero_extendsidi2 instruction pattern(s).
3744 (define_expand "zero_extendsidi2"
3745 [(set (match_operand:DI 0 "register_operand" "")
3746 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3751 emit_clobber (operands[0]);
3752 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3753 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3758 (define_insn "*zero_extendsidi2"
3759 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3760 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3766 [(set_attr "op_type" "RRE,RXY,RIL")
3767 (set_attr "type" "*,*,larl")
3768 (set_attr "cpu_facility" "*,*,z10")
3769 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3772 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3775 (define_insn "*llgt_sidi"
3776 [(set (match_operand:DI 0 "register_operand" "=d")
3777 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3778 (const_int 2147483647)))]
3781 [(set_attr "op_type" "RXE")
3782 (set_attr "z10prop" "z10_super_E1")])
3784 (define_insn_and_split "*llgt_sidi_split"
3785 [(set (match_operand:DI 0 "register_operand" "=d")
3786 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3787 (const_int 2147483647)))
3788 (clobber (reg:CC CC_REGNUM))]
3791 "&& reload_completed"
3793 (and:DI (subreg:DI (match_dup 1) 0)
3794 (const_int 2147483647)))]
3797 (define_insn "*llgt_sisi"
3798 [(set (match_operand:SI 0 "register_operand" "=d,d")
3799 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3800 (const_int 2147483647)))]
3805 [(set_attr "op_type" "RRE,RXE")
3806 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3808 (define_insn "*llgt_didi"
3809 [(set (match_operand:DI 0 "register_operand" "=d,d")
3810 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3811 (const_int 2147483647)))]
3816 [(set_attr "op_type" "RRE,RXE")
3817 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3820 [(set (match_operand:DSI 0 "register_operand" "")
3821 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
3822 (const_int 2147483647)))
3823 (clobber (reg:CC CC_REGNUM))]
3824 "TARGET_ZARCH && reload_completed"
3826 (and:DSI (match_dup 1)
3827 (const_int 2147483647)))]
3831 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3834 (define_expand "zero_extend<mode>di2"
3835 [(set (match_operand:DI 0 "register_operand" "")
3836 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3841 rtx tmp = gen_reg_rtx (SImode);
3842 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3843 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3846 else if (!TARGET_EXTIMM)
3848 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3849 GET_MODE_BITSIZE(<MODE>mode));
3850 operands[1] = gen_lowpart (DImode, operands[1]);
3851 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3852 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3857 (define_expand "zero_extend<mode>si2"
3858 [(set (match_operand:SI 0 "register_operand" "")
3859 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3864 operands[1] = gen_lowpart (SImode, operands[1]);
3865 emit_insn (gen_andsi3 (operands[0], operands[1],
3866 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3872 (define_insn "*zero_extendhi<mode>2_z10"
3873 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3874 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3880 [(set_attr "op_type" "RXY,RRE,RIL")
3881 (set_attr "type" "*,*,larl")
3882 (set_attr "cpu_facility" "*,*,z10")
3883 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
3885 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3886 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3887 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3888 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3893 [(set_attr "op_type" "RRE,RXY")
3894 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3897 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3898 [(set (match_operand:GPR 0 "register_operand" "=d")
3899 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3900 "TARGET_ZARCH && !TARGET_EXTIMM"
3902 [(set_attr "op_type" "RXY")
3903 (set_attr "z10prop" "z10_fwd_A3")])
3905 (define_insn_and_split "*zero_extendhisi2_31"
3906 [(set (match_operand:SI 0 "register_operand" "=&d")
3907 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3908 (clobber (reg:CC CC_REGNUM))]
3911 "&& reload_completed"
3912 [(set (match_dup 0) (const_int 0))
3914 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3915 (clobber (reg:CC CC_REGNUM))])]
3916 "operands[2] = gen_lowpart (HImode, operands[0]);")
3918 (define_insn_and_split "*zero_extendqisi2_31"
3919 [(set (match_operand:SI 0 "register_operand" "=&d")
3920 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3923 "&& reload_completed"
3924 [(set (match_dup 0) (const_int 0))
3925 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3926 "operands[2] = gen_lowpart (QImode, operands[0]);")
3929 ; zero_extendqihi2 instruction pattern(s).
3932 (define_expand "zero_extendqihi2"
3933 [(set (match_operand:HI 0 "register_operand" "")
3934 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3935 "TARGET_ZARCH && !TARGET_EXTIMM"
3937 operands[1] = gen_lowpart (HImode, operands[1]);
3938 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3942 (define_insn "*zero_extendqihi2_64"
3943 [(set (match_operand:HI 0 "register_operand" "=d")
3944 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3945 "TARGET_ZARCH && !TARGET_EXTIMM"
3947 [(set_attr "op_type" "RXY")
3948 (set_attr "z10prop" "z10_fwd_A3")])
3950 (define_insn_and_split "*zero_extendqihi2_31"
3951 [(set (match_operand:HI 0 "register_operand" "=&d")
3952 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3955 "&& reload_completed"
3956 [(set (match_dup 0) (const_int 0))
3957 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3958 "operands[2] = gen_lowpart (QImode, operands[0]);")
3961 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3964 (define_expand "fixuns_truncdddi2"
3966 [(set (match_operand:DI 0 "register_operand" "")
3967 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3968 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
3969 (clobber (reg:CC CC_REGNUM))])]
3975 rtx label1 = gen_label_rtx ();
3976 rtx label2 = gen_label_rtx ();
3977 rtx temp = gen_reg_rtx (TDmode);
3978 REAL_VALUE_TYPE cmp, sub;
3980 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3981 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3983 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3984 solution is doing the check and the subtraction in TD mode and using a
3985 TD -> DI convert afterwards. */
3986 emit_insn (gen_extendddtd2 (temp, operands[1]));
3987 temp = force_reg (TDmode, temp);
3988 emit_cmp_and_jump_insns (temp,
3989 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
3990 LT, NULL_RTX, VOIDmode, 0, label1);
3991 emit_insn (gen_subtd3 (temp, temp,
3992 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3993 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3996 emit_label (label1);
3997 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3998 emit_label (label2);
4003 (define_expand "fixuns_trunctddi2"
4005 [(set (match_operand:DI 0 "register_operand" "")
4006 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4007 (unspec:DI [(const_int 5)] UNSPEC_ROUND)
4008 (clobber (reg:CC CC_REGNUM))])]
4014 rtx label1 = gen_label_rtx ();
4015 rtx label2 = gen_label_rtx ();
4016 rtx temp = gen_reg_rtx (TDmode);
4017 REAL_VALUE_TYPE cmp, sub;
4019 operands[1] = force_reg (TDmode, operands[1]);
4020 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4021 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4023 emit_cmp_and_jump_insns (operands[1],
4024 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
4025 LT, NULL_RTX, VOIDmode, 0, label1);
4026 emit_insn (gen_subtd3 (temp, operands[1],
4027 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
4028 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
4031 emit_label (label1);
4032 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
4033 emit_label (label2);
4039 ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
4040 ; instruction pattern(s).
4043 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
4045 [(set (match_operand:GPR 0 "register_operand" "")
4046 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4047 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4048 (clobber (reg:CC CC_REGNUM))])]
4053 rtx label1 = gen_label_rtx ();
4054 rtx label2 = gen_label_rtx ();
4055 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4056 REAL_VALUE_TYPE cmp, sub;
4058 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4059 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
4060 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
4062 emit_cmp_and_jump_insns (operands[1],
4063 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
4064 LT, NULL_RTX, VOIDmode, 0, label1);
4065 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4066 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
4067 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4071 emit_label (label1);
4072 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4073 operands[1], GEN_INT (5)));
4074 emit_label (label2);
4079 ; fixuns_trunc(td|dd)si2 expander
4080 (define_expand "fixuns_trunc<mode>si2"
4082 [(set (match_operand:SI 0 "register_operand" "")
4083 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4084 (unspec:SI [(const_int 5)] UNSPEC_ROUND)
4085 (clobber (reg:CC CC_REGNUM))])]
4086 "TARGET_Z196 && TARGET_HARD_DFP"
4089 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4091 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4092 ; clfdtr, clfxtr, clgdtr, clgxtr
4093 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4094 [(set (match_operand:GPR 0 "register_operand" "=r")
4095 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4096 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4097 (clobber (reg:CC CC_REGNUM))]
4099 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4100 [(set_attr "op_type" "RRF")
4101 (set_attr "type" "ftoi")])
4103 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4104 [(set (match_operand:GPR 0 "register_operand" "")
4105 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4108 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4113 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
4114 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
4115 [(set (match_operand:GPR 0 "register_operand" "=d")
4116 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
4117 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4118 (clobber (reg:CC CC_REGNUM))]
4120 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
4121 [(set_attr "op_type" "RRE")
4122 (set_attr "type" "ftoi")])
4126 ; fix_trunc(td|dd)di2 instruction pattern(s).
4129 (define_expand "fix_trunc<mode>di2"
4130 [(set (match_operand:DI 0 "register_operand" "")
4131 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
4132 "TARGET_ZARCH && TARGET_HARD_DFP"
4134 operands[1] = force_reg (<MODE>mode, operands[1]);
4135 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
4141 (define_insn "fix_trunc<DFP:mode>di2_dfp"
4142 [(set (match_operand:DI 0 "register_operand" "=d")
4143 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
4144 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
4145 (clobber (reg:CC CC_REGNUM))]
4146 "TARGET_ZARCH && TARGET_HARD_DFP"
4147 "cg<DFP:xde>tr\t%0,%h2,%1"
4148 [(set_attr "op_type" "RRF")
4149 (set_attr "type" "ftoidfp")])
4153 ; fix_trunctf(si|di)2 instruction pattern(s).
4156 (define_expand "fix_trunctf<mode>2"
4157 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
4158 (fix:GPR (match_operand:TF 1 "register_operand" "")))
4159 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
4160 (clobber (reg:CC CC_REGNUM))])]
4166 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4169 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
4170 (define_insn "floatdi<mode>2"
4171 [(set (match_operand:FP 0 "register_operand" "=f")
4172 (float:FP (match_operand:DI 1 "register_operand" "d")))]
4173 "TARGET_ZARCH && TARGET_HARD_FLOAT"
4174 "c<xde>g<bt>r\t%0,%1"
4175 [(set_attr "op_type" "RRE")
4176 (set_attr "type" "itof<mode>" )])
4178 ; cxfbr, cdfbr, cefbr
4179 (define_insn "floatsi<mode>2"
4180 [(set (match_operand:BFP 0 "register_operand" "=f")
4181 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
4184 [(set_attr "op_type" "RRE")
4185 (set_attr "type" "itof<mode>" )])
4188 (define_insn "floatsi<mode>2"
4189 [(set (match_operand:DFP 0 "register_operand" "=f")
4190 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
4191 "TARGET_Z196 && TARGET_HARD_FLOAT"
4192 "c<xde>ftr\t%0,0,%1,0"
4193 [(set_attr "op_type" "RRE")
4194 (set_attr "type" "itof<mode>" )])
4197 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
4200 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
4201 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
4202 (define_insn "floatuns<GPR:mode><FP:mode>2"
4203 [(set (match_operand:FP 0 "register_operand" "=f")
4204 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
4205 "TARGET_Z196 && TARGET_HARD_FLOAT"
4206 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
4207 [(set_attr "op_type" "RRE")
4208 (set_attr "type" "itof<FP:mode>" )])
4211 ; truncdfsf2 instruction pattern(s).
4214 (define_insn "truncdfsf2"
4215 [(set (match_operand:SF 0 "register_operand" "=f")
4216 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
4219 [(set_attr "op_type" "RRE")
4220 (set_attr "type" "ftruncdf")])
4223 ; trunctf(df|sf)2 instruction pattern(s).
4227 (define_insn "trunctf<mode>2"
4228 [(set (match_operand:DSF 0 "register_operand" "=f")
4229 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
4230 (clobber (match_scratch:TF 2 "=f"))]
4232 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
4233 [(set_attr "length" "6")
4234 (set_attr "type" "ftrunctf")])
4237 ; trunctddd2 and truncddsd2 instruction pattern(s).
4240 (define_insn "trunctddd2"
4241 [(set (match_operand:DD 0 "register_operand" "=f")
4242 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
4243 (clobber (match_scratch:TD 2 "=f"))]
4245 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
4246 [(set_attr "length" "6")
4247 (set_attr "type" "ftruncdd")])
4249 (define_insn "truncddsd2"
4250 [(set (match_operand:SD 0 "register_operand" "=f")
4251 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4254 [(set_attr "op_type" "RRF")
4255 (set_attr "type" "ftruncsd")])
4258 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4261 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4262 (define_insn "extend<DSF:mode><BFP:mode>2"
4263 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4264 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4266 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4268 l<BFP:xde><DSF:xde>br\t%0,%1
4269 l<BFP:xde><DSF:xde>b\t%0,%1"
4270 [(set_attr "op_type" "RRE,RXE")
4271 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4274 ; extendddtd2 and extendsddd2 instruction pattern(s).
4277 (define_insn "extendddtd2"
4278 [(set (match_operand:TD 0 "register_operand" "=f")
4279 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4282 [(set_attr "op_type" "RRF")
4283 (set_attr "type" "fsimptf")])
4285 (define_insn "extendsddd2"
4286 [(set (match_operand:DD 0 "register_operand" "=f")
4287 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4290 [(set_attr "op_type" "RRF")
4291 (set_attr "type" "fsimptf")])
4293 ; Binary <-> Decimal floating point trunc patterns
4296 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4297 [(set (reg:DFP_ALL FPR0_REGNUM)
4298 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4299 (use (reg:SI GPR0_REGNUM))
4300 (clobber (reg:CC CC_REGNUM))]
4304 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4305 [(set (reg:BFP FPR0_REGNUM)
4306 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4307 (use (reg:SI GPR0_REGNUM))
4308 (clobber (reg:CC CC_REGNUM))]
4312 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4313 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4314 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4316 [(set (reg:DFP_ALL FPR0_REGNUM)
4317 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4318 (use (reg:SI GPR0_REGNUM))
4319 (clobber (reg:CC CC_REGNUM))])
4320 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4321 (reg:DFP_ALL FPR0_REGNUM))]
4323 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4325 HOST_WIDE_INT flags;
4327 flags = (PFPO_CONVERT |
4328 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4329 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4331 operands[2] = GEN_INT (flags);
4334 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4335 [(set (reg:DFP_ALL FPR2_REGNUM)
4336 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4337 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4339 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4340 (use (reg:SI GPR0_REGNUM))
4341 (clobber (reg:CC CC_REGNUM))])
4342 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4344 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4346 HOST_WIDE_INT flags;
4348 flags = (PFPO_CONVERT |
4349 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4350 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4352 operands[2] = GEN_INT (flags);
4356 ; Binary <-> Decimal floating point extend patterns
4359 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4360 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4361 (use (reg:SI GPR0_REGNUM))
4362 (clobber (reg:CC CC_REGNUM))]
4366 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4367 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4368 (use (reg:SI GPR0_REGNUM))
4369 (clobber (reg:CC CC_REGNUM))]
4373 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4374 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4375 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4377 [(set (reg:DFP_ALL FPR0_REGNUM)
4378 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4379 (use (reg:SI GPR0_REGNUM))
4380 (clobber (reg:CC CC_REGNUM))])
4381 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4382 (reg:DFP_ALL FPR0_REGNUM))]
4384 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4386 HOST_WIDE_INT flags;
4388 flags = (PFPO_CONVERT |
4389 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4390 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4392 operands[2] = GEN_INT (flags);
4395 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4396 [(set (reg:DFP_ALL FPR2_REGNUM)
4397 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4398 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4400 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4401 (use (reg:SI GPR0_REGNUM))
4402 (clobber (reg:CC CC_REGNUM))])
4403 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4405 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4407 HOST_WIDE_INT flags;
4409 flags = (PFPO_CONVERT |
4410 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4411 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4413 operands[2] = GEN_INT (flags);
4418 ;; ARITHMETIC OPERATIONS
4420 ; arithmetic operations set the ConditionCode,
4421 ; because of unpredictable Bits in Register for Halfword and Byte
4422 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4425 ;;- Add instructions.
4429 ; addti3 instruction pattern(s).
4432 (define_insn_and_split "addti3"
4433 [(set (match_operand:TI 0 "register_operand" "=&d")
4434 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4435 (match_operand:TI 2 "general_operand" "do") ) )
4436 (clobber (reg:CC CC_REGNUM))]
4439 "&& reload_completed"
4441 [(set (reg:CCL1 CC_REGNUM)
4442 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4444 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4446 [(set (match_dup 3) (plus:DI
4447 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4448 (match_dup 4)) (match_dup 5)))
4449 (clobber (reg:CC CC_REGNUM))])]
4450 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4451 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4452 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4453 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4454 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4455 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4458 ; adddi3 instruction pattern(s).
4461 (define_expand "adddi3"
4463 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4464 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4465 (match_operand:DI 2 "general_operand" "")))
4466 (clobber (reg:CC CC_REGNUM))])]
4470 (define_insn "*adddi3_sign"
4471 [(set (match_operand:DI 0 "register_operand" "=d,d")
4472 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4473 (match_operand:DI 1 "register_operand" "0,0")))
4474 (clobber (reg:CC CC_REGNUM))]
4479 [(set_attr "op_type" "RRE,RXY")
4480 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4482 (define_insn "*adddi3_zero_cc"
4483 [(set (reg CC_REGNUM)
4484 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4485 (match_operand:DI 1 "register_operand" "0,0"))
4487 (set (match_operand:DI 0 "register_operand" "=d,d")
4488 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4489 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4493 [(set_attr "op_type" "RRE,RXY")
4494 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4496 (define_insn "*adddi3_zero_cconly"
4497 [(set (reg CC_REGNUM)
4498 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4499 (match_operand:DI 1 "register_operand" "0,0"))
4501 (clobber (match_scratch:DI 0 "=d,d"))]
4502 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4506 [(set_attr "op_type" "RRE,RXY")
4507 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4509 (define_insn "*adddi3_zero"
4510 [(set (match_operand:DI 0 "register_operand" "=d,d")
4511 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4512 (match_operand:DI 1 "register_operand" "0,0")))
4513 (clobber (reg:CC CC_REGNUM))]
4518 [(set_attr "op_type" "RRE,RXY")
4519 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4521 (define_insn_and_split "*adddi3_31z"
4522 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4523 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4524 (match_operand:DI 2 "general_operand" "do") ) )
4525 (clobber (reg:CC CC_REGNUM))]
4526 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4528 "&& reload_completed"
4530 [(set (reg:CCL1 CC_REGNUM)
4531 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4533 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4535 [(set (match_dup 3) (plus:SI
4536 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4537 (match_dup 4)) (match_dup 5)))
4538 (clobber (reg:CC CC_REGNUM))])]
4539 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4540 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4541 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4542 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4543 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4544 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4546 (define_insn_and_split "*adddi3_31"
4547 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4548 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4549 (match_operand:DI 2 "general_operand" "do") ) )
4550 (clobber (reg:CC CC_REGNUM))]
4553 "&& reload_completed"
4555 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4556 (clobber (reg:CC CC_REGNUM))])
4558 [(set (reg:CCL1 CC_REGNUM)
4559 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4561 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4563 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4565 (label_ref (match_dup 9))))
4567 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4568 (clobber (reg:CC CC_REGNUM))])
4570 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4571 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4572 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4573 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4574 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4575 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4576 operands[9] = gen_label_rtx ();")
4579 ; addsi3 instruction pattern(s).
4582 (define_expand "addsi3"
4584 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4585 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4586 (match_operand:SI 2 "general_operand" "")))
4587 (clobber (reg:CC CC_REGNUM))])]
4591 (define_insn "*addsi3_sign"
4592 [(set (match_operand:SI 0 "register_operand" "=d,d")
4593 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4594 (match_operand:SI 1 "register_operand" "0,0")))
4595 (clobber (reg:CC CC_REGNUM))]
4600 [(set_attr "op_type" "RX,RXY")
4601 (set_attr "z196prop" "z196_cracked,z196_cracked")])
4604 ; add(di|si)3 instruction pattern(s).
4607 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4608 (define_insn "*add<mode>3"
4609 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
4610 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
4611 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
4612 (clobber (reg:CC CC_REGNUM))]
4624 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
4625 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
4626 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
4627 z10_super_E1,z10_super_E1,z10_super_E1")])
4629 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
4630 (define_insn "*add<mode>3_carry1_cc"
4631 [(set (reg CC_REGNUM)
4632 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
4633 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
4635 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
4636 (plus:GPR (match_dup 1) (match_dup 2)))]
4637 "s390_match_ccmode (insn, CCL1mode)"
4643 al<g>hsik\t%0,%1,%h2
4647 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4648 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4649 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4650 z10_super_E1,z10_super_E1,z10_super_E1")])
4652 ; alr, al, aly, algr, alg, alrk, algrk
4653 (define_insn "*add<mode>3_carry1_cconly"
4654 [(set (reg CC_REGNUM)
4655 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4656 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4658 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4659 "s390_match_ccmode (insn, CCL1mode)"
4665 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4666 (set_attr "cpu_facility" "*,z196,*,*")
4667 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4669 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4670 (define_insn "*add<mode>3_carry2_cc"
4671 [(set (reg CC_REGNUM)
4672 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4673 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4675 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4676 (plus:GPR (match_dup 1) (match_dup 2)))]
4677 "s390_match_ccmode (insn, CCL1mode)"
4683 al<g>hsik\t%0,%1,%h2
4687 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4688 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4689 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
4690 z10_super_E1,z10_super_E1,z10_super_E1")])
4692 ; alr, al, aly, algr, alg, alrk, algrk
4693 (define_insn "*add<mode>3_carry2_cconly"
4694 [(set (reg CC_REGNUM)
4695 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4696 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4698 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4699 "s390_match_ccmode (insn, CCL1mode)"
4705 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4706 (set_attr "cpu_facility" "*,z196,*,*")
4707 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4709 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
4710 (define_insn "*add<mode>3_cc"
4711 [(set (reg CC_REGNUM)
4712 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
4713 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
4715 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
4716 (plus:GPR (match_dup 1) (match_dup 2)))]
4717 "s390_match_ccmode (insn, CCLmode)"
4723 al<g>hsik\t%0,%1,%h2
4727 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
4728 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
4729 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
4730 *,z10_super_E1,z10_super_E1,z10_super_E1")])
4732 ; alr, al, aly, algr, alg, alrk, algrk
4733 (define_insn "*add<mode>3_cconly"
4734 [(set (reg CC_REGNUM)
4735 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4736 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
4738 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4739 "s390_match_ccmode (insn, CCLmode)"
4745 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4746 (set_attr "cpu_facility" "*,z196,*,*")
4747 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4749 ; alr, al, aly, algr, alg, alrk, algrk
4750 (define_insn "*add<mode>3_cconly2"
4751 [(set (reg CC_REGNUM)
4752 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
4753 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
4754 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
4755 "s390_match_ccmode(insn, CCLmode)"
4761 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
4762 (set_attr "cpu_facility" "*,z196,*,*")
4763 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4765 ; ahi, afi, aghi, agfi, asi, agsi
4766 (define_insn "*add<mode>3_imm_cc"
4767 [(set (reg CC_REGNUM)
4768 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
4769 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
4771 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
4772 (plus:GPR (match_dup 1) (match_dup 2)))]
4773 "s390_match_ccmode (insn, CCAmode)
4774 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4775 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4776 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4777 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4783 [(set_attr "op_type" "RI,RIE,RIL,SIY")
4784 (set_attr "cpu_facility" "*,z196,extimm,z10")
4785 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
4788 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4791 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4792 (define_insn "add<mode>3"
4793 [(set (match_operand:FP 0 "register_operand" "=f, f")
4794 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4795 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4796 (clobber (reg:CC CC_REGNUM))]
4799 a<xde><bt>r\t%0,<op1>%2
4801 [(set_attr "op_type" "<RRer>,RXE")
4802 (set_attr "type" "fsimp<mode>")])
4804 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4805 (define_insn "*add<mode>3_cc"
4806 [(set (reg CC_REGNUM)
4807 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4808 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4809 (match_operand:FP 3 "const0_operand" "")))
4810 (set (match_operand:FP 0 "register_operand" "=f,f")
4811 (plus:FP (match_dup 1) (match_dup 2)))]
4812 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4814 a<xde><bt>r\t%0,<op1>%2
4816 [(set_attr "op_type" "<RRer>,RXE")
4817 (set_attr "type" "fsimp<mode>")])
4819 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4820 (define_insn "*add<mode>3_cconly"
4821 [(set (reg CC_REGNUM)
4822 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4823 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4824 (match_operand:FP 3 "const0_operand" "")))
4825 (clobber (match_scratch:FP 0 "=f,f"))]
4826 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4828 a<xde><bt>r\t%0,<op1>%2
4830 [(set_attr "op_type" "<RRer>,RXE")
4831 (set_attr "type" "fsimp<mode>")])
4835 ;;- Subtract instructions.
4839 ; subti3 instruction pattern(s).
4842 (define_insn_and_split "subti3"
4843 [(set (match_operand:TI 0 "register_operand" "=&d")
4844 (minus:TI (match_operand:TI 1 "register_operand" "0")
4845 (match_operand:TI 2 "general_operand" "do") ) )
4846 (clobber (reg:CC CC_REGNUM))]
4849 "&& reload_completed"
4851 [(set (reg:CCL2 CC_REGNUM)
4852 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4854 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4856 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4857 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4858 (clobber (reg:CC CC_REGNUM))])]
4859 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4860 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4861 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4862 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4863 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4864 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4867 ; subdi3 instruction pattern(s).
4870 (define_expand "subdi3"
4872 [(set (match_operand:DI 0 "register_operand" "")
4873 (minus:DI (match_operand:DI 1 "register_operand" "")
4874 (match_operand:DI 2 "general_operand" "")))
4875 (clobber (reg:CC CC_REGNUM))])]
4879 (define_insn "*subdi3_sign"
4880 [(set (match_operand:DI 0 "register_operand" "=d,d")
4881 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4882 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4883 (clobber (reg:CC CC_REGNUM))]
4888 [(set_attr "op_type" "RRE,RXY")
4889 (set_attr "z10prop" "z10_c,*")
4890 (set_attr "z196prop" "z196_cracked")])
4892 (define_insn "*subdi3_zero_cc"
4893 [(set (reg CC_REGNUM)
4894 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4895 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4897 (set (match_operand:DI 0 "register_operand" "=d,d")
4898 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4899 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4903 [(set_attr "op_type" "RRE,RXY")
4904 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4906 (define_insn "*subdi3_zero_cconly"
4907 [(set (reg CC_REGNUM)
4908 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4909 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4911 (clobber (match_scratch:DI 0 "=d,d"))]
4912 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
4916 [(set_attr "op_type" "RRE,RXY")
4917 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4919 (define_insn "*subdi3_zero"
4920 [(set (match_operand:DI 0 "register_operand" "=d,d")
4921 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4922 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4923 (clobber (reg:CC CC_REGNUM))]
4928 [(set_attr "op_type" "RRE,RXY")
4929 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4931 (define_insn_and_split "*subdi3_31z"
4932 [(set (match_operand:DI 0 "register_operand" "=&d")
4933 (minus:DI (match_operand:DI 1 "register_operand" "0")
4934 (match_operand:DI 2 "general_operand" "do") ) )
4935 (clobber (reg:CC CC_REGNUM))]
4936 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
4938 "&& reload_completed"
4940 [(set (reg:CCL2 CC_REGNUM)
4941 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4943 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4945 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4946 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4947 (clobber (reg:CC CC_REGNUM))])]
4948 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4949 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4950 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4951 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4952 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4953 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4955 (define_insn_and_split "*subdi3_31"
4956 [(set (match_operand:DI 0 "register_operand" "=&d")
4957 (minus:DI (match_operand:DI 1 "register_operand" "0")
4958 (match_operand:DI 2 "general_operand" "do") ) )
4959 (clobber (reg:CC CC_REGNUM))]
4962 "&& reload_completed"
4964 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4965 (clobber (reg:CC CC_REGNUM))])
4967 [(set (reg:CCL2 CC_REGNUM)
4968 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4970 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4972 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4974 (label_ref (match_dup 9))))
4976 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4977 (clobber (reg:CC CC_REGNUM))])
4979 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4980 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4981 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4982 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4983 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4984 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4985 operands[9] = gen_label_rtx ();")
4988 ; subsi3 instruction pattern(s).
4991 (define_expand "subsi3"
4993 [(set (match_operand:SI 0 "register_operand" "")
4994 (minus:SI (match_operand:SI 1 "register_operand" "")
4995 (match_operand:SI 2 "general_operand" "")))
4996 (clobber (reg:CC CC_REGNUM))])]
5000 (define_insn "*subsi3_sign"
5001 [(set (match_operand:SI 0 "register_operand" "=d,d")
5002 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
5003 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
5004 (clobber (reg:CC CC_REGNUM))]
5009 [(set_attr "op_type" "RX,RXY")
5010 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5013 ; sub(di|si)3 instruction pattern(s).
5016 ; sr, s, sy, sgr, sg, srk, sgrk
5017 (define_insn "*sub<mode>3"
5018 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5019 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5020 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
5021 (clobber (reg:CC CC_REGNUM))]
5028 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5029 (set_attr "cpu_facility" "*,z196,*,*")
5030 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5032 ; slr, sl, sly, slgr, slg, slrk, slgrk
5033 (define_insn "*sub<mode>3_borrow_cc"
5034 [(set (reg CC_REGNUM)
5035 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5036 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5038 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5039 (minus:GPR (match_dup 1) (match_dup 2)))]
5040 "s390_match_ccmode (insn, CCL2mode)"
5046 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5047 (set_attr "cpu_facility" "*,z196,*,*")
5048 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5050 ; slr, sl, sly, slgr, slg, slrk, slgrk
5051 (define_insn "*sub<mode>3_borrow_cconly"
5052 [(set (reg CC_REGNUM)
5053 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5054 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5056 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5057 "s390_match_ccmode (insn, CCL2mode)"
5063 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5064 (set_attr "cpu_facility" "*,z196,*,*")
5065 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5067 ; slr, sl, sly, slgr, slg, slrk, slgrk
5068 (define_insn "*sub<mode>3_cc"
5069 [(set (reg CC_REGNUM)
5070 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5071 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5073 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5074 (minus:GPR (match_dup 1) (match_dup 2)))]
5075 "s390_match_ccmode (insn, CCLmode)"
5081 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5082 (set_attr "cpu_facility" "*,z196,*,*")
5083 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5085 ; slr, sl, sly, slgr, slg, slrk, slgrk
5086 (define_insn "*sub<mode>3_cc2"
5087 [(set (reg CC_REGNUM)
5088 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5089 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5090 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
5091 (minus:GPR (match_dup 1) (match_dup 2)))]
5092 "s390_match_ccmode (insn, CCL3mode)"
5098 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5099 (set_attr "cpu_facility" "*,z196,*,*")
5100 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5102 ; slr, sl, sly, slgr, slg, slrk, slgrk
5103 (define_insn "*sub<mode>3_cconly"
5104 [(set (reg CC_REGNUM)
5105 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
5106 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5108 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5109 "s390_match_ccmode (insn, CCLmode)"
5115 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5116 (set_attr "cpu_facility" "*,z196,*,*")
5117 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5120 ; slr, sl, sly, slgr, slg, slrk, slgrk
5121 (define_insn "*sub<mode>3_cconly2"
5122 [(set (reg CC_REGNUM)
5123 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
5124 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
5125 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5126 "s390_match_ccmode (insn, CCL3mode)"
5132 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5133 (set_attr "cpu_facility" "*,z196,*,*")
5134 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
5138 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
5141 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5142 (define_insn "sub<mode>3"
5143 [(set (match_operand:FP 0 "register_operand" "=f, f")
5144 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5145 (match_operand:FP 2 "general_operand" "f,<Rf>")))
5146 (clobber (reg:CC CC_REGNUM))]
5149 s<xde><bt>r\t%0,<op1>%2
5151 [(set_attr "op_type" "<RRer>,RXE")
5152 (set_attr "type" "fsimp<mode>")])
5154 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5155 (define_insn "*sub<mode>3_cc"
5156 [(set (reg CC_REGNUM)
5157 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5158 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5159 (match_operand:FP 3 "const0_operand" "")))
5160 (set (match_operand:FP 0 "register_operand" "=f,f")
5161 (minus:FP (match_dup 1) (match_dup 2)))]
5162 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5164 s<xde><bt>r\t%0,<op1>%2
5166 [(set_attr "op_type" "<RRer>,RXE")
5167 (set_attr "type" "fsimp<mode>")])
5169 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
5170 (define_insn "*sub<mode>3_cconly"
5171 [(set (reg CC_REGNUM)
5172 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
5173 (match_operand:FP 2 "general_operand" "f,<Rf>"))
5174 (match_operand:FP 3 "const0_operand" "")))
5175 (clobber (match_scratch:FP 0 "=f,f"))]
5176 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5178 s<xde><bt>r\t%0,<op1>%2
5180 [(set_attr "op_type" "<RRer>,RXE")
5181 (set_attr "type" "fsimp<mode>")])
5185 ;;- Conditional add/subtract instructions.
5189 ; add(di|si)cc instruction pattern(s).
5192 ; the following 4 patterns are used when the result of an add with
5193 ; carry is checked for an overflow condition
5195 ; op1 + op2 + c < op1
5197 ; alcr, alc, alcgr, alcg
5198 (define_insn "*add<mode>3_alc_carry1_cc"
5199 [(set (reg CC_REGNUM)
5201 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5202 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5203 (match_operand:GPR 2 "general_operand" "d,RT"))
5205 (set (match_operand:GPR 0 "register_operand" "=d,d")
5206 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5207 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5211 [(set_attr "op_type" "RRE,RXY")
5212 (set_attr "z196prop" "z196_alone,z196_alone")])
5214 ; alcr, alc, alcgr, alcg
5215 (define_insn "*add<mode>3_alc_carry1_cconly"
5216 [(set (reg CC_REGNUM)
5218 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5219 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5220 (match_operand:GPR 2 "general_operand" "d,RT"))
5222 (clobber (match_scratch:GPR 0 "=d,d"))]
5223 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5227 [(set_attr "op_type" "RRE,RXY")
5228 (set_attr "z196prop" "z196_alone,z196_alone")])
5230 ; op1 + op2 + c < op2
5232 ; alcr, alc, alcgr, alcg
5233 (define_insn "*add<mode>3_alc_carry2_cc"
5234 [(set (reg CC_REGNUM)
5236 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5237 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5238 (match_operand:GPR 2 "general_operand" "d,RT"))
5240 (set (match_operand:GPR 0 "register_operand" "=d,d")
5241 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5242 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5246 [(set_attr "op_type" "RRE,RXY")])
5248 ; alcr, alc, alcgr, alcg
5249 (define_insn "*add<mode>3_alc_carry2_cconly"
5250 [(set (reg CC_REGNUM)
5252 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5253 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5254 (match_operand:GPR 2 "general_operand" "d,RT"))
5256 (clobber (match_scratch:GPR 0 "=d,d"))]
5257 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
5261 [(set_attr "op_type" "RRE,RXY")])
5263 ; alcr, alc, alcgr, alcg
5264 (define_insn "*add<mode>3_alc_cc"
5265 [(set (reg CC_REGNUM)
5267 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5268 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5269 (match_operand:GPR 2 "general_operand" "d,RT"))
5271 (set (match_operand:GPR 0 "register_operand" "=d,d")
5272 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5273 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5277 [(set_attr "op_type" "RRE,RXY")])
5279 ; alcr, alc, alcgr, alcg
5280 (define_insn "*add<mode>3_alc"
5281 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5282 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5283 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5284 (match_operand:GPR 2 "general_operand" "d,RT")))
5285 (clobber (reg:CC CC_REGNUM))]
5290 [(set_attr "op_type" "RRE,RXY")])
5292 ; slbr, slb, slbgr, slbg
5293 (define_insn "*sub<mode>3_slb_cc"
5294 [(set (reg CC_REGNUM)
5296 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5297 (match_operand:GPR 2 "general_operand" "d,RT"))
5298 (match_operand:GPR 3 "s390_slb_comparison" ""))
5300 (set (match_operand:GPR 0 "register_operand" "=d,d")
5301 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5302 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5306 [(set_attr "op_type" "RRE,RXY")
5307 (set_attr "z10prop" "z10_c,*")])
5309 ; slbr, slb, slbgr, slbg
5310 (define_insn "*sub<mode>3_slb"
5311 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5312 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5313 (match_operand:GPR 2 "general_operand" "d,RT"))
5314 (match_operand:GPR 3 "s390_slb_comparison" "")))
5315 (clobber (reg:CC CC_REGNUM))]
5320 [(set_attr "op_type" "RRE,RXY")
5321 (set_attr "z10prop" "z10_c,*")])
5323 (define_expand "add<mode>cc"
5324 [(match_operand:GPR 0 "register_operand" "")
5325 (match_operand 1 "comparison_operator" "")
5326 (match_operand:GPR 2 "register_operand" "")
5327 (match_operand:GPR 3 "const_int_operand" "")]
5329 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5330 XEXP (operands[1], 0), XEXP (operands[1], 1),
5331 operands[0], operands[2],
5332 operands[3])) FAIL; DONE;")
5335 ; scond instruction pattern(s).
5338 (define_insn_and_split "*scond<mode>"
5339 [(set (match_operand:GPR 0 "register_operand" "=&d")
5340 (match_operand:GPR 1 "s390_alc_comparison" ""))
5341 (clobber (reg:CC CC_REGNUM))]
5344 "&& reload_completed"
5345 [(set (match_dup 0) (const_int 0))
5347 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5349 (clobber (reg:CC CC_REGNUM))])]
5352 (define_insn_and_split "*scond<mode>_neg"
5353 [(set (match_operand:GPR 0 "register_operand" "=&d")
5354 (match_operand:GPR 1 "s390_slb_comparison" ""))
5355 (clobber (reg:CC CC_REGNUM))]
5358 "&& reload_completed"
5359 [(set (match_dup 0) (const_int 0))
5361 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5363 (clobber (reg:CC CC_REGNUM))])
5365 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5366 (clobber (reg:CC CC_REGNUM))])]
5370 (define_expand "cstore<mode>4"
5371 [(set (match_operand:SI 0 "register_operand" "")
5372 (match_operator:SI 1 "s390_scond_operator"
5373 [(match_operand:GPR 2 "register_operand" "")
5374 (match_operand:GPR 3 "general_operand" "")]))]
5376 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
5377 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5379 (define_expand "cstorecc4"
5381 [(set (match_operand:SI 0 "register_operand" "")
5382 (match_operator:SI 1 "s390_eqne_operator"
5383 [(match_operand:CCZ1 2 "register_operand")
5384 (match_operand 3 "const0_operand")]))
5385 (clobber (reg:CC CC_REGNUM))])]
5387 "emit_insn (gen_sne (operands[0], operands[2]));
5388 if (GET_CODE (operands[1]) == EQ)
5389 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
5392 (define_insn_and_split "sne"
5393 [(set (match_operand:SI 0 "register_operand" "=d")
5394 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5396 (clobber (reg:CC CC_REGNUM))]
5401 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5402 (clobber (reg:CC CC_REGNUM))])])
5406 ;; - Conditional move instructions (introduced with z196)
5409 (define_expand "mov<mode>cc"
5410 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
5411 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5412 (match_operand:GPR 2 "nonimmediate_operand" "")
5413 (match_operand:GPR 3 "nonimmediate_operand" "")))]
5415 "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
5416 XEXP (operands[1], 0), XEXP (operands[1], 1));")
5418 ; locr, loc, stoc, locgr, locg, stocg
5419 (define_insn_and_split "*mov<mode>cc"
5420 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
5422 (match_operator 1 "s390_comparison"
5423 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
5425 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
5426 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
5436 "&& reload_completed
5437 && MEM_P (operands[3]) && MEM_P (operands[4])"
5440 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5445 (match_op_dup 1 [(match_dup 2) (const_int 0)])
5449 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
5452 ;;- Multiply instructions.
5456 ; muldi3 instruction pattern(s).
5459 (define_insn "*muldi3_sign"
5460 [(set (match_operand:DI 0 "register_operand" "=d,d")
5461 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5462 (match_operand:DI 1 "register_operand" "0,0")))]
5467 [(set_attr "op_type" "RRE,RXY")
5468 (set_attr "type" "imuldi")])
5470 (define_insn "muldi3"
5471 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5472 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5473 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5480 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5481 (set_attr "type" "imuldi")
5482 (set_attr "cpu_facility" "*,*,*,z10")])
5485 ; mulsi3 instruction pattern(s).
5488 (define_insn "*mulsi3_sign"
5489 [(set (match_operand:SI 0 "register_operand" "=d,d")
5490 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5491 (match_operand:SI 1 "register_operand" "0,0")))]
5496 [(set_attr "op_type" "RX,RXY")
5497 (set_attr "type" "imulhi")
5498 (set_attr "cpu_facility" "*,z10")])
5500 (define_insn "mulsi3"
5501 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5502 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5503 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5511 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5512 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5513 (set_attr "cpu_facility" "*,*,*,*,z10")])
5516 ; mulsidi3 instruction pattern(s).
5519 (define_insn "mulsidi3"
5520 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5521 (mult:DI (sign_extend:DI
5522 (match_operand:SI 1 "register_operand" "%0,0,0"))
5524 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5530 [(set_attr "op_type" "RR,RX,RXY")
5531 (set_attr "type" "imulsi")
5532 (set_attr "cpu_facility" "*,*,z10")])
5535 ; umul instruction pattern(s).
5538 ; mlr, ml, mlgr, mlg
5539 (define_insn "umul<dwh><mode>3"
5540 [(set (match_operand:DW 0 "register_operand" "=d, d")
5541 (mult:DW (zero_extend:DW
5542 (match_operand:<DWH> 1 "register_operand" "%0, 0"))
5544 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
5549 [(set_attr "op_type" "RRE,RXY")
5550 (set_attr "type" "imul<dwh>")])
5553 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5556 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5557 (define_insn "mul<mode>3"
5558 [(set (match_operand:FP 0 "register_operand" "=f,f")
5559 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5560 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5563 m<xdee><bt>r\t%0,<op1>%2
5565 [(set_attr "op_type" "<RRer>,RXE")
5566 (set_attr "type" "fmul<mode>")])
5568 ; madbr, maebr, maxb, madb, maeb
5569 (define_insn "fma<mode>4"
5570 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5571 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5572 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5573 (match_operand:DSF 3 "register_operand" "0,0")))]
5578 [(set_attr "op_type" "RRE,RXE")
5579 (set_attr "type" "fmadd<mode>")])
5581 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5582 (define_insn "fms<mode>4"
5583 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5584 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
5585 (match_operand:DSF 2 "nonimmediate_operand" "f,R")
5586 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
5591 [(set_attr "op_type" "RRE,RXE")
5592 (set_attr "type" "fmadd<mode>")])
5595 ;;- Divide and modulo instructions.
5599 ; divmoddi4 instruction pattern(s).
5602 (define_expand "divmoddi4"
5603 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5604 (div:DI (match_operand:DI 1 "register_operand" "")
5605 (match_operand:DI 2 "general_operand" "")))
5606 (set (match_operand:DI 3 "general_operand" "")
5607 (mod:DI (match_dup 1) (match_dup 2)))])
5608 (clobber (match_dup 4))]
5611 rtx insn, div_equal, mod_equal;
5613 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5614 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5616 operands[4] = gen_reg_rtx(TImode);
5617 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5619 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5620 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5622 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5623 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5628 (define_insn "divmodtidi3"
5629 [(set (match_operand:TI 0 "register_operand" "=d,d")
5633 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5634 (match_operand:DI 2 "general_operand" "d,RT")))
5636 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5641 [(set_attr "op_type" "RRE,RXY")
5642 (set_attr "type" "idiv")])
5644 (define_insn "divmodtisi3"
5645 [(set (match_operand:TI 0 "register_operand" "=d,d")
5649 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5651 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5654 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5659 [(set_attr "op_type" "RRE,RXY")
5660 (set_attr "type" "idiv")])
5663 ; udivmoddi4 instruction pattern(s).
5666 (define_expand "udivmoddi4"
5667 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5668 (udiv:DI (match_operand:DI 1 "general_operand" "")
5669 (match_operand:DI 2 "nonimmediate_operand" "")))
5670 (set (match_operand:DI 3 "general_operand" "")
5671 (umod:DI (match_dup 1) (match_dup 2)))])
5672 (clobber (match_dup 4))]
5675 rtx insn, div_equal, mod_equal, equal;
5677 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5678 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5679 equal = gen_rtx_IOR (TImode,
5680 gen_rtx_ASHIFT (TImode,
5681 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5683 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5685 operands[4] = gen_reg_rtx(TImode);
5686 emit_clobber (operands[4]);
5687 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5688 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5690 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5691 set_unique_reg_note (insn, REG_EQUAL, equal);
5693 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5694 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5696 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5697 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5702 (define_insn "udivmodtidi3"
5703 [(set (match_operand:TI 0 "register_operand" "=d,d")
5708 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5710 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5714 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5719 [(set_attr "op_type" "RRE,RXY")
5720 (set_attr "type" "idiv")])
5723 ; divmodsi4 instruction pattern(s).
5726 (define_expand "divmodsi4"
5727 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5728 (div:SI (match_operand:SI 1 "general_operand" "")
5729 (match_operand:SI 2 "nonimmediate_operand" "")))
5730 (set (match_operand:SI 3 "general_operand" "")
5731 (mod:SI (match_dup 1) (match_dup 2)))])
5732 (clobber (match_dup 4))]
5735 rtx insn, div_equal, mod_equal, equal;
5737 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5738 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5739 equal = gen_rtx_IOR (DImode,
5740 gen_rtx_ASHIFT (DImode,
5741 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5743 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5745 operands[4] = gen_reg_rtx(DImode);
5746 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5748 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5749 set_unique_reg_note (insn, REG_EQUAL, equal);
5751 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5752 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5754 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5755 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5760 (define_insn "divmoddisi3"
5761 [(set (match_operand:DI 0 "register_operand" "=d,d")
5766 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5768 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5772 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5777 [(set_attr "op_type" "RR,RX")
5778 (set_attr "type" "idiv")])
5781 ; udivsi3 and umodsi3 instruction pattern(s).
5784 (define_expand "udivmodsi4"
5785 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5786 (udiv:SI (match_operand:SI 1 "general_operand" "")
5787 (match_operand:SI 2 "nonimmediate_operand" "")))
5788 (set (match_operand:SI 3 "general_operand" "")
5789 (umod:SI (match_dup 1) (match_dup 2)))])
5790 (clobber (match_dup 4))]
5791 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5793 rtx insn, div_equal, mod_equal, equal;
5795 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5796 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5797 equal = gen_rtx_IOR (DImode,
5798 gen_rtx_ASHIFT (DImode,
5799 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5801 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5803 operands[4] = gen_reg_rtx(DImode);
5804 emit_clobber (operands[4]);
5805 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5806 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5808 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5809 set_unique_reg_note (insn, REG_EQUAL, equal);
5811 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5812 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5814 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5815 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5820 (define_insn "udivmoddisi3"
5821 [(set (match_operand:DI 0 "register_operand" "=d,d")
5826 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5828 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5832 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5833 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5837 [(set_attr "op_type" "RRE,RXY")
5838 (set_attr "type" "idiv")])
5840 (define_expand "udivsi3"
5841 [(set (match_operand:SI 0 "register_operand" "=d")
5842 (udiv:SI (match_operand:SI 1 "general_operand" "")
5843 (match_operand:SI 2 "general_operand" "")))
5844 (clobber (match_dup 3))]
5845 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5847 rtx insn, udiv_equal, umod_equal, equal;
5849 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5850 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5851 equal = gen_rtx_IOR (DImode,
5852 gen_rtx_ASHIFT (DImode,
5853 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5855 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5857 operands[3] = gen_reg_rtx (DImode);
5859 if (CONSTANT_P (operands[2]))
5861 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5863 rtx label1 = gen_label_rtx ();
5865 operands[1] = make_safe_from (operands[1], operands[0]);
5866 emit_move_insn (operands[0], const0_rtx);
5867 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
5869 emit_move_insn (operands[0], const1_rtx);
5870 emit_label (label1);
5874 operands[2] = force_reg (SImode, operands[2]);
5875 operands[2] = make_safe_from (operands[2], operands[0]);
5877 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5878 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5880 set_unique_reg_note (insn, REG_EQUAL, equal);
5882 insn = emit_move_insn (operands[0],
5883 gen_lowpart (SImode, operands[3]));
5884 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5889 rtx label1 = gen_label_rtx ();
5890 rtx label2 = gen_label_rtx ();
5891 rtx label3 = gen_label_rtx ();
5893 operands[1] = force_reg (SImode, operands[1]);
5894 operands[1] = make_safe_from (operands[1], operands[0]);
5895 operands[2] = force_reg (SImode, operands[2]);
5896 operands[2] = make_safe_from (operands[2], operands[0]);
5898 emit_move_insn (operands[0], const0_rtx);
5899 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5901 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5903 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5905 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5906 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5908 set_unique_reg_note (insn, REG_EQUAL, equal);
5910 insn = emit_move_insn (operands[0],
5911 gen_lowpart (SImode, operands[3]));
5912 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5915 emit_label (label1);
5916 emit_move_insn (operands[0], operands[1]);
5918 emit_label (label2);
5919 emit_move_insn (operands[0], const1_rtx);
5920 emit_label (label3);
5922 emit_move_insn (operands[0], operands[0]);
5926 (define_expand "umodsi3"
5927 [(set (match_operand:SI 0 "register_operand" "=d")
5928 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5929 (match_operand:SI 2 "nonimmediate_operand" "")))
5930 (clobber (match_dup 3))]
5931 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
5933 rtx insn, udiv_equal, umod_equal, equal;
5935 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5936 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5937 equal = gen_rtx_IOR (DImode,
5938 gen_rtx_ASHIFT (DImode,
5939 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5941 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5943 operands[3] = gen_reg_rtx (DImode);
5945 if (CONSTANT_P (operands[2]))
5947 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5949 rtx label1 = gen_label_rtx ();
5951 operands[1] = make_safe_from (operands[1], operands[0]);
5952 emit_move_insn (operands[0], operands[1]);
5953 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
5955 emit_insn (gen_abssi2 (operands[0], operands[2]));
5956 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5957 emit_label (label1);
5961 operands[2] = force_reg (SImode, operands[2]);
5962 operands[2] = make_safe_from (operands[2], operands[0]);
5964 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5965 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5967 set_unique_reg_note (insn, REG_EQUAL, equal);
5969 insn = emit_move_insn (operands[0],
5970 gen_highpart (SImode, operands[3]));
5971 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5976 rtx label1 = gen_label_rtx ();
5977 rtx label2 = gen_label_rtx ();
5978 rtx label3 = gen_label_rtx ();
5980 operands[1] = force_reg (SImode, operands[1]);
5981 operands[1] = make_safe_from (operands[1], operands[0]);
5982 operands[2] = force_reg (SImode, operands[2]);
5983 operands[2] = make_safe_from (operands[2], operands[0]);
5985 emit_move_insn(operands[0], operands[1]);
5986 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
5988 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
5990 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
5992 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5993 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5995 set_unique_reg_note (insn, REG_EQUAL, equal);
5997 insn = emit_move_insn (operands[0],
5998 gen_highpart (SImode, operands[3]));
5999 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
6002 emit_label (label1);
6003 emit_move_insn (operands[0], const0_rtx);
6005 emit_label (label2);
6006 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
6007 emit_label (label3);
6013 ; div(df|sf)3 instruction pattern(s).
6016 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
6017 (define_insn "div<mode>3"
6018 [(set (match_operand:FP 0 "register_operand" "=f,f")
6019 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
6020 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
6023 d<xde><bt>r\t%0,<op1>%2
6025 [(set_attr "op_type" "<RRer>,RXE")
6026 (set_attr "type" "fdiv<mode>")])
6030 ;;- And instructions.
6033 (define_expand "and<mode>3"
6034 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6035 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
6036 (match_operand:INT 2 "general_operand" "")))
6037 (clobber (reg:CC CC_REGNUM))]
6039 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
6042 ; anddi3 instruction pattern(s).
6045 (define_insn "*anddi3_cc"
6046 [(set (reg CC_REGNUM)
6047 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6048 (match_operand:DI 2 "general_operand" " d,d,RT"))
6050 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6051 (and:DI (match_dup 1) (match_dup 2)))]
6052 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6057 [(set_attr "op_type" "RRE,RRF,RXY")
6058 (set_attr "cpu_facility" "*,z196,*")
6059 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6061 (define_insn "*anddi3_cconly"
6062 [(set (reg CC_REGNUM)
6063 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6064 (match_operand:DI 2 "general_operand" " d,d,RT"))
6066 (clobber (match_scratch:DI 0 "=d,d, d"))]
6067 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
6068 /* Do not steal TM patterns. */
6069 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
6074 [(set_attr "op_type" "RRE,RRF,RXY")
6075 (set_attr "cpu_facility" "*,z196,*")
6076 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6078 (define_insn "*anddi3"
6079 [(set (match_operand:DI 0 "nonimmediate_operand"
6080 "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
6081 (and:DI (match_operand:DI 1 "nonimmediate_operand"
6082 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6083 (match_operand:DI 2 "general_operand"
6084 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
6085 (clobber (reg:CC CC_REGNUM))]
6086 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6101 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6102 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
6103 (set_attr "z10prop" "*,
6118 [(set (match_operand:DI 0 "s_operand" "")
6119 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6120 (clobber (reg:CC CC_REGNUM))]
6123 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6124 (clobber (reg:CC CC_REGNUM))])]
6125 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6129 ; andsi3 instruction pattern(s).
6132 (define_insn "*andsi3_cc"
6133 [(set (reg CC_REGNUM)
6134 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6135 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6137 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6138 (and:SI (match_dup 1) (match_dup 2)))]
6139 "s390_match_ccmode(insn, CCTmode)"
6146 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6147 (set_attr "cpu_facility" "*,*,z196,*,*")
6148 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6150 (define_insn "*andsi3_cconly"
6151 [(set (reg CC_REGNUM)
6152 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6153 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6155 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6156 "s390_match_ccmode(insn, CCTmode)
6157 /* Do not steal TM patterns. */
6158 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
6165 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6166 (set_attr "cpu_facility" "*,*,z196,*,*")
6167 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6168 z10_super_E1,z10_super_E1")])
6170 (define_insn "*andsi3_zarch"
6171 [(set (match_operand:SI 0 "nonimmediate_operand"
6172 "=d,d, d, d, d,d,d,d,d, AQ,Q")
6173 (and:SI (match_operand:SI 1 "nonimmediate_operand"
6174 "%d,o, 0, 0, 0,0,d,0,0, 0,0")
6175 (match_operand:SI 2 "general_operand"
6176 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
6177 (clobber (reg:CC CC_REGNUM))]
6178 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6191 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6192 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
6193 (set_attr "z10prop" "*,
6205 (define_insn "*andsi3_esa"
6206 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
6207 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
6208 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
6209 (clobber (reg:CC CC_REGNUM))]
6210 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6216 [(set_attr "op_type" "RR,RX,SI,SS")
6217 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6221 [(set (match_operand:SI 0 "s_operand" "")
6222 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6223 (clobber (reg:CC CC_REGNUM))]
6226 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6227 (clobber (reg:CC CC_REGNUM))])]
6228 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6231 ; andhi3 instruction pattern(s).
6234 (define_insn "*andhi3_zarch"
6235 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6236 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6237 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
6238 (clobber (reg:CC CC_REGNUM))]
6239 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6246 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6247 (set_attr "cpu_facility" "*,z196,*,*,*")
6248 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
6251 (define_insn "*andhi3_esa"
6252 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6253 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6254 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
6255 (clobber (reg:CC CC_REGNUM))]
6256 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6261 [(set_attr "op_type" "RR,SI,SS")
6262 (set_attr "z10prop" "z10_super_E1,*,*")
6266 [(set (match_operand:HI 0 "s_operand" "")
6267 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6268 (clobber (reg:CC CC_REGNUM))]
6271 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
6272 (clobber (reg:CC CC_REGNUM))])]
6273 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
6276 ; andqi3 instruction pattern(s).
6279 (define_insn "*andqi3_zarch"
6280 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6281 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6282 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6283 (clobber (reg:CC CC_REGNUM))]
6284 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6292 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6293 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6294 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
6296 (define_insn "*andqi3_esa"
6297 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6298 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6299 (match_operand:QI 2 "general_operand" "d,n,Q")))
6300 (clobber (reg:CC CC_REGNUM))]
6301 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6306 [(set_attr "op_type" "RR,SI,SS")
6307 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6310 ; Block and (NC) patterns.
6314 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6315 (and:BLK (match_dup 0)
6316 (match_operand:BLK 1 "memory_operand" "Q")))
6317 (use (match_operand 2 "const_int_operand" "n"))
6318 (clobber (reg:CC CC_REGNUM))]
6319 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6320 "nc\t%O0(%2,%R0),%S1"
6321 [(set_attr "op_type" "SS")
6322 (set_attr "z196prop" "z196_cracked")])
6325 [(set (match_operand 0 "memory_operand" "")
6327 (match_operand 1 "memory_operand" "")))
6328 (clobber (reg:CC CC_REGNUM))]
6330 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6331 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6333 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6335 (clobber (reg:CC CC_REGNUM))])]
6337 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6338 operands[0] = adjust_address (operands[0], BLKmode, 0);
6339 operands[1] = adjust_address (operands[1], BLKmode, 0);
6344 [(set (match_operand:BLK 0 "memory_operand" "")
6345 (and:BLK (match_dup 0)
6346 (match_operand:BLK 1 "memory_operand" "")))
6347 (use (match_operand 2 "const_int_operand" ""))
6348 (clobber (reg:CC CC_REGNUM))])
6350 [(set (match_operand:BLK 3 "memory_operand" "")
6351 (and:BLK (match_dup 3)
6352 (match_operand:BLK 4 "memory_operand" "")))
6353 (use (match_operand 5 "const_int_operand" ""))
6354 (clobber (reg:CC CC_REGNUM))])]
6355 "s390_offset_p (operands[0], operands[3], operands[2])
6356 && s390_offset_p (operands[1], operands[4], operands[2])
6357 && !s390_overlap_p (operands[0], operands[1],
6358 INTVAL (operands[2]) + INTVAL (operands[5]))
6359 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6361 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6363 (clobber (reg:CC CC_REGNUM))])]
6364 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6365 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6366 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6370 ;;- Bit set (inclusive or) instructions.
6373 (define_expand "ior<mode>3"
6374 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6375 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6376 (match_operand:INT 2 "general_operand" "")))
6377 (clobber (reg:CC CC_REGNUM))]
6379 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6382 ; iordi3 instruction pattern(s).
6385 (define_insn "*iordi3_cc"
6386 [(set (reg CC_REGNUM)
6387 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6388 (match_operand:DI 2 "general_operand" " d,d,RT"))
6390 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6391 (ior:DI (match_dup 1) (match_dup 2)))]
6392 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6397 [(set_attr "op_type" "RRE,RRF,RXY")
6398 (set_attr "cpu_facility" "*,z196,*")
6399 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6401 (define_insn "*iordi3_cconly"
6402 [(set (reg CC_REGNUM)
6403 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
6404 (match_operand:DI 2 "general_operand" " d,d,RT"))
6406 (clobber (match_scratch:DI 0 "=d,d,d"))]
6407 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6412 [(set_attr "op_type" "RRE,RRF,RXY")
6413 (set_attr "cpu_facility" "*,z196,*")
6414 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6416 (define_insn "*iordi3"
6417 [(set (match_operand:DI 0 "nonimmediate_operand"
6418 "=d, d, d, d, d, d,d,d, d, AQ,Q")
6419 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
6420 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
6421 (match_operand:DI 2 "general_operand"
6422 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6423 (clobber (reg:CC CC_REGNUM))]
6424 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6437 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
6438 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
6439 (set_attr "z10prop" "z10_super_E1,
6452 [(set (match_operand:DI 0 "s_operand" "")
6453 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6454 (clobber (reg:CC CC_REGNUM))]
6457 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6458 (clobber (reg:CC CC_REGNUM))])]
6459 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6462 ; iorsi3 instruction pattern(s).
6465 (define_insn "*iorsi3_cc"
6466 [(set (reg CC_REGNUM)
6467 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6468 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6470 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6471 (ior:SI (match_dup 1) (match_dup 2)))]
6472 "s390_match_ccmode(insn, CCTmode)"
6479 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6480 (set_attr "cpu_facility" "*,*,z196,*,*")
6481 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6483 (define_insn "*iorsi3_cconly"
6484 [(set (reg CC_REGNUM)
6485 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6486 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6488 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6489 "s390_match_ccmode(insn, CCTmode)"
6496 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6497 (set_attr "cpu_facility" "*,*,z196,*,*")
6498 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
6500 (define_insn "*iorsi3_zarch"
6501 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
6502 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
6503 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
6504 (clobber (reg:CC CC_REGNUM))]
6505 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6516 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
6517 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
6518 (set_attr "z10prop" "z10_super_E1,
6528 (define_insn "*iorsi3_esa"
6529 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6530 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6531 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6532 (clobber (reg:CC CC_REGNUM))]
6533 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6539 [(set_attr "op_type" "RR,RX,SI,SS")
6540 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6543 [(set (match_operand:SI 0 "s_operand" "")
6544 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6545 (clobber (reg:CC CC_REGNUM))]
6548 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6549 (clobber (reg:CC CC_REGNUM))])]
6550 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6553 ; iorhi3 instruction pattern(s).
6556 (define_insn "*iorhi3_zarch"
6557 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6558 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
6559 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
6560 (clobber (reg:CC CC_REGNUM))]
6561 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6568 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
6569 (set_attr "cpu_facility" "*,z196,*,*,*")
6570 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
6572 (define_insn "*iorhi3_esa"
6573 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6574 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6575 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6576 (clobber (reg:CC CC_REGNUM))]
6577 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6582 [(set_attr "op_type" "RR,SI,SS")
6583 (set_attr "z10prop" "z10_super_E1,*,*")])
6586 [(set (match_operand:HI 0 "s_operand" "")
6587 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6588 (clobber (reg:CC CC_REGNUM))]
6591 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6592 (clobber (reg:CC CC_REGNUM))])]
6593 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6596 ; iorqi3 instruction pattern(s).
6599 (define_insn "*iorqi3_zarch"
6600 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6601 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6602 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
6603 (clobber (reg:CC CC_REGNUM))]
6604 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6612 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
6613 (set_attr "cpu_facility" "*,z196,*,*,*,*")
6614 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
6615 z10_super,z10_super,*")])
6617 (define_insn "*iorqi3_esa"
6618 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6619 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6620 (match_operand:QI 2 "general_operand" "d,n,Q")))
6621 (clobber (reg:CC CC_REGNUM))]
6622 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6627 [(set_attr "op_type" "RR,SI,SS")
6628 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6631 ; Block inclusive or (OC) patterns.
6635 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6636 (ior:BLK (match_dup 0)
6637 (match_operand:BLK 1 "memory_operand" "Q")))
6638 (use (match_operand 2 "const_int_operand" "n"))
6639 (clobber (reg:CC CC_REGNUM))]
6640 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6641 "oc\t%O0(%2,%R0),%S1"
6642 [(set_attr "op_type" "SS")
6643 (set_attr "z196prop" "z196_cracked")])
6646 [(set (match_operand 0 "memory_operand" "")
6648 (match_operand 1 "memory_operand" "")))
6649 (clobber (reg:CC CC_REGNUM))]
6651 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6652 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6654 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6656 (clobber (reg:CC CC_REGNUM))])]
6658 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6659 operands[0] = adjust_address (operands[0], BLKmode, 0);
6660 operands[1] = adjust_address (operands[1], BLKmode, 0);
6665 [(set (match_operand:BLK 0 "memory_operand" "")
6666 (ior:BLK (match_dup 0)
6667 (match_operand:BLK 1 "memory_operand" "")))
6668 (use (match_operand 2 "const_int_operand" ""))
6669 (clobber (reg:CC CC_REGNUM))])
6671 [(set (match_operand:BLK 3 "memory_operand" "")
6672 (ior:BLK (match_dup 3)
6673 (match_operand:BLK 4 "memory_operand" "")))
6674 (use (match_operand 5 "const_int_operand" ""))
6675 (clobber (reg:CC CC_REGNUM))])]
6676 "s390_offset_p (operands[0], operands[3], operands[2])
6677 && s390_offset_p (operands[1], operands[4], operands[2])
6678 && !s390_overlap_p (operands[0], operands[1],
6679 INTVAL (operands[2]) + INTVAL (operands[5]))
6680 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6682 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6684 (clobber (reg:CC CC_REGNUM))])]
6685 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6686 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6687 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6691 ;;- Xor instructions.
6694 (define_expand "xor<mode>3"
6695 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6696 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6697 (match_operand:INT 2 "general_operand" "")))
6698 (clobber (reg:CC CC_REGNUM))]
6700 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6703 ; xordi3 instruction pattern(s).
6706 (define_insn "*xordi3_cc"
6707 [(set (reg CC_REGNUM)
6708 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6709 (match_operand:DI 2 "general_operand" " d,d,RT"))
6711 (set (match_operand:DI 0 "register_operand" "=d,d, d")
6712 (xor:DI (match_dup 1) (match_dup 2)))]
6713 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6718 [(set_attr "op_type" "RRE,RRF,RXY")
6719 (set_attr "cpu_facility" "*,z196,*")
6720 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6722 (define_insn "*xordi3_cconly"
6723 [(set (reg CC_REGNUM)
6724 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
6725 (match_operand:DI 2 "general_operand" " d,d,RT"))
6727 (clobber (match_scratch:DI 0 "=d,d, d"))]
6728 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
6733 [(set_attr "op_type" "RRE,RRF,RXY")
6734 (set_attr "cpu_facility" "*,z196,*")
6735 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
6737 (define_insn "*xordi3"
6738 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
6739 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
6740 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
6741 (clobber (reg:CC CC_REGNUM))]
6742 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6751 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
6752 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
6753 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
6754 *,z10_super_E1,*,*")])
6757 [(set (match_operand:DI 0 "s_operand" "")
6758 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6759 (clobber (reg:CC CC_REGNUM))]
6762 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6763 (clobber (reg:CC CC_REGNUM))])]
6764 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6767 ; xorsi3 instruction pattern(s).
6770 (define_insn "*xorsi3_cc"
6771 [(set (reg CC_REGNUM)
6772 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6773 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6775 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
6776 (xor:SI (match_dup 1) (match_dup 2)))]
6777 "s390_match_ccmode(insn, CCTmode)"
6784 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6785 (set_attr "cpu_facility" "*,*,z196,*,*")
6786 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6787 z10_super_E1,z10_super_E1")])
6789 (define_insn "*xorsi3_cconly"
6790 [(set (reg CC_REGNUM)
6791 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
6792 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
6794 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
6795 "s390_match_ccmode(insn, CCTmode)"
6802 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
6803 (set_attr "cpu_facility" "*,*,z196,*,*")
6804 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6805 z10_super_E1,z10_super_E1")])
6807 (define_insn "*xorsi3"
6808 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
6809 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
6810 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
6811 (clobber (reg:CC CC_REGNUM))]
6812 "s390_logical_operator_ok_p (operands)"
6821 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
6822 (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
6823 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
6824 z10_super_E1,z10_super_E1,*,*")])
6827 [(set (match_operand:SI 0 "s_operand" "")
6828 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6829 (clobber (reg:CC CC_REGNUM))]
6832 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6833 (clobber (reg:CC CC_REGNUM))])]
6834 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6837 ; xorhi3 instruction pattern(s).
6840 (define_insn "*xorhi3"
6841 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
6842 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
6843 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
6844 (clobber (reg:CC CC_REGNUM))]
6845 "s390_logical_operator_ok_p (operands)"
6852 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
6853 (set_attr "cpu_facility" "*,*,z196,*,*")
6854 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
6857 [(set (match_operand:HI 0 "s_operand" "")
6858 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6859 (clobber (reg:CC CC_REGNUM))]
6862 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6863 (clobber (reg:CC CC_REGNUM))])]
6864 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6867 ; xorqi3 instruction pattern(s).
6870 (define_insn "*xorqi3"
6871 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
6872 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
6873 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
6874 (clobber (reg:CC CC_REGNUM))]
6875 "s390_logical_operator_ok_p (operands)"
6883 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
6884 (set_attr "cpu_facility" "*,*,z196,*,*,*")
6885 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
6889 ; Block exclusive or (XC) patterns.
6893 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6894 (xor:BLK (match_dup 0)
6895 (match_operand:BLK 1 "memory_operand" "Q")))
6896 (use (match_operand 2 "const_int_operand" "n"))
6897 (clobber (reg:CC CC_REGNUM))]
6898 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6899 "xc\t%O0(%2,%R0),%S1"
6900 [(set_attr "op_type" "SS")])
6903 [(set (match_operand 0 "memory_operand" "")
6905 (match_operand 1 "memory_operand" "")))
6906 (clobber (reg:CC CC_REGNUM))]
6908 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6909 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6911 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6913 (clobber (reg:CC CC_REGNUM))])]
6915 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6916 operands[0] = adjust_address (operands[0], BLKmode, 0);
6917 operands[1] = adjust_address (operands[1], BLKmode, 0);
6922 [(set (match_operand:BLK 0 "memory_operand" "")
6923 (xor:BLK (match_dup 0)
6924 (match_operand:BLK 1 "memory_operand" "")))
6925 (use (match_operand 2 "const_int_operand" ""))
6926 (clobber (reg:CC CC_REGNUM))])
6928 [(set (match_operand:BLK 3 "memory_operand" "")
6929 (xor:BLK (match_dup 3)
6930 (match_operand:BLK 4 "memory_operand" "")))
6931 (use (match_operand 5 "const_int_operand" ""))
6932 (clobber (reg:CC CC_REGNUM))])]
6933 "s390_offset_p (operands[0], operands[3], operands[2])
6934 && s390_offset_p (operands[1], operands[4], operands[2])
6935 && !s390_overlap_p (operands[0], operands[1],
6936 INTVAL (operands[2]) + INTVAL (operands[5]))
6937 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6939 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6941 (clobber (reg:CC CC_REGNUM))])]
6942 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6943 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6944 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6947 ; Block xor (XC) patterns with src == dest.
6950 (define_insn "*xc_zero"
6951 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6953 (use (match_operand 1 "const_int_operand" "n"))
6954 (clobber (reg:CC CC_REGNUM))]
6955 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6956 "xc\t%O0(%1,%R0),%S0"
6957 [(set_attr "op_type" "SS")
6958 (set_attr "z196prop" "z196_cracked")])
6962 [(set (match_operand:BLK 0 "memory_operand" "")
6964 (use (match_operand 1 "const_int_operand" ""))
6965 (clobber (reg:CC CC_REGNUM))])
6967 [(set (match_operand:BLK 2 "memory_operand" "")
6969 (use (match_operand 3 "const_int_operand" ""))
6970 (clobber (reg:CC CC_REGNUM))])]
6971 "s390_offset_p (operands[0], operands[2], operands[1])
6972 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6974 [(set (match_dup 4) (const_int 0))
6976 (clobber (reg:CC CC_REGNUM))])]
6977 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6978 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6982 ;;- Negate instructions.
6986 ; neg(di|si)2 instruction pattern(s).
6989 (define_expand "neg<mode>2"
6991 [(set (match_operand:DSI 0 "register_operand" "=d")
6992 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6993 (clobber (reg:CC CC_REGNUM))])]
6997 (define_insn "*negdi2_sign_cc"
6998 [(set (reg CC_REGNUM)
6999 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
7000 (match_operand:SI 1 "register_operand" "d") 0)
7001 (const_int 32)) (const_int 32)))
7003 (set (match_operand:DI 0 "register_operand" "=d")
7004 (neg:DI (sign_extend:DI (match_dup 1))))]
7005 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7007 [(set_attr "op_type" "RRE")
7008 (set_attr "z10prop" "z10_c")])
7010 (define_insn "*negdi2_sign"
7011 [(set (match_operand:DI 0 "register_operand" "=d")
7012 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7013 (clobber (reg:CC CC_REGNUM))]
7016 [(set_attr "op_type" "RRE")
7017 (set_attr "z10prop" "z10_c")])
7020 (define_insn "*neg<mode>2_cc"
7021 [(set (reg CC_REGNUM)
7022 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7024 (set (match_operand:GPR 0 "register_operand" "=d")
7025 (neg:GPR (match_dup 1)))]
7026 "s390_match_ccmode (insn, CCAmode)"
7028 [(set_attr "op_type" "RR<E>")
7029 (set_attr "z10prop" "z10_super_c_E1")])
7032 (define_insn "*neg<mode>2_cconly"
7033 [(set (reg CC_REGNUM)
7034 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
7036 (clobber (match_scratch:GPR 0 "=d"))]
7037 "s390_match_ccmode (insn, CCAmode)"
7039 [(set_attr "op_type" "RR<E>")
7040 (set_attr "z10prop" "z10_super_c_E1")])
7043 (define_insn "*neg<mode>2"
7044 [(set (match_operand:GPR 0 "register_operand" "=d")
7045 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
7046 (clobber (reg:CC CC_REGNUM))]
7049 [(set_attr "op_type" "RR<E>")
7050 (set_attr "z10prop" "z10_super_c_E1")])
7052 (define_insn_and_split "*negdi2_31"
7053 [(set (match_operand:DI 0 "register_operand" "=d")
7054 (neg:DI (match_operand:DI 1 "register_operand" "d")))
7055 (clobber (reg:CC CC_REGNUM))]
7058 "&& reload_completed"
7060 [(set (match_dup 2) (neg:SI (match_dup 3)))
7061 (clobber (reg:CC CC_REGNUM))])
7063 [(set (reg:CCAP CC_REGNUM)
7064 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
7065 (set (match_dup 4) (neg:SI (match_dup 5)))])
7067 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
7069 (label_ref (match_dup 6))))
7071 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
7072 (clobber (reg:CC CC_REGNUM))])
7074 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
7075 operands[3] = operand_subword (operands[1], 0, 0, DImode);
7076 operands[4] = operand_subword (operands[0], 1, 0, DImode);
7077 operands[5] = operand_subword (operands[1], 1, 0, DImode);
7078 operands[6] = gen_label_rtx ();")
7081 ; neg(df|sf)2 instruction pattern(s).
7084 (define_expand "neg<mode>2"
7086 [(set (match_operand:BFP 0 "register_operand" "=f")
7087 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7088 (clobber (reg:CC CC_REGNUM))])]
7092 ; lcxbr, lcdbr, lcebr
7093 (define_insn "*neg<mode>2_cc"
7094 [(set (reg CC_REGNUM)
7095 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7096 (match_operand:BFP 2 "const0_operand" "")))
7097 (set (match_operand:BFP 0 "register_operand" "=f")
7098 (neg:BFP (match_dup 1)))]
7099 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7101 [(set_attr "op_type" "RRE")
7102 (set_attr "type" "fsimp<mode>")])
7104 ; lcxbr, lcdbr, lcebr
7105 (define_insn "*neg<mode>2_cconly"
7106 [(set (reg CC_REGNUM)
7107 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
7108 (match_operand:BFP 2 "const0_operand" "")))
7109 (clobber (match_scratch:BFP 0 "=f"))]
7110 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7112 [(set_attr "op_type" "RRE")
7113 (set_attr "type" "fsimp<mode>")])
7116 (define_insn "*neg<mode>2_nocc"
7117 [(set (match_operand:FP 0 "register_operand" "=f")
7118 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7121 [(set_attr "op_type" "RRE")
7122 (set_attr "type" "fsimp<mode>")])
7124 ; lcxbr, lcdbr, lcebr
7125 (define_insn "*neg<mode>2"
7126 [(set (match_operand:BFP 0 "register_operand" "=f")
7127 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
7128 (clobber (reg:CC CC_REGNUM))]
7131 [(set_attr "op_type" "RRE")
7132 (set_attr "type" "fsimp<mode>")])
7136 ;;- Absolute value instructions.
7140 ; abs(di|si)2 instruction pattern(s).
7143 (define_insn "*absdi2_sign_cc"
7144 [(set (reg CC_REGNUM)
7145 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7146 (match_operand:SI 1 "register_operand" "d") 0)
7147 (const_int 32)) (const_int 32)))
7149 (set (match_operand:DI 0 "register_operand" "=d")
7150 (abs:DI (sign_extend:DI (match_dup 1))))]
7151 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7153 [(set_attr "op_type" "RRE")
7154 (set_attr "z10prop" "z10_c")])
7156 (define_insn "*absdi2_sign"
7157 [(set (match_operand:DI 0 "register_operand" "=d")
7158 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
7159 (clobber (reg:CC CC_REGNUM))]
7162 [(set_attr "op_type" "RRE")
7163 (set_attr "z10prop" "z10_c")])
7166 (define_insn "*abs<mode>2_cc"
7167 [(set (reg CC_REGNUM)
7168 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
7170 (set (match_operand:GPR 0 "register_operand" "=d")
7171 (abs:GPR (match_dup 1)))]
7172 "s390_match_ccmode (insn, CCAmode)"
7174 [(set_attr "op_type" "RR<E>")
7175 (set_attr "z10prop" "z10_c")])
7178 (define_insn "*abs<mode>2_cconly"
7179 [(set (reg CC_REGNUM)
7180 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
7182 (clobber (match_scratch:GPR 0 "=d"))]
7183 "s390_match_ccmode (insn, CCAmode)"
7185 [(set_attr "op_type" "RR<E>")
7186 (set_attr "z10prop" "z10_c")])
7189 (define_insn "abs<mode>2"
7190 [(set (match_operand:GPR 0 "register_operand" "=d")
7191 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7192 (clobber (reg:CC CC_REGNUM))]
7195 [(set_attr "op_type" "RR<E>")
7196 (set_attr "z10prop" "z10_c")])
7199 ; abs(df|sf)2 instruction pattern(s).
7202 (define_expand "abs<mode>2"
7204 [(set (match_operand:BFP 0 "register_operand" "=f")
7205 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7206 (clobber (reg:CC CC_REGNUM))])]
7210 ; lpxbr, lpdbr, lpebr
7211 (define_insn "*abs<mode>2_cc"
7212 [(set (reg CC_REGNUM)
7213 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7214 (match_operand:BFP 2 "const0_operand" "")))
7215 (set (match_operand:BFP 0 "register_operand" "=f")
7216 (abs:BFP (match_dup 1)))]
7217 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7219 [(set_attr "op_type" "RRE")
7220 (set_attr "type" "fsimp<mode>")])
7222 ; lpxbr, lpdbr, lpebr
7223 (define_insn "*abs<mode>2_cconly"
7224 [(set (reg CC_REGNUM)
7225 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
7226 (match_operand:BFP 2 "const0_operand" "")))
7227 (clobber (match_scratch:BFP 0 "=f"))]
7228 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7230 [(set_attr "op_type" "RRE")
7231 (set_attr "type" "fsimp<mode>")])
7234 (define_insn "*abs<mode>2_nocc"
7235 [(set (match_operand:FP 0 "register_operand" "=f")
7236 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
7239 [(set_attr "op_type" "RRE")
7240 (set_attr "type" "fsimp<mode>")])
7242 ; lpxbr, lpdbr, lpebr
7243 (define_insn "*abs<mode>2"
7244 [(set (match_operand:BFP 0 "register_operand" "=f")
7245 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7246 (clobber (reg:CC CC_REGNUM))]
7249 [(set_attr "op_type" "RRE")
7250 (set_attr "type" "fsimp<mode>")])
7254 ;;- Negated absolute value instructions
7261 (define_insn "*negabsdi2_sign_cc"
7262 [(set (reg CC_REGNUM)
7263 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
7264 (match_operand:SI 1 "register_operand" "d") 0)
7265 (const_int 32)) (const_int 32))))
7267 (set (match_operand:DI 0 "register_operand" "=d")
7268 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
7269 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
7271 [(set_attr "op_type" "RRE")
7272 (set_attr "z10prop" "z10_c")])
7274 (define_insn "*negabsdi2_sign"
7275 [(set (match_operand:DI 0 "register_operand" "=d")
7276 (neg:DI (abs:DI (sign_extend:DI
7277 (match_operand:SI 1 "register_operand" "d")))))
7278 (clobber (reg:CC CC_REGNUM))]
7281 [(set_attr "op_type" "RRE")
7282 (set_attr "z10prop" "z10_c")])
7285 (define_insn "*negabs<mode>2_cc"
7286 [(set (reg CC_REGNUM)
7287 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7289 (set (match_operand:GPR 0 "register_operand" "=d")
7290 (neg:GPR (abs:GPR (match_dup 1))))]
7291 "s390_match_ccmode (insn, CCAmode)"
7293 [(set_attr "op_type" "RR<E>")
7294 (set_attr "z10prop" "z10_c")])
7297 (define_insn "*negabs<mode>2_cconly"
7298 [(set (reg CC_REGNUM)
7299 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
7301 (clobber (match_scratch:GPR 0 "=d"))]
7302 "s390_match_ccmode (insn, CCAmode)"
7304 [(set_attr "op_type" "RR<E>")
7305 (set_attr "z10prop" "z10_c")])
7308 (define_insn "*negabs<mode>2"
7309 [(set (match_operand:GPR 0 "register_operand" "=d")
7310 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
7311 (clobber (reg:CC CC_REGNUM))]
7314 [(set_attr "op_type" "RR<E>")
7315 (set_attr "z10prop" "z10_c")])
7321 ; lnxbr, lndbr, lnebr
7322 (define_insn "*negabs<mode>2_cc"
7323 [(set (reg CC_REGNUM)
7324 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7325 (match_operand:BFP 2 "const0_operand" "")))
7326 (set (match_operand:BFP 0 "register_operand" "=f")
7327 (neg:BFP (abs:BFP (match_dup 1))))]
7328 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7330 [(set_attr "op_type" "RRE")
7331 (set_attr "type" "fsimp<mode>")])
7333 ; lnxbr, lndbr, lnebr
7334 (define_insn "*negabs<mode>2_cconly"
7335 [(set (reg CC_REGNUM)
7336 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
7337 (match_operand:BFP 2 "const0_operand" "")))
7338 (clobber (match_scratch:BFP 0 "=f"))]
7339 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
7341 [(set_attr "op_type" "RRE")
7342 (set_attr "type" "fsimp<mode>")])
7345 (define_insn "*negabs<mode>2_nocc"
7346 [(set (match_operand:FP 0 "register_operand" "=f")
7347 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
7350 [(set_attr "op_type" "RRE")
7351 (set_attr "type" "fsimp<mode>")])
7353 ; lnxbr, lndbr, lnebr
7354 (define_insn "*negabs<mode>2"
7355 [(set (match_operand:BFP 0 "register_operand" "=f")
7356 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
7357 (clobber (reg:CC CC_REGNUM))]
7360 [(set_attr "op_type" "RRE")
7361 (set_attr "type" "fsimp<mode>")])
7364 ;;- Square root instructions.
7368 ; sqrt(df|sf)2 instruction pattern(s).
7371 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7372 (define_insn "sqrt<mode>2"
7373 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7374 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7379 [(set_attr "op_type" "RRE,RXE")
7380 (set_attr "type" "fsqrt<mode>")])
7384 ;;- One complement instructions.
7388 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7391 (define_expand "one_cmpl<mode>2"
7393 [(set (match_operand:INT 0 "register_operand" "")
7394 (xor:INT (match_operand:INT 1 "register_operand" "")
7396 (clobber (reg:CC CC_REGNUM))])]
7402 ;; Find leftmost bit instructions.
7405 (define_expand "clzdi2"
7406 [(set (match_operand:DI 0 "register_operand" "=d")
7407 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7408 "TARGET_EXTIMM && TARGET_ZARCH"
7410 rtx insn, clz_equal;
7411 rtx wide_reg = gen_reg_rtx (TImode);
7412 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7414 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7416 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7418 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7419 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7424 (define_insn "clztidi2"
7425 [(set (match_operand:TI 0 "register_operand" "=d")
7429 (xor:DI (match_operand:DI 1 "register_operand" "d")
7430 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7431 (subreg:SI (clz:DI (match_dup 1)) 4))))
7434 (zero_extend:TI (clz:DI (match_dup 1)))))
7435 (clobber (reg:CC CC_REGNUM))]
7436 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7437 == (unsigned HOST_WIDE_INT) 1 << 63
7438 && TARGET_EXTIMM && TARGET_ZARCH"
7440 [(set_attr "op_type" "RRE")])
7444 ;;- Rotate instructions.
7448 ; rotl(di|si)3 instruction pattern(s).
7452 (define_insn "rotl<mode>3"
7453 [(set (match_operand:GPR 0 "register_operand" "=d")
7454 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7455 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7458 [(set_attr "op_type" "RSE")
7459 (set_attr "atype" "reg")
7460 (set_attr "z10prop" "z10_super_E1")])
7463 (define_insn "*rotl<mode>3_and"
7464 [(set (match_operand:GPR 0 "register_operand" "=d")
7465 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7466 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7467 (match_operand:SI 3 "const_int_operand" "n"))))]
7468 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7470 [(set_attr "op_type" "RSE")
7471 (set_attr "atype" "reg")
7472 (set_attr "z10prop" "z10_super_E1")])
7476 ;;- Shift instructions.
7480 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7481 ; Left shifts and logical right shifts
7483 (define_expand "<shift><mode>3"
7484 [(set (match_operand:DSI 0 "register_operand" "")
7485 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7486 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7491 (define_insn "*<shift>di3_31"
7492 [(set (match_operand:DI 0 "register_operand" "=d")
7493 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7494 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7497 [(set_attr "op_type" "RS")
7498 (set_attr "atype" "reg")
7499 (set_attr "z196prop" "z196_cracked")])
7501 ; sll, srl, sllg, srlg, sllk, srlk
7502 (define_insn "*<shift><mode>3"
7503 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7504 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7505 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
7508 s<lr>l<g>\t%0,<1>%Y2
7509 s<lr>l<gk>\t%0,%1,%Y2"
7510 [(set_attr "op_type" "RS<E>,RSY")
7511 (set_attr "atype" "reg,reg")
7512 (set_attr "cpu_facility" "*,z196")
7513 (set_attr "z10prop" "z10_super_E1,*")])
7516 (define_insn "*<shift>di3_31_and"
7517 [(set (match_operand:DI 0 "register_operand" "=d")
7518 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7519 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7520 (match_operand:SI 3 "const_int_operand" "n"))))]
7521 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7523 [(set_attr "op_type" "RS")
7524 (set_attr "atype" "reg")])
7526 ; sll, srl, sllg, srlg, sllk, srlk
7527 (define_insn "*<shift><mode>3_and"
7528 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7529 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7530 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7531 (match_operand:SI 3 "const_int_operand" "n,n"))))]
7532 "(INTVAL (operands[3]) & 63) == 63"
7534 s<lr>l<g>\t%0,<1>%Y2
7535 s<lr>l<gk>\t%0,%1,%Y2"
7536 [(set_attr "op_type" "RS<E>,RSY")
7537 (set_attr "atype" "reg,reg")
7538 (set_attr "cpu_facility" "*,z196")
7539 (set_attr "z10prop" "z10_super_E1,*")])
7542 ; ashr(di|si)3 instruction pattern(s).
7543 ; Arithmetic right shifts
7545 (define_expand "ashr<mode>3"
7547 [(set (match_operand:DSI 0 "register_operand" "")
7548 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7549 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7550 (clobber (reg:CC CC_REGNUM))])]
7554 (define_insn "*ashrdi3_cc_31"
7555 [(set (reg CC_REGNUM)
7556 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7557 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7559 (set (match_operand:DI 0 "register_operand" "=d")
7560 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7561 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7563 [(set_attr "op_type" "RS")
7564 (set_attr "atype" "reg")])
7566 (define_insn "*ashrdi3_cconly_31"
7567 [(set (reg CC_REGNUM)
7568 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7569 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7571 (clobber (match_scratch:DI 0 "=d"))]
7572 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
7574 [(set_attr "op_type" "RS")
7575 (set_attr "atype" "reg")])
7577 (define_insn "*ashrdi3_31"
7578 [(set (match_operand:DI 0 "register_operand" "=d")
7579 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7580 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7581 (clobber (reg:CC CC_REGNUM))]
7584 [(set_attr "op_type" "RS")
7585 (set_attr "atype" "reg")])
7588 (define_insn "*ashr<mode>3_cc"
7589 [(set (reg CC_REGNUM)
7590 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7591 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7593 (set (match_operand:GPR 0 "register_operand" "=d,d")
7594 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7595 "s390_match_ccmode(insn, CCSmode)"
7599 [(set_attr "op_type" "RS<E>,RSY")
7600 (set_attr "atype" "reg,reg")
7601 (set_attr "cpu_facility" "*,z196")
7602 (set_attr "z10prop" "z10_super_E1,*")])
7605 (define_insn "*ashr<mode>3_cconly"
7606 [(set (reg CC_REGNUM)
7607 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7608 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
7610 (clobber (match_scratch:GPR 0 "=d,d"))]
7611 "s390_match_ccmode(insn, CCSmode)"
7615 [(set_attr "op_type" "RS<E>,RSY")
7616 (set_attr "atype" "reg,reg")
7617 (set_attr "cpu_facility" "*,z196")
7618 (set_attr "z10prop" "z10_super_E1,*")])
7621 (define_insn "*ashr<mode>3"
7622 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7623 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7624 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
7625 (clobber (reg:CC CC_REGNUM))]
7630 [(set_attr "op_type" "RS<E>,RSY")
7631 (set_attr "atype" "reg,reg")
7632 (set_attr "cpu_facility" "*,z196")
7633 (set_attr "z10prop" "z10_super_E1,*")])
7636 ; shift pattern with implicit ANDs
7638 (define_insn "*ashrdi3_cc_31_and"
7639 [(set (reg CC_REGNUM)
7640 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7641 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7642 (match_operand:SI 3 "const_int_operand" "n")))
7644 (set (match_operand:DI 0 "register_operand" "=d")
7645 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7646 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7647 && (INTVAL (operands[3]) & 63) == 63"
7649 [(set_attr "op_type" "RS")
7650 (set_attr "atype" "reg")])
7652 (define_insn "*ashrdi3_cconly_31_and"
7653 [(set (reg CC_REGNUM)
7654 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7655 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7656 (match_operand:SI 3 "const_int_operand" "n")))
7658 (clobber (match_scratch:DI 0 "=d"))]
7659 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
7660 && (INTVAL (operands[3]) & 63) == 63"
7662 [(set_attr "op_type" "RS")
7663 (set_attr "atype" "reg")])
7665 (define_insn "*ashrdi3_31_and"
7666 [(set (match_operand:DI 0 "register_operand" "=d")
7667 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7668 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7669 (match_operand:SI 3 "const_int_operand" "n"))))
7670 (clobber (reg:CC CC_REGNUM))]
7671 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7673 [(set_attr "op_type" "RS")
7674 (set_attr "atype" "reg")])
7677 (define_insn "*ashr<mode>3_cc_and"
7678 [(set (reg CC_REGNUM)
7679 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7680 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7681 (match_operand:SI 3 "const_int_operand" "n,n")))
7683 (set (match_operand:GPR 0 "register_operand" "=d,d")
7684 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7685 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7689 [(set_attr "op_type" "RS<E>,RSY")
7690 (set_attr "atype" "reg,reg")
7691 (set_attr "cpu_facility" "*,z196")
7692 (set_attr "z10prop" "z10_super_E1,*")])
7695 (define_insn "*ashr<mode>3_cconly_and"
7696 [(set (reg CC_REGNUM)
7697 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7698 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7699 (match_operand:SI 3 "const_int_operand" "n,n")))
7701 (clobber (match_scratch:GPR 0 "=d,d"))]
7702 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7706 [(set_attr "op_type" "RS<E>,RSY")
7707 (set_attr "atype" "reg,reg")
7708 (set_attr "cpu_facility" "*,z196")
7709 (set_attr "z10prop" "z10_super_E1,*")])
7712 (define_insn "*ashr<mode>3_and"
7713 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7714 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
7715 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
7716 (match_operand:SI 3 "const_int_operand" "n,n"))))
7717 (clobber (reg:CC CC_REGNUM))]
7718 "(INTVAL (operands[3]) & 63) == 63"
7722 [(set_attr "op_type" "RS<E>,RSY")
7723 (set_attr "atype" "reg,reg")
7724 (set_attr "cpu_facility" "*,z196")
7725 (set_attr "z10prop" "z10_super_E1,*")])
7729 ;; Branch instruction patterns.
7732 (define_expand "cbranch<mode>4"
7734 (if_then_else (match_operator 0 "comparison_operator"
7735 [(match_operand:GPR 1 "register_operand" "")
7736 (match_operand:GPR 2 "general_operand" "")])
7737 (label_ref (match_operand 3 "" ""))
7740 "s390_emit_jump (operands[3],
7741 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7744 (define_expand "cbranch<mode>4"
7746 (if_then_else (match_operator 0 "comparison_operator"
7747 [(match_operand:FP 1 "register_operand" "")
7748 (match_operand:FP 2 "general_operand" "")])
7749 (label_ref (match_operand 3 "" ""))
7752 "s390_emit_jump (operands[3],
7753 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7756 (define_expand "cbranchcc4"
7758 (if_then_else (match_operator 0 "s390_eqne_operator"
7759 [(match_operand 1 "cc_reg_operand" "")
7760 (match_operand 2 "const0_operand" "")])
7761 (label_ref (match_operand 3 "" ""))
7764 "s390_emit_jump (operands[3],
7765 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
7771 ;;- Conditional jump instructions.
7774 (define_insn "*cjump_64"
7777 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7778 (label_ref (match_operand 0 "" ""))
7782 if (get_attr_length (insn) == 4)
7785 return "jg%C1\t%l0";
7787 [(set_attr "op_type" "RI")
7788 (set_attr "type" "branch")
7789 (set (attr "length")
7790 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7791 (const_int 4) (const_int 6)))])
7793 (define_insn "*cjump_31"
7796 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7797 (label_ref (match_operand 0 "" ""))
7801 gcc_assert (get_attr_length (insn) == 4);
7804 [(set_attr "op_type" "RI")
7805 (set_attr "type" "branch")
7806 (set (attr "length")
7807 (if_then_else (not (match_test "flag_pic"))
7808 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7809 (const_int 4) (const_int 6))
7810 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7811 (const_int 4) (const_int 8))))])
7813 (define_insn "*cjump_long"
7816 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7817 (match_operand 0 "address_operand" "ZQZR")
7821 if (get_attr_op_type (insn) == OP_TYPE_RR)
7826 [(set (attr "op_type")
7827 (if_then_else (match_operand 0 "register_operand" "")
7828 (const_string "RR") (const_string "RX")))
7829 (set_attr "type" "branch")
7830 (set_attr "atype" "agen")])
7834 ;;- Negated conditional jump instructions.
7837 (define_insn "*icjump_64"
7840 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7842 (label_ref (match_operand 0 "" ""))))]
7845 if (get_attr_length (insn) == 4)
7848 return "jg%D1\t%l0";
7850 [(set_attr "op_type" "RI")
7851 (set_attr "type" "branch")
7852 (set (attr "length")
7853 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7854 (const_int 4) (const_int 6)))])
7856 (define_insn "*icjump_31"
7859 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7861 (label_ref (match_operand 0 "" ""))))]
7864 gcc_assert (get_attr_length (insn) == 4);
7867 [(set_attr "op_type" "RI")
7868 (set_attr "type" "branch")
7869 (set (attr "length")
7870 (if_then_else (not (match_test "flag_pic"))
7871 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7872 (const_int 4) (const_int 6))
7873 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7874 (const_int 4) (const_int 8))))])
7876 (define_insn "*icjump_long"
7879 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7881 (match_operand 0 "address_operand" "ZQZR")))]
7884 if (get_attr_op_type (insn) == OP_TYPE_RR)
7889 [(set (attr "op_type")
7890 (if_then_else (match_operand 0 "register_operand" "")
7891 (const_string "RR") (const_string "RX")))
7892 (set_attr "type" "branch")
7893 (set_attr "atype" "agen")])
7896 ;;- Trap instructions.
7900 [(trap_if (const_int 1) (const_int 0))]
7903 [(set_attr "op_type" "RI")
7904 (set_attr "type" "branch")])
7906 (define_expand "ctrap<mode>4"
7907 [(trap_if (match_operator 0 "comparison_operator"
7908 [(match_operand:GPR 1 "register_operand" "")
7909 (match_operand:GPR 2 "general_operand" "")])
7910 (match_operand 3 "const0_operand" ""))]
7913 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7914 operands[1], operands[2]);
7915 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7919 (define_expand "ctrap<mode>4"
7920 [(trap_if (match_operator 0 "comparison_operator"
7921 [(match_operand:FP 1 "register_operand" "")
7922 (match_operand:FP 2 "general_operand" "")])
7923 (match_operand 3 "const0_operand" ""))]
7926 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
7927 operands[1], operands[2]);
7928 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
7932 (define_insn "condtrap"
7933 [(trap_if (match_operator 0 "s390_comparison"
7934 [(match_operand 1 "cc_reg_operand" "c")
7939 [(set_attr "op_type" "RI")
7940 (set_attr "type" "branch")])
7942 ; crt, cgrt, cit, cgit
7943 (define_insn "*cmp_and_trap_signed_int<mode>"
7944 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7945 [(match_operand:GPR 1 "register_operand" "d,d")
7946 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7952 [(set_attr "op_type" "RRF,RIE")
7953 (set_attr "type" "branch")
7954 (set_attr "z10prop" "z10_super_c,z10_super")])
7956 ; clrt, clgrt, clfit, clgit, clt, clgt
7957 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7958 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7959 [(match_operand:GPR 1 "register_operand" "d,d, d")
7960 (match_operand:GPR 2 "general_operand" "d,D,RT")])
7967 [(set_attr "op_type" "RRF,RIE,RSY")
7968 (set_attr "type" "branch")
7969 (set_attr "z10prop" "z10_super_c,z10_super,*")
7970 (set_attr "cpu_facility" "z10,z10,zEC12")])
7973 (define_insn "*load_and_trap<mode>"
7974 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
7977 (set (match_operand:GPR 1 "register_operand" "=d")
7981 [(set_attr "op_type" "RXY")])
7985 ;;- Loop instructions.
7987 ;; This is all complicated by the fact that since this is a jump insn
7988 ;; we must handle our own output reloads.
7992 ; This splitter will be matched by combine and has to add the 2 moves
7993 ; necessary to load the compare and the increment values into a
7994 ; register pair as needed by brxle.
7996 (define_insn_and_split "*brx_stage1_<GPR:mode>"
7999 (match_operator 6 "s390_brx_operator"
8000 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
8001 (match_operand:GPR 2 "general_operand" ""))
8002 (match_operand:GPR 3 "register_operand" "")])
8003 (label_ref (match_operand 0 "" ""))
8005 (set (match_operand:GPR 4 "nonimmediate_operand" "")
8006 (plus:GPR (match_dup 1) (match_dup 2)))
8007 (clobber (match_scratch:GPR 5 ""))]
8010 "!reload_completed && !reload_in_progress"
8011 [(set (match_dup 7) (match_dup 2)) ; the increment
8012 (set (match_dup 8) (match_dup 3)) ; the comparison value
8013 (parallel [(set (pc)
8016 [(plus:GPR (match_dup 1) (match_dup 7))
8018 (label_ref (match_dup 0))
8021 (plus:GPR (match_dup 1) (match_dup 7)))
8022 (clobber (match_dup 5))
8023 (clobber (reg:CC CC_REGNUM))])]
8025 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
8026 operands[7] = gen_lowpart (<GPR:MODE>mode,
8027 gen_highpart (word_mode, dreg));
8028 operands[8] = gen_lowpart (<GPR:MODE>mode,
8029 gen_lowpart (word_mode, dreg));
8034 (define_insn_and_split "*brxg_64bit"
8037 (match_operator 5 "s390_brx_operator"
8038 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
8039 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
8040 (subreg:DI (match_dup 2) 8)])
8041 (label_ref (match_operand 0 "" ""))
8043 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
8044 (plus:DI (match_dup 1)
8045 (subreg:DI (match_dup 2) 0)))
8046 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
8047 (clobber (reg:CC CC_REGNUM))]
8050 if (which_alternative != 0)
8052 else if (get_attr_length (insn) == 6)
8053 return "brx%E5g\t%1,%2,%l0";
8055 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
8057 "&& reload_completed
8058 && (!REG_P (operands[3])
8059 || !rtx_equal_p (operands[1], operands[3]))"
8060 [(set (match_dup 4) (match_dup 1))
8061 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
8062 (clobber (reg:CC CC_REGNUM))])
8063 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
8064 (set (match_dup 3) (match_dup 4))
8065 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8066 (label_ref (match_dup 0))
8069 [(set_attr "op_type" "RIE")
8070 (set_attr "type" "branch")
8071 (set (attr "length")
8072 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8073 (const_int 6) (const_int 16)))])
8077 (define_insn_and_split "*brx_64bit"
8080 (match_operator 5 "s390_brx_operator"
8081 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8082 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
8083 (subreg:SI (match_dup 2) 12)])
8084 (label_ref (match_operand 0 "" ""))
8086 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8087 (plus:SI (match_dup 1)
8088 (subreg:SI (match_dup 2) 4)))
8089 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8090 (clobber (reg:CC CC_REGNUM))]
8093 if (which_alternative != 0)
8095 else if (get_attr_length (insn) == 6)
8096 return "brx%C5\t%1,%2,%l0";
8098 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8100 "&& reload_completed
8101 && (!REG_P (operands[3])
8102 || !rtx_equal_p (operands[1], operands[3]))"
8103 [(set (match_dup 4) (match_dup 1))
8104 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
8105 (clobber (reg:CC CC_REGNUM))])
8106 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
8107 (set (match_dup 3) (match_dup 4))
8108 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8109 (label_ref (match_dup 0))
8112 [(set_attr "op_type" "RSI")
8113 (set_attr "type" "branch")
8114 (set (attr "length")
8115 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8116 (const_int 6) (const_int 14)))])
8120 (define_insn_and_split "*brx_31bit"
8123 (match_operator 5 "s390_brx_operator"
8124 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
8125 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
8126 (subreg:SI (match_dup 2) 4)])
8127 (label_ref (match_operand 0 "" ""))
8129 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
8130 (plus:SI (match_dup 1)
8131 (subreg:SI (match_dup 2) 0)))
8132 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
8133 (clobber (reg:CC CC_REGNUM))]
8134 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
8136 if (which_alternative != 0)
8138 else if (get_attr_length (insn) == 6)
8139 return "brx%C5\t%1,%2,%l0";
8141 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
8143 "&& reload_completed
8144 && (!REG_P (operands[3])
8145 || !rtx_equal_p (operands[1], operands[3]))"
8146 [(set (match_dup 4) (match_dup 1))
8147 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
8148 (clobber (reg:CC CC_REGNUM))])
8149 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
8150 (set (match_dup 3) (match_dup 4))
8151 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
8152 (label_ref (match_dup 0))
8155 [(set_attr "op_type" "RSI")
8156 (set_attr "type" "branch")
8157 (set (attr "length")
8158 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8159 (const_int 6) (const_int 14)))])
8164 (define_expand "doloop_end"
8165 [(use (match_operand 0 "" "")) ; loop pseudo
8166 (use (match_operand 1 "" "")) ; iterations; zero if unknown
8167 (use (match_operand 2 "" "")) ; max iterations
8168 (use (match_operand 3 "" "")) ; loop level
8169 (use (match_operand 4 "" "")) ; label
8170 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
8173 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
8174 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
8175 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
8176 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
8177 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
8178 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
8185 (define_insn_and_split "doloop_si64"
8188 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8190 (label_ref (match_operand 0 "" ""))
8192 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8193 (plus:SI (match_dup 1) (const_int -1)))
8194 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8195 (clobber (reg:CC CC_REGNUM))]
8198 if (which_alternative != 0)
8200 else if (get_attr_length (insn) == 4)
8201 return "brct\t%1,%l0";
8203 return "ahi\t%1,-1\;jgne\t%l0";
8205 "&& reload_completed
8206 && (! REG_P (operands[2])
8207 || ! rtx_equal_p (operands[1], operands[2]))"
8208 [(set (match_dup 3) (match_dup 1))
8209 (parallel [(set (reg:CCAN CC_REGNUM)
8210 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8212 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8213 (set (match_dup 2) (match_dup 3))
8214 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8215 (label_ref (match_dup 0))
8218 [(set_attr "op_type" "RI")
8219 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8220 ; hurt us in the (rare) case of ahi.
8221 (set_attr "z10prop" "z10_super_E1")
8222 (set_attr "type" "branch")
8223 (set (attr "length")
8224 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8225 (const_int 4) (const_int 10)))])
8227 (define_insn_and_split "doloop_si31"
8230 (ne (match_operand:SI 1 "register_operand" "d,d,d")
8232 (label_ref (match_operand 0 "" ""))
8234 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
8235 (plus:SI (match_dup 1) (const_int -1)))
8236 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
8237 (clobber (reg:CC CC_REGNUM))]
8240 if (which_alternative != 0)
8242 else if (get_attr_length (insn) == 4)
8243 return "brct\t%1,%l0";
8247 "&& reload_completed
8248 && (! REG_P (operands[2])
8249 || ! rtx_equal_p (operands[1], operands[2]))"
8250 [(set (match_dup 3) (match_dup 1))
8251 (parallel [(set (reg:CCAN CC_REGNUM)
8252 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
8254 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
8255 (set (match_dup 2) (match_dup 3))
8256 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8257 (label_ref (match_dup 0))
8260 [(set_attr "op_type" "RI")
8261 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8262 ; hurt us in the (rare) case of ahi.
8263 (set_attr "z10prop" "z10_super_E1")
8264 (set_attr "type" "branch")
8265 (set (attr "length")
8266 (if_then_else (not (match_test "flag_pic"))
8267 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8268 (const_int 4) (const_int 6))
8269 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8270 (const_int 4) (const_int 8))))])
8272 (define_insn "*doloop_si_long"
8275 (ne (match_operand:SI 1 "register_operand" "d")
8277 (match_operand 0 "address_operand" "ZQZR")
8279 (set (match_operand:SI 2 "register_operand" "=1")
8280 (plus:SI (match_dup 1) (const_int -1)))
8281 (clobber (match_scratch:SI 3 "=X"))
8282 (clobber (reg:CC CC_REGNUM))]
8285 if (get_attr_op_type (insn) == OP_TYPE_RR)
8286 return "bctr\t%1,%0";
8288 return "bct\t%1,%a0";
8290 [(set (attr "op_type")
8291 (if_then_else (match_operand 0 "register_operand" "")
8292 (const_string "RR") (const_string "RX")))
8293 (set_attr "type" "branch")
8294 (set_attr "atype" "agen")
8295 (set_attr "z10prop" "z10_c")
8296 (set_attr "z196prop" "z196_cracked")])
8298 (define_insn_and_split "doloop_di"
8301 (ne (match_operand:DI 1 "register_operand" "d,d,d")
8303 (label_ref (match_operand 0 "" ""))
8305 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
8306 (plus:DI (match_dup 1) (const_int -1)))
8307 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
8308 (clobber (reg:CC CC_REGNUM))]
8311 if (which_alternative != 0)
8313 else if (get_attr_length (insn) == 4)
8314 return "brctg\t%1,%l0";
8316 return "aghi\t%1,-1\;jgne\t%l0";
8318 "&& reload_completed
8319 && (! REG_P (operands[2])
8320 || ! rtx_equal_p (operands[1], operands[2]))"
8321 [(set (match_dup 3) (match_dup 1))
8322 (parallel [(set (reg:CCAN CC_REGNUM)
8323 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
8325 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
8326 (set (match_dup 2) (match_dup 3))
8327 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
8328 (label_ref (match_dup 0))
8331 [(set_attr "op_type" "RI")
8332 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
8333 ; hurt us in the (rare) case of ahi.
8334 (set_attr "z10prop" "z10_super_E1")
8335 (set_attr "type" "branch")
8336 (set (attr "length")
8337 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8338 (const_int 4) (const_int 10)))])
8341 ;;- Unconditional jump instructions.
8345 ; jump instruction pattern(s).
8348 (define_expand "jump"
8349 [(match_operand 0 "" "")]
8351 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
8353 (define_insn "*jump64"
8354 [(set (pc) (label_ref (match_operand 0 "" "")))]
8357 if (get_attr_length (insn) == 4)
8362 [(set_attr "op_type" "RI")
8363 (set_attr "type" "branch")
8364 (set (attr "length")
8365 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8366 (const_int 4) (const_int 6)))])
8368 (define_insn "*jump31"
8369 [(set (pc) (label_ref (match_operand 0 "" "")))]
8372 gcc_assert (get_attr_length (insn) == 4);
8375 [(set_attr "op_type" "RI")
8376 (set_attr "type" "branch")
8377 (set (attr "length")
8378 (if_then_else (not (match_test "flag_pic"))
8379 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8380 (const_int 4) (const_int 6))
8381 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
8382 (const_int 4) (const_int 8))))])
8385 ; indirect-jump instruction pattern(s).
8388 (define_insn "indirect_jump"
8389 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
8392 if (get_attr_op_type (insn) == OP_TYPE_RR)
8397 [(set (attr "op_type")
8398 (if_then_else (match_operand 0 "register_operand" "")
8399 (const_string "RR") (const_string "RX")))
8400 (set_attr "type" "branch")
8401 (set_attr "atype" "agen")])
8404 ; casesi instruction pattern(s).
8407 (define_insn "casesi_jump"
8408 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
8409 (use (label_ref (match_operand 1 "" "")))]
8412 if (get_attr_op_type (insn) == OP_TYPE_RR)
8417 [(set (attr "op_type")
8418 (if_then_else (match_operand 0 "register_operand" "")
8419 (const_string "RR") (const_string "RX")))
8420 (set_attr "type" "branch")
8421 (set_attr "atype" "agen")])
8423 (define_expand "casesi"
8424 [(match_operand:SI 0 "general_operand" "")
8425 (match_operand:SI 1 "general_operand" "")
8426 (match_operand:SI 2 "general_operand" "")
8427 (label_ref (match_operand 3 "" ""))
8428 (label_ref (match_operand 4 "" ""))]
8431 rtx index = gen_reg_rtx (SImode);
8432 rtx base = gen_reg_rtx (Pmode);
8433 rtx target = gen_reg_rtx (Pmode);
8435 emit_move_insn (index, operands[0]);
8436 emit_insn (gen_subsi3 (index, index, operands[1]));
8437 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
8440 if (Pmode != SImode)
8441 index = convert_to_mode (Pmode, index, 1);
8442 if (GET_CODE (index) != REG)
8443 index = copy_to_mode_reg (Pmode, index);
8446 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
8448 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
8450 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
8452 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
8453 emit_move_insn (target, index);
8456 target = gen_rtx_PLUS (Pmode, base, target);
8457 emit_jump_insn (gen_casesi_jump (target, operands[3]));
8464 ;;- Jump to subroutine.
8469 ; untyped call instruction pattern(s).
8472 ;; Call subroutine returning any type.
8473 (define_expand "untyped_call"
8474 [(parallel [(call (match_operand 0 "" "")
8476 (match_operand 1 "" "")
8477 (match_operand 2 "" "")])]
8482 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
8484 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8486 rtx set = XVECEXP (operands[2], 0, i);
8487 emit_move_insn (SET_DEST (set), SET_SRC (set));
8490 /* The optimizer does not know that the call sets the function value
8491 registers we stored in the result block. We avoid problems by
8492 claiming that all hard registers are used and clobbered at this
8494 emit_insn (gen_blockage ());
8499 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
8500 ;; all of memory. This blocks insns from being moved across this point.
8502 (define_insn "blockage"
8503 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8506 [(set_attr "type" "none")
8507 (set_attr "length" "0")])
8513 (define_expand "sibcall"
8514 [(call (match_operand 0 "" "")
8515 (match_operand 1 "" ""))]
8518 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
8522 (define_insn "*sibcall_br"
8523 [(call (mem:QI (reg SIBCALL_REGNUM))
8524 (match_operand 0 "const_int_operand" "n"))]
8525 "SIBLING_CALL_P (insn)
8526 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
8528 [(set_attr "op_type" "RR")
8529 (set_attr "type" "branch")
8530 (set_attr "atype" "agen")])
8532 (define_insn "*sibcall_brc"
8533 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8534 (match_operand 1 "const_int_operand" "n"))]
8535 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8537 [(set_attr "op_type" "RI")
8538 (set_attr "type" "branch")])
8540 (define_insn "*sibcall_brcl"
8541 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8542 (match_operand 1 "const_int_operand" "n"))]
8543 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8545 [(set_attr "op_type" "RIL")
8546 (set_attr "type" "branch")])
8549 ; sibcall_value patterns
8552 (define_expand "sibcall_value"
8553 [(set (match_operand 0 "" "")
8554 (call (match_operand 1 "" "")
8555 (match_operand 2 "" "")))]
8558 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
8562 (define_insn "*sibcall_value_br"
8563 [(set (match_operand 0 "" "")
8564 (call (mem:QI (reg SIBCALL_REGNUM))
8565 (match_operand 1 "const_int_operand" "n")))]
8566 "SIBLING_CALL_P (insn)
8567 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
8569 [(set_attr "op_type" "RR")
8570 (set_attr "type" "branch")
8571 (set_attr "atype" "agen")])
8573 (define_insn "*sibcall_value_brc"
8574 [(set (match_operand 0 "" "")
8575 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8576 (match_operand 2 "const_int_operand" "n")))]
8577 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
8579 [(set_attr "op_type" "RI")
8580 (set_attr "type" "branch")])
8582 (define_insn "*sibcall_value_brcl"
8583 [(set (match_operand 0 "" "")
8584 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8585 (match_operand 2 "const_int_operand" "n")))]
8586 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
8588 [(set_attr "op_type" "RIL")
8589 (set_attr "type" "branch")])
8593 ; call instruction pattern(s).
8596 (define_expand "call"
8597 [(call (match_operand 0 "" "")
8598 (match_operand 1 "" ""))
8599 (use (match_operand 2 "" ""))]
8602 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
8603 gen_rtx_REG (Pmode, RETURN_REGNUM));
8607 (define_insn "*bras"
8608 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8609 (match_operand 1 "const_int_operand" "n"))
8610 (clobber (match_operand 2 "register_operand" "=r"))]
8611 "!SIBLING_CALL_P (insn)
8612 && TARGET_SMALL_EXEC
8613 && GET_MODE (operands[2]) == Pmode"
8615 [(set_attr "op_type" "RI")
8616 (set_attr "type" "jsr")
8617 (set_attr "z196prop" "z196_cracked")])
8619 (define_insn "*brasl"
8620 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
8621 (match_operand 1 "const_int_operand" "n"))
8622 (clobber (match_operand 2 "register_operand" "=r"))]
8623 "!SIBLING_CALL_P (insn)
8625 && GET_MODE (operands[2]) == Pmode"
8627 [(set_attr "op_type" "RIL")
8628 (set_attr "type" "jsr")
8629 (set_attr "z196prop" "z196_cracked")])
8631 (define_insn "*basr"
8632 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
8633 (match_operand 1 "const_int_operand" "n"))
8634 (clobber (match_operand 2 "register_operand" "=r"))]
8635 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8637 if (get_attr_op_type (insn) == OP_TYPE_RR)
8638 return "basr\t%2,%0";
8640 return "bas\t%2,%a0";
8642 [(set (attr "op_type")
8643 (if_then_else (match_operand 0 "register_operand" "")
8644 (const_string "RR") (const_string "RX")))
8645 (set_attr "type" "jsr")
8646 (set_attr "atype" "agen")
8647 (set_attr "z196prop" "z196_cracked")])
8650 ; call_value instruction pattern(s).
8653 (define_expand "call_value"
8654 [(set (match_operand 0 "" "")
8655 (call (match_operand 1 "" "")
8656 (match_operand 2 "" "")))
8657 (use (match_operand 3 "" ""))]
8660 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8661 gen_rtx_REG (Pmode, RETURN_REGNUM));
8665 (define_insn "*bras_r"
8666 [(set (match_operand 0 "" "")
8667 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8668 (match_operand:SI 2 "const_int_operand" "n")))
8669 (clobber (match_operand 3 "register_operand" "=r"))]
8670 "!SIBLING_CALL_P (insn)
8671 && TARGET_SMALL_EXEC
8672 && GET_MODE (operands[3]) == Pmode"
8674 [(set_attr "op_type" "RI")
8675 (set_attr "type" "jsr")
8676 (set_attr "z196prop" "z196_cracked")])
8678 (define_insn "*brasl_r"
8679 [(set (match_operand 0 "" "")
8680 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8681 (match_operand 2 "const_int_operand" "n")))
8682 (clobber (match_operand 3 "register_operand" "=r"))]
8683 "!SIBLING_CALL_P (insn)
8685 && GET_MODE (operands[3]) == Pmode"
8687 [(set_attr "op_type" "RIL")
8688 (set_attr "type" "jsr")
8689 (set_attr "z196prop" "z196_cracked")])
8691 (define_insn "*basr_r"
8692 [(set (match_operand 0 "" "")
8693 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8694 (match_operand 2 "const_int_operand" "n")))
8695 (clobber (match_operand 3 "register_operand" "=r"))]
8696 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8698 if (get_attr_op_type (insn) == OP_TYPE_RR)
8699 return "basr\t%3,%1";
8701 return "bas\t%3,%a1";
8703 [(set (attr "op_type")
8704 (if_then_else (match_operand 1 "register_operand" "")
8705 (const_string "RR") (const_string "RX")))
8706 (set_attr "type" "jsr")
8707 (set_attr "atype" "agen")
8708 (set_attr "z196prop" "z196_cracked")])
8711 ;;- Thread-local storage support.
8714 (define_expand "get_thread_pointer<mode>"
8715 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
8719 (define_expand "set_thread_pointer<mode>"
8720 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
8721 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
8725 (define_insn "*set_tp"
8726 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8729 [(set_attr "type" "none")
8730 (set_attr "length" "0")])
8732 (define_insn "*tls_load_64"
8733 [(set (match_operand:DI 0 "register_operand" "=d")
8734 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8735 (match_operand:DI 2 "" "")]
8739 [(set_attr "op_type" "RXE")
8740 (set_attr "z10prop" "z10_fwd_A3")])
8742 (define_insn "*tls_load_31"
8743 [(set (match_operand:SI 0 "register_operand" "=d,d")
8744 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8745 (match_operand:SI 2 "" "")]
8751 [(set_attr "op_type" "RX,RXY")
8752 (set_attr "type" "load")
8753 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8755 (define_insn "*bras_tls"
8756 [(set (match_operand 0 "" "")
8757 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8758 (match_operand 2 "const_int_operand" "n")))
8759 (clobber (match_operand 3 "register_operand" "=r"))
8760 (use (match_operand 4 "" ""))]
8761 "!SIBLING_CALL_P (insn)
8762 && TARGET_SMALL_EXEC
8763 && GET_MODE (operands[3]) == Pmode"
8765 [(set_attr "op_type" "RI")
8766 (set_attr "type" "jsr")
8767 (set_attr "z196prop" "z196_cracked")])
8769 (define_insn "*brasl_tls"
8770 [(set (match_operand 0 "" "")
8771 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8772 (match_operand 2 "const_int_operand" "n")))
8773 (clobber (match_operand 3 "register_operand" "=r"))
8774 (use (match_operand 4 "" ""))]
8775 "!SIBLING_CALL_P (insn)
8777 && GET_MODE (operands[3]) == Pmode"
8779 [(set_attr "op_type" "RIL")
8780 (set_attr "type" "jsr")
8781 (set_attr "z196prop" "z196_cracked")])
8783 (define_insn "*basr_tls"
8784 [(set (match_operand 0 "" "")
8785 (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
8786 (match_operand 2 "const_int_operand" "n")))
8787 (clobber (match_operand 3 "register_operand" "=r"))
8788 (use (match_operand 4 "" ""))]
8789 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8791 if (get_attr_op_type (insn) == OP_TYPE_RR)
8792 return "basr\t%3,%1%J4";
8794 return "bas\t%3,%a1%J4";
8796 [(set (attr "op_type")
8797 (if_then_else (match_operand 1 "register_operand" "")
8798 (const_string "RR") (const_string "RX")))
8799 (set_attr "type" "jsr")
8800 (set_attr "atype" "agen")
8801 (set_attr "z196prop" "z196_cracked")])
8804 ;;- Atomic operations
8808 ; memory barrier patterns.
8811 (define_expand "mem_signal_fence"
8812 [(match_operand:SI 0 "const_int_operand")] ;; model
8815 /* The s390 memory model is strong enough not to require any
8816 barrier in order to synchronize a thread with itself. */
8820 (define_expand "mem_thread_fence"
8821 [(match_operand:SI 0 "const_int_operand")] ;; model
8824 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
8825 enough not to require barriers of any kind. */
8826 if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST)
8828 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8829 MEM_VOLATILE_P (mem) = 1;
8830 emit_insn (gen_mem_thread_fence_1 (mem));
8835 ; Although bcr is superscalar on Z10, this variant will never
8836 ; become part of an execution group.
8837 (define_insn "mem_thread_fence_1"
8838 [(set (match_operand:BLK 0 "" "")
8839 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
8842 [(set_attr "op_type" "RR")])
8845 ; atomic load/store operations
8848 ; Atomic loads need not examine the memory model at all.
8849 (define_expand "atomic_load<mode>"
8850 [(match_operand:DINT 0 "register_operand") ;; output
8851 (match_operand:DINT 1 "memory_operand") ;; memory
8852 (match_operand:SI 2 "const_int_operand")] ;; model
8855 if (<MODE>mode == TImode)
8856 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
8857 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8858 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
8860 emit_move_insn (operands[0], operands[1]);
8864 ; Different from movdi_31 in that we want no splitters.
8865 (define_insn "atomic_loaddi_1"
8866 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
8867 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
8875 [(set_attr "op_type" "RS,RSY,RS,RSY")
8876 (set_attr "type" "lm,lm,floaddf,floaddf")])
8878 (define_insn "atomic_loadti_1"
8879 [(set (match_operand:TI 0 "register_operand" "=r")
8880 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
8884 [(set_attr "op_type" "RXY")
8885 (set_attr "type" "other")])
8887 ; Atomic stores must(?) enforce sequential consistency.
8888 (define_expand "atomic_store<mode>"
8889 [(match_operand:DINT 0 "memory_operand") ;; memory
8890 (match_operand:DINT 1 "register_operand") ;; input
8891 (match_operand:SI 2 "const_int_operand")] ;; model
8894 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
8896 if (<MODE>mode == TImode)
8897 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
8898 else if (<MODE>mode == DImode && !TARGET_ZARCH)
8899 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
8901 emit_move_insn (operands[0], operands[1]);
8902 if (model == MEMMODEL_SEQ_CST)
8903 emit_insn (gen_mem_thread_fence (operands[2]));
8907 ; Different from movdi_31 in that we want no splitters.
8908 (define_insn "atomic_storedi_1"
8909 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
8910 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
8918 [(set_attr "op_type" "RS,RSY,RS,RSY")
8919 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
8921 (define_insn "atomic_storeti_1"
8922 [(set (match_operand:TI 0 "memory_operand" "=RT")
8923 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
8927 [(set_attr "op_type" "RXY")
8928 (set_attr "type" "other")])
8931 ; compare and swap patterns.
8934 (define_expand "atomic_compare_and_swap<mode>"
8935 [(match_operand:SI 0 "register_operand") ;; bool success output
8936 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
8937 (match_operand:DGPR 2 "memory_operand") ;; memory
8938 (match_operand:DGPR 3 "register_operand") ;; expected intput
8939 (match_operand:DGPR 4 "register_operand") ;; newval intput
8940 (match_operand:SI 5 "const_int_operand") ;; is_weak
8941 (match_operand:SI 6 "const_int_operand") ;; success model
8942 (match_operand:SI 7 "const_int_operand")] ;; failure model
8945 rtx cc, cmp, output = operands[1];
8947 if (!register_operand (output, <MODE>mode))
8948 output = gen_reg_rtx (<MODE>mode);
8950 emit_insn (gen_atomic_compare_and_swap<mode>_internal
8951 (output, operands[2], operands[3], operands[4]));
8953 /* We deliberately accept non-register operands in the predicate
8954 to ensure the write back to the output operand happens *before*
8955 the store-flags code below. This makes it easier for combine
8956 to merge the store-flags code with a potential test-and-branch
8957 pattern following (immediately!) afterwards. */
8958 if (output != operands[1])
8959 emit_move_insn (operands[1], output);
8961 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
8962 cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
8963 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
8967 (define_expand "atomic_compare_and_swap<mode>"
8968 [(match_operand:SI 0 "register_operand") ;; bool success output
8969 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
8970 (match_operand:HQI 2 "memory_operand") ;; memory
8971 (match_operand:HQI 3 "general_operand") ;; expected intput
8972 (match_operand:HQI 4 "general_operand") ;; newval intput
8973 (match_operand:SI 5 "const_int_operand") ;; is_weak
8974 (match_operand:SI 6 "const_int_operand") ;; success model
8975 (match_operand:SI 7 "const_int_operand")] ;; failure model
8978 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
8979 operands[3], operands[4], INTVAL (operands[5]));
8983 (define_expand "atomic_compare_and_swap<mode>_internal"
8985 [(set (match_operand:DGPR 0 "register_operand")
8986 (match_operand:DGPR 1 "memory_operand"))
8988 (unspec_volatile:DGPR
8990 (match_operand:DGPR 2 "register_operand")
8991 (match_operand:DGPR 3 "register_operand")]
8993 (set (reg:CCZ1 CC_REGNUM)
8994 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8998 (define_insn "*atomic_compare_and_swap<mode>_1"
8999 [(set (match_operand:TDI 0 "register_operand" "=r")
9000 (match_operand:TDI 1 "memory_operand" "+QS"))
9002 (unspec_volatile:TDI
9004 (match_operand:TDI 2 "register_operand" "0")
9005 (match_operand:TDI 3 "register_operand" "r")]
9007 (set (reg:CCZ1 CC_REGNUM)
9008 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9010 "c<td>sg\t%0,%3,%S1"
9011 [(set_attr "op_type" "RSY")
9012 (set_attr "type" "sem")])
9015 (define_insn "*atomic_compare_and_swapdi_2"
9016 [(set (match_operand:DI 0 "register_operand" "=r,r")
9017 (match_operand:DI 1 "memory_operand" "+Q,S"))
9021 (match_operand:DI 2 "register_operand" "0,0")
9022 (match_operand:DI 3 "register_operand" "r,r")]
9024 (set (reg:CCZ1 CC_REGNUM)
9025 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9030 [(set_attr "op_type" "RS,RSY")
9031 (set_attr "type" "sem")])
9034 (define_insn "*atomic_compare_and_swapsi_3"
9035 [(set (match_operand:SI 0 "register_operand" "=r,r")
9036 (match_operand:SI 1 "memory_operand" "+Q,S"))
9040 (match_operand:SI 2 "register_operand" "0,0")
9041 (match_operand:SI 3 "register_operand" "r,r")]
9043 (set (reg:CCZ1 CC_REGNUM)
9044 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
9049 [(set_attr "op_type" "RS,RSY")
9050 (set_attr "type" "sem")])
9053 ; Other atomic instruction patterns.
9056 ; z196 load and add, xor, or and and instructions
9058 (define_expand "atomic_fetch_<atomic><mode>"
9059 [(match_operand:GPR 0 "register_operand") ;; val out
9061 (match_operand:GPR 1 "memory_operand") ;; memory
9062 (match_operand:GPR 2 "register_operand")) ;; val in
9063 (match_operand:SI 3 "const_int_operand")] ;; model
9066 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
9067 (operands[0], operands[1], operands[2]));
9071 ; lan, lang, lao, laog, lax, laxg, laa, laag
9072 (define_insn "atomic_fetch_<atomic><mode>_iaf"
9073 [(set (match_operand:GPR 0 "register_operand" "=d")
9074 (match_operand:GPR 1 "memory_operand" "+QS"))
9076 (unspec_volatile:GPR
9077 [(ATOMIC_Z196:GPR (match_dup 1)
9078 (match_operand:GPR 2 "general_operand" "d"))]
9080 (clobber (reg:CC CC_REGNUM))]
9082 "la<noxa><g>\t%0,%2,%1"
9083 [(set_attr "op_type" "RSY")
9084 (set_attr "type" "sem")])
9086 ;; For SImode and larger, the optabs.c code will do just fine in
9087 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
9088 ;; better by expanding our own loop.
9090 (define_expand "atomic_<atomic><mode>"
9092 (match_operand:HQI 0 "memory_operand") ;; memory
9093 (match_operand:HQI 1 "general_operand")) ;; val in
9094 (match_operand:SI 2 "const_int_operand")] ;; model
9097 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
9098 operands[1], false);
9102 (define_expand "atomic_fetch_<atomic><mode>"
9103 [(match_operand:HQI 0 "register_operand") ;; val out
9105 (match_operand:HQI 1 "memory_operand") ;; memory
9106 (match_operand:HQI 2 "general_operand")) ;; val in
9107 (match_operand:SI 3 "const_int_operand")] ;; model
9110 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9111 operands[2], false);
9115 (define_expand "atomic_<atomic>_fetch<mode>"
9116 [(match_operand:HQI 0 "register_operand") ;; val out
9118 (match_operand:HQI 1 "memory_operand") ;; memory
9119 (match_operand:HQI 2 "general_operand")) ;; val in
9120 (match_operand:SI 3 "const_int_operand")] ;; model
9123 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
9128 (define_expand "atomic_exchange<mode>"
9129 [(match_operand:HQI 0 "register_operand") ;; val out
9130 (match_operand:HQI 1 "memory_operand") ;; memory
9131 (match_operand:HQI 2 "general_operand") ;; val in
9132 (match_operand:SI 3 "const_int_operand")] ;; model
9135 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
9136 operands[2], false);
9141 ;;- Miscellaneous instructions.
9145 ; allocate stack instruction pattern(s).
9148 (define_expand "allocate_stack"
9149 [(match_operand 0 "general_operand" "")
9150 (match_operand 1 "general_operand" "")]
9153 rtx temp = gen_reg_rtx (Pmode);
9155 emit_move_insn (temp, s390_back_chain_rtx ());
9156 anti_adjust_stack (operands[1]);
9157 emit_move_insn (s390_back_chain_rtx (), temp);
9159 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9165 ; setjmp instruction pattern.
9168 (define_expand "builtin_setjmp_receiver"
9169 [(match_operand 0 "" "")]
9172 emit_insn (s390_load_got ());
9173 emit_use (pic_offset_table_rtx);
9177 ;; These patterns say how to save and restore the stack pointer. We need not
9178 ;; save the stack pointer at function level since we are careful to
9179 ;; preserve the backchain. At block level, we have to restore the backchain
9180 ;; when we restore the stack pointer.
9182 ;; For nonlocal gotos, we must save both the stack pointer and its
9183 ;; backchain and restore both. Note that in the nonlocal case, the
9184 ;; save area is a memory location.
9186 (define_expand "save_stack_function"
9187 [(match_operand 0 "general_operand" "")
9188 (match_operand 1 "general_operand" "")]
9192 (define_expand "restore_stack_function"
9193 [(match_operand 0 "general_operand" "")
9194 (match_operand 1 "general_operand" "")]
9198 (define_expand "restore_stack_block"
9199 [(match_operand 0 "register_operand" "")
9200 (match_operand 1 "register_operand" "")]
9203 rtx temp = gen_reg_rtx (Pmode);
9205 emit_move_insn (temp, s390_back_chain_rtx ());
9206 emit_move_insn (operands[0], operands[1]);
9207 emit_move_insn (s390_back_chain_rtx (), temp);
9212 (define_expand "save_stack_nonlocal"
9213 [(match_operand 0 "memory_operand" "")
9214 (match_operand 1 "register_operand" "")]
9217 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9219 /* Copy the backchain to the first word, sp to the second and the
9220 literal pool base to the third. */
9222 rtx save_bc = adjust_address (operands[0], Pmode, 0);
9223 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
9224 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
9226 if (TARGET_BACKCHAIN)
9227 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
9229 emit_move_insn (save_sp, operands[1]);
9230 emit_move_insn (save_bp, base);
9235 (define_expand "restore_stack_nonlocal"
9236 [(match_operand 0 "register_operand" "")
9237 (match_operand 1 "memory_operand" "")]
9240 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
9241 rtx temp = NULL_RTX;
9243 /* Restore the backchain from the first word, sp from the second and the
9244 literal pool base from the third. */
9246 rtx save_bc = adjust_address (operands[1], Pmode, 0);
9247 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
9248 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
9250 if (TARGET_BACKCHAIN)
9251 temp = force_reg (Pmode, save_bc);
9253 emit_move_insn (base, save_bp);
9254 emit_move_insn (operands[0], save_sp);
9257 emit_move_insn (s390_back_chain_rtx (), temp);
9263 (define_expand "exception_receiver"
9267 s390_set_has_landing_pad_p (true);
9272 ; nop instruction pattern(s).
9279 [(set_attr "op_type" "RR")
9280 (set_attr "z10prop" "z10_fr_E1")])
9286 [(set_attr "op_type" "RR")])
9290 ; Special literal pool access instruction pattern(s).
9293 (define_insn "*pool_entry"
9294 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
9295 UNSPECV_POOL_ENTRY)]
9298 enum machine_mode mode = GET_MODE (PATTERN (insn));
9299 unsigned int align = GET_MODE_BITSIZE (mode);
9300 s390_output_pool_entry (operands[0], mode, align);
9303 [(set (attr "length")
9304 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
9306 (define_insn "pool_align"
9307 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
9308 UNSPECV_POOL_ALIGN)]
9311 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9313 (define_insn "pool_section_start"
9314 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
9317 [(set_attr "length" "0")])
9319 (define_insn "pool_section_end"
9320 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
9323 [(set_attr "length" "0")])
9325 (define_insn "main_base_31_small"
9326 [(set (match_operand 0 "register_operand" "=a")
9327 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9328 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9330 [(set_attr "op_type" "RR")
9331 (set_attr "type" "la")
9332 (set_attr "z196prop" "z196_cracked")])
9334 (define_insn "main_base_31_large"
9335 [(set (match_operand 0 "register_operand" "=a")
9336 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
9337 (set (pc) (label_ref (match_operand 2 "" "")))]
9338 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9340 [(set_attr "op_type" "RI")
9341 (set_attr "z196prop" "z196_cracked")])
9343 (define_insn "main_base_64"
9344 [(set (match_operand 0 "register_operand" "=a")
9345 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
9346 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9348 [(set_attr "op_type" "RIL")
9349 (set_attr "type" "larl")
9350 (set_attr "z10prop" "z10_fwd_A1")])
9352 (define_insn "main_pool"
9353 [(set (match_operand 0 "register_operand" "=a")
9354 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
9355 "GET_MODE (operands[0]) == Pmode"
9360 (if_then_else (match_test "TARGET_CPU_ZARCH")
9361 (const_string "larl") (const_string "la")))])
9363 (define_insn "reload_base_31"
9364 [(set (match_operand 0 "register_operand" "=a")
9365 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9366 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9367 "basr\t%0,0\;la\t%0,%1-.(%0)"
9368 [(set_attr "length" "6")
9369 (set_attr "type" "la")
9370 (set_attr "z196prop" "z196_cracked")])
9372 (define_insn "reload_base_64"
9373 [(set (match_operand 0 "register_operand" "=a")
9374 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
9375 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
9377 [(set_attr "op_type" "RIL")
9378 (set_attr "type" "larl")
9379 (set_attr "z10prop" "z10_fwd_A1")])
9382 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
9387 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
9390 ;; Insns related to generating the function prologue and epilogue.
9394 (define_expand "prologue"
9395 [(use (const_int 0))]
9397 "s390_emit_prologue (); DONE;")
9399 (define_expand "epilogue"
9400 [(use (const_int 1))]
9402 "s390_emit_epilogue (false); DONE;")
9404 (define_expand "sibcall_epilogue"
9405 [(use (const_int 0))]
9407 "s390_emit_epilogue (true); DONE;")
9409 (define_insn "*return"
9411 (use (match_operand 0 "register_operand" "a"))]
9412 "GET_MODE (operands[0]) == Pmode"
9414 [(set_attr "op_type" "RR")
9415 (set_attr "type" "jsr")
9416 (set_attr "atype" "agen")])
9419 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
9420 ;; pointer. This is used for compatibility.
9422 (define_expand "ptr_extend"
9423 [(set (match_operand:DI 0 "register_operand" "=r")
9424 (match_operand:SI 1 "register_operand" "r"))]
9427 emit_insn (gen_anddi3 (operands[0],
9428 gen_lowpart (DImode, operands[1]),
9429 GEN_INT (0x7fffffff)));
9433 ;; Instruction definition to expand eh_return macro to support
9434 ;; swapping in special linkage return addresses.
9436 (define_expand "eh_return"
9437 [(use (match_operand 0 "register_operand" ""))]
9440 s390_emit_tpf_eh_return (operands[0]);
9445 ; Stack Protector Patterns
9448 (define_expand "stack_protect_set"
9449 [(set (match_operand 0 "memory_operand" "")
9450 (match_operand 1 "memory_operand" ""))]
9453 #ifdef TARGET_THREAD_SSP_OFFSET
9455 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9456 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9459 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
9461 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
9466 (define_insn "stack_protect_set<mode>"
9467 [(set (match_operand:DSI 0 "memory_operand" "=Q")
9468 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
9470 "mvc\t%O0(%G0,%R0),%S1"
9471 [(set_attr "op_type" "SS")])
9473 (define_expand "stack_protect_test"
9474 [(set (reg:CC CC_REGNUM)
9475 (compare (match_operand 0 "memory_operand" "")
9476 (match_operand 1 "memory_operand" "")))
9477 (match_operand 2 "" "")]
9481 #ifdef TARGET_THREAD_SSP_OFFSET
9483 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
9484 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
9487 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
9489 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
9491 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
9492 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
9493 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
9497 (define_insn "stack_protect_test<mode>"
9498 [(set (reg:CCZ CC_REGNUM)
9499 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
9500 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
9502 "clc\t%O0(%G0,%R0),%S1"
9503 [(set_attr "op_type" "SS")])
9505 ; This is used in s390_emit_prologue in order to prevent insns
9506 ; adjusting the stack pointer to be moved over insns writing stack
9507 ; slots using a copy of the stack pointer in a different register.
9508 (define_insn "stack_tie"
9509 [(set (match_operand:BLK 0 "memory_operand" "+m")
9510 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9513 [(set_attr "length" "0")])
9517 ; Data prefetch patterns
9520 (define_insn "prefetch"
9521 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
9522 (match_operand:SI 1 "const_int_operand" " n,n")
9523 (match_operand:SI 2 "const_int_operand" " n,n"))]
9526 switch (which_alternative)
9529 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
9531 if (larl_operand (operands[0], Pmode))
9532 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
9535 /* This might be reached for symbolic operands with an odd
9536 addend. We simply omit the prefetch for such rare cases. */
9541 [(set_attr "type" "load,larl")
9542 (set_attr "op_type" "RXY,RIL")
9543 (set_attr "z10prop" "z10_super")
9544 (set_attr "z196prop" "z196_alone")])
9548 ; Byte swap instructions
9551 (define_insn "bswap<mode>2"
9552 [(set (match_operand:GPR 0 "register_operand" "=d, d")
9553 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
9558 [(set_attr "type" "*,load")
9559 (set_attr "op_type" "RRE,RXY")
9560 (set_attr "z10prop" "z10_super")])
9564 ; Population count instruction
9567 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
9568 ; portions and stores the result in the corresponding bytes in op0.
9569 (define_insn "*popcount<mode>"
9570 [(set (match_operand:INT 0 "register_operand" "=d")
9571 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
9572 (clobber (reg:CC CC_REGNUM))]
9575 [(set_attr "op_type" "RRE")])
9577 (define_expand "popcountdi2"
9579 (parallel [(set (match_operand:DI 0 "register_operand" "")
9580 (unspec:DI [(match_operand:DI 1 "register_operand")]
9582 (clobber (reg:CC CC_REGNUM))])
9584 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
9586 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9587 (clobber (reg:CC CC_REGNUM))])
9590 (ashift:DI (match_dup 0) (const_int 16)))
9592 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9593 (clobber (reg:CC CC_REGNUM))])
9595 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
9597 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
9598 (clobber (reg:CC CC_REGNUM))])
9600 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
9601 "TARGET_Z196 && TARGET_64BIT"
9602 "operands[2] = gen_reg_rtx (DImode);")
9604 (define_expand "popcountsi2"
9606 (parallel [(set (match_operand:SI 0 "register_operand" "")
9607 (unspec:SI [(match_operand:SI 1 "register_operand")]
9609 (clobber (reg:CC CC_REGNUM))])
9612 (ashift:SI (match_dup 0) (const_int 16)))
9614 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9615 (clobber (reg:CC CC_REGNUM))])
9617 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
9619 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9620 (clobber (reg:CC CC_REGNUM))])
9622 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
9624 "operands[2] = gen_reg_rtx (SImode);")
9626 (define_expand "popcounthi2"
9628 (parallel [(set (match_operand:HI 0 "register_operand" "")
9629 (unspec:HI [(match_operand:HI 1 "register_operand")]
9631 (clobber (reg:CC CC_REGNUM))])
9634 (ashift:SI (match_dup 0) (const_int 8)))
9636 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
9637 (clobber (reg:CC CC_REGNUM))])
9639 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
9641 "operands[2] = gen_reg_rtx (SImode);")
9643 (define_expand "popcountqi2"
9645 (parallel [(set (match_operand:QI 0 "register_operand" "")
9646 (unspec:QI [(match_operand:QI 1 "register_operand")]
9648 (clobber (reg:CC CC_REGNUM))])]
9653 ;;- Copy sign instructions
9656 (define_insn "copysign<mode>3"
9657 [(set (match_operand:FP 0 "register_operand" "=f")
9658 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
9659 (match_operand:FP 2 "register_operand" "f")]
9663 [(set_attr "op_type" "RRF")
9664 (set_attr "type" "fsimp<mode>")])