gcc/config/rs6000/power4.md

   1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors.
   2 ;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify it
   7 ;; under the terms of the GNU General Public License as published
   8 ;; by the Free Software Foundation; either version 2, or (at your
   9 ;; option) any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 ;; License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to the
  18 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  19 ;; MA 02111-1307, USA.
  20
  21 ;; Sources: IBM Red Book and White Paper on POWER4
  22
  23 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
  24 ;; Instructions that update more than one register get broken into two
  25 ;; (split) or more internal ops.  The chip can issue up to 5
  26 ;; internal ops per cycle.
  27
  28 (define_automaton "power4iu,power4fpu,power4vec,power4misc")
  29
  30 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu")
  31 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc")
  32 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu")
  33 (define_cpu_unit "bpu_power4,cru_power4" "power4misc")
  34 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec")
  35 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4"
  36                  "power4misc")
  37
  38 (define_reservation "lsq_power4"
  39                     "(du1_power4,lsu1_power4)\
  40                     |(du2_power4,lsu2_power4)\
  41                     |(du3_power4,lsu2_power4)\
  42                     |(du4_power4,lsu1_power4)")
  43
  44 (define_reservation "lsuq_power4"
  45                     "(du1_power4+du2_power4,lsu1_power4+iu2_power4)\
  46                     |(du2_power4+du3_power4,lsu2_power4+iu2_power4)\
  47                     |(du3_power4+du4_power4,lsu2_power4+iu1_power4)")
  48
  49 (define_reservation "iq_power4"
  50                     "(du1_power4,iu1_power4)\
  51                     |(du2_power4,iu2_power4)\
  52                     |(du3_power4,iu2_power4)\
  53                     |(du4_power4,iu1_power4)")
  54
  55 (define_reservation "fpq_power4"
  56                     "(du1_power4,fpu1_power4)\
  57                     |(du2_power4,fpu2_power4)\
  58                     |(du3_power4,fpu2_power4)\
  59                     |(du4_power4,fpu1_power4)")
  60
  61 (define_reservation "vq_power4"
  62                     "(du1_power4,vec_power4)\
  63                     |(du2_power4,vec_power4)\
  64                     |(du3_power4,vec_power4)\
  65                     |(du4_power4,vec_power4)")
  66
  67 (define_reservation "vpq_power4"
  68                     "(du1_power4,vecperm_power4)\
  69                     |(du2_power4,vecperm_power4)\
  70                     |(du3_power4,vecperm_power4)\
  71                     |(du4_power4,vecperm_power4)")
  72
  73
  74 ; Dispatch slots are allocated in order conforming to program order.
  75 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4")
  76 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4")
  77 (absence_set "du3_power4" "du4_power4,du5_power4")
  78 (absence_set "du4_power4" "du5_power4")
  79
  80
  81 ; Load/store
  82 (define_insn_reservation "power4-load" 4 ; 3
  83   (and (eq_attr "type" "load")
  84        (eq_attr "cpu" "power4"))
  85   "lsq_power4")
  86
  87 (define_insn_reservation "power4-load-ext" 5
  88   (and (eq_attr "type" "load_ext")
  89        (eq_attr "cpu" "power4"))
  90   "(du1_power4+du2_power4,lsu1_power4,nothing,nothing,iu2_power4)\
  91   |(du2_power4+du3_power4,lsu2_power4,nothing,nothing,iu2_power4)\
  92   |(du3_power4+du4_power4,lsu2_power4,nothing,nothing,iu1_power4)")
  93
  94 (define_insn_reservation "power4-load-ext-update" 5
  95   (and (eq_attr "type" "load_ext_u")
  96        (eq_attr "cpu" "power4"))
  97   "du1_power4+du2_power4+du3_power4+du4_power4,\
  98    lsu1_power4+iu2_power4,nothing,nothing,iu2_power4")
  99
 100 (define_insn_reservation "power4-load-ext-update-indexed" 5
 101   (and (eq_attr "type" "load_ext_ux")
 102        (eq_attr "cpu" "power4"))
 103   "du1_power4+du2_power4+du3_power4+du4_power4,\
 104    iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
 105
 106 (define_insn_reservation "power4-load-update-indexed" 3
 107   (and (eq_attr "type" "load_ux")
 108        (eq_attr "cpu" "power4"))
 109   "du1_power4+du2_power4+du3_power4+du4_power4,\
 110    iu1_power4,lsu2_power4+iu2_power4")
 111
 112 (define_insn_reservation "power4-load-update" 4 ; 3
 113   (and (eq_attr "type" "load_u")
 114        (eq_attr "cpu" "power4"))
 115   "lsuq_power4")
 116
 117 (define_insn_reservation "power4-fpload" 6 ; 5
 118   (and (eq_attr "type" "fpload")
 119        (eq_attr "cpu" "power4"))
 120   "lsq_power4")
 121
 122 (define_insn_reservation "power4-fpload-update" 6 ; 5
 123   (and (eq_attr "type" "fpload_u,fpload_ux")
 124        (eq_attr "cpu" "power4"))
 125   "lsuq_power4")
 126
 127 (define_insn_reservation "power4-vecload" 6 ; 5
 128   (and (eq_attr "type" "vecload")
 129        (eq_attr "cpu" "power4"))
 130   "lsq_power4")
 131
 132 (define_insn_reservation "power4-store" 12
 133   (and (eq_attr "type" "store")
 134        (eq_attr "cpu" "power4"))
 135   "(du1_power4,lsu1_power4,iu1_power4)\
 136   |(du2_power4,lsu2_power4,iu2_power4)\
 137   |(du3_power4,lsu2_power4,iu2_power4)\
 138   |(du4_power4,lsu1_power4,iu1_power4)")
 139
 140 (define_insn_reservation "power4-store-update" 12
 141   (and (eq_attr "type" "store_u")
 142        (eq_attr "cpu" "power4"))
 143   "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\
 144   |(du2_power4+du3_power4,lsu2_power4+iu2_power4,iu2_power4)\
 145   |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\
 146   |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)")
 147
 148 (define_insn_reservation "power4-store-update-indexed" 12
 149   (and (eq_attr "type" "store_ux")
 150        (eq_attr "cpu" "power4"))
 151    "du1_power4+du2_power4+du3_power4+du4_power4,\
 152     iu1_power4,lsu2_power4+iu2_power4,iu2_power4")
 153
 154 (define_insn_reservation "power4-fpstore" 12
 155   (and (eq_attr "type" "fpstore")
 156        (eq_attr "cpu" "power4"))
 157   "(du1_power4,lsu1_power4,fpu1_power4)\
 158   |(du2_power4,lsu2_power4,fpu2_power4)\
 159   |(du3_power4,lsu2_power4,fpu2_power4)\
 160   |(du4_power4,lsu1_power4,fpu1_power4)")
 161
 162 (define_insn_reservation "power4-fpstore-update" 12
 163   (and (eq_attr "type" "fpstore_u,fpstore_ux")
 164        (eq_attr "cpu" "power4"))
 165   "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\
 166   |(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\
 167   |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)")
 168
 169 (define_insn_reservation "power4-vecstore" 12
 170   (and (eq_attr "type" "vecstore")
 171        (eq_attr "cpu" "power4"))
 172   "(du1_power4,lsu1_power4,vec_power4)\
 173   |(du2_power4,lsu2_power4,vec_power4)\
 174   |(du3_power4,lsu2_power4,vec_power4)\
 175   |(du4_power4,lsu1_power4,vec_power4)")
 176
 177
 178 ; Integer latency is 2 cycles
 179 (define_insn_reservation "power4-integer" 2
 180   (and (eq_attr "type" "integer")
 181        (eq_attr "cpu" "power4"))
 182   "iq_power4")
 183
 184 (define_insn_reservation "power4-two" 2
 185   (and (eq_attr "type" "two")
 186        (eq_attr "cpu" "power4"))
 187   "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
 188   |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
 189   |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\
 190   |(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)")
 191
 192 (define_insn_reservation "power4-three" 2
 193   (and (eq_attr "type" "three")
 194        (eq_attr "cpu" "power4"))
 195   "(du1_power4+du2_power4+du3_power4,\
 196     iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
 197   |(du2_power4+du3_power4+du4_power4,\
 198     iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
 199   |(du3_power4+du4_power4+du1_power4,\
 200     iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
 201   |(du4_power4+du1_power4+du2_power4,\
 202     iu1_power4,nothing,iu2_power4,nothing,iu2_power4)")
 203
 204 (define_insn_reservation "power4-insert" 4
 205   (and (eq_attr "type" "insert_word")
 206        (eq_attr "cpu" "power4"))
 207   "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
 208   |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
 209   |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)")
 210
 211 (define_insn_reservation "power4-cmp" 3
 212   (and (eq_attr "type" "cmp,fast_compare")
 213        (eq_attr "cpu" "power4"))
 214   "iq_power4")
 215
 216 (define_insn_reservation "power4-compare" 2
 217   (and (eq_attr "type" "compare,delayed_compare")
 218        (eq_attr "cpu" "power4"))
 219   "(du1_power4+du2_power4,iu1_power4,iu2_power4)\
 220   |(du2_power4+du3_power4,iu2_power4,iu2_power4)\
 221   |(du3_power4+du4_power4,iu2_power4,iu1_power4)")
 222
 223 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 224
 225 (define_insn_reservation "power4-lmul-cmp" 7
 226   (and (eq_attr "type" "lmul_compare")
 227        (eq_attr "cpu" "power4"))
 228   "(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\
 229   |(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\
 230   |(du3_power4+du4_power4,iu2_power4*6,iu1_power4)")
 231
 232 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 233
 234 (define_insn_reservation "power4-imul-cmp" 5
 235   (and (eq_attr "type" "imul_compare")
 236        (eq_attr "cpu" "power4"))
 237   "(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\
 238   |(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\
 239   |(du3_power4+du4_power4,iu2_power4*4,iu1_power4)")
 240
 241 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 242
 243 (define_insn_reservation "power4-lmul" 7
 244   (and (eq_attr "type" "lmul")
 245        (eq_attr "cpu" "power4"))
 246   "(du1_power4,iu1_power4*6)\
 247   |(du2_power4,iu2_power4*6)\
 248   |(du3_power4,iu2_power4*6)\
 249   |(du4_power4,iu1_power4*6)")
 250
 251 (define_insn_reservation "power4-imul" 5
 252   (and (eq_attr "type" "imul")
 253        (eq_attr "cpu" "power4"))
 254   "(du1_power4,iu1_power4*4)\
 255   |(du2_power4,iu2_power4*4)\
 256   |(du3_power4,iu2_power4*4)\
 257   |(du4_power4,iu1_power4*4)")
 258
 259 (define_insn_reservation "power4-imul3" 4
 260   (and (eq_attr "type" "imul2,imul3")
 261        (eq_attr "cpu" "power4"))
 262   "(du1_power4,iu1_power4*3)\
 263   |(du2_power4,iu2_power4*3)\
 264   |(du3_power4,iu2_power4*3)\
 265   |(du4_power4,iu1_power4*3)")
 266
 267
 268 ; SPR move only executes in first IU.
 269 ; Integer division only executes in second IU.
 270 (define_insn_reservation "power4-idiv" 36
 271   (and (eq_attr "type" "idiv")
 272        (eq_attr "cpu" "power4"))
 273   "du1_power4+du2_power4,iu2_power4*35")
 274
 275 (define_insn_reservation "power4-ldiv" 68
 276   (and (eq_attr "type" "ldiv")
 277        (eq_attr "cpu" "power4"))
 278   "du1_power4+du2_power4,iu2_power4*67")
 279
 280
 281 (define_insn_reservation "power4-mtjmpr" 3
 282   (and (eq_attr "type" "mtjmpr,mfjmpr")
 283        (eq_attr "cpu" "power4"))
 284   "du1_power4,bpu_power4")
 285
 286
 287 ; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
 288 ; grabbing previous dispatch slots once this is assigned.
 289 (define_insn_reservation "power4-branch" 2
 290   (and (eq_attr "type" "jmpreg,branch")
 291        (eq_attr "cpu" "power4"))
 292   "(du5_power4\
 293    |du4_power4+du5_power4\
 294    |du3_power4+du4_power4+du5_power4\
 295    |du2_power4+du3_power4+du4_power4+du5_power4\
 296    |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
 297
 298
 299 ; Condition Register logical ops are split if non-destructive (RT != RB)
 300 (define_insn_reservation "power4-crlogical" 2
 301   (and (eq_attr "type" "cr_logical")
 302        (eq_attr "cpu" "power4"))
 303   "du1_power4,cru_power4")
 304
 305 (define_insn_reservation "power4-delayedcr" 4
 306   (and (eq_attr "type" "delayed_cr")
 307        (eq_attr "cpu" "power4"))
 308   "du1_power4+du2_power4,cru_power4,cru_power4")
 309
 310 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
 311 (define_insn_reservation "power4-mfcr" 6
 312   (and (eq_attr "type" "mfcr")
 313        (eq_attr "cpu" "power4"))
 314   "du1_power4+du2_power4+du3_power4+du4_power4,\
 315    du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\
 316    cru_power4,cru_power4,cru_power4")
 317
 318 ; mfcrf (1 field)
 319 (define_insn_reservation "power4-mfcrf" 3
 320   (and (eq_attr "type" "mfcrf")
 321        (eq_attr "cpu" "power4"))
 322   "du1_power4,cru_power4")
 323
 324 ; mtcrf (1 field)
 325 (define_insn_reservation "power4-mtcr" 4
 326   (and (eq_attr "type" "mtcr")
 327        (eq_attr "cpu" "power4"))
 328   "du1_power4,iu1_power4")
 329
 330 ; Basic FP latency is 6 cycles
 331 (define_insn_reservation "power4-fp" 6
 332   (and (eq_attr "type" "fp,dmul")
 333        (eq_attr "cpu" "power4"))
 334   "fpq_power4")
 335
 336 (define_insn_reservation "power4-fpcompare" 5
 337   (and (eq_attr "type" "fpcompare")
 338        (eq_attr "cpu" "power4"))
 339   "fpq_power4")
 340
 341 (define_insn_reservation "power4-sdiv" 33
 342   (and (eq_attr "type" "sdiv,ddiv")
 343        (eq_attr "cpu" "power4"))
 344   "(du1_power4,fpu1_power4*28)\
 345   |(du2_power4,fpu2_power4*28)\
 346   |(du3_power4,fpu2_power4*28)\
 347   |(du4_power4,fpu1_power4*28)")
 348
 349 (define_insn_reservation "power4-sqrt" 40
 350   (and (eq_attr "type" "ssqrt,dsqrt")
 351        (eq_attr "cpu" "power4"))
 352   "(du1_power4,fpu1_power4*35)\
 353   |(du2_power4,fpu2_power4*35)\
 354   |(du3_power4,fpu2_power4*35)\
 355   |(du4_power4,fpu2_power4*35)")
 356
 357
 358 ; VMX
 359 (define_insn_reservation "power4-vecsimple" 2
 360   (and (eq_attr "type" "vecsimple")
 361        (eq_attr "cpu" "power4"))
 362   "vq_power4")
 363
 364 (define_insn_reservation "power4-veccomplex" 5
 365   (and (eq_attr "type" "veccomplex")
 366        (eq_attr "cpu" "power4"))
 367   "vq_power4")
 368
 369 ; vecfp compare
 370 (define_insn_reservation "power4-veccmp" 8
 371   (and (eq_attr "type" "veccmp")
 372        (eq_attr "cpu" "power4"))
 373   "vq_power4")
 374
 375 (define_insn_reservation "power4-vecfloat" 8
 376   (and (eq_attr "type" "vecfloat")
 377        (eq_attr "cpu" "power4"))
 378   "vq_power4")
 379
 380 (define_insn_reservation "power4-vecperm" 2
 381   (and (eq_attr "type" "vecperm")
 382        (eq_attr "cpu" "power4"))
 383   "vpq_power4")
 384
 385 (define_bypass 4 "power4-vecload" "power4-vecperm")
 386
 387 (define_bypass 3 "power4-vecsimple" "power4-vecperm")
 388 (define_bypass 6 "power4-veccomplex" "power4-vecperm")
 389 (define_bypass 3 "power4-vecperm"
 390                  "power4-vecsimple,power4-veccomplex,power4-vecfloat")
 391 (define_bypass 9 "power4-vecfloat" "power4-vecperm")
 392
 393 (define_bypass 5 "power4-vecsimple,power4-veccomplex"
 394                  "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
 395
 396 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore")
 397 (define_bypass 7 "power4-veccomplex" "power4-vecstore")
 398 (define_bypass 10 "power4-vecfloat" "power4-vecstore")