1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2015 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
37 #include "fold-const.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
41 #include "print-tree.h"
49 #include "insn-codes.h"
58 #include "cfgcleanup.h"
59 #include "diagnostic-core.h"
63 #include "common/common-target.h"
64 #include "langhooks.h"
67 #include "sched-int.h"
68 #include "internal-fn.h"
69 #include "gimple-fold.h"
72 #include "gimple-iterator.h"
73 #include "gimple-walk.h"
76 #include "tm-constrs.h"
79 #include "tree-vectorizer.h"
82 #include "target-globals.h"
85 #include "tree-pass.h"
87 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
90 #include "gstab.h" /* for N_SLINE */
93 /* This file should be included last. */
94 #include "target-def.h"
96 #ifndef TARGET_NO_PROTOTYPE
97 #define TARGET_NO_PROTOTYPE 0
100 #define min(A,B) ((A) < (B) ? (A) : (B))
101 #define max(A,B) ((A) > (B) ? (A) : (B))
103 /* Structure used to define the rs6000 stack */
104 typedef struct rs6000_stack
{
105 int reload_completed
; /* stack info won't change from here on */
106 int first_gp_reg_save
; /* first callee saved GP register used */
107 int first_fp_reg_save
; /* first callee saved FP register used */
108 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
109 int lr_save_p
; /* true if the link reg needs to be saved */
110 int cr_save_p
; /* true if the CR reg needs to be saved */
111 unsigned int vrsave_mask
; /* mask of vec registers to save */
112 int push_p
; /* true if we need to allocate stack space */
113 int calls_p
; /* true if the function makes any calls */
114 int world_save_p
; /* true if we're saving *everything*:
115 r13-r31, cr, f14-f31, vrsave, v20-v31 */
116 enum rs6000_abi abi
; /* which ABI to use */
117 int gp_save_offset
; /* offset to save GP regs from initial SP */
118 int fp_save_offset
; /* offset to save FP regs from initial SP */
119 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
120 int lr_save_offset
; /* offset to save LR from initial SP */
121 int cr_save_offset
; /* offset to save CR from initial SP */
122 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
123 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
124 int varargs_save_offset
; /* offset to save the varargs registers */
125 int ehrd_offset
; /* offset to EH return data */
126 int ehcr_offset
; /* offset to EH CR field data */
127 int reg_size
; /* register size (4 or 8) */
128 HOST_WIDE_INT vars_size
; /* variable save area size */
129 int parm_size
; /* outgoing parameter size */
130 int save_size
; /* save area size */
131 int fixed_size
; /* fixed size of stack frame */
132 int gp_size
; /* size of saved GP registers */
133 int fp_size
; /* size of saved FP registers */
134 int altivec_size
; /* size of saved AltiVec registers */
135 int cr_size
; /* size to hold CR if not in fixed area */
136 int vrsave_size
; /* size to hold VRSAVE */
137 int altivec_padding_size
; /* size of altivec alignment padding */
138 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
139 int spe_padding_size
;
140 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
141 int spe_64bit_regs_used
;
145 /* A C structure for machine-specific, per-function data.
146 This is added to the cfun structure. */
147 typedef struct GTY(()) machine_function
149 /* Whether the instruction chain has been scanned already. */
150 int insn_chain_scanned_p
;
151 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
152 int ra_needs_full_frame
;
153 /* Flags if __builtin_return_address (0) was used. */
155 /* Cache lr_save_p after expansion of builtin_eh_return. */
157 /* Whether we need to save the TOC to the reserved stack location in the
158 function prologue. */
159 bool save_toc_in_prologue
;
160 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
161 varargs save area. */
162 HOST_WIDE_INT varargs_save_offset
;
163 /* Temporary stack slot to use for SDmode copies. This slot is
164 64-bits wide and is allocated early enough so that the offset
165 does not overflow the 16-bit load/store offset field. */
166 rtx sdmode_stack_slot
;
167 /* Alternative internal arg pointer for -fsplit-stack. */
168 rtx split_stack_arg_pointer
;
169 bool split_stack_argp_used
;
170 /* Flag if r2 setup is needed with ELFv2 ABI. */
171 bool r2_setup_needed
;
174 /* Support targetm.vectorize.builtin_mask_for_load. */
175 static GTY(()) tree altivec_builtin_mask_for_load
;
177 /* Set to nonzero once AIX common-mode calls have been defined. */
178 static GTY(()) int common_mode_defined
;
180 /* Label number of label created for -mrelocatable, to call to so we can
181 get the address of the GOT section */
182 static int rs6000_pic_labelno
;
185 /* Counter for labels which are to be placed in .fixup. */
186 int fixuplabelno
= 0;
189 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
192 /* Specify the machine mode that pointers have. After generation of rtl, the
193 compiler makes no further distinction between pointers and any other objects
194 of this machine mode. The type is unsigned since not all things that
195 include rs6000.h also include machmode.h. */
196 unsigned rs6000_pmode
;
198 /* Width in bits of a pointer. */
199 unsigned rs6000_pointer_size
;
201 #ifdef HAVE_AS_GNU_ATTRIBUTE
202 /* Flag whether floating point values have been passed/returned. */
203 static bool rs6000_passes_float
;
204 /* Flag whether vector values have been passed/returned. */
205 static bool rs6000_passes_vector
;
206 /* Flag whether small (<= 8 byte) structures have been returned. */
207 static bool rs6000_returns_struct
;
210 /* Value is TRUE if register/mode pair is acceptable. */
211 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
213 /* Maximum number of registers needed for a given register class and mode. */
214 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
216 /* How many registers are needed for a given register and mode. */
217 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
219 /* Map register number to register class. */
220 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
222 static int dbg_cost_ctrl
;
224 /* Built in types. */
225 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
226 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
228 /* Flag to say the TOC is initialized */
230 char toc_label_name
[10];
232 /* Cached value of rs6000_variable_issue. This is cached in
233 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
234 static short cached_can_issue_more
;
236 static GTY(()) section
*read_only_data_section
;
237 static GTY(()) section
*private_data_section
;
238 static GTY(()) section
*tls_data_section
;
239 static GTY(()) section
*tls_private_data_section
;
240 static GTY(()) section
*read_only_private_data_section
;
241 static GTY(()) section
*sdata2_section
;
242 static GTY(()) section
*toc_section
;
244 struct builtin_description
246 const HOST_WIDE_INT mask
;
247 const enum insn_code icode
;
248 const char *const name
;
249 const enum rs6000_builtins code
;
252 /* Describe the vector unit used for modes. */
253 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
254 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
256 /* Register classes for various constraints that are based on the target
258 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
260 /* Describe the alignment of a vector. */
261 int rs6000_vector_align
[NUM_MACHINE_MODES
];
263 /* Map selected modes to types for builtins. */
264 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
266 /* What modes to automatically generate reciprocal divide estimate (fre) and
267 reciprocal sqrt (frsqrte) for. */
268 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
270 /* Masks to determine which reciprocal esitmate instructions to generate
272 enum rs6000_recip_mask
{
273 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
274 RECIP_DF_DIV
= 0x002,
275 RECIP_V4SF_DIV
= 0x004,
276 RECIP_V2DF_DIV
= 0x008,
278 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
279 RECIP_DF_RSQRT
= 0x020,
280 RECIP_V4SF_RSQRT
= 0x040,
281 RECIP_V2DF_RSQRT
= 0x080,
283 /* Various combination of flags for -mrecip=xxx. */
285 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
286 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
287 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
289 RECIP_HIGH_PRECISION
= RECIP_ALL
,
291 /* On low precision machines like the power5, don't enable double precision
292 reciprocal square root estimate, since it isn't accurate enough. */
293 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
296 /* -mrecip options. */
299 const char *string
; /* option name */
300 unsigned int mask
; /* mask bits to set */
301 } recip_options
[] = {
302 { "all", RECIP_ALL
},
303 { "none", RECIP_NONE
},
304 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
306 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
307 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
308 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
309 | RECIP_V2DF_RSQRT
) },
310 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
311 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
314 /* Pointer to function (in rs6000-c.c) that can define or undefine target
315 macros that have changed. Languages that don't support the preprocessor
316 don't link in rs6000-c.c, so we can't call it directly. */
317 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
319 /* Simplfy register classes into simpler classifications. We assume
320 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
321 check for standard register classes (gpr/floating/altivec/vsx) and
322 floating/vector classes (float/altivec/vsx). */
324 enum rs6000_reg_type
{
337 /* Map register class to register type. */
338 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
340 /* First/last register type for the 'normal' register types (i.e. general
341 purpose, floating point, altivec, and VSX registers). */
342 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
344 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
347 /* Register classes we care about in secondary reload or go if legitimate
348 address. We only need to worry about GPR, FPR, and Altivec registers here,
349 along an ANY field that is the OR of the 3 register classes. */
351 enum rs6000_reload_reg_type
{
352 RELOAD_REG_GPR
, /* General purpose registers. */
353 RELOAD_REG_FPR
, /* Traditional floating point regs. */
354 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
355 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
359 /* For setting up register classes, loop through the 3 register classes mapping
360 into real registers, and skip the ANY class, which is just an OR of the
362 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
363 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
365 /* Map reload register type to a register in the register class. */
366 struct reload_reg_map_type
{
367 const char *name
; /* Register class name. */
368 int reg
; /* Register in the register class. */
371 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
372 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
373 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
374 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
375 { "Any", -1 }, /* RELOAD_REG_ANY. */
378 /* Mask bits for each register class, indexed per mode. Historically the
379 compiler has been more restrictive which types can do PRE_MODIFY instead of
380 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
381 typedef unsigned char addr_mask_type
;
383 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
384 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
385 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
386 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
387 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
388 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
389 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
391 /* Register type masks based on the type, of valid addressing modes. */
392 struct rs6000_reg_addr
{
393 enum insn_code reload_load
; /* INSN to reload for loading. */
394 enum insn_code reload_store
; /* INSN to reload for storing. */
395 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
396 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
397 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
398 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
399 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
402 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
404 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
406 mode_supports_pre_incdec_p (machine_mode mode
)
408 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
412 /* Helper function to say whether a mode supports PRE_MODIFY. */
414 mode_supports_pre_modify_p (machine_mode mode
)
416 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
421 /* Target cpu costs. */
423 struct processor_costs
{
424 const int mulsi
; /* cost of SImode multiplication. */
425 const int mulsi_const
; /* cost of SImode multiplication by constant. */
426 const int mulsi_const9
; /* cost of SImode mult by short constant. */
427 const int muldi
; /* cost of DImode multiplication. */
428 const int divsi
; /* cost of SImode division. */
429 const int divdi
; /* cost of DImode division. */
430 const int fp
; /* cost of simple SFmode and DFmode insns. */
431 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
432 const int sdiv
; /* cost of SFmode division (fdivs). */
433 const int ddiv
; /* cost of DFmode division (fdiv). */
434 const int cache_line_size
; /* cache line size in bytes. */
435 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
436 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
437 const int simultaneous_prefetches
; /* number of parallel prefetch
439 const int sfdf_convert
; /* cost of SF->DF conversion. */
442 const struct processor_costs
*rs6000_cost
;
444 /* Processor costs (relative to an add) */
446 /* Instruction size costs on 32bit processors. */
448 struct processor_costs size32_cost
= {
449 COSTS_N_INSNS (1), /* mulsi */
450 COSTS_N_INSNS (1), /* mulsi_const */
451 COSTS_N_INSNS (1), /* mulsi_const9 */
452 COSTS_N_INSNS (1), /* muldi */
453 COSTS_N_INSNS (1), /* divsi */
454 COSTS_N_INSNS (1), /* divdi */
455 COSTS_N_INSNS (1), /* fp */
456 COSTS_N_INSNS (1), /* dmul */
457 COSTS_N_INSNS (1), /* sdiv */
458 COSTS_N_INSNS (1), /* ddiv */
459 32, /* cache line size */
463 0, /* SF->DF convert */
466 /* Instruction size costs on 64bit processors. */
468 struct processor_costs size64_cost
= {
469 COSTS_N_INSNS (1), /* mulsi */
470 COSTS_N_INSNS (1), /* mulsi_const */
471 COSTS_N_INSNS (1), /* mulsi_const9 */
472 COSTS_N_INSNS (1), /* muldi */
473 COSTS_N_INSNS (1), /* divsi */
474 COSTS_N_INSNS (1), /* divdi */
475 COSTS_N_INSNS (1), /* fp */
476 COSTS_N_INSNS (1), /* dmul */
477 COSTS_N_INSNS (1), /* sdiv */
478 COSTS_N_INSNS (1), /* ddiv */
479 128, /* cache line size */
483 0, /* SF->DF convert */
486 /* Instruction costs on RS64A processors. */
488 struct processor_costs rs64a_cost
= {
489 COSTS_N_INSNS (20), /* mulsi */
490 COSTS_N_INSNS (12), /* mulsi_const */
491 COSTS_N_INSNS (8), /* mulsi_const9 */
492 COSTS_N_INSNS (34), /* muldi */
493 COSTS_N_INSNS (65), /* divsi */
494 COSTS_N_INSNS (67), /* divdi */
495 COSTS_N_INSNS (4), /* fp */
496 COSTS_N_INSNS (4), /* dmul */
497 COSTS_N_INSNS (31), /* sdiv */
498 COSTS_N_INSNS (31), /* ddiv */
499 128, /* cache line size */
503 0, /* SF->DF convert */
506 /* Instruction costs on MPCCORE processors. */
508 struct processor_costs mpccore_cost
= {
509 COSTS_N_INSNS (2), /* mulsi */
510 COSTS_N_INSNS (2), /* mulsi_const */
511 COSTS_N_INSNS (2), /* mulsi_const9 */
512 COSTS_N_INSNS (2), /* muldi */
513 COSTS_N_INSNS (6), /* divsi */
514 COSTS_N_INSNS (6), /* divdi */
515 COSTS_N_INSNS (4), /* fp */
516 COSTS_N_INSNS (5), /* dmul */
517 COSTS_N_INSNS (10), /* sdiv */
518 COSTS_N_INSNS (17), /* ddiv */
519 32, /* cache line size */
523 0, /* SF->DF convert */
526 /* Instruction costs on PPC403 processors. */
528 struct processor_costs ppc403_cost
= {
529 COSTS_N_INSNS (4), /* mulsi */
530 COSTS_N_INSNS (4), /* mulsi_const */
531 COSTS_N_INSNS (4), /* mulsi_const9 */
532 COSTS_N_INSNS (4), /* muldi */
533 COSTS_N_INSNS (33), /* divsi */
534 COSTS_N_INSNS (33), /* divdi */
535 COSTS_N_INSNS (11), /* fp */
536 COSTS_N_INSNS (11), /* dmul */
537 COSTS_N_INSNS (11), /* sdiv */
538 COSTS_N_INSNS (11), /* ddiv */
539 32, /* cache line size */
543 0, /* SF->DF convert */
546 /* Instruction costs on PPC405 processors. */
548 struct processor_costs ppc405_cost
= {
549 COSTS_N_INSNS (5), /* mulsi */
550 COSTS_N_INSNS (4), /* mulsi_const */
551 COSTS_N_INSNS (3), /* mulsi_const9 */
552 COSTS_N_INSNS (5), /* muldi */
553 COSTS_N_INSNS (35), /* divsi */
554 COSTS_N_INSNS (35), /* divdi */
555 COSTS_N_INSNS (11), /* fp */
556 COSTS_N_INSNS (11), /* dmul */
557 COSTS_N_INSNS (11), /* sdiv */
558 COSTS_N_INSNS (11), /* ddiv */
559 32, /* cache line size */
563 0, /* SF->DF convert */
566 /* Instruction costs on PPC440 processors. */
568 struct processor_costs ppc440_cost
= {
569 COSTS_N_INSNS (3), /* mulsi */
570 COSTS_N_INSNS (2), /* mulsi_const */
571 COSTS_N_INSNS (2), /* mulsi_const9 */
572 COSTS_N_INSNS (3), /* muldi */
573 COSTS_N_INSNS (34), /* divsi */
574 COSTS_N_INSNS (34), /* divdi */
575 COSTS_N_INSNS (5), /* fp */
576 COSTS_N_INSNS (5), /* dmul */
577 COSTS_N_INSNS (19), /* sdiv */
578 COSTS_N_INSNS (33), /* ddiv */
579 32, /* cache line size */
583 0, /* SF->DF convert */
586 /* Instruction costs on PPC476 processors. */
588 struct processor_costs ppc476_cost
= {
589 COSTS_N_INSNS (4), /* mulsi */
590 COSTS_N_INSNS (4), /* mulsi_const */
591 COSTS_N_INSNS (4), /* mulsi_const9 */
592 COSTS_N_INSNS (4), /* muldi */
593 COSTS_N_INSNS (11), /* divsi */
594 COSTS_N_INSNS (11), /* divdi */
595 COSTS_N_INSNS (6), /* fp */
596 COSTS_N_INSNS (6), /* dmul */
597 COSTS_N_INSNS (19), /* sdiv */
598 COSTS_N_INSNS (33), /* ddiv */
599 32, /* l1 cache line size */
603 0, /* SF->DF convert */
606 /* Instruction costs on PPC601 processors. */
608 struct processor_costs ppc601_cost
= {
609 COSTS_N_INSNS (5), /* mulsi */
610 COSTS_N_INSNS (5), /* mulsi_const */
611 COSTS_N_INSNS (5), /* mulsi_const9 */
612 COSTS_N_INSNS (5), /* muldi */
613 COSTS_N_INSNS (36), /* divsi */
614 COSTS_N_INSNS (36), /* divdi */
615 COSTS_N_INSNS (4), /* fp */
616 COSTS_N_INSNS (5), /* dmul */
617 COSTS_N_INSNS (17), /* sdiv */
618 COSTS_N_INSNS (31), /* ddiv */
619 32, /* cache line size */
623 0, /* SF->DF convert */
626 /* Instruction costs on PPC603 processors. */
628 struct processor_costs ppc603_cost
= {
629 COSTS_N_INSNS (5), /* mulsi */
630 COSTS_N_INSNS (3), /* mulsi_const */
631 COSTS_N_INSNS (2), /* mulsi_const9 */
632 COSTS_N_INSNS (5), /* muldi */
633 COSTS_N_INSNS (37), /* divsi */
634 COSTS_N_INSNS (37), /* divdi */
635 COSTS_N_INSNS (3), /* fp */
636 COSTS_N_INSNS (4), /* dmul */
637 COSTS_N_INSNS (18), /* sdiv */
638 COSTS_N_INSNS (33), /* ddiv */
639 32, /* cache line size */
643 0, /* SF->DF convert */
646 /* Instruction costs on PPC604 processors. */
648 struct processor_costs ppc604_cost
= {
649 COSTS_N_INSNS (4), /* mulsi */
650 COSTS_N_INSNS (4), /* mulsi_const */
651 COSTS_N_INSNS (4), /* mulsi_const9 */
652 COSTS_N_INSNS (4), /* muldi */
653 COSTS_N_INSNS (20), /* divsi */
654 COSTS_N_INSNS (20), /* divdi */
655 COSTS_N_INSNS (3), /* fp */
656 COSTS_N_INSNS (3), /* dmul */
657 COSTS_N_INSNS (18), /* sdiv */
658 COSTS_N_INSNS (32), /* ddiv */
659 32, /* cache line size */
663 0, /* SF->DF convert */
666 /* Instruction costs on PPC604e processors. */
668 struct processor_costs ppc604e_cost
= {
669 COSTS_N_INSNS (2), /* mulsi */
670 COSTS_N_INSNS (2), /* mulsi_const */
671 COSTS_N_INSNS (2), /* mulsi_const9 */
672 COSTS_N_INSNS (2), /* muldi */
673 COSTS_N_INSNS (20), /* divsi */
674 COSTS_N_INSNS (20), /* divdi */
675 COSTS_N_INSNS (3), /* fp */
676 COSTS_N_INSNS (3), /* dmul */
677 COSTS_N_INSNS (18), /* sdiv */
678 COSTS_N_INSNS (32), /* ddiv */
679 32, /* cache line size */
683 0, /* SF->DF convert */
686 /* Instruction costs on PPC620 processors. */
688 struct processor_costs ppc620_cost
= {
689 COSTS_N_INSNS (5), /* mulsi */
690 COSTS_N_INSNS (4), /* mulsi_const */
691 COSTS_N_INSNS (3), /* mulsi_const9 */
692 COSTS_N_INSNS (7), /* muldi */
693 COSTS_N_INSNS (21), /* divsi */
694 COSTS_N_INSNS (37), /* divdi */
695 COSTS_N_INSNS (3), /* fp */
696 COSTS_N_INSNS (3), /* dmul */
697 COSTS_N_INSNS (18), /* sdiv */
698 COSTS_N_INSNS (32), /* ddiv */
699 128, /* cache line size */
703 0, /* SF->DF convert */
706 /* Instruction costs on PPC630 processors. */
708 struct processor_costs ppc630_cost
= {
709 COSTS_N_INSNS (5), /* mulsi */
710 COSTS_N_INSNS (4), /* mulsi_const */
711 COSTS_N_INSNS (3), /* mulsi_const9 */
712 COSTS_N_INSNS (7), /* muldi */
713 COSTS_N_INSNS (21), /* divsi */
714 COSTS_N_INSNS (37), /* divdi */
715 COSTS_N_INSNS (3), /* fp */
716 COSTS_N_INSNS (3), /* dmul */
717 COSTS_N_INSNS (17), /* sdiv */
718 COSTS_N_INSNS (21), /* ddiv */
719 128, /* cache line size */
723 0, /* SF->DF convert */
726 /* Instruction costs on Cell processor. */
727 /* COSTS_N_INSNS (1) ~ one add. */
729 struct processor_costs ppccell_cost
= {
730 COSTS_N_INSNS (9/2)+2, /* mulsi */
731 COSTS_N_INSNS (6/2), /* mulsi_const */
732 COSTS_N_INSNS (6/2), /* mulsi_const9 */
733 COSTS_N_INSNS (15/2)+2, /* muldi */
734 COSTS_N_INSNS (38/2), /* divsi */
735 COSTS_N_INSNS (70/2), /* divdi */
736 COSTS_N_INSNS (10/2), /* fp */
737 COSTS_N_INSNS (10/2), /* dmul */
738 COSTS_N_INSNS (74/2), /* sdiv */
739 COSTS_N_INSNS (74/2), /* ddiv */
740 128, /* cache line size */
744 0, /* SF->DF convert */
747 /* Instruction costs on PPC750 and PPC7400 processors. */
749 struct processor_costs ppc750_cost
= {
750 COSTS_N_INSNS (5), /* mulsi */
751 COSTS_N_INSNS (3), /* mulsi_const */
752 COSTS_N_INSNS (2), /* mulsi_const9 */
753 COSTS_N_INSNS (5), /* muldi */
754 COSTS_N_INSNS (17), /* divsi */
755 COSTS_N_INSNS (17), /* divdi */
756 COSTS_N_INSNS (3), /* fp */
757 COSTS_N_INSNS (3), /* dmul */
758 COSTS_N_INSNS (17), /* sdiv */
759 COSTS_N_INSNS (31), /* ddiv */
760 32, /* cache line size */
764 0, /* SF->DF convert */
767 /* Instruction costs on PPC7450 processors. */
769 struct processor_costs ppc7450_cost
= {
770 COSTS_N_INSNS (4), /* mulsi */
771 COSTS_N_INSNS (3), /* mulsi_const */
772 COSTS_N_INSNS (3), /* mulsi_const9 */
773 COSTS_N_INSNS (4), /* muldi */
774 COSTS_N_INSNS (23), /* divsi */
775 COSTS_N_INSNS (23), /* divdi */
776 COSTS_N_INSNS (5), /* fp */
777 COSTS_N_INSNS (5), /* dmul */
778 COSTS_N_INSNS (21), /* sdiv */
779 COSTS_N_INSNS (35), /* ddiv */
780 32, /* cache line size */
784 0, /* SF->DF convert */
787 /* Instruction costs on PPC8540 processors. */
789 struct processor_costs ppc8540_cost
= {
790 COSTS_N_INSNS (4), /* mulsi */
791 COSTS_N_INSNS (4), /* mulsi_const */
792 COSTS_N_INSNS (4), /* mulsi_const9 */
793 COSTS_N_INSNS (4), /* muldi */
794 COSTS_N_INSNS (19), /* divsi */
795 COSTS_N_INSNS (19), /* divdi */
796 COSTS_N_INSNS (4), /* fp */
797 COSTS_N_INSNS (4), /* dmul */
798 COSTS_N_INSNS (29), /* sdiv */
799 COSTS_N_INSNS (29), /* ddiv */
800 32, /* cache line size */
803 1, /* prefetch streams /*/
804 0, /* SF->DF convert */
807 /* Instruction costs on E300C2 and E300C3 cores. */
809 struct processor_costs ppce300c2c3_cost
= {
810 COSTS_N_INSNS (4), /* mulsi */
811 COSTS_N_INSNS (4), /* mulsi_const */
812 COSTS_N_INSNS (4), /* mulsi_const9 */
813 COSTS_N_INSNS (4), /* muldi */
814 COSTS_N_INSNS (19), /* divsi */
815 COSTS_N_INSNS (19), /* divdi */
816 COSTS_N_INSNS (3), /* fp */
817 COSTS_N_INSNS (4), /* dmul */
818 COSTS_N_INSNS (18), /* sdiv */
819 COSTS_N_INSNS (33), /* ddiv */
823 1, /* prefetch streams /*/
824 0, /* SF->DF convert */
827 /* Instruction costs on PPCE500MC processors. */
829 struct processor_costs ppce500mc_cost
= {
830 COSTS_N_INSNS (4), /* mulsi */
831 COSTS_N_INSNS (4), /* mulsi_const */
832 COSTS_N_INSNS (4), /* mulsi_const9 */
833 COSTS_N_INSNS (4), /* muldi */
834 COSTS_N_INSNS (14), /* divsi */
835 COSTS_N_INSNS (14), /* divdi */
836 COSTS_N_INSNS (8), /* fp */
837 COSTS_N_INSNS (10), /* dmul */
838 COSTS_N_INSNS (36), /* sdiv */
839 COSTS_N_INSNS (66), /* ddiv */
840 64, /* cache line size */
843 1, /* prefetch streams /*/
844 0, /* SF->DF convert */
847 /* Instruction costs on PPCE500MC64 processors. */
849 struct processor_costs ppce500mc64_cost
= {
850 COSTS_N_INSNS (4), /* mulsi */
851 COSTS_N_INSNS (4), /* mulsi_const */
852 COSTS_N_INSNS (4), /* mulsi_const9 */
853 COSTS_N_INSNS (4), /* muldi */
854 COSTS_N_INSNS (14), /* divsi */
855 COSTS_N_INSNS (14), /* divdi */
856 COSTS_N_INSNS (4), /* fp */
857 COSTS_N_INSNS (10), /* dmul */
858 COSTS_N_INSNS (36), /* sdiv */
859 COSTS_N_INSNS (66), /* ddiv */
860 64, /* cache line size */
863 1, /* prefetch streams /*/
864 0, /* SF->DF convert */
867 /* Instruction costs on PPCE5500 processors. */
869 struct processor_costs ppce5500_cost
= {
870 COSTS_N_INSNS (5), /* mulsi */
871 COSTS_N_INSNS (5), /* mulsi_const */
872 COSTS_N_INSNS (4), /* mulsi_const9 */
873 COSTS_N_INSNS (5), /* muldi */
874 COSTS_N_INSNS (14), /* divsi */
875 COSTS_N_INSNS (14), /* divdi */
876 COSTS_N_INSNS (7), /* fp */
877 COSTS_N_INSNS (10), /* dmul */
878 COSTS_N_INSNS (36), /* sdiv */
879 COSTS_N_INSNS (66), /* ddiv */
880 64, /* cache line size */
883 1, /* prefetch streams /*/
884 0, /* SF->DF convert */
887 /* Instruction costs on PPCE6500 processors. */
889 struct processor_costs ppce6500_cost
= {
890 COSTS_N_INSNS (5), /* mulsi */
891 COSTS_N_INSNS (5), /* mulsi_const */
892 COSTS_N_INSNS (4), /* mulsi_const9 */
893 COSTS_N_INSNS (5), /* muldi */
894 COSTS_N_INSNS (14), /* divsi */
895 COSTS_N_INSNS (14), /* divdi */
896 COSTS_N_INSNS (7), /* fp */
897 COSTS_N_INSNS (10), /* dmul */
898 COSTS_N_INSNS (36), /* sdiv */
899 COSTS_N_INSNS (66), /* ddiv */
900 64, /* cache line size */
903 1, /* prefetch streams /*/
904 0, /* SF->DF convert */
907 /* Instruction costs on AppliedMicro Titan processors. */
909 struct processor_costs titan_cost
= {
910 COSTS_N_INSNS (5), /* mulsi */
911 COSTS_N_INSNS (5), /* mulsi_const */
912 COSTS_N_INSNS (5), /* mulsi_const9 */
913 COSTS_N_INSNS (5), /* muldi */
914 COSTS_N_INSNS (18), /* divsi */
915 COSTS_N_INSNS (18), /* divdi */
916 COSTS_N_INSNS (10), /* fp */
917 COSTS_N_INSNS (10), /* dmul */
918 COSTS_N_INSNS (46), /* sdiv */
919 COSTS_N_INSNS (72), /* ddiv */
920 32, /* cache line size */
923 1, /* prefetch streams /*/
924 0, /* SF->DF convert */
927 /* Instruction costs on POWER4 and POWER5 processors. */
929 struct processor_costs power4_cost
= {
930 COSTS_N_INSNS (3), /* mulsi */
931 COSTS_N_INSNS (2), /* mulsi_const */
932 COSTS_N_INSNS (2), /* mulsi_const9 */
933 COSTS_N_INSNS (4), /* muldi */
934 COSTS_N_INSNS (18), /* divsi */
935 COSTS_N_INSNS (34), /* divdi */
936 COSTS_N_INSNS (3), /* fp */
937 COSTS_N_INSNS (3), /* dmul */
938 COSTS_N_INSNS (17), /* sdiv */
939 COSTS_N_INSNS (17), /* ddiv */
940 128, /* cache line size */
943 8, /* prefetch streams /*/
944 0, /* SF->DF convert */
947 /* Instruction costs on POWER6 processors. */
949 struct processor_costs power6_cost
= {
950 COSTS_N_INSNS (8), /* mulsi */
951 COSTS_N_INSNS (8), /* mulsi_const */
952 COSTS_N_INSNS (8), /* mulsi_const9 */
953 COSTS_N_INSNS (8), /* muldi */
954 COSTS_N_INSNS (22), /* divsi */
955 COSTS_N_INSNS (28), /* divdi */
956 COSTS_N_INSNS (3), /* fp */
957 COSTS_N_INSNS (3), /* dmul */
958 COSTS_N_INSNS (13), /* sdiv */
959 COSTS_N_INSNS (16), /* ddiv */
960 128, /* cache line size */
963 16, /* prefetch streams */
964 0, /* SF->DF convert */
967 /* Instruction costs on POWER7 processors. */
969 struct processor_costs power7_cost
= {
970 COSTS_N_INSNS (2), /* mulsi */
971 COSTS_N_INSNS (2), /* mulsi_const */
972 COSTS_N_INSNS (2), /* mulsi_const9 */
973 COSTS_N_INSNS (2), /* muldi */
974 COSTS_N_INSNS (18), /* divsi */
975 COSTS_N_INSNS (34), /* divdi */
976 COSTS_N_INSNS (3), /* fp */
977 COSTS_N_INSNS (3), /* dmul */
978 COSTS_N_INSNS (13), /* sdiv */
979 COSTS_N_INSNS (16), /* ddiv */
980 128, /* cache line size */
983 12, /* prefetch streams */
984 COSTS_N_INSNS (3), /* SF->DF convert */
987 /* Instruction costs on POWER8 processors. */
989 struct processor_costs power8_cost
= {
990 COSTS_N_INSNS (3), /* mulsi */
991 COSTS_N_INSNS (3), /* mulsi_const */
992 COSTS_N_INSNS (3), /* mulsi_const9 */
993 COSTS_N_INSNS (3), /* muldi */
994 COSTS_N_INSNS (19), /* divsi */
995 COSTS_N_INSNS (35), /* divdi */
996 COSTS_N_INSNS (3), /* fp */
997 COSTS_N_INSNS (3), /* dmul */
998 COSTS_N_INSNS (14), /* sdiv */
999 COSTS_N_INSNS (17), /* ddiv */
1000 128, /* cache line size */
1003 12, /* prefetch streams */
1004 COSTS_N_INSNS (3), /* SF->DF convert */
1007 /* Instruction costs on POWER A2 processors. */
1009 struct processor_costs ppca2_cost
= {
1010 COSTS_N_INSNS (16), /* mulsi */
1011 COSTS_N_INSNS (16), /* mulsi_const */
1012 COSTS_N_INSNS (16), /* mulsi_const9 */
1013 COSTS_N_INSNS (16), /* muldi */
1014 COSTS_N_INSNS (22), /* divsi */
1015 COSTS_N_INSNS (28), /* divdi */
1016 COSTS_N_INSNS (3), /* fp */
1017 COSTS_N_INSNS (3), /* dmul */
1018 COSTS_N_INSNS (59), /* sdiv */
1019 COSTS_N_INSNS (72), /* ddiv */
1022 2048, /* l2 cache */
1023 16, /* prefetch streams */
1024 0, /* SF->DF convert */
1028 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1029 #undef RS6000_BUILTIN_1
1030 #undef RS6000_BUILTIN_2
1031 #undef RS6000_BUILTIN_3
1032 #undef RS6000_BUILTIN_A
1033 #undef RS6000_BUILTIN_D
1034 #undef RS6000_BUILTIN_E
1035 #undef RS6000_BUILTIN_H
1036 #undef RS6000_BUILTIN_P
1037 #undef RS6000_BUILTIN_Q
1038 #undef RS6000_BUILTIN_S
1039 #undef RS6000_BUILTIN_X
1041 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1042 { NAME, ICODE, MASK, ATTR },
1044 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1045 { NAME, ICODE, MASK, ATTR },
1047 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1048 { NAME, ICODE, MASK, ATTR },
1050 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1051 { NAME, ICODE, MASK, ATTR },
1053 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1054 { NAME, ICODE, MASK, ATTR },
1056 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1057 { NAME, ICODE, MASK, ATTR },
1059 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1060 { NAME, ICODE, MASK, ATTR },
1062 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1063 { NAME, ICODE, MASK, ATTR },
1065 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1066 { NAME, ICODE, MASK, ATTR },
1068 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1069 { NAME, ICODE, MASK, ATTR },
1071 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1072 { NAME, ICODE, MASK, ATTR },
1074 struct rs6000_builtin_info_type
{
1076 const enum insn_code icode
;
1077 const HOST_WIDE_INT mask
;
1078 const unsigned attr
;
1081 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1083 #include "rs6000-builtin.def"
1086 #undef RS6000_BUILTIN_1
1087 #undef RS6000_BUILTIN_2
1088 #undef RS6000_BUILTIN_3
1089 #undef RS6000_BUILTIN_A
1090 #undef RS6000_BUILTIN_D
1091 #undef RS6000_BUILTIN_E
1092 #undef RS6000_BUILTIN_H
1093 #undef RS6000_BUILTIN_P
1094 #undef RS6000_BUILTIN_Q
1095 #undef RS6000_BUILTIN_S
1096 #undef RS6000_BUILTIN_X
1098 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1099 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1102 static bool rs6000_debug_legitimate_address_p (machine_mode
, rtx
, bool);
1103 static bool spe_func_has_64bit_regs_p (void);
1104 static struct machine_function
* rs6000_init_machine_status (void);
1105 static int rs6000_ra_ever_killed (void);
1106 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1107 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1108 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1109 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1110 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1111 static int rs6000_memory_move_cost (machine_mode
, reg_class_t
, bool);
1112 static bool rs6000_debug_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
1113 static int rs6000_debug_address_cost (rtx
, machine_mode
, addr_space_t
,
1115 static int rs6000_debug_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
1116 static bool is_microcoded_insn (rtx_insn
*);
1117 static bool is_nonpipeline_insn (rtx_insn
*);
1118 static bool is_cracked_insn (rtx_insn
*);
1119 static bool is_load_insn (rtx
, rtx
*);
1120 static bool is_store_insn (rtx
, rtx
*);
1121 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1122 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1123 static bool insn_must_be_first_in_group (rtx_insn
*);
1124 static bool insn_must_be_last_in_group (rtx_insn
*);
1125 static void altivec_init_builtins (void);
1126 static tree
builtin_function_type (machine_mode
, machine_mode
,
1127 machine_mode
, machine_mode
,
1128 enum rs6000_builtins
, const char *name
);
1129 static void rs6000_common_init_builtins (void);
1130 static void paired_init_builtins (void);
1131 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1132 static void spe_init_builtins (void);
1133 static void htm_init_builtins (void);
1134 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1135 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1136 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1137 static rs6000_stack_t
*rs6000_stack_info (void);
1138 static void is_altivec_return_reg (rtx
, void *);
1139 int easy_vector_constant (rtx
, machine_mode
);
1140 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, machine_mode
);
1141 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1142 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1145 static void macho_branch_islands (void);
1147 static rtx
rs6000_legitimize_reload_address (rtx
, machine_mode
, int, int,
1149 static rtx
rs6000_debug_legitimize_reload_address (rtx
, machine_mode
, int,
1151 static bool rs6000_mode_dependent_address (const_rtx
);
1152 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1153 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1155 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1158 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1159 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1161 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1163 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1166 static bool rs6000_cannot_change_mode_class (machine_mode
,
1169 static bool rs6000_debug_cannot_change_mode_class (machine_mode
,
1172 static bool rs6000_save_toc_in_prologue_p (void);
1173 static rtx
rs6000_internal_arg_pointer (void);
1175 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, machine_mode
, int, int,
1177 = rs6000_legitimize_reload_address
;
1179 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1180 = rs6000_mode_dependent_address
;
1182 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1184 = rs6000_secondary_reload_class
;
1186 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1187 = rs6000_preferred_reload_class
;
1189 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1191 = rs6000_secondary_memory_needed
;
1193 bool (*rs6000_cannot_change_mode_class_ptr
) (machine_mode
,
1196 = rs6000_cannot_change_mode_class
;
1198 const int INSN_NOT_AVAILABLE
= -1;
1200 static void rs6000_print_isa_options (FILE *, int, const char *,
1202 static void rs6000_print_builtin_options (FILE *, int, const char *,
1205 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1206 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1207 enum rs6000_reg_type
,
1209 secondary_reload_info
*,
1211 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1213 /* Hash table stuff for keeping track of TOC entries. */
1215 struct GTY((for_user
)) toc_hash_struct
1217 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1218 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1220 machine_mode key_mode
;
1224 struct toc_hasher
: ggc_ptr_hash
<toc_hash_struct
>
1226 static hashval_t
hash (toc_hash_struct
*);
1227 static bool equal (toc_hash_struct
*, toc_hash_struct
*);
1230 static GTY (()) hash_table
<toc_hasher
> *toc_hash_table
;
1232 /* Hash table to keep track of the argument types for builtin functions. */
1234 struct GTY((for_user
)) builtin_hash_struct
1237 machine_mode mode
[4]; /* return value + 3 arguments. */
1238 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1241 struct builtin_hasher
: ggc_ptr_hash
<builtin_hash_struct
>
1243 static hashval_t
hash (builtin_hash_struct
*);
1244 static bool equal (builtin_hash_struct
*, builtin_hash_struct
*);
1247 static GTY (()) hash_table
<builtin_hasher
> *builtin_hash_table
;
1250 /* Default register names. */
1251 char rs6000_reg_names
[][8] =
1253 "0", "1", "2", "3", "4", "5", "6", "7",
1254 "8", "9", "10", "11", "12", "13", "14", "15",
1255 "16", "17", "18", "19", "20", "21", "22", "23",
1256 "24", "25", "26", "27", "28", "29", "30", "31",
1257 "0", "1", "2", "3", "4", "5", "6", "7",
1258 "8", "9", "10", "11", "12", "13", "14", "15",
1259 "16", "17", "18", "19", "20", "21", "22", "23",
1260 "24", "25", "26", "27", "28", "29", "30", "31",
1261 "mq", "lr", "ctr","ap",
1262 "0", "1", "2", "3", "4", "5", "6", "7",
1264 /* AltiVec registers. */
1265 "0", "1", "2", "3", "4", "5", "6", "7",
1266 "8", "9", "10", "11", "12", "13", "14", "15",
1267 "16", "17", "18", "19", "20", "21", "22", "23",
1268 "24", "25", "26", "27", "28", "29", "30", "31",
1270 /* SPE registers. */
1271 "spe_acc", "spefscr",
1272 /* Soft frame pointer. */
1274 /* HTM SPR registers. */
1275 "tfhar", "tfiar", "texasr",
1276 /* SPE High registers. */
1277 "0", "1", "2", "3", "4", "5", "6", "7",
1278 "8", "9", "10", "11", "12", "13", "14", "15",
1279 "16", "17", "18", "19", "20", "21", "22", "23",
1280 "24", "25", "26", "27", "28", "29", "30", "31"
1283 #ifdef TARGET_REGNAMES
1284 static const char alt_reg_names
[][8] =
1286 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1287 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1288 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1289 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1290 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1291 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1292 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1293 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1294 "mq", "lr", "ctr", "ap",
1295 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1297 /* AltiVec registers. */
1298 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1299 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1300 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1301 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1303 /* SPE registers. */
1304 "spe_acc", "spefscr",
1305 /* Soft frame pointer. */
1307 /* HTM SPR registers. */
1308 "tfhar", "tfiar", "texasr",
1309 /* SPE High registers. */
1310 "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
1311 "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
1312 "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
1313 "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
1317 /* Table of valid machine attributes. */
1319 static const struct attribute_spec rs6000_attribute_table
[] =
1321 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1322 affects_type_identity } */
1323 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1325 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1327 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1329 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1331 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1333 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1334 SUBTARGET_ATTRIBUTE_TABLE
,
1336 { NULL
, 0, 0, false, false, false, NULL
, false }
1339 #ifndef TARGET_PROFILE_KERNEL
1340 #define TARGET_PROFILE_KERNEL 0
1343 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1344 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1346 /* Initialize the GCC target structure. */
1347 #undef TARGET_ATTRIBUTE_TABLE
1348 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1349 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1350 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1351 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1352 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1354 #undef TARGET_ASM_ALIGNED_DI_OP
1355 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1357 /* Default unaligned ops are only provided for ELF. Find the ops needed
1358 for non-ELF systems. */
1359 #ifndef OBJECT_FORMAT_ELF
1361 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1363 #undef TARGET_ASM_UNALIGNED_HI_OP
1364 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1365 #undef TARGET_ASM_UNALIGNED_SI_OP
1366 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1367 #undef TARGET_ASM_UNALIGNED_DI_OP
1368 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1371 #undef TARGET_ASM_UNALIGNED_HI_OP
1372 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1373 #undef TARGET_ASM_UNALIGNED_SI_OP
1374 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1375 #undef TARGET_ASM_UNALIGNED_DI_OP
1376 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1377 #undef TARGET_ASM_ALIGNED_DI_OP
1378 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1382 /* This hook deals with fixups for relocatable code and DI-mode objects
1384 #undef TARGET_ASM_INTEGER
1385 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1387 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1388 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1389 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1392 #undef TARGET_SET_UP_BY_PROLOGUE
1393 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1395 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1396 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1398 #undef TARGET_INTERNAL_ARG_POINTER
1399 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1401 #undef TARGET_HAVE_TLS
1402 #define TARGET_HAVE_TLS HAVE_AS_TLS
1404 #undef TARGET_CANNOT_FORCE_CONST_MEM
1405 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1407 #undef TARGET_DELEGITIMIZE_ADDRESS
1408 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1410 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1411 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1413 #undef TARGET_ASM_FUNCTION_PROLOGUE
1414 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1415 #undef TARGET_ASM_FUNCTION_EPILOGUE
1416 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1418 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1419 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1421 #undef TARGET_LEGITIMIZE_ADDRESS
1422 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1424 #undef TARGET_SCHED_VARIABLE_ISSUE
1425 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1427 #undef TARGET_SCHED_ISSUE_RATE
1428 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1429 #undef TARGET_SCHED_ADJUST_COST
1430 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1431 #undef TARGET_SCHED_ADJUST_PRIORITY
1432 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1433 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1434 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1435 #undef TARGET_SCHED_INIT
1436 #define TARGET_SCHED_INIT rs6000_sched_init
1437 #undef TARGET_SCHED_FINISH
1438 #define TARGET_SCHED_FINISH rs6000_sched_finish
1439 #undef TARGET_SCHED_REORDER
1440 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1441 #undef TARGET_SCHED_REORDER2
1442 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1444 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1445 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1447 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1448 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1450 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1451 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1452 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1453 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1454 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1455 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1456 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1457 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1459 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1460 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1461 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1462 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1463 rs6000_builtin_support_vector_misalignment
1464 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1465 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1466 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1467 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1468 rs6000_builtin_vectorization_cost
1469 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1470 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1471 rs6000_preferred_simd_mode
1472 #undef TARGET_VECTORIZE_INIT_COST
1473 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1474 #undef TARGET_VECTORIZE_ADD_STMT_COST
1475 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1476 #undef TARGET_VECTORIZE_FINISH_COST
1477 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1478 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1479 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1481 #undef TARGET_INIT_BUILTINS
1482 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1483 #undef TARGET_BUILTIN_DECL
1484 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1486 #undef TARGET_EXPAND_BUILTIN
1487 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1489 #undef TARGET_MANGLE_TYPE
1490 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1492 #undef TARGET_INIT_LIBFUNCS
1493 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1496 #undef TARGET_BINDS_LOCAL_P
1497 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1500 #undef TARGET_MS_BITFIELD_LAYOUT_P
1501 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1503 #undef TARGET_ASM_OUTPUT_MI_THUNK
1504 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1506 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1507 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1509 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1510 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1512 #undef TARGET_REGISTER_MOVE_COST
1513 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1514 #undef TARGET_MEMORY_MOVE_COST
1515 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1516 #undef TARGET_RTX_COSTS
1517 #define TARGET_RTX_COSTS rs6000_rtx_costs
1518 #undef TARGET_ADDRESS_COST
1519 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1521 #undef TARGET_DWARF_REGISTER_SPAN
1522 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1524 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1525 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1527 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1528 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1530 #undef TARGET_PROMOTE_FUNCTION_MODE
1531 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1533 #undef TARGET_RETURN_IN_MEMORY
1534 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1536 #undef TARGET_RETURN_IN_MSB
1537 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1539 #undef TARGET_SETUP_INCOMING_VARARGS
1540 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1542 /* Always strict argument naming on rs6000. */
1543 #undef TARGET_STRICT_ARGUMENT_NAMING
1544 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1545 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1546 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1547 #undef TARGET_SPLIT_COMPLEX_ARG
1548 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1549 #undef TARGET_MUST_PASS_IN_STACK
1550 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1551 #undef TARGET_PASS_BY_REFERENCE
1552 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1553 #undef TARGET_ARG_PARTIAL_BYTES
1554 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1555 #undef TARGET_FUNCTION_ARG_ADVANCE
1556 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1557 #undef TARGET_FUNCTION_ARG
1558 #define TARGET_FUNCTION_ARG rs6000_function_arg
1559 #undef TARGET_FUNCTION_ARG_BOUNDARY
1560 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1562 #undef TARGET_BUILD_BUILTIN_VA_LIST
1563 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1565 #undef TARGET_EXPAND_BUILTIN_VA_START
1566 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1568 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1569 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1571 #undef TARGET_EH_RETURN_FILTER_MODE
1572 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1574 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1575 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1577 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1578 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1580 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1581 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1583 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1584 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1586 #undef TARGET_MD_ASM_ADJUST
1587 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1589 #undef TARGET_OPTION_OVERRIDE
1590 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1592 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1593 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1594 rs6000_builtin_vectorized_function
1597 #undef TARGET_STACK_PROTECT_FAIL
1598 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1602 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1603 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1606 /* Use a 32-bit anchor range. This leads to sequences like:
1608 addis tmp,anchor,high
1611 where tmp itself acts as an anchor, and can be shared between
1612 accesses to the same 64k page. */
1613 #undef TARGET_MIN_ANCHOR_OFFSET
1614 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1615 #undef TARGET_MAX_ANCHOR_OFFSET
1616 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1617 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1618 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1619 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1620 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1622 #undef TARGET_BUILTIN_RECIPROCAL
1623 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1625 #undef TARGET_EXPAND_TO_RTL_HOOK
1626 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1628 #undef TARGET_INSTANTIATE_DECLS
1629 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1631 #undef TARGET_SECONDARY_RELOAD
1632 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1634 #undef TARGET_LEGITIMATE_ADDRESS_P
1635 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1637 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1638 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1641 #define TARGET_LRA_P rs6000_lra_p
1643 #undef TARGET_CAN_ELIMINATE
1644 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1646 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1647 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1649 #undef TARGET_TRAMPOLINE_INIT
1650 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1652 #undef TARGET_FUNCTION_VALUE
1653 #define TARGET_FUNCTION_VALUE rs6000_function_value
1655 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1656 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1658 #undef TARGET_OPTION_SAVE
1659 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1661 #undef TARGET_OPTION_RESTORE
1662 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1664 #undef TARGET_OPTION_PRINT
1665 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1667 #undef TARGET_CAN_INLINE_P
1668 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1670 #undef TARGET_SET_CURRENT_FUNCTION
1671 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1673 #undef TARGET_LEGITIMATE_CONSTANT_P
1674 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1676 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1677 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1679 #undef TARGET_CAN_USE_DOLOOP_P
1680 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1682 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1683 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1685 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1686 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1687 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1688 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1689 #undef TARGET_UNWIND_WORD_MODE
1690 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1693 /* Processor table. */
1696 const char *const name
; /* Canonical processor name. */
1697 const enum processor_type processor
; /* Processor type enum value. */
1698 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1701 static struct rs6000_ptt
const processor_target_table
[] =
1703 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1704 #include "rs6000-cpus.def"
1708 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1712 rs6000_cpu_name_lookup (const char *name
)
1718 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1719 if (! strcmp (name
, processor_target_table
[i
].name
))
1727 /* Return number of consecutive hard regs needed starting at reg REGNO
1728 to hold something of mode MODE.
1729 This is ordinarily the length in words of a value of mode MODE
1730 but can be less for certain modes in special long registers.
1732 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1733 scalar instructions. The upper 32 bits are only available to the
1736 POWER and PowerPC GPRs hold 32 bits worth;
1737 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1740 rs6000_hard_regno_nregs_internal (int regno
, machine_mode mode
)
1742 unsigned HOST_WIDE_INT reg_size
;
1744 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
1745 128-bit floating point that can go in vector registers, which has VSX
1746 memory addressing. */
1747 if (FP_REGNO_P (regno
))
1748 reg_size
= (VECTOR_MEM_VSX_P (mode
)
1749 ? UNITS_PER_VSX_WORD
1750 : UNITS_PER_FP_WORD
);
1752 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1753 reg_size
= UNITS_PER_SPE_WORD
;
1755 else if (ALTIVEC_REGNO_P (regno
))
1756 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1758 /* The value returned for SCmode in the E500 double case is 2 for
1759 ABI compatibility; storing an SCmode value in a single register
1760 would require function_arg and rs6000_spe_function_arg to handle
1761 SCmode so as to pass the value correctly in a pair of
1763 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1764 && !DECIMAL_FLOAT_MODE_P (mode
) && SPE_SIMD_REGNO_P (regno
))
1765 reg_size
= UNITS_PER_FP_WORD
;
1768 reg_size
= UNITS_PER_WORD
;
1770 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1773 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1776 rs6000_hard_regno_mode_ok (int regno
, machine_mode mode
)
1778 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1780 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1781 register combinations, and use PTImode where we need to deal with quad
1782 word memory operations. Don't allow quad words in the argument or frame
1783 pointer registers, just registers 0..31. */
1784 if (mode
== PTImode
)
1785 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1786 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1787 && ((regno
& 1) == 0));
1789 /* If we don't allow 128-bit binary floating point, disallow the 128-bit
1790 types from going in any registers. Similarly if __float128 is not
1791 supported, don't allow __float128/__ibm128 types. */
1792 if (!TARGET_LONG_DOUBLE_128
1793 && (mode
== TFmode
|| mode
== KFmode
|| mode
== IFmode
))
1796 if (!TARGET_FLOAT128
&& (mode
== KFmode
|| mode
== IFmode
))
1799 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1800 implementations. Don't allow an item to be split between a FP register
1801 and an Altivec register. Allow TImode in all VSX registers if the user
1803 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1804 && (VECTOR_MEM_VSX_P (mode
)
1805 || FLOAT128_VECTOR_P (mode
)
1806 || reg_addr
[mode
].scalar_in_vmx_p
1807 || (TARGET_VSX_TIMODE
&& mode
== TImode
)
1808 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
1810 if (FP_REGNO_P (regno
))
1811 return FP_REGNO_P (last_regno
);
1813 if (ALTIVEC_REGNO_P (regno
))
1815 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
1818 return ALTIVEC_REGNO_P (last_regno
);
1822 /* The GPRs can hold any mode, but values bigger than one register
1823 cannot go past R31. */
1824 if (INT_REGNO_P (regno
))
1825 return INT_REGNO_P (last_regno
);
1827 /* The float registers (except for VSX vector modes) can only hold floating
1828 modes and DImode. */
1829 if (FP_REGNO_P (regno
))
1831 if (FLOAT128_VECTOR_P (mode
))
1834 if (SCALAR_FLOAT_MODE_P (mode
)
1835 && (mode
!= TDmode
|| (regno
% 2) == 0)
1836 && FP_REGNO_P (last_regno
))
1839 if (GET_MODE_CLASS (mode
) == MODE_INT
1840 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1843 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1844 && PAIRED_VECTOR_MODE (mode
))
1850 /* The CR register can only hold CC modes. */
1851 if (CR_REGNO_P (regno
))
1852 return GET_MODE_CLASS (mode
) == MODE_CC
;
1854 if (CA_REGNO_P (regno
))
1855 return mode
== Pmode
|| mode
== SImode
;
1857 /* AltiVec only in AldyVec registers. */
1858 if (ALTIVEC_REGNO_P (regno
))
1859 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
1860 || mode
== V1TImode
);
1862 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1863 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1866 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1867 and it must be able to fit within the register set. */
1869 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1872 /* Print interesting facts about registers. */
1874 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1878 for (r
= first_regno
; r
<= last_regno
; ++r
)
1880 const char *comma
= "";
1883 if (first_regno
== last_regno
)
1884 fprintf (stderr
, "%s:\t", reg_name
);
1886 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1889 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1890 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1894 fprintf (stderr
, ",\n\t");
1899 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1900 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1901 rs6000_hard_regno_nregs
[m
][r
]);
1903 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1908 if (call_used_regs
[r
])
1912 fprintf (stderr
, ",\n\t");
1917 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1925 fprintf (stderr
, ",\n\t");
1930 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1936 fprintf (stderr
, ",\n\t");
1940 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1941 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1946 fprintf (stderr
, ",\n\t");
1950 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1955 rs6000_debug_vector_unit (enum rs6000_vector v
)
1961 case VECTOR_NONE
: ret
= "none"; break;
1962 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1963 case VECTOR_VSX
: ret
= "vsx"; break;
1964 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1965 case VECTOR_PAIRED
: ret
= "paired"; break;
1966 case VECTOR_SPE
: ret
= "spe"; break;
1967 case VECTOR_OTHER
: ret
= "other"; break;
1968 default: ret
= "unknown"; break;
1974 /* Inner function printing just the address mask for a particular reload
1976 DEBUG_FUNCTION
char *
1977 rs6000_debug_addr_mask (addr_mask_type mask
, bool keep_spaces
)
1982 if ((mask
& RELOAD_REG_VALID
) != 0)
1984 else if (keep_spaces
)
1987 if ((mask
& RELOAD_REG_MULTIPLE
) != 0)
1989 else if (keep_spaces
)
1992 if ((mask
& RELOAD_REG_INDEXED
) != 0)
1994 else if (keep_spaces
)
1997 if ((mask
& RELOAD_REG_OFFSET
) != 0)
1999 else if (keep_spaces
)
2002 if ((mask
& RELOAD_REG_PRE_INCDEC
) != 0)
2004 else if (keep_spaces
)
2007 if ((mask
& RELOAD_REG_PRE_MODIFY
) != 0)
2009 else if (keep_spaces
)
2012 if ((mask
& RELOAD_REG_AND_M16
) != 0)
2014 else if (keep_spaces
)
2022 /* Print the address masks in a human readble fashion. */
2024 rs6000_debug_print_mode (ssize_t m
)
2028 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
2029 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2030 fprintf (stderr
, " %s: %s", reload_reg_map
[rc
].name
,
2031 rs6000_debug_addr_mask (reg_addr
[m
].addr_mask
[rc
], true));
2033 if (rs6000_vector_unit
[m
] != VECTOR_NONE
2034 || rs6000_vector_mem
[m
] != VECTOR_NONE
2035 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
2036 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
)
2037 || reg_addr
[m
].scalar_in_vmx_p
)
2040 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c",
2041 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
2042 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
2043 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
2044 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*',
2045 (reg_addr
[m
].scalar_in_vmx_p
) ? 'y' : 'n');
2048 fputs ("\n", stderr
);
2051 #define DEBUG_FMT_ID "%-32s= "
2052 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2053 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2054 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2056 /* Print various interesting information with -mdebug=reg. */
2058 rs6000_debug_reg_global (void)
2060 static const char *const tf
[2] = { "false", "true" };
2061 const char *nl
= (const char *)0;
2064 char costly_num
[20];
2066 char flags_buffer
[40];
2067 const char *costly_str
;
2068 const char *nop_str
;
2069 const char *trace_str
;
2070 const char *abi_str
;
2071 const char *cmodel_str
;
2072 const char *float128_str
;
2073 struct cl_target_option cl_opts
;
2075 /* Modes we want tieable information on. */
2076 static const machine_mode print_tieable_modes
[] = {
2114 /* Virtual regs we are interested in. */
2115 const static struct {
2116 int regno
; /* register number. */
2117 const char *name
; /* register name. */
2118 } virtual_regs
[] = {
2119 { STACK_POINTER_REGNUM
, "stack pointer:" },
2120 { TOC_REGNUM
, "toc: " },
2121 { STATIC_CHAIN_REGNUM
, "static chain: " },
2122 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2123 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2124 { ARG_POINTER_REGNUM
, "arg pointer: " },
2125 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2126 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2127 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2128 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2129 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2130 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2131 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2132 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2133 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2134 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2137 fputs ("\nHard register information:\n", stderr
);
2138 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2139 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2140 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2143 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2144 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2145 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2146 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2147 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2148 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2149 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2150 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2152 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2153 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2154 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2158 "d reg_class = %s\n"
2159 "f reg_class = %s\n"
2160 "v reg_class = %s\n"
2161 "wa reg_class = %s\n"
2162 "wd reg_class = %s\n"
2163 "wf reg_class = %s\n"
2164 "wg reg_class = %s\n"
2165 "wh reg_class = %s\n"
2166 "wi reg_class = %s\n"
2167 "wj reg_class = %s\n"
2168 "wk reg_class = %s\n"
2169 "wl reg_class = %s\n"
2170 "wm reg_class = %s\n"
2171 "wp reg_class = %s\n"
2172 "wq reg_class = %s\n"
2173 "wr reg_class = %s\n"
2174 "ws reg_class = %s\n"
2175 "wt reg_class = %s\n"
2176 "wu reg_class = %s\n"
2177 "wv reg_class = %s\n"
2178 "ww reg_class = %s\n"
2179 "wx reg_class = %s\n"
2180 "wy reg_class = %s\n"
2181 "wz reg_class = %s\n"
2183 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2184 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2185 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2186 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2187 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2188 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2189 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2190 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2191 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2192 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2193 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2194 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2195 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2196 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wp
]],
2197 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wq
]],
2198 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2199 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2200 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2201 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2202 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2203 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2204 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2205 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2206 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2209 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2210 rs6000_debug_print_mode (m
);
2212 fputs ("\n", stderr
);
2214 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2216 machine_mode mode1
= print_tieable_modes
[m1
];
2217 bool first_time
= true;
2219 nl
= (const char *)0;
2220 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2222 machine_mode mode2
= print_tieable_modes
[m2
];
2223 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2227 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2232 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2237 fputs ("\n", stderr
);
2243 if (rs6000_recip_control
)
2245 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2247 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2248 if (rs6000_recip_bits
[m
])
2251 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2253 (RS6000_RECIP_AUTO_RE_P (m
)
2255 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2256 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2258 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2261 fputs ("\n", stderr
);
2264 if (rs6000_cpu_index
>= 0)
2266 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2268 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2270 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2271 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2274 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2276 if (rs6000_tune_index
>= 0)
2278 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2280 = processor_target_table
[rs6000_tune_index
].target_enable
;
2282 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2283 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2286 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2288 cl_target_option_save (&cl_opts
, &global_options
);
2289 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2292 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2293 rs6000_isa_flags_explicit
);
2295 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2296 rs6000_builtin_mask
);
2298 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2300 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2301 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2303 switch (rs6000_sched_costly_dep
)
2305 case max_dep_latency
:
2306 costly_str
= "max_dep_latency";
2310 costly_str
= "no_dep_costly";
2313 case all_deps_costly
:
2314 costly_str
= "all_deps_costly";
2317 case true_store_to_load_dep_costly
:
2318 costly_str
= "true_store_to_load_dep_costly";
2321 case store_to_load_dep_costly
:
2322 costly_str
= "store_to_load_dep_costly";
2326 costly_str
= costly_num
;
2327 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2331 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2333 switch (rs6000_sched_insert_nops
)
2335 case sched_finish_regroup_exact
:
2336 nop_str
= "sched_finish_regroup_exact";
2339 case sched_finish_pad_groups
:
2340 nop_str
= "sched_finish_pad_groups";
2343 case sched_finish_none
:
2344 nop_str
= "sched_finish_none";
2349 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2353 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2355 switch (rs6000_sdata
)
2362 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2366 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2370 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2375 switch (rs6000_traceback
)
2377 case traceback_default
: trace_str
= "default"; break;
2378 case traceback_none
: trace_str
= "none"; break;
2379 case traceback_part
: trace_str
= "part"; break;
2380 case traceback_full
: trace_str
= "full"; break;
2381 default: trace_str
= "unknown"; break;
2384 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2386 switch (rs6000_current_cmodel
)
2388 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2389 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2390 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2391 default: cmodel_str
= "unknown"; break;
2394 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2396 switch (rs6000_current_abi
)
2398 case ABI_NONE
: abi_str
= "none"; break;
2399 case ABI_AIX
: abi_str
= "aix"; break;
2400 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2401 case ABI_V4
: abi_str
= "V4"; break;
2402 case ABI_DARWIN
: abi_str
= "darwin"; break;
2403 default: abi_str
= "unknown"; break;
2406 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2408 if (rs6000_altivec_abi
)
2409 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2412 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2414 if (rs6000_darwin64_abi
)
2415 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2417 if (rs6000_float_gprs
)
2418 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2420 fprintf (stderr
, DEBUG_FMT_S
, "fprs",
2421 (TARGET_FPRS
? "true" : "false"));
2423 fprintf (stderr
, DEBUG_FMT_S
, "single_float",
2424 (TARGET_SINGLE_FLOAT
? "true" : "false"));
2426 fprintf (stderr
, DEBUG_FMT_S
, "double_float",
2427 (TARGET_DOUBLE_FLOAT
? "true" : "false"));
2429 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2430 (TARGET_SOFT_FLOAT
? "true" : "false"));
2432 fprintf (stderr
, DEBUG_FMT_S
, "e500_single",
2433 (TARGET_E500_SINGLE
? "true" : "false"));
2435 fprintf (stderr
, DEBUG_FMT_S
, "e500_double",
2436 (TARGET_E500_DOUBLE
? "true" : "false"));
2438 switch (TARGET_FLOAT128
)
2440 case FLOAT128_NONE
: float128_str
= "none"; break;
2441 case FLOAT128_SW
: float128_str
= "software"; break;
2442 default: float128_str
= "unknown"; break;
2445 fprintf (stderr
, DEBUG_FMT_S
, "float128", float128_str
);
2447 if (TARGET_LINK_STACK
)
2448 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2450 if (targetm
.lra_p ())
2451 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2453 if (TARGET_P8_FUSION
)
2454 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2455 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2457 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2458 TARGET_SECURE_PLT
? "secure" : "bss");
2459 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2460 aix_struct_return
? "aix" : "sysv");
2461 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2462 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2463 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2464 tf
[!!rs6000_align_branch_targets
]);
2465 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2466 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2467 rs6000_long_double_type_size
);
2468 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2469 (int)rs6000_sched_restricted_insns_priority
);
2470 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2472 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2473 (int)RS6000_BUILTIN_COUNT
);
2476 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2477 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2481 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2482 legitimate address support to figure out the appropriate addressing to
2486 rs6000_setup_reg_addr_masks (void)
2488 ssize_t rc
, reg
, m
, nregs
;
2489 addr_mask_type any_addr_mask
, addr_mask
;
2491 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2493 machine_mode m2
= (machine_mode
)m
;
2495 /* SDmode is special in that we want to access it only via REG+REG
2496 addressing on power7 and above, since we want to use the LFIWZX and
2497 STFIWZX instructions to load it. */
2498 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2501 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2504 reg
= reload_reg_map
[rc
].reg
;
2506 /* Can mode values go in the GPR/FPR/Altivec registers? */
2507 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2509 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2510 addr_mask
|= RELOAD_REG_VALID
;
2512 /* Indicate if the mode takes more than 1 physical register. If
2513 it takes a single register, indicate it can do REG+REG
2515 if (nregs
> 1 || m
== BLKmode
)
2516 addr_mask
|= RELOAD_REG_MULTIPLE
;
2518 addr_mask
|= RELOAD_REG_INDEXED
;
2520 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2521 addressing. Restrict addressing on SPE for 64-bit types
2522 because of the SUBREG hackery used to address 64-bit floats in
2526 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2527 && GET_MODE_SIZE (m2
) <= 8
2528 && !VECTOR_MODE_P (m2
)
2529 && !COMPLEX_MODE_P (m2
)
2531 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m2
) == 8))
2533 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2535 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2536 we don't allow PRE_MODIFY for some multi-register
2541 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2545 if (TARGET_POWERPC64
)
2546 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2552 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2558 /* GPR and FPR registers can do REG+OFFSET addressing, except
2559 possibly for SDmode. */
2560 if ((addr_mask
!= 0) && !indexed_only_p
2561 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2562 addr_mask
|= RELOAD_REG_OFFSET
;
2564 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2565 addressing on 128-bit types. */
2566 if (rc
== RELOAD_REG_VMX
&& GET_MODE_SIZE (m2
) == 16
2567 && (addr_mask
& RELOAD_REG_VALID
) != 0)
2568 addr_mask
|= RELOAD_REG_AND_M16
;
2570 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2571 any_addr_mask
|= addr_mask
;
2574 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2579 /* Initialize the various global tables that are based on register size. */
2581 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2587 /* Precalculate REGNO_REG_CLASS. */
2588 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2589 for (r
= 1; r
< 32; ++r
)
2590 rs6000_regno_regclass
[r
] = BASE_REGS
;
2592 for (r
= 32; r
< 64; ++r
)
2593 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2595 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2596 rs6000_regno_regclass
[r
] = NO_REGS
;
2598 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2599 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2601 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2602 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2603 rs6000_regno_regclass
[r
] = CR_REGS
;
2605 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2606 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2607 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
2608 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2609 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2610 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2611 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2612 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2613 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2614 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2615 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2616 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2618 /* Precalculate register class to simpler reload register class. We don't
2619 need all of the register classes that are combinations of different
2620 classes, just the simple ones that have constraint letters. */
2621 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2622 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2624 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2625 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2626 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2627 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2628 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2629 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2630 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2631 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2632 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2633 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2634 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2635 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2639 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2640 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2644 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2645 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2648 /* Precalculate the valid memory formats as well as the vector information,
2649 this must be set up before the rs6000_hard_regno_nregs_internal calls
2651 gcc_assert ((int)VECTOR_NONE
== 0);
2652 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2653 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2655 gcc_assert ((int)CODE_FOR_nothing
== 0);
2656 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2658 gcc_assert ((int)NO_REGS
== 0);
2659 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2661 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2662 believes it can use native alignment or still uses 128-bit alignment. */
2663 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2674 /* V2DF mode, VSX only. */
2677 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2678 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2679 rs6000_vector_align
[V2DFmode
] = align64
;
2682 /* V4SF mode, either VSX or Altivec. */
2685 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2686 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2687 rs6000_vector_align
[V4SFmode
] = align32
;
2689 else if (TARGET_ALTIVEC
)
2691 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2692 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2693 rs6000_vector_align
[V4SFmode
] = align32
;
2696 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2700 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2701 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2702 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2703 rs6000_vector_align
[V4SImode
] = align32
;
2704 rs6000_vector_align
[V8HImode
] = align32
;
2705 rs6000_vector_align
[V16QImode
] = align32
;
2709 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2710 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2711 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2715 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2716 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2717 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2721 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2722 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2725 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2726 rs6000_vector_unit
[V2DImode
]
2727 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2728 rs6000_vector_align
[V2DImode
] = align64
;
2730 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
2731 rs6000_vector_unit
[V1TImode
]
2732 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2733 rs6000_vector_align
[V1TImode
] = 128;
2736 /* DFmode, see if we want to use the VSX unit. Memory is handled
2737 differently, so don't set rs6000_vector_mem. */
2738 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2740 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2741 rs6000_vector_align
[DFmode
] = 64;
2744 /* SFmode, see if we want to use the VSX unit. */
2745 if (TARGET_P8_VECTOR
&& TARGET_VSX_SCALAR_FLOAT
)
2747 rs6000_vector_unit
[SFmode
] = VECTOR_VSX
;
2748 rs6000_vector_align
[SFmode
] = 32;
2751 /* Allow TImode in VSX register and set the VSX memory macros. */
2752 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2754 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2755 rs6000_vector_align
[TImode
] = align64
;
2758 /* TODO add SPE and paired floating point vector support. */
2760 /* Register class constraints for the constraints that depend on compile
2761 switches. When the VSX code was added, different constraints were added
2762 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2763 of the VSX registers are used. The register classes for scalar floating
2764 point types is set, based on whether we allow that type into the upper
2765 (Altivec) registers. GCC has register classes to target the Altivec
2766 registers for load/store operations, to select using a VSX memory
2767 operation instead of the traditional floating point operation. The
2770 d - Register class to use with traditional DFmode instructions.
2771 f - Register class to use with traditional SFmode instructions.
2772 v - Altivec register.
2773 wa - Any VSX register.
2774 wc - Reserved to represent individual CR bits (used in LLVM).
2775 wd - Preferred register class for V2DFmode.
2776 wf - Preferred register class for V4SFmode.
2777 wg - Float register for power6x move insns.
2778 wh - FP register for direct move instructions.
2779 wi - FP or VSX register to hold 64-bit integers for VSX insns.
2780 wj - FP or VSX register to hold 64-bit integers for direct moves.
2781 wk - FP or VSX register to hold 64-bit doubles for direct moves.
2782 wl - Float register if we can do 32-bit signed int loads.
2783 wm - VSX register for ISA 2.07 direct move operations.
2784 wn - always NO_REGS.
2785 wr - GPR if 64-bit mode is permitted.
2786 ws - Register class to do ISA 2.06 DF operations.
2787 wt - VSX register for TImode in VSX registers.
2788 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2789 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2790 ww - Register class to do SF conversions in with VSX operations.
2791 wx - Float register if we can do 32-bit int stores.
2792 wy - Register class to do ISA 2.07 SF operations.
2793 wz - Float register if we can do 32-bit unsigned int loads. */
2795 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2796 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
2798 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2799 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
2803 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2804 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
2805 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
2806 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = FLOAT_REGS
; /* DImode */
2808 if (TARGET_VSX_TIMODE
)
2809 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
2811 if (TARGET_UPPER_REGS_DF
) /* DFmode */
2813 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2814 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2817 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2820 /* Add conditional constraints based on various options, to allow us to
2821 collapse multiple insn patterns. */
2823 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2825 if (TARGET_MFPGPR
) /* DFmode */
2826 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2829 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
2831 if (TARGET_DIRECT_MOVE
)
2833 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
2834 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
2835 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
2836 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
2837 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
2838 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2841 if (TARGET_POWERPC64
)
2842 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2844 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
) /* SFmode */
2846 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2847 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2848 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2850 else if (TARGET_P8_VECTOR
)
2852 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2853 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2855 else if (TARGET_VSX
)
2856 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2859 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
2862 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
2864 if (TARGET_FLOAT128
)
2866 rs6000_constraints
[RS6000_CONSTRAINT_wq
] = VSX_REGS
; /* KFmode */
2867 if (rs6000_ieeequad
)
2868 rs6000_constraints
[RS6000_CONSTRAINT_wp
] = VSX_REGS
; /* TFmode */
2871 /* Set up the reload helper and direct move functions. */
2872 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2876 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2877 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2878 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2879 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2880 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2881 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2882 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2883 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2884 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
2885 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
2886 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2887 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2888 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2889 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2890 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2891 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2892 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2893 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2894 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2895 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2897 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
2899 if (TARGET_NO_SDMODE_STACK
)
2901 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2902 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2905 if (TARGET_VSX_TIMODE
)
2907 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2908 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2911 if (TARGET_DIRECT_MOVE
)
2913 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2914 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
2915 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2916 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2917 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2918 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2919 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2920 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2921 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2923 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2924 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
2925 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2926 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2927 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2928 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2929 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2930 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2931 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2936 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2937 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2938 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2939 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2940 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2941 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2942 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2943 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2944 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
2945 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
2946 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2947 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2948 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2949 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2950 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2951 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2952 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2953 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2954 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2955 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2957 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
2959 if (TARGET_NO_SDMODE_STACK
)
2961 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2962 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2965 if (TARGET_VSX_TIMODE
)
2967 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2968 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2971 if (TARGET_DIRECT_MOVE
)
2973 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2974 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2975 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2979 if (TARGET_UPPER_REGS_DF
)
2980 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
2982 if (TARGET_UPPER_REGS_SF
)
2983 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
2986 /* Precalculate HARD_REGNO_NREGS. */
2987 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2988 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2989 rs6000_hard_regno_nregs
[m
][r
]
2990 = rs6000_hard_regno_nregs_internal (r
, (machine_mode
)m
);
2992 /* Precalculate HARD_REGNO_MODE_OK. */
2993 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2994 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2995 if (rs6000_hard_regno_mode_ok (r
, (machine_mode
)m
))
2996 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2998 /* Precalculate CLASS_MAX_NREGS sizes. */
2999 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
3003 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
3004 reg_size
= UNITS_PER_VSX_WORD
;
3006 else if (c
== ALTIVEC_REGS
)
3007 reg_size
= UNITS_PER_ALTIVEC_WORD
;
3009 else if (c
== FLOAT_REGS
)
3010 reg_size
= UNITS_PER_FP_WORD
;
3013 reg_size
= UNITS_PER_WORD
;
3015 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3017 machine_mode m2
= (machine_mode
)m
;
3018 int reg_size2
= reg_size
;
3020 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3022 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
) && FLOAT128_2REG_P (m
))
3023 reg_size2
= UNITS_PER_FP_WORD
;
3025 rs6000_class_max_nregs
[m
][c
]
3026 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
3030 if (TARGET_E500_DOUBLE
)
3031 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
3033 /* Calculate which modes to automatically generate code to use a the
3034 reciprocal divide and square root instructions. In the future, possibly
3035 automatically generate the instructions even if the user did not specify
3036 -mrecip. The older machines double precision reciprocal sqrt estimate is
3037 not accurate enough. */
3038 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
3040 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3042 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3043 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3044 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3045 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3046 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3048 if (TARGET_FRSQRTES
)
3049 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3051 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3052 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3053 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3054 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3055 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3057 if (rs6000_recip_control
)
3059 if (!flag_finite_math_only
)
3060 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
3061 if (flag_trapping_math
)
3062 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
3063 if (!flag_reciprocal_math
)
3064 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
3065 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
3067 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
3068 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
3069 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3071 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
3072 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
3073 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3075 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
3076 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
3077 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3079 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
3080 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
3081 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3083 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
3084 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
3085 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3087 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
3088 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
3089 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3091 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
3092 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
3093 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3095 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
3096 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
3097 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3101 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3102 legitimate address support to figure out the appropriate addressing to
3104 rs6000_setup_reg_addr_masks ();
3106 if (global_init_p
|| TARGET_DEBUG_TARGET
)
3108 if (TARGET_DEBUG_REG
)
3109 rs6000_debug_reg_global ();
3111 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
3113 "SImode variable mult cost = %d\n"
3114 "SImode constant mult cost = %d\n"
3115 "SImode short constant mult cost = %d\n"
3116 "DImode multipliciation cost = %d\n"
3117 "SImode division cost = %d\n"
3118 "DImode division cost = %d\n"
3119 "Simple fp operation cost = %d\n"
3120 "DFmode multiplication cost = %d\n"
3121 "SFmode division cost = %d\n"
3122 "DFmode division cost = %d\n"
3123 "cache line size = %d\n"
3124 "l1 cache size = %d\n"
3125 "l2 cache size = %d\n"
3126 "simultaneous prefetches = %d\n"
3129 rs6000_cost
->mulsi_const
,
3130 rs6000_cost
->mulsi_const9
,
3138 rs6000_cost
->cache_line_size
,
3139 rs6000_cost
->l1_cache_size
,
3140 rs6000_cost
->l2_cache_size
,
3141 rs6000_cost
->simultaneous_prefetches
);
3146 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3149 darwin_rs6000_override_options (void)
3151 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3153 rs6000_altivec_abi
= 1;
3154 TARGET_ALTIVEC_VRSAVE
= 1;
3155 rs6000_current_abi
= ABI_DARWIN
;
3157 if (DEFAULT_ABI
== ABI_DARWIN
3159 darwin_one_byte_bool
= 1;
3161 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3163 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3164 warning (0, "-m64 requires PowerPC64 architecture, enabling");
3168 rs6000_default_long_calls
= 1;
3169 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3172 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3174 if (!flag_mkernel
&& !flag_apple_kext
3176 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3177 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3179 /* Unless the user (not the configurer) has explicitly overridden
3180 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3181 G4 unless targeting the kernel. */
3184 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3185 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3186 && ! global_options_set
.x_rs6000_cpu_index
)
3188 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3193 /* If not otherwise specified by a target, make 'long double' equivalent to
3196 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3197 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3200 /* Return the builtin mask of the various options used that could affect which
3201 builtins were used. In the past we used target_flags, but we've run out of
3202 bits, and some options like SPE and PAIRED are no longer in
3206 rs6000_builtin_mask_calculate (void)
3208 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3209 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3210 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
3211 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3212 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3213 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3214 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3215 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3216 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3217 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3218 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3219 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3220 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3221 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3222 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3223 | ((TARGET_LONG_DOUBLE_128
) ? RS6000_BTM_LDBL128
: 0));
3226 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3227 to clobber the XER[CA] bit because clobbering that bit without telling
3228 the compiler worked just fine with versions of GCC before GCC 5, and
3229 breaking a lot of older code in ways that are hard to track down is
3230 not such a great idea. */
3233 rs6000_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
3234 vec
<const char *> &/*constraints*/,
3235 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
3237 clobbers
.safe_push (gen_rtx_REG (SImode
, CA_REGNO
));
3238 SET_HARD_REG_BIT (clobbered_regs
, CA_REGNO
);
3242 /* Override command line options. Mostly we process the processor type and
3243 sometimes adjust other TARGET_ options. */
3246 rs6000_option_override_internal (bool global_init_p
)
3249 bool have_cpu
= false;
3251 /* The default cpu requested at configure time, if any. */
3252 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3254 HOST_WIDE_INT set_masks
;
3257 struct cl_target_option
*main_target_opt
3258 = ((global_init_p
|| target_option_default_node
== NULL
)
3259 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3261 /* Print defaults. */
3262 if ((TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
) && global_init_p
)
3263 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
3265 /* Remember the explicit arguments. */
3267 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3269 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3270 library functions, so warn about it. The flag may be useful for
3271 performance studies from time to time though, so don't disable it
3273 if (global_options_set
.x_rs6000_alignment_flags
3274 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3275 && DEFAULT_ABI
== ABI_DARWIN
3277 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3278 " it is incompatible with the installed C and C++ libraries");
3280 /* Numerous experiment shows that IRA based loop pressure
3281 calculation works better for RTL loop invariant motion on targets
3282 with enough (>= 32) registers. It is an expensive optimization.
3283 So it is on only for peak performance. */
3284 if (optimize
>= 3 && global_init_p
3285 && !global_options_set
.x_flag_ira_loop_pressure
)
3286 flag_ira_loop_pressure
= 1;
3288 /* Set the pointer size. */
3291 rs6000_pmode
= (int)DImode
;
3292 rs6000_pointer_size
= 64;
3296 rs6000_pmode
= (int)SImode
;
3297 rs6000_pointer_size
= 32;
3300 /* Some OSs don't support saving the high part of 64-bit registers on context
3301 switch. Other OSs don't support saving Altivec registers. On those OSs,
3302 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3303 if the user wants either, the user must explicitly specify them and we
3304 won't interfere with the user's specification. */
3306 set_masks
= POWERPC_MASKS
;
3307 #ifdef OS_MISSING_POWERPC64
3308 if (OS_MISSING_POWERPC64
)
3309 set_masks
&= ~OPTION_MASK_POWERPC64
;
3311 #ifdef OS_MISSING_ALTIVEC
3312 if (OS_MISSING_ALTIVEC
)
3313 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3316 /* Don't override by the processor default if given explicitly. */
3317 set_masks
&= ~rs6000_isa_flags_explicit
;
3319 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3320 the cpu in a target attribute or pragma, but did not specify a tuning
3321 option, use the cpu for the tuning option rather than the option specified
3322 with -mtune on the command line. Process a '--with-cpu' configuration
3323 request as an implicit --cpu. */
3324 if (rs6000_cpu_index
>= 0)
3326 cpu_index
= rs6000_cpu_index
;
3329 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3331 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3334 else if (implicit_cpu
)
3336 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3341 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3342 const char *default_cpu
= ((!TARGET_POWERPC64
)
3344 : ((BYTES_BIG_ENDIAN
)
3348 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3352 gcc_assert (cpu_index
>= 0);
3354 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3355 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3356 with those from the cpu, except for options that were explicitly set. If
3357 we don't have a cpu, do not override the target bits set in
3361 rs6000_isa_flags
&= ~set_masks
;
3362 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3367 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3368 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3369 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3370 to using rs6000_isa_flags, we need to do the initialization here.
3372 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3373 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3374 HOST_WIDE_INT flags
= ((TARGET_DEFAULT
) ? TARGET_DEFAULT
3375 : processor_target_table
[cpu_index
].target_enable
);
3376 rs6000_isa_flags
|= (flags
& ~rs6000_isa_flags_explicit
);
3379 if (rs6000_tune_index
>= 0)
3380 tune_index
= rs6000_tune_index
;
3382 rs6000_tune_index
= tune_index
= cpu_index
;
3386 enum processor_type tune_proc
3387 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3390 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3391 if (processor_target_table
[i
].processor
== tune_proc
)
3393 rs6000_tune_index
= tune_index
= i
;
3398 gcc_assert (tune_index
>= 0);
3399 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3401 /* Pick defaults for SPE related control flags. Do this early to make sure
3402 that the TARGET_ macros are representative ASAP. */
3404 int spe_capable_cpu
=
3405 (rs6000_cpu
== PROCESSOR_PPC8540
3406 || rs6000_cpu
== PROCESSOR_PPC8548
);
3408 if (!global_options_set
.x_rs6000_spe_abi
)
3409 rs6000_spe_abi
= spe_capable_cpu
;
3411 if (!global_options_set
.x_rs6000_spe
)
3412 rs6000_spe
= spe_capable_cpu
;
3414 if (!global_options_set
.x_rs6000_float_gprs
)
3416 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3417 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3421 if (global_options_set
.x_rs6000_spe_abi
3424 error ("not configured for SPE ABI");
3426 if (global_options_set
.x_rs6000_spe
3429 error ("not configured for SPE instruction set");
3431 if (main_target_opt
!= NULL
3432 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3433 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3434 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3435 error ("target attribute or pragma changes SPE ABI");
3437 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3438 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3439 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3442 error ("AltiVec not supported in this target");
3444 error ("SPE not supported in this target");
3446 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3449 error ("SPE not supported in this target");
3452 /* Disable Cell microcode if we are optimizing for the Cell
3453 and not optimizing for size. */
3454 if (rs6000_gen_cell_microcode
== -1)
3455 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3458 /* If we are optimizing big endian systems for space and it's OK to
3459 use instructions that would be microcoded on the Cell, use the
3460 load/store multiple and string instructions. */
3461 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3462 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3463 | OPTION_MASK_STRING
);
3465 /* Don't allow -mmultiple or -mstring on little endian systems
3466 unless the cpu is a 750, because the hardware doesn't support the
3467 instructions used in little endian mode, and causes an alignment
3468 trap. The 750 does not cause an alignment trap (except when the
3469 target is unaligned). */
3471 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3473 if (TARGET_MULTIPLE
)
3475 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3476 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3477 warning (0, "-mmultiple is not supported on little endian systems");
3482 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3483 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3484 warning (0, "-mstring is not supported on little endian systems");
3488 /* If little-endian, default to -mstrict-align on older processors.
3489 Testing for htm matches power8 and later. */
3490 if (!BYTES_BIG_ENDIAN
3491 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3492 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3494 /* -maltivec={le,be} implies -maltivec. */
3495 if (rs6000_altivec_element_order
!= 0)
3496 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3498 /* Disallow -maltivec=le in big endian mode for now. This is not
3499 known to be useful for anyone. */
3500 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
3502 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
3503 rs6000_altivec_element_order
= 0;
3506 /* Add some warnings for VSX. */
3509 const char *msg
= NULL
;
3510 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3511 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3513 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3514 msg
= N_("-mvsx requires hardware floating point");
3517 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3518 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3521 else if (TARGET_PAIRED_FLOAT
)
3522 msg
= N_("-mvsx and -mpaired are incompatible");
3523 else if (TARGET_AVOID_XFORM
> 0)
3524 msg
= N_("-mvsx needs indexed addressing");
3525 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3526 & OPTION_MASK_ALTIVEC
))
3528 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3529 msg
= N_("-mvsx and -mno-altivec are incompatible");
3531 msg
= N_("-mno-altivec disables vsx");
3537 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3538 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3542 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3543 the -mcpu setting to enable options that conflict. */
3544 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3545 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3546 | OPTION_MASK_ALTIVEC
3547 | OPTION_MASK_VSX
)) != 0)
3548 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3549 | OPTION_MASK_DIRECT_MOVE
)
3550 & ~rs6000_isa_flags_explicit
);
3552 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3553 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3555 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3556 unless the user explicitly used the -mno-<option> to disable the code. */
3557 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3558 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3559 else if (TARGET_VSX
)
3560 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3561 else if (TARGET_POPCNTD
)
3562 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3563 else if (TARGET_DFP
)
3564 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3565 else if (TARGET_CMPB
)
3566 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3567 else if (TARGET_FPRND
)
3568 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3569 else if (TARGET_POPCNTB
)
3570 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3571 else if (TARGET_ALTIVEC
)
3572 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3574 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3576 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3577 error ("-mcrypto requires -maltivec");
3578 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3581 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3583 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3584 error ("-mdirect-move requires -mvsx");
3585 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3588 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3590 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3591 error ("-mpower8-vector requires -maltivec");
3592 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3595 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3597 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3598 error ("-mpower8-vector requires -mvsx");
3599 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3602 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3604 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3605 error ("-mvsx-timode requires -mvsx");
3606 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3609 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
3611 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
3612 error ("-mhard-dfp requires -mhard-float");
3613 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
3616 /* Allow an explicit -mupper-regs to set both -mupper-regs-df and
3617 -mupper-regs-sf, depending on the cpu, unless the user explicitly also set
3618 the individual option. */
3619 if (TARGET_UPPER_REGS
> 0)
3622 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
))
3624 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_DF
;
3625 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DF
;
3627 if (TARGET_P8_VECTOR
3628 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
))
3630 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_SF
;
3631 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_SF
;
3634 else if (TARGET_UPPER_REGS
== 0)
3637 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
))
3639 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
3640 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DF
;
3642 if (TARGET_P8_VECTOR
3643 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
))
3645 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_SF
;
3646 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_SF
;
3650 if (TARGET_UPPER_REGS_DF
&& !TARGET_VSX
)
3652 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
)
3653 error ("-mupper-regs-df requires -mvsx");
3654 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
3657 if (TARGET_UPPER_REGS_SF
&& !TARGET_P8_VECTOR
)
3659 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
)
3660 error ("-mupper-regs-sf requires -mpower8-vector");
3661 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_SF
;
3664 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3665 silently turn off quad memory mode. */
3666 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
3668 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3669 warning (0, N_("-mquad-memory requires 64-bit mode"));
3671 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
3672 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
3674 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
3675 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
3678 /* Non-atomic quad memory load/store are disabled for little endian, since
3679 the words are reversed, but atomic operations can still be done by
3680 swapping the words. */
3681 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
3683 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3684 warning (0, N_("-mquad-memory is not available in little endian mode"));
3686 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3689 /* Assume if the user asked for normal quad memory instructions, they want
3690 the atomic versions as well, unless they explicity told us not to use quad
3691 word atomic instructions. */
3692 if (TARGET_QUAD_MEMORY
3693 && !TARGET_QUAD_MEMORY_ATOMIC
3694 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
3695 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
3697 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3698 generating power8 instructions. */
3699 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3700 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3701 & OPTION_MASK_P8_FUSION
);
3703 /* Power8 does not fuse sign extended loads with the addis. If we are
3704 optimizing at high levels for speed, convert a sign extended load into a
3705 zero extending load, and an explicit sign extension. */
3706 if (TARGET_P8_FUSION
3707 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3708 && optimize_function_for_speed_p (cfun
)
3710 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3712 /* Set the appropriate IEEE 128-bit floating option. Do not enable float128
3713 support by default until the libgcc support is added. */
3714 if (TARGET_FLOAT128
== FLOAT128_UNSET
)
3715 TARGET_FLOAT128
= FLOAT128_NONE
;
3716 else if (TARGET_FLOAT128
== FLOAT128_SW
&& !TARGET_VSX
)
3717 error ("-mfloat128-software requires VSX support");
3719 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
3720 support. If we only have ISA 2.06 support, and the user did not specify
3721 the switch, leave it set to -1 so the movmisalign patterns are enabled,
3722 but we don't enable the full vectorization support */
3723 if (TARGET_ALLOW_MOVMISALIGN
== -1 && TARGET_P8_VECTOR
&& TARGET_DIRECT_MOVE
)
3724 TARGET_ALLOW_MOVMISALIGN
= 1;
3726 else if (TARGET_ALLOW_MOVMISALIGN
&& !TARGET_VSX
)
3728 if (TARGET_ALLOW_MOVMISALIGN
> 0)
3729 error ("-mallow-movmisalign requires -mvsx");
3731 TARGET_ALLOW_MOVMISALIGN
= 0;
3734 /* Determine when unaligned vector accesses are permitted, and when
3735 they are preferred over masked Altivec loads. Note that if
3736 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
3737 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
3739 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
3743 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
3744 error ("-mefficient-unaligned-vsx requires -mvsx");
3746 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
3749 else if (!TARGET_ALLOW_MOVMISALIGN
)
3751 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
3752 error ("-mefficient-unaligned-vsx requires -mallow-movmisalign");
3754 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
3758 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3759 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3761 /* E500mc does "better" if we inline more aggressively. Respect the
3762 user's opinion, though. */
3763 if (rs6000_block_move_inline_limit
== 0
3764 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3765 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3766 || rs6000_cpu
== PROCESSOR_PPCE5500
3767 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3768 rs6000_block_move_inline_limit
= 128;
3770 /* store_one_arg depends on expand_block_move to handle at least the
3771 size of reg_parm_stack_space. */
3772 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3773 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3777 /* If the appropriate debug option is enabled, replace the target hooks
3778 with debug versions that call the real version and then prints
3779 debugging information. */
3780 if (TARGET_DEBUG_COST
)
3782 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3783 targetm
.address_cost
= rs6000_debug_address_cost
;
3784 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3787 if (TARGET_DEBUG_ADDR
)
3789 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3790 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3791 rs6000_secondary_reload_class_ptr
3792 = rs6000_debug_secondary_reload_class
;
3793 rs6000_secondary_memory_needed_ptr
3794 = rs6000_debug_secondary_memory_needed
;
3795 rs6000_cannot_change_mode_class_ptr
3796 = rs6000_debug_cannot_change_mode_class
;
3797 rs6000_preferred_reload_class_ptr
3798 = rs6000_debug_preferred_reload_class
;
3799 rs6000_legitimize_reload_address_ptr
3800 = rs6000_debug_legitimize_reload_address
;
3801 rs6000_mode_dependent_address_ptr
3802 = rs6000_debug_mode_dependent_address
;
3805 if (rs6000_veclibabi_name
)
3807 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3808 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3811 error ("unknown vectorization library ABI type (%s) for "
3812 "-mveclibabi= switch", rs6000_veclibabi_name
);
3818 if (!global_options_set
.x_rs6000_long_double_type_size
)
3820 if (main_target_opt
!= NULL
3821 && (main_target_opt
->x_rs6000_long_double_type_size
3822 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3823 error ("target attribute or pragma changes long double size");
3825 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3828 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3829 if (!global_options_set
.x_rs6000_ieeequad
)
3830 rs6000_ieeequad
= 1;
3833 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3834 target attribute or pragma which automatically enables both options,
3835 unless the altivec ABI was set. This is set by default for 64-bit, but
3837 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3838 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3839 & ~rs6000_isa_flags_explicit
);
3841 /* Enable Altivec ABI for AIX -maltivec. */
3842 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3844 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3845 error ("target attribute or pragma changes AltiVec ABI");
3847 rs6000_altivec_abi
= 1;
3850 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3851 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3852 be explicitly overridden in either case. */
3855 if (!global_options_set
.x_rs6000_altivec_abi
3856 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3858 if (main_target_opt
!= NULL
&&
3859 !main_target_opt
->x_rs6000_altivec_abi
)
3860 error ("target attribute or pragma changes AltiVec ABI");
3862 rs6000_altivec_abi
= 1;
3866 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3867 So far, the only darwin64 targets are also MACH-O. */
3869 && DEFAULT_ABI
== ABI_DARWIN
3872 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3873 error ("target attribute or pragma changes darwin64 ABI");
3876 rs6000_darwin64_abi
= 1;
3877 /* Default to natural alignment, for better performance. */
3878 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3882 /* Place FP constants in the constant pool instead of TOC
3883 if section anchors enabled. */
3884 if (flag_section_anchors
3885 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3886 TARGET_NO_FP_IN_TOC
= 1;
3888 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3889 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3891 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3892 SUBTARGET_OVERRIDE_OPTIONS
;
3894 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3895 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3897 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3898 SUB3TARGET_OVERRIDE_OPTIONS
;
3901 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3902 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3904 /* For the E500 family of cores, reset the single/double FP flags to let us
3905 check that they remain constant across attributes or pragmas. Also,
3906 clear a possible request for string instructions, not supported and which
3907 we might have silently queried above for -Os.
3909 For other families, clear ISEL in case it was set implicitly.
3914 case PROCESSOR_PPC8540
:
3915 case PROCESSOR_PPC8548
:
3916 case PROCESSOR_PPCE500MC
:
3917 case PROCESSOR_PPCE500MC64
:
3918 case PROCESSOR_PPCE5500
:
3919 case PROCESSOR_PPCE6500
:
3921 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3922 rs6000_double_float
= TARGET_E500_DOUBLE
;
3924 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3930 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3931 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3936 if (main_target_opt
)
3938 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3939 error ("target attribute or pragma changes single precision floating "
3941 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3942 error ("target attribute or pragma changes double precision floating "
3946 /* Detect invalid option combinations with E500. */
3949 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3950 && rs6000_cpu
!= PROCESSOR_POWER5
3951 && rs6000_cpu
!= PROCESSOR_POWER6
3952 && rs6000_cpu
!= PROCESSOR_POWER7
3953 && rs6000_cpu
!= PROCESSOR_POWER8
3954 && rs6000_cpu
!= PROCESSOR_PPCA2
3955 && rs6000_cpu
!= PROCESSOR_CELL
3956 && rs6000_cpu
!= PROCESSOR_PPC476
);
3957 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3958 || rs6000_cpu
== PROCESSOR_POWER5
3959 || rs6000_cpu
== PROCESSOR_POWER7
3960 || rs6000_cpu
== PROCESSOR_POWER8
);
3961 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3962 || rs6000_cpu
== PROCESSOR_POWER5
3963 || rs6000_cpu
== PROCESSOR_POWER6
3964 || rs6000_cpu
== PROCESSOR_POWER7
3965 || rs6000_cpu
== PROCESSOR_POWER8
3966 || rs6000_cpu
== PROCESSOR_PPCE500MC
3967 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3968 || rs6000_cpu
== PROCESSOR_PPCE5500
3969 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3971 /* Allow debug switches to override the above settings. These are set to -1
3972 in rs6000.opt to indicate the user hasn't directly set the switch. */
3973 if (TARGET_ALWAYS_HINT
>= 0)
3974 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3976 if (TARGET_SCHED_GROUPS
>= 0)
3977 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3979 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3980 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3982 rs6000_sched_restricted_insns_priority
3983 = (rs6000_sched_groups
? 1 : 0);
3985 /* Handle -msched-costly-dep option. */
3986 rs6000_sched_costly_dep
3987 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3989 if (rs6000_sched_costly_dep_str
)
3991 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3992 rs6000_sched_costly_dep
= no_dep_costly
;
3993 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3994 rs6000_sched_costly_dep
= all_deps_costly
;
3995 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3996 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3997 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3998 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
4000 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
4001 atoi (rs6000_sched_costly_dep_str
));
4004 /* Handle -minsert-sched-nops option. */
4005 rs6000_sched_insert_nops
4006 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
4008 if (rs6000_sched_insert_nops_str
)
4010 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
4011 rs6000_sched_insert_nops
= sched_finish_none
;
4012 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
4013 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
4014 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
4015 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
4017 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
4018 atoi (rs6000_sched_insert_nops_str
));
4023 #ifdef TARGET_REGNAMES
4024 /* If the user desires alternate register names, copy in the
4025 alternate names now. */
4026 if (TARGET_REGNAMES
)
4027 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
4030 /* Set aix_struct_return last, after the ABI is determined.
4031 If -maix-struct-return or -msvr4-struct-return was explicitly
4032 used, don't override with the ABI default. */
4033 if (!global_options_set
.x_aix_struct_return
)
4034 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
4037 /* IBM XL compiler defaults to unsigned bitfields. */
4038 if (TARGET_XL_COMPAT
)
4039 flag_signed_bitfields
= 0;
4042 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
4043 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
4046 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
4048 /* We can only guarantee the availability of DI pseudo-ops when
4049 assembling for 64-bit targets. */
4052 targetm
.asm_out
.aligned_op
.di
= NULL
;
4053 targetm
.asm_out
.unaligned_op
.di
= NULL
;
4057 /* Set branch target alignment, if not optimizing for size. */
4060 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4061 aligned 8byte to avoid misprediction by the branch predictor. */
4062 if (rs6000_cpu
== PROCESSOR_TITAN
4063 || rs6000_cpu
== PROCESSOR_CELL
)
4065 if (align_functions
<= 0)
4066 align_functions
= 8;
4067 if (align_jumps
<= 0)
4069 if (align_loops
<= 0)
4072 if (rs6000_align_branch_targets
)
4074 if (align_functions
<= 0)
4075 align_functions
= 16;
4076 if (align_jumps
<= 0)
4078 if (align_loops
<= 0)
4080 can_override_loop_align
= 1;
4084 if (align_jumps_max_skip
<= 0)
4085 align_jumps_max_skip
= 15;
4086 if (align_loops_max_skip
<= 0)
4087 align_loops_max_skip
= 15;
4090 /* Arrange to save and restore machine status around nested functions. */
4091 init_machine_status
= rs6000_init_machine_status
;
4093 /* We should always be splitting complex arguments, but we can't break
4094 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4095 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
4096 targetm
.calls
.split_complex_arg
= NULL
;
4099 /* Initialize rs6000_cost with the appropriate target costs. */
4101 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
4105 case PROCESSOR_RS64A
:
4106 rs6000_cost
= &rs64a_cost
;
4109 case PROCESSOR_MPCCORE
:
4110 rs6000_cost
= &mpccore_cost
;
4113 case PROCESSOR_PPC403
:
4114 rs6000_cost
= &ppc403_cost
;
4117 case PROCESSOR_PPC405
:
4118 rs6000_cost
= &ppc405_cost
;
4121 case PROCESSOR_PPC440
:
4122 rs6000_cost
= &ppc440_cost
;
4125 case PROCESSOR_PPC476
:
4126 rs6000_cost
= &ppc476_cost
;
4129 case PROCESSOR_PPC601
:
4130 rs6000_cost
= &ppc601_cost
;
4133 case PROCESSOR_PPC603
:
4134 rs6000_cost
= &ppc603_cost
;
4137 case PROCESSOR_PPC604
:
4138 rs6000_cost
= &ppc604_cost
;
4141 case PROCESSOR_PPC604e
:
4142 rs6000_cost
= &ppc604e_cost
;
4145 case PROCESSOR_PPC620
:
4146 rs6000_cost
= &ppc620_cost
;
4149 case PROCESSOR_PPC630
:
4150 rs6000_cost
= &ppc630_cost
;
4153 case PROCESSOR_CELL
:
4154 rs6000_cost
= &ppccell_cost
;
4157 case PROCESSOR_PPC750
:
4158 case PROCESSOR_PPC7400
:
4159 rs6000_cost
= &ppc750_cost
;
4162 case PROCESSOR_PPC7450
:
4163 rs6000_cost
= &ppc7450_cost
;
4166 case PROCESSOR_PPC8540
:
4167 case PROCESSOR_PPC8548
:
4168 rs6000_cost
= &ppc8540_cost
;
4171 case PROCESSOR_PPCE300C2
:
4172 case PROCESSOR_PPCE300C3
:
4173 rs6000_cost
= &ppce300c2c3_cost
;
4176 case PROCESSOR_PPCE500MC
:
4177 rs6000_cost
= &ppce500mc_cost
;
4180 case PROCESSOR_PPCE500MC64
:
4181 rs6000_cost
= &ppce500mc64_cost
;
4184 case PROCESSOR_PPCE5500
:
4185 rs6000_cost
= &ppce5500_cost
;
4188 case PROCESSOR_PPCE6500
:
4189 rs6000_cost
= &ppce6500_cost
;
4192 case PROCESSOR_TITAN
:
4193 rs6000_cost
= &titan_cost
;
4196 case PROCESSOR_POWER4
:
4197 case PROCESSOR_POWER5
:
4198 rs6000_cost
= &power4_cost
;
4201 case PROCESSOR_POWER6
:
4202 rs6000_cost
= &power6_cost
;
4205 case PROCESSOR_POWER7
:
4206 rs6000_cost
= &power7_cost
;
4209 case PROCESSOR_POWER8
:
4210 rs6000_cost
= &power8_cost
;
4213 case PROCESSOR_PPCA2
:
4214 rs6000_cost
= &ppca2_cost
;
4223 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
4224 rs6000_cost
->simultaneous_prefetches
,
4225 global_options
.x_param_values
,
4226 global_options_set
.x_param_values
);
4227 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
4228 global_options
.x_param_values
,
4229 global_options_set
.x_param_values
);
4230 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
4231 rs6000_cost
->cache_line_size
,
4232 global_options
.x_param_values
,
4233 global_options_set
.x_param_values
);
4234 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
4235 global_options
.x_param_values
,
4236 global_options_set
.x_param_values
);
4238 /* Increase loop peeling limits based on performance analysis. */
4239 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
4240 global_options
.x_param_values
,
4241 global_options_set
.x_param_values
);
4242 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
4243 global_options
.x_param_values
,
4244 global_options_set
.x_param_values
);
4246 /* If using typedef char *va_list, signal that
4247 __builtin_va_start (&ap, 0) can be optimized to
4248 ap = __builtin_next_arg (0). */
4249 if (DEFAULT_ABI
!= ABI_V4
)
4250 targetm
.expand_builtin_va_start
= NULL
;
4253 /* Set up single/double float flags.
4254 If TARGET_HARD_FLOAT is set, but neither single or double is set,
4255 then set both flags. */
4256 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
4257 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
4258 rs6000_single_float
= rs6000_double_float
= 1;
4260 /* If not explicitly specified via option, decide whether to generate indexed
4261 load/store instructions. */
4262 if (TARGET_AVOID_XFORM
== -1)
4263 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4264 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4265 need indexed accesses and the type used is the scalar type of the element
4266 being loaded or stored. */
4267 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
4268 && !TARGET_ALTIVEC
);
4270 /* Set the -mrecip options. */
4271 if (rs6000_recip_name
)
4273 char *p
= ASTRDUP (rs6000_recip_name
);
4275 unsigned int mask
, i
;
4278 while ((q
= strtok (p
, ",")) != NULL
)
4289 if (!strcmp (q
, "default"))
4290 mask
= ((TARGET_RECIP_PRECISION
)
4291 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
4294 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
4295 if (!strcmp (q
, recip_options
[i
].string
))
4297 mask
= recip_options
[i
].mask
;
4301 if (i
== ARRAY_SIZE (recip_options
))
4303 error ("unknown option for -mrecip=%s", q
);
4311 rs6000_recip_control
&= ~mask
;
4313 rs6000_recip_control
|= mask
;
4317 /* Set the builtin mask of the various options used that could affect which
4318 builtins were used. In the past we used target_flags, but we've run out
4319 of bits, and some options like SPE and PAIRED are no longer in
4321 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4322 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4323 rs6000_print_builtin_options (stderr
, 0, "builtin mask",
4324 rs6000_builtin_mask
);
4326 /* Initialize all of the registers. */
4327 rs6000_init_hard_regno_mode_ok (global_init_p
);
4329 /* Save the initial options in case the user does function specific options */
4331 target_option_default_node
= target_option_current_node
4332 = build_target_option_node (&global_options
);
4334 /* If not explicitly specified via option, decide whether to generate the
4335 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4336 if (TARGET_LINK_STACK
== -1)
4337 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
4342 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4343 define the target cpu type. */
4346 rs6000_option_override (void)
4348 (void) rs6000_option_override_internal (true);
4350 /* Register machine-specific passes. This needs to be done at start-up.
4351 It's convenient to do it here (like i386 does). */
4352 opt_pass
*pass_analyze_swaps
= make_pass_analyze_swaps (g
);
4354 struct register_pass_info analyze_swaps_info
4355 = { pass_analyze_swaps
, "cse1", 1, PASS_POS_INSERT_BEFORE
};
4357 register_pass (&analyze_swaps_info
);
4361 /* Implement targetm.vectorize.builtin_mask_for_load. */
4363 rs6000_builtin_mask_for_load (void)
4365 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4366 if ((TARGET_ALTIVEC
&& !TARGET_VSX
)
4367 || (TARGET_VSX
&& !TARGET_EFFICIENT_UNALIGNED_VSX
))
4368 return altivec_builtin_mask_for_load
;
4373 /* Implement LOOP_ALIGN. */
4375 rs6000_loop_align (rtx label
)
4380 /* Don't override loop alignment if -falign-loops was specified. */
4381 if (!can_override_loop_align
)
4382 return align_loops_log
;
4384 bb
= BLOCK_FOR_INSN (label
);
4385 ninsns
= num_loop_insns(bb
->loop_father
);
4387 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4388 if (ninsns
> 4 && ninsns
<= 8
4389 && (rs6000_cpu
== PROCESSOR_POWER4
4390 || rs6000_cpu
== PROCESSOR_POWER5
4391 || rs6000_cpu
== PROCESSOR_POWER6
4392 || rs6000_cpu
== PROCESSOR_POWER7
4393 || rs6000_cpu
== PROCESSOR_POWER8
))
4396 return align_loops_log
;
4399 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4401 rs6000_loop_align_max_skip (rtx_insn
*label
)
4403 return (1 << rs6000_loop_align (label
)) - 1;
4406 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4407 after applying N number of iterations. This routine does not determine
4408 how may iterations are required to reach desired alignment. */
4411 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4418 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4421 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4431 /* Assuming that all other types are naturally aligned. CHECKME! */
4436 /* Return true if the vector misalignment factor is supported by the
4439 rs6000_builtin_support_vector_misalignment (machine_mode mode
,
4446 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4449 /* Return if movmisalign pattern is not supported for this mode. */
4450 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4453 if (misalignment
== -1)
4455 /* Misalignment factor is unknown at compile time but we know
4456 it's word aligned. */
4457 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4459 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4461 if (element_size
== 64 || element_size
== 32)
4468 /* VSX supports word-aligned vector. */
4469 if (misalignment
% 4 == 0)
4475 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4477 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4478 tree vectype
, int misalign
)
4483 switch (type_of_cost
)
4493 case cond_branch_not_taken
:
4502 case vec_promote_demote
:
4508 case cond_branch_taken
:
4511 case unaligned_load
:
4512 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4515 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4517 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4519 /* Double word aligned. */
4527 /* Double word aligned. */
4531 /* Unknown misalignment. */
4544 /* Misaligned loads are not supported. */
4549 case unaligned_store
:
4550 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4553 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4555 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4557 /* Double word aligned. */
4565 /* Double word aligned. */
4569 /* Unknown misalignment. */
4582 /* Misaligned stores are not supported. */
4588 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4589 elem_type
= TREE_TYPE (vectype
);
4590 /* 32-bit vectors loaded into registers are stored as double
4591 precision, so we need n/2 converts in addition to the usual
4592 n/2 merges to construct a vector of short floats from them. */
4593 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4594 && TYPE_PRECISION (elem_type
) == 32)
4595 return elements
+ 1;
4597 return elements
/ 2 + 1;
4604 /* Implement targetm.vectorize.preferred_simd_mode. */
4607 rs6000_preferred_simd_mode (machine_mode mode
)
4616 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4642 if (TARGET_PAIRED_FLOAT
4648 typedef struct _rs6000_cost_data
4650 struct loop
*loop_info
;
4654 /* Test for likely overcommitment of vector hardware resources. If a
4655 loop iteration is relatively large, and too large a percentage of
4656 instructions in the loop are vectorized, the cost model may not
4657 adequately reflect delays from unavailable vector resources.
4658 Penalize the loop body cost for this case. */
4661 rs6000_density_test (rs6000_cost_data
*data
)
4663 const int DENSITY_PCT_THRESHOLD
= 85;
4664 const int DENSITY_SIZE_THRESHOLD
= 70;
4665 const int DENSITY_PENALTY
= 10;
4666 struct loop
*loop
= data
->loop_info
;
4667 basic_block
*bbs
= get_loop_body (loop
);
4668 int nbbs
= loop
->num_nodes
;
4669 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4672 for (i
= 0; i
< nbbs
; i
++)
4674 basic_block bb
= bbs
[i
];
4675 gimple_stmt_iterator gsi
;
4677 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4679 gimple
*stmt
= gsi_stmt (gsi
);
4680 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4682 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4683 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4689 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4691 if (density_pct
> DENSITY_PCT_THRESHOLD
4692 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4694 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4695 if (dump_enabled_p ())
4696 dump_printf_loc (MSG_NOTE
, vect_location
,
4697 "density %d%%, cost %d exceeds threshold, penalizing "
4698 "loop body cost by %d%%", density_pct
,
4699 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4703 /* Implement targetm.vectorize.init_cost. */
4706 rs6000_init_cost (struct loop
*loop_info
)
4708 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4709 data
->loop_info
= loop_info
;
4710 data
->cost
[vect_prologue
] = 0;
4711 data
->cost
[vect_body
] = 0;
4712 data
->cost
[vect_epilogue
] = 0;
4716 /* Implement targetm.vectorize.add_stmt_cost. */
4719 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4720 struct _stmt_vec_info
*stmt_info
, int misalign
,
4721 enum vect_cost_model_location where
)
4723 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4724 unsigned retval
= 0;
4726 if (flag_vect_cost_model
)
4728 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4729 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4731 /* Statements in an inner loop relative to the loop being
4732 vectorized are weighted more heavily. The value here is
4733 arbitrary and could potentially be improved with analysis. */
4734 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4735 count
*= 50; /* FIXME. */
4737 retval
= (unsigned) (count
* stmt_cost
);
4738 cost_data
->cost
[where
] += retval
;
4744 /* Implement targetm.vectorize.finish_cost. */
4747 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4748 unsigned *body_cost
, unsigned *epilogue_cost
)
4750 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4752 if (cost_data
->loop_info
)
4753 rs6000_density_test (cost_data
);
4755 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4756 *body_cost
= cost_data
->cost
[vect_body
];
4757 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4760 /* Implement targetm.vectorize.destroy_cost_data. */
4763 rs6000_destroy_cost_data (void *data
)
4768 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4769 library with vectorized intrinsics. */
4772 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4775 const char *suffix
= NULL
;
4776 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4779 machine_mode el_mode
, in_mode
;
4782 /* Libmass is suitable for unsafe math only as it does not correctly support
4783 parts of IEEE with the required precision such as denormals. Only support
4784 it if we have VSX to use the simd d2 or f4 functions.
4785 XXX: Add variable length support. */
4786 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4789 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4790 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4791 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4792 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4793 if (el_mode
!= in_mode
4797 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4799 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4802 case BUILT_IN_ATAN2
:
4803 case BUILT_IN_HYPOT
:
4809 case BUILT_IN_ACOSH
:
4811 case BUILT_IN_ASINH
:
4813 case BUILT_IN_ATANH
:
4821 case BUILT_IN_EXPM1
:
4822 case BUILT_IN_LGAMMA
:
4823 case BUILT_IN_LOG10
:
4824 case BUILT_IN_LOG1P
:
4832 bdecl
= builtin_decl_implicit (fn
);
4833 suffix
= "d2"; /* pow -> powd2 */
4834 if (el_mode
!= DFmode
4840 case BUILT_IN_ATAN2F
:
4841 case BUILT_IN_HYPOTF
:
4846 case BUILT_IN_ACOSF
:
4847 case BUILT_IN_ACOSHF
:
4848 case BUILT_IN_ASINF
:
4849 case BUILT_IN_ASINHF
:
4850 case BUILT_IN_ATANF
:
4851 case BUILT_IN_ATANHF
:
4852 case BUILT_IN_CBRTF
:
4854 case BUILT_IN_COSHF
:
4856 case BUILT_IN_ERFCF
:
4857 case BUILT_IN_EXP2F
:
4859 case BUILT_IN_EXPM1F
:
4860 case BUILT_IN_LGAMMAF
:
4861 case BUILT_IN_LOG10F
:
4862 case BUILT_IN_LOG1PF
:
4863 case BUILT_IN_LOG2F
:
4866 case BUILT_IN_SINHF
:
4867 case BUILT_IN_SQRTF
:
4869 case BUILT_IN_TANHF
:
4870 bdecl
= builtin_decl_implicit (fn
);
4871 suffix
= "4"; /* powf -> powf4 */
4872 if (el_mode
!= SFmode
4885 gcc_assert (suffix
!= NULL
);
4886 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4890 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4891 strcat (name
, suffix
);
4894 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4895 else if (n_args
== 2)
4896 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4900 /* Build a function declaration for the vectorized function. */
4901 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4902 FUNCTION_DECL
, get_identifier (name
), fntype
);
4903 TREE_PUBLIC (new_fndecl
) = 1;
4904 DECL_EXTERNAL (new_fndecl
) = 1;
4905 DECL_IS_NOVOPS (new_fndecl
) = 1;
4906 TREE_READONLY (new_fndecl
) = 1;
4911 /* Returns a function decl for a vectorized version of the builtin function
4912 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4913 if it is not available. */
4916 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4919 machine_mode in_mode
, out_mode
;
4922 if (TARGET_DEBUG_BUILTIN
)
4923 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4924 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4925 GET_MODE_NAME (TYPE_MODE (type_out
)),
4926 GET_MODE_NAME (TYPE_MODE (type_in
)));
4928 if (TREE_CODE (type_out
) != VECTOR_TYPE
4929 || TREE_CODE (type_in
) != VECTOR_TYPE
4930 || !TARGET_VECTORIZE_BUILTINS
)
4933 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4934 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4935 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4936 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4938 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4940 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4943 case BUILT_IN_CLZIMAX
:
4944 case BUILT_IN_CLZLL
:
4947 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4949 if (out_mode
== QImode
&& out_n
== 16)
4950 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4951 else if (out_mode
== HImode
&& out_n
== 8)
4952 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4953 else if (out_mode
== SImode
&& out_n
== 4)
4954 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4955 else if (out_mode
== DImode
&& out_n
== 2)
4956 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4959 case BUILT_IN_COPYSIGN
:
4960 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4961 && out_mode
== DFmode
&& out_n
== 2
4962 && in_mode
== DFmode
&& in_n
== 2)
4963 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4965 case BUILT_IN_COPYSIGNF
:
4966 if (out_mode
!= SFmode
|| out_n
!= 4
4967 || in_mode
!= SFmode
|| in_n
!= 4)
4969 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4970 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4971 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4972 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4974 case BUILT_IN_POPCOUNTIMAX
:
4975 case BUILT_IN_POPCOUNTLL
:
4976 case BUILT_IN_POPCOUNTL
:
4977 case BUILT_IN_POPCOUNT
:
4978 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4980 if (out_mode
== QImode
&& out_n
== 16)
4981 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4982 else if (out_mode
== HImode
&& out_n
== 8)
4983 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4984 else if (out_mode
== SImode
&& out_n
== 4)
4985 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4986 else if (out_mode
== DImode
&& out_n
== 2)
4987 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4991 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4992 && out_mode
== DFmode
&& out_n
== 2
4993 && in_mode
== DFmode
&& in_n
== 2)
4994 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4996 case BUILT_IN_SQRTF
:
4997 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4998 && out_mode
== SFmode
&& out_n
== 4
4999 && in_mode
== SFmode
&& in_n
== 4)
5000 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
5003 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5004 && out_mode
== DFmode
&& out_n
== 2
5005 && in_mode
== DFmode
&& in_n
== 2)
5006 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
5008 case BUILT_IN_CEILF
:
5009 if (out_mode
!= SFmode
|| out_n
!= 4
5010 || in_mode
!= SFmode
|| in_n
!= 4)
5012 if (VECTOR_UNIT_VSX_P (V4SFmode
))
5013 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
5014 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
5015 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
5017 case BUILT_IN_FLOOR
:
5018 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5019 && out_mode
== DFmode
&& out_n
== 2
5020 && in_mode
== DFmode
&& in_n
== 2)
5021 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
5023 case BUILT_IN_FLOORF
:
5024 if (out_mode
!= SFmode
|| out_n
!= 4
5025 || in_mode
!= SFmode
|| in_n
!= 4)
5027 if (VECTOR_UNIT_VSX_P (V4SFmode
))
5028 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
5029 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
5030 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
5033 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5034 && out_mode
== DFmode
&& out_n
== 2
5035 && in_mode
== DFmode
&& in_n
== 2)
5036 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
5039 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5040 && out_mode
== SFmode
&& out_n
== 4
5041 && in_mode
== SFmode
&& in_n
== 4)
5042 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
5043 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5044 && out_mode
== SFmode
&& out_n
== 4
5045 && in_mode
== SFmode
&& in_n
== 4)
5046 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
5048 case BUILT_IN_TRUNC
:
5049 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5050 && out_mode
== DFmode
&& out_n
== 2
5051 && in_mode
== DFmode
&& in_n
== 2)
5052 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
5054 case BUILT_IN_TRUNCF
:
5055 if (out_mode
!= SFmode
|| out_n
!= 4
5056 || in_mode
!= SFmode
|| in_n
!= 4)
5058 if (VECTOR_UNIT_VSX_P (V4SFmode
))
5059 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
5060 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
5061 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
5063 case BUILT_IN_NEARBYINT
:
5064 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5065 && flag_unsafe_math_optimizations
5066 && out_mode
== DFmode
&& out_n
== 2
5067 && in_mode
== DFmode
&& in_n
== 2)
5068 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
5070 case BUILT_IN_NEARBYINTF
:
5071 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5072 && flag_unsafe_math_optimizations
5073 && out_mode
== SFmode
&& out_n
== 4
5074 && in_mode
== SFmode
&& in_n
== 4)
5075 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
5078 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5079 && !flag_trapping_math
5080 && out_mode
== DFmode
&& out_n
== 2
5081 && in_mode
== DFmode
&& in_n
== 2)
5082 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
5084 case BUILT_IN_RINTF
:
5085 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5086 && !flag_trapping_math
5087 && out_mode
== SFmode
&& out_n
== 4
5088 && in_mode
== SFmode
&& in_n
== 4)
5089 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
5096 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
5098 enum rs6000_builtins fn
5099 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
5102 case RS6000_BUILTIN_RSQRTF
:
5103 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5104 && out_mode
== SFmode
&& out_n
== 4
5105 && in_mode
== SFmode
&& in_n
== 4)
5106 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
5108 case RS6000_BUILTIN_RSQRT
:
5109 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5110 && out_mode
== DFmode
&& out_n
== 2
5111 && in_mode
== DFmode
&& in_n
== 2)
5112 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
5114 case RS6000_BUILTIN_RECIPF
:
5115 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5116 && out_mode
== SFmode
&& out_n
== 4
5117 && in_mode
== SFmode
&& in_n
== 4)
5118 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
5120 case RS6000_BUILTIN_RECIP
:
5121 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5122 && out_mode
== DFmode
&& out_n
== 2
5123 && in_mode
== DFmode
&& in_n
== 2)
5124 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
5131 /* Generate calls to libmass if appropriate. */
5132 if (rs6000_veclib_handler
)
5133 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
5138 /* Default CPU string for rs6000*_file_start functions. */
5139 static const char *rs6000_default_cpu
;
5141 /* Do anything needed at the start of the asm file. */
5144 rs6000_file_start (void)
5147 const char *start
= buffer
;
5148 FILE *file
= asm_out_file
;
5150 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
5152 default_file_start ();
5154 if (flag_verbose_asm
)
5156 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
5158 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
5160 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
5164 if (global_options_set
.x_rs6000_cpu_index
)
5166 fprintf (file
, "%s -mcpu=%s", start
,
5167 processor_target_table
[rs6000_cpu_index
].name
);
5171 if (global_options_set
.x_rs6000_tune_index
)
5173 fprintf (file
, "%s -mtune=%s", start
,
5174 processor_target_table
[rs6000_tune_index
].name
);
5178 if (PPC405_ERRATUM77
)
5180 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
5184 #ifdef USING_ELFOS_H
5185 switch (rs6000_sdata
)
5187 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
5188 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
5189 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
5190 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
5193 if (rs6000_sdata
&& g_switch_value
)
5195 fprintf (file
, "%s -G %d", start
,
5205 #ifdef USING_ELFOS_H
5206 if (rs6000_default_cpu
== 0 || rs6000_default_cpu
[0] == '\0'
5207 || !global_options_set
.x_rs6000_cpu_index
)
5209 fputs ("\t.machine ", asm_out_file
);
5210 if ((rs6000_isa_flags
& OPTION_MASK_DIRECT_MOVE
) != 0)
5211 fputs ("power8\n", asm_out_file
);
5212 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTD
) != 0)
5213 fputs ("power7\n", asm_out_file
);
5214 else if ((rs6000_isa_flags
& OPTION_MASK_CMPB
) != 0)
5215 fputs ("power6\n", asm_out_file
);
5216 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTB
) != 0)
5217 fputs ("power5\n", asm_out_file
);
5218 else if ((rs6000_isa_flags
& OPTION_MASK_MFCRF
) != 0)
5219 fputs ("power4\n", asm_out_file
);
5220 else if ((rs6000_isa_flags
& OPTION_MASK_POWERPC64
) != 0)
5221 fputs ("ppc64\n", asm_out_file
);
5223 fputs ("ppc\n", asm_out_file
);
5227 if (DEFAULT_ABI
== ABI_ELFv2
)
5228 fprintf (file
, "\t.abiversion 2\n");
5230 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
5231 || (TARGET_ELF
&& flag_pic
== 2))
5233 switch_to_section (toc_section
);
5234 switch_to_section (text_section
);
5239 /* Return nonzero if this function is known to have a null epilogue. */
5242 direct_return (void)
5244 if (reload_completed
)
5246 rs6000_stack_t
*info
= rs6000_stack_info ();
5248 if (info
->first_gp_reg_save
== 32
5249 && info
->first_fp_reg_save
== 64
5250 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
5251 && ! info
->lr_save_p
5252 && ! info
->cr_save_p
5253 && info
->vrsave_size
== 0
5261 /* Return the number of instructions it takes to form a constant in an
5262 integer register. */
5265 num_insns_constant_wide (HOST_WIDE_INT value
)
5267 /* signed constant loadable with addi */
5268 if (((unsigned HOST_WIDE_INT
) value
+ 0x8000) < 0x10000)
5271 /* constant loadable with addis */
5272 else if ((value
& 0xffff) == 0
5273 && (value
>> 31 == -1 || value
>> 31 == 0))
5276 else if (TARGET_POWERPC64
)
5278 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
5279 HOST_WIDE_INT high
= value
>> 31;
5281 if (high
== 0 || high
== -1)
5287 return num_insns_constant_wide (high
) + 1;
5289 return num_insns_constant_wide (low
) + 1;
5291 return (num_insns_constant_wide (high
)
5292 + num_insns_constant_wide (low
) + 1);
5300 num_insns_constant (rtx op
, machine_mode mode
)
5302 HOST_WIDE_INT low
, high
;
5304 switch (GET_CODE (op
))
5307 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
5308 && rs6000_is_valid_and_mask (op
, mode
))
5311 return num_insns_constant_wide (INTVAL (op
));
5313 case CONST_WIDE_INT
:
5316 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
5317 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
5318 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
5323 if (mode
== SFmode
|| mode
== SDmode
)
5328 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
5329 if (DECIMAL_FLOAT_MODE_P (mode
))
5330 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
5332 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
5333 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
5339 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
5340 if (DECIMAL_FLOAT_MODE_P (mode
))
5341 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
5343 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
5344 high
= l
[WORDS_BIG_ENDIAN
== 0];
5345 low
= l
[WORDS_BIG_ENDIAN
!= 0];
5348 return (num_insns_constant_wide (low
)
5349 + num_insns_constant_wide (high
));
5352 if ((high
== 0 && low
>= 0)
5353 || (high
== -1 && low
< 0))
5354 return num_insns_constant_wide (low
);
5356 else if (rs6000_is_valid_and_mask (op
, mode
))
5360 return num_insns_constant_wide (high
) + 1;
5363 return (num_insns_constant_wide (high
)
5364 + num_insns_constant_wide (low
) + 1);
5372 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5373 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5374 corresponding element of the vector, but for V4SFmode and V2SFmode,
5375 the corresponding "float" is interpreted as an SImode integer. */
5378 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5382 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5383 gcc_assert (GET_MODE (op
) != V2DImode
5384 && GET_MODE (op
) != V2DFmode
);
5386 tmp
= CONST_VECTOR_ELT (op
, elt
);
5387 if (GET_MODE (op
) == V4SFmode
5388 || GET_MODE (op
) == V2SFmode
)
5389 tmp
= gen_lowpart (SImode
, tmp
);
5390 return INTVAL (tmp
);
5393 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5394 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5395 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5396 all items are set to the same value and contain COPIES replicas of the
5397 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5398 operand and the others are set to the value of the operand's msb. */
5401 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5403 machine_mode mode
= GET_MODE (op
);
5404 machine_mode inner
= GET_MODE_INNER (mode
);
5412 HOST_WIDE_INT splat_val
;
5413 HOST_WIDE_INT msb_val
;
5415 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5418 nunits
= GET_MODE_NUNITS (mode
);
5419 bitsize
= GET_MODE_BITSIZE (inner
);
5420 mask
= GET_MODE_MASK (inner
);
5422 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5424 msb_val
= val
>= 0 ? 0 : -1;
5426 /* Construct the value to be splatted, if possible. If not, return 0. */
5427 for (i
= 2; i
<= copies
; i
*= 2)
5429 HOST_WIDE_INT small_val
;
5431 small_val
= splat_val
>> bitsize
;
5433 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
5435 splat_val
= small_val
;
5438 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5439 if (EASY_VECTOR_15 (splat_val
))
5442 /* Also check if we can splat, and then add the result to itself. Do so if
5443 the value is positive, of if the splat instruction is using OP's mode;
5444 for splat_val < 0, the splat and the add should use the same mode. */
5445 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5446 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5449 /* Also check if are loading up the most significant bit which can be done by
5450 loading up -1 and shifting the value left by -1. */
5451 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5457 /* Check if VAL is present in every STEP-th element, and the
5458 other elements are filled with its most significant bit. */
5459 for (i
= 1; i
< nunits
; ++i
)
5461 HOST_WIDE_INT desired_val
;
5462 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5463 if ((i
& (step
- 1)) == 0)
5466 desired_val
= msb_val
;
5468 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5475 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
5476 instruction, filling in the bottom elements with 0 or -1.
5478 Return 0 if the constant cannot be generated with VSLDOI. Return positive
5479 for the number of zeroes to shift in, or negative for the number of 0xff
5482 OP is a CONST_VECTOR. */
5485 vspltis_shifted (rtx op
)
5487 machine_mode mode
= GET_MODE (op
);
5488 machine_mode inner
= GET_MODE_INNER (mode
);
5496 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
)
5499 /* We need to create pseudo registers to do the shift, so don't recognize
5500 shift vector constants after reload. */
5501 if (!can_create_pseudo_p ())
5504 nunits
= GET_MODE_NUNITS (mode
);
5505 mask
= GET_MODE_MASK (inner
);
5507 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? 0 : nunits
- 1);
5509 /* Check if the value can really be the operand of a vspltis[bhw]. */
5510 if (EASY_VECTOR_15 (val
))
5513 /* Also check if we are loading up the most significant bit which can be done
5514 by loading up -1 and shifting the value left by -1. */
5515 else if (EASY_VECTOR_MSB (val
, inner
))
5521 /* Check if VAL is present in every STEP-th element until we find elements
5522 that are 0 or all 1 bits. */
5523 for (i
= 1; i
< nunits
; ++i
)
5525 unsigned elt
= BYTES_BIG_ENDIAN
? i
: nunits
- 1 - i
;
5526 HOST_WIDE_INT elt_val
= const_vector_elt_as_int (op
, elt
);
5528 /* If the value isn't the splat value, check for the remaining elements
5534 for (j
= i
+1; j
< nunits
; ++j
)
5536 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
5537 if (const_vector_elt_as_int (op
, elt2
) != 0)
5541 return (nunits
- i
) * GET_MODE_SIZE (inner
);
5544 else if ((elt_val
& mask
) == mask
)
5546 for (j
= i
+1; j
< nunits
; ++j
)
5548 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
5549 if ((const_vector_elt_as_int (op
, elt2
) & mask
) != mask
)
5553 return -((nunits
- i
) * GET_MODE_SIZE (inner
));
5561 /* If all elements are equal, we don't need to do VLSDOI. */
5566 /* Return true if OP is of the given MODE and can be synthesized
5567 with a vspltisb, vspltish or vspltisw. */
5570 easy_altivec_constant (rtx op
, machine_mode mode
)
5572 unsigned step
, copies
;
5574 if (mode
== VOIDmode
)
5575 mode
= GET_MODE (op
);
5576 else if (mode
!= GET_MODE (op
))
5579 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5581 if (mode
== V2DFmode
)
5582 return zero_constant (op
, mode
);
5584 else if (mode
== V2DImode
)
5586 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5587 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5590 if (zero_constant (op
, mode
))
5593 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5594 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5600 /* V1TImode is a special container for TImode. Ignore for now. */
5601 else if (mode
== V1TImode
)
5604 /* Start with a vspltisw. */
5605 step
= GET_MODE_NUNITS (mode
) / 4;
5608 if (vspltis_constant (op
, step
, copies
))
5611 /* Then try with a vspltish. */
5617 if (vspltis_constant (op
, step
, copies
))
5620 /* And finally a vspltisb. */
5626 if (vspltis_constant (op
, step
, copies
))
5629 if (vspltis_shifted (op
) != 0)
5635 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5636 result is OP. Abort if it is not possible. */
5639 gen_easy_altivec_constant (rtx op
)
5641 machine_mode mode
= GET_MODE (op
);
5642 int nunits
= GET_MODE_NUNITS (mode
);
5643 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5644 unsigned step
= nunits
/ 4;
5645 unsigned copies
= 1;
5647 /* Start with a vspltisw. */
5648 if (vspltis_constant (op
, step
, copies
))
5649 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5651 /* Then try with a vspltish. */
5657 if (vspltis_constant (op
, step
, copies
))
5658 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5660 /* And finally a vspltisb. */
5666 if (vspltis_constant (op
, step
, copies
))
5667 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5673 output_vec_const_move (rtx
*operands
)
5675 int cst
, cst2
, shift
;
5681 mode
= GET_MODE (dest
);
5685 if (zero_constant (vec
, mode
))
5686 return "xxlxor %x0,%x0,%x0";
5688 if (TARGET_P8_VECTOR
&& vec
== CONSTM1_RTX (mode
))
5689 return "xxlorc %x0,%x0,%x0";
5691 if ((mode
== V2DImode
|| mode
== V1TImode
)
5692 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5693 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5694 return (TARGET_P8_VECTOR
) ? "xxlorc %x0,%x0,%x0" : "vspltisw %0,-1";
5700 if (zero_constant (vec
, mode
))
5701 return "vxor %0,%0,%0";
5703 /* Do we need to construct a value using VSLDOI? */
5704 shift
= vspltis_shifted (vec
);
5708 splat_vec
= gen_easy_altivec_constant (vec
);
5709 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5710 operands
[1] = XEXP (splat_vec
, 0);
5711 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5714 switch (GET_MODE (splat_vec
))
5717 return "vspltisw %0,%1";
5720 return "vspltish %0,%1";
5723 return "vspltisb %0,%1";
5730 gcc_assert (TARGET_SPE
);
5732 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5733 pattern of V1DI, V4HI, and V2SF.
5735 FIXME: We should probably return # and add post reload
5736 splitters for these, but this way is so easy ;-). */
5737 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5738 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5739 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5740 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5742 return "li %0,%1\n\tevmergelo %0,%0,%0";
5743 else if (WORDS_BIG_ENDIAN
)
5744 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5746 return "li %0,%2\n\tevmergelo %0,%0,%0\n\tli %0,%1";
5749 /* Initialize TARGET of vector PAIRED to VALS. */
5752 paired_expand_vector_init (rtx target
, rtx vals
)
5754 machine_mode mode
= GET_MODE (target
);
5755 int n_elts
= GET_MODE_NUNITS (mode
);
5757 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5760 for (i
= 0; i
< n_elts
; ++i
)
5762 x
= XVECEXP (vals
, 0, i
);
5763 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
5768 /* Load from constant pool. */
5769 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5775 /* The vector is initialized only with non-constants. */
5776 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5777 XVECEXP (vals
, 0, 1));
5779 emit_move_insn (target
, new_rtx
);
5783 /* One field is non-constant and the other one is a constant. Load the
5784 constant from the constant pool and use ps_merge instruction to
5785 construct the whole vector. */
5786 op1
= XVECEXP (vals
, 0, 0);
5787 op2
= XVECEXP (vals
, 0, 1);
5789 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5791 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5792 emit_move_insn (tmp
, constant_op
);
5794 if (CONSTANT_P (op1
))
5795 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5797 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5799 emit_move_insn (target
, new_rtx
);
5803 paired_expand_vector_move (rtx operands
[])
5805 rtx op0
= operands
[0], op1
= operands
[1];
5807 emit_move_insn (op0
, op1
);
5810 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5811 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5812 operands for the relation operation COND. This is a recursive
5816 paired_emit_vector_compare (enum rtx_code rcode
,
5817 rtx dest
, rtx op0
, rtx op1
,
5818 rtx cc_op0
, rtx cc_op1
)
5820 rtx tmp
= gen_reg_rtx (V2SFmode
);
5823 gcc_assert (TARGET_PAIRED_FLOAT
);
5824 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5830 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5834 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5835 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5839 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5842 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5845 tmp1
= gen_reg_rtx (V2SFmode
);
5846 max
= gen_reg_rtx (V2SFmode
);
5847 min
= gen_reg_rtx (V2SFmode
);
5848 gen_reg_rtx (V2SFmode
);
5850 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5851 emit_insn (gen_selv2sf4
5852 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5853 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5854 emit_insn (gen_selv2sf4
5855 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5856 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5857 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5860 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5863 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5866 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5869 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5872 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5881 /* Emit vector conditional expression.
5882 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5883 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5886 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5887 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5889 enum rtx_code rcode
= GET_CODE (cond
);
5891 if (!TARGET_PAIRED_FLOAT
)
5894 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5899 /* Initialize vector TARGET to VALS. */
5902 rs6000_expand_vector_init (rtx target
, rtx vals
)
5904 machine_mode mode
= GET_MODE (target
);
5905 machine_mode inner_mode
= GET_MODE_INNER (mode
);
5906 int n_elts
= GET_MODE_NUNITS (mode
);
5907 int n_var
= 0, one_var
= -1;
5908 bool all_same
= true, all_const_zero
= true;
5912 for (i
= 0; i
< n_elts
; ++i
)
5914 x
= XVECEXP (vals
, 0, i
);
5915 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
5916 ++n_var
, one_var
= i
;
5917 else if (x
!= CONST0_RTX (inner_mode
))
5918 all_const_zero
= false;
5920 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5926 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5927 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5928 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5930 /* Zero register. */
5931 emit_insn (gen_rtx_SET (target
, gen_rtx_XOR (mode
, target
, target
)));
5934 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5936 /* Splat immediate. */
5937 emit_insn (gen_rtx_SET (target
, const_vec
));
5942 /* Load from constant pool. */
5943 emit_move_insn (target
, const_vec
);
5948 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5949 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5951 rtx op0
= XVECEXP (vals
, 0, 0);
5952 rtx op1
= XVECEXP (vals
, 0, 1);
5955 if (!MEM_P (op0
) && !REG_P (op0
))
5956 op0
= force_reg (inner_mode
, op0
);
5957 if (mode
== V2DFmode
)
5958 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5960 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5964 op0
= force_reg (inner_mode
, op0
);
5965 op1
= force_reg (inner_mode
, op1
);
5966 if (mode
== V2DFmode
)
5967 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5969 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5974 /* With single precision floating point on VSX, know that internally single
5975 precision is actually represented as a double, and either make 2 V2DF
5976 vectors, and convert these vectors to single precision, or do one
5977 conversion, and splat the result to the other elements. */
5978 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5982 rtx freg
= gen_reg_rtx (V4SFmode
);
5983 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5984 rtx cvt
= ((TARGET_XSCVDPSPN
)
5985 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5986 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5989 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
, const0_rtx
));
5993 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5994 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5995 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5996 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5997 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5998 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5999 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
6000 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
6002 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
6003 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
6004 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6005 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6006 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
6011 /* Store value to stack temp. Load vector element. Splat. However, splat
6012 of 64-bit items is not supported on Altivec. */
6013 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
6015 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6016 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
6017 XVECEXP (vals
, 0, 0));
6018 x
= gen_rtx_UNSPEC (VOIDmode
,
6019 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6020 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6022 gen_rtx_SET (target
, mem
),
6024 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
6025 gen_rtx_PARALLEL (VOIDmode
,
6026 gen_rtvec (1, const0_rtx
)));
6027 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, x
)));
6031 /* One field is non-constant. Load constant then overwrite
6035 rtx copy
= copy_rtx (vals
);
6037 /* Load constant part of vector, substitute neighboring value for
6039 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
6040 rs6000_expand_vector_init (target
, copy
);
6042 /* Insert variable. */
6043 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
6047 /* Construct the vector in memory one field at a time
6048 and load the whole vector. */
6049 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6050 for (i
= 0; i
< n_elts
; i
++)
6051 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
6052 i
* GET_MODE_SIZE (inner_mode
)),
6053 XVECEXP (vals
, 0, i
));
6054 emit_move_insn (target
, mem
);
6057 /* Set field ELT of TARGET to VAL. */
6060 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
6062 machine_mode mode
= GET_MODE (target
);
6063 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6064 rtx reg
= gen_reg_rtx (mode
);
6066 int width
= GET_MODE_SIZE (inner_mode
);
6069 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
6071 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
6072 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
6073 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
6077 /* Simplify setting single element vectors like V1TImode. */
6078 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
6080 emit_move_insn (target
, gen_lowpart (mode
, val
));
6084 /* Load single variable value. */
6085 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
6086 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
6087 x
= gen_rtx_UNSPEC (VOIDmode
,
6088 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
6089 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6091 gen_rtx_SET (reg
, mem
),
6094 /* Linear sequence. */
6095 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
6096 for (i
= 0; i
< 16; ++i
)
6097 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
6099 /* Set permute mask to insert element into target. */
6100 for (i
= 0; i
< width
; ++i
)
6101 XVECEXP (mask
, 0, elt
*width
+ i
)
6102 = GEN_INT (i
+ 0x10);
6103 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
6105 if (BYTES_BIG_ENDIAN
)
6106 x
= gen_rtx_UNSPEC (mode
,
6107 gen_rtvec (3, target
, reg
,
6108 force_reg (V16QImode
, x
)),
6112 /* Invert selector. We prefer to generate VNAND on P8 so
6113 that future fusion opportunities can kick in, but must
6114 generate VNOR elsewhere. */
6115 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
6116 rtx iorx
= (TARGET_P8_VECTOR
6117 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
6118 : gen_rtx_AND (V16QImode
, notx
, notx
));
6119 rtx tmp
= gen_reg_rtx (V16QImode
);
6120 emit_insn (gen_rtx_SET (tmp
, iorx
));
6122 /* Permute with operands reversed and adjusted selector. */
6123 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
6127 emit_insn (gen_rtx_SET (target
, x
));
6130 /* Extract field ELT from VEC into TARGET. */
6133 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
6135 machine_mode mode
= GET_MODE (vec
);
6136 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6139 if (VECTOR_MEM_VSX_P (mode
))
6146 gcc_assert (elt
== 0 && inner_mode
== TImode
);
6147 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
6150 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
6153 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
6156 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
6161 /* Allocate mode-sized buffer. */
6162 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6164 emit_move_insn (mem
, vec
);
6166 /* Add offset to field within buffer matching vector element. */
6167 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
6169 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
6172 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
6175 invalid_e500_subreg (rtx op
, machine_mode mode
)
6177 if (TARGET_E500_DOUBLE
)
6179 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
6180 subreg:TI and reg:TF. Decimal float modes are like integer
6181 modes (only low part of each register used) for this
6183 if (GET_CODE (op
) == SUBREG
6184 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
6185 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
6186 && REG_P (SUBREG_REG (op
))
6187 && (GET_MODE (SUBREG_REG (op
)) == DFmode
6188 || GET_MODE (SUBREG_REG (op
)) == TFmode
6189 || GET_MODE (SUBREG_REG (op
)) == IFmode
6190 || GET_MODE (SUBREG_REG (op
)) == KFmode
))
6193 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
6195 if (GET_CODE (op
) == SUBREG
6196 && (mode
== DFmode
|| mode
== TFmode
|| mode
== IFmode
6198 && REG_P (SUBREG_REG (op
))
6199 && (GET_MODE (SUBREG_REG (op
)) == DImode
6200 || GET_MODE (SUBREG_REG (op
)) == TImode
6201 || GET_MODE (SUBREG_REG (op
)) == PTImode
6202 || GET_MODE (SUBREG_REG (op
)) == DDmode
6203 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
6208 && GET_CODE (op
) == SUBREG
6210 && REG_P (SUBREG_REG (op
))
6211 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
6217 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
6218 selects whether the alignment is abi mandated, optional, or
6219 both abi and optional alignment. */
6222 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
6224 if (how
!= align_opt
)
6226 if (TREE_CODE (type
) == VECTOR_TYPE
)
6228 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
6229 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
6234 else if (align
< 128)
6237 else if (TARGET_E500_DOUBLE
6238 && TREE_CODE (type
) == REAL_TYPE
6239 && TYPE_MODE (type
) == DFmode
)
6246 if (how
!= align_abi
)
6248 if (TREE_CODE (type
) == ARRAY_TYPE
6249 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
6251 if (align
< BITS_PER_WORD
)
6252 align
= BITS_PER_WORD
;
6259 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
6262 rs6000_special_adjust_field_align_p (tree field
, unsigned int computed
)
6264 if (TARGET_ALTIVEC
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6266 if (computed
!= 128)
6269 if (!warned
&& warn_psabi
)
6272 inform (input_location
,
6273 "the layout of aggregates containing vectors with"
6274 " %d-byte alignment has changed in GCC 5",
6275 computed
/ BITS_PER_UNIT
);
6278 /* In current GCC there is no special case. */
6285 /* AIX increases natural record alignment to doubleword if the first
6286 field is an FP double while the FP fields remain word aligned. */
6289 rs6000_special_round_type_align (tree type
, unsigned int computed
,
6290 unsigned int specified
)
6292 unsigned int align
= MAX (computed
, specified
);
6293 tree field
= TYPE_FIELDS (type
);
6295 /* Skip all non field decls */
6296 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
6297 field
= DECL_CHAIN (field
);
6299 if (field
!= NULL
&& field
!= type
)
6301 type
= TREE_TYPE (field
);
6302 while (TREE_CODE (type
) == ARRAY_TYPE
)
6303 type
= TREE_TYPE (type
);
6305 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
6306 align
= MAX (align
, 64);
6312 /* Darwin increases record alignment to the natural alignment of
6316 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
6317 unsigned int specified
)
6319 unsigned int align
= MAX (computed
, specified
);
6321 if (TYPE_PACKED (type
))
6324 /* Find the first field, looking down into aggregates. */
6326 tree field
= TYPE_FIELDS (type
);
6327 /* Skip all non field decls */
6328 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
6329 field
= DECL_CHAIN (field
);
6332 /* A packed field does not contribute any extra alignment. */
6333 if (DECL_PACKED (field
))
6335 type
= TREE_TYPE (field
);
6336 while (TREE_CODE (type
) == ARRAY_TYPE
)
6337 type
= TREE_TYPE (type
);
6338 } while (AGGREGATE_TYPE_P (type
));
6340 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
6341 align
= MAX (align
, TYPE_ALIGN (type
));
6346 /* Return 1 for an operand in small memory on V.4/eabi. */
6349 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
6350 machine_mode mode ATTRIBUTE_UNUSED
)
6355 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
6358 if (DEFAULT_ABI
!= ABI_V4
)
6361 /* Vector and float memory instructions have a limited offset on the
6362 SPE, so using a vector or float variable directly as an operand is
6365 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
6368 if (GET_CODE (op
) == SYMBOL_REF
)
6371 else if (GET_CODE (op
) != CONST
6372 || GET_CODE (XEXP (op
, 0)) != PLUS
6373 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
6374 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
6379 rtx sum
= XEXP (op
, 0);
6380 HOST_WIDE_INT summand
;
6382 /* We have to be careful here, because it is the referenced address
6383 that must be 32k from _SDA_BASE_, not just the symbol. */
6384 summand
= INTVAL (XEXP (sum
, 1));
6385 if (summand
< 0 || summand
> g_switch_value
)
6388 sym_ref
= XEXP (sum
, 0);
6391 return SYMBOL_REF_SMALL_P (sym_ref
);
6397 /* Return true if either operand is a general purpose register. */
6400 gpr_or_gpr_p (rtx op0
, rtx op1
)
6402 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
6403 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
6406 /* Return true if this is a move direct operation between GPR registers and
6407 floating point/VSX registers. */
6410 direct_move_p (rtx op0
, rtx op1
)
6414 if (!REG_P (op0
) || !REG_P (op1
))
6417 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
6420 regno0
= REGNO (op0
);
6421 regno1
= REGNO (op1
);
6422 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
6425 if (INT_REGNO_P (regno0
))
6426 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
6428 else if (INT_REGNO_P (regno1
))
6430 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
6433 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
6440 /* Return true if this is a load or store quad operation. This function does
6441 not handle the atomic quad memory instructions. */
6444 quad_load_store_p (rtx op0
, rtx op1
)
6448 if (!TARGET_QUAD_MEMORY
)
6451 else if (REG_P (op0
) && MEM_P (op1
))
6452 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
6453 && quad_memory_operand (op1
, GET_MODE (op1
))
6454 && !reg_overlap_mentioned_p (op0
, op1
));
6456 else if (MEM_P (op0
) && REG_P (op1
))
6457 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
6458 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
6463 if (TARGET_DEBUG_ADDR
)
6465 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
6466 ret
? "true" : "false");
6467 debug_rtx (gen_rtx_SET (op0
, op1
));
6473 /* Given an address, return a constant offset term if one exists. */
6476 address_offset (rtx op
)
6478 if (GET_CODE (op
) == PRE_INC
6479 || GET_CODE (op
) == PRE_DEC
)
6481 else if (GET_CODE (op
) == PRE_MODIFY
6482 || GET_CODE (op
) == LO_SUM
)
6485 if (GET_CODE (op
) == CONST
)
6488 if (GET_CODE (op
) == PLUS
)
6491 if (CONST_INT_P (op
))
6497 /* Return true if the MEM operand is a memory operand suitable for use
6498 with a (full width, possibly multiple) gpr load/store. On
6499 powerpc64 this means the offset must be divisible by 4.
6500 Implements 'Y' constraint.
6502 Accept direct, indexed, offset, lo_sum and tocref. Since this is
6503 a constraint function we know the operand has satisfied a suitable
6504 memory predicate. Also accept some odd rtl generated by reload
6505 (see rs6000_legitimize_reload_address for various forms). It is
6506 important that reload rtl be accepted by appropriate constraints
6507 but not by the operand predicate.
6509 Offsetting a lo_sum should not be allowed, except where we know by
6510 alignment that a 32k boundary is not crossed, but see the ???
6511 comment in rs6000_legitimize_reload_address. Note that by
6512 "offsetting" here we mean a further offset to access parts of the
6513 MEM. It's fine to have a lo_sum where the inner address is offset
6514 from a sym, since the same sym+offset will appear in the high part
6515 of the address calculation. */
6518 mem_operand_gpr (rtx op
, machine_mode mode
)
6520 unsigned HOST_WIDE_INT offset
;
6522 rtx addr
= XEXP (op
, 0);
6524 op
= address_offset (addr
);
6528 offset
= INTVAL (op
);
6529 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6532 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6536 if (GET_CODE (addr
) == LO_SUM
)
6537 /* For lo_sum addresses, we must allow any offset except one that
6538 causes a wrap, so test only the low 16 bits. */
6539 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6541 return offset
+ 0x8000 < 0x10000u
- extra
;
6544 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6547 reg_offset_addressing_ok_p (machine_mode mode
)
6561 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6562 TImode is not a vector mode, if we want to use the VSX registers to
6563 move it around, we need to restrict ourselves to reg+reg addressing.
6564 Similarly for IEEE 128-bit floating point that is passed in a single
6566 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6574 /* Paired vector modes. Only reg+reg addressing is valid. */
6575 if (TARGET_PAIRED_FLOAT
)
6580 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6581 addressing for the LFIWZX and STFIWX instructions. */
6582 if (TARGET_NO_SDMODE_STACK
)
6594 virtual_stack_registers_memory_p (rtx op
)
6598 if (GET_CODE (op
) == REG
)
6599 regnum
= REGNO (op
);
6601 else if (GET_CODE (op
) == PLUS
6602 && GET_CODE (XEXP (op
, 0)) == REG
6603 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6604 regnum
= REGNO (XEXP (op
, 0));
6609 return (regnum
>= FIRST_VIRTUAL_REGISTER
6610 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6613 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6614 is known to not straddle a 32k boundary. This function is used
6615 to determine whether -mcmodel=medium code can use TOC pointer
6616 relative addressing for OP. This means the alignment of the TOC
6617 pointer must also be taken into account, and unfortunately that is
6620 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
6621 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
6625 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6629 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6631 if (GET_CODE (op
) != SYMBOL_REF
)
6634 dsize
= GET_MODE_SIZE (mode
);
6635 decl
= SYMBOL_REF_DECL (op
);
6641 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6642 replacing memory addresses with an anchor plus offset. We
6643 could find the decl by rummaging around in the block->objects
6644 VEC for the given offset but that seems like too much work. */
6645 dalign
= BITS_PER_UNIT
;
6646 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6647 && SYMBOL_REF_ANCHOR_P (op
)
6648 && SYMBOL_REF_BLOCK (op
) != NULL
)
6650 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6652 dalign
= block
->alignment
;
6653 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6655 else if (CONSTANT_POOL_ADDRESS_P (op
))
6657 /* It would be nice to have get_pool_align().. */
6658 machine_mode cmode
= get_pool_mode (op
);
6660 dalign
= GET_MODE_ALIGNMENT (cmode
);
6663 else if (DECL_P (decl
))
6665 dalign
= DECL_ALIGN (decl
);
6669 /* Allow BLKmode when the entire object is known to not
6670 cross a 32k boundary. */
6671 if (!DECL_SIZE_UNIT (decl
))
6674 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6677 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6681 dalign
/= BITS_PER_UNIT
;
6682 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
6683 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
6684 return dalign
>= dsize
;
6690 /* Find how many bits of the alignment we know for this access. */
6691 dalign
/= BITS_PER_UNIT
;
6692 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
6693 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
6695 lsb
= offset
& -offset
;
6699 return dalign
>= dsize
;
6703 constant_pool_expr_p (rtx op
)
6707 split_const (op
, &base
, &offset
);
6708 return (GET_CODE (base
) == SYMBOL_REF
6709 && CONSTANT_POOL_ADDRESS_P (base
)
6710 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6713 static const_rtx tocrel_base
, tocrel_offset
;
6715 /* Return true if OP is a toc pointer relative address (the output
6716 of create_TOC_reference). If STRICT, do not match high part or
6717 non-split -mcmodel=large/medium toc pointer relative addresses. */
6720 toc_relative_expr_p (const_rtx op
, bool strict
)
6725 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6727 /* Only match the low part. */
6728 if (GET_CODE (op
) == LO_SUM
6729 && REG_P (XEXP (op
, 0))
6730 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6737 tocrel_offset
= const0_rtx
;
6738 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6740 tocrel_base
= XEXP (op
, 0);
6741 tocrel_offset
= XEXP (op
, 1);
6744 return (GET_CODE (tocrel_base
) == UNSPEC
6745 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6748 /* Return true if X is a constant pool address, and also for cmodel=medium
6749 if X is a toc-relative address known to be offsettable within MODE. */
6752 legitimate_constant_pool_address_p (const_rtx x
, machine_mode mode
,
6755 return (toc_relative_expr_p (x
, strict
)
6756 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6757 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6759 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6760 INTVAL (tocrel_offset
), mode
)));
6764 legitimate_small_data_p (machine_mode mode
, rtx x
)
6766 return (DEFAULT_ABI
== ABI_V4
6767 && !flag_pic
&& !TARGET_TOC
6768 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6769 && small_data_operand (x
, mode
));
6772 /* SPE offset addressing is limited to 5-bits worth of double words. */
6773 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6776 rs6000_legitimate_offset_address_p (machine_mode mode
, rtx x
,
6777 bool strict
, bool worst_case
)
6779 unsigned HOST_WIDE_INT offset
;
6782 if (GET_CODE (x
) != PLUS
)
6784 if (!REG_P (XEXP (x
, 0)))
6786 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6788 if (!reg_offset_addressing_ok_p (mode
))
6789 return virtual_stack_registers_memory_p (x
);
6790 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6792 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6795 offset
= INTVAL (XEXP (x
, 1));
6803 /* SPE vector modes. */
6804 return SPE_CONST_OFFSET_OK (offset
);
6809 /* On e500v2, we may have:
6811 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6813 Which gets addressed with evldd instructions. */
6814 if (TARGET_E500_DOUBLE
)
6815 return SPE_CONST_OFFSET_OK (offset
);
6817 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6819 if (VECTOR_MEM_VSX_P (mode
))
6824 if (!TARGET_POWERPC64
)
6826 else if (offset
& 3)
6833 if (TARGET_E500_DOUBLE
)
6834 return (SPE_CONST_OFFSET_OK (offset
)
6835 && SPE_CONST_OFFSET_OK (offset
+ 8));
6844 if (!TARGET_POWERPC64
)
6846 else if (offset
& 3)
6855 return offset
< 0x10000 - extra
;
6859 legitimate_indexed_address_p (rtx x
, int strict
)
6863 if (GET_CODE (x
) != PLUS
)
6869 /* Recognize the rtl generated by reload which we know will later be
6870 replaced with proper base and index regs. */
6872 && reload_in_progress
6873 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6877 return (REG_P (op0
) && REG_P (op1
)
6878 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6879 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6880 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6881 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6885 avoiding_indexed_address_p (machine_mode mode
)
6887 /* Avoid indexed addressing for modes that have non-indexed
6888 load/store instruction forms. */
6889 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6893 legitimate_indirect_address_p (rtx x
, int strict
)
6895 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6899 macho_lo_sum_memory_operand (rtx x
, machine_mode mode
)
6901 if (!TARGET_MACHO
|| !flag_pic
6902 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6906 if (GET_CODE (x
) != LO_SUM
)
6908 if (GET_CODE (XEXP (x
, 0)) != REG
)
6910 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6914 return CONSTANT_P (x
);
6918 legitimate_lo_sum_address_p (machine_mode mode
, rtx x
, int strict
)
6920 if (GET_CODE (x
) != LO_SUM
)
6922 if (GET_CODE (XEXP (x
, 0)) != REG
)
6924 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6926 /* Restrict addressing for DI because of our SUBREG hackery. */
6927 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6931 if (TARGET_ELF
|| TARGET_MACHO
)
6935 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6937 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6938 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6939 recognizes some LO_SUM addresses as valid although this
6940 function says opposite. In most cases, LRA through different
6941 transformations can generate correct code for address reloads.
6942 It can not manage only some LO_SUM cases. So we need to add
6943 code analogous to one in rs6000_legitimize_reload_address for
6944 LOW_SUM here saying that some addresses are still valid. */
6945 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6946 && small_toc_ref (x
, VOIDmode
));
6947 if (TARGET_TOC
&& ! large_toc_ok
)
6949 if (GET_MODE_NUNITS (mode
) != 1)
6951 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6952 && !(/* ??? Assume floating point reg based on mode? */
6953 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6954 && (mode
== DFmode
|| mode
== DDmode
)))
6957 return CONSTANT_P (x
) || large_toc_ok
;
6964 /* Try machine-dependent ways of modifying an illegitimate address
6965 to be legitimate. If we find one, return the new, valid address.
6966 This is used from only one place: `memory_address' in explow.c.
6968 OLDX is the address as it was before break_out_memory_refs was
6969 called. In some cases it is useful to look at this to decide what
6972 It is always safe for this function to do nothing. It exists to
6973 recognize opportunities to optimize the output.
6975 On RS/6000, first check for the sum of a register with a constant
6976 integer that is out of range. If so, generate code to add the
6977 constant with the low-order 16 bits masked to the register and force
6978 this result into another register (this can be done with `cau').
6979 Then generate an address of REG+(CONST&0xffff), allowing for the
6980 possibility of bit 16 being a one.
6982 Then check for the sum of a register and something not constant, try to
6983 load the other things into a register and return the sum. */
6986 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6991 if (!reg_offset_addressing_ok_p (mode
))
6993 if (virtual_stack_registers_memory_p (x
))
6996 /* In theory we should not be seeing addresses of the form reg+0,
6997 but just in case it is generated, optimize it away. */
6998 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6999 return force_reg (Pmode
, XEXP (x
, 0));
7001 /* For TImode with load/store quad, restrict addresses to just a single
7002 pointer, so it works with both GPRs and VSX registers. */
7003 /* Make sure both operands are registers. */
7004 else if (GET_CODE (x
) == PLUS
7005 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
7006 return gen_rtx_PLUS (Pmode
,
7007 force_reg (Pmode
, XEXP (x
, 0)),
7008 force_reg (Pmode
, XEXP (x
, 1)));
7010 return force_reg (Pmode
, x
);
7012 if (GET_CODE (x
) == SYMBOL_REF
)
7014 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
7016 return rs6000_legitimize_tls_address (x
, model
);
7028 /* As in legitimate_offset_address_p we do not assume
7029 worst-case. The mode here is just a hint as to the registers
7030 used. A TImode is usually in gprs, but may actually be in
7031 fprs. Leave worst-case scenario for reload to handle via
7032 insn constraints. PTImode is only GPRs. */
7039 if (GET_CODE (x
) == PLUS
7040 && GET_CODE (XEXP (x
, 0)) == REG
7041 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7042 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
7044 && !(SPE_VECTOR_MODE (mode
)
7045 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
7047 HOST_WIDE_INT high_int
, low_int
;
7049 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
7050 if (low_int
>= 0x8000 - extra
)
7052 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
7053 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
7054 GEN_INT (high_int
)), 0);
7055 return plus_constant (Pmode
, sum
, low_int
);
7057 else if (GET_CODE (x
) == PLUS
7058 && GET_CODE (XEXP (x
, 0)) == REG
7059 && GET_CODE (XEXP (x
, 1)) != CONST_INT
7060 && GET_MODE_NUNITS (mode
) == 1
7061 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
7062 || (/* ??? Assume floating point reg based on mode? */
7063 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7064 && (mode
== DFmode
|| mode
== DDmode
)))
7065 && !avoiding_indexed_address_p (mode
))
7067 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
7068 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
7070 else if (SPE_VECTOR_MODE (mode
)
7071 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
7075 /* We accept [reg + reg] and [reg + OFFSET]. */
7077 if (GET_CODE (x
) == PLUS
)
7079 rtx op1
= XEXP (x
, 0);
7080 rtx op2
= XEXP (x
, 1);
7083 op1
= force_reg (Pmode
, op1
);
7085 if (GET_CODE (op2
) != REG
7086 && (GET_CODE (op2
) != CONST_INT
7087 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
7088 || (GET_MODE_SIZE (mode
) > 8
7089 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
7090 op2
= force_reg (Pmode
, op2
);
7092 /* We can't always do [reg + reg] for these, because [reg +
7093 reg + offset] is not a legitimate addressing mode. */
7094 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
7096 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
7097 return force_reg (Pmode
, y
);
7102 return force_reg (Pmode
, x
);
7104 else if ((TARGET_ELF
7106 || !MACHO_DYNAMIC_NO_PIC_P
7112 && GET_CODE (x
) != CONST_INT
7113 && GET_CODE (x
) != CONST_WIDE_INT
7114 && GET_CODE (x
) != CONST_DOUBLE
7116 && GET_MODE_NUNITS (mode
) == 1
7117 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
7118 || (/* ??? Assume floating point reg based on mode? */
7119 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7120 && (mode
== DFmode
|| mode
== DDmode
))))
7122 rtx reg
= gen_reg_rtx (Pmode
);
7124 emit_insn (gen_elf_high (reg
, x
));
7126 emit_insn (gen_macho_high (reg
, x
));
7127 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
7130 && GET_CODE (x
) == SYMBOL_REF
7131 && constant_pool_expr_p (x
)
7132 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
7133 return create_TOC_reference (x
, NULL_RTX
);
7138 /* Debug version of rs6000_legitimize_address. */
7140 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
7146 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
7147 insns
= get_insns ();
7153 "\nrs6000_legitimize_address: mode %s, old code %s, "
7154 "new code %s, modified\n",
7155 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
7156 GET_RTX_NAME (GET_CODE (ret
)));
7158 fprintf (stderr
, "Original address:\n");
7161 fprintf (stderr
, "oldx:\n");
7164 fprintf (stderr
, "New address:\n");
7169 fprintf (stderr
, "Insns added:\n");
7170 debug_rtx_list (insns
, 20);
7176 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
7177 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
7188 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7189 We need to emit DTP-relative relocations. */
7191 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
7193 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7198 fputs ("\t.long\t", file
);
7201 fputs (DOUBLE_INT_ASM_OP
, file
);
7206 output_addr_const (file
, x
);
7208 fputs ("@dtprel+0x8000", file
);
7209 else if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
)
7211 switch (SYMBOL_REF_TLS_MODEL (x
))
7215 case TLS_MODEL_LOCAL_EXEC
:
7216 fputs ("@le", file
);
7218 case TLS_MODEL_INITIAL_EXEC
:
7219 fputs ("@ie", file
);
7221 case TLS_MODEL_GLOBAL_DYNAMIC
:
7222 case TLS_MODEL_LOCAL_DYNAMIC
:
7231 /* Return true if X is a symbol that refers to real (rather than emulated)
7235 rs6000_real_tls_symbol_ref_p (rtx x
)
7237 return (GET_CODE (x
) == SYMBOL_REF
7238 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
7241 /* In the name of slightly smaller debug output, and to cater to
7242 general assembler lossage, recognize various UNSPEC sequences
7243 and turn them back into a direct symbol reference. */
7246 rs6000_delegitimize_address (rtx orig_x
)
7250 orig_x
= delegitimize_mem_from_attrs (orig_x
);
7256 if (TARGET_CMODEL
!= CMODEL_SMALL
7257 && GET_CODE (y
) == LO_SUM
)
7261 if (GET_CODE (y
) == PLUS
7262 && GET_MODE (y
) == Pmode
7263 && CONST_INT_P (XEXP (y
, 1)))
7265 offset
= XEXP (y
, 1);
7269 if (GET_CODE (y
) == UNSPEC
7270 && XINT (y
, 1) == UNSPEC_TOCREL
)
7272 y
= XVECEXP (y
, 0, 0);
7275 /* Do not associate thread-local symbols with the original
7276 constant pool symbol. */
7278 && GET_CODE (y
) == SYMBOL_REF
7279 && CONSTANT_POOL_ADDRESS_P (y
)
7280 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
7284 if (offset
!= NULL_RTX
)
7285 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
7286 if (!MEM_P (orig_x
))
7289 return replace_equiv_address_nv (orig_x
, y
);
7293 && GET_CODE (orig_x
) == LO_SUM
7294 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
7296 y
= XEXP (XEXP (orig_x
, 1), 0);
7297 if (GET_CODE (y
) == UNSPEC
7298 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
7299 return XVECEXP (y
, 0, 0);
7305 /* Return true if X shouldn't be emitted into the debug info.
7306 The linker doesn't like .toc section references from
7307 .debug_* sections, so reject .toc section symbols. */
7310 rs6000_const_not_ok_for_debug_p (rtx x
)
7312 if (GET_CODE (x
) == SYMBOL_REF
7313 && CONSTANT_POOL_ADDRESS_P (x
))
7315 rtx c
= get_pool_constant (x
);
7316 machine_mode cmode
= get_pool_mode (x
);
7317 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
7324 /* Construct the SYMBOL_REF for the tls_get_addr function. */
7326 static GTY(()) rtx rs6000_tls_symbol
;
7328 rs6000_tls_get_addr (void)
7330 if (!rs6000_tls_symbol
)
7331 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
7333 return rs6000_tls_symbol
;
7336 /* Construct the SYMBOL_REF for TLS GOT references. */
7338 static GTY(()) rtx rs6000_got_symbol
;
7340 rs6000_got_sym (void)
7342 if (!rs6000_got_symbol
)
7344 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7345 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
7346 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
7349 return rs6000_got_symbol
;
7352 /* AIX Thread-Local Address support. */
7355 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
7357 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
7361 name
= XSTR (addr
, 0);
7362 /* Append TLS CSECT qualifier, unless the symbol already is qualified
7363 or the symbol will be in TLS private data section. */
7364 if (name
[strlen (name
) - 1] != ']'
7365 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
7366 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
7368 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
7369 strcpy (tlsname
, name
);
7371 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
7372 tlsaddr
= copy_rtx (addr
);
7373 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
7378 /* Place addr into TOC constant pool. */
7379 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
7381 /* Output the TOC entry and create the MEM referencing the value. */
7382 if (constant_pool_expr_p (XEXP (sym
, 0))
7383 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
7385 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
7386 mem
= gen_const_mem (Pmode
, tocref
);
7387 set_mem_alias_set (mem
, get_TOC_alias_set ());
7392 /* Use global-dynamic for local-dynamic. */
7393 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
7394 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
7396 /* Create new TOC reference for @m symbol. */
7397 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
7398 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
7399 strcpy (tlsname
, "*LCM");
7400 strcat (tlsname
, name
+ 3);
7401 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
7402 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
7403 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
7404 rtx modmem
= gen_const_mem (Pmode
, tocref
);
7405 set_mem_alias_set (modmem
, get_TOC_alias_set ());
7407 rtx modreg
= gen_reg_rtx (Pmode
);
7408 emit_insn (gen_rtx_SET (modreg
, modmem
));
7410 tmpreg
= gen_reg_rtx (Pmode
);
7411 emit_insn (gen_rtx_SET (tmpreg
, mem
));
7413 dest
= gen_reg_rtx (Pmode
);
7415 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
7417 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
7420 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
7421 else if (TARGET_32BIT
)
7423 tlsreg
= gen_reg_rtx (SImode
);
7424 emit_insn (gen_tls_get_tpointer (tlsreg
));
7427 tlsreg
= gen_rtx_REG (DImode
, 13);
7429 /* Load the TOC value into temporary register. */
7430 tmpreg
= gen_reg_rtx (Pmode
);
7431 emit_insn (gen_rtx_SET (tmpreg
, mem
));
7432 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
7433 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
7435 /* Add TOC symbol value to TLS pointer. */
7436 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
7441 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
7442 this (thread-local) address. */
7445 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
7450 return rs6000_legitimize_tls_address_aix (addr
, model
);
7452 dest
= gen_reg_rtx (Pmode
);
7453 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
7459 tlsreg
= gen_rtx_REG (Pmode
, 13);
7460 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
7464 tlsreg
= gen_rtx_REG (Pmode
, 2);
7465 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
7469 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
7473 tmp
= gen_reg_rtx (Pmode
);
7476 tlsreg
= gen_rtx_REG (Pmode
, 13);
7477 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
7481 tlsreg
= gen_rtx_REG (Pmode
, 2);
7482 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
7486 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
7488 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
7493 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
7495 /* We currently use relocations like @got@tlsgd for tls, which
7496 means the linker will handle allocation of tls entries, placing
7497 them in the .got section. So use a pointer to the .got section,
7498 not one to secondary TOC sections used by 64-bit -mminimal-toc,
7499 or to secondary GOT sections used by 32-bit -fPIC. */
7501 got
= gen_rtx_REG (Pmode
, 2);
7505 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
7508 rtx gsym
= rs6000_got_sym ();
7509 got
= gen_reg_rtx (Pmode
);
7511 rs6000_emit_move (got
, gsym
, Pmode
);
7516 tmp1
= gen_reg_rtx (Pmode
);
7517 tmp2
= gen_reg_rtx (Pmode
);
7518 mem
= gen_const_mem (Pmode
, tmp1
);
7519 lab
= gen_label_rtx ();
7520 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
7521 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
7522 if (TARGET_LINK_STACK
)
7523 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
7524 emit_move_insn (tmp2
, mem
);
7525 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
7526 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7531 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7533 tga
= rs6000_tls_get_addr ();
7534 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7535 1, const0_rtx
, Pmode
);
7537 r3
= gen_rtx_REG (Pmode
, 3);
7538 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7541 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7543 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7545 else if (DEFAULT_ABI
== ABI_V4
)
7546 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7549 call_insn
= last_call_insn ();
7550 PATTERN (call_insn
) = insn
;
7551 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7552 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7553 pic_offset_table_rtx
);
7555 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7557 tga
= rs6000_tls_get_addr ();
7558 tmp1
= gen_reg_rtx (Pmode
);
7559 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7560 1, const0_rtx
, Pmode
);
7562 r3
= gen_rtx_REG (Pmode
, 3);
7563 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7566 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7568 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7570 else if (DEFAULT_ABI
== ABI_V4
)
7571 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7574 call_insn
= last_call_insn ();
7575 PATTERN (call_insn
) = insn
;
7576 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7577 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7578 pic_offset_table_rtx
);
7580 if (rs6000_tls_size
== 16)
7583 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7585 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7587 else if (rs6000_tls_size
== 32)
7589 tmp2
= gen_reg_rtx (Pmode
);
7591 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7593 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7596 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7598 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7602 tmp2
= gen_reg_rtx (Pmode
);
7604 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7606 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7608 insn
= gen_rtx_SET (dest
, gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7614 /* IE, or 64-bit offset LE. */
7615 tmp2
= gen_reg_rtx (Pmode
);
7617 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7619 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7622 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7624 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7632 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7635 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7637 if (GET_CODE (x
) == HIGH
7638 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7641 /* A TLS symbol in the TOC cannot contain a sum. */
7642 if (GET_CODE (x
) == CONST
7643 && GET_CODE (XEXP (x
, 0)) == PLUS
7644 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7645 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7648 /* Do not place an ELF TLS symbol in the constant pool. */
7649 return TARGET_ELF
&& tls_referenced_p (x
);
7652 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7653 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7654 can be addressed relative to the toc pointer. */
7657 use_toc_relative_ref (rtx sym
, machine_mode mode
)
7659 return ((constant_pool_expr_p (sym
)
7660 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7661 get_pool_mode (sym
)))
7662 || (TARGET_CMODEL
== CMODEL_MEDIUM
7663 && SYMBOL_REF_LOCAL_P (sym
)
7664 && GET_MODE_SIZE (mode
) <= POWERPC64_TOC_POINTER_ALIGNMENT
));
7667 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7668 replace the input X, or the original X if no replacement is called for.
7669 The output parameter *WIN is 1 if the calling macro should goto WIN,
7672 For RS/6000, we wish to handle large displacements off a base
7673 register by splitting the addend across an addiu/addis and the mem insn.
7674 This cuts number of extra insns needed from 3 to 1.
7676 On Darwin, we use this to generate code for floating point constants.
7677 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7678 The Darwin code is inside #if TARGET_MACHO because only then are the
7679 machopic_* functions defined. */
7681 rs6000_legitimize_reload_address (rtx x
, machine_mode mode
,
7682 int opnum
, int type
,
7683 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7685 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7687 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7688 DFmode/DImode MEM. */
7691 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7692 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7693 reg_offset_p
= false;
7695 /* We must recognize output that we have already generated ourselves. */
7696 if (GET_CODE (x
) == PLUS
7697 && GET_CODE (XEXP (x
, 0)) == PLUS
7698 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7699 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7700 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7702 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7703 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7704 opnum
, (enum reload_type
) type
);
7709 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7710 if (GET_CODE (x
) == LO_SUM
7711 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7713 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7714 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7715 opnum
, (enum reload_type
) type
);
7721 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7722 && GET_CODE (x
) == LO_SUM
7723 && GET_CODE (XEXP (x
, 0)) == PLUS
7724 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7725 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7726 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7727 && machopic_operand_p (XEXP (x
, 1)))
7729 /* Result of previous invocation of this function on Darwin
7730 floating point constant. */
7731 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7732 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7733 opnum
, (enum reload_type
) type
);
7739 if (TARGET_CMODEL
!= CMODEL_SMALL
7741 && small_toc_ref (x
, VOIDmode
))
7743 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7744 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7745 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7746 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7747 opnum
, (enum reload_type
) type
);
7752 if (GET_CODE (x
) == PLUS
7753 && GET_CODE (XEXP (x
, 0)) == REG
7754 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7755 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7756 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7758 && !SPE_VECTOR_MODE (mode
)
7759 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7760 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7762 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7763 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7765 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7767 /* Check for 32-bit overflow. */
7768 if (high
+ low
!= val
)
7774 /* Reload the high part into a base reg; leave the low part
7775 in the mem directly. */
7777 x
= gen_rtx_PLUS (GET_MODE (x
),
7778 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7782 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7783 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7784 opnum
, (enum reload_type
) type
);
7789 if (GET_CODE (x
) == SYMBOL_REF
7791 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7792 && !SPE_VECTOR_MODE (mode
)
7794 && DEFAULT_ABI
== ABI_DARWIN
7795 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7796 && machopic_symbol_defined_p (x
)
7798 && DEFAULT_ABI
== ABI_V4
7801 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7802 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7804 ??? Assume floating point reg based on mode? This assumption is
7805 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7806 where reload ends up doing a DFmode load of a constant from
7807 mem using two gprs. Unfortunately, at this point reload
7808 hasn't yet selected regs so poking around in reload data
7809 won't help and even if we could figure out the regs reliably,
7810 we'd still want to allow this transformation when the mem is
7811 naturally aligned. Since we say the address is good here, we
7812 can't disable offsets from LO_SUMs in mem_operand_gpr.
7813 FIXME: Allow offset from lo_sum for other modes too, when
7814 mem is sufficiently aligned.
7816 Also disallow this if the type can go in VMX/Altivec registers, since
7817 those registers do not have d-form (reg+offset) address modes. */
7818 && !reg_addr
[mode
].scalar_in_vmx_p
7823 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7825 && (mode
!= DImode
|| TARGET_POWERPC64
)
7826 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7827 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7832 rtx offset
= machopic_gen_offset (x
);
7833 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7834 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7835 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7839 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7840 gen_rtx_HIGH (Pmode
, x
), x
);
7842 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7843 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7844 opnum
, (enum reload_type
) type
);
7849 /* Reload an offset address wrapped by an AND that represents the
7850 masking of the lower bits. Strip the outer AND and let reload
7851 convert the offset address into an indirect address. For VSX,
7852 force reload to create the address with an AND in a separate
7853 register, because we can't guarantee an altivec register will
7855 if (VECTOR_MEM_ALTIVEC_P (mode
)
7856 && GET_CODE (x
) == AND
7857 && GET_CODE (XEXP (x
, 0)) == PLUS
7858 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7859 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7860 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7861 && INTVAL (XEXP (x
, 1)) == -16)
7870 && GET_CODE (x
) == SYMBOL_REF
7871 && use_toc_relative_ref (x
, mode
))
7873 x
= create_TOC_reference (x
, NULL_RTX
);
7874 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7875 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7876 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7877 opnum
, (enum reload_type
) type
);
7885 /* Debug version of rs6000_legitimize_reload_address. */
7887 rs6000_debug_legitimize_reload_address (rtx x
, machine_mode mode
,
7888 int opnum
, int type
,
7889 int ind_levels
, int *win
)
7891 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7894 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7895 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7896 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7900 fprintf (stderr
, "Same address returned\n");
7902 fprintf (stderr
, "NULL returned\n");
7905 fprintf (stderr
, "New address:\n");
7912 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7913 that is a valid memory address for an instruction.
7914 The MODE argument is the machine mode for the MEM expression
7915 that wants to use this address.
7917 On the RS/6000, there are four valid address: a SYMBOL_REF that
7918 refers to a constant pool entry of an address (or the sum of it
7919 plus a constant), a short (16-bit signed) constant plus a register,
7920 the sum of two registers, or a register indirect, possibly with an
7921 auto-increment. For DFmode, DDmode and DImode with a constant plus
7922 register, we must ensure that both words are addressable or PowerPC64
7923 with offset word aligned.
7925 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7926 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7927 because adjacent memory cells are accessed by adding word-sized offsets
7928 during assembly output. */
7930 rs6000_legitimate_address_p (machine_mode mode
, rtx x
, bool reg_ok_strict
)
7932 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7934 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7935 if (VECTOR_MEM_ALTIVEC_P (mode
)
7936 && GET_CODE (x
) == AND
7937 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7938 && INTVAL (XEXP (x
, 1)) == -16)
7941 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7943 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7946 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7947 && mode_supports_pre_incdec_p (mode
)
7948 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7950 if (virtual_stack_registers_memory_p (x
))
7952 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7955 && legitimate_constant_pool_address_p (x
, mode
,
7956 reg_ok_strict
|| lra_in_progress
))
7958 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7959 allow register indirect addresses. This will allow the values to go in
7960 either GPRs or VSX registers without reloading. The vector types would
7961 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7962 somewhat split, in that some uses are GPR based, and some VSX based. */
7963 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7965 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7968 && GET_CODE (x
) == PLUS
7969 && GET_CODE (XEXP (x
, 0)) == REG
7970 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7971 || XEXP (x
, 0) == arg_pointer_rtx
)
7972 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7974 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7976 if (!FLOAT128_2REG_P (mode
)
7977 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7979 || (mode
!= DFmode
&& mode
!= DDmode
)
7980 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7981 && (TARGET_POWERPC64
|| mode
!= DImode
)
7982 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7984 && !avoiding_indexed_address_p (mode
)
7985 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7987 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7988 && mode_supports_pre_modify_p (mode
)
7989 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7990 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7991 reg_ok_strict
, false)
7992 || (!avoiding_indexed_address_p (mode
)
7993 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7994 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7996 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
8001 /* Debug version of rs6000_legitimate_address_p. */
8003 rs6000_debug_legitimate_address_p (machine_mode mode
, rtx x
,
8006 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
8008 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
8009 "strict = %d, reload = %s, code = %s\n",
8010 ret
? "true" : "false",
8011 GET_MODE_NAME (mode
),
8015 : (reload_in_progress
? "progress" : "before")),
8016 GET_RTX_NAME (GET_CODE (x
)));
8022 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
8025 rs6000_mode_dependent_address_p (const_rtx addr
,
8026 addr_space_t as ATTRIBUTE_UNUSED
)
8028 return rs6000_mode_dependent_address_ptr (addr
);
8031 /* Go to LABEL if ADDR (a legitimate address expression)
8032 has an effect that depends on the machine mode it is used for.
8034 On the RS/6000 this is true of all integral offsets (since AltiVec
8035 and VSX modes don't allow them) or is a pre-increment or decrement.
8037 ??? Except that due to conceptual problems in offsettable_address_p
8038 we can't really report the problems of integral offsets. So leave
8039 this assuming that the adjustable offset must be valid for the
8040 sub-words of a TFmode operand, which is what we had before. */
8043 rs6000_mode_dependent_address (const_rtx addr
)
8045 switch (GET_CODE (addr
))
8048 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
8049 is considered a legitimate address before reload, so there
8050 are no offset restrictions in that case. Note that this
8051 condition is safe in strict mode because any address involving
8052 virtual_stack_vars_rtx or arg_pointer_rtx would already have
8053 been rejected as illegitimate. */
8054 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
8055 && XEXP (addr
, 0) != arg_pointer_rtx
8056 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
8058 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
8059 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
8064 /* Anything in the constant pool is sufficiently aligned that
8065 all bytes have the same high part address. */
8066 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
8068 /* Auto-increment cases are now treated generically in recog.c. */
8070 return TARGET_UPDATE
;
8072 /* AND is only allowed in Altivec loads. */
8083 /* Debug version of rs6000_mode_dependent_address. */
8085 rs6000_debug_mode_dependent_address (const_rtx addr
)
8087 bool ret
= rs6000_mode_dependent_address (addr
);
8089 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
8090 ret
? "true" : "false");
8096 /* Implement FIND_BASE_TERM. */
8099 rs6000_find_base_term (rtx op
)
8104 if (GET_CODE (base
) == CONST
)
8105 base
= XEXP (base
, 0);
8106 if (GET_CODE (base
) == PLUS
)
8107 base
= XEXP (base
, 0);
8108 if (GET_CODE (base
) == UNSPEC
)
8109 switch (XINT (base
, 1))
8112 case UNSPEC_MACHOPIC_OFFSET
:
8113 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
8114 for aliasing purposes. */
8115 return XVECEXP (base
, 0, 0);
8121 /* More elaborate version of recog's offsettable_memref_p predicate
8122 that works around the ??? note of rs6000_mode_dependent_address.
8123 In particular it accepts
8125 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
8127 in 32-bit mode, that the recog predicate rejects. */
8130 rs6000_offsettable_memref_p (rtx op
, machine_mode reg_mode
)
8137 /* First mimic offsettable_memref_p. */
8138 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
8141 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
8142 the latter predicate knows nothing about the mode of the memory
8143 reference and, therefore, assumes that it is the largest supported
8144 mode (TFmode). As a consequence, legitimate offsettable memory
8145 references are rejected. rs6000_legitimate_offset_address_p contains
8146 the correct logic for the PLUS case of rs6000_mode_dependent_address,
8147 at least with a little bit of help here given that we know the
8148 actual registers used. */
8149 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
8150 || GET_MODE_SIZE (reg_mode
) == 4);
8151 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
8155 /* Change register usage conditional on target flags. */
8157 rs6000_conditional_register_usage (void)
8161 if (TARGET_DEBUG_TARGET
)
8162 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
8164 /* Set MQ register fixed (already call_used) so that it will not be
8168 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
8170 fixed_regs
[13] = call_used_regs
[13]
8171 = call_really_used_regs
[13] = 1;
8173 /* Conditionally disable FPRs. */
8174 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
8175 for (i
= 32; i
< 64; i
++)
8176 fixed_regs
[i
] = call_used_regs
[i
]
8177 = call_really_used_regs
[i
] = 1;
8179 /* The TOC register is not killed across calls in a way that is
8180 visible to the compiler. */
8181 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
8182 call_really_used_regs
[2] = 0;
8184 if (DEFAULT_ABI
== ABI_V4
8185 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
8187 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8189 if (DEFAULT_ABI
== ABI_V4
8190 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
8192 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8193 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8194 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8196 if (DEFAULT_ABI
== ABI_DARWIN
8197 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
8198 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8199 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8200 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8202 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
8203 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8204 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8208 global_regs
[SPEFSCR_REGNO
] = 1;
8209 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
8210 registers in prologues and epilogues. We no longer use r14
8211 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
8212 pool for link-compatibility with older versions of GCC. Once
8213 "old" code has died out, we can return r14 to the allocation
8216 = call_used_regs
[14]
8217 = call_really_used_regs
[14] = 1;
8220 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
8222 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
8223 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8224 call_really_used_regs
[VRSAVE_REGNO
] = 1;
8227 if (TARGET_ALTIVEC
|| TARGET_VSX
)
8228 global_regs
[VSCR_REGNO
] = 1;
8230 if (TARGET_ALTIVEC_ABI
)
8232 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
8233 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8235 /* AIX reserves VR20:31 in non-extended ABI mode. */
8237 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
8238 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8243 /* Output insns to set DEST equal to the constant SOURCE as a series of
8244 lis, ori and shl instructions and return TRUE. */
8247 rs6000_emit_set_const (rtx dest
, rtx source
)
8249 machine_mode mode
= GET_MODE (dest
);
8254 gcc_checking_assert (CONST_INT_P (source
));
8255 c
= INTVAL (source
);
8260 emit_insn (gen_rtx_SET (dest
, source
));
8264 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
8266 emit_insn (gen_rtx_SET (copy_rtx (temp
),
8267 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
8268 emit_insn (gen_rtx_SET (dest
,
8269 gen_rtx_IOR (SImode
, copy_rtx (temp
),
8270 GEN_INT (c
& 0xffff))));
8274 if (!TARGET_POWERPC64
)
8278 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
8280 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
8282 emit_move_insn (hi
, GEN_INT (c
>> 32));
8283 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
8284 emit_move_insn (lo
, GEN_INT (c
));
8287 rs6000_emit_set_long_const (dest
, c
);
8294 insn
= get_last_insn ();
8295 set
= single_set (insn
);
8296 if (! CONSTANT_P (SET_SRC (set
)))
8297 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
8302 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
8303 Output insns to set DEST equal to the constant C as a series of
8304 lis, ori and shl instructions. */
8307 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
8310 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
8320 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
8321 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
8322 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
8324 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
8325 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
8327 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8329 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8330 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
8332 emit_move_insn (dest
,
8333 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8336 else if (ud3
== 0 && ud4
== 0)
8338 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8340 gcc_assert (ud2
& 0x8000);
8341 emit_move_insn (copy_rtx (temp
),
8342 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
8344 emit_move_insn (copy_rtx (temp
),
8345 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8347 emit_move_insn (dest
,
8348 gen_rtx_ZERO_EXTEND (DImode
,
8349 gen_lowpart (SImode
,
8352 else if ((ud4
== 0xffff && (ud3
& 0x8000))
8353 || (ud4
== 0 && ! (ud3
& 0x8000)))
8355 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8357 emit_move_insn (copy_rtx (temp
),
8358 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
8360 emit_move_insn (copy_rtx (temp
),
8361 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8363 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8364 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
8367 emit_move_insn (dest
,
8368 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8373 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8375 emit_move_insn (copy_rtx (temp
),
8376 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
8378 emit_move_insn (copy_rtx (temp
),
8379 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8382 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
8383 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
8386 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8387 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8388 GEN_INT (ud2
<< 16)));
8390 emit_move_insn (dest
,
8391 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8396 /* Helper for the following. Get rid of [r+r] memory refs
8397 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
8400 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
8402 if (reload_in_progress
)
8405 if (GET_CODE (operands
[0]) == MEM
8406 && GET_CODE (XEXP (operands
[0], 0)) != REG
8407 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
8408 GET_MODE (operands
[0]), false))
8410 = replace_equiv_address (operands
[0],
8411 copy_addr_to_reg (XEXP (operands
[0], 0)));
8413 if (GET_CODE (operands
[1]) == MEM
8414 && GET_CODE (XEXP (operands
[1], 0)) != REG
8415 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
8416 GET_MODE (operands
[1]), false))
8418 = replace_equiv_address (operands
[1],
8419 copy_addr_to_reg (XEXP (operands
[1], 0)));
8422 /* Generate a vector of constants to permute MODE for a little-endian
8423 storage operation by swapping the two halves of a vector. */
8425 rs6000_const_vec (machine_mode mode
)
8453 v
= rtvec_alloc (subparts
);
8455 for (i
= 0; i
< subparts
/ 2; ++i
)
8456 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
8457 for (i
= subparts
/ 2; i
< subparts
; ++i
)
8458 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
8463 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
8464 for a VSX load or store operation. */
8466 rs6000_gen_le_vsx_permute (rtx source
, machine_mode mode
)
8468 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
8469 return gen_rtx_VEC_SELECT (mode
, source
, par
);
8472 /* Emit a little-endian load from vector memory location SOURCE to VSX
8473 register DEST in mode MODE. The load is done with two permuting
8474 insn's that represent an lxvd2x and xxpermdi. */
8476 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, machine_mode mode
)
8478 rtx tmp
, permute_mem
, permute_reg
;
8480 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8482 if (mode
== TImode
|| mode
== V1TImode
)
8485 dest
= gen_lowpart (V2DImode
, dest
);
8486 source
= adjust_address (source
, V2DImode
, 0);
8489 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
8490 permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
8491 permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8492 emit_insn (gen_rtx_SET (tmp
, permute_mem
));
8493 emit_insn (gen_rtx_SET (dest
, permute_reg
));
8496 /* Emit a little-endian store to vector memory location DEST from VSX
8497 register SOURCE in mode MODE. The store is done with two permuting
8498 insn's that represent an xxpermdi and an stxvd2x. */
8500 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, machine_mode mode
)
8502 rtx tmp
, permute_src
, permute_tmp
;
8504 /* This should never be called during or after reload, because it does
8505 not re-permute the source register. It is intended only for use
8507 gcc_assert (!reload_in_progress
&& !lra_in_progress
&& !reload_completed
);
8509 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
8511 if (mode
== TImode
|| mode
== V1TImode
)
8514 dest
= adjust_address (dest
, V2DImode
, 0);
8515 source
= gen_lowpart (V2DImode
, source
);
8518 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
8519 permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
8520 permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8521 emit_insn (gen_rtx_SET (tmp
, permute_src
));
8522 emit_insn (gen_rtx_SET (dest
, permute_tmp
));
8525 /* Emit a sequence representing a little-endian VSX load or store,
8526 moving data from SOURCE to DEST in mode MODE. This is done
8527 separately from rs6000_emit_move to ensure it is called only
8528 during expand. LE VSX loads and stores introduced later are
8529 handled with a split. The expand-time RTL generation allows
8530 us to optimize away redundant pairs of register-permutes. */
8532 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, machine_mode mode
)
8534 gcc_assert (!BYTES_BIG_ENDIAN
8535 && VECTOR_MEM_VSX_P (mode
)
8536 && !gpr_or_gpr_p (dest
, source
)
8537 && (MEM_P (source
) ^ MEM_P (dest
)));
8541 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
8542 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8546 if (!REG_P (source
))
8547 source
= force_reg (mode
, source
);
8548 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8552 /* Emit a move from SOURCE to DEST in mode MODE. */
8554 rs6000_emit_move (rtx dest
, rtx source
, machine_mode mode
)
8558 operands
[1] = source
;
8560 if (TARGET_DEBUG_ADDR
)
8563 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8564 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8565 GET_MODE_NAME (mode
),
8568 can_create_pseudo_p ());
8570 fprintf (stderr
, "source:\n");
8574 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8575 if (CONST_WIDE_INT_P (operands
[1])
8576 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8578 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8582 /* Check if GCC is setting up a block move that will end up using FP
8583 registers as temporaries. We must make sure this is acceptable. */
8584 if (GET_CODE (operands
[0]) == MEM
8585 && GET_CODE (operands
[1]) == MEM
8587 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8588 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8589 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8590 ? 32 : MEM_ALIGN (operands
[0])))
8591 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8593 : MEM_ALIGN (operands
[1]))))
8594 && ! MEM_VOLATILE_P (operands
[0])
8595 && ! MEM_VOLATILE_P (operands
[1]))
8597 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8598 adjust_address (operands
[1], SImode
, 0));
8599 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8600 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8604 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8605 && !gpc_reg_operand (operands
[1], mode
))
8606 operands
[1] = force_reg (mode
, operands
[1]);
8608 /* Recognize the case where operand[1] is a reference to thread-local
8609 data and load its address to a register. */
8610 if (tls_referenced_p (operands
[1]))
8612 enum tls_model model
;
8613 rtx tmp
= operands
[1];
8616 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8618 addend
= XEXP (XEXP (tmp
, 0), 1);
8619 tmp
= XEXP (XEXP (tmp
, 0), 0);
8622 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8623 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8624 gcc_assert (model
!= 0);
8626 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8629 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8630 tmp
= force_operand (tmp
, operands
[0]);
8635 /* Handle the case where reload calls us with an invalid address. */
8636 if (reload_in_progress
&& mode
== Pmode
8637 && (! general_operand (operands
[1], mode
)
8638 || ! nonimmediate_operand (operands
[0], mode
)))
8641 /* 128-bit constant floating-point values on Darwin should really be loaded
8642 as two parts. However, this premature splitting is a problem when DFmode
8643 values can go into Altivec registers. */
8644 if (FLOAT128_IBM_P (mode
) && !reg_addr
[DFmode
].scalar_in_vmx_p
8645 && GET_CODE (operands
[1]) == CONST_DOUBLE
)
8647 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8648 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8650 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8651 GET_MODE_SIZE (DFmode
)),
8652 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8653 GET_MODE_SIZE (DFmode
)),
8658 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8659 cfun
->machine
->sdmode_stack_slot
=
8660 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8663 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
8664 p1:SD) if p1 is not of floating point class and p0 is spilled as
8665 we can have no analogous movsd_store for this. */
8666 if (lra_in_progress
&& mode
== DDmode
8667 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8668 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8669 && GET_CODE (operands
[1]) == SUBREG
&& REG_P (SUBREG_REG (operands
[1]))
8670 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
8673 int regno
= REGNO (SUBREG_REG (operands
[1]));
8675 if (regno
>= FIRST_PSEUDO_REGISTER
)
8677 cl
= reg_preferred_class (regno
);
8678 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
8680 if (regno
>= 0 && ! FP_REGNO_P (regno
))
8683 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
8684 operands
[1] = SUBREG_REG (operands
[1]);
8689 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8690 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8691 && (REG_P (operands
[1])
8692 || (GET_CODE (operands
[1]) == SUBREG
8693 && REG_P (SUBREG_REG (operands
[1])))))
8695 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8696 ? SUBREG_REG (operands
[1]) : operands
[1]);
8699 if (regno
>= FIRST_PSEUDO_REGISTER
)
8701 cl
= reg_preferred_class (regno
);
8702 gcc_assert (cl
!= NO_REGS
);
8703 regno
= ira_class_hard_regs
[cl
][0];
8705 if (FP_REGNO_P (regno
))
8707 if (GET_MODE (operands
[0]) != DDmode
)
8708 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8709 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8711 else if (INT_REGNO_P (regno
))
8712 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8717 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
8718 p:DD)) if p0 is not of floating point class and p1 is spilled as
8719 we can have no analogous movsd_load for this. */
8720 if (lra_in_progress
&& mode
== DDmode
8721 && GET_CODE (operands
[0]) == SUBREG
&& REG_P (SUBREG_REG (operands
[0]))
8722 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
8723 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8724 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8727 int regno
= REGNO (SUBREG_REG (operands
[0]));
8729 if (regno
>= FIRST_PSEUDO_REGISTER
)
8731 cl
= reg_preferred_class (regno
);
8732 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
8734 if (regno
>= 0 && ! FP_REGNO_P (regno
))
8737 operands
[0] = SUBREG_REG (operands
[0]);
8738 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
8743 && (REG_P (operands
[0])
8744 || (GET_CODE (operands
[0]) == SUBREG
8745 && REG_P (SUBREG_REG (operands
[0]))))
8746 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8747 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8749 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8750 ? SUBREG_REG (operands
[0]) : operands
[0]);
8753 if (regno
>= FIRST_PSEUDO_REGISTER
)
8755 cl
= reg_preferred_class (regno
);
8756 gcc_assert (cl
!= NO_REGS
);
8757 regno
= ira_class_hard_regs
[cl
][0];
8759 if (FP_REGNO_P (regno
))
8761 if (GET_MODE (operands
[1]) != DDmode
)
8762 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8763 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8765 else if (INT_REGNO_P (regno
))
8766 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8772 if (reload_in_progress
8774 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8775 && MEM_P (operands
[0])
8776 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8777 && REG_P (operands
[1]))
8779 if (FP_REGNO_P (REGNO (operands
[1])))
8781 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8782 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8783 emit_insn (gen_movsd_store (mem
, operands
[1]));
8785 else if (INT_REGNO_P (REGNO (operands
[1])))
8787 rtx mem
= operands
[0];
8788 if (BYTES_BIG_ENDIAN
)
8789 mem
= adjust_address_nv (mem
, mode
, 4);
8790 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8791 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8797 if (reload_in_progress
8799 && REG_P (operands
[0])
8800 && MEM_P (operands
[1])
8801 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8802 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8804 if (FP_REGNO_P (REGNO (operands
[0])))
8806 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8807 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8808 emit_insn (gen_movsd_load (operands
[0], mem
));
8810 else if (INT_REGNO_P (REGNO (operands
[0])))
8812 rtx mem
= operands
[1];
8813 if (BYTES_BIG_ENDIAN
)
8814 mem
= adjust_address_nv (mem
, mode
, 4);
8815 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8816 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8823 /* FIXME: In the long term, this switch statement should go away
8824 and be replaced by a sequence of tests based on things like
8830 if (CONSTANT_P (operands
[1])
8831 && GET_CODE (operands
[1]) != CONST_INT
)
8832 operands
[1] = force_const_mem (mode
, operands
[1]);
8839 if (FLOAT128_2REG_P (mode
))
8840 rs6000_eliminate_indexed_memrefs (operands
);
8847 if (CONSTANT_P (operands
[1])
8848 && ! easy_fp_constant (operands
[1], mode
))
8849 operands
[1] = force_const_mem (mode
, operands
[1]);
8863 if (CONSTANT_P (operands
[1])
8864 && !easy_vector_constant (operands
[1], mode
))
8865 operands
[1] = force_const_mem (mode
, operands
[1]);
8870 /* Use default pattern for address of ELF small data */
8873 && DEFAULT_ABI
== ABI_V4
8874 && (GET_CODE (operands
[1]) == SYMBOL_REF
8875 || GET_CODE (operands
[1]) == CONST
)
8876 && small_data_operand (operands
[1], mode
))
8878 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
8882 if (DEFAULT_ABI
== ABI_V4
8883 && mode
== Pmode
&& mode
== SImode
8884 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8886 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8890 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8894 && CONSTANT_P (operands
[1])
8895 && GET_CODE (operands
[1]) != HIGH
8896 && GET_CODE (operands
[1]) != CONST_INT
)
8898 rtx target
= (!can_create_pseudo_p ()
8900 : gen_reg_rtx (mode
));
8902 /* If this is a function address on -mcall-aixdesc,
8903 convert it to the address of the descriptor. */
8904 if (DEFAULT_ABI
== ABI_AIX
8905 && GET_CODE (operands
[1]) == SYMBOL_REF
8906 && XSTR (operands
[1], 0)[0] == '.')
8908 const char *name
= XSTR (operands
[1], 0);
8910 while (*name
== '.')
8912 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8913 CONSTANT_POOL_ADDRESS_P (new_ref
)
8914 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8915 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8916 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8917 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8918 operands
[1] = new_ref
;
8921 if (DEFAULT_ABI
== ABI_DARWIN
)
8924 if (MACHO_DYNAMIC_NO_PIC_P
)
8926 /* Take care of any required data indirection. */
8927 operands
[1] = rs6000_machopic_legitimize_pic_address (
8928 operands
[1], mode
, operands
[0]);
8929 if (operands
[0] != operands
[1])
8930 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
8934 emit_insn (gen_macho_high (target
, operands
[1]));
8935 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8939 emit_insn (gen_elf_high (target
, operands
[1]));
8940 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8944 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8945 and we have put it in the TOC, we just need to make a TOC-relative
8948 && GET_CODE (operands
[1]) == SYMBOL_REF
8949 && use_toc_relative_ref (operands
[1], mode
))
8950 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8951 else if (mode
== Pmode
8952 && CONSTANT_P (operands
[1])
8953 && GET_CODE (operands
[1]) != HIGH
8954 && ((GET_CODE (operands
[1]) != CONST_INT
8955 && ! easy_fp_constant (operands
[1], mode
))
8956 || (GET_CODE (operands
[1]) == CONST_INT
8957 && (num_insns_constant (operands
[1], mode
)
8958 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8959 || (GET_CODE (operands
[0]) == REG
8960 && FP_REGNO_P (REGNO (operands
[0]))))
8961 && !toc_relative_expr_p (operands
[1], false)
8962 && (TARGET_CMODEL
== CMODEL_SMALL
8963 || can_create_pseudo_p ()
8964 || (REG_P (operands
[0])
8965 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8969 /* Darwin uses a special PIC legitimizer. */
8970 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8973 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8975 if (operands
[0] != operands
[1])
8976 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
8981 /* If we are to limit the number of things we put in the TOC and
8982 this is a symbol plus a constant we can add in one insn,
8983 just put the symbol in the TOC and add the constant. Don't do
8984 this if reload is in progress. */
8985 if (GET_CODE (operands
[1]) == CONST
8986 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8987 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8988 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8989 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8990 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8991 && ! side_effects_p (operands
[0]))
8994 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8995 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8997 sym
= force_reg (mode
, sym
);
8998 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
9002 operands
[1] = force_const_mem (mode
, operands
[1]);
9005 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
9006 && constant_pool_expr_p (XEXP (operands
[1], 0))
9007 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
9008 get_pool_constant (XEXP (operands
[1], 0)),
9009 get_pool_mode (XEXP (operands
[1], 0))))
9011 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
9013 operands
[1] = gen_const_mem (mode
, tocref
);
9014 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
9020 if (!VECTOR_MEM_VSX_P (TImode
))
9021 rs6000_eliminate_indexed_memrefs (operands
);
9025 rs6000_eliminate_indexed_memrefs (operands
);
9029 fatal_insn ("bad move", gen_rtx_SET (dest
, source
));
9032 /* Above, we may have called force_const_mem which may have returned
9033 an invalid address. If we can, fix this up; otherwise, reload will
9034 have to deal with it. */
9035 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
9036 operands
[1] = validize_mem (operands
[1]);
9039 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
9042 /* Return true if a structure, union or array containing FIELD should be
9043 accessed using `BLKMODE'.
9045 For the SPE, simd types are V2SI, and gcc can be tempted to put the
9046 entire thing in a DI and use subregs to access the internals.
9047 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
9048 back-end. Because a single GPR can hold a V2SI, but not a DI, the
9049 best thing to do is set structs to BLKmode and avoid Severe Tire
9052 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
9053 fit into 1, whereas DI still needs two. */
9056 rs6000_member_type_forces_blk (const_tree field
, machine_mode mode
)
9058 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
9059 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
9062 /* Nonzero if we can use a floating-point register to pass this arg. */
9063 #define USE_FP_FOR_ARG_P(CUM,MODE) \
9064 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
9065 && (CUM)->fregno <= FP_ARG_MAX_REG \
9066 && TARGET_HARD_FLOAT && TARGET_FPRS)
9068 /* Nonzero if we can use an AltiVec register to pass this arg. */
9069 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
9070 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
9071 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
9072 && TARGET_ALTIVEC_ABI \
9075 /* Walk down the type tree of TYPE counting consecutive base elements.
9076 If *MODEP is VOIDmode, then set it to the first valid floating point
9077 or vector type. If a non-floating point or vector type is found, or
9078 if a floating point or vector type that doesn't match a non-VOIDmode
9079 *MODEP is found, then return -1, otherwise return the count in the
9083 rs6000_aggregate_candidate (const_tree type
, machine_mode
*modep
)
9088 switch (TREE_CODE (type
))
9091 mode
= TYPE_MODE (type
);
9092 if (!SCALAR_FLOAT_MODE_P (mode
))
9095 if (*modep
== VOIDmode
)
9104 mode
= TYPE_MODE (TREE_TYPE (type
));
9105 if (!SCALAR_FLOAT_MODE_P (mode
))
9108 if (*modep
== VOIDmode
)
9117 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
9120 /* Use V4SImode as representative of all 128-bit vector types. */
9121 size
= int_size_in_bytes (type
);
9131 if (*modep
== VOIDmode
)
9134 /* Vector modes are considered to be opaque: two vectors are
9135 equivalent for the purposes of being homogeneous aggregates
9136 if they are the same size. */
9145 tree index
= TYPE_DOMAIN (type
);
9147 /* Can't handle incomplete types nor sizes that are not
9149 if (!COMPLETE_TYPE_P (type
)
9150 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9153 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
9156 || !TYPE_MAX_VALUE (index
)
9157 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
9158 || !TYPE_MIN_VALUE (index
)
9159 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
9163 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
9164 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
9166 /* There must be no padding. */
9167 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9179 /* Can't handle incomplete types nor sizes that are not
9181 if (!COMPLETE_TYPE_P (type
)
9182 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9185 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
9187 if (TREE_CODE (field
) != FIELD_DECL
)
9190 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
9196 /* There must be no padding. */
9197 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9204 case QUAL_UNION_TYPE
:
9206 /* These aren't very interesting except in a degenerate case. */
9211 /* Can't handle incomplete types nor sizes that are not
9213 if (!COMPLETE_TYPE_P (type
)
9214 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9217 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
9219 if (TREE_CODE (field
) != FIELD_DECL
)
9222 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
9225 count
= count
> sub_count
? count
: sub_count
;
9228 /* There must be no padding. */
9229 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9242 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
9243 float or vector aggregate that shall be passed in FP/vector registers
9244 according to the ELFv2 ABI, return the homogeneous element mode in
9245 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
9247 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
9250 rs6000_discover_homogeneous_aggregate (machine_mode mode
, const_tree type
,
9251 machine_mode
*elt_mode
,
9254 /* Note that we do not accept complex types at the top level as
9255 homogeneous aggregates; these types are handled via the
9256 targetm.calls.split_complex_arg mechanism. Complex types
9257 can be elements of homogeneous aggregates, however. */
9258 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
9260 machine_mode field_mode
= VOIDmode
;
9261 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
9263 if (field_count
> 0)
9265 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
) ?
9266 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
9268 /* The ELFv2 ABI allows homogeneous aggregates to occupy
9269 up to AGGR_ARG_NUM_REG registers. */
9270 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
9273 *elt_mode
= field_mode
;
9275 *n_elts
= field_count
;
9288 /* Return a nonzero value to say to return the function value in
9289 memory, just as large structures are always returned. TYPE will be
9290 the data type of the value, and FNTYPE will be the type of the
9291 function doing the returning, or @code{NULL} for libcalls.
9293 The AIX ABI for the RS/6000 specifies that all structures are
9294 returned in memory. The Darwin ABI does the same.
9296 For the Darwin 64 Bit ABI, a function result can be returned in
9297 registers or in memory, depending on the size of the return data
9298 type. If it is returned in registers, the value occupies the same
9299 registers as it would if it were the first and only function
9300 argument. Otherwise, the function places its result in memory at
9301 the location pointed to by GPR3.
9303 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
9304 but a draft put them in memory, and GCC used to implement the draft
9305 instead of the final standard. Therefore, aix_struct_return
9306 controls this instead of DEFAULT_ABI; V.4 targets needing backward
9307 compatibility can change DRAFT_V4_STRUCT_RET to override the
9308 default, and -m switches get the final word. See
9309 rs6000_option_override_internal for more details.
9311 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
9312 long double support is enabled. These values are returned in memory.
9314 int_size_in_bytes returns -1 for variable size objects, which go in
9315 memory always. The cast to unsigned makes -1 > 8. */
9318 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
9320 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
9322 && rs6000_darwin64_abi
9323 && TREE_CODE (type
) == RECORD_TYPE
9324 && int_size_in_bytes (type
) > 0)
9326 CUMULATIVE_ARGS valcum
;
9330 valcum
.fregno
= FP_ARG_MIN_REG
;
9331 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
9332 /* Do a trial code generation as if this were going to be passed
9333 as an argument; if any part goes in memory, we return NULL. */
9334 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
9337 /* Otherwise fall through to more conventional ABI rules. */
9340 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
9341 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
9345 /* The ELFv2 ABI returns aggregates up to 16B in registers */
9346 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
9347 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
9350 if (AGGREGATE_TYPE_P (type
)
9351 && (aix_struct_return
9352 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
9355 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
9356 modes only exist for GCC vector types if -maltivec. */
9357 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
9358 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
9361 /* Return synthetic vectors in memory. */
9362 if (TREE_CODE (type
) == VECTOR_TYPE
9363 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
9365 static bool warned_for_return_big_vectors
= false;
9366 if (!warned_for_return_big_vectors
)
9368 warning (0, "GCC vector returned by reference: "
9369 "non-standard ABI extension with no compatibility guarantee");
9370 warned_for_return_big_vectors
= true;
9375 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
9376 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
9382 /* Specify whether values returned in registers should be at the most
9383 significant end of a register. We want aggregates returned by
9384 value to match the way aggregates are passed to functions. */
9387 rs6000_return_in_msb (const_tree valtype
)
9389 return (DEFAULT_ABI
== ABI_ELFv2
9391 && AGGREGATE_TYPE_P (valtype
)
9392 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
9395 #ifdef HAVE_AS_GNU_ATTRIBUTE
9396 /* Return TRUE if a call to function FNDECL may be one that
9397 potentially affects the function calling ABI of the object file. */
9400 call_ABI_of_interest (tree fndecl
)
9402 if (symtab
->state
== EXPANSION
)
9404 struct cgraph_node
*c_node
;
9406 /* Libcalls are always interesting. */
9407 if (fndecl
== NULL_TREE
)
9410 /* Any call to an external function is interesting. */
9411 if (DECL_EXTERNAL (fndecl
))
9414 /* Interesting functions that we are emitting in this object file. */
9415 c_node
= cgraph_node::get (fndecl
);
9416 c_node
= c_node
->ultimate_alias_target ();
9417 return !c_node
->only_called_directly_p ();
9423 /* Initialize a variable CUM of type CUMULATIVE_ARGS
9424 for a call to a function whose data type is FNTYPE.
9425 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
9427 For incoming args we set the number of arguments in the prototype large
9428 so we never return a PARALLEL. */
9431 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
9432 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
9433 int libcall
, int n_named_args
,
9434 tree fndecl ATTRIBUTE_UNUSED
,
9435 machine_mode return_mode ATTRIBUTE_UNUSED
)
9437 static CUMULATIVE_ARGS zero_cumulative
;
9439 *cum
= zero_cumulative
;
9441 cum
->fregno
= FP_ARG_MIN_REG
;
9442 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
9443 cum
->prototype
= (fntype
&& prototype_p (fntype
));
9444 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
9445 ? CALL_LIBCALL
: CALL_NORMAL
);
9446 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
9447 cum
->stdarg
= stdarg_p (fntype
);
9449 cum
->nargs_prototype
= 0;
9450 if (incoming
|| cum
->prototype
)
9451 cum
->nargs_prototype
= n_named_args
;
9453 /* Check for a longcall attribute. */
9454 if ((!fntype
&& rs6000_default_long_calls
)
9456 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
9457 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
9458 cum
->call_cookie
|= CALL_LONG
;
9460 if (TARGET_DEBUG_ARG
)
9462 fprintf (stderr
, "\ninit_cumulative_args:");
9465 tree ret_type
= TREE_TYPE (fntype
);
9466 fprintf (stderr
, " ret code = %s,",
9467 get_tree_code_name (TREE_CODE (ret_type
)));
9470 if (cum
->call_cookie
& CALL_LONG
)
9471 fprintf (stderr
, " longcall,");
9473 fprintf (stderr
, " proto = %d, nargs = %d\n",
9474 cum
->prototype
, cum
->nargs_prototype
);
9477 #ifdef HAVE_AS_GNU_ATTRIBUTE
9478 if (DEFAULT_ABI
== ABI_V4
)
9480 cum
->escapes
= call_ABI_of_interest (fndecl
);
9487 return_type
= TREE_TYPE (fntype
);
9488 return_mode
= TYPE_MODE (return_type
);
9491 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
9493 if (return_type
!= NULL
)
9495 if (TREE_CODE (return_type
) == RECORD_TYPE
9496 && TYPE_TRANSPARENT_AGGR (return_type
))
9498 return_type
= TREE_TYPE (first_field (return_type
));
9499 return_mode
= TYPE_MODE (return_type
);
9501 if (AGGREGATE_TYPE_P (return_type
)
9502 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
9504 rs6000_returns_struct
= true;
9506 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (return_mode
))
9507 rs6000_passes_float
= true;
9508 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
9509 || SPE_VECTOR_MODE (return_mode
))
9510 rs6000_passes_vector
= true;
9517 && TARGET_ALTIVEC_ABI
9518 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
9520 error ("cannot return value in vector register because"
9521 " altivec instructions are disabled, use -maltivec"
9526 /* The mode the ABI uses for a word. This is not the same as word_mode
9527 for -m32 -mpowerpc64. This is used to implement various target hooks. */
9530 rs6000_abi_word_mode (void)
9532 return TARGET_32BIT
? SImode
: DImode
;
9535 /* On rs6000, function arguments are promoted, as are function return
9539 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
9541 int *punsignedp ATTRIBUTE_UNUSED
,
9544 PROMOTE_MODE (mode
, *punsignedp
, type
);
9549 /* Return true if TYPE must be passed on the stack and not in registers. */
9552 rs6000_must_pass_in_stack (machine_mode mode
, const_tree type
)
9554 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
9555 return must_pass_in_stack_var_size (mode
, type
);
9557 return must_pass_in_stack_var_size_or_pad (mode
, type
);
9560 /* If defined, a C expression which determines whether, and in which
9561 direction, to pad out an argument with extra space. The value
9562 should be of type `enum direction': either `upward' to pad above
9563 the argument, `downward' to pad below, or `none' to inhibit
9566 For the AIX ABI structs are always stored left shifted in their
9570 function_arg_padding (machine_mode mode
, const_tree type
)
9572 #ifndef AGGREGATE_PADDING_FIXED
9573 #define AGGREGATE_PADDING_FIXED 0
9575 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
9576 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
9579 if (!AGGREGATE_PADDING_FIXED
)
9581 /* GCC used to pass structures of the same size as integer types as
9582 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
9583 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
9584 passed padded downward, except that -mstrict-align further
9585 muddied the water in that multi-component structures of 2 and 4
9586 bytes in size were passed padded upward.
9588 The following arranges for best compatibility with previous
9589 versions of gcc, but removes the -mstrict-align dependency. */
9590 if (BYTES_BIG_ENDIAN
)
9592 HOST_WIDE_INT size
= 0;
9594 if (mode
== BLKmode
)
9596 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
9597 size
= int_size_in_bytes (type
);
9600 size
= GET_MODE_SIZE (mode
);
9602 if (size
== 1 || size
== 2 || size
== 4)
9608 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
9610 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
9614 /* Fall back to the default. */
9615 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
9618 /* If defined, a C expression that gives the alignment boundary, in bits,
9619 of an argument with the specified mode and type. If it is not defined,
9620 PARM_BOUNDARY is used for all arguments.
9622 V.4 wants long longs and doubles to be double word aligned. Just
9623 testing the mode size is a boneheaded way to do this as it means
9624 that other types such as complex int are also double word aligned.
9625 However, we're stuck with this because changing the ABI might break
9626 existing library interfaces.
9628 Doubleword align SPE vectors.
9629 Quadword align Altivec/VSX vectors.
9630 Quadword align large synthetic vector types. */
9633 rs6000_function_arg_boundary (machine_mode mode
, const_tree type
)
9635 machine_mode elt_mode
;
9638 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9640 if (DEFAULT_ABI
== ABI_V4
9641 && (GET_MODE_SIZE (mode
) == 8
9642 || (TARGET_HARD_FLOAT
9644 && FLOAT128_2REG_P (mode
))))
9646 else if (FLOAT128_VECTOR_P (mode
))
9648 else if (SPE_VECTOR_MODE (mode
)
9649 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9650 && int_size_in_bytes (type
) >= 8
9651 && int_size_in_bytes (type
) < 16))
9653 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9654 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9655 && int_size_in_bytes (type
) >= 16))
9658 /* Aggregate types that need > 8 byte alignment are quadword-aligned
9659 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
9660 -mcompat-align-parm is used. */
9661 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
9662 || DEFAULT_ABI
== ABI_ELFv2
)
9663 && type
&& TYPE_ALIGN (type
) > 64)
9665 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
9666 or homogeneous float/vector aggregates here. We already handled
9667 vector aggregates above, but still need to check for float here. */
9668 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
9669 && !SCALAR_FLOAT_MODE_P (elt_mode
));
9671 /* We used to check for BLKmode instead of the above aggregate type
9672 check. Warn when this results in any difference to the ABI. */
9673 if (aggregate_p
!= (mode
== BLKmode
))
9676 if (!warned
&& warn_psabi
)
9679 inform (input_location
,
9680 "the ABI of passing aggregates with %d-byte alignment"
9681 " has changed in GCC 5",
9682 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
9690 /* Similar for the Darwin64 ABI. Note that for historical reasons we
9691 implement the "aggregate type" check as a BLKmode check here; this
9692 means certain aggregate types are in fact not aligned. */
9693 if (TARGET_MACHO
&& rs6000_darwin64_abi
9695 && type
&& TYPE_ALIGN (type
) > 64)
9698 return PARM_BOUNDARY
;
9701 /* The offset in words to the start of the parameter save area. */
9704 rs6000_parm_offset (void)
9706 return (DEFAULT_ABI
== ABI_V4
? 2
9707 : DEFAULT_ABI
== ABI_ELFv2
? 4
9711 /* For a function parm of MODE and TYPE, return the starting word in
9712 the parameter area. NWORDS of the parameter area are already used. */
9715 rs6000_parm_start (machine_mode mode
, const_tree type
,
9716 unsigned int nwords
)
9720 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9721 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9724 /* Compute the size (in words) of a function argument. */
9726 static unsigned long
9727 rs6000_arg_size (machine_mode mode
, const_tree type
)
9731 if (mode
!= BLKmode
)
9732 size
= GET_MODE_SIZE (mode
);
9734 size
= int_size_in_bytes (type
);
9737 return (size
+ 3) >> 2;
9739 return (size
+ 7) >> 3;
9742 /* Use this to flush pending int fields. */
9745 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9746 HOST_WIDE_INT bitpos
, int final
)
9748 unsigned int startbit
, endbit
;
9749 int intregs
, intoffset
;
9752 /* Handle the situations where a float is taking up the first half
9753 of the GPR, and the other half is empty (typically due to
9754 alignment restrictions). We can detect this by a 8-byte-aligned
9755 int field, or by seeing that this is the final flush for this
9756 argument. Count the word and continue on. */
9757 if (cum
->floats_in_gpr
== 1
9758 && (cum
->intoffset
% 64 == 0
9759 || (cum
->intoffset
== -1 && final
)))
9762 cum
->floats_in_gpr
= 0;
9765 if (cum
->intoffset
== -1)
9768 intoffset
= cum
->intoffset
;
9769 cum
->intoffset
= -1;
9770 cum
->floats_in_gpr
= 0;
9772 if (intoffset
% BITS_PER_WORD
!= 0)
9774 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9776 if (mode
== BLKmode
)
9778 /* We couldn't find an appropriate mode, which happens,
9779 e.g., in packed structs when there are 3 bytes to load.
9780 Back intoffset back to the beginning of the word in this
9782 intoffset
= intoffset
& -BITS_PER_WORD
;
9786 startbit
= intoffset
& -BITS_PER_WORD
;
9787 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9788 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9789 cum
->words
+= intregs
;
9790 /* words should be unsigned. */
9791 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9793 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9798 /* The darwin64 ABI calls for us to recurse down through structs,
9799 looking for elements passed in registers. Unfortunately, we have
9800 to track int register count here also because of misalignments
9801 in powerpc alignment mode. */
9804 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9806 HOST_WIDE_INT startbitpos
)
9810 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9811 if (TREE_CODE (f
) == FIELD_DECL
)
9813 HOST_WIDE_INT bitpos
= startbitpos
;
9814 tree ftype
= TREE_TYPE (f
);
9816 if (ftype
== error_mark_node
)
9818 mode
= TYPE_MODE (ftype
);
9820 if (DECL_SIZE (f
) != 0
9821 && tree_fits_uhwi_p (bit_position (f
)))
9822 bitpos
+= int_bit_position (f
);
9824 /* ??? FIXME: else assume zero offset. */
9826 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9827 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9828 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9830 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9831 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9832 cum
->fregno
+= n_fpregs
;
9833 /* Single-precision floats present a special problem for
9834 us, because they are smaller than an 8-byte GPR, and so
9835 the structure-packing rules combined with the standard
9836 varargs behavior mean that we want to pack float/float
9837 and float/int combinations into a single register's
9838 space. This is complicated by the arg advance flushing,
9839 which works on arbitrarily large groups of int-type
9843 if (cum
->floats_in_gpr
== 1)
9845 /* Two floats in a word; count the word and reset
9848 cum
->floats_in_gpr
= 0;
9850 else if (bitpos
% 64 == 0)
9852 /* A float at the beginning of an 8-byte word;
9853 count it and put off adjusting cum->words until
9854 we see if a arg advance flush is going to do it
9856 cum
->floats_in_gpr
++;
9860 /* The float is at the end of a word, preceded
9861 by integer fields, so the arg advance flush
9862 just above has already set cum->words and
9863 everything is taken care of. */
9867 cum
->words
+= n_fpregs
;
9869 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9871 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9875 else if (cum
->intoffset
== -1)
9876 cum
->intoffset
= bitpos
;
9880 /* Check for an item that needs to be considered specially under the darwin 64
9881 bit ABI. These are record types where the mode is BLK or the structure is
9884 rs6000_darwin64_struct_check_p (machine_mode mode
, const_tree type
)
9886 return rs6000_darwin64_abi
9887 && ((mode
== BLKmode
9888 && TREE_CODE (type
) == RECORD_TYPE
9889 && int_size_in_bytes (type
) > 0)
9890 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9891 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9894 /* Update the data in CUM to advance over an argument
9895 of mode MODE and data type TYPE.
9896 (TYPE is null for libcalls where that information may not be available.)
9898 Note that for args passed by reference, function_arg will be called
9899 with MODE and TYPE set to that of the pointer to the arg, not the arg
9903 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, machine_mode mode
,
9904 const_tree type
, bool named
, int depth
)
9906 machine_mode elt_mode
;
9909 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9911 /* Only tick off an argument if we're not recursing. */
9913 cum
->nargs_prototype
--;
9915 #ifdef HAVE_AS_GNU_ATTRIBUTE
9916 if (DEFAULT_ABI
== ABI_V4
9919 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
))
9920 rs6000_passes_float
= true;
9921 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9922 rs6000_passes_vector
= true;
9923 else if (SPE_VECTOR_MODE (mode
)
9925 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9926 rs6000_passes_vector
= true;
9930 if (TARGET_ALTIVEC_ABI
9931 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9932 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9933 && int_size_in_bytes (type
) == 16)))
9937 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9939 cum
->vregno
+= n_elts
;
9941 if (!TARGET_ALTIVEC
)
9942 error ("cannot pass argument in vector register because"
9943 " altivec instructions are disabled, use -maltivec"
9946 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9947 even if it is going to be passed in a vector register.
9948 Darwin does the same for variable-argument functions. */
9949 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9951 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9961 /* Vector parameters must be 16-byte aligned. In 32-bit
9962 mode this means we need to take into account the offset
9963 to the parameter save area. In 64-bit mode, they just
9964 have to start on an even word, since the parameter save
9965 area is 16-byte aligned. */
9967 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9969 align
= cum
->words
& 1;
9970 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9972 if (TARGET_DEBUG_ARG
)
9974 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9976 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9977 cum
->nargs_prototype
, cum
->prototype
,
9978 GET_MODE_NAME (mode
));
9982 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9984 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9987 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9989 int size
= int_size_in_bytes (type
);
9990 /* Variable sized types have size == -1 and are
9991 treated as if consisting entirely of ints.
9992 Pad to 16 byte boundary if needed. */
9993 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9994 && (cum
->words
% 2) != 0)
9996 /* For varargs, we can just go up by the size of the struct. */
9998 cum
->words
+= (size
+ 7) / 8;
10001 /* It is tempting to say int register count just goes up by
10002 sizeof(type)/8, but this is wrong in a case such as
10003 { int; double; int; } [powerpc alignment]. We have to
10004 grovel through the fields for these too. */
10005 cum
->intoffset
= 0;
10006 cum
->floats_in_gpr
= 0;
10007 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
10008 rs6000_darwin64_record_arg_advance_flush (cum
,
10009 size
* BITS_PER_UNIT
, 1);
10011 if (TARGET_DEBUG_ARG
)
10013 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
10014 cum
->words
, TYPE_ALIGN (type
), size
);
10016 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
10017 cum
->nargs_prototype
, cum
->prototype
,
10018 GET_MODE_NAME (mode
));
10021 else if (DEFAULT_ABI
== ABI_V4
)
10023 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10024 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10025 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10026 || FLOAT128_2REG_P (mode
)
10027 || DECIMAL_FLOAT_MODE_P (mode
)))
10029 /* _Decimal128 must use an even/odd register pair. This assumes
10030 that the register number is odd when fregno is odd. */
10031 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10034 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
10035 <= FP_ARG_V4_MAX_REG
)
10036 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
10039 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
10040 if (mode
== DFmode
|| FLOAT128_IBM_P (mode
)
10041 || mode
== DDmode
|| mode
== TDmode
)
10042 cum
->words
+= cum
->words
& 1;
10043 cum
->words
+= rs6000_arg_size (mode
, type
);
10048 int n_words
= rs6000_arg_size (mode
, type
);
10049 int gregno
= cum
->sysv_gregno
;
10051 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10052 (r7,r8) or (r9,r10). As does any other 2 word item such
10053 as complex int due to a historical mistake. */
10055 gregno
+= (1 - gregno
) & 1;
10057 /* Multi-reg args are not split between registers and stack. */
10058 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10060 /* Long long and SPE vectors are aligned on the stack.
10061 So are other 2 word items such as complex int due to
10062 a historical mistake. */
10064 cum
->words
+= cum
->words
& 1;
10065 cum
->words
+= n_words
;
10068 /* Note: continuing to accumulate gregno past when we've started
10069 spilling to the stack indicates the fact that we've started
10070 spilling to the stack to expand_builtin_saveregs. */
10071 cum
->sysv_gregno
= gregno
+ n_words
;
10074 if (TARGET_DEBUG_ARG
)
10076 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
10077 cum
->words
, cum
->fregno
);
10078 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
10079 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
10080 fprintf (stderr
, "mode = %4s, named = %d\n",
10081 GET_MODE_NAME (mode
), named
);
10086 int n_words
= rs6000_arg_size (mode
, type
);
10087 int start_words
= cum
->words
;
10088 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
10090 cum
->words
= align_words
+ n_words
;
10092 if (SCALAR_FLOAT_MODE_P (elt_mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10094 /* _Decimal128 must be passed in an even/odd float register pair.
10095 This assumes that the register number is odd when fregno is
10097 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10099 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
10102 if (TARGET_DEBUG_ARG
)
10104 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
10105 cum
->words
, cum
->fregno
);
10106 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
10107 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
10108 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
10109 named
, align_words
- start_words
, depth
);
10115 rs6000_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
10116 const_tree type
, bool named
)
10118 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
10123 spe_build_register_parallel (machine_mode mode
, int gregno
)
10125 rtx r1
, r3
, r5
, r7
;
10130 r1
= gen_rtx_REG (DImode
, gregno
);
10131 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10132 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
10136 r1
= gen_rtx_REG (DImode
, gregno
);
10137 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10138 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
10139 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
10140 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
10143 r1
= gen_rtx_REG (DImode
, gregno
);
10144 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10145 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
10146 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
10147 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
10148 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
10149 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
10150 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
10151 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
10154 gcc_unreachable ();
10158 /* Determine where to put a SIMD argument on the SPE. */
10160 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, machine_mode mode
,
10163 int gregno
= cum
->sysv_gregno
;
10165 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
10166 are passed and returned in a pair of GPRs for ABI compatibility. */
10167 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
10168 || mode
== DCmode
|| mode
== TCmode
))
10170 int n_words
= rs6000_arg_size (mode
, type
);
10172 /* Doubles go in an odd/even register pair (r5/r6, etc). */
10173 if (mode
== DFmode
)
10174 gregno
+= (1 - gregno
) & 1;
10176 /* Multi-reg args are not split between registers and stack. */
10177 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10180 return spe_build_register_parallel (mode
, gregno
);
10184 int n_words
= rs6000_arg_size (mode
, type
);
10186 /* SPE vectors are put in odd registers. */
10187 if (n_words
== 2 && (gregno
& 1) == 0)
10190 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
10193 machine_mode m
= SImode
;
10195 r1
= gen_rtx_REG (m
, gregno
);
10196 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
10197 r2
= gen_rtx_REG (m
, gregno
+ 1);
10198 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
10199 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
10206 if (gregno
<= GP_ARG_MAX_REG
)
10207 return gen_rtx_REG (mode
, gregno
);
10213 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
10214 structure between cum->intoffset and bitpos to integer registers. */
10217 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
10218 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
10221 unsigned int regno
;
10222 unsigned int startbit
, endbit
;
10223 int this_regno
, intregs
, intoffset
;
10226 if (cum
->intoffset
== -1)
10229 intoffset
= cum
->intoffset
;
10230 cum
->intoffset
= -1;
10232 /* If this is the trailing part of a word, try to only load that
10233 much into the register. Otherwise load the whole register. Note
10234 that in the latter case we may pick up unwanted bits. It's not a
10235 problem at the moment but may wish to revisit. */
10237 if (intoffset
% BITS_PER_WORD
!= 0)
10239 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
10241 if (mode
== BLKmode
)
10243 /* We couldn't find an appropriate mode, which happens,
10244 e.g., in packed structs when there are 3 bytes to load.
10245 Back intoffset back to the beginning of the word in this
10247 intoffset
= intoffset
& -BITS_PER_WORD
;
10254 startbit
= intoffset
& -BITS_PER_WORD
;
10255 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
10256 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
10257 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
10259 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
10260 cum
->use_stack
= 1;
10262 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
10266 intoffset
/= BITS_PER_UNIT
;
10269 regno
= GP_ARG_MIN_REG
+ this_regno
;
10270 reg
= gen_rtx_REG (mode
, regno
);
10272 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
10275 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
10279 while (intregs
> 0);
10282 /* Recursive workhorse for the following. */
10285 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
10286 HOST_WIDE_INT startbitpos
, rtx rvec
[],
10291 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
10292 if (TREE_CODE (f
) == FIELD_DECL
)
10294 HOST_WIDE_INT bitpos
= startbitpos
;
10295 tree ftype
= TREE_TYPE (f
);
10297 if (ftype
== error_mark_node
)
10299 mode
= TYPE_MODE (ftype
);
10301 if (DECL_SIZE (f
) != 0
10302 && tree_fits_uhwi_p (bit_position (f
)))
10303 bitpos
+= int_bit_position (f
);
10305 /* ??? FIXME: else assume zero offset. */
10307 if (TREE_CODE (ftype
) == RECORD_TYPE
)
10308 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
10309 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
10311 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
10315 case SCmode
: mode
= SFmode
; break;
10316 case DCmode
: mode
= DFmode
; break;
10317 case TCmode
: mode
= TFmode
; break;
10321 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
10322 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
10324 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
10325 && (mode
== TFmode
|| mode
== TDmode
));
10326 /* Long double or _Decimal128 split over regs and memory. */
10327 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
10331 = gen_rtx_EXPR_LIST (VOIDmode
,
10332 gen_rtx_REG (mode
, cum
->fregno
++),
10333 GEN_INT (bitpos
/ BITS_PER_UNIT
));
10334 if (FLOAT128_2REG_P (mode
))
10337 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
10339 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
10341 = gen_rtx_EXPR_LIST (VOIDmode
,
10342 gen_rtx_REG (mode
, cum
->vregno
++),
10343 GEN_INT (bitpos
/ BITS_PER_UNIT
));
10345 else if (cum
->intoffset
== -1)
10346 cum
->intoffset
= bitpos
;
10350 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
10351 the register(s) to be used for each field and subfield of a struct
10352 being passed by value, along with the offset of where the
10353 register's value may be found in the block. FP fields go in FP
10354 register, vector fields go in vector registers, and everything
10355 else goes in int registers, packed as in memory.
10357 This code is also used for function return values. RETVAL indicates
10358 whether this is the case.
10360 Much of this is taken from the SPARC V9 port, which has a similar
10361 calling convention. */
10364 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
10365 bool named
, bool retval
)
10367 rtx rvec
[FIRST_PSEUDO_REGISTER
];
10368 int k
= 1, kbase
= 1;
10369 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
10370 /* This is a copy; modifications are not visible to our caller. */
10371 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
10372 CUMULATIVE_ARGS
*cum
= ©_cum
;
10374 /* Pad to 16 byte boundary if needed. */
10375 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
10376 && (cum
->words
% 2) != 0)
10379 cum
->intoffset
= 0;
10380 cum
->use_stack
= 0;
10381 cum
->named
= named
;
10383 /* Put entries into rvec[] for individual FP and vector fields, and
10384 for the chunks of memory that go in int regs. Note we start at
10385 element 1; 0 is reserved for an indication of using memory, and
10386 may or may not be filled in below. */
10387 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
10388 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
10390 /* If any part of the struct went on the stack put all of it there.
10391 This hack is because the generic code for
10392 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
10393 parts of the struct are not at the beginning. */
10394 if (cum
->use_stack
)
10397 return NULL_RTX
; /* doesn't go in registers at all */
10399 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10401 if (k
> 1 || cum
->use_stack
)
10402 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
10407 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
10410 rs6000_mixed_function_arg (machine_mode mode
, const_tree type
,
10415 rtx rvec
[GP_ARG_NUM_REG
+ 1];
10417 if (align_words
>= GP_ARG_NUM_REG
)
10420 n_units
= rs6000_arg_size (mode
, type
);
10422 /* Optimize the simple case where the arg fits in one gpr, except in
10423 the case of BLKmode due to assign_parms assuming that registers are
10424 BITS_PER_WORD wide. */
10426 || (n_units
== 1 && mode
!= BLKmode
))
10427 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10430 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
10431 /* Not all of the arg fits in gprs. Say that it goes in memory too,
10432 using a magic NULL_RTX component.
10433 This is not strictly correct. Only some of the arg belongs in
10434 memory, not all of it. However, the normal scheme using
10435 function_arg_partial_nregs can result in unusual subregs, eg.
10436 (subreg:SI (reg:DF) 4), which are not handled well. The code to
10437 store the whole arg to memory is often more efficient than code
10438 to store pieces, and we know that space is available in the right
10439 place for the whole arg. */
10440 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10445 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
10446 rtx off
= GEN_INT (i
++ * 4);
10447 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10449 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
10451 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10454 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
10455 but must also be copied into the parameter save area starting at
10456 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
10457 to the GPRs and/or memory. Return the number of elements used. */
10460 rs6000_psave_function_arg (machine_mode mode
, const_tree type
,
10461 int align_words
, rtx
*rvec
)
10465 if (align_words
< GP_ARG_NUM_REG
)
10467 int n_words
= rs6000_arg_size (mode
, type
);
10469 if (align_words
+ n_words
> GP_ARG_NUM_REG
10471 || (TARGET_32BIT
&& TARGET_POWERPC64
))
10473 /* If this is partially on the stack, then we only
10474 include the portion actually in registers here. */
10475 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
10478 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10480 /* Not all of the arg fits in gprs. Say that it goes in memory
10481 too, using a magic NULL_RTX component. Also see comment in
10482 rs6000_mixed_function_arg for why the normal
10483 function_arg_partial_nregs scheme doesn't work in this case. */
10484 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10489 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
10490 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
10491 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10493 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
10497 /* The whole arg fits in gprs. */
10498 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10499 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
10504 /* It's entirely in memory. */
10505 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10511 /* RVEC is a vector of K components of an argument of mode MODE.
10512 Construct the final function_arg return value from it. */
10515 rs6000_finish_function_arg (machine_mode mode
, rtx
*rvec
, int k
)
10517 gcc_assert (k
>= 1);
10519 /* Avoid returning a PARALLEL in the trivial cases. */
10522 if (XEXP (rvec
[0], 0) == NULL_RTX
)
10525 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
10526 return XEXP (rvec
[0], 0);
10529 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10532 /* Determine where to put an argument to a function.
10533 Value is zero to push the argument on the stack,
10534 or a hard register in which to store the argument.
10536 MODE is the argument's machine mode.
10537 TYPE is the data type of the argument (as a tree).
10538 This is null for libcalls where that information may
10540 CUM is a variable of type CUMULATIVE_ARGS which gives info about
10541 the preceding args and about the function being called. It is
10542 not modified in this routine.
10543 NAMED is nonzero if this argument is a named parameter
10544 (otherwise it is an extra parameter matching an ellipsis).
10546 On RS/6000 the first eight words of non-FP are normally in registers
10547 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
10548 Under V.4, the first 8 FP args are in registers.
10550 If this is floating-point and no prototype is specified, we use
10551 both an FP and integer register (or possibly FP reg and stack). Library
10552 functions (when CALL_LIBCALL is set) always have the proper types for args,
10553 so we can pass the FP value just in one register. emit_library_function
10554 doesn't support PARALLEL anyway.
10556 Note that for args passed by reference, function_arg will be called
10557 with MODE and TYPE set to that of the pointer to the arg, not the arg
10561 rs6000_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
10562 const_tree type
, bool named
)
10564 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10565 enum rs6000_abi abi
= DEFAULT_ABI
;
10566 machine_mode elt_mode
;
10569 /* Return a marker to indicate whether CR1 needs to set or clear the
10570 bit that V.4 uses to say fp args were passed in registers.
10571 Assume that we don't need the marker for software floating point,
10572 or compiler generated library calls. */
10573 if (mode
== VOIDmode
)
10576 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
10578 || (cum
->nargs_prototype
< 0
10579 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
10581 /* For the SPE, we need to crxor CR6 always. */
10582 if (TARGET_SPE_ABI
)
10583 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
10584 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10585 return GEN_INT (cum
->call_cookie
10586 | ((cum
->fregno
== FP_ARG_MIN_REG
)
10587 ? CALL_V4_SET_FP_ARGS
10588 : CALL_V4_CLEAR_FP_ARGS
));
10591 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
10594 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10596 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10598 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
10599 if (rslt
!= NULL_RTX
)
10601 /* Else fall through to usual handling. */
10604 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10606 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10610 /* Do we also need to pass this argument in the parameter
10612 if (TARGET_64BIT
&& ! cum
->prototype
)
10614 int align_words
= (cum
->words
+ 1) & ~1;
10615 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10618 /* Describe where this argument goes in the vector registers. */
10619 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
10621 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
10622 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10623 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10626 return rs6000_finish_function_arg (mode
, rvec
, k
);
10628 else if (TARGET_ALTIVEC_ABI
10629 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
10630 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10631 && int_size_in_bytes (type
) == 16)))
10633 if (named
|| abi
== ABI_V4
)
10637 /* Vector parameters to varargs functions under AIX or Darwin
10638 get passed in memory and possibly also in GPRs. */
10639 int align
, align_words
, n_words
;
10640 machine_mode part_mode
;
10642 /* Vector parameters must be 16-byte aligned. In 32-bit
10643 mode this means we need to take into account the offset
10644 to the parameter save area. In 64-bit mode, they just
10645 have to start on an even word, since the parameter save
10646 area is 16-byte aligned. */
10648 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
10650 align
= cum
->words
& 1;
10651 align_words
= cum
->words
+ align
;
10653 /* Out of registers? Memory, then. */
10654 if (align_words
>= GP_ARG_NUM_REG
)
10657 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10658 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10660 /* The vector value goes in GPRs. Only the part of the
10661 value in GPRs is reported here. */
10663 n_words
= rs6000_arg_size (mode
, type
);
10664 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10665 /* Fortunately, there are only two possibilities, the value
10666 is either wholly in GPRs or half in GPRs and half not. */
10667 part_mode
= DImode
;
10669 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10672 else if (TARGET_SPE_ABI
&& TARGET_SPE
10673 && (SPE_VECTOR_MODE (mode
)
10674 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10677 || mode
== TCmode
))))
10678 return rs6000_spe_function_arg (cum
, mode
, type
);
10680 else if (abi
== ABI_V4
)
10682 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10683 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10684 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10685 || FLOAT128_2REG_P (mode
)
10686 || DECIMAL_FLOAT_MODE_P (mode
)))
10688 /* _Decimal128 must use an even/odd register pair. This assumes
10689 that the register number is odd when fregno is odd. */
10690 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10693 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
10694 <= FP_ARG_V4_MAX_REG
)
10695 return gen_rtx_REG (mode
, cum
->fregno
);
10701 int n_words
= rs6000_arg_size (mode
, type
);
10702 int gregno
= cum
->sysv_gregno
;
10704 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10705 (r7,r8) or (r9,r10). As does any other 2 word item such
10706 as complex int due to a historical mistake. */
10708 gregno
+= (1 - gregno
) & 1;
10710 /* Multi-reg args are not split between registers and stack. */
10711 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10714 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10715 return rs6000_mixed_function_arg (mode
, type
,
10716 gregno
- GP_ARG_MIN_REG
);
10717 return gen_rtx_REG (mode
, gregno
);
10722 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10724 /* _Decimal128 must be passed in an even/odd float register pair.
10725 This assumes that the register number is odd when fregno is odd. */
10726 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10729 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10731 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10734 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10737 /* Do we also need to pass this argument in the parameter
10739 if (type
&& (cum
->nargs_prototype
<= 0
10740 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10741 && TARGET_XL_COMPAT
10742 && align_words
>= GP_ARG_NUM_REG
)))
10743 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10745 /* Describe where this argument goes in the fprs. */
10746 for (i
= 0; i
< n_elts
10747 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10749 /* Check if the argument is split over registers and memory.
10750 This can only ever happen for long double or _Decimal128;
10751 complex types are handled via split_complex_arg. */
10752 machine_mode fmode
= elt_mode
;
10753 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10755 gcc_assert (FLOAT128_2REG_P (fmode
));
10756 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10759 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10760 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10761 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10764 /* If there were not enough FPRs to hold the argument, the rest
10765 usually goes into memory. However, if the current position
10766 is still within the register parameter area, a portion may
10767 actually have to go into GPRs.
10769 Note that it may happen that the portion of the argument
10770 passed in the first "half" of the first GPR was already
10771 passed in the last FPR as well.
10773 For unnamed arguments, we already set up GPRs to cover the
10774 whole argument in rs6000_psave_function_arg, so there is
10775 nothing further to do at this point. */
10776 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
10777 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
10778 && cum
->nargs_prototype
> 0)
10780 static bool warned
;
10782 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
10783 int n_words
= rs6000_arg_size (mode
, type
);
10785 align_words
+= fpr_words
;
10786 n_words
-= fpr_words
;
10790 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
10791 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
10792 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10794 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
10796 if (!warned
&& warn_psabi
)
10799 inform (input_location
,
10800 "the ABI of passing homogeneous float aggregates"
10801 " has changed in GCC 5");
10805 return rs6000_finish_function_arg (mode
, rvec
, k
);
10807 else if (align_words
< GP_ARG_NUM_REG
)
10809 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10810 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10812 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10819 /* For an arg passed partly in registers and partly in memory, this is
10820 the number of bytes passed in registers. For args passed entirely in
10821 registers or entirely in memory, zero. When an arg is described by a
10822 PARALLEL, perhaps using more than one register type, this function
10823 returns the number of bytes used by the first element of the PARALLEL. */
10826 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
10827 tree type
, bool named
)
10829 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10830 bool passed_in_gprs
= true;
10833 machine_mode elt_mode
;
10836 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10838 if (DEFAULT_ABI
== ABI_V4
)
10841 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10843 /* If we are passing this arg in the fixed parameter save area
10844 (gprs or memory) as well as VRs, we do not use the partial
10845 bytes mechanism; instead, rs6000_function_arg will return a
10846 PARALLEL including a memory element as necessary. */
10847 if (TARGET_64BIT
&& ! cum
->prototype
)
10850 /* Otherwise, we pass in VRs only. Check for partial copies. */
10851 passed_in_gprs
= false;
10852 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10853 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10856 /* In this complicated case we just disable the partial_nregs code. */
10857 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10860 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10862 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10864 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10866 /* If we are passing this arg in the fixed parameter save area
10867 (gprs or memory) as well as FPRs, we do not use the partial
10868 bytes mechanism; instead, rs6000_function_arg will return a
10869 PARALLEL including a memory element as necessary. */
10871 && (cum
->nargs_prototype
<= 0
10872 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10873 && TARGET_XL_COMPAT
10874 && align_words
>= GP_ARG_NUM_REG
)))
10877 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10878 passed_in_gprs
= false;
10879 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10881 /* Compute number of bytes / words passed in FPRs. If there
10882 is still space available in the register parameter area
10883 *after* that amount, a part of the argument will be passed
10884 in GPRs. In that case, the total amount passed in any
10885 registers is equal to the amount that would have been passed
10886 in GPRs if everything were passed there, so we fall back to
10887 the GPR code below to compute the appropriate value. */
10888 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10889 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10890 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
10892 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
10893 passed_in_gprs
= true;
10900 && align_words
< GP_ARG_NUM_REG
10901 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10902 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10904 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10905 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10910 /* A C expression that indicates when an argument must be passed by
10911 reference. If nonzero for an argument, a copy of that argument is
10912 made in memory and a pointer to the argument is passed instead of
10913 the argument itself. The pointer is passed in whatever way is
10914 appropriate for passing a pointer to that type.
10916 Under V.4, aggregates and long double are passed by reference.
10918 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10919 reference unless the AltiVec vector extension ABI is in force.
10921 As an extension to all ABIs, variable sized types are passed by
10925 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10926 machine_mode mode
, const_tree type
,
10927 bool named ATTRIBUTE_UNUSED
)
10932 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
10933 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
10935 if (TARGET_DEBUG_ARG
)
10936 fprintf (stderr
, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
10940 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10942 if (TARGET_DEBUG_ARG
)
10943 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10947 if (int_size_in_bytes (type
) < 0)
10949 if (TARGET_DEBUG_ARG
)
10950 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10954 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10955 modes only exist for GCC vector types if -maltivec. */
10956 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10958 if (TARGET_DEBUG_ARG
)
10959 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10963 /* Pass synthetic vectors in memory. */
10964 if (TREE_CODE (type
) == VECTOR_TYPE
10965 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10967 static bool warned_for_pass_big_vectors
= false;
10968 if (TARGET_DEBUG_ARG
)
10969 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10970 if (!warned_for_pass_big_vectors
)
10972 warning (0, "GCC vector passed by reference: "
10973 "non-standard ABI extension with no compatibility guarantee");
10974 warned_for_pass_big_vectors
= true;
10982 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10983 already processes. Return true if the parameter must be passed
10984 (fully or partially) on the stack. */
10987 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10993 /* Catch errors. */
10994 if (type
== NULL
|| type
== error_mark_node
)
10997 /* Handle types with no storage requirement. */
10998 if (TYPE_MODE (type
) == VOIDmode
)
11001 /* Handle complex types. */
11002 if (TREE_CODE (type
) == COMPLEX_TYPE
)
11003 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
11004 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
11006 /* Handle transparent aggregates. */
11007 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
11008 && TYPE_TRANSPARENT_AGGR (type
))
11009 type
= TREE_TYPE (first_field (type
));
11011 /* See if this arg was passed by invisible reference. */
11012 if (pass_by_reference (get_cumulative_args (args_so_far
),
11013 TYPE_MODE (type
), type
, true))
11014 type
= build_pointer_type (type
);
11016 /* Find mode as it is passed by the ABI. */
11017 unsignedp
= TYPE_UNSIGNED (type
);
11018 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
11020 /* If we must pass in stack, we need a stack. */
11021 if (rs6000_must_pass_in_stack (mode
, type
))
11024 /* If there is no incoming register, we need a stack. */
11025 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
11026 if (entry_parm
== NULL
)
11029 /* Likewise if we need to pass both in registers and on the stack. */
11030 if (GET_CODE (entry_parm
) == PARALLEL
11031 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
11034 /* Also true if we're partially in registers and partially not. */
11035 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
11038 /* Update info on where next arg arrives in registers. */
11039 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
11043 /* Return true if FUN has no prototype, has a variable argument
11044 list, or passes any parameter in memory. */
11047 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
11049 tree fntype
, result
;
11050 CUMULATIVE_ARGS args_so_far_v
;
11051 cumulative_args_t args_so_far
;
11054 /* Must be a libcall, all of which only use reg parms. */
11059 fntype
= TREE_TYPE (fun
);
11061 /* Varargs functions need the parameter save area. */
11062 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
11065 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
11066 args_so_far
= pack_cumulative_args (&args_so_far_v
);
11068 /* When incoming, we will have been passed the function decl.
11069 It is necessary to use the decl to handle K&R style functions,
11070 where TYPE_ARG_TYPES may not be available. */
11073 gcc_assert (DECL_P (fun
));
11074 result
= DECL_RESULT (fun
);
11077 result
= TREE_TYPE (fntype
);
11079 if (result
&& aggregate_value_p (result
, fntype
))
11081 if (!TYPE_P (result
))
11082 result
= TREE_TYPE (result
);
11083 result
= build_pointer_type (result
);
11084 rs6000_parm_needs_stack (args_so_far
, result
);
11091 for (parm
= DECL_ARGUMENTS (fun
);
11092 parm
&& parm
!= void_list_node
;
11093 parm
= TREE_CHAIN (parm
))
11094 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
11099 function_args_iterator args_iter
;
11102 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
11103 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
11110 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
11111 usually a constant depending on the ABI. However, in the ELFv2 ABI
11112 the register parameter area is optional when calling a function that
11113 has a prototype is scope, has no variable argument list, and passes
11114 all parameters in registers. */
11117 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
11119 int reg_parm_stack_space
;
11121 switch (DEFAULT_ABI
)
11124 reg_parm_stack_space
= 0;
11129 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
11133 /* ??? Recomputing this every time is a bit expensive. Is there
11134 a place to cache this information? */
11135 if (rs6000_function_parms_need_stack (fun
, incoming
))
11136 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
11138 reg_parm_stack_space
= 0;
11142 return reg_parm_stack_space
;
11146 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
11149 machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
11154 for (i
= 0; i
< nregs
; i
++)
11156 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
11157 if (reload_completed
)
11159 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
11162 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
11163 i
* GET_MODE_SIZE (reg_mode
));
11166 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
11170 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
11174 /* Perform any needed actions needed for a function that is receiving a
11175 variable number of arguments.
11179 MODE and TYPE are the mode and type of the current parameter.
11181 PRETEND_SIZE is a variable that should be set to the amount of stack
11182 that must be pushed by the prolog to pretend that our caller pushed
11185 Normally, this macro will push all remaining incoming registers on the
11186 stack and set PRETEND_SIZE to the length of the registers pushed. */
11189 setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
11190 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
11193 CUMULATIVE_ARGS next_cum
;
11194 int reg_size
= TARGET_32BIT
? 4 : 8;
11195 rtx save_area
= NULL_RTX
, mem
;
11196 int first_reg_offset
;
11197 alias_set_type set
;
11199 /* Skip the last named argument. */
11200 next_cum
= *get_cumulative_args (cum
);
11201 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
11203 if (DEFAULT_ABI
== ABI_V4
)
11205 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
11209 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
11210 HOST_WIDE_INT offset
= 0;
11212 /* Try to optimize the size of the varargs save area.
11213 The ABI requires that ap.reg_save_area is doubleword
11214 aligned, but we don't need to allocate space for all
11215 the bytes, only those to which we actually will save
11217 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
11218 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
11219 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11220 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
11221 && cfun
->va_list_fpr_size
)
11224 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
11225 * UNITS_PER_FP_WORD
;
11226 if (cfun
->va_list_fpr_size
11227 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
11228 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
11230 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
11231 * UNITS_PER_FP_WORD
;
11235 offset
= -((first_reg_offset
* reg_size
) & ~7);
11236 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
11238 gpr_reg_num
= cfun
->va_list_gpr_size
;
11239 if (reg_size
== 4 && (first_reg_offset
& 1))
11242 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
11245 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
11246 * UNITS_PER_FP_WORD
11247 - (int) (GP_ARG_NUM_REG
* reg_size
);
11249 if (gpr_size
+ fpr_size
)
11252 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
11253 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
11254 reg_save_area
= XEXP (reg_save_area
, 0);
11255 if (GET_CODE (reg_save_area
) == PLUS
)
11257 gcc_assert (XEXP (reg_save_area
, 0)
11258 == virtual_stack_vars_rtx
);
11259 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
11260 offset
+= INTVAL (XEXP (reg_save_area
, 1));
11263 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
11266 cfun
->machine
->varargs_save_offset
= offset
;
11267 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
11272 first_reg_offset
= next_cum
.words
;
11273 save_area
= crtl
->args
.internal_arg_pointer
;
11275 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
11276 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
11279 set
= get_varargs_alias_set ();
11280 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
11281 && cfun
->va_list_gpr_size
)
11283 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
11285 if (va_list_gpr_counter_field
)
11286 /* V4 va_list_gpr_size counts number of registers needed. */
11287 n_gpr
= cfun
->va_list_gpr_size
;
11289 /* char * va_list instead counts number of bytes needed. */
11290 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
11295 mem
= gen_rtx_MEM (BLKmode
,
11296 plus_constant (Pmode
, save_area
,
11297 first_reg_offset
* reg_size
));
11298 MEM_NOTRAP_P (mem
) = 1;
11299 set_mem_alias_set (mem
, set
);
11300 set_mem_align (mem
, BITS_PER_WORD
);
11302 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
11306 /* Save FP registers if needed. */
11307 if (DEFAULT_ABI
== ABI_V4
11308 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11310 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
11311 && cfun
->va_list_fpr_size
)
11313 int fregno
= next_cum
.fregno
, nregs
;
11314 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
11315 rtx lab
= gen_label_rtx ();
11316 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
11317 * UNITS_PER_FP_WORD
);
11320 (gen_rtx_SET (pc_rtx
,
11321 gen_rtx_IF_THEN_ELSE (VOIDmode
,
11322 gen_rtx_NE (VOIDmode
, cr1
,
11324 gen_rtx_LABEL_REF (VOIDmode
, lab
),
11328 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
11329 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
11331 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11333 plus_constant (Pmode
, save_area
, off
));
11334 MEM_NOTRAP_P (mem
) = 1;
11335 set_mem_alias_set (mem
, set
);
11336 set_mem_align (mem
, GET_MODE_ALIGNMENT (
11337 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11338 ? DFmode
: SFmode
));
11339 emit_move_insn (mem
, gen_rtx_REG (
11340 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11341 ? DFmode
: SFmode
, fregno
));
11348 /* Create the va_list data type. */
11351 rs6000_build_builtin_va_list (void)
11353 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
11355 /* For AIX, prefer 'char *' because that's what the system
11356 header files like. */
11357 if (DEFAULT_ABI
!= ABI_V4
)
11358 return build_pointer_type (char_type_node
);
11360 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
11361 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
11362 get_identifier ("__va_list_tag"), record
);
11364 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
11365 unsigned_char_type_node
);
11366 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
11367 unsigned_char_type_node
);
11368 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
11369 every user file. */
11370 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11371 get_identifier ("reserved"), short_unsigned_type_node
);
11372 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11373 get_identifier ("overflow_arg_area"),
11375 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11376 get_identifier ("reg_save_area"),
11379 va_list_gpr_counter_field
= f_gpr
;
11380 va_list_fpr_counter_field
= f_fpr
;
11382 DECL_FIELD_CONTEXT (f_gpr
) = record
;
11383 DECL_FIELD_CONTEXT (f_fpr
) = record
;
11384 DECL_FIELD_CONTEXT (f_res
) = record
;
11385 DECL_FIELD_CONTEXT (f_ovf
) = record
;
11386 DECL_FIELD_CONTEXT (f_sav
) = record
;
11388 TYPE_STUB_DECL (record
) = type_decl
;
11389 TYPE_NAME (record
) = type_decl
;
11390 TYPE_FIELDS (record
) = f_gpr
;
11391 DECL_CHAIN (f_gpr
) = f_fpr
;
11392 DECL_CHAIN (f_fpr
) = f_res
;
11393 DECL_CHAIN (f_res
) = f_ovf
;
11394 DECL_CHAIN (f_ovf
) = f_sav
;
11396 layout_type (record
);
11398 /* The correct type is an array type of one element. */
11399 return build_array_type (record
, build_index_type (size_zero_node
));
11402 /* Implement va_start. */
11405 rs6000_va_start (tree valist
, rtx nextarg
)
11407 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
11408 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
11409 tree gpr
, fpr
, ovf
, sav
, t
;
11411 /* Only SVR4 needs something special. */
11412 if (DEFAULT_ABI
!= ABI_V4
)
11414 std_expand_builtin_va_start (valist
, nextarg
);
11418 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11419 f_fpr
= DECL_CHAIN (f_gpr
);
11420 f_res
= DECL_CHAIN (f_fpr
);
11421 f_ovf
= DECL_CHAIN (f_res
);
11422 f_sav
= DECL_CHAIN (f_ovf
);
11424 valist
= build_simple_mem_ref (valist
);
11425 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11426 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11428 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11430 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11433 /* Count number of gp and fp argument registers used. */
11434 words
= crtl
->args
.info
.words
;
11435 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
11437 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
11440 if (TARGET_DEBUG_ARG
)
11441 fprintf (stderr
, "va_start: words = " HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
11442 HOST_WIDE_INT_PRINT_DEC
", n_fpr = " HOST_WIDE_INT_PRINT_DEC
"\n",
11443 words
, n_gpr
, n_fpr
);
11445 if (cfun
->va_list_gpr_size
)
11447 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
11448 build_int_cst (NULL_TREE
, n_gpr
));
11449 TREE_SIDE_EFFECTS (t
) = 1;
11450 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11453 if (cfun
->va_list_fpr_size
)
11455 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
11456 build_int_cst (NULL_TREE
, n_fpr
));
11457 TREE_SIDE_EFFECTS (t
) = 1;
11458 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11460 #ifdef HAVE_AS_GNU_ATTRIBUTE
11461 if (call_ABI_of_interest (cfun
->decl
))
11462 rs6000_passes_float
= true;
11466 /* Find the overflow area. */
11467 t
= make_tree (TREE_TYPE (ovf
), crtl
->args
.internal_arg_pointer
);
11469 t
= fold_build_pointer_plus_hwi (t
, words
* MIN_UNITS_PER_WORD
);
11470 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
11471 TREE_SIDE_EFFECTS (t
) = 1;
11472 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11474 /* If there were no va_arg invocations, don't set up the register
11476 if (!cfun
->va_list_gpr_size
11477 && !cfun
->va_list_fpr_size
11478 && n_gpr
< GP_ARG_NUM_REG
11479 && n_fpr
< FP_ARG_V4_MAX_REG
)
11482 /* Find the register save area. */
11483 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
11484 if (cfun
->machine
->varargs_save_offset
)
11485 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
11486 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
11487 TREE_SIDE_EFFECTS (t
) = 1;
11488 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11491 /* Implement va_arg. */
11494 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
11495 gimple_seq
*post_p
)
11497 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
11498 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
11499 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
11500 tree lab_false
, lab_over
, addr
;
11502 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
11506 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
11508 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
11509 return build_va_arg_indirect_ref (t
);
11512 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
11513 earlier version of gcc, with the property that it always applied alignment
11514 adjustments to the va-args (even for zero-sized types). The cheapest way
11515 to deal with this is to replicate the effect of the part of
11516 std_gimplify_va_arg_expr that carries out the align adjust, for the case
11518 We don't need to check for pass-by-reference because of the test above.
11519 We can return a simplifed answer, since we know there's no offset to add. */
11522 && rs6000_darwin64_abi
)
11523 || DEFAULT_ABI
== ABI_ELFv2
11524 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
11525 && integer_zerop (TYPE_SIZE (type
)))
11527 unsigned HOST_WIDE_INT align
, boundary
;
11528 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
11529 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
11530 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
11531 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
11532 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
11533 boundary
/= BITS_PER_UNIT
;
11534 if (boundary
> align
)
11537 /* This updates arg ptr by the amount that would be necessary
11538 to align the zero-sized (but not zero-alignment) item. */
11539 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
11540 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
11541 gimplify_and_add (t
, pre_p
);
11543 t
= fold_convert (sizetype
, valist_tmp
);
11544 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
11545 fold_convert (TREE_TYPE (valist
),
11546 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
11547 size_int (-boundary
))));
11548 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
11549 gimplify_and_add (t
, pre_p
);
11551 /* Since it is zero-sized there's no increment for the item itself. */
11552 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
11553 return build_va_arg_indirect_ref (valist_tmp
);
11556 if (DEFAULT_ABI
!= ABI_V4
)
11558 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
11560 tree elem_type
= TREE_TYPE (type
);
11561 machine_mode elem_mode
= TYPE_MODE (elem_type
);
11562 int elem_size
= GET_MODE_SIZE (elem_mode
);
11564 if (elem_size
< UNITS_PER_WORD
)
11566 tree real_part
, imag_part
;
11567 gimple_seq post
= NULL
;
11569 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11571 /* Copy the value into a temporary, lest the formal temporary
11572 be reused out from under us. */
11573 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
11574 gimple_seq_add_seq (pre_p
, post
);
11576 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11579 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
11583 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
11586 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11587 f_fpr
= DECL_CHAIN (f_gpr
);
11588 f_res
= DECL_CHAIN (f_fpr
);
11589 f_ovf
= DECL_CHAIN (f_res
);
11590 f_sav
= DECL_CHAIN (f_ovf
);
11592 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11593 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11595 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11597 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11600 size
= int_size_in_bytes (type
);
11601 rsize
= (size
+ 3) / 4;
11604 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11605 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
11606 || (TARGET_DOUBLE_FLOAT
11607 && (TYPE_MODE (type
) == DFmode
11608 || FLOAT128_2REG_P (TYPE_MODE (type
))
11609 || DECIMAL_FLOAT_MODE_P (TYPE_MODE (type
))))))
11611 /* FP args go in FP registers, if present. */
11613 n_reg
= (size
+ 7) / 8;
11614 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
11615 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
11616 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
11621 /* Otherwise into GP registers. */
11630 /* Pull the value out of the saved registers.... */
11633 addr
= create_tmp_var (ptr_type_node
, "addr");
11635 /* AltiVec vectors never go in registers when -mabi=altivec. */
11636 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
11640 lab_false
= create_artificial_label (input_location
);
11641 lab_over
= create_artificial_label (input_location
);
11643 /* Long long and SPE vectors are aligned in the registers.
11644 As are any other 2 gpr item such as complex int due to a
11645 historical mistake. */
11647 if (n_reg
== 2 && reg
== gpr
)
11650 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11651 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
11652 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
11653 unshare_expr (reg
), u
);
11655 /* _Decimal128 is passed in even/odd fpr pairs; the stored
11656 reg number is 0 for f1, so we want to make it odd. */
11657 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
11659 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11660 build_int_cst (TREE_TYPE (reg
), 1));
11661 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
11664 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
11665 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
11666 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
11667 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
11668 gimplify_and_add (t
, pre_p
);
11672 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
11674 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11675 build_int_cst (TREE_TYPE (reg
), n_reg
));
11676 u
= fold_convert (sizetype
, u
);
11677 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
11678 t
= fold_build_pointer_plus (t
, u
);
11680 /* _Decimal32 varargs are located in the second word of the 64-bit
11681 FP register for 32-bit binaries. */
11683 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11684 && TYPE_MODE (type
) == SDmode
)
11685 t
= fold_build_pointer_plus_hwi (t
, size
);
11687 gimplify_assign (addr
, t
, pre_p
);
11689 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
11691 stmt
= gimple_build_label (lab_false
);
11692 gimple_seq_add_stmt (pre_p
, stmt
);
11694 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
11696 /* Ensure that we don't find any more args in regs.
11697 Alignment has taken care of for special cases. */
11698 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
11702 /* ... otherwise out of the overflow area. */
11704 /* Care for on-stack alignment if needed. */
11708 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
11709 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
11710 build_int_cst (TREE_TYPE (t
), -align
));
11712 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
11714 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
11716 t
= fold_build_pointer_plus_hwi (t
, size
);
11717 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
11721 stmt
= gimple_build_label (lab_over
);
11722 gimple_seq_add_stmt (pre_p
, stmt
);
11725 if (STRICT_ALIGNMENT
11726 && (TYPE_ALIGN (type
)
11727 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
11729 /* The value (of type complex double, for example) may not be
11730 aligned in memory in the saved registers, so copy via a
11731 temporary. (This is the same code as used for SPARC.) */
11732 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
11733 tree dest_addr
= build_fold_addr_expr (tmp
);
11735 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
11736 3, dest_addr
, addr
, size_int (rsize
* 4));
11738 gimplify_and_add (copy
, pre_p
);
11742 addr
= fold_convert (ptrtype
, addr
);
11743 return build_va_arg_indirect_ref (addr
);
11749 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11752 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11753 const char *attr_string
= "";
11755 gcc_assert (name
!= NULL
);
11756 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11758 if (rs6000_builtin_decls
[(int)code
])
11759 fatal_error (input_location
,
11760 "internal error: builtin function %s already processed", name
);
11762 rs6000_builtin_decls
[(int)code
] = t
=
11763 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11765 /* Set any special attributes. */
11766 if ((classify
& RS6000_BTC_CONST
) != 0)
11768 /* const function, function only depends on the inputs. */
11769 TREE_READONLY (t
) = 1;
11770 TREE_NOTHROW (t
) = 1;
11771 attr_string
= ", pure";
11773 else if ((classify
& RS6000_BTC_PURE
) != 0)
11775 /* pure function, function can read global memory, but does not set any
11777 DECL_PURE_P (t
) = 1;
11778 TREE_NOTHROW (t
) = 1;
11779 attr_string
= ", const";
11781 else if ((classify
& RS6000_BTC_FP
) != 0)
11783 /* Function is a math function. If rounding mode is on, then treat the
11784 function as not reading global memory, but it can have arbitrary side
11785 effects. If it is off, then assume the function is a const function.
11786 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11787 builtin-attribute.def that is used for the math functions. */
11788 TREE_NOTHROW (t
) = 1;
11789 if (flag_rounding_math
)
11791 DECL_PURE_P (t
) = 1;
11792 DECL_IS_NOVOPS (t
) = 1;
11793 attr_string
= ", fp, pure";
11797 TREE_READONLY (t
) = 1;
11798 attr_string
= ", fp, const";
11801 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11802 gcc_unreachable ();
11804 if (TARGET_DEBUG_BUILTIN
)
11805 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11806 (int)code
, name
, attr_string
);
11809 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11811 #undef RS6000_BUILTIN_1
11812 #undef RS6000_BUILTIN_2
11813 #undef RS6000_BUILTIN_3
11814 #undef RS6000_BUILTIN_A
11815 #undef RS6000_BUILTIN_D
11816 #undef RS6000_BUILTIN_E
11817 #undef RS6000_BUILTIN_H
11818 #undef RS6000_BUILTIN_P
11819 #undef RS6000_BUILTIN_Q
11820 #undef RS6000_BUILTIN_S
11821 #undef RS6000_BUILTIN_X
11823 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11824 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11825 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11826 { MASK, ICODE, NAME, ENUM },
11828 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11829 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11830 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11831 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11832 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11833 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11834 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11835 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11837 static const struct builtin_description bdesc_3arg
[] =
11839 #include "rs6000-builtin.def"
11842 /* DST operations: void foo (void *, const int, const char). */
11844 #undef RS6000_BUILTIN_1
11845 #undef RS6000_BUILTIN_2
11846 #undef RS6000_BUILTIN_3
11847 #undef RS6000_BUILTIN_A
11848 #undef RS6000_BUILTIN_D
11849 #undef RS6000_BUILTIN_E
11850 #undef RS6000_BUILTIN_H
11851 #undef RS6000_BUILTIN_P
11852 #undef RS6000_BUILTIN_Q
11853 #undef RS6000_BUILTIN_S
11854 #undef RS6000_BUILTIN_X
11856 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11857 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11858 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11859 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11860 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11861 { MASK, ICODE, NAME, ENUM },
11863 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11864 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11865 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11866 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11867 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11868 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11870 static const struct builtin_description bdesc_dst
[] =
11872 #include "rs6000-builtin.def"
11875 /* Simple binary operations: VECc = foo (VECa, VECb). */
11877 #undef RS6000_BUILTIN_1
11878 #undef RS6000_BUILTIN_2
11879 #undef RS6000_BUILTIN_3
11880 #undef RS6000_BUILTIN_A
11881 #undef RS6000_BUILTIN_D
11882 #undef RS6000_BUILTIN_E
11883 #undef RS6000_BUILTIN_H
11884 #undef RS6000_BUILTIN_P
11885 #undef RS6000_BUILTIN_Q
11886 #undef RS6000_BUILTIN_S
11887 #undef RS6000_BUILTIN_X
11889 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11890 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11891 { MASK, ICODE, NAME, ENUM },
11893 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11894 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11895 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11896 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11897 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11898 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11899 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11900 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11901 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11903 static const struct builtin_description bdesc_2arg
[] =
11905 #include "rs6000-builtin.def"
11908 #undef RS6000_BUILTIN_1
11909 #undef RS6000_BUILTIN_2
11910 #undef RS6000_BUILTIN_3
11911 #undef RS6000_BUILTIN_A
11912 #undef RS6000_BUILTIN_D
11913 #undef RS6000_BUILTIN_E
11914 #undef RS6000_BUILTIN_H
11915 #undef RS6000_BUILTIN_P
11916 #undef RS6000_BUILTIN_Q
11917 #undef RS6000_BUILTIN_S
11918 #undef RS6000_BUILTIN_X
11920 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11921 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11922 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11923 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11924 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11925 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11926 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11927 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11928 { MASK, ICODE, NAME, ENUM },
11930 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11931 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11932 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11934 /* AltiVec predicates. */
11936 static const struct builtin_description bdesc_altivec_preds
[] =
11938 #include "rs6000-builtin.def"
11941 /* SPE predicates. */
11942 #undef RS6000_BUILTIN_1
11943 #undef RS6000_BUILTIN_2
11944 #undef RS6000_BUILTIN_3
11945 #undef RS6000_BUILTIN_A
11946 #undef RS6000_BUILTIN_D
11947 #undef RS6000_BUILTIN_E
11948 #undef RS6000_BUILTIN_H
11949 #undef RS6000_BUILTIN_P
11950 #undef RS6000_BUILTIN_Q
11951 #undef RS6000_BUILTIN_S
11952 #undef RS6000_BUILTIN_X
11954 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11955 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11956 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11957 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11958 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11959 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11960 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11961 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11962 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11963 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11964 { MASK, ICODE, NAME, ENUM },
11966 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11968 static const struct builtin_description bdesc_spe_predicates
[] =
11970 #include "rs6000-builtin.def"
11973 /* SPE evsel predicates. */
11974 #undef RS6000_BUILTIN_1
11975 #undef RS6000_BUILTIN_2
11976 #undef RS6000_BUILTIN_3
11977 #undef RS6000_BUILTIN_A
11978 #undef RS6000_BUILTIN_D
11979 #undef RS6000_BUILTIN_E
11980 #undef RS6000_BUILTIN_H
11981 #undef RS6000_BUILTIN_P
11982 #undef RS6000_BUILTIN_Q
11983 #undef RS6000_BUILTIN_S
11984 #undef RS6000_BUILTIN_X
11986 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11987 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11988 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11989 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11990 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11991 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11992 { MASK, ICODE, NAME, ENUM },
11994 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11995 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11996 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11997 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11998 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12000 static const struct builtin_description bdesc_spe_evsel
[] =
12002 #include "rs6000-builtin.def"
12005 /* PAIRED predicates. */
12006 #undef RS6000_BUILTIN_1
12007 #undef RS6000_BUILTIN_2
12008 #undef RS6000_BUILTIN_3
12009 #undef RS6000_BUILTIN_A
12010 #undef RS6000_BUILTIN_D
12011 #undef RS6000_BUILTIN_E
12012 #undef RS6000_BUILTIN_H
12013 #undef RS6000_BUILTIN_P
12014 #undef RS6000_BUILTIN_Q
12015 #undef RS6000_BUILTIN_S
12016 #undef RS6000_BUILTIN_X
12018 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12019 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12020 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12021 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12022 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12023 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12024 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12025 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12026 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
12027 { MASK, ICODE, NAME, ENUM },
12029 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12030 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12032 static const struct builtin_description bdesc_paired_preds
[] =
12034 #include "rs6000-builtin.def"
12037 /* ABS* operations. */
12039 #undef RS6000_BUILTIN_1
12040 #undef RS6000_BUILTIN_2
12041 #undef RS6000_BUILTIN_3
12042 #undef RS6000_BUILTIN_A
12043 #undef RS6000_BUILTIN_D
12044 #undef RS6000_BUILTIN_E
12045 #undef RS6000_BUILTIN_H
12046 #undef RS6000_BUILTIN_P
12047 #undef RS6000_BUILTIN_Q
12048 #undef RS6000_BUILTIN_S
12049 #undef RS6000_BUILTIN_X
12051 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12052 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12053 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12054 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
12055 { MASK, ICODE, NAME, ENUM },
12057 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12058 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12059 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12060 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12061 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12062 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12063 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12065 static const struct builtin_description bdesc_abs
[] =
12067 #include "rs6000-builtin.def"
12070 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
12073 #undef RS6000_BUILTIN_1
12074 #undef RS6000_BUILTIN_2
12075 #undef RS6000_BUILTIN_3
12076 #undef RS6000_BUILTIN_A
12077 #undef RS6000_BUILTIN_D
12078 #undef RS6000_BUILTIN_E
12079 #undef RS6000_BUILTIN_H
12080 #undef RS6000_BUILTIN_P
12081 #undef RS6000_BUILTIN_Q
12082 #undef RS6000_BUILTIN_S
12083 #undef RS6000_BUILTIN_X
12085 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
12086 { MASK, ICODE, NAME, ENUM },
12088 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12089 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12090 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12091 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12092 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12093 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12094 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12095 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12096 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12097 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12099 static const struct builtin_description bdesc_1arg
[] =
12101 #include "rs6000-builtin.def"
12104 /* HTM builtins. */
12105 #undef RS6000_BUILTIN_1
12106 #undef RS6000_BUILTIN_2
12107 #undef RS6000_BUILTIN_3
12108 #undef RS6000_BUILTIN_A
12109 #undef RS6000_BUILTIN_D
12110 #undef RS6000_BUILTIN_E
12111 #undef RS6000_BUILTIN_H
12112 #undef RS6000_BUILTIN_P
12113 #undef RS6000_BUILTIN_Q
12114 #undef RS6000_BUILTIN_S
12115 #undef RS6000_BUILTIN_X
12117 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12118 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12119 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12120 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12121 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12122 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12123 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
12124 { MASK, ICODE, NAME, ENUM },
12126 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12127 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12128 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12129 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12131 static const struct builtin_description bdesc_htm
[] =
12133 #include "rs6000-builtin.def"
12136 #undef RS6000_BUILTIN_1
12137 #undef RS6000_BUILTIN_2
12138 #undef RS6000_BUILTIN_3
12139 #undef RS6000_BUILTIN_A
12140 #undef RS6000_BUILTIN_D
12141 #undef RS6000_BUILTIN_E
12142 #undef RS6000_BUILTIN_H
12143 #undef RS6000_BUILTIN_P
12144 #undef RS6000_BUILTIN_Q
12145 #undef RS6000_BUILTIN_S
12147 /* Return true if a builtin function is overloaded. */
12149 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
12151 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
12154 /* Expand an expression EXP that calls a builtin without arguments. */
12156 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
12159 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12161 if (icode
== CODE_FOR_nothing
)
12162 /* Builtin not supported on this processor. */
12166 || GET_MODE (target
) != tmode
12167 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12168 target
= gen_reg_rtx (tmode
);
12170 pat
= GEN_FCN (icode
) (target
);
12180 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
12183 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12184 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12185 rtx op0
= expand_normal (arg0
);
12186 rtx op1
= expand_normal (arg1
);
12187 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12188 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12190 if (icode
== CODE_FOR_nothing
)
12191 /* Builtin not supported on this processor. */
12194 /* If we got invalid arguments bail out before generating bad rtl. */
12195 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12198 if (GET_CODE (op0
) != CONST_INT
12199 || INTVAL (op0
) > 255
12200 || INTVAL (op0
) < 0)
12202 error ("argument 1 must be an 8-bit field value");
12206 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12207 op0
= copy_to_mode_reg (mode0
, op0
);
12209 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12210 op1
= copy_to_mode_reg (mode1
, op1
);
12212 pat
= GEN_FCN (icode
) (op0
, op1
);
12222 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12225 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12226 rtx op0
= expand_normal (arg0
);
12227 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12228 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12230 if (icode
== CODE_FOR_nothing
)
12231 /* Builtin not supported on this processor. */
12234 /* If we got invalid arguments bail out before generating bad rtl. */
12235 if (arg0
== error_mark_node
)
12238 if (icode
== CODE_FOR_altivec_vspltisb
12239 || icode
== CODE_FOR_altivec_vspltish
12240 || icode
== CODE_FOR_altivec_vspltisw
12241 || icode
== CODE_FOR_spe_evsplatfi
12242 || icode
== CODE_FOR_spe_evsplati
)
12244 /* Only allow 5-bit *signed* literals. */
12245 if (GET_CODE (op0
) != CONST_INT
12246 || INTVAL (op0
) > 15
12247 || INTVAL (op0
) < -16)
12249 error ("argument 1 must be a 5-bit signed literal");
12255 || GET_MODE (target
) != tmode
12256 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12257 target
= gen_reg_rtx (tmode
);
12259 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12260 op0
= copy_to_mode_reg (mode0
, op0
);
12262 pat
= GEN_FCN (icode
) (target
, op0
);
12271 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
12273 rtx pat
, scratch1
, scratch2
;
12274 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12275 rtx op0
= expand_normal (arg0
);
12276 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12277 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12279 /* If we have invalid arguments, bail out before generating bad rtl. */
12280 if (arg0
== error_mark_node
)
12284 || GET_MODE (target
) != tmode
12285 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12286 target
= gen_reg_rtx (tmode
);
12288 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12289 op0
= copy_to_mode_reg (mode0
, op0
);
12291 scratch1
= gen_reg_rtx (mode0
);
12292 scratch2
= gen_reg_rtx (mode0
);
12294 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
12303 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12306 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12307 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12308 rtx op0
= expand_normal (arg0
);
12309 rtx op1
= expand_normal (arg1
);
12310 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12311 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12312 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12314 if (icode
== CODE_FOR_nothing
)
12315 /* Builtin not supported on this processor. */
12318 /* If we got invalid arguments bail out before generating bad rtl. */
12319 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12322 if (icode
== CODE_FOR_altivec_vcfux
12323 || icode
== CODE_FOR_altivec_vcfsx
12324 || icode
== CODE_FOR_altivec_vctsxs
12325 || icode
== CODE_FOR_altivec_vctuxs
12326 || icode
== CODE_FOR_altivec_vspltb
12327 || icode
== CODE_FOR_altivec_vsplth
12328 || icode
== CODE_FOR_altivec_vspltw
12329 || icode
== CODE_FOR_spe_evaddiw
12330 || icode
== CODE_FOR_spe_evldd
12331 || icode
== CODE_FOR_spe_evldh
12332 || icode
== CODE_FOR_spe_evldw
12333 || icode
== CODE_FOR_spe_evlhhesplat
12334 || icode
== CODE_FOR_spe_evlhhossplat
12335 || icode
== CODE_FOR_spe_evlhhousplat
12336 || icode
== CODE_FOR_spe_evlwhe
12337 || icode
== CODE_FOR_spe_evlwhos
12338 || icode
== CODE_FOR_spe_evlwhou
12339 || icode
== CODE_FOR_spe_evlwhsplat
12340 || icode
== CODE_FOR_spe_evlwwsplat
12341 || icode
== CODE_FOR_spe_evrlwi
12342 || icode
== CODE_FOR_spe_evslwi
12343 || icode
== CODE_FOR_spe_evsrwis
12344 || icode
== CODE_FOR_spe_evsubifw
12345 || icode
== CODE_FOR_spe_evsrwiu
)
12347 /* Only allow 5-bit unsigned literals. */
12349 if (TREE_CODE (arg1
) != INTEGER_CST
12350 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
12352 error ("argument 2 must be a 5-bit unsigned literal");
12358 || GET_MODE (target
) != tmode
12359 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12360 target
= gen_reg_rtx (tmode
);
12362 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12363 op0
= copy_to_mode_reg (mode0
, op0
);
12364 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12365 op1
= copy_to_mode_reg (mode1
, op1
);
12367 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12376 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12379 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
12380 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12381 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12382 rtx op0
= expand_normal (arg0
);
12383 rtx op1
= expand_normal (arg1
);
12384 machine_mode tmode
= SImode
;
12385 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12386 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12389 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
12391 error ("argument 1 of __builtin_altivec_predicate must be a constant");
12395 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
12397 gcc_assert (mode0
== mode1
);
12399 /* If we have invalid arguments, bail out before generating bad rtl. */
12400 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12404 || GET_MODE (target
) != tmode
12405 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12406 target
= gen_reg_rtx (tmode
);
12408 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12409 op0
= copy_to_mode_reg (mode0
, op0
);
12410 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12411 op1
= copy_to_mode_reg (mode1
, op1
);
12413 scratch
= gen_reg_rtx (mode0
);
12415 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12420 /* The vec_any* and vec_all* predicates use the same opcodes for two
12421 different operations, but the bits in CR6 will be different
12422 depending on what information we want. So we have to play tricks
12423 with CR6 to get the right bits out.
12425 If you think this is disgusting, look at the specs for the
12426 AltiVec predicates. */
12428 switch (cr6_form_int
)
12431 emit_insn (gen_cr6_test_for_zero (target
));
12434 emit_insn (gen_cr6_test_for_zero_reverse (target
));
12437 emit_insn (gen_cr6_test_for_lt (target
));
12440 emit_insn (gen_cr6_test_for_lt_reverse (target
));
12443 error ("argument 1 of __builtin_altivec_predicate is out of range");
12451 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
12454 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12455 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12456 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12457 machine_mode mode0
= Pmode
;
12458 machine_mode mode1
= Pmode
;
12459 rtx op0
= expand_normal (arg0
);
12460 rtx op1
= expand_normal (arg1
);
12462 if (icode
== CODE_FOR_nothing
)
12463 /* Builtin not supported on this processor. */
12466 /* If we got invalid arguments bail out before generating bad rtl. */
12467 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12471 || GET_MODE (target
) != tmode
12472 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12473 target
= gen_reg_rtx (tmode
);
12475 op1
= copy_to_mode_reg (mode1
, op1
);
12477 if (op0
== const0_rtx
)
12479 addr
= gen_rtx_MEM (tmode
, op1
);
12483 op0
= copy_to_mode_reg (mode0
, op0
);
12484 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12487 pat
= GEN_FCN (icode
) (target
, addr
);
12496 /* Return a constant vector for use as a little-endian permute control vector
12497 to reverse the order of elements of the given vector mode. */
12499 swap_selector_for_mode (machine_mode mode
)
12501 /* These are little endian vectors, so their elements are reversed
12502 from what you would normally expect for a permute control vector. */
12503 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
12504 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
12505 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
12506 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
12507 unsigned int *swaparray
, i
;
12524 swaparray
= swap16
;
12527 gcc_unreachable ();
12530 for (i
= 0; i
< 16; ++i
)
12531 perm
[i
] = GEN_INT (swaparray
[i
]);
12533 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
12536 /* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
12537 with -maltivec=be specified. Issue the load followed by an element-reversing
12540 altivec_expand_lvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12542 rtx tmp
= gen_reg_rtx (mode
);
12543 rtx load
= gen_rtx_SET (tmp
, op1
);
12544 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12545 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
12546 rtx sel
= swap_selector_for_mode (mode
);
12547 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
12549 gcc_assert (REG_P (op0
));
12551 emit_insn (gen_rtx_SET (op0
, vperm
));
12554 /* Generate code for a "stvx" or "stvxl" built-in for a little endian target
12555 with -maltivec=be specified. Issue the store preceded by an element-reversing
12558 altivec_expand_stvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12560 rtx tmp
= gen_reg_rtx (mode
);
12561 rtx store
= gen_rtx_SET (op0
, tmp
);
12562 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12563 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
12564 rtx sel
= swap_selector_for_mode (mode
);
12567 gcc_assert (REG_P (op1
));
12568 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12569 emit_insn (gen_rtx_SET (tmp
, vperm
));
12573 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
12574 specified. Issue the store preceded by an element-reversing permute. */
12576 altivec_expand_stvex_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12578 machine_mode inner_mode
= GET_MODE_INNER (mode
);
12579 rtx tmp
= gen_reg_rtx (mode
);
12580 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
12581 rtx sel
= swap_selector_for_mode (mode
);
12584 gcc_assert (REG_P (op1
));
12585 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12586 emit_insn (gen_rtx_SET (tmp
, vperm
));
12587 emit_insn (gen_rtx_SET (op0
, stvx
));
12591 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
12594 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12595 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12596 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12597 machine_mode mode0
= Pmode
;
12598 machine_mode mode1
= Pmode
;
12599 rtx op0
= expand_normal (arg0
);
12600 rtx op1
= expand_normal (arg1
);
12602 if (icode
== CODE_FOR_nothing
)
12603 /* Builtin not supported on this processor. */
12606 /* If we got invalid arguments bail out before generating bad rtl. */
12607 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12611 || GET_MODE (target
) != tmode
12612 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12613 target
= gen_reg_rtx (tmode
);
12615 op1
= copy_to_mode_reg (mode1
, op1
);
12617 if (op0
== const0_rtx
)
12619 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
12623 op0
= copy_to_mode_reg (mode0
, op0
);
12624 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12627 pat
= GEN_FCN (icode
) (target
, addr
);
12637 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
12639 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12640 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12641 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12642 rtx op0
= expand_normal (arg0
);
12643 rtx op1
= expand_normal (arg1
);
12644 rtx op2
= expand_normal (arg2
);
12646 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12647 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12648 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
12650 /* Invalid arguments. Bail before doing anything stoopid! */
12651 if (arg0
== error_mark_node
12652 || arg1
== error_mark_node
12653 || arg2
== error_mark_node
)
12656 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
12657 op0
= copy_to_mode_reg (mode2
, op0
);
12658 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
12659 op1
= copy_to_mode_reg (mode0
, op1
);
12660 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
12661 op2
= copy_to_mode_reg (mode1
, op2
);
12663 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
12670 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
12672 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12673 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12674 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12675 rtx op0
= expand_normal (arg0
);
12676 rtx op1
= expand_normal (arg1
);
12677 rtx op2
= expand_normal (arg2
);
12679 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12680 machine_mode mode1
= Pmode
;
12681 machine_mode mode2
= Pmode
;
12683 /* Invalid arguments. Bail before doing anything stoopid! */
12684 if (arg0
== error_mark_node
12685 || arg1
== error_mark_node
12686 || arg2
== error_mark_node
)
12689 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
12690 op0
= copy_to_mode_reg (tmode
, op0
);
12692 op2
= copy_to_mode_reg (mode2
, op2
);
12694 if (op1
== const0_rtx
)
12696 addr
= gen_rtx_MEM (tmode
, op2
);
12700 op1
= copy_to_mode_reg (mode1
, op1
);
12701 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12704 pat
= GEN_FCN (icode
) (addr
, op0
);
12711 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
12713 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12714 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12715 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12716 rtx op0
= expand_normal (arg0
);
12717 rtx op1
= expand_normal (arg1
);
12718 rtx op2
= expand_normal (arg2
);
12720 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12721 machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
12722 machine_mode mode1
= Pmode
;
12723 machine_mode mode2
= Pmode
;
12725 /* Invalid arguments. Bail before doing anything stoopid! */
12726 if (arg0
== error_mark_node
12727 || arg1
== error_mark_node
12728 || arg2
== error_mark_node
)
12731 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
12732 op0
= copy_to_mode_reg (smode
, op0
);
12734 op2
= copy_to_mode_reg (mode2
, op2
);
12736 if (op1
== const0_rtx
)
12738 addr
= gen_rtx_MEM (tmode
, op2
);
12742 op1
= copy_to_mode_reg (mode1
, op1
);
12743 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12746 pat
= GEN_FCN (icode
) (addr
, op0
);
12752 /* Return the appropriate SPR number associated with the given builtin. */
12753 static inline HOST_WIDE_INT
12754 htm_spr_num (enum rs6000_builtins code
)
12756 if (code
== HTM_BUILTIN_GET_TFHAR
12757 || code
== HTM_BUILTIN_SET_TFHAR
)
12759 else if (code
== HTM_BUILTIN_GET_TFIAR
12760 || code
== HTM_BUILTIN_SET_TFIAR
)
12762 else if (code
== HTM_BUILTIN_GET_TEXASR
12763 || code
== HTM_BUILTIN_SET_TEXASR
)
12765 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
12766 || code
== HTM_BUILTIN_SET_TEXASRU
);
12767 return TEXASRU_SPR
;
12770 /* Return the appropriate SPR regno associated with the given builtin. */
12771 static inline HOST_WIDE_INT
12772 htm_spr_regno (enum rs6000_builtins code
)
12774 if (code
== HTM_BUILTIN_GET_TFHAR
12775 || code
== HTM_BUILTIN_SET_TFHAR
)
12776 return TFHAR_REGNO
;
12777 else if (code
== HTM_BUILTIN_GET_TFIAR
12778 || code
== HTM_BUILTIN_SET_TFIAR
)
12779 return TFIAR_REGNO
;
12780 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
12781 || code
== HTM_BUILTIN_SET_TEXASR
12782 || code
== HTM_BUILTIN_GET_TEXASRU
12783 || code
== HTM_BUILTIN_SET_TEXASRU
);
12784 return TEXASR_REGNO
;
12787 /* Return the correct ICODE value depending on whether we are
12788 setting or reading the HTM SPRs. */
12789 static inline enum insn_code
12790 rs6000_htm_spr_icode (bool nonvoid
)
12793 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
12795 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
12798 /* Expand the HTM builtin in EXP and store the result in TARGET.
12799 Store true in *EXPANDEDP if we found a builtin to expand. */
12801 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12803 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12804 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
12805 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12806 const struct builtin_description
*d
;
12811 if (!TARGET_POWERPC64
12812 && (fcode
== HTM_BUILTIN_TABORTDC
12813 || fcode
== HTM_BUILTIN_TABORTDCI
))
12815 size_t uns_fcode
= (size_t)fcode
;
12816 const char *name
= rs6000_builtin_info
[uns_fcode
].name
;
12817 error ("builtin %s is only valid in 64-bit mode", name
);
12821 /* Expand the HTM builtins. */
12823 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
12824 if (d
->code
== fcode
)
12826 rtx op
[MAX_HTM_OPERANDS
], pat
;
12829 call_expr_arg_iterator iter
;
12830 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
12831 enum insn_code icode
= d
->icode
;
12832 const struct insn_operand_data
*insn_op
;
12833 bool uses_spr
= (attr
& RS6000_BTC_SPR
);
12837 icode
= rs6000_htm_spr_icode (nonvoid
);
12838 insn_op
= &insn_data
[icode
].operand
[0];
12842 machine_mode tmode
= (uses_spr
) ? insn_op
->mode
: SImode
;
12844 || GET_MODE (target
) != tmode
12845 || (uses_spr
&& !(*insn_op
->predicate
) (target
, tmode
)))
12846 target
= gen_reg_rtx (tmode
);
12848 op
[nopnds
++] = target
;
12851 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
12853 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
12856 insn_op
= &insn_data
[icode
].operand
[nopnds
];
12858 op
[nopnds
] = expand_normal (arg
);
12860 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
12862 if (!strcmp (insn_op
->constraint
, "n"))
12864 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
12865 if (!CONST_INT_P (op
[nopnds
]))
12866 error ("argument %d must be an unsigned literal", arg_num
);
12868 error ("argument %d is an unsigned literal that is "
12869 "out of range", arg_num
);
12872 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
12878 /* Handle the builtins for extended mnemonics. These accept
12879 no arguments, but map to builtins that take arguments. */
12882 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
12883 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
12884 op
[nopnds
++] = GEN_INT (1);
12885 #ifdef ENABLE_CHECKING
12886 attr
|= RS6000_BTC_UNARY
;
12889 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12890 op
[nopnds
++] = GEN_INT (0);
12891 #ifdef ENABLE_CHECKING
12892 attr
|= RS6000_BTC_UNARY
;
12899 /* If this builtin accesses SPRs, then pass in the appropriate
12900 SPR number and SPR regno as the last two operands. */
12903 machine_mode mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
12904 op
[nopnds
++] = gen_rtx_CONST_INT (mode
, htm_spr_num (fcode
));
12905 op
[nopnds
++] = gen_rtx_REG (mode
, htm_spr_regno (fcode
));
12907 /* If this builtin accesses a CR, then pass in a scratch
12908 CR as the last operand. */
12909 else if (attr
& RS6000_BTC_CR
)
12910 { cr
= gen_reg_rtx (CCmode
);
12914 #ifdef ENABLE_CHECKING
12915 int expected_nopnds
= 0;
12916 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12917 expected_nopnds
= 1;
12918 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12919 expected_nopnds
= 2;
12920 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12921 expected_nopnds
= 3;
12922 if (!(attr
& RS6000_BTC_VOID
))
12923 expected_nopnds
+= 1;
12925 expected_nopnds
+= 2;
12927 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12933 pat
= GEN_FCN (icode
) (op
[0]);
12936 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12939 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12942 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12945 gcc_unreachable ();
12951 if (attr
& RS6000_BTC_CR
)
12953 if (fcode
== HTM_BUILTIN_TBEGIN
)
12955 /* Emit code to set TARGET to true or false depending on
12956 whether the tbegin. instruction successfully or failed
12957 to start a transaction. We do this by placing the 1's
12958 complement of CR's EQ bit into TARGET. */
12959 rtx scratch
= gen_reg_rtx (SImode
);
12960 emit_insn (gen_rtx_SET (scratch
,
12961 gen_rtx_EQ (SImode
, cr
,
12963 emit_insn (gen_rtx_SET (target
,
12964 gen_rtx_XOR (SImode
, scratch
,
12969 /* Emit code to copy the 4-bit condition register field
12970 CR into the least significant end of register TARGET. */
12971 rtx scratch1
= gen_reg_rtx (SImode
);
12972 rtx scratch2
= gen_reg_rtx (SImode
);
12973 rtx subreg
= simplify_gen_subreg (CCmode
, scratch1
, SImode
, 0);
12974 emit_insn (gen_movcc (subreg
, cr
));
12975 emit_insn (gen_lshrsi3 (scratch2
, scratch1
, GEN_INT (28)));
12976 emit_insn (gen_andsi3 (target
, scratch2
, GEN_INT (0xf)));
12985 *expandedp
= false;
12990 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12993 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12994 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12995 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12996 rtx op0
= expand_normal (arg0
);
12997 rtx op1
= expand_normal (arg1
);
12998 rtx op2
= expand_normal (arg2
);
12999 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13000 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13001 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13002 machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
13004 if (icode
== CODE_FOR_nothing
)
13005 /* Builtin not supported on this processor. */
13008 /* If we got invalid arguments bail out before generating bad rtl. */
13009 if (arg0
== error_mark_node
13010 || arg1
== error_mark_node
13011 || arg2
== error_mark_node
)
13014 /* Check and prepare argument depending on the instruction code.
13016 Note that a switch statement instead of the sequence of tests
13017 would be incorrect as many of the CODE_FOR values could be
13018 CODE_FOR_nothing and that would yield multiple alternatives
13019 with identical values. We'd never reach here at runtime in
13021 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
13022 || icode
== CODE_FOR_altivec_vsldoi_v4si
13023 || icode
== CODE_FOR_altivec_vsldoi_v8hi
13024 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
13026 /* Only allow 4-bit unsigned literals. */
13028 if (TREE_CODE (arg2
) != INTEGER_CST
13029 || TREE_INT_CST_LOW (arg2
) & ~0xf)
13031 error ("argument 3 must be a 4-bit unsigned literal");
13035 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
13036 || icode
== CODE_FOR_vsx_xxpermdi_v2di
13037 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
13038 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
13039 || icode
== CODE_FOR_vsx_xxsldwi_v4si
13040 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
13041 || icode
== CODE_FOR_vsx_xxsldwi_v2di
13042 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
13044 /* Only allow 2-bit unsigned literals. */
13046 if (TREE_CODE (arg2
) != INTEGER_CST
13047 || TREE_INT_CST_LOW (arg2
) & ~0x3)
13049 error ("argument 3 must be a 2-bit unsigned literal");
13053 else if (icode
== CODE_FOR_vsx_set_v2df
13054 || icode
== CODE_FOR_vsx_set_v2di
13055 || icode
== CODE_FOR_bcdadd
13056 || icode
== CODE_FOR_bcdadd_lt
13057 || icode
== CODE_FOR_bcdadd_eq
13058 || icode
== CODE_FOR_bcdadd_gt
13059 || icode
== CODE_FOR_bcdsub
13060 || icode
== CODE_FOR_bcdsub_lt
13061 || icode
== CODE_FOR_bcdsub_eq
13062 || icode
== CODE_FOR_bcdsub_gt
)
13064 /* Only allow 1-bit unsigned literals. */
13066 if (TREE_CODE (arg2
) != INTEGER_CST
13067 || TREE_INT_CST_LOW (arg2
) & ~0x1)
13069 error ("argument 3 must be a 1-bit unsigned literal");
13073 else if (icode
== CODE_FOR_dfp_ddedpd_dd
13074 || icode
== CODE_FOR_dfp_ddedpd_td
)
13076 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
13078 if (TREE_CODE (arg0
) != INTEGER_CST
13079 || TREE_INT_CST_LOW (arg2
) & ~0x3)
13081 error ("argument 1 must be 0 or 2");
13085 else if (icode
== CODE_FOR_dfp_denbcd_dd
13086 || icode
== CODE_FOR_dfp_denbcd_td
)
13088 /* Only allow 1-bit unsigned literals. */
13090 if (TREE_CODE (arg0
) != INTEGER_CST
13091 || TREE_INT_CST_LOW (arg0
) & ~0x1)
13093 error ("argument 1 must be a 1-bit unsigned literal");
13097 else if (icode
== CODE_FOR_dfp_dscli_dd
13098 || icode
== CODE_FOR_dfp_dscli_td
13099 || icode
== CODE_FOR_dfp_dscri_dd
13100 || icode
== CODE_FOR_dfp_dscri_td
)
13102 /* Only allow 6-bit unsigned literals. */
13104 if (TREE_CODE (arg1
) != INTEGER_CST
13105 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
13107 error ("argument 2 must be a 6-bit unsigned literal");
13111 else if (icode
== CODE_FOR_crypto_vshasigmaw
13112 || icode
== CODE_FOR_crypto_vshasigmad
)
13114 /* Check whether the 2nd and 3rd arguments are integer constants and in
13115 range and prepare arguments. */
13117 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (arg1
, 2))
13119 error ("argument 2 must be 0 or 1");
13124 if (TREE_CODE (arg2
) != INTEGER_CST
|| wi::geu_p (arg1
, 16))
13126 error ("argument 3 must be in the range 0..15");
13132 || GET_MODE (target
) != tmode
13133 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13134 target
= gen_reg_rtx (tmode
);
13136 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13137 op0
= copy_to_mode_reg (mode0
, op0
);
13138 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13139 op1
= copy_to_mode_reg (mode1
, op1
);
13140 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13141 op2
= copy_to_mode_reg (mode2
, op2
);
13143 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
13144 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
13146 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13154 /* Expand the lvx builtins. */
13156 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
13158 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13159 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13161 machine_mode tmode
, mode0
;
13163 enum insn_code icode
;
13167 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
13168 icode
= CODE_FOR_vector_altivec_load_v16qi
;
13170 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
13171 icode
= CODE_FOR_vector_altivec_load_v8hi
;
13173 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
13174 icode
= CODE_FOR_vector_altivec_load_v4si
;
13176 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
13177 icode
= CODE_FOR_vector_altivec_load_v4sf
;
13179 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
13180 icode
= CODE_FOR_vector_altivec_load_v2df
;
13182 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
13183 icode
= CODE_FOR_vector_altivec_load_v2di
;
13184 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
13185 icode
= CODE_FOR_vector_altivec_load_v1ti
;
13188 *expandedp
= false;
13194 arg0
= CALL_EXPR_ARG (exp
, 0);
13195 op0
= expand_normal (arg0
);
13196 tmode
= insn_data
[icode
].operand
[0].mode
;
13197 mode0
= insn_data
[icode
].operand
[1].mode
;
13200 || GET_MODE (target
) != tmode
13201 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13202 target
= gen_reg_rtx (tmode
);
13204 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13205 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13207 pat
= GEN_FCN (icode
) (target
, op0
);
13214 /* Expand the stvx builtins. */
13216 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
13219 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13220 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13222 machine_mode mode0
, mode1
;
13224 enum insn_code icode
;
13228 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
13229 icode
= CODE_FOR_vector_altivec_store_v16qi
;
13231 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
13232 icode
= CODE_FOR_vector_altivec_store_v8hi
;
13234 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
13235 icode
= CODE_FOR_vector_altivec_store_v4si
;
13237 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
13238 icode
= CODE_FOR_vector_altivec_store_v4sf
;
13240 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
13241 icode
= CODE_FOR_vector_altivec_store_v2df
;
13243 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
13244 icode
= CODE_FOR_vector_altivec_store_v2di
;
13245 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
13246 icode
= CODE_FOR_vector_altivec_store_v1ti
;
13249 *expandedp
= false;
13253 arg0
= CALL_EXPR_ARG (exp
, 0);
13254 arg1
= CALL_EXPR_ARG (exp
, 1);
13255 op0
= expand_normal (arg0
);
13256 op1
= expand_normal (arg1
);
13257 mode0
= insn_data
[icode
].operand
[0].mode
;
13258 mode1
= insn_data
[icode
].operand
[1].mode
;
13260 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13261 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13262 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13263 op1
= copy_to_mode_reg (mode1
, op1
);
13265 pat
= GEN_FCN (icode
) (op0
, op1
);
13273 /* Expand the dst builtins. */
13275 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
13278 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13279 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13280 tree arg0
, arg1
, arg2
;
13281 machine_mode mode0
, mode1
;
13282 rtx pat
, op0
, op1
, op2
;
13283 const struct builtin_description
*d
;
13286 *expandedp
= false;
13288 /* Handle DST variants. */
13290 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
13291 if (d
->code
== fcode
)
13293 arg0
= CALL_EXPR_ARG (exp
, 0);
13294 arg1
= CALL_EXPR_ARG (exp
, 1);
13295 arg2
= CALL_EXPR_ARG (exp
, 2);
13296 op0
= expand_normal (arg0
);
13297 op1
= expand_normal (arg1
);
13298 op2
= expand_normal (arg2
);
13299 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
13300 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
13302 /* Invalid arguments, bail out before generating bad rtl. */
13303 if (arg0
== error_mark_node
13304 || arg1
== error_mark_node
13305 || arg2
== error_mark_node
)
13310 if (TREE_CODE (arg2
) != INTEGER_CST
13311 || TREE_INT_CST_LOW (arg2
) & ~0x3)
13313 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
13317 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
13318 op0
= copy_to_mode_reg (Pmode
, op0
);
13319 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
13320 op1
= copy_to_mode_reg (mode1
, op1
);
13322 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
13332 /* Expand vec_init builtin. */
13334 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
13336 machine_mode tmode
= TYPE_MODE (type
);
13337 machine_mode inner_mode
= GET_MODE_INNER (tmode
);
13338 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
13340 gcc_assert (VECTOR_MODE_P (tmode
));
13341 gcc_assert (n_elt
== call_expr_nargs (exp
));
13343 if (!target
|| !register_operand (target
, tmode
))
13344 target
= gen_reg_rtx (tmode
);
13346 /* If we have a vector compromised of a single element, such as V1TImode, do
13347 the initialization directly. */
13348 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
13350 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
13351 emit_move_insn (target
, gen_lowpart (tmode
, x
));
13355 rtvec v
= rtvec_alloc (n_elt
);
13357 for (i
= 0; i
< n_elt
; ++i
)
13359 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
13360 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
13363 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
13369 /* Return the integer constant in ARG. Constrain it to be in the range
13370 of the subparts of VEC_TYPE; issue an error if not. */
13373 get_element_number (tree vec_type
, tree arg
)
13375 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
13377 if (!tree_fits_uhwi_p (arg
)
13378 || (elt
= tree_to_uhwi (arg
), elt
> max
))
13380 error ("selector must be an integer constant in the range 0..%wi", max
);
13387 /* Expand vec_set builtin. */
13389 altivec_expand_vec_set_builtin (tree exp
)
13391 machine_mode tmode
, mode1
;
13392 tree arg0
, arg1
, arg2
;
13396 arg0
= CALL_EXPR_ARG (exp
, 0);
13397 arg1
= CALL_EXPR_ARG (exp
, 1);
13398 arg2
= CALL_EXPR_ARG (exp
, 2);
13400 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
13401 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
13402 gcc_assert (VECTOR_MODE_P (tmode
));
13404 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
13405 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
13406 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
13408 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
13409 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
13411 op0
= force_reg (tmode
, op0
);
13412 op1
= force_reg (mode1
, op1
);
13414 rs6000_expand_vector_set (op0
, op1
, elt
);
13419 /* Expand vec_ext builtin. */
13421 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
13423 machine_mode tmode
, mode0
;
13428 arg0
= CALL_EXPR_ARG (exp
, 0);
13429 arg1
= CALL_EXPR_ARG (exp
, 1);
13431 op0
= expand_normal (arg0
);
13432 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
13434 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
13435 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
13436 gcc_assert (VECTOR_MODE_P (mode0
));
13438 op0
= force_reg (mode0
, op0
);
13440 if (optimize
|| !target
|| !register_operand (target
, tmode
))
13441 target
= gen_reg_rtx (tmode
);
13443 rs6000_expand_vector_extract (target
, op0
, elt
);
13448 /* Expand the builtin in EXP and store the result in TARGET. Store
13449 true in *EXPANDEDP if we found a builtin to expand. */
13451 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13453 const struct builtin_description
*d
;
13455 enum insn_code icode
;
13456 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13459 machine_mode tmode
, mode0
;
13460 enum rs6000_builtins fcode
13461 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13463 if (rs6000_overloaded_builtin_p (fcode
))
13466 error ("unresolved overload for Altivec builtin %qF", fndecl
);
13468 /* Given it is invalid, just generate a normal call. */
13469 return expand_call (exp
, target
, false);
13472 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
13476 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
13480 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
13488 case ALTIVEC_BUILTIN_STVX_V2DF
:
13489 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
13490 case ALTIVEC_BUILTIN_STVX_V2DI
:
13491 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
13492 case ALTIVEC_BUILTIN_STVX_V4SF
:
13493 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
13494 case ALTIVEC_BUILTIN_STVX
:
13495 case ALTIVEC_BUILTIN_STVX_V4SI
:
13496 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
13497 case ALTIVEC_BUILTIN_STVX_V8HI
:
13498 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
13499 case ALTIVEC_BUILTIN_STVX_V16QI
:
13500 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
13501 case ALTIVEC_BUILTIN_STVEBX
:
13502 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
13503 case ALTIVEC_BUILTIN_STVEHX
:
13504 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
13505 case ALTIVEC_BUILTIN_STVEWX
:
13506 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
13507 case ALTIVEC_BUILTIN_STVXL_V2DF
:
13508 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
13509 case ALTIVEC_BUILTIN_STVXL_V2DI
:
13510 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
13511 case ALTIVEC_BUILTIN_STVXL_V4SF
:
13512 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
13513 case ALTIVEC_BUILTIN_STVXL
:
13514 case ALTIVEC_BUILTIN_STVXL_V4SI
:
13515 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
13516 case ALTIVEC_BUILTIN_STVXL_V8HI
:
13517 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
13518 case ALTIVEC_BUILTIN_STVXL_V16QI
:
13519 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
13521 case ALTIVEC_BUILTIN_STVLX
:
13522 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
13523 case ALTIVEC_BUILTIN_STVLXL
:
13524 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
13525 case ALTIVEC_BUILTIN_STVRX
:
13526 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
13527 case ALTIVEC_BUILTIN_STVRXL
:
13528 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
13530 case VSX_BUILTIN_STXVD2X_V1TI
:
13531 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
13532 case VSX_BUILTIN_STXVD2X_V2DF
:
13533 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
13534 case VSX_BUILTIN_STXVD2X_V2DI
:
13535 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
13536 case VSX_BUILTIN_STXVW4X_V4SF
:
13537 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
13538 case VSX_BUILTIN_STXVW4X_V4SI
:
13539 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
13540 case VSX_BUILTIN_STXVW4X_V8HI
:
13541 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
13542 case VSX_BUILTIN_STXVW4X_V16QI
:
13543 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
13545 case ALTIVEC_BUILTIN_MFVSCR
:
13546 icode
= CODE_FOR_altivec_mfvscr
;
13547 tmode
= insn_data
[icode
].operand
[0].mode
;
13550 || GET_MODE (target
) != tmode
13551 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13552 target
= gen_reg_rtx (tmode
);
13554 pat
= GEN_FCN (icode
) (target
);
13560 case ALTIVEC_BUILTIN_MTVSCR
:
13561 icode
= CODE_FOR_altivec_mtvscr
;
13562 arg0
= CALL_EXPR_ARG (exp
, 0);
13563 op0
= expand_normal (arg0
);
13564 mode0
= insn_data
[icode
].operand
[0].mode
;
13566 /* If we got invalid arguments bail out before generating bad rtl. */
13567 if (arg0
== error_mark_node
)
13570 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13571 op0
= copy_to_mode_reg (mode0
, op0
);
13573 pat
= GEN_FCN (icode
) (op0
);
13578 case ALTIVEC_BUILTIN_DSSALL
:
13579 emit_insn (gen_altivec_dssall ());
13582 case ALTIVEC_BUILTIN_DSS
:
13583 icode
= CODE_FOR_altivec_dss
;
13584 arg0
= CALL_EXPR_ARG (exp
, 0);
13586 op0
= expand_normal (arg0
);
13587 mode0
= insn_data
[icode
].operand
[0].mode
;
13589 /* If we got invalid arguments bail out before generating bad rtl. */
13590 if (arg0
== error_mark_node
)
13593 if (TREE_CODE (arg0
) != INTEGER_CST
13594 || TREE_INT_CST_LOW (arg0
) & ~0x3)
13596 error ("argument to dss must be a 2-bit unsigned literal");
13600 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13601 op0
= copy_to_mode_reg (mode0
, op0
);
13603 emit_insn (gen_altivec_dss (op0
));
13606 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
13607 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
13608 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
13609 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
13610 case VSX_BUILTIN_VEC_INIT_V2DF
:
13611 case VSX_BUILTIN_VEC_INIT_V2DI
:
13612 case VSX_BUILTIN_VEC_INIT_V1TI
:
13613 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
13615 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
13616 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
13617 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
13618 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
13619 case VSX_BUILTIN_VEC_SET_V2DF
:
13620 case VSX_BUILTIN_VEC_SET_V2DI
:
13621 case VSX_BUILTIN_VEC_SET_V1TI
:
13622 return altivec_expand_vec_set_builtin (exp
);
13624 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
13625 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
13626 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
13627 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
13628 case VSX_BUILTIN_VEC_EXT_V2DF
:
13629 case VSX_BUILTIN_VEC_EXT_V2DI
:
13630 case VSX_BUILTIN_VEC_EXT_V1TI
:
13631 return altivec_expand_vec_ext_builtin (exp
, target
);
13635 /* Fall through. */
13638 /* Expand abs* operations. */
13640 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
13641 if (d
->code
== fcode
)
13642 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
13644 /* Expand the AltiVec predicates. */
13645 d
= bdesc_altivec_preds
;
13646 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
13647 if (d
->code
== fcode
)
13648 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
13650 /* LV* are funky. We initialized them differently. */
13653 case ALTIVEC_BUILTIN_LVSL
:
13654 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
13655 exp
, target
, false);
13656 case ALTIVEC_BUILTIN_LVSR
:
13657 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
13658 exp
, target
, false);
13659 case ALTIVEC_BUILTIN_LVEBX
:
13660 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
13661 exp
, target
, false);
13662 case ALTIVEC_BUILTIN_LVEHX
:
13663 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
13664 exp
, target
, false);
13665 case ALTIVEC_BUILTIN_LVEWX
:
13666 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
13667 exp
, target
, false);
13668 case ALTIVEC_BUILTIN_LVXL_V2DF
:
13669 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
13670 exp
, target
, false);
13671 case ALTIVEC_BUILTIN_LVXL_V2DI
:
13672 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
13673 exp
, target
, false);
13674 case ALTIVEC_BUILTIN_LVXL_V4SF
:
13675 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
13676 exp
, target
, false);
13677 case ALTIVEC_BUILTIN_LVXL
:
13678 case ALTIVEC_BUILTIN_LVXL_V4SI
:
13679 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
13680 exp
, target
, false);
13681 case ALTIVEC_BUILTIN_LVXL_V8HI
:
13682 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
13683 exp
, target
, false);
13684 case ALTIVEC_BUILTIN_LVXL_V16QI
:
13685 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
13686 exp
, target
, false);
13687 case ALTIVEC_BUILTIN_LVX_V2DF
:
13688 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
13689 exp
, target
, false);
13690 case ALTIVEC_BUILTIN_LVX_V2DI
:
13691 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
13692 exp
, target
, false);
13693 case ALTIVEC_BUILTIN_LVX_V4SF
:
13694 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
13695 exp
, target
, false);
13696 case ALTIVEC_BUILTIN_LVX
:
13697 case ALTIVEC_BUILTIN_LVX_V4SI
:
13698 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
13699 exp
, target
, false);
13700 case ALTIVEC_BUILTIN_LVX_V8HI
:
13701 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
13702 exp
, target
, false);
13703 case ALTIVEC_BUILTIN_LVX_V16QI
:
13704 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
13705 exp
, target
, false);
13706 case ALTIVEC_BUILTIN_LVLX
:
13707 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
13708 exp
, target
, true);
13709 case ALTIVEC_BUILTIN_LVLXL
:
13710 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
13711 exp
, target
, true);
13712 case ALTIVEC_BUILTIN_LVRX
:
13713 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
13714 exp
, target
, true);
13715 case ALTIVEC_BUILTIN_LVRXL
:
13716 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
13717 exp
, target
, true);
13718 case VSX_BUILTIN_LXVD2X_V1TI
:
13719 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
13720 exp
, target
, false);
13721 case VSX_BUILTIN_LXVD2X_V2DF
:
13722 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
13723 exp
, target
, false);
13724 case VSX_BUILTIN_LXVD2X_V2DI
:
13725 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
13726 exp
, target
, false);
13727 case VSX_BUILTIN_LXVW4X_V4SF
:
13728 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
13729 exp
, target
, false);
13730 case VSX_BUILTIN_LXVW4X_V4SI
:
13731 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
13732 exp
, target
, false);
13733 case VSX_BUILTIN_LXVW4X_V8HI
:
13734 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
13735 exp
, target
, false);
13736 case VSX_BUILTIN_LXVW4X_V16QI
:
13737 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
13738 exp
, target
, false);
13742 /* Fall through. */
13745 *expandedp
= false;
13749 /* Expand the builtin in EXP and store the result in TARGET. Store
13750 true in *EXPANDEDP if we found a builtin to expand. */
13752 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
13754 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13755 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13756 const struct builtin_description
*d
;
13763 case PAIRED_BUILTIN_STX
:
13764 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
13765 case PAIRED_BUILTIN_LX
:
13766 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
13769 /* Fall through. */
13772 /* Expand the paired predicates. */
13773 d
= bdesc_paired_preds
;
13774 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
13775 if (d
->code
== fcode
)
13776 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
13778 *expandedp
= false;
13782 /* Binops that need to be initialized manually, but can be expanded
13783 automagically by rs6000_expand_binop_builtin. */
13784 static const struct builtin_description bdesc_2arg_spe
[] =
13786 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
13787 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
13788 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
13789 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
13790 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
13791 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
13792 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
13793 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
13794 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
13795 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
13796 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
13797 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
13798 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
13799 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
13800 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
13801 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
13802 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
13803 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
13804 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
13805 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
13806 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
13807 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
13810 /* Expand the builtin in EXP and store the result in TARGET. Store
13811 true in *EXPANDEDP if we found a builtin to expand.
13813 This expands the SPE builtins that are not simple unary and binary
13816 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13818 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13820 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13821 enum insn_code icode
;
13822 machine_mode tmode
, mode0
;
13824 const struct builtin_description
*d
;
13829 /* Syntax check for a 5-bit unsigned immediate. */
13832 case SPE_BUILTIN_EVSTDD
:
13833 case SPE_BUILTIN_EVSTDH
:
13834 case SPE_BUILTIN_EVSTDW
:
13835 case SPE_BUILTIN_EVSTWHE
:
13836 case SPE_BUILTIN_EVSTWHO
:
13837 case SPE_BUILTIN_EVSTWWE
:
13838 case SPE_BUILTIN_EVSTWWO
:
13839 arg1
= CALL_EXPR_ARG (exp
, 2);
13840 if (TREE_CODE (arg1
) != INTEGER_CST
13841 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13843 error ("argument 2 must be a 5-bit unsigned literal");
13851 /* The evsplat*i instructions are not quite generic. */
13854 case SPE_BUILTIN_EVSPLATFI
:
13855 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
13857 case SPE_BUILTIN_EVSPLATI
:
13858 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
13864 d
= bdesc_2arg_spe
;
13865 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
13866 if (d
->code
== fcode
)
13867 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13869 d
= bdesc_spe_predicates
;
13870 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
13871 if (d
->code
== fcode
)
13872 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
13874 d
= bdesc_spe_evsel
;
13875 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
13876 if (d
->code
== fcode
)
13877 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
13881 case SPE_BUILTIN_EVSTDDX
:
13882 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
13883 case SPE_BUILTIN_EVSTDHX
:
13884 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
13885 case SPE_BUILTIN_EVSTDWX
:
13886 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
13887 case SPE_BUILTIN_EVSTWHEX
:
13888 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
13889 case SPE_BUILTIN_EVSTWHOX
:
13890 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
13891 case SPE_BUILTIN_EVSTWWEX
:
13892 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
13893 case SPE_BUILTIN_EVSTWWOX
:
13894 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
13895 case SPE_BUILTIN_EVSTDD
:
13896 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
13897 case SPE_BUILTIN_EVSTDH
:
13898 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
13899 case SPE_BUILTIN_EVSTDW
:
13900 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
13901 case SPE_BUILTIN_EVSTWHE
:
13902 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
13903 case SPE_BUILTIN_EVSTWHO
:
13904 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
13905 case SPE_BUILTIN_EVSTWWE
:
13906 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
13907 case SPE_BUILTIN_EVSTWWO
:
13908 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
13909 case SPE_BUILTIN_MFSPEFSCR
:
13910 icode
= CODE_FOR_spe_mfspefscr
;
13911 tmode
= insn_data
[icode
].operand
[0].mode
;
13914 || GET_MODE (target
) != tmode
13915 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13916 target
= gen_reg_rtx (tmode
);
13918 pat
= GEN_FCN (icode
) (target
);
13923 case SPE_BUILTIN_MTSPEFSCR
:
13924 icode
= CODE_FOR_spe_mtspefscr
;
13925 arg0
= CALL_EXPR_ARG (exp
, 0);
13926 op0
= expand_normal (arg0
);
13927 mode0
= insn_data
[icode
].operand
[0].mode
;
13929 if (arg0
== error_mark_node
)
13932 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13933 op0
= copy_to_mode_reg (mode0
, op0
);
13935 pat
= GEN_FCN (icode
) (op0
);
13943 *expandedp
= false;
13948 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13950 rtx pat
, scratch
, tmp
;
13951 tree form
= CALL_EXPR_ARG (exp
, 0);
13952 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13953 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13954 rtx op0
= expand_normal (arg0
);
13955 rtx op1
= expand_normal (arg1
);
13956 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13957 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13959 enum rtx_code code
;
13961 if (TREE_CODE (form
) != INTEGER_CST
)
13963 error ("argument 1 of __builtin_paired_predicate must be a constant");
13967 form_int
= TREE_INT_CST_LOW (form
);
13969 gcc_assert (mode0
== mode1
);
13971 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13975 || GET_MODE (target
) != SImode
13976 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13977 target
= gen_reg_rtx (SImode
);
13978 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13979 op0
= copy_to_mode_reg (mode0
, op0
);
13980 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13981 op1
= copy_to_mode_reg (mode1
, op1
);
13983 scratch
= gen_reg_rtx (CCFPmode
);
13985 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14007 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
14010 error ("argument 1 of __builtin_paired_predicate is out of range");
14014 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
14015 emit_move_insn (target
, tmp
);
14020 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
14022 rtx pat
, scratch
, tmp
;
14023 tree form
= CALL_EXPR_ARG (exp
, 0);
14024 tree arg0
= CALL_EXPR_ARG (exp
, 1);
14025 tree arg1
= CALL_EXPR_ARG (exp
, 2);
14026 rtx op0
= expand_normal (arg0
);
14027 rtx op1
= expand_normal (arg1
);
14028 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14029 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14031 enum rtx_code code
;
14033 if (TREE_CODE (form
) != INTEGER_CST
)
14035 error ("argument 1 of __builtin_spe_predicate must be a constant");
14039 form_int
= TREE_INT_CST_LOW (form
);
14041 gcc_assert (mode0
== mode1
);
14043 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14047 || GET_MODE (target
) != SImode
14048 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
14049 target
= gen_reg_rtx (SImode
);
14051 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14052 op0
= copy_to_mode_reg (mode0
, op0
);
14053 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14054 op1
= copy_to_mode_reg (mode1
, op1
);
14056 scratch
= gen_reg_rtx (CCmode
);
14058 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14063 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
14064 _lower_. We use one compare, but look in different bits of the
14065 CR for each variant.
14067 There are 2 elements in each SPE simd type (upper/lower). The CR
14068 bits are set as follows:
14070 BIT0 | BIT 1 | BIT 2 | BIT 3
14071 U | L | (U | L) | (U & L)
14073 So, for an "all" relationship, BIT 3 would be set.
14074 For an "any" relationship, BIT 2 would be set. Etc.
14076 Following traditional nomenclature, these bits map to:
14078 BIT0 | BIT 1 | BIT 2 | BIT 3
14081 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
14086 /* All variant. OV bit. */
14088 /* We need to get to the OV bit, which is the ORDERED bit. We
14089 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
14090 that's ugly and will make validate_condition_mode die.
14091 So let's just use another pattern. */
14092 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
14094 /* Any variant. EQ bit. */
14098 /* Upper variant. LT bit. */
14102 /* Lower variant. GT bit. */
14107 error ("argument 1 of __builtin_spe_predicate is out of range");
14111 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
14112 emit_move_insn (target
, tmp
);
14117 /* The evsel builtins look like this:
14119 e = __builtin_spe_evsel_OP (a, b, c, d);
14121 and work like this:
14123 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
14124 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
14128 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
14131 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14132 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14133 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14134 tree arg3
= CALL_EXPR_ARG (exp
, 3);
14135 rtx op0
= expand_normal (arg0
);
14136 rtx op1
= expand_normal (arg1
);
14137 rtx op2
= expand_normal (arg2
);
14138 rtx op3
= expand_normal (arg3
);
14139 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14140 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14142 gcc_assert (mode0
== mode1
);
14144 if (arg0
== error_mark_node
|| arg1
== error_mark_node
14145 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
14149 || GET_MODE (target
) != mode0
14150 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
14151 target
= gen_reg_rtx (mode0
);
14153 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14154 op0
= copy_to_mode_reg (mode0
, op0
);
14155 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
14156 op1
= copy_to_mode_reg (mode0
, op1
);
14157 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
14158 op2
= copy_to_mode_reg (mode0
, op2
);
14159 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
14160 op3
= copy_to_mode_reg (mode0
, op3
);
14162 /* Generate the compare. */
14163 scratch
= gen_reg_rtx (CCmode
);
14164 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14169 if (mode0
== V2SImode
)
14170 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
14172 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
14177 /* Raise an error message for a builtin function that is called without the
14178 appropriate target options being set. */
14181 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
14183 size_t uns_fncode
= (size_t)fncode
;
14184 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
14185 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
14187 gcc_assert (name
!= NULL
);
14188 if ((fnmask
& RS6000_BTM_CELL
) != 0)
14189 error ("Builtin function %s is only valid for the cell processor", name
);
14190 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
14191 error ("Builtin function %s requires the -mvsx option", name
);
14192 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
14193 error ("Builtin function %s requires the -mhtm option", name
);
14194 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
14195 error ("Builtin function %s requires the -maltivec option", name
);
14196 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
14197 error ("Builtin function %s requires the -mpaired option", name
);
14198 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
14199 error ("Builtin function %s requires the -mspe option", name
);
14200 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
14201 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
14202 error ("Builtin function %s requires the -mhard-dfp and"
14203 " -mpower8-vector options", name
);
14204 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
14205 error ("Builtin function %s requires the -mhard-dfp option", name
);
14206 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
14207 error ("Builtin function %s requires the -mpower8-vector option", name
);
14208 else if ((fnmask
& (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
14209 == (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
14210 error ("Builtin function %s requires the -mhard-float and"
14211 " -mlong-double-128 options", name
);
14212 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
14213 error ("Builtin function %s requires the -mhard-float option", name
);
14215 error ("Builtin function %s is not supported with the current options",
14219 /* Expand an expression EXP that calls a built-in function,
14220 with result going to TARGET if that's convenient
14221 (and in mode MODE if that's convenient).
14222 SUBTARGET may be used as the target for computing one of EXP's operands.
14223 IGNORE is nonzero if the value is to be ignored. */
14226 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14227 machine_mode mode ATTRIBUTE_UNUSED
,
14228 int ignore ATTRIBUTE_UNUSED
)
14230 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14231 enum rs6000_builtins fcode
14232 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
14233 size_t uns_fcode
= (size_t)fcode
;
14234 const struct builtin_description
*d
;
14238 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
14239 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
14241 if (TARGET_DEBUG_BUILTIN
)
14243 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
14244 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
14245 const char *name2
= ((icode
!= CODE_FOR_nothing
)
14246 ? get_insn_name ((int)icode
)
14250 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
14252 default: name3
= "unknown"; break;
14253 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
14254 case RS6000_BTC_UNARY
: name3
= "unary"; break;
14255 case RS6000_BTC_BINARY
: name3
= "binary"; break;
14256 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
14257 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
14258 case RS6000_BTC_ABS
: name3
= "abs"; break;
14259 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
14260 case RS6000_BTC_DST
: name3
= "dst"; break;
14265 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
14266 (name1
) ? name1
: "---", fcode
,
14267 (name2
) ? name2
: "---", (int)icode
,
14269 func_valid_p
? "" : ", not valid");
14274 rs6000_invalid_builtin (fcode
);
14276 /* Given it is invalid, just generate a normal call. */
14277 return expand_call (exp
, target
, ignore
);
14282 case RS6000_BUILTIN_RECIP
:
14283 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
14285 case RS6000_BUILTIN_RECIPF
:
14286 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
14288 case RS6000_BUILTIN_RSQRTF
:
14289 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
14291 case RS6000_BUILTIN_RSQRT
:
14292 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
14294 case POWER7_BUILTIN_BPERMD
:
14295 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
14296 ? CODE_FOR_bpermd_di
14297 : CODE_FOR_bpermd_si
), exp
, target
);
14299 case RS6000_BUILTIN_GET_TB
:
14300 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
14303 case RS6000_BUILTIN_MFTB
:
14304 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
14305 ? CODE_FOR_rs6000_mftb_di
14306 : CODE_FOR_rs6000_mftb_si
),
14309 case RS6000_BUILTIN_MFFS
:
14310 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
14312 case RS6000_BUILTIN_MTFSF
:
14313 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
14315 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
14316 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
14318 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr_direct
14319 : (int) CODE_FOR_altivec_lvsl_direct
);
14320 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14321 machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
14325 gcc_assert (TARGET_ALTIVEC
);
14327 arg
= CALL_EXPR_ARG (exp
, 0);
14328 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
14329 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
14330 addr
= memory_address (mode
, op
);
14331 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
14335 /* For the load case need to negate the address. */
14336 op
= gen_reg_rtx (GET_MODE (addr
));
14337 emit_insn (gen_rtx_SET (op
, gen_rtx_NEG (GET_MODE (addr
), addr
)));
14339 op
= gen_rtx_MEM (mode
, op
);
14342 || GET_MODE (target
) != tmode
14343 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14344 target
= gen_reg_rtx (tmode
);
14346 pat
= GEN_FCN (icode
) (target
, op
);
14354 case ALTIVEC_BUILTIN_VCFUX
:
14355 case ALTIVEC_BUILTIN_VCFSX
:
14356 case ALTIVEC_BUILTIN_VCTUXS
:
14357 case ALTIVEC_BUILTIN_VCTSXS
:
14358 /* FIXME: There's got to be a nicer way to handle this case than
14359 constructing a new CALL_EXPR. */
14360 if (call_expr_nargs (exp
) == 1)
14362 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
14363 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
14371 if (TARGET_ALTIVEC
)
14373 ret
= altivec_expand_builtin (exp
, target
, &success
);
14380 ret
= spe_expand_builtin (exp
, target
, &success
);
14385 if (TARGET_PAIRED_FLOAT
)
14387 ret
= paired_expand_builtin (exp
, target
, &success
);
14394 ret
= htm_expand_builtin (exp
, target
, &success
);
14400 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
14401 gcc_assert (attr
== RS6000_BTC_UNARY
14402 || attr
== RS6000_BTC_BINARY
14403 || attr
== RS6000_BTC_TERNARY
);
14405 /* Handle simple unary operations. */
14407 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
14408 if (d
->code
== fcode
)
14409 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
14411 /* Handle simple binary operations. */
14413 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
14414 if (d
->code
== fcode
)
14415 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
14417 /* Handle simple ternary operations. */
14419 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
14420 if (d
->code
== fcode
)
14421 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
14423 gcc_unreachable ();
14427 rs6000_init_builtins (void)
14432 machine_mode ieee128_mode
;
14433 machine_mode ibm128_mode
;
14435 if (TARGET_DEBUG_BUILTIN
)
14436 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
14437 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
14438 (TARGET_SPE
) ? ", spe" : "",
14439 (TARGET_ALTIVEC
) ? ", altivec" : "",
14440 (TARGET_VSX
) ? ", vsx" : "");
14442 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
14443 V2SF_type_node
= build_vector_type (float_type_node
, 2);
14444 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
14445 V2DF_type_node
= build_vector_type (double_type_node
, 2);
14446 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
14447 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
14448 V4SF_type_node
= build_vector_type (float_type_node
, 4);
14449 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
14450 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
14452 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
14453 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
14454 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
14455 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
14457 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
14458 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
14459 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
14460 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
14462 /* We use V1TI mode as a special container to hold __int128_t items that
14463 must live in VSX registers. */
14464 if (intTI_type_node
)
14466 V1TI_type_node
= build_vector_type (intTI_type_node
, 1);
14467 unsigned_V1TI_type_node
= build_vector_type (unsigned_intTI_type_node
, 1);
14470 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
14471 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
14472 'vector unsigned short'. */
14474 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
14475 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
14476 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
14477 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
14478 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
14480 long_integer_type_internal_node
= long_integer_type_node
;
14481 long_unsigned_type_internal_node
= long_unsigned_type_node
;
14482 long_long_integer_type_internal_node
= long_long_integer_type_node
;
14483 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
14484 intQI_type_internal_node
= intQI_type_node
;
14485 uintQI_type_internal_node
= unsigned_intQI_type_node
;
14486 intHI_type_internal_node
= intHI_type_node
;
14487 uintHI_type_internal_node
= unsigned_intHI_type_node
;
14488 intSI_type_internal_node
= intSI_type_node
;
14489 uintSI_type_internal_node
= unsigned_intSI_type_node
;
14490 intDI_type_internal_node
= intDI_type_node
;
14491 uintDI_type_internal_node
= unsigned_intDI_type_node
;
14492 intTI_type_internal_node
= intTI_type_node
;
14493 uintTI_type_internal_node
= unsigned_intTI_type_node
;
14494 float_type_internal_node
= float_type_node
;
14495 double_type_internal_node
= double_type_node
;
14496 long_double_type_internal_node
= long_double_type_node
;
14497 dfloat64_type_internal_node
= dfloat64_type_node
;
14498 dfloat128_type_internal_node
= dfloat128_type_node
;
14499 void_type_internal_node
= void_type_node
;
14501 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
14502 IFmode is the IBM extended 128-bit format that is a pair of doubles.
14503 TFmode will be either IEEE 128-bit floating point or the IBM double-double
14504 format that uses a pair of doubles, depending on the switches and
14506 if (TARGET_IEEEQUAD
)
14508 ieee128_mode
= TFmode
;
14509 ibm128_mode
= IFmode
;
14513 ieee128_mode
= KFmode
;
14514 ibm128_mode
= TFmode
;
14517 ieee128_float_type_node
= make_node (REAL_TYPE
);
14518 TYPE_PRECISION (ieee128_float_type_node
) = 128;
14519 layout_type (ieee128_float_type_node
);
14520 SET_TYPE_MODE (ieee128_float_type_node
, ieee128_mode
);
14522 ibm128_float_type_node
= make_node (REAL_TYPE
);
14523 TYPE_PRECISION (ibm128_float_type_node
) = 128;
14524 layout_type (ibm128_float_type_node
);
14525 SET_TYPE_MODE (ibm128_float_type_node
, ibm128_mode
);
14527 /* Initialize the modes for builtin_function_type, mapping a machine mode to
14529 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
14530 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
14531 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
14532 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
14533 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
14534 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
14535 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
14536 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
14537 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
14538 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
14539 builtin_mode_to_type
[IFmode
][0] = ibm128_float_type_node
;
14540 builtin_mode_to_type
[KFmode
][0] = ieee128_float_type_node
;
14541 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
14542 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
14543 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
14544 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
14545 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
14546 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
14547 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
14548 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
14549 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
14550 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
14551 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
14552 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
14553 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
14554 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
14555 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
14556 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
14557 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
14558 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
14560 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
14561 TYPE_NAME (bool_char_type_node
) = tdecl
;
14563 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
14564 TYPE_NAME (bool_short_type_node
) = tdecl
;
14566 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
14567 TYPE_NAME (bool_int_type_node
) = tdecl
;
14569 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
14570 TYPE_NAME (pixel_type_node
) = tdecl
;
14572 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
14573 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
14574 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
14575 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
14576 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
14578 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
14579 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
14581 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
14582 TYPE_NAME (V16QI_type_node
) = tdecl
;
14584 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
14585 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
14587 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
14588 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
14590 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
14591 TYPE_NAME (V8HI_type_node
) = tdecl
;
14593 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
14594 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
14596 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
14597 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
14599 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
14600 TYPE_NAME (V4SI_type_node
) = tdecl
;
14602 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
14603 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
14605 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
14606 TYPE_NAME (V4SF_type_node
) = tdecl
;
14608 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
14609 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
14611 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
14612 TYPE_NAME (V2DF_type_node
) = tdecl
;
14614 if (TARGET_POWERPC64
)
14616 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
14617 TYPE_NAME (V2DI_type_node
) = tdecl
;
14619 tdecl
= add_builtin_type ("__vector unsigned long",
14620 unsigned_V2DI_type_node
);
14621 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
14623 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
14624 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
14628 tdecl
= add_builtin_type ("__vector long long", V2DI_type_node
);
14629 TYPE_NAME (V2DI_type_node
) = tdecl
;
14631 tdecl
= add_builtin_type ("__vector unsigned long long",
14632 unsigned_V2DI_type_node
);
14633 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
14635 tdecl
= add_builtin_type ("__vector __bool long long",
14636 bool_V2DI_type_node
);
14637 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
14640 if (V1TI_type_node
)
14642 tdecl
= add_builtin_type ("__vector __int128", V1TI_type_node
);
14643 TYPE_NAME (V1TI_type_node
) = tdecl
;
14645 tdecl
= add_builtin_type ("__vector unsigned __int128",
14646 unsigned_V1TI_type_node
);
14647 TYPE_NAME (unsigned_V1TI_type_node
) = tdecl
;
14650 /* Paired and SPE builtins are only available if you build a compiler with
14651 the appropriate options, so only create those builtins with the
14652 appropriate compiler option. Create Altivec and VSX builtins on machines
14653 with at least the general purpose extensions (970 and newer) to allow the
14654 use of the target attribute. */
14655 if (TARGET_PAIRED_FLOAT
)
14656 paired_init_builtins ();
14658 spe_init_builtins ();
14659 if (TARGET_EXTRA_BUILTINS
)
14660 altivec_init_builtins ();
14662 htm_init_builtins ();
14664 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
14665 rs6000_common_init_builtins ();
14667 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
14668 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
14669 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
14671 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
14672 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
14673 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
14675 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
14676 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
14677 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
14679 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
14680 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
14681 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
14683 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
14684 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
14685 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
14686 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
14688 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14690 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
14693 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14696 ftype
= build_function_type_list (unsigned_intSI_type_node
,
14698 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
14700 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
14701 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
14703 ftype
= build_function_type_list (void_type_node
,
14704 intSI_type_node
, double_type_node
,
14706 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
14709 /* AIX libm provides clog as __clog. */
14710 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
14711 set_user_assembler_name (tdecl
, "__clog");
14714 #ifdef SUBTARGET_INIT_BUILTINS
14715 SUBTARGET_INIT_BUILTINS
;
14719 /* Returns the rs6000 builtin decl for CODE. */
14722 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
14724 HOST_WIDE_INT fnmask
;
14726 if (code
>= RS6000_BUILTIN_COUNT
)
14727 return error_mark_node
;
14729 fnmask
= rs6000_builtin_info
[code
].mask
;
14730 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
14732 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
14733 return error_mark_node
;
14736 return rs6000_builtin_decls
[code
];
14740 spe_init_builtins (void)
14742 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
14743 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
14744 const struct builtin_description
*d
;
14747 tree v2si_ftype_4_v2si
14748 = build_function_type_list (opaque_V2SI_type_node
,
14749 opaque_V2SI_type_node
,
14750 opaque_V2SI_type_node
,
14751 opaque_V2SI_type_node
,
14752 opaque_V2SI_type_node
,
14755 tree v2sf_ftype_4_v2sf
14756 = build_function_type_list (opaque_V2SF_type_node
,
14757 opaque_V2SF_type_node
,
14758 opaque_V2SF_type_node
,
14759 opaque_V2SF_type_node
,
14760 opaque_V2SF_type_node
,
14763 tree int_ftype_int_v2si_v2si
14764 = build_function_type_list (integer_type_node
,
14766 opaque_V2SI_type_node
,
14767 opaque_V2SI_type_node
,
14770 tree int_ftype_int_v2sf_v2sf
14771 = build_function_type_list (integer_type_node
,
14773 opaque_V2SF_type_node
,
14774 opaque_V2SF_type_node
,
14777 tree void_ftype_v2si_puint_int
14778 = build_function_type_list (void_type_node
,
14779 opaque_V2SI_type_node
,
14784 tree void_ftype_v2si_puint_char
14785 = build_function_type_list (void_type_node
,
14786 opaque_V2SI_type_node
,
14791 tree void_ftype_v2si_pv2si_int
14792 = build_function_type_list (void_type_node
,
14793 opaque_V2SI_type_node
,
14794 opaque_p_V2SI_type_node
,
14798 tree void_ftype_v2si_pv2si_char
14799 = build_function_type_list (void_type_node
,
14800 opaque_V2SI_type_node
,
14801 opaque_p_V2SI_type_node
,
14805 tree void_ftype_int
14806 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14808 tree int_ftype_void
14809 = build_function_type_list (integer_type_node
, NULL_TREE
);
14811 tree v2si_ftype_pv2si_int
14812 = build_function_type_list (opaque_V2SI_type_node
,
14813 opaque_p_V2SI_type_node
,
14817 tree v2si_ftype_puint_int
14818 = build_function_type_list (opaque_V2SI_type_node
,
14823 tree v2si_ftype_pushort_int
14824 = build_function_type_list (opaque_V2SI_type_node
,
14829 tree v2si_ftype_signed_char
14830 = build_function_type_list (opaque_V2SI_type_node
,
14831 signed_char_type_node
,
14834 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
14836 /* Initialize irregular SPE builtins. */
14838 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
14839 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
14840 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
14841 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
14842 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
14843 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
14844 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
14845 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
14846 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
14847 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
14848 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
14849 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
14850 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
14851 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
14852 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
14853 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
14854 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
14855 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
14858 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
14859 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
14860 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
14861 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
14862 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
14863 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
14864 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
14865 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
14866 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
14867 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
14868 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
14869 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
14870 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
14871 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
14872 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
14873 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
14874 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
14875 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
14876 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
14877 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
14878 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
14879 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
14882 d
= bdesc_spe_predicates
;
14883 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
14887 switch (insn_data
[d
->icode
].operand
[1].mode
)
14890 type
= int_ftype_int_v2si_v2si
;
14893 type
= int_ftype_int_v2sf_v2sf
;
14896 gcc_unreachable ();
14899 def_builtin (d
->name
, type
, d
->code
);
14902 /* Evsel predicates. */
14903 d
= bdesc_spe_evsel
;
14904 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
14908 switch (insn_data
[d
->icode
].operand
[1].mode
)
14911 type
= v2si_ftype_4_v2si
;
14914 type
= v2sf_ftype_4_v2sf
;
14917 gcc_unreachable ();
14920 def_builtin (d
->name
, type
, d
->code
);
14925 paired_init_builtins (void)
14927 const struct builtin_description
*d
;
14930 tree int_ftype_int_v2sf_v2sf
14931 = build_function_type_list (integer_type_node
,
14936 tree pcfloat_type_node
=
14937 build_pointer_type (build_qualified_type
14938 (float_type_node
, TYPE_QUAL_CONST
));
14940 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
14941 long_integer_type_node
,
14944 tree void_ftype_v2sf_long_pcfloat
=
14945 build_function_type_list (void_type_node
,
14947 long_integer_type_node
,
14952 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
14953 PAIRED_BUILTIN_LX
);
14956 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
14957 PAIRED_BUILTIN_STX
);
14960 d
= bdesc_paired_preds
;
14961 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
14965 if (TARGET_DEBUG_BUILTIN
)
14966 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
14967 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
14968 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
14970 switch (insn_data
[d
->icode
].operand
[1].mode
)
14973 type
= int_ftype_int_v2sf_v2sf
;
14976 gcc_unreachable ();
14979 def_builtin (d
->name
, type
, d
->code
);
14984 altivec_init_builtins (void)
14986 const struct builtin_description
*d
;
14991 tree pvoid_type_node
= build_pointer_type (void_type_node
);
14993 tree pcvoid_type_node
14994 = build_pointer_type (build_qualified_type (void_type_node
,
14997 tree int_ftype_opaque
14998 = build_function_type_list (integer_type_node
,
14999 opaque_V4SI_type_node
, NULL_TREE
);
15000 tree opaque_ftype_opaque
15001 = build_function_type_list (integer_type_node
, NULL_TREE
);
15002 tree opaque_ftype_opaque_int
15003 = build_function_type_list (opaque_V4SI_type_node
,
15004 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
15005 tree opaque_ftype_opaque_opaque_int
15006 = build_function_type_list (opaque_V4SI_type_node
,
15007 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
15008 integer_type_node
, NULL_TREE
);
15009 tree int_ftype_int_opaque_opaque
15010 = build_function_type_list (integer_type_node
,
15011 integer_type_node
, opaque_V4SI_type_node
,
15012 opaque_V4SI_type_node
, NULL_TREE
);
15013 tree int_ftype_int_v4si_v4si
15014 = build_function_type_list (integer_type_node
,
15015 integer_type_node
, V4SI_type_node
,
15016 V4SI_type_node
, NULL_TREE
);
15017 tree int_ftype_int_v2di_v2di
15018 = build_function_type_list (integer_type_node
,
15019 integer_type_node
, V2DI_type_node
,
15020 V2DI_type_node
, NULL_TREE
);
15021 tree void_ftype_v4si
15022 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
15023 tree v8hi_ftype_void
15024 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
15025 tree void_ftype_void
15026 = build_function_type_list (void_type_node
, NULL_TREE
);
15027 tree void_ftype_int
15028 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
15030 tree opaque_ftype_long_pcvoid
15031 = build_function_type_list (opaque_V4SI_type_node
,
15032 long_integer_type_node
, pcvoid_type_node
,
15034 tree v16qi_ftype_long_pcvoid
15035 = build_function_type_list (V16QI_type_node
,
15036 long_integer_type_node
, pcvoid_type_node
,
15038 tree v8hi_ftype_long_pcvoid
15039 = build_function_type_list (V8HI_type_node
,
15040 long_integer_type_node
, pcvoid_type_node
,
15042 tree v4si_ftype_long_pcvoid
15043 = build_function_type_list (V4SI_type_node
,
15044 long_integer_type_node
, pcvoid_type_node
,
15046 tree v4sf_ftype_long_pcvoid
15047 = build_function_type_list (V4SF_type_node
,
15048 long_integer_type_node
, pcvoid_type_node
,
15050 tree v2df_ftype_long_pcvoid
15051 = build_function_type_list (V2DF_type_node
,
15052 long_integer_type_node
, pcvoid_type_node
,
15054 tree v2di_ftype_long_pcvoid
15055 = build_function_type_list (V2DI_type_node
,
15056 long_integer_type_node
, pcvoid_type_node
,
15059 tree void_ftype_opaque_long_pvoid
15060 = build_function_type_list (void_type_node
,
15061 opaque_V4SI_type_node
, long_integer_type_node
,
15062 pvoid_type_node
, NULL_TREE
);
15063 tree void_ftype_v4si_long_pvoid
15064 = build_function_type_list (void_type_node
,
15065 V4SI_type_node
, long_integer_type_node
,
15066 pvoid_type_node
, NULL_TREE
);
15067 tree void_ftype_v16qi_long_pvoid
15068 = build_function_type_list (void_type_node
,
15069 V16QI_type_node
, long_integer_type_node
,
15070 pvoid_type_node
, NULL_TREE
);
15071 tree void_ftype_v8hi_long_pvoid
15072 = build_function_type_list (void_type_node
,
15073 V8HI_type_node
, long_integer_type_node
,
15074 pvoid_type_node
, NULL_TREE
);
15075 tree void_ftype_v4sf_long_pvoid
15076 = build_function_type_list (void_type_node
,
15077 V4SF_type_node
, long_integer_type_node
,
15078 pvoid_type_node
, NULL_TREE
);
15079 tree void_ftype_v2df_long_pvoid
15080 = build_function_type_list (void_type_node
,
15081 V2DF_type_node
, long_integer_type_node
,
15082 pvoid_type_node
, NULL_TREE
);
15083 tree void_ftype_v2di_long_pvoid
15084 = build_function_type_list (void_type_node
,
15085 V2DI_type_node
, long_integer_type_node
,
15086 pvoid_type_node
, NULL_TREE
);
15087 tree int_ftype_int_v8hi_v8hi
15088 = build_function_type_list (integer_type_node
,
15089 integer_type_node
, V8HI_type_node
,
15090 V8HI_type_node
, NULL_TREE
);
15091 tree int_ftype_int_v16qi_v16qi
15092 = build_function_type_list (integer_type_node
,
15093 integer_type_node
, V16QI_type_node
,
15094 V16QI_type_node
, NULL_TREE
);
15095 tree int_ftype_int_v4sf_v4sf
15096 = build_function_type_list (integer_type_node
,
15097 integer_type_node
, V4SF_type_node
,
15098 V4SF_type_node
, NULL_TREE
);
15099 tree int_ftype_int_v2df_v2df
15100 = build_function_type_list (integer_type_node
,
15101 integer_type_node
, V2DF_type_node
,
15102 V2DF_type_node
, NULL_TREE
);
15103 tree v2di_ftype_v2di
15104 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
15105 tree v4si_ftype_v4si
15106 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
15107 tree v8hi_ftype_v8hi
15108 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
15109 tree v16qi_ftype_v16qi
15110 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
15111 tree v4sf_ftype_v4sf
15112 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
15113 tree v2df_ftype_v2df
15114 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
15115 tree void_ftype_pcvoid_int_int
15116 = build_function_type_list (void_type_node
,
15117 pcvoid_type_node
, integer_type_node
,
15118 integer_type_node
, NULL_TREE
);
15120 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
15121 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
15122 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
15123 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
15124 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
15125 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
15126 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
15127 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
15128 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
15129 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
15130 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
15131 ALTIVEC_BUILTIN_LVXL_V2DF
);
15132 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
15133 ALTIVEC_BUILTIN_LVXL_V2DI
);
15134 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
15135 ALTIVEC_BUILTIN_LVXL_V4SF
);
15136 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
15137 ALTIVEC_BUILTIN_LVXL_V4SI
);
15138 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
15139 ALTIVEC_BUILTIN_LVXL_V8HI
);
15140 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
15141 ALTIVEC_BUILTIN_LVXL_V16QI
);
15142 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
15143 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
15144 ALTIVEC_BUILTIN_LVX_V2DF
);
15145 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
15146 ALTIVEC_BUILTIN_LVX_V2DI
);
15147 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
15148 ALTIVEC_BUILTIN_LVX_V4SF
);
15149 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
15150 ALTIVEC_BUILTIN_LVX_V4SI
);
15151 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
15152 ALTIVEC_BUILTIN_LVX_V8HI
);
15153 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
15154 ALTIVEC_BUILTIN_LVX_V16QI
);
15155 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
15156 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
15157 ALTIVEC_BUILTIN_STVX_V2DF
);
15158 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
15159 ALTIVEC_BUILTIN_STVX_V2DI
);
15160 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
15161 ALTIVEC_BUILTIN_STVX_V4SF
);
15162 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
15163 ALTIVEC_BUILTIN_STVX_V4SI
);
15164 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
15165 ALTIVEC_BUILTIN_STVX_V8HI
);
15166 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
15167 ALTIVEC_BUILTIN_STVX_V16QI
);
15168 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
15169 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
15170 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
15171 ALTIVEC_BUILTIN_STVXL_V2DF
);
15172 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
15173 ALTIVEC_BUILTIN_STVXL_V2DI
);
15174 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
15175 ALTIVEC_BUILTIN_STVXL_V4SF
);
15176 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
15177 ALTIVEC_BUILTIN_STVXL_V4SI
);
15178 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
15179 ALTIVEC_BUILTIN_STVXL_V8HI
);
15180 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
15181 ALTIVEC_BUILTIN_STVXL_V16QI
);
15182 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
15183 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
15184 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
15185 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
15186 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
15187 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
15188 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
15189 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
15190 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
15191 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
15192 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
15193 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
15194 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
15195 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
15196 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
15197 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
15199 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
15200 VSX_BUILTIN_LXVD2X_V2DF
);
15201 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
15202 VSX_BUILTIN_LXVD2X_V2DI
);
15203 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
15204 VSX_BUILTIN_LXVW4X_V4SF
);
15205 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
15206 VSX_BUILTIN_LXVW4X_V4SI
);
15207 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
15208 VSX_BUILTIN_LXVW4X_V8HI
);
15209 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
15210 VSX_BUILTIN_LXVW4X_V16QI
);
15211 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
15212 VSX_BUILTIN_STXVD2X_V2DF
);
15213 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
15214 VSX_BUILTIN_STXVD2X_V2DI
);
15215 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
15216 VSX_BUILTIN_STXVW4X_V4SF
);
15217 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
15218 VSX_BUILTIN_STXVW4X_V4SI
);
15219 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
15220 VSX_BUILTIN_STXVW4X_V8HI
);
15221 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
15222 VSX_BUILTIN_STXVW4X_V16QI
);
15223 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
15224 VSX_BUILTIN_VEC_LD
);
15225 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
15226 VSX_BUILTIN_VEC_ST
);
15228 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
15229 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
15230 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
15232 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
15233 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
15234 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
15235 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
15236 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
15237 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
15238 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
15239 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
15240 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
15241 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
15242 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
15243 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
15245 /* Cell builtins. */
15246 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
15247 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
15248 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
15249 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
15251 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
15252 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
15253 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
15254 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
15256 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
15257 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
15258 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
15259 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
15261 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
15262 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
15263 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
15264 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
15266 /* Add the DST variants. */
15268 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
15269 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
15271 /* Initialize the predicates. */
15272 d
= bdesc_altivec_preds
;
15273 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
15275 machine_mode mode1
;
15278 if (rs6000_overloaded_builtin_p (d
->code
))
15281 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
15286 type
= int_ftype_int_opaque_opaque
;
15289 type
= int_ftype_int_v2di_v2di
;
15292 type
= int_ftype_int_v4si_v4si
;
15295 type
= int_ftype_int_v8hi_v8hi
;
15298 type
= int_ftype_int_v16qi_v16qi
;
15301 type
= int_ftype_int_v4sf_v4sf
;
15304 type
= int_ftype_int_v2df_v2df
;
15307 gcc_unreachable ();
15310 def_builtin (d
->name
, type
, d
->code
);
15313 /* Initialize the abs* operators. */
15315 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
15317 machine_mode mode0
;
15320 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
15325 type
= v2di_ftype_v2di
;
15328 type
= v4si_ftype_v4si
;
15331 type
= v8hi_ftype_v8hi
;
15334 type
= v16qi_ftype_v16qi
;
15337 type
= v4sf_ftype_v4sf
;
15340 type
= v2df_ftype_v2df
;
15343 gcc_unreachable ();
15346 def_builtin (d
->name
, type
, d
->code
);
15349 /* Initialize target builtin that implements
15350 targetm.vectorize.builtin_mask_for_load. */
15352 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
15353 v16qi_ftype_long_pcvoid
,
15354 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
15355 BUILT_IN_MD
, NULL
, NULL_TREE
);
15356 TREE_READONLY (decl
) = 1;
15357 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
15358 altivec_builtin_mask_for_load
= decl
;
15360 /* Access to the vec_init patterns. */
15361 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
15362 integer_type_node
, integer_type_node
,
15363 integer_type_node
, NULL_TREE
);
15364 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
15366 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
15367 short_integer_type_node
,
15368 short_integer_type_node
,
15369 short_integer_type_node
,
15370 short_integer_type_node
,
15371 short_integer_type_node
,
15372 short_integer_type_node
,
15373 short_integer_type_node
, NULL_TREE
);
15374 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
15376 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
15377 char_type_node
, char_type_node
,
15378 char_type_node
, char_type_node
,
15379 char_type_node
, char_type_node
,
15380 char_type_node
, char_type_node
,
15381 char_type_node
, char_type_node
,
15382 char_type_node
, char_type_node
,
15383 char_type_node
, char_type_node
,
15384 char_type_node
, NULL_TREE
);
15385 def_builtin ("__builtin_vec_init_v16qi", ftype
,
15386 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
15388 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
15389 float_type_node
, float_type_node
,
15390 float_type_node
, NULL_TREE
);
15391 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
15393 /* VSX builtins. */
15394 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
15395 double_type_node
, NULL_TREE
);
15396 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
15398 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
15399 intDI_type_node
, NULL_TREE
);
15400 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
15402 /* Access to the vec_set patterns. */
15403 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
15405 integer_type_node
, NULL_TREE
);
15406 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
15408 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
15410 integer_type_node
, NULL_TREE
);
15411 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
15413 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
15415 integer_type_node
, NULL_TREE
);
15416 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
15418 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
15420 integer_type_node
, NULL_TREE
);
15421 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
15423 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
15425 integer_type_node
, NULL_TREE
);
15426 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
15428 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
15430 integer_type_node
, NULL_TREE
);
15431 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
15433 /* Access to the vec_extract patterns. */
15434 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
15435 integer_type_node
, NULL_TREE
);
15436 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
15438 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
15439 integer_type_node
, NULL_TREE
);
15440 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
15442 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
15443 integer_type_node
, NULL_TREE
);
15444 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
15446 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
15447 integer_type_node
, NULL_TREE
);
15448 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
15450 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
15451 integer_type_node
, NULL_TREE
);
15452 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
15454 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
15455 integer_type_node
, NULL_TREE
);
15456 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
15459 if (V1TI_type_node
)
15461 tree v1ti_ftype_long_pcvoid
15462 = build_function_type_list (V1TI_type_node
,
15463 long_integer_type_node
, pcvoid_type_node
,
15465 tree void_ftype_v1ti_long_pvoid
15466 = build_function_type_list (void_type_node
,
15467 V1TI_type_node
, long_integer_type_node
,
15468 pvoid_type_node
, NULL_TREE
);
15469 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
15470 VSX_BUILTIN_LXVD2X_V1TI
);
15471 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
15472 VSX_BUILTIN_STXVD2X_V1TI
);
15473 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
15474 NULL_TREE
, NULL_TREE
);
15475 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
15476 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
15478 integer_type_node
, NULL_TREE
);
15479 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
15480 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
15481 integer_type_node
, NULL_TREE
);
15482 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
15488 htm_init_builtins (void)
15490 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15491 const struct builtin_description
*d
;
15495 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
15497 tree op
[MAX_HTM_OPERANDS
], type
;
15498 HOST_WIDE_INT mask
= d
->mask
;
15499 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
15500 bool void_func
= (attr
& RS6000_BTC_VOID
);
15501 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
15503 tree gpr_type_node
;
15507 if (TARGET_32BIT
&& TARGET_POWERPC64
)
15508 gpr_type_node
= long_long_unsigned_type_node
;
15510 gpr_type_node
= long_unsigned_type_node
;
15512 if (attr
& RS6000_BTC_SPR
)
15514 rettype
= gpr_type_node
;
15515 argtype
= gpr_type_node
;
15517 else if (d
->code
== HTM_BUILTIN_TABORTDC
15518 || d
->code
== HTM_BUILTIN_TABORTDCI
)
15520 rettype
= unsigned_type_node
;
15521 argtype
= gpr_type_node
;
15525 rettype
= unsigned_type_node
;
15526 argtype
= unsigned_type_node
;
15529 if ((mask
& builtin_mask
) != mask
)
15531 if (TARGET_DEBUG_BUILTIN
)
15532 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
15538 if (TARGET_DEBUG_BUILTIN
)
15539 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
15540 (long unsigned) i
);
15544 op
[nopnds
++] = (void_func
) ? void_type_node
: rettype
;
15546 if (attr_args
== RS6000_BTC_UNARY
)
15547 op
[nopnds
++] = argtype
;
15548 else if (attr_args
== RS6000_BTC_BINARY
)
15550 op
[nopnds
++] = argtype
;
15551 op
[nopnds
++] = argtype
;
15553 else if (attr_args
== RS6000_BTC_TERNARY
)
15555 op
[nopnds
++] = argtype
;
15556 op
[nopnds
++] = argtype
;
15557 op
[nopnds
++] = argtype
;
15563 type
= build_function_type_list (op
[0], NULL_TREE
);
15566 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
15569 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
15572 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
15576 gcc_unreachable ();
15579 def_builtin (d
->name
, type
, d
->code
);
15583 /* Hash function for builtin functions with up to 3 arguments and a return
15586 builtin_hasher::hash (builtin_hash_struct
*bh
)
15591 for (i
= 0; i
< 4; i
++)
15593 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
15594 ret
= (ret
* 2) + bh
->uns_p
[i
];
15600 /* Compare builtin hash entries H1 and H2 for equivalence. */
15602 builtin_hasher::equal (builtin_hash_struct
*p1
, builtin_hash_struct
*p2
)
15604 return ((p1
->mode
[0] == p2
->mode
[0])
15605 && (p1
->mode
[1] == p2
->mode
[1])
15606 && (p1
->mode
[2] == p2
->mode
[2])
15607 && (p1
->mode
[3] == p2
->mode
[3])
15608 && (p1
->uns_p
[0] == p2
->uns_p
[0])
15609 && (p1
->uns_p
[1] == p2
->uns_p
[1])
15610 && (p1
->uns_p
[2] == p2
->uns_p
[2])
15611 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
15614 /* Map types for builtin functions with an explicit return type and up to 3
15615 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
15616 of the argument. */
15618 builtin_function_type (machine_mode mode_ret
, machine_mode mode_arg0
,
15619 machine_mode mode_arg1
, machine_mode mode_arg2
,
15620 enum rs6000_builtins builtin
, const char *name
)
15622 struct builtin_hash_struct h
;
15623 struct builtin_hash_struct
*h2
;
15626 tree ret_type
= NULL_TREE
;
15627 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
15629 /* Create builtin_hash_table. */
15630 if (builtin_hash_table
== NULL
)
15631 builtin_hash_table
= hash_table
<builtin_hasher
>::create_ggc (1500);
15633 h
.type
= NULL_TREE
;
15634 h
.mode
[0] = mode_ret
;
15635 h
.mode
[1] = mode_arg0
;
15636 h
.mode
[2] = mode_arg1
;
15637 h
.mode
[3] = mode_arg2
;
15643 /* If the builtin is a type that produces unsigned results or takes unsigned
15644 arguments, and it is returned as a decl for the vectorizer (such as
15645 widening multiplies, permute), make sure the arguments and return value
15646 are type correct. */
15649 /* unsigned 1 argument functions. */
15650 case CRYPTO_BUILTIN_VSBOX
:
15651 case P8V_BUILTIN_VGBBD
:
15652 case MISC_BUILTIN_CDTBCD
:
15653 case MISC_BUILTIN_CBCDTD
:
15658 /* unsigned 2 argument functions. */
15659 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
15660 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
15661 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
15662 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
15663 case CRYPTO_BUILTIN_VCIPHER
:
15664 case CRYPTO_BUILTIN_VCIPHERLAST
:
15665 case CRYPTO_BUILTIN_VNCIPHER
:
15666 case CRYPTO_BUILTIN_VNCIPHERLAST
:
15667 case CRYPTO_BUILTIN_VPMSUMB
:
15668 case CRYPTO_BUILTIN_VPMSUMH
:
15669 case CRYPTO_BUILTIN_VPMSUMW
:
15670 case CRYPTO_BUILTIN_VPMSUMD
:
15671 case CRYPTO_BUILTIN_VPMSUM
:
15672 case MISC_BUILTIN_ADDG6S
:
15673 case MISC_BUILTIN_DIVWEU
:
15674 case MISC_BUILTIN_DIVWEUO
:
15675 case MISC_BUILTIN_DIVDEU
:
15676 case MISC_BUILTIN_DIVDEUO
:
15682 /* unsigned 3 argument functions. */
15683 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
15684 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
15685 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
15686 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
15687 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
15688 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
15689 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
15690 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
15691 case VSX_BUILTIN_VPERM_16QI_UNS
:
15692 case VSX_BUILTIN_VPERM_8HI_UNS
:
15693 case VSX_BUILTIN_VPERM_4SI_UNS
:
15694 case VSX_BUILTIN_VPERM_2DI_UNS
:
15695 case VSX_BUILTIN_XXSEL_16QI_UNS
:
15696 case VSX_BUILTIN_XXSEL_8HI_UNS
:
15697 case VSX_BUILTIN_XXSEL_4SI_UNS
:
15698 case VSX_BUILTIN_XXSEL_2DI_UNS
:
15699 case CRYPTO_BUILTIN_VPERMXOR
:
15700 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
15701 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
15702 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
15703 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
15704 case CRYPTO_BUILTIN_VSHASIGMAW
:
15705 case CRYPTO_BUILTIN_VSHASIGMAD
:
15706 case CRYPTO_BUILTIN_VSHASIGMA
:
15713 /* signed permute functions with unsigned char mask. */
15714 case ALTIVEC_BUILTIN_VPERM_16QI
:
15715 case ALTIVEC_BUILTIN_VPERM_8HI
:
15716 case ALTIVEC_BUILTIN_VPERM_4SI
:
15717 case ALTIVEC_BUILTIN_VPERM_4SF
:
15718 case ALTIVEC_BUILTIN_VPERM_2DI
:
15719 case ALTIVEC_BUILTIN_VPERM_2DF
:
15720 case VSX_BUILTIN_VPERM_16QI
:
15721 case VSX_BUILTIN_VPERM_8HI
:
15722 case VSX_BUILTIN_VPERM_4SI
:
15723 case VSX_BUILTIN_VPERM_4SF
:
15724 case VSX_BUILTIN_VPERM_2DI
:
15725 case VSX_BUILTIN_VPERM_2DF
:
15729 /* unsigned args, signed return. */
15730 case VSX_BUILTIN_XVCVUXDDP_UNS
:
15731 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
15735 /* signed args, unsigned return. */
15736 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
15737 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
15738 case MISC_BUILTIN_UNPACK_TD
:
15739 case MISC_BUILTIN_UNPACK_V1TI
:
15743 /* unsigned arguments for 128-bit pack instructions. */
15744 case MISC_BUILTIN_PACK_TD
:
15745 case MISC_BUILTIN_PACK_V1TI
:
15754 /* Figure out how many args are present. */
15755 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
15759 fatal_error (input_location
,
15760 "internal error: builtin function %s had no type", name
);
15762 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
15763 if (!ret_type
&& h
.uns_p
[0])
15764 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
15767 fatal_error (input_location
,
15768 "internal error: builtin function %s had an unexpected "
15769 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
15771 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
15772 arg_type
[i
] = NULL_TREE
;
15774 for (i
= 0; i
< num_args
; i
++)
15776 int m
= (int) h
.mode
[i
+1];
15777 int uns_p
= h
.uns_p
[i
+1];
15779 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
15780 if (!arg_type
[i
] && uns_p
)
15781 arg_type
[i
] = builtin_mode_to_type
[m
][0];
15784 fatal_error (input_location
,
15785 "internal error: builtin function %s, argument %d "
15786 "had unexpected argument type %s", name
, i
,
15787 GET_MODE_NAME (m
));
15790 builtin_hash_struct
**found
= builtin_hash_table
->find_slot (&h
, INSERT
);
15791 if (*found
== NULL
)
15793 h2
= ggc_alloc
<builtin_hash_struct
> ();
15797 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
15798 arg_type
[2], NULL_TREE
);
15801 return (*found
)->type
;
15805 rs6000_common_init_builtins (void)
15807 const struct builtin_description
*d
;
15810 tree opaque_ftype_opaque
= NULL_TREE
;
15811 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
15812 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
15813 tree v2si_ftype_qi
= NULL_TREE
;
15814 tree v2si_ftype_v2si_qi
= NULL_TREE
;
15815 tree v2si_ftype_int_qi
= NULL_TREE
;
15816 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15818 if (!TARGET_PAIRED_FLOAT
)
15820 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
15821 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
15824 /* Paired and SPE builtins are only available if you build a compiler with
15825 the appropriate options, so only create those builtins with the
15826 appropriate compiler option. Create Altivec and VSX builtins on machines
15827 with at least the general purpose extensions (970 and newer) to allow the
15828 use of the target attribute.. */
15830 if (TARGET_EXTRA_BUILTINS
)
15831 builtin_mask
|= RS6000_BTM_COMMON
;
15833 /* Add the ternary operators. */
15835 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
15838 HOST_WIDE_INT mask
= d
->mask
;
15840 if ((mask
& builtin_mask
) != mask
)
15842 if (TARGET_DEBUG_BUILTIN
)
15843 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
15847 if (rs6000_overloaded_builtin_p (d
->code
))
15849 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
15850 type
= opaque_ftype_opaque_opaque_opaque
15851 = build_function_type_list (opaque_V4SI_type_node
,
15852 opaque_V4SI_type_node
,
15853 opaque_V4SI_type_node
,
15854 opaque_V4SI_type_node
,
15859 enum insn_code icode
= d
->icode
;
15862 if (TARGET_DEBUG_BUILTIN
)
15863 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
15869 if (icode
== CODE_FOR_nothing
)
15871 if (TARGET_DEBUG_BUILTIN
)
15872 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
15878 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
15879 insn_data
[icode
].operand
[1].mode
,
15880 insn_data
[icode
].operand
[2].mode
,
15881 insn_data
[icode
].operand
[3].mode
,
15885 def_builtin (d
->name
, type
, d
->code
);
15888 /* Add the binary operators. */
15890 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
15892 machine_mode mode0
, mode1
, mode2
;
15894 HOST_WIDE_INT mask
= d
->mask
;
15896 if ((mask
& builtin_mask
) != mask
)
15898 if (TARGET_DEBUG_BUILTIN
)
15899 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
15903 if (rs6000_overloaded_builtin_p (d
->code
))
15905 if (! (type
= opaque_ftype_opaque_opaque
))
15906 type
= opaque_ftype_opaque_opaque
15907 = build_function_type_list (opaque_V4SI_type_node
,
15908 opaque_V4SI_type_node
,
15909 opaque_V4SI_type_node
,
15914 enum insn_code icode
= d
->icode
;
15917 if (TARGET_DEBUG_BUILTIN
)
15918 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
15924 if (icode
== CODE_FOR_nothing
)
15926 if (TARGET_DEBUG_BUILTIN
)
15927 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
15933 mode0
= insn_data
[icode
].operand
[0].mode
;
15934 mode1
= insn_data
[icode
].operand
[1].mode
;
15935 mode2
= insn_data
[icode
].operand
[2].mode
;
15937 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
15939 if (! (type
= v2si_ftype_v2si_qi
))
15940 type
= v2si_ftype_v2si_qi
15941 = build_function_type_list (opaque_V2SI_type_node
,
15942 opaque_V2SI_type_node
,
15947 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
15948 && mode2
== QImode
)
15950 if (! (type
= v2si_ftype_int_qi
))
15951 type
= v2si_ftype_int_qi
15952 = build_function_type_list (opaque_V2SI_type_node
,
15959 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
15963 def_builtin (d
->name
, type
, d
->code
);
15966 /* Add the simple unary operators. */
15968 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
15970 machine_mode mode0
, mode1
;
15972 HOST_WIDE_INT mask
= d
->mask
;
15974 if ((mask
& builtin_mask
) != mask
)
15976 if (TARGET_DEBUG_BUILTIN
)
15977 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
15981 if (rs6000_overloaded_builtin_p (d
->code
))
15983 if (! (type
= opaque_ftype_opaque
))
15984 type
= opaque_ftype_opaque
15985 = build_function_type_list (opaque_V4SI_type_node
,
15986 opaque_V4SI_type_node
,
15991 enum insn_code icode
= d
->icode
;
15994 if (TARGET_DEBUG_BUILTIN
)
15995 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
16001 if (icode
== CODE_FOR_nothing
)
16003 if (TARGET_DEBUG_BUILTIN
)
16004 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
16010 mode0
= insn_data
[icode
].operand
[0].mode
;
16011 mode1
= insn_data
[icode
].operand
[1].mode
;
16013 if (mode0
== V2SImode
&& mode1
== QImode
)
16015 if (! (type
= v2si_ftype_qi
))
16016 type
= v2si_ftype_qi
16017 = build_function_type_list (opaque_V2SI_type_node
,
16023 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
16027 def_builtin (d
->name
, type
, d
->code
);
16032 rs6000_init_libfuncs (void)
16034 if (!TARGET_IEEEQUAD
)
16035 /* AIX/Darwin/64-bit Linux quad floating point routines. */
16036 if (!TARGET_XL_COMPAT
)
16038 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
16039 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
16040 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
16041 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
16043 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
16045 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
16046 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
16047 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
16048 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
16049 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
16050 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
16051 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
16053 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
16054 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
16055 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
16056 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
16057 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
16058 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
16059 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
16060 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
16063 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
16064 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
16068 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
16069 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
16070 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
16071 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
16075 /* 32-bit SVR4 quad floating point routines. */
16077 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
16078 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
16079 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
16080 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
16081 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
16082 if (TARGET_PPC_GPOPT
)
16083 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
16085 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
16086 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
16087 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
16088 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
16089 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
16090 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
16092 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
16093 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
16094 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
16095 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
16096 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
16097 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
16098 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
16099 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
16104 /* Expand a block clear operation, and return 1 if successful. Return 0
16105 if we should let the compiler generate normal code.
16107 operands[0] is the destination
16108 operands[1] is the length
16109 operands[3] is the alignment */
16112 expand_block_clear (rtx operands
[])
16114 rtx orig_dest
= operands
[0];
16115 rtx bytes_rtx
= operands
[1];
16116 rtx align_rtx
= operands
[3];
16117 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
16118 HOST_WIDE_INT align
;
16119 HOST_WIDE_INT bytes
;
16124 /* If this is not a fixed size move, just call memcpy */
16128 /* This must be a fixed size alignment */
16129 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
16130 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
16132 /* Anything to clear? */
16133 bytes
= INTVAL (bytes_rtx
);
16137 /* Use the builtin memset after a point, to avoid huge code bloat.
16138 When optimize_size, avoid any significant code bloat; calling
16139 memset is about 4 instructions, so allow for one instruction to
16140 load zero and three to do clearing. */
16141 if (TARGET_ALTIVEC
&& align
>= 128)
16143 else if (TARGET_POWERPC64
&& (align
>= 64 || !STRICT_ALIGNMENT
))
16145 else if (TARGET_SPE
&& align
>= 64)
16150 if (optimize_size
&& bytes
> 3 * clear_step
)
16152 if (! optimize_size
&& bytes
> 8 * clear_step
)
16155 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
16157 machine_mode mode
= BLKmode
;
16160 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
16165 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
16170 else if (bytes
>= 8 && TARGET_POWERPC64
16171 && (align
>= 64 || !STRICT_ALIGNMENT
))
16175 if (offset
== 0 && align
< 64)
16179 /* If the address form is reg+offset with offset not a
16180 multiple of four, reload into reg indirect form here
16181 rather than waiting for reload. This way we get one
16182 reload, not one per store. */
16183 addr
= XEXP (orig_dest
, 0);
16184 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16185 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16186 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16188 addr
= copy_addr_to_reg (addr
);
16189 orig_dest
= replace_equiv_address (orig_dest
, addr
);
16193 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
16194 { /* move 4 bytes */
16198 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
16199 { /* move 2 bytes */
16203 else /* move 1 byte at a time */
16209 dest
= adjust_address (orig_dest
, mode
, offset
);
16211 emit_move_insn (dest
, CONST0_RTX (mode
));
16218 /* Expand a block move operation, and return 1 if successful. Return 0
16219 if we should let the compiler generate normal code.
16221 operands[0] is the destination
16222 operands[1] is the source
16223 operands[2] is the length
16224 operands[3] is the alignment */
16226 #define MAX_MOVE_REG 4
16229 expand_block_move (rtx operands
[])
16231 rtx orig_dest
= operands
[0];
16232 rtx orig_src
= operands
[1];
16233 rtx bytes_rtx
= operands
[2];
16234 rtx align_rtx
= operands
[3];
16235 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
16240 rtx stores
[MAX_MOVE_REG
];
16243 /* If this is not a fixed size move, just call memcpy */
16247 /* This must be a fixed size alignment */
16248 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
16249 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
16251 /* Anything to move? */
16252 bytes
= INTVAL (bytes_rtx
);
16256 if (bytes
> rs6000_block_move_inline_limit
)
16259 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
16262 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
16263 rtx (*mov
) (rtx
, rtx
);
16265 machine_mode mode
= BLKmode
;
16268 /* Altivec first, since it will be faster than a string move
16269 when it applies, and usually not significantly larger. */
16270 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
16274 gen_func
.mov
= gen_movv4si
;
16276 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
16280 gen_func
.mov
= gen_movv2si
;
16282 else if (TARGET_STRING
16283 && bytes
> 24 /* move up to 32 bytes at a time */
16289 && ! fixed_regs
[10]
16290 && ! fixed_regs
[11]
16291 && ! fixed_regs
[12])
16293 move_bytes
= (bytes
> 32) ? 32 : bytes
;
16294 gen_func
.movmemsi
= gen_movmemsi_8reg
;
16296 else if (TARGET_STRING
16297 && bytes
> 16 /* move up to 24 bytes at a time */
16303 && ! fixed_regs
[10])
16305 move_bytes
= (bytes
> 24) ? 24 : bytes
;
16306 gen_func
.movmemsi
= gen_movmemsi_6reg
;
16308 else if (TARGET_STRING
16309 && bytes
> 8 /* move up to 16 bytes at a time */
16313 && ! fixed_regs
[8])
16315 move_bytes
= (bytes
> 16) ? 16 : bytes
;
16316 gen_func
.movmemsi
= gen_movmemsi_4reg
;
16318 else if (bytes
>= 8 && TARGET_POWERPC64
16319 && (align
>= 64 || !STRICT_ALIGNMENT
))
16323 gen_func
.mov
= gen_movdi
;
16324 if (offset
== 0 && align
< 64)
16328 /* If the address form is reg+offset with offset not a
16329 multiple of four, reload into reg indirect form here
16330 rather than waiting for reload. This way we get one
16331 reload, not one per load and/or store. */
16332 addr
= XEXP (orig_dest
, 0);
16333 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16334 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16335 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16337 addr
= copy_addr_to_reg (addr
);
16338 orig_dest
= replace_equiv_address (orig_dest
, addr
);
16340 addr
= XEXP (orig_src
, 0);
16341 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16342 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16343 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16345 addr
= copy_addr_to_reg (addr
);
16346 orig_src
= replace_equiv_address (orig_src
, addr
);
16350 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
16351 { /* move up to 8 bytes at a time */
16352 move_bytes
= (bytes
> 8) ? 8 : bytes
;
16353 gen_func
.movmemsi
= gen_movmemsi_2reg
;
16355 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
16356 { /* move 4 bytes */
16359 gen_func
.mov
= gen_movsi
;
16361 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
16362 { /* move 2 bytes */
16365 gen_func
.mov
= gen_movhi
;
16367 else if (TARGET_STRING
&& bytes
> 1)
16368 { /* move up to 4 bytes at a time */
16369 move_bytes
= (bytes
> 4) ? 4 : bytes
;
16370 gen_func
.movmemsi
= gen_movmemsi_1reg
;
16372 else /* move 1 byte at a time */
16376 gen_func
.mov
= gen_movqi
;
16379 src
= adjust_address (orig_src
, mode
, offset
);
16380 dest
= adjust_address (orig_dest
, mode
, offset
);
16382 if (mode
!= BLKmode
)
16384 rtx tmp_reg
= gen_reg_rtx (mode
);
16386 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
16387 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
16390 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
16393 for (i
= 0; i
< num_reg
; i
++)
16394 emit_insn (stores
[i
]);
16398 if (mode
== BLKmode
)
16400 /* Move the address into scratch registers. The movmemsi
16401 patterns require zero offset. */
16402 if (!REG_P (XEXP (src
, 0)))
16404 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
16405 src
= replace_equiv_address (src
, src_reg
);
16407 set_mem_size (src
, move_bytes
);
16409 if (!REG_P (XEXP (dest
, 0)))
16411 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
16412 dest
= replace_equiv_address (dest
, dest_reg
);
16414 set_mem_size (dest
, move_bytes
);
16416 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
16417 GEN_INT (move_bytes
& 31),
16426 /* Return a string to perform a load_multiple operation.
16427 operands[0] is the vector.
16428 operands[1] is the source address.
16429 operands[2] is the first destination register. */
16432 rs6000_output_load_multiple (rtx operands
[3])
16434 /* We have to handle the case where the pseudo used to contain the address
16435 is assigned to one of the output registers. */
16437 int words
= XVECLEN (operands
[0], 0);
16440 if (XVECLEN (operands
[0], 0) == 1)
16441 return "lwz %2,0(%1)";
16443 for (i
= 0; i
< words
; i
++)
16444 if (refers_to_regno_p (REGNO (operands
[2]) + i
, operands
[1]))
16448 xop
[0] = GEN_INT (4 * (words
-1));
16449 xop
[1] = operands
[1];
16450 xop
[2] = operands
[2];
16451 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
16456 xop
[0] = GEN_INT (4 * (words
-1));
16457 xop
[1] = operands
[1];
16458 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
16459 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
16464 for (j
= 0; j
< words
; j
++)
16467 xop
[0] = GEN_INT (j
* 4);
16468 xop
[1] = operands
[1];
16469 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
16470 output_asm_insn ("lwz %2,%0(%1)", xop
);
16472 xop
[0] = GEN_INT (i
* 4);
16473 xop
[1] = operands
[1];
16474 output_asm_insn ("lwz %1,%0(%1)", xop
);
16479 return "lswi %2,%1,%N0";
16483 /* A validation routine: say whether CODE, a condition code, and MODE
16484 match. The other alternatives either don't make sense or should
16485 never be generated. */
16488 validate_condition_mode (enum rtx_code code
, machine_mode mode
)
16490 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
16491 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
16492 && GET_MODE_CLASS (mode
) == MODE_CC
);
16494 /* These don't make sense. */
16495 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
16496 || mode
!= CCUNSmode
);
16498 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
16499 || mode
== CCUNSmode
);
16501 gcc_assert (mode
== CCFPmode
16502 || (code
!= ORDERED
&& code
!= UNORDERED
16503 && code
!= UNEQ
&& code
!= LTGT
16504 && code
!= UNGT
&& code
!= UNLT
16505 && code
!= UNGE
&& code
!= UNLE
));
16507 /* These should never be generated except for
16508 flag_finite_math_only. */
16509 gcc_assert (mode
!= CCFPmode
16510 || flag_finite_math_only
16511 || (code
!= LE
&& code
!= GE
16512 && code
!= UNEQ
&& code
!= LTGT
16513 && code
!= UNGT
&& code
!= UNLT
));
16515 /* These are invalid; the information is not there. */
16516 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
16520 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
16521 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
16522 not zero, store there the bit offset (counted from the right) where
16523 the single stretch of 1 bits begins; and similarly for B, the bit
16524 offset where it ends. */
16527 rs6000_is_valid_mask (rtx mask
, int *b
, int *e
, machine_mode mode
)
16529 unsigned HOST_WIDE_INT val
= INTVAL (mask
);
16530 unsigned HOST_WIDE_INT bit
;
16532 int n
= GET_MODE_PRECISION (mode
);
16534 if (mode
!= DImode
&& mode
!= SImode
)
16537 if (INTVAL (mask
) >= 0)
16540 ne
= exact_log2 (bit
);
16541 nb
= exact_log2 (val
+ bit
);
16543 else if (val
+ 1 == 0)
16552 nb
= exact_log2 (bit
);
16553 ne
= exact_log2 (val
+ bit
);
16558 ne
= exact_log2 (bit
);
16559 if (val
+ bit
== 0)
16567 if (nb
< 0 || ne
< 0 || nb
>= n
|| ne
>= n
)
16578 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
16579 or rldicr instruction, to implement an AND with it in mode MODE. */
16582 rs6000_is_valid_and_mask (rtx mask
, machine_mode mode
)
16586 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
16589 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
16591 if (mode
== DImode
)
16592 return (ne
== 0 || nb
== 63 || (nb
< 32 && ne
<= nb
));
16594 /* For SImode, rlwinm can do everything. */
16595 if (mode
== SImode
)
16596 return (nb
< 32 && ne
< 32);
16601 /* Return the instruction template for an AND with mask in mode MODE, with
16602 operands OPERANDS. If DOT is true, make it a record-form instruction. */
16605 rs6000_insn_for_and_mask (machine_mode mode
, rtx
*operands
, bool dot
)
16609 if (!rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
))
16610 gcc_unreachable ();
16612 if (mode
== DImode
&& ne
== 0)
16614 operands
[3] = GEN_INT (63 - nb
);
16616 return "rldicl. %0,%1,0,%3";
16617 return "rldicl %0,%1,0,%3";
16620 if (mode
== DImode
&& nb
== 63)
16622 operands
[3] = GEN_INT (63 - ne
);
16624 return "rldicr. %0,%1,0,%3";
16625 return "rldicr %0,%1,0,%3";
16628 if (nb
< 32 && ne
< 32)
16630 operands
[3] = GEN_INT (31 - nb
);
16631 operands
[4] = GEN_INT (31 - ne
);
16633 return "rlwinm. %0,%1,0,%3,%4";
16634 return "rlwinm %0,%1,0,%3,%4";
16637 gcc_unreachable ();
16640 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
16641 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
16642 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
16645 rs6000_is_valid_shift_mask (rtx mask
, rtx shift
, machine_mode mode
)
16649 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
16652 int n
= GET_MODE_PRECISION (mode
);
16655 if (CONST_INT_P (XEXP (shift
, 1)))
16657 sh
= INTVAL (XEXP (shift
, 1));
16658 if (sh
< 0 || sh
>= n
)
16662 rtx_code code
= GET_CODE (shift
);
16664 /* Convert any shift by 0 to a rotate, to simplify below code. */
16668 /* Convert rotate to simple shift if we can, to make analysis simpler. */
16669 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
16671 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
16677 /* DImode rotates need rld*. */
16678 if (mode
== DImode
&& code
== ROTATE
)
16679 return (nb
== 63 || ne
== 0 || ne
== sh
);
16681 /* SImode rotates need rlw*. */
16682 if (mode
== SImode
&& code
== ROTATE
)
16683 return (nb
< 32 && ne
< 32 && sh
< 32);
16685 /* Wrap-around masks are only okay for rotates. */
16689 /* Variable shifts are only okay for rotates. */
16693 /* Don't allow ASHIFT if the mask is wrong for that. */
16694 if (code
== ASHIFT
&& ne
< sh
)
16697 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
16698 if the mask is wrong for that. */
16699 if (nb
< 32 && ne
< 32 && sh
< 32
16700 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
16703 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
16704 if the mask is wrong for that. */
16705 if (code
== LSHIFTRT
)
16707 if (nb
== 63 || ne
== 0 || ne
== sh
)
16708 return !(code
== LSHIFTRT
&& nb
>= sh
);
16713 /* Return the instruction template for a shift with mask in mode MODE, with
16714 operands OPERANDS. If DOT is true, make it a record-form instruction. */
16717 rs6000_insn_for_shift_mask (machine_mode mode
, rtx
*operands
, bool dot
)
16721 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
16722 gcc_unreachable ();
16724 if (mode
== DImode
&& ne
== 0)
16726 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
16727 operands
[2] = GEN_INT (64 - INTVAL (operands
[2]));
16728 operands
[3] = GEN_INT (63 - nb
);
16730 return "rld%I2cl. %0,%1,%2,%3";
16731 return "rld%I2cl %0,%1,%2,%3";
16734 if (mode
== DImode
&& nb
== 63)
16736 operands
[3] = GEN_INT (63 - ne
);
16738 return "rld%I2cr. %0,%1,%2,%3";
16739 return "rld%I2cr %0,%1,%2,%3";
16743 && GET_CODE (operands
[4]) != LSHIFTRT
16744 && CONST_INT_P (operands
[2])
16745 && ne
== INTVAL (operands
[2]))
16747 operands
[3] = GEN_INT (63 - nb
);
16749 return "rld%I2c. %0,%1,%2,%3";
16750 return "rld%I2c %0,%1,%2,%3";
16753 if (nb
< 32 && ne
< 32)
16755 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
16756 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
16757 operands
[3] = GEN_INT (31 - nb
);
16758 operands
[4] = GEN_INT (31 - ne
);
16760 return "rlw%I2nm. %0,%1,%2,%3,%4";
16761 return "rlw%I2nm %0,%1,%2,%3,%4";
16764 gcc_unreachable ();
16767 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
16768 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
16769 ASHIFT, or LSHIFTRT) in mode MODE. */
16772 rs6000_is_valid_insert_mask (rtx mask
, rtx shift
, machine_mode mode
)
16776 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
16779 int n
= GET_MODE_PRECISION (mode
);
16781 int sh
= INTVAL (XEXP (shift
, 1));
16782 if (sh
< 0 || sh
>= n
)
16785 rtx_code code
= GET_CODE (shift
);
16787 /* Convert any shift by 0 to a rotate, to simplify below code. */
16791 /* Convert rotate to simple shift if we can, to make analysis simpler. */
16792 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
16794 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
16800 /* DImode rotates need rldimi. */
16801 if (mode
== DImode
&& code
== ROTATE
)
16804 /* SImode rotates need rlwimi. */
16805 if (mode
== SImode
&& code
== ROTATE
)
16806 return (nb
< 32 && ne
< 32 && sh
< 32);
16808 /* Wrap-around masks are only okay for rotates. */
16812 /* Don't allow ASHIFT if the mask is wrong for that. */
16813 if (code
== ASHIFT
&& ne
< sh
)
16816 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
16817 if the mask is wrong for that. */
16818 if (nb
< 32 && ne
< 32 && sh
< 32
16819 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
16822 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
16823 if the mask is wrong for that. */
16824 if (code
== LSHIFTRT
)
16827 return !(code
== LSHIFTRT
&& nb
>= sh
);
16832 /* Return the instruction template for an insert with mask in mode MODE, with
16833 operands OPERANDS. If DOT is true, make it a record-form instruction. */
16836 rs6000_insn_for_insert_mask (machine_mode mode
, rtx
*operands
, bool dot
)
16840 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
16841 gcc_unreachable ();
16843 /* Prefer rldimi because rlwimi is cracked. */
16844 if (TARGET_POWERPC64
16845 && (!dot
|| mode
== DImode
)
16846 && GET_CODE (operands
[4]) != LSHIFTRT
16847 && ne
== INTVAL (operands
[2]))
16849 operands
[3] = GEN_INT (63 - nb
);
16851 return "rldimi. %0,%1,%2,%3";
16852 return "rldimi %0,%1,%2,%3";
16855 if (nb
< 32 && ne
< 32)
16857 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
16858 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
16859 operands
[3] = GEN_INT (31 - nb
);
16860 operands
[4] = GEN_INT (31 - ne
);
16862 return "rlwimi. %0,%1,%2,%3,%4";
16863 return "rlwimi %0,%1,%2,%3,%4";
16866 gcc_unreachable ();
16869 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
16870 using two machine instructions. */
16873 rs6000_is_valid_2insn_and (rtx c
, machine_mode mode
)
16875 /* There are two kinds of AND we can handle with two insns:
16876 1) those we can do with two rl* insn;
16879 We do not handle that last case yet. */
16881 /* If there is just one stretch of ones, we can do it. */
16882 if (rs6000_is_valid_mask (c
, NULL
, NULL
, mode
))
16885 /* Otherwise, fill in the lowest "hole"; if we can do the result with
16886 one insn, we can do the whole thing with two. */
16887 unsigned HOST_WIDE_INT val
= INTVAL (c
);
16888 unsigned HOST_WIDE_INT bit1
= val
& -val
;
16889 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
16890 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
16891 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
16892 return rs6000_is_valid_and_mask (GEN_INT (val
+ bit3
- bit2
), mode
);
16895 /* Emit a potentially record-form instruction, setting DST from SRC.
16896 If DOT is 0, that is all; otherwise, set CCREG to the result of the
16897 signed comparison of DST with zero. If DOT is 1, the generated RTL
16898 doesn't care about the DST result; if DOT is 2, it does. If CCREG
16899 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
16900 a separate COMPARE. */
16903 rs6000_emit_dot_insn (rtx dst
, rtx src
, int dot
, rtx ccreg
)
16907 emit_move_insn (dst
, src
);
16911 if (cc_reg_not_cr0_operand (ccreg
, CCmode
))
16913 emit_move_insn (dst
, src
);
16914 emit_move_insn (ccreg
, gen_rtx_COMPARE (CCmode
, dst
, const0_rtx
));
16918 rtx ccset
= gen_rtx_SET (ccreg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
));
16921 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, dst
);
16922 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, clobber
)));
16926 rtx set
= gen_rtx_SET (dst
, src
);
16927 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, set
)));
16931 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
16932 If EXPAND is true, split rotate-and-mask instructions we generate to
16933 their constituent parts as well (this is used during expand); if DOT
16934 is 1, make the last insn a record-form instruction clobbering the
16935 destination GPR and setting the CC reg (from operands[3]); if 2, set
16936 that GPR as well as the CC reg. */
16939 rs6000_emit_2insn_and (machine_mode mode
, rtx
*operands
, bool expand
, int dot
)
16941 gcc_assert (!(expand
&& dot
));
16943 unsigned HOST_WIDE_INT val
= INTVAL (operands
[2]);
16945 /* If it is one stretch of ones, it is DImode; shift left, mask, then
16946 shift right. This generates better code than doing the masks without
16947 shifts, or shifting first right and then left. */
16949 if (rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
) && nb
>= ne
)
16951 gcc_assert (mode
== DImode
);
16953 int shift
= 63 - nb
;
16956 rtx tmp1
= gen_reg_rtx (DImode
);
16957 rtx tmp2
= gen_reg_rtx (DImode
);
16958 emit_insn (gen_ashldi3 (tmp1
, operands
[1], GEN_INT (shift
)));
16959 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (val
<< shift
)));
16960 emit_insn (gen_lshrdi3 (operands
[0], tmp2
, GEN_INT (shift
)));
16964 rtx tmp
= gen_rtx_ASHIFT (mode
, operands
[1], GEN_INT (shift
));
16965 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (val
<< shift
));
16966 emit_move_insn (operands
[0], tmp
);
16967 tmp
= gen_rtx_LSHIFTRT (mode
, operands
[0], GEN_INT (shift
));
16968 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
16973 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
16974 that does the rest. */
16975 unsigned HOST_WIDE_INT bit1
= val
& -val
;
16976 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
16977 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
16978 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
16980 unsigned HOST_WIDE_INT mask1
= -bit3
+ bit2
- 1;
16981 unsigned HOST_WIDE_INT mask2
= val
+ bit3
- bit2
;
16983 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2
), mode
));
16985 /* Two "no-rotate"-and-mask instructions, for SImode. */
16986 if (rs6000_is_valid_and_mask (GEN_INT (mask1
), mode
))
16988 gcc_assert (mode
== SImode
);
16990 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
16991 rtx tmp
= gen_rtx_AND (mode
, operands
[1], GEN_INT (mask1
));
16992 emit_move_insn (reg
, tmp
);
16993 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
16994 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
16998 gcc_assert (mode
== DImode
);
17000 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
17001 insns; we have to do the first in SImode, because it wraps. */
17002 if (mask2
<= 0xffffffff
17003 && rs6000_is_valid_and_mask (GEN_INT (mask1
), SImode
))
17005 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
17006 rtx tmp
= gen_rtx_AND (SImode
, gen_lowpart (SImode
, operands
[1]),
17008 rtx reg_low
= gen_lowpart (SImode
, reg
);
17009 emit_move_insn (reg_low
, tmp
);
17010 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
17011 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
17015 /* Two rld* insns: rotate, clear the hole in the middle (which now is
17016 at the top end), rotate back and clear the other hole. */
17017 int right
= exact_log2 (bit3
);
17018 int left
= 64 - right
;
17020 /* Rotate the mask too. */
17021 mask1
= (mask1
>> right
) | ((bit2
- 1) << left
);
17025 rtx tmp1
= gen_reg_rtx (DImode
);
17026 rtx tmp2
= gen_reg_rtx (DImode
);
17027 rtx tmp3
= gen_reg_rtx (DImode
);
17028 emit_insn (gen_rotldi3 (tmp1
, operands
[1], GEN_INT (left
)));
17029 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (mask1
)));
17030 emit_insn (gen_rotldi3 (tmp3
, tmp2
, GEN_INT (right
)));
17031 emit_insn (gen_anddi3 (operands
[0], tmp3
, GEN_INT (mask2
)));
17035 rtx tmp
= gen_rtx_ROTATE (mode
, operands
[1], GEN_INT (left
));
17036 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask1
));
17037 emit_move_insn (operands
[0], tmp
);
17038 tmp
= gen_rtx_ROTATE (mode
, operands
[0], GEN_INT (right
));
17039 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask2
));
17040 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
17044 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
17045 for lfq and stfq insns iff the registers are hard registers. */
17048 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
17050 /* We might have been passed a SUBREG. */
17051 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
17054 /* We might have been passed non floating point registers. */
17055 if (!FP_REGNO_P (REGNO (reg1
))
17056 || !FP_REGNO_P (REGNO (reg2
)))
17059 return (REGNO (reg1
) == REGNO (reg2
) - 1);
17062 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
17063 addr1 and addr2 must be in consecutive memory locations
17064 (addr2 == addr1 + 8). */
17067 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
17070 unsigned int reg1
, reg2
;
17071 int offset1
, offset2
;
17073 /* The mems cannot be volatile. */
17074 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
17077 addr1
= XEXP (mem1
, 0);
17078 addr2
= XEXP (mem2
, 0);
17080 /* Extract an offset (if used) from the first addr. */
17081 if (GET_CODE (addr1
) == PLUS
)
17083 /* If not a REG, return zero. */
17084 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
17088 reg1
= REGNO (XEXP (addr1
, 0));
17089 /* The offset must be constant! */
17090 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
17092 offset1
= INTVAL (XEXP (addr1
, 1));
17095 else if (GET_CODE (addr1
) != REG
)
17099 reg1
= REGNO (addr1
);
17100 /* This was a simple (mem (reg)) expression. Offset is 0. */
17104 /* And now for the second addr. */
17105 if (GET_CODE (addr2
) == PLUS
)
17107 /* If not a REG, return zero. */
17108 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
17112 reg2
= REGNO (XEXP (addr2
, 0));
17113 /* The offset must be constant. */
17114 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
17116 offset2
= INTVAL (XEXP (addr2
, 1));
17119 else if (GET_CODE (addr2
) != REG
)
17123 reg2
= REGNO (addr2
);
17124 /* This was a simple (mem (reg)) expression. Offset is 0. */
17128 /* Both of these must have the same base register. */
17132 /* The offset for the second addr must be 8 more than the first addr. */
17133 if (offset2
!= offset1
+ 8)
17136 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
17143 rs6000_secondary_memory_needed_rtx (machine_mode mode
)
17145 static bool eliminated
= false;
17148 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
17149 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
17152 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
17153 gcc_assert (mem
!= NULL_RTX
);
17157 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
17158 cfun
->machine
->sdmode_stack_slot
= mem
;
17164 if (TARGET_DEBUG_ADDR
)
17166 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
17167 GET_MODE_NAME (mode
));
17169 fprintf (stderr
, "\tNULL_RTX\n");
17177 /* Return the mode to be used for memory when a secondary memory
17178 location is needed. For SDmode values we need to use DDmode, in
17179 all other cases we can use the same mode. */
17181 rs6000_secondary_memory_needed_mode (machine_mode mode
)
17183 if (lra_in_progress
&& mode
== SDmode
)
17189 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
17191 /* Don't walk into types. */
17192 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
17194 *walk_subtrees
= 0;
17198 switch (TREE_CODE (*tp
))
17207 case VIEW_CONVERT_EXPR
:
17208 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
17218 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
17219 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
17220 only work on the traditional altivec registers, note if an altivec register
17223 static enum rs6000_reg_type
17224 register_to_reg_type (rtx reg
, bool *is_altivec
)
17226 HOST_WIDE_INT regno
;
17227 enum reg_class rclass
;
17229 if (GET_CODE (reg
) == SUBREG
)
17230 reg
= SUBREG_REG (reg
);
17233 return NO_REG_TYPE
;
17235 regno
= REGNO (reg
);
17236 if (regno
>= FIRST_PSEUDO_REGISTER
)
17238 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
17239 return PSEUDO_REG_TYPE
;
17241 regno
= true_regnum (reg
);
17242 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
17243 return PSEUDO_REG_TYPE
;
17246 gcc_assert (regno
>= 0);
17248 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
17249 *is_altivec
= true;
17251 rclass
= rs6000_regno_regclass
[regno
];
17252 return reg_class_to_reg_type
[(int)rclass
];
17255 /* Helper function to return the cost of adding a TOC entry address. */
17258 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask
)
17262 if (TARGET_CMODEL
!= CMODEL_SMALL
)
17263 ret
= ((addr_mask
& RELOAD_REG_OFFSET
) == 0) ? 1 : 2;
17266 ret
= (TARGET_MINIMAL_TOC
) ? 6 : 3;
17271 /* Helper function for rs6000_secondary_reload to determine whether the memory
17272 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
17273 needs reloading. Return negative if the memory is not handled by the memory
17274 helper functions and to try a different reload method, 0 if no additional
17275 instructions are need, and positive to give the extra cost for the
17279 rs6000_secondary_reload_memory (rtx addr
,
17280 enum reg_class rclass
,
17283 int extra_cost
= 0;
17284 rtx reg
, and_arg
, plus_arg0
, plus_arg1
;
17285 addr_mask_type addr_mask
;
17286 const char *type
= NULL
;
17287 const char *fail_msg
= NULL
;
17289 if (GPR_REG_CLASS_P (rclass
))
17290 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
17292 else if (rclass
== FLOAT_REGS
)
17293 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
17295 else if (rclass
== ALTIVEC_REGS
)
17296 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
17298 /* For the combined VSX_REGS, turn off Altivec AND -16. */
17299 else if (rclass
== VSX_REGS
)
17300 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
]
17301 & ~RELOAD_REG_AND_M16
);
17305 if (TARGET_DEBUG_ADDR
)
17307 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
17308 "class is not GPR, FPR, VMX\n",
17309 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
17314 /* If the register isn't valid in this register class, just return now. */
17315 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
17317 if (TARGET_DEBUG_ADDR
)
17319 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
17320 "not valid in class\n",
17321 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
17326 switch (GET_CODE (addr
))
17328 /* Does the register class supports auto update forms for this mode? We
17329 don't need a scratch register, since the powerpc only supports
17330 PRE_INC, PRE_DEC, and PRE_MODIFY. */
17333 reg
= XEXP (addr
, 0);
17334 if (!base_reg_operand (addr
, GET_MODE (reg
)))
17336 fail_msg
= "no base register #1";
17340 else if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
17348 reg
= XEXP (addr
, 0);
17349 plus_arg1
= XEXP (addr
, 1);
17350 if (!base_reg_operand (reg
, GET_MODE (reg
))
17351 || GET_CODE (plus_arg1
) != PLUS
17352 || !rtx_equal_p (reg
, XEXP (plus_arg1
, 0)))
17354 fail_msg
= "bad PRE_MODIFY";
17358 else if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
17365 /* Do we need to simulate AND -16 to clear the bottom address bits used
17366 in VMX load/stores? Only allow the AND for vector sizes. */
17368 and_arg
= XEXP (addr
, 0);
17369 if (GET_MODE_SIZE (mode
) != 16
17370 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
17371 || INTVAL (XEXP (addr
, 1)) != -16)
17373 fail_msg
= "bad Altivec AND #1";
17377 if (rclass
!= ALTIVEC_REGS
)
17379 if (legitimate_indirect_address_p (and_arg
, false))
17382 else if (legitimate_indexed_address_p (and_arg
, false))
17387 fail_msg
= "bad Altivec AND #2";
17395 /* If this is an indirect address, make sure it is a base register. */
17398 if (!legitimate_indirect_address_p (addr
, false))
17405 /* If this is an indexed address, make sure the register class can handle
17406 indexed addresses for this mode. */
17408 plus_arg0
= XEXP (addr
, 0);
17409 plus_arg1
= XEXP (addr
, 1);
17411 /* (plus (plus (reg) (constant)) (constant)) is generated during
17412 push_reload processing, so handle it now. */
17413 if (GET_CODE (plus_arg0
) == PLUS
&& CONST_INT_P (plus_arg1
))
17415 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17422 /* (plus (plus (reg) (constant)) (reg)) is also generated during
17423 push_reload processing, so handle it now. */
17424 else if (GET_CODE (plus_arg0
) == PLUS
&& REG_P (plus_arg1
))
17426 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
17429 type
= "indexed #2";
17433 else if (!base_reg_operand (plus_arg0
, GET_MODE (plus_arg0
)))
17435 fail_msg
= "no base register #2";
17439 else if (int_reg_operand (plus_arg1
, GET_MODE (plus_arg1
)))
17441 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0
17442 || !legitimate_indexed_address_p (addr
, false))
17449 /* Make sure the register class can handle offset addresses. */
17450 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
17452 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17461 fail_msg
= "bad PLUS";
17468 if (!legitimate_lo_sum_address_p (mode
, addr
, false))
17470 fail_msg
= "bad LO_SUM";
17474 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17481 /* Static addresses need to create a TOC entry. */
17486 extra_cost
= rs6000_secondary_reload_toc_costs (addr_mask
);
17489 /* TOC references look like offsetable memory. */
17491 if (TARGET_CMODEL
== CMODEL_SMALL
|| XINT (addr
, 1) != UNSPEC_TOCREL
)
17493 fail_msg
= "bad UNSPEC";
17497 else if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17500 type
= "toc reference";
17506 fail_msg
= "bad address";
17511 if (TARGET_DEBUG_ADDR
/* && extra_cost != 0 */)
17513 if (extra_cost
< 0)
17515 "rs6000_secondary_reload_memory error: mode = %s, "
17516 "class = %s, addr_mask = '%s', %s\n",
17517 GET_MODE_NAME (mode
),
17518 reg_class_names
[rclass
],
17519 rs6000_debug_addr_mask (addr_mask
, false),
17520 (fail_msg
!= NULL
) ? fail_msg
: "<bad address>");
17524 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
17525 "addr_mask = '%s', extra cost = %d, %s\n",
17526 GET_MODE_NAME (mode
),
17527 reg_class_names
[rclass
],
17528 rs6000_debug_addr_mask (addr_mask
, false),
17530 (type
) ? type
: "<none>");
17538 /* Helper function for rs6000_secondary_reload to return true if a move to a
17539 different register classe is really a simple move. */
17542 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
17543 enum rs6000_reg_type from_type
,
17548 /* Add support for various direct moves available. In this function, we only
17549 look at cases where we don't need any extra registers, and one or more
17550 simple move insns are issued. At present, 32-bit integers are not allowed
17551 in FPR/VSX registers. Single precision binary floating is not a simple
17552 move because we need to convert to the single precision memory layout.
17553 The 4-byte SDmode can be moved. */
17554 size
= GET_MODE_SIZE (mode
);
17555 if (TARGET_DIRECT_MOVE
17556 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
17557 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
17558 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
17561 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
17562 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
17563 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
17566 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
17567 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
17568 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
17574 /* Power8 helper function for rs6000_secondary_reload, handle all of the
17575 special direct moves that involve allocating an extra register, return the
17576 insn code of the helper function if there is such a function or
17577 CODE_FOR_nothing if not. */
17580 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
17581 enum rs6000_reg_type from_type
,
17583 secondary_reload_info
*sri
,
17587 enum insn_code icode
= CODE_FOR_nothing
;
17589 int size
= GET_MODE_SIZE (mode
);
17591 if (TARGET_POWERPC64
)
17595 /* Handle moving 128-bit values from GPRs to VSX point registers on
17596 power8 when running in 64-bit mode using XXPERMDI to glue the two
17597 64-bit values back together. */
17598 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
17600 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
17601 icode
= reg_addr
[mode
].reload_vsx_gpr
;
17604 /* Handle moving 128-bit values from VSX point registers to GPRs on
17605 power8 when running in 64-bit mode using XXPERMDI to get access to the
17606 bottom 64-bit value. */
17607 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
17609 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
17610 icode
= reg_addr
[mode
].reload_gpr_vsx
;
17614 else if (mode
== SFmode
)
17616 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
17618 cost
= 3; /* xscvdpspn, mfvsrd, and. */
17619 icode
= reg_addr
[mode
].reload_gpr_vsx
;
17622 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
17624 cost
= 2; /* mtvsrz, xscvspdpn. */
17625 icode
= reg_addr
[mode
].reload_vsx_gpr
;
17630 if (TARGET_POWERPC64
&& size
== 16)
17632 /* Handle moving 128-bit values from GPRs to VSX point registers on
17633 power8 when running in 64-bit mode using XXPERMDI to glue the two
17634 64-bit values back together. */
17635 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
17637 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
17638 icode
= reg_addr
[mode
].reload_vsx_gpr
;
17641 /* Handle moving 128-bit values from VSX point registers to GPRs on
17642 power8 when running in 64-bit mode using XXPERMDI to get access to the
17643 bottom 64-bit value. */
17644 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
17646 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
17647 icode
= reg_addr
[mode
].reload_gpr_vsx
;
17651 else if (!TARGET_POWERPC64
&& size
== 8)
17653 /* Handle moving 64-bit values from GPRs to floating point registers on
17654 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
17655 values back together. Altivec register classes must be handled
17656 specially since a different instruction is used, and the secondary
17657 reload support requires a single instruction class in the scratch
17658 register constraint. However, right now TFmode is not allowed in
17659 Altivec registers, so the pattern will never match. */
17660 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
17662 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
17663 icode
= reg_addr
[mode
].reload_fpr_gpr
;
17667 if (icode
!= CODE_FOR_nothing
)
17672 sri
->icode
= icode
;
17673 sri
->extra_cost
= cost
;
17680 /* Return whether a move between two register classes can be done either
17681 directly (simple move) or via a pattern that uses a single extra temporary
17682 (using power8's direct move in this case. */
17685 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
17686 enum rs6000_reg_type from_type
,
17688 secondary_reload_info
*sri
,
17691 /* Fall back to load/store reloads if either type is not a register. */
17692 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
17695 /* If we haven't allocated registers yet, assume the move can be done for the
17696 standard register types. */
17697 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
17698 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
17699 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
17702 /* Moves to the same set of registers is a simple move for non-specialized
17704 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
17707 /* Check whether a simple move can be done directly. */
17708 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
17712 sri
->icode
= CODE_FOR_nothing
;
17713 sri
->extra_cost
= 0;
17718 /* Now check if we can do it in a few steps. */
17719 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
17723 /* Inform reload about cases where moving X with a mode MODE to a register in
17724 RCLASS requires an extra scratch or immediate register. Return the class
17725 needed for the immediate register.
17727 For VSX and Altivec, we may need a register to convert sp+offset into
17730 For misaligned 64-bit gpr loads and stores we need a register to
17731 convert an offset address to indirect. */
17734 rs6000_secondary_reload (bool in_p
,
17736 reg_class_t rclass_i
,
17738 secondary_reload_info
*sri
)
17740 enum reg_class rclass
= (enum reg_class
) rclass_i
;
17741 reg_class_t ret
= ALL_REGS
;
17742 enum insn_code icode
;
17743 bool default_p
= false;
17744 bool done_p
= false;
17746 /* Allow subreg of memory before/during reload. */
17747 bool memory_p
= (MEM_P (x
)
17748 || (!reload_completed
&& GET_CODE (x
) == SUBREG
17749 && MEM_P (SUBREG_REG (x
))));
17751 sri
->icode
= CODE_FOR_nothing
;
17752 sri
->extra_cost
= 0;
17754 ? reg_addr
[mode
].reload_load
17755 : reg_addr
[mode
].reload_store
);
17757 if (REG_P (x
) || register_operand (x
, mode
))
17759 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
17760 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
17761 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
17765 enum rs6000_reg_type exchange
= to_type
;
17766 to_type
= from_type
;
17767 from_type
= exchange
;
17770 /* Can we do a direct move of some sort? */
17771 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
17774 icode
= (enum insn_code
)sri
->icode
;
17781 /* Make sure 0.0 is not reloaded or forced into memory. */
17782 if (x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
17789 /* If this is a scalar floating point value and we want to load it into the
17790 traditional Altivec registers, do it via a move via a traditional floating
17791 point register. Also make sure that non-zero constants use a FPR. */
17792 if (!done_p
&& reg_addr
[mode
].scalar_in_vmx_p
17793 && (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
17794 && (memory_p
|| (GET_CODE (x
) == CONST_DOUBLE
)))
17801 /* Handle reload of load/stores if we have reload helper functions. */
17802 if (!done_p
&& icode
!= CODE_FOR_nothing
&& memory_p
)
17804 int extra_cost
= rs6000_secondary_reload_memory (XEXP (x
, 0), rclass
,
17807 if (extra_cost
>= 0)
17811 if (extra_cost
> 0)
17813 sri
->extra_cost
= extra_cost
;
17814 sri
->icode
= icode
;
17819 /* Handle unaligned loads and stores of integer registers. */
17820 if (!done_p
&& TARGET_POWERPC64
17821 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
17823 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
17825 rtx addr
= XEXP (x
, 0);
17826 rtx off
= address_offset (addr
);
17828 if (off
!= NULL_RTX
)
17830 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
17831 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
17833 /* We need a secondary reload when our legitimate_address_p
17834 says the address is good (as otherwise the entire address
17835 will be reloaded), and the offset is not a multiple of
17836 four or we have an address wrap. Address wrap will only
17837 occur for LO_SUMs since legitimate_offset_address_p
17838 rejects addresses for 16-byte mems that will wrap. */
17839 if (GET_CODE (addr
) == LO_SUM
17840 ? (1 /* legitimate_address_p allows any offset for lo_sum */
17841 && ((offset
& 3) != 0
17842 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
17843 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
17844 && (offset
& 3) != 0))
17846 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
17848 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_load
17849 : CODE_FOR_reload_di_load
);
17851 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_store
17852 : CODE_FOR_reload_di_store
);
17853 sri
->extra_cost
= 2;
17864 if (!done_p
&& !TARGET_POWERPC64
17865 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
17867 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
17869 rtx addr
= XEXP (x
, 0);
17870 rtx off
= address_offset (addr
);
17872 if (off
!= NULL_RTX
)
17874 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
17875 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
17877 /* We need a secondary reload when our legitimate_address_p
17878 says the address is good (as otherwise the entire address
17879 will be reloaded), and we have a wrap.
17881 legitimate_lo_sum_address_p allows LO_SUM addresses to
17882 have any offset so test for wrap in the low 16 bits.
17884 legitimate_offset_address_p checks for the range
17885 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
17886 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
17887 [0x7ff4,0x7fff] respectively, so test for the
17888 intersection of these ranges, [0x7ffc,0x7fff] and
17889 [0x7ff4,0x7ff7] respectively.
17891 Note that the address we see here may have been
17892 manipulated by legitimize_reload_address. */
17893 if (GET_CODE (addr
) == LO_SUM
17894 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
17895 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
17898 sri
->icode
= CODE_FOR_reload_si_load
;
17900 sri
->icode
= CODE_FOR_reload_si_store
;
17901 sri
->extra_cost
= 2;
17916 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
17918 gcc_assert (ret
!= ALL_REGS
);
17920 if (TARGET_DEBUG_ADDR
)
17923 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
17925 reg_class_names
[ret
],
17926 in_p
? "true" : "false",
17927 reg_class_names
[rclass
],
17928 GET_MODE_NAME (mode
));
17930 if (reload_completed
)
17931 fputs (", after reload", stderr
);
17934 fputs (", done_p not set", stderr
);
17937 fputs (", default secondary reload", stderr
);
17939 if (sri
->icode
!= CODE_FOR_nothing
)
17940 fprintf (stderr
, ", reload func = %s, extra cost = %d",
17941 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
17943 fputs ("\n", stderr
);
17950 /* Better tracing for rs6000_secondary_reload_inner. */
17953 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
17958 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
17960 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
17961 store_p
? "store" : "load");
17964 set
= gen_rtx_SET (mem
, reg
);
17966 set
= gen_rtx_SET (reg
, mem
);
17968 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
17969 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
17972 static void rs6000_secondary_reload_fail (int, rtx
, rtx
, rtx
, bool)
17973 ATTRIBUTE_NORETURN
;
17976 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
17979 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
17980 gcc_unreachable ();
17983 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
17984 reload helper functions. These were identified in
17985 rs6000_secondary_reload_memory, and if reload decided to use the secondary
17986 reload, it calls the insns:
17987 reload_<RELOAD:mode>_<P:mptrsize>_store
17988 reload_<RELOAD:mode>_<P:mptrsize>_load
17990 which in turn calls this function, to do whatever is necessary to create
17991 valid addresses. */
17994 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
17996 int regno
= true_regnum (reg
);
17997 machine_mode mode
= GET_MODE (reg
);
17998 addr_mask_type addr_mask
;
18001 rtx op_reg
, op0
, op1
;
18006 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
|| !MEM_P (mem
)
18007 || !base_reg_operand (scratch
, GET_MODE (scratch
)))
18008 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18010 if (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
))
18011 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
18013 else if (IN_RANGE (regno
, FIRST_FPR_REGNO
, LAST_FPR_REGNO
))
18014 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
18016 else if (IN_RANGE (regno
, FIRST_ALTIVEC_REGNO
, LAST_ALTIVEC_REGNO
))
18017 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
18020 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18022 /* Make sure the mode is valid in this register class. */
18023 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
18024 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18026 if (TARGET_DEBUG_ADDR
)
18027 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
18029 new_addr
= addr
= XEXP (mem
, 0);
18030 switch (GET_CODE (addr
))
18032 /* Does the register class support auto update forms for this mode? If
18033 not, do the update now. We don't need a scratch register, since the
18034 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
18037 op_reg
= XEXP (addr
, 0);
18038 if (!base_reg_operand (op_reg
, Pmode
))
18039 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18041 if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
18043 emit_insn (gen_add2_insn (op_reg
, GEN_INT (GET_MODE_SIZE (mode
))));
18049 op0
= XEXP (addr
, 0);
18050 op1
= XEXP (addr
, 1);
18051 if (!base_reg_operand (op0
, Pmode
)
18052 || GET_CODE (op1
) != PLUS
18053 || !rtx_equal_p (op0
, XEXP (op1
, 0)))
18054 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18056 if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
18058 emit_insn (gen_rtx_SET (op0
, op1
));
18063 /* Do we need to simulate AND -16 to clear the bottom address bits used
18064 in VMX load/stores? */
18066 op0
= XEXP (addr
, 0);
18067 op1
= XEXP (addr
, 1);
18068 if ((addr_mask
& RELOAD_REG_AND_M16
) == 0)
18070 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
18073 else if (GET_CODE (op1
) == PLUS
)
18075 emit_insn (gen_rtx_SET (scratch
, op1
));
18080 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18082 and_op
= gen_rtx_AND (GET_MODE (scratch
), op_reg
, op1
);
18083 cc_clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
18084 rv
= gen_rtvec (2, gen_rtx_SET (scratch
, and_op
), cc_clobber
);
18085 emit_insn (gen_rtx_PARALLEL (VOIDmode
, rv
));
18086 new_addr
= scratch
;
18090 /* If this is an indirect address, make sure it is a base register. */
18093 if (!base_reg_operand (addr
, GET_MODE (addr
)))
18095 emit_insn (gen_rtx_SET (scratch
, addr
));
18096 new_addr
= scratch
;
18100 /* If this is an indexed address, make sure the register class can handle
18101 indexed addresses for this mode. */
18103 op0
= XEXP (addr
, 0);
18104 op1
= XEXP (addr
, 1);
18105 if (!base_reg_operand (op0
, Pmode
))
18106 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18108 else if (int_reg_operand (op1
, Pmode
))
18110 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
18112 emit_insn (gen_rtx_SET (scratch
, addr
));
18113 new_addr
= scratch
;
18117 /* Make sure the register class can handle offset addresses. */
18118 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
18120 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
18122 emit_insn (gen_rtx_SET (scratch
, addr
));
18123 new_addr
= scratch
;
18128 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18133 op0
= XEXP (addr
, 0);
18134 op1
= XEXP (addr
, 1);
18135 if (!base_reg_operand (op0
, Pmode
))
18136 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18138 else if (int_reg_operand (op1
, Pmode
))
18140 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
18142 emit_insn (gen_rtx_SET (scratch
, addr
));
18143 new_addr
= scratch
;
18147 /* Make sure the register class can handle offset addresses. */
18148 else if (legitimate_lo_sum_address_p (mode
, addr
, false))
18150 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
18152 emit_insn (gen_rtx_SET (scratch
, addr
));
18153 new_addr
= scratch
;
18158 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18165 rs6000_emit_move (scratch
, addr
, Pmode
);
18166 new_addr
= scratch
;
18170 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
18173 /* Adjust the address if it changed. */
18174 if (addr
!= new_addr
)
18176 mem
= replace_equiv_address_nv (mem
, new_addr
);
18177 if (TARGET_DEBUG_ADDR
)
18178 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
18181 /* Now create the move. */
18183 emit_insn (gen_rtx_SET (mem
, reg
));
18185 emit_insn (gen_rtx_SET (reg
, mem
));
18190 /* Convert reloads involving 64-bit gprs and misaligned offset
18191 addressing, or multiple 32-bit gprs and offsets that are too large,
18192 to use indirect addressing. */
18195 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
18197 int regno
= true_regnum (reg
);
18198 enum reg_class rclass
;
18200 rtx scratch_or_premodify
= scratch
;
18202 if (TARGET_DEBUG_ADDR
)
18204 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
18205 store_p
? "store" : "load");
18206 fprintf (stderr
, "reg:\n");
18208 fprintf (stderr
, "mem:\n");
18210 fprintf (stderr
, "scratch:\n");
18211 debug_rtx (scratch
);
18214 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
18215 gcc_assert (GET_CODE (mem
) == MEM
);
18216 rclass
= REGNO_REG_CLASS (regno
);
18217 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
18218 addr
= XEXP (mem
, 0);
18220 if (GET_CODE (addr
) == PRE_MODIFY
)
18222 gcc_assert (REG_P (XEXP (addr
, 0))
18223 && GET_CODE (XEXP (addr
, 1)) == PLUS
18224 && XEXP (XEXP (addr
, 1), 0) == XEXP (addr
, 0));
18225 scratch_or_premodify
= XEXP (addr
, 0);
18226 if (!HARD_REGISTER_P (scratch_or_premodify
))
18227 /* If we have a pseudo here then reload will have arranged
18228 to have it replaced, but only in the original insn.
18229 Use the replacement here too. */
18230 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
18232 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
18233 expressions from the original insn, without unsharing them.
18234 Any RTL that points into the original insn will of course
18235 have register replacements applied. That is why we don't
18236 need to look for replacements under the PLUS. */
18237 addr
= XEXP (addr
, 1);
18239 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
18241 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
18243 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
18245 /* Now create the move. */
18247 emit_insn (gen_rtx_SET (mem
, reg
));
18249 emit_insn (gen_rtx_SET (reg
, mem
));
18254 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
18255 this function has any SDmode references. If we are on a power7 or later, we
18256 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
18257 can load/store the value. */
18260 rs6000_alloc_sdmode_stack_slot (void)
18264 gimple_stmt_iterator gsi
;
18266 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
18267 /* We use a different approach for dealing with the secondary
18272 if (TARGET_NO_SDMODE_STACK
)
18275 FOR_EACH_BB_FN (bb
, cfun
)
18276 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
18278 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
18281 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
18282 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
18288 /* Check for any SDmode parameters of the function. */
18289 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
18291 if (TREE_TYPE (t
) == error_mark_node
)
18294 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
18295 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
18297 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
18298 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
18306 rs6000_instantiate_decls (void)
18308 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
18309 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
18312 /* Given an rtx X being reloaded into a reg required to be
18313 in class CLASS, return the class of reg to actually use.
18314 In general this is just CLASS; but on some machines
18315 in some cases it is preferable to use a more restrictive class.
18317 On the RS/6000, we have to return NO_REGS when we want to reload a
18318 floating-point CONST_DOUBLE to force it to be copied to memory.
18320 We also don't want to reload integer values into floating-point
18321 registers if we can at all help it. In fact, this can
18322 cause reload to die, if it tries to generate a reload of CTR
18323 into a FP register and discovers it doesn't have the memory location
18326 ??? Would it be a good idea to have reload do the converse, that is
18327 try to reload floating modes into FP registers if possible?
18330 static enum reg_class
18331 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
18333 machine_mode mode
= GET_MODE (x
);
18334 bool is_constant
= CONSTANT_P (x
);
18336 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
18337 the reloading of address expressions using PLUS into floating point
18339 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
) && GET_CODE (x
) != PLUS
)
18343 /* Zero is always allowed in all VSX registers. */
18344 if (x
== CONST0_RTX (mode
))
18347 /* If this is a vector constant that can be formed with a few Altivec
18348 instructions, we want altivec registers. */
18349 if (GET_CODE (x
) == CONST_VECTOR
&& easy_vector_constant (x
, mode
))
18350 return ALTIVEC_REGS
;
18352 /* Force constant to memory. */
18356 /* If this is a scalar floating point value, prefer the traditional
18357 floating point registers so that we can use D-form (register+offset)
18359 if (GET_MODE_SIZE (mode
) < 16)
18362 /* Prefer the Altivec registers if Altivec is handling the vector
18363 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
18365 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
18366 || mode
== V1TImode
)
18367 return ALTIVEC_REGS
;
18372 if (is_constant
|| GET_CODE (x
) == PLUS
)
18374 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
18375 return GENERAL_REGS
;
18376 if (reg_class_subset_p (BASE_REGS
, rclass
))
18381 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
18382 return GENERAL_REGS
;
18387 /* Debug version of rs6000_preferred_reload_class. */
18388 static enum reg_class
18389 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
18391 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
18394 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
18396 reg_class_names
[ret
], reg_class_names
[rclass
],
18397 GET_MODE_NAME (GET_MODE (x
)));
18403 /* If we are copying between FP or AltiVec registers and anything else, we need
18404 a memory location. The exception is when we are targeting ppc64 and the
18405 move to/from fpr to gpr instructions are available. Also, under VSX, you
18406 can copy vector registers from the FP register set to the Altivec register
18407 set and vice versa. */
18410 rs6000_secondary_memory_needed (enum reg_class from_class
,
18411 enum reg_class to_class
,
18414 enum rs6000_reg_type from_type
, to_type
;
18415 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
18416 || (to_class
== ALTIVEC_REGS
));
18418 /* If a simple/direct move is available, we don't need secondary memory */
18419 from_type
= reg_class_to_reg_type
[(int)from_class
];
18420 to_type
= reg_class_to_reg_type
[(int)to_class
];
18422 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
18423 (secondary_reload_info
*)0, altivec_p
))
18426 /* If we have a floating point or vector register class, we need to use
18427 memory to transfer the data. */
18428 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
18434 /* Debug version of rs6000_secondary_memory_needed. */
18436 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
18437 enum reg_class to_class
,
18440 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
18443 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
18444 "to_class = %s, mode = %s\n",
18445 ret
? "true" : "false",
18446 reg_class_names
[from_class
],
18447 reg_class_names
[to_class
],
18448 GET_MODE_NAME (mode
));
18453 /* Return the register class of a scratch register needed to copy IN into
18454 or out of a register in RCLASS in MODE. If it can be done directly,
18455 NO_REGS is returned. */
18457 static enum reg_class
18458 rs6000_secondary_reload_class (enum reg_class rclass
, machine_mode mode
,
18463 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
18465 && MACHOPIC_INDIRECT
18469 /* We cannot copy a symbolic operand directly into anything
18470 other than BASE_REGS for TARGET_ELF. So indicate that a
18471 register from BASE_REGS is needed as an intermediate
18474 On Darwin, pic addresses require a load from memory, which
18475 needs a base register. */
18476 if (rclass
!= BASE_REGS
18477 && (GET_CODE (in
) == SYMBOL_REF
18478 || GET_CODE (in
) == HIGH
18479 || GET_CODE (in
) == LABEL_REF
18480 || GET_CODE (in
) == CONST
))
18484 if (GET_CODE (in
) == REG
)
18486 regno
= REGNO (in
);
18487 if (regno
>= FIRST_PSEUDO_REGISTER
)
18489 regno
= true_regnum (in
);
18490 if (regno
>= FIRST_PSEUDO_REGISTER
)
18494 else if (GET_CODE (in
) == SUBREG
)
18496 regno
= true_regnum (in
);
18497 if (regno
>= FIRST_PSEUDO_REGISTER
)
18503 /* If we have VSX register moves, prefer moving scalar values between
18504 Altivec registers and GPR by going via an FPR (and then via memory)
18505 instead of reloading the secondary memory address for Altivec moves. */
18507 && GET_MODE_SIZE (mode
) < 16
18508 && (((rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
18509 && (regno
>= 0 && ALTIVEC_REGNO_P (regno
)))
18510 || ((rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
18511 && (regno
>= 0 && INT_REGNO_P (regno
)))))
18514 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
18516 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
18517 || (regno
>= 0 && INT_REGNO_P (regno
)))
18520 /* Constants, memory, and VSX registers can go into VSX registers (both the
18521 traditional floating point and the altivec registers). */
18522 if (rclass
== VSX_REGS
18523 && (regno
== -1 || VSX_REGNO_P (regno
)))
18526 /* Constants, memory, and FP registers can go into FP registers. */
18527 if ((regno
== -1 || FP_REGNO_P (regno
))
18528 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
18529 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
18531 /* Memory, and AltiVec registers can go into AltiVec registers. */
18532 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
18533 && rclass
== ALTIVEC_REGS
)
18536 /* We can copy among the CR registers. */
18537 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
18538 && regno
>= 0 && CR_REGNO_P (regno
))
18541 /* Otherwise, we need GENERAL_REGS. */
18542 return GENERAL_REGS
;
18545 /* Debug version of rs6000_secondary_reload_class. */
18546 static enum reg_class
18547 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
18548 machine_mode mode
, rtx in
)
18550 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
18552 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
18553 "mode = %s, input rtx:\n",
18554 reg_class_names
[ret
], reg_class_names
[rclass
],
18555 GET_MODE_NAME (mode
));
18561 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
18564 rs6000_cannot_change_mode_class (machine_mode from
,
18566 enum reg_class rclass
)
18568 unsigned from_size
= GET_MODE_SIZE (from
);
18569 unsigned to_size
= GET_MODE_SIZE (to
);
18571 if (from_size
!= to_size
)
18573 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
18575 if (reg_classes_intersect_p (xclass
, rclass
))
18577 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
18578 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
18579 bool to_float128_vector_p
= FLOAT128_VECTOR_P (to
);
18580 bool from_float128_vector_p
= FLOAT128_VECTOR_P (from
);
18582 /* Don't allow 64-bit types to overlap with 128-bit types that take a
18583 single register under VSX because the scalar part of the register
18584 is in the upper 64-bits, and not the lower 64-bits. Types like
18585 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
18586 IEEE floating point can't overlap, and neither can small
18589 if (to_float128_vector_p
&& from_float128_vector_p
)
18592 else if (to_float128_vector_p
|| from_float128_vector_p
)
18595 /* TDmode in floating-mode registers must always go into a register
18596 pair with the most significant word in the even-numbered register
18597 to match ISA requirements. In little-endian mode, this does not
18598 match subreg numbering, so we cannot allow subregs. */
18599 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
18602 if (from_size
< 8 || to_size
< 8)
18605 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
18608 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
18617 if (TARGET_E500_DOUBLE
18618 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
18619 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
18620 || (((to
) == IFmode
) + ((from
) == IFmode
)) == 1
18621 || (((to
) == KFmode
) + ((from
) == KFmode
)) == 1
18622 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
18623 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
18624 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
18627 /* Since the VSX register set includes traditional floating point registers
18628 and altivec registers, just check for the size being different instead of
18629 trying to check whether the modes are vector modes. Otherwise it won't
18630 allow say DF and DI to change classes. For types like TFmode and TDmode
18631 that take 2 64-bit registers, rather than a single 128-bit register, don't
18632 allow subregs of those types to other 128 bit types. */
18633 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
18635 unsigned num_regs
= (from_size
+ 15) / 16;
18636 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
18637 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
18640 return (from_size
!= 8 && from_size
!= 16);
18643 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
18644 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
18647 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
18648 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
18654 /* Debug version of rs6000_cannot_change_mode_class. */
18656 rs6000_debug_cannot_change_mode_class (machine_mode from
,
18658 enum reg_class rclass
)
18660 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
18663 "rs6000_cannot_change_mode_class, return %s, from = %s, "
18664 "to = %s, rclass = %s\n",
18665 ret
? "true" : "false",
18666 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
18667 reg_class_names
[rclass
]);
18672 /* Return a string to do a move operation of 128 bits of data. */
18675 rs6000_output_move_128bit (rtx operands
[])
18677 rtx dest
= operands
[0];
18678 rtx src
= operands
[1];
18679 machine_mode mode
= GET_MODE (dest
);
18682 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
18683 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
18687 dest_regno
= REGNO (dest
);
18688 dest_gpr_p
= INT_REGNO_P (dest_regno
);
18689 dest_fp_p
= FP_REGNO_P (dest_regno
);
18690 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
18691 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
18696 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
18701 src_regno
= REGNO (src
);
18702 src_gpr_p
= INT_REGNO_P (src_regno
);
18703 src_fp_p
= FP_REGNO_P (src_regno
);
18704 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
18705 src_vsx_p
= src_fp_p
| src_vmx_p
;
18710 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
18713 /* Register moves. */
18714 if (dest_regno
>= 0 && src_regno
>= 0)
18721 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
18725 else if (TARGET_VSX
&& dest_vsx_p
)
18728 return "xxlor %x0,%x1,%x1";
18730 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
18734 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
18735 return "vor %0,%1,%1";
18737 else if (dest_fp_p
&& src_fp_p
)
18742 else if (dest_regno
>= 0 && MEM_P (src
))
18746 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
18752 else if (TARGET_ALTIVEC
&& dest_vmx_p
18753 && altivec_indexed_or_indirect_operand (src
, mode
))
18754 return "lvx %0,%y1";
18756 else if (TARGET_VSX
&& dest_vsx_p
)
18758 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
18759 return "lxvw4x %x0,%y1";
18761 return "lxvd2x %x0,%y1";
18764 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
18765 return "lvx %0,%y1";
18767 else if (dest_fp_p
)
18772 else if (src_regno
>= 0 && MEM_P (dest
))
18776 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
18777 return "stq %1,%0";
18782 else if (TARGET_ALTIVEC
&& src_vmx_p
18783 && altivec_indexed_or_indirect_operand (src
, mode
))
18784 return "stvx %1,%y0";
18786 else if (TARGET_VSX
&& src_vsx_p
)
18788 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
18789 return "stxvw4x %x1,%y0";
18791 return "stxvd2x %x1,%y0";
18794 else if (TARGET_ALTIVEC
&& src_vmx_p
)
18795 return "stvx %1,%y0";
18802 else if (dest_regno
>= 0
18803 && (GET_CODE (src
) == CONST_INT
18804 || GET_CODE (src
) == CONST_WIDE_INT
18805 || GET_CODE (src
) == CONST_DOUBLE
18806 || GET_CODE (src
) == CONST_VECTOR
))
18811 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
18812 return "xxlxor %x0,%x0,%x0";
18814 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
18815 return output_vec_const_move (operands
);
18818 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest
, src
));
18821 /* Validate a 128-bit move. */
18823 rs6000_move_128bit_ok_p (rtx operands
[])
18825 machine_mode mode
= GET_MODE (operands
[0]);
18826 return (gpc_reg_operand (operands
[0], mode
)
18827 || gpc_reg_operand (operands
[1], mode
));
18830 /* Return true if a 128-bit move needs to be split. */
18832 rs6000_split_128bit_ok_p (rtx operands
[])
18834 if (!reload_completed
)
18837 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
18840 if (quad_load_store_p (operands
[0], operands
[1]))
18847 /* Given a comparison operation, return the bit number in CCR to test. We
18848 know this is a valid comparison.
18850 SCC_P is 1 if this is for an scc. That means that %D will have been
18851 used instead of %C, so the bits will be in different places.
18853 Return -1 if OP isn't a valid comparison for some reason. */
18856 ccr_bit (rtx op
, int scc_p
)
18858 enum rtx_code code
= GET_CODE (op
);
18859 machine_mode cc_mode
;
18864 if (!COMPARISON_P (op
))
18867 reg
= XEXP (op
, 0);
18869 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
18871 cc_mode
= GET_MODE (reg
);
18872 cc_regnum
= REGNO (reg
);
18873 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
18875 validate_condition_mode (code
, cc_mode
);
18877 /* When generating a sCOND operation, only positive conditions are
18880 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
18881 || code
== GTU
|| code
== LTU
);
18886 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
18888 return base_bit
+ 2;
18889 case GT
: case GTU
: case UNLE
:
18890 return base_bit
+ 1;
18891 case LT
: case LTU
: case UNGE
:
18893 case ORDERED
: case UNORDERED
:
18894 return base_bit
+ 3;
18897 /* If scc, we will have done a cror to put the bit in the
18898 unordered position. So test that bit. For integer, this is ! LT
18899 unless this is an scc insn. */
18900 return scc_p
? base_bit
+ 3 : base_bit
;
18903 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
18906 gcc_unreachable ();
18910 /* Return the GOT register. */
18913 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
18915 /* The second flow pass currently (June 1999) can't update
18916 regs_ever_live without disturbing other parts of the compiler, so
18917 update it here to make the prolog/epilogue code happy. */
18918 if (!can_create_pseudo_p ()
18919 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
18920 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
18922 crtl
->uses_pic_offset_table
= 1;
18924 return pic_offset_table_rtx
;
18927 static rs6000_stack_t stack_info
;
18929 /* Function to init struct machine_function.
18930 This will be called, via a pointer variable,
18931 from push_function_context. */
18933 static struct machine_function
*
18934 rs6000_init_machine_status (void)
18936 stack_info
.reload_completed
= 0;
18937 return ggc_cleared_alloc
<machine_function
> ();
18940 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
18942 /* Write out a function code label. */
18945 rs6000_output_function_entry (FILE *file
, const char *fname
)
18947 if (fname
[0] != '.')
18949 switch (DEFAULT_ABI
)
18952 gcc_unreachable ();
18958 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
18968 RS6000_OUTPUT_BASENAME (file
, fname
);
18971 /* Print an operand. Recognize special options, documented below. */
18974 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
18975 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
18977 #define SMALL_DATA_RELOC "sda21"
18978 #define SMALL_DATA_REG 0
18982 print_operand (FILE *file
, rtx x
, int code
)
18985 unsigned HOST_WIDE_INT uval
;
18989 /* %a is output_address. */
18991 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
18995 /* Like 'J' but get to the GT bit only. */
18996 gcc_assert (REG_P (x
));
18998 /* Bit 1 is GT bit. */
18999 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
19001 /* Add one for shift count in rlinm for scc. */
19002 fprintf (file
, "%d", i
+ 1);
19006 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
19009 output_operand_lossage ("invalid %%e value");
19014 if ((uval
& 0xffff) == 0 && uval
!= 0)
19019 /* X is a CR register. Print the number of the EQ bit of the CR */
19020 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
19021 output_operand_lossage ("invalid %%E value");
19023 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
19027 /* X is a CR register. Print the shift count needed to move it
19028 to the high-order four bits. */
19029 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
19030 output_operand_lossage ("invalid %%f value");
19032 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
19036 /* Similar, but print the count for the rotate in the opposite
19038 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
19039 output_operand_lossage ("invalid %%F value");
19041 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
19045 /* X is a constant integer. If it is negative, print "m",
19046 otherwise print "z". This is to make an aze or ame insn. */
19047 if (GET_CODE (x
) != CONST_INT
)
19048 output_operand_lossage ("invalid %%G value");
19049 else if (INTVAL (x
) >= 0)
19056 /* If constant, output low-order five bits. Otherwise, write
19059 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
19061 print_operand (file
, x
, 0);
19065 /* If constant, output low-order six bits. Otherwise, write
19068 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
19070 print_operand (file
, x
, 0);
19074 /* Print `i' if this is a constant, else nothing. */
19080 /* Write the bit number in CCR for jump. */
19081 i
= ccr_bit (x
, 0);
19083 output_operand_lossage ("invalid %%j code");
19085 fprintf (file
, "%d", i
);
19089 /* Similar, but add one for shift count in rlinm for scc and pass
19090 scc flag to `ccr_bit'. */
19091 i
= ccr_bit (x
, 1);
19093 output_operand_lossage ("invalid %%J code");
19095 /* If we want bit 31, write a shift count of zero, not 32. */
19096 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
19100 /* X must be a constant. Write the 1's complement of the
19103 output_operand_lossage ("invalid %%k value");
19105 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
19109 /* X must be a symbolic constant on ELF. Write an
19110 expression suitable for an 'addi' that adds in the low 16
19111 bits of the MEM. */
19112 if (GET_CODE (x
) == CONST
)
19114 if (GET_CODE (XEXP (x
, 0)) != PLUS
19115 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
19116 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
19117 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
19118 output_operand_lossage ("invalid %%K value");
19120 print_operand_address (file
, x
);
19121 fputs ("@l", file
);
19124 /* %l is output_asm_label. */
19127 /* Write second word of DImode or DFmode reference. Works on register
19128 or non-indexed memory only. */
19130 fputs (reg_names
[REGNO (x
) + 1], file
);
19131 else if (MEM_P (x
))
19133 /* Handle possible auto-increment. Since it is pre-increment and
19134 we have already done it, we can just use an offset of word. */
19135 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
19136 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19137 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
19139 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19140 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
19143 output_address (XEXP (adjust_address_nv (x
, SImode
,
19147 if (small_data_operand (x
, GET_MODE (x
)))
19148 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19149 reg_names
[SMALL_DATA_REG
]);
19154 /* Write the number of elements in the vector times 4. */
19155 if (GET_CODE (x
) != PARALLEL
)
19156 output_operand_lossage ("invalid %%N value");
19158 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
19162 /* Similar, but subtract 1 first. */
19163 if (GET_CODE (x
) != PARALLEL
)
19164 output_operand_lossage ("invalid %%O value");
19166 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
19170 /* X is a CONST_INT that is a power of two. Output the logarithm. */
19173 || (i
= exact_log2 (INTVAL (x
))) < 0)
19174 output_operand_lossage ("invalid %%p value");
19176 fprintf (file
, "%d", i
);
19180 /* The operand must be an indirect memory reference. The result
19181 is the register name. */
19182 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
19183 || REGNO (XEXP (x
, 0)) >= 32)
19184 output_operand_lossage ("invalid %%P value");
19186 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
19190 /* This outputs the logical code corresponding to a boolean
19191 expression. The expression may have one or both operands
19192 negated (if one, only the first one). For condition register
19193 logical operations, it will also treat the negated
19194 CR codes as NOTs, but not handle NOTs of them. */
19196 const char *const *t
= 0;
19198 enum rtx_code code
= GET_CODE (x
);
19199 static const char * const tbl
[3][3] = {
19200 { "and", "andc", "nor" },
19201 { "or", "orc", "nand" },
19202 { "xor", "eqv", "xor" } };
19206 else if (code
== IOR
)
19208 else if (code
== XOR
)
19211 output_operand_lossage ("invalid %%q value");
19213 if (GET_CODE (XEXP (x
, 0)) != NOT
)
19217 if (GET_CODE (XEXP (x
, 1)) == NOT
)
19228 if (! TARGET_MFCRF
)
19234 /* X is a CR register. Print the mask for `mtcrf'. */
19235 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
19236 output_operand_lossage ("invalid %%R value");
19238 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
19242 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
19243 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
19245 /* Bit 3 is OV bit. */
19246 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
19248 /* If we want bit 31, write a shift count of zero, not 32. */
19249 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
19253 /* Print the symbolic name of a branch target register. */
19254 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
19255 && REGNO (x
) != CTR_REGNO
))
19256 output_operand_lossage ("invalid %%T value");
19257 else if (REGNO (x
) == LR_REGNO
)
19258 fputs ("lr", file
);
19260 fputs ("ctr", file
);
19264 /* High-order or low-order 16 bits of constant, whichever is non-zero,
19265 for use in unsigned operand. */
19268 output_operand_lossage ("invalid %%u value");
19273 if ((uval
& 0xffff) == 0)
19276 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
19280 /* High-order 16 bits of constant for use in signed operand. */
19282 output_operand_lossage ("invalid %%v value");
19284 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
19285 (INTVAL (x
) >> 16) & 0xffff);
19289 /* Print `u' if this has an auto-increment or auto-decrement. */
19291 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
19292 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
19293 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
19298 /* Print the trap code for this operand. */
19299 switch (GET_CODE (x
))
19302 fputs ("eq", file
); /* 4 */
19305 fputs ("ne", file
); /* 24 */
19308 fputs ("lt", file
); /* 16 */
19311 fputs ("le", file
); /* 20 */
19314 fputs ("gt", file
); /* 8 */
19317 fputs ("ge", file
); /* 12 */
19320 fputs ("llt", file
); /* 2 */
19323 fputs ("lle", file
); /* 6 */
19326 fputs ("lgt", file
); /* 1 */
19329 fputs ("lge", file
); /* 5 */
19332 gcc_unreachable ();
19337 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
19340 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
19341 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
19343 print_operand (file
, x
, 0);
19347 /* X is a FPR or Altivec register used in a VSX context. */
19348 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
19349 output_operand_lossage ("invalid %%x value");
19352 int reg
= REGNO (x
);
19353 int vsx_reg
= (FP_REGNO_P (reg
)
19355 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
19357 #ifdef TARGET_REGNAMES
19358 if (TARGET_REGNAMES
)
19359 fprintf (file
, "%%vs%d", vsx_reg
);
19362 fprintf (file
, "%d", vsx_reg
);
19368 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
19369 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
19370 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
19375 /* Like 'L', for third word of TImode/PTImode */
19377 fputs (reg_names
[REGNO (x
) + 2], file
);
19378 else if (MEM_P (x
))
19380 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
19381 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19382 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
19383 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19384 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
19386 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
19387 if (small_data_operand (x
, GET_MODE (x
)))
19388 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19389 reg_names
[SMALL_DATA_REG
]);
19394 /* X is a SYMBOL_REF. Write out the name preceded by a
19395 period and without any trailing data in brackets. Used for function
19396 names. If we are configured for System V (or the embedded ABI) on
19397 the PowerPC, do not emit the period, since those systems do not use
19398 TOCs and the like. */
19399 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
19401 /* For macho, check to see if we need a stub. */
19404 const char *name
= XSTR (x
, 0);
19406 if (darwin_emit_branch_islands
19407 && MACHOPIC_INDIRECT
19408 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
19409 name
= machopic_indirection_name (x
, /*stub_p=*/true);
19411 assemble_name (file
, name
);
19413 else if (!DOT_SYMBOLS
)
19414 assemble_name (file
, XSTR (x
, 0));
19416 rs6000_output_function_entry (file
, XSTR (x
, 0));
19420 /* Like 'L', for last word of TImode/PTImode. */
19422 fputs (reg_names
[REGNO (x
) + 3], file
);
19423 else if (MEM_P (x
))
19425 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
19426 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19427 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
19428 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19429 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
19431 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
19432 if (small_data_operand (x
, GET_MODE (x
)))
19433 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19434 reg_names
[SMALL_DATA_REG
]);
19438 /* Print AltiVec or SPE memory operand. */
19443 gcc_assert (MEM_P (x
));
19447 /* Ugly hack because %y is overloaded. */
19448 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
19449 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
19450 || FLOAT128_2REG_P (GET_MODE (x
))
19451 || GET_MODE (x
) == TImode
19452 || GET_MODE (x
) == PTImode
))
19454 /* Handle [reg]. */
19457 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
19460 /* Handle [reg+UIMM]. */
19461 else if (GET_CODE (tmp
) == PLUS
&&
19462 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
19466 gcc_assert (REG_P (XEXP (tmp
, 0)));
19468 x
= INTVAL (XEXP (tmp
, 1));
19469 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
19473 /* Fall through. Must be [reg+reg]. */
19475 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
19476 && GET_CODE (tmp
) == AND
19477 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
19478 && INTVAL (XEXP (tmp
, 1)) == -16)
19479 tmp
= XEXP (tmp
, 0);
19480 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
19481 && GET_CODE (tmp
) == PRE_MODIFY
)
19482 tmp
= XEXP (tmp
, 1);
19484 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
19487 if (GET_CODE (tmp
) != PLUS
19488 || !REG_P (XEXP (tmp
, 0))
19489 || !REG_P (XEXP (tmp
, 1)))
19491 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
19495 if (REGNO (XEXP (tmp
, 0)) == 0)
19496 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
19497 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
19499 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
19500 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
19507 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
19508 else if (MEM_P (x
))
19510 /* We need to handle PRE_INC and PRE_DEC here, since we need to
19511 know the width from the mode. */
19512 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
19513 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
19514 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
19515 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19516 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
19517 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
19518 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19519 output_address (XEXP (XEXP (x
, 0), 1));
19521 output_address (XEXP (x
, 0));
19525 if (toc_relative_expr_p (x
, false))
19526 /* This hack along with a corresponding hack in
19527 rs6000_output_addr_const_extra arranges to output addends
19528 where the assembler expects to find them. eg.
19529 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
19530 without this hack would be output as "x@toc+4". We
19532 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
19534 output_addr_const (file
, x
);
19539 if (const char *name
= get_some_local_dynamic_name ())
19540 assemble_name (file
, name
);
19542 output_operand_lossage ("'%%&' used without any "
19543 "local dynamic TLS references");
19547 output_operand_lossage ("invalid %%xn code");
19551 /* Print the address of an operand. */
19554 print_operand_address (FILE *file
, rtx x
)
19557 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
19558 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
19559 || GET_CODE (x
) == LABEL_REF
)
19561 output_addr_const (file
, x
);
19562 if (small_data_operand (x
, GET_MODE (x
)))
19563 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19564 reg_names
[SMALL_DATA_REG
]);
19566 gcc_assert (!TARGET_TOC
);
19568 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
19569 && REG_P (XEXP (x
, 1)))
19571 if (REGNO (XEXP (x
, 0)) == 0)
19572 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
19573 reg_names
[ REGNO (XEXP (x
, 0)) ]);
19575 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
19576 reg_names
[ REGNO (XEXP (x
, 1)) ]);
19578 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
19579 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
19580 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
19581 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
19583 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
19584 && CONSTANT_P (XEXP (x
, 1)))
19586 fprintf (file
, "lo16(");
19587 output_addr_const (file
, XEXP (x
, 1));
19588 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
19592 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
19593 && CONSTANT_P (XEXP (x
, 1)))
19595 output_addr_const (file
, XEXP (x
, 1));
19596 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
19599 else if (toc_relative_expr_p (x
, false))
19601 /* This hack along with a corresponding hack in
19602 rs6000_output_addr_const_extra arranges to output addends
19603 where the assembler expects to find them. eg.
19605 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
19606 without this hack would be output as "x@toc+8@l(9)". We
19607 want "x+8@toc@l(9)". */
19608 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
19609 if (GET_CODE (x
) == LO_SUM
)
19610 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
19612 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
19615 gcc_unreachable ();
19618 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
19621 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
19623 if (GET_CODE (x
) == UNSPEC
)
19624 switch (XINT (x
, 1))
19626 case UNSPEC_TOCREL
:
19627 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
19628 && REG_P (XVECEXP (x
, 0, 1))
19629 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
19630 output_addr_const (file
, XVECEXP (x
, 0, 0));
19631 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
19633 if (INTVAL (tocrel_offset
) >= 0)
19634 fprintf (file
, "+");
19635 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
19637 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
19640 assemble_name (file
, toc_label_name
);
19642 else if (TARGET_ELF
)
19643 fputs ("@toc", file
);
19647 case UNSPEC_MACHOPIC_OFFSET
:
19648 output_addr_const (file
, XVECEXP (x
, 0, 0));
19650 machopic_output_function_base_name (file
);
19657 /* Target hook for assembling integer objects. The PowerPC version has
19658 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
19659 is defined. It also needs to handle DI-mode objects on 64-bit
19663 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
19665 #ifdef RELOCATABLE_NEEDS_FIXUP
19666 /* Special handling for SI values. */
19667 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
19669 static int recurse
= 0;
19671 /* For -mrelocatable, we mark all addresses that need to be fixed up in
19672 the .fixup section. Since the TOC section is already relocated, we
19673 don't need to mark it here. We used to skip the text section, but it
19674 should never be valid for relocated addresses to be placed in the text
19676 if (TARGET_RELOCATABLE
19677 && in_section
!= toc_section
19679 && !CONST_SCALAR_INT_P (x
)
19685 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
19687 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
19688 fprintf (asm_out_file
, "\t.long\t(");
19689 output_addr_const (asm_out_file
, x
);
19690 fprintf (asm_out_file
, ")@fixup\n");
19691 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
19692 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
19693 fprintf (asm_out_file
, "\t.long\t");
19694 assemble_name (asm_out_file
, buf
);
19695 fprintf (asm_out_file
, "\n\t.previous\n");
19699 /* Remove initial .'s to turn a -mcall-aixdesc function
19700 address into the address of the descriptor, not the function
19702 else if (GET_CODE (x
) == SYMBOL_REF
19703 && XSTR (x
, 0)[0] == '.'
19704 && DEFAULT_ABI
== ABI_AIX
)
19706 const char *name
= XSTR (x
, 0);
19707 while (*name
== '.')
19710 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
19714 #endif /* RELOCATABLE_NEEDS_FIXUP */
19715 return default_assemble_integer (x
, size
, aligned_p
);
19718 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
19719 /* Emit an assembler directive to set symbol visibility for DECL to
19720 VISIBILITY_TYPE. */
19723 rs6000_assemble_visibility (tree decl
, int vis
)
19728 /* Functions need to have their entry point symbol visibility set as
19729 well as their descriptor symbol visibility. */
19730 if (DEFAULT_ABI
== ABI_AIX
19732 && TREE_CODE (decl
) == FUNCTION_DECL
)
19734 static const char * const visibility_types
[] = {
19735 NULL
, "internal", "hidden", "protected"
19738 const char *name
, *type
;
19740 name
= ((* targetm
.strip_name_encoding
)
19741 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
19742 type
= visibility_types
[vis
];
19744 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
19745 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
19748 default_assemble_visibility (decl
, vis
);
19753 rs6000_reverse_condition (machine_mode mode
, enum rtx_code code
)
19755 /* Reversal of FP compares takes care -- an ordered compare
19756 becomes an unordered compare and vice versa. */
19757 if (mode
== CCFPmode
19758 && (!flag_finite_math_only
19759 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
19760 || code
== UNEQ
|| code
== LTGT
))
19761 return reverse_condition_maybe_unordered (code
);
19763 return reverse_condition (code
);
19766 /* Generate a compare for CODE. Return a brand-new rtx that
19767 represents the result of the compare. */
19770 rs6000_generate_compare (rtx cmp
, machine_mode mode
)
19772 machine_mode comp_mode
;
19773 rtx compare_result
;
19774 enum rtx_code code
= GET_CODE (cmp
);
19775 rtx op0
= XEXP (cmp
, 0);
19776 rtx op1
= XEXP (cmp
, 1);
19778 if (FLOAT_MODE_P (mode
))
19779 comp_mode
= CCFPmode
;
19780 else if (code
== GTU
|| code
== LTU
19781 || code
== GEU
|| code
== LEU
)
19782 comp_mode
= CCUNSmode
;
19783 else if ((code
== EQ
|| code
== NE
)
19784 && unsigned_reg_p (op0
)
19785 && (unsigned_reg_p (op1
)
19786 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
19787 /* These are unsigned values, perhaps there will be a later
19788 ordering compare that can be shared with this one. */
19789 comp_mode
= CCUNSmode
;
19791 comp_mode
= CCmode
;
19793 /* If we have an unsigned compare, make sure we don't have a signed value as
19795 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
19796 && INTVAL (op1
) < 0)
19798 op0
= copy_rtx_if_shared (op0
);
19799 op1
= force_reg (GET_MODE (op0
), op1
);
19800 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
19803 /* First, the compare. */
19804 compare_result
= gen_reg_rtx (comp_mode
);
19806 /* E500 FP compare instructions on the GPRs. Yuck! */
19807 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
19808 && FLOAT_MODE_P (mode
))
19810 rtx cmp
, or_result
, compare_result2
;
19811 machine_mode op_mode
= GET_MODE (op0
);
19814 if (op_mode
== VOIDmode
)
19815 op_mode
= GET_MODE (op1
);
19817 /* First reverse the condition codes that aren't directly supported. */
19825 code
= reverse_condition_maybe_unordered (code
);
19838 gcc_unreachable ();
19841 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
19842 This explains the following mess. */
19850 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19851 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
19852 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
19856 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19857 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
19858 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
19864 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19865 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
19866 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
19870 gcc_unreachable ();
19879 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19880 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
19881 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
19885 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19886 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
19887 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
19893 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19894 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
19895 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
19899 gcc_unreachable ();
19908 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19909 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
19910 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
19914 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19915 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
19916 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
19922 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19923 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
19924 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
19928 gcc_unreachable ();
19933 gcc_unreachable ();
19936 /* Synthesize LE and GE from LT/GT || EQ. */
19937 if (code
== LE
|| code
== GE
)
19941 compare_result2
= gen_reg_rtx (CCFPmode
);
19947 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19948 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
19949 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
19953 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19954 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
19955 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
19961 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19962 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
19963 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
19967 gcc_unreachable ();
19972 /* OR them together. */
19973 or_result
= gen_reg_rtx (CCFPmode
);
19974 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
19976 compare_result
= or_result
;
19979 code
= reverse_p
? NE
: EQ
;
19984 /* IEEE 128-bit support in VSX registers. The comparison function (__cmpkf2)
19985 returns 0..15 that is laid out the same way as the PowerPC CR register
19986 would for a normal floating point comparison. */
19987 else if (FLOAT128_IEEE_P (mode
))
19989 rtx and_reg
= gen_reg_rtx (SImode
);
19990 rtx dest
= gen_reg_rtx (SImode
);
19991 rtx libfunc
= optab_libfunc (cmp_optab
, mode
);
19992 HOST_WIDE_INT mask_value
= 0;
19994 /* Values that __cmpkf2 returns. */
19995 #define PPC_CMP_UNORDERED 0x1 /* isnan (a) || isnan (b). */
19996 #define PPC_CMP_EQUAL 0x2 /* a == b. */
19997 #define PPC_CMP_GREATER_THEN 0x4 /* a > b. */
19998 #define PPC_CMP_LESS_THEN 0x8 /* a < b. */
20003 mask_value
= PPC_CMP_EQUAL
;
20008 mask_value
= PPC_CMP_EQUAL
;
20013 mask_value
= PPC_CMP_GREATER_THEN
;
20018 mask_value
= PPC_CMP_GREATER_THEN
| PPC_CMP_EQUAL
;
20023 mask_value
= PPC_CMP_LESS_THEN
;
20028 mask_value
= PPC_CMP_LESS_THEN
| PPC_CMP_EQUAL
;
20033 mask_value
= PPC_CMP_GREATER_THEN
;
20038 mask_value
= PPC_CMP_GREATER_THEN
| PPC_CMP_EQUAL
;
20043 mask_value
= PPC_CMP_LESS_THEN
;
20048 mask_value
= PPC_CMP_LESS_THEN
| PPC_CMP_EQUAL
;
20053 mask_value
= PPC_CMP_EQUAL
| PPC_CMP_UNORDERED
;
20057 mask_value
= PPC_CMP_EQUAL
| PPC_CMP_UNORDERED
;
20062 mask_value
= PPC_CMP_UNORDERED
;
20067 mask_value
= PPC_CMP_UNORDERED
;
20072 gcc_unreachable ();
20075 gcc_assert (mask_value
!= 0);
20076 and_reg
= emit_library_call_value (libfunc
, and_reg
, LCT_CONST
, SImode
, 2,
20077 op0
, mode
, op1
, mode
);
20079 emit_insn (gen_andsi3 (dest
, and_reg
, GEN_INT (mask_value
)));
20080 compare_result
= gen_reg_rtx (CCmode
);
20081 comp_mode
= CCmode
;
20083 emit_insn (gen_rtx_SET (compare_result
,
20084 gen_rtx_COMPARE (comp_mode
, dest
, const0_rtx
)));
20089 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
20090 CLOBBERs to match cmptf_internal2 pattern. */
20091 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
20092 && FLOAT128_IBM_P (GET_MODE (op0
))
20093 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
20094 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
20096 gen_rtx_SET (compare_result
,
20097 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
20098 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20099 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20100 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20101 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20102 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20103 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20104 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20105 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
20106 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
20107 else if (GET_CODE (op1
) == UNSPEC
20108 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
20110 rtx op1b
= XVECEXP (op1
, 0, 0);
20111 comp_mode
= CCEQmode
;
20112 compare_result
= gen_reg_rtx (CCEQmode
);
20114 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
20116 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
20119 emit_insn (gen_rtx_SET (compare_result
,
20120 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
20123 /* Some kinds of FP comparisons need an OR operation;
20124 under flag_finite_math_only we don't bother. */
20125 if (FLOAT_MODE_P (mode
)
20126 && !FLOAT128_IEEE_P (mode
)
20127 && !flag_finite_math_only
20128 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
20129 && (code
== LE
|| code
== GE
20130 || code
== UNEQ
|| code
== LTGT
20131 || code
== UNGT
|| code
== UNLT
))
20133 enum rtx_code or1
, or2
;
20134 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
20135 rtx or_result
= gen_reg_rtx (CCEQmode
);
20139 case LE
: or1
= LT
; or2
= EQ
; break;
20140 case GE
: or1
= GT
; or2
= EQ
; break;
20141 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
20142 case LTGT
: or1
= LT
; or2
= GT
; break;
20143 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
20144 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
20145 default: gcc_unreachable ();
20147 validate_condition_mode (or1
, comp_mode
);
20148 validate_condition_mode (or2
, comp_mode
);
20149 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
20150 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
20151 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
20152 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
20154 emit_insn (gen_rtx_SET (or_result
, compare2_rtx
));
20156 compare_result
= or_result
;
20160 validate_condition_mode (code
, GET_MODE (compare_result
));
20162 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
20166 /* Expand floating point conversion to/from __float128 and __ibm128. */
20169 rs6000_expand_float128_convert (rtx dest
, rtx src
, bool unsigned_p
)
20171 machine_mode dest_mode
= GET_MODE (dest
);
20172 machine_mode src_mode
= GET_MODE (src
);
20173 convert_optab cvt
= unknown_optab
;
20174 rtx libfunc
= NULL_RTX
;
20177 if (dest_mode
== src_mode
)
20178 gcc_unreachable ();
20180 if (FLOAT128_IEEE_P (dest_mode
))
20182 if (src_mode
== SFmode
20183 || src_mode
== DFmode
20184 || FLOAT128_IBM_P (src_mode
))
20187 else if (GET_MODE_CLASS (src_mode
) == MODE_INT
)
20188 cvt
= (unsigned_p
) ? ufloat_optab
: sfloat_optab
;
20190 else if (FLOAT128_IEEE_P (src_mode
))
20191 emit_move_insn (dest
, gen_lowpart (dest_mode
, src
));
20194 gcc_unreachable ();
20197 else if (FLOAT128_IEEE_P (src_mode
))
20199 if (dest_mode
== SFmode
20200 || dest_mode
== DFmode
20201 || FLOAT128_IBM_P (dest_mode
))
20204 else if (GET_MODE_CLASS (dest_mode
) == MODE_INT
)
20205 cvt
= (unsigned_p
) ? ufix_optab
: sfix_optab
;
20208 gcc_unreachable ();
20212 gcc_unreachable ();
20214 gcc_assert (cvt
!= unknown_optab
);
20215 libfunc
= convert_optab_libfunc (cvt
, dest_mode
, src_mode
);
20216 gcc_assert (libfunc
!= NULL_RTX
);
20218 dest2
= emit_library_call_value (libfunc
, dest
, LCT_CONST
, dest_mode
, 1, src
,
20221 gcc_assert (dest
!= NULL_RTX
);
20222 if (!rtx_equal_p (dest
, dest2
))
20223 emit_move_insn (dest
, dest2
);
20228 /* Emit the RTL for an sISEL pattern. */
20231 rs6000_emit_sISEL (machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
20233 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
20236 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
20237 can be used as that dest register. Return the dest register. */
20240 rs6000_emit_eqne (machine_mode mode
, rtx op1
, rtx op2
, rtx scratch
)
20242 if (op2
== const0_rtx
)
20245 if (GET_CODE (scratch
) == SCRATCH
)
20246 scratch
= gen_reg_rtx (mode
);
20248 if (logical_operand (op2
, mode
))
20249 emit_insn (gen_rtx_SET (scratch
, gen_rtx_XOR (mode
, op1
, op2
)));
20251 emit_insn (gen_rtx_SET (scratch
,
20252 gen_rtx_PLUS (mode
, op1
, negate_rtx (mode
, op2
))));
20258 rs6000_emit_sCOND (machine_mode mode
, rtx operands
[])
20261 machine_mode op_mode
;
20262 enum rtx_code cond_code
;
20263 rtx result
= operands
[0];
20265 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
20266 cond_code
= GET_CODE (condition_rtx
);
20268 if (FLOAT_MODE_P (mode
)
20269 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
20273 PUT_MODE (condition_rtx
, SImode
);
20274 t
= XEXP (condition_rtx
, 0);
20276 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
20278 if (cond_code
== NE
)
20279 emit_insn (gen_e500_flip_gt_bit (t
, t
));
20281 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
20285 if (cond_code
== NE
20286 || cond_code
== GE
|| cond_code
== LE
20287 || cond_code
== GEU
|| cond_code
== LEU
20288 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
20290 rtx not_result
= gen_reg_rtx (CCEQmode
);
20291 rtx not_op
, rev_cond_rtx
;
20292 machine_mode cc_mode
;
20294 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
20296 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
20297 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
20298 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
20299 emit_insn (gen_rtx_SET (not_result
, not_op
));
20300 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
20303 op_mode
= GET_MODE (XEXP (operands
[1], 0));
20304 if (op_mode
== VOIDmode
)
20305 op_mode
= GET_MODE (XEXP (operands
[1], 1));
20307 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
20309 PUT_MODE (condition_rtx
, DImode
);
20310 convert_move (result
, condition_rtx
, 0);
20314 PUT_MODE (condition_rtx
, SImode
);
20315 emit_insn (gen_rtx_SET (result
, condition_rtx
));
20319 /* Emit a branch of kind CODE to location LOC. */
20322 rs6000_emit_cbranch (machine_mode mode
, rtx operands
[])
20324 rtx condition_rtx
, loc_ref
;
20326 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
20327 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
20328 emit_jump_insn (gen_rtx_SET (pc_rtx
,
20329 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
20330 loc_ref
, pc_rtx
)));
20333 /* Return the string to output a conditional branch to LABEL, which is
20334 the operand template of the label, or NULL if the branch is really a
20335 conditional return.
20337 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
20338 condition code register and its mode specifies what kind of
20339 comparison we made.
20341 REVERSED is nonzero if we should reverse the sense of the comparison.
20343 INSN is the insn. */
20346 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
20348 static char string
[64];
20349 enum rtx_code code
= GET_CODE (op
);
20350 rtx cc_reg
= XEXP (op
, 0);
20351 machine_mode mode
= GET_MODE (cc_reg
);
20352 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
20353 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
20354 int really_reversed
= reversed
^ need_longbranch
;
20360 validate_condition_mode (code
, mode
);
20362 /* Work out which way this really branches. We could use
20363 reverse_condition_maybe_unordered here always but this
20364 makes the resulting assembler clearer. */
20365 if (really_reversed
)
20367 /* Reversal of FP compares takes care -- an ordered compare
20368 becomes an unordered compare and vice versa. */
20369 if (mode
== CCFPmode
)
20370 code
= reverse_condition_maybe_unordered (code
);
20372 code
= reverse_condition (code
);
20375 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
20377 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
20382 /* Opposite of GT. */
20391 gcc_unreachable ();
20397 /* Not all of these are actually distinct opcodes, but
20398 we distinguish them for clarity of the resulting assembler. */
20399 case NE
: case LTGT
:
20400 ccode
= "ne"; break;
20401 case EQ
: case UNEQ
:
20402 ccode
= "eq"; break;
20404 ccode
= "ge"; break;
20405 case GT
: case GTU
: case UNGT
:
20406 ccode
= "gt"; break;
20408 ccode
= "le"; break;
20409 case LT
: case LTU
: case UNLT
:
20410 ccode
= "lt"; break;
20411 case UNORDERED
: ccode
= "un"; break;
20412 case ORDERED
: ccode
= "nu"; break;
20413 case UNGE
: ccode
= "nl"; break;
20414 case UNLE
: ccode
= "ng"; break;
20416 gcc_unreachable ();
20419 /* Maybe we have a guess as to how likely the branch is. */
20421 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
20422 if (note
!= NULL_RTX
)
20424 /* PROB is the difference from 50%. */
20425 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
20427 /* Only hint for highly probable/improbable branches on newer
20428 cpus as static prediction overrides processor dynamic
20429 prediction. For older cpus we may as well always hint, but
20430 assume not taken for branches that are very close to 50% as a
20431 mispredicted taken branch is more expensive than a
20432 mispredicted not-taken branch. */
20433 if (rs6000_always_hint
20434 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
20435 && br_prob_note_reliable_p (note
)))
20437 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
20438 && ((prob
> 0) ^ need_longbranch
))
20446 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
20448 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
20450 /* We need to escape any '%' characters in the reg_names string.
20451 Assume they'd only be the first character.... */
20452 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
20454 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
20458 /* If the branch distance was too far, we may have to use an
20459 unconditional branch to go the distance. */
20460 if (need_longbranch
)
20461 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
20463 s
+= sprintf (s
, ",%s", label
);
20469 /* Return the string to flip the GT bit on a CR. */
20471 output_e500_flip_gt_bit (rtx dst
, rtx src
)
20473 static char string
[64];
20476 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
20477 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
20480 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
20481 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
20483 sprintf (string
, "crnot %d,%d", a
, b
);
20487 /* Return insn for VSX or Altivec comparisons. */
20490 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
20493 machine_mode mode
= GET_MODE (op0
);
20501 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
20511 mask
= gen_reg_rtx (mode
);
20512 emit_insn (gen_rtx_SET (mask
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
20519 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
20520 DMODE is expected destination mode. This is a recursive function. */
20523 rs6000_emit_vector_compare (enum rtx_code rcode
,
20525 machine_mode dmode
)
20528 bool swap_operands
= false;
20529 bool try_again
= false;
20531 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
20532 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
20534 /* See if the comparison works as is. */
20535 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
20543 swap_operands
= true;
20548 swap_operands
= true;
20556 /* Invert condition and try again.
20557 e.g., A != B becomes ~(A==B). */
20559 enum rtx_code rev_code
;
20560 enum insn_code nor_code
;
20563 rev_code
= reverse_condition_maybe_unordered (rcode
);
20564 if (rev_code
== UNKNOWN
)
20567 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
20568 if (nor_code
== CODE_FOR_nothing
)
20571 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
20575 mask
= gen_reg_rtx (dmode
);
20576 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
20584 /* Try GT/GTU/LT/LTU OR EQ */
20587 enum insn_code ior_code
;
20588 enum rtx_code new_code
;
20609 gcc_unreachable ();
20612 ior_code
= optab_handler (ior_optab
, dmode
);
20613 if (ior_code
== CODE_FOR_nothing
)
20616 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
20620 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
20624 mask
= gen_reg_rtx (dmode
);
20625 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
20636 std::swap (op0
, op1
);
20638 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
20643 /* You only get two chances. */
20647 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
20648 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
20649 operands for the relation operation COND. */
20652 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
20653 rtx cond
, rtx cc_op0
, rtx cc_op1
)
20655 machine_mode dest_mode
= GET_MODE (dest
);
20656 machine_mode mask_mode
= GET_MODE (cc_op0
);
20657 enum rtx_code rcode
= GET_CODE (cond
);
20658 machine_mode cc_mode
= CCmode
;
20662 bool invert_move
= false;
20664 if (VECTOR_UNIT_NONE_P (dest_mode
))
20667 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
20668 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
20672 /* Swap operands if we can, and fall back to doing the operation as
20673 specified, and doing a NOR to invert the test. */
20679 /* Invert condition and try again.
20680 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
20681 invert_move
= true;
20682 rcode
= reverse_condition_maybe_unordered (rcode
);
20683 if (rcode
== UNKNOWN
)
20687 /* Mark unsigned tests with CCUNSmode. */
20692 cc_mode
= CCUNSmode
;
20699 /* Get the vector mask for the given relational operations. */
20700 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
20708 op_true
= op_false
;
20712 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
20713 CONST0_RTX (dest_mode
));
20714 emit_insn (gen_rtx_SET (dest
,
20715 gen_rtx_IF_THEN_ELSE (dest_mode
,
20722 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
20723 operands of the last comparison is nonzero/true, FALSE_COND if it
20724 is zero/false. Return 0 if the hardware has no such operation. */
20727 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
20729 enum rtx_code code
= GET_CODE (op
);
20730 rtx op0
= XEXP (op
, 0);
20731 rtx op1
= XEXP (op
, 1);
20732 REAL_VALUE_TYPE c1
;
20733 machine_mode compare_mode
= GET_MODE (op0
);
20734 machine_mode result_mode
= GET_MODE (dest
);
20736 bool is_against_zero
;
20738 /* These modes should always match. */
20739 if (GET_MODE (op1
) != compare_mode
20740 /* In the isel case however, we can use a compare immediate, so
20741 op1 may be a small constant. */
20742 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
20744 if (GET_MODE (true_cond
) != result_mode
)
20746 if (GET_MODE (false_cond
) != result_mode
)
20749 /* Don't allow using floating point comparisons for integer results for
20751 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
20754 /* First, work out if the hardware can do this at all, or
20755 if it's too slow.... */
20756 if (!FLOAT_MODE_P (compare_mode
))
20759 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
20762 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
20763 && SCALAR_FLOAT_MODE_P (compare_mode
))
20766 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
20768 /* A floating-point subtract might overflow, underflow, or produce
20769 an inexact result, thus changing the floating-point flags, so it
20770 can't be generated if we care about that. It's safe if one side
20771 of the construct is zero, since then no subtract will be
20773 if (SCALAR_FLOAT_MODE_P (compare_mode
)
20774 && flag_trapping_math
&& ! is_against_zero
)
20777 /* Eliminate half of the comparisons by switching operands, this
20778 makes the remaining code simpler. */
20779 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
20780 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
20782 code
= reverse_condition_maybe_unordered (code
);
20784 true_cond
= false_cond
;
20788 /* UNEQ and LTGT take four instructions for a comparison with zero,
20789 it'll probably be faster to use a branch here too. */
20790 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
20793 if (GET_CODE (op1
) == CONST_DOUBLE
)
20794 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
20796 /* We're going to try to implement comparisons by performing
20797 a subtract, then comparing against zero. Unfortunately,
20798 Inf - Inf is NaN which is not zero, and so if we don't
20799 know that the operand is finite and the comparison
20800 would treat EQ different to UNORDERED, we can't do it. */
20801 if (HONOR_INFINITIES (compare_mode
)
20802 && code
!= GT
&& code
!= UNGE
20803 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
20804 /* Constructs of the form (a OP b ? a : b) are safe. */
20805 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
20806 || (! rtx_equal_p (op0
, true_cond
)
20807 && ! rtx_equal_p (op1
, true_cond
))))
20810 /* At this point we know we can use fsel. */
20812 /* Reduce the comparison to a comparison against zero. */
20813 if (! is_against_zero
)
20815 temp
= gen_reg_rtx (compare_mode
);
20816 emit_insn (gen_rtx_SET (temp
, gen_rtx_MINUS (compare_mode
, op0
, op1
)));
20818 op1
= CONST0_RTX (compare_mode
);
20821 /* If we don't care about NaNs we can reduce some of the comparisons
20822 down to faster ones. */
20823 if (! HONOR_NANS (compare_mode
))
20829 true_cond
= false_cond
;
20842 /* Now, reduce everything down to a GE. */
20849 temp
= gen_reg_rtx (compare_mode
);
20850 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
20855 temp
= gen_reg_rtx (compare_mode
);
20856 emit_insn (gen_rtx_SET (temp
, gen_rtx_ABS (compare_mode
, op0
)));
20861 temp
= gen_reg_rtx (compare_mode
);
20862 emit_insn (gen_rtx_SET (temp
,
20863 gen_rtx_NEG (compare_mode
,
20864 gen_rtx_ABS (compare_mode
, op0
))));
20869 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
20870 temp
= gen_reg_rtx (result_mode
);
20871 emit_insn (gen_rtx_SET (temp
,
20872 gen_rtx_IF_THEN_ELSE (result_mode
,
20873 gen_rtx_GE (VOIDmode
,
20875 true_cond
, false_cond
)));
20876 false_cond
= true_cond
;
20879 temp
= gen_reg_rtx (compare_mode
);
20880 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
20885 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
20886 temp
= gen_reg_rtx (result_mode
);
20887 emit_insn (gen_rtx_SET (temp
,
20888 gen_rtx_IF_THEN_ELSE (result_mode
,
20889 gen_rtx_GE (VOIDmode
,
20891 true_cond
, false_cond
)));
20892 true_cond
= false_cond
;
20895 temp
= gen_reg_rtx (compare_mode
);
20896 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
20901 gcc_unreachable ();
20904 emit_insn (gen_rtx_SET (dest
,
20905 gen_rtx_IF_THEN_ELSE (result_mode
,
20906 gen_rtx_GE (VOIDmode
,
20908 true_cond
, false_cond
)));
20912 /* Same as above, but for ints (isel). */
20915 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
20917 rtx condition_rtx
, cr
;
20918 machine_mode mode
= GET_MODE (dest
);
20919 enum rtx_code cond_code
;
20920 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
20923 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
20926 /* We still have to do the compare, because isel doesn't do a
20927 compare, it just looks at the CRx bits set by a previous compare
20929 condition_rtx
= rs6000_generate_compare (op
, mode
);
20930 cond_code
= GET_CODE (condition_rtx
);
20931 cr
= XEXP (condition_rtx
, 0);
20932 signedp
= GET_MODE (cr
) == CCmode
;
20934 isel_func
= (mode
== SImode
20935 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
20936 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
20940 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
20941 /* isel handles these directly. */
20945 /* We need to swap the sense of the comparison. */
20947 std::swap (false_cond
, true_cond
);
20948 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
20953 false_cond
= force_reg (mode
, false_cond
);
20954 if (true_cond
!= const0_rtx
)
20955 true_cond
= force_reg (mode
, true_cond
);
20957 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
20963 output_isel (rtx
*operands
)
20965 enum rtx_code code
;
20967 code
= GET_CODE (operands
[1]);
20969 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
20971 gcc_assert (GET_CODE (operands
[2]) == REG
20972 && GET_CODE (operands
[3]) == REG
);
20973 PUT_CODE (operands
[1], reverse_condition (code
));
20974 return "isel %0,%3,%2,%j1";
20977 return "isel %0,%2,%3,%j1";
20981 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
20983 machine_mode mode
= GET_MODE (op0
);
20987 /* VSX/altivec have direct min/max insns. */
20988 if ((code
== SMAX
|| code
== SMIN
)
20989 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
20990 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
20992 emit_insn (gen_rtx_SET (dest
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
20996 if (code
== SMAX
|| code
== SMIN
)
21001 if (code
== SMAX
|| code
== UMAX
)
21002 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
21003 op0
, op1
, mode
, 0);
21005 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
21006 op1
, op0
, mode
, 0);
21007 gcc_assert (target
);
21008 if (target
!= dest
)
21009 emit_move_insn (dest
, target
);
21012 /* A subroutine of the atomic operation splitters. Jump to LABEL if
21013 COND is true. Mark the jump as unlikely to be taken. */
21016 emit_unlikely_jump (rtx cond
, rtx label
)
21018 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
21021 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
21022 x
= emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
21023 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
21026 /* A subroutine of the atomic operation splitters. Emit a load-locked
21027 instruction in MODE. For QI/HImode, possibly use a pattern than includes
21028 the zero_extend operation. */
21031 emit_load_locked (machine_mode mode
, rtx reg
, rtx mem
)
21033 rtx (*fn
) (rtx
, rtx
) = NULL
;
21038 fn
= gen_load_lockedqi
;
21041 fn
= gen_load_lockedhi
;
21044 if (GET_MODE (mem
) == QImode
)
21045 fn
= gen_load_lockedqi_si
;
21046 else if (GET_MODE (mem
) == HImode
)
21047 fn
= gen_load_lockedhi_si
;
21049 fn
= gen_load_lockedsi
;
21052 fn
= gen_load_lockeddi
;
21055 fn
= gen_load_lockedti
;
21058 gcc_unreachable ();
21060 emit_insn (fn (reg
, mem
));
21063 /* A subroutine of the atomic operation splitters. Emit a store-conditional
21064 instruction in MODE. */
21067 emit_store_conditional (machine_mode mode
, rtx res
, rtx mem
, rtx val
)
21069 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
21074 fn
= gen_store_conditionalqi
;
21077 fn
= gen_store_conditionalhi
;
21080 fn
= gen_store_conditionalsi
;
21083 fn
= gen_store_conditionaldi
;
21086 fn
= gen_store_conditionalti
;
21089 gcc_unreachable ();
21092 /* Emit sync before stwcx. to address PPC405 Erratum. */
21093 if (PPC405_ERRATUM77
)
21094 emit_insn (gen_hwsync ());
21096 emit_insn (fn (res
, mem
, val
));
21099 /* Expand barriers before and after a load_locked/store_cond sequence. */
21102 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
21104 rtx addr
= XEXP (mem
, 0);
21105 int strict_p
= (reload_in_progress
|| reload_completed
);
21107 if (!legitimate_indirect_address_p (addr
, strict_p
)
21108 && !legitimate_indexed_address_p (addr
, strict_p
))
21110 addr
= force_reg (Pmode
, addr
);
21111 mem
= replace_equiv_address_nv (mem
, addr
);
21116 case MEMMODEL_RELAXED
:
21117 case MEMMODEL_CONSUME
:
21118 case MEMMODEL_ACQUIRE
:
21120 case MEMMODEL_RELEASE
:
21121 case MEMMODEL_ACQ_REL
:
21122 emit_insn (gen_lwsync ());
21124 case MEMMODEL_SEQ_CST
:
21125 emit_insn (gen_hwsync ());
21128 gcc_unreachable ();
21134 rs6000_post_atomic_barrier (enum memmodel model
)
21138 case MEMMODEL_RELAXED
:
21139 case MEMMODEL_CONSUME
:
21140 case MEMMODEL_RELEASE
:
21142 case MEMMODEL_ACQUIRE
:
21143 case MEMMODEL_ACQ_REL
:
21144 case MEMMODEL_SEQ_CST
:
21145 emit_insn (gen_isync ());
21148 gcc_unreachable ();
21152 /* A subroutine of the various atomic expanders. For sub-word operations,
21153 we must adjust things to operate on SImode. Given the original MEM,
21154 return a new aligned memory. Also build and return the quantities by
21155 which to shift and mask. */
21158 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
21160 rtx addr
, align
, shift
, mask
, mem
;
21161 HOST_WIDE_INT shift_mask
;
21162 machine_mode mode
= GET_MODE (orig_mem
);
21164 /* For smaller modes, we have to implement this via SImode. */
21165 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
21167 addr
= XEXP (orig_mem
, 0);
21168 addr
= force_reg (GET_MODE (addr
), addr
);
21170 /* Aligned memory containing subword. Generate a new memory. We
21171 do not want any of the existing MEM_ATTR data, as we're now
21172 accessing memory outside the original object. */
21173 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
21174 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21175 mem
= gen_rtx_MEM (SImode
, align
);
21176 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
21177 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
21178 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
21180 /* Shift amount for subword relative to aligned word. */
21181 shift
= gen_reg_rtx (SImode
);
21182 addr
= gen_lowpart (SImode
, addr
);
21183 rtx tmp
= gen_reg_rtx (SImode
);
21184 emit_insn (gen_ashlsi3 (tmp
, addr
, GEN_INT (3)));
21185 emit_insn (gen_andsi3 (shift
, tmp
, GEN_INT (shift_mask
)));
21186 if (BYTES_BIG_ENDIAN
)
21187 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
21188 shift
, 1, OPTAB_LIB_WIDEN
);
21191 /* Mask for insertion. */
21192 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
21193 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21199 /* A subroutine of the various atomic expanders. For sub-word operands,
21200 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
21203 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
21207 x
= gen_reg_rtx (SImode
);
21208 emit_insn (gen_rtx_SET (x
, gen_rtx_AND (SImode
,
21209 gen_rtx_NOT (SImode
, mask
),
21212 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
21217 /* A subroutine of the various atomic expanders. For sub-word operands,
21218 extract WIDE to NARROW via SHIFT. */
21221 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
21223 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
21224 wide
, 1, OPTAB_LIB_WIDEN
);
21225 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
21228 /* Expand an atomic compare and swap operation. */
21231 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
21233 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
21234 rtx label1
, label2
, x
, mask
, shift
;
21235 machine_mode mode
, orig_mode
;
21236 enum memmodel mod_s
, mod_f
;
21239 boolval
= operands
[0];
21240 retval
= operands
[1];
21242 oldval
= operands
[3];
21243 newval
= operands
[4];
21244 is_weak
= (INTVAL (operands
[5]) != 0);
21245 mod_s
= memmodel_base (INTVAL (operands
[6]));
21246 mod_f
= memmodel_base (INTVAL (operands
[7]));
21247 orig_mode
= mode
= GET_MODE (mem
);
21249 mask
= shift
= NULL_RTX
;
21250 if (mode
== QImode
|| mode
== HImode
)
21252 /* Before power8, we didn't have access to lbarx/lharx, so generate a
21253 lwarx and shift/mask operations. With power8, we need to do the
21254 comparison in SImode, but the store is still done in QI/HImode. */
21255 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
21257 if (!TARGET_SYNC_HI_QI
)
21259 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
21261 /* Shift and mask OLDVAL into position with the word. */
21262 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
21263 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21265 /* Shift and mask NEWVAL into position within the word. */
21266 newval
= convert_modes (SImode
, mode
, newval
, 1);
21267 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
21268 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21271 /* Prepare to adjust the return value. */
21272 retval
= gen_reg_rtx (SImode
);
21275 else if (reg_overlap_mentioned_p (retval
, oldval
))
21276 oldval
= copy_to_reg (oldval
);
21278 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
21283 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
21284 emit_label (XEXP (label1
, 0));
21286 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
21288 emit_load_locked (mode
, retval
, mem
);
21293 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
21294 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21297 cond
= gen_reg_rtx (CCmode
);
21298 /* If we have TImode, synthesize a comparison. */
21299 if (mode
!= TImode
)
21300 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
21303 rtx xor1_result
= gen_reg_rtx (DImode
);
21304 rtx xor2_result
= gen_reg_rtx (DImode
);
21305 rtx or_result
= gen_reg_rtx (DImode
);
21306 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
21307 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
21308 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
21309 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
21311 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
21312 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
21313 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
21314 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
21317 emit_insn (gen_rtx_SET (cond
, x
));
21319 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
21320 emit_unlikely_jump (x
, label2
);
21324 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
21326 emit_store_conditional (orig_mode
, cond
, mem
, x
);
21330 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
21331 emit_unlikely_jump (x
, label1
);
21334 if (!is_mm_relaxed (mod_f
))
21335 emit_label (XEXP (label2
, 0));
21337 rs6000_post_atomic_barrier (mod_s
);
21339 if (is_mm_relaxed (mod_f
))
21340 emit_label (XEXP (label2
, 0));
21343 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
21344 else if (mode
!= GET_MODE (operands
[1]))
21345 convert_move (operands
[1], retval
, 1);
21347 /* In all cases, CR0 contains EQ on success, and NE on failure. */
21348 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
21349 emit_insn (gen_rtx_SET (boolval
, x
));
21352 /* Expand an atomic exchange operation. */
21355 rs6000_expand_atomic_exchange (rtx operands
[])
21357 rtx retval
, mem
, val
, cond
;
21359 enum memmodel model
;
21360 rtx label
, x
, mask
, shift
;
21362 retval
= operands
[0];
21365 model
= memmodel_base (INTVAL (operands
[3]));
21366 mode
= GET_MODE (mem
);
21368 mask
= shift
= NULL_RTX
;
21369 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
21371 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
21373 /* Shift and mask VAL into position with the word. */
21374 val
= convert_modes (SImode
, mode
, val
, 1);
21375 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
21376 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21378 /* Prepare to adjust the return value. */
21379 retval
= gen_reg_rtx (SImode
);
21383 mem
= rs6000_pre_atomic_barrier (mem
, model
);
21385 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
21386 emit_label (XEXP (label
, 0));
21388 emit_load_locked (mode
, retval
, mem
);
21392 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
21394 cond
= gen_reg_rtx (CCmode
);
21395 emit_store_conditional (mode
, cond
, mem
, x
);
21397 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
21398 emit_unlikely_jump (x
, label
);
21400 rs6000_post_atomic_barrier (model
);
21403 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
21406 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
21407 to perform. MEM is the memory on which to operate. VAL is the second
21408 operand of the binary operator. BEFORE and AFTER are optional locations to
21409 return the value of MEM either before of after the operation. MODEL_RTX
21410 is a CONST_INT containing the memory model to use. */
21413 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
21414 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
21416 enum memmodel model
= memmodel_base (INTVAL (model_rtx
));
21417 machine_mode mode
= GET_MODE (mem
);
21418 machine_mode store_mode
= mode
;
21419 rtx label
, x
, cond
, mask
, shift
;
21420 rtx before
= orig_before
, after
= orig_after
;
21422 mask
= shift
= NULL_RTX
;
21423 /* On power8, we want to use SImode for the operation. On previous systems,
21424 use the operation in a subword and shift/mask to get the proper byte or
21426 if (mode
== QImode
|| mode
== HImode
)
21428 if (TARGET_SYNC_HI_QI
)
21430 val
= convert_modes (SImode
, mode
, val
, 1);
21432 /* Prepare to adjust the return value. */
21433 before
= gen_reg_rtx (SImode
);
21435 after
= gen_reg_rtx (SImode
);
21440 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
21442 /* Shift and mask VAL into position with the word. */
21443 val
= convert_modes (SImode
, mode
, val
, 1);
21444 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
21445 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21451 /* We've already zero-extended VAL. That is sufficient to
21452 make certain that it does not affect other bits. */
21457 /* If we make certain that all of the other bits in VAL are
21458 set, that will be sufficient to not affect other bits. */
21459 x
= gen_rtx_NOT (SImode
, mask
);
21460 x
= gen_rtx_IOR (SImode
, x
, val
);
21461 emit_insn (gen_rtx_SET (val
, x
));
21468 /* These will all affect bits outside the field and need
21469 adjustment via MASK within the loop. */
21473 gcc_unreachable ();
21476 /* Prepare to adjust the return value. */
21477 before
= gen_reg_rtx (SImode
);
21479 after
= gen_reg_rtx (SImode
);
21480 store_mode
= mode
= SImode
;
21484 mem
= rs6000_pre_atomic_barrier (mem
, model
);
21486 label
= gen_label_rtx ();
21487 emit_label (label
);
21488 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
21490 if (before
== NULL_RTX
)
21491 before
= gen_reg_rtx (mode
);
21493 emit_load_locked (mode
, before
, mem
);
21497 x
= expand_simple_binop (mode
, AND
, before
, val
,
21498 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21499 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
21503 after
= expand_simple_binop (mode
, code
, before
, val
,
21504 after
, 1, OPTAB_LIB_WIDEN
);
21510 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
21511 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
21512 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
21514 else if (store_mode
!= mode
)
21515 x
= convert_modes (store_mode
, mode
, x
, 1);
21517 cond
= gen_reg_rtx (CCmode
);
21518 emit_store_conditional (store_mode
, cond
, mem
, x
);
21520 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
21521 emit_unlikely_jump (x
, label
);
21523 rs6000_post_atomic_barrier (model
);
21527 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
21528 then do the calcuations in a SImode register. */
21530 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
21532 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
21534 else if (store_mode
!= mode
)
21536 /* QImode/HImode on machines with lbarx/lharx where we do the native
21537 operation and then do the calcuations in a SImode register. */
21539 convert_move (orig_before
, before
, 1);
21541 convert_move (orig_after
, after
, 1);
21543 else if (orig_after
&& after
!= orig_after
)
21544 emit_move_insn (orig_after
, after
);
21547 /* Emit instructions to move SRC to DST. Called by splitters for
21548 multi-register moves. It will emit at most one instruction for
21549 each register that is accessed; that is, it won't emit li/lis pairs
21550 (or equivalent for 64-bit code). One of SRC or DST must be a hard
21554 rs6000_split_multireg_move (rtx dst
, rtx src
)
21556 /* The register number of the first register being moved. */
21558 /* The mode that is to be moved. */
21560 /* The mode that the move is being done in, and its size. */
21561 machine_mode reg_mode
;
21563 /* The number of registers that will be moved. */
21566 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
21567 mode
= GET_MODE (dst
);
21568 nregs
= hard_regno_nregs
[reg
][mode
];
21569 if (FP_REGNO_P (reg
))
21570 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
21571 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
21572 else if (ALTIVEC_REGNO_P (reg
))
21573 reg_mode
= V16QImode
;
21574 else if (TARGET_E500_DOUBLE
&& FLOAT128_2REG_P (mode
))
21577 reg_mode
= word_mode
;
21578 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
21580 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
21582 /* TDmode residing in FP registers is special, since the ISA requires that
21583 the lower-numbered word of a register pair is always the most significant
21584 word, even in little-endian mode. This does not match the usual subreg
21585 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
21586 the appropriate constituent registers "by hand" in little-endian mode.
21588 Note we do not need to check for destructive overlap here since TDmode
21589 can only reside in even/odd register pairs. */
21590 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
21595 for (i
= 0; i
< nregs
; i
++)
21597 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
21598 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
21600 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
21601 i
* reg_mode_size
);
21603 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
21604 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
21606 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
21607 i
* reg_mode_size
);
21609 emit_insn (gen_rtx_SET (p_dst
, p_src
));
21615 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
21617 /* Move register range backwards, if we might have destructive
21620 for (i
= nregs
- 1; i
>= 0; i
--)
21621 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
21622 i
* reg_mode_size
),
21623 simplify_gen_subreg (reg_mode
, src
, mode
,
21624 i
* reg_mode_size
)));
21630 bool used_update
= false;
21631 rtx restore_basereg
= NULL_RTX
;
21633 if (MEM_P (src
) && INT_REGNO_P (reg
))
21637 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
21638 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
21641 breg
= XEXP (XEXP (src
, 0), 0);
21642 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
21643 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
21644 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
21645 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
21646 src
= replace_equiv_address (src
, breg
);
21648 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
21650 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
21652 rtx basereg
= XEXP (XEXP (src
, 0), 0);
21655 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
21656 emit_insn (gen_rtx_SET (ndst
,
21657 gen_rtx_MEM (reg_mode
,
21659 used_update
= true;
21662 emit_insn (gen_rtx_SET (basereg
,
21663 XEXP (XEXP (src
, 0), 1)));
21664 src
= replace_equiv_address (src
, basereg
);
21668 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
21669 emit_insn (gen_rtx_SET (basereg
, XEXP (src
, 0)));
21670 src
= replace_equiv_address (src
, basereg
);
21674 breg
= XEXP (src
, 0);
21675 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
21676 breg
= XEXP (breg
, 0);
21678 /* If the base register we are using to address memory is
21679 also a destination reg, then change that register last. */
21681 && REGNO (breg
) >= REGNO (dst
)
21682 && REGNO (breg
) < REGNO (dst
) + nregs
)
21683 j
= REGNO (breg
) - REGNO (dst
);
21685 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
21689 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
21690 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
21693 breg
= XEXP (XEXP (dst
, 0), 0);
21694 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
21695 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
21696 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
21698 /* We have to update the breg before doing the store.
21699 Use store with update, if available. */
21703 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
21704 emit_insn (TARGET_32BIT
21705 ? (TARGET_POWERPC64
21706 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
21707 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
21708 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
21709 used_update
= true;
21712 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
21713 dst
= replace_equiv_address (dst
, breg
);
21715 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
21716 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
21718 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
21720 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
21723 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
21724 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode
,
21727 used_update
= true;
21730 emit_insn (gen_rtx_SET (basereg
,
21731 XEXP (XEXP (dst
, 0), 1)));
21732 dst
= replace_equiv_address (dst
, basereg
);
21736 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
21737 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
21738 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
21740 && REG_P (offsetreg
)
21741 && REGNO (basereg
) != REGNO (offsetreg
));
21742 if (REGNO (basereg
) == 0)
21744 rtx tmp
= offsetreg
;
21745 offsetreg
= basereg
;
21748 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
21749 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
21750 dst
= replace_equiv_address (dst
, basereg
);
21753 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
21754 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
21757 for (i
= 0; i
< nregs
; i
++)
21759 /* Calculate index to next subword. */
21764 /* If compiler already emitted move of first word by
21765 store with update, no need to do anything. */
21766 if (j
== 0 && used_update
)
21769 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
21770 j
* reg_mode_size
),
21771 simplify_gen_subreg (reg_mode
, src
, mode
,
21772 j
* reg_mode_size
)));
21774 if (restore_basereg
!= NULL_RTX
)
21775 emit_insn (restore_basereg
);
21780 /* This page contains routines that are used to determine what the
21781 function prologue and epilogue code will do and write them out. */
21786 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
21789 /* Return the first fixed-point register that is required to be
21790 saved. 32 if none. */
21793 first_reg_to_save (void)
21797 /* Find lowest numbered live register. */
21798 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
21799 if (save_reg_p (first_reg
))
21802 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
21803 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
21804 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
21805 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
21806 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
21807 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
21811 && crtl
->uses_pic_offset_table
21812 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
21813 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
21819 /* Similar, for FP regs. */
21822 first_fp_reg_to_save (void)
21826 /* Find lowest numbered live register. */
21827 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
21828 if (save_reg_p (first_reg
))
21834 /* Similar, for AltiVec regs. */
21837 first_altivec_reg_to_save (void)
21841 /* Stack frame remains as is unless we are in AltiVec ABI. */
21842 if (! TARGET_ALTIVEC_ABI
)
21843 return LAST_ALTIVEC_REGNO
+ 1;
21845 /* On Darwin, the unwind routines are compiled without
21846 TARGET_ALTIVEC, and use save_world to save/restore the
21847 altivec registers when necessary. */
21848 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
21849 && ! TARGET_ALTIVEC
)
21850 return FIRST_ALTIVEC_REGNO
+ 20;
21852 /* Find lowest numbered live register. */
21853 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21854 if (save_reg_p (i
))
21860 /* Return a 32-bit mask of the AltiVec registers we need to set in
21861 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
21862 the 32-bit word is 0. */
21864 static unsigned int
21865 compute_vrsave_mask (void)
21867 unsigned int i
, mask
= 0;
21869 /* On Darwin, the unwind routines are compiled without
21870 TARGET_ALTIVEC, and use save_world to save/restore the
21871 call-saved altivec registers when necessary. */
21872 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
21873 && ! TARGET_ALTIVEC
)
21876 /* First, find out if we use _any_ altivec registers. */
21877 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21878 if (df_regs_ever_live_p (i
))
21879 mask
|= ALTIVEC_REG_BIT (i
);
21884 /* Next, remove the argument registers from the set. These must
21885 be in the VRSAVE mask set by the caller, so we don't need to add
21886 them in again. More importantly, the mask we compute here is
21887 used to generate CLOBBERs in the set_vrsave insn, and we do not
21888 wish the argument registers to die. */
21889 for (i
= ALTIVEC_ARG_MIN_REG
; i
< (unsigned) crtl
->args
.info
.vregno
; i
++)
21890 mask
&= ~ALTIVEC_REG_BIT (i
);
21892 /* Similarly, remove the return value from the set. */
21895 diddle_return_value (is_altivec_return_reg
, &yes
);
21897 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
21903 /* For a very restricted set of circumstances, we can cut down the
21904 size of prologues/epilogues by calling our own save/restore-the-world
21908 compute_save_world_info (rs6000_stack_t
*info_ptr
)
21910 info_ptr
->world_save_p
= 1;
21911 info_ptr
->world_save_p
21912 = (WORLD_SAVE_P (info_ptr
)
21913 && DEFAULT_ABI
== ABI_DARWIN
21914 && !cfun
->has_nonlocal_label
21915 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
21916 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
21917 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
21918 && info_ptr
->cr_save_p
);
21920 /* This will not work in conjunction with sibcalls. Make sure there
21921 are none. (This check is expensive, but seldom executed.) */
21922 if (WORLD_SAVE_P (info_ptr
))
21925 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
21926 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
21928 info_ptr
->world_save_p
= 0;
21933 if (WORLD_SAVE_P (info_ptr
))
21935 /* Even if we're not touching VRsave, make sure there's room on the
21936 stack for it, if it looks like we're calling SAVE_WORLD, which
21937 will attempt to save it. */
21938 info_ptr
->vrsave_size
= 4;
21940 /* If we are going to save the world, we need to save the link register too. */
21941 info_ptr
->lr_save_p
= 1;
21943 /* "Save" the VRsave register too if we're saving the world. */
21944 if (info_ptr
->vrsave_mask
== 0)
21945 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
21947 /* Because the Darwin register save/restore routines only handle
21948 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
21950 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
21951 && (info_ptr
->first_altivec_reg_save
21952 >= FIRST_SAVED_ALTIVEC_REGNO
));
21959 is_altivec_return_reg (rtx reg
, void *xyes
)
21961 bool *yes
= (bool *) xyes
;
21962 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
21967 /* Look for user-defined global regs in the range FIRST to LAST-1.
21968 We should not restore these, and so cannot use lmw or out-of-line
21969 restore functions if there are any. We also can't save them
21970 (well, emit frame notes for them), because frame unwinding during
21971 exception handling will restore saved registers. */
21974 global_regs_p (unsigned first
, unsigned last
)
21976 while (first
< last
)
21977 if (global_regs
[first
++])
21982 /* Determine the strategy for savings/restoring registers. */
21985 SAVRES_MULTIPLE
= 0x1,
21986 SAVE_INLINE_FPRS
= 0x2,
21987 SAVE_INLINE_GPRS
= 0x4,
21988 REST_INLINE_FPRS
= 0x8,
21989 REST_INLINE_GPRS
= 0x10,
21990 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
21991 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
21992 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
21993 SAVE_INLINE_VRS
= 0x100,
21994 REST_INLINE_VRS
= 0x200
21998 rs6000_savres_strategy (rs6000_stack_t
*info
,
21999 bool using_static_chain_p
)
22004 if (TARGET_MULTIPLE
22005 && !TARGET_POWERPC64
22006 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
22007 && info
->first_gp_reg_save
< 31
22008 && !global_regs_p (info
->first_gp_reg_save
, 32))
22009 strategy
|= SAVRES_MULTIPLE
;
22011 if (crtl
->calls_eh_return
22012 || cfun
->machine
->ra_need_lr
)
22013 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
22014 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
22015 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
22017 if (info
->first_fp_reg_save
== 64
22018 /* The out-of-line FP routines use double-precision stores;
22019 we can't use those routines if we don't have such stores. */
22020 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
22021 || global_regs_p (info
->first_fp_reg_save
, 64))
22022 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
22024 if (info
->first_gp_reg_save
== 32
22025 || (!(strategy
& SAVRES_MULTIPLE
)
22026 && global_regs_p (info
->first_gp_reg_save
, 32)))
22027 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22029 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
22030 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
22031 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22033 /* Define cutoff for using out-of-line functions to save registers. */
22034 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
22036 if (!optimize_size
)
22038 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
22039 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22040 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22044 /* Prefer out-of-line restore if it will exit. */
22045 if (info
->first_fp_reg_save
> 61)
22046 strategy
|= SAVE_INLINE_FPRS
;
22047 if (info
->first_gp_reg_save
> 29)
22049 if (info
->first_fp_reg_save
== 64)
22050 strategy
|= SAVE_INLINE_GPRS
;
22052 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22054 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
22055 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22058 else if (DEFAULT_ABI
== ABI_DARWIN
)
22060 if (info
->first_fp_reg_save
> 60)
22061 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
22062 if (info
->first_gp_reg_save
> 29)
22063 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22064 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22068 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
22069 if (info
->first_fp_reg_save
> 61)
22070 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
22071 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
22072 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
22075 /* Don't bother to try to save things out-of-line if r11 is occupied
22076 by the static chain. It would require too much fiddling and the
22077 static chain is rarely used anyway. FPRs are saved w.r.t the stack
22078 pointer on Darwin, and AIX uses r1 or r12. */
22079 if (using_static_chain_p
22080 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
22081 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
22083 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
22085 /* We can only use the out-of-line routines to restore if we've
22086 saved all the registers from first_fp_reg_save in the prologue.
22087 Otherwise, we risk loading garbage. */
22088 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
22092 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
22093 if (!save_reg_p (i
))
22095 strategy
|= REST_INLINE_FPRS
;
22100 /* If we are going to use store multiple, then don't even bother
22101 with the out-of-line routines, since the store-multiple
22102 instruction will always be smaller. */
22103 if ((strategy
& SAVRES_MULTIPLE
))
22104 strategy
|= SAVE_INLINE_GPRS
;
22106 /* info->lr_save_p isn't yet set if the only reason lr needs to be
22107 saved is an out-of-line save or restore. Set up the value for
22108 the next test (excluding out-of-line gpr restore). */
22109 lr_save_p
= (info
->lr_save_p
22110 || !(strategy
& SAVE_INLINE_GPRS
)
22111 || !(strategy
& SAVE_INLINE_FPRS
)
22112 || !(strategy
& SAVE_INLINE_VRS
)
22113 || !(strategy
& REST_INLINE_FPRS
)
22114 || !(strategy
& REST_INLINE_VRS
));
22116 /* The situation is more complicated with load multiple. We'd
22117 prefer to use the out-of-line routines for restores, since the
22118 "exit" out-of-line routines can handle the restore of LR and the
22119 frame teardown. However if doesn't make sense to use the
22120 out-of-line routine if that is the only reason we'd need to save
22121 LR, and we can't use the "exit" out-of-line gpr restore if we
22122 have saved some fprs; In those cases it is advantageous to use
22123 load multiple when available. */
22124 if ((strategy
& SAVRES_MULTIPLE
)
22126 || info
->first_fp_reg_save
!= 64))
22127 strategy
|= REST_INLINE_GPRS
;
22129 /* Saving CR interferes with the exit routines used on the SPE, so
22132 && info
->spe_64bit_regs_used
22133 && info
->cr_save_p
)
22134 strategy
|= REST_INLINE_GPRS
;
22136 /* We can only use load multiple or the out-of-line routines to
22137 restore if we've used store multiple or out-of-line routines
22138 in the prologue, i.e. if we've saved all the registers from
22139 first_gp_reg_save. Otherwise, we risk loading garbage. */
22140 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
22141 == SAVE_INLINE_GPRS
)
22145 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
22146 if (!save_reg_p (i
))
22148 strategy
|= REST_INLINE_GPRS
;
22153 if (TARGET_ELF
&& TARGET_64BIT
)
22155 if (!(strategy
& SAVE_INLINE_FPRS
))
22156 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
22157 else if (!(strategy
& SAVE_INLINE_GPRS
)
22158 && info
->first_fp_reg_save
== 64)
22159 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
22161 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
22162 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
22164 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
22165 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
22170 /* Calculate the stack information for the current function. This is
22171 complicated by having two separate calling sequences, the AIX calling
22172 sequence and the V.4 calling sequence.
22174 AIX (and Darwin/Mac OS X) stack frames look like:
22176 SP----> +---------------------------------------+
22177 | back chain to caller | 0 0
22178 +---------------------------------------+
22179 | saved CR | 4 8 (8-11)
22180 +---------------------------------------+
22182 +---------------------------------------+
22183 | reserved for compilers | 12 24
22184 +---------------------------------------+
22185 | reserved for binders | 16 32
22186 +---------------------------------------+
22187 | saved TOC pointer | 20 40
22188 +---------------------------------------+
22189 | Parameter save area (P) | 24 48
22190 +---------------------------------------+
22191 | Alloca space (A) | 24+P etc.
22192 +---------------------------------------+
22193 | Local variable space (L) | 24+P+A
22194 +---------------------------------------+
22195 | Float/int conversion temporary (X) | 24+P+A+L
22196 +---------------------------------------+
22197 | Save area for AltiVec registers (W) | 24+P+A+L+X
22198 +---------------------------------------+
22199 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
22200 +---------------------------------------+
22201 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
22202 +---------------------------------------+
22203 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
22204 +---------------------------------------+
22205 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
22206 +---------------------------------------+
22207 old SP->| back chain to caller's caller |
22208 +---------------------------------------+
22210 The required alignment for AIX configurations is two words (i.e., 8
22213 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
22215 SP----> +---------------------------------------+
22216 | Back chain to caller | 0
22217 +---------------------------------------+
22218 | Save area for CR | 8
22219 +---------------------------------------+
22221 +---------------------------------------+
22222 | Saved TOC pointer | 24
22223 +---------------------------------------+
22224 | Parameter save area (P) | 32
22225 +---------------------------------------+
22226 | Alloca space (A) | 32+P
22227 +---------------------------------------+
22228 | Local variable space (L) | 32+P+A
22229 +---------------------------------------+
22230 | Save area for AltiVec registers (W) | 32+P+A+L
22231 +---------------------------------------+
22232 | AltiVec alignment padding (Y) | 32+P+A+L+W
22233 +---------------------------------------+
22234 | Save area for GP registers (G) | 32+P+A+L+W+Y
22235 +---------------------------------------+
22236 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
22237 +---------------------------------------+
22238 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
22239 +---------------------------------------+
22242 V.4 stack frames look like:
22244 SP----> +---------------------------------------+
22245 | back chain to caller | 0
22246 +---------------------------------------+
22247 | caller's saved LR | 4
22248 +---------------------------------------+
22249 | Parameter save area (P) | 8
22250 +---------------------------------------+
22251 | Alloca space (A) | 8+P
22252 +---------------------------------------+
22253 | Varargs save area (V) | 8+P+A
22254 +---------------------------------------+
22255 | Local variable space (L) | 8+P+A+V
22256 +---------------------------------------+
22257 | Float/int conversion temporary (X) | 8+P+A+V+L
22258 +---------------------------------------+
22259 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
22260 +---------------------------------------+
22261 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
22262 +---------------------------------------+
22263 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
22264 +---------------------------------------+
22265 | SPE: area for 64-bit GP registers |
22266 +---------------------------------------+
22267 | SPE alignment padding |
22268 +---------------------------------------+
22269 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
22270 +---------------------------------------+
22271 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
22272 +---------------------------------------+
22273 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
22274 +---------------------------------------+
22275 old SP->| back chain to caller's caller |
22276 +---------------------------------------+
22278 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
22279 given. (But note below and in sysv4.h that we require only 8 and
22280 may round up the size of our stack frame anyways. The historical
22281 reason is early versions of powerpc-linux which didn't properly
22282 align the stack at program startup. A happy side-effect is that
22283 -mno-eabi libraries can be used with -meabi programs.)
22285 The EABI configuration defaults to the V.4 layout. However,
22286 the stack alignment requirements may differ. If -mno-eabi is not
22287 given, the required stack alignment is 8 bytes; if -mno-eabi is
22288 given, the required alignment is 16 bytes. (But see V.4 comment
22291 #ifndef ABI_STACK_BOUNDARY
22292 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
22295 static rs6000_stack_t
*
22296 rs6000_stack_info (void)
22298 /* We should never be called for thunks, we are not set up for that. */
22299 gcc_assert (!cfun
->is_thunk
);
22301 rs6000_stack_t
*info_ptr
= &stack_info
;
22302 int reg_size
= TARGET_32BIT
? 4 : 8;
22307 HOST_WIDE_INT non_fixed_size
;
22308 bool using_static_chain_p
;
22310 if (reload_completed
&& info_ptr
->reload_completed
)
22313 memset (info_ptr
, 0, sizeof (*info_ptr
));
22314 info_ptr
->reload_completed
= reload_completed
;
22318 /* Cache value so we don't rescan instruction chain over and over. */
22319 if (cfun
->machine
->insn_chain_scanned_p
== 0)
22320 cfun
->machine
->insn_chain_scanned_p
22321 = spe_func_has_64bit_regs_p () + 1;
22322 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
22325 /* Select which calling sequence. */
22326 info_ptr
->abi
= DEFAULT_ABI
;
22328 /* Calculate which registers need to be saved & save area size. */
22329 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
22330 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
22331 even if it currently looks like we won't. Reload may need it to
22332 get at a constant; if so, it will have already created a constant
22333 pool entry for it. */
22334 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
22335 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
22336 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
22337 && crtl
->uses_const_pool
22338 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
22339 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
22341 first_gp
= info_ptr
->first_gp_reg_save
;
22343 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
22345 /* For the SPE, we have an additional upper 32-bits on each GPR.
22346 Ideally we should save the entire 64-bits only when the upper
22347 half is used in SIMD instructions. Since we only record
22348 registers live (not the size they are used in), this proves
22349 difficult because we'd have to traverse the instruction chain at
22350 the right time, taking reload into account. This is a real pain,
22351 so we opt to save the GPRs in 64-bits always if but one register
22352 gets used in 64-bits. Otherwise, all the registers in the frame
22353 get saved in 32-bits.
22355 So... since when we save all GPRs (except the SP) in 64-bits, the
22356 traditional GP save area will be empty. */
22357 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
22358 info_ptr
->gp_size
= 0;
22360 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
22361 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
22363 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
22364 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
22365 - info_ptr
->first_altivec_reg_save
);
22367 /* Does this function call anything? */
22368 info_ptr
->calls_p
= (! crtl
->is_leaf
22369 || cfun
->machine
->ra_needs_full_frame
);
22371 /* Determine if we need to save the condition code registers. */
22372 if (df_regs_ever_live_p (CR2_REGNO
)
22373 || df_regs_ever_live_p (CR3_REGNO
)
22374 || df_regs_ever_live_p (CR4_REGNO
))
22376 info_ptr
->cr_save_p
= 1;
22377 if (DEFAULT_ABI
== ABI_V4
)
22378 info_ptr
->cr_size
= reg_size
;
22381 /* If the current function calls __builtin_eh_return, then we need
22382 to allocate stack space for registers that will hold data for
22383 the exception handler. */
22384 if (crtl
->calls_eh_return
)
22387 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
22390 /* SPE saves EH registers in 64-bits. */
22391 ehrd_size
= i
* (TARGET_SPE_ABI
22392 && info_ptr
->spe_64bit_regs_used
!= 0
22393 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
22398 /* In the ELFv2 ABI, we also need to allocate space for separate
22399 CR field save areas if the function calls __builtin_eh_return. */
22400 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
22402 /* This hard-codes that we have three call-saved CR fields. */
22403 ehcr_size
= 3 * reg_size
;
22404 /* We do *not* use the regular CR save mechanism. */
22405 info_ptr
->cr_save_p
= 0;
22410 /* Determine various sizes. */
22411 info_ptr
->reg_size
= reg_size
;
22412 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
22413 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
22414 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
22415 TARGET_ALTIVEC
? 16 : 8);
22416 if (FRAME_GROWS_DOWNWARD
)
22417 info_ptr
->vars_size
22418 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
22419 + info_ptr
->parm_size
,
22420 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
22421 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
22422 + info_ptr
->parm_size
);
22424 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
22425 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
22427 info_ptr
->spe_gp_size
= 0;
22429 if (TARGET_ALTIVEC_ABI
)
22430 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
22432 info_ptr
->vrsave_mask
= 0;
22434 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
22435 info_ptr
->vrsave_size
= 4;
22437 info_ptr
->vrsave_size
= 0;
22439 compute_save_world_info (info_ptr
);
22441 /* Calculate the offsets. */
22442 switch (DEFAULT_ABI
)
22446 gcc_unreachable ();
22451 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
22452 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
22454 if (TARGET_ALTIVEC_ABI
)
22456 info_ptr
->vrsave_save_offset
22457 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
22459 /* Align stack so vector save area is on a quadword boundary.
22460 The padding goes above the vectors. */
22461 if (info_ptr
->altivec_size
!= 0)
22462 info_ptr
->altivec_padding_size
22463 = info_ptr
->vrsave_save_offset
& 0xF;
22465 info_ptr
->altivec_padding_size
= 0;
22467 info_ptr
->altivec_save_offset
22468 = info_ptr
->vrsave_save_offset
22469 - info_ptr
->altivec_padding_size
22470 - info_ptr
->altivec_size
;
22471 gcc_assert (info_ptr
->altivec_size
== 0
22472 || info_ptr
->altivec_save_offset
% 16 == 0);
22474 /* Adjust for AltiVec case. */
22475 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
22478 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
22480 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
22481 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
22482 info_ptr
->lr_save_offset
= 2*reg_size
;
22486 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
22487 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
22488 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
22490 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
22492 /* Align stack so SPE GPR save area is aligned on a
22493 double-word boundary. */
22494 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
22495 info_ptr
->spe_padding_size
22496 = 8 - (-info_ptr
->cr_save_offset
% 8);
22498 info_ptr
->spe_padding_size
= 0;
22500 info_ptr
->spe_gp_save_offset
22501 = info_ptr
->cr_save_offset
22502 - info_ptr
->spe_padding_size
22503 - info_ptr
->spe_gp_size
;
22505 /* Adjust for SPE case. */
22506 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
22508 else if (TARGET_ALTIVEC_ABI
)
22510 info_ptr
->vrsave_save_offset
22511 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
22513 /* Align stack so vector save area is on a quadword boundary. */
22514 if (info_ptr
->altivec_size
!= 0)
22515 info_ptr
->altivec_padding_size
22516 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
22518 info_ptr
->altivec_padding_size
= 0;
22520 info_ptr
->altivec_save_offset
22521 = info_ptr
->vrsave_save_offset
22522 - info_ptr
->altivec_padding_size
22523 - info_ptr
->altivec_size
;
22525 /* Adjust for AltiVec case. */
22526 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
22529 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
22530 info_ptr
->ehrd_offset
-= ehrd_size
;
22531 info_ptr
->lr_save_offset
= reg_size
;
22535 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
22536 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
22537 + info_ptr
->gp_size
22538 + info_ptr
->altivec_size
22539 + info_ptr
->altivec_padding_size
22540 + info_ptr
->spe_gp_size
22541 + info_ptr
->spe_padding_size
22544 + info_ptr
->cr_size
22545 + info_ptr
->vrsave_size
,
22548 non_fixed_size
= (info_ptr
->vars_size
22549 + info_ptr
->parm_size
22550 + info_ptr
->save_size
);
22552 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
22553 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
22555 /* Determine if we need to save the link register. */
22556 if (info_ptr
->calls_p
22557 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22559 && !TARGET_PROFILE_KERNEL
)
22560 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
22561 #ifdef TARGET_RELOCATABLE
22562 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
22564 || rs6000_ra_ever_killed ())
22565 info_ptr
->lr_save_p
= 1;
22567 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
22568 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
22569 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
22570 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
22571 using_static_chain_p
);
22573 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
22574 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
22575 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
22576 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
22577 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
22578 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
22579 info_ptr
->lr_save_p
= 1;
22581 if (info_ptr
->lr_save_p
)
22582 df_set_regs_ever_live (LR_REGNO
, true);
22584 /* Determine if we need to allocate any stack frame:
22586 For AIX we need to push the stack if a frame pointer is needed
22587 (because the stack might be dynamically adjusted), if we are
22588 debugging, if we make calls, or if the sum of fp_save, gp_save,
22589 and local variables are more than the space needed to save all
22590 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
22591 + 18*8 = 288 (GPR13 reserved).
22593 For V.4 we don't have the stack cushion that AIX uses, but assume
22594 that the debugger can handle stackless frames. */
22596 if (info_ptr
->calls_p
)
22597 info_ptr
->push_p
= 1;
22599 else if (DEFAULT_ABI
== ABI_V4
)
22600 info_ptr
->push_p
= non_fixed_size
!= 0;
22602 else if (frame_pointer_needed
)
22603 info_ptr
->push_p
= 1;
22605 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
22606 info_ptr
->push_p
= 1;
22609 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
22614 /* Return true if the current function uses any GPRs in 64-bit SIMD
22618 spe_func_has_64bit_regs_p (void)
22620 rtx_insn
*insns
, *insn
;
22622 /* Functions that save and restore all the call-saved registers will
22623 need to save/restore the registers in 64-bits. */
22624 if (crtl
->calls_eh_return
22625 || cfun
->calls_setjmp
22626 || crtl
->has_nonlocal_goto
)
22629 insns
= get_insns ();
22631 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
22637 /* FIXME: This should be implemented with attributes...
22639 (set_attr "spe64" "true")....then,
22640 if (get_spe64(insn)) return true;
22642 It's the only reliable way to do the stuff below. */
22644 i
= PATTERN (insn
);
22645 if (GET_CODE (i
) == SET
)
22647 machine_mode mode
= GET_MODE (SET_SRC (i
));
22649 if (SPE_VECTOR_MODE (mode
))
22651 if (TARGET_E500_DOUBLE
22652 && (mode
== DFmode
|| FLOAT128_2REG_P (mode
)))
22662 debug_stack_info (rs6000_stack_t
*info
)
22664 const char *abi_string
;
22667 info
= rs6000_stack_info ();
22669 fprintf (stderr
, "\nStack information for function %s:\n",
22670 ((current_function_decl
&& DECL_NAME (current_function_decl
))
22671 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
22676 default: abi_string
= "Unknown"; break;
22677 case ABI_NONE
: abi_string
= "NONE"; break;
22678 case ABI_AIX
: abi_string
= "AIX"; break;
22679 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
22680 case ABI_DARWIN
: abi_string
= "Darwin"; break;
22681 case ABI_V4
: abi_string
= "V.4"; break;
22684 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
22686 if (TARGET_ALTIVEC_ABI
)
22687 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
22689 if (TARGET_SPE_ABI
)
22690 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
22692 if (info
->first_gp_reg_save
!= 32)
22693 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
22695 if (info
->first_fp_reg_save
!= 64)
22696 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
22698 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
22699 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
22700 info
->first_altivec_reg_save
);
22702 if (info
->lr_save_p
)
22703 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
22705 if (info
->cr_save_p
)
22706 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
22708 if (info
->vrsave_mask
)
22709 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
22712 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
22715 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
22718 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
22721 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
22723 if (info
->altivec_size
)
22724 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
22725 info
->altivec_save_offset
);
22727 if (info
->spe_gp_size
)
22728 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
22729 info
->spe_gp_save_offset
);
22731 if (info
->vrsave_size
)
22732 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
22733 info
->vrsave_save_offset
);
22735 if (info
->lr_save_p
)
22736 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
22738 if (info
->cr_save_p
)
22739 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
22741 if (info
->varargs_save_offset
)
22742 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
22744 if (info
->total_size
)
22745 fprintf (stderr
, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
22748 if (info
->vars_size
)
22749 fprintf (stderr
, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
22752 if (info
->parm_size
)
22753 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
22755 if (info
->fixed_size
)
22756 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
22759 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
22761 if (info
->spe_gp_size
)
22762 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
22765 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
22767 if (info
->altivec_size
)
22768 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
22770 if (info
->vrsave_size
)
22771 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
22773 if (info
->altivec_padding_size
)
22774 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
22775 info
->altivec_padding_size
);
22777 if (info
->spe_padding_size
)
22778 fprintf (stderr
, "\tspe_padding_size = %5d\n",
22779 info
->spe_padding_size
);
22782 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
22784 if (info
->save_size
)
22785 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
22787 if (info
->reg_size
!= 4)
22788 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
22790 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
22792 fprintf (stderr
, "\n");
22796 rs6000_return_addr (int count
, rtx frame
)
22798 /* Currently we don't optimize very well between prolog and body
22799 code and for PIC code the code can be actually quite bad, so
22800 don't try to be too clever here. */
22802 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
22804 cfun
->machine
->ra_needs_full_frame
= 1;
22811 plus_constant (Pmode
,
22813 (gen_rtx_MEM (Pmode
,
22814 memory_address (Pmode
, frame
))),
22815 RETURN_ADDRESS_OFFSET
)));
22818 cfun
->machine
->ra_need_lr
= 1;
22819 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
22822 /* Say whether a function is a candidate for sibcall handling or not. */
22825 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
22830 fntype
= TREE_TYPE (decl
);
22832 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
22834 /* We can't do it if the called function has more vector parameters
22835 than the current function; there's nowhere to put the VRsave code. */
22836 if (TARGET_ALTIVEC_ABI
22837 && TARGET_ALTIVEC_VRSAVE
22838 && !(decl
&& decl
== current_function_decl
))
22840 function_args_iterator args_iter
;
22844 /* Functions with vector parameters are required to have a
22845 prototype, so the argument type info must be available
22847 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
22848 if (TREE_CODE (type
) == VECTOR_TYPE
22849 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
22852 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
22853 if (TREE_CODE (type
) == VECTOR_TYPE
22854 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
22861 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
22862 functions, because the callee may have a different TOC pointer to
22863 the caller and there's no way to ensure we restore the TOC when
22864 we return. With the secure-plt SYSV ABI we can't make non-local
22865 calls when -fpic/PIC because the plt call stubs use r30. */
22866 if (DEFAULT_ABI
== ABI_DARWIN
22867 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22869 && !DECL_EXTERNAL (decl
)
22870 && !DECL_WEAK (decl
)
22871 && (*targetm
.binds_local_p
) (decl
))
22872 || (DEFAULT_ABI
== ABI_V4
22873 && (!TARGET_SECURE_PLT
22876 && (*targetm
.binds_local_p
) (decl
)))))
22878 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
22880 if (!lookup_attribute ("longcall", attr_list
)
22881 || lookup_attribute ("shortcall", attr_list
))
22889 rs6000_ra_ever_killed (void)
22895 if (cfun
->is_thunk
)
22898 if (cfun
->machine
->lr_save_state
)
22899 return cfun
->machine
->lr_save_state
- 1;
22901 /* regs_ever_live has LR marked as used if any sibcalls are present,
22902 but this should not force saving and restoring in the
22903 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
22904 clobbers LR, so that is inappropriate. */
22906 /* Also, the prologue can generate a store into LR that
22907 doesn't really count, like this:
22910 bcl to set PIC register
22914 When we're called from the epilogue, we need to avoid counting
22915 this as a store. */
22917 push_topmost_sequence ();
22918 top
= get_insns ();
22919 pop_topmost_sequence ();
22920 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
22922 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
22928 if (!SIBLING_CALL_P (insn
))
22931 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
22933 else if (set_of (reg
, insn
) != NULL_RTX
22934 && !prologue_epilogue_contains (insn
))
22941 /* Emit instructions needed to load the TOC register.
22942 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
22943 a constant pool; or for SVR4 -fpic. */
22946 rs6000_emit_load_toc_table (int fromprolog
)
22949 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
22951 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
22954 rtx lab
, tmp1
, tmp2
, got
;
22956 lab
= gen_label_rtx ();
22957 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
22958 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
22960 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
22962 got
= rs6000_got_sym ();
22963 tmp1
= tmp2
= dest
;
22966 tmp1
= gen_reg_rtx (Pmode
);
22967 tmp2
= gen_reg_rtx (Pmode
);
22969 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
22970 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
22971 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
22972 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
22974 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
22976 emit_insn (gen_load_toc_v4_pic_si ());
22977 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
22979 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
22982 rtx temp0
= (fromprolog
22983 ? gen_rtx_REG (Pmode
, 0)
22984 : gen_reg_rtx (Pmode
));
22990 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
22991 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
22993 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
22994 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
22996 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
22997 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
22998 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
23004 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
23005 lab
= gen_label_rtx ();
23006 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
23007 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
23008 if (TARGET_LINK_STACK
)
23009 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
23010 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
23012 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
23014 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
23016 /* This is for AIX code running in non-PIC ELF32. */
23019 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
23020 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
23022 emit_insn (gen_elf_high (dest
, realsym
));
23023 emit_insn (gen_elf_low (dest
, dest
, realsym
));
23027 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23030 emit_insn (gen_load_toc_aix_si (dest
));
23032 emit_insn (gen_load_toc_aix_di (dest
));
23036 /* Emit instructions to restore the link register after determining where
23037 its value has been stored. */
23040 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
23042 rs6000_stack_t
*info
= rs6000_stack_info ();
23045 operands
[0] = source
;
23046 operands
[1] = scratch
;
23048 if (info
->lr_save_p
)
23050 rtx frame_rtx
= stack_pointer_rtx
;
23051 HOST_WIDE_INT sp_offset
= 0;
23054 if (frame_pointer_needed
23055 || cfun
->calls_alloca
23056 || info
->total_size
> 32767)
23058 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
23059 emit_move_insn (operands
[1], tmp
);
23060 frame_rtx
= operands
[1];
23062 else if (info
->push_p
)
23063 sp_offset
= info
->total_size
;
23065 tmp
= plus_constant (Pmode
, frame_rtx
,
23066 info
->lr_save_offset
+ sp_offset
);
23067 tmp
= gen_frame_mem (Pmode
, tmp
);
23068 emit_move_insn (tmp
, operands
[0]);
23071 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
23073 /* Freeze lr_save_p. We've just emitted rtl that depends on the
23074 state of lr_save_p so any change from here on would be a bug. In
23075 particular, stop rs6000_ra_ever_killed from considering the SET
23076 of lr we may have added just above. */
23077 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
23080 static GTY(()) alias_set_type set
= -1;
23083 get_TOC_alias_set (void)
23086 set
= new_alias_set ();
23090 /* This returns nonzero if the current function uses the TOC. This is
23091 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
23092 is generated by the ABI_V4 load_toc_* patterns. */
23099 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
23102 rtx pat
= PATTERN (insn
);
23105 if (GET_CODE (pat
) == PARALLEL
)
23106 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
23108 rtx sub
= XVECEXP (pat
, 0, i
);
23109 if (GET_CODE (sub
) == USE
)
23111 sub
= XEXP (sub
, 0);
23112 if (GET_CODE (sub
) == UNSPEC
23113 && XINT (sub
, 1) == UNSPEC_TOC
)
23123 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
23125 rtx tocrel
, tocreg
, hi
;
23127 if (TARGET_DEBUG_ADDR
)
23129 if (GET_CODE (symbol
) == SYMBOL_REF
)
23130 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
23134 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
23135 GET_RTX_NAME (GET_CODE (symbol
)));
23136 debug_rtx (symbol
);
23140 if (!can_create_pseudo_p ())
23141 df_set_regs_ever_live (TOC_REGISTER
, true);
23143 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
23144 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
23145 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
23148 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
23149 if (largetoc_reg
!= NULL
)
23151 emit_move_insn (largetoc_reg
, hi
);
23154 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
23157 /* Issue assembly directives that create a reference to the given DWARF
23158 FRAME_TABLE_LABEL from the current function section. */
23160 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
23162 fprintf (asm_out_file
, "\t.ref %s\n",
23163 (* targetm
.strip_name_encoding
) (frame_table_label
));
23166 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
23167 and the change to the stack pointer. */
23170 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
23177 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
23178 if (hard_frame_needed
)
23179 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
23180 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
23181 || (hard_frame_needed
23182 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
23185 p
= rtvec_alloc (i
);
23188 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
23189 RTVEC_ELT (p
, i
) = gen_rtx_SET (mem
, const0_rtx
);
23192 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
23195 /* Emit the correct code for allocating stack space, as insns.
23196 If COPY_REG, make sure a copy of the old frame is left there.
23197 The generated code may use hard register 0 as a temporary. */
23200 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
23203 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
23204 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
23205 rtx todec
= gen_int_mode (-size
, Pmode
);
23208 if (INTVAL (todec
) != -size
)
23210 warning (0, "stack frame too large");
23211 emit_insn (gen_trap ());
23215 if (crtl
->limit_stack
)
23217 if (REG_P (stack_limit_rtx
)
23218 && REGNO (stack_limit_rtx
) > 1
23219 && REGNO (stack_limit_rtx
) <= 31)
23221 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
23222 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
23225 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
23227 && DEFAULT_ABI
== ABI_V4
)
23229 rtx toload
= gen_rtx_CONST (VOIDmode
,
23230 gen_rtx_PLUS (Pmode
,
23234 emit_insn (gen_elf_high (tmp_reg
, toload
));
23235 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
23236 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
23240 warning (0, "stack limit expression is not supported");
23246 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
23248 emit_move_insn (copy_reg
, stack_reg
);
23253 /* Need a note here so that try_split doesn't get confused. */
23254 if (get_last_insn () == NULL_RTX
)
23255 emit_note (NOTE_INSN_DELETED
);
23256 insn
= emit_move_insn (tmp_reg
, todec
);
23257 try_split (PATTERN (insn
), insn
, 0);
23261 insn
= emit_insn (TARGET_32BIT
23262 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
23264 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
23265 todec
, stack_reg
));
23266 /* Since we didn't use gen_frame_mem to generate the MEM, grab
23267 it now and set the alias set/attributes. The above gen_*_update
23268 calls will generate a PARALLEL with the MEM set being the first
23270 par
= PATTERN (insn
);
23271 gcc_assert (GET_CODE (par
) == PARALLEL
);
23272 set
= XVECEXP (par
, 0, 0);
23273 gcc_assert (GET_CODE (set
) == SET
);
23274 mem
= SET_DEST (set
);
23275 gcc_assert (MEM_P (mem
));
23276 MEM_NOTRAP_P (mem
) = 1;
23277 set_mem_alias_set (mem
, get_frame_alias_set ());
23279 RTX_FRAME_RELATED_P (insn
) = 1;
23280 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
23281 gen_rtx_SET (stack_reg
, gen_rtx_PLUS (Pmode
, stack_reg
,
23282 GEN_INT (-size
))));
23286 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
23288 #if PROBE_INTERVAL > 32768
23289 #error Cannot use indexed addressing mode for stack probing
23292 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
23293 inclusive. These are offsets from the current stack pointer. */
23296 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
23298 /* See if we have a constant small number of probes to generate. If so,
23299 that's the easy case. */
23300 if (first
+ size
<= 32768)
23304 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
23305 it exceeds SIZE. If only one probe is needed, this will not
23306 generate any code. Then probe at FIRST + SIZE. */
23307 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
23308 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
23311 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
23315 /* Otherwise, do the same as above, but in a loop. Note that we must be
23316 extra careful with variables wrapping around because we might be at
23317 the very top (or the very bottom) of the address space and we have
23318 to be able to handle this case properly; in particular, we use an
23319 equality test for the loop condition. */
23322 HOST_WIDE_INT rounded_size
;
23323 rtx r12
= gen_rtx_REG (Pmode
, 12);
23324 rtx r0
= gen_rtx_REG (Pmode
, 0);
23326 /* Sanity check for the addressing mode we're going to use. */
23327 gcc_assert (first
<= 32768);
23329 /* Step 1: round SIZE to the previous multiple of the interval. */
23331 rounded_size
= size
& -PROBE_INTERVAL
;
23334 /* Step 2: compute initial and final value of the loop counter. */
23336 /* TEST_ADDR = SP + FIRST. */
23337 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, stack_pointer_rtx
,
23340 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
23341 if (rounded_size
> 32768)
23343 emit_move_insn (r0
, GEN_INT (-rounded_size
));
23344 emit_insn (gen_rtx_SET (r0
, gen_rtx_PLUS (Pmode
, r12
, r0
)));
23347 emit_insn (gen_rtx_SET (r0
, plus_constant (Pmode
, r12
,
23351 /* Step 3: the loop
23353 while (TEST_ADDR != LAST_ADDR)
23355 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
23359 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
23360 until it is equal to ROUNDED_SIZE. */
23363 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
23365 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
23368 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
23369 that SIZE is equal to ROUNDED_SIZE. */
23371 if (size
!= rounded_size
)
23372 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
23376 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
23377 absolute addresses. */
23380 output_probe_stack_range (rtx reg1
, rtx reg2
)
23382 static int labelno
= 0;
23383 char loop_lab
[32], end_lab
[32];
23386 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
23387 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
23389 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
23391 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
23395 output_asm_insn ("cmpd 0,%0,%1", xops
);
23397 output_asm_insn ("cmpw 0,%0,%1", xops
);
23399 fputs ("\tbeq 0,", asm_out_file
);
23400 assemble_name_raw (asm_out_file
, end_lab
);
23401 fputc ('\n', asm_out_file
);
23403 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
23404 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
23405 output_asm_insn ("addi %0,%0,%1", xops
);
23407 /* Probe at TEST_ADDR and branch. */
23408 xops
[1] = gen_rtx_REG (Pmode
, 0);
23409 output_asm_insn ("stw %1,0(%0)", xops
);
23410 fprintf (asm_out_file
, "\tb ");
23411 assemble_name_raw (asm_out_file
, loop_lab
);
23412 fputc ('\n', asm_out_file
);
23414 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
23419 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
23420 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
23421 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
23422 deduce these equivalences by itself so it wasn't necessary to hold
23423 its hand so much. Don't be tempted to always supply d2_f_d_e with
23424 the actual cfa register, ie. r31 when we are using a hard frame
23425 pointer. That fails when saving regs off r1, and sched moves the
23426 r31 setup past the reg saves. */
23429 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
23430 rtx reg2
, rtx rreg
)
23434 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
23436 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
23439 gcc_checking_assert (val
== 0);
23440 real
= PATTERN (insn
);
23441 if (GET_CODE (real
) == PARALLEL
)
23442 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
23443 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
23445 rtx set
= XVECEXP (real
, 0, i
);
23447 RTX_FRAME_RELATED_P (set
) = 1;
23449 RTX_FRAME_RELATED_P (insn
) = 1;
23453 /* copy_rtx will not make unique copies of registers, so we need to
23454 ensure we don't have unwanted sharing here. */
23456 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
23459 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
23461 real
= copy_rtx (PATTERN (insn
));
23463 if (reg2
!= NULL_RTX
)
23464 real
= replace_rtx (real
, reg2
, rreg
);
23466 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
23467 gcc_checking_assert (val
== 0);
23469 real
= replace_rtx (real
, reg
,
23470 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
23471 STACK_POINTER_REGNUM
),
23474 /* We expect that 'real' is either a SET or a PARALLEL containing
23475 SETs (and possibly other stuff). In a PARALLEL, all the SETs
23476 are important so they all have to be marked RTX_FRAME_RELATED_P. */
23478 if (GET_CODE (real
) == SET
)
23482 temp
= simplify_rtx (SET_SRC (set
));
23484 SET_SRC (set
) = temp
;
23485 temp
= simplify_rtx (SET_DEST (set
));
23487 SET_DEST (set
) = temp
;
23488 if (GET_CODE (SET_DEST (set
)) == MEM
)
23490 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
23492 XEXP (SET_DEST (set
), 0) = temp
;
23499 gcc_assert (GET_CODE (real
) == PARALLEL
);
23500 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
23501 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
23503 rtx set
= XVECEXP (real
, 0, i
);
23505 temp
= simplify_rtx (SET_SRC (set
));
23507 SET_SRC (set
) = temp
;
23508 temp
= simplify_rtx (SET_DEST (set
));
23510 SET_DEST (set
) = temp
;
23511 if (GET_CODE (SET_DEST (set
)) == MEM
)
23513 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
23515 XEXP (SET_DEST (set
), 0) = temp
;
23517 RTX_FRAME_RELATED_P (set
) = 1;
23521 RTX_FRAME_RELATED_P (insn
) = 1;
23522 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
23527 /* Returns an insn that has a vrsave set operation with the
23528 appropriate CLOBBERs. */
23531 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
23534 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
23535 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
23538 = gen_rtx_SET (vrsave
,
23539 gen_rtx_UNSPEC_VOLATILE (SImode
,
23540 gen_rtvec (2, reg
, vrsave
),
23541 UNSPECV_SET_VRSAVE
));
23545 /* We need to clobber the registers in the mask so the scheduler
23546 does not move sets to VRSAVE before sets of AltiVec registers.
23548 However, if the function receives nonlocal gotos, reload will set
23549 all call saved registers live. We will end up with:
23551 (set (reg 999) (mem))
23552 (parallel [ (set (reg vrsave) (unspec blah))
23553 (clobber (reg 999))])
23555 The clobber will cause the store into reg 999 to be dead, and
23556 flow will attempt to delete an epilogue insn. In this case, we
23557 need an unspec use/set of the register. */
23559 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23560 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23562 if (!epiloguep
|| call_used_regs
[i
])
23563 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
23564 gen_rtx_REG (V4SImode
, i
));
23567 rtx reg
= gen_rtx_REG (V4SImode
, i
);
23570 = gen_rtx_SET (reg
,
23571 gen_rtx_UNSPEC (V4SImode
,
23572 gen_rtvec (1, reg
), 27));
23576 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
23578 for (i
= 0; i
< nclobs
; ++i
)
23579 XVECEXP (insn
, 0, i
) = clobs
[i
];
23585 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
23589 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
23590 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
23591 return gen_rtx_SET (store
? mem
: reg
, store
? reg
: mem
);
23595 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
23597 return gen_frame_set (reg
, frame_reg
, offset
, false);
23601 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
23603 return gen_frame_set (reg
, frame_reg
, offset
, true);
23606 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
23607 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
23610 emit_frame_save (rtx frame_reg
, machine_mode mode
,
23611 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
23615 /* Some cases that need register indexed addressing. */
23616 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
23617 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
23618 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
23620 && SPE_VECTOR_MODE (mode
)
23621 && !SPE_CONST_OFFSET_OK (offset
))));
23623 reg
= gen_rtx_REG (mode
, regno
);
23624 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
23625 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
23626 NULL_RTX
, NULL_RTX
);
23629 /* Emit an offset memory reference suitable for a frame store, while
23630 converting to a valid addressing mode. */
23633 gen_frame_mem_offset (machine_mode mode
, rtx reg
, int offset
)
23635 rtx int_rtx
, offset_rtx
;
23637 int_rtx
= GEN_INT (offset
);
23639 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
23640 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
23642 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
23643 emit_move_insn (offset_rtx
, int_rtx
);
23646 offset_rtx
= int_rtx
;
23648 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
23651 #ifndef TARGET_FIX_AND_CONTINUE
23652 #define TARGET_FIX_AND_CONTINUE 0
23655 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
23656 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
23657 #define LAST_SAVRES_REGISTER 31
23658 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
23669 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
23671 /* Temporary holding space for an out-of-line register save/restore
23673 static char savres_routine_name
[30];
23675 /* Return the name for an out-of-line register save/restore routine.
23676 We are saving/restoring GPRs if GPR is true. */
23679 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
23681 const char *prefix
= "";
23682 const char *suffix
= "";
23684 /* Different targets are supposed to define
23685 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
23686 routine name could be defined with:
23688 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
23690 This is a nice idea in practice, but in reality, things are
23691 complicated in several ways:
23693 - ELF targets have save/restore routines for GPRs.
23695 - SPE targets use different prefixes for 32/64-bit registers, and
23696 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
23698 - PPC64 ELF targets have routines for save/restore of GPRs that
23699 differ in what they do with the link register, so having a set
23700 prefix doesn't work. (We only use one of the save routines at
23701 the moment, though.)
23703 - PPC32 elf targets have "exit" versions of the restore routines
23704 that restore the link register and can save some extra space.
23705 These require an extra suffix. (There are also "tail" versions
23706 of the restore routines and "GOT" versions of the save routines,
23707 but we don't generate those at present. Same problems apply,
23710 We deal with all this by synthesizing our own prefix/suffix and
23711 using that for the simple sprintf call shown above. */
23714 /* No floating point saves on the SPE. */
23715 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
23717 if ((sel
& SAVRES_SAVE
))
23718 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
23720 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
23722 if ((sel
& SAVRES_LR
))
23725 else if (DEFAULT_ABI
== ABI_V4
)
23730 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
23731 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
23732 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
23733 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
23734 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
23735 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
23739 if ((sel
& SAVRES_LR
))
23742 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23744 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
23745 /* No out-of-line save/restore routines for GPRs on AIX. */
23746 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
23750 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
23751 prefix
= ((sel
& SAVRES_SAVE
)
23752 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
23753 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
23754 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
23756 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
23757 if ((sel
& SAVRES_LR
))
23758 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
23762 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
23763 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
23766 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
23767 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
23772 if (DEFAULT_ABI
== ABI_DARWIN
)
23774 /* The Darwin approach is (slightly) different, in order to be
23775 compatible with code generated by the system toolchain. There is a
23776 single symbol for the start of save sequence, and the code here
23777 embeds an offset into that code on the basis of the first register
23779 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
23780 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
23781 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
23782 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
23783 (regno
- 13) * 4, prefix
, regno
);
23784 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
23785 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
23786 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
23787 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
23788 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
23789 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
23794 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
23796 return savres_routine_name
;
23799 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
23800 We are saving/restoring GPRs if GPR is true. */
23803 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
23805 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
23806 ? info
->first_gp_reg_save
23807 : (sel
& SAVRES_REG
) == SAVRES_FPR
23808 ? info
->first_fp_reg_save
- 32
23809 : (sel
& SAVRES_REG
) == SAVRES_VR
23810 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
23815 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
23816 versions of the gpr routines. */
23817 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
23818 && info
->spe_64bit_regs_used
)
23819 select
^= SAVRES_FPR
^ SAVRES_GPR
;
23821 /* Don't generate bogus routine names. */
23822 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
23823 && regno
<= LAST_SAVRES_REGISTER
23824 && select
>= 0 && select
<= 12);
23826 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
23832 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23834 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
23835 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
23836 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
23842 /* Emit a sequence of insns, including a stack tie if needed, for
23843 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
23844 reset the stack pointer, but move the base of the frame into
23845 reg UPDT_REGNO for use by out-of-line register restore routines. */
23848 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
23849 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
23850 unsigned updt_regno
)
23854 /* This blockage is needed so that sched doesn't decide to move
23855 the sp change before the register restores. */
23856 if (DEFAULT_ABI
== ABI_V4
23858 && info
->spe_64bit_regs_used
!= 0
23859 && info
->first_gp_reg_save
!= 32))
23860 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
23862 /* If we are restoring registers out-of-line, we will be using the
23863 "exit" variants of the restore routines, which will reset the
23864 stack for us. But we do need to point updt_reg into the
23865 right place for those routines. */
23866 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
23868 if (frame_off
!= 0)
23869 return emit_insn (gen_add3_insn (updt_reg_rtx
,
23870 frame_reg_rtx
, GEN_INT (frame_off
)));
23871 else if (REGNO (frame_reg_rtx
) != updt_regno
)
23872 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
23877 /* Return the register number used as a pointer by out-of-line
23878 save/restore functions. */
23880 static inline unsigned
23881 ptr_regno_for_savres (int sel
)
23883 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23884 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
23885 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
23888 /* Construct a parallel rtx describing the effect of a call to an
23889 out-of-line register save/restore routine, and emit the insn
23890 or jump_insn as appropriate. */
23893 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
23894 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
23895 machine_mode reg_mode
, int sel
)
23898 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
23899 int reg_size
= GET_MODE_SIZE (reg_mode
);
23905 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
23906 ? info
->first_gp_reg_save
23907 : (sel
& SAVRES_REG
) == SAVRES_FPR
23908 ? info
->first_fp_reg_save
23909 : (sel
& SAVRES_REG
) == SAVRES_VR
23910 ? info
->first_altivec_reg_save
23912 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
23914 : (sel
& SAVRES_REG
) == SAVRES_FPR
23916 : (sel
& SAVRES_REG
) == SAVRES_VR
23917 ? LAST_ALTIVEC_REGNO
+ 1
23919 n_regs
= end_reg
- start_reg
;
23920 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
23921 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
23924 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
23925 RTVEC_ELT (p
, offset
++) = ret_rtx
;
23927 RTVEC_ELT (p
, offset
++)
23928 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
23930 sym
= rs6000_savres_routine_sym (info
, sel
);
23931 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
23933 use_reg
= ptr_regno_for_savres (sel
);
23934 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
23936 /* Vector regs are saved/restored using [reg+reg] addressing. */
23937 RTVEC_ELT (p
, offset
++)
23938 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
23939 RTVEC_ELT (p
, offset
++)
23940 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
23943 RTVEC_ELT (p
, offset
++)
23944 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
23946 for (i
= 0; i
< end_reg
- start_reg
; i
++)
23947 RTVEC_ELT (p
, i
+ offset
)
23948 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
23949 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
23950 (sel
& SAVRES_SAVE
) != 0);
23952 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
23953 RTVEC_ELT (p
, i
+ offset
)
23954 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
23956 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
23958 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
23960 insn
= emit_jump_insn (par
);
23961 JUMP_LABEL (insn
) = ret_rtx
;
23964 insn
= emit_insn (par
);
23968 /* Emit code to store CR fields that need to be saved into REG. */
23971 rs6000_emit_move_from_cr (rtx reg
)
23973 /* Only the ELFv2 ABI allows storing only selected fields. */
23974 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
23976 int i
, cr_reg
[8], count
= 0;
23978 /* Collect CR fields that must be saved. */
23979 for (i
= 0; i
< 8; i
++)
23980 if (save_reg_p (CR0_REGNO
+ i
))
23981 cr_reg
[count
++] = i
;
23983 /* If it's just a single one, use mfcrf. */
23986 rtvec p
= rtvec_alloc (1);
23987 rtvec r
= rtvec_alloc (2);
23988 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
23989 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
23991 = gen_rtx_SET (reg
,
23992 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
23994 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23998 /* ??? It might be better to handle count == 2 / 3 cases here
23999 as well, using logical operations to combine the values. */
24002 emit_insn (gen_movesi_from_cr (reg
));
24005 /* Determine whether the gp REG is really used. */
24008 rs6000_reg_live_or_pic_offset_p (int reg
)
24010 /* If the function calls eh_return, claim used all the registers that would
24011 be checked for liveness otherwise. This is required for the PIC offset
24012 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
24013 register allocation purposes in this case. */
24015 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
24016 && (!call_used_regs
[reg
]
24017 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
24018 && !TARGET_SINGLE_PIC_BASE
24019 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
24020 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
24021 && !TARGET_SINGLE_PIC_BASE
24022 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
24023 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
24026 /* Return whether the split-stack arg pointer (r12) is used. */
24029 split_stack_arg_pointer_used_p (void)
24031 /* If the pseudo holding the arg pointer is no longer a pseudo,
24032 then the arg pointer is used. */
24033 if (cfun
->machine
->split_stack_arg_pointer
!= NULL_RTX
24034 && (!REG_P (cfun
->machine
->split_stack_arg_pointer
)
24035 || (REGNO (cfun
->machine
->split_stack_arg_pointer
)
24036 < FIRST_PSEUDO_REGISTER
)))
24039 /* Unfortunately we also need to do some code scanning, since
24040 r12 may have been substituted for the pseudo. */
24042 basic_block bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
;
24043 FOR_BB_INSNS (bb
, insn
)
24044 if (NONDEBUG_INSN_P (insn
))
24046 /* A call destroys r12. */
24051 FOR_EACH_INSN_USE (use
, insn
)
24053 rtx x
= DF_REF_REG (use
);
24054 if (REG_P (x
) && REGNO (x
) == 12)
24058 FOR_EACH_INSN_DEF (def
, insn
)
24060 rtx x
= DF_REF_REG (def
);
24061 if (REG_P (x
) && REGNO (x
) == 12)
24065 return bitmap_bit_p (DF_LR_OUT (bb
), 12);
24068 /* Emit function prologue as insns. */
24071 rs6000_emit_prologue (void)
24073 rs6000_stack_t
*info
= rs6000_stack_info ();
24074 machine_mode reg_mode
= Pmode
;
24075 int reg_size
= TARGET_32BIT
? 4 : 8;
24076 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
24077 rtx frame_reg_rtx
= sp_reg_rtx
;
24078 unsigned int cr_save_regno
;
24079 rtx cr_save_rtx
= NULL_RTX
;
24082 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
24083 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
24084 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
24085 int using_split_stack
= (flag_split_stack
24086 && (lookup_attribute ("no_split_stack",
24087 DECL_ATTRIBUTES (cfun
->decl
))
24090 /* Offset to top of frame for frame_reg and sp respectively. */
24091 HOST_WIDE_INT frame_off
= 0;
24092 HOST_WIDE_INT sp_off
= 0;
24093 /* sp_adjust is the stack adjusting instruction, tracked so that the
24094 insn setting up the split-stack arg pointer can be emitted just
24095 prior to it, when r12 is not used here for other purposes. */
24096 rtx_insn
*sp_adjust
= 0;
24098 #ifdef ENABLE_CHECKING
24099 /* Track and check usage of r0, r11, r12. */
24100 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
24101 #define START_USE(R) do \
24103 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
24104 reg_inuse |= 1 << (R); \
24106 #define END_USE(R) do \
24108 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
24109 reg_inuse &= ~(1 << (R)); \
24111 #define NOT_INUSE(R) do \
24113 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
24116 #define START_USE(R) do {} while (0)
24117 #define END_USE(R) do {} while (0)
24118 #define NOT_INUSE(R) do {} while (0)
24121 if (DEFAULT_ABI
== ABI_ELFv2
)
24123 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
24125 /* With -mminimal-toc we may generate an extra use of r2 below. */
24126 if (!TARGET_SINGLE_PIC_BASE
24127 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
24128 cfun
->machine
->r2_setup_needed
= true;
24132 if (flag_stack_usage_info
)
24133 current_function_static_stack_size
= info
->total_size
;
24135 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
24137 HOST_WIDE_INT size
= info
->total_size
;
24139 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
24141 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
24142 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
24143 size
- STACK_CHECK_PROTECT
);
24146 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
24149 if (TARGET_FIX_AND_CONTINUE
)
24151 /* gdb on darwin arranges to forward a function from the old
24152 address by modifying the first 5 instructions of the function
24153 to branch to the overriding function. This is necessary to
24154 permit function pointers that point to the old function to
24155 actually forward to the new function. */
24156 emit_insn (gen_nop ());
24157 emit_insn (gen_nop ());
24158 emit_insn (gen_nop ());
24159 emit_insn (gen_nop ());
24160 emit_insn (gen_nop ());
24163 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
24165 reg_mode
= V2SImode
;
24169 /* Handle world saves specially here. */
24170 if (WORLD_SAVE_P (info
))
24177 /* save_world expects lr in r0. */
24178 reg0
= gen_rtx_REG (Pmode
, 0);
24179 if (info
->lr_save_p
)
24181 insn
= emit_move_insn (reg0
,
24182 gen_rtx_REG (Pmode
, LR_REGNO
));
24183 RTX_FRAME_RELATED_P (insn
) = 1;
24186 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
24187 assumptions about the offsets of various bits of the stack
24189 gcc_assert (info
->gp_save_offset
== -220
24190 && info
->fp_save_offset
== -144
24191 && info
->lr_save_offset
== 8
24192 && info
->cr_save_offset
== 4
24195 && (!crtl
->calls_eh_return
24196 || info
->ehrd_offset
== -432)
24197 && info
->vrsave_save_offset
== -224
24198 && info
->altivec_save_offset
== -416);
24200 treg
= gen_rtx_REG (SImode
, 11);
24201 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
24203 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
24204 in R11. It also clobbers R12, so beware! */
24206 /* Preserve CR2 for save_world prologues */
24208 sz
+= 32 - info
->first_gp_reg_save
;
24209 sz
+= 64 - info
->first_fp_reg_save
;
24210 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
24211 p
= rtvec_alloc (sz
);
24213 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
24214 gen_rtx_REG (SImode
,
24216 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
24217 gen_rtx_SYMBOL_REF (Pmode
,
24219 /* We do floats first so that the instruction pattern matches
24221 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24223 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24225 info
->first_fp_reg_save
+ i
),
24227 info
->fp_save_offset
+ frame_off
+ 8 * i
);
24228 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
24230 = gen_frame_store (gen_rtx_REG (V4SImode
,
24231 info
->first_altivec_reg_save
+ i
),
24233 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
24234 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24236 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24238 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
24240 /* CR register traditionally saved as CR2. */
24242 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
24243 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
24244 /* Explain about use of R0. */
24245 if (info
->lr_save_p
)
24247 = gen_frame_store (reg0
,
24248 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24249 /* Explain what happens to the stack pointer. */
24251 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
24252 RTVEC_ELT (p
, j
++) = gen_rtx_SET (sp_reg_rtx
, newval
);
24255 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24256 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
24257 treg
, GEN_INT (-info
->total_size
));
24258 sp_off
= frame_off
= info
->total_size
;
24261 strategy
= info
->savres_strategy
;
24263 /* For V.4, update stack before we do any saving and set back pointer. */
24264 if (! WORLD_SAVE_P (info
)
24266 && (DEFAULT_ABI
== ABI_V4
24267 || crtl
->calls_eh_return
))
24269 bool need_r11
= (TARGET_SPE
24270 ? (!(strategy
& SAVE_INLINE_GPRS
)
24271 && info
->spe_64bit_regs_used
== 0)
24272 : (!(strategy
& SAVE_INLINE_FPRS
)
24273 || !(strategy
& SAVE_INLINE_GPRS
)
24274 || !(strategy
& SAVE_INLINE_VRS
)));
24275 int ptr_regno
= -1;
24276 rtx ptr_reg
= NULL_RTX
;
24279 if (info
->total_size
< 32767)
24280 frame_off
= info
->total_size
;
24283 else if (info
->cr_save_p
24285 || info
->first_fp_reg_save
< 64
24286 || info
->first_gp_reg_save
< 32
24287 || info
->altivec_size
!= 0
24288 || info
->vrsave_size
!= 0
24289 || crtl
->calls_eh_return
)
24293 /* The prologue won't be saving any regs so there is no need
24294 to set up a frame register to access any frame save area.
24295 We also won't be using frame_off anywhere below, but set
24296 the correct value anyway to protect against future
24297 changes to this function. */
24298 frame_off
= info
->total_size
;
24300 if (ptr_regno
!= -1)
24302 /* Set up the frame offset to that needed by the first
24303 out-of-line save function. */
24304 START_USE (ptr_regno
);
24305 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24306 frame_reg_rtx
= ptr_reg
;
24307 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
24308 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
24309 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
24310 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
24311 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
24312 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
24313 frame_off
= -ptr_off
;
24315 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
24317 if (REGNO (frame_reg_rtx
) == 12)
24319 sp_off
= info
->total_size
;
24320 if (frame_reg_rtx
!= sp_reg_rtx
)
24321 rs6000_emit_stack_tie (frame_reg_rtx
, false);
24324 /* If we use the link register, get it into r0. */
24325 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
24327 rtx addr
, reg
, mem
;
24329 reg
= gen_rtx_REG (Pmode
, 0);
24331 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
24332 RTX_FRAME_RELATED_P (insn
) = 1;
24334 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
24335 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
24337 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
24338 GEN_INT (info
->lr_save_offset
+ frame_off
));
24339 mem
= gen_rtx_MEM (Pmode
, addr
);
24340 /* This should not be of rs6000_sr_alias_set, because of
24341 __builtin_return_address. */
24343 insn
= emit_move_insn (mem
, reg
);
24344 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
24345 NULL_RTX
, NULL_RTX
);
24350 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
24351 r12 will be needed by out-of-line gpr restore. */
24352 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24353 && !(strategy
& (SAVE_INLINE_GPRS
24354 | SAVE_NOINLINE_GPRS_SAVES_LR
))
24356 if (!WORLD_SAVE_P (info
)
24358 && REGNO (frame_reg_rtx
) != cr_save_regno
24359 && !(using_static_chain_p
&& cr_save_regno
== 11)
24360 && !(using_split_stack
&& cr_save_regno
== 12 && sp_adjust
))
24362 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
24363 START_USE (cr_save_regno
);
24364 rs6000_emit_move_from_cr (cr_save_rtx
);
24367 /* Do any required saving of fpr's. If only one or two to save, do
24368 it ourselves. Otherwise, call function. */
24369 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
24372 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24373 if (save_reg_p (info
->first_fp_reg_save
+ i
))
24374 emit_frame_save (frame_reg_rtx
,
24375 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24376 ? DFmode
: SFmode
),
24377 info
->first_fp_reg_save
+ i
,
24378 info
->fp_save_offset
+ frame_off
+ 8 * i
,
24379 sp_off
- frame_off
);
24381 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
24383 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
24384 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24385 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
24386 rtx ptr_reg
= frame_reg_rtx
;
24388 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24389 gcc_checking_assert (frame_off
== 0);
24392 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24393 NOT_INUSE (ptr_regno
);
24394 emit_insn (gen_add3_insn (ptr_reg
,
24395 frame_reg_rtx
, GEN_INT (frame_off
)));
24397 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
24398 info
->fp_save_offset
,
24399 info
->lr_save_offset
,
24401 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
24402 NULL_RTX
, NULL_RTX
);
24407 /* Save GPRs. This is done as a PARALLEL if we are using
24408 the store-multiple instructions. */
24409 if (!WORLD_SAVE_P (info
)
24411 && info
->spe_64bit_regs_used
!= 0
24412 && info
->first_gp_reg_save
!= 32)
24415 rtx spe_save_area_ptr
;
24416 HOST_WIDE_INT save_off
;
24417 int ool_adjust
= 0;
24419 /* Determine whether we can address all of the registers that need
24420 to be saved with an offset from frame_reg_rtx that fits in
24421 the small const field for SPE memory instructions. */
24422 int spe_regs_addressable
24423 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
24424 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
24425 && (strategy
& SAVE_INLINE_GPRS
));
24427 if (spe_regs_addressable
)
24429 spe_save_area_ptr
= frame_reg_rtx
;
24430 save_off
= frame_off
;
24434 /* Make r11 point to the start of the SPE save area. We need
24435 to be careful here if r11 is holding the static chain. If
24436 it is, then temporarily save it in r0. */
24437 HOST_WIDE_INT offset
;
24439 if (!(strategy
& SAVE_INLINE_GPRS
))
24440 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
24441 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
24442 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
24443 save_off
= frame_off
- offset
;
24445 if (using_static_chain_p
)
24447 rtx r0
= gen_rtx_REG (Pmode
, 0);
24450 gcc_assert (info
->first_gp_reg_save
> 11);
24452 emit_move_insn (r0
, spe_save_area_ptr
);
24454 else if (REGNO (frame_reg_rtx
) != 11)
24457 emit_insn (gen_addsi3 (spe_save_area_ptr
,
24458 frame_reg_rtx
, GEN_INT (offset
)));
24459 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
24460 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
24463 if ((strategy
& SAVE_INLINE_GPRS
))
24465 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24466 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24467 emit_frame_save (spe_save_area_ptr
, reg_mode
,
24468 info
->first_gp_reg_save
+ i
,
24469 (info
->spe_gp_save_offset
+ save_off
24471 sp_off
- save_off
);
24475 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
24476 info
->spe_gp_save_offset
+ save_off
,
24478 SAVRES_SAVE
| SAVRES_GPR
);
24480 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
24481 NULL_RTX
, NULL_RTX
);
24484 /* Move the static chain pointer back. */
24485 if (!spe_regs_addressable
)
24487 if (using_static_chain_p
)
24489 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
24492 else if (REGNO (frame_reg_rtx
) != 11)
24496 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
24498 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
24499 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
24500 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
24501 rtx ptr_reg
= frame_reg_rtx
;
24502 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
24503 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
24506 if (ptr_regno
== 12)
24509 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24511 /* Need to adjust r11 (r12) if we saved any FPRs. */
24512 if (end_save
+ frame_off
!= 0)
24514 rtx offset
= GEN_INT (end_save
+ frame_off
);
24517 frame_off
= -end_save
;
24519 NOT_INUSE (ptr_regno
);
24520 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24522 else if (!ptr_set_up
)
24524 NOT_INUSE (ptr_regno
);
24525 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24527 ptr_off
= -end_save
;
24528 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
24529 info
->gp_save_offset
+ ptr_off
,
24530 info
->lr_save_offset
+ ptr_off
,
24532 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
24533 NULL_RTX
, NULL_RTX
);
24537 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
24541 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
24542 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24544 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24546 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
24547 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24548 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
24549 NULL_RTX
, NULL_RTX
);
24551 else if (!WORLD_SAVE_P (info
))
24554 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24555 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24556 emit_frame_save (frame_reg_rtx
, reg_mode
,
24557 info
->first_gp_reg_save
+ i
,
24558 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
24559 sp_off
- frame_off
);
24562 if (crtl
->calls_eh_return
)
24569 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
24570 if (regno
== INVALID_REGNUM
)
24574 p
= rtvec_alloc (i
);
24578 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
24579 if (regno
== INVALID_REGNUM
)
24583 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
24585 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
24586 RTVEC_ELT (p
, i
) = insn
;
24587 RTX_FRAME_RELATED_P (insn
) = 1;
24590 insn
= emit_insn (gen_blockage ());
24591 RTX_FRAME_RELATED_P (insn
) = 1;
24592 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
24595 /* In AIX ABI we need to make sure r2 is really saved. */
24596 if (TARGET_AIX
&& crtl
->calls_eh_return
)
24598 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
24599 rtx save_insn
, join_insn
, note
;
24600 long toc_restore_insn
;
24602 tmp_reg
= gen_rtx_REG (Pmode
, 11);
24603 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
24604 if (using_static_chain_p
)
24607 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
24611 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
24612 /* Peek at instruction to which this function returns. If it's
24613 restoring r2, then we know we've already saved r2. We can't
24614 unconditionally save r2 because the value we have will already
24615 be updated if we arrived at this function via a plt call or
24616 toc adjusting stub. */
24617 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
24618 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
24619 + RS6000_TOC_SAVE_SLOT
);
24620 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
24621 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
24622 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
24623 validate_condition_mode (EQ
, CCUNSmode
);
24624 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
24625 emit_insn (gen_rtx_SET (compare_result
,
24626 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
24627 toc_save_done
= gen_label_rtx ();
24628 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
24629 gen_rtx_EQ (VOIDmode
, compare_result
,
24631 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
24633 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
24634 JUMP_LABEL (jump
) = toc_save_done
;
24635 LABEL_NUSES (toc_save_done
) += 1;
24637 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
24638 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
24639 sp_off
- frame_off
);
24641 emit_label (toc_save_done
);
24643 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
24644 have a CFG that has different saves along different paths.
24645 Move the note to a dummy blockage insn, which describes that
24646 R2 is unconditionally saved after the label. */
24647 /* ??? An alternate representation might be a special insn pattern
24648 containing both the branch and the store. That might let the
24649 code that minimizes the number of DW_CFA_advance opcodes better
24650 freedom in placing the annotations. */
24651 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
24653 remove_note (save_insn
, note
);
24655 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
24656 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
24657 RTX_FRAME_RELATED_P (save_insn
) = 0;
24659 join_insn
= emit_insn (gen_blockage ());
24660 REG_NOTES (join_insn
) = note
;
24661 RTX_FRAME_RELATED_P (join_insn
) = 1;
24663 if (using_static_chain_p
)
24665 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
24672 /* Save CR if we use any that must be preserved. */
24673 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
24675 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
24676 GEN_INT (info
->cr_save_offset
+ frame_off
));
24677 rtx mem
= gen_frame_mem (SImode
, addr
);
24679 /* If we didn't copy cr before, do so now using r0. */
24680 if (cr_save_rtx
== NULL_RTX
)
24683 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
24684 rs6000_emit_move_from_cr (cr_save_rtx
);
24687 /* Saving CR requires a two-instruction sequence: one instruction
24688 to move the CR to a general-purpose register, and a second
24689 instruction that stores the GPR to memory.
24691 We do not emit any DWARF CFI records for the first of these,
24692 because we cannot properly represent the fact that CR is saved in
24693 a register. One reason is that we cannot express that multiple
24694 CR fields are saved; another reason is that on 64-bit, the size
24695 of the CR register in DWARF (4 bytes) differs from the size of
24696 a general-purpose register.
24698 This means if any intervening instruction were to clobber one of
24699 the call-saved CR fields, we'd have incorrect CFI. To prevent
24700 this from happening, we mark the store to memory as a use of
24701 those CR fields, which prevents any such instruction from being
24702 scheduled in between the two instructions. */
24707 crsave_v
[n_crsave
++] = gen_rtx_SET (mem
, cr_save_rtx
);
24708 for (i
= 0; i
< 8; i
++)
24709 if (save_reg_p (CR0_REGNO
+ i
))
24710 crsave_v
[n_crsave
++]
24711 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
24713 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
24714 gen_rtvec_v (n_crsave
, crsave_v
)));
24715 END_USE (REGNO (cr_save_rtx
));
24717 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
24718 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
24719 so we need to construct a frame expression manually. */
24720 RTX_FRAME_RELATED_P (insn
) = 1;
24722 /* Update address to be stack-pointer relative, like
24723 rs6000_frame_related would do. */
24724 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
24725 GEN_INT (info
->cr_save_offset
+ sp_off
));
24726 mem
= gen_frame_mem (SImode
, addr
);
24728 if (DEFAULT_ABI
== ABI_ELFv2
)
24730 /* In the ELFv2 ABI we generate separate CFI records for each
24731 CR field that was actually saved. They all point to the
24732 same 32-bit stack slot. */
24736 for (i
= 0; i
< 8; i
++)
24737 if (save_reg_p (CR0_REGNO
+ i
))
24740 = gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24742 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
24746 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
24747 gen_rtx_PARALLEL (VOIDmode
,
24748 gen_rtvec_v (n_crframe
, crframe
)));
24752 /* In other ABIs, by convention, we use a single CR regnum to
24753 represent the fact that all call-saved CR fields are saved.
24754 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
24755 rtx set
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR2_REGNO
));
24756 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
24760 /* In the ELFv2 ABI we need to save all call-saved CR fields into
24761 *separate* slots if the routine calls __builtin_eh_return, so
24762 that they can be independently restored by the unwinder. */
24763 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24765 int i
, cr_off
= info
->ehcr_offset
;
24768 /* ??? We might get better performance by using multiple mfocrf
24770 crsave
= gen_rtx_REG (SImode
, 0);
24771 emit_insn (gen_movesi_from_cr (crsave
));
24773 for (i
= 0; i
< 8; i
++)
24774 if (!call_used_regs
[CR0_REGNO
+ i
])
24776 rtvec p
= rtvec_alloc (2);
24778 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
24780 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
24782 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24784 RTX_FRAME_RELATED_P (insn
) = 1;
24785 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
24786 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
24787 sp_reg_rtx
, cr_off
+ sp_off
));
24789 cr_off
+= reg_size
;
24793 /* Update stack and set back pointer unless this is V.4,
24794 for which it was done previously. */
24795 if (!WORLD_SAVE_P (info
) && info
->push_p
24796 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
24798 rtx ptr_reg
= NULL
;
24801 /* If saving altivec regs we need to be able to address all save
24802 locations using a 16-bit offset. */
24803 if ((strategy
& SAVE_INLINE_VRS
) == 0
24804 || (info
->altivec_size
!= 0
24805 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
24806 + info
->total_size
- frame_off
) > 32767)
24807 || (info
->vrsave_size
!= 0
24808 && (info
->vrsave_save_offset
24809 + info
->total_size
- frame_off
) > 32767))
24811 int sel
= SAVRES_SAVE
| SAVRES_VR
;
24812 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
24814 if (using_static_chain_p
24815 && ptr_regno
== STATIC_CHAIN_REGNUM
)
24817 if (REGNO (frame_reg_rtx
) != ptr_regno
)
24818 START_USE (ptr_regno
);
24819 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24820 frame_reg_rtx
= ptr_reg
;
24821 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
24822 frame_off
= -ptr_off
;
24824 else if (REGNO (frame_reg_rtx
) == 1)
24825 frame_off
= info
->total_size
;
24826 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
24828 if (REGNO (frame_reg_rtx
) == 12)
24830 sp_off
= info
->total_size
;
24831 if (frame_reg_rtx
!= sp_reg_rtx
)
24832 rs6000_emit_stack_tie (frame_reg_rtx
, false);
24835 /* Set frame pointer, if needed. */
24836 if (frame_pointer_needed
)
24838 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
24840 RTX_FRAME_RELATED_P (insn
) = 1;
24843 /* Save AltiVec registers if needed. Save here because the red zone does
24844 not always include AltiVec registers. */
24845 if (!WORLD_SAVE_P (info
)
24846 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
24848 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24850 /* Oddly, the vector save/restore functions point r0 at the end
24851 of the save area, then use r11 or r12 to load offsets for
24852 [reg+reg] addressing. */
24853 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24854 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
24855 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24857 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
24859 if (scratch_regno
== 12)
24861 if (end_save
+ frame_off
!= 0)
24863 rtx offset
= GEN_INT (end_save
+ frame_off
);
24865 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24868 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24870 ptr_off
= -end_save
;
24871 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24872 info
->altivec_save_offset
+ ptr_off
,
24873 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
24874 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
24875 NULL_RTX
, NULL_RTX
);
24876 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
24878 /* The oddity mentioned above clobbered our frame reg. */
24879 emit_move_insn (frame_reg_rtx
, ptr_reg
);
24880 frame_off
= ptr_off
;
24883 else if (!WORLD_SAVE_P (info
)
24884 && info
->altivec_size
!= 0)
24888 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24889 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24891 rtx areg
, savereg
, mem
;
24894 offset
= (info
->altivec_save_offset
+ frame_off
24895 + 16 * (i
- info
->first_altivec_reg_save
));
24897 savereg
= gen_rtx_REG (V4SImode
, i
);
24900 areg
= gen_rtx_REG (Pmode
, 0);
24901 emit_move_insn (areg
, GEN_INT (offset
));
24903 /* AltiVec addressing mode is [reg+reg]. */
24904 mem
= gen_frame_mem (V4SImode
,
24905 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
24907 /* Rather than emitting a generic move, force use of the stvx
24908 instruction, which we always want. In particular we don't
24909 want xxpermdi/stxvd2x for little endian. */
24910 insn
= emit_insn (gen_altivec_stvx_v4si_internal (mem
, savereg
));
24912 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
24913 areg
, GEN_INT (offset
));
24917 /* VRSAVE is a bit vector representing which AltiVec registers
24918 are used. The OS uses this to determine which vector
24919 registers to save on a context switch. We need to save
24920 VRSAVE on the stack frame, add whatever AltiVec registers we
24921 used in this function, and do the corresponding magic in the
24924 if (!WORLD_SAVE_P (info
)
24925 && info
->vrsave_size
!= 0)
24931 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
24932 be using r12 as frame_reg_rtx and r11 as the static chain
24933 pointer for nested functions. */
24935 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24936 && !using_static_chain_p
)
24938 else if (using_split_stack
|| REGNO (frame_reg_rtx
) == 12)
24941 if (using_static_chain_p
)
24945 NOT_INUSE (save_regno
);
24946 reg
= gen_rtx_REG (SImode
, save_regno
);
24947 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
24949 emit_insn (gen_get_vrsave_internal (reg
));
24951 emit_insn (gen_rtx_SET (reg
, vrsave
));
24954 offset
= info
->vrsave_save_offset
+ frame_off
;
24955 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
24957 /* Include the registers in the mask. */
24958 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
24960 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
24963 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
24964 if (!TARGET_SINGLE_PIC_BASE
24965 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
24966 || (DEFAULT_ABI
== ABI_V4
24967 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
24968 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
24970 /* If emit_load_toc_table will use the link register, we need to save
24971 it. We use R12 for this purpose because emit_load_toc_table
24972 can use register 0. This allows us to use a plain 'blr' to return
24973 from the procedure more often. */
24974 int save_LR_around_toc_setup
= (TARGET_ELF
24975 && DEFAULT_ABI
== ABI_V4
24977 && ! info
->lr_save_p
24978 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
24979 if (save_LR_around_toc_setup
)
24981 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
24982 rtx tmp
= gen_rtx_REG (Pmode
, 12);
24985 insn
= emit_move_insn (tmp
, lr
);
24986 RTX_FRAME_RELATED_P (insn
) = 1;
24988 rs6000_emit_load_toc_table (TRUE
);
24990 insn
= emit_move_insn (lr
, tmp
);
24991 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
24992 RTX_FRAME_RELATED_P (insn
) = 1;
24995 rs6000_emit_load_toc_table (TRUE
);
24999 if (!TARGET_SINGLE_PIC_BASE
25000 && DEFAULT_ABI
== ABI_DARWIN
25001 && flag_pic
&& crtl
->uses_pic_offset_table
)
25003 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
25004 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
25006 /* Save and restore LR locally around this call (in R0). */
25007 if (!info
->lr_save_p
)
25008 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
25010 emit_insn (gen_load_macho_picbase (src
));
25012 emit_move_insn (gen_rtx_REG (Pmode
,
25013 RS6000_PIC_OFFSET_TABLE_REGNUM
),
25016 if (!info
->lr_save_p
)
25017 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
25021 /* If we need to, save the TOC register after doing the stack setup.
25022 Do not emit eh frame info for this save. The unwinder wants info,
25023 conceptually attached to instructions in this function, about
25024 register values in the caller of this function. This R2 may have
25025 already been changed from the value in the caller.
25026 We don't attempt to write accurate DWARF EH frame info for R2
25027 because code emitted by gcc for a (non-pointer) function call
25028 doesn't save and restore R2. Instead, R2 is managed out-of-line
25029 by a linker generated plt call stub when the function resides in
25030 a shared library. This behaviour is costly to describe in DWARF,
25031 both in terms of the size of DWARF info and the time taken in the
25032 unwinder to interpret it. R2 changes, apart from the
25033 calls_eh_return case earlier in this function, are handled by
25034 linux-unwind.h frob_update_context. */
25035 if (rs6000_save_toc_in_prologue_p ())
25037 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
25038 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
25041 if (using_split_stack
&& split_stack_arg_pointer_used_p ())
25043 /* Set up the arg pointer (r12) for -fsplit-stack code. If
25044 __morestack was called, it left the arg pointer to the old
25045 stack in r29. Otherwise, the arg pointer is the top of the
25047 cfun
->machine
->split_stack_argp_used
= true;
25050 rtx r12
= gen_rtx_REG (Pmode
, 12);
25051 rtx set_r12
= gen_rtx_SET (r12
, sp_reg_rtx
);
25052 emit_insn_before (set_r12
, sp_adjust
);
25054 else if (frame_off
!= 0 || REGNO (frame_reg_rtx
) != 12)
25056 rtx r12
= gen_rtx_REG (Pmode
, 12);
25057 if (frame_off
== 0)
25058 emit_move_insn (r12
, frame_reg_rtx
);
25060 emit_insn (gen_add3_insn (r12
, frame_reg_rtx
, GEN_INT (frame_off
)));
25064 rtx r12
= gen_rtx_REG (Pmode
, 12);
25065 rtx r29
= gen_rtx_REG (Pmode
, 29);
25066 rtx cr7
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
25067 rtx not_more
= gen_label_rtx ();
25070 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
25071 gen_rtx_GEU (VOIDmode
, cr7
, const0_rtx
),
25072 gen_rtx_LABEL_REF (VOIDmode
, not_more
),
25074 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
25075 JUMP_LABEL (jump
) = not_more
;
25076 LABEL_NUSES (not_more
) += 1;
25077 emit_move_insn (r12
, r29
);
25078 emit_label (not_more
);
25083 /* Output .extern statements for the save/restore routines we use. */
25086 rs6000_output_savres_externs (FILE *file
)
25088 rs6000_stack_t
*info
= rs6000_stack_info ();
25090 if (TARGET_DEBUG_STACK
)
25091 debug_stack_info (info
);
25093 /* Write .extern for any function we will call to save and restore
25095 if (info
->first_fp_reg_save
< 64
25100 int regno
= info
->first_fp_reg_save
- 32;
25102 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
25104 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
25105 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
25106 name
= rs6000_savres_routine_name (info
, regno
, sel
);
25107 fprintf (file
, "\t.extern %s\n", name
);
25109 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
25111 bool lr
= (info
->savres_strategy
25112 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
25113 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
25114 name
= rs6000_savres_routine_name (info
, regno
, sel
);
25115 fprintf (file
, "\t.extern %s\n", name
);
25120 /* Write function prologue. */
25123 rs6000_output_function_prologue (FILE *file
,
25124 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
25126 if (!cfun
->is_thunk
)
25127 rs6000_output_savres_externs (file
);
25129 /* ELFv2 ABI r2 setup code and local entry point. This must follow
25130 immediately after the global entry point label. */
25131 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
25133 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
25135 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
25136 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
25138 fputs ("\t.localentry\t", file
);
25139 assemble_name (file
, name
);
25140 fputs (",.-", file
);
25141 assemble_name (file
, name
);
25142 fputs ("\n", file
);
25145 /* Output -mprofile-kernel code. This needs to be done here instead of
25146 in output_function_profile since it must go after the ELFv2 ABI
25147 local entry point. */
25148 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
25150 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
25151 gcc_assert (!TARGET_32BIT
);
25153 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
25155 /* In the ELFv2 ABI we have no compiler stack word. It must be
25156 the resposibility of _mcount to preserve the static chain
25157 register if required. */
25158 if (DEFAULT_ABI
!= ABI_ELFv2
25159 && cfun
->static_chain_decl
!= NULL
)
25161 asm_fprintf (file
, "\tstd %s,24(%s)\n",
25162 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
25163 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
25164 asm_fprintf (file
, "\tld %s,24(%s)\n",
25165 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
25168 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
25171 rs6000_pic_labelno
++;
25174 /* Non-zero if vmx regs are restored before the frame pop, zero if
25175 we restore after the pop when possible. */
25176 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
25178 /* Restoring cr is a two step process: loading a reg from the frame
25179 save, then moving the reg to cr. For ABI_V4 we must let the
25180 unwinder know that the stack location is no longer valid at or
25181 before the stack deallocation, but we can't emit a cfa_restore for
25182 cr at the stack deallocation like we do for other registers.
25183 The trouble is that it is possible for the move to cr to be
25184 scheduled after the stack deallocation. So say exactly where cr
25185 is located on each of the two insns. */
25188 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
25190 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
25191 rtx reg
= gen_rtx_REG (SImode
, regno
);
25192 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
25194 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
25196 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
25197 rtx set
= gen_rtx_SET (reg
, cr
);
25199 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
25200 RTX_FRAME_RELATED_P (insn
) = 1;
25205 /* Reload CR from REG. */
25208 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
25213 if (using_mfcr_multiple
)
25215 for (i
= 0; i
< 8; i
++)
25216 if (save_reg_p (CR0_REGNO
+ i
))
25218 gcc_assert (count
);
25221 if (using_mfcr_multiple
&& count
> 1)
25227 p
= rtvec_alloc (count
);
25230 for (i
= 0; i
< 8; i
++)
25231 if (save_reg_p (CR0_REGNO
+ i
))
25233 rtvec r
= rtvec_alloc (2);
25234 RTVEC_ELT (r
, 0) = reg
;
25235 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
25236 RTVEC_ELT (p
, ndx
) =
25237 gen_rtx_SET (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
25238 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
25241 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25242 gcc_assert (ndx
== count
);
25244 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
25245 CR field separately. */
25246 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
25248 for (i
= 0; i
< 8; i
++)
25249 if (save_reg_p (CR0_REGNO
+ i
))
25250 add_reg_note (insn
, REG_CFA_RESTORE
,
25251 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
25253 RTX_FRAME_RELATED_P (insn
) = 1;
25257 for (i
= 0; i
< 8; i
++)
25258 if (save_reg_p (CR0_REGNO
+ i
))
25260 rtx insn
= emit_insn (gen_movsi_to_cr_one
25261 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
25263 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
25264 CR field separately, attached to the insn that in fact
25265 restores this particular CR field. */
25266 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
25268 add_reg_note (insn
, REG_CFA_RESTORE
,
25269 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
25271 RTX_FRAME_RELATED_P (insn
) = 1;
25275 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
25276 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
25277 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
25279 rtx_insn
*insn
= get_last_insn ();
25280 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
25282 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
25283 RTX_FRAME_RELATED_P (insn
) = 1;
25287 /* Like cr, the move to lr instruction can be scheduled after the
25288 stack deallocation, but unlike cr, its stack frame save is still
25289 valid. So we only need to emit the cfa_restore on the correct
25293 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
25295 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
25296 rtx reg
= gen_rtx_REG (Pmode
, regno
);
25298 emit_move_insn (reg
, mem
);
25302 restore_saved_lr (int regno
, bool exit_func
)
25304 rtx reg
= gen_rtx_REG (Pmode
, regno
);
25305 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
25306 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
25308 if (!exit_func
&& flag_shrink_wrap
)
25310 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
25311 RTX_FRAME_RELATED_P (insn
) = 1;
25316 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
25318 if (DEFAULT_ABI
== ABI_ELFv2
)
25321 for (i
= 0; i
< 8; i
++)
25322 if (save_reg_p (CR0_REGNO
+ i
))
25324 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
25325 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
25329 else if (info
->cr_save_p
)
25330 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
25331 gen_rtx_REG (SImode
, CR2_REGNO
),
25334 if (info
->lr_save_p
)
25335 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
25336 gen_rtx_REG (Pmode
, LR_REGNO
),
25338 return cfa_restores
;
25341 /* Return true if OFFSET from stack pointer can be clobbered by signals.
25342 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
25343 below stack pointer not cloberred by signals. */
25346 offset_below_red_zone_p (HOST_WIDE_INT offset
)
25348 return offset
< (DEFAULT_ABI
== ABI_V4
25350 : TARGET_32BIT
? -220 : -288);
25353 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
25356 emit_cfa_restores (rtx cfa_restores
)
25358 rtx_insn
*insn
= get_last_insn ();
25359 rtx
*loc
= ®_NOTES (insn
);
25362 loc
= &XEXP (*loc
, 1);
25363 *loc
= cfa_restores
;
25364 RTX_FRAME_RELATED_P (insn
) = 1;
25367 /* Emit function epilogue as insns. */
25370 rs6000_emit_epilogue (int sibcall
)
25372 rs6000_stack_t
*info
;
25373 int restoring_GPRs_inline
;
25374 int restoring_FPRs_inline
;
25375 int using_load_multiple
;
25376 int using_mtcr_multiple
;
25377 int use_backchain_to_restore_sp
;
25380 HOST_WIDE_INT frame_off
= 0;
25381 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
25382 rtx frame_reg_rtx
= sp_reg_rtx
;
25383 rtx cfa_restores
= NULL_RTX
;
25385 rtx cr_save_reg
= NULL_RTX
;
25386 machine_mode reg_mode
= Pmode
;
25387 int reg_size
= TARGET_32BIT
? 4 : 8;
25390 unsigned ptr_regno
;
25392 info
= rs6000_stack_info ();
25394 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
25396 reg_mode
= V2SImode
;
25400 strategy
= info
->savres_strategy
;
25401 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
25402 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
25403 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
25404 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
25405 || rs6000_cpu
== PROCESSOR_PPC603
25406 || rs6000_cpu
== PROCESSOR_PPC750
25408 /* Restore via the backchain when we have a large frame, since this
25409 is more efficient than an addis, addi pair. The second condition
25410 here will not trigger at the moment; We don't actually need a
25411 frame pointer for alloca, but the generic parts of the compiler
25412 give us one anyway. */
25413 use_backchain_to_restore_sp
= (info
->total_size
+ (info
->lr_save_p
25414 ? info
->lr_save_offset
25416 || (cfun
->calls_alloca
25417 && !frame_pointer_needed
));
25418 restore_lr
= (info
->lr_save_p
25419 && (restoring_FPRs_inline
25420 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
25421 && (restoring_GPRs_inline
25422 || info
->first_fp_reg_save
< 64));
25424 if (WORLD_SAVE_P (info
))
25428 const char *alloc_rname
;
25431 /* eh_rest_world_r10 will return to the location saved in the LR
25432 stack slot (which is not likely to be our caller.)
25433 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
25434 rest_world is similar, except any R10 parameter is ignored.
25435 The exception-handling stuff that was here in 2.95 is no
25436 longer necessary. */
25440 + 32 - info
->first_gp_reg_save
25441 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
25442 + 63 + 1 - info
->first_fp_reg_save
);
25444 strcpy (rname
, ((crtl
->calls_eh_return
) ?
25445 "*eh_rest_world_r10" : "*rest_world"));
25446 alloc_rname
= ggc_strdup (rname
);
25449 RTVEC_ELT (p
, j
++) = ret_rtx
;
25450 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
25451 gen_rtx_REG (Pmode
,
25454 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
25455 /* The instruction pattern requires a clobber here;
25456 it is shared with the restVEC helper. */
25458 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
25461 /* CR register traditionally saved as CR2. */
25462 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
25464 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
25465 if (flag_shrink_wrap
)
25467 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
25468 gen_rtx_REG (Pmode
, LR_REGNO
),
25470 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25474 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25476 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
25478 = gen_frame_load (reg
,
25479 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
25480 if (flag_shrink_wrap
)
25481 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25483 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
25485 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
25487 = gen_frame_load (reg
,
25488 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
25489 if (flag_shrink_wrap
)
25490 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25492 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
25494 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
25495 ? DFmode
: SFmode
),
25496 info
->first_fp_reg_save
+ i
);
25498 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
25499 if (flag_shrink_wrap
)
25500 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25503 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
25505 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
25507 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
25509 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
25511 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
25512 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25514 if (flag_shrink_wrap
)
25516 REG_NOTES (insn
) = cfa_restores
;
25517 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
25518 RTX_FRAME_RELATED_P (insn
) = 1;
25523 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
25525 frame_off
= info
->total_size
;
25527 /* Restore AltiVec registers if we must do so before adjusting the
25529 if (info
->altivec_size
!= 0
25530 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
25531 || (DEFAULT_ABI
!= ABI_V4
25532 && offset_below_red_zone_p (info
->altivec_save_offset
))))
25535 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
25537 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
25538 if (use_backchain_to_restore_sp
)
25540 int frame_regno
= 11;
25542 if ((strategy
& REST_INLINE_VRS
) == 0)
25544 /* Of r11 and r12, select the one not clobbered by an
25545 out-of-line restore function for the frame register. */
25546 frame_regno
= 11 + 12 - scratch_regno
;
25548 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
25549 emit_move_insn (frame_reg_rtx
,
25550 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
25553 else if (frame_pointer_needed
)
25554 frame_reg_rtx
= hard_frame_pointer_rtx
;
25556 if ((strategy
& REST_INLINE_VRS
) == 0)
25558 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
25560 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
25561 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
25563 if (end_save
+ frame_off
!= 0)
25565 rtx offset
= GEN_INT (end_save
+ frame_off
);
25567 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
25570 emit_move_insn (ptr_reg
, frame_reg_rtx
);
25572 ptr_off
= -end_save
;
25573 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
25574 info
->altivec_save_offset
+ ptr_off
,
25575 0, V4SImode
, SAVRES_VR
);
25579 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25580 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
25582 rtx addr
, areg
, mem
, reg
;
25584 areg
= gen_rtx_REG (Pmode
, 0);
25586 (areg
, GEN_INT (info
->altivec_save_offset
25588 + 16 * (i
- info
->first_altivec_reg_save
)));
25590 /* AltiVec addressing mode is [reg+reg]. */
25591 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
25592 mem
= gen_frame_mem (V4SImode
, addr
);
25594 reg
= gen_rtx_REG (V4SImode
, i
);
25595 /* Rather than emitting a generic move, force use of the
25596 lvx instruction, which we always want. In particular
25597 we don't want lxvd2x/xxpermdi for little endian. */
25598 (void) emit_insn (gen_altivec_lvx_v4si_internal (reg
, mem
));
25602 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25603 if (((strategy
& REST_INLINE_VRS
) == 0
25604 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
25605 && (flag_shrink_wrap
25606 || (offset_below_red_zone_p
25607 (info
->altivec_save_offset
25608 + 16 * (i
- info
->first_altivec_reg_save
)))))
25610 rtx reg
= gen_rtx_REG (V4SImode
, i
);
25611 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25615 /* Restore VRSAVE if we must do so before adjusting the stack. */
25616 if (info
->vrsave_size
!= 0
25617 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
25618 || (DEFAULT_ABI
!= ABI_V4
25619 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
25623 if (frame_reg_rtx
== sp_reg_rtx
)
25625 if (use_backchain_to_restore_sp
)
25627 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
25628 emit_move_insn (frame_reg_rtx
,
25629 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
25632 else if (frame_pointer_needed
)
25633 frame_reg_rtx
= hard_frame_pointer_rtx
;
25636 reg
= gen_rtx_REG (SImode
, 12);
25637 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
25638 info
->vrsave_save_offset
+ frame_off
));
25640 emit_insn (generate_set_vrsave (reg
, info
, 1));
25644 /* If we have a large stack frame, restore the old stack pointer
25645 using the backchain. */
25646 if (use_backchain_to_restore_sp
)
25648 if (frame_reg_rtx
== sp_reg_rtx
)
25650 /* Under V.4, don't reset the stack pointer until after we're done
25651 loading the saved registers. */
25652 if (DEFAULT_ABI
== ABI_V4
)
25653 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
25655 insn
= emit_move_insn (frame_reg_rtx
,
25656 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
25659 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
25660 && DEFAULT_ABI
== ABI_V4
)
25661 /* frame_reg_rtx has been set up by the altivec restore. */
25665 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
25666 frame_reg_rtx
= sp_reg_rtx
;
25669 /* If we have a frame pointer, we can restore the old stack pointer
25671 else if (frame_pointer_needed
)
25673 frame_reg_rtx
= sp_reg_rtx
;
25674 if (DEFAULT_ABI
== ABI_V4
)
25675 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
25676 /* Prevent reordering memory accesses against stack pointer restore. */
25677 else if (cfun
->calls_alloca
25678 || offset_below_red_zone_p (-info
->total_size
))
25679 rs6000_emit_stack_tie (frame_reg_rtx
, true);
25681 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
25682 GEN_INT (info
->total_size
)));
25685 else if (info
->push_p
25686 && DEFAULT_ABI
!= ABI_V4
25687 && !crtl
->calls_eh_return
)
25689 /* Prevent reordering memory accesses against stack pointer restore. */
25690 if (cfun
->calls_alloca
25691 || offset_below_red_zone_p (-info
->total_size
))
25692 rs6000_emit_stack_tie (frame_reg_rtx
, false);
25693 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
25694 GEN_INT (info
->total_size
)));
25697 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
25701 REG_NOTES (insn
) = cfa_restores
;
25702 cfa_restores
= NULL_RTX
;
25704 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
25705 RTX_FRAME_RELATED_P (insn
) = 1;
25708 /* Restore AltiVec registers if we have not done so already. */
25709 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
25710 && info
->altivec_size
!= 0
25711 && (DEFAULT_ABI
== ABI_V4
25712 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
25716 if ((strategy
& REST_INLINE_VRS
) == 0)
25718 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
25720 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
25721 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
25722 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
25724 if (end_save
+ frame_off
!= 0)
25726 rtx offset
= GEN_INT (end_save
+ frame_off
);
25728 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
25731 emit_move_insn (ptr_reg
, frame_reg_rtx
);
25733 ptr_off
= -end_save
;
25734 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
25735 info
->altivec_save_offset
+ ptr_off
,
25736 0, V4SImode
, SAVRES_VR
);
25737 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
25739 /* Frame reg was clobbered by out-of-line save. Restore it
25740 from ptr_reg, and if we are calling out-of-line gpr or
25741 fpr restore set up the correct pointer and offset. */
25742 unsigned newptr_regno
= 1;
25743 if (!restoring_GPRs_inline
)
25745 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
25746 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
25747 newptr_regno
= ptr_regno_for_savres (sel
);
25748 end_save
= info
->gp_save_offset
+ info
->gp_size
;
25750 else if (!restoring_FPRs_inline
)
25752 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
25753 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
25754 newptr_regno
= ptr_regno_for_savres (sel
);
25755 end_save
= info
->fp_save_offset
+ info
->fp_size
;
25758 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
25759 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
25761 if (end_save
+ ptr_off
!= 0)
25763 rtx offset
= GEN_INT (end_save
+ ptr_off
);
25765 frame_off
= -end_save
;
25767 emit_insn (gen_addsi3_carry (frame_reg_rtx
,
25770 emit_insn (gen_adddi3_carry (frame_reg_rtx
,
25775 frame_off
= ptr_off
;
25776 emit_move_insn (frame_reg_rtx
, ptr_reg
);
25782 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25783 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
25785 rtx addr
, areg
, mem
, reg
;
25787 areg
= gen_rtx_REG (Pmode
, 0);
25789 (areg
, GEN_INT (info
->altivec_save_offset
25791 + 16 * (i
- info
->first_altivec_reg_save
)));
25793 /* AltiVec addressing mode is [reg+reg]. */
25794 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
25795 mem
= gen_frame_mem (V4SImode
, addr
);
25797 reg
= gen_rtx_REG (V4SImode
, i
);
25798 /* Rather than emitting a generic move, force use of the
25799 lvx instruction, which we always want. In particular
25800 we don't want lxvd2x/xxpermdi for little endian. */
25801 (void) emit_insn (gen_altivec_lvx_v4si_internal (reg
, mem
));
25805 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25806 if (((strategy
& REST_INLINE_VRS
) == 0
25807 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
25808 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
25810 rtx reg
= gen_rtx_REG (V4SImode
, i
);
25811 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25815 /* Restore VRSAVE if we have not done so already. */
25816 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
25817 && info
->vrsave_size
!= 0
25818 && (DEFAULT_ABI
== ABI_V4
25819 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
25823 reg
= gen_rtx_REG (SImode
, 12);
25824 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
25825 info
->vrsave_save_offset
+ frame_off
));
25827 emit_insn (generate_set_vrsave (reg
, info
, 1));
25830 /* If we exit by an out-of-line restore function on ABI_V4 then that
25831 function will deallocate the stack, so we don't need to worry
25832 about the unwinder restoring cr from an invalid stack frame
25834 exit_func
= (!restoring_FPRs_inline
25835 || (!restoring_GPRs_inline
25836 && info
->first_fp_reg_save
== 64));
25838 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
25839 *separate* slots if the routine calls __builtin_eh_return, so
25840 that they can be independently restored by the unwinder. */
25841 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
25843 int i
, cr_off
= info
->ehcr_offset
;
25845 for (i
= 0; i
< 8; i
++)
25846 if (!call_used_regs
[CR0_REGNO
+ i
])
25848 rtx reg
= gen_rtx_REG (SImode
, 0);
25849 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
25850 cr_off
+ frame_off
));
25852 insn
= emit_insn (gen_movsi_to_cr_one
25853 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
25855 if (!exit_func
&& flag_shrink_wrap
)
25857 add_reg_note (insn
, REG_CFA_RESTORE
,
25858 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
25860 RTX_FRAME_RELATED_P (insn
) = 1;
25863 cr_off
+= reg_size
;
25867 /* Get the old lr if we saved it. If we are restoring registers
25868 out-of-line, then the out-of-line routines can do this for us. */
25869 if (restore_lr
&& restoring_GPRs_inline
)
25870 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
25872 /* Get the old cr if we saved it. */
25873 if (info
->cr_save_p
)
25875 unsigned cr_save_regno
= 12;
25877 if (!restoring_GPRs_inline
)
25879 /* Ensure we don't use the register used by the out-of-line
25880 gpr register restore below. */
25881 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
25882 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
25883 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
25885 if (gpr_ptr_regno
== 12)
25886 cr_save_regno
= 11;
25887 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
25889 else if (REGNO (frame_reg_rtx
) == 12)
25890 cr_save_regno
= 11;
25892 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
25893 info
->cr_save_offset
+ frame_off
,
25897 /* Set LR here to try to overlap restores below. */
25898 if (restore_lr
&& restoring_GPRs_inline
)
25899 restore_saved_lr (0, exit_func
);
25901 /* Load exception handler data registers, if needed. */
25902 if (crtl
->calls_eh_return
)
25904 unsigned int i
, regno
;
25908 rtx reg
= gen_rtx_REG (reg_mode
, 2);
25909 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
25910 frame_off
+ RS6000_TOC_SAVE_SLOT
));
25917 regno
= EH_RETURN_DATA_REGNO (i
);
25918 if (regno
== INVALID_REGNUM
)
25921 /* Note: possible use of r0 here to address SPE regs. */
25922 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
25923 info
->ehrd_offset
+ frame_off
25924 + reg_size
* (int) i
);
25926 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
25930 /* Restore GPRs. This is done as a PARALLEL if we are using
25931 the load-multiple instructions. */
25933 && info
->spe_64bit_regs_used
25934 && info
->first_gp_reg_save
!= 32)
25936 /* Determine whether we can address all of the registers that need
25937 to be saved with an offset from frame_reg_rtx that fits in
25938 the small const field for SPE memory instructions. */
25939 int spe_regs_addressable
25940 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
25941 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
25942 && restoring_GPRs_inline
);
25944 if (!spe_regs_addressable
)
25946 int ool_adjust
= 0;
25947 rtx old_frame_reg_rtx
= frame_reg_rtx
;
25948 /* Make r11 point to the start of the SPE save area. We worried about
25949 not clobbering it when we were saving registers in the prologue.
25950 There's no need to worry here because the static chain is passed
25951 anew to every function. */
25953 if (!restoring_GPRs_inline
)
25954 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
25955 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
25956 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
25957 GEN_INT (info
->spe_gp_save_offset
25960 /* Keep the invariant that frame_reg_rtx + frame_off points
25961 at the top of the stack frame. */
25962 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
25965 if (restoring_GPRs_inline
)
25967 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
25969 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25970 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
25972 rtx offset
, addr
, mem
, reg
;
25974 /* We're doing all this to ensure that the immediate offset
25975 fits into the immediate field of 'evldd'. */
25976 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
25978 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
25979 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
25980 mem
= gen_rtx_MEM (V2SImode
, addr
);
25981 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
25983 emit_move_insn (reg
, mem
);
25987 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
25988 info
->spe_gp_save_offset
+ frame_off
,
25989 info
->lr_save_offset
+ frame_off
,
25991 SAVRES_GPR
| SAVRES_LR
);
25993 else if (!restoring_GPRs_inline
)
25995 /* We are jumping to an out-of-line function. */
25997 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
25998 bool can_use_exit
= end_save
== 0;
25999 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
26002 /* Emit stack reset code if we need it. */
26003 ptr_regno
= ptr_regno_for_savres (sel
);
26004 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
26006 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
26007 else if (end_save
+ frame_off
!= 0)
26008 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
26009 GEN_INT (end_save
+ frame_off
)));
26010 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
26011 emit_move_insn (ptr_reg
, frame_reg_rtx
);
26012 if (REGNO (frame_reg_rtx
) == ptr_regno
)
26013 frame_off
= -end_save
;
26015 if (can_use_exit
&& info
->cr_save_p
)
26016 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
26018 ptr_off
= -end_save
;
26019 rs6000_emit_savres_rtx (info
, ptr_reg
,
26020 info
->gp_save_offset
+ ptr_off
,
26021 info
->lr_save_offset
+ ptr_off
,
26024 else if (using_load_multiple
)
26027 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
26028 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26030 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
26032 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
26033 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26037 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
26038 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
26039 emit_insn (gen_frame_load
26040 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
26042 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
26045 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
26047 /* If the frame pointer was used then we can't delay emitting
26048 a REG_CFA_DEF_CFA note. This must happen on the insn that
26049 restores the frame pointer, r31. We may have already emitted
26050 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
26051 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
26052 be harmless if emitted. */
26053 if (frame_pointer_needed
)
26055 insn
= get_last_insn ();
26056 add_reg_note (insn
, REG_CFA_DEF_CFA
,
26057 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
26058 RTX_FRAME_RELATED_P (insn
) = 1;
26061 /* Set up cfa_restores. We always need these when
26062 shrink-wrapping. If not shrink-wrapping then we only need
26063 the cfa_restore when the stack location is no longer valid.
26064 The cfa_restores must be emitted on or before the insn that
26065 invalidates the stack, and of course must not be emitted
26066 before the insn that actually does the restore. The latter
26067 is why it is a bad idea to emit the cfa_restores as a group
26068 on the last instruction here that actually does a restore:
26069 That insn may be reordered with respect to others doing
26071 if (flag_shrink_wrap
26072 && !restoring_GPRs_inline
26073 && info
->first_fp_reg_save
== 64)
26074 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
26076 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
26077 if (!restoring_GPRs_inline
26078 || using_load_multiple
26079 || rs6000_reg_live_or_pic_offset_p (i
))
26081 rtx reg
= gen_rtx_REG (reg_mode
, i
);
26083 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26087 if (!restoring_GPRs_inline
26088 && info
->first_fp_reg_save
== 64)
26090 /* We are jumping to an out-of-line function. */
26092 emit_cfa_restores (cfa_restores
);
26096 if (restore_lr
&& !restoring_GPRs_inline
)
26098 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
26099 restore_saved_lr (0, exit_func
);
26102 /* Restore fpr's if we need to do it without calling a function. */
26103 if (restoring_FPRs_inline
)
26104 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
26105 if (save_reg_p (info
->first_fp_reg_save
+ i
))
26107 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
26108 ? DFmode
: SFmode
),
26109 info
->first_fp_reg_save
+ i
);
26110 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
26111 info
->fp_save_offset
+ frame_off
+ 8 * i
));
26112 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
26113 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
26116 /* If we saved cr, restore it here. Just those that were used. */
26117 if (info
->cr_save_p
)
26118 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
26120 /* If this is V.4, unwind the stack pointer after all of the loads
26121 have been done, or set up r11 if we are restoring fp out of line. */
26123 if (!restoring_FPRs_inline
)
26125 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
26126 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
26127 ptr_regno
= ptr_regno_for_savres (sel
);
26130 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
26131 if (REGNO (frame_reg_rtx
) == ptr_regno
)
26134 if (insn
&& restoring_FPRs_inline
)
26138 REG_NOTES (insn
) = cfa_restores
;
26139 cfa_restores
= NULL_RTX
;
26141 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
26142 RTX_FRAME_RELATED_P (insn
) = 1;
26145 if (crtl
->calls_eh_return
)
26147 rtx sa
= EH_RETURN_STACKADJ_RTX
;
26148 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
26154 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
26155 if (! restoring_FPRs_inline
)
26157 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
26158 RTVEC_ELT (p
, 0) = ret_rtx
;
26164 /* We can't hang the cfa_restores off a simple return,
26165 since the shrink-wrap code sometimes uses an existing
26166 return. This means there might be a path from
26167 pre-prologue code to this return, and dwarf2cfi code
26168 wants the eh_frame unwinder state to be the same on
26169 all paths to any point. So we need to emit the
26170 cfa_restores before the return. For -m64 we really
26171 don't need epilogue cfa_restores at all, except for
26172 this irritating dwarf2cfi with shrink-wrap
26173 requirement; The stack red-zone means eh_frame info
26174 from the prologue telling the unwinder to restore
26175 from the stack is perfectly good right to the end of
26177 emit_insn (gen_blockage ());
26178 emit_cfa_restores (cfa_restores
);
26179 cfa_restores
= NULL_RTX
;
26181 p
= rtvec_alloc (2);
26182 RTVEC_ELT (p
, 0) = simple_return_rtx
;
26185 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
26186 ? gen_rtx_USE (VOIDmode
,
26187 gen_rtx_REG (Pmode
, LR_REGNO
))
26188 : gen_rtx_CLOBBER (VOIDmode
,
26189 gen_rtx_REG (Pmode
, LR_REGNO
)));
26191 /* If we have to restore more than two FP registers, branch to the
26192 restore function. It will return to our caller. */
26193 if (! restoring_FPRs_inline
)
26199 if (flag_shrink_wrap
)
26200 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
26202 sym
= rs6000_savres_routine_sym (info
,
26203 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
26204 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
26205 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
26206 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
26208 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
26210 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
26212 RTVEC_ELT (p
, i
+ 4)
26213 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
26214 if (flag_shrink_wrap
)
26215 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
26220 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
26226 /* Ensure the cfa_restores are hung off an insn that won't
26227 be reordered above other restores. */
26228 emit_insn (gen_blockage ());
26230 emit_cfa_restores (cfa_restores
);
26234 /* Write function epilogue. */
26237 rs6000_output_function_epilogue (FILE *file
,
26238 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
26241 macho_branch_islands ();
26242 /* Mach-O doesn't support labels at the end of objects, so if
26243 it looks like we might want one, insert a NOP. */
26245 rtx_insn
*insn
= get_last_insn ();
26246 rtx_insn
*deleted_debug_label
= NULL
;
26249 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
26251 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
26252 notes only, instead set their CODE_LABEL_NUMBER to -1,
26253 otherwise there would be code generation differences
26254 in between -g and -g0. */
26255 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
26256 deleted_debug_label
= insn
;
26257 insn
= PREV_INSN (insn
);
26262 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
26263 fputs ("\tnop\n", file
);
26264 else if (deleted_debug_label
)
26265 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
26266 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
26267 CODE_LABEL_NUMBER (insn
) = -1;
26271 /* Output a traceback table here. See /usr/include/sys/debug.h for info
26274 We don't output a traceback table if -finhibit-size-directive was
26275 used. The documentation for -finhibit-size-directive reads
26276 ``don't output a @code{.size} assembler directive, or anything
26277 else that would cause trouble if the function is split in the
26278 middle, and the two halves are placed at locations far apart in
26279 memory.'' The traceback table has this property, since it
26280 includes the offset from the start of the function to the
26281 traceback table itself.
26283 System V.4 Powerpc's (and the embedded ABI derived from it) use a
26284 different traceback table. */
26285 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26286 && ! flag_inhibit_size_directive
26287 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
26289 const char *fname
= NULL
;
26290 const char *language_string
= lang_hooks
.name
;
26291 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
26293 int optional_tbtab
;
26294 rs6000_stack_t
*info
= rs6000_stack_info ();
26296 if (rs6000_traceback
== traceback_full
)
26297 optional_tbtab
= 1;
26298 else if (rs6000_traceback
== traceback_part
)
26299 optional_tbtab
= 0;
26301 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
26303 if (optional_tbtab
)
26305 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
26306 while (*fname
== '.') /* V.4 encodes . in the name */
26309 /* Need label immediately before tbtab, so we can compute
26310 its offset from the function start. */
26311 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
26312 ASM_OUTPUT_LABEL (file
, fname
);
26315 /* The .tbtab pseudo-op can only be used for the first eight
26316 expressions, since it can't handle the possibly variable
26317 length fields that follow. However, if you omit the optional
26318 fields, the assembler outputs zeros for all optional fields
26319 anyways, giving each variable length field is minimum length
26320 (as defined in sys/debug.h). Thus we can not use the .tbtab
26321 pseudo-op at all. */
26323 /* An all-zero word flags the start of the tbtab, for debuggers
26324 that have to find it by searching forward from the entry
26325 point or from the current pc. */
26326 fputs ("\t.long 0\n", file
);
26328 /* Tbtab format type. Use format type 0. */
26329 fputs ("\t.byte 0,", file
);
26331 /* Language type. Unfortunately, there does not seem to be any
26332 official way to discover the language being compiled, so we
26333 use language_string.
26334 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
26335 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
26336 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
26337 either, so for now use 0. */
26339 || ! strcmp (language_string
, "GNU GIMPLE")
26340 || ! strcmp (language_string
, "GNU Go")
26341 || ! strcmp (language_string
, "libgccjit"))
26343 else if (! strcmp (language_string
, "GNU F77")
26344 || lang_GNU_Fortran ())
26346 else if (! strcmp (language_string
, "GNU Pascal"))
26348 else if (! strcmp (language_string
, "GNU Ada"))
26350 else if (lang_GNU_CXX ()
26351 || ! strcmp (language_string
, "GNU Objective-C++"))
26353 else if (! strcmp (language_string
, "GNU Java"))
26355 else if (! strcmp (language_string
, "GNU Objective-C"))
26358 gcc_unreachable ();
26359 fprintf (file
, "%d,", i
);
26361 /* 8 single bit fields: global linkage (not set for C extern linkage,
26362 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
26363 from start of procedure stored in tbtab, internal function, function
26364 has controlled storage, function has no toc, function uses fp,
26365 function logs/aborts fp operations. */
26366 /* Assume that fp operations are used if any fp reg must be saved. */
26367 fprintf (file
, "%d,",
26368 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
26370 /* 6 bitfields: function is interrupt handler, name present in
26371 proc table, function calls alloca, on condition directives
26372 (controls stack walks, 3 bits), saves condition reg, saves
26374 /* The `function calls alloca' bit seems to be set whenever reg 31 is
26375 set up as a frame pointer, even when there is no alloca call. */
26376 fprintf (file
, "%d,",
26377 ((optional_tbtab
<< 6)
26378 | ((optional_tbtab
& frame_pointer_needed
) << 5)
26379 | (info
->cr_save_p
<< 1)
26380 | (info
->lr_save_p
)));
26382 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
26384 fprintf (file
, "%d,",
26385 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
26387 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
26388 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
26390 if (optional_tbtab
)
26392 /* Compute the parameter info from the function decl argument
26395 int next_parm_info_bit
= 31;
26397 for (decl
= DECL_ARGUMENTS (current_function_decl
);
26398 decl
; decl
= DECL_CHAIN (decl
))
26400 rtx parameter
= DECL_INCOMING_RTL (decl
);
26401 machine_mode mode
= GET_MODE (parameter
);
26403 if (GET_CODE (parameter
) == REG
)
26405 if (SCALAR_FLOAT_MODE_P (mode
))
26428 gcc_unreachable ();
26431 /* If only one bit will fit, don't or in this entry. */
26432 if (next_parm_info_bit
> 0)
26433 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
26434 next_parm_info_bit
-= 2;
26438 fixed_parms
+= ((GET_MODE_SIZE (mode
)
26439 + (UNITS_PER_WORD
- 1))
26441 next_parm_info_bit
-= 1;
26447 /* Number of fixed point parameters. */
26448 /* This is actually the number of words of fixed point parameters; thus
26449 an 8 byte struct counts as 2; and thus the maximum value is 8. */
26450 fprintf (file
, "%d,", fixed_parms
);
26452 /* 2 bitfields: number of floating point parameters (7 bits), parameters
26454 /* This is actually the number of fp registers that hold parameters;
26455 and thus the maximum value is 13. */
26456 /* Set parameters on stack bit if parameters are not in their original
26457 registers, regardless of whether they are on the stack? Xlc
26458 seems to set the bit when not optimizing. */
26459 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
26461 if (! optional_tbtab
)
26464 /* Optional fields follow. Some are variable length. */
26466 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
26467 11 double float. */
26468 /* There is an entry for each parameter in a register, in the order that
26469 they occur in the parameter list. Any intervening arguments on the
26470 stack are ignored. If the list overflows a long (max possible length
26471 34 bits) then completely leave off all elements that don't fit. */
26472 /* Only emit this long if there was at least one parameter. */
26473 if (fixed_parms
|| float_parms
)
26474 fprintf (file
, "\t.long %d\n", parm_info
);
26476 /* Offset from start of code to tb table. */
26477 fputs ("\t.long ", file
);
26478 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
26479 RS6000_OUTPUT_BASENAME (file
, fname
);
26481 rs6000_output_function_entry (file
, fname
);
26484 /* Interrupt handler mask. */
26485 /* Omit this long, since we never set the interrupt handler bit
26488 /* Number of CTL (controlled storage) anchors. */
26489 /* Omit this long, since the has_ctl bit is never set above. */
26491 /* Displacement into stack of each CTL anchor. */
26492 /* Omit this list of longs, because there are no CTL anchors. */
26494 /* Length of function name. */
26497 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
26499 /* Function name. */
26500 assemble_string (fname
, strlen (fname
));
26502 /* Register for alloca automatic storage; this is always reg 31.
26503 Only emit this if the alloca bit was set above. */
26504 if (frame_pointer_needed
)
26505 fputs ("\t.byte 31\n", file
);
26507 fputs ("\t.align 2\n", file
);
26511 /* -fsplit-stack support. */
26513 /* A SYMBOL_REF for __morestack. */
26514 static GTY(()) rtx morestack_ref
;
26517 gen_add3_const (rtx rt
, rtx ra
, long c
)
26520 return gen_adddi3 (rt
, ra
, GEN_INT (c
));
26522 return gen_addsi3 (rt
, ra
, GEN_INT (c
));
26525 /* Emit -fsplit-stack prologue, which goes before the regular function
26526 prologue (at local entry point in the case of ELFv2). */
26529 rs6000_expand_split_stack_prologue (void)
26531 rs6000_stack_t
*info
= rs6000_stack_info ();
26532 unsigned HOST_WIDE_INT allocate
;
26533 long alloc_hi
, alloc_lo
;
26534 rtx r0
, r1
, r12
, lr
, ok_label
, compare
, jump
, call_fusage
;
26537 gcc_assert (flag_split_stack
&& reload_completed
);
26542 if (global_regs
[29])
26544 error ("-fsplit-stack uses register r29");
26545 inform (DECL_SOURCE_LOCATION (global_regs_decl
[29]),
26546 "conflicts with %qD", global_regs_decl
[29]);
26549 allocate
= info
->total_size
;
26550 if (allocate
> (unsigned HOST_WIDE_INT
) 1 << 31)
26552 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
26555 if (morestack_ref
== NULL_RTX
)
26557 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
26558 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
26559 | SYMBOL_FLAG_FUNCTION
);
26562 r0
= gen_rtx_REG (Pmode
, 0);
26563 r1
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26564 r12
= gen_rtx_REG (Pmode
, 12);
26565 emit_insn (gen_load_split_stack_limit (r0
));
26566 /* Always emit two insns here to calculate the requested stack,
26567 so that the linker can edit them when adjusting size for calling
26568 non-split-stack code. */
26569 alloc_hi
= (-allocate
+ 0x8000) & ~0xffffL
;
26570 alloc_lo
= -allocate
- alloc_hi
;
26573 emit_insn (gen_add3_const (r12
, r1
, alloc_hi
));
26575 emit_insn (gen_add3_const (r12
, r12
, alloc_lo
));
26577 emit_insn (gen_nop ());
26581 emit_insn (gen_add3_const (r12
, r1
, alloc_lo
));
26582 emit_insn (gen_nop ());
26585 compare
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
26586 emit_insn (gen_rtx_SET (compare
, gen_rtx_COMPARE (CCUNSmode
, r12
, r0
)));
26587 ok_label
= gen_label_rtx ();
26588 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
26589 gen_rtx_GEU (VOIDmode
, compare
, const0_rtx
),
26590 gen_rtx_LABEL_REF (VOIDmode
, ok_label
),
26592 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
26593 JUMP_LABEL (jump
) = ok_label
;
26594 /* Mark the jump as very likely to be taken. */
26595 add_int_reg_note (jump
, REG_BR_PROB
,
26596 REG_BR_PROB_BASE
- REG_BR_PROB_BASE
/ 100);
26598 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
26599 insn
= emit_move_insn (r0
, lr
);
26600 RTX_FRAME_RELATED_P (insn
) = 1;
26601 insn
= emit_insn (gen_frame_store (r0
, r1
, info
->lr_save_offset
));
26602 RTX_FRAME_RELATED_P (insn
) = 1;
26604 insn
= emit_call_insn (gen_call (gen_rtx_MEM (SImode
, morestack_ref
),
26605 const0_rtx
, const0_rtx
));
26606 call_fusage
= NULL_RTX
;
26607 use_reg (&call_fusage
, r12
);
26608 add_function_usage_to (insn
, call_fusage
);
26609 emit_insn (gen_frame_load (r0
, r1
, info
->lr_save_offset
));
26610 insn
= emit_move_insn (lr
, r0
);
26611 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
26612 RTX_FRAME_RELATED_P (insn
) = 1;
26613 emit_insn (gen_split_stack_return ());
26615 emit_label (ok_label
);
26616 LABEL_NUSES (ok_label
) = 1;
26619 /* Return the internal arg pointer used for function incoming
26620 arguments. When -fsplit-stack, the arg pointer is r12 so we need
26621 to copy it to a pseudo in order for it to be preserved over calls
26622 and suchlike. We'd really like to use a pseudo here for the
26623 internal arg pointer but data-flow analysis is not prepared to
26624 accept pseudos as live at the beginning of a function. */
26627 rs6000_internal_arg_pointer (void)
26629 if (flag_split_stack
26630 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
26634 if (cfun
->machine
->split_stack_arg_pointer
== NULL_RTX
)
26638 cfun
->machine
->split_stack_arg_pointer
= gen_reg_rtx (Pmode
);
26639 REG_POINTER (cfun
->machine
->split_stack_arg_pointer
) = 1;
26641 /* Put the pseudo initialization right after the note at the
26642 beginning of the function. */
26643 pat
= gen_rtx_SET (cfun
->machine
->split_stack_arg_pointer
,
26644 gen_rtx_REG (Pmode
, 12));
26645 push_topmost_sequence ();
26646 emit_insn_after (pat
, get_insns ());
26647 pop_topmost_sequence ();
26649 return plus_constant (Pmode
, cfun
->machine
->split_stack_arg_pointer
,
26650 FIRST_PARM_OFFSET (current_function_decl
));
26652 return virtual_incoming_args_rtx
;
26655 /* We may have to tell the dataflow pass that the split stack prologue
26656 is initializing a register. */
26659 rs6000_live_on_entry (bitmap regs
)
26661 if (flag_split_stack
)
26662 bitmap_set_bit (regs
, 12);
26665 /* Emit -fsplit-stack dynamic stack allocation space check. */
26668 rs6000_split_stack_space_check (rtx size
, rtx label
)
26670 rtx sp
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26671 rtx limit
= gen_reg_rtx (Pmode
);
26672 rtx requested
= gen_reg_rtx (Pmode
);
26673 rtx cmp
= gen_reg_rtx (CCUNSmode
);
26676 emit_insn (gen_load_split_stack_limit (limit
));
26677 if (CONST_INT_P (size
))
26678 emit_insn (gen_add3_insn (requested
, sp
, GEN_INT (-INTVAL (size
))));
26681 size
= force_reg (Pmode
, size
);
26682 emit_move_insn (requested
, gen_rtx_MINUS (Pmode
, sp
, size
));
26684 emit_insn (gen_rtx_SET (cmp
, gen_rtx_COMPARE (CCUNSmode
, requested
, limit
)));
26685 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
26686 gen_rtx_GEU (VOIDmode
, cmp
, const0_rtx
),
26687 gen_rtx_LABEL_REF (VOIDmode
, label
),
26689 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
26690 JUMP_LABEL (jump
) = label
;
26693 /* A C compound statement that outputs the assembler code for a thunk
26694 function, used to implement C++ virtual function calls with
26695 multiple inheritance. The thunk acts as a wrapper around a virtual
26696 function, adjusting the implicit object parameter before handing
26697 control off to the real function.
26699 First, emit code to add the integer DELTA to the location that
26700 contains the incoming first argument. Assume that this argument
26701 contains a pointer, and is the one used to pass the `this' pointer
26702 in C++. This is the incoming argument *before* the function
26703 prologue, e.g. `%o0' on a sparc. The addition must preserve the
26704 values of all other incoming arguments.
26706 After the addition, emit code to jump to FUNCTION, which is a
26707 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
26708 not touch the return address. Hence returning from FUNCTION will
26709 return to whoever called the current `thunk'.
26711 The effect must be as if FUNCTION had been called directly with the
26712 adjusted first argument. This macro is responsible for emitting
26713 all of the code for a thunk function; output_function_prologue()
26714 and output_function_epilogue() are not invoked.
26716 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
26717 been extracted from it.) It might possibly be useful on some
26718 targets, but probably not.
26720 If you do not define this macro, the target-independent code in the
26721 C++ frontend will generate a less efficient heavyweight thunk that
26722 calls FUNCTION instead of jumping to it. The generic approach does
26723 not support varargs. */
26726 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
26727 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
26730 rtx this_rtx
, funexp
;
26733 reload_completed
= 1;
26734 epilogue_completed
= 1;
26736 /* Mark the end of the (empty) prologue. */
26737 emit_note (NOTE_INSN_PROLOGUE_END
);
26739 /* Find the "this" pointer. If the function returns a structure,
26740 the structure return pointer is in r3. */
26741 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
26742 this_rtx
= gen_rtx_REG (Pmode
, 4);
26744 this_rtx
= gen_rtx_REG (Pmode
, 3);
26746 /* Apply the constant offset, if required. */
26748 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
26750 /* Apply the offset from the vtable, if required. */
26753 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
26754 rtx tmp
= gen_rtx_REG (Pmode
, 12);
26756 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
26757 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
26759 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
26760 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
26764 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
26766 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
26768 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
26771 /* Generate a tail call to the target function. */
26772 if (!TREE_USED (function
))
26774 assemble_external (function
);
26775 TREE_USED (function
) = 1;
26777 funexp
= XEXP (DECL_RTL (function
), 0);
26778 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
26781 if (MACHOPIC_INDIRECT
)
26782 funexp
= machopic_indirect_call_target (funexp
);
26785 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
26786 generate sibcall RTL explicitly. */
26787 insn
= emit_call_insn (
26788 gen_rtx_PARALLEL (VOIDmode
,
26790 gen_rtx_CALL (VOIDmode
,
26791 funexp
, const0_rtx
),
26792 gen_rtx_USE (VOIDmode
, const0_rtx
),
26793 gen_rtx_USE (VOIDmode
,
26794 gen_rtx_REG (SImode
,
26796 simple_return_rtx
)));
26797 SIBLING_CALL_P (insn
) = 1;
26800 /* Ensure we have a global entry point for the thunk. ??? We could
26801 avoid that if the target routine doesn't need a global entry point,
26802 but we do not know whether this is the case at this point. */
26803 if (DEFAULT_ABI
== ABI_ELFv2
)
26804 cfun
->machine
->r2_setup_needed
= true;
26806 /* Run just enough of rest_of_compilation to get the insns emitted.
26807 There's not really enough bulk here to make other passes such as
26808 instruction scheduling worth while. Note that use_thunk calls
26809 assemble_start_function and assemble_end_function. */
26810 insn
= get_insns ();
26811 shorten_branches (insn
);
26812 final_start_function (insn
, file
, 1);
26813 final (insn
, file
, 1);
26814 final_end_function ();
26816 reload_completed
= 0;
26817 epilogue_completed
= 0;
26820 /* A quick summary of the various types of 'constant-pool tables'
26823 Target Flags Name One table per
26824 AIX (none) AIX TOC object file
26825 AIX -mfull-toc AIX TOC object file
26826 AIX -mminimal-toc AIX minimal TOC translation unit
26827 SVR4/EABI (none) SVR4 SDATA object file
26828 SVR4/EABI -fpic SVR4 pic object file
26829 SVR4/EABI -fPIC SVR4 PIC translation unit
26830 SVR4/EABI -mrelocatable EABI TOC function
26831 SVR4/EABI -maix AIX TOC object file
26832 SVR4/EABI -maix -mminimal-toc
26833 AIX minimal TOC translation unit
26835 Name Reg. Set by entries contains:
26836 made by addrs? fp? sum?
26838 AIX TOC 2 crt0 as Y option option
26839 AIX minimal TOC 30 prolog gcc Y Y option
26840 SVR4 SDATA 13 crt0 gcc N Y N
26841 SVR4 pic 30 prolog ld Y not yet N
26842 SVR4 PIC 30 prolog gcc Y option option
26843 EABI TOC 30 prolog gcc Y option option
26847 /* Hash functions for the hash table. */
26850 rs6000_hash_constant (rtx k
)
26852 enum rtx_code code
= GET_CODE (k
);
26853 machine_mode mode
= GET_MODE (k
);
26854 unsigned result
= (code
<< 3) ^ mode
;
26855 const char *format
;
26858 format
= GET_RTX_FORMAT (code
);
26859 flen
= strlen (format
);
26865 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
26867 case CONST_WIDE_INT
:
26870 flen
= CONST_WIDE_INT_NUNITS (k
);
26871 for (i
= 0; i
< flen
; i
++)
26872 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
26877 if (mode
!= VOIDmode
)
26878 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
26890 for (; fidx
< flen
; fidx
++)
26891 switch (format
[fidx
])
26896 const char *str
= XSTR (k
, fidx
);
26897 len
= strlen (str
);
26898 result
= result
* 613 + len
;
26899 for (i
= 0; i
< len
; i
++)
26900 result
= result
* 613 + (unsigned) str
[i
];
26905 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
26909 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
26912 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
26913 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
26917 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
26918 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
26925 gcc_unreachable ();
26932 toc_hasher::hash (toc_hash_struct
*thc
)
26934 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
26937 /* Compare H1 and H2 for equivalence. */
26940 toc_hasher::equal (toc_hash_struct
*h1
, toc_hash_struct
*h2
)
26945 if (h1
->key_mode
!= h2
->key_mode
)
26948 return rtx_equal_p (r1
, r2
);
26951 /* These are the names given by the C++ front-end to vtables, and
26952 vtable-like objects. Ideally, this logic should not be here;
26953 instead, there should be some programmatic way of inquiring as
26954 to whether or not an object is a vtable. */
26956 #define VTABLE_NAME_P(NAME) \
26957 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
26958 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
26959 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
26960 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
26961 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
26963 #ifdef NO_DOLLAR_IN_LABEL
26964 /* Return a GGC-allocated character string translating dollar signs in
26965 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
26968 rs6000_xcoff_strip_dollar (const char *name
)
26974 q
= (const char *) strchr (name
, '$');
26976 if (q
== 0 || q
== name
)
26979 len
= strlen (name
);
26980 strip
= XALLOCAVEC (char, len
+ 1);
26981 strcpy (strip
, name
);
26982 p
= strip
+ (q
- name
);
26986 p
= strchr (p
+ 1, '$');
26989 return ggc_alloc_string (strip
, len
);
26994 rs6000_output_symbol_ref (FILE *file
, rtx x
)
26996 /* Currently C++ toc references to vtables can be emitted before it
26997 is decided whether the vtable is public or private. If this is
26998 the case, then the linker will eventually complain that there is
26999 a reference to an unknown section. Thus, for vtables only,
27000 we emit the TOC reference to reference the symbol and not the
27002 const char *name
= XSTR (x
, 0);
27004 tree decl
= SYMBOL_REF_DECL (x
);
27005 if (decl
/* sync condition with assemble_external () */
27006 && DECL_P (decl
) && DECL_EXTERNAL (decl
) && TREE_PUBLIC (decl
)
27007 && (TREE_CODE (decl
) == VAR_DECL
27008 || TREE_CODE (decl
) == FUNCTION_DECL
)
27009 && name
[strlen (name
) - 1] != ']')
27011 name
= concat (name
,
27012 (TREE_CODE (decl
) == FUNCTION_DECL
27013 ? "[DS]" : "[UA]"),
27015 XSTR (x
, 0) = name
;
27018 if (VTABLE_NAME_P (name
))
27020 RS6000_OUTPUT_BASENAME (file
, name
);
27023 assemble_name (file
, name
);
27026 /* Output a TOC entry. We derive the entry name from what is being
27030 output_toc (FILE *file
, rtx x
, int labelno
, machine_mode mode
)
27033 const char *name
= buf
;
27035 HOST_WIDE_INT offset
= 0;
27037 gcc_assert (!TARGET_NO_TOC
);
27039 /* When the linker won't eliminate them, don't output duplicate
27040 TOC entries (this happens on AIX if there is any kind of TOC,
27041 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
27043 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
27045 struct toc_hash_struct
*h
;
27047 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
27048 time because GGC is not initialized at that point. */
27049 if (toc_hash_table
== NULL
)
27050 toc_hash_table
= hash_table
<toc_hasher
>::create_ggc (1021);
27052 h
= ggc_alloc
<toc_hash_struct
> ();
27054 h
->key_mode
= mode
;
27055 h
->labelno
= labelno
;
27057 toc_hash_struct
**found
= toc_hash_table
->find_slot (h
, INSERT
);
27058 if (*found
== NULL
)
27060 else /* This is indeed a duplicate.
27061 Set this label equal to that label. */
27063 fputs ("\t.set ", file
);
27064 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
27065 fprintf (file
, "%d,", labelno
);
27066 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
27067 fprintf (file
, "%d\n", ((*found
)->labelno
));
27070 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
27071 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
27072 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
27074 fputs ("\t.set ", file
);
27075 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
27076 fprintf (file
, "%d,", labelno
);
27077 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
27078 fprintf (file
, "%d\n", ((*found
)->labelno
));
27085 /* If we're going to put a double constant in the TOC, make sure it's
27086 aligned properly when strict alignment is on. */
27087 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
27088 && STRICT_ALIGNMENT
27089 && GET_MODE_BITSIZE (mode
) >= 64
27090 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
27091 ASM_OUTPUT_ALIGN (file
, 3);
27094 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
27096 /* Handle FP constants specially. Note that if we have a minimal
27097 TOC, things we put here aren't actually in the TOC, so we can allow
27099 if (GET_CODE (x
) == CONST_DOUBLE
&&
27100 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
27101 || GET_MODE (x
) == IFmode
|| GET_MODE (x
) == KFmode
))
27103 REAL_VALUE_TYPE rv
;
27106 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
27107 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
27108 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
27110 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
27114 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27115 fputs (DOUBLE_INT_ASM_OP
, file
);
27117 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
27118 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
27119 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
27120 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
27121 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
27122 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
27123 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
27124 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
27129 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27130 fputs ("\t.long ", file
);
27132 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
27133 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
27134 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
27135 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
27136 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
27137 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
27141 else if (GET_CODE (x
) == CONST_DOUBLE
&&
27142 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
27144 REAL_VALUE_TYPE rv
;
27147 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
27149 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
27150 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
27152 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
27156 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27157 fputs (DOUBLE_INT_ASM_OP
, file
);
27159 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
27160 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
27161 fprintf (file
, "0x%lx%08lx\n",
27162 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
27163 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
27168 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27169 fputs ("\t.long ", file
);
27171 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
27172 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
27173 fprintf (file
, "0x%lx,0x%lx\n",
27174 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
27178 else if (GET_CODE (x
) == CONST_DOUBLE
&&
27179 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
27181 REAL_VALUE_TYPE rv
;
27184 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
27185 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
27186 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
27188 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
27192 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27193 fputs (DOUBLE_INT_ASM_OP
, file
);
27195 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
27196 if (WORDS_BIG_ENDIAN
)
27197 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
27199 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
27204 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27205 fputs ("\t.long ", file
);
27207 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
27208 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
27212 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
27214 unsigned HOST_WIDE_INT low
;
27215 HOST_WIDE_INT high
;
27217 low
= INTVAL (x
) & 0xffffffff;
27218 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
27220 /* TOC entries are always Pmode-sized, so when big-endian
27221 smaller integer constants in the TOC need to be padded.
27222 (This is still a win over putting the constants in
27223 a separate constant pool, because then we'd have
27224 to have both a TOC entry _and_ the actual constant.)
27226 For a 32-bit target, CONST_INT values are loaded and shifted
27227 entirely within `low' and can be stored in one TOC entry. */
27229 /* It would be easy to make this work, but it doesn't now. */
27230 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
27232 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
27235 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
27236 high
= (HOST_WIDE_INT
) low
>> 32;
27242 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27243 fputs (DOUBLE_INT_ASM_OP
, file
);
27245 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
27246 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
27247 fprintf (file
, "0x%lx%08lx\n",
27248 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
27253 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
27255 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27256 fputs ("\t.long ", file
);
27258 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
27259 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
27260 fprintf (file
, "0x%lx,0x%lx\n",
27261 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
27265 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27266 fputs ("\t.long ", file
);
27268 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
27269 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
27275 if (GET_CODE (x
) == CONST
)
27277 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
27278 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
27280 base
= XEXP (XEXP (x
, 0), 0);
27281 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
27284 switch (GET_CODE (base
))
27287 name
= XSTR (base
, 0);
27291 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
27292 CODE_LABEL_NUMBER (XEXP (base
, 0)));
27296 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
27300 gcc_unreachable ();
27303 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
27304 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
27307 fputs ("\t.tc ", file
);
27308 RS6000_OUTPUT_BASENAME (file
, name
);
27311 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
27313 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
27315 /* Mark large TOC symbols on AIX with [TE] so they are mapped
27316 after other TOC symbols, reducing overflow of small TOC access
27317 to [TC] symbols. */
27318 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
27319 ? "[TE]," : "[TC],", file
);
27322 /* Currently C++ toc references to vtables can be emitted before it
27323 is decided whether the vtable is public or private. If this is
27324 the case, then the linker will eventually complain that there is
27325 a TOC reference to an unknown section. Thus, for vtables only,
27326 we emit the TOC reference to reference the symbol and not the
27328 if (VTABLE_NAME_P (name
))
27330 RS6000_OUTPUT_BASENAME (file
, name
);
27332 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
27333 else if (offset
> 0)
27334 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
27337 output_addr_const (file
, x
);
27340 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
)
27342 switch (SYMBOL_REF_TLS_MODEL (base
))
27346 case TLS_MODEL_LOCAL_EXEC
:
27347 fputs ("@le", file
);
27349 case TLS_MODEL_INITIAL_EXEC
:
27350 fputs ("@ie", file
);
27352 /* Use global-dynamic for local-dynamic. */
27353 case TLS_MODEL_GLOBAL_DYNAMIC
:
27354 case TLS_MODEL_LOCAL_DYNAMIC
:
27356 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
27357 fputs ("\t.tc .", file
);
27358 RS6000_OUTPUT_BASENAME (file
, name
);
27359 fputs ("[TC],", file
);
27360 output_addr_const (file
, x
);
27361 fputs ("@m", file
);
27364 gcc_unreachable ();
27372 /* Output an assembler pseudo-op to write an ASCII string of N characters
27373 starting at P to FILE.
27375 On the RS/6000, we have to do this using the .byte operation and
27376 write out special characters outside the quoted string.
27377 Also, the assembler is broken; very long strings are truncated,
27378 so we must artificially break them up early. */
27381 output_ascii (FILE *file
, const char *p
, int n
)
27384 int i
, count_string
;
27385 const char *for_string
= "\t.byte \"";
27386 const char *for_decimal
= "\t.byte ";
27387 const char *to_close
= NULL
;
27390 for (i
= 0; i
< n
; i
++)
27393 if (c
>= ' ' && c
< 0177)
27396 fputs (for_string
, file
);
27399 /* Write two quotes to get one. */
27407 for_decimal
= "\"\n\t.byte ";
27411 if (count_string
>= 512)
27413 fputs (to_close
, file
);
27415 for_string
= "\t.byte \"";
27416 for_decimal
= "\t.byte ";
27424 fputs (for_decimal
, file
);
27425 fprintf (file
, "%d", c
);
27427 for_string
= "\n\t.byte \"";
27428 for_decimal
= ", ";
27434 /* Now close the string if we have written one. Then end the line. */
27436 fputs (to_close
, file
);
27439 /* Generate a unique section name for FILENAME for a section type
27440 represented by SECTION_DESC. Output goes into BUF.
27442 SECTION_DESC can be any string, as long as it is different for each
27443 possible section type.
27445 We name the section in the same manner as xlc. The name begins with an
27446 underscore followed by the filename (after stripping any leading directory
27447 names) with the last period replaced by the string SECTION_DESC. If
27448 FILENAME does not contain a period, SECTION_DESC is appended to the end of
27452 rs6000_gen_section_name (char **buf
, const char *filename
,
27453 const char *section_desc
)
27455 const char *q
, *after_last_slash
, *last_period
= 0;
27459 after_last_slash
= filename
;
27460 for (q
= filename
; *q
; q
++)
27463 after_last_slash
= q
+ 1;
27464 else if (*q
== '.')
27468 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
27469 *buf
= (char *) xmalloc (len
);
27474 for (q
= after_last_slash
; *q
; q
++)
27476 if (q
== last_period
)
27478 strcpy (p
, section_desc
);
27479 p
+= strlen (section_desc
);
27483 else if (ISALNUM (*q
))
27487 if (last_period
== 0)
27488 strcpy (p
, section_desc
);
27493 /* Emit profile function. */
27496 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
27498 /* Non-standard profiling for kernels, which just saves LR then calls
27499 _mcount without worrying about arg saves. The idea is to change
27500 the function prologue as little as possible as it isn't easy to
27501 account for arg save/restore code added just for _mcount. */
27502 if (TARGET_PROFILE_KERNEL
)
27505 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27507 #ifndef NO_PROFILE_COUNTERS
27508 # define NO_PROFILE_COUNTERS 0
27510 if (NO_PROFILE_COUNTERS
)
27511 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
27512 LCT_NORMAL
, VOIDmode
, 0);
27516 const char *label_name
;
27519 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
27520 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
27521 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
27523 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
27524 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
27527 else if (DEFAULT_ABI
== ABI_DARWIN
)
27529 const char *mcount_name
= RS6000_MCOUNT
;
27530 int caller_addr_regno
= LR_REGNO
;
27532 /* Be conservative and always set this, at least for now. */
27533 crtl
->uses_pic_offset_table
= 1;
27536 /* For PIC code, set up a stub and collect the caller's address
27537 from r0, which is where the prologue puts it. */
27538 if (MACHOPIC_INDIRECT
27539 && crtl
->uses_pic_offset_table
)
27540 caller_addr_regno
= 0;
27542 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
27543 LCT_NORMAL
, VOIDmode
, 1,
27544 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
27548 /* Write function profiler code. */
27551 output_function_profiler (FILE *file
, int labelno
)
27555 switch (DEFAULT_ABI
)
27558 gcc_unreachable ();
27563 warning (0, "no profiling of 64-bit code for this ABI");
27566 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
27567 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
27568 if (NO_PROFILE_COUNTERS
)
27570 asm_fprintf (file
, "\tstw %s,4(%s)\n",
27571 reg_names
[0], reg_names
[1]);
27573 else if (TARGET_SECURE_PLT
&& flag_pic
)
27575 if (TARGET_LINK_STACK
)
27578 get_ppc476_thunk_name (name
);
27579 asm_fprintf (file
, "\tbl %s\n", name
);
27582 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
27583 asm_fprintf (file
, "\tstw %s,4(%s)\n",
27584 reg_names
[0], reg_names
[1]);
27585 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
27586 asm_fprintf (file
, "\taddis %s,%s,",
27587 reg_names
[12], reg_names
[12]);
27588 assemble_name (file
, buf
);
27589 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
27590 assemble_name (file
, buf
);
27591 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
27593 else if (flag_pic
== 1)
27595 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
27596 asm_fprintf (file
, "\tstw %s,4(%s)\n",
27597 reg_names
[0], reg_names
[1]);
27598 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
27599 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
27600 assemble_name (file
, buf
);
27601 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
27603 else if (flag_pic
> 1)
27605 asm_fprintf (file
, "\tstw %s,4(%s)\n",
27606 reg_names
[0], reg_names
[1]);
27607 /* Now, we need to get the address of the label. */
27608 if (TARGET_LINK_STACK
)
27611 get_ppc476_thunk_name (name
);
27612 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
27613 assemble_name (file
, buf
);
27614 fputs ("-.\n1:", file
);
27615 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
27616 asm_fprintf (file
, "\taddi %s,%s,4\n",
27617 reg_names
[11], reg_names
[11]);
27621 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
27622 assemble_name (file
, buf
);
27623 fputs ("-.\n1:", file
);
27624 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
27626 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
27627 reg_names
[0], reg_names
[11]);
27628 asm_fprintf (file
, "\tadd %s,%s,%s\n",
27629 reg_names
[0], reg_names
[0], reg_names
[11]);
27633 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
27634 assemble_name (file
, buf
);
27635 fputs ("@ha\n", file
);
27636 asm_fprintf (file
, "\tstw %s,4(%s)\n",
27637 reg_names
[0], reg_names
[1]);
27638 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
27639 assemble_name (file
, buf
);
27640 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
27643 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
27644 fprintf (file
, "\tbl %s%s\n",
27645 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
27651 /* Don't do anything, done in output_profile_hook (). */
27658 /* The following variable value is the last issued insn. */
27660 static rtx last_scheduled_insn
;
27662 /* The following variable helps to balance issuing of load and
27663 store instructions */
27665 static int load_store_pendulum
;
27667 /* Power4 load update and store update instructions are cracked into a
27668 load or store and an integer insn which are executed in the same cycle.
27669 Branches have their own dispatch slot which does not count against the
27670 GCC issue rate, but it changes the program flow so there are no other
27671 instructions to issue in this cycle. */
27674 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
27676 last_scheduled_insn
= insn
;
27677 if (GET_CODE (PATTERN (insn
)) == USE
27678 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27680 cached_can_issue_more
= more
;
27681 return cached_can_issue_more
;
27684 if (insn_terminates_group_p (insn
, current_group
))
27686 cached_can_issue_more
= 0;
27687 return cached_can_issue_more
;
27690 /* If no reservation, but reach here */
27691 if (recog_memoized (insn
) < 0)
27694 if (rs6000_sched_groups
)
27696 if (is_microcoded_insn (insn
))
27697 cached_can_issue_more
= 0;
27698 else if (is_cracked_insn (insn
))
27699 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
27701 cached_can_issue_more
= more
- 1;
27703 return cached_can_issue_more
;
27706 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
27709 cached_can_issue_more
= more
- 1;
27710 return cached_can_issue_more
;
27714 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
27716 int r
= rs6000_variable_issue_1 (insn
, more
);
27718 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
27722 /* Adjust the cost of a scheduling dependency. Return the new cost of
27723 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
27726 rs6000_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
, int cost
)
27728 enum attr_type attr_type
;
27730 if (! recog_memoized (insn
))
27733 switch (REG_NOTE_KIND (link
))
27737 /* Data dependency; DEP_INSN writes a register that INSN reads
27738 some cycles later. */
27740 /* Separate a load from a narrower, dependent store. */
27741 if (rs6000_sched_groups
27742 && GET_CODE (PATTERN (insn
)) == SET
27743 && GET_CODE (PATTERN (dep_insn
)) == SET
27744 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
27745 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
27746 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
27747 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
27750 attr_type
= get_attr_type (insn
);
27755 /* Tell the first scheduling pass about the latency between
27756 a mtctr and bctr (and mtlr and br/blr). The first
27757 scheduling pass will not know about this latency since
27758 the mtctr instruction, which has the latency associated
27759 to it, will be generated by reload. */
27762 /* Leave some extra cycles between a compare and its
27763 dependent branch, to inhibit expensive mispredicts. */
27764 if ((rs6000_cpu_attr
== CPU_PPC603
27765 || rs6000_cpu_attr
== CPU_PPC604
27766 || rs6000_cpu_attr
== CPU_PPC604E
27767 || rs6000_cpu_attr
== CPU_PPC620
27768 || rs6000_cpu_attr
== CPU_PPC630
27769 || rs6000_cpu_attr
== CPU_PPC750
27770 || rs6000_cpu_attr
== CPU_PPC7400
27771 || rs6000_cpu_attr
== CPU_PPC7450
27772 || rs6000_cpu_attr
== CPU_PPCE5500
27773 || rs6000_cpu_attr
== CPU_PPCE6500
27774 || rs6000_cpu_attr
== CPU_POWER4
27775 || rs6000_cpu_attr
== CPU_POWER5
27776 || rs6000_cpu_attr
== CPU_POWER7
27777 || rs6000_cpu_attr
== CPU_POWER8
27778 || rs6000_cpu_attr
== CPU_CELL
)
27779 && recog_memoized (dep_insn
)
27780 && (INSN_CODE (dep_insn
) >= 0))
27782 switch (get_attr_type (dep_insn
))
27785 case TYPE_FPCOMPARE
:
27786 case TYPE_CR_LOGICAL
:
27787 case TYPE_DELAYED_CR
:
27791 if (get_attr_dot (dep_insn
) == DOT_YES
)
27796 if (get_attr_dot (dep_insn
) == DOT_YES
27797 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
27808 if ((rs6000_cpu
== PROCESSOR_POWER6
)
27809 && recog_memoized (dep_insn
)
27810 && (INSN_CODE (dep_insn
) >= 0))
27813 if (GET_CODE (PATTERN (insn
)) != SET
)
27814 /* If this happens, we have to extend this to schedule
27815 optimally. Return default for now. */
27818 /* Adjust the cost for the case where the value written
27819 by a fixed point operation is used as the address
27820 gen value on a store. */
27821 switch (get_attr_type (dep_insn
))
27826 if (! store_data_bypass_p (dep_insn
, insn
))
27827 return get_attr_sign_extend (dep_insn
)
27828 == SIGN_EXTEND_YES
? 6 : 4;
27833 if (! store_data_bypass_p (dep_insn
, insn
))
27834 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
27844 if (! store_data_bypass_p (dep_insn
, insn
))
27852 if (get_attr_update (dep_insn
) == UPDATE_YES
27853 && ! store_data_bypass_p (dep_insn
, insn
))
27859 if (! store_data_bypass_p (dep_insn
, insn
))
27865 if (! store_data_bypass_p (dep_insn
, insn
))
27866 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
27876 if ((rs6000_cpu
== PROCESSOR_POWER6
)
27877 && recog_memoized (dep_insn
)
27878 && (INSN_CODE (dep_insn
) >= 0))
27881 /* Adjust the cost for the case where the value written
27882 by a fixed point instruction is used within the address
27883 gen portion of a subsequent load(u)(x) */
27884 switch (get_attr_type (dep_insn
))
27889 if (set_to_load_agen (dep_insn
, insn
))
27890 return get_attr_sign_extend (dep_insn
)
27891 == SIGN_EXTEND_YES
? 6 : 4;
27896 if (set_to_load_agen (dep_insn
, insn
))
27897 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
27907 if (set_to_load_agen (dep_insn
, insn
))
27915 if (get_attr_update (dep_insn
) == UPDATE_YES
27916 && set_to_load_agen (dep_insn
, insn
))
27922 if (set_to_load_agen (dep_insn
, insn
))
27928 if (set_to_load_agen (dep_insn
, insn
))
27929 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
27939 if ((rs6000_cpu
== PROCESSOR_POWER6
)
27940 && get_attr_update (insn
) == UPDATE_NO
27941 && recog_memoized (dep_insn
)
27942 && (INSN_CODE (dep_insn
) >= 0)
27943 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
27950 /* Fall out to return default cost. */
27954 case REG_DEP_OUTPUT
:
27955 /* Output dependency; DEP_INSN writes a register that INSN writes some
27957 if ((rs6000_cpu
== PROCESSOR_POWER6
)
27958 && recog_memoized (dep_insn
)
27959 && (INSN_CODE (dep_insn
) >= 0))
27961 attr_type
= get_attr_type (insn
);
27966 if (get_attr_type (dep_insn
) == TYPE_FP
)
27970 if (get_attr_update (insn
) == UPDATE_NO
27971 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
27979 /* Anti dependency; DEP_INSN reads a register that INSN writes some
27984 gcc_unreachable ();
27990 /* Debug version of rs6000_adjust_cost. */
27993 rs6000_debug_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
,
27996 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
28002 switch (REG_NOTE_KIND (link
))
28004 default: dep
= "unknown depencency"; break;
28005 case REG_DEP_TRUE
: dep
= "data dependency"; break;
28006 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
28007 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
28011 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
28012 "%s, insn:\n", ret
, cost
, dep
);
28020 /* The function returns a true if INSN is microcoded.
28021 Return false otherwise. */
28024 is_microcoded_insn (rtx_insn
*insn
)
28026 if (!insn
|| !NONDEBUG_INSN_P (insn
)
28027 || GET_CODE (PATTERN (insn
)) == USE
28028 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28031 if (rs6000_cpu_attr
== CPU_CELL
)
28032 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
28034 if (rs6000_sched_groups
28035 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
28037 enum attr_type type
= get_attr_type (insn
);
28038 if ((type
== TYPE_LOAD
28039 && get_attr_update (insn
) == UPDATE_YES
28040 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
28041 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
28042 && get_attr_update (insn
) == UPDATE_YES
28043 && get_attr_indexed (insn
) == INDEXED_YES
)
28044 || type
== TYPE_MFCR
)
28051 /* The function returns true if INSN is cracked into 2 instructions
28052 by the processor (and therefore occupies 2 issue slots). */
28055 is_cracked_insn (rtx_insn
*insn
)
28057 if (!insn
|| !NONDEBUG_INSN_P (insn
)
28058 || GET_CODE (PATTERN (insn
)) == USE
28059 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28062 if (rs6000_sched_groups
28063 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
28065 enum attr_type type
= get_attr_type (insn
);
28066 if ((type
== TYPE_LOAD
28067 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
28068 && get_attr_update (insn
) == UPDATE_NO
)
28069 || (type
== TYPE_LOAD
28070 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
28071 && get_attr_update (insn
) == UPDATE_YES
28072 && get_attr_indexed (insn
) == INDEXED_NO
)
28073 || (type
== TYPE_STORE
28074 && get_attr_update (insn
) == UPDATE_YES
28075 && get_attr_indexed (insn
) == INDEXED_NO
)
28076 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
28077 && get_attr_update (insn
) == UPDATE_YES
)
28078 || type
== TYPE_DELAYED_CR
28079 || (type
== TYPE_EXTS
28080 && get_attr_dot (insn
) == DOT_YES
)
28081 || (type
== TYPE_SHIFT
28082 && get_attr_dot (insn
) == DOT_YES
28083 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
28084 || (type
== TYPE_MUL
28085 && get_attr_dot (insn
) == DOT_YES
)
28086 || type
== TYPE_DIV
28087 || (type
== TYPE_INSERT
28088 && get_attr_size (insn
) == SIZE_32
))
28095 /* The function returns true if INSN can be issued only from
28096 the branch slot. */
28099 is_branch_slot_insn (rtx_insn
*insn
)
28101 if (!insn
|| !NONDEBUG_INSN_P (insn
)
28102 || GET_CODE (PATTERN (insn
)) == USE
28103 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28106 if (rs6000_sched_groups
)
28108 enum attr_type type
= get_attr_type (insn
);
28109 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
28117 /* The function returns true if out_inst sets a value that is
28118 used in the address generation computation of in_insn */
28120 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
28122 rtx out_set
, in_set
;
28124 /* For performance reasons, only handle the simple case where
28125 both loads are a single_set. */
28126 out_set
= single_set (out_insn
);
28129 in_set
= single_set (in_insn
);
28131 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
28137 /* Try to determine base/offset/size parts of the given MEM.
28138 Return true if successful, false if all the values couldn't
28141 This function only looks for REG or REG+CONST address forms.
28142 REG+REG address form will return false. */
28145 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
28146 HOST_WIDE_INT
*size
)
28149 if MEM_SIZE_KNOWN_P (mem
)
28150 *size
= MEM_SIZE (mem
);
28154 addr_rtx
= (XEXP (mem
, 0));
28155 if (GET_CODE (addr_rtx
) == PRE_MODIFY
)
28156 addr_rtx
= XEXP (addr_rtx
, 1);
28159 while (GET_CODE (addr_rtx
) == PLUS
28160 && CONST_INT_P (XEXP (addr_rtx
, 1)))
28162 *offset
+= INTVAL (XEXP (addr_rtx
, 1));
28163 addr_rtx
= XEXP (addr_rtx
, 0);
28165 if (!REG_P (addr_rtx
))
28172 /* The function returns true if the target storage location of
28173 mem1 is adjacent to the target storage location of mem2 */
28174 /* Return 1 if memory locations are adjacent. */
28177 adjacent_mem_locations (rtx mem1
, rtx mem2
)
28180 HOST_WIDE_INT off1
, size1
, off2
, size2
;
28182 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
28183 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
28184 return ((REGNO (reg1
) == REGNO (reg2
))
28185 && ((off1
+ size1
== off2
)
28186 || (off2
+ size2
== off1
)));
28191 /* This function returns true if it can be determined that the two MEM
28192 locations overlap by at least 1 byte based on base reg/offset/size. */
28195 mem_locations_overlap (rtx mem1
, rtx mem2
)
28198 HOST_WIDE_INT off1
, size1
, off2
, size2
;
28200 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
28201 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
28202 return ((REGNO (reg1
) == REGNO (reg2
))
28203 && (((off1
<= off2
) && (off1
+ size1
> off2
))
28204 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
28209 /* A C statement (sans semicolon) to update the integer scheduling
28210 priority INSN_PRIORITY (INSN). Increase the priority to execute the
28211 INSN earlier, reduce the priority to execute INSN later. Do not
28212 define this macro if you do not need to adjust the scheduling
28213 priorities of insns. */
28216 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
28218 rtx load_mem
, str_mem
;
28219 /* On machines (like the 750) which have asymmetric integer units,
28220 where one integer unit can do multiply and divides and the other
28221 can't, reduce the priority of multiply/divide so it is scheduled
28222 before other integer operations. */
28225 if (! INSN_P (insn
))
28228 if (GET_CODE (PATTERN (insn
)) == USE
)
28231 switch (rs6000_cpu_attr
) {
28233 switch (get_attr_type (insn
))
28240 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
28241 priority
, priority
);
28242 if (priority
>= 0 && priority
< 0x01000000)
28249 if (insn_must_be_first_in_group (insn
)
28250 && reload_completed
28251 && current_sched_info
->sched_max_insns_priority
28252 && rs6000_sched_restricted_insns_priority
)
28255 /* Prioritize insns that can be dispatched only in the first
28257 if (rs6000_sched_restricted_insns_priority
== 1)
28258 /* Attach highest priority to insn. This means that in
28259 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
28260 precede 'priority' (critical path) considerations. */
28261 return current_sched_info
->sched_max_insns_priority
;
28262 else if (rs6000_sched_restricted_insns_priority
== 2)
28263 /* Increase priority of insn by a minimal amount. This means that in
28264 haifa-sched.c:ready_sort(), only 'priority' (critical path)
28265 considerations precede dispatch-slot restriction considerations. */
28266 return (priority
+ 1);
28269 if (rs6000_cpu
== PROCESSOR_POWER6
28270 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
28271 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
28272 /* Attach highest priority to insn if the scheduler has just issued two
28273 stores and this instruction is a load, or two loads and this instruction
28274 is a store. Power6 wants loads and stores scheduled alternately
28276 return current_sched_info
->sched_max_insns_priority
;
28281 /* Return true if the instruction is nonpipelined on the Cell. */
28283 is_nonpipeline_insn (rtx_insn
*insn
)
28285 enum attr_type type
;
28286 if (!insn
|| !NONDEBUG_INSN_P (insn
)
28287 || GET_CODE (PATTERN (insn
)) == USE
28288 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28291 type
= get_attr_type (insn
);
28292 if (type
== TYPE_MUL
28293 || type
== TYPE_DIV
28294 || type
== TYPE_SDIV
28295 || type
== TYPE_DDIV
28296 || type
== TYPE_SSQRT
28297 || type
== TYPE_DSQRT
28298 || type
== TYPE_MFCR
28299 || type
== TYPE_MFCRF
28300 || type
== TYPE_MFJMPR
)
28308 /* Return how many instructions the machine can issue per cycle. */
28311 rs6000_issue_rate (void)
28313 /* Unless scheduling for register pressure, use issue rate of 1 for
28314 first scheduling pass to decrease degradation. */
28315 if (!reload_completed
&& !flag_sched_pressure
)
28318 switch (rs6000_cpu_attr
) {
28320 case CPU_PPC601
: /* ? */
28330 case CPU_PPCE300C2
:
28331 case CPU_PPCE300C3
:
28332 case CPU_PPCE500MC
:
28333 case CPU_PPCE500MC64
:
28356 /* Return how many instructions to look ahead for better insn
28360 rs6000_use_sched_lookahead (void)
28362 switch (rs6000_cpu_attr
)
28369 return (reload_completed
? 8 : 0);
28376 /* We are choosing insn from the ready queue. Return zero if INSN can be
28379 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
28381 if (ready_index
== 0)
28384 if (rs6000_cpu_attr
!= CPU_CELL
)
28387 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
28389 if (!reload_completed
28390 || is_nonpipeline_insn (insn
)
28391 || is_microcoded_insn (insn
))
28397 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
28398 and return true. */
28401 find_mem_ref (rtx pat
, rtx
*mem_ref
)
28406 /* stack_tie does not produce any real memory traffic. */
28407 if (tie_operand (pat
, VOIDmode
))
28410 if (GET_CODE (pat
) == MEM
)
28416 /* Recursively process the pattern. */
28417 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
28419 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
28423 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
28426 else if (fmt
[i
] == 'E')
28427 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
28429 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
28437 /* Determine if PAT is a PATTERN of a load insn. */
28440 is_load_insn1 (rtx pat
, rtx
*load_mem
)
28442 if (!pat
|| pat
== NULL_RTX
)
28445 if (GET_CODE (pat
) == SET
)
28446 return find_mem_ref (SET_SRC (pat
), load_mem
);
28448 if (GET_CODE (pat
) == PARALLEL
)
28452 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
28453 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
28460 /* Determine if INSN loads from memory. */
28463 is_load_insn (rtx insn
, rtx
*load_mem
)
28465 if (!insn
|| !INSN_P (insn
))
28471 return is_load_insn1 (PATTERN (insn
), load_mem
);
28474 /* Determine if PAT is a PATTERN of a store insn. */
28477 is_store_insn1 (rtx pat
, rtx
*str_mem
)
28479 if (!pat
|| pat
== NULL_RTX
)
28482 if (GET_CODE (pat
) == SET
)
28483 return find_mem_ref (SET_DEST (pat
), str_mem
);
28485 if (GET_CODE (pat
) == PARALLEL
)
28489 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
28490 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
28497 /* Determine if INSN stores to memory. */
28500 is_store_insn (rtx insn
, rtx
*str_mem
)
28502 if (!insn
|| !INSN_P (insn
))
28505 return is_store_insn1 (PATTERN (insn
), str_mem
);
28508 /* Returns whether the dependence between INSN and NEXT is considered
28509 costly by the given target. */
28512 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
28516 rtx load_mem
, str_mem
;
28518 /* If the flag is not enabled - no dependence is considered costly;
28519 allow all dependent insns in the same group.
28520 This is the most aggressive option. */
28521 if (rs6000_sched_costly_dep
== no_dep_costly
)
28524 /* If the flag is set to 1 - a dependence is always considered costly;
28525 do not allow dependent instructions in the same group.
28526 This is the most conservative option. */
28527 if (rs6000_sched_costly_dep
== all_deps_costly
)
28530 insn
= DEP_PRO (dep
);
28531 next
= DEP_CON (dep
);
28533 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
28534 && is_load_insn (next
, &load_mem
)
28535 && is_store_insn (insn
, &str_mem
))
28536 /* Prevent load after store in the same group. */
28539 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
28540 && is_load_insn (next
, &load_mem
)
28541 && is_store_insn (insn
, &str_mem
)
28542 && DEP_TYPE (dep
) == REG_DEP_TRUE
28543 && mem_locations_overlap(str_mem
, load_mem
))
28544 /* Prevent load after store in the same group if it is a true
28548 /* The flag is set to X; dependences with latency >= X are considered costly,
28549 and will not be scheduled in the same group. */
28550 if (rs6000_sched_costly_dep
<= max_dep_latency
28551 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
28557 /* Return the next insn after INSN that is found before TAIL is reached,
28558 skipping any "non-active" insns - insns that will not actually occupy
28559 an issue slot. Return NULL_RTX if such an insn is not found. */
28562 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
28564 if (insn
== NULL_RTX
|| insn
== tail
)
28569 insn
= NEXT_INSN (insn
);
28570 if (insn
== NULL_RTX
|| insn
== tail
)
28574 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
28575 || (NONJUMP_INSN_P (insn
)
28576 && GET_CODE (PATTERN (insn
)) != USE
28577 && GET_CODE (PATTERN (insn
)) != CLOBBER
28578 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
28584 /* We are about to begin issuing insns for this clock cycle. */
28587 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
28588 rtx_insn
**ready ATTRIBUTE_UNUSED
,
28589 int *pn_ready ATTRIBUTE_UNUSED
,
28590 int clock_var ATTRIBUTE_UNUSED
)
28592 int n_ready
= *pn_ready
;
28595 fprintf (dump
, "// rs6000_sched_reorder :\n");
28597 /* Reorder the ready list, if the second to last ready insn
28598 is a nonepipeline insn. */
28599 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
28601 if (is_nonpipeline_insn (ready
[n_ready
- 1])
28602 && (recog_memoized (ready
[n_ready
- 2]) > 0))
28603 /* Simply swap first two insns. */
28604 std::swap (ready
[n_ready
- 1], ready
[n_ready
- 2]);
28607 if (rs6000_cpu
== PROCESSOR_POWER6
)
28608 load_store_pendulum
= 0;
28610 return rs6000_issue_rate ();
28613 /* Like rs6000_sched_reorder, but called after issuing each insn. */
28616 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
28617 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
28620 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
28622 /* For Power6, we need to handle some special cases to try and keep the
28623 store queue from overflowing and triggering expensive flushes.
28625 This code monitors how load and store instructions are being issued
28626 and skews the ready list one way or the other to increase the likelihood
28627 that a desired instruction is issued at the proper time.
28629 A couple of things are done. First, we maintain a "load_store_pendulum"
28630 to track the current state of load/store issue.
28632 - If the pendulum is at zero, then no loads or stores have been
28633 issued in the current cycle so we do nothing.
28635 - If the pendulum is 1, then a single load has been issued in this
28636 cycle and we attempt to locate another load in the ready list to
28639 - If the pendulum is -2, then two stores have already been
28640 issued in this cycle, so we increase the priority of the first load
28641 in the ready list to increase it's likelihood of being chosen first
28644 - If the pendulum is -1, then a single store has been issued in this
28645 cycle and we attempt to locate another store in the ready list to
28646 issue with it, preferring a store to an adjacent memory location to
28647 facilitate store pairing in the store queue.
28649 - If the pendulum is 2, then two loads have already been
28650 issued in this cycle, so we increase the priority of the first store
28651 in the ready list to increase it's likelihood of being chosen first
28654 - If the pendulum < -2 or > 2, then do nothing.
28656 Note: This code covers the most common scenarios. There exist non
28657 load/store instructions which make use of the LSU and which
28658 would need to be accounted for to strictly model the behavior
28659 of the machine. Those instructions are currently unaccounted
28660 for to help minimize compile time overhead of this code.
28662 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
28667 rtx load_mem
, str_mem
;
28669 if (is_store_insn (last_scheduled_insn
, &str_mem
))
28670 /* Issuing a store, swing the load_store_pendulum to the left */
28671 load_store_pendulum
--;
28672 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
28673 /* Issuing a load, swing the load_store_pendulum to the right */
28674 load_store_pendulum
++;
28676 return cached_can_issue_more
;
28678 /* If the pendulum is balanced, or there is only one instruction on
28679 the ready list, then all is well, so return. */
28680 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
28681 return cached_can_issue_more
;
28683 if (load_store_pendulum
== 1)
28685 /* A load has been issued in this cycle. Scan the ready list
28686 for another load to issue with it */
28691 if (is_load_insn (ready
[pos
], &load_mem
))
28693 /* Found a load. Move it to the head of the ready list,
28694 and adjust it's priority so that it is more likely to
28697 for (i
=pos
; i
<*pn_ready
-1; i
++)
28698 ready
[i
] = ready
[i
+ 1];
28699 ready
[*pn_ready
-1] = tmp
;
28701 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
28702 INSN_PRIORITY (tmp
)++;
28708 else if (load_store_pendulum
== -2)
28710 /* Two stores have been issued in this cycle. Increase the
28711 priority of the first load in the ready list to favor it for
28712 issuing in the next cycle. */
28717 if (is_load_insn (ready
[pos
], &load_mem
)
28719 && INSN_PRIORITY_KNOWN (ready
[pos
]))
28721 INSN_PRIORITY (ready
[pos
])++;
28723 /* Adjust the pendulum to account for the fact that a load
28724 was found and increased in priority. This is to prevent
28725 increasing the priority of multiple loads */
28726 load_store_pendulum
--;
28733 else if (load_store_pendulum
== -1)
28735 /* A store has been issued in this cycle. Scan the ready list for
28736 another store to issue with it, preferring a store to an adjacent
28738 int first_store_pos
= -1;
28744 if (is_store_insn (ready
[pos
], &str_mem
))
28747 /* Maintain the index of the first store found on the
28749 if (first_store_pos
== -1)
28750 first_store_pos
= pos
;
28752 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
28753 && adjacent_mem_locations (str_mem
, str_mem2
))
28755 /* Found an adjacent store. Move it to the head of the
28756 ready list, and adjust it's priority so that it is
28757 more likely to stay there */
28759 for (i
=pos
; i
<*pn_ready
-1; i
++)
28760 ready
[i
] = ready
[i
+ 1];
28761 ready
[*pn_ready
-1] = tmp
;
28763 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
28764 INSN_PRIORITY (tmp
)++;
28766 first_store_pos
= -1;
28774 if (first_store_pos
>= 0)
28776 /* An adjacent store wasn't found, but a non-adjacent store was,
28777 so move the non-adjacent store to the front of the ready
28778 list, and adjust its priority so that it is more likely to
28780 tmp
= ready
[first_store_pos
];
28781 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
28782 ready
[i
] = ready
[i
+ 1];
28783 ready
[*pn_ready
-1] = tmp
;
28784 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
28785 INSN_PRIORITY (tmp
)++;
28788 else if (load_store_pendulum
== 2)
28790 /* Two loads have been issued in this cycle. Increase the priority
28791 of the first store in the ready list to favor it for issuing in
28797 if (is_store_insn (ready
[pos
], &str_mem
)
28799 && INSN_PRIORITY_KNOWN (ready
[pos
]))
28801 INSN_PRIORITY (ready
[pos
])++;
28803 /* Adjust the pendulum to account for the fact that a store
28804 was found and increased in priority. This is to prevent
28805 increasing the priority of multiple stores */
28806 load_store_pendulum
++;
28815 return cached_can_issue_more
;
28818 /* Return whether the presence of INSN causes a dispatch group termination
28819 of group WHICH_GROUP.
28821 If WHICH_GROUP == current_group, this function will return true if INSN
28822 causes the termination of the current group (i.e, the dispatch group to
28823 which INSN belongs). This means that INSN will be the last insn in the
28824 group it belongs to.
28826 If WHICH_GROUP == previous_group, this function will return true if INSN
28827 causes the termination of the previous group (i.e, the dispatch group that
28828 precedes the group to which INSN belongs). This means that INSN will be
28829 the first insn in the group it belongs to). */
28832 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
28839 first
= insn_must_be_first_in_group (insn
);
28840 last
= insn_must_be_last_in_group (insn
);
28845 if (which_group
== current_group
)
28847 else if (which_group
== previous_group
)
28855 insn_must_be_first_in_group (rtx_insn
*insn
)
28857 enum attr_type type
;
28861 || DEBUG_INSN_P (insn
)
28862 || GET_CODE (PATTERN (insn
)) == USE
28863 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28866 switch (rs6000_cpu
)
28868 case PROCESSOR_POWER5
:
28869 if (is_cracked_insn (insn
))
28871 case PROCESSOR_POWER4
:
28872 if (is_microcoded_insn (insn
))
28875 if (!rs6000_sched_groups
)
28878 type
= get_attr_type (insn
);
28885 case TYPE_DELAYED_CR
:
28886 case TYPE_CR_LOGICAL
:
28899 case PROCESSOR_POWER6
:
28900 type
= get_attr_type (insn
);
28909 case TYPE_FPCOMPARE
:
28920 if (get_attr_dot (insn
) == DOT_NO
28921 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
28926 if (get_attr_size (insn
) == SIZE_32
)
28934 if (get_attr_update (insn
) == UPDATE_YES
)
28942 case PROCESSOR_POWER7
:
28943 type
= get_attr_type (insn
);
28947 case TYPE_CR_LOGICAL
:
28961 if (get_attr_dot (insn
) == DOT_YES
)
28966 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
28967 || get_attr_update (insn
) == UPDATE_YES
)
28974 if (get_attr_update (insn
) == UPDATE_YES
)
28982 case PROCESSOR_POWER8
:
28983 type
= get_attr_type (insn
);
28987 case TYPE_CR_LOGICAL
:
28988 case TYPE_DELAYED_CR
:
28996 case TYPE_VECSTORE
:
29003 if (get_attr_dot (insn
) == DOT_YES
)
29008 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
29009 || get_attr_update (insn
) == UPDATE_YES
)
29014 if (get_attr_update (insn
) == UPDATE_YES
29015 && get_attr_indexed (insn
) == INDEXED_YES
)
29031 insn_must_be_last_in_group (rtx_insn
*insn
)
29033 enum attr_type type
;
29037 || DEBUG_INSN_P (insn
)
29038 || GET_CODE (PATTERN (insn
)) == USE
29039 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
29042 switch (rs6000_cpu
) {
29043 case PROCESSOR_POWER4
:
29044 case PROCESSOR_POWER5
:
29045 if (is_microcoded_insn (insn
))
29048 if (is_branch_slot_insn (insn
))
29052 case PROCESSOR_POWER6
:
29053 type
= get_attr_type (insn
);
29061 case TYPE_FPCOMPARE
:
29072 if (get_attr_dot (insn
) == DOT_NO
29073 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
29078 if (get_attr_size (insn
) == SIZE_32
)
29086 case PROCESSOR_POWER7
:
29087 type
= get_attr_type (insn
);
29097 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
29098 && get_attr_update (insn
) == UPDATE_YES
)
29103 if (get_attr_update (insn
) == UPDATE_YES
29104 && get_attr_indexed (insn
) == INDEXED_YES
)
29112 case PROCESSOR_POWER8
:
29113 type
= get_attr_type (insn
);
29125 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
29126 && get_attr_update (insn
) == UPDATE_YES
)
29131 if (get_attr_update (insn
) == UPDATE_YES
29132 && get_attr_indexed (insn
) == INDEXED_YES
)
29147 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
29148 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
29151 is_costly_group (rtx
*group_insns
, rtx next_insn
)
29154 int issue_rate
= rs6000_issue_rate ();
29156 for (i
= 0; i
< issue_rate
; i
++)
29158 sd_iterator_def sd_it
;
29160 rtx insn
= group_insns
[i
];
29165 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
29167 rtx next
= DEP_CON (dep
);
29169 if (next
== next_insn
29170 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
29178 /* Utility of the function redefine_groups.
29179 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
29180 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
29181 to keep it "far" (in a separate group) from GROUP_INSNS, following
29182 one of the following schemes, depending on the value of the flag
29183 -minsert_sched_nops = X:
29184 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
29185 in order to force NEXT_INSN into a separate group.
29186 (2) X < sched_finish_regroup_exact: insert exactly X nops.
29187 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
29188 insertion (has a group just ended, how many vacant issue slots remain in the
29189 last group, and how many dispatch groups were encountered so far). */
29192 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
29193 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
29198 int issue_rate
= rs6000_issue_rate ();
29199 bool end
= *group_end
;
29202 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
29203 return can_issue_more
;
29205 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
29206 return can_issue_more
;
29208 force
= is_costly_group (group_insns
, next_insn
);
29210 return can_issue_more
;
29212 if (sched_verbose
> 6)
29213 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
29214 *group_count
,can_issue_more
);
29216 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
29219 can_issue_more
= 0;
29221 /* Since only a branch can be issued in the last issue_slot, it is
29222 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
29223 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
29224 in this case the last nop will start a new group and the branch
29225 will be forced to the new group. */
29226 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
29229 /* Do we have a special group ending nop? */
29230 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
29231 || rs6000_cpu_attr
== CPU_POWER8
)
29233 nop
= gen_group_ending_nop ();
29234 emit_insn_before (nop
, next_insn
);
29235 can_issue_more
= 0;
29238 while (can_issue_more
> 0)
29241 emit_insn_before (nop
, next_insn
);
29249 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
29251 int n_nops
= rs6000_sched_insert_nops
;
29253 /* Nops can't be issued from the branch slot, so the effective
29254 issue_rate for nops is 'issue_rate - 1'. */
29255 if (can_issue_more
== 0)
29256 can_issue_more
= issue_rate
;
29258 if (can_issue_more
== 0)
29260 can_issue_more
= issue_rate
- 1;
29263 for (i
= 0; i
< issue_rate
; i
++)
29265 group_insns
[i
] = 0;
29272 emit_insn_before (nop
, next_insn
);
29273 if (can_issue_more
== issue_rate
- 1) /* new group begins */
29276 if (can_issue_more
== 0)
29278 can_issue_more
= issue_rate
- 1;
29281 for (i
= 0; i
< issue_rate
; i
++)
29283 group_insns
[i
] = 0;
29289 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
29292 /* Is next_insn going to start a new group? */
29295 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
29296 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
29297 || (can_issue_more
< issue_rate
&&
29298 insn_terminates_group_p (next_insn
, previous_group
)));
29299 if (*group_end
&& end
)
29302 if (sched_verbose
> 6)
29303 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
29304 *group_count
, can_issue_more
);
29305 return can_issue_more
;
29308 return can_issue_more
;
29311 /* This function tries to synch the dispatch groups that the compiler "sees"
29312 with the dispatch groups that the processor dispatcher is expected to
29313 form in practice. It tries to achieve this synchronization by forcing the
29314 estimated processor grouping on the compiler (as opposed to the function
29315 'pad_goups' which tries to force the scheduler's grouping on the processor).
29317 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
29318 examines the (estimated) dispatch groups that will be formed by the processor
29319 dispatcher. It marks these group boundaries to reflect the estimated
29320 processor grouping, overriding the grouping that the scheduler had marked.
29321 Depending on the value of the flag '-minsert-sched-nops' this function can
29322 force certain insns into separate groups or force a certain distance between
29323 them by inserting nops, for example, if there exists a "costly dependence"
29326 The function estimates the group boundaries that the processor will form as
29327 follows: It keeps track of how many vacant issue slots are available after
29328 each insn. A subsequent insn will start a new group if one of the following
29330 - no more vacant issue slots remain in the current dispatch group.
29331 - only the last issue slot, which is the branch slot, is vacant, but the next
29332 insn is not a branch.
29333 - only the last 2 or less issue slots, including the branch slot, are vacant,
29334 which means that a cracked insn (which occupies two issue slots) can't be
29335 issued in this group.
29336 - less than 'issue_rate' slots are vacant, and the next insn always needs to
29337 start a new group. */
29340 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
29343 rtx_insn
*insn
, *next_insn
;
29345 int can_issue_more
;
29348 int group_count
= 0;
29352 issue_rate
= rs6000_issue_rate ();
29353 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
29354 for (i
= 0; i
< issue_rate
; i
++)
29356 group_insns
[i
] = 0;
29358 can_issue_more
= issue_rate
;
29360 insn
= get_next_active_insn (prev_head_insn
, tail
);
29363 while (insn
!= NULL_RTX
)
29365 slot
= (issue_rate
- can_issue_more
);
29366 group_insns
[slot
] = insn
;
29368 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
29369 if (insn_terminates_group_p (insn
, current_group
))
29370 can_issue_more
= 0;
29372 next_insn
= get_next_active_insn (insn
, tail
);
29373 if (next_insn
== NULL_RTX
)
29374 return group_count
+ 1;
29376 /* Is next_insn going to start a new group? */
29378 = (can_issue_more
== 0
29379 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
29380 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
29381 || (can_issue_more
< issue_rate
&&
29382 insn_terminates_group_p (next_insn
, previous_group
)));
29384 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
29385 next_insn
, &group_end
, can_issue_more
,
29391 can_issue_more
= 0;
29392 for (i
= 0; i
< issue_rate
; i
++)
29394 group_insns
[i
] = 0;
29398 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
29399 PUT_MODE (next_insn
, VOIDmode
);
29400 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
29401 PUT_MODE (next_insn
, TImode
);
29404 if (can_issue_more
== 0)
29405 can_issue_more
= issue_rate
;
29408 return group_count
;
29411 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
29412 dispatch group boundaries that the scheduler had marked. Pad with nops
29413 any dispatch groups which have vacant issue slots, in order to force the
29414 scheduler's grouping on the processor dispatcher. The function
29415 returns the number of dispatch groups found. */
29418 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
29421 rtx_insn
*insn
, *next_insn
;
29424 int can_issue_more
;
29426 int group_count
= 0;
29428 /* Initialize issue_rate. */
29429 issue_rate
= rs6000_issue_rate ();
29430 can_issue_more
= issue_rate
;
29432 insn
= get_next_active_insn (prev_head_insn
, tail
);
29433 next_insn
= get_next_active_insn (insn
, tail
);
29435 while (insn
!= NULL_RTX
)
29438 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
29440 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
29442 if (next_insn
== NULL_RTX
)
29447 /* If the scheduler had marked group termination at this location
29448 (between insn and next_insn), and neither insn nor next_insn will
29449 force group termination, pad the group with nops to force group
29452 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
29453 && !insn_terminates_group_p (insn
, current_group
)
29454 && !insn_terminates_group_p (next_insn
, previous_group
))
29456 if (!is_branch_slot_insn (next_insn
))
29459 while (can_issue_more
)
29462 emit_insn_before (nop
, next_insn
);
29467 can_issue_more
= issue_rate
;
29472 next_insn
= get_next_active_insn (insn
, tail
);
29475 return group_count
;
29478 /* We're beginning a new block. Initialize data structures as necessary. */
29481 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
29482 int sched_verbose ATTRIBUTE_UNUSED
,
29483 int max_ready ATTRIBUTE_UNUSED
)
29485 last_scheduled_insn
= NULL_RTX
;
29486 load_store_pendulum
= 0;
29489 /* The following function is called at the end of scheduling BB.
29490 After reload, it inserts nops at insn group bundling. */
29493 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
29498 fprintf (dump
, "=== Finishing schedule.\n");
29500 if (reload_completed
&& rs6000_sched_groups
)
29502 /* Do not run sched_finish hook when selective scheduling enabled. */
29503 if (sel_sched_p ())
29506 if (rs6000_sched_insert_nops
== sched_finish_none
)
29509 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
29510 n_groups
= pad_groups (dump
, sched_verbose
,
29511 current_sched_info
->prev_head
,
29512 current_sched_info
->next_tail
);
29514 n_groups
= redefine_groups (dump
, sched_verbose
,
29515 current_sched_info
->prev_head
,
29516 current_sched_info
->next_tail
);
29518 if (sched_verbose
>= 6)
29520 fprintf (dump
, "ngroups = %d\n", n_groups
);
29521 print_rtl (dump
, current_sched_info
->prev_head
);
29522 fprintf (dump
, "Done finish_sched\n");
29527 struct _rs6000_sched_context
29529 short cached_can_issue_more
;
29530 rtx last_scheduled_insn
;
29531 int load_store_pendulum
;
29534 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
29535 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
29537 /* Allocate store for new scheduling context. */
29539 rs6000_alloc_sched_context (void)
29541 return xmalloc (sizeof (rs6000_sched_context_def
));
29544 /* If CLEAN_P is true then initializes _SC with clean data,
29545 and from the global context otherwise. */
29547 rs6000_init_sched_context (void *_sc
, bool clean_p
)
29549 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
29553 sc
->cached_can_issue_more
= 0;
29554 sc
->last_scheduled_insn
= NULL_RTX
;
29555 sc
->load_store_pendulum
= 0;
29559 sc
->cached_can_issue_more
= cached_can_issue_more
;
29560 sc
->last_scheduled_insn
= last_scheduled_insn
;
29561 sc
->load_store_pendulum
= load_store_pendulum
;
29565 /* Sets the global scheduling context to the one pointed to by _SC. */
29567 rs6000_set_sched_context (void *_sc
)
29569 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
29571 gcc_assert (sc
!= NULL
);
29573 cached_can_issue_more
= sc
->cached_can_issue_more
;
29574 last_scheduled_insn
= sc
->last_scheduled_insn
;
29575 load_store_pendulum
= sc
->load_store_pendulum
;
29580 rs6000_free_sched_context (void *_sc
)
29582 gcc_assert (_sc
!= NULL
);
29588 /* Length in units of the trampoline for entering a nested function. */
29591 rs6000_trampoline_size (void)
29595 switch (DEFAULT_ABI
)
29598 gcc_unreachable ();
29601 ret
= (TARGET_32BIT
) ? 12 : 24;
29605 gcc_assert (!TARGET_32BIT
);
29611 ret
= (TARGET_32BIT
) ? 40 : 48;
29618 /* Emit RTL insns to initialize the variable parts of a trampoline.
29619 FNADDR is an RTX for the address of the function's pure code.
29620 CXT is an RTX for the static chain value for the function. */
29623 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
29625 int regsize
= (TARGET_32BIT
) ? 4 : 8;
29626 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
29627 rtx ctx_reg
= force_reg (Pmode
, cxt
);
29628 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
29630 switch (DEFAULT_ABI
)
29633 gcc_unreachable ();
29635 /* Under AIX, just build the 3 word function descriptor */
29638 rtx fnmem
, fn_reg
, toc_reg
;
29640 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
29641 error ("You cannot take the address of a nested function if you use "
29642 "the -mno-pointers-to-nested-functions option.");
29644 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
29645 fn_reg
= gen_reg_rtx (Pmode
);
29646 toc_reg
= gen_reg_rtx (Pmode
);
29648 /* Macro to shorten the code expansions below. */
29649 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
29651 m_tramp
= replace_equiv_address (m_tramp
, addr
);
29653 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
29654 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
29655 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
29656 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
29657 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
29663 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
29667 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
29668 LCT_NORMAL
, VOIDmode
, 4,
29670 GEN_INT (rs6000_trampoline_size ()), SImode
,
29678 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
29679 identifier as an argument, so the front end shouldn't look it up. */
29682 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
29684 return is_attribute_p ("altivec", attr_id
);
29687 /* Handle the "altivec" attribute. The attribute may have
29688 arguments as follows:
29690 __attribute__((altivec(vector__)))
29691 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
29692 __attribute__((altivec(bool__))) (always followed by 'unsigned')
29694 and may appear more than once (e.g., 'vector bool char') in a
29695 given declaration. */
29698 rs6000_handle_altivec_attribute (tree
*node
,
29699 tree name ATTRIBUTE_UNUSED
,
29701 int flags ATTRIBUTE_UNUSED
,
29702 bool *no_add_attrs
)
29704 tree type
= *node
, result
= NULL_TREE
;
29708 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
29709 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
29710 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
29713 while (POINTER_TYPE_P (type
)
29714 || TREE_CODE (type
) == FUNCTION_TYPE
29715 || TREE_CODE (type
) == METHOD_TYPE
29716 || TREE_CODE (type
) == ARRAY_TYPE
)
29717 type
= TREE_TYPE (type
);
29719 mode
= TYPE_MODE (type
);
29721 /* Check for invalid AltiVec type qualifiers. */
29722 if (type
== long_double_type_node
)
29723 error ("use of %<long double%> in AltiVec types is invalid");
29724 else if (type
== boolean_type_node
)
29725 error ("use of boolean types in AltiVec types is invalid");
29726 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
29727 error ("use of %<complex%> in AltiVec types is invalid");
29728 else if (DECIMAL_FLOAT_MODE_P (mode
))
29729 error ("use of decimal floating point types in AltiVec types is invalid");
29730 else if (!TARGET_VSX
)
29732 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
29735 error ("use of %<long%> in AltiVec types is invalid for "
29736 "64-bit code without -mvsx");
29737 else if (rs6000_warn_altivec_long
)
29738 warning (0, "use of %<long%> in AltiVec types is deprecated; "
29741 else if (type
== long_long_unsigned_type_node
29742 || type
== long_long_integer_type_node
)
29743 error ("use of %<long long%> in AltiVec types is invalid without "
29745 else if (type
== double_type_node
)
29746 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
29749 switch (altivec_type
)
29752 unsigned_p
= TYPE_UNSIGNED (type
);
29756 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
29759 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
29762 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
29765 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
29768 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
29770 case SFmode
: result
= V4SF_type_node
; break;
29771 case DFmode
: result
= V2DF_type_node
; break;
29772 /* If the user says 'vector int bool', we may be handed the 'bool'
29773 attribute _before_ the 'vector' attribute, and so select the
29774 proper type in the 'b' case below. */
29775 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
29776 case V2DImode
: case V2DFmode
:
29784 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
29785 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
29786 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
29787 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
29794 case V8HImode
: result
= pixel_V8HI_type_node
;
29800 /* Propagate qualifiers attached to the element type
29801 onto the vector type. */
29802 if (result
&& result
!= type
&& TYPE_QUALS (type
))
29803 result
= build_qualified_type (result
, TYPE_QUALS (type
));
29805 *no_add_attrs
= true; /* No need to hang on to the attribute. */
29808 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
29813 /* AltiVec defines four built-in scalar types that serve as vector
29814 elements; we must teach the compiler how to mangle them. */
29816 static const char *
29817 rs6000_mangle_type (const_tree type
)
29819 type
= TYPE_MAIN_VARIANT (type
);
29821 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
29822 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
29825 if (type
== bool_char_type_node
) return "U6__boolc";
29826 if (type
== bool_short_type_node
) return "U6__bools";
29827 if (type
== pixel_type_node
) return "u7__pixel";
29828 if (type
== bool_int_type_node
) return "U6__booli";
29829 if (type
== bool_long_type_node
) return "U6__booll";
29831 /* Mangle IBM extended float long double as `g' (__float128) on
29832 powerpc*-linux where long-double-64 previously was the default. */
29833 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
29835 && TARGET_LONG_DOUBLE_128
29836 && !TARGET_IEEEQUAD
)
29839 /* For all other types, use normal C++ mangling. */
29843 /* Handle a "longcall" or "shortcall" attribute; arguments as in
29844 struct attribute_spec.handler. */
29847 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
29848 tree args ATTRIBUTE_UNUSED
,
29849 int flags ATTRIBUTE_UNUSED
,
29850 bool *no_add_attrs
)
29852 if (TREE_CODE (*node
) != FUNCTION_TYPE
29853 && TREE_CODE (*node
) != FIELD_DECL
29854 && TREE_CODE (*node
) != TYPE_DECL
)
29856 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
29858 *no_add_attrs
= true;
29864 /* Set longcall attributes on all functions declared when
29865 rs6000_default_long_calls is true. */
29867 rs6000_set_default_type_attributes (tree type
)
29869 if (rs6000_default_long_calls
29870 && (TREE_CODE (type
) == FUNCTION_TYPE
29871 || TREE_CODE (type
) == METHOD_TYPE
))
29872 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
29874 TYPE_ATTRIBUTES (type
));
29877 darwin_set_default_type_attributes (type
);
29881 /* Return a reference suitable for calling a function with the
29882 longcall attribute. */
29885 rs6000_longcall_ref (rtx call_ref
)
29887 const char *call_name
;
29890 if (GET_CODE (call_ref
) != SYMBOL_REF
)
29893 /* System V adds '.' to the internal name, so skip them. */
29894 call_name
= XSTR (call_ref
, 0);
29895 if (*call_name
== '.')
29897 while (*call_name
== '.')
29900 node
= get_identifier (call_name
);
29901 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
29904 return force_reg (Pmode
, call_ref
);
29907 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
29908 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
29911 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
29912 struct attribute_spec.handler. */
29914 rs6000_handle_struct_attribute (tree
*node
, tree name
,
29915 tree args ATTRIBUTE_UNUSED
,
29916 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
29919 if (DECL_P (*node
))
29921 if (TREE_CODE (*node
) == TYPE_DECL
)
29922 type
= &TREE_TYPE (*node
);
29927 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
29928 || TREE_CODE (*type
) == UNION_TYPE
)))
29930 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
29931 *no_add_attrs
= true;
29934 else if ((is_attribute_p ("ms_struct", name
)
29935 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
29936 || ((is_attribute_p ("gcc_struct", name
)
29937 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
29939 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
29941 *no_add_attrs
= true;
29948 rs6000_ms_bitfield_layout_p (const_tree record_type
)
29950 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
29951 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
29952 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
29955 #ifdef USING_ELFOS_H
29957 /* A get_unnamed_section callback, used for switching to toc_section. */
29960 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
29962 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29963 && TARGET_MINIMAL_TOC
29964 && !TARGET_RELOCATABLE
)
29966 if (!toc_initialized
)
29968 toc_initialized
= 1;
29969 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
29970 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
29971 fprintf (asm_out_file
, "\t.tc ");
29972 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
29973 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
29974 fprintf (asm_out_file
, "\n");
29976 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29977 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
29978 fprintf (asm_out_file
, " = .+32768\n");
29981 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29983 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29984 && !TARGET_RELOCATABLE
)
29985 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
29988 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29989 if (!toc_initialized
)
29991 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
29992 fprintf (asm_out_file
, " = .+32768\n");
29993 toc_initialized
= 1;
29998 /* Implement TARGET_ASM_INIT_SECTIONS. */
30001 rs6000_elf_asm_init_sections (void)
30004 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
30007 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
30008 SDATA2_SECTION_ASM_OP
);
30011 /* Implement TARGET_SELECT_RTX_SECTION. */
30014 rs6000_elf_select_rtx_section (machine_mode mode
, rtx x
,
30015 unsigned HOST_WIDE_INT align
)
30017 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
30018 return toc_section
;
30020 return default_elf_select_rtx_section (mode
, x
, align
);
30023 /* For a SYMBOL_REF, set generic flags and then perform some
30024 target-specific processing.
30026 When the AIX ABI is requested on a non-AIX system, replace the
30027 function name with the real name (with a leading .) rather than the
30028 function descriptor name. This saves a lot of overriding code to
30029 read the prefixes. */
30031 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
30033 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
30035 default_encode_section_info (decl
, rtl
, first
);
30038 && TREE_CODE (decl
) == FUNCTION_DECL
30040 && DEFAULT_ABI
== ABI_AIX
)
30042 rtx sym_ref
= XEXP (rtl
, 0);
30043 size_t len
= strlen (XSTR (sym_ref
, 0));
30044 char *str
= XALLOCAVEC (char, len
+ 2);
30046 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
30047 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
30052 compare_section_name (const char *section
, const char *templ
)
30056 len
= strlen (templ
);
30057 return (strncmp (section
, templ
, len
) == 0
30058 && (section
[len
] == 0 || section
[len
] == '.'));
30062 rs6000_elf_in_small_data_p (const_tree decl
)
30064 if (rs6000_sdata
== SDATA_NONE
)
30067 /* We want to merge strings, so we never consider them small data. */
30068 if (TREE_CODE (decl
) == STRING_CST
)
30071 /* Functions are never in the small data area. */
30072 if (TREE_CODE (decl
) == FUNCTION_DECL
)
30075 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
30077 const char *section
= DECL_SECTION_NAME (decl
);
30078 if (compare_section_name (section
, ".sdata")
30079 || compare_section_name (section
, ".sdata2")
30080 || compare_section_name (section
, ".gnu.linkonce.s")
30081 || compare_section_name (section
, ".sbss")
30082 || compare_section_name (section
, ".sbss2")
30083 || compare_section_name (section
, ".gnu.linkonce.sb")
30084 || strcmp (section
, ".PPC.EMB.sdata0") == 0
30085 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
30090 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
30093 && size
<= g_switch_value
30094 /* If it's not public, and we're not going to reference it there,
30095 there's no need to put it in the small data section. */
30096 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
30103 #endif /* USING_ELFOS_H */
30105 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
30108 rs6000_use_blocks_for_constant_p (machine_mode mode
, const_rtx x
)
30110 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
30113 /* Do not place thread-local symbols refs in the object blocks. */
30116 rs6000_use_blocks_for_decl_p (const_tree decl
)
30118 return !DECL_THREAD_LOCAL_P (decl
);
30121 /* Return a REG that occurs in ADDR with coefficient 1.
30122 ADDR can be effectively incremented by incrementing REG.
30124 r0 is special and we must not select it as an address
30125 register by this routine since our caller will try to
30126 increment the returned register via an "la" instruction. */
30129 find_addr_reg (rtx addr
)
30131 while (GET_CODE (addr
) == PLUS
)
30133 if (GET_CODE (XEXP (addr
, 0)) == REG
30134 && REGNO (XEXP (addr
, 0)) != 0)
30135 addr
= XEXP (addr
, 0);
30136 else if (GET_CODE (XEXP (addr
, 1)) == REG
30137 && REGNO (XEXP (addr
, 1)) != 0)
30138 addr
= XEXP (addr
, 1);
30139 else if (CONSTANT_P (XEXP (addr
, 0)))
30140 addr
= XEXP (addr
, 1);
30141 else if (CONSTANT_P (XEXP (addr
, 1)))
30142 addr
= XEXP (addr
, 0);
30144 gcc_unreachable ();
30146 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
30151 rs6000_fatal_bad_address (rtx op
)
30153 fatal_insn ("bad address", op
);
30158 typedef struct branch_island_d
{
30159 tree function_name
;
30165 static vec
<branch_island
, va_gc
> *branch_islands
;
30167 /* Remember to generate a branch island for far calls to the given
30171 add_compiler_branch_island (tree label_name
, tree function_name
,
30174 branch_island bi
= {function_name
, label_name
, line_number
};
30175 vec_safe_push (branch_islands
, bi
);
30178 /* Generate far-jump branch islands for everything recorded in
30179 branch_islands. Invoked immediately after the last instruction of
30180 the epilogue has been emitted; the branch islands must be appended
30181 to, and contiguous with, the function body. Mach-O stubs are
30182 generated in machopic_output_stub(). */
30185 macho_branch_islands (void)
30189 while (!vec_safe_is_empty (branch_islands
))
30191 branch_island
*bi
= &branch_islands
->last ();
30192 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
30193 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
30194 char name_buf
[512];
30195 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
30196 if (name
[0] == '*' || name
[0] == '&')
30197 strcpy (name_buf
, name
+1);
30201 strcpy (name_buf
+1, name
);
30203 strcpy (tmp_buf
, "\n");
30204 strcat (tmp_buf
, label
);
30205 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
30206 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
30207 dbxout_stabd (N_SLINE
, bi
->line_number
);
30208 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
30211 if (TARGET_LINK_STACK
)
30214 get_ppc476_thunk_name (name
);
30215 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
30216 strcat (tmp_buf
, name
);
30217 strcat (tmp_buf
, "\n");
30218 strcat (tmp_buf
, label
);
30219 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
30223 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
30224 strcat (tmp_buf
, label
);
30225 strcat (tmp_buf
, "_pic\n");
30226 strcat (tmp_buf
, label
);
30227 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
30230 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
30231 strcat (tmp_buf
, name_buf
);
30232 strcat (tmp_buf
, " - ");
30233 strcat (tmp_buf
, label
);
30234 strcat (tmp_buf
, "_pic)\n");
30236 strcat (tmp_buf
, "\tmtlr r0\n");
30238 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
30239 strcat (tmp_buf
, name_buf
);
30240 strcat (tmp_buf
, " - ");
30241 strcat (tmp_buf
, label
);
30242 strcat (tmp_buf
, "_pic)\n");
30244 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
30248 strcat (tmp_buf
, ":\nlis r12,hi16(");
30249 strcat (tmp_buf
, name_buf
);
30250 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
30251 strcat (tmp_buf
, name_buf
);
30252 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
30254 output_asm_insn (tmp_buf
, 0);
30255 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
30256 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
30257 dbxout_stabd (N_SLINE
, bi
->line_number
);
30258 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
30259 branch_islands
->pop ();
30263 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
30264 already there or not. */
30267 no_previous_def (tree function_name
)
30272 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
30273 if (function_name
== bi
->function_name
)
30278 /* GET_PREV_LABEL gets the label name from the previous definition of
30282 get_prev_label (tree function_name
)
30287 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
30288 if (function_name
== bi
->function_name
)
30289 return bi
->label_name
;
30293 /* INSN is either a function call or a millicode call. It may have an
30294 unconditional jump in its delay slot.
30296 CALL_DEST is the routine we are calling. */
30299 output_call (rtx_insn
*insn
, rtx
*operands
, int dest_operand_number
,
30300 int cookie_operand_number
)
30302 static char buf
[256];
30303 if (darwin_emit_branch_islands
30304 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
30305 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
30308 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
30310 if (no_previous_def (funname
))
30312 rtx label_rtx
= gen_label_rtx ();
30313 char *label_buf
, temp_buf
[256];
30314 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
30315 CODE_LABEL_NUMBER (label_rtx
));
30316 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
30317 labelname
= get_identifier (label_buf
);
30318 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
30321 labelname
= get_prev_label (funname
);
30323 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
30324 instruction will reach 'foo', otherwise link as 'bl L42'".
30325 "L42" should be a 'branch island', that will do a far jump to
30326 'foo'. Branch islands are generated in
30327 macho_branch_islands(). */
30328 sprintf (buf
, "jbsr %%z%d,%.246s",
30329 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
30332 sprintf (buf
, "bl %%z%d", dest_operand_number
);
30336 /* Generate PIC and indirect symbol stubs. */
30339 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
30341 unsigned int length
;
30342 char *symbol_name
, *lazy_ptr_name
;
30343 char *local_label_0
;
30344 static int label
= 0;
30346 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
30347 symb
= (*targetm
.strip_name_encoding
) (symb
);
30350 length
= strlen (symb
);
30351 symbol_name
= XALLOCAVEC (char, length
+ 32);
30352 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
30354 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
30355 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
30358 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
30360 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
30364 fprintf (file
, "\t.align 5\n");
30366 fprintf (file
, "%s:\n", stub
);
30367 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
30370 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
30371 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
30373 fprintf (file
, "\tmflr r0\n");
30374 if (TARGET_LINK_STACK
)
30377 get_ppc476_thunk_name (name
);
30378 fprintf (file
, "\tbl %s\n", name
);
30379 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
30383 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
30384 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
30386 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
30387 lazy_ptr_name
, local_label_0
);
30388 fprintf (file
, "\tmtlr r0\n");
30389 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
30390 (TARGET_64BIT
? "ldu" : "lwzu"),
30391 lazy_ptr_name
, local_label_0
);
30392 fprintf (file
, "\tmtctr r12\n");
30393 fprintf (file
, "\tbctr\n");
30397 fprintf (file
, "\t.align 4\n");
30399 fprintf (file
, "%s:\n", stub
);
30400 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
30402 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
30403 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
30404 (TARGET_64BIT
? "ldu" : "lwzu"),
30406 fprintf (file
, "\tmtctr r12\n");
30407 fprintf (file
, "\tbctr\n");
30410 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
30411 fprintf (file
, "%s:\n", lazy_ptr_name
);
30412 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
30413 fprintf (file
, "%sdyld_stub_binding_helper\n",
30414 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
30417 /* Legitimize PIC addresses. If the address is already
30418 position-independent, we return ORIG. Newly generated
30419 position-independent addresses go into a reg. This is REG if non
30420 zero, otherwise we allocate register(s) as necessary. */
30422 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
30425 rs6000_machopic_legitimize_pic_address (rtx orig
, machine_mode mode
,
30430 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
30431 reg
= gen_reg_rtx (Pmode
);
30433 if (GET_CODE (orig
) == CONST
)
30437 if (GET_CODE (XEXP (orig
, 0)) == PLUS
30438 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
30441 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
30443 /* Use a different reg for the intermediate value, as
30444 it will be marked UNCHANGING. */
30445 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
30446 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
30449 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
30452 if (GET_CODE (offset
) == CONST_INT
)
30454 if (SMALL_INT (offset
))
30455 return plus_constant (Pmode
, base
, INTVAL (offset
));
30456 else if (! reload_in_progress
&& ! reload_completed
)
30457 offset
= force_reg (Pmode
, offset
);
30460 rtx mem
= force_const_mem (Pmode
, orig
);
30461 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
30464 return gen_rtx_PLUS (Pmode
, base
, offset
);
30467 /* Fall back on generic machopic code. */
30468 return machopic_legitimize_pic_address (orig
, mode
, reg
);
30471 /* Output a .machine directive for the Darwin assembler, and call
30472 the generic start_file routine. */
30475 rs6000_darwin_file_start (void)
30477 static const struct
30481 HOST_WIDE_INT if_set
;
30483 { "ppc64", "ppc64", MASK_64BIT
},
30484 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
30485 { "power4", "ppc970", 0 },
30486 { "G5", "ppc970", 0 },
30487 { "7450", "ppc7450", 0 },
30488 { "7400", "ppc7400", MASK_ALTIVEC
},
30489 { "G4", "ppc7400", 0 },
30490 { "750", "ppc750", 0 },
30491 { "740", "ppc750", 0 },
30492 { "G3", "ppc750", 0 },
30493 { "604e", "ppc604e", 0 },
30494 { "604", "ppc604", 0 },
30495 { "603e", "ppc603", 0 },
30496 { "603", "ppc603", 0 },
30497 { "601", "ppc601", 0 },
30498 { NULL
, "ppc", 0 } };
30499 const char *cpu_id
= "";
30502 rs6000_file_start ();
30503 darwin_file_start ();
30505 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
30507 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
30508 cpu_id
= rs6000_default_cpu
;
30510 if (global_options_set
.x_rs6000_cpu_index
)
30511 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
30513 /* Look through the mapping array. Pick the first name that either
30514 matches the argument, has a bit set in IF_SET that is also set
30515 in the target flags, or has a NULL name. */
30518 while (mapping
[i
].arg
!= NULL
30519 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
30520 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
30523 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
30526 #endif /* TARGET_MACHO */
30530 rs6000_elf_reloc_rw_mask (void)
30534 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
30540 /* Record an element in the table of global constructors. SYMBOL is
30541 a SYMBOL_REF of the function to be called; PRIORITY is a number
30542 between 0 and MAX_INIT_PRIORITY.
30544 This differs from default_named_section_asm_out_constructor in
30545 that we have special handling for -mrelocatable. */
30547 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
30549 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
30551 const char *section
= ".ctors";
30554 if (priority
!= DEFAULT_INIT_PRIORITY
)
30556 sprintf (buf
, ".ctors.%.5u",
30557 /* Invert the numbering so the linker puts us in the proper
30558 order; constructors are run from right to left, and the
30559 linker sorts in increasing order. */
30560 MAX_INIT_PRIORITY
- priority
);
30564 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
30565 assemble_align (POINTER_SIZE
);
30567 if (TARGET_RELOCATABLE
)
30569 fputs ("\t.long (", asm_out_file
);
30570 output_addr_const (asm_out_file
, symbol
);
30571 fputs (")@fixup\n", asm_out_file
);
30574 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
30577 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
30579 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
30581 const char *section
= ".dtors";
30584 if (priority
!= DEFAULT_INIT_PRIORITY
)
30586 sprintf (buf
, ".dtors.%.5u",
30587 /* Invert the numbering so the linker puts us in the proper
30588 order; constructors are run from right to left, and the
30589 linker sorts in increasing order. */
30590 MAX_INIT_PRIORITY
- priority
);
30594 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
30595 assemble_align (POINTER_SIZE
);
30597 if (TARGET_RELOCATABLE
)
30599 fputs ("\t.long (", asm_out_file
);
30600 output_addr_const (asm_out_file
, symbol
);
30601 fputs (")@fixup\n", asm_out_file
);
30604 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
30608 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
30610 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
30612 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
30613 ASM_OUTPUT_LABEL (file
, name
);
30614 fputs (DOUBLE_INT_ASM_OP
, file
);
30615 rs6000_output_function_entry (file
, name
);
30616 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
30619 fputs ("\t.size\t", file
);
30620 assemble_name (file
, name
);
30621 fputs (",24\n\t.type\t.", file
);
30622 assemble_name (file
, name
);
30623 fputs (",@function\n", file
);
30624 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
30626 fputs ("\t.globl\t.", file
);
30627 assemble_name (file
, name
);
30632 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
30633 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
30634 rs6000_output_function_entry (file
, name
);
30635 fputs (":\n", file
);
30639 if (TARGET_RELOCATABLE
30640 && !TARGET_SECURE_PLT
30641 && (get_pool_size () != 0 || crtl
->profile
)
30646 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
30648 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
30649 fprintf (file
, "\t.long ");
30650 assemble_name (file
, buf
);
30652 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
30653 assemble_name (file
, buf
);
30657 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
30658 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
30660 if (DEFAULT_ABI
== ABI_AIX
)
30662 const char *desc_name
, *orig_name
;
30664 orig_name
= (*targetm
.strip_name_encoding
) (name
);
30665 desc_name
= orig_name
;
30666 while (*desc_name
== '.')
30669 if (TREE_PUBLIC (decl
))
30670 fprintf (file
, "\t.globl %s\n", desc_name
);
30672 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
30673 fprintf (file
, "%s:\n", desc_name
);
30674 fprintf (file
, "\t.long %s\n", orig_name
);
30675 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
30676 fputs ("\t.long 0\n", file
);
30677 fprintf (file
, "\t.previous\n");
30679 ASM_OUTPUT_LABEL (file
, name
);
30682 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
30684 rs6000_elf_file_end (void)
30686 #ifdef HAVE_AS_GNU_ATTRIBUTE
30687 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
30689 if (rs6000_passes_float
)
30690 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
30691 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
30692 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
30694 if (rs6000_passes_vector
)
30695 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
30696 (TARGET_ALTIVEC_ABI
? 2
30697 : TARGET_SPE_ABI
? 3
30699 if (rs6000_returns_struct
)
30700 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
30701 aix_struct_return
? 2 : 1);
30704 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
30705 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
30706 file_end_indicate_exec_stack ();
30709 if (flag_split_stack
)
30710 file_end_indicate_split_stack ();
30716 #ifndef HAVE_XCOFF_DWARF_EXTRAS
30717 #define HAVE_XCOFF_DWARF_EXTRAS 0
30720 static enum unwind_info_type
30721 rs6000_xcoff_debug_unwind_info (void)
30723 if (HAVE_XCOFF_DWARF_EXTRAS
)
30730 rs6000_xcoff_asm_output_anchor (rtx symbol
)
30734 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
30735 SYMBOL_REF_BLOCK_OFFSET (symbol
));
30736 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
30737 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
30738 fprintf (asm_out_file
, ",");
30739 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
30740 fprintf (asm_out_file
, "\n");
30744 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
30746 fputs (GLOBAL_ASM_OP
, stream
);
30747 RS6000_OUTPUT_BASENAME (stream
, name
);
30748 putc ('\n', stream
);
30751 /* A get_unnamed_decl callback, used for read-only sections. PTR
30752 points to the section string variable. */
30755 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
30757 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
30758 *(const char *const *) directive
,
30759 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
30762 /* Likewise for read-write sections. */
30765 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
30767 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
30768 *(const char *const *) directive
,
30769 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
30773 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
30775 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
30776 *(const char *const *) directive
,
30777 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
30780 /* A get_unnamed_section callback, used for switching to toc_section. */
30783 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
30785 if (TARGET_MINIMAL_TOC
)
30787 /* toc_section is always selected at least once from
30788 rs6000_xcoff_file_start, so this is guaranteed to
30789 always be defined once and only once in each file. */
30790 if (!toc_initialized
)
30792 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
30793 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
30794 toc_initialized
= 1;
30796 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
30797 (TARGET_32BIT
? "" : ",3"));
30800 fputs ("\t.toc\n", asm_out_file
);
30803 /* Implement TARGET_ASM_INIT_SECTIONS. */
30806 rs6000_xcoff_asm_init_sections (void)
30808 read_only_data_section
30809 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
30810 &xcoff_read_only_section_name
);
30812 private_data_section
30813 = get_unnamed_section (SECTION_WRITE
,
30814 rs6000_xcoff_output_readwrite_section_asm_op
,
30815 &xcoff_private_data_section_name
);
30818 = get_unnamed_section (SECTION_TLS
,
30819 rs6000_xcoff_output_tls_section_asm_op
,
30820 &xcoff_tls_data_section_name
);
30822 tls_private_data_section
30823 = get_unnamed_section (SECTION_TLS
,
30824 rs6000_xcoff_output_tls_section_asm_op
,
30825 &xcoff_private_data_section_name
);
30827 read_only_private_data_section
30828 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
30829 &xcoff_private_data_section_name
);
30832 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
30834 readonly_data_section
= read_only_data_section
;
30838 rs6000_xcoff_reloc_rw_mask (void)
30844 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
30845 tree decl ATTRIBUTE_UNUSED
)
30848 static const char * const suffix
[5] = { "PR", "RO", "RW", "TL", "XO" };
30850 if (flags
& SECTION_EXCLUDE
)
30852 else if (flags
& SECTION_DEBUG
)
30854 fprintf (asm_out_file
, "\t.dwsect %s\n", name
);
30857 else if (flags
& SECTION_CODE
)
30859 else if (flags
& SECTION_TLS
)
30861 else if (flags
& SECTION_WRITE
)
30866 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
30867 (flags
& SECTION_CODE
) ? "." : "",
30868 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
30871 #define IN_NAMED_SECTION(DECL) \
30872 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
30873 && DECL_SECTION_NAME (DECL) != NULL)
30876 rs6000_xcoff_select_section (tree decl
, int reloc
,
30877 unsigned HOST_WIDE_INT align
)
30879 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
30881 if (align
> BIGGEST_ALIGNMENT
)
30883 resolve_unique_section (decl
, reloc
, true);
30884 if (IN_NAMED_SECTION (decl
))
30885 return get_named_section (decl
, NULL
, reloc
);
30888 if (decl_readonly_section (decl
, reloc
))
30890 if (TREE_PUBLIC (decl
))
30891 return read_only_data_section
;
30893 return read_only_private_data_section
;
30898 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
30900 if (TREE_PUBLIC (decl
))
30901 return tls_data_section
;
30902 else if (bss_initializer_p (decl
))
30904 /* Convert to COMMON to emit in BSS. */
30905 DECL_COMMON (decl
) = 1;
30906 return tls_comm_section
;
30909 return tls_private_data_section
;
30913 if (TREE_PUBLIC (decl
))
30914 return data_section
;
30916 return private_data_section
;
30921 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
30925 /* Use select_section for private data and uninitialized data with
30926 alignment <= BIGGEST_ALIGNMENT. */
30927 if (!TREE_PUBLIC (decl
)
30928 || DECL_COMMON (decl
)
30929 || (DECL_INITIAL (decl
) == NULL_TREE
30930 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
30931 || DECL_INITIAL (decl
) == error_mark_node
30932 || (flag_zero_initialized_in_bss
30933 && initializer_zerop (DECL_INITIAL (decl
))))
30936 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
30937 name
= (*targetm
.strip_name_encoding
) (name
);
30938 set_decl_section_name (decl
, name
);
30941 /* Select section for constant in constant pool.
30943 On RS/6000, all constants are in the private read-only data area.
30944 However, if this is being placed in the TOC it must be output as a
30948 rs6000_xcoff_select_rtx_section (machine_mode mode
, rtx x
,
30949 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
30951 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
30952 return toc_section
;
30954 return read_only_private_data_section
;
30957 /* Remove any trailing [DS] or the like from the symbol name. */
30959 static const char *
30960 rs6000_xcoff_strip_name_encoding (const char *name
)
30965 len
= strlen (name
);
30966 if (name
[len
- 1] == ']')
30967 return ggc_alloc_string (name
, len
- 4);
30972 /* Section attributes. AIX is always PIC. */
30974 static unsigned int
30975 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
30977 unsigned int align
;
30978 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
30980 /* Align to at least UNIT size. */
30981 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
30982 align
= MIN_UNITS_PER_WORD
;
30984 /* Increase alignment of large objects if not already stricter. */
30985 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
30986 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
30987 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
30989 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
30992 /* Output at beginning of assembler file.
30994 Initialize the section names for the RS/6000 at this point.
30996 Specify filename, including full path, to assembler.
30998 We want to go into the TOC section so at least one .toc will be emitted.
30999 Also, in order to output proper .bs/.es pairs, we need at least one static
31000 [RW] section emitted.
31002 Finally, declare mcount when profiling to make the assembler happy. */
31005 rs6000_xcoff_file_start (void)
31007 rs6000_gen_section_name (&xcoff_bss_section_name
,
31008 main_input_filename
, ".bss_");
31009 rs6000_gen_section_name (&xcoff_private_data_section_name
,
31010 main_input_filename
, ".rw_");
31011 rs6000_gen_section_name (&xcoff_read_only_section_name
,
31012 main_input_filename
, ".ro_");
31013 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
31014 main_input_filename
, ".tls_");
31015 rs6000_gen_section_name (&xcoff_tbss_section_name
,
31016 main_input_filename
, ".tbss_[UL]");
31018 fputs ("\t.file\t", asm_out_file
);
31019 output_quoted_string (asm_out_file
, main_input_filename
);
31020 fputc ('\n', asm_out_file
);
31021 if (write_symbols
!= NO_DEBUG
)
31022 switch_to_section (private_data_section
);
31023 switch_to_section (text_section
);
31025 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
31026 rs6000_file_start ();
31029 /* Output at end of assembler file.
31030 On the RS/6000, referencing data should automatically pull in text. */
31033 rs6000_xcoff_file_end (void)
31035 switch_to_section (text_section
);
31036 fputs ("_section_.text:\n", asm_out_file
);
31037 switch_to_section (data_section
);
31038 fputs (TARGET_32BIT
31039 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
31043 struct declare_alias_data
31046 bool function_descriptor
;
31049 /* Declare alias N. A helper function for for_node_and_aliases. */
31052 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
31054 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
31055 /* Main symbol is output specially, because varasm machinery does part of
31056 the job for us - we do not need to declare .globl/lglobs and such. */
31057 if (!n
->alias
|| n
->weakref
)
31060 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
31063 /* Prevent assemble_alias from trying to use .set pseudo operation
31064 that does not behave as expected by the middle-end. */
31065 TREE_ASM_WRITTEN (n
->decl
) = true;
31067 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
31068 char *buffer
= (char *) alloca (strlen (name
) + 2);
31070 int dollar_inside
= 0;
31072 strcpy (buffer
, name
);
31073 p
= strchr (buffer
, '$');
31077 p
= strchr (p
+ 1, '$');
31079 if (TREE_PUBLIC (n
->decl
))
31081 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
31083 if (dollar_inside
) {
31084 if (data
->function_descriptor
)
31085 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
31087 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
31089 if (data
->function_descriptor
)
31090 fputs ("\t.globl .", data
->file
);
31092 fputs ("\t.globl ", data
->file
);
31093 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
31094 putc ('\n', data
->file
);
31096 #ifdef ASM_WEAKEN_DECL
31097 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
31098 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
31105 if (data
->function_descriptor
)
31106 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
31108 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
31110 if (data
->function_descriptor
)
31111 fputs ("\t.lglobl .", data
->file
);
31113 fputs ("\t.lglobl ", data
->file
);
31114 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
31115 putc ('\n', data
->file
);
31117 if (data
->function_descriptor
)
31118 fputs (".", data
->file
);
31119 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
31120 fputs (":\n", data
->file
);
31124 /* This macro produces the initial definition of a function name.
31125 On the RS/6000, we need to place an extra '.' in the function name and
31126 output the function descriptor.
31127 Dollar signs are converted to underscores.
31129 The csect for the function will have already been created when
31130 text_section was selected. We do have to go back to that csect, however.
31132 The third and fourth parameters to the .function pseudo-op (16 and 044)
31133 are placeholders which no longer have any use.
31135 Because AIX assembler's .set command has unexpected semantics, we output
31136 all aliases as alternative labels in front of the definition. */
31139 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
31141 char *buffer
= (char *) alloca (strlen (name
) + 1);
31143 int dollar_inside
= 0;
31144 struct declare_alias_data data
= {file
, false};
31146 strcpy (buffer
, name
);
31147 p
= strchr (buffer
, '$');
31151 p
= strchr (p
+ 1, '$');
31153 if (TREE_PUBLIC (decl
))
31155 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
31157 if (dollar_inside
) {
31158 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
31159 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
31161 fputs ("\t.globl .", file
);
31162 RS6000_OUTPUT_BASENAME (file
, buffer
);
31168 if (dollar_inside
) {
31169 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
31170 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
31172 fputs ("\t.lglobl .", file
);
31173 RS6000_OUTPUT_BASENAME (file
, buffer
);
31176 fputs ("\t.csect ", file
);
31177 RS6000_OUTPUT_BASENAME (file
, buffer
);
31178 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
31179 RS6000_OUTPUT_BASENAME (file
, buffer
);
31180 fputs (":\n", file
);
31181 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
31182 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
31183 RS6000_OUTPUT_BASENAME (file
, buffer
);
31184 fputs (", TOC[tc0], 0\n", file
);
31186 switch_to_section (function_section (decl
));
31188 RS6000_OUTPUT_BASENAME (file
, buffer
);
31189 fputs (":\n", file
);
31190 data
.function_descriptor
= true;
31191 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
31192 if (!DECL_IGNORED_P (decl
))
31194 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
31195 xcoffout_declare_function (file
, decl
, buffer
);
31196 else if (write_symbols
== DWARF2_DEBUG
)
31198 name
= (*targetm
.strip_name_encoding
) (name
);
31199 fprintf (file
, "\t.function .%s,.%s,2,0\n", name
, name
);
31205 /* This macro produces the initial definition of a object (variable) name.
31206 Because AIX assembler's .set command has unexpected semantics, we output
31207 all aliases as alternative labels in front of the definition. */
31210 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
31212 struct declare_alias_data data
= {file
, false};
31213 RS6000_OUTPUT_BASENAME (file
, name
);
31214 fputs (":\n", file
);
31215 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
31218 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
31221 rs6000_asm_output_dwarf_pcrel (FILE *file
, int size
, const char *label
)
31223 fputs (integer_asm_op (size
, FALSE
), file
);
31224 assemble_name (file
, label
);
31225 fputs ("-$", file
);
31228 /* Output a symbol offset relative to the dbase for the current object.
31229 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
31232 __gcc_unwind_dbase is embedded in all executables/libraries through
31233 libgcc/config/rs6000/crtdbase.S. */
31236 rs6000_asm_output_dwarf_datarel (FILE *file
, int size
, const char *label
)
31238 fputs (integer_asm_op (size
, FALSE
), file
);
31239 assemble_name (file
, label
);
31240 fputs("-__gcc_unwind_dbase", file
);
31245 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
31250 default_encode_section_info (decl
, rtl
, first
);
31252 /* Careful not to prod global register variables. */
31255 symbol
= XEXP (rtl
, 0);
31256 if (GET_CODE (symbol
) != SYMBOL_REF
)
31259 flags
= SYMBOL_REF_FLAGS (symbol
);
31261 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
31262 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
31264 SYMBOL_REF_FLAGS (symbol
) = flags
;
31266 #endif /* HAVE_AS_TLS */
31267 #endif /* TARGET_XCOFF */
31269 /* Compute a (partial) cost for rtx X. Return true if the complete
31270 cost has been computed, and false if subexpressions should be
31271 scanned. In either case, *TOTAL contains the cost result. */
31274 rs6000_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
31275 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
31277 int code
= GET_CODE (x
);
31281 /* On the RS/6000, if it is valid in the insn, it is free. */
31283 if (((outer_code
== SET
31284 || outer_code
== PLUS
31285 || outer_code
== MINUS
)
31286 && (satisfies_constraint_I (x
)
31287 || satisfies_constraint_L (x
)))
31288 || (outer_code
== AND
31289 && (satisfies_constraint_K (x
)
31291 ? satisfies_constraint_L (x
)
31292 : satisfies_constraint_J (x
))))
31293 || ((outer_code
== IOR
|| outer_code
== XOR
)
31294 && (satisfies_constraint_K (x
)
31296 ? satisfies_constraint_L (x
)
31297 : satisfies_constraint_J (x
))))
31298 || outer_code
== ASHIFT
31299 || outer_code
== ASHIFTRT
31300 || outer_code
== LSHIFTRT
31301 || outer_code
== ROTATE
31302 || outer_code
== ROTATERT
31303 || outer_code
== ZERO_EXTRACT
31304 || (outer_code
== MULT
31305 && satisfies_constraint_I (x
))
31306 || ((outer_code
== DIV
|| outer_code
== UDIV
31307 || outer_code
== MOD
|| outer_code
== UMOD
)
31308 && exact_log2 (INTVAL (x
)) >= 0)
31309 || (outer_code
== COMPARE
31310 && (satisfies_constraint_I (x
)
31311 || satisfies_constraint_K (x
)))
31312 || ((outer_code
== EQ
|| outer_code
== NE
)
31313 && (satisfies_constraint_I (x
)
31314 || satisfies_constraint_K (x
)
31316 ? satisfies_constraint_L (x
)
31317 : satisfies_constraint_J (x
))))
31318 || (outer_code
== GTU
31319 && satisfies_constraint_I (x
))
31320 || (outer_code
== LTU
31321 && satisfies_constraint_P (x
)))
31326 else if ((outer_code
== PLUS
31327 && reg_or_add_cint_operand (x
, VOIDmode
))
31328 || (outer_code
== MINUS
31329 && reg_or_sub_cint_operand (x
, VOIDmode
))
31330 || ((outer_code
== SET
31331 || outer_code
== IOR
31332 || outer_code
== XOR
)
31334 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
31336 *total
= COSTS_N_INSNS (1);
31342 case CONST_WIDE_INT
:
31347 /* When optimizing for size, MEM should be slightly more expensive
31348 than generating address, e.g., (plus (reg) (const)).
31349 L1 cache latency is about two instructions. */
31350 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
31359 if (FLOAT_MODE_P (mode
))
31360 *total
= rs6000_cost
->fp
;
31362 *total
= COSTS_N_INSNS (1);
31366 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
31367 && satisfies_constraint_I (XEXP (x
, 1)))
31369 if (INTVAL (XEXP (x
, 1)) >= -256
31370 && INTVAL (XEXP (x
, 1)) <= 255)
31371 *total
= rs6000_cost
->mulsi_const9
;
31373 *total
= rs6000_cost
->mulsi_const
;
31375 else if (mode
== SFmode
)
31376 *total
= rs6000_cost
->fp
;
31377 else if (FLOAT_MODE_P (mode
))
31378 *total
= rs6000_cost
->dmul
;
31379 else if (mode
== DImode
)
31380 *total
= rs6000_cost
->muldi
;
31382 *total
= rs6000_cost
->mulsi
;
31386 if (mode
== SFmode
)
31387 *total
= rs6000_cost
->fp
;
31389 *total
= rs6000_cost
->dmul
;
31394 if (FLOAT_MODE_P (mode
))
31396 *total
= mode
== DFmode
? rs6000_cost
->ddiv
31397 : rs6000_cost
->sdiv
;
31404 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
31405 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
31407 if (code
== DIV
|| code
== MOD
)
31409 *total
= COSTS_N_INSNS (2);
31412 *total
= COSTS_N_INSNS (1);
31416 if (GET_MODE (XEXP (x
, 1)) == DImode
)
31417 *total
= rs6000_cost
->divdi
;
31419 *total
= rs6000_cost
->divsi
;
31421 /* Add in shift and subtract for MOD. */
31422 if (code
== MOD
|| code
== UMOD
)
31423 *total
+= COSTS_N_INSNS (2);
31428 *total
= COSTS_N_INSNS (4);
31432 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
31436 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
31440 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
31443 *total
= COSTS_N_INSNS (1);
31447 if (CONST_INT_P (XEXP (x
, 1)))
31449 rtx left
= XEXP (x
, 0);
31450 rtx_code left_code
= GET_CODE (left
);
31452 /* rotate-and-mask: 1 insn. */
31453 if ((left_code
== ROTATE
31454 || left_code
== ASHIFT
31455 || left_code
== LSHIFTRT
)
31456 && rs6000_is_valid_shift_mask (XEXP (x
, 1), left
, mode
))
31458 *total
= rtx_cost (XEXP (left
, 0), mode
, left_code
, 0, speed
);
31459 if (!CONST_INT_P (XEXP (left
, 1)))
31460 *total
+= rtx_cost (XEXP (left
, 1), SImode
, left_code
, 1, speed
);
31461 *total
+= COSTS_N_INSNS (1);
31465 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
31466 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
31467 if (rs6000_is_valid_and_mask (XEXP (x
, 1), mode
)
31468 || (val
& 0xffff) == val
31469 || (val
& 0xffff0000) == val
31470 || ((val
& 0xffff) == 0 && mode
== SImode
))
31472 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
31473 *total
+= COSTS_N_INSNS (1);
31478 if (rs6000_is_valid_2insn_and (XEXP (x
, 1), mode
))
31480 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
31481 *total
+= COSTS_N_INSNS (2);
31486 *total
= COSTS_N_INSNS (1);
31491 *total
= COSTS_N_INSNS (1);
31497 *total
= COSTS_N_INSNS (1);
31505 /* Handle mul_highpart. */
31506 if (outer_code
== TRUNCATE
31507 && GET_CODE (XEXP (x
, 0)) == MULT
)
31509 if (mode
== DImode
)
31510 *total
= rs6000_cost
->muldi
;
31512 *total
= rs6000_cost
->mulsi
;
31515 else if (outer_code
== AND
)
31518 *total
= COSTS_N_INSNS (1);
31523 if (GET_CODE (XEXP (x
, 0)) == MEM
)
31526 *total
= COSTS_N_INSNS (1);
31532 if (!FLOAT_MODE_P (mode
))
31534 *total
= COSTS_N_INSNS (1);
31540 case UNSIGNED_FLOAT
:
31543 case FLOAT_TRUNCATE
:
31544 *total
= rs6000_cost
->fp
;
31548 if (mode
== DFmode
)
31549 *total
= rs6000_cost
->sfdf_convert
;
31551 *total
= rs6000_cost
->fp
;
31555 switch (XINT (x
, 1))
31558 *total
= rs6000_cost
->fp
;
31570 *total
= COSTS_N_INSNS (1);
31573 else if (FLOAT_MODE_P (mode
)
31574 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31576 *total
= rs6000_cost
->fp
;
31585 /* Carry bit requires mode == Pmode.
31586 NEG or PLUS already counted so only add one. */
31588 && (outer_code
== NEG
|| outer_code
== PLUS
))
31590 *total
= COSTS_N_INSNS (1);
31593 if (outer_code
== SET
)
31595 if (XEXP (x
, 1) == const0_rtx
)
31597 if (TARGET_ISEL
&& !TARGET_MFCRF
)
31598 *total
= COSTS_N_INSNS (8);
31600 *total
= COSTS_N_INSNS (2);
31605 *total
= COSTS_N_INSNS (3);
31614 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
31616 if (TARGET_ISEL
&& !TARGET_MFCRF
)
31617 *total
= COSTS_N_INSNS (8);
31619 *total
= COSTS_N_INSNS (2);
31623 if (outer_code
== COMPARE
)
31637 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
31640 rs6000_debug_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
31641 int opno
, int *total
, bool speed
)
31643 bool ret
= rs6000_rtx_costs (x
, mode
, outer_code
, opno
, total
, speed
);
31646 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
31647 "opno = %d, total = %d, speed = %s, x:\n",
31648 ret
? "complete" : "scan inner",
31649 GET_MODE_NAME (mode
),
31650 GET_RTX_NAME (outer_code
),
31653 speed
? "true" : "false");
31660 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
31663 rs6000_debug_address_cost (rtx x
, machine_mode mode
,
31664 addr_space_t as
, bool speed
)
31666 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
31668 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
31669 ret
, speed
? "true" : "false");
31676 /* A C expression returning the cost of moving data from a register of class
31677 CLASS1 to one of CLASS2. */
31680 rs6000_register_move_cost (machine_mode mode
,
31681 reg_class_t from
, reg_class_t to
)
31685 if (TARGET_DEBUG_COST
)
31688 /* Moves from/to GENERAL_REGS. */
31689 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
31690 || reg_classes_intersect_p (from
, GENERAL_REGS
))
31692 reg_class_t rclass
= from
;
31694 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
31697 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
31698 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
31699 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
31701 /* It's more expensive to move CR_REGS than CR0_REGS because of the
31703 else if (rclass
== CR_REGS
)
31706 /* For those processors that have slow LR/CTR moves, make them more
31707 expensive than memory in order to bias spills to memory .*/
31708 else if ((rs6000_cpu
== PROCESSOR_POWER6
31709 || rs6000_cpu
== PROCESSOR_POWER7
31710 || rs6000_cpu
== PROCESSOR_POWER8
)
31711 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
31712 ret
= 6 * hard_regno_nregs
[0][mode
];
31715 /* A move will cost one instruction per GPR moved. */
31716 ret
= 2 * hard_regno_nregs
[0][mode
];
31719 /* If we have VSX, we can easily move between FPR or Altivec registers. */
31720 else if (VECTOR_MEM_VSX_P (mode
)
31721 && reg_classes_intersect_p (to
, VSX_REGS
)
31722 && reg_classes_intersect_p (from
, VSX_REGS
))
31723 ret
= 2 * hard_regno_nregs
[32][mode
];
31725 /* Moving between two similar registers is just one instruction. */
31726 else if (reg_classes_intersect_p (to
, from
))
31727 ret
= (FLOAT128_2REG_P (mode
)) ? 4 : 2;
31729 /* Everything else has to go through GENERAL_REGS. */
31731 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
31732 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
31734 if (TARGET_DEBUG_COST
)
31736 if (dbg_cost_ctrl
== 1)
31738 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
31739 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
31740 reg_class_names
[to
]);
31747 /* A C expressions returning the cost of moving data of MODE from a register to
31751 rs6000_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
31752 bool in ATTRIBUTE_UNUSED
)
31756 if (TARGET_DEBUG_COST
)
31759 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
31760 ret
= 4 * hard_regno_nregs
[0][mode
];
31761 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
31762 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
31763 ret
= 4 * hard_regno_nregs
[32][mode
];
31764 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
31765 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
31767 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
31769 if (TARGET_DEBUG_COST
)
31771 if (dbg_cost_ctrl
== 1)
31773 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
31774 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
31781 /* Returns a code for a target-specific builtin that implements
31782 reciprocal of the function, or NULL_TREE if not available. */
31785 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
31786 bool sqrt ATTRIBUTE_UNUSED
)
31788 if (optimize_insn_for_size_p ())
31794 case VSX_BUILTIN_XVSQRTDP
:
31795 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
31798 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
31800 case VSX_BUILTIN_XVSQRTSP
:
31801 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
31804 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
31813 case BUILT_IN_SQRT
:
31814 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
31817 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
31819 case BUILT_IN_SQRTF
:
31820 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
31823 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
31830 /* Load up a constant. If the mode is a vector mode, splat the value across
31831 all of the vector elements. */
31834 rs6000_load_constant_and_splat (machine_mode mode
, REAL_VALUE_TYPE dconst
)
31838 if (mode
== SFmode
|| mode
== DFmode
)
31840 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
31841 reg
= force_reg (mode
, d
);
31843 else if (mode
== V4SFmode
)
31845 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
31846 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
31847 reg
= gen_reg_rtx (mode
);
31848 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
31850 else if (mode
== V2DFmode
)
31852 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
31853 rtvec v
= gen_rtvec (2, d
, d
);
31854 reg
= gen_reg_rtx (mode
);
31855 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
31858 gcc_unreachable ();
31863 /* Generate an FMA instruction. */
31866 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
31868 machine_mode mode
= GET_MODE (target
);
31871 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
31872 gcc_assert (dst
!= NULL
);
31875 emit_move_insn (target
, dst
);
31878 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
31881 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
31883 machine_mode mode
= GET_MODE (target
);
31886 /* Altivec does not support fms directly;
31887 generate in terms of fma in that case. */
31888 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
31889 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
31892 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
31893 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
31895 gcc_assert (dst
!= NULL
);
31898 emit_move_insn (target
, dst
);
31901 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
31904 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
31906 machine_mode mode
= GET_MODE (dst
);
31909 /* This is a tad more complicated, since the fnma_optab is for
31910 a different expression: fma(-m1, m2, a), which is the same
31911 thing except in the case of signed zeros.
31913 Fortunately we know that if FMA is supported that FNMSUB is
31914 also supported in the ISA. Just expand it directly. */
31916 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
31918 r
= gen_rtx_NEG (mode
, a
);
31919 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
31920 r
= gen_rtx_NEG (mode
, r
);
31921 emit_insn (gen_rtx_SET (dst
, r
));
31924 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
31925 add a reg_note saying that this was a division. Support both scalar and
31926 vector divide. Assumes no trapping math and finite arguments. */
31929 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
31931 machine_mode mode
= GET_MODE (dst
);
31932 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
31935 /* Low precision estimates guarantee 5 bits of accuracy. High
31936 precision estimates guarantee 14 bits of accuracy. SFmode
31937 requires 23 bits of accuracy. DFmode requires 52 bits of
31938 accuracy. Each pass at least doubles the accuracy, leading
31939 to the following. */
31940 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
31941 if (mode
== DFmode
|| mode
== V2DFmode
)
31944 enum insn_code code
= optab_handler (smul_optab
, mode
);
31945 insn_gen_fn gen_mul
= GEN_FCN (code
);
31947 gcc_assert (code
!= CODE_FOR_nothing
);
31949 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
31951 /* x0 = 1./d estimate */
31952 x0
= gen_reg_rtx (mode
);
31953 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
31956 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
31959 /* e0 = 1. - d * x0 */
31960 e0
= gen_reg_rtx (mode
);
31961 rs6000_emit_nmsub (e0
, d
, x0
, one
);
31963 /* x1 = x0 + e0 * x0 */
31964 x1
= gen_reg_rtx (mode
);
31965 rs6000_emit_madd (x1
, e0
, x0
, x0
);
31967 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
31968 ++i
, xprev
= xnext
, eprev
= enext
) {
31970 /* enext = eprev * eprev */
31971 enext
= gen_reg_rtx (mode
);
31972 emit_insn (gen_mul (enext
, eprev
, eprev
));
31974 /* xnext = xprev + enext * xprev */
31975 xnext
= gen_reg_rtx (mode
);
31976 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
31982 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
31984 /* u = n * xprev */
31985 u
= gen_reg_rtx (mode
);
31986 emit_insn (gen_mul (u
, n
, xprev
));
31988 /* v = n - (d * u) */
31989 v
= gen_reg_rtx (mode
);
31990 rs6000_emit_nmsub (v
, d
, u
, n
);
31992 /* dst = (v * xprev) + u */
31993 rs6000_emit_madd (dst
, v
, xprev
, u
);
31996 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
31999 /* Newton-Raphson approximation of single/double-precision floating point
32000 rsqrt. Assumes no trapping math and finite arguments. */
32003 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
32005 machine_mode mode
= GET_MODE (src
);
32006 rtx x0
= gen_reg_rtx (mode
);
32007 rtx y
= gen_reg_rtx (mode
);
32009 /* Low precision estimates guarantee 5 bits of accuracy. High
32010 precision estimates guarantee 14 bits of accuracy. SFmode
32011 requires 23 bits of accuracy. DFmode requires 52 bits of
32012 accuracy. Each pass at least doubles the accuracy, leading
32013 to the following. */
32014 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
32015 if (mode
== DFmode
|| mode
== V2DFmode
)
32018 REAL_VALUE_TYPE dconst3_2
;
32021 enum insn_code code
= optab_handler (smul_optab
, mode
);
32022 insn_gen_fn gen_mul
= GEN_FCN (code
);
32024 gcc_assert (code
!= CODE_FOR_nothing
);
32026 /* Load up the constant 1.5 either as a scalar, or as a vector. */
32027 real_from_integer (&dconst3_2
, VOIDmode
, 3, SIGNED
);
32028 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
32030 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
32032 /* x0 = rsqrt estimate */
32033 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
32036 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
32037 rs6000_emit_msub (y
, src
, halfthree
, src
);
32039 for (i
= 0; i
< passes
; i
++)
32041 rtx x1
= gen_reg_rtx (mode
);
32042 rtx u
= gen_reg_rtx (mode
);
32043 rtx v
= gen_reg_rtx (mode
);
32045 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
32046 emit_insn (gen_mul (u
, x0
, x0
));
32047 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
32048 emit_insn (gen_mul (x1
, x0
, v
));
32052 emit_move_insn (dst
, x0
);
32056 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
32057 (Power7) targets. DST is the target, and SRC is the argument operand. */
32060 rs6000_emit_popcount (rtx dst
, rtx src
)
32062 machine_mode mode
= GET_MODE (dst
);
32065 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
32066 if (TARGET_POPCNTD
)
32068 if (mode
== SImode
)
32069 emit_insn (gen_popcntdsi2 (dst
, src
));
32071 emit_insn (gen_popcntddi2 (dst
, src
));
32075 tmp1
= gen_reg_rtx (mode
);
32077 if (mode
== SImode
)
32079 emit_insn (gen_popcntbsi2 (tmp1
, src
));
32080 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
32082 tmp2
= force_reg (SImode
, tmp2
);
32083 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
32087 emit_insn (gen_popcntbdi2 (tmp1
, src
));
32088 tmp2
= expand_mult (DImode
, tmp1
,
32089 GEN_INT ((HOST_WIDE_INT
)
32090 0x01010101 << 32 | 0x01010101),
32092 tmp2
= force_reg (DImode
, tmp2
);
32093 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
32098 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
32099 target, and SRC is the argument operand. */
32102 rs6000_emit_parity (rtx dst
, rtx src
)
32104 machine_mode mode
= GET_MODE (dst
);
32107 tmp
= gen_reg_rtx (mode
);
32109 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
32112 if (mode
== SImode
)
32114 emit_insn (gen_popcntbsi2 (tmp
, src
));
32115 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
32119 emit_insn (gen_popcntbdi2 (tmp
, src
));
32120 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
32125 if (mode
== SImode
)
32127 /* Is mult+shift >= shift+xor+shift+xor? */
32128 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
32130 rtx tmp1
, tmp2
, tmp3
, tmp4
;
32132 tmp1
= gen_reg_rtx (SImode
);
32133 emit_insn (gen_popcntbsi2 (tmp1
, src
));
32135 tmp2
= gen_reg_rtx (SImode
);
32136 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
32137 tmp3
= gen_reg_rtx (SImode
);
32138 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
32140 tmp4
= gen_reg_rtx (SImode
);
32141 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
32142 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
32145 rs6000_emit_popcount (tmp
, src
);
32146 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
32150 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
32151 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
32153 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
32155 tmp1
= gen_reg_rtx (DImode
);
32156 emit_insn (gen_popcntbdi2 (tmp1
, src
));
32158 tmp2
= gen_reg_rtx (DImode
);
32159 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
32160 tmp3
= gen_reg_rtx (DImode
);
32161 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
32163 tmp4
= gen_reg_rtx (DImode
);
32164 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
32165 tmp5
= gen_reg_rtx (DImode
);
32166 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
32168 tmp6
= gen_reg_rtx (DImode
);
32169 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
32170 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
32173 rs6000_emit_popcount (tmp
, src
);
32174 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
32178 /* Expand an Altivec constant permutation for little endian mode.
32179 There are two issues: First, the two input operands must be
32180 swapped so that together they form a double-wide array in LE
32181 order. Second, the vperm instruction has surprising behavior
32182 in LE mode: it interprets the elements of the source vectors
32183 in BE mode ("left to right") and interprets the elements of
32184 the destination vector in LE mode ("right to left"). To
32185 correct for this, we must subtract each element of the permute
32186 control vector from 31.
32188 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
32189 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
32190 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
32191 serve as the permute control vector. Then, in BE mode,
32195 places the desired result in vr9. However, in LE mode the
32196 vector contents will be
32198 vr10 = 00000003 00000002 00000001 00000000
32199 vr11 = 00000007 00000006 00000005 00000004
32201 The result of the vperm using the same permute control vector is
32203 vr9 = 05000000 07000000 01000000 03000000
32205 That is, the leftmost 4 bytes of vr10 are interpreted as the
32206 source for the rightmost 4 bytes of vr9, and so on.
32208 If we change the permute control vector to
32210 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
32218 vr9 = 00000006 00000004 00000002 00000000. */
32221 altivec_expand_vec_perm_const_le (rtx operands
[4])
32225 rtx constv
, unspec
;
32226 rtx target
= operands
[0];
32227 rtx op0
= operands
[1];
32228 rtx op1
= operands
[2];
32229 rtx sel
= operands
[3];
32231 /* Unpack and adjust the constant selector. */
32232 for (i
= 0; i
< 16; ++i
)
32234 rtx e
= XVECEXP (sel
, 0, i
);
32235 unsigned int elt
= 31 - (INTVAL (e
) & 31);
32236 perm
[i
] = GEN_INT (elt
);
32239 /* Expand to a permute, swapping the inputs and using the
32240 adjusted selector. */
32242 op0
= force_reg (V16QImode
, op0
);
32244 op1
= force_reg (V16QImode
, op1
);
32246 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
32247 constv
= force_reg (V16QImode
, constv
);
32248 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
32250 if (!REG_P (target
))
32252 rtx tmp
= gen_reg_rtx (V16QImode
);
32253 emit_move_insn (tmp
, unspec
);
32257 emit_move_insn (target
, unspec
);
32260 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
32261 permute control vector. But here it's not a constant, so we must
32262 generate a vector NAND or NOR to do the adjustment. */
32265 altivec_expand_vec_perm_le (rtx operands
[4])
32267 rtx notx
, iorx
, unspec
;
32268 rtx target
= operands
[0];
32269 rtx op0
= operands
[1];
32270 rtx op1
= operands
[2];
32271 rtx sel
= operands
[3];
32273 rtx norreg
= gen_reg_rtx (V16QImode
);
32274 machine_mode mode
= GET_MODE (target
);
32276 /* Get everything in regs so the pattern matches. */
32278 op0
= force_reg (mode
, op0
);
32280 op1
= force_reg (mode
, op1
);
32282 sel
= force_reg (V16QImode
, sel
);
32283 if (!REG_P (target
))
32284 tmp
= gen_reg_rtx (mode
);
32286 /* Invert the selector with a VNAND if available, else a VNOR.
32287 The VNAND is preferred for future fusion opportunities. */
32288 notx
= gen_rtx_NOT (V16QImode
, sel
);
32289 iorx
= (TARGET_P8_VECTOR
32290 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
32291 : gen_rtx_AND (V16QImode
, notx
, notx
));
32292 emit_insn (gen_rtx_SET (norreg
, iorx
));
32294 /* Permute with operands reversed and adjusted selector. */
32295 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
32298 /* Copy into target, possibly by way of a register. */
32299 if (!REG_P (target
))
32301 emit_move_insn (tmp
, unspec
);
32305 emit_move_insn (target
, unspec
);
32308 /* Expand an Altivec constant permutation. Return true if we match
32309 an efficient implementation; false to fall back to VPERM. */
32312 altivec_expand_vec_perm_const (rtx operands
[4])
32314 struct altivec_perm_insn
{
32315 HOST_WIDE_INT mask
;
32316 enum insn_code impl
;
32317 unsigned char perm
[16];
32319 static const struct altivec_perm_insn patterns
[] = {
32320 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
32321 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
32322 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
32323 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
32324 { OPTION_MASK_ALTIVEC
,
32325 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
32326 : CODE_FOR_altivec_vmrglb_direct
),
32327 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
32328 { OPTION_MASK_ALTIVEC
,
32329 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
32330 : CODE_FOR_altivec_vmrglh_direct
),
32331 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
32332 { OPTION_MASK_ALTIVEC
,
32333 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
32334 : CODE_FOR_altivec_vmrglw_direct
),
32335 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
32336 { OPTION_MASK_ALTIVEC
,
32337 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
32338 : CODE_FOR_altivec_vmrghb_direct
),
32339 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
32340 { OPTION_MASK_ALTIVEC
,
32341 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
32342 : CODE_FOR_altivec_vmrghh_direct
),
32343 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
32344 { OPTION_MASK_ALTIVEC
,
32345 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
32346 : CODE_FOR_altivec_vmrghw_direct
),
32347 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
32348 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
32349 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
32350 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
32351 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
32354 unsigned int i
, j
, elt
, which
;
32355 unsigned char perm
[16];
32356 rtx target
, op0
, op1
, sel
, x
;
32359 target
= operands
[0];
32364 /* Unpack the constant selector. */
32365 for (i
= which
= 0; i
< 16; ++i
)
32367 rtx e
= XVECEXP (sel
, 0, i
);
32368 elt
= INTVAL (e
) & 31;
32369 which
|= (elt
< 16 ? 1 : 2);
32373 /* Simplify the constant selector based on operands. */
32377 gcc_unreachable ();
32381 if (!rtx_equal_p (op0
, op1
))
32386 for (i
= 0; i
< 16; ++i
)
32398 /* Look for splat patterns. */
32403 for (i
= 0; i
< 16; ++i
)
32404 if (perm
[i
] != elt
)
32408 if (!BYTES_BIG_ENDIAN
)
32410 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
32416 for (i
= 0; i
< 16; i
+= 2)
32417 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
32421 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
32422 x
= gen_reg_rtx (V8HImode
);
32423 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
32425 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
32432 for (i
= 0; i
< 16; i
+= 4)
32434 || perm
[i
+ 1] != elt
+ 1
32435 || perm
[i
+ 2] != elt
+ 2
32436 || perm
[i
+ 3] != elt
+ 3)
32440 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
32441 x
= gen_reg_rtx (V4SImode
);
32442 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
32444 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
32450 /* Look for merge and pack patterns. */
32451 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
32455 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
32458 elt
= patterns
[j
].perm
[0];
32459 if (perm
[0] == elt
)
32461 else if (perm
[0] == elt
+ 16)
32465 for (i
= 1; i
< 16; ++i
)
32467 elt
= patterns
[j
].perm
[i
];
32469 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
32470 else if (one_vec
&& elt
>= 16)
32472 if (perm
[i
] != elt
)
32477 enum insn_code icode
= patterns
[j
].impl
;
32478 machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
32479 machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
32481 /* For little-endian, don't use vpkuwum and vpkuhum if the
32482 underlying vector type is not V4SI and V8HI, respectively.
32483 For example, using vpkuwum with a V8HI picks up the even
32484 halfwords (BE numbering) when the even halfwords (LE
32485 numbering) are what we need. */
32486 if (!BYTES_BIG_ENDIAN
32487 && icode
== CODE_FOR_altivec_vpkuwum_direct
32488 && ((GET_CODE (op0
) == REG
32489 && GET_MODE (op0
) != V4SImode
)
32490 || (GET_CODE (op0
) == SUBREG
32491 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
32493 if (!BYTES_BIG_ENDIAN
32494 && icode
== CODE_FOR_altivec_vpkuhum_direct
32495 && ((GET_CODE (op0
) == REG
32496 && GET_MODE (op0
) != V8HImode
)
32497 || (GET_CODE (op0
) == SUBREG
32498 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
32501 /* For little-endian, the two input operands must be swapped
32502 (or swapped back) to ensure proper right-to-left numbering
32504 if (swapped
^ !BYTES_BIG_ENDIAN
)
32505 std::swap (op0
, op1
);
32506 if (imode
!= V16QImode
)
32508 op0
= gen_lowpart (imode
, op0
);
32509 op1
= gen_lowpart (imode
, op1
);
32511 if (omode
== V16QImode
)
32514 x
= gen_reg_rtx (omode
);
32515 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
32516 if (omode
!= V16QImode
)
32517 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
32522 if (!BYTES_BIG_ENDIAN
)
32524 altivec_expand_vec_perm_const_le (operands
);
32531 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
32532 Return true if we match an efficient implementation. */
32535 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
32536 unsigned char perm0
, unsigned char perm1
)
32540 /* If both selectors come from the same operand, fold to single op. */
32541 if ((perm0
& 2) == (perm1
& 2))
32548 /* If both operands are equal, fold to simpler permutation. */
32549 if (rtx_equal_p (op0
, op1
))
32552 perm1
= (perm1
& 1) + 2;
32554 /* If the first selector comes from the second operand, swap. */
32555 else if (perm0
& 2)
32561 std::swap (op0
, op1
);
32563 /* If the second selector does not come from the second operand, fail. */
32564 else if ((perm1
& 2) == 0)
32568 if (target
!= NULL
)
32570 machine_mode vmode
, dmode
;
32573 vmode
= GET_MODE (target
);
32574 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
32575 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
32576 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
32577 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
32578 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
32579 emit_insn (gen_rtx_SET (target
, x
));
32585 rs6000_expand_vec_perm_const (rtx operands
[4])
32587 rtx target
, op0
, op1
, sel
;
32588 unsigned char perm0
, perm1
;
32590 target
= operands
[0];
32595 /* Unpack the constant selector. */
32596 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
32597 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
32599 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
32602 /* Test whether a constant permutation is supported. */
32605 rs6000_vectorize_vec_perm_const_ok (machine_mode vmode
,
32606 const unsigned char *sel
)
32608 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
32609 if (TARGET_ALTIVEC
)
32612 /* Check for ps_merge* or evmerge* insns. */
32613 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
32614 || (TARGET_SPE
&& vmode
== V2SImode
))
32616 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
32617 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
32618 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
32624 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
32627 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
32628 machine_mode vmode
, unsigned nelt
, rtx perm
[])
32630 machine_mode imode
;
32634 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
32636 imode
= mode_for_size (GET_MODE_UNIT_BITSIZE (vmode
), MODE_INT
, 0);
32637 imode
= mode_for_vector (imode
, nelt
);
32640 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
32641 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
32643 emit_move_insn (target
, x
);
32646 /* Expand an extract even operation. */
32649 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
32651 machine_mode vmode
= GET_MODE (target
);
32652 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
32655 for (i
= 0; i
< nelt
; i
++)
32656 perm
[i
] = GEN_INT (i
* 2);
32658 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
32661 /* Expand a vector interleave operation. */
32664 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
32666 machine_mode vmode
= GET_MODE (target
);
32667 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
32670 high
= (highp
? 0 : nelt
/ 2);
32671 for (i
= 0; i
< nelt
/ 2; i
++)
32673 perm
[i
* 2] = GEN_INT (i
+ high
);
32674 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
32677 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
32680 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
32682 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
32684 HOST_WIDE_INT
hwi_scale (scale
);
32685 REAL_VALUE_TYPE r_pow
;
32686 rtvec v
= rtvec_alloc (2);
32688 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
32689 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
32690 elt
= CONST_DOUBLE_FROM_REAL_VALUE (r_pow
, DFmode
);
32691 RTVEC_ELT (v
, 0) = elt
;
32692 RTVEC_ELT (v
, 1) = elt
;
32693 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
32694 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
32697 /* Return an RTX representing where to find the function value of a
32698 function returning MODE. */
32700 rs6000_complex_function_value (machine_mode mode
)
32702 unsigned int regno
;
32704 machine_mode inner
= GET_MODE_INNER (mode
);
32705 unsigned int inner_bytes
= GET_MODE_UNIT_SIZE (mode
);
32707 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
32708 regno
= FP_ARG_RETURN
;
32711 regno
= GP_ARG_RETURN
;
32713 /* 32-bit is OK since it'll go in r3/r4. */
32714 if (TARGET_32BIT
&& inner_bytes
>= 4)
32715 return gen_rtx_REG (mode
, regno
);
32718 if (inner_bytes
>= 8)
32719 return gen_rtx_REG (mode
, regno
);
32721 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
32723 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
32724 GEN_INT (inner_bytes
));
32725 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
32728 /* Return an rtx describing a return value of MODE as a PARALLEL
32729 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
32730 stride REG_STRIDE. */
32733 rs6000_parallel_return (machine_mode mode
,
32734 int n_elts
, machine_mode elt_mode
,
32735 unsigned int regno
, unsigned int reg_stride
)
32737 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
32740 for (i
= 0; i
< n_elts
; i
++)
32742 rtx r
= gen_rtx_REG (elt_mode
, regno
);
32743 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
32744 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
32745 regno
+= reg_stride
;
32751 /* Target hook for TARGET_FUNCTION_VALUE.
32753 On the SPE, both FPs and vectors are returned in r3.
32755 On RS/6000 an integer value is in r3 and a floating-point value is in
32756 fp1, unless -msoft-float. */
32759 rs6000_function_value (const_tree valtype
,
32760 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
32761 bool outgoing ATTRIBUTE_UNUSED
)
32764 unsigned int regno
;
32765 machine_mode elt_mode
;
32768 /* Special handling for structs in darwin64. */
32770 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
32772 CUMULATIVE_ARGS valcum
;
32776 valcum
.fregno
= FP_ARG_MIN_REG
;
32777 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
32778 /* Do a trial code generation as if this were going to be passed as
32779 an argument; if any part goes in memory, we return NULL. */
32780 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
32783 /* Otherwise fall through to standard ABI rules. */
32786 mode
= TYPE_MODE (valtype
);
32788 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
32789 if (rs6000_discover_homogeneous_aggregate (mode
, valtype
, &elt_mode
, &n_elts
))
32791 int first_reg
, n_regs
;
32793 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode
))
32795 /* _Decimal128 must use even/odd register pairs. */
32796 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
32797 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
32801 first_reg
= ALTIVEC_ARG_RETURN
;
32805 return rs6000_parallel_return (mode
, n_elts
, elt_mode
, first_reg
, n_regs
);
32808 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
32809 if (TARGET_32BIT
&& TARGET_POWERPC64
)
32818 int count
= GET_MODE_SIZE (mode
) / 4;
32819 return rs6000_parallel_return (mode
, count
, SImode
, GP_ARG_RETURN
, 1);
32822 if ((INTEGRAL_TYPE_P (valtype
)
32823 && GET_MODE_BITSIZE (mode
) < (TARGET_32BIT
? 32 : 64))
32824 || POINTER_TYPE_P (valtype
))
32825 mode
= TARGET_32BIT
? SImode
: DImode
;
32827 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
32828 /* _Decimal128 must use an even/odd register pair. */
32829 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
32830 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
32831 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
32832 regno
= FP_ARG_RETURN
;
32833 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
32834 && targetm
.calls
.split_complex_arg
)
32835 return rs6000_complex_function_value (mode
);
32836 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
32837 return register is used in both cases, and we won't see V2DImode/V2DFmode
32838 for pure altivec, combine the two cases. */
32839 else if ((TREE_CODE (valtype
) == VECTOR_TYPE
|| FLOAT128_VECTOR_P (mode
))
32840 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
32841 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
32842 regno
= ALTIVEC_ARG_RETURN
;
32843 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
32844 && (mode
== DFmode
|| mode
== DCmode
32845 || FLOAT128_IBM_P (mode
) || mode
== TCmode
))
32846 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
32848 regno
= GP_ARG_RETURN
;
32850 return gen_rtx_REG (mode
, regno
);
32853 /* Define how to find the value returned by a library function
32854 assuming the value has mode MODE. */
32856 rs6000_libcall_value (machine_mode mode
)
32858 unsigned int regno
;
32860 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
32861 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
32862 return rs6000_parallel_return (mode
, 2, SImode
, GP_ARG_RETURN
, 1);
32864 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
32865 /* _Decimal128 must use an even/odd register pair. */
32866 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
32867 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
)
32868 && TARGET_HARD_FLOAT
&& TARGET_FPRS
32869 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
32870 regno
= FP_ARG_RETURN
;
32871 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
32872 return register is used in both cases, and we won't see V2DImode/V2DFmode
32873 for pure altivec, combine the two cases. */
32874 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
32875 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
32876 regno
= ALTIVEC_ARG_RETURN
;
32877 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
32878 return rs6000_complex_function_value (mode
);
32879 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
32880 && (mode
== DFmode
|| mode
== DCmode
32881 || FLOAT128_IBM_P (mode
) || mode
== TCmode
))
32882 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
32884 regno
= GP_ARG_RETURN
;
32886 return gen_rtx_REG (mode
, regno
);
32890 /* Return true if we use LRA instead of reload pass. */
32892 rs6000_lra_p (void)
32894 return rs6000_lra_flag
;
32897 /* Given FROM and TO register numbers, say whether this elimination is allowed.
32898 Frame pointer elimination is automatically handled.
32900 For the RS/6000, if frame pointer elimination is being done, we would like
32901 to convert ap into fp, not sp.
32903 We need r30 if -mminimal-toc was specified, and there are constant pool
32907 rs6000_can_eliminate (const int from
, const int to
)
32909 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
32910 ? ! frame_pointer_needed
32911 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
32912 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
32916 /* Define the offset between two registers, FROM to be eliminated and its
32917 replacement TO, at the start of a routine. */
32919 rs6000_initial_elimination_offset (int from
, int to
)
32921 rs6000_stack_t
*info
= rs6000_stack_info ();
32922 HOST_WIDE_INT offset
;
32924 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
32925 offset
= info
->push_p
? 0 : -info
->total_size
;
32926 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
32928 offset
= info
->push_p
? 0 : -info
->total_size
;
32929 if (FRAME_GROWS_DOWNWARD
)
32930 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
32932 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
32933 offset
= FRAME_GROWS_DOWNWARD
32934 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
32936 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
32937 offset
= info
->total_size
;
32938 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
32939 offset
= info
->push_p
? info
->total_size
: 0;
32940 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
32943 gcc_unreachable ();
32949 rs6000_dwarf_register_span (rtx reg
)
32953 unsigned regno
= REGNO (reg
);
32954 machine_mode mode
= GET_MODE (reg
);
32958 && (SPE_VECTOR_MODE (GET_MODE (reg
))
32959 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
32960 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
32965 regno
= REGNO (reg
);
32967 /* The duality of the SPE register size wreaks all kinds of havoc.
32968 This is a way of distinguishing r0 in 32-bits from r0 in
32970 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
32971 gcc_assert (words
<= 4);
32972 for (i
= 0; i
< words
; i
++, regno
++)
32974 if (BYTES_BIG_ENDIAN
)
32976 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
32977 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
32981 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
32982 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
32986 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
32989 /* Fill in sizes for SPE register high parts in table used by unwinder. */
32992 rs6000_init_dwarf_reg_sizes_extra (tree address
)
32997 machine_mode mode
= TYPE_MODE (char_type_node
);
32998 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
32999 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
33000 rtx value
= gen_int_mode (4, mode
);
33002 for (i
= FIRST_SPE_HIGH_REGNO
; i
< LAST_SPE_HIGH_REGNO
+1; i
++)
33004 int column
= DWARF_REG_TO_UNWIND_COLUMN
33005 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
33006 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
33008 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
33012 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
33015 machine_mode mode
= TYPE_MODE (char_type_node
);
33016 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
33017 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
33018 rtx value
= gen_int_mode (16, mode
);
33020 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
33021 The unwinder still needs to know the size of Altivec registers. */
33023 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
33025 int column
= DWARF_REG_TO_UNWIND_COLUMN
33026 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
33027 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
33029 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
33034 /* Map internal gcc register numbers to debug format register numbers.
33035 FORMAT specifies the type of debug register number to use:
33036 0 -- debug information, except for frame-related sections
33037 1 -- DWARF .debug_frame section
33038 2 -- DWARF .eh_frame section */
33041 rs6000_dbx_register_number (unsigned int regno
, unsigned int format
)
33043 /* We never use the GCC internal number for SPE high registers.
33044 Those are mapped to the 1200..1231 range for all debug formats. */
33045 if (SPE_HIGH_REGNO_P (regno
))
33046 return regno
- FIRST_SPE_HIGH_REGNO
+ 1200;
33048 /* Except for the above, we use the internal number for non-DWARF
33049 debug information, and also for .eh_frame. */
33050 if ((format
== 0 && write_symbols
!= DWARF2_DEBUG
) || format
== 2)
33053 /* On some platforms, we use the standard DWARF register
33054 numbering for .debug_info and .debug_frame. */
33055 #ifdef RS6000_USE_DWARF_NUMBERING
33058 if (regno
== LR_REGNO
)
33060 if (regno
== CTR_REGNO
)
33062 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
33063 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
33064 The actual code emitted saves the whole of CR, so we map CR2_REGNO
33065 to the DWARF reg for CR. */
33066 if (format
== 1 && regno
== CR2_REGNO
)
33068 if (CR_REGNO_P (regno
))
33069 return regno
- CR0_REGNO
+ 86;
33070 if (regno
== CA_REGNO
)
33071 return 101; /* XER */
33072 if (ALTIVEC_REGNO_P (regno
))
33073 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
33074 if (regno
== VRSAVE_REGNO
)
33076 if (regno
== VSCR_REGNO
)
33078 if (regno
== SPE_ACC_REGNO
)
33080 if (regno
== SPEFSCR_REGNO
)
33086 /* target hook eh_return_filter_mode */
33087 static machine_mode
33088 rs6000_eh_return_filter_mode (void)
33090 return TARGET_32BIT
? SImode
: word_mode
;
33093 /* Target hook for scalar_mode_supported_p. */
33095 rs6000_scalar_mode_supported_p (machine_mode mode
)
33097 /* -m32 does not support TImode. This is the default, from
33098 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
33099 same ABI as for -m32. But default_scalar_mode_supported_p allows
33100 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
33101 for -mpowerpc64. */
33102 if (TARGET_32BIT
&& mode
== TImode
)
33105 if (DECIMAL_FLOAT_MODE_P (mode
))
33106 return default_decimal_float_supported_p ();
33107 else if (mode
== KFmode
)
33108 return TARGET_FLOAT128
;
33110 return default_scalar_mode_supported_p (mode
);
33113 /* Target hook for vector_mode_supported_p. */
33115 rs6000_vector_mode_supported_p (machine_mode mode
)
33118 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
33121 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
33124 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
33125 128-bit, the compiler might try to widen IEEE 128-bit to IBM
33127 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
) && !FLOAT128_IEEE_P (mode
))
33134 /* Target hook for invalid_arg_for_unprototyped_fn. */
33135 static const char *
33136 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
33138 return (!rs6000_darwin64_abi
33140 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
33141 && (funcdecl
== NULL_TREE
33142 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
33143 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
33144 ? N_("AltiVec argument passed to unprototyped function")
33148 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
33149 setup by using __stack_chk_fail_local hidden function instead of
33150 calling __stack_chk_fail directly. Otherwise it is better to call
33151 __stack_chk_fail directly. */
33153 static tree ATTRIBUTE_UNUSED
33154 rs6000_stack_protect_fail (void)
33156 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
33157 ? default_hidden_stack_protect_fail ()
33158 : default_external_stack_protect_fail ();
33162 rs6000_final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
33163 int num_operands ATTRIBUTE_UNUSED
)
33165 if (rs6000_warn_cell_microcode
)
33168 int insn_code_number
= recog_memoized (insn
);
33169 location_t location
= INSN_LOCATION (insn
);
33171 /* Punt on insns we cannot recognize. */
33172 if (insn_code_number
< 0)
33175 temp
= get_insn_template (insn_code_number
, insn
);
33177 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
33178 warning_at (location
, OPT_mwarn_cell_microcode
,
33179 "emitting microcode insn %s\t[%s] #%d",
33180 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
33181 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
33182 warning_at (location
, OPT_mwarn_cell_microcode
,
33183 "emitting conditional microcode insn %s\t[%s] #%d",
33184 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
33188 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
33191 static unsigned HOST_WIDE_INT
33192 rs6000_asan_shadow_offset (void)
33194 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
33198 /* Mask options that we want to support inside of attribute((target)) and
33199 #pragma GCC target operations. Note, we do not include things like
33200 64/32-bit, endianess, hard/soft floating point, etc. that would have
33201 different calling sequences. */
33203 struct rs6000_opt_mask
{
33204 const char *name
; /* option name */
33205 HOST_WIDE_INT mask
; /* mask to set */
33206 bool invert
; /* invert sense of mask */
33207 bool valid_target
; /* option is a target option */
33210 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
33212 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
33213 { "cmpb", OPTION_MASK_CMPB
, false, true },
33214 { "crypto", OPTION_MASK_CRYPTO
, false, true },
33215 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
33216 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
33217 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX
,
33219 { "fprnd", OPTION_MASK_FPRND
, false, true },
33220 { "hard-dfp", OPTION_MASK_DFP
, false, true },
33221 { "htm", OPTION_MASK_HTM
, false, true },
33222 { "isel", OPTION_MASK_ISEL
, false, true },
33223 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
33224 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
33225 { "mulhw", OPTION_MASK_MULHW
, false, true },
33226 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
33227 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
33228 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
33229 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
33230 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
33231 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
33232 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
33233 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
33234 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
33235 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
33236 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
33237 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT
, false, true },
33238 { "string", OPTION_MASK_STRING
, false, true },
33239 { "update", OPTION_MASK_NO_UPDATE
, true , true },
33240 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, true },
33241 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, true },
33242 { "vsx", OPTION_MASK_VSX
, false, true },
33243 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
33244 #ifdef OPTION_MASK_64BIT
33246 { "aix64", OPTION_MASK_64BIT
, false, false },
33247 { "aix32", OPTION_MASK_64BIT
, true, false },
33249 { "64", OPTION_MASK_64BIT
, false, false },
33250 { "32", OPTION_MASK_64BIT
, true, false },
33253 #ifdef OPTION_MASK_EABI
33254 { "eabi", OPTION_MASK_EABI
, false, false },
33256 #ifdef OPTION_MASK_LITTLE_ENDIAN
33257 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
33258 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
33260 #ifdef OPTION_MASK_RELOCATABLE
33261 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
33263 #ifdef OPTION_MASK_STRICT_ALIGN
33264 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
33266 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
33267 { "string", OPTION_MASK_STRING
, false, false },
33270 /* Builtin mask mapping for printing the flags. */
33271 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
33273 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
33274 { "vsx", RS6000_BTM_VSX
, false, false },
33275 { "spe", RS6000_BTM_SPE
, false, false },
33276 { "paired", RS6000_BTM_PAIRED
, false, false },
33277 { "fre", RS6000_BTM_FRE
, false, false },
33278 { "fres", RS6000_BTM_FRES
, false, false },
33279 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
33280 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
33281 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
33282 { "cell", RS6000_BTM_CELL
, false, false },
33283 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
33284 { "crypto", RS6000_BTM_CRYPTO
, false, false },
33285 { "htm", RS6000_BTM_HTM
, false, false },
33286 { "hard-dfp", RS6000_BTM_DFP
, false, false },
33287 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
33288 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
33291 /* Option variables that we want to support inside attribute((target)) and
33292 #pragma GCC target operations. */
33294 struct rs6000_opt_var
{
33295 const char *name
; /* option name */
33296 size_t global_offset
; /* offset of the option in global_options. */
33297 size_t target_offset
; /* offset of the option in target optiosn. */
33300 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
33303 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
33304 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
33305 { "avoid-indexed-addresses",
33306 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
33307 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
33309 offsetof (struct gcc_options
, x_rs6000_paired_float
),
33310 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
33312 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
33313 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
33314 { "optimize-swaps",
33315 offsetof (struct gcc_options
, x_rs6000_optimize_swaps
),
33316 offsetof (struct cl_target_option
, x_rs6000_optimize_swaps
), },
33317 { "allow-movmisalign",
33318 offsetof (struct gcc_options
, x_TARGET_ALLOW_MOVMISALIGN
),
33319 offsetof (struct cl_target_option
, x_TARGET_ALLOW_MOVMISALIGN
), },
33320 { "allow-df-permute",
33321 offsetof (struct gcc_options
, x_TARGET_ALLOW_DF_PERMUTE
),
33322 offsetof (struct cl_target_option
, x_TARGET_ALLOW_DF_PERMUTE
), },
33324 offsetof (struct gcc_options
, x_TARGET_SCHED_GROUPS
),
33325 offsetof (struct cl_target_option
, x_TARGET_SCHED_GROUPS
), },
33327 offsetof (struct gcc_options
, x_TARGET_ALWAYS_HINT
),
33328 offsetof (struct cl_target_option
, x_TARGET_ALWAYS_HINT
), },
33329 { "align-branch-targets",
33330 offsetof (struct gcc_options
, x_TARGET_ALIGN_BRANCH_TARGETS
),
33331 offsetof (struct cl_target_option
, x_TARGET_ALIGN_BRANCH_TARGETS
), },
33332 { "vectorize-builtins",
33333 offsetof (struct gcc_options
, x_TARGET_VECTORIZE_BUILTINS
),
33334 offsetof (struct cl_target_option
, x_TARGET_VECTORIZE_BUILTINS
), },
33336 offsetof (struct gcc_options
, x_tls_markers
),
33337 offsetof (struct cl_target_option
, x_tls_markers
), },
33339 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
33340 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
33342 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
33343 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
33344 { "gen-cell-microcode",
33345 offsetof (struct gcc_options
, x_rs6000_gen_cell_microcode
),
33346 offsetof (struct cl_target_option
, x_rs6000_gen_cell_microcode
), },
33347 { "warn-cell-microcode",
33348 offsetof (struct gcc_options
, x_rs6000_warn_cell_microcode
),
33349 offsetof (struct cl_target_option
, x_rs6000_warn_cell_microcode
), },
33352 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
33353 parsing. Return true if there were no errors. */
33356 rs6000_inner_target_options (tree args
, bool attr_p
)
33360 if (args
== NULL_TREE
)
33363 else if (TREE_CODE (args
) == STRING_CST
)
33365 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
33368 while ((q
= strtok (p
, ",")) != NULL
)
33370 bool error_p
= false;
33371 bool not_valid_p
= false;
33372 const char *cpu_opt
= NULL
;
33375 if (strncmp (q
, "cpu=", 4) == 0)
33377 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
33378 if (cpu_index
>= 0)
33379 rs6000_cpu_index
= cpu_index
;
33386 else if (strncmp (q
, "tune=", 5) == 0)
33388 int tune_index
= rs6000_cpu_name_lookup (q
+5);
33389 if (tune_index
>= 0)
33390 rs6000_tune_index
= tune_index
;
33400 bool invert
= false;
33404 if (strncmp (r
, "no-", 3) == 0)
33410 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
33411 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
33413 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
33415 if (!rs6000_opt_masks
[i
].valid_target
)
33416 not_valid_p
= true;
33420 rs6000_isa_flags_explicit
|= mask
;
33422 /* VSX needs altivec, so -mvsx automagically sets
33423 altivec and disables -mavoid-indexed-addresses. */
33426 if (mask
== OPTION_MASK_VSX
)
33428 mask
|= OPTION_MASK_ALTIVEC
;
33429 TARGET_AVOID_XFORM
= 0;
33433 if (rs6000_opt_masks
[i
].invert
)
33437 rs6000_isa_flags
&= ~mask
;
33439 rs6000_isa_flags
|= mask
;
33444 if (error_p
&& !not_valid_p
)
33446 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
33447 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
33449 size_t j
= rs6000_opt_vars
[i
].global_offset
;
33450 *((int *) ((char *)&global_options
+ j
)) = !invert
;
33452 not_valid_p
= false;
33460 const char *eprefix
, *esuffix
;
33465 eprefix
= "__attribute__((__target__(";
33470 eprefix
= "#pragma GCC target ";
33475 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
33477 else if (not_valid_p
)
33478 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
33480 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
33485 else if (TREE_CODE (args
) == TREE_LIST
)
33489 tree value
= TREE_VALUE (args
);
33492 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
33496 args
= TREE_CHAIN (args
);
33498 while (args
!= NULL_TREE
);
33502 gcc_unreachable ();
33507 /* Print out the target options as a list for -mdebug=target. */
33510 rs6000_debug_target_options (tree args
, const char *prefix
)
33512 if (args
== NULL_TREE
)
33513 fprintf (stderr
, "%s<NULL>", prefix
);
33515 else if (TREE_CODE (args
) == STRING_CST
)
33517 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
33520 while ((q
= strtok (p
, ",")) != NULL
)
33523 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
33528 else if (TREE_CODE (args
) == TREE_LIST
)
33532 tree value
= TREE_VALUE (args
);
33535 rs6000_debug_target_options (value
, prefix
);
33538 args
= TREE_CHAIN (args
);
33540 while (args
!= NULL_TREE
);
33544 gcc_unreachable ();
33550 /* Hook to validate attribute((target("..."))). */
33553 rs6000_valid_attribute_p (tree fndecl
,
33554 tree
ARG_UNUSED (name
),
33558 struct cl_target_option cur_target
;
33560 tree old_optimize
= build_optimization_node (&global_options
);
33561 tree new_target
, new_optimize
;
33562 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
33564 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
33566 if (TARGET_DEBUG_TARGET
)
33568 tree tname
= DECL_NAME (fndecl
);
33569 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
33571 fprintf (stderr
, "function: %.*s\n",
33572 (int) IDENTIFIER_LENGTH (tname
),
33573 IDENTIFIER_POINTER (tname
));
33575 fprintf (stderr
, "function: unknown\n");
33577 fprintf (stderr
, "args:");
33578 rs6000_debug_target_options (args
, " ");
33579 fprintf (stderr
, "\n");
33582 fprintf (stderr
, "flags: 0x%x\n", flags
);
33584 fprintf (stderr
, "--------------------\n");
33587 old_optimize
= build_optimization_node (&global_options
);
33588 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
33590 /* If the function changed the optimization levels as well as setting target
33591 options, start with the optimizations specified. */
33592 if (func_optimize
&& func_optimize
!= old_optimize
)
33593 cl_optimization_restore (&global_options
,
33594 TREE_OPTIMIZATION (func_optimize
));
33596 /* The target attributes may also change some optimization flags, so update
33597 the optimization options if necessary. */
33598 cl_target_option_save (&cur_target
, &global_options
);
33599 rs6000_cpu_index
= rs6000_tune_index
= -1;
33600 ret
= rs6000_inner_target_options (args
, true);
33602 /* Set up any additional state. */
33605 ret
= rs6000_option_override_internal (false);
33606 new_target
= build_target_option_node (&global_options
);
33611 new_optimize
= build_optimization_node (&global_options
);
33618 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
33620 if (old_optimize
!= new_optimize
)
33621 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
33624 cl_target_option_restore (&global_options
, &cur_target
);
33626 if (old_optimize
!= new_optimize
)
33627 cl_optimization_restore (&global_options
,
33628 TREE_OPTIMIZATION (old_optimize
));
33634 /* Hook to validate the current #pragma GCC target and set the state, and
33635 update the macros based on what was changed. If ARGS is NULL, then
33636 POP_TARGET is used to reset the options. */
33639 rs6000_pragma_target_parse (tree args
, tree pop_target
)
33641 tree prev_tree
= build_target_option_node (&global_options
);
33643 struct cl_target_option
*prev_opt
, *cur_opt
;
33644 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
33645 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
33647 if (TARGET_DEBUG_TARGET
)
33649 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
33650 fprintf (stderr
, "args:");
33651 rs6000_debug_target_options (args
, " ");
33652 fprintf (stderr
, "\n");
33656 fprintf (stderr
, "pop_target:\n");
33657 debug_tree (pop_target
);
33660 fprintf (stderr
, "pop_target: <NULL>\n");
33662 fprintf (stderr
, "--------------------\n");
33667 cur_tree
= ((pop_target
)
33669 : target_option_default_node
);
33670 cl_target_option_restore (&global_options
,
33671 TREE_TARGET_OPTION (cur_tree
));
33675 rs6000_cpu_index
= rs6000_tune_index
= -1;
33676 if (!rs6000_inner_target_options (args
, false)
33677 || !rs6000_option_override_internal (false)
33678 || (cur_tree
= build_target_option_node (&global_options
))
33681 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
33682 fprintf (stderr
, "invalid pragma\n");
33688 target_option_current_node
= cur_tree
;
33690 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
33691 change the macros that are defined. */
33692 if (rs6000_target_modify_macros_ptr
)
33694 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
33695 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
33696 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
33698 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
33699 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
33700 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
33702 diff_bumask
= (prev_bumask
^ cur_bumask
);
33703 diff_flags
= (prev_flags
^ cur_flags
);
33705 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
33707 /* Delete old macros. */
33708 rs6000_target_modify_macros_ptr (false,
33709 prev_flags
& diff_flags
,
33710 prev_bumask
& diff_bumask
);
33712 /* Define new macros. */
33713 rs6000_target_modify_macros_ptr (true,
33714 cur_flags
& diff_flags
,
33715 cur_bumask
& diff_bumask
);
33723 /* Remember the last target of rs6000_set_current_function. */
33724 static GTY(()) tree rs6000_previous_fndecl
;
33726 /* Establish appropriate back-end context for processing the function
33727 FNDECL. The argument might be NULL to indicate processing at top
33728 level, outside of any function scope. */
33730 rs6000_set_current_function (tree fndecl
)
33732 tree old_tree
= (rs6000_previous_fndecl
33733 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
33736 tree new_tree
= (fndecl
33737 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
33740 if (TARGET_DEBUG_TARGET
)
33742 bool print_final
= false;
33743 fprintf (stderr
, "\n==================== rs6000_set_current_function");
33746 fprintf (stderr
, ", fndecl %s (%p)",
33747 (DECL_NAME (fndecl
)
33748 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
33749 : "<unknown>"), (void *)fndecl
);
33751 if (rs6000_previous_fndecl
)
33752 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
33754 fprintf (stderr
, "\n");
33757 fprintf (stderr
, "\nnew fndecl target specific options:\n");
33758 debug_tree (new_tree
);
33759 print_final
= true;
33764 fprintf (stderr
, "\nold fndecl target specific options:\n");
33765 debug_tree (old_tree
);
33766 print_final
= true;
33770 fprintf (stderr
, "--------------------\n");
33773 /* Only change the context if the function changes. This hook is called
33774 several times in the course of compiling a function, and we don't want to
33775 slow things down too much or call target_reinit when it isn't safe. */
33776 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
33778 rs6000_previous_fndecl
= fndecl
;
33779 if (old_tree
== new_tree
)
33782 else if (new_tree
&& new_tree
!= target_option_default_node
)
33784 cl_target_option_restore (&global_options
,
33785 TREE_TARGET_OPTION (new_tree
));
33786 if (TREE_TARGET_GLOBALS (new_tree
))
33787 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
33789 TREE_TARGET_GLOBALS (new_tree
)
33790 = save_target_globals_default_opts ();
33793 else if (old_tree
&& old_tree
!= target_option_default_node
)
33795 new_tree
= target_option_current_node
;
33796 cl_target_option_restore (&global_options
,
33797 TREE_TARGET_OPTION (new_tree
));
33798 if (TREE_TARGET_GLOBALS (new_tree
))
33799 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
33800 else if (new_tree
== target_option_default_node
)
33801 restore_target_globals (&default_target_globals
);
33803 TREE_TARGET_GLOBALS (new_tree
)
33804 = save_target_globals_default_opts ();
33810 /* Save the current options */
33813 rs6000_function_specific_save (struct cl_target_option
*ptr
,
33814 struct gcc_options
*opts
)
33816 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
33817 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
33820 /* Restore the current options */
33823 rs6000_function_specific_restore (struct gcc_options
*opts
,
33824 struct cl_target_option
*ptr
)
33827 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
33828 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
33829 (void) rs6000_option_override_internal (false);
33832 /* Print the current options */
33835 rs6000_function_specific_print (FILE *file
, int indent
,
33836 struct cl_target_option
*ptr
)
33838 rs6000_print_isa_options (file
, indent
, "Isa options set",
33839 ptr
->x_rs6000_isa_flags
);
33841 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
33842 ptr
->x_rs6000_isa_flags_explicit
);
33845 /* Helper function to print the current isa or misc options on a line. */
33848 rs6000_print_options_internal (FILE *file
,
33850 const char *string
,
33851 HOST_WIDE_INT flags
,
33852 const char *prefix
,
33853 const struct rs6000_opt_mask
*opts
,
33854 size_t num_elements
)
33857 size_t start_column
= 0;
33859 size_t max_column
= 76;
33860 const char *comma
= "";
33863 start_column
+= fprintf (file
, "%*s", indent
, "");
33867 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
33871 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
33873 /* Print the various mask options. */
33874 cur_column
= start_column
;
33875 for (i
= 0; i
< num_elements
; i
++)
33877 if ((flags
& opts
[i
].mask
) != 0)
33879 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
33880 size_t len
= (strlen (comma
)
33883 + strlen (rs6000_opt_masks
[i
].name
));
33886 if (cur_column
> max_column
)
33888 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
33889 cur_column
= start_column
+ len
;
33893 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
33894 rs6000_opt_masks
[i
].name
);
33895 flags
&= ~ opts
[i
].mask
;
33900 fputs ("\n", file
);
33903 /* Helper function to print the current isa options on a line. */
33906 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
33907 HOST_WIDE_INT flags
)
33909 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
33910 &rs6000_opt_masks
[0],
33911 ARRAY_SIZE (rs6000_opt_masks
));
33915 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
33916 HOST_WIDE_INT flags
)
33918 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
33919 &rs6000_builtin_mask_names
[0],
33920 ARRAY_SIZE (rs6000_builtin_mask_names
));
33924 /* Hook to determine if one function can safely inline another. */
33927 rs6000_can_inline_p (tree caller
, tree callee
)
33930 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
33931 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
33933 /* If callee has no option attributes, then it is ok to inline. */
33937 /* If caller has no option attributes, but callee does then it is not ok to
33939 else if (!caller_tree
)
33944 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
33945 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
33947 /* Callee's options should a subset of the caller's, i.e. a vsx function
33948 can inline an altivec function but a non-vsx function can't inline a
33950 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
33951 == callee_opts
->x_rs6000_isa_flags
)
33955 if (TARGET_DEBUG_TARGET
)
33956 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
33957 (DECL_NAME (caller
)
33958 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
33960 (DECL_NAME (callee
)
33961 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
33963 (ret
? "can" : "cannot"));
33968 /* Allocate a stack temp and fixup the address so it meets the particular
33969 memory requirements (either offetable or REG+REG addressing). */
33972 rs6000_allocate_stack_temp (machine_mode mode
,
33973 bool offsettable_p
,
33976 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
33977 rtx addr
= XEXP (stack
, 0);
33978 int strict_p
= (reload_in_progress
|| reload_completed
);
33980 if (!legitimate_indirect_address_p (addr
, strict_p
))
33983 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
33984 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
33986 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
33987 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
33993 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
33994 to such a form to deal with memory reference instructions like STFIWX that
33995 only take reg+reg addressing. */
33998 rs6000_address_for_fpconvert (rtx x
)
34000 int strict_p
= (reload_in_progress
|| reload_completed
);
34003 gcc_assert (MEM_P (x
));
34004 addr
= XEXP (x
, 0);
34005 if (! legitimate_indirect_address_p (addr
, strict_p
)
34006 && ! legitimate_indexed_address_p (addr
, strict_p
))
34008 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
34010 rtx reg
= XEXP (addr
, 0);
34011 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
34012 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
34013 gcc_assert (REG_P (reg
));
34014 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
34017 else if (GET_CODE (addr
) == PRE_MODIFY
)
34019 rtx reg
= XEXP (addr
, 0);
34020 rtx expr
= XEXP (addr
, 1);
34021 gcc_assert (REG_P (reg
));
34022 gcc_assert (GET_CODE (expr
) == PLUS
);
34023 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
34027 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
34033 /* Given a memory reference, if it is not in the form for altivec memory
34034 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
34035 convert to the altivec format. */
34038 rs6000_address_for_altivec (rtx x
)
34040 gcc_assert (MEM_P (x
));
34041 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
34043 rtx addr
= XEXP (x
, 0);
34044 int strict_p
= (reload_in_progress
|| reload_completed
);
34046 if (!legitimate_indexed_address_p (addr
, strict_p
)
34047 && !legitimate_indirect_address_p (addr
, strict_p
))
34048 addr
= copy_to_mode_reg (Pmode
, addr
);
34050 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
34051 x
= change_address (x
, GET_MODE (x
), addr
);
34057 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
34059 On the RS/6000, all integer constants are acceptable, most won't be valid
34060 for particular insns, though. Only easy FP constants are acceptable. */
34063 rs6000_legitimate_constant_p (machine_mode mode
, rtx x
)
34065 if (TARGET_ELF
&& tls_referenced_p (x
))
34068 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
34069 || GET_MODE (x
) == VOIDmode
34070 || (TARGET_POWERPC64
&& mode
== DImode
)
34071 || easy_fp_constant (x
, mode
)
34072 || easy_vector_constant (x
, mode
));
34076 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
34079 chain_already_loaded (rtx_insn
*last
)
34081 for (; last
!= NULL
; last
= PREV_INSN (last
))
34083 if (NONJUMP_INSN_P (last
))
34085 rtx patt
= PATTERN (last
);
34087 if (GET_CODE (patt
) == SET
)
34089 rtx lhs
= XEXP (patt
, 0);
34091 if (REG_P (lhs
) && REGNO (lhs
) == STATIC_CHAIN_REGNUM
)
34099 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
34102 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
34104 const bool direct_call_p
34105 = GET_CODE (func_desc
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (func_desc
);
34106 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
34107 rtx toc_load
= NULL_RTX
;
34108 rtx toc_restore
= NULL_RTX
;
34110 rtx abi_reg
= NULL_RTX
;
34115 /* Handle longcall attributes. */
34116 if (INTVAL (cookie
) & CALL_LONG
)
34117 func_desc
= rs6000_longcall_ref (func_desc
);
34119 /* Handle indirect calls. */
34120 if (GET_CODE (func_desc
) != SYMBOL_REF
34121 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
34123 /* Save the TOC into its reserved slot before the call,
34124 and prepare to restore it after the call. */
34125 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
34126 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
34127 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
34128 gen_rtx_PLUS (Pmode
, stack_ptr
,
34129 stack_toc_offset
));
34130 rtx stack_toc_unspec
= gen_rtx_UNSPEC (Pmode
,
34131 gen_rtvec (1, stack_toc_offset
),
34133 toc_restore
= gen_rtx_SET (toc_reg
, stack_toc_unspec
);
34135 /* Can we optimize saving the TOC in the prologue or
34136 do we need to do it at every call? */
34137 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
34138 cfun
->machine
->save_toc_in_prologue
= true;
34141 MEM_VOLATILE_P (stack_toc_mem
) = 1;
34142 emit_move_insn (stack_toc_mem
, toc_reg
);
34145 if (DEFAULT_ABI
== ABI_ELFv2
)
34147 /* A function pointer in the ELFv2 ABI is just a plain address, but
34148 the ABI requires it to be loaded into r12 before the call. */
34149 func_addr
= gen_rtx_REG (Pmode
, 12);
34150 emit_move_insn (func_addr
, func_desc
);
34151 abi_reg
= func_addr
;
34155 /* A function pointer under AIX is a pointer to a data area whose
34156 first word contains the actual address of the function, whose
34157 second word contains a pointer to its TOC, and whose third word
34158 contains a value to place in the static chain register (r11).
34159 Note that if we load the static chain, our "trampoline" need
34160 not have any executable code. */
34162 /* Load up address of the actual function. */
34163 func_desc
= force_reg (Pmode
, func_desc
);
34164 func_addr
= gen_reg_rtx (Pmode
);
34165 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
34167 /* Prepare to load the TOC of the called function. Note that the
34168 TOC load must happen immediately before the actual call so
34169 that unwinding the TOC registers works correctly. See the
34170 comment in frob_update_context. */
34171 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
34172 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
34173 gen_rtx_PLUS (Pmode
, func_desc
,
34175 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
34177 /* If we have a static chain, load it up. But, if the call was
34178 originally direct, the 3rd word has not been written since no
34179 trampoline has been built, so we ought not to load it, lest we
34180 override a static chain value. */
34182 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
34183 && !chain_already_loaded (get_current_sequence ()->next
->last
))
34185 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
34186 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
34187 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
34188 gen_rtx_PLUS (Pmode
, func_desc
,
34190 emit_move_insn (sc_reg
, func_sc_mem
);
34197 /* Direct calls use the TOC: for local calls, the callee will
34198 assume the TOC register is set; for non-local calls, the
34199 PLT stub needs the TOC register. */
34201 func_addr
= func_desc
;
34204 /* Create the call. */
34205 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
34206 if (value
!= NULL_RTX
)
34207 call
[0] = gen_rtx_SET (value
, call
[0]);
34211 call
[n_call
++] = toc_load
;
34213 call
[n_call
++] = toc_restore
;
34215 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
34217 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
34218 insn
= emit_call_insn (insn
);
34220 /* Mention all registers defined by the ABI to hold information
34221 as uses in CALL_INSN_FUNCTION_USAGE. */
34223 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
34226 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
34229 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
34234 gcc_assert (INTVAL (cookie
) == 0);
34236 /* Create the call. */
34237 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
34238 if (value
!= NULL_RTX
)
34239 call
[0] = gen_rtx_SET (value
, call
[0]);
34241 call
[1] = simple_return_rtx
;
34243 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
34244 insn
= emit_call_insn (insn
);
34246 /* Note use of the TOC register. */
34247 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
34248 /* We need to also mark a use of the link register since the function we
34249 sibling-call to will use it to return to our caller. */
34250 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
34253 /* Return whether we need to always update the saved TOC pointer when we update
34254 the stack pointer. */
34257 rs6000_save_toc_in_prologue_p (void)
34259 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
34262 #ifdef HAVE_GAS_HIDDEN
34263 # define USE_HIDDEN_LINKONCE 1
34265 # define USE_HIDDEN_LINKONCE 0
34268 /* Fills in the label name that should be used for a 476 link stack thunk. */
34271 get_ppc476_thunk_name (char name
[32])
34273 gcc_assert (TARGET_LINK_STACK
);
34275 if (USE_HIDDEN_LINKONCE
)
34276 sprintf (name
, "__ppc476.get_thunk");
34278 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
34281 /* This function emits the simple thunk routine that is used to preserve
34282 the link stack on the 476 cpu. */
34284 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
34286 rs6000_code_end (void)
34291 if (!TARGET_LINK_STACK
)
34294 get_ppc476_thunk_name (name
);
34296 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
34297 build_function_type_list (void_type_node
, NULL_TREE
));
34298 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
34299 NULL_TREE
, void_type_node
);
34300 TREE_PUBLIC (decl
) = 1;
34301 TREE_STATIC (decl
) = 1;
34304 if (USE_HIDDEN_LINKONCE
)
34306 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
34307 targetm
.asm_out
.unique_section (decl
, 0);
34308 switch_to_section (get_named_section (decl
, NULL
, 0));
34309 DECL_WEAK (decl
) = 1;
34310 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
34311 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
34312 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
34313 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
34318 switch_to_section (text_section
);
34319 ASM_OUTPUT_LABEL (asm_out_file
, name
);
34322 DECL_INITIAL (decl
) = make_node (BLOCK
);
34323 current_function_decl
= decl
;
34324 init_function_start (decl
);
34325 first_function_block_is_cold
= false;
34326 /* Make sure unwind info is emitted for the thunk if needed. */
34327 final_start_function (emit_barrier (), asm_out_file
, 1);
34329 fputs ("\tblr\n", asm_out_file
);
34331 final_end_function ();
34332 init_insn_lengths ();
34333 free_after_compilation (cfun
);
34335 current_function_decl
= NULL
;
34338 /* Add r30 to hard reg set if the prologue sets it up and it is not
34339 pic_offset_table_rtx. */
34342 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
34344 if (!TARGET_SINGLE_PIC_BASE
34346 && TARGET_MINIMAL_TOC
34347 && get_pool_size () != 0)
34348 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
34349 if (cfun
->machine
->split_stack_argp_used
)
34350 add_to_hard_reg_set (&set
->set
, Pmode
, 12);
34354 /* Helper function for rs6000_split_logical to emit a logical instruction after
34355 spliting the operation to single GPR registers.
34357 DEST is the destination register.
34358 OP1 and OP2 are the input source registers.
34359 CODE is the base operation (AND, IOR, XOR, NOT).
34360 MODE is the machine mode.
34361 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
34362 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
34363 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
34366 rs6000_split_logical_inner (rtx dest
,
34369 enum rtx_code code
,
34371 bool complement_final_p
,
34372 bool complement_op1_p
,
34373 bool complement_op2_p
)
34377 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
34378 if (op2
&& GET_CODE (op2
) == CONST_INT
34379 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
34380 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
34382 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
34383 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
34385 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
34390 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
34394 else if (value
== mask
)
34396 if (!rtx_equal_p (dest
, op1
))
34397 emit_insn (gen_rtx_SET (dest
, op1
));
34402 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
34403 into separate ORI/ORIS or XORI/XORIS instrucitons. */
34404 else if (code
== IOR
|| code
== XOR
)
34408 if (!rtx_equal_p (dest
, op1
))
34409 emit_insn (gen_rtx_SET (dest
, op1
));
34415 if (code
== AND
&& mode
== SImode
34416 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
34418 emit_insn (gen_andsi3 (dest
, op1
, op2
));
34422 if (complement_op1_p
)
34423 op1
= gen_rtx_NOT (mode
, op1
);
34425 if (complement_op2_p
)
34426 op2
= gen_rtx_NOT (mode
, op2
);
34428 /* For canonical RTL, if only one arm is inverted it is the first. */
34429 if (!complement_op1_p
&& complement_op2_p
)
34430 std::swap (op1
, op2
);
34432 bool_rtx
= ((code
== NOT
)
34433 ? gen_rtx_NOT (mode
, op1
)
34434 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
34436 if (complement_final_p
)
34437 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
34439 emit_insn (gen_rtx_SET (dest
, bool_rtx
));
34442 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
34443 operations are split immediately during RTL generation to allow for more
34444 optimizations of the AND/IOR/XOR.
34446 OPERANDS is an array containing the destination and two input operands.
34447 CODE is the base operation (AND, IOR, XOR, NOT).
34448 MODE is the machine mode.
34449 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
34450 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
34451 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
34452 CLOBBER_REG is either NULL or a scratch register of type CC to allow
34453 formation of the AND instructions. */
34456 rs6000_split_logical_di (rtx operands
[3],
34457 enum rtx_code code
,
34458 bool complement_final_p
,
34459 bool complement_op1_p
,
34460 bool complement_op2_p
)
34462 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
34463 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
34464 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
34465 enum hi_lo
{ hi
= 0, lo
= 1 };
34466 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
34469 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
34470 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
34471 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
34472 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
34475 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
34478 if (GET_CODE (operands
[2]) != CONST_INT
)
34480 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
34481 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
34485 HOST_WIDE_INT value
= INTVAL (operands
[2]);
34486 HOST_WIDE_INT value_hi_lo
[2];
34488 gcc_assert (!complement_final_p
);
34489 gcc_assert (!complement_op1_p
);
34490 gcc_assert (!complement_op2_p
);
34492 value_hi_lo
[hi
] = value
>> 32;
34493 value_hi_lo
[lo
] = value
& lower_32bits
;
34495 for (i
= 0; i
< 2; i
++)
34497 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
34499 if (sub_value
& sign_bit
)
34500 sub_value
|= upper_32bits
;
34502 op2_hi_lo
[i
] = GEN_INT (sub_value
);
34504 /* If this is an AND instruction, check to see if we need to load
34505 the value in a register. */
34506 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
34507 && !and_operand (op2_hi_lo
[i
], SImode
))
34508 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
34513 for (i
= 0; i
< 2; i
++)
34515 /* Split large IOR/XOR operations. */
34516 if ((code
== IOR
|| code
== XOR
)
34517 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
34518 && !complement_final_p
34519 && !complement_op1_p
34520 && !complement_op2_p
34521 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
34523 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
34524 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
34525 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
34526 rtx tmp
= gen_reg_rtx (SImode
);
34528 /* Make sure the constant is sign extended. */
34529 if ((hi_16bits
& sign_bit
) != 0)
34530 hi_16bits
|= upper_32bits
;
34532 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
34533 code
, SImode
, false, false, false);
34535 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
34536 code
, SImode
, false, false, false);
34539 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
34540 code
, SImode
, complement_final_p
,
34541 complement_op1_p
, complement_op2_p
);
34547 /* Split the insns that make up boolean operations operating on multiple GPR
34548 registers. The boolean MD patterns ensure that the inputs either are
34549 exactly the same as the output registers, or there is no overlap.
34551 OPERANDS is an array containing the destination and two input operands.
34552 CODE is the base operation (AND, IOR, XOR, NOT).
34553 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
34554 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
34555 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
34558 rs6000_split_logical (rtx operands
[3],
34559 enum rtx_code code
,
34560 bool complement_final_p
,
34561 bool complement_op1_p
,
34562 bool complement_op2_p
)
34564 machine_mode mode
= GET_MODE (operands
[0]);
34565 machine_mode sub_mode
;
34567 int sub_size
, regno0
, regno1
, nregs
, i
;
34569 /* If this is DImode, use the specialized version that can run before
34570 register allocation. */
34571 if (mode
== DImode
&& !TARGET_POWERPC64
)
34573 rs6000_split_logical_di (operands
, code
, complement_final_p
,
34574 complement_op1_p
, complement_op2_p
);
34580 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
34581 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
34582 sub_size
= GET_MODE_SIZE (sub_mode
);
34583 regno0
= REGNO (op0
);
34584 regno1
= REGNO (op1
);
34586 gcc_assert (reload_completed
);
34587 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
34588 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
34590 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
34591 gcc_assert (nregs
> 1);
34593 if (op2
&& REG_P (op2
))
34594 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
34596 for (i
= 0; i
< nregs
; i
++)
34598 int offset
= i
* sub_size
;
34599 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
34600 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
34601 rtx sub_op2
= ((code
== NOT
)
34603 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
34605 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
34606 complement_final_p
, complement_op1_p
,
34614 /* Return true if the peephole2 can combine a load involving a combination of
34615 an addis instruction and a load with an offset that can be fused together on
34619 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
34620 rtx addis_value
, /* addis value. */
34621 rtx target
, /* target register that is loaded. */
34622 rtx mem
) /* bottom part of the memory addr. */
34627 /* Validate arguments. */
34628 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
34631 if (!base_reg_operand (target
, GET_MODE (target
)))
34634 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
34637 /* Allow sign/zero extension. */
34638 if (GET_CODE (mem
) == ZERO_EXTEND
34639 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
34640 mem
= XEXP (mem
, 0);
34645 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
34648 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
34649 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
34652 /* Validate that the register used to load the high value is either the
34653 register being loaded, or we can safely replace its use.
34655 This function is only called from the peephole2 pass and we assume that
34656 there are 2 instructions in the peephole (addis and load), so we want to
34657 check if the target register was not used in the memory address and the
34658 register to hold the addis result is dead after the peephole. */
34659 if (REGNO (addis_reg
) != REGNO (target
))
34661 if (reg_mentioned_p (target
, mem
))
34664 if (!peep2_reg_dead_p (2, addis_reg
))
34667 /* If the target register being loaded is the stack pointer, we must
34668 avoid loading any other value into it, even temporarily. */
34669 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
34673 base_reg
= XEXP (addr
, 0);
34674 return REGNO (addis_reg
) == REGNO (base_reg
);
34677 /* During the peephole2 pass, adjust and expand the insns for a load fusion
34678 sequence. We adjust the addis register to use the target register. If the
34679 load sign extends, we adjust the code to do the zero extending load, and an
34680 explicit sign extension later since the fusion only covers zero extending
34684 operands[0] register set with addis (to be replaced with target)
34685 operands[1] value set via addis
34686 operands[2] target register being loaded
34687 operands[3] D-form memory reference using operands[0]. */
34690 expand_fusion_gpr_load (rtx
*operands
)
34692 rtx addis_value
= operands
[1];
34693 rtx target
= operands
[2];
34694 rtx orig_mem
= operands
[3];
34695 rtx new_addr
, new_mem
, orig_addr
, offset
;
34696 enum rtx_code plus_or_lo_sum
;
34697 machine_mode target_mode
= GET_MODE (target
);
34698 machine_mode extend_mode
= target_mode
;
34699 machine_mode ptr_mode
= Pmode
;
34700 enum rtx_code extend
= UNKNOWN
;
34702 if (GET_CODE (orig_mem
) == ZERO_EXTEND
34703 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
34705 extend
= GET_CODE (orig_mem
);
34706 orig_mem
= XEXP (orig_mem
, 0);
34707 target_mode
= GET_MODE (orig_mem
);
34710 gcc_assert (MEM_P (orig_mem
));
34712 orig_addr
= XEXP (orig_mem
, 0);
34713 plus_or_lo_sum
= GET_CODE (orig_addr
);
34714 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
34716 offset
= XEXP (orig_addr
, 1);
34717 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
34718 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
34720 if (extend
!= UNKNOWN
)
34721 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
34723 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
34724 UNSPEC_FUSION_GPR
);
34725 emit_insn (gen_rtx_SET (target
, new_mem
));
34727 if (extend
== SIGN_EXTEND
)
34729 int sub_off
= ((BYTES_BIG_ENDIAN
)
34730 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
34733 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
34735 emit_insn (gen_rtx_SET (target
,
34736 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
34742 /* Return a string to fuse an addis instruction with a gpr load to the same
34743 register that we loaded up the addis instruction. The address that is used
34744 is the logical address that was formed during peephole2:
34745 (lo_sum (high) (low-part))
34747 The code is complicated, so we call output_asm_insn directly, and just
34751 emit_fusion_gpr_load (rtx target
, rtx mem
)
34757 const char *addis_str
= NULL
;
34758 const char *load_str
= NULL
;
34759 const char *mode_name
= NULL
;
34760 char insn_template
[80];
34762 const char *comment_str
= ASM_COMMENT_START
;
34764 if (GET_CODE (mem
) == ZERO_EXTEND
)
34765 mem
= XEXP (mem
, 0);
34767 gcc_assert (REG_P (target
) && MEM_P (mem
));
34769 if (*comment_str
== ' ')
34772 addr
= XEXP (mem
, 0);
34773 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
34774 gcc_unreachable ();
34776 addis_value
= XEXP (addr
, 0);
34777 load_offset
= XEXP (addr
, 1);
34779 /* Now emit the load instruction to the same register. */
34780 mode
= GET_MODE (mem
);
34784 mode_name
= "char";
34789 mode_name
= "short";
34799 gcc_assert (TARGET_POWERPC64
);
34800 mode_name
= "long";
34805 gcc_unreachable ();
34808 /* Emit the addis instruction. */
34809 fuse_ops
[0] = target
;
34810 if (satisfies_constraint_L (addis_value
))
34812 fuse_ops
[1] = addis_value
;
34813 addis_str
= "lis %0,%v1";
34816 else if (GET_CODE (addis_value
) == PLUS
)
34818 rtx op0
= XEXP (addis_value
, 0);
34819 rtx op1
= XEXP (addis_value
, 1);
34821 if (REG_P (op0
) && CONST_INT_P (op1
)
34822 && satisfies_constraint_L (op1
))
34826 addis_str
= "addis %0,%1,%v2";
34830 else if (GET_CODE (addis_value
) == HIGH
)
34832 rtx value
= XEXP (addis_value
, 0);
34833 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
34835 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
34836 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
34838 addis_str
= "addis %0,%2,%1@toc@ha";
34840 else if (TARGET_XCOFF
)
34841 addis_str
= "addis %0,%1@u(%2)";
34844 gcc_unreachable ();
34847 else if (GET_CODE (value
) == PLUS
)
34849 rtx op0
= XEXP (value
, 0);
34850 rtx op1
= XEXP (value
, 1);
34852 if (GET_CODE (op0
) == UNSPEC
34853 && XINT (op0
, 1) == UNSPEC_TOCREL
34854 && CONST_INT_P (op1
))
34856 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
34857 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
34860 addis_str
= "addis %0,%2,%1+%3@toc@ha";
34862 else if (TARGET_XCOFF
)
34863 addis_str
= "addis %0,%1+%3@u(%2)";
34866 gcc_unreachable ();
34870 else if (satisfies_constraint_L (value
))
34872 fuse_ops
[1] = value
;
34873 addis_str
= "lis %0,%v1";
34876 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
34878 fuse_ops
[1] = value
;
34879 addis_str
= "lis %0,%1@ha";
34884 fatal_insn ("Could not generate addis value for fusion", addis_value
);
34886 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
34887 comment_str
, mode_name
);
34888 output_asm_insn (insn_template
, fuse_ops
);
34890 /* Emit the D-form load instruction. */
34891 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
34893 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
34894 fuse_ops
[1] = load_offset
;
34895 output_asm_insn (insn_template
, fuse_ops
);
34898 else if (GET_CODE (load_offset
) == UNSPEC
34899 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
34902 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
34904 else if (TARGET_XCOFF
)
34905 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
34908 gcc_unreachable ();
34910 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
34911 output_asm_insn (insn_template
, fuse_ops
);
34914 else if (GET_CODE (load_offset
) == PLUS
34915 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
34916 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
34917 && CONST_INT_P (XEXP (load_offset
, 1)))
34919 rtx tocrel_unspec
= XEXP (load_offset
, 0);
34921 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
34923 else if (TARGET_XCOFF
)
34924 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
34927 gcc_unreachable ();
34929 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
34930 fuse_ops
[2] = XEXP (load_offset
, 1);
34931 output_asm_insn (insn_template
, fuse_ops
);
34934 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
34936 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
34938 fuse_ops
[1] = load_offset
;
34939 output_asm_insn (insn_template
, fuse_ops
);
34943 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
34948 /* Analyze vector computations and remove unnecessary doubleword
34949 swaps (xxswapdi instructions). This pass is performed only
34950 for little-endian VSX code generation.
34952 For this specific case, loads and stores of 4x32 and 2x64 vectors
34953 are inefficient. These are implemented using the lvx2dx and
34954 stvx2dx instructions, which invert the order of doublewords in
34955 a vector register. Thus the code generation inserts an xxswapdi
34956 after each such load, and prior to each such store. (For spill
34957 code after register assignment, an additional xxswapdi is inserted
34958 following each store in order to return a hard register to its
34961 The extra xxswapdi instructions reduce performance. This can be
34962 particularly bad for vectorized code. The purpose of this pass
34963 is to reduce the number of xxswapdi instructions required for
34966 The primary insight is that much code that operates on vectors
34967 does not care about the relative order of elements in a register,
34968 so long as the correct memory order is preserved. If we have
34969 a computation where all input values are provided by lvxd2x/xxswapdi
34970 sequences, all outputs are stored using xxswapdi/stvxd2x sequences,
34971 and all intermediate computations are pure SIMD (independent of
34972 element order), then all the xxswapdi's associated with the loads
34973 and stores may be removed.
34975 This pass uses some of the infrastructure and logical ideas from
34976 the "web" pass in web.c. We create maximal webs of computations
34977 fitting the description above using union-find. Each such web is
34978 then optimized by removing its unnecessary xxswapdi instructions.
34980 The pass is placed prior to global optimization so that we can
34981 perform the optimization in the safest and simplest way possible;
34982 that is, by replacing each xxswapdi insn with a register copy insn.
34983 Subsequent forward propagation will remove copies where possible.
34985 There are some operations sensitive to element order for which we
34986 can still allow the operation, provided we modify those operations.
34987 These include CONST_VECTORs, for which we must swap the first and
34988 second halves of the constant vector; and SUBREGs, for which we
34989 must adjust the byte offset to account for the swapped doublewords.
34990 A remaining opportunity would be non-immediate-form splats, for
34991 which we should adjust the selected lane of the input. We should
34992 also make code generation adjustments for sum-across operations,
34993 since this is a common vectorizer reduction.
34995 Because we run prior to the first split, we can see loads and stores
34996 here that match *vsx_le_perm_{load,store}_<mode>. These are vanilla
34997 vector loads and stores that have not yet been split into a permuting
34998 load/store and a swap. (One way this can happen is with a builtin
34999 call to vec_vsx_{ld,st}.) We can handle these as well, but rather
35000 than deleting a swap, we convert the load/store into a permuting
35001 load/store (which effectively removes the swap). */
35003 /* Notes on Permutes
35005 We do not currently handle computations that contain permutes. There
35006 is a general transformation that can be performed correctly, but it
35007 may introduce more expensive code than it replaces. To handle these
35008 would require a cost model to determine when to perform the optimization.
35009 This commentary records how this could be done if desired.
35011 The most general permute is something like this (example for V16QI):
35013 (vec_select:V16QI (vec_concat:V32QI (op1:V16QI) (op2:V16QI))
35014 (parallel [(const_int a0) (const_int a1)
35016 (const_int a14) (const_int a15)]))
35018 where a0,...,a15 are in [0,31] and select elements from op1 and op2
35019 to produce in the result.
35021 Regardless of mode, we can convert the PARALLEL to a mask of 16
35022 byte-element selectors. Let's call this M, with M[i] representing
35023 the ith byte-element selector value. Then if we swap doublewords
35024 throughout the computation, we can get correct behavior by replacing
35025 M with M' as follows:
35027 M'[i] = { (M[i]+8)%16 : M[i] in [0,15]
35028 { ((M[i]+8)%16)+16 : M[i] in [16,31]
35030 This seems promising at first, since we are just replacing one mask
35031 with another. But certain masks are preferable to others. If M
35032 is a mask that matches a vmrghh pattern, for example, M' certainly
35033 will not. Instead of a single vmrghh, we would generate a load of
35034 M' and a vperm. So we would need to know how many xxswapd's we can
35035 remove as a result of this transformation to determine if it's
35036 profitable; and preferably the logic would need to be aware of all
35037 the special preferable masks.
35039 Another form of permute is an UNSPEC_VPERM, in which the mask is
35040 already in a register. In some cases, this mask may be a constant
35041 that we can discover with ud-chains, in which case the above
35042 transformation is ok. However, the common usage here is for the
35043 mask to be produced by an UNSPEC_LVSL, in which case the mask
35044 cannot be known at compile time. In such a case we would have to
35045 generate several instructions to compute M' as above at run time,
35046 and a cost model is needed again.
35048 However, when the mask M for an UNSPEC_VPERM is loaded from the
35049 constant pool, we can replace M with M' as above at no cost
35050 beyond adding a constant pool entry. */
35052 /* This is based on the union-find logic in web.c. web_entry_base is
35053 defined in df.h. */
35054 class swap_web_entry
: public web_entry_base
35057 /* Pointer to the insn. */
35059 /* Set if insn contains a mention of a vector register. All other
35060 fields are undefined if this field is unset. */
35061 unsigned int is_relevant
: 1;
35062 /* Set if insn is a load. */
35063 unsigned int is_load
: 1;
35064 /* Set if insn is a store. */
35065 unsigned int is_store
: 1;
35066 /* Set if insn is a doubleword swap. This can either be a register swap
35067 or a permuting load or store (test is_load and is_store for this). */
35068 unsigned int is_swap
: 1;
35069 /* Set if the insn has a live-in use of a parameter register. */
35070 unsigned int is_live_in
: 1;
35071 /* Set if the insn has a live-out def of a return register. */
35072 unsigned int is_live_out
: 1;
35073 /* Set if the insn contains a subreg reference of a vector register. */
35074 unsigned int contains_subreg
: 1;
35075 /* Set if the insn contains a 128-bit integer operand. */
35076 unsigned int is_128_int
: 1;
35077 /* Set if this is a call-insn. */
35078 unsigned int is_call
: 1;
35079 /* Set if this insn does not perform a vector operation for which
35080 element order matters, or if we know how to fix it up if it does.
35081 Undefined if is_swap is set. */
35082 unsigned int is_swappable
: 1;
35083 /* A nonzero value indicates what kind of special handling for this
35084 insn is required if doublewords are swapped. Undefined if
35085 is_swappable is not set. */
35086 unsigned int special_handling
: 4;
35087 /* Set if the web represented by this entry cannot be optimized. */
35088 unsigned int web_not_optimizable
: 1;
35089 /* Set if this insn should be deleted. */
35090 unsigned int will_delete
: 1;
35093 enum special_handling_values
{
35106 /* Union INSN with all insns containing definitions that reach USE.
35107 Detect whether USE is live-in to the current function. */
35109 union_defs (swap_web_entry
*insn_entry
, rtx insn
, df_ref use
)
35111 struct df_link
*link
= DF_REF_CHAIN (use
);
35114 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
35118 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
35119 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
35121 if (DF_REF_INSN_INFO (link
->ref
))
35123 rtx def_insn
= DF_REF_INSN (link
->ref
);
35124 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
35125 insn_entry
+ INSN_UID (def_insn
));
35132 /* Union INSN with all insns containing uses reached from DEF.
35133 Detect whether DEF is live-out from the current function. */
35135 union_uses (swap_web_entry
*insn_entry
, rtx insn
, df_ref def
)
35137 struct df_link
*link
= DF_REF_CHAIN (def
);
35140 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
35144 /* This could be an eh use or some other artificial use;
35145 we treat these all the same (killing the optimization). */
35146 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
35147 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
35149 if (DF_REF_INSN_INFO (link
->ref
))
35151 rtx use_insn
= DF_REF_INSN (link
->ref
);
35152 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
35153 insn_entry
+ INSN_UID (use_insn
));
35160 /* Return 1 iff INSN is a load insn, including permuting loads that
35161 represent an lvxd2x instruction; else return 0. */
35162 static unsigned int
35163 insn_is_load_p (rtx insn
)
35165 rtx body
= PATTERN (insn
);
35167 if (GET_CODE (body
) == SET
)
35169 if (GET_CODE (SET_SRC (body
)) == MEM
)
35172 if (GET_CODE (SET_SRC (body
)) == VEC_SELECT
35173 && GET_CODE (XEXP (SET_SRC (body
), 0)) == MEM
)
35179 if (GET_CODE (body
) != PARALLEL
)
35182 rtx set
= XVECEXP (body
, 0, 0);
35184 if (GET_CODE (set
) == SET
&& GET_CODE (SET_SRC (set
)) == MEM
)
35190 /* Return 1 iff INSN is a store insn, including permuting stores that
35191 represent an stvxd2x instruction; else return 0. */
35192 static unsigned int
35193 insn_is_store_p (rtx insn
)
35195 rtx body
= PATTERN (insn
);
35196 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == MEM
)
35198 if (GET_CODE (body
) != PARALLEL
)
35200 rtx set
= XVECEXP (body
, 0, 0);
35201 if (GET_CODE (set
) == SET
&& GET_CODE (SET_DEST (set
)) == MEM
)
35206 /* Return 1 iff INSN swaps doublewords. This may be a reg-reg swap,
35207 a permuting load, or a permuting store. */
35208 static unsigned int
35209 insn_is_swap_p (rtx insn
)
35211 rtx body
= PATTERN (insn
);
35212 if (GET_CODE (body
) != SET
)
35214 rtx rhs
= SET_SRC (body
);
35215 if (GET_CODE (rhs
) != VEC_SELECT
)
35217 rtx parallel
= XEXP (rhs
, 1);
35218 if (GET_CODE (parallel
) != PARALLEL
)
35220 unsigned int len
= XVECLEN (parallel
, 0);
35221 if (len
!= 2 && len
!= 4 && len
!= 8 && len
!= 16)
35223 for (unsigned int i
= 0; i
< len
/ 2; ++i
)
35225 rtx op
= XVECEXP (parallel
, 0, i
);
35226 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != len
/ 2 + i
)
35229 for (unsigned int i
= len
/ 2; i
< len
; ++i
)
35231 rtx op
= XVECEXP (parallel
, 0, i
);
35232 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != i
- len
/ 2)
35238 /* Return TRUE if insn is a swap fed by a load from the constant pool. */
35240 const_load_sequence_p (swap_web_entry
*insn_entry
, rtx insn
)
35242 unsigned uid
= INSN_UID (insn
);
35243 if (!insn_entry
[uid
].is_swap
|| insn_entry
[uid
].is_load
)
35246 /* Find the unique use in the swap and locate its def. If the def
35247 isn't unique, punt. */
35248 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
35250 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
35252 struct df_link
*def_link
= DF_REF_CHAIN (use
);
35253 if (!def_link
|| def_link
->next
)
35256 rtx def_insn
= DF_REF_INSN (def_link
->ref
);
35257 unsigned uid2
= INSN_UID (def_insn
);
35258 if (!insn_entry
[uid2
].is_load
|| !insn_entry
[uid2
].is_swap
)
35261 rtx body
= PATTERN (def_insn
);
35262 if (GET_CODE (body
) != SET
35263 || GET_CODE (SET_SRC (body
)) != VEC_SELECT
35264 || GET_CODE (XEXP (SET_SRC (body
), 0)) != MEM
)
35267 rtx mem
= XEXP (SET_SRC (body
), 0);
35268 rtx base_reg
= XEXP (mem
, 0);
35271 insn_info
= DF_INSN_INFO_GET (def_insn
);
35272 FOR_EACH_INSN_INFO_USE (base_use
, insn_info
)
35274 if (!rtx_equal_p (DF_REF_REG (base_use
), base_reg
))
35277 struct df_link
*base_def_link
= DF_REF_CHAIN (base_use
);
35278 if (!base_def_link
|| base_def_link
->next
)
35281 rtx tocrel_insn
= DF_REF_INSN (base_def_link
->ref
);
35282 rtx tocrel_body
= PATTERN (tocrel_insn
);
35284 if (GET_CODE (tocrel_body
) != SET
)
35286 if (!toc_relative_expr_p (SET_SRC (tocrel_body
), false))
35288 split_const (XVECEXP (tocrel_base
, 0, 0), &base
, &offset
);
35289 if (GET_CODE (base
) != SYMBOL_REF
|| !CONSTANT_POOL_ADDRESS_P (base
))
35296 /* Return 1 iff OP is an operand that will not be affected by having
35297 vector doublewords swapped in memory. */
35298 static unsigned int
35299 rtx_is_swappable_p (rtx op
, unsigned int *special
)
35301 enum rtx_code code
= GET_CODE (op
);
35320 *special
= SH_CONST_VECTOR
;
35324 case VEC_DUPLICATE
:
35325 /* Opportunity: If XEXP (op, 0) has the same mode as the result,
35326 and XEXP (op, 1) is a PARALLEL with a single QImode const int,
35327 it represents a vector splat for which we can do special
35329 if (GET_CODE (XEXP (op
, 0)) == CONST_INT
)
35331 else if (GET_CODE (XEXP (op
, 0)) == REG
35332 && GET_MODE_INNER (GET_MODE (op
)) == GET_MODE (XEXP (op
, 0)))
35333 /* This catches V2DF and V2DI splat, at a minimum. */
35335 else if (GET_CODE (XEXP (op
, 0)) == VEC_SELECT
)
35336 /* If the duplicated item is from a select, defer to the select
35337 processing to see if we can change the lane for the splat. */
35338 return rtx_is_swappable_p (XEXP (op
, 0), special
);
35343 /* A vec_extract operation is ok if we change the lane. */
35344 if (GET_CODE (XEXP (op
, 0)) == REG
35345 && GET_MODE_INNER (GET_MODE (XEXP (op
, 0))) == GET_MODE (op
)
35346 && GET_CODE ((parallel
= XEXP (op
, 1))) == PARALLEL
35347 && XVECLEN (parallel
, 0) == 1
35348 && GET_CODE (XVECEXP (parallel
, 0, 0)) == CONST_INT
)
35350 *special
= SH_EXTRACT
;
35353 /* An XXPERMDI is ok if we adjust the lanes. Note that if the
35354 XXPERMDI is a swap operation, it will be identified by
35355 insn_is_swap_p and therefore we won't get here. */
35356 else if (GET_CODE (XEXP (op
, 0)) == VEC_CONCAT
35357 && (GET_MODE (XEXP (op
, 0)) == V4DFmode
35358 || GET_MODE (XEXP (op
, 0)) == V4DImode
)
35359 && GET_CODE ((parallel
= XEXP (op
, 1))) == PARALLEL
35360 && XVECLEN (parallel
, 0) == 2
35361 && GET_CODE (XVECEXP (parallel
, 0, 0)) == CONST_INT
35362 && GET_CODE (XVECEXP (parallel
, 0, 1)) == CONST_INT
)
35364 *special
= SH_XXPERMDI
;
35372 /* Various operations are unsafe for this optimization, at least
35373 without significant additional work. Permutes are obviously
35374 problematic, as both the permute control vector and the ordering
35375 of the target values are invalidated by doubleword swapping.
35376 Vector pack and unpack modify the number of vector lanes.
35377 Merge-high/low will not operate correctly on swapped operands.
35378 Vector shifts across element boundaries are clearly uncool,
35379 as are vector select and concatenate operations. Vector
35380 sum-across instructions define one operand with a specific
35381 order-dependent element, so additional fixup code would be
35382 needed to make those work. Vector set and non-immediate-form
35383 vector splat are element-order sensitive. A few of these
35384 cases might be workable with special handling if required.
35385 Adding cost modeling would be appropriate in some cases. */
35386 int val
= XINT (op
, 1);
35391 case UNSPEC_VMRGH_DIRECT
:
35392 case UNSPEC_VMRGL_DIRECT
:
35393 case UNSPEC_VPACK_SIGN_SIGN_SAT
:
35394 case UNSPEC_VPACK_SIGN_UNS_SAT
:
35395 case UNSPEC_VPACK_UNS_UNS_MOD
:
35396 case UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
:
35397 case UNSPEC_VPACK_UNS_UNS_SAT
:
35399 case UNSPEC_VPERM_UNS
:
35400 case UNSPEC_VPERMHI
:
35401 case UNSPEC_VPERMSI
:
35403 case UNSPEC_VSLDOI
:
35406 case UNSPEC_VSUM2SWS
:
35407 case UNSPEC_VSUM4S
:
35408 case UNSPEC_VSUM4UBS
:
35409 case UNSPEC_VSUMSWS
:
35410 case UNSPEC_VSUMSWS_DIRECT
:
35411 case UNSPEC_VSX_CONCAT
:
35412 case UNSPEC_VSX_SET
:
35413 case UNSPEC_VSX_SLDWI
:
35414 case UNSPEC_VUNPACK_HI_SIGN
:
35415 case UNSPEC_VUNPACK_HI_SIGN_DIRECT
:
35416 case UNSPEC_VUNPACK_LO_SIGN
:
35417 case UNSPEC_VUNPACK_LO_SIGN_DIRECT
:
35418 case UNSPEC_VUPKHPX
:
35419 case UNSPEC_VUPKHS_V4SF
:
35420 case UNSPEC_VUPKHU_V4SF
:
35421 case UNSPEC_VUPKLPX
:
35422 case UNSPEC_VUPKLS_V4SF
:
35423 case UNSPEC_VUPKLU_V4SF
:
35424 case UNSPEC_VSX_CVDPSPN
:
35425 case UNSPEC_VSX_CVSPDP
:
35426 case UNSPEC_VSX_CVSPDPN
:
35428 case UNSPEC_VSPLT_DIRECT
:
35429 *special
= SH_SPLAT
;
35438 const char *fmt
= GET_RTX_FORMAT (code
);
35441 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
35442 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
35444 unsigned int special_op
= SH_NONE
;
35445 ok
&= rtx_is_swappable_p (XEXP (op
, i
), &special_op
);
35446 if (special_op
== SH_NONE
)
35448 /* Ensure we never have two kinds of special handling
35449 for the same insn. */
35450 if (*special
!= SH_NONE
&& *special
!= special_op
)
35452 *special
= special_op
;
35454 else if (fmt
[i
] == 'E')
35455 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
35457 unsigned int special_op
= SH_NONE
;
35458 ok
&= rtx_is_swappable_p (XVECEXP (op
, i
, j
), &special_op
);
35459 if (special_op
== SH_NONE
)
35461 /* Ensure we never have two kinds of special handling
35462 for the same insn. */
35463 if (*special
!= SH_NONE
&& *special
!= special_op
)
35465 *special
= special_op
;
35471 /* Return 1 iff INSN is an operand that will not be affected by
35472 having vector doublewords swapped in memory (in which case
35473 *SPECIAL is unchanged), or that can be modified to be correct
35474 if vector doublewords are swapped in memory (in which case
35475 *SPECIAL is changed to a value indicating how). */
35476 static unsigned int
35477 insn_is_swappable_p (swap_web_entry
*insn_entry
, rtx insn
,
35478 unsigned int *special
)
35480 /* Calls are always bad. */
35481 if (GET_CODE (insn
) == CALL_INSN
)
35484 /* Loads and stores seen here are not permuting, but we can still
35485 fix them up by converting them to permuting ones. Exceptions:
35486 UNSPEC_LVE, UNSPEC_LVX, and UNSPEC_STVX, which have a PARALLEL
35487 body instead of a SET; and UNSPEC_STVE, which has an UNSPEC
35488 for the SET source. */
35489 rtx body
= PATTERN (insn
);
35490 int i
= INSN_UID (insn
);
35492 if (insn_entry
[i
].is_load
)
35494 if (GET_CODE (body
) == SET
)
35496 *special
= SH_NOSWAP_LD
;
35503 if (insn_entry
[i
].is_store
)
35505 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) != UNSPEC
)
35507 *special
= SH_NOSWAP_ST
;
35514 /* A convert to single precision can be left as is provided that
35515 all of its uses are in xxspltw instructions that splat BE element
35517 if (GET_CODE (body
) == SET
35518 && GET_CODE (SET_SRC (body
)) == UNSPEC
35519 && XINT (SET_SRC (body
), 1) == UNSPEC_VSX_CVDPSPN
)
35522 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
35524 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
35526 struct df_link
*link
= DF_REF_CHAIN (def
);
35530 for (; link
; link
= link
->next
) {
35531 rtx use_insn
= DF_REF_INSN (link
->ref
);
35532 rtx use_body
= PATTERN (use_insn
);
35533 if (GET_CODE (use_body
) != SET
35534 || GET_CODE (SET_SRC (use_body
)) != UNSPEC
35535 || XINT (SET_SRC (use_body
), 1) != UNSPEC_VSX_XXSPLTW
35536 || XEXP (XEXP (SET_SRC (use_body
), 0), 1) != const0_rtx
)
35544 /* A concatenation of two doublewords is ok if we reverse the
35545 order of the inputs. */
35546 if (GET_CODE (body
) == SET
35547 && GET_CODE (SET_SRC (body
)) == VEC_CONCAT
35548 && (GET_MODE (SET_SRC (body
)) == V2DFmode
35549 || GET_MODE (SET_SRC (body
)) == V2DImode
))
35551 *special
= SH_CONCAT
;
35555 /* An UNSPEC_VPERM is ok if the mask operand is loaded from the
35557 if (GET_CODE (body
) == SET
35558 && GET_CODE (SET_SRC (body
)) == UNSPEC
35559 && XINT (SET_SRC (body
), 1) == UNSPEC_VPERM
35560 && XVECLEN (SET_SRC (body
), 0) == 3
35561 && GET_CODE (XVECEXP (SET_SRC (body
), 0, 2)) == REG
)
35563 rtx mask_reg
= XVECEXP (SET_SRC (body
), 0, 2);
35564 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
35566 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
35567 if (rtx_equal_p (DF_REF_REG (use
), mask_reg
))
35569 struct df_link
*def_link
= DF_REF_CHAIN (use
);
35570 /* Punt if multiple definitions for this reg. */
35571 if (def_link
&& !def_link
->next
&&
35572 const_load_sequence_p (insn_entry
,
35573 DF_REF_INSN (def_link
->ref
)))
35575 *special
= SH_VPERM
;
35581 /* Otherwise check the operands for vector lane violations. */
35582 return rtx_is_swappable_p (body
, special
);
35585 enum chain_purpose
{ FOR_LOADS
, FOR_STORES
};
35587 /* Return true if the UD or DU chain headed by LINK is non-empty,
35588 and every entry on the chain references an insn that is a
35589 register swap. Furthermore, if PURPOSE is FOR_LOADS, each such
35590 register swap must have only permuting loads as reaching defs.
35591 If PURPOSE is FOR_STORES, each such register swap must have only
35592 register swaps or permuting stores as reached uses. */
35594 chain_contains_only_swaps (swap_web_entry
*insn_entry
, struct df_link
*link
,
35595 enum chain_purpose purpose
)
35600 for (; link
; link
= link
->next
)
35602 if (!VECTOR_MODE_P (GET_MODE (DF_REF_REG (link
->ref
))))
35605 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
35608 rtx reached_insn
= DF_REF_INSN (link
->ref
);
35609 unsigned uid
= INSN_UID (reached_insn
);
35610 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (reached_insn
);
35612 if (!insn_entry
[uid
].is_swap
|| insn_entry
[uid
].is_load
35613 || insn_entry
[uid
].is_store
)
35616 if (purpose
== FOR_LOADS
)
35619 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
35621 struct df_link
*swap_link
= DF_REF_CHAIN (use
);
35625 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
35628 rtx swap_def_insn
= DF_REF_INSN (swap_link
->ref
);
35629 unsigned uid2
= INSN_UID (swap_def_insn
);
35631 /* Only permuting loads are allowed. */
35632 if (!insn_entry
[uid2
].is_swap
|| !insn_entry
[uid2
].is_load
)
35635 swap_link
= swap_link
->next
;
35639 else if (purpose
== FOR_STORES
)
35642 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
35644 struct df_link
*swap_link
= DF_REF_CHAIN (def
);
35648 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
35651 rtx swap_use_insn
= DF_REF_INSN (swap_link
->ref
);
35652 unsigned uid2
= INSN_UID (swap_use_insn
);
35654 /* Permuting stores or register swaps are allowed. */
35655 if (!insn_entry
[uid2
].is_swap
|| insn_entry
[uid2
].is_load
)
35658 swap_link
= swap_link
->next
;
35667 /* Mark the xxswapdi instructions associated with permuting loads and
35668 stores for removal. Note that we only flag them for deletion here,
35669 as there is a possibility of a swap being reached from multiple
35672 mark_swaps_for_removal (swap_web_entry
*insn_entry
, unsigned int i
)
35674 rtx insn
= insn_entry
[i
].insn
;
35675 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
35677 if (insn_entry
[i
].is_load
)
35680 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
35682 struct df_link
*link
= DF_REF_CHAIN (def
);
35684 /* We know by now that these are swaps, so we can delete
35685 them confidently. */
35688 rtx use_insn
= DF_REF_INSN (link
->ref
);
35689 insn_entry
[INSN_UID (use_insn
)].will_delete
= 1;
35694 else if (insn_entry
[i
].is_store
)
35697 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
35699 /* Ignore uses for addressability. */
35700 machine_mode mode
= GET_MODE (DF_REF_REG (use
));
35701 if (!VECTOR_MODE_P (mode
))
35704 struct df_link
*link
= DF_REF_CHAIN (use
);
35706 /* We know by now that these are swaps, so we can delete
35707 them confidently. */
35710 rtx def_insn
= DF_REF_INSN (link
->ref
);
35711 insn_entry
[INSN_UID (def_insn
)].will_delete
= 1;
35718 /* OP is either a CONST_VECTOR or an expression containing one.
35719 Swap the first half of the vector with the second in the first
35720 case. Recurse to find it in the second. */
35722 swap_const_vector_halves (rtx op
)
35725 enum rtx_code code
= GET_CODE (op
);
35726 if (GET_CODE (op
) == CONST_VECTOR
)
35728 int half_units
= GET_MODE_NUNITS (GET_MODE (op
)) / 2;
35729 for (i
= 0; i
< half_units
; ++i
)
35731 rtx temp
= CONST_VECTOR_ELT (op
, i
);
35732 CONST_VECTOR_ELT (op
, i
) = CONST_VECTOR_ELT (op
, i
+ half_units
);
35733 CONST_VECTOR_ELT (op
, i
+ half_units
) = temp
;
35739 const char *fmt
= GET_RTX_FORMAT (code
);
35740 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
35741 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
35742 swap_const_vector_halves (XEXP (op
, i
));
35743 else if (fmt
[i
] == 'E')
35744 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
35745 swap_const_vector_halves (XVECEXP (op
, i
, j
));
35749 /* Find all subregs of a vector expression that perform a narrowing,
35750 and adjust the subreg index to account for doubleword swapping. */
35752 adjust_subreg_index (rtx op
)
35754 enum rtx_code code
= GET_CODE (op
);
35756 && (GET_MODE_SIZE (GET_MODE (op
))
35757 < GET_MODE_SIZE (GET_MODE (XEXP (op
, 0)))))
35759 unsigned int index
= SUBREG_BYTE (op
);
35764 SUBREG_BYTE (op
) = index
;
35767 const char *fmt
= GET_RTX_FORMAT (code
);
35769 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
35770 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
35771 adjust_subreg_index (XEXP (op
, i
));
35772 else if (fmt
[i
] == 'E')
35773 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
35774 adjust_subreg_index (XVECEXP (op
, i
, j
));
35777 /* Convert the non-permuting load INSN to a permuting one. */
35779 permute_load (rtx_insn
*insn
)
35781 rtx body
= PATTERN (insn
);
35782 rtx mem_op
= SET_SRC (body
);
35783 rtx tgt_reg
= SET_DEST (body
);
35784 machine_mode mode
= GET_MODE (tgt_reg
);
35785 int n_elts
= GET_MODE_NUNITS (mode
);
35786 int half_elts
= n_elts
/ 2;
35787 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
35789 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
35790 XVECEXP (par
, 0, i
) = GEN_INT (j
);
35791 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
35792 XVECEXP (par
, 0, i
) = GEN_INT (j
);
35793 rtx sel
= gen_rtx_VEC_SELECT (mode
, mem_op
, par
);
35794 SET_SRC (body
) = sel
;
35795 INSN_CODE (insn
) = -1; /* Force re-recognition. */
35796 df_insn_rescan (insn
);
35799 fprintf (dump_file
, "Replacing load %d with permuted load\n",
35803 /* Convert the non-permuting store INSN to a permuting one. */
35805 permute_store (rtx_insn
*insn
)
35807 rtx body
= PATTERN (insn
);
35808 rtx src_reg
= SET_SRC (body
);
35809 machine_mode mode
= GET_MODE (src_reg
);
35810 int n_elts
= GET_MODE_NUNITS (mode
);
35811 int half_elts
= n_elts
/ 2;
35812 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
35814 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
35815 XVECEXP (par
, 0, i
) = GEN_INT (j
);
35816 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
35817 XVECEXP (par
, 0, i
) = GEN_INT (j
);
35818 rtx sel
= gen_rtx_VEC_SELECT (mode
, src_reg
, par
);
35819 SET_SRC (body
) = sel
;
35820 INSN_CODE (insn
) = -1; /* Force re-recognition. */
35821 df_insn_rescan (insn
);
35824 fprintf (dump_file
, "Replacing store %d with permuted store\n",
35828 /* Given OP that contains a vector extract operation, adjust the index
35829 of the extracted lane to account for the doubleword swap. */
35831 adjust_extract (rtx_insn
*insn
)
35833 rtx pattern
= PATTERN (insn
);
35834 if (GET_CODE (pattern
) == PARALLEL
)
35835 pattern
= XVECEXP (pattern
, 0, 0);
35836 rtx src
= SET_SRC (pattern
);
35837 /* The vec_select may be wrapped in a vec_duplicate for a splat, so
35838 account for that. */
35839 rtx sel
= GET_CODE (src
) == VEC_DUPLICATE
? XEXP (src
, 0) : src
;
35840 rtx par
= XEXP (sel
, 1);
35841 int half_elts
= GET_MODE_NUNITS (GET_MODE (XEXP (sel
, 0))) >> 1;
35842 int lane
= INTVAL (XVECEXP (par
, 0, 0));
35843 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
35844 XVECEXP (par
, 0, 0) = GEN_INT (lane
);
35845 INSN_CODE (insn
) = -1; /* Force re-recognition. */
35846 df_insn_rescan (insn
);
35849 fprintf (dump_file
, "Changing lane for extract %d\n", INSN_UID (insn
));
35852 /* Given OP that contains a vector direct-splat operation, adjust the index
35853 of the source lane to account for the doubleword swap. */
35855 adjust_splat (rtx_insn
*insn
)
35857 rtx body
= PATTERN (insn
);
35858 rtx unspec
= XEXP (body
, 1);
35859 int half_elts
= GET_MODE_NUNITS (GET_MODE (unspec
)) >> 1;
35860 int lane
= INTVAL (XVECEXP (unspec
, 0, 1));
35861 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
35862 XVECEXP (unspec
, 0, 1) = GEN_INT (lane
);
35863 INSN_CODE (insn
) = -1; /* Force re-recognition. */
35864 df_insn_rescan (insn
);
35867 fprintf (dump_file
, "Changing lane for splat %d\n", INSN_UID (insn
));
35870 /* Given OP that contains an XXPERMDI operation (that is not a doubleword
35871 swap), reverse the order of the source operands and adjust the indices
35872 of the source lanes to account for doubleword reversal. */
35874 adjust_xxpermdi (rtx_insn
*insn
)
35876 rtx set
= PATTERN (insn
);
35877 rtx select
= XEXP (set
, 1);
35878 rtx concat
= XEXP (select
, 0);
35879 rtx src0
= XEXP (concat
, 0);
35880 XEXP (concat
, 0) = XEXP (concat
, 1);
35881 XEXP (concat
, 1) = src0
;
35882 rtx parallel
= XEXP (select
, 1);
35883 int lane0
= INTVAL (XVECEXP (parallel
, 0, 0));
35884 int lane1
= INTVAL (XVECEXP (parallel
, 0, 1));
35885 int new_lane0
= 3 - lane1
;
35886 int new_lane1
= 3 - lane0
;
35887 XVECEXP (parallel
, 0, 0) = GEN_INT (new_lane0
);
35888 XVECEXP (parallel
, 0, 1) = GEN_INT (new_lane1
);
35889 INSN_CODE (insn
) = -1; /* Force re-recognition. */
35890 df_insn_rescan (insn
);
35893 fprintf (dump_file
, "Changing lanes for xxpermdi %d\n", INSN_UID (insn
));
35896 /* Given OP that contains a VEC_CONCAT operation of two doublewords,
35897 reverse the order of those inputs. */
35899 adjust_concat (rtx_insn
*insn
)
35901 rtx set
= PATTERN (insn
);
35902 rtx concat
= XEXP (set
, 1);
35903 rtx src0
= XEXP (concat
, 0);
35904 XEXP (concat
, 0) = XEXP (concat
, 1);
35905 XEXP (concat
, 1) = src0
;
35906 INSN_CODE (insn
) = -1; /* Force re-recognition. */
35907 df_insn_rescan (insn
);
35910 fprintf (dump_file
, "Reversing inputs for concat %d\n", INSN_UID (insn
));
35913 /* Given an UNSPEC_VPERM insn, modify the mask loaded from the
35914 constant pool to reflect swapped doublewords. */
35916 adjust_vperm (rtx_insn
*insn
)
35918 /* We previously determined that the UNSPEC_VPERM was fed by a
35919 swap of a swapping load of a TOC-relative constant pool symbol.
35920 Find the MEM in the swapping load and replace it with a MEM for
35921 the adjusted mask constant. */
35922 rtx set
= PATTERN (insn
);
35923 rtx mask_reg
= XVECEXP (SET_SRC (set
), 0, 2);
35925 /* Find the swap. */
35926 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
35928 rtx_insn
*swap_insn
= 0;
35929 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
35930 if (rtx_equal_p (DF_REF_REG (use
), mask_reg
))
35932 struct df_link
*def_link
= DF_REF_CHAIN (use
);
35933 gcc_assert (def_link
&& !def_link
->next
);
35934 swap_insn
= DF_REF_INSN (def_link
->ref
);
35937 gcc_assert (swap_insn
);
35939 /* Find the load. */
35940 insn_info
= DF_INSN_INFO_GET (swap_insn
);
35941 rtx_insn
*load_insn
= 0;
35942 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
35944 struct df_link
*def_link
= DF_REF_CHAIN (use
);
35945 gcc_assert (def_link
&& !def_link
->next
);
35946 load_insn
= DF_REF_INSN (def_link
->ref
);
35949 gcc_assert (load_insn
);
35951 /* Find the TOC-relative symbol access. */
35952 insn_info
= DF_INSN_INFO_GET (load_insn
);
35953 rtx_insn
*tocrel_insn
= 0;
35954 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
35956 struct df_link
*def_link
= DF_REF_CHAIN (use
);
35957 gcc_assert (def_link
&& !def_link
->next
);
35958 tocrel_insn
= DF_REF_INSN (def_link
->ref
);
35961 gcc_assert (tocrel_insn
);
35963 /* Find the embedded CONST_VECTOR. We have to call toc_relative_expr_p
35964 to set tocrel_base; otherwise it would be unnecessary as we've
35965 already established it will return true. */
35967 if (!toc_relative_expr_p (SET_SRC (PATTERN (tocrel_insn
)), false))
35968 gcc_unreachable ();
35969 split_const (XVECEXP (tocrel_base
, 0, 0), &base
, &offset
);
35970 rtx const_vector
= get_pool_constant (base
);
35971 gcc_assert (GET_CODE (const_vector
) == CONST_VECTOR
);
35973 /* Create an adjusted mask from the initial mask. */
35974 unsigned int new_mask
[16], i
, val
;
35975 for (i
= 0; i
< 16; ++i
) {
35976 val
= INTVAL (XVECEXP (const_vector
, 0, i
));
35978 new_mask
[i
] = (val
+ 8) % 16;
35980 new_mask
[i
] = ((val
+ 8) % 16) + 16;
35983 /* Create a new CONST_VECTOR and a MEM that references it. */
35984 rtx vals
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
35985 for (i
= 0; i
< 16; ++i
)
35986 XVECEXP (vals
, 0, i
) = GEN_INT (new_mask
[i
]);
35987 rtx new_const_vector
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (vals
, 0));
35988 rtx new_mem
= force_const_mem (V16QImode
, new_const_vector
);
35989 /* This gives us a MEM whose base operand is a SYMBOL_REF, which we
35990 can't recognize. Force the SYMBOL_REF into a register. */
35991 if (!REG_P (XEXP (new_mem
, 0))) {
35992 rtx base_reg
= force_reg (Pmode
, XEXP (new_mem
, 0));
35993 XEXP (new_mem
, 0) = base_reg
;
35994 /* Move the newly created insn ahead of the load insn. */
35995 rtx_insn
*force_insn
= get_last_insn ();
35996 remove_insn (force_insn
);
35997 rtx_insn
*before_load_insn
= PREV_INSN (load_insn
);
35998 add_insn_after (force_insn
, before_load_insn
, BLOCK_FOR_INSN (load_insn
));
35999 df_insn_rescan (before_load_insn
);
36000 df_insn_rescan (force_insn
);
36003 /* Replace the MEM in the load instruction and rescan it. */
36004 XEXP (SET_SRC (PATTERN (load_insn
)), 0) = new_mem
;
36005 INSN_CODE (load_insn
) = -1; /* Force re-recognition. */
36006 df_insn_rescan (load_insn
);
36009 fprintf (dump_file
, "Adjusting mask for vperm %d\n", INSN_UID (insn
));
36012 /* The insn described by INSN_ENTRY[I] can be swapped, but only
36013 with special handling. Take care of that here. */
36015 handle_special_swappables (swap_web_entry
*insn_entry
, unsigned i
)
36017 rtx_insn
*insn
= insn_entry
[i
].insn
;
36018 rtx body
= PATTERN (insn
);
36020 switch (insn_entry
[i
].special_handling
)
36023 gcc_unreachable ();
36024 case SH_CONST_VECTOR
:
36026 /* A CONST_VECTOR will only show up somewhere in the RHS of a SET. */
36027 gcc_assert (GET_CODE (body
) == SET
);
36028 rtx rhs
= SET_SRC (body
);
36029 swap_const_vector_halves (rhs
);
36031 fprintf (dump_file
, "Swapping constant halves in insn %d\n", i
);
36035 /* A subreg of the same size is already safe. For subregs that
36036 select a smaller portion of a reg, adjust the index for
36037 swapped doublewords. */
36038 adjust_subreg_index (body
);
36040 fprintf (dump_file
, "Adjusting subreg in insn %d\n", i
);
36043 /* Convert a non-permuting load to a permuting one. */
36044 permute_load (insn
);
36047 /* Convert a non-permuting store to a permuting one. */
36048 permute_store (insn
);
36051 /* Change the lane on an extract operation. */
36052 adjust_extract (insn
);
36055 /* Change the lane on a direct-splat operation. */
36056 adjust_splat (insn
);
36059 /* Change the lanes on an XXPERMDI operation. */
36060 adjust_xxpermdi (insn
);
36063 /* Reverse the order of a concatenation operation. */
36064 adjust_concat (insn
);
36067 /* Change the mask loaded from the constant pool for a VPERM. */
36068 adjust_vperm (insn
);
36073 /* Find the insn from the Ith table entry, which is known to be a
36074 register swap Y = SWAP(X). Replace it with a copy Y = X. */
36076 replace_swap_with_copy (swap_web_entry
*insn_entry
, unsigned i
)
36078 rtx_insn
*insn
= insn_entry
[i
].insn
;
36079 rtx body
= PATTERN (insn
);
36080 rtx src_reg
= XEXP (SET_SRC (body
), 0);
36081 rtx copy
= gen_rtx_SET (SET_DEST (body
), src_reg
);
36082 rtx_insn
*new_insn
= emit_insn_before (copy
, insn
);
36083 set_block_for_insn (new_insn
, BLOCK_FOR_INSN (insn
));
36084 df_insn_rescan (new_insn
);
36088 unsigned int new_uid
= INSN_UID (new_insn
);
36089 fprintf (dump_file
, "Replacing swap %d with copy %d\n", i
, new_uid
);
36092 df_insn_delete (insn
);
36093 remove_insn (insn
);
36094 insn
->set_deleted ();
36097 /* Dump the swap table to DUMP_FILE. */
36099 dump_swap_insn_table (swap_web_entry
*insn_entry
)
36101 int e
= get_max_uid ();
36102 fprintf (dump_file
, "\nRelevant insns with their flag settings\n\n");
36104 for (int i
= 0; i
< e
; ++i
)
36105 if (insn_entry
[i
].is_relevant
)
36107 swap_web_entry
*pred_entry
= (swap_web_entry
*)insn_entry
[i
].pred ();
36108 fprintf (dump_file
, "%6d %6d ", i
,
36109 pred_entry
&& pred_entry
->insn
36110 ? INSN_UID (pred_entry
->insn
) : 0);
36111 if (insn_entry
[i
].is_load
)
36112 fputs ("load ", dump_file
);
36113 if (insn_entry
[i
].is_store
)
36114 fputs ("store ", dump_file
);
36115 if (insn_entry
[i
].is_swap
)
36116 fputs ("swap ", dump_file
);
36117 if (insn_entry
[i
].is_live_in
)
36118 fputs ("live-in ", dump_file
);
36119 if (insn_entry
[i
].is_live_out
)
36120 fputs ("live-out ", dump_file
);
36121 if (insn_entry
[i
].contains_subreg
)
36122 fputs ("subreg ", dump_file
);
36123 if (insn_entry
[i
].is_128_int
)
36124 fputs ("int128 ", dump_file
);
36125 if (insn_entry
[i
].is_call
)
36126 fputs ("call ", dump_file
);
36127 if (insn_entry
[i
].is_swappable
)
36129 fputs ("swappable ", dump_file
);
36130 if (insn_entry
[i
].special_handling
== SH_CONST_VECTOR
)
36131 fputs ("special:constvec ", dump_file
);
36132 else if (insn_entry
[i
].special_handling
== SH_SUBREG
)
36133 fputs ("special:subreg ", dump_file
);
36134 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_LD
)
36135 fputs ("special:load ", dump_file
);
36136 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_ST
)
36137 fputs ("special:store ", dump_file
);
36138 else if (insn_entry
[i
].special_handling
== SH_EXTRACT
)
36139 fputs ("special:extract ", dump_file
);
36140 else if (insn_entry
[i
].special_handling
== SH_SPLAT
)
36141 fputs ("special:splat ", dump_file
);
36142 else if (insn_entry
[i
].special_handling
== SH_XXPERMDI
)
36143 fputs ("special:xxpermdi ", dump_file
);
36144 else if (insn_entry
[i
].special_handling
== SH_CONCAT
)
36145 fputs ("special:concat ", dump_file
);
36146 else if (insn_entry
[i
].special_handling
== SH_VPERM
)
36147 fputs ("special:vperm ", dump_file
);
36149 if (insn_entry
[i
].web_not_optimizable
)
36150 fputs ("unoptimizable ", dump_file
);
36151 if (insn_entry
[i
].will_delete
)
36152 fputs ("delete ", dump_file
);
36153 fputs ("\n", dump_file
);
36155 fputs ("\n", dump_file
);
36158 /* Main entry point for this pass. */
36160 rs6000_analyze_swaps (function
*fun
)
36162 swap_web_entry
*insn_entry
;
36166 /* Dataflow analysis for use-def chains. */
36167 df_set_flags (DF_RD_PRUNE_DEAD_DEFS
);
36168 df_chain_add_problem (DF_DU_CHAIN
| DF_UD_CHAIN
);
36170 df_set_flags (DF_DEFER_INSN_RESCAN
);
36172 /* Allocate structure to represent webs of insns. */
36173 insn_entry
= XCNEWVEC (swap_web_entry
, get_max_uid ());
36175 /* Walk the insns to gather basic data. */
36176 FOR_ALL_BB_FN (bb
, fun
)
36177 FOR_BB_INSNS (bb
, insn
)
36179 unsigned int uid
= INSN_UID (insn
);
36180 if (NONDEBUG_INSN_P (insn
))
36182 insn_entry
[uid
].insn
= insn
;
36184 if (GET_CODE (insn
) == CALL_INSN
)
36185 insn_entry
[uid
].is_call
= 1;
36187 /* Walk the uses and defs to see if we mention vector regs.
36188 Record any constraints on optimization of such mentions. */
36189 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
36191 FOR_EACH_INSN_INFO_USE (mention
, insn_info
)
36193 /* We use DF_REF_REAL_REG here to get inside any subregs. */
36194 machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
36196 /* If a use gets its value from a call insn, it will be
36197 a hard register and will look like (reg:V4SI 3 3).
36198 The df analysis creates two mentions for GPR3 and GPR4,
36199 both DImode. We must recognize this and treat it as a
36200 vector mention to ensure the call is unioned with this
36202 if (mode
== DImode
&& DF_REF_INSN_INFO (mention
))
36204 rtx feeder
= DF_REF_INSN (mention
);
36205 /* FIXME: It is pretty hard to get from the df mention
36206 to the mode of the use in the insn. We arbitrarily
36207 pick a vector mode here, even though the use might
36208 be a real DImode. We can be too conservative
36209 (create a web larger than necessary) because of
36210 this, so consider eventually fixing this. */
36211 if (GET_CODE (feeder
) == CALL_INSN
)
36215 if (VECTOR_MODE_P (mode
) || mode
== TImode
)
36217 insn_entry
[uid
].is_relevant
= 1;
36218 if (mode
== TImode
|| mode
== V1TImode
)
36219 insn_entry
[uid
].is_128_int
= 1;
36220 if (DF_REF_INSN_INFO (mention
))
36221 insn_entry
[uid
].contains_subreg
36222 = !rtx_equal_p (DF_REF_REG (mention
),
36223 DF_REF_REAL_REG (mention
));
36224 union_defs (insn_entry
, insn
, mention
);
36227 FOR_EACH_INSN_INFO_DEF (mention
, insn_info
)
36229 /* We use DF_REF_REAL_REG here to get inside any subregs. */
36230 machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
36232 /* If we're loading up a hard vector register for a call,
36233 it looks like (set (reg:V4SI 9 9) (...)). The df
36234 analysis creates two mentions for GPR9 and GPR10, both
36235 DImode. So relying on the mode from the mentions
36236 isn't sufficient to ensure we union the call into the
36237 web with the parameter setup code. */
36238 if (mode
== DImode
&& GET_CODE (insn
) == SET
36239 && VECTOR_MODE_P (GET_MODE (SET_DEST (insn
))))
36240 mode
= GET_MODE (SET_DEST (insn
));
36242 if (VECTOR_MODE_P (mode
) || mode
== TImode
)
36244 insn_entry
[uid
].is_relevant
= 1;
36245 if (mode
== TImode
|| mode
== V1TImode
)
36246 insn_entry
[uid
].is_128_int
= 1;
36247 if (DF_REF_INSN_INFO (mention
))
36248 insn_entry
[uid
].contains_subreg
36249 = !rtx_equal_p (DF_REF_REG (mention
),
36250 DF_REF_REAL_REG (mention
));
36251 /* REG_FUNCTION_VALUE_P is not valid for subregs. */
36252 else if (REG_FUNCTION_VALUE_P (DF_REF_REG (mention
)))
36253 insn_entry
[uid
].is_live_out
= 1;
36254 union_uses (insn_entry
, insn
, mention
);
36258 if (insn_entry
[uid
].is_relevant
)
36260 /* Determine if this is a load or store. */
36261 insn_entry
[uid
].is_load
= insn_is_load_p (insn
);
36262 insn_entry
[uid
].is_store
= insn_is_store_p (insn
);
36264 /* Determine if this is a doubleword swap. If not,
36265 determine whether it can legally be swapped. */
36266 if (insn_is_swap_p (insn
))
36267 insn_entry
[uid
].is_swap
= 1;
36270 unsigned int special
= SH_NONE
;
36271 insn_entry
[uid
].is_swappable
36272 = insn_is_swappable_p (insn_entry
, insn
, &special
);
36273 if (special
!= SH_NONE
&& insn_entry
[uid
].contains_subreg
)
36274 insn_entry
[uid
].is_swappable
= 0;
36275 else if (special
!= SH_NONE
)
36276 insn_entry
[uid
].special_handling
= special
;
36277 else if (insn_entry
[uid
].contains_subreg
)
36278 insn_entry
[uid
].special_handling
= SH_SUBREG
;
36286 fprintf (dump_file
, "\nSwap insn entry table when first built\n");
36287 dump_swap_insn_table (insn_entry
);
36290 /* Record unoptimizable webs. */
36291 unsigned e
= get_max_uid (), i
;
36292 for (i
= 0; i
< e
; ++i
)
36294 if (!insn_entry
[i
].is_relevant
)
36297 swap_web_entry
*root
36298 = (swap_web_entry
*)(&insn_entry
[i
])->unionfind_root ();
36300 if (insn_entry
[i
].is_live_in
|| insn_entry
[i
].is_live_out
36301 || (insn_entry
[i
].contains_subreg
36302 && insn_entry
[i
].special_handling
!= SH_SUBREG
)
36303 || insn_entry
[i
].is_128_int
|| insn_entry
[i
].is_call
36304 || !(insn_entry
[i
].is_swappable
|| insn_entry
[i
].is_swap
))
36305 root
->web_not_optimizable
= 1;
36307 /* If we have loads or stores that aren't permuting then the
36308 optimization isn't appropriate. */
36309 else if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
36310 && !insn_entry
[i
].is_swap
&& !insn_entry
[i
].is_swappable
)
36311 root
->web_not_optimizable
= 1;
36313 /* If we have permuting loads or stores that are not accompanied
36314 by a register swap, the optimization isn't appropriate. */
36315 else if (insn_entry
[i
].is_load
&& insn_entry
[i
].is_swap
)
36317 rtx insn
= insn_entry
[i
].insn
;
36318 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
36321 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
36323 struct df_link
*link
= DF_REF_CHAIN (def
);
36325 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_LOADS
))
36327 root
->web_not_optimizable
= 1;
36332 else if (insn_entry
[i
].is_store
&& insn_entry
[i
].is_swap
)
36334 rtx insn
= insn_entry
[i
].insn
;
36335 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
36338 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
36340 struct df_link
*link
= DF_REF_CHAIN (use
);
36342 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_STORES
))
36344 root
->web_not_optimizable
= 1;
36353 fprintf (dump_file
, "\nSwap insn entry table after web analysis\n");
36354 dump_swap_insn_table (insn_entry
);
36357 /* For each load and store in an optimizable web (which implies
36358 the loads and stores are permuting), find the associated
36359 register swaps and mark them for removal. Due to various
36360 optimizations we may mark the same swap more than once. Also
36361 perform special handling for swappable insns that require it. */
36362 for (i
= 0; i
< e
; ++i
)
36363 if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
36364 && insn_entry
[i
].is_swap
)
36366 swap_web_entry
* root_entry
36367 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
36368 if (!root_entry
->web_not_optimizable
)
36369 mark_swaps_for_removal (insn_entry
, i
);
36371 else if (insn_entry
[i
].is_swappable
&& insn_entry
[i
].special_handling
)
36373 swap_web_entry
* root_entry
36374 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
36375 if (!root_entry
->web_not_optimizable
)
36376 handle_special_swappables (insn_entry
, i
);
36379 /* Now delete the swaps marked for removal. */
36380 for (i
= 0; i
< e
; ++i
)
36381 if (insn_entry
[i
].will_delete
)
36382 replace_swap_with_copy (insn_entry
, i
);
36389 const pass_data pass_data_analyze_swaps
=
36391 RTL_PASS
, /* type */
36392 "swaps", /* name */
36393 OPTGROUP_NONE
, /* optinfo_flags */
36394 TV_NONE
, /* tv_id */
36395 0, /* properties_required */
36396 0, /* properties_provided */
36397 0, /* properties_destroyed */
36398 0, /* todo_flags_start */
36399 TODO_df_finish
, /* todo_flags_finish */
36402 class pass_analyze_swaps
: public rtl_opt_pass
36405 pass_analyze_swaps(gcc::context
*ctxt
)
36406 : rtl_opt_pass(pass_data_analyze_swaps
, ctxt
)
36409 /* opt_pass methods: */
36410 virtual bool gate (function
*)
36412 return (optimize
> 0 && !BYTES_BIG_ENDIAN
&& TARGET_VSX
36413 && rs6000_optimize_swaps
);
36416 virtual unsigned int execute (function
*fun
)
36418 return rs6000_analyze_swaps (fun
);
36421 }; // class pass_analyze_swaps
36424 make_pass_analyze_swaps (gcc::context
*ctxt
)
36426 return new pass_analyze_swaps (ctxt
);
36429 #ifdef RS6000_GLIBC_ATOMIC_FENV
36430 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
36431 static tree atomic_hold_decl
, atomic_clear_decl
, atomic_update_decl
;
36434 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
36437 rs6000_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
36439 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
)
36441 #ifdef RS6000_GLIBC_ATOMIC_FENV
36442 if (atomic_hold_decl
== NULL_TREE
)
36445 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
36446 get_identifier ("__atomic_feholdexcept"),
36447 build_function_type_list (void_type_node
,
36448 double_ptr_type_node
,
36450 TREE_PUBLIC (atomic_hold_decl
) = 1;
36451 DECL_EXTERNAL (atomic_hold_decl
) = 1;
36454 if (atomic_clear_decl
== NULL_TREE
)
36457 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
36458 get_identifier ("__atomic_feclearexcept"),
36459 build_function_type_list (void_type_node
,
36461 TREE_PUBLIC (atomic_clear_decl
) = 1;
36462 DECL_EXTERNAL (atomic_clear_decl
) = 1;
36465 tree const_double
= build_qualified_type (double_type_node
,
36467 tree const_double_ptr
= build_pointer_type (const_double
);
36468 if (atomic_update_decl
== NULL_TREE
)
36471 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
36472 get_identifier ("__atomic_feupdateenv"),
36473 build_function_type_list (void_type_node
,
36476 TREE_PUBLIC (atomic_update_decl
) = 1;
36477 DECL_EXTERNAL (atomic_update_decl
) = 1;
36480 tree fenv_var
= create_tmp_var (double_type_node
);
36481 mark_addressable (fenv_var
);
36482 tree fenv_addr
= build1 (ADDR_EXPR
, double_ptr_type_node
, fenv_var
);
36484 *hold
= build_call_expr (atomic_hold_decl
, 1, fenv_addr
);
36485 *clear
= build_call_expr (atomic_clear_decl
, 0);
36486 *update
= build_call_expr (atomic_update_decl
, 1,
36487 fold_convert (const_double_ptr
, fenv_addr
));
36492 tree mffs
= rs6000_builtin_decls
[RS6000_BUILTIN_MFFS
];
36493 tree mtfsf
= rs6000_builtin_decls
[RS6000_BUILTIN_MTFSF
];
36494 tree call_mffs
= build_call_expr (mffs
, 0);
36496 /* Generates the equivalent of feholdexcept (&fenv_var)
36498 *fenv_var = __builtin_mffs ();
36500 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
36501 __builtin_mtfsf (0xff, fenv_hold); */
36503 /* Mask to clear everything except for the rounding modes and non-IEEE
36504 arithmetic flag. */
36505 const unsigned HOST_WIDE_INT hold_exception_mask
=
36506 HOST_WIDE_INT_C (0xffffffff00000007);
36508 tree fenv_var
= create_tmp_var (double_type_node
);
36510 tree hold_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_var
, call_mffs
);
36512 tree fenv_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_var
);
36513 tree fenv_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
36514 build_int_cst (uint64_type_node
,
36515 hold_exception_mask
));
36517 tree fenv_hold_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
36520 tree hold_mtfsf
= build_call_expr (mtfsf
, 2,
36521 build_int_cst (unsigned_type_node
, 0xff),
36524 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_mffs
, hold_mtfsf
);
36526 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
36528 double fenv_clear = __builtin_mffs ();
36529 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
36530 __builtin_mtfsf (0xff, fenv_clear); */
36532 /* Mask to clear everything except for the rounding modes and non-IEEE
36533 arithmetic flag. */
36534 const unsigned HOST_WIDE_INT clear_exception_mask
=
36535 HOST_WIDE_INT_C (0xffffffff00000000);
36537 tree fenv_clear
= create_tmp_var (double_type_node
);
36539 tree clear_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_clear
, call_mffs
);
36541 tree fenv_clean_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_clear
);
36542 tree fenv_clear_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
,
36544 build_int_cst (uint64_type_node
,
36545 clear_exception_mask
));
36547 tree fenv_clear_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
36548 fenv_clear_llu_and
);
36550 tree clear_mtfsf
= build_call_expr (mtfsf
, 2,
36551 build_int_cst (unsigned_type_node
, 0xff),
36554 *clear
= build2 (COMPOUND_EXPR
, void_type_node
, clear_mffs
, clear_mtfsf
);
36556 /* Generates the equivalent of feupdateenv (&fenv_var)
36558 double old_fenv = __builtin_mffs ();
36559 double fenv_update;
36560 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
36561 (*(uint64_t*)fenv_var 0x1ff80fff);
36562 __builtin_mtfsf (0xff, fenv_update); */
36564 const unsigned HOST_WIDE_INT update_exception_mask
=
36565 HOST_WIDE_INT_C (0xffffffff1fffff00);
36566 const unsigned HOST_WIDE_INT new_exception_mask
=
36567 HOST_WIDE_INT_C (0x1ff80fff);
36569 tree old_fenv
= create_tmp_var (double_type_node
);
36570 tree update_mffs
= build2 (MODIFY_EXPR
, void_type_node
, old_fenv
, call_mffs
);
36572 tree old_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, old_fenv
);
36573 tree old_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, old_llu
,
36574 build_int_cst (uint64_type_node
,
36575 update_exception_mask
));
36577 tree new_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
36578 build_int_cst (uint64_type_node
,
36579 new_exception_mask
));
36581 tree new_llu_mask
= build2 (BIT_IOR_EXPR
, uint64_type_node
,
36582 old_llu_and
, new_llu_and
);
36584 tree fenv_update_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
36587 tree update_mtfsf
= build_call_expr (mtfsf
, 2,
36588 build_int_cst (unsigned_type_node
, 0xff),
36589 fenv_update_mtfsf
);
36591 *update
= build2 (COMPOUND_EXPR
, void_type_node
, update_mffs
, update_mtfsf
);
36595 struct gcc_target targetm
= TARGET_INITIALIZER
;
36597 #include "gt-rs6000.h"