2015-09-03 Richard Biener <rguenther@suse.de>
[official-gcc.git] / gcc / mode-switching.c
blob4529bc29fa266842961e7e4d4138b9d2f020e97d
1 /* CPU mode switching
2 Copyright (C) 1998-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "backend.h"
24 #include "cfghooks.h"
25 #include "rtl.h"
26 #include "df.h"
27 #include "target.h"
28 #include "regs.h"
29 #include "flags.h"
30 #include "insn-config.h"
31 #include "recog.h"
32 #include "cfgrtl.h"
33 #include "cfganal.h"
34 #include "lcm.h"
35 #include "cfgcleanup.h"
36 #include "tm_p.h"
37 #include "tree-pass.h"
38 #include "emit-rtl.h"
40 /* We want target macros for the mode switching code to be able to refer
41 to instruction attribute values. */
42 #include "insn-attr.h"
44 #ifdef OPTIMIZE_MODE_SWITCHING
46 /* The algorithm for setting the modes consists of scanning the insn list
47 and finding all the insns which require a specific mode. Each insn gets
48 a unique struct seginfo element. These structures are inserted into a list
49 for each basic block. For each entity, there is an array of bb_info over
50 the flow graph basic blocks (local var 'bb_info'), which contains a list
51 of all insns within that basic block, in the order they are encountered.
53 For each entity, any basic block WITHOUT any insns requiring a specific
54 mode are given a single entry without a mode (each basic block in the
55 flow graph must have at least one entry in the segment table).
57 The LCM algorithm is then run over the flow graph to determine where to
58 place the sets to the highest-priority mode with respect to the first
59 insn in any one block. Any adjustments required to the transparency
60 vectors are made, then the next iteration starts for the next-lower
61 priority mode, till for each entity all modes are exhausted.
63 More details can be found in the code of optimize_mode_switching. */
65 /* This structure contains the information for each insn which requires
66 either single or double mode to be set.
67 MODE is the mode this insn must be executed in.
68 INSN_PTR is the insn to be executed (may be the note that marks the
69 beginning of a basic block).
70 BBNUM is the flow graph basic block this insn occurs in.
71 NEXT is the next insn in the same basic block. */
72 struct seginfo
74 int mode;
75 rtx_insn *insn_ptr;
76 int bbnum;
77 struct seginfo *next;
78 HARD_REG_SET regs_live;
81 struct bb_info
83 struct seginfo *seginfo;
84 int computing;
85 int mode_out;
86 int mode_in;
89 static struct seginfo * new_seginfo (int, rtx_insn *, int, HARD_REG_SET);
90 static void add_seginfo (struct bb_info *, struct seginfo *);
91 static void reg_dies (rtx, HARD_REG_SET *);
92 static void reg_becomes_live (rtx, const_rtx, void *);
94 /* Clear ode I from entity J in bitmap B. */
95 #define clear_mode_bit(b, j, i) \
96 bitmap_clear_bit (b, (j * max_num_modes) + i)
98 /* Test mode I from entity J in bitmap B. */
99 #define mode_bit_p(b, j, i) \
100 bitmap_bit_p (b, (j * max_num_modes) + i)
102 /* Set mode I from entity J in bitmal B. */
103 #define set_mode_bit(b, j, i) \
104 bitmap_set_bit (b, (j * max_num_modes) + i)
106 /* Emit modes segments from EDGE_LIST associated with entity E.
107 INFO gives mode availability for each mode. */
109 static bool
110 commit_mode_sets (struct edge_list *edge_list, int e, struct bb_info *info)
112 bool need_commit = false;
114 for (int ed = NUM_EDGES (edge_list) - 1; ed >= 0; ed--)
116 edge eg = INDEX_EDGE (edge_list, ed);
117 int mode;
119 if ((mode = (int)(intptr_t)(eg->aux)) != -1)
121 HARD_REG_SET live_at_edge;
122 basic_block src_bb = eg->src;
123 int cur_mode = info[src_bb->index].mode_out;
124 rtx_insn *mode_set;
126 REG_SET_TO_HARD_REG_SET (live_at_edge, df_get_live_out (src_bb));
128 rtl_profile_for_edge (eg);
129 start_sequence ();
131 targetm.mode_switching.emit (e, mode, cur_mode, live_at_edge);
133 mode_set = get_insns ();
134 end_sequence ();
135 default_rtl_profile ();
137 /* Do not bother to insert empty sequence. */
138 if (mode_set == NULL)
139 continue;
141 /* We should not get an abnormal edge here. */
142 gcc_assert (! (eg->flags & EDGE_ABNORMAL));
144 need_commit = true;
145 insert_insn_on_edge (mode_set, eg);
149 return need_commit;
152 /* Allocate a new BBINFO structure, initialized with the MODE, INSN,
153 and basic block BB parameters.
154 INSN may not be a NOTE_INSN_BASIC_BLOCK, unless it is an empty
155 basic block; that allows us later to insert instructions in a FIFO-like
156 manner. */
158 static struct seginfo *
159 new_seginfo (int mode, rtx_insn *insn, int bb, HARD_REG_SET regs_live)
161 struct seginfo *ptr;
163 gcc_assert (!NOTE_INSN_BASIC_BLOCK_P (insn)
164 || insn == BB_END (NOTE_BASIC_BLOCK (insn)));
165 ptr = XNEW (struct seginfo);
166 ptr->mode = mode;
167 ptr->insn_ptr = insn;
168 ptr->bbnum = bb;
169 ptr->next = NULL;
170 COPY_HARD_REG_SET (ptr->regs_live, regs_live);
171 return ptr;
174 /* Add a seginfo element to the end of a list.
175 HEAD is a pointer to the list beginning.
176 INFO is the structure to be linked in. */
178 static void
179 add_seginfo (struct bb_info *head, struct seginfo *info)
181 struct seginfo *ptr;
183 if (head->seginfo == NULL)
184 head->seginfo = info;
185 else
187 ptr = head->seginfo;
188 while (ptr->next != NULL)
189 ptr = ptr->next;
190 ptr->next = info;
194 /* Record in LIVE that register REG died. */
196 static void
197 reg_dies (rtx reg, HARD_REG_SET *live)
199 int regno;
201 if (!REG_P (reg))
202 return;
204 regno = REGNO (reg);
205 if (regno < FIRST_PSEUDO_REGISTER)
206 remove_from_hard_reg_set (live, GET_MODE (reg), regno);
209 /* Record in LIVE that register REG became live.
210 This is called via note_stores. */
212 static void
213 reg_becomes_live (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *live)
215 int regno;
217 if (GET_CODE (reg) == SUBREG)
218 reg = SUBREG_REG (reg);
220 if (!REG_P (reg))
221 return;
223 regno = REGNO (reg);
224 if (regno < FIRST_PSEUDO_REGISTER)
225 add_to_hard_reg_set ((HARD_REG_SET *) live, GET_MODE (reg), regno);
228 /* Split the fallthrough edge to the exit block, so that we can note
229 that there NORMAL_MODE is required. Return the new block if it's
230 inserted before the exit block. Otherwise return null. */
232 static basic_block
233 create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
235 edge eg;
236 edge_iterator ei;
237 basic_block pre_exit;
239 /* The only non-call predecessor at this stage is a block with a
240 fallthrough edge; there can be at most one, but there could be
241 none at all, e.g. when exit is called. */
242 pre_exit = 0;
243 FOR_EACH_EDGE (eg, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds)
244 if (eg->flags & EDGE_FALLTHRU)
246 basic_block src_bb = eg->src;
247 rtx_insn *last_insn;
248 rtx ret_reg;
250 gcc_assert (!pre_exit);
251 /* If this function returns a value at the end, we have to
252 insert the final mode switch before the return value copy
253 to its hard register. */
254 if (EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1
255 && NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))
256 && GET_CODE (PATTERN (last_insn)) == USE
257 && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)
259 int ret_start = REGNO (ret_reg);
260 int nregs = REG_NREGS (ret_reg);
261 int ret_end = ret_start + nregs;
262 bool short_block = false;
263 bool multi_reg_return = false;
264 bool forced_late_switch = false;
265 rtx_insn *before_return_copy;
269 rtx_insn *return_copy = PREV_INSN (last_insn);
270 rtx return_copy_pat, copy_reg;
271 int copy_start, copy_num;
272 int j;
274 if (NONDEBUG_INSN_P (return_copy))
276 /* When using SJLJ exceptions, the call to the
277 unregister function is inserted between the
278 clobber of the return value and the copy.
279 We do not want to split the block before this
280 or any other call; if we have not found the
281 copy yet, the copy must have been deleted. */
282 if (CALL_P (return_copy))
284 short_block = true;
285 break;
287 return_copy_pat = PATTERN (return_copy);
288 switch (GET_CODE (return_copy_pat))
290 case USE:
291 /* Skip USEs of multiple return registers.
292 __builtin_apply pattern is also handled here. */
293 if (GET_CODE (XEXP (return_copy_pat, 0)) == REG
294 && (targetm.calls.function_value_regno_p
295 (REGNO (XEXP (return_copy_pat, 0)))))
297 multi_reg_return = true;
298 last_insn = return_copy;
299 continue;
301 break;
303 case ASM_OPERANDS:
304 /* Skip barrier insns. */
305 if (!MEM_VOLATILE_P (return_copy_pat))
306 break;
308 /* Fall through. */
310 case ASM_INPUT:
311 case UNSPEC_VOLATILE:
312 last_insn = return_copy;
313 continue;
315 default:
316 break;
319 /* If the return register is not (in its entirety)
320 likely spilled, the return copy might be
321 partially or completely optimized away. */
322 return_copy_pat = single_set (return_copy);
323 if (!return_copy_pat)
325 return_copy_pat = PATTERN (return_copy);
326 if (GET_CODE (return_copy_pat) != CLOBBER)
327 break;
328 else if (!optimize)
330 /* This might be (clobber (reg [<result>]))
331 when not optimizing. Then check if
332 the previous insn is the clobber for
333 the return register. */
334 copy_reg = SET_DEST (return_copy_pat);
335 if (GET_CODE (copy_reg) == REG
336 && !HARD_REGISTER_NUM_P (REGNO (copy_reg)))
338 if (INSN_P (PREV_INSN (return_copy)))
340 return_copy = PREV_INSN (return_copy);
341 return_copy_pat = PATTERN (return_copy);
342 if (GET_CODE (return_copy_pat) != CLOBBER)
343 break;
348 copy_reg = SET_DEST (return_copy_pat);
349 if (GET_CODE (copy_reg) == REG)
350 copy_start = REGNO (copy_reg);
351 else if (GET_CODE (copy_reg) == SUBREG
352 && GET_CODE (SUBREG_REG (copy_reg)) == REG)
353 copy_start = REGNO (SUBREG_REG (copy_reg));
354 else
356 /* When control reaches end of non-void function,
357 there are no return copy insns at all. This
358 avoids an ice on that invalid function. */
359 if (ret_start + nregs == ret_end)
360 short_block = true;
361 break;
363 if (!targetm.calls.function_value_regno_p (copy_start))
364 copy_num = 0;
365 else
366 copy_num
367 = hard_regno_nregs[copy_start][GET_MODE (copy_reg)];
369 /* If the return register is not likely spilled, - as is
370 the case for floating point on SH4 - then it might
371 be set by an arithmetic operation that needs a
372 different mode than the exit block. */
373 for (j = n_entities - 1; j >= 0; j--)
375 int e = entity_map[j];
376 int mode =
377 targetm.mode_switching.needed (e, return_copy);
379 if (mode != num_modes[e]
380 && mode != targetm.mode_switching.exit (e))
381 break;
383 if (j >= 0)
385 /* __builtin_return emits a sequence of loads to all
386 return registers. One of them might require
387 another mode than MODE_EXIT, even if it is
388 unrelated to the return value, so we want to put
389 the final mode switch after it. */
390 if (multi_reg_return
391 && targetm.calls.function_value_regno_p
392 (copy_start))
393 forced_late_switch = true;
395 /* For the SH4, floating point loads depend on fpscr,
396 thus we might need to put the final mode switch
397 after the return value copy. That is still OK,
398 because a floating point return value does not
399 conflict with address reloads. */
400 if (copy_start >= ret_start
401 && copy_start + copy_num <= ret_end
402 && OBJECT_P (SET_SRC (return_copy_pat)))
403 forced_late_switch = true;
404 break;
406 if (copy_num == 0)
408 last_insn = return_copy;
409 continue;
412 if (copy_start >= ret_start
413 && copy_start + copy_num <= ret_end)
414 nregs -= copy_num;
415 else if (!multi_reg_return
416 || !targetm.calls.function_value_regno_p
417 (copy_start))
418 break;
419 last_insn = return_copy;
421 /* ??? Exception handling can lead to the return value
422 copy being already separated from the return value use,
423 as in unwind-dw2.c .
424 Similarly, conditionally returning without a value,
425 and conditionally using builtin_return can lead to an
426 isolated use. */
427 if (return_copy == BB_HEAD (src_bb))
429 short_block = true;
430 break;
432 last_insn = return_copy;
434 while (nregs);
436 /* If we didn't see a full return value copy, verify that there
437 is a plausible reason for this. If some, but not all of the
438 return register is likely spilled, we can expect that there
439 is a copy for the likely spilled part. */
440 gcc_assert (!nregs
441 || forced_late_switch
442 || short_block
443 || !(targetm.class_likely_spilled_p
444 (REGNO_REG_CLASS (ret_start)))
445 || (nregs
446 != hard_regno_nregs[ret_start][GET_MODE (ret_reg)])
447 /* For multi-hard-register floating point
448 values, sometimes the likely-spilled part
449 is ordinarily copied first, then the other
450 part is set with an arithmetic operation.
451 This doesn't actually cause reload
452 failures, so let it pass. */
453 || (GET_MODE_CLASS (GET_MODE (ret_reg)) != MODE_INT
454 && nregs != 1));
456 if (!NOTE_INSN_BASIC_BLOCK_P (last_insn))
458 before_return_copy
459 = emit_note_before (NOTE_INSN_DELETED, last_insn);
460 /* Instructions preceding LAST_INSN in the same block might
461 require a different mode than MODE_EXIT, so if we might
462 have such instructions, keep them in a separate block
463 from pre_exit. */
464 src_bb = split_block (src_bb,
465 PREV_INSN (before_return_copy))->dest;
467 else
468 before_return_copy = last_insn;
469 pre_exit = split_block (src_bb, before_return_copy)->src;
471 else
473 pre_exit = split_edge (eg);
477 return pre_exit;
480 /* Find all insns that need a particular mode setting, and insert the
481 necessary mode switches. Return true if we did work. */
483 static int
484 optimize_mode_switching (void)
486 int e;
487 basic_block bb;
488 bool need_commit = false;
489 static const int num_modes[] = NUM_MODES_FOR_MODE_SWITCHING;
490 #define N_ENTITIES ARRAY_SIZE (num_modes)
491 int entity_map[N_ENTITIES];
492 struct bb_info *bb_info[N_ENTITIES];
493 int i, j;
494 int n_entities = 0;
495 int max_num_modes = 0;
496 bool emitted ATTRIBUTE_UNUSED = false;
497 basic_block post_entry = 0;
498 basic_block pre_exit = 0;
499 struct edge_list *edge_list = 0;
501 /* These bitmaps are used for the LCM algorithm. */
502 sbitmap *kill, *del, *insert, *antic, *transp, *comp;
503 sbitmap *avin, *avout;
505 for (e = N_ENTITIES - 1; e >= 0; e--)
506 if (OPTIMIZE_MODE_SWITCHING (e))
508 int entry_exit_extra = 0;
510 /* Create the list of segments within each basic block.
511 If NORMAL_MODE is defined, allow for two extra
512 blocks split from the entry and exit block. */
513 if (targetm.mode_switching.entry && targetm.mode_switching.exit)
514 entry_exit_extra = 3;
516 bb_info[n_entities]
517 = XCNEWVEC (struct bb_info,
518 last_basic_block_for_fn (cfun) + entry_exit_extra);
519 entity_map[n_entities++] = e;
520 if (num_modes[e] > max_num_modes)
521 max_num_modes = num_modes[e];
524 if (! n_entities)
525 return 0;
527 /* Make sure if MODE_ENTRY is defined MODE_EXIT is defined. */
528 gcc_assert ((targetm.mode_switching.entry && targetm.mode_switching.exit)
529 || (!targetm.mode_switching.entry
530 && !targetm.mode_switching.exit));
532 if (targetm.mode_switching.entry && targetm.mode_switching.exit)
534 /* Split the edge from the entry block, so that we can note that
535 there NORMAL_MODE is supplied. */
536 post_entry = split_edge (single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun)));
537 pre_exit = create_pre_exit (n_entities, entity_map, num_modes);
540 df_analyze ();
542 /* Create the bitmap vectors. */
543 antic = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
544 n_entities * max_num_modes);
545 transp = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
546 n_entities * max_num_modes);
547 comp = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
548 n_entities * max_num_modes);
549 avin = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
550 n_entities * max_num_modes);
551 avout = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
552 n_entities * max_num_modes);
553 kill = sbitmap_vector_alloc (last_basic_block_for_fn (cfun),
554 n_entities * max_num_modes);
556 bitmap_vector_ones (transp, last_basic_block_for_fn (cfun));
557 bitmap_vector_clear (antic, last_basic_block_for_fn (cfun));
558 bitmap_vector_clear (comp, last_basic_block_for_fn (cfun));
560 for (j = n_entities - 1; j >= 0; j--)
562 int e = entity_map[j];
563 int no_mode = num_modes[e];
564 struct bb_info *info = bb_info[j];
565 rtx_insn *insn;
567 /* Determine what the first use (if any) need for a mode of entity E is.
568 This will be the mode that is anticipatable for this block.
569 Also compute the initial transparency settings. */
570 FOR_EACH_BB_FN (bb, cfun)
572 struct seginfo *ptr;
573 int last_mode = no_mode;
574 bool any_set_required = false;
575 HARD_REG_SET live_now;
577 info[bb->index].mode_out = info[bb->index].mode_in = no_mode;
579 REG_SET_TO_HARD_REG_SET (live_now, df_get_live_in (bb));
581 /* Pretend the mode is clobbered across abnormal edges. */
583 edge_iterator ei;
584 edge eg;
585 FOR_EACH_EDGE (eg, ei, bb->preds)
586 if (eg->flags & EDGE_COMPLEX)
587 break;
588 if (eg)
590 rtx_insn *ins_pos = BB_HEAD (bb);
591 if (LABEL_P (ins_pos))
592 ins_pos = NEXT_INSN (ins_pos);
593 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (ins_pos));
594 if (ins_pos != BB_END (bb))
595 ins_pos = NEXT_INSN (ins_pos);
596 ptr = new_seginfo (no_mode, ins_pos, bb->index, live_now);
597 add_seginfo (info + bb->index, ptr);
598 for (i = 0; i < no_mode; i++)
599 clear_mode_bit (transp[bb->index], j, i);
603 FOR_BB_INSNS (bb, insn)
605 if (INSN_P (insn))
607 int mode = targetm.mode_switching.needed (e, insn);
608 rtx link;
610 if (mode != no_mode && mode != last_mode)
612 any_set_required = true;
613 last_mode = mode;
614 ptr = new_seginfo (mode, insn, bb->index, live_now);
615 add_seginfo (info + bb->index, ptr);
616 for (i = 0; i < no_mode; i++)
617 clear_mode_bit (transp[bb->index], j, i);
620 if (targetm.mode_switching.after)
621 last_mode = targetm.mode_switching.after (e, last_mode,
622 insn);
624 /* Update LIVE_NOW. */
625 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
626 if (REG_NOTE_KIND (link) == REG_DEAD)
627 reg_dies (XEXP (link, 0), &live_now);
629 note_stores (PATTERN (insn), reg_becomes_live, &live_now);
630 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
631 if (REG_NOTE_KIND (link) == REG_UNUSED)
632 reg_dies (XEXP (link, 0), &live_now);
636 info[bb->index].computing = last_mode;
637 /* Check for blocks without ANY mode requirements.
638 N.B. because of MODE_AFTER, last_mode might still
639 be different from no_mode, in which case we need to
640 mark the block as nontransparent. */
641 if (!any_set_required)
643 ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now);
644 add_seginfo (info + bb->index, ptr);
645 if (last_mode != no_mode)
646 for (i = 0; i < no_mode; i++)
647 clear_mode_bit (transp[bb->index], j, i);
650 if (targetm.mode_switching.entry && targetm.mode_switching.exit)
652 int mode = targetm.mode_switching.entry (e);
654 info[post_entry->index].mode_out =
655 info[post_entry->index].mode_in = no_mode;
656 if (pre_exit)
658 info[pre_exit->index].mode_out =
659 info[pre_exit->index].mode_in = no_mode;
662 if (mode != no_mode)
664 bb = post_entry;
666 /* By always making this nontransparent, we save
667 an extra check in make_preds_opaque. We also
668 need this to avoid confusing pre_edge_lcm when
669 antic is cleared but transp and comp are set. */
670 for (i = 0; i < no_mode; i++)
671 clear_mode_bit (transp[bb->index], j, i);
673 /* Insert a fake computing definition of MODE into entry
674 blocks which compute no mode. This represents the mode on
675 entry. */
676 info[bb->index].computing = mode;
678 if (pre_exit)
679 info[pre_exit->index].seginfo->mode =
680 targetm.mode_switching.exit (e);
684 /* Set the anticipatable and computing arrays. */
685 for (i = 0; i < no_mode; i++)
687 int m = targetm.mode_switching.priority (entity_map[j], i);
689 FOR_EACH_BB_FN (bb, cfun)
691 if (info[bb->index].seginfo->mode == m)
692 set_mode_bit (antic[bb->index], j, m);
694 if (info[bb->index].computing == m)
695 set_mode_bit (comp[bb->index], j, m);
700 /* Calculate the optimal locations for the
701 placement mode switches to modes with priority I. */
703 FOR_EACH_BB_FN (bb, cfun)
704 bitmap_not (kill[bb->index], transp[bb->index]);
706 edge_list = pre_edge_lcm_avs (n_entities * max_num_modes, transp, comp, antic,
707 kill, avin, avout, &insert, &del);
709 for (j = n_entities - 1; j >= 0; j--)
711 int no_mode = num_modes[entity_map[j]];
713 /* Insert all mode sets that have been inserted by lcm. */
715 for (int ed = NUM_EDGES (edge_list) - 1; ed >= 0; ed--)
717 edge eg = INDEX_EDGE (edge_list, ed);
719 eg->aux = (void *)(intptr_t)-1;
721 for (i = 0; i < no_mode; i++)
723 int m = targetm.mode_switching.priority (entity_map[j], i);
724 if (mode_bit_p (insert[ed], j, m))
726 eg->aux = (void *)(intptr_t)m;
727 break;
732 FOR_EACH_BB_FN (bb, cfun)
734 struct bb_info *info = bb_info[j];
735 int last_mode = no_mode;
737 /* intialize mode in availability for bb. */
738 for (i = 0; i < no_mode; i++)
739 if (mode_bit_p (avout[bb->index], j, i))
741 if (last_mode == no_mode)
742 last_mode = i;
743 if (last_mode != i)
745 last_mode = no_mode;
746 break;
749 info[bb->index].mode_out = last_mode;
751 /* intialize mode out availability for bb. */
752 last_mode = no_mode;
753 for (i = 0; i < no_mode; i++)
754 if (mode_bit_p (avin[bb->index], j, i))
756 if (last_mode == no_mode)
757 last_mode = i;
758 if (last_mode != i)
760 last_mode = no_mode;
761 break;
764 info[bb->index].mode_in = last_mode;
766 for (i = 0; i < no_mode; i++)
767 if (mode_bit_p (del[bb->index], j, i))
768 info[bb->index].seginfo->mode = no_mode;
771 /* Now output the remaining mode sets in all the segments. */
773 /* In case there was no mode inserted. the mode information on the edge
774 might not be complete.
775 Update mode info on edges and commit pending mode sets. */
776 need_commit |= commit_mode_sets (edge_list, entity_map[j], bb_info[j]);
778 /* Reset modes for next entity. */
779 clear_aux_for_edges ();
781 FOR_EACH_BB_FN (bb, cfun)
783 struct seginfo *ptr, *next;
784 int cur_mode = bb_info[j][bb->index].mode_in;
786 for (ptr = bb_info[j][bb->index].seginfo; ptr; ptr = next)
788 next = ptr->next;
789 if (ptr->mode != no_mode)
791 rtx_insn *mode_set;
793 rtl_profile_for_bb (bb);
794 start_sequence ();
796 targetm.mode_switching.emit (entity_map[j], ptr->mode,
797 cur_mode, ptr->regs_live);
798 mode_set = get_insns ();
799 end_sequence ();
801 /* modes kill each other inside a basic block. */
802 cur_mode = ptr->mode;
804 /* Insert MODE_SET only if it is nonempty. */
805 if (mode_set != NULL_RTX)
807 emitted = true;
808 if (NOTE_INSN_BASIC_BLOCK_P (ptr->insn_ptr))
809 /* We need to emit the insns in a FIFO-like manner,
810 i.e. the first to be emitted at our insertion
811 point ends up first in the instruction steam.
812 Because we made sure that NOTE_INSN_BASIC_BLOCK is
813 only used for initially empty basic blocks, we
814 can achieve this by appending at the end of
815 the block. */
816 emit_insn_after
817 (mode_set, BB_END (NOTE_BASIC_BLOCK (ptr->insn_ptr)));
818 else
819 emit_insn_before (mode_set, ptr->insn_ptr);
822 default_rtl_profile ();
825 free (ptr);
829 free (bb_info[j]);
832 free_edge_list (edge_list);
834 /* Finished. Free up all the things we've allocated. */
835 sbitmap_vector_free (del);
836 sbitmap_vector_free (insert);
837 sbitmap_vector_free (kill);
838 sbitmap_vector_free (antic);
839 sbitmap_vector_free (transp);
840 sbitmap_vector_free (comp);
841 sbitmap_vector_free (avin);
842 sbitmap_vector_free (avout);
844 if (need_commit)
845 commit_edge_insertions ();
847 if (targetm.mode_switching.entry && targetm.mode_switching.exit)
848 cleanup_cfg (CLEANUP_NO_INSN_DEL);
849 else if (!need_commit && !emitted)
850 return 0;
852 return 1;
855 #endif /* OPTIMIZE_MODE_SWITCHING */
857 namespace {
859 const pass_data pass_data_mode_switching =
861 RTL_PASS, /* type */
862 "mode_sw", /* name */
863 OPTGROUP_NONE, /* optinfo_flags */
864 TV_MODE_SWITCH, /* tv_id */
865 0, /* properties_required */
866 0, /* properties_provided */
867 0, /* properties_destroyed */
868 0, /* todo_flags_start */
869 TODO_df_finish, /* todo_flags_finish */
872 class pass_mode_switching : public rtl_opt_pass
874 public:
875 pass_mode_switching (gcc::context *ctxt)
876 : rtl_opt_pass (pass_data_mode_switching, ctxt)
879 /* opt_pass methods: */
880 /* The epiphany backend creates a second instance of this pass, so we need
881 a clone method. */
882 opt_pass * clone () { return new pass_mode_switching (m_ctxt); }
883 virtual bool gate (function *)
885 #ifdef OPTIMIZE_MODE_SWITCHING
886 return true;
887 #else
888 return false;
889 #endif
892 virtual unsigned int execute (function *)
894 #ifdef OPTIMIZE_MODE_SWITCHING
895 optimize_mode_switching ();
896 #endif /* OPTIMIZE_MODE_SWITCHING */
897 return 0;
900 }; // class pass_mode_switching
902 } // anon namespace
904 rtl_opt_pass *
905 make_pass_mode_switching (gcc::context *ctxt)
907 return new pass_mode_switching (ctxt);