gcc/ira.h

   1 /* Communication between the Integrated Register Allocator (IRA) and
   2    the rest of the compiler.
   3    Copyright (C) 2006-2014 Free Software Foundation, Inc.
   4    Contributed by Vladimir Makarov <vmakarov@redhat.com>.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_IRA_H
  23 #define GCC_IRA_H
  24
  25 /* True when we use LRA instead of reload pass for the current
  26    function.  */
  27 extern bool ira_use_lra_p;
  28
  29 /* True if we have allocno conflicts.  It is false for non-optimized
  30    mode or when the conflict table is too big.  */
  31 extern bool ira_conflicts_p;
  32
  33 struct target_ira
  34 {
  35   /* Map: hard register number -> allocno class it belongs to.  If the
  36      corresponding class is NO_REGS, the hard register is not available
  37      for allocation.  */
  38   enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
  39
  40   /* Number of allocno classes.  Allocno classes are register classes
  41      which can be used for allocations of allocnos.  */
  42   int x_ira_allocno_classes_num;
  43
  44   /* The array containing allocno classes.  Only first
  45      IRA_ALLOCNO_CLASSES_NUM elements are used for this.  */
  46   enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
  47
  48   /* Map of all register classes to corresponding allocno classes
  49      containing the given class.  If given class is not a subset of an
  50      allocno class, we translate it into the cheapest allocno class.  */
  51   enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
  52
  53   /* Number of pressure classes.  Pressure classes are register
  54      classes for which we calculate register pressure.  */
  55   int x_ira_pressure_classes_num;
  56
  57   /* The array containing pressure classes.  Only first
  58      IRA_PRESSURE_CLASSES_NUM elements are used for this.  */
  59   enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
  60
  61   /* Map of all register classes to corresponding pressure classes
  62      containing the given class.  If given class is not a subset of an
  63      pressure class, we translate it into the cheapest pressure
  64      class.  */
  65   enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
  66
  67   /* Biggest pressure register class containing stack registers.
  68      NO_REGS if there are no stack registers.  */
  69   enum reg_class x_ira_stack_reg_pressure_class;
  70
  71   /* Maps: register class x machine mode -> maximal/minimal number of
  72      hard registers of given class needed to store value of given
  73      mode.  */
  74   unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
  75   unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
  76
  77   /* Array analogous to target hook TARGET_MEMORY_MOVE_COST.  */
  78   short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
  79
  80   /* Array of number of hard registers of given class which are
  81      available for the allocation.  The order is defined by the
  82      allocation order.  */
  83   short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
  84
  85   /* The number of elements of the above array for given register
  86      class.  */
  87   int x_ira_class_hard_regs_num[N_REG_CLASSES];
  88
  89   /* Register class subset relation: TRUE if the first class is a subset
  90      of the second one considering only hard registers available for the
  91      allocation.  */
  92   int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
  93
  94   /* The biggest class inside of intersection of the two classes (that
  95      is calculated taking only hard registers available for allocation
  96      into account.  If the both classes contain no hard registers
  97      available for allocation, the value is calculated with taking all
  98      hard-registers including fixed ones into account.  */
  99   enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
 100
 101   /* True if the two classes (that is calculated taking only hard
 102      registers available for allocation into account; are
 103      intersected.  */
 104   bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
 105
 106   /* If class CL has a single allocatable register of mode M,
 107      index [CL][M] gives the number of that register, otherwise it is -1.  */
 108   short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE];
 109
 110   /* Function specific hard registers can not be used for the register
 111      allocation.  */
 112   HARD_REG_SET x_ira_no_alloc_regs;
 113 };
 114
 115 extern struct target_ira default_target_ira;
 116 #if SWITCHABLE_TARGET
 117 extern struct target_ira *this_target_ira;
 118 #else
 119 #define this_target_ira (&default_target_ira)
 120 #endif
 121
 122 #define ira_hard_regno_allocno_class \
 123   (this_target_ira->x_ira_hard_regno_allocno_class)
 124 #define ira_allocno_classes_num \
 125   (this_target_ira->x_ira_allocno_classes_num)
 126 #define ira_allocno_classes \
 127   (this_target_ira->x_ira_allocno_classes)
 128 #define ira_allocno_class_translate \
 129   (this_target_ira->x_ira_allocno_class_translate)
 130 #define ira_pressure_classes_num \
 131   (this_target_ira->x_ira_pressure_classes_num)
 132 #define ira_pressure_classes \
 133   (this_target_ira->x_ira_pressure_classes)
 134 #define ira_pressure_class_translate \
 135   (this_target_ira->x_ira_pressure_class_translate)
 136 #define ira_stack_reg_pressure_class \
 137   (this_target_ira->x_ira_stack_reg_pressure_class)
 138 #define ira_reg_class_max_nregs \
 139   (this_target_ira->x_ira_reg_class_max_nregs)
 140 #define ira_reg_class_min_nregs \
 141   (this_target_ira->x_ira_reg_class_min_nregs)
 142 #define ira_memory_move_cost \
 143   (this_target_ira->x_ira_memory_move_cost)
 144 #define ira_class_hard_regs \
 145   (this_target_ira->x_ira_class_hard_regs)
 146 #define ira_class_hard_regs_num \
 147   (this_target_ira->x_ira_class_hard_regs_num)
 148 #define ira_class_subset_p \
 149   (this_target_ira->x_ira_class_subset_p)
 150 #define ira_reg_class_subset \
 151   (this_target_ira->x_ira_reg_class_subset)
 152 #define ira_reg_classes_intersect_p \
 153   (this_target_ira->x_ira_reg_classes_intersect_p)
 154 #define ira_class_singleton \
 155   (this_target_ira->x_ira_class_singleton)
 156 #define ira_no_alloc_regs \
 157   (this_target_ira->x_ira_no_alloc_regs)
 158
 159 /* Major structure describing equivalence info for a pseudo.  */
 160 struct ira_reg_equiv_s
 161 {
 162   /* True if we can use this equivalence.  */
 163   bool defined_p;
 164   /* True if the usage of the equivalence is profitable.  */
 165   bool profitable_p;
 166   /* Equiv. memory, constant, invariant, and initializing insns of
 167      given pseudo-register or NULL_RTX.  */
 168   rtx memory;
 169   rtx constant;
 170   rtx invariant;
 171   /* Always NULL_RTX if defined_p is false.  */
 172   rtx_insn_list *init_insns;
 173 };
 174
 175 /* The length of the following array.  */
 176 extern int ira_reg_equiv_len;
 177
 178 /* Info about equiv. info for each register.  */
 179 extern struct ira_reg_equiv_s *ira_reg_equiv;
 180
 181 extern void ira_init_once (void);
 182 extern void ira_init (void);
 183 extern void ira_setup_eliminable_regset (void);
 184 extern rtx ira_eliminate_regs (rtx, machine_mode);
 185 extern void ira_set_pseudo_classes (bool, FILE *);
 186 extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *);
 187 extern void ira_expand_reg_equiv (void);
 188 extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *);
 189
 190 extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *);
 191 extern void ira_mark_allocation_change (int);
 192 extern void ira_mark_memory_move_deletion (int, int);
 193 extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
 194                                   HARD_REG_SET *, bitmap);
 195 extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int);
 196 extern void ira_mark_new_stack_slot (rtx, int, unsigned int);
 197 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx);
 198 extern bool ira_bad_reload_regno (int, rtx, rtx);
 199
 200 extern void ira_adjust_equiv_reg_cost (unsigned, int);
 201
 202 #endif /* GCC_IRA_H */